system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void calcConvolutionForwardPaddedInGPU( float *in, float *padded_in, int batch_size, int in_size_x, int in_size_y, int in_size_z, int padding)
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if( id < batch_size * in_size_x * in_size_y * in_size_z ){
int in_index = id;
int x = id % in_size_x;
id /= in_size_x;
int y = id % in_size_y;
id /= in_size_y;
int z = id % in_size_z;
id /= in_size_z;
int b = id;
int pad_index = b * (in_size_z * (in_size_x + 2*padding) * (in_size_y + 2*padding) ) +
z * ((in_size_x + 2*padding) * (in_size_y + 2*padding)) +
(y+padding) * (in_size_x + 2*padding) +
(x+padding) ;
padded_in[pad_index] = in[in_index];
}
/* original code
for ( int b = 0; b < in.size.b; ++b ){
for ( int z = 0; z < in.size.z; ++z ){
for ( int y = 0; y < in.size.y; ++y ){
for ( int x = 0; x < in.size.x; ++x ){
padded_in( b, padding+x, padding+y, z ) = in( b, x, y, z );
}
}
}
}
*/
} | code for sm_80
Function : _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0050*/ ULDC.64 UR6, c[0x0][0x178] ; /* 0x00005e0000067ab9 */
/* 0x000fe40000000a00 */
/*0060*/ UIMAD UR4, UR4, UR6, URZ ; /* 0x00000006040472a4 */
/* 0x000fe2000f8e023f */
/*0070*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e660000002100 */
/*0080*/ UIMAD UR4, UR4, UR7, URZ ; /* 0x00000007040472a4 */
/* 0x000fe2000f8e023f */
/*0090*/ IMAD R3, R0, c[0x0][0xc], R3 ; /* 0x0000030000037a24 */
/* 0x001fc800078e0203 */
/*00a0*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0202 */
/*00b0*/ ISETP.GE.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fda000bf06270 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*00e0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fc60000000a00 */
/*00f0*/ IMAD.WIDE R4, R3, R2, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fca00078e0202 */
/*0100*/ LDG.E R0, [R4.64] ; /* 0x0000000804007981 */
/* 0x0000a2000c1e1900 */
/*0110*/ IABS R9, c[0x0][0x174] ; /* 0x00005d0000097a13 */
/* 0x000fe20000000000 */
/*0120*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe40000000800 */
/*0130*/ ULDC UR5, c[0x0][0x178] ; /* 0x00005e0000057ab9 */
/* 0x000fe20000000800 */
/*0140*/ I2F.RP R8, R9 ; /* 0x0000000900087306 */
/* 0x000e620000209400 */
/*0150*/ ULEA UR5, UR4, UR5, 0x1 ; /* 0x0000000504057291 */
/* 0x000fe4000f8e083f */
/*0160*/ ULDC UR6, c[0x0][0x174] ; /* 0x00005d0000067ab9 */
/* 0x000fe20000000800 */
/*0170*/ IABS R4, R3 ; /* 0x0000000300047213 */
/* 0x001fe20000000000 */
/*0180*/ ULEA UR4, UR4, UR6, 0x1 ; /* 0x0000000604047291 */
/* 0x000fc6000f8e083f */
/*0190*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x002e240000001000 */
/*01a0*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fcc0007ffe0ff */
/*01b0*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*01c0*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x001fe200000001ff */
/*01d0*/ IMAD.MOV R10, RZ, RZ, -R7 ; /* 0x000000ffff0a7224 */
/* 0x002fc800078e0a07 */
/*01e0*/ IMAD R11, R10, R9, RZ ; /* 0x000000090a0b7224 */
/* 0x000fe200078e02ff */
/*01f0*/ IABS R10, c[0x0][0x178] ; /* 0x00005e00000a7a13 */
/* 0x000fc80000000000 */
/*0200*/ IMAD.HI.U32 R7, R7, R11, R6 ; /* 0x0000000b07077227 */
/* 0x000fe200078e0006 */
/*0210*/ I2F.RP R8, R10 ; /* 0x0000000a00087306 */
/* 0x000e2a0000209400 */
/*0220*/ IMAD.HI.U32 R7, R7, R4, RZ ; /* 0x0000000407077227 */
/* 0x000fc800078e00ff */
/*0230*/ IMAD.MOV R5, RZ, RZ, -R7 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a07 */
/*0240*/ IMAD R4, R9.reuse, R5, R4 ; /* 0x0000000509047224 */
/* 0x040fe200078e0204 */
/*0250*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e280000001000 */
/*0260*/ ISETP.GT.U32.AND P2, PT, R9, R4, PT ; /* 0x000000040900720c */
/* 0x000fda0003f44070 */
/*0270*/ @!P2 IMAD.IADD R4, R4, 0x1, -R9 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a09 */
/*0280*/ IADD3 R5, R8, 0xffffffe, RZ ; /* 0x0ffffffe08057810 */
/* 0x001fe40007ffe0ff */
/*0290*/ @!P2 IADD3 R7, R7, 0x1, RZ ; /* 0x000000010707a810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ ISETP.GE.U32.AND P0, PT, R4, R9, PT ; /* 0x000000090400720c */
/* 0x000fe40003f06070 */
/*02b0*/ LOP3.LUT R4, R3, c[0x0][0x174], RZ, 0x3c, !PT ; /* 0x00005d0003047a12 */
/* 0x000fe200078e3cff */
/*02c0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e22000021f000 */
/*02d0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fe40003f45270 */
/*02e0*/ ISETP.GE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f26270 */
/*02f0*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fcc00000001ff */
/*0300*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fc80007ffe0ff */
/*0310*/ MOV R8, R7 ; /* 0x0000000700087202 */
/* 0x000fe20000000f00 */
/*0320*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x001fc800078e0a05 */
/*0330*/ @!P1 IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff089224 */
/* 0x000fe200078e0a08 */
/*0340*/ @!P2 LOP3.LUT R8, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff08aa12 */
/* 0x000fe200078e33ff */
/*0350*/ IMAD R7, R7, R10, RZ ; /* 0x0000000a07077224 */
/* 0x000fc600078e02ff */
/*0360*/ IABS R6, R8 ; /* 0x0000000800067213 */
/* 0x000fe20000000000 */
/*0370*/ IMAD.HI.U32 R4, R5, R7, R4 ; /* 0x0000000705047227 */
/* 0x000fc800078e0004 */
/*0380*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0006 */
/*0390*/ IMAD.HI.U32 R4, R4, R5, RZ ; /* 0x0000000504047227 */
/* 0x000fc800078e00ff */
/*03a0*/ IMAD.MOV R6, RZ, RZ, -R4 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a04 */
/*03b0*/ IMAD R5, R10, R6, R5 ; /* 0x000000060a057224 */
/* 0x000fe200078e0205 */
/*03c0*/ IADD3 R6, -R8, RZ, RZ ; /* 0x000000ff08067210 */
/* 0x000fc80007ffe1ff */
/*03d0*/ ISETP.GT.U32.AND P2, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x000fe20003f44070 */
/*03e0*/ IMAD R3, R6, c[0x0][0x174], R3 ; /* 0x00005d0006037a24 */
/* 0x000fca00078e0203 */
/*03f0*/ IADD3 R3, R3, c[0x0][0x180], RZ ; /* 0x0000600003037a10 */
/* 0x000fce0007ffe0ff */
/*0400*/ @!P2 IADD3 R5, R5, -R10.reuse, RZ ; /* 0x8000000a0505a210 */
/* 0x080fe40007ffe0ff */
/*0410*/ @!P2 IADD3 R4, R4, 0x1, RZ ; /* 0x000000010404a810 */
/* 0x000fe40007ffe0ff */
/*0420*/ ISETP.GE.U32.AND P0, PT, R5, R10, PT ; /* 0x0000000a0500720c */
/* 0x000fe40003f06070 */
/*0430*/ LOP3.LUT R5, R8, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e0008057a12 */
/* 0x000fe400078e3cff */
/*0440*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f45270 */
/*0450*/ ISETP.GE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fce0003f26270 */
/*0460*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fcc0007ffe0ff */
/*0470*/ @!P1 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff049224 */
/* 0x000fe200078e0a04 */
/*0480*/ @!P2 LOP3.LUT R4, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff04aa12 */
/* 0x000fca00078e33ff */
/*0490*/ IMAD.MOV R5, RZ, RZ, -R4 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a04 */
/*04a0*/ IMAD R5, R5, c[0x0][0x178], R8 ; /* 0x00005e0005057a24 */
/* 0x000fca00078e0208 */
/*04b0*/ IADD3 R5, R5, c[0x0][0x180], RZ ; /* 0x0000600005057a10 */
/* 0x000fca0007ffe0ff */
/*04c0*/ IMAD R4, R4, UR5, R5 ; /* 0x0000000504047c24 */
/* 0x000fc8000f8e0205 */
/*04d0*/ IMAD R3, R4, UR4, R3 ; /* 0x0000000404037c24 */
/* 0x000fc8000f8e0203 */
/*04e0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*04f0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x004fe2000c101908 */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void calcConvolutionForwardPaddedInGPU( float *in, float *padded_in, int batch_size, int in_size_x, int in_size_y, int in_size_z, int padding)
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if( id < batch_size * in_size_x * in_size_y * in_size_z ){
int in_index = id;
int x = id % in_size_x;
id /= in_size_x;
int y = id % in_size_y;
id /= in_size_y;
int z = id % in_size_z;
id /= in_size_z;
int b = id;
int pad_index = b * (in_size_z * (in_size_x + 2*padding) * (in_size_y + 2*padding) ) +
z * ((in_size_x + 2*padding) * (in_size_y + 2*padding)) +
(y+padding) * (in_size_x + 2*padding) +
(x+padding) ;
padded_in[pad_index] = in[in_index];
}
/* original code
for ( int b = 0; b < in.size.b; ++b ){
for ( int z = 0; z < in.size.z; ++z ){
for ( int y = 0; y < in.size.y; ++y ){
for ( int x = 0; x < in.size.x; ++x ){
padded_in( b, padding+x, padding+y, z ) = in( b, x, y, z );
}
}
}
}
*/
} | .file "tmpxft_0018a100_00000000-6_calcConvolutionForwardPaddedInGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z60__device_stub__Z33calcConvolutionForwardPaddedInGPUPfS_iiiiiPfS_iiiii
.type _Z60__device_stub__Z33calcConvolutionForwardPaddedInGPUPfS_iiiiiPfS_iiiii, @function
_Z60__device_stub__Z33calcConvolutionForwardPaddedInGPUPfS_iiiiiPfS_iiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z60__device_stub__Z33calcConvolutionForwardPaddedInGPUPfS_iiiiiPfS_iiiii, .-_Z60__device_stub__Z33calcConvolutionForwardPaddedInGPUPfS_iiiiiPfS_iiiii
.globl _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii
.type _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii, @function
_Z33calcConvolutionForwardPaddedInGPUPfS_iiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z60__device_stub__Z33calcConvolutionForwardPaddedInGPUPfS_iiiiiPfS_iiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii, .-_Z33calcConvolutionForwardPaddedInGPUPfS_iiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z33calcConvolutionForwardPaddedInGPUPfS_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void calcConvolutionForwardPaddedInGPU( float *in, float *padded_in, int batch_size, int in_size_x, int in_size_y, int in_size_z, int padding)
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if( id < batch_size * in_size_x * in_size_y * in_size_z ){
int in_index = id;
int x = id % in_size_x;
id /= in_size_x;
int y = id % in_size_y;
id /= in_size_y;
int z = id % in_size_z;
id /= in_size_z;
int b = id;
int pad_index = b * (in_size_z * (in_size_x + 2*padding) * (in_size_y + 2*padding) ) +
z * ((in_size_x + 2*padding) * (in_size_y + 2*padding)) +
(y+padding) * (in_size_x + 2*padding) +
(x+padding) ;
padded_in[pad_index] = in[in_index];
}
/* original code
for ( int b = 0; b < in.size.b; ++b ){
for ( int z = 0; z < in.size.z; ++z ){
for ( int y = 0; y < in.size.y; ++y ){
for ( int x = 0; x < in.size.x; ++x ){
padded_in( b, padding+x, padding+y, z ) = in( b, x, y, z );
}
}
}
}
*/
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calcConvolutionForwardPaddedInGPU( float *in, float *padded_in, int batch_size, int in_size_x, int in_size_y, int in_size_z, int padding)
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if( id < batch_size * in_size_x * in_size_y * in_size_z ){
int in_index = id;
int x = id % in_size_x;
id /= in_size_x;
int y = id % in_size_y;
id /= in_size_y;
int z = id % in_size_z;
id /= in_size_z;
int b = id;
int pad_index = b * (in_size_z * (in_size_x + 2*padding) * (in_size_y + 2*padding) ) +
z * ((in_size_x + 2*padding) * (in_size_y + 2*padding)) +
(y+padding) * (in_size_x + 2*padding) +
(x+padding) ;
padded_in[pad_index] = in[in_index];
}
/* original code
for ( int b = 0; b < in.size.b; ++b ){
for ( int z = 0; z < in.size.z; ++z ){
for ( int y = 0; y < in.size.y; ++y ){
for ( int x = 0; x < in.size.x; ++x ){
padded_in( b, padding+x, padding+y, z ) = in( b, x, y, z );
}
}
}
}
*/
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calcConvolutionForwardPaddedInGPU( float *in, float *padded_in, int batch_size, int in_size_x, int in_size_y, int in_size_z, int padding)
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if( id < batch_size * in_size_x * in_size_y * in_size_z ){
int in_index = id;
int x = id % in_size_x;
id /= in_size_x;
int y = id % in_size_y;
id /= in_size_y;
int z = id % in_size_z;
id /= in_size_z;
int b = id;
int pad_index = b * (in_size_z * (in_size_x + 2*padding) * (in_size_y + 2*padding) ) +
z * ((in_size_x + 2*padding) * (in_size_y + 2*padding)) +
(y+padding) * (in_size_x + 2*padding) +
(x+padding) ;
padded_in[pad_index] = in[in_index];
}
/* original code
for ( int b = 0; b < in.size.b; ++b ){
for ( int z = 0; z < in.size.z; ++z ){
for ( int y = 0; y < in.size.y; ++y ){
for ( int x = 0; x < in.size.x; ++x ){
padded_in( b, padding+x, padding+y, z ) = in( b, x, y, z );
}
}
}
}
*/
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii
.globl _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii
.p2align 8
.type _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii,@function
_Z33calcConvolutionForwardPaddedInGPUPfS_iiiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s2, s3
s_mul_i32 s3, s5, s4
v_add_nc_u32_e32 v0, s2, v0
s_mul_i32 s2, s3, s6
s_mul_i32 s2, s2, s7
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[8:11], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_load_b32 s0, s[0:1], 0x20
s_ashr_i32 s1, s5, 31
v_ashrrev_i32_e32 v4, 31, v0
s_add_i32 s2, s5, s1
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_xor_b32 s2, s2, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_sub_i32 s3, 0, s2
v_add_nc_u32_e32 v5, v0, v4
v_xor_b32_e32 v5, v5, v4
v_xor_b32_e32 v4, s1, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_cvt_f32_u32_e32 v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v3, s3, v1
s_ashr_i32 s3, s6, 31
s_add_i32 s4, s6, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s4, s3
v_cvt_f32_u32_e32 v6, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v1, v3
s_sub_i32 s1, 0, s4
v_add_nc_u32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v5, v1
v_mul_lo_u32 v3, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v5, v3
v_add_nc_u32_e32 v5, 1, v1
v_subrev_nc_u32_e32 v7, s2, v3
v_cmp_le_u32_e32 vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v5, vcc_lo
v_rcp_iflag_f32_e32 v5, v6
v_dual_cndmask_b32 v3, v3, v7 :: v_dual_add_nc_u32 v6, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s2, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v5
v_cndmask_b32_e32 v1, v1, v6, vcc_lo
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v4
v_sub_nc_u32_e32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v4, s1, v3
s_lshl_b32 s1, s0, 1
s_add_i32 s2, s1, s6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v1
s_add_i32 s1, s1, s5
v_mul_hi_u32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, v1, v5
v_xor_b32_e32 v6, v6, v5
v_xor_b32_e32 v5, s3, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v4
v_mul_hi_u32 v3, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v3, s4
v_sub_nc_u32_e32 v4, v6, v4
v_add_nc_u32_e32 v6, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v7, s4, v4
v_cmp_le_u32_e32 vcc_lo, s4, v4
v_dual_cndmask_b32 v3, v3, v6 :: v_dual_cndmask_b32 v4, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, 1, v3
v_cmp_le_u32_e32 vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
v_xor_b32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v3, v5
v_mul_lo_u32 v4, v3, s6
v_mul_lo_u32 v3, v3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v1, v4
v_mul_lo_u32 v1, v1, s5
v_add3_u32 v3, v4, s0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v0, v0, v1
v_mul_lo_u32 v3, v3, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v0, s0, v3
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s10, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii, .Lfunc_end0-_Z33calcConvolutionForwardPaddedInGPUPfS_iiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calcConvolutionForwardPaddedInGPU( float *in, float *padded_in, int batch_size, int in_size_x, int in_size_y, int in_size_z, int padding)
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if( id < batch_size * in_size_x * in_size_y * in_size_z ){
int in_index = id;
int x = id % in_size_x;
id /= in_size_x;
int y = id % in_size_y;
id /= in_size_y;
int z = id % in_size_z;
id /= in_size_z;
int b = id;
int pad_index = b * (in_size_z * (in_size_x + 2*padding) * (in_size_y + 2*padding) ) +
z * ((in_size_x + 2*padding) * (in_size_y + 2*padding)) +
(y+padding) * (in_size_x + 2*padding) +
(x+padding) ;
padded_in[pad_index] = in[in_index];
}
/* original code
for ( int b = 0; b < in.size.b; ++b ){
for ( int z = 0; z < in.size.z; ++z ){
for ( int y = 0; y < in.size.y; ++y ){
for ( int x = 0; x < in.size.x; ++x ){
padded_in( b, padding+x, padding+y, z ) = in( b, x, y, z );
}
}
}
}
*/
} | .text
.file "calcConvolutionForwardPaddedInGPU.hip"
.globl _Z48__device_stub__calcConvolutionForwardPaddedInGPUPfS_iiiii # -- Begin function _Z48__device_stub__calcConvolutionForwardPaddedInGPUPfS_iiiii
.p2align 4, 0x90
.type _Z48__device_stub__calcConvolutionForwardPaddedInGPUPfS_iiiii,@function
_Z48__device_stub__calcConvolutionForwardPaddedInGPUPfS_iiiii: # @_Z48__device_stub__calcConvolutionForwardPaddedInGPUPfS_iiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z33calcConvolutionForwardPaddedInGPUPfS_iiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z48__device_stub__calcConvolutionForwardPaddedInGPUPfS_iiiii, .Lfunc_end0-_Z48__device_stub__calcConvolutionForwardPaddedInGPUPfS_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z33calcConvolutionForwardPaddedInGPUPfS_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii,@object # @_Z33calcConvolutionForwardPaddedInGPUPfS_iiiii
.section .rodata,"a",@progbits
.globl _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii
.p2align 3, 0x0
_Z33calcConvolutionForwardPaddedInGPUPfS_iiiii:
.quad _Z48__device_stub__calcConvolutionForwardPaddedInGPUPfS_iiiii
.size _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z33calcConvolutionForwardPaddedInGPUPfS_iiiii"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z48__device_stub__calcConvolutionForwardPaddedInGPUPfS_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0050*/ ULDC.64 UR6, c[0x0][0x178] ; /* 0x00005e0000067ab9 */
/* 0x000fe40000000a00 */
/*0060*/ UIMAD UR4, UR4, UR6, URZ ; /* 0x00000006040472a4 */
/* 0x000fe2000f8e023f */
/*0070*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e660000002100 */
/*0080*/ UIMAD UR4, UR4, UR7, URZ ; /* 0x00000007040472a4 */
/* 0x000fe2000f8e023f */
/*0090*/ IMAD R3, R0, c[0x0][0xc], R3 ; /* 0x0000030000037a24 */
/* 0x001fc800078e0203 */
/*00a0*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0202 */
/*00b0*/ ISETP.GE.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fda000bf06270 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*00e0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fc60000000a00 */
/*00f0*/ IMAD.WIDE R4, R3, R2, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fca00078e0202 */
/*0100*/ LDG.E R0, [R4.64] ; /* 0x0000000804007981 */
/* 0x0000a2000c1e1900 */
/*0110*/ IABS R9, c[0x0][0x174] ; /* 0x00005d0000097a13 */
/* 0x000fe20000000000 */
/*0120*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe40000000800 */
/*0130*/ ULDC UR5, c[0x0][0x178] ; /* 0x00005e0000057ab9 */
/* 0x000fe20000000800 */
/*0140*/ I2F.RP R8, R9 ; /* 0x0000000900087306 */
/* 0x000e620000209400 */
/*0150*/ ULEA UR5, UR4, UR5, 0x1 ; /* 0x0000000504057291 */
/* 0x000fe4000f8e083f */
/*0160*/ ULDC UR6, c[0x0][0x174] ; /* 0x00005d0000067ab9 */
/* 0x000fe20000000800 */
/*0170*/ IABS R4, R3 ; /* 0x0000000300047213 */
/* 0x001fe20000000000 */
/*0180*/ ULEA UR4, UR4, UR6, 0x1 ; /* 0x0000000604047291 */
/* 0x000fc6000f8e083f */
/*0190*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x002e240000001000 */
/*01a0*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fcc0007ffe0ff */
/*01b0*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*01c0*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x001fe200000001ff */
/*01d0*/ IMAD.MOV R10, RZ, RZ, -R7 ; /* 0x000000ffff0a7224 */
/* 0x002fc800078e0a07 */
/*01e0*/ IMAD R11, R10, R9, RZ ; /* 0x000000090a0b7224 */
/* 0x000fe200078e02ff */
/*01f0*/ IABS R10, c[0x0][0x178] ; /* 0x00005e00000a7a13 */
/* 0x000fc80000000000 */
/*0200*/ IMAD.HI.U32 R7, R7, R11, R6 ; /* 0x0000000b07077227 */
/* 0x000fe200078e0006 */
/*0210*/ I2F.RP R8, R10 ; /* 0x0000000a00087306 */
/* 0x000e2a0000209400 */
/*0220*/ IMAD.HI.U32 R7, R7, R4, RZ ; /* 0x0000000407077227 */
/* 0x000fc800078e00ff */
/*0230*/ IMAD.MOV R5, RZ, RZ, -R7 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a07 */
/*0240*/ IMAD R4, R9.reuse, R5, R4 ; /* 0x0000000509047224 */
/* 0x040fe200078e0204 */
/*0250*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e280000001000 */
/*0260*/ ISETP.GT.U32.AND P2, PT, R9, R4, PT ; /* 0x000000040900720c */
/* 0x000fda0003f44070 */
/*0270*/ @!P2 IMAD.IADD R4, R4, 0x1, -R9 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a09 */
/*0280*/ IADD3 R5, R8, 0xffffffe, RZ ; /* 0x0ffffffe08057810 */
/* 0x001fe40007ffe0ff */
/*0290*/ @!P2 IADD3 R7, R7, 0x1, RZ ; /* 0x000000010707a810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ ISETP.GE.U32.AND P0, PT, R4, R9, PT ; /* 0x000000090400720c */
/* 0x000fe40003f06070 */
/*02b0*/ LOP3.LUT R4, R3, c[0x0][0x174], RZ, 0x3c, !PT ; /* 0x00005d0003047a12 */
/* 0x000fe200078e3cff */
/*02c0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e22000021f000 */
/*02d0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fe40003f45270 */
/*02e0*/ ISETP.GE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f26270 */
/*02f0*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fcc00000001ff */
/*0300*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fc80007ffe0ff */
/*0310*/ MOV R8, R7 ; /* 0x0000000700087202 */
/* 0x000fe20000000f00 */
/*0320*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x001fc800078e0a05 */
/*0330*/ @!P1 IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff089224 */
/* 0x000fe200078e0a08 */
/*0340*/ @!P2 LOP3.LUT R8, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff08aa12 */
/* 0x000fe200078e33ff */
/*0350*/ IMAD R7, R7, R10, RZ ; /* 0x0000000a07077224 */
/* 0x000fc600078e02ff */
/*0360*/ IABS R6, R8 ; /* 0x0000000800067213 */
/* 0x000fe20000000000 */
/*0370*/ IMAD.HI.U32 R4, R5, R7, R4 ; /* 0x0000000705047227 */
/* 0x000fc800078e0004 */
/*0380*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0006 */
/*0390*/ IMAD.HI.U32 R4, R4, R5, RZ ; /* 0x0000000504047227 */
/* 0x000fc800078e00ff */
/*03a0*/ IMAD.MOV R6, RZ, RZ, -R4 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a04 */
/*03b0*/ IMAD R5, R10, R6, R5 ; /* 0x000000060a057224 */
/* 0x000fe200078e0205 */
/*03c0*/ IADD3 R6, -R8, RZ, RZ ; /* 0x000000ff08067210 */
/* 0x000fc80007ffe1ff */
/*03d0*/ ISETP.GT.U32.AND P2, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x000fe20003f44070 */
/*03e0*/ IMAD R3, R6, c[0x0][0x174], R3 ; /* 0x00005d0006037a24 */
/* 0x000fca00078e0203 */
/*03f0*/ IADD3 R3, R3, c[0x0][0x180], RZ ; /* 0x0000600003037a10 */
/* 0x000fce0007ffe0ff */
/*0400*/ @!P2 IADD3 R5, R5, -R10.reuse, RZ ; /* 0x8000000a0505a210 */
/* 0x080fe40007ffe0ff */
/*0410*/ @!P2 IADD3 R4, R4, 0x1, RZ ; /* 0x000000010404a810 */
/* 0x000fe40007ffe0ff */
/*0420*/ ISETP.GE.U32.AND P0, PT, R5, R10, PT ; /* 0x0000000a0500720c */
/* 0x000fe40003f06070 */
/*0430*/ LOP3.LUT R5, R8, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e0008057a12 */
/* 0x000fe400078e3cff */
/*0440*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f45270 */
/*0450*/ ISETP.GE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fce0003f26270 */
/*0460*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fcc0007ffe0ff */
/*0470*/ @!P1 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff049224 */
/* 0x000fe200078e0a04 */
/*0480*/ @!P2 LOP3.LUT R4, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff04aa12 */
/* 0x000fca00078e33ff */
/*0490*/ IMAD.MOV R5, RZ, RZ, -R4 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a04 */
/*04a0*/ IMAD R5, R5, c[0x0][0x178], R8 ; /* 0x00005e0005057a24 */
/* 0x000fca00078e0208 */
/*04b0*/ IADD3 R5, R5, c[0x0][0x180], RZ ; /* 0x0000600005057a10 */
/* 0x000fca0007ffe0ff */
/*04c0*/ IMAD R4, R4, UR5, R5 ; /* 0x0000000504047c24 */
/* 0x000fc8000f8e0205 */
/*04d0*/ IMAD R3, R4, UR4, R3 ; /* 0x0000000404037c24 */
/* 0x000fc8000f8e0203 */
/*04e0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*04f0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x004fe2000c101908 */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii
.globl _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii
.p2align 8
.type _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii,@function
_Z33calcConvolutionForwardPaddedInGPUPfS_iiiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s2, s3
s_mul_i32 s3, s5, s4
v_add_nc_u32_e32 v0, s2, v0
s_mul_i32 s2, s3, s6
s_mul_i32 s2, s2, s7
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[8:11], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_load_b32 s0, s[0:1], 0x20
s_ashr_i32 s1, s5, 31
v_ashrrev_i32_e32 v4, 31, v0
s_add_i32 s2, s5, s1
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_xor_b32 s2, s2, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_sub_i32 s3, 0, s2
v_add_nc_u32_e32 v5, v0, v4
v_xor_b32_e32 v5, v5, v4
v_xor_b32_e32 v4, s1, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_cvt_f32_u32_e32 v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v3, s3, v1
s_ashr_i32 s3, s6, 31
s_add_i32 s4, s6, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s4, s3
v_cvt_f32_u32_e32 v6, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v1, v3
s_sub_i32 s1, 0, s4
v_add_nc_u32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v5, v1
v_mul_lo_u32 v3, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v5, v3
v_add_nc_u32_e32 v5, 1, v1
v_subrev_nc_u32_e32 v7, s2, v3
v_cmp_le_u32_e32 vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v5, vcc_lo
v_rcp_iflag_f32_e32 v5, v6
v_dual_cndmask_b32 v3, v3, v7 :: v_dual_add_nc_u32 v6, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s2, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v5
v_cndmask_b32_e32 v1, v1, v6, vcc_lo
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v4
v_sub_nc_u32_e32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v4, s1, v3
s_lshl_b32 s1, s0, 1
s_add_i32 s2, s1, s6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v1
s_add_i32 s1, s1, s5
v_mul_hi_u32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, v1, v5
v_xor_b32_e32 v6, v6, v5
v_xor_b32_e32 v5, s3, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v4
v_mul_hi_u32 v3, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v3, s4
v_sub_nc_u32_e32 v4, v6, v4
v_add_nc_u32_e32 v6, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v7, s4, v4
v_cmp_le_u32_e32 vcc_lo, s4, v4
v_dual_cndmask_b32 v3, v3, v6 :: v_dual_cndmask_b32 v4, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, 1, v3
v_cmp_le_u32_e32 vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
v_xor_b32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v3, v5
v_mul_lo_u32 v4, v3, s6
v_mul_lo_u32 v3, v3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v1, v4
v_mul_lo_u32 v1, v1, s5
v_add3_u32 v3, v4, s0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v0, v0, v1
v_mul_lo_u32 v3, v3, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v0, s0, v3
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s10, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii, .Lfunc_end0-_Z33calcConvolutionForwardPaddedInGPUPfS_iiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018a100_00000000-6_calcConvolutionForwardPaddedInGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z60__device_stub__Z33calcConvolutionForwardPaddedInGPUPfS_iiiiiPfS_iiiii
.type _Z60__device_stub__Z33calcConvolutionForwardPaddedInGPUPfS_iiiiiPfS_iiiii, @function
_Z60__device_stub__Z33calcConvolutionForwardPaddedInGPUPfS_iiiiiPfS_iiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z60__device_stub__Z33calcConvolutionForwardPaddedInGPUPfS_iiiiiPfS_iiiii, .-_Z60__device_stub__Z33calcConvolutionForwardPaddedInGPUPfS_iiiiiPfS_iiiii
.globl _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii
.type _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii, @function
_Z33calcConvolutionForwardPaddedInGPUPfS_iiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z60__device_stub__Z33calcConvolutionForwardPaddedInGPUPfS_iiiiiPfS_iiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii, .-_Z33calcConvolutionForwardPaddedInGPUPfS_iiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z33calcConvolutionForwardPaddedInGPUPfS_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "calcConvolutionForwardPaddedInGPU.hip"
.globl _Z48__device_stub__calcConvolutionForwardPaddedInGPUPfS_iiiii # -- Begin function _Z48__device_stub__calcConvolutionForwardPaddedInGPUPfS_iiiii
.p2align 4, 0x90
.type _Z48__device_stub__calcConvolutionForwardPaddedInGPUPfS_iiiii,@function
_Z48__device_stub__calcConvolutionForwardPaddedInGPUPfS_iiiii: # @_Z48__device_stub__calcConvolutionForwardPaddedInGPUPfS_iiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z33calcConvolutionForwardPaddedInGPUPfS_iiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z48__device_stub__calcConvolutionForwardPaddedInGPUPfS_iiiii, .Lfunc_end0-_Z48__device_stub__calcConvolutionForwardPaddedInGPUPfS_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z33calcConvolutionForwardPaddedInGPUPfS_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii,@object # @_Z33calcConvolutionForwardPaddedInGPUPfS_iiiii
.section .rodata,"a",@progbits
.globl _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii
.p2align 3, 0x0
_Z33calcConvolutionForwardPaddedInGPUPfS_iiiii:
.quad _Z48__device_stub__calcConvolutionForwardPaddedInGPUPfS_iiiii
.size _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z33calcConvolutionForwardPaddedInGPUPfS_iiiii"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z48__device_stub__calcConvolutionForwardPaddedInGPUPfS_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z33calcConvolutionForwardPaddedInGPUPfS_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Subtract( float * x, size_t idx, size_t N, float W0, float W1)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-2)*N+i] = W0*x[(idx-1)*N+i] - W1*x[(idx-2)*N+i];
}
return;
} | code for sm_80
Function : _Z8SubtractPfmmff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fc80000011404 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R5, c[0x0][0x174], PT, P0 ; /* 0x00005d0005007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0090*/ IADD3 R2, P1, RZ, -c[0x0][0x170], RZ ; /* 0x80005c00ff027a10 */
/* 0x000fe20007f3e0ff */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff067624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0004 */
/*00d0*/ IADD3 R0, P0, -R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a10 */
/* 0x000fe40007f1e1ff */
/*00e0*/ IADD3.X R3, RZ, ~c[0x0][0x174], RZ, P1, !PT ; /* 0x80005d00ff037a10 */
/* 0x000fe40000ffe4ff */
/*00f0*/ IADD3.X R6, R6, -0x1, RZ, P0, !PT ; /* 0xffffffff06067810 */
/* 0x000fc600007fe4ff */
/*0100*/ IMAD.WIDE.U32 R2, R0, c[0x0][0x170], R2 ; /* 0x00005c0000027a25 */
/* 0x000fc800078e0002 */
/*0110*/ IMAD R7, R6, c[0x0][0x170], RZ ; /* 0x00005c0006077a24 */
/* 0x000fe200078e02ff */
/*0120*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x000fc60000000f00 */
/*0130*/ IMAD R13, R0, c[0x0][0x174], R7 ; /* 0x00005d00000d7a24 */
/* 0x000fe400078e0207 */
/*0140*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0005 */
/*0150*/ IMAD.IADD R11, R3, 0x1, R13 ; /* 0x00000001030b7824 */
/* 0x000fe400078e020d */
/*0160*/ IADD3 R5, P0, R6, R2, RZ ; /* 0x0000000206057210 */
/* 0x000fca0007f1e0ff */
/*0170*/ IMAD.X R8, R7, 0x1, R11, P0 ; /* 0x0000000107087824 */
/* 0x000fe200000e060b */
/*0180*/ LEA R4, P0, R5, c[0x0][0x160], 0x2 ; /* 0x0000580005047a11 */
/* 0x000fe200078010ff */
/*0190*/ IMAD.WIDE.U32 R6, R0, c[0x0][0x170], R6 ; /* 0x00005c0000067a25 */
/* 0x000fc600078e0006 */
/*01a0*/ LEA.HI.X R5, R5, c[0x0][0x164], R8, 0x2, P0 ; /* 0x0000590005057a11 */
/* 0x000fe400000f1408 */
/*01b0*/ IADD3 R7, R13, R7, RZ ; /* 0x000000070d077210 */
/* 0x000fe40007ffe0ff */
/*01c0*/ LEA R8, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006087a11 */
/* 0x000fc800078010ff */
/*01d0*/ LEA.HI.X R9, R6, c[0x0][0x164], R7, 0x2, P0 ; /* 0x0000590006097a11 */
/* 0x000fe400000f1407 */
/*01e0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee2000c1e1900 */
/*0200*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0f7624 */
/* 0x000fe400078e00ff */
/*0210*/ FMUL R7, R6, c[0x0][0x17c] ; /* 0x00005f0006077a20 */
/* 0x004fe40000400000 */
/*0220*/ IMAD R6, R15, c[0x0][0xc], R10 ; /* 0x000003000f067a24 */
/* 0x000fc400078e020a */
/*0230*/ FFMA R7, R8, c[0x0][0x178], -R7 ; /* 0x00005e0008077a23 */
/* 0x008fc60000000807 */
/*0240*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fe40003f06070 */
/*0250*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e2000c101904 */
/*0260*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fe40000000f00 */
/*0270*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x001fc80000011406 */
/*0280*/ ISETP.GE.U32.AND.EX P0, PT, R7, c[0x0][0x174], PT, P0 ; /* 0x00005d0007007a0c */
/* 0x000fda0003f06100 */
/*0290*/ @!P0 BRA 0x160 ; /* 0xfffffec000008947 */
/* 0x000fea000383ffff */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ BRA 0x2b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Subtract( float * x, size_t idx, size_t N, float W0, float W1)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-2)*N+i] = W0*x[(idx-1)*N+i] - W1*x[(idx-2)*N+i];
}
return;
} | .file "tmpxft_00015030_00000000-6_Subtract.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8SubtractPfmmffPfmmff
.type _Z31__device_stub__Z8SubtractPfmmffPfmmff, @function
_Z31__device_stub__Z8SubtractPfmmffPfmmff:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8SubtractPfmmff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z8SubtractPfmmffPfmmff, .-_Z31__device_stub__Z8SubtractPfmmffPfmmff
.globl _Z8SubtractPfmmff
.type _Z8SubtractPfmmff, @function
_Z8SubtractPfmmff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8SubtractPfmmffPfmmff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8SubtractPfmmff, .-_Z8SubtractPfmmff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8SubtractPfmmff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8SubtractPfmmff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Subtract( float * x, size_t idx, size_t N, float W0, float W1)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-2)*N+i] = W0*x[(idx-1)*N+i] - W1*x[(idx-2)*N+i];
}
return;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Subtract( float * x, size_t idx, size_t N, float W0, float W1)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-2)*N+i] = W0*x[(idx-1)*N+i] - W1*x[(idx-2)*N+i];
}
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Subtract( float * x, size_t idx, size_t N, float W0, float W1)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-2)*N+i] = W0*x[(idx-1)*N+i] - W1*x[(idx-2)*N+i];
}
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8SubtractPfmmff
.globl _Z8SubtractPfmmff
.p2align 8
.type _Z8SubtractPfmmff,@function
_Z8SubtractPfmmff:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_load_b32 s12, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s10, -1
s_addc_u32 s5, s11, -1
s_mul_i32 s7, s4, s3
s_mul_hi_u32 s13, s4, s2
s_mul_i32 s5, s5, s2
s_add_i32 s7, s13, s7
s_mul_i32 s4, s4, s2
s_add_i32 s5, s7, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_add_u32 s4, s8, s4
s_addc_u32 s5, s9, s5
s_add_u32 s7, s10, -2
s_addc_u32 s10, s11, -1
s_mul_i32 s11, s7, s3
s_mul_hi_u32 s13, s7, s2
s_mul_i32 s14, s10, s2
s_add_i32 s11, s13, s11
s_mul_i32 s10, s7, s2
s_add_i32 s11, s11, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[10:11], 2
s_add_u32 s7, s8, s10
s_addc_u32 s8, s9, s11
s_add_i32 s15, s15, s12
s_mov_b32 s9, 0
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_mul_i32 s6, s12, s6
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v5, vcc_lo, s7, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s8, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[3:4]
s_clause 0x1
global_load_b32 v2, v[5:6], off
global_load_b32 v0, v[0:1], off
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(1)
v_mul_f32_e32 v7, s1, v2
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
v_add_nc_u32_e32 v3, s6, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_fma_f32 v0, v0, s0, -v7
global_store_b32 v[5:6], v0, off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8SubtractPfmmff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8SubtractPfmmff, .Lfunc_end0-_Z8SubtractPfmmff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8SubtractPfmmff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8SubtractPfmmff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Subtract( float * x, size_t idx, size_t N, float W0, float W1)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-2)*N+i] = W0*x[(idx-1)*N+i] - W1*x[(idx-2)*N+i];
}
return;
} | .text
.file "Subtract.hip"
.globl _Z23__device_stub__SubtractPfmmff # -- Begin function _Z23__device_stub__SubtractPfmmff
.p2align 4, 0x90
.type _Z23__device_stub__SubtractPfmmff,@function
_Z23__device_stub__SubtractPfmmff: # @_Z23__device_stub__SubtractPfmmff
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8SubtractPfmmff, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__SubtractPfmmff, .Lfunc_end0-_Z23__device_stub__SubtractPfmmff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8SubtractPfmmff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8SubtractPfmmff,@object # @_Z8SubtractPfmmff
.section .rodata,"a",@progbits
.globl _Z8SubtractPfmmff
.p2align 3, 0x0
_Z8SubtractPfmmff:
.quad _Z23__device_stub__SubtractPfmmff
.size _Z8SubtractPfmmff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8SubtractPfmmff"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__SubtractPfmmff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8SubtractPfmmff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8SubtractPfmmff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fc80000011404 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R5, c[0x0][0x174], PT, P0 ; /* 0x00005d0005007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0090*/ IADD3 R2, P1, RZ, -c[0x0][0x170], RZ ; /* 0x80005c00ff027a10 */
/* 0x000fe20007f3e0ff */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff067624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0004 */
/*00d0*/ IADD3 R0, P0, -R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a10 */
/* 0x000fe40007f1e1ff */
/*00e0*/ IADD3.X R3, RZ, ~c[0x0][0x174], RZ, P1, !PT ; /* 0x80005d00ff037a10 */
/* 0x000fe40000ffe4ff */
/*00f0*/ IADD3.X R6, R6, -0x1, RZ, P0, !PT ; /* 0xffffffff06067810 */
/* 0x000fc600007fe4ff */
/*0100*/ IMAD.WIDE.U32 R2, R0, c[0x0][0x170], R2 ; /* 0x00005c0000027a25 */
/* 0x000fc800078e0002 */
/*0110*/ IMAD R7, R6, c[0x0][0x170], RZ ; /* 0x00005c0006077a24 */
/* 0x000fe200078e02ff */
/*0120*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x000fc60000000f00 */
/*0130*/ IMAD R13, R0, c[0x0][0x174], R7 ; /* 0x00005d00000d7a24 */
/* 0x000fe400078e0207 */
/*0140*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0005 */
/*0150*/ IMAD.IADD R11, R3, 0x1, R13 ; /* 0x00000001030b7824 */
/* 0x000fe400078e020d */
/*0160*/ IADD3 R5, P0, R6, R2, RZ ; /* 0x0000000206057210 */
/* 0x000fca0007f1e0ff */
/*0170*/ IMAD.X R8, R7, 0x1, R11, P0 ; /* 0x0000000107087824 */
/* 0x000fe200000e060b */
/*0180*/ LEA R4, P0, R5, c[0x0][0x160], 0x2 ; /* 0x0000580005047a11 */
/* 0x000fe200078010ff */
/*0190*/ IMAD.WIDE.U32 R6, R0, c[0x0][0x170], R6 ; /* 0x00005c0000067a25 */
/* 0x000fc600078e0006 */
/*01a0*/ LEA.HI.X R5, R5, c[0x0][0x164], R8, 0x2, P0 ; /* 0x0000590005057a11 */
/* 0x000fe400000f1408 */
/*01b0*/ IADD3 R7, R13, R7, RZ ; /* 0x000000070d077210 */
/* 0x000fe40007ffe0ff */
/*01c0*/ LEA R8, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006087a11 */
/* 0x000fc800078010ff */
/*01d0*/ LEA.HI.X R9, R6, c[0x0][0x164], R7, 0x2, P0 ; /* 0x0000590006097a11 */
/* 0x000fe400000f1407 */
/*01e0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee2000c1e1900 */
/*0200*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0f7624 */
/* 0x000fe400078e00ff */
/*0210*/ FMUL R7, R6, c[0x0][0x17c] ; /* 0x00005f0006077a20 */
/* 0x004fe40000400000 */
/*0220*/ IMAD R6, R15, c[0x0][0xc], R10 ; /* 0x000003000f067a24 */
/* 0x000fc400078e020a */
/*0230*/ FFMA R7, R8, c[0x0][0x178], -R7 ; /* 0x00005e0008077a23 */
/* 0x008fc60000000807 */
/*0240*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fe40003f06070 */
/*0250*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e2000c101904 */
/*0260*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fe40000000f00 */
/*0270*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x001fc80000011406 */
/*0280*/ ISETP.GE.U32.AND.EX P0, PT, R7, c[0x0][0x174], PT, P0 ; /* 0x00005d0007007a0c */
/* 0x000fda0003f06100 */
/*0290*/ @!P0 BRA 0x160 ; /* 0xfffffec000008947 */
/* 0x000fea000383ffff */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ BRA 0x2b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8SubtractPfmmff
.globl _Z8SubtractPfmmff
.p2align 8
.type _Z8SubtractPfmmff,@function
_Z8SubtractPfmmff:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_load_b32 s12, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s10, -1
s_addc_u32 s5, s11, -1
s_mul_i32 s7, s4, s3
s_mul_hi_u32 s13, s4, s2
s_mul_i32 s5, s5, s2
s_add_i32 s7, s13, s7
s_mul_i32 s4, s4, s2
s_add_i32 s5, s7, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_add_u32 s4, s8, s4
s_addc_u32 s5, s9, s5
s_add_u32 s7, s10, -2
s_addc_u32 s10, s11, -1
s_mul_i32 s11, s7, s3
s_mul_hi_u32 s13, s7, s2
s_mul_i32 s14, s10, s2
s_add_i32 s11, s13, s11
s_mul_i32 s10, s7, s2
s_add_i32 s11, s11, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[10:11], 2
s_add_u32 s7, s8, s10
s_addc_u32 s8, s9, s11
s_add_i32 s15, s15, s12
s_mov_b32 s9, 0
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_mul_i32 s6, s12, s6
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v5, vcc_lo, s7, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s8, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[3:4]
s_clause 0x1
global_load_b32 v2, v[5:6], off
global_load_b32 v0, v[0:1], off
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(1)
v_mul_f32_e32 v7, s1, v2
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
v_add_nc_u32_e32 v3, s6, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_fma_f32 v0, v0, s0, -v7
global_store_b32 v[5:6], v0, off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8SubtractPfmmff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8SubtractPfmmff, .Lfunc_end0-_Z8SubtractPfmmff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8SubtractPfmmff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8SubtractPfmmff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00015030_00000000-6_Subtract.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8SubtractPfmmffPfmmff
.type _Z31__device_stub__Z8SubtractPfmmffPfmmff, @function
_Z31__device_stub__Z8SubtractPfmmffPfmmff:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8SubtractPfmmff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z8SubtractPfmmffPfmmff, .-_Z31__device_stub__Z8SubtractPfmmffPfmmff
.globl _Z8SubtractPfmmff
.type _Z8SubtractPfmmff, @function
_Z8SubtractPfmmff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8SubtractPfmmffPfmmff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8SubtractPfmmff, .-_Z8SubtractPfmmff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8SubtractPfmmff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8SubtractPfmmff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Subtract.hip"
.globl _Z23__device_stub__SubtractPfmmff # -- Begin function _Z23__device_stub__SubtractPfmmff
.p2align 4, 0x90
.type _Z23__device_stub__SubtractPfmmff,@function
_Z23__device_stub__SubtractPfmmff: # @_Z23__device_stub__SubtractPfmmff
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8SubtractPfmmff, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__SubtractPfmmff, .Lfunc_end0-_Z23__device_stub__SubtractPfmmff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8SubtractPfmmff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8SubtractPfmmff,@object # @_Z8SubtractPfmmff
.section .rodata,"a",@progbits
.globl _Z8SubtractPfmmff
.p2align 3, 0x0
_Z8SubtractPfmmff:
.quad _Z23__device_stub__SubtractPfmmff
.size _Z8SubtractPfmmff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8SubtractPfmmff"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__SubtractPfmmff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8SubtractPfmmff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <vector>
__global__
void convolution_1d_y(float *const input_image,
int width,
int channels,
int kernel_size,
float *result) {
int col = blockDim.x * blockIdx.x + threadIdx.x;
int row = blockIdx.y;
const int stride = gridDim.x * blockDim.x;
const int offset = row * width * channels;
const float kernel_weight = 1.0f / kernel_size;
const int half_kernel = kernel_size / 2;
// Individual threads, each one dealing with 1 channel
for (; col >= half_kernel * channels && col < (width - half_kernel) * channels; col += stride) {
// Sum neighbors
for (int i = -half_kernel * channels; i <= half_kernel * channels; i += channels)
result[offset + col] += input_image[offset + col + i];
// Reweigh
result[offset + col] *= kernel_weight;
}
}
void blur_separable_gpu(float *const input_image,
int width,
int height,
int channels,
float* result) {
const dim3 blockSize(256, 1);
const dim3 gridSize((width * 3 + blockSize.x - 1) / blockSize.x, height);
convolution_1d_y<<<gridSize, blockSize>>>(input_image, width, 3, 9, result);
} | code for sm_80
Function : _Z16convolution_1d_yPfiiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F R4, c[0x0][0x170] ; /* 0x00005c0000047b06 */
/* 0x000e220000201400 */
/*0020*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000ea20000002600 */
/*0050*/ IADD3 R0, R4, 0x1800000, RZ ; /* 0x0180000004007810 */
/* 0x001fc80007ffe0ff */
/*0060*/ LOP3.LUT R0, R0, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000000007812 */
/* 0x000fc800078ec0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R0, 0x1ffffff, PT ; /* 0x01ffffff0000780c */
/* 0x000fe20003f04070 */
/*0080*/ IMAD R0, R2, c[0x0][0x0], R3 ; /* 0x0000000002007a24 */
/* 0x002fe400078e0203 */
/*0090*/ IMAD R3, R5, c[0x0][0x168], RZ ; /* 0x00005a0005037a24 */
/* 0x004fd400078e02ff */
/*00a0*/ @P0 BRA 0xf0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*00b0*/ MOV R2, 0xd0 ; /* 0x000000d000027802 */
/* 0x000fe40000000f00 */
/*00c0*/ CALL.REL.NOINC 0x430 ; /* 0x0000036000007944 */
/* 0x000fea0003c00000 */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0006 */
/*00e0*/ BRA 0x130 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*00f0*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x000e240000001000 */
/*0100*/ FFMA R2, R4, R5, -1 ; /* 0xbf80000004027423 */
/* 0x001fc80000000005 */
/*0110*/ FADD.FTZ R2, -R2, -RZ ; /* 0x800000ff02027221 */
/* 0x000fc80000010100 */
/*0120*/ FFMA R2, R5, R2, R5 ; /* 0x0000000205027223 */
/* 0x000fe40000000005 */
/*0130*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0140*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fe4000f8f083f */
/*0150*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000a00 */
/*0160*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc80008011404 */
/*0170*/ UIMAD UR8, UR4, UR7, URZ ; /* 0x00000007040872a4 */
/* 0x000fe4000f8e023f */
/*0180*/ UIADD3 UR5, -UR4, UR6, URZ ; /* 0x0000000604057290 */
/* 0x000fc8000fffe13f */
/*0190*/ UIMAD UR5, UR5, UR7, URZ ; /* 0x00000007050572a4 */
/* 0x000fe2000f8e023f */
/*01a0*/ ISETP.GE.AND P0, PT, R0, UR8, PT ; /* 0x0000000800007c0c */
/* 0x000fca000bf06270 */
/*01b0*/ ISETP.GE.OR P0, PT, R0, UR5, !P0 ; /* 0x0000000500007c0c */
/* 0x000fda000c706670 */
/*01c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.MOV R8, RZ, RZ, -c[0x0][0x16c] ; /* 0x80005b00ff087624 */
/* 0x000fe200078e02ff */
/*01e0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*01f0*/ IMAD R8, R8, UR4, RZ ; /* 0x0000000408087c24 */
/* 0x000fca000f8e02ff */
/*0200*/ ISETP.GT.AND P0, PT, R8, UR8, PT ; /* 0x0000000808007c0c */
/* 0x000fda000bf04270 */
/*0210*/ @P0 BRA 0x370 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*0220*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe400078e00ff */
/*0230*/ IMAD R12, R3, c[0x0][0x16c], R0 ; /* 0x00005b00030c7a24 */
/* 0x000fc800078e0200 */
/*0240*/ IMAD.WIDE R6, R12, R11, c[0x0][0x178] ; /* 0x00005e000c067625 */
/* 0x001fca00078e020b */
/*0250*/ LDG.E R9, [R6.64] ; /* 0x0000000606097981 */
/* 0x000162000c1e1900 */
/*0260*/ MOV R10, R8 ; /* 0x00000008000a7202 */
/* 0x000fca0000000f00 */
/*0270*/ IMAD.IADD R4, R12, 0x1, R10 ; /* 0x000000010c047824 */
/* 0x000fc800078e020a */
/*0280*/ IMAD.WIDE R4, R4, R11, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e020b */
/*0290*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ IADD3 R10, R10, c[0x0][0x16c], RZ ; /* 0x00005b000a0a7a10 */
/* 0x000fc80007ffe0ff */
/*02b0*/ ISETP.GT.AND P0, PT, R10, UR8, PT ; /* 0x000000080a007c0c */
/* 0x000fe2000bf04270 */
/*02c0*/ FADD R9, R4, R9 ; /* 0x0000000904097221 */
/* 0x026fca0000000000 */
/*02d0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0003ee000c101906 */
/*02e0*/ @!P0 BRA 0x270 ; /* 0xffffff8000008947 */
/* 0x000fea000383ffff */
/*02f0*/ FMUL R9, R9, R2 ; /* 0x0000000209097220 */
/* 0x002fe40000400000 */
/*0300*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff057624 */
/* 0x000fc600078e00ff */
/*0310*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0003e2000c101906 */
/*0320*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x000fca00078e0200 */
/*0330*/ ISETP.GE.AND P0, PT, R0.reuse, UR8, PT ; /* 0x0000000800007c0c */
/* 0x040fe4000bf06270 */
/*0340*/ ISETP.LT.AND P1, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fda000bf21270 */
/*0350*/ @P0 BRA P1, 0x220 ; /* 0xfffffec000000947 */
/* 0x002fea000083ffff */
/*0360*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0370*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x001fe400078e00ff */
/*0380*/ IMAD R4, R3, c[0x0][0x16c], R0 ; /* 0x00005b0003047a24 */
/* 0x000fc800078e0200 */
/*0390*/ IMAD.WIDE R4, R4, R5, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fca00078e0205 */
/*03a0*/ LDG.E R7, [R4.64] ; /* 0x0000000604077981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ MOV R9, c[0x0][0xc] ; /* 0x0000030000097a02 */
/* 0x000fca0000000f00 */
/*03c0*/ IMAD R0, R9, c[0x0][0x0], R0 ; /* 0x0000000009007a24 */
/* 0x000fca00078e0200 */
/*03d0*/ ISETP.GE.AND P0, PT, R0.reuse, UR8, PT ; /* 0x0000000800007c0c */
/* 0x040fe4000bf06270 */
/*03e0*/ ISETP.LT.AND P1, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fe2000bf21270 */
/*03f0*/ FMUL R7, R7, R2 ; /* 0x0000000207077220 */
/* 0x004fca0000400000 */
/*0400*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*0410*/ @P0 BRA P1, 0x370 ; /* 0xffffff5000000947 */
/* 0x000fea000083ffff */
/*0420*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0430*/ IMAD.SHL.U32 R5, R4, 0x2, RZ ; /* 0x0000000204057824 */
/* 0x000fca00078e00ff */
/*0440*/ SHF.R.U32.HI R5, RZ, 0x18, R5 ; /* 0x00000018ff057819 */
/* 0x000fc80000011605 */
/*0450*/ ISETP.NE.U32.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05070 */
/*0460*/ @P0 BRA 0x520 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0470*/ IMAD.SHL.U32 R5, R4, 0x2, RZ ; /* 0x0000000204057824 */
/* 0x000fca00078e00ff */
/*0480*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0490*/ @!P0 MUFU.RCP R5, R4 ; /* 0x0000000400058308 */
/* 0x0000620000001000 */
/*04a0*/ @!P0 BRA 0x740 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*04b0*/ FFMA R4, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004047823 */
/* 0x001fc800000000ff */
/*04c0*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x002e240000001000 */
/*04d0*/ FFMA R6, R4, R5, -1 ; /* 0xbf80000004067423 */
/* 0x001fc80000000005 */
/*04e0*/ FADD.FTZ R6, -R6, -RZ ; /* 0x800000ff06067221 */
/* 0x000fc80000010100 */
/*04f0*/ FFMA R5, R5, R6, R5 ; /* 0x0000000605057223 */
/* 0x000fc80000000005 */
/*0500*/ FFMA R5, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005057823 */
/* 0x000fe200000000ff */
/*0510*/ BRA 0x740 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*0520*/ IADD3 R6, R5, -0xfd, RZ ; /* 0xffffff0305067810 */
/* 0x000fc80007ffe0ff */
/*0530*/ ISETP.GT.U32.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fda0003f04070 */
/*0540*/ @P0 BRA 0x730 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*0550*/ LOP3.LUT R7, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04077812 */
/* 0x000fe200078ec0ff */
/*0560*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3 ; /* 0x00000003ff0b7424 */
/* 0x000fc600078e00ff */
/*0570*/ LOP3.LUT R7, R7, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000007077812 */
/* 0x000fe400078efcff */
/*0580*/ SHF.L.U32 R12, R11, R6, RZ ; /* 0x000000060b0c7219 */
/* 0x000fe400000006ff */
/*0590*/ MUFU.RCP R8, R7 ; /* 0x0000000700087308 */
/* 0x000e240000001000 */
/*05a0*/ FFMA R9, R7, R8, -1 ; /* 0xbf80000007097423 */
/* 0x001fc80000000008 */
/*05b0*/ FADD.FTZ R9, -R9, -RZ ; /* 0x800000ff09097221 */
/* 0x000fc80000010100 */
/*05c0*/ FFMA.RM R10, R8.reuse, R9.reuse, R8.reuse ; /* 0x00000009080a7223 */
/* 0x1c0fe40000004008 */
/*05d0*/ FFMA.RP R9, R8, R9, R8 ; /* 0x0000000908097223 */
/* 0x000fc60000008008 */
/*05e0*/ LOP3.LUT R8, R10.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0a087812 */
/* 0x040fe400078ec0ff */
/*05f0*/ FSETP.NEU.FTZ.AND P0, PT, R10, R9, PT ; /* 0x000000090a00720b */
/* 0x000fe40003f1d000 */
/*0600*/ LOP3.LUT R9, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008097812 */
/* 0x000fe400078efcff */
/*0610*/ SEL R8, RZ, 0xffffffff, !P0 ; /* 0xffffffffff087807 */
/* 0x000fe40004000000 */
/*0620*/ LOP3.LUT R7, R12, R9, RZ, 0xc0, !PT ; /* 0x000000090c077212 */
/* 0x000fe400078ec0ff */
/*0630*/ IADD3 R8, -R8, RZ, RZ ; /* 0x000000ff08087210 */
/* 0x000fc40007ffe1ff */
/*0640*/ SHF.R.U32.HI R7, RZ, R6.reuse, R7 ; /* 0x00000006ff077219 */
/* 0x080fe40000011607 */
/*0650*/ LOP3.LUT P1, RZ, R8, R6, R9, 0xf8, !PT ; /* 0x0000000608ff7212 */
/* 0x000fe4000782f809 */
/*0660*/ LOP3.LUT P0, RZ, R7.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000107ff7812 */
/* 0x040fe4000780c0ff */
/*0670*/ LOP3.LUT P2, RZ, R7, 0x2, RZ, 0xc0, !PT ; /* 0x0000000207ff7812 */
/* 0x000fc8000784c0ff */
/*0680*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*0690*/ LOP3.LUT P1, RZ, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04ff7812 */
/* 0x000fe4000782c0ff */
/*06a0*/ SEL R6, RZ, 0x1, !P0 ; /* 0x00000001ff067807 */
/* 0x000fca0004000000 */
/*06b0*/ IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff067224 */
/* 0x000fca00078e0a06 */
/*06c0*/ ISETP.GE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f06270 */
/*06d0*/ IADD3 R6, R5, -0xfc, RZ ; /* 0xffffff0405067810 */
/* 0x000fc80007ffe0ff */
/*06e0*/ SHF.R.U32.HI R5, RZ, R6, R9 ; /* 0x00000006ff057219 */
/* 0x000fce0000011609 */
/*06f0*/ @!P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105058810 */
/* 0x000fca0007ffe0ff */
/*0700*/ @!P1 IMAD.SHL.U32 R5, R5, 0x2, RZ ; /* 0x0000000205059824 */
/* 0x000fca00078e00ff */
/*0710*/ LOP3.LUT R5, R5, 0x80000000, R4, 0xf8, !PT ; /* 0x8000000005057812 */
/* 0x000fe200078ef804 */
/*0720*/ BRA 0x740 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0730*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x0000640000001000 */
/*0740*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x002fe200078e0005 */
/*0750*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x001fe20000000f00 */
/*0760*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0770*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff88004007950 */
/* 0x000fea0003c3ffff */
/*0780*/ BRA 0x780; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <vector>
__global__
void convolution_1d_y(float *const input_image,
int width,
int channels,
int kernel_size,
float *result) {
int col = blockDim.x * blockIdx.x + threadIdx.x;
int row = blockIdx.y;
const int stride = gridDim.x * blockDim.x;
const int offset = row * width * channels;
const float kernel_weight = 1.0f / kernel_size;
const int half_kernel = kernel_size / 2;
// Individual threads, each one dealing with 1 channel
for (; col >= half_kernel * channels && col < (width - half_kernel) * channels; col += stride) {
// Sum neighbors
for (int i = -half_kernel * channels; i <= half_kernel * channels; i += channels)
result[offset + col] += input_image[offset + col + i];
// Reweigh
result[offset + col] *= kernel_weight;
}
}
void blur_separable_gpu(float *const input_image,
int width,
int height,
int channels,
float* result) {
const dim3 blockSize(256, 1);
const dim3 gridSize((width * 3 + blockSize.x - 1) / blockSize.x, height);
convolution_1d_y<<<gridSize, blockSize>>>(input_image, width, 3, 9, result);
} | .file "tmpxft_000eff88_00000000-6_convolution_gpu_blur_separable.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16convolution_1d_yPfiiiS_PfiiiS_
.type _Z41__device_stub__Z16convolution_1d_yPfiiiS_PfiiiS_, @function
_Z41__device_stub__Z16convolution_1d_yPfiiiS_PfiiiS_:
.LFB4057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16convolution_1d_yPfiiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4057:
.size _Z41__device_stub__Z16convolution_1d_yPfiiiS_PfiiiS_, .-_Z41__device_stub__Z16convolution_1d_yPfiiiS_PfiiiS_
.globl _Z16convolution_1d_yPfiiiS_
.type _Z16convolution_1d_yPfiiiS_, @function
_Z16convolution_1d_yPfiiiS_:
.LFB4058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16convolution_1d_yPfiiiS_PfiiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4058:
.size _Z16convolution_1d_yPfiiiS_, .-_Z16convolution_1d_yPfiiiS_
.globl _Z18blur_separable_gpuPfiiiS_
.type _Z18blur_separable_gpuPfiiiS_, @function
_Z18blur_separable_gpuPfiiiS_:
.LFB4032:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movl %esi, %ebx
movq %r8, %r12
movl $1, 12(%rsp)
leal 255(%rsi,%rsi,2), %eax
shrl $8, %eax
movl %eax, 20(%rsp)
movl %edx, 24(%rsp)
movl $256, 8(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %r12, %r8
movl $9, %ecx
movl $3, %edx
movl %ebx, %esi
movq %rbp, %rdi
call _Z41__device_stub__Z16convolution_1d_yPfiiiS_PfiiiS_
jmp .L11
.cfi_endproc
.LFE4032:
.size _Z18blur_separable_gpuPfiiiS_, .-_Z18blur_separable_gpuPfiiiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16convolution_1d_yPfiiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16convolution_1d_yPfiiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <vector>
__global__
void convolution_1d_y(float *const input_image,
int width,
int channels,
int kernel_size,
float *result) {
int col = blockDim.x * blockIdx.x + threadIdx.x;
int row = blockIdx.y;
const int stride = gridDim.x * blockDim.x;
const int offset = row * width * channels;
const float kernel_weight = 1.0f / kernel_size;
const int half_kernel = kernel_size / 2;
// Individual threads, each one dealing with 1 channel
for (; col >= half_kernel * channels && col < (width - half_kernel) * channels; col += stride) {
// Sum neighbors
for (int i = -half_kernel * channels; i <= half_kernel * channels; i += channels)
result[offset + col] += input_image[offset + col + i];
// Reweigh
result[offset + col] *= kernel_weight;
}
}
void blur_separable_gpu(float *const input_image,
int width,
int height,
int channels,
float* result) {
const dim3 blockSize(256, 1);
const dim3 gridSize((width * 3 + blockSize.x - 1) / blockSize.x, height);
convolution_1d_y<<<gridSize, blockSize>>>(input_image, width, 3, 9, result);
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
__global__
void convolution_1d_y(float *const input_image,
int width,
int channels,
int kernel_size,
float *result) {
int col = blockDim.x * blockIdx.x + threadIdx.x;
int row = blockIdx.y;
const int stride = gridDim.x * blockDim.x;
const int offset = row * width * channels;
const float kernel_weight = 1.0f / kernel_size;
const int half_kernel = kernel_size / 2;
// Individual threads, each one dealing with 1 channel
for (; col >= half_kernel * channels && col < (width - half_kernel) * channels; col += stride) {
// Sum neighbors
for (int i = -half_kernel * channels; i <= half_kernel * channels; i += channels)
result[offset + col] += input_image[offset + col + i];
// Reweigh
result[offset + col] *= kernel_weight;
}
}
void blur_separable_gpu(float *const input_image,
int width,
int height,
int channels,
float* result) {
const dim3 blockSize(256, 1);
const dim3 gridSize((width * 3 + blockSize.x - 1) / blockSize.x, height);
convolution_1d_y<<<gridSize, blockSize>>>(input_image, width, 3, 9, result);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
__global__
void convolution_1d_y(float *const input_image,
int width,
int channels,
int kernel_size,
float *result) {
int col = blockDim.x * blockIdx.x + threadIdx.x;
int row = blockIdx.y;
const int stride = gridDim.x * blockDim.x;
const int offset = row * width * channels;
const float kernel_weight = 1.0f / kernel_size;
const int half_kernel = kernel_size / 2;
// Individual threads, each one dealing with 1 channel
for (; col >= half_kernel * channels && col < (width - half_kernel) * channels; col += stride) {
// Sum neighbors
for (int i = -half_kernel * channels; i <= half_kernel * channels; i += channels)
result[offset + col] += input_image[offset + col + i];
// Reweigh
result[offset + col] *= kernel_weight;
}
}
void blur_separable_gpu(float *const input_image,
int width,
int height,
int channels,
float* result) {
const dim3 blockSize(256, 1);
const dim3 gridSize((width * 3 + blockSize.x - 1) / blockSize.x, height);
convolution_1d_y<<<gridSize, blockSize>>>(input_image, width, 3, 9, result);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16convolution_1d_yPfiiiS_
.globl _Z16convolution_1d_yPfiiiS_
.p2align 8
.type _Z16convolution_1d_yPfiiiS_,@function
_Z16convolution_1d_yPfiiiS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x8
s_add_u32 s6, s0, 32
s_addc_u32 s7, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s2, 0xffff
s_lshr_b32 s2, s3, 31
s_mul_i32 s14, s14, s8
s_add_i32 s2, s3, s2
v_add_nc_u32_e32 v7, s14, v0
s_ashr_i32 s9, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_sub_i32 s11, s4, s9
s_mul_i32 s10, s9, s5
s_mul_i32 s11, s11, s5
v_cmp_le_i32_e32 vcc_lo, s10, v7
v_cmp_gt_i32_e64 s2, s11, v7
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s12, s2
s_cbranch_execz .LBB0_6
v_cvt_f32_i32_e32 v1, s3
s_load_b32 s13, s[6:7], 0x0
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x18
s_sub_i32 s1, 0, s10
s_mul_i32 s0, s15, s4
v_div_scale_f32 v2, null, v1, v1, 1.0
v_div_scale_f32 v5, vcc_lo, 1.0, v1, 1.0
s_cmp_ge_i32 s10, s1
s_delay_alu instid0(VALU_DEP_2)
v_rcp_f32_e32 v3, v2
s_mul_i32 s4, s0, s5
s_cselect_b32 s12, -1, 0
s_sub_i32 s0, s0, s9
s_ashr_i32 s9, s5, 31
s_mul_i32 s0, s5, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_add3_u32 v0, s14, s0, v0
s_mov_b32 s14, 0
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v2, v3, 1.0
s_waitcnt lgkmcnt(0)
s_mul_i32 s13, s13, s8
s_mov_b32 s8, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_lshl_b64 s[8:9], s[8:9], 2
v_fmac_f32_e32 v3, v4, v3
v_mul_f32_e32 v4, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v2, v4, v5
v_fmac_f32_e32 v4, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v2, v4, v5
v_div_fmas_f32 v2, v2, v3, v4
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v8, v2, v1, 1.0
s_branch .LBB0_3
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v7, s13, v7
v_add_nc_u32_e32 v0, s13, v0
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s0, s11, v7
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s10, v7
global_load_b32 v3, v[1:2], off
s_or_b32 s0, vcc_lo, s0
s_and_b32 s0, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s14, s0, s14
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, v8, v3
global_store_b32 v[1:2], v3, off
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB0_6
.LBB0_3:
v_add_nc_u32_e32 v2, s4, v7
s_and_not1_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB0_2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s0, s1
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v9, v[3:4], off
.LBB0_5:
global_load_b32 v1, v[5:6], off
v_add_co_u32 v5, vcc_lo, v5, s8
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
s_add_i32 s0, s0, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_i32 s0, s10
s_waitcnt vmcnt(0)
v_add_f32_e32 v9, v1, v9
global_store_b32 v[3:4], v9, off
s_cbranch_scc0 .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16convolution_1d_yPfiiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16convolution_1d_yPfiiiS_, .Lfunc_end0-_Z16convolution_1d_yPfiiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16convolution_1d_yPfiiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16convolution_1d_yPfiiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
__global__
void convolution_1d_y(float *const input_image,
int width,
int channels,
int kernel_size,
float *result) {
int col = blockDim.x * blockIdx.x + threadIdx.x;
int row = blockIdx.y;
const int stride = gridDim.x * blockDim.x;
const int offset = row * width * channels;
const float kernel_weight = 1.0f / kernel_size;
const int half_kernel = kernel_size / 2;
// Individual threads, each one dealing with 1 channel
for (; col >= half_kernel * channels && col < (width - half_kernel) * channels; col += stride) {
// Sum neighbors
for (int i = -half_kernel * channels; i <= half_kernel * channels; i += channels)
result[offset + col] += input_image[offset + col + i];
// Reweigh
result[offset + col] *= kernel_weight;
}
}
void blur_separable_gpu(float *const input_image,
int width,
int height,
int channels,
float* result) {
const dim3 blockSize(256, 1);
const dim3 gridSize((width * 3 + blockSize.x - 1) / blockSize.x, height);
convolution_1d_y<<<gridSize, blockSize>>>(input_image, width, 3, 9, result);
} | .text
.file "convolution_gpu_blur_separable.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z31__device_stub__convolution_1d_yPfiiiS_ # -- Begin function _Z31__device_stub__convolution_1d_yPfiiiS_
.p2align 4, 0x90
.type _Z31__device_stub__convolution_1d_yPfiiiS_,@function
_Z31__device_stub__convolution_1d_yPfiiiS_: # @_Z31__device_stub__convolution_1d_yPfiiiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16convolution_1d_yPfiiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__convolution_1d_yPfiiiS_, .Lfunc_end0-_Z31__device_stub__convolution_1d_yPfiiiS_
.cfi_endproc
# -- End function
.globl _Z18blur_separable_gpuPfiiiS_ # -- Begin function _Z18blur_separable_gpuPfiiiS_
.p2align 4, 0x90
.type _Z18blur_separable_gpuPfiiiS_,@function
_Z18blur_separable_gpuPfiiiS_: # @_Z18blur_separable_gpuPfiiiS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %r8, %rbx
# kill: def $edx killed $edx def $rdx
movl %esi, %r14d
movq %rdi, %r15
leal (%r14,%r14,2), %edi
addl $255, %edi
shrl $8, %edi
shlq $32, %rdx
orq %rdx, %rdi
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r15, 72(%rsp)
movl %r14d, 12(%rsp)
movl $3, 8(%rsp)
movl $9, 4(%rsp)
movq %rbx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16convolution_1d_yPfiiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z18blur_separable_gpuPfiiiS_, .Lfunc_end1-_Z18blur_separable_gpuPfiiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16convolution_1d_yPfiiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16convolution_1d_yPfiiiS_,@object # @_Z16convolution_1d_yPfiiiS_
.section .rodata,"a",@progbits
.globl _Z16convolution_1d_yPfiiiS_
.p2align 3, 0x0
_Z16convolution_1d_yPfiiiS_:
.quad _Z31__device_stub__convolution_1d_yPfiiiS_
.size _Z16convolution_1d_yPfiiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16convolution_1d_yPfiiiS_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__convolution_1d_yPfiiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16convolution_1d_yPfiiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16convolution_1d_yPfiiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F R4, c[0x0][0x170] ; /* 0x00005c0000047b06 */
/* 0x000e220000201400 */
/*0020*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000ea20000002600 */
/*0050*/ IADD3 R0, R4, 0x1800000, RZ ; /* 0x0180000004007810 */
/* 0x001fc80007ffe0ff */
/*0060*/ LOP3.LUT R0, R0, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000000007812 */
/* 0x000fc800078ec0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R0, 0x1ffffff, PT ; /* 0x01ffffff0000780c */
/* 0x000fe20003f04070 */
/*0080*/ IMAD R0, R2, c[0x0][0x0], R3 ; /* 0x0000000002007a24 */
/* 0x002fe400078e0203 */
/*0090*/ IMAD R3, R5, c[0x0][0x168], RZ ; /* 0x00005a0005037a24 */
/* 0x004fd400078e02ff */
/*00a0*/ @P0 BRA 0xf0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*00b0*/ MOV R2, 0xd0 ; /* 0x000000d000027802 */
/* 0x000fe40000000f00 */
/*00c0*/ CALL.REL.NOINC 0x430 ; /* 0x0000036000007944 */
/* 0x000fea0003c00000 */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0006 */
/*00e0*/ BRA 0x130 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*00f0*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x000e240000001000 */
/*0100*/ FFMA R2, R4, R5, -1 ; /* 0xbf80000004027423 */
/* 0x001fc80000000005 */
/*0110*/ FADD.FTZ R2, -R2, -RZ ; /* 0x800000ff02027221 */
/* 0x000fc80000010100 */
/*0120*/ FFMA R2, R5, R2, R5 ; /* 0x0000000205027223 */
/* 0x000fe40000000005 */
/*0130*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0140*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fe4000f8f083f */
/*0150*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000a00 */
/*0160*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc80008011404 */
/*0170*/ UIMAD UR8, UR4, UR7, URZ ; /* 0x00000007040872a4 */
/* 0x000fe4000f8e023f */
/*0180*/ UIADD3 UR5, -UR4, UR6, URZ ; /* 0x0000000604057290 */
/* 0x000fc8000fffe13f */
/*0190*/ UIMAD UR5, UR5, UR7, URZ ; /* 0x00000007050572a4 */
/* 0x000fe2000f8e023f */
/*01a0*/ ISETP.GE.AND P0, PT, R0, UR8, PT ; /* 0x0000000800007c0c */
/* 0x000fca000bf06270 */
/*01b0*/ ISETP.GE.OR P0, PT, R0, UR5, !P0 ; /* 0x0000000500007c0c */
/* 0x000fda000c706670 */
/*01c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.MOV R8, RZ, RZ, -c[0x0][0x16c] ; /* 0x80005b00ff087624 */
/* 0x000fe200078e02ff */
/*01e0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*01f0*/ IMAD R8, R8, UR4, RZ ; /* 0x0000000408087c24 */
/* 0x000fca000f8e02ff */
/*0200*/ ISETP.GT.AND P0, PT, R8, UR8, PT ; /* 0x0000000808007c0c */
/* 0x000fda000bf04270 */
/*0210*/ @P0 BRA 0x370 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*0220*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe400078e00ff */
/*0230*/ IMAD R12, R3, c[0x0][0x16c], R0 ; /* 0x00005b00030c7a24 */
/* 0x000fc800078e0200 */
/*0240*/ IMAD.WIDE R6, R12, R11, c[0x0][0x178] ; /* 0x00005e000c067625 */
/* 0x001fca00078e020b */
/*0250*/ LDG.E R9, [R6.64] ; /* 0x0000000606097981 */
/* 0x000162000c1e1900 */
/*0260*/ MOV R10, R8 ; /* 0x00000008000a7202 */
/* 0x000fca0000000f00 */
/*0270*/ IMAD.IADD R4, R12, 0x1, R10 ; /* 0x000000010c047824 */
/* 0x000fc800078e020a */
/*0280*/ IMAD.WIDE R4, R4, R11, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e020b */
/*0290*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ IADD3 R10, R10, c[0x0][0x16c], RZ ; /* 0x00005b000a0a7a10 */
/* 0x000fc80007ffe0ff */
/*02b0*/ ISETP.GT.AND P0, PT, R10, UR8, PT ; /* 0x000000080a007c0c */
/* 0x000fe2000bf04270 */
/*02c0*/ FADD R9, R4, R9 ; /* 0x0000000904097221 */
/* 0x026fca0000000000 */
/*02d0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0003ee000c101906 */
/*02e0*/ @!P0 BRA 0x270 ; /* 0xffffff8000008947 */
/* 0x000fea000383ffff */
/*02f0*/ FMUL R9, R9, R2 ; /* 0x0000000209097220 */
/* 0x002fe40000400000 */
/*0300*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff057624 */
/* 0x000fc600078e00ff */
/*0310*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0003e2000c101906 */
/*0320*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x000fca00078e0200 */
/*0330*/ ISETP.GE.AND P0, PT, R0.reuse, UR8, PT ; /* 0x0000000800007c0c */
/* 0x040fe4000bf06270 */
/*0340*/ ISETP.LT.AND P1, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fda000bf21270 */
/*0350*/ @P0 BRA P1, 0x220 ; /* 0xfffffec000000947 */
/* 0x002fea000083ffff */
/*0360*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0370*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x001fe400078e00ff */
/*0380*/ IMAD R4, R3, c[0x0][0x16c], R0 ; /* 0x00005b0003047a24 */
/* 0x000fc800078e0200 */
/*0390*/ IMAD.WIDE R4, R4, R5, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fca00078e0205 */
/*03a0*/ LDG.E R7, [R4.64] ; /* 0x0000000604077981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ MOV R9, c[0x0][0xc] ; /* 0x0000030000097a02 */
/* 0x000fca0000000f00 */
/*03c0*/ IMAD R0, R9, c[0x0][0x0], R0 ; /* 0x0000000009007a24 */
/* 0x000fca00078e0200 */
/*03d0*/ ISETP.GE.AND P0, PT, R0.reuse, UR8, PT ; /* 0x0000000800007c0c */
/* 0x040fe4000bf06270 */
/*03e0*/ ISETP.LT.AND P1, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fe2000bf21270 */
/*03f0*/ FMUL R7, R7, R2 ; /* 0x0000000207077220 */
/* 0x004fca0000400000 */
/*0400*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*0410*/ @P0 BRA P1, 0x370 ; /* 0xffffff5000000947 */
/* 0x000fea000083ffff */
/*0420*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0430*/ IMAD.SHL.U32 R5, R4, 0x2, RZ ; /* 0x0000000204057824 */
/* 0x000fca00078e00ff */
/*0440*/ SHF.R.U32.HI R5, RZ, 0x18, R5 ; /* 0x00000018ff057819 */
/* 0x000fc80000011605 */
/*0450*/ ISETP.NE.U32.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05070 */
/*0460*/ @P0 BRA 0x520 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0470*/ IMAD.SHL.U32 R5, R4, 0x2, RZ ; /* 0x0000000204057824 */
/* 0x000fca00078e00ff */
/*0480*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0490*/ @!P0 MUFU.RCP R5, R4 ; /* 0x0000000400058308 */
/* 0x0000620000001000 */
/*04a0*/ @!P0 BRA 0x740 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*04b0*/ FFMA R4, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004047823 */
/* 0x001fc800000000ff */
/*04c0*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x002e240000001000 */
/*04d0*/ FFMA R6, R4, R5, -1 ; /* 0xbf80000004067423 */
/* 0x001fc80000000005 */
/*04e0*/ FADD.FTZ R6, -R6, -RZ ; /* 0x800000ff06067221 */
/* 0x000fc80000010100 */
/*04f0*/ FFMA R5, R5, R6, R5 ; /* 0x0000000605057223 */
/* 0x000fc80000000005 */
/*0500*/ FFMA R5, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005057823 */
/* 0x000fe200000000ff */
/*0510*/ BRA 0x740 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*0520*/ IADD3 R6, R5, -0xfd, RZ ; /* 0xffffff0305067810 */
/* 0x000fc80007ffe0ff */
/*0530*/ ISETP.GT.U32.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fda0003f04070 */
/*0540*/ @P0 BRA 0x730 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*0550*/ LOP3.LUT R7, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04077812 */
/* 0x000fe200078ec0ff */
/*0560*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3 ; /* 0x00000003ff0b7424 */
/* 0x000fc600078e00ff */
/*0570*/ LOP3.LUT R7, R7, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000007077812 */
/* 0x000fe400078efcff */
/*0580*/ SHF.L.U32 R12, R11, R6, RZ ; /* 0x000000060b0c7219 */
/* 0x000fe400000006ff */
/*0590*/ MUFU.RCP R8, R7 ; /* 0x0000000700087308 */
/* 0x000e240000001000 */
/*05a0*/ FFMA R9, R7, R8, -1 ; /* 0xbf80000007097423 */
/* 0x001fc80000000008 */
/*05b0*/ FADD.FTZ R9, -R9, -RZ ; /* 0x800000ff09097221 */
/* 0x000fc80000010100 */
/*05c0*/ FFMA.RM R10, R8.reuse, R9.reuse, R8.reuse ; /* 0x00000009080a7223 */
/* 0x1c0fe40000004008 */
/*05d0*/ FFMA.RP R9, R8, R9, R8 ; /* 0x0000000908097223 */
/* 0x000fc60000008008 */
/*05e0*/ LOP3.LUT R8, R10.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0a087812 */
/* 0x040fe400078ec0ff */
/*05f0*/ FSETP.NEU.FTZ.AND P0, PT, R10, R9, PT ; /* 0x000000090a00720b */
/* 0x000fe40003f1d000 */
/*0600*/ LOP3.LUT R9, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008097812 */
/* 0x000fe400078efcff */
/*0610*/ SEL R8, RZ, 0xffffffff, !P0 ; /* 0xffffffffff087807 */
/* 0x000fe40004000000 */
/*0620*/ LOP3.LUT R7, R12, R9, RZ, 0xc0, !PT ; /* 0x000000090c077212 */
/* 0x000fe400078ec0ff */
/*0630*/ IADD3 R8, -R8, RZ, RZ ; /* 0x000000ff08087210 */
/* 0x000fc40007ffe1ff */
/*0640*/ SHF.R.U32.HI R7, RZ, R6.reuse, R7 ; /* 0x00000006ff077219 */
/* 0x080fe40000011607 */
/*0650*/ LOP3.LUT P1, RZ, R8, R6, R9, 0xf8, !PT ; /* 0x0000000608ff7212 */
/* 0x000fe4000782f809 */
/*0660*/ LOP3.LUT P0, RZ, R7.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000107ff7812 */
/* 0x040fe4000780c0ff */
/*0670*/ LOP3.LUT P2, RZ, R7, 0x2, RZ, 0xc0, !PT ; /* 0x0000000207ff7812 */
/* 0x000fc8000784c0ff */
/*0680*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*0690*/ LOP3.LUT P1, RZ, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04ff7812 */
/* 0x000fe4000782c0ff */
/*06a0*/ SEL R6, RZ, 0x1, !P0 ; /* 0x00000001ff067807 */
/* 0x000fca0004000000 */
/*06b0*/ IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff067224 */
/* 0x000fca00078e0a06 */
/*06c0*/ ISETP.GE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f06270 */
/*06d0*/ IADD3 R6, R5, -0xfc, RZ ; /* 0xffffff0405067810 */
/* 0x000fc80007ffe0ff */
/*06e0*/ SHF.R.U32.HI R5, RZ, R6, R9 ; /* 0x00000006ff057219 */
/* 0x000fce0000011609 */
/*06f0*/ @!P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105058810 */
/* 0x000fca0007ffe0ff */
/*0700*/ @!P1 IMAD.SHL.U32 R5, R5, 0x2, RZ ; /* 0x0000000205059824 */
/* 0x000fca00078e00ff */
/*0710*/ LOP3.LUT R5, R5, 0x80000000, R4, 0xf8, !PT ; /* 0x8000000005057812 */
/* 0x000fe200078ef804 */
/*0720*/ BRA 0x740 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0730*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x0000640000001000 */
/*0740*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x002fe200078e0005 */
/*0750*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x001fe20000000f00 */
/*0760*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0770*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff88004007950 */
/* 0x000fea0003c3ffff */
/*0780*/ BRA 0x780; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16convolution_1d_yPfiiiS_
.globl _Z16convolution_1d_yPfiiiS_
.p2align 8
.type _Z16convolution_1d_yPfiiiS_,@function
_Z16convolution_1d_yPfiiiS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x8
s_add_u32 s6, s0, 32
s_addc_u32 s7, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s2, 0xffff
s_lshr_b32 s2, s3, 31
s_mul_i32 s14, s14, s8
s_add_i32 s2, s3, s2
v_add_nc_u32_e32 v7, s14, v0
s_ashr_i32 s9, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_sub_i32 s11, s4, s9
s_mul_i32 s10, s9, s5
s_mul_i32 s11, s11, s5
v_cmp_le_i32_e32 vcc_lo, s10, v7
v_cmp_gt_i32_e64 s2, s11, v7
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s12, s2
s_cbranch_execz .LBB0_6
v_cvt_f32_i32_e32 v1, s3
s_load_b32 s13, s[6:7], 0x0
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x18
s_sub_i32 s1, 0, s10
s_mul_i32 s0, s15, s4
v_div_scale_f32 v2, null, v1, v1, 1.0
v_div_scale_f32 v5, vcc_lo, 1.0, v1, 1.0
s_cmp_ge_i32 s10, s1
s_delay_alu instid0(VALU_DEP_2)
v_rcp_f32_e32 v3, v2
s_mul_i32 s4, s0, s5
s_cselect_b32 s12, -1, 0
s_sub_i32 s0, s0, s9
s_ashr_i32 s9, s5, 31
s_mul_i32 s0, s5, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_add3_u32 v0, s14, s0, v0
s_mov_b32 s14, 0
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v2, v3, 1.0
s_waitcnt lgkmcnt(0)
s_mul_i32 s13, s13, s8
s_mov_b32 s8, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_lshl_b64 s[8:9], s[8:9], 2
v_fmac_f32_e32 v3, v4, v3
v_mul_f32_e32 v4, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v2, v4, v5
v_fmac_f32_e32 v4, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v2, v4, v5
v_div_fmas_f32 v2, v2, v3, v4
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v8, v2, v1, 1.0
s_branch .LBB0_3
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v7, s13, v7
v_add_nc_u32_e32 v0, s13, v0
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s0, s11, v7
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s10, v7
global_load_b32 v3, v[1:2], off
s_or_b32 s0, vcc_lo, s0
s_and_b32 s0, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s14, s0, s14
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, v8, v3
global_store_b32 v[1:2], v3, off
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB0_6
.LBB0_3:
v_add_nc_u32_e32 v2, s4, v7
s_and_not1_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB0_2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s0, s1
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v9, v[3:4], off
.LBB0_5:
global_load_b32 v1, v[5:6], off
v_add_co_u32 v5, vcc_lo, v5, s8
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
s_add_i32 s0, s0, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_i32 s0, s10
s_waitcnt vmcnt(0)
v_add_f32_e32 v9, v1, v9
global_store_b32 v[3:4], v9, off
s_cbranch_scc0 .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16convolution_1d_yPfiiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16convolution_1d_yPfiiiS_, .Lfunc_end0-_Z16convolution_1d_yPfiiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16convolution_1d_yPfiiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16convolution_1d_yPfiiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000eff88_00000000-6_convolution_gpu_blur_separable.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16convolution_1d_yPfiiiS_PfiiiS_
.type _Z41__device_stub__Z16convolution_1d_yPfiiiS_PfiiiS_, @function
_Z41__device_stub__Z16convolution_1d_yPfiiiS_PfiiiS_:
.LFB4057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16convolution_1d_yPfiiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4057:
.size _Z41__device_stub__Z16convolution_1d_yPfiiiS_PfiiiS_, .-_Z41__device_stub__Z16convolution_1d_yPfiiiS_PfiiiS_
.globl _Z16convolution_1d_yPfiiiS_
.type _Z16convolution_1d_yPfiiiS_, @function
_Z16convolution_1d_yPfiiiS_:
.LFB4058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16convolution_1d_yPfiiiS_PfiiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4058:
.size _Z16convolution_1d_yPfiiiS_, .-_Z16convolution_1d_yPfiiiS_
.globl _Z18blur_separable_gpuPfiiiS_
.type _Z18blur_separable_gpuPfiiiS_, @function
_Z18blur_separable_gpuPfiiiS_:
.LFB4032:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movl %esi, %ebx
movq %r8, %r12
movl $1, 12(%rsp)
leal 255(%rsi,%rsi,2), %eax
shrl $8, %eax
movl %eax, 20(%rsp)
movl %edx, 24(%rsp)
movl $256, 8(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %r12, %r8
movl $9, %ecx
movl $3, %edx
movl %ebx, %esi
movq %rbp, %rdi
call _Z41__device_stub__Z16convolution_1d_yPfiiiS_PfiiiS_
jmp .L11
.cfi_endproc
.LFE4032:
.size _Z18blur_separable_gpuPfiiiS_, .-_Z18blur_separable_gpuPfiiiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16convolution_1d_yPfiiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16convolution_1d_yPfiiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "convolution_gpu_blur_separable.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z31__device_stub__convolution_1d_yPfiiiS_ # -- Begin function _Z31__device_stub__convolution_1d_yPfiiiS_
.p2align 4, 0x90
.type _Z31__device_stub__convolution_1d_yPfiiiS_,@function
_Z31__device_stub__convolution_1d_yPfiiiS_: # @_Z31__device_stub__convolution_1d_yPfiiiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16convolution_1d_yPfiiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__convolution_1d_yPfiiiS_, .Lfunc_end0-_Z31__device_stub__convolution_1d_yPfiiiS_
.cfi_endproc
# -- End function
.globl _Z18blur_separable_gpuPfiiiS_ # -- Begin function _Z18blur_separable_gpuPfiiiS_
.p2align 4, 0x90
.type _Z18blur_separable_gpuPfiiiS_,@function
_Z18blur_separable_gpuPfiiiS_: # @_Z18blur_separable_gpuPfiiiS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %r8, %rbx
# kill: def $edx killed $edx def $rdx
movl %esi, %r14d
movq %rdi, %r15
leal (%r14,%r14,2), %edi
addl $255, %edi
shrl $8, %edi
shlq $32, %rdx
orq %rdx, %rdi
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r15, 72(%rsp)
movl %r14d, 12(%rsp)
movl $3, 8(%rsp)
movl $9, 4(%rsp)
movq %rbx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16convolution_1d_yPfiiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z18blur_separable_gpuPfiiiS_, .Lfunc_end1-_Z18blur_separable_gpuPfiiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16convolution_1d_yPfiiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16convolution_1d_yPfiiiS_,@object # @_Z16convolution_1d_yPfiiiS_
.section .rodata,"a",@progbits
.globl _Z16convolution_1d_yPfiiiS_
.p2align 3, 0x0
_Z16convolution_1d_yPfiiiS_:
.quad _Z31__device_stub__convolution_1d_yPfiiiS_
.size _Z16convolution_1d_yPfiiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16convolution_1d_yPfiiiS_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__convolution_1d_yPfiiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16convolution_1d_yPfiiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <fcntl.h>
#include "string.h"
#include <math.h>
#define DEFAULT_FILENAME "small-zibra-unsplash.ppm"
#define MAX_VALUE 256 //max value of the pic luminance
#define NUM_BINS 256 //num of bins equals to the max value
__constant__ double PARAMS[4];
void write_ppm( char const *filename, int xsize, int ysize, int maxval, unsigned int *pic);
unsigned int *read_ppm( char *filename, int * xsize, int * ysize, int *maxval );
void write_CSV(char const *filename,int width, int height, unsigned int *input);
void matrixRotation(unsigned int *input, unsigned int *output, int width, int height, double angle);
void computerGoldHisto(unsigned int* input, unsigned int* histo, int width, int height);
void getNewXY(int inputX, int inputY, int width, int height,double angle, int *outputX, int *outputY);
__global__ void rotation_kernel_naive(unsigned int *input,unsigned int *output,int width, int height,double angle);
__global__ void rotation_kernel_2(unsigned int *input,unsigned int *output,int width, int height,double angle);
__global__ void rotation_kernel_3(unsigned int *input,unsigned int *output,int width,int height);
__global__ void histo_kernel_naive(unsigned int *input,unsigned int *histo,int width, int height);
__global__ void histo_kernel_2(unsigned int *input,unsigned int *histo,int width, int height);
int main( int argc, char **argv )
{
double ang ;
char *filename;
filename = strdup( DEFAULT_FILENAME);
ang = 45.0;
if (argc > 1) {
if (argc == 3) { //angle and filename
ang = atoi( argv[1] );
filename = strdup( argv[2]);
}
if (argc == 2) { // angle
ang = atoi( argv[1] );
}
}
fprintf(stderr, "file %s , rotation angle: %f\n", filename, ang);
//initialization paramters
int xsize, ysize,maxval;
unsigned int *h_histoCPU;
unsigned int *h_Input;
unsigned int *h_rotated;
//read input from image
unsigned int *pic = read_ppm( filename, &xsize, &ysize, &maxval );
int diaLen = (unsigned int) (sqrt(xsize * xsize + ysize* ysize) + 3);//paddle extra 3 for safer non-cropped rotation
printf("width:%d, height:%d,maxVal: %d, diagonal size: %d \n",xsize,ysize,maxval,diaLen );
//decide memory size
size_t histo_size = MAX_VALUE * diaLen * 3 * sizeof(int);
size_t rotate_size = diaLen * diaLen * 3 * sizeof(int);
//allocate memory
h_histoCPU = (unsigned int*)malloc(histo_size);
h_rotated= (unsigned int*)malloc(rotate_size);
h_Input = (unsigned int*)malloc(rotate_size);
if (!h_Input || !h_histoCPU || !h_rotated) {
fprintf(stderr, " unable to malloc \n");
exit(-1); // fail
}
//decide rotate angle， rotation is done swirlly along the image center.
double angle = - ang / 360 * M_PI * 2;
//paddle data for h_Input, make it squre with side length as the input diagonal length
int deltaX = diaLen - xsize ;
int deltaY = diaLen - ysize ;
for(int i=0;i<diaLen;i++){
for(int j = 0; j< diaLen;j++){
if(i>=deltaY / 2 && i< (ysize + deltaY/2) && j >= deltaX/2 && j < (xsize + deltaX/2)){
h_Input[i*diaLen+j]=pic[(i-deltaY/2)*xsize + (j-deltaX/2)];
}else{
h_Input[i*diaLen+j] = 0;
}
}
}
//calculate new coordinate
int outputX, outputY;
double realAngle = -angle;
int originX = 0;
int originY = 200;
getNewXY(originX,originY, xsize, ysize, realAngle, &outputX, &outputY);
printf("(%d, %d) rotated to newX: %d, newY: %d \n", originX,originY,outputX, outputY);
//output the paddledInput
write_ppm( "paddledInput.ppm", diaLen, diaLen, 255, h_Input);
//timer for cpu rotation------------------------
cudaEvent_t start, stop;
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
//run rotation on cpu
matrixRotation( h_Input, h_rotated, diaLen, diaLen, angle);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time,start,stop);
printf("cpu rotation time: %f milliseconds\n",time);
cudaEventDestroy(start);
cudaEventDestroy(stop);
//output rotated image
write_ppm( "rotated_gold.ppm", diaLen, diaLen, 255, h_rotated);
write_CSV("rotated_gold.csv",diaLen,diaLen, h_rotated);
//write_CSV("picture.csv",xsize,ysize, pic);
//initialization h_BinsCPU
for(int i = 0;i<NUM_BINS;i++){
for(int j = 0;j<MAX_VALUE;j++){
h_histoCPU[i*MAX_VALUE+j] = 0;
}
}
//timer for CPU histogram
float time2;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
//run histo on CPU
computerGoldHisto(h_rotated,h_histoCPU,diaLen,diaLen);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time2,start,stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("cpu histo time: %f milliseconds\n",time2);
//output histo result to CSV file
write_CSV("histoBinCPU.csv",diaLen,MAX_VALUE, h_histoCPU);
//cudaMalloc for rotation kernel
unsigned int *h_histoGPU;
unsigned int *h_rotatedGPU;
unsigned int *h_rotatedGPU2;
unsigned int *h_rotatedGPU3;
unsigned int *d_Input;
unsigned int *d_rotated;
unsigned int *d_rotated_naive;
unsigned int *d_histo;
//memory allocate in the host
h_rotatedGPU = (unsigned int*)malloc(rotate_size);
h_rotatedGPU2 = (unsigned int*)malloc(rotate_size);
h_rotatedGPU3 = (unsigned int*)malloc(rotate_size);
h_histoGPU = (unsigned int*)malloc(histo_size);
if (!h_rotatedGPU ||!h_histoGPU||!h_rotatedGPU2||!h_rotatedGPU3) {
fprintf(stderr, " unable to malloc \n");
exit(-1); // fail
}
cudaMalloc((void**)&d_Input,rotate_size);
cudaMalloc((void**)&d_rotated,rotate_size);
cudaMalloc((void**)&d_rotated_naive,rotate_size);
//cudaMemcpy
cudaMemcpy(d_Input,h_Input,rotate_size,cudaMemcpyHostToDevice);
//kernel dimension
int blockSize = 8;
dim3 blockDim(blockSize,blockSize,1);
int gridSize = (diaLen + blockSize -1)/blockSize;
dim3 gridDim(gridSize,gridSize,1);
float time3;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
//launch kernel 100 times and take average time
for(int i = 0;i<100;i++){
rotation_kernel_naive<<<gridDim,blockDim>>>(d_Input,d_rotated_naive,diaLen,diaLen,angle);
}
cudaEventRecord(stop,0);
cudaMemcpy(h_rotatedGPU,d_rotated_naive,rotate_size,cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time3,start,stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("GPU rotation_kernel_naive time: %f milliseconds\n",time3 / 100);
//output GPU rotate result
write_ppm( "rotated_GPU_naive.ppm", diaLen, diaLen, 255, h_rotatedGPU);
//GPU rotation with optimization, using registers to store pre-calculated values
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
//launch kernel 100 times and take average time
for(int i = 0;i<100;i++){
rotation_kernel_2<<<gridDim,blockDim>>>(d_Input,d_rotated,diaLen,diaLen,angle);
}
cudaEventRecord(stop,0);
cudaMemcpy(h_rotatedGPU2,d_rotated,rotate_size,cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float time3_2;
cudaEventElapsedTime(&time3_2,start,stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("GPU rotation_kernel_2 time: %f milliseconds\n",time3_2 / 100);
//output GPU rotate result
write_ppm( "rotated_GPU2.ppm", diaLen, diaLen, 255, h_rotatedGPU2);
//rotation kernel_3 using constant memory---------------------------------
double *P;
P = (double*) malloc(4 * sizeof(double));
P[0] = (double)diaLen / 2; //xCenter
P[1] = (double)diaLen / 2; //yCenter
P[2] = sin(angle);
P[3] = cos(angle);
//load data to constant memory
cudaMemcpyToSymbol(PARAMS, P, 4 * sizeof(double));
//timer
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
//launch kernel 100 times and take average time
for(int i = 0;i<100;i++){
rotation_kernel_3<<<gridDim,blockDim>>>(d_Input,d_rotated,diaLen,diaLen);
}
cudaEventRecord(stop,0);
cudaMemcpy(h_rotatedGPU3,d_rotated,rotate_size,cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float time3_3;
cudaEventElapsedTime(&time3_3,start,stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("GPU rotation kernel_3 tiem: %f milliseconds\n",time3_3 / 100);
//output GPU rotate result
write_ppm( "rotated_GPU3.ppm", diaLen, diaLen, 255, h_rotatedGPU3);
//-------end of rotation kernel-----------------------------------------------
//cudaFree part 1
cudaFree(d_Input);
cudaFree(d_rotated_naive);
//------GPU histo start----------------------------------------
// //cudaMalloc for histoGPU
cudaMalloc((void**)&d_histo,histo_size);
//------naive histo kernel-----------------------------------------
float time4;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
//launch kernel 100 times and take average time
int blockSize2 = 32;
int gridSize2 = ceil((float)diaLen/blockSize2);
dim3 blockDim2 (blockSize2,blockSize2,1);
dim3 gridDim2 (gridSize2,gridSize2,1);
histo_kernel_naive<<<gridDim2,blockDim2>>>(d_rotated,d_histo,diaLen,diaLen);
cudaEventRecord(stop,0);
cudaMemcpy(h_histoGPU,d_histo,histo_size,cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time4,start,stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("GPU histo_naive time: %f milliseconds\n",time4 );
// //output histo result to CSV file
write_CSV("histoBinGPU_kernel_naive.csv",diaLen,MAX_VALUE, h_histoGPU);
//----------end---------------------------------------------------------------
//------histo kernel 2, one thread work with one input----------------------------
unsigned int *h_histoGPU2;
h_histoGPU2 = (unsigned int*)malloc(histo_size);
if (!h_histoGPU2) {
fprintf(stderr, " unable to malloc \n");
exit(-1); // fail
}
unsigned int *d_histo2;
cudaMalloc((void**)&d_histo2,histo_size);
float time5;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
//launch kernel 100 times and take average time
for(int i = 0;i<100;i++){
histo_kernel_2<<<diaLen,256>>>(d_rotated,d_histo2,diaLen,diaLen);
}
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaMemcpy(h_histoGPU2,d_histo2,histo_size,cudaMemcpyDeviceToHost);
cudaEventElapsedTime(&time5,start,stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("GPU histo_kernel_2 time: %f milliseconds\n",time5 / 100);
// //output histo result to CSV file
write_CSV("histoBinGPU_kernel_2.csv",diaLen,MAX_VALUE, h_histoGPU2);
//----------end---------------------------------------------------------------
//cudaFREE part 2
cudaFree(d_rotated);
cudaFree(d_histo);
cudaFree(d_histo2);
//Free host memory
free(h_Input);
free(h_rotated);
free(h_rotatedGPU);
free(h_rotatedGPU2);
free(h_rotatedGPU3);
free(h_histoCPU);
free(h_histoGPU);
free(h_histoGPU2);
fprintf(stderr, "done\n");
}
//--------rotation kernel naive----------------------------------------
__global__ void rotation_kernel_naive(unsigned int *input,unsigned int *output,int width, int height,double angle){
//TO DO
double xCenter = (double)width / 2;
double yCenter = (double)height / 2;
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int index = y * width + x;
int orgX = 0;
int orgY = 0;
//boundary check
if(x >=0 && x < width && y >=0 && y < height){
orgX = (int)(cos(angle) * ((double)x - xCenter)- sin(angle) * ((double)y - yCenter) + xCenter);
orgY = (int)(sin(angle) * ((double)x - xCenter) + cos(angle) * ((double)y - yCenter) + yCenter);
}
if(orgX>=0 && orgX < width && orgY>=0 && orgY<height){
output[index] = input[ orgY * width + orgX];
}
}
//--------rotation kernel 2----------------------------------------
__global__ void rotation_kernel_2(unsigned int *input,unsigned int *output,int width, int height,double angle){
//TO DO
double xCenter = (double)width / 2; // x center of image
double yCenter = (double)height / 2; // y center of image
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int index = y * width + x;
double sinA = sin(angle);
double cosA = cos(angle);
double shiftX = (double)x - xCenter;
double shiftY = (double)y - yCenter;
int orgX = 0;
int orgY = 0;
//boundary check
if(x >=0 && x < width && y >=0 && y < height){
orgX = (int)(cosA * shiftX - sinA * shiftY + xCenter);
orgY = (int)(sinA * shiftX + cosA * shiftY + yCenter);
}
if(orgX>=0 && orgX < width && orgY>=0 && orgY<height){
output[index] = input[ orgY * width + orgX];
}
}
//--------rotation kernel 3 using constant memory----------------------------------------
__global__ void rotation_kernel_3(unsigned int *input,unsigned int *output,int width, int height){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int index = y * width + x;
double shiftX = (double)x - PARAMS[0];
double shiftY = (double)y - PARAMS[1];
int orgX = 0;
int orgY = 0;
//boundary check
if(x >=0 && x < width && y >=0 && y < height){
orgX = (int)(PARAMS[3] * shiftX - PARAMS[2] * shiftY + PARAMS[0]);
orgY = (int)(PARAMS[2] * shiftX + PARAMS[3] * shiftY + PARAMS[1]);
}
if(orgX>=0 && orgX < width && orgY>=0 && orgY<height){
output[index] = input[ orgY * width + orgX];
}
}
//----------cpu for matrix rotation--------------------------
//rotate as a swirl from , from the center
void matrixRotation(unsigned int *input, unsigned int *output, int width, int height, double angle){
double xCenter = (double)width / 2;
double yCenter = (double)height / 2;
//for non-crop rotation put both the height and width of the output the diagonal length of the origin input
for(int y = 0;y<height;y++){
for(int x = 0;x<width;x++){
int orgX = (int)(cos(angle) * ((double)x -xCenter) - sin(angle) * ((double)y - yCenter) + xCenter ) ;
int orgY = (int)(sin(angle) * ((double)x -xCenter) + cos(angle) * ((double)y - yCenter) + yCenter );
if(orgX>=0 && orgX < width && orgY>=0 && orgY < height){
output[y*width+x] = input[orgY * width +orgX];
}
}
}
}
//----------histo kernel naive: using global memory--------------------------------------
__global__ void histo_kernel_naive(unsigned int *input,unsigned int *histo,int width, int height){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if(x >=0 && x < width && y >=0 && y < height){
atomicAdd(&histo[input[y*width+x]*width+x],1);
}
}
//histo_kernel_2<<<diaLen,256>>>(d_rotated,d_histo2,diaLen,diaLen);
//----------histo kernel 2: with shared memory,each threads deal with one input
__global__ void histo_kernel_2(unsigned int *input,unsigned int *histo,int width, int height){
__shared__ unsigned int H[NUM_BINS];// one column of the output bin
int tx = threadIdx.x;
int col = blockIdx.x;//col number of input
int bd = blockDim.x;
H[tx] = 0;
__syncthreads();
for(int t =0;t<(height+bd-1)/bd;t++){ //when height is bigger than blockDim
int row = t*bd+tx;
if(row<height){
int value = input[row*width+col];
atomicAdd(&H[value],1);
}
}
__syncthreads();
histo[tx*width+col] = H[tx];
}
//histo_kernel_3<<<diaLen,256>>>,
//----------histo kernel 3: with shared memory for input, each thread collecting one bin
__global__ void histo_kernel_3(unsigned int *input,unsigned int *histo,int width, int height){
__shared__ unsigned int IN[NUM_BINS]; //use to storing input
int tx = threadIdx.x;
int col = blockIdx.x;//col number of input
int h = 0;
for(int t =0;t<(height+NUM_BINS-1)/NUM_BINS;t++){ //when height is bigger than NUM_BINS
int row = t*NUM_BINS+tx;
if(row<height){
IN[tx] = input[row*width+col];
}else{
IN[tx] = 300; // padding nonsense value to avoid addition
}
__syncthreads();
for(int i = 0;i<NUM_BINS;i++){//each thread loop through the input
int value = IN[i];
if(tx == value){
h++;
}
}
}
histo[tx*width+col] = h;
}
//----------cpu for histo along y direction-------------------
void computerGoldHisto(unsigned int* input, unsigned int* histo, int width, int height){
for(int i = 0; i<height;i++){
for(int j = 0;j<width;j++){
int data = input[i*width+j];
histo[data*width+j]++;
}
}
}
//-----------read image to array-----------------------------------------------------------------
unsigned int *read_ppm( char *filename, int * xsize, int * ysize, int *maxval ){
if ( !filename || filename[0] == '\0') {
fprintf(stderr, "read_ppm but no file name\n");
return NULL; // fail
}
FILE *fp;
fprintf(stderr, "read_ppm( %s )\n", filename);
fp = fopen( filename, "rb");
if (!fp)
{
fprintf(stderr, "read_ppm() ERROR file '%s' cannot be opened for reading\n", filename);
return NULL; // fail
}
char chars[1024];
//int num = read(fd, chars, 1000);
int num = fread(chars, sizeof(char), 1000, fp);
if (chars[0] != 'P' || chars[1] != '6')
{
fprintf(stderr, "Texture::Texture() ERROR file '%s' does not start with \"P6\" I am expecting a binary PPM file\n", filename);
return NULL;
}
unsigned int width, height, maxvalue;
char *ptr = chars+3; // P 6 newline
if (*ptr == '#') // comment line!
{
ptr = 1 + strstr(ptr, "\n");
}
num = sscanf(ptr, "%d\n%d\n%d", &width, &height, &maxvalue);
fprintf(stderr, "read %d things width %d height %d maxval %d\n", num, width, height, maxvalue);
*xsize = width;
*ysize = height;
*maxval = maxvalue;
unsigned int *pic = (unsigned int *)malloc( width * height * sizeof(unsigned int));
if (!pic) {
fprintf(stderr, "read_ppm() unable to allocate %d x %d unsigned ints for the picture\n", width, height);
return NULL; // fail but return
}
// allocate buffer to read the rest of the file into
int bufsize = 3 * width * height * sizeof(unsigned char);
if ((*maxval) > 255) bufsize *= 2;
unsigned char *buf = (unsigned char *)malloc( bufsize );
if (!buf) {
fprintf(stderr, "read_ppm() unable to allocate %d bytes of read buffer\n", bufsize);
return NULL; // fail but return
}
// really read
char duh[80];
char *line = chars;
// find the start of the pixel data.
sprintf(duh, "%d\0", *xsize);
line = strstr(line, duh);
//fprintf(stderr, "%s found at offset %d\n", duh, line-chars);
line += strlen(duh) + 1;
sprintf(duh, "%d\0", *ysize);
line = strstr(line, duh);
//fprintf(stderr, "%s found at offset %d\n", duh, line-chars);
line += strlen(duh) + 1;
sprintf(duh, "%d\0", *maxval);
line = strstr(line, duh);
fprintf(stderr, "%s found at offset %d\n", duh, line - chars);
line += strlen(duh) + 1;
long offset = line - chars;
//lseek(fd, offset, SEEK_SET); // move to the correct offset
fseek(fp, offset, SEEK_SET); // move to the correct offset
//long numread = read(fd, buf, bufsize);
long numread = fread(buf, sizeof(char), bufsize, fp);
fprintf(stderr, "Texture %s read %ld of %ld bytes\n", filename, numread, bufsize);
fclose(fp);
int pixels = (*xsize) * (*ysize);
for (int i=0; i<pixels; i++)
pic[i] = (int) buf[3*i]; // red channel
return pic; // success
}
//--------------wiret array to a image-------------------------------------------------------------------
void write_ppm( char const *filename, int xsize, int ysize, int maxval,unsigned int *pic)
{
FILE *fp;
// int x,y;
fp = fopen(filename, "wb");
if (!fp)
{
fprintf(stderr, "FAILED TO OPEN FILE '%s' for writing\n");
exit(-1);
}
fprintf(fp, "P6\n");
fprintf(fp,"%d %d\n%d\n", xsize, ysize, maxval);
int numpix = xsize * ysize;
for (int i=0; i<numpix; i++) {
unsigned char uc = (unsigned char) pic[i];
fprintf(fp, "%c%c%c", uc, uc, uc);
}
fclose(fp);
}
//write histoBin result to excel diaLen, MAX_VALUE
void write_CSV(char const *filename,int width, int height, unsigned int *input){
FILE *fp;
fp = fopen(filename, "w+");
if (!fp)
{
fprintf(stderr, "FAILED TO OPEN FILE '%s' for writing\n");
exit(-1);
}
for(int i = 0;i< height;i++){
for(int j = 0;j<width;j++){
fprintf(fp,"%d,",input[i*width+j]);
}
fprintf(fp,"\n");
}
fclose(fp);
}
// calculate newX newY after padding and rotation
void getNewXY(int inputX, int inputY, int width, int height,double angle, int *outputX, int *outputY){
double diaLen = (int)(sqrt(width * width + height * height) + 3);
double deltaX = diaLen - width ;
double deltaY = diaLen - height;
// printf("deltaX: %f, deltaY: %f\n",deltaX,deltaY);
double x = (double)inputX - deltaX / 2;
double y = (double)inputY - deltaY/ 2;
// printf("paddled x and y are: %f, %f\n", x, y);
double xCenter = -diaLen / 2;
double yCenter = -diaLen / 2;
// printf("deltaX: %f, deltaY: %f\n",xCenter,yCenter);
*outputX = -1 * (int)(cos(angle) * (x -xCenter) - sin(angle) * (y - yCenter) + xCenter ) ;
*outputY = -1 * (int)(sin(angle) * (x -xCenter) + cos(angle) * (y - yCenter) + yCenter );
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <fcntl.h>
#include "string.h"
#include <math.h>
#define DEFAULT_FILENAME "small-zibra-unsplash.ppm"
#define MAX_VALUE 256 //max value of the pic luminance
#define NUM_BINS 256 //num of bins equals to the max value
__constant__ double PARAMS[4];
void write_ppm( char const *filename, int xsize, int ysize, int maxval, unsigned int *pic);
unsigned int *read_ppm( char *filename, int * xsize, int * ysize, int *maxval );
void write_CSV(char const *filename,int width, int height, unsigned int *input);
void matrixRotation(unsigned int *input, unsigned int *output, int width, int height, double angle);
void computerGoldHisto(unsigned int* input, unsigned int* histo, int width, int height);
void getNewXY(int inputX, int inputY, int width, int height,double angle, int *outputX, int *outputY);
__global__ void rotation_kernel_naive(unsigned int *input,unsigned int *output,int width, int height,double angle);
__global__ void rotation_kernel_2(unsigned int *input,unsigned int *output,int width, int height,double angle);
__global__ void rotation_kernel_3(unsigned int *input,unsigned int *output,int width,int height);
__global__ void histo_kernel_naive(unsigned int *input,unsigned int *histo,int width, int height);
__global__ void histo_kernel_2(unsigned int *input,unsigned int *histo,int width, int height);
int main( int argc, char **argv )
{
double ang ;
char *filename;
filename = strdup( DEFAULT_FILENAME);
ang = 45.0;
if (argc > 1) {
if (argc == 3) { //angle and filename
ang = atoi( argv[1] );
filename = strdup( argv[2]);
}
if (argc == 2) { // angle
ang = atoi( argv[1] );
}
}
fprintf(stderr, "file %s , rotation angle: %f\n", filename, ang);
//initialization paramters
int xsize, ysize,maxval;
unsigned int *h_histoCPU;
unsigned int *h_Input;
unsigned int *h_rotated;
//read input from image
unsigned int *pic = read_ppm( filename, &xsize, &ysize, &maxval );
int diaLen = (unsigned int) (sqrt(xsize * xsize + ysize* ysize) + 3);//paddle extra 3 for safer non-cropped rotation
printf("width:%d, height:%d,maxVal: %d, diagonal size: %d \n",xsize,ysize,maxval,diaLen );
//decide memory size
size_t histo_size = MAX_VALUE * diaLen * 3 * sizeof(int);
size_t rotate_size = diaLen * diaLen * 3 * sizeof(int);
//allocate memory
h_histoCPU = (unsigned int*)malloc(histo_size);
h_rotated= (unsigned int*)malloc(rotate_size);
h_Input = (unsigned int*)malloc(rotate_size);
if (!h_Input || !h_histoCPU || !h_rotated) {
fprintf(stderr, " unable to malloc \n");
exit(-1); // fail
}
//decide rotate angle， rotation is done swirlly along the image center.
double angle = - ang / 360 * M_PI * 2;
//paddle data for h_Input, make it squre with side length as the input diagonal length
int deltaX = diaLen - xsize ;
int deltaY = diaLen - ysize ;
for(int i=0;i<diaLen;i++){
for(int j = 0; j< diaLen;j++){
if(i>=deltaY / 2 && i< (ysize + deltaY/2) && j >= deltaX/2 && j < (xsize + deltaX/2)){
h_Input[i*diaLen+j]=pic[(i-deltaY/2)*xsize + (j-deltaX/2)];
}else{
h_Input[i*diaLen+j] = 0;
}
}
}
//calculate new coordinate
int outputX, outputY;
double realAngle = -angle;
int originX = 0;
int originY = 200;
getNewXY(originX,originY, xsize, ysize, realAngle, &outputX, &outputY);
printf("(%d, %d) rotated to newX: %d, newY: %d \n", originX,originY,outputX, outputY);
//output the paddledInput
write_ppm( "paddledInput.ppm", diaLen, diaLen, 255, h_Input);
//timer for cpu rotation------------------------
hipEvent_t start, stop;
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
//run rotation on cpu
matrixRotation( h_Input, h_rotated, diaLen, diaLen, angle);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time,start,stop);
printf("cpu rotation time: %f milliseconds\n",time);
hipEventDestroy(start);
hipEventDestroy(stop);
//output rotated image
write_ppm( "rotated_gold.ppm", diaLen, diaLen, 255, h_rotated);
write_CSV("rotated_gold.csv",diaLen,diaLen, h_rotated);
//write_CSV("picture.csv",xsize,ysize, pic);
//initialization h_BinsCPU
for(int i = 0;i<NUM_BINS;i++){
for(int j = 0;j<MAX_VALUE;j++){
h_histoCPU[i*MAX_VALUE+j] = 0;
}
}
//timer for CPU histogram
float time2;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
//run histo on CPU
computerGoldHisto(h_rotated,h_histoCPU,diaLen,diaLen);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time2,start,stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("cpu histo time: %f milliseconds\n",time2);
//output histo result to CSV file
write_CSV("histoBinCPU.csv",diaLen,MAX_VALUE, h_histoCPU);
//cudaMalloc for rotation kernel
unsigned int *h_histoGPU;
unsigned int *h_rotatedGPU;
unsigned int *h_rotatedGPU2;
unsigned int *h_rotatedGPU3;
unsigned int *d_Input;
unsigned int *d_rotated;
unsigned int *d_rotated_naive;
unsigned int *d_histo;
//memory allocate in the host
h_rotatedGPU = (unsigned int*)malloc(rotate_size);
h_rotatedGPU2 = (unsigned int*)malloc(rotate_size);
h_rotatedGPU3 = (unsigned int*)malloc(rotate_size);
h_histoGPU = (unsigned int*)malloc(histo_size);
if (!h_rotatedGPU ||!h_histoGPU||!h_rotatedGPU2||!h_rotatedGPU3) {
fprintf(stderr, " unable to malloc \n");
exit(-1); // fail
}
hipMalloc((void**)&d_Input,rotate_size);
hipMalloc((void**)&d_rotated,rotate_size);
hipMalloc((void**)&d_rotated_naive,rotate_size);
//cudaMemcpy
hipMemcpy(d_Input,h_Input,rotate_size,hipMemcpyHostToDevice);
//kernel dimension
int blockSize = 8;
dim3 blockDim(blockSize,blockSize,1);
int gridSize = (diaLen + blockSize -1)/blockSize;
dim3 gridDim(gridSize,gridSize,1);
float time3;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
//launch kernel 100 times and take average time
for(int i = 0;i<100;i++){
rotation_kernel_naive<<<gridDim,blockDim>>>(d_Input,d_rotated_naive,diaLen,diaLen,angle);
}
hipEventRecord(stop,0);
hipMemcpy(h_rotatedGPU,d_rotated_naive,rotate_size,hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
hipEventElapsedTime(&time3,start,stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("GPU rotation_kernel_naive time: %f milliseconds\n",time3 / 100);
//output GPU rotate result
write_ppm( "rotated_GPU_naive.ppm", diaLen, diaLen, 255, h_rotatedGPU);
//GPU rotation with optimization, using registers to store pre-calculated values
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
//launch kernel 100 times and take average time
for(int i = 0;i<100;i++){
rotation_kernel_2<<<gridDim,blockDim>>>(d_Input,d_rotated,diaLen,diaLen,angle);
}
hipEventRecord(stop,0);
hipMemcpy(h_rotatedGPU2,d_rotated,rotate_size,hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float time3_2;
hipEventElapsedTime(&time3_2,start,stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("GPU rotation_kernel_2 time: %f milliseconds\n",time3_2 / 100);
//output GPU rotate result
write_ppm( "rotated_GPU2.ppm", diaLen, diaLen, 255, h_rotatedGPU2);
//rotation kernel_3 using constant memory---------------------------------
double *P;
P = (double*) malloc(4 * sizeof(double));
P[0] = (double)diaLen / 2; //xCenter
P[1] = (double)diaLen / 2; //yCenter
P[2] = sin(angle);
P[3] = cos(angle);
//load data to constant memory
hipMemcpyToSymbol(HIP_SYMBOL(PARAMS), P, 4 * sizeof(double));
//timer
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
//launch kernel 100 times and take average time
for(int i = 0;i<100;i++){
rotation_kernel_3<<<gridDim,blockDim>>>(d_Input,d_rotated,diaLen,diaLen);
}
hipEventRecord(stop,0);
hipMemcpy(h_rotatedGPU3,d_rotated,rotate_size,hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float time3_3;
hipEventElapsedTime(&time3_3,start,stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("GPU rotation kernel_3 tiem: %f milliseconds\n",time3_3 / 100);
//output GPU rotate result
write_ppm( "rotated_GPU3.ppm", diaLen, diaLen, 255, h_rotatedGPU3);
//-------end of rotation kernel-----------------------------------------------
//cudaFree part 1
hipFree(d_Input);
hipFree(d_rotated_naive);
//------GPU histo start----------------------------------------
// //cudaMalloc for histoGPU
hipMalloc((void**)&d_histo,histo_size);
//------naive histo kernel-----------------------------------------
float time4;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
//launch kernel 100 times and take average time
int blockSize2 = 32;
int gridSize2 = ceil((float)diaLen/blockSize2);
dim3 blockDim2 (blockSize2,blockSize2,1);
dim3 gridDim2 (gridSize2,gridSize2,1);
histo_kernel_naive<<<gridDim2,blockDim2>>>(d_rotated,d_histo,diaLen,diaLen);
hipEventRecord(stop,0);
hipMemcpy(h_histoGPU,d_histo,histo_size,hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
hipEventElapsedTime(&time4,start,stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("GPU histo_naive time: %f milliseconds\n",time4 );
// //output histo result to CSV file
write_CSV("histoBinGPU_kernel_naive.csv",diaLen,MAX_VALUE, h_histoGPU);
//----------end---------------------------------------------------------------
//------histo kernel 2, one thread work with one input----------------------------
unsigned int *h_histoGPU2;
h_histoGPU2 = (unsigned int*)malloc(histo_size);
if (!h_histoGPU2) {
fprintf(stderr, " unable to malloc \n");
exit(-1); // fail
}
unsigned int *d_histo2;
hipMalloc((void**)&d_histo2,histo_size);
float time5;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
//launch kernel 100 times and take average time
for(int i = 0;i<100;i++){
histo_kernel_2<<<diaLen,256>>>(d_rotated,d_histo2,diaLen,diaLen);
}
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipMemcpy(h_histoGPU2,d_histo2,histo_size,hipMemcpyDeviceToHost);
hipEventElapsedTime(&time5,start,stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("GPU histo_kernel_2 time: %f milliseconds\n",time5 / 100);
// //output histo result to CSV file
write_CSV("histoBinGPU_kernel_2.csv",diaLen,MAX_VALUE, h_histoGPU2);
//----------end---------------------------------------------------------------
//cudaFREE part 2
hipFree(d_rotated);
hipFree(d_histo);
hipFree(d_histo2);
//Free host memory
free(h_Input);
free(h_rotated);
free(h_rotatedGPU);
free(h_rotatedGPU2);
free(h_rotatedGPU3);
free(h_histoCPU);
free(h_histoGPU);
free(h_histoGPU2);
fprintf(stderr, "done\n");
}
//--------rotation kernel naive----------------------------------------
__global__ void rotation_kernel_naive(unsigned int *input,unsigned int *output,int width, int height,double angle){
//TO DO
double xCenter = (double)width / 2;
double yCenter = (double)height / 2;
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int index = y * width + x;
int orgX = 0;
int orgY = 0;
//boundary check
if(x >=0 && x < width && y >=0 && y < height){
orgX = (int)(cos(angle) * ((double)x - xCenter)- sin(angle) * ((double)y - yCenter) + xCenter);
orgY = (int)(sin(angle) * ((double)x - xCenter) + cos(angle) * ((double)y - yCenter) + yCenter);
}
if(orgX>=0 && orgX < width && orgY>=0 && orgY<height){
output[index] = input[ orgY * width + orgX];
}
}
//--------rotation kernel 2----------------------------------------
__global__ void rotation_kernel_2(unsigned int *input,unsigned int *output,int width, int height,double angle){
//TO DO
double xCenter = (double)width / 2; // x center of image
double yCenter = (double)height / 2; // y center of image
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int index = y * width + x;
double sinA = sin(angle);
double cosA = cos(angle);
double shiftX = (double)x - xCenter;
double shiftY = (double)y - yCenter;
int orgX = 0;
int orgY = 0;
//boundary check
if(x >=0 && x < width && y >=0 && y < height){
orgX = (int)(cosA * shiftX - sinA * shiftY + xCenter);
orgY = (int)(sinA * shiftX + cosA * shiftY + yCenter);
}
if(orgX>=0 && orgX < width && orgY>=0 && orgY<height){
output[index] = input[ orgY * width + orgX];
}
}
//--------rotation kernel 3 using constant memory----------------------------------------
__global__ void rotation_kernel_3(unsigned int *input,unsigned int *output,int width, int height){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int index = y * width + x;
double shiftX = (double)x - PARAMS[0];
double shiftY = (double)y - PARAMS[1];
int orgX = 0;
int orgY = 0;
//boundary check
if(x >=0 && x < width && y >=0 && y < height){
orgX = (int)(PARAMS[3] * shiftX - PARAMS[2] * shiftY + PARAMS[0]);
orgY = (int)(PARAMS[2] * shiftX + PARAMS[3] * shiftY + PARAMS[1]);
}
if(orgX>=0 && orgX < width && orgY>=0 && orgY<height){
output[index] = input[ orgY * width + orgX];
}
}
//----------cpu for matrix rotation--------------------------
//rotate as a swirl from , from the center
void matrixRotation(unsigned int *input, unsigned int *output, int width, int height, double angle){
double xCenter = (double)width / 2;
double yCenter = (double)height / 2;
//for non-crop rotation put both the height and width of the output the diagonal length of the origin input
for(int y = 0;y<height;y++){
for(int x = 0;x<width;x++){
int orgX = (int)(cos(angle) * ((double)x -xCenter) - sin(angle) * ((double)y - yCenter) + xCenter ) ;
int orgY = (int)(sin(angle) * ((double)x -xCenter) + cos(angle) * ((double)y - yCenter) + yCenter );
if(orgX>=0 && orgX < width && orgY>=0 && orgY < height){
output[y*width+x] = input[orgY * width +orgX];
}
}
}
}
//----------histo kernel naive: using global memory--------------------------------------
__global__ void histo_kernel_naive(unsigned int *input,unsigned int *histo,int width, int height){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if(x >=0 && x < width && y >=0 && y < height){
atomicAdd(&histo[input[y*width+x]*width+x],1);
}
}
//histo_kernel_2<<<diaLen,256>>>(d_rotated,d_histo2,diaLen,diaLen);
//----------histo kernel 2: with shared memory,each threads deal with one input
__global__ void histo_kernel_2(unsigned int *input,unsigned int *histo,int width, int height){
__shared__ unsigned int H[NUM_BINS];// one column of the output bin
int tx = threadIdx.x;
int col = blockIdx.x;//col number of input
int bd = blockDim.x;
H[tx] = 0;
__syncthreads();
for(int t =0;t<(height+bd-1)/bd;t++){ //when height is bigger than blockDim
int row = t*bd+tx;
if(row<height){
int value = input[row*width+col];
atomicAdd(&H[value],1);
}
}
__syncthreads();
histo[tx*width+col] = H[tx];
}
//histo_kernel_3<<<diaLen,256>>>,
//----------histo kernel 3: with shared memory for input, each thread collecting one bin
__global__ void histo_kernel_3(unsigned int *input,unsigned int *histo,int width, int height){
__shared__ unsigned int IN[NUM_BINS]; //use to storing input
int tx = threadIdx.x;
int col = blockIdx.x;//col number of input
int h = 0;
for(int t =0;t<(height+NUM_BINS-1)/NUM_BINS;t++){ //when height is bigger than NUM_BINS
int row = t*NUM_BINS+tx;
if(row<height){
IN[tx] = input[row*width+col];
}else{
IN[tx] = 300; // padding nonsense value to avoid addition
}
__syncthreads();
for(int i = 0;i<NUM_BINS;i++){//each thread loop through the input
int value = IN[i];
if(tx == value){
h++;
}
}
}
histo[tx*width+col] = h;
}
//----------cpu for histo along y direction-------------------
void computerGoldHisto(unsigned int* input, unsigned int* histo, int width, int height){
for(int i = 0; i<height;i++){
for(int j = 0;j<width;j++){
int data = input[i*width+j];
histo[data*width+j]++;
}
}
}
//-----------read image to array-----------------------------------------------------------------
unsigned int *read_ppm( char *filename, int * xsize, int * ysize, int *maxval ){
if ( !filename || filename[0] == '\0') {
fprintf(stderr, "read_ppm but no file name\n");
return NULL; // fail
}
FILE *fp;
fprintf(stderr, "read_ppm( %s )\n", filename);
fp = fopen( filename, "rb");
if (!fp)
{
fprintf(stderr, "read_ppm() ERROR file '%s' cannot be opened for reading\n", filename);
return NULL; // fail
}
char chars[1024];
//int num = read(fd, chars, 1000);
int num = fread(chars, sizeof(char), 1000, fp);
if (chars[0] != 'P' || chars[1] != '6')
{
fprintf(stderr, "Texture::Texture() ERROR file '%s' does not start with \"P6\" I am expecting a binary PPM file\n", filename);
return NULL;
}
unsigned int width, height, maxvalue;
char *ptr = chars+3; // P 6 newline
if (*ptr == '#') // comment line!
{
ptr = 1 + strstr(ptr, "\n");
}
num = sscanf(ptr, "%d\n%d\n%d", &width, &height, &maxvalue);
fprintf(stderr, "read %d things width %d height %d maxval %d\n", num, width, height, maxvalue);
*xsize = width;
*ysize = height;
*maxval = maxvalue;
unsigned int *pic = (unsigned int *)malloc( width * height * sizeof(unsigned int));
if (!pic) {
fprintf(stderr, "read_ppm() unable to allocate %d x %d unsigned ints for the picture\n", width, height);
return NULL; // fail but return
}
// allocate buffer to read the rest of the file into
int bufsize = 3 * width * height * sizeof(unsigned char);
if ((*maxval) > 255) bufsize *= 2;
unsigned char *buf = (unsigned char *)malloc( bufsize );
if (!buf) {
fprintf(stderr, "read_ppm() unable to allocate %d bytes of read buffer\n", bufsize);
return NULL; // fail but return
}
// really read
char duh[80];
char *line = chars;
// find the start of the pixel data.
sprintf(duh, "%d\0", *xsize);
line = strstr(line, duh);
//fprintf(stderr, "%s found at offset %d\n", duh, line-chars);
line += strlen(duh) + 1;
sprintf(duh, "%d\0", *ysize);
line = strstr(line, duh);
//fprintf(stderr, "%s found at offset %d\n", duh, line-chars);
line += strlen(duh) + 1;
sprintf(duh, "%d\0", *maxval);
line = strstr(line, duh);
fprintf(stderr, "%s found at offset %d\n", duh, line - chars);
line += strlen(duh) + 1;
long offset = line - chars;
//lseek(fd, offset, SEEK_SET); // move to the correct offset
fseek(fp, offset, SEEK_SET); // move to the correct offset
//long numread = read(fd, buf, bufsize);
long numread = fread(buf, sizeof(char), bufsize, fp);
fprintf(stderr, "Texture %s read %ld of %ld bytes\n", filename, numread, bufsize);
fclose(fp);
int pixels = (*xsize) * (*ysize);
for (int i=0; i<pixels; i++)
pic[i] = (int) buf[3*i]; // red channel
return pic; // success
}
//--------------wiret array to a image-------------------------------------------------------------------
void write_ppm( char const *filename, int xsize, int ysize, int maxval,unsigned int *pic)
{
FILE *fp;
// int x,y;
fp = fopen(filename, "wb");
if (!fp)
{
fprintf(stderr, "FAILED TO OPEN FILE '%s' for writing\n");
exit(-1);
}
fprintf(fp, "P6\n");
fprintf(fp,"%d %d\n%d\n", xsize, ysize, maxval);
int numpix = xsize * ysize;
for (int i=0; i<numpix; i++) {
unsigned char uc = (unsigned char) pic[i];
fprintf(fp, "%c%c%c", uc, uc, uc);
}
fclose(fp);
}
//write histoBin result to excel diaLen, MAX_VALUE
void write_CSV(char const *filename,int width, int height, unsigned int *input){
FILE *fp;
fp = fopen(filename, "w+");
if (!fp)
{
fprintf(stderr, "FAILED TO OPEN FILE '%s' for writing\n");
exit(-1);
}
for(int i = 0;i< height;i++){
for(int j = 0;j<width;j++){
fprintf(fp,"%d,",input[i*width+j]);
}
fprintf(fp,"\n");
}
fclose(fp);
}
// calculate newX newY after padding and rotation
void getNewXY(int inputX, int inputY, int width, int height,double angle, int *outputX, int *outputY){
double diaLen = (int)(sqrt(width * width + height * height) + 3);
double deltaX = diaLen - width ;
double deltaY = diaLen - height;
// printf("deltaX: %f, deltaY: %f\n",deltaX,deltaY);
double x = (double)inputX - deltaX / 2;
double y = (double)inputY - deltaY/ 2;
// printf("paddled x and y are: %f, %f\n", x, y);
double xCenter = -diaLen / 2;
double yCenter = -diaLen / 2;
// printf("deltaX: %f, deltaY: %f\n",xCenter,yCenter);
*outputX = -1 * (int)(cos(angle) * (x -xCenter) - sin(angle) * (y - yCenter) + xCenter ) ;
*outputY = -1 * (int)(sin(angle) * (x -xCenter) + cos(angle) * (y - yCenter) + yCenter );
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define imin(a,b) (a<b?a:b)
__global__ void set(double *dx,int N)
{
int tid=threadIdx.x+blockIdx.x*blockDim.x ;
if (tid<N)
dx[tid]=0.0;
} | code for sm_80
Function : _Z3setPdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101b04 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define imin(a,b) (a<b?a:b)
__global__ void set(double *dx,int N)
{
int tid=threadIdx.x+blockIdx.x*blockDim.x ;
if (tid<N)
dx[tid]=0.0;
} | .file "tmpxft_001655c5_00000000-6_set.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z3setPdiPdi
.type _Z23__device_stub__Z3setPdiPdi, @function
_Z23__device_stub__Z3setPdiPdi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3setPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z23__device_stub__Z3setPdiPdi, .-_Z23__device_stub__Z3setPdiPdi
.globl _Z3setPdi
.type _Z3setPdi, @function
_Z3setPdi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z3setPdiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3setPdi, .-_Z3setPdi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3setPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3setPdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define imin(a,b) (a<b?a:b)
__global__ void set(double *dx,int N)
{
int tid=threadIdx.x+blockIdx.x*blockDim.x ;
if (tid<N)
dx[tid]=0.0;
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define imin(a,b) (a<b?a:b)
__global__ void set(double *dx,int N)
{
int tid=threadIdx.x+blockIdx.x*blockDim.x ;
if (tid<N)
dx[tid]=0.0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define imin(a,b) (a<b?a:b)
__global__ void set(double *dx,int N)
{
int tid=threadIdx.x+blockIdx.x*blockDim.x ;
if (tid<N)
dx[tid]=0.0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3setPdi
.globl _Z3setPdi
.p2align 8
.type _Z3setPdi,@function
_Z3setPdi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3setPdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3setPdi, .Lfunc_end0-_Z3setPdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3setPdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3setPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define imin(a,b) (a<b?a:b)
__global__ void set(double *dx,int N)
{
int tid=threadIdx.x+blockIdx.x*blockDim.x ;
if (tid<N)
dx[tid]=0.0;
} | .text
.file "set.hip"
.globl _Z18__device_stub__setPdi # -- Begin function _Z18__device_stub__setPdi
.p2align 4, 0x90
.type _Z18__device_stub__setPdi,@function
_Z18__device_stub__setPdi: # @_Z18__device_stub__setPdi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3setPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__setPdi, .Lfunc_end0-_Z18__device_stub__setPdi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3setPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3setPdi,@object # @_Z3setPdi
.section .rodata,"a",@progbits
.globl _Z3setPdi
.p2align 3, 0x0
_Z3setPdi:
.quad _Z18__device_stub__setPdi
.size _Z3setPdi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3setPdi"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__setPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3setPdi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3setPdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101b04 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3setPdi
.globl _Z3setPdi
.p2align 8
.type _Z3setPdi,@function
_Z3setPdi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3setPdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3setPdi, .Lfunc_end0-_Z3setPdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3setPdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3setPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001655c5_00000000-6_set.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z3setPdiPdi
.type _Z23__device_stub__Z3setPdiPdi, @function
_Z23__device_stub__Z3setPdiPdi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3setPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z23__device_stub__Z3setPdiPdi, .-_Z23__device_stub__Z3setPdiPdi
.globl _Z3setPdi
.type _Z3setPdi, @function
_Z3setPdi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z3setPdiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3setPdi, .-_Z3setPdi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3setPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3setPdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "set.hip"
.globl _Z18__device_stub__setPdi # -- Begin function _Z18__device_stub__setPdi
.p2align 4, 0x90
.type _Z18__device_stub__setPdi,@function
_Z18__device_stub__setPdi: # @_Z18__device_stub__setPdi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3setPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__setPdi, .Lfunc_end0-_Z18__device_stub__setPdi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3setPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3setPdi,@object # @_Z3setPdi
.section .rodata,"a",@progbits
.globl _Z3setPdi
.p2align 3, 0x0
_Z3setPdi:
.quad _Z18__device_stub__setPdi
.size _Z3setPdi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3setPdi"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__setPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3setPdi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<thrust/reduce.h> | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<thrust/reduce.h> | #include <hip/hip_runtime.h>
#include<thrust/reduce.h> |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<thrust/reduce.h> | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<thrust/reduce.h> | .text
.file "exercise.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Ex. 6
// =====
// Modify the kernel so that each thread will also include its number.
#include <stdio.h>
__global__
void helloFromGPU() {
printf("Hello World from thread number %d!\n", threadIdx.x);
}
int main(int argc, char *argv[]) {
// Hello from CPU
printf("Hello World from CPU!\n");
helloFromGPU<<<1, 10>>>();
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z12helloFromGPUv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f1e0ff */
/*0070*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0090*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100800 */
/*00a0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00b0*/ MOV R11, 0x120 ; /* 0x00000120000b7802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R20, 0xa0 ; /* 0x000000a000147802 */
/* 0x000fc40000000f00 */
/*00d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0100*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0110*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Ex. 6
// =====
// Modify the kernel so that each thread will also include its number.
#include <stdio.h>
__global__
void helloFromGPU() {
printf("Hello World from thread number %d!\n", threadIdx.x);
}
int main(int argc, char *argv[]) {
// Hello from CPU
printf("Hello World from CPU!\n");
helloFromGPU<<<1, 10>>>();
cudaDeviceReset();
return 0;
} | .file "tmpxft_000b3ae4_00000000-6_ex6.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12helloFromGPUvv
.type _Z31__device_stub__Z12helloFromGPUvv, @function
_Z31__device_stub__Z12helloFromGPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12helloFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z12helloFromGPUvv, .-_Z31__device_stub__Z12helloFromGPUvv
.globl _Z12helloFromGPUv
.type _Z12helloFromGPUv, @function
_Z12helloFromGPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12helloFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12helloFromGPUv, .-_Z12helloFromGPUv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from CPU!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z31__device_stub__Z12helloFromGPUvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z12helloFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12helloFromGPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Ex. 6
// =====
// Modify the kernel so that each thread will also include its number.
#include <stdio.h>
__global__
void helloFromGPU() {
printf("Hello World from thread number %d!\n", threadIdx.x);
}
int main(int argc, char *argv[]) {
// Hello from CPU
printf("Hello World from CPU!\n");
helloFromGPU<<<1, 10>>>();
cudaDeviceReset();
return 0;
} | // Ex. 6
// =====
// Modify the kernel so that each thread will also include its number.
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__
void helloFromGPU() {
printf("Hello World from thread number %d!\n", threadIdx.x);
}
int main(int argc, char *argv[]) {
// Hello from CPU
printf("Hello World from CPU!\n");
helloFromGPU<<<1, 10>>>();
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Ex. 6
// =====
// Modify the kernel so that each thread will also include its number.
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__
void helloFromGPU() {
printf("Hello World from thread number %d!\n", threadIdx.x);
}
int main(int argc, char *argv[]) {
// Hello from CPU
printf("Hello World from CPU!\n");
helloFromGPU<<<1, 10>>>();
hipDeviceReset();
return 0;
} | .text
.file "ex6.hip"
.globl _Z27__device_stub__helloFromGPUv # -- Begin function _Z27__device_stub__helloFromGPUv
.p2align 4, 0x90
.type _Z27__device_stub__helloFromGPUv,@function
_Z27__device_stub__helloFromGPUv: # @_Z27__device_stub__helloFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__helloFromGPUv, .Lfunc_end0-_Z27__device_stub__helloFromGPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12helloFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12helloFromGPUv,@object # @_Z12helloFromGPUv
.section .rodata,"a",@progbits
.globl _Z12helloFromGPUv
.p2align 3, 0x0
_Z12helloFromGPUv:
.quad _Z27__device_stub__helloFromGPUv
.size _Z12helloFromGPUv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12helloFromGPUv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from CPU!"
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__helloFromGPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12helloFromGPUv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b3ae4_00000000-6_ex6.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12helloFromGPUvv
.type _Z31__device_stub__Z12helloFromGPUvv, @function
_Z31__device_stub__Z12helloFromGPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12helloFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z12helloFromGPUvv, .-_Z31__device_stub__Z12helloFromGPUvv
.globl _Z12helloFromGPUv
.type _Z12helloFromGPUv, @function
_Z12helloFromGPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12helloFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12helloFromGPUv, .-_Z12helloFromGPUv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from CPU!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z31__device_stub__Z12helloFromGPUvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z12helloFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12helloFromGPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ex6.hip"
.globl _Z27__device_stub__helloFromGPUv # -- Begin function _Z27__device_stub__helloFromGPUv
.p2align 4, 0x90
.type _Z27__device_stub__helloFromGPUv,@function
_Z27__device_stub__helloFromGPUv: # @_Z27__device_stub__helloFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__helloFromGPUv, .Lfunc_end0-_Z27__device_stub__helloFromGPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12helloFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12helloFromGPUv,@object # @_Z12helloFromGPUv
.section .rodata,"a",@progbits
.globl _Z12helloFromGPUv
.p2align 3, 0x0
_Z12helloFromGPUv:
.quad _Z27__device_stub__helloFromGPUv
.size _Z12helloFromGPUv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12helloFromGPUv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from CPU!"
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__helloFromGPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12helloFromGPUv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#include <cuda.h>
#include <stdlib.h>
#define N 256
__global__ void add(int *a, int *b, int* d) {
int tx = threadIdx.x, ty = threadIdx.y;
int bidx = blockIdx.x, bidy = blockIdx.y;
int bx = blockDim.x, by = blockDim.y;
int gy = gridDim.y;
int bid = bidx*gy + bidy;
int tid = bid*bx*by + tx*by + ty;
int c = a[tid] + b[tid];
atomicAdd(d, c);
}
void print_five(int* a, int* b){
int r = 35;
for(int i=0; i<10; ++i){
r += i;
printf("%d %d\n", a[r], b[r]);
}
}
void random_ints(int *a, int n){
int i;
for (i = 0; i < n; ++i)
a[i] = rand() %10;
}
int main(void) {
int *a, *b, *d; // host copies of a, b, c
int *d_a, *d_b, *d_d; // device copies of a, b, c
int size = N * sizeof(int), s = sizeof(int);
// Alloc space for device copies of a, b, c
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_d, s);
// Alloc space for host copies of a, b, c and setup input values
a = (int *)malloc(size); random_ints(a, N);
b = (int *)malloc(size); random_ints(b, N);
d = (int *)malloc(s); *d = 0;
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_d, d, s, cudaMemcpyHostToDevice);
// Launch add() kernel on GPU with N blocks
dim3 thread(4,4),block(4, 4);
add<<<block, thread>>>(d_a, d_b, d_d);
// Copy result back to host
cudaMemcpy(d, d_d, s, cudaMemcpyDeviceToHost);
print_five(a,b);
printf("%d\n",*d);
// Cleanup
free(a); free(b); free(d);
cudaFree(d_a); cudaFree(d_b); cudaFree(d_d);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e680000002100 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000ea20000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x10], R7 ; /* 0x0000040000007a24 */
/* 0x001fe200078e0207 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fc600000001ff */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fc800078e0203 */
/*0090*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x004fc800078e0205 */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe400078e0207 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*00f0*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe20000000f00 */
/*0100*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*0110*/ S2R R6, SR_LANEID ; /* 0x0000000000067919 */
/* 0x000e2a0000000000 */
/*0120*/ ISETP.EQ.U32.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x001fc4000bf02070 */
/*0130*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe40000000f00 */
/*0140*/ IADD3 R0, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x004fc80007ffe0ff */
/*0150*/ REDUX.SUM UR5, R0 ; /* 0x00000000000573c4 */
/* 0x000e24000000c000 */
/*0160*/ MOV R9, UR5 ; /* 0x0000000500097c02 */
/* 0x001fca0008000f00 */
/*0170*/ @P0 RED.E.ADD.STRONG.GPU [R6.64], R9 ; /* 0x000000090600098e */
/* 0x000fe2000c10e186 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#include <cuda.h>
#include <stdlib.h>
#define N 256
__global__ void add(int *a, int *b, int* d) {
int tx = threadIdx.x, ty = threadIdx.y;
int bidx = blockIdx.x, bidy = blockIdx.y;
int bx = blockDim.x, by = blockDim.y;
int gy = gridDim.y;
int bid = bidx*gy + bidy;
int tid = bid*bx*by + tx*by + ty;
int c = a[tid] + b[tid];
atomicAdd(d, c);
}
void print_five(int* a, int* b){
int r = 35;
for(int i=0; i<10; ++i){
r += i;
printf("%d %d\n", a[r], b[r]);
}
}
void random_ints(int *a, int n){
int i;
for (i = 0; i < n; ++i)
a[i] = rand() %10;
}
int main(void) {
int *a, *b, *d; // host copies of a, b, c
int *d_a, *d_b, *d_d; // device copies of a, b, c
int size = N * sizeof(int), s = sizeof(int);
// Alloc space for device copies of a, b, c
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_d, s);
// Alloc space for host copies of a, b, c and setup input values
a = (int *)malloc(size); random_ints(a, N);
b = (int *)malloc(size); random_ints(b, N);
d = (int *)malloc(s); *d = 0;
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_d, d, s, cudaMemcpyHostToDevice);
// Launch add() kernel on GPU with N blocks
dim3 thread(4,4),block(4, 4);
add<<<block, thread>>>(d_a, d_b, d_d);
// Copy result back to host
cudaMemcpy(d, d_d, s, cudaMemcpyDeviceToHost);
print_five(a,b);
printf("%d\n",*d);
// Cleanup
free(a); free(b); free(d);
cudaFree(d_a); cudaFree(d_b); cudaFree(d_d);
return 0;
} | .file "tmpxft_001299f6_00000000-6_test6.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d %d\n"
.text
.globl _Z10print_fivePiS_
.type _Z10print_fivePiS_, @function
_Z10print_fivePiS_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r13
movq %rsi, %r12
movl $0, %ebx
movl $35, %ebp
leaq .LC0(%rip), %r14
.L4:
addl %ebx, %ebp
movslq %ebp, %rax
movl (%r12,%rax,4), %ecx
movl 0(%r13,%rax,4), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl $10, %ebx
jne .L4
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10print_fivePiS_, .-_Z10print_fivePiS_
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L12
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L9:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L9
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1
.LC1:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1024, %edi
call malloc@PLT
movq %rax, %r12
movl $256, %esi
movq %rax, %rdi
call _Z11random_intsPii
movl $1024, %edi
call malloc@PLT
movq %rax, %rbp
movl $256, %esi
movq %rax, %rdi
call _Z11random_intsPii
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, (%rax)
movl $1, %ecx
movl $1024, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1024, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 32(%rsp)
movl $4, 36(%rsp)
movl $4, 44(%rsp)
movl $4, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L24:
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbp, %rsi
movq %r12, %rdi
call _Z10print_fivePiS_
movl (%rbx), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L24
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
#include <cuda.h>
#include <stdlib.h>
#define N 256
__global__ void add(int *a, int *b, int* d) {
int tx = threadIdx.x, ty = threadIdx.y;
int bidx = blockIdx.x, bidy = blockIdx.y;
int bx = blockDim.x, by = blockDim.y;
int gy = gridDim.y;
int bid = bidx*gy + bidy;
int tid = bid*bx*by + tx*by + ty;
int c = a[tid] + b[tid];
atomicAdd(d, c);
}
void print_five(int* a, int* b){
int r = 35;
for(int i=0; i<10; ++i){
r += i;
printf("%d %d\n", a[r], b[r]);
}
}
void random_ints(int *a, int n){
int i;
for (i = 0; i < n; ++i)
a[i] = rand() %10;
}
int main(void) {
int *a, *b, *d; // host copies of a, b, c
int *d_a, *d_b, *d_d; // device copies of a, b, c
int size = N * sizeof(int), s = sizeof(int);
// Alloc space for device copies of a, b, c
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_d, s);
// Alloc space for host copies of a, b, c and setup input values
a = (int *)malloc(size); random_ints(a, N);
b = (int *)malloc(size); random_ints(b, N);
d = (int *)malloc(s); *d = 0;
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_d, d, s, cudaMemcpyHostToDevice);
// Launch add() kernel on GPU with N blocks
dim3 thread(4,4),block(4, 4);
add<<<block, thread>>>(d_a, d_b, d_d);
// Copy result back to host
cudaMemcpy(d, d_d, s, cudaMemcpyDeviceToHost);
print_five(a,b);
printf("%d\n",*d);
// Cleanup
free(a); free(b); free(d);
cudaFree(d_a); cudaFree(d_b); cudaFree(d_d);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#define N 256
__global__ void add(int *a, int *b, int* d) {
int tx = threadIdx.x, ty = threadIdx.y;
int bidx = blockIdx.x, bidy = blockIdx.y;
int bx = blockDim.x, by = blockDim.y;
int gy = gridDim.y;
int bid = bidx*gy + bidy;
int tid = bid*bx*by + tx*by + ty;
int c = a[tid] + b[tid];
atomicAdd(d, c);
}
void print_five(int* a, int* b){
int r = 35;
for(int i=0; i<10; ++i){
r += i;
printf("%d %d\n", a[r], b[r]);
}
}
void random_ints(int *a, int n){
int i;
for (i = 0; i < n; ++i)
a[i] = rand() %10;
}
int main(void) {
int *a, *b, *d; // host copies of a, b, c
int *d_a, *d_b, *d_d; // device copies of a, b, c
int size = N * sizeof(int), s = sizeof(int);
// Alloc space for device copies of a, b, c
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_d, s);
// Alloc space for host copies of a, b, c and setup input values
a = (int *)malloc(size); random_ints(a, N);
b = (int *)malloc(size); random_ints(b, N);
d = (int *)malloc(s); *d = 0;
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
hipMemcpy(d_d, d, s, hipMemcpyHostToDevice);
// Launch add() kernel on GPU with N blocks
dim3 thread(4,4),block(4, 4);
add<<<block, thread>>>(d_a, d_b, d_d);
// Copy result back to host
hipMemcpy(d, d_d, s, hipMemcpyDeviceToHost);
print_five(a,b);
printf("%d\n",*d);
// Cleanup
free(a); free(b); free(d);
hipFree(d_a); hipFree(d_b); hipFree(d_d);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#define N 256
__global__ void add(int *a, int *b, int* d) {
int tx = threadIdx.x, ty = threadIdx.y;
int bidx = blockIdx.x, bidy = blockIdx.y;
int bx = blockDim.x, by = blockDim.y;
int gy = gridDim.y;
int bid = bidx*gy + bidy;
int tid = bid*bx*by + tx*by + ty;
int c = a[tid] + b[tid];
atomicAdd(d, c);
}
void print_five(int* a, int* b){
int r = 35;
for(int i=0; i<10; ++i){
r += i;
printf("%d %d\n", a[r], b[r]);
}
}
void random_ints(int *a, int n){
int i;
for (i = 0; i < n; ++i)
a[i] = rand() %10;
}
int main(void) {
int *a, *b, *d; // host copies of a, b, c
int *d_a, *d_b, *d_d; // device copies of a, b, c
int size = N * sizeof(int), s = sizeof(int);
// Alloc space for device copies of a, b, c
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_d, s);
// Alloc space for host copies of a, b, c and setup input values
a = (int *)malloc(size); random_ints(a, N);
b = (int *)malloc(size); random_ints(b, N);
d = (int *)malloc(s); *d = 0;
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
hipMemcpy(d_d, d, s, hipMemcpyHostToDevice);
// Launch add() kernel on GPU with N blocks
dim3 thread(4,4),block(4, 4);
add<<<block, thread>>>(d_a, d_b, d_d);
// Copy result back to host
hipMemcpy(d, d_d, s, hipMemcpyDeviceToHost);
print_five(a,b);
printf("%d\n",*d);
// Cleanup
free(a); free(b); free(d);
hipFree(d_a); hipFree(d_b); hipFree(d_d);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s8, s[0:1], 0x24
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s14
s_and_b32 s4, s8, 0xffff
s_add_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s3, s4, v[1:2]
s_lshr_b32 s3, s8, 16
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[3:4], null, v2, s3, v[0:1]
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v0, v2
.LBB0_1:
s_ctz_i32_b32 s4, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v0, s4
s_lshl_b32 s4, 1, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s2, s2, s4
s_add_i32 s3, s3, s5
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB0_1
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#define N 256
__global__ void add(int *a, int *b, int* d) {
int tx = threadIdx.x, ty = threadIdx.y;
int bidx = blockIdx.x, bidy = blockIdx.y;
int bx = blockDim.x, by = blockDim.y;
int gy = gridDim.y;
int bid = bidx*gy + bidy;
int tid = bid*bx*by + tx*by + ty;
int c = a[tid] + b[tid];
atomicAdd(d, c);
}
void print_five(int* a, int* b){
int r = 35;
for(int i=0; i<10; ++i){
r += i;
printf("%d %d\n", a[r], b[r]);
}
}
void random_ints(int *a, int n){
int i;
for (i = 0; i < n; ++i)
a[i] = rand() %10;
}
int main(void) {
int *a, *b, *d; // host copies of a, b, c
int *d_a, *d_b, *d_d; // device copies of a, b, c
int size = N * sizeof(int), s = sizeof(int);
// Alloc space for device copies of a, b, c
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_d, s);
// Alloc space for host copies of a, b, c and setup input values
a = (int *)malloc(size); random_ints(a, N);
b = (int *)malloc(size); random_ints(b, N);
d = (int *)malloc(s); *d = 0;
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
hipMemcpy(d_d, d, s, hipMemcpyHostToDevice);
// Launch add() kernel on GPU with N blocks
dim3 thread(4,4),block(4, 4);
add<<<block, thread>>>(d_a, d_b, d_d);
// Copy result back to host
hipMemcpy(d, d_d, s, hipMemcpyDeviceToHost);
print_five(a,b);
printf("%d\n",*d);
// Cleanup
free(a); free(b); free(d);
hipFree(d_a); hipFree(d_b); hipFree(d_d);
return 0;
} | .text
.file "test6.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl _Z10print_fivePiS_ # -- Begin function _Z10print_fivePiS_
.p2align 4, 0x90
.type _Z10print_fivePiS_,@function
_Z10print_fivePiS_: # @_Z10print_fivePiS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
movl $35, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
addl %r12d, %r15d
movl (%r14,%r15,4), %esi
movl (%rbx,%r15,4), %edx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $10, %r12
jne .LBB1_1
# %bb.2:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10print_fivePiS_, .Lfunc_end1-_Z10print_fivePiS_
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z11random_intsPii, .Lfunc_end2-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $256, %r14 # imm = 0x100
jne .LBB3_1
# %bb.2: # %_Z11random_intsPii.exit
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_3: # %.lr.ph.i28
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r14,%r15,4)
incq %r15
cmpq $256, %r15 # imm = 0x100
jne .LBB3_3
# %bb.4: # %_Z11random_intsPii.exit32
movl $4, %edi
callq malloc
movq %rax, %r15
movl $0, (%rax)
movq 16(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $4, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $17179869188, %rdi # imm = 0x400000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq (%rsp), %rsi
movl $4, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $35, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_7: # =>This Inner Loop Header: Depth=1
addl %r13d, %r12d
movl (%rbx,%r12,4), %esi
movl (%r14,%r12,4), %edx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq $10, %r13
jne .LBB3_7
# %bb.8: # %_Z10print_fivePiS_.exit
movl (%r15), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %d\n"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d\n"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e680000002100 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000ea20000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x10], R7 ; /* 0x0000040000007a24 */
/* 0x001fe200078e0207 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fc600000001ff */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fc800078e0203 */
/*0090*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x004fc800078e0205 */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe400078e0207 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*00f0*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe20000000f00 */
/*0100*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*0110*/ S2R R6, SR_LANEID ; /* 0x0000000000067919 */
/* 0x000e2a0000000000 */
/*0120*/ ISETP.EQ.U32.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x001fc4000bf02070 */
/*0130*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe40000000f00 */
/*0140*/ IADD3 R0, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x004fc80007ffe0ff */
/*0150*/ REDUX.SUM UR5, R0 ; /* 0x00000000000573c4 */
/* 0x000e24000000c000 */
/*0160*/ MOV R9, UR5 ; /* 0x0000000500097c02 */
/* 0x001fca0008000f00 */
/*0170*/ @P0 RED.E.ADD.STRONG.GPU [R6.64], R9 ; /* 0x000000090600098e */
/* 0x000fe2000c10e186 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s8, s[0:1], 0x24
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s14
s_and_b32 s4, s8, 0xffff
s_add_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s3, s4, v[1:2]
s_lshr_b32 s3, s8, 16
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[3:4], null, v2, s3, v[0:1]
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v0, v2
.LBB0_1:
s_ctz_i32_b32 s4, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v0, s4
s_lshl_b32 s4, 1, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s2, s2, s4
s_add_i32 s3, s3, s5
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB0_1
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001299f6_00000000-6_test6.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d %d\n"
.text
.globl _Z10print_fivePiS_
.type _Z10print_fivePiS_, @function
_Z10print_fivePiS_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r13
movq %rsi, %r12
movl $0, %ebx
movl $35, %ebp
leaq .LC0(%rip), %r14
.L4:
addl %ebx, %ebp
movslq %ebp, %rax
movl (%r12,%rax,4), %ecx
movl 0(%r13,%rax,4), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl $10, %ebx
jne .L4
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10print_fivePiS_, .-_Z10print_fivePiS_
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L12
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L9:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L9
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1
.LC1:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1024, %edi
call malloc@PLT
movq %rax, %r12
movl $256, %esi
movq %rax, %rdi
call _Z11random_intsPii
movl $1024, %edi
call malloc@PLT
movq %rax, %rbp
movl $256, %esi
movq %rax, %rdi
call _Z11random_intsPii
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, (%rax)
movl $1, %ecx
movl $1024, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1024, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 32(%rsp)
movl $4, 36(%rsp)
movl $4, 44(%rsp)
movl $4, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L24:
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbp, %rsi
movq %r12, %rdi
call _Z10print_fivePiS_
movl (%rbx), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L24
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test6.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl _Z10print_fivePiS_ # -- Begin function _Z10print_fivePiS_
.p2align 4, 0x90
.type _Z10print_fivePiS_,@function
_Z10print_fivePiS_: # @_Z10print_fivePiS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
movl $35, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
addl %r12d, %r15d
movl (%r14,%r15,4), %esi
movl (%rbx,%r15,4), %edx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $10, %r12
jne .LBB1_1
# %bb.2:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10print_fivePiS_, .Lfunc_end1-_Z10print_fivePiS_
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z11random_intsPii, .Lfunc_end2-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $256, %r14 # imm = 0x100
jne .LBB3_1
# %bb.2: # %_Z11random_intsPii.exit
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_3: # %.lr.ph.i28
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r14,%r15,4)
incq %r15
cmpq $256, %r15 # imm = 0x100
jne .LBB3_3
# %bb.4: # %_Z11random_intsPii.exit32
movl $4, %edi
callq malloc
movq %rax, %r15
movl $0, (%rax)
movq 16(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $4, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $17179869188, %rdi # imm = 0x400000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq (%rsp), %rsi
movl $4, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $35, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_7: # =>This Inner Loop Header: Depth=1
addl %r13d, %r12d
movl (%rbx,%r12,4), %esi
movl (%r14,%r12,4), %edx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq $10, %r13
jne .LBB3_7
# %bb.8: # %_Z10print_fivePiS_.exit
movl (%r15), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %d\n"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d\n"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void matrixMulCUDA2(float *C, float *A, float *B, int n)
{
/*
Each thread computes more than 1 matrix elements
*/
// Define the starting row and ending row for each thread
int startRow = threadIdx.y * TILE_WIDTH;
int endRow = startRow + TILE_WIDTH;
// Define the starting column and ending column for each thread
int startCol = threadIdx.x * TILE_WIDTH;
int endCol = startCol + TILE_WIDTH;
// Now we have some block in 2 dimensions
for (int row = startRow; row < endRow; row++) {
for (int col = startCol; col < endCol; col++) {
if (row >= n || col >= n) {
continue;
}
// Compute the proper sum for each block
float sum = 0.0f; // Defined as a register (Better than directly writing to C)
for (int k = 0; k < n; k++) {
sum += A[row * n + k] * B[k * n + col];
}
// Write back sum into C
C[row * n + col] = sum;
}
}
} | code for sm_80
Function : _Z14matrixMulCUDA2PfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0020*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f01270 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0050*/ IMAD.SHL.U32 R3, R3, 0x10, RZ ; /* 0x0000001003037824 */
/* 0x001fe200078e00ff */
/*0060*/ SHF.L.U32 R0, R0, 0x4, RZ ; /* 0x0000000400007819 */
/* 0x002fc800000006ff */
/*0070*/ IADD3 R4, R3, 0xf, RZ ; /* 0x0000000f03047810 */
/* 0x000fe40007ffe0ff */
/*0080*/ IADD3 R2, R0, 0xf, RZ ; /* 0x0000000f00027810 */
/* 0x000fe40007ffe0ff */
/*0090*/ @P0 BRA 0x400 ; /* 0x0000036000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R5, R0.reuse, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x040fe40007ffe0ff */
/*00b0*/ IADD3 R8, R0.reuse, 0x2, RZ ; /* 0x0000000200087810 */
/* 0x040fe40007ffe0ff */
/*00c0*/ IADD3 R9, R0.reuse, 0x3, RZ ; /* 0x0000000300097810 */
/* 0x040fe40007ffe0ff */
/*00d0*/ IADD3 R10, R0, 0x4, RZ ; /* 0x00000004000a7810 */
/* 0x000fc40007ffe0ff */
/*00e0*/ IADD3 R11, R0.reuse, 0x5, RZ ; /* 0x00000005000b7810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ IADD3 R12, R0.reuse, 0x6, RZ ; /* 0x00000006000c7810 */
/* 0x040fe40007ffe0ff */
/*0100*/ IADD3 R13, R0.reuse, 0x7, RZ ; /* 0x00000007000d7810 */
/* 0x040fe40007ffe0ff */
/*0110*/ IADD3 R14, R0.reuse, 0x8, RZ ; /* 0x00000008000e7810 */
/* 0x040fe40007ffe0ff */
/*0120*/ IADD3 R15, R0.reuse, 0x9, RZ ; /* 0x00000009000f7810 */
/* 0x040fe40007ffe0ff */
/*0130*/ IADD3 R16, R0, 0xa, RZ ; /* 0x0000000a00107810 */
/* 0x000fc40007ffe0ff */
/*0140*/ IADD3 R17, R0.reuse, 0xb, RZ ; /* 0x0000000b00117810 */
/* 0x040fe40007ffe0ff */
/*0150*/ IADD3 R18, R0.reuse, 0xc, RZ ; /* 0x0000000c00127810 */
/* 0x040fe40007ffe0ff */
/*0160*/ IADD3 R19, R0.reuse, 0xd, RZ ; /* 0x0000000d00137810 */
/* 0x040fe40007ffe0ff */
/*0170*/ IADD3 R20, R0, 0xe, RZ ; /* 0x0000000e00147810 */
/* 0x000fe40007ffe0ff */
/*0180*/ ISETP.GE.AND P0, PT, R3.reuse, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x040fe20003f06270 */
/*0190*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*01a0*/ IMAD R6, R3, c[0x0][0x178], R0 ; /* 0x00005e0003067a24 */
/* 0x000fe400078e0200 */
/*01b0*/ ISETP.GE.OR P3, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fc40000766670 */
/*01c0*/ ISETP.GE.OR P2, PT, R5, c[0x0][0x178], P0 ; /* 0x00005e0005007a0c */
/* 0x000fe40000746670 */
/*01d0*/ ISETP.GE.OR P1, PT, R8, c[0x0][0x178], P0 ; /* 0x00005e0008007a0c */
/* 0x000fe40000726670 */
/*01e0*/ ISETP.GE.OR P6, PT, R9, c[0x0][0x178], P0 ; /* 0x00005e0009007a0c */
/* 0x000fe200007c6670 */
/*01f0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0200*/ ISETP.GE.OR P5, PT, R10, c[0x0][0x178], P0 ; /* 0x00005e000a007a0c */
/* 0x000fe400007a6670 */
/*0210*/ ISETP.GE.OR P4, PT, R11, c[0x0][0x178], P0 ; /* 0x00005e000b007a0c */
/* 0x000fc60000786670 */
/*0220*/ @!P3 STG.E [R6.64], RZ ; /* 0x000000ff0600b986 */
/* 0x0001e2000c101904 */
/*0230*/ ISETP.GE.OR P3, PT, R12, c[0x0][0x178], P0 ; /* 0x00005e000c007a0c */
/* 0x000fc60000766670 */
/*0240*/ @!P2 STG.E [R6.64+0x4], RZ ; /* 0x000004ff0600a986 */
/* 0x0001e2000c101904 */
/*0250*/ ISETP.GE.OR P2, PT, R13, c[0x0][0x178], P0 ; /* 0x00005e000d007a0c */
/* 0x000fc60000746670 */
/*0260*/ @!P1 STG.E [R6.64+0x8], RZ ; /* 0x000008ff06009986 */
/* 0x0001e2000c101904 */
/*0270*/ ISETP.GE.OR P1, PT, R14, c[0x0][0x178], P0 ; /* 0x00005e000e007a0c */
/* 0x000fc60000726670 */
/*0280*/ @!P6 STG.E [R6.64+0xc], RZ ; /* 0x00000cff0600e986 */
/* 0x0001e2000c101904 */
/*0290*/ ISETP.GE.OR P6, PT, R15, c[0x0][0x178], P0 ; /* 0x00005e000f007a0c */
/* 0x000fc600007c6670 */
/*02a0*/ @!P5 STG.E [R6.64+0x10], RZ ; /* 0x000010ff0600d986 */
/* 0x0001e2000c101904 */
/*02b0*/ ISETP.GE.OR P5, PT, R16, c[0x0][0x178], P0 ; /* 0x00005e0010007a0c */
/* 0x000fc600007a6670 */
/*02c0*/ @!P4 STG.E [R6.64+0x14], RZ ; /* 0x000014ff0600c986 */
/* 0x0001e2000c101904 */
/*02d0*/ ISETP.GE.OR P4, PT, R17, c[0x0][0x178], P0 ; /* 0x00005e0011007a0c */
/* 0x000fc60000786670 */
/*02e0*/ @!P3 STG.E [R6.64+0x18], RZ ; /* 0x000018ff0600b986 */
/* 0x0001e2000c101904 */
/*02f0*/ ISETP.GE.OR P3, PT, R18, c[0x0][0x178], P0 ; /* 0x00005e0012007a0c */
/* 0x000fc60000766670 */
/*0300*/ @!P2 STG.E [R6.64+0x1c], RZ ; /* 0x00001cff0600a986 */
/* 0x0001e2000c101904 */
/*0310*/ ISETP.GE.OR P2, PT, R19, c[0x0][0x178], P0 ; /* 0x00005e0013007a0c */
/* 0x000fc60000746670 */
/*0320*/ @!P1 STG.E [R6.64+0x20], RZ ; /* 0x000020ff06009986 */
/* 0x0001e2000c101904 */
/*0330*/ ISETP.GE.OR P1, PT, R20, c[0x0][0x178], P0 ; /* 0x00005e0014007a0c */
/* 0x000fe40000726670 */
/*0340*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x178], P0 ; /* 0x00005e0002007a0c */
/* 0x000fe20000706670 */
/*0350*/ @!P6 STG.E [R6.64+0x24], RZ ; /* 0x000024ff0600e986 */
/* 0x0001e8000c101904 */
/*0360*/ @!P5 STG.E [R6.64+0x28], RZ ; /* 0x000028ff0600d986 */
/* 0x0001e8000c101904 */
/*0370*/ @!P4 STG.E [R6.64+0x2c], RZ ; /* 0x00002cff0600c986 */
/* 0x0001e8000c101904 */
/*0380*/ @!P3 STG.E [R6.64+0x30], RZ ; /* 0x000030ff0600b986 */
/* 0x0001e8000c101904 */
/*0390*/ @!P2 STG.E [R6.64+0x34], RZ ; /* 0x000034ff0600a986 */
/* 0x0001e8000c101904 */
/*03a0*/ @!P1 STG.E [R6.64+0x38], RZ ; /* 0x000038ff06009986 */
/* 0x0001e8000c101904 */
/*03b0*/ @!P0 STG.E [R6.64+0x3c], RZ ; /* 0x00003cff06008986 */
/* 0x0001e2000c101904 */
/*03c0*/ ISETP.GE.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fc40003f06270 */
/*03d0*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fd60007ffe0ff */
/*03e0*/ @!P0 BRA 0x180 ; /* 0xfffffd9000008947 */
/* 0x001fea000383ffff */
/*03f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0400*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff057624 */
/* 0x000fca00078e00ff */
/*0410*/ IADD3 R6, R5.reuse, -0x1, RZ ; /* 0xffffffff05067810 */
/* 0x040fe40007ffe0ff */
/*0420*/ LOP3.LUT R5, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305057812 */
/* 0x000fe400078ec0ff */
/*0430*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f26070 */
/*0440*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe40007ffe1ff */
/*0450*/ MOV R12, 0x4 ; /* 0x00000004000c7802 */
/* 0x000fe20000000f00 */
/*0460*/ IMAD R7, R3, c[0x0][0x178], RZ ; /* 0x00005e0003077a24 */
/* 0x000fe200078e02ff */
/*0470*/ BSSY B0, 0x10f0 ; /* 0x00000c7000007945 */
/* 0x000fe20003800000 */
/*0480*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0490*/ MOV R8, R0 ; /* 0x0000000000087202 */
/* 0x000fe20000000f00 */
/*04a0*/ IMAD.WIDE R12, R7, R12, c[0x0][0x168] ; /* 0x00005a00070c7625 */
/* 0x001fc800078e020c */
/*04b0*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fe20003f06270 */
/*04c0*/ BSSY B1, 0x10a0 ; /* 0x00000bd000017945 */
/* 0x000fe60003800000 */
/*04d0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*04e0*/ @P0 BRA 0x1090 ; /* 0x00000ba000000947 */
/* 0x001fea0003800000 */
/*04f0*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*0500*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fe200078e00ff */
/*0510*/ @!P1 BRA 0xee0 ; /* 0x000009c000009947 */
/* 0x000fea0003800000 */
/*0520*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*0530*/ IMAD.IADD R16, R0, 0x1, R9 ; /* 0x0000000100107824 */
/* 0x000fe200078e0209 */
/*0540*/ MOV R17, 0x4 ; /* 0x0000000400117802 */
/* 0x000fe20000000f00 */
/*0550*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fe200078e00ff */
/*0560*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fe20000000f00 */
/*0570*/ IMAD.MOV.U32 R11, RZ, RZ, R6 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0006 */
/*0580*/ MOV R14, R12 ; /* 0x0000000c000e7202 */
/* 0x000fe20000000f00 */
/*0590*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e000d */
/*05a0*/ IMAD.WIDE R16, R16, R17, c[0x0][0x170] ; /* 0x00005c0010107625 */
/* 0x000fc800078e0211 */
/*05b0*/ @!P0 BRA 0xd50 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*05c0*/ ISETP.GT.AND P2, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe40003f44270 */
/*05d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*05e0*/ @!P2 BRA 0xa90 ; /* 0x000004a00000a947 */
/* 0x000fea0003800000 */
/*05f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0600*/ LDG.E R29, [R16.64] ; /* 0x00000004101d7981 */
/* 0x000ea8000c1e1900 */
/*0610*/ LDG.E R28, [R14.64] ; /* 0x000000040e1c7981 */
/* 0x000ea2000c1e1900 */
/*0620*/ MOV R25, c[0x0][0x178] ; /* 0x00005e0000197a02 */
/* 0x000fc60000000f00 */
/*0630*/ LDG.E R26, [R14.64+0x4] ; /* 0x000004040e1a7981 */
/* 0x000ee4000c1e1900 */
/*0640*/ IMAD.WIDE R22, R25, 0x4, R16 ; /* 0x0000000419167825 */
/* 0x000fca00078e0210 */
/*0650*/ LDG.E R27, [R22.64] ; /* 0x00000004161b7981 */
/* 0x0000e2000c1e1900 */
/*0660*/ IMAD.WIDE R20, R25, 0x4, R22 ; /* 0x0000000419147825 */
/* 0x000fcc00078e0216 */
/*0670*/ IMAD.WIDE R18, R25, 0x4, R20 ; /* 0x0000000419127825 */
/* 0x000fe200078e0214 */
/*0680*/ LDG.E R23, [R14.64+0x8] ; /* 0x000008040e177981 */
/* 0x001f28000c1e1900 */
/*0690*/ LDG.E R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000122000c1e1900 */
/*06a0*/ FFMA R28, R29, R28, R24 ; /* 0x0000001c1d1c7223 */
/* 0x004fc60000000018 */
/*06b0*/ LDG.E R29, [R14.64+0xc] ; /* 0x00000c040e1d7981 */
/* 0x000ea8000c1e1900 */
/*06c0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x0006a2000c1e1900 */
/*06d0*/ IMAD.WIDE R16, R25, 0x4, R18 ; /* 0x0000000419107825 */
/* 0x000fc800078e0212 */
/*06e0*/ FFMA R18, R27, R26, R28 ; /* 0x0000001a1b127223 */
/* 0x008fe2000000001c */
/*06f0*/ LDG.E R19, [R14.64+0x10] ; /* 0x000010040e137981 */
/* 0x000ee2000c1e1900 */
/*0700*/ IMAD.WIDE R26, R25, 0x4, R16 ; /* 0x00000004191a7825 */
/* 0x000fc600078e0210 */
/*0710*/ LDG.E R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x0002e6000c1e1900 */
/*0720*/ IMAD.WIDE R20, R25, 0x4, R26 ; /* 0x0000000419147825 */
/* 0x001fc800078e021a */
/*0730*/ FFMA R22, R22, R23, R18 ; /* 0x0000001716167223 */
/* 0x010fe20000000012 */
/*0740*/ LDG.E R17, [R14.64+0x14] ; /* 0x000014040e117981 */
/* 0x002f28000c1e1900 */
/*0750*/ LDG.E R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x000f22000c1e1900 */
/*0760*/ FFMA R18, R24, R29, R22 ; /* 0x0000001d18127223 */
/* 0x004fc60000000016 */
/*0770*/ LDG.E R29, [R14.64+0x18] ; /* 0x000018040e1d7981 */
/* 0x000ea8000c1e1900 */
/*0780*/ LDG.E R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x0006a2000c1e1900 */
/*0790*/ IMAD.WIDE R22, R25, 0x4, R20 ; /* 0x0000000419167825 */
/* 0x000fc800078e0214 */
/*07a0*/ FFMA R20, R28, R19, R18 ; /* 0x000000131c147223 */
/* 0x008fe20000000012 */
/*07b0*/ LDG.E R21, [R14.64+0x1c] ; /* 0x00001c040e157981 */
/* 0x000ee2000c1e1900 */
/*07c0*/ IMAD.WIDE R18, R25, 0x4, R22 ; /* 0x0000000419127825 */
/* 0x000fc600078e0216 */
/*07d0*/ LDG.E R28, [R22.64] ; /* 0x00000004161c7981 */
/* 0x0008e4000c1e1900 */
/*07e0*/ FFMA R22, R16, R17, R20 ; /* 0x0000001110167223 */
/* 0x010fe40000000014 */
/*07f0*/ LDG.E R23, [R14.64+0x20] ; /* 0x000020040e177981 */
/* 0x000f22000c1e1900 */
/*0800*/ IMAD.WIDE R16, R25, 0x4, R18 ; /* 0x0000000419107825 */
/* 0x000fc600078e0212 */
/*0810*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000128000c1e1900 */
/*0820*/ LDG.E R19, [R14.64+0x24] ; /* 0x000024040e137981 */
/* 0x001f62000c1e1900 */
/*0830*/ FFMA R29, R24, R29, R22 ; /* 0x0000001d181d7223 */
/* 0x004fc60000000016 */
/*0840*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000162000c1e1900 */
/*0850*/ IMAD.WIDE R26, R25, 0x4, R16 ; /* 0x00000004191a7825 */
/* 0x000fca00078e0210 */
/*0860*/ LDG.E R22, [R26.64] ; /* 0x000000041a167981 */
/* 0x0002a8000c1e1900 */
/*0870*/ LDG.E R17, [R14.64+0x28] ; /* 0x000028040e117981 */
/* 0x001ea2000c1e1900 */
/*0880*/ FFMA R21, R28, R21, R29 ; /* 0x000000151c157223 */
/* 0x008fe4000000001d */
/*0890*/ IMAD.WIDE R28, R25, 0x4, R26 ; /* 0x00000004191c7825 */
/* 0x000fe400078e021a */
/*08a0*/ LDG.E R26, [R14.64+0x2c] ; /* 0x00002c040e1a7981 */
/* 0x002ee8000c1e1900 */
/*08b0*/ LDG.E R27, [R14.64+0x30] ; /* 0x000030040e1b7981 */
/* 0x000ee2000c1e1900 */
/*08c0*/ FFMA R16, R20, R23, R21 ; /* 0x0000001714107223 */
/* 0x010fc60000000015 */
/*08d0*/ LDG.E R23, [R28.64] ; /* 0x000000041c177981 */
/* 0x0000e2000c1e1900 */
/*08e0*/ IMAD.WIDE R20, R25, 0x4, R28 ; /* 0x0000000419147825 */
/* 0x000fc600078e021c */
/*08f0*/ LDG.E R29, [R14.64+0x38] ; /* 0x000038040e1d7981 */
/* 0x001122000c1e1900 */
/*0900*/ FFMA R16, R24, R19, R16 ; /* 0x0000001318107223 */
/* 0x020fc60000000010 */
/*0910*/ LDG.E R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x000362000c1e1900 */
/*0920*/ IMAD.WIDE R18, R25, 0x4, R20 ; /* 0x0000000419127825 */
/* 0x000fc800078e0214 */
/*0930*/ FFMA R22, R22, R17, R16 ; /* 0x0000001116167223 */
/* 0x004fe40000000010 */
/*0940*/ IMAD.WIDE R16, R25, 0x4, R18 ; /* 0x0000000419107825 */
/* 0x000fe200078e0212 */
/*0950*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x0022a8000c1e1900 */
/*0960*/ LDG.E R21, [R14.64+0x3c] ; /* 0x00003c040e157981 */
/* 0x0000a8000c1e1900 */
/*0970*/ LDG.E R19, [R14.64+0x34] ; /* 0x000034040e137981 */
/* 0x0020a2000c1e1900 */
/*0980*/ FFMA R28, R23, R26, R22 ; /* 0x0000001a171c7223 */
/* 0x008fc40000000016 */
/*0990*/ IMAD.WIDE R22, R25, 0x4, R16 ; /* 0x0000000419167825 */
/* 0x000fe200078e0210 */
/*09a0*/ LDG.E R26, [R16.64] ; /* 0x00000004101a7981 */
/* 0x000326000c1e1900 */
/*09b0*/ FFMA R27, R24, R27, R28 ; /* 0x0000001b181b7223 */
/* 0x020fe4000000001c */
/*09c0*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x000ee2000c1e1900 */
/*09d0*/ IADD3 R11, R11, -0x10, RZ ; /* 0xfffffff00b0b7810 */
/* 0x000fc80007ffe0ff */
/*09e0*/ ISETP.GT.AND P2, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe40003f44270 */
/*09f0*/ IADD3 R18, P3, R14, 0x40, RZ ; /* 0x000000400e127810 */
/* 0x000fe20007f7e0ff */
/*0a00*/ IMAD.WIDE R16, R25, 0x4, R22 ; /* 0x0000000419107825 */
/* 0x002fe200078e0216 */
/*0a10*/ IADD3 R10, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fe40007ffe0ff */
/*0a20*/ MOV R14, R18 ; /* 0x00000012000e7202 */
/* 0x001fe20000000f00 */
/*0a30*/ FFMA R20, R20, R19, R27 ; /* 0x0000001314147223 */
/* 0x004fe4000000001b */
/*0a40*/ IMAD.X R19, RZ, RZ, R15, P3 ; /* 0x000000ffff137224 */
/* 0x000fc800018e060f */
/*0a50*/ IMAD.MOV.U32 R15, RZ, RZ, R19 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0013 */
/*0a60*/ FFMA R20, R26, R29, R20 ; /* 0x0000001d1a147223 */
/* 0x010fc80000000014 */
/*0a70*/ FFMA R24, R24, R21, R20 ; /* 0x0000001518187223 */
/* 0x008fe20000000014 */
/*0a80*/ @P2 BRA 0x600 ; /* 0xfffffb7000002947 */
/* 0x000fea000383ffff */
/*0a90*/ ISETP.GT.AND P2, PT, R11, 0x4, PT ; /* 0x000000040b00780c */
/* 0x000fda0003f44270 */
/*0aa0*/ @!P2 BRA 0xd30 ; /* 0x000002800000a947 */
/* 0x000fea0003800000 */
/*0ab0*/ MOV R25, c[0x0][0x178] ; /* 0x00005e0000197a02 */
/* 0x000fe20000000f00 */
/*0ac0*/ LDG.E R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x0000a8000c1e1900 */
/*0ad0*/ LDG.E R29, [R14.64] ; /* 0x000000040e1d7981 */
/* 0x000ea2000c1e1900 */
/*0ae0*/ IMAD.WIDE R18, R25, 0x4, R16 ; /* 0x0000000419127825 */
/* 0x000fc600078e0210 */
/*0af0*/ LDG.E R26, [R14.64+0x4] ; /* 0x000004040e1a7981 */
/* 0x000ee8000c1e1900 */
/*0b00*/ LDG.E R27, [R18.64] ; /* 0x00000004121b7981 */
/* 0x0002e2000c1e1900 */
/*0b10*/ IMAD.WIDE R20, R25, 0x4, R18 ; /* 0x0000000419147825 */
/* 0x000fcc00078e0212 */
/*0b20*/ IMAD.WIDE R22, R25.reuse, 0x4, R20 ; /* 0x0000000419167825 */
/* 0x040fe200078e0214 */
/*0b30*/ LDG.E R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x002328000c1e1900 */
/*0b40*/ LDG.E R19, [R14.64+0x8] ; /* 0x000008040e137981 */
/* 0x000f22000c1e1900 */
/*0b50*/ IMAD.WIDE R16, R25, 0x4, R22 ; /* 0x0000000419107825 */
/* 0x001fc600078e0216 */
/*0b60*/ LDG.E R21, [R14.64+0x10] ; /* 0x000010040e157981 */
/* 0x002f62000c1e1900 */
/*0b70*/ FFMA R28, R28, R29, R24 ; /* 0x0000001d1c1c7223 */
/* 0x004fc60000000018 */
/*0b80*/ LDG.E R29, [R14.64+0xc] ; /* 0x00000c040e1d7981 */
/* 0x000ea8000c1e1900 */
/*0b90*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0000a2000c1e1900 */
/*0ba0*/ FFMA R20, R27, R26, R28 ; /* 0x0000001a1b147223 */
/* 0x008fc6000000001c */
/*0bb0*/ LDG.E R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x000362000c1e1900 */
/*0bc0*/ IMAD.WIDE R26, R25, 0x4, R16 ; /* 0x00000004191a7825 */
/* 0x000fc600078e0210 */
/*0bd0*/ LDG.E R17, [R14.64+0x18] ; /* 0x000018040e117981 */
/* 0x002ee2000c1e1900 */
/*0be0*/ FFMA R16, R18, R19, R20 ; /* 0x0000001312107223 */
/* 0x010fe40000000014 */
/*0bf0*/ IMAD.WIDE R18, R25.reuse, 0x4, R26 ; /* 0x0000000419127825 */
/* 0x040fe200078e021a */
/*0c00*/ LDG.E R20, [R26.64] ; /* 0x000000041a147981 */
/* 0x000f2a000c1e1900 */
/*0c10*/ IMAD.WIDE R22, R25, 0x4, R18 ; /* 0x0000000419167825 */
/* 0x001fc800078e0212 */
/*0c20*/ FFMA R16, R24, R29, R16 ; /* 0x0000001d18107223 */
/* 0x004fe40000000010 */
/*0c30*/ LDG.E R29, [R14.64+0x14] ; /* 0x000014040e1d7981 */
/* 0x000f28000c1e1900 */
/*0c40*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000ee2000c1e1900 */
/*0c50*/ FFMA R16, R28, R21, R16 ; /* 0x000000151c107223 */
/* 0x020fc60000000010 */
/*0c60*/ LDG.E R28, [R14.64+0x1c] ; /* 0x00001c040e1c7981 */
/* 0x0000a8000c1e1900 */
/*0c70*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x000ea2000c1e1900 */
/*0c80*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0c90*/ IADD3 R10, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fe40007ffe0ff */
/*0ca0*/ IADD3 R11, R11, -0x8, RZ ; /* 0xfffffff80b0b7810 */
/* 0x000fe20007ffe0ff */
/*0cb0*/ FFMA R16, R20, R29, R16 ; /* 0x0000001d14107223 */
/* 0x010fe20000000010 */
/*0cc0*/ IADD3 R20, P2, R14, 0x20, RZ ; /* 0x000000200e147810 */
/* 0x000fc60007f5e0ff */
/*0cd0*/ FFMA R24, R24, R17, R16 ; /* 0x0000001118187223 */
/* 0x008fe40000000010 */
/*0ce0*/ IMAD.X R27, RZ, RZ, R15, P2 ; /* 0x000000ffff1b7224 */
/* 0x000fe200010e060f */
/*0cf0*/ MOV R14, R20 ; /* 0x00000014000e7202 */
/* 0x001fe20000000f00 */
/*0d00*/ IMAD.WIDE R16, R25, 0x4, R22 ; /* 0x0000000419107825 */
/* 0x000fc800078e0216 */
/*0d10*/ FFMA R24, R21, R28, R24 ; /* 0x0000001c15187223 */
/* 0x004fe40000000018 */
/*0d20*/ IMAD.MOV.U32 R15, RZ, RZ, R27 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e001b */
/*0d30*/ ISETP.NE.OR P0, PT, R11, RZ, P0 ; /* 0x000000ff0b00720c */
/* 0x000fda0000705670 */
/*0d40*/ @!P0 BRA 0xee0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0d50*/ LDG.E R26, [R16.64] ; /* 0x00000004101a7981 */
/* 0x0000a8000c1e1900 */
/*0d60*/ LDG.E R25, [R14.64] ; /* 0x000000040e197981 */
/* 0x000ea2000c1e1900 */
/*0d70*/ MOV R27, c[0x0][0x178] ; /* 0x00005e00001b7a02 */
/* 0x000fc60000000f00 */
/*0d80*/ LDG.E R29, [R14.64+0x4] ; /* 0x000004040e1d7981 */
/* 0x000ee4000c1e1900 */
/*0d90*/ IMAD.WIDE R22, R27.reuse, 0x4, R16 ; /* 0x000000041b167825 */
/* 0x040fe400078e0210 */
/*0da0*/ LDG.E R17, [R14.64+0x8] ; /* 0x000008040e117981 */
/* 0x001f28000c1e1900 */
/*0db0*/ IMAD.WIDE R20, R27.reuse, 0x4, R22 ; /* 0x000000041b147825 */
/* 0x040fe200078e0216 */
/*0dc0*/ LDG.E R28, [R22.64] ; /* 0x00000004161c7981 */
/* 0x0000e8000c1e1900 */
/*0dd0*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000f22000c1e1900 */
/*0de0*/ IMAD.WIDE R18, R27, 0x4, R20 ; /* 0x000000041b127825 */
/* 0x000fc800078e0214 */
/*0df0*/ FFMA R26, R26, R25, R24 ; /* 0x000000191a1a7223 */
/* 0x004fe40000000018 */
/*0e00*/ LDG.E R25, [R14.64+0xc] ; /* 0x00000c040e197981 */
/* 0x0002a8000c1e1900 */
/*0e10*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000ea2000c1e1900 */
/*0e20*/ IADD3 R11, R11, -0x4, RZ ; /* 0xfffffffc0b0b7810 */
/* 0x000fc80007ffe0ff */
/*0e30*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f05270 */
/*0e40*/ IADD3 R22, P2, R14, 0x10, RZ ; /* 0x000000100e167810 */
/* 0x001fe20007f5e0ff */
/*0e50*/ FFMA R26, R28, R29, R26 ; /* 0x0000001d1c1a7223 */
/* 0x008fc8000000001a */
/*0e60*/ FFMA R26, R16, R17, R26 ; /* 0x00000011101a7223 */
/* 0x010fe4000000001a */
/*0e70*/ IMAD.X R23, RZ, RZ, R15, P2 ; /* 0x000000ffff177224 */
/* 0x000fe200010e060f */
/*0e80*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe20007ffe0ff */
/*0e90*/ IMAD.WIDE R16, R27, 0x4, R18 ; /* 0x000000041b107825 */
/* 0x000fe200078e0212 */
/*0ea0*/ MOV R14, R22 ; /* 0x00000016000e7202 */
/* 0x002fc60000000f00 */
/*0eb0*/ IMAD.MOV.U32 R15, RZ, RZ, R23 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0017 */
/*0ec0*/ FFMA R24, R24, R25, R26 ; /* 0x0000001918187223 */
/* 0x004fe2000000001a */
/*0ed0*/ @P0 BRA 0xd50 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ee0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ef0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe200078e00ff */
/*0f00*/ IADD3 R14, R7, R8, RZ ; /* 0x00000008070e7210 */
/* 0x000fca0007ffe0ff */
/*0f10*/ IMAD.WIDE R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fcc00078e020f */
/*0f20*/ @!P0 BRA 0x1080 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*0f30*/ IADD3 R11, R7, R10, RZ ; /* 0x0000000a070b7210 */
/* 0x000fe20007ffe0ff */
/*0f40*/ IMAD.MOV.U32 R22, RZ, RZ, 0x4 ; /* 0x00000004ff167424 */
/* 0x000fe400078e00ff */
/*0f50*/ IMAD R19, R10, c[0x0][0x178], R8 ; /* 0x00005e000a137a24 */
/* 0x000fe400078e0208 */
/*0f60*/ IMAD.WIDE R10, R11, R22, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fc800078e0216 */
/*0f70*/ IMAD.WIDE R16, R19, R22, c[0x0][0x170] ; /* 0x00005c0013107625 */
/* 0x000fe200078e0216 */
/*0f80*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000eaa000c1e1900 */
/*0f90*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ea2000c1e1900 */
/*0fa0*/ ISETP.NE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe20003f05270 */
/*0fb0*/ FFMA R24, R17, R18, R24 ; /* 0x0000001211187223 */
/* 0x004fd80000000018 */
/*0fc0*/ @!P0 BRA 0x1080 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0fd0*/ ISETP.NE.AND P0, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe20003f05270 */
/*0fe0*/ LDG.E R20, [R10.64+0x4] ; /* 0x000004040a147981 */
/* 0x000ea2000c1e1900 */
/*0ff0*/ IADD3 R19, R19, c[0x0][0x178], RZ ; /* 0x00005e0013137a10 */
/* 0x000fd60007ffe0ff */
/*1000*/ @P0 IADD3 R16, R19.reuse, c[0x0][0x178], RZ ; /* 0x00005e0013100a10 */
/* 0x040fe20007ffe0ff */
/*1010*/ IMAD.WIDE R18, R19, R22.reuse, c[0x0][0x170] ; /* 0x00005c0013127625 */
/* 0x080fe200078e0216 */
/*1020*/ @P0 LDG.E R21, [R10.64+0x8] ; /* 0x000008040a150981 */
/* 0x000ee6000c1e1900 */
/*1030*/ @P0 IMAD.WIDE R16, R16, R22, c[0x0][0x170] ; /* 0x00005c0010100625 */
/* 0x000fe400078e0216 */
/*1040*/ LDG.E R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x000ea8000c1e1900 */
/*1050*/ @P0 LDG.E R17, [R16.64] ; /* 0x0000000410110981 */
/* 0x000ee2000c1e1900 */
/*1060*/ FFMA R24, R19, R20, R24 ; /* 0x0000001413187223 */
/* 0x004fc80000000018 */
/*1070*/ @P0 FFMA R24, R17, R21, R24 ; /* 0x0000001511180223 */
/* 0x008fca0000000018 */
/*1080*/ STG.E [R14.64], R24 ; /* 0x000000180e007986 */
/* 0x0001e4000c101904 */
/*1090*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*10a0*/ ISETP.GE.AND P0, PT, R8.reuse, R2, PT ; /* 0x000000020800720c */
/* 0x040fe40003f06270 */
/*10b0*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe40007ffe0ff */
/*10c0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fd20007ffe0ff */
/*10d0*/ @!P0 BRA 0x4b0 ; /* 0xfffff3d000008947 */
/* 0x000fea000383ffff */
/*10e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*10f0*/ ISETP.GE.AND P0, PT, R3.reuse, R4, PT ; /* 0x000000040300720c */
/* 0x040fe40003f06270 */
/*1100*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fd60007ffe0ff */
/*1110*/ @!P0 BRA 0x450 ; /* 0xfffff33000008947 */
/* 0x000fea000383ffff */
/*1120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1130*/ BRA 0x1130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void matrixMulCUDA2(float *C, float *A, float *B, int n)
{
/*
Each thread computes more than 1 matrix elements
*/
// Define the starting row and ending row for each thread
int startRow = threadIdx.y * TILE_WIDTH;
int endRow = startRow + TILE_WIDTH;
// Define the starting column and ending column for each thread
int startCol = threadIdx.x * TILE_WIDTH;
int endCol = startCol + TILE_WIDTH;
// Now we have some block in 2 dimensions
for (int row = startRow; row < endRow; row++) {
for (int col = startCol; col < endCol; col++) {
if (row >= n || col >= n) {
continue;
}
// Compute the proper sum for each block
float sum = 0.0f; // Defined as a register (Better than directly writing to C)
for (int k = 0; k < n; k++) {
sum += A[row * n + k] * B[k * n + col];
}
// Write back sum into C
C[row * n + col] = sum;
}
}
} | .file "tmpxft_000c59e0_00000000-6_matrixMulCUDA2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14matrixMulCUDA2PfS_S_iPfS_S_i
.type _Z39__device_stub__Z14matrixMulCUDA2PfS_S_iPfS_S_i, @function
_Z39__device_stub__Z14matrixMulCUDA2PfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14matrixMulCUDA2PfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z14matrixMulCUDA2PfS_S_iPfS_S_i, .-_Z39__device_stub__Z14matrixMulCUDA2PfS_S_iPfS_S_i
.globl _Z14matrixMulCUDA2PfS_S_i
.type _Z14matrixMulCUDA2PfS_S_i, @function
_Z14matrixMulCUDA2PfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14matrixMulCUDA2PfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14matrixMulCUDA2PfS_S_i, .-_Z14matrixMulCUDA2PfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14matrixMulCUDA2PfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14matrixMulCUDA2PfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void matrixMulCUDA2(float *C, float *A, float *B, int n)
{
/*
Each thread computes more than 1 matrix elements
*/
// Define the starting row and ending row for each thread
int startRow = threadIdx.y * TILE_WIDTH;
int endRow = startRow + TILE_WIDTH;
// Define the starting column and ending column for each thread
int startCol = threadIdx.x * TILE_WIDTH;
int endCol = startCol + TILE_WIDTH;
// Now we have some block in 2 dimensions
for (int row = startRow; row < endRow; row++) {
for (int col = startCol; col < endCol; col++) {
if (row >= n || col >= n) {
continue;
}
// Compute the proper sum for each block
float sum = 0.0f; // Defined as a register (Better than directly writing to C)
for (int k = 0; k < n; k++) {
sum += A[row * n + k] * B[k * n + col];
}
// Write back sum into C
C[row * n + col] = sum;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMulCUDA2(float *C, float *A, float *B, int n)
{
/*
Each thread computes more than 1 matrix elements
*/
// Define the starting row and ending row for each thread
int startRow = threadIdx.y * TILE_WIDTH;
int endRow = startRow + TILE_WIDTH;
// Define the starting column and ending column for each thread
int startCol = threadIdx.x * TILE_WIDTH;
int endCol = startCol + TILE_WIDTH;
// Now we have some block in 2 dimensions
for (int row = startRow; row < endRow; row++) {
for (int col = startCol; col < endCol; col++) {
if (row >= n || col >= n) {
continue;
}
// Compute the proper sum for each block
float sum = 0.0f; // Defined as a register (Better than directly writing to C)
for (int k = 0; k < n; k++) {
sum += A[row * n + k] * B[k * n + col];
}
// Write back sum into C
C[row * n + col] = sum;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMulCUDA2(float *C, float *A, float *B, int n)
{
/*
Each thread computes more than 1 matrix elements
*/
// Define the starting row and ending row for each thread
int startRow = threadIdx.y * TILE_WIDTH;
int endRow = startRow + TILE_WIDTH;
// Define the starting column and ending column for each thread
int startCol = threadIdx.x * TILE_WIDTH;
int endCol = startCol + TILE_WIDTH;
// Now we have some block in 2 dimensions
for (int row = startRow; row < endRow; row++) {
for (int col = startCol; col < endCol; col++) {
if (row >= n || col >= n) {
continue;
}
// Compute the proper sum for each block
float sum = 0.0f; // Defined as a register (Better than directly writing to C)
for (int k = 0; k < n; k++) {
sum += A[row * n + k] * B[k * n + col];
}
// Write back sum into C
C[row * n + col] = sum;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14matrixMulCUDA2PfS_S_i
.globl _Z14matrixMulCUDA2PfS_S_i
.p2align 8
.type _Z14matrixMulCUDA2PfS_S_i,@function
_Z14matrixMulCUDA2PfS_S_i:
s_clause 0x2
s_load_b32 s8, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b32_e32 v1, 4, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v7, 0x3ff0, v1
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v10, 4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v8, 15, v7
v_or_b32_e32 v9, 15, v10
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v2, v0, s8
s_cmp_gt_i32 s8, 0
s_cselect_b32 s1, -1, 0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 4, v2
s_branch .LBB0_2
.LBB0_1:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v0, 1, v10
v_cmp_eq_u32_e32 vcc_lo, v10, v9
v_add_nc_u32_e32 v2, s8, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v10, v0
s_or_b32 s9, vcc_lo, s9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execz .LBB0_9
.LBB0_2:
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v12, v7
v_mul_lo_u32 v11, v10, s8
v_cmp_gt_i32_e64 s0, s8, v10
s_mov_b32 s10, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_3:
v_add_nc_u32_e32 v5, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_store_b32 v[5:6], v13, off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v0, 1, v12
v_cmp_eq_u32_e32 vcc_lo, v12, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v12, v0
s_or_b32 s10, vcc_lo, s10
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB0_1
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s8, v12
s_and_b32 s12, s0, vcc_lo
s_and_saveexec_b32 s11, s12
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v13, 0
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_3
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
v_mov_b32_e32 v0, v12
s_mov_b32 s12, s8
.p2align 6
.LBB0_8:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[14:15], 2, v[0:1]
s_add_i32 s12, s12, -1
s_cmp_eq_u32 s12, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v14, vcc_lo, s2, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
global_load_b32 v16, v[5:6], off
global_load_b32 v14, v[14:15], off
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_nc_u32_e32 v0, s8, v0
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v13, v16, v14
s_cbranch_scc0 .LBB0_8
s_branch .LBB0_3
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14matrixMulCUDA2PfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 13
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14matrixMulCUDA2PfS_S_i, .Lfunc_end0-_Z14matrixMulCUDA2PfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14matrixMulCUDA2PfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 15
.sgpr_spill_count: 0
.symbol: _Z14matrixMulCUDA2PfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMulCUDA2(float *C, float *A, float *B, int n)
{
/*
Each thread computes more than 1 matrix elements
*/
// Define the starting row and ending row for each thread
int startRow = threadIdx.y * TILE_WIDTH;
int endRow = startRow + TILE_WIDTH;
// Define the starting column and ending column for each thread
int startCol = threadIdx.x * TILE_WIDTH;
int endCol = startCol + TILE_WIDTH;
// Now we have some block in 2 dimensions
for (int row = startRow; row < endRow; row++) {
for (int col = startCol; col < endCol; col++) {
if (row >= n || col >= n) {
continue;
}
// Compute the proper sum for each block
float sum = 0.0f; // Defined as a register (Better than directly writing to C)
for (int k = 0; k < n; k++) {
sum += A[row * n + k] * B[k * n + col];
}
// Write back sum into C
C[row * n + col] = sum;
}
}
} | .text
.file "matrixMulCUDA2.hip"
.globl _Z29__device_stub__matrixMulCUDA2PfS_S_i # -- Begin function _Z29__device_stub__matrixMulCUDA2PfS_S_i
.p2align 4, 0x90
.type _Z29__device_stub__matrixMulCUDA2PfS_S_i,@function
_Z29__device_stub__matrixMulCUDA2PfS_S_i: # @_Z29__device_stub__matrixMulCUDA2PfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14matrixMulCUDA2PfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__matrixMulCUDA2PfS_S_i, .Lfunc_end0-_Z29__device_stub__matrixMulCUDA2PfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14matrixMulCUDA2PfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14matrixMulCUDA2PfS_S_i,@object # @_Z14matrixMulCUDA2PfS_S_i
.section .rodata,"a",@progbits
.globl _Z14matrixMulCUDA2PfS_S_i
.p2align 3, 0x0
_Z14matrixMulCUDA2PfS_S_i:
.quad _Z29__device_stub__matrixMulCUDA2PfS_S_i
.size _Z14matrixMulCUDA2PfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14matrixMulCUDA2PfS_S_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__matrixMulCUDA2PfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14matrixMulCUDA2PfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14matrixMulCUDA2PfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0020*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f01270 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0050*/ IMAD.SHL.U32 R3, R3, 0x10, RZ ; /* 0x0000001003037824 */
/* 0x001fe200078e00ff */
/*0060*/ SHF.L.U32 R0, R0, 0x4, RZ ; /* 0x0000000400007819 */
/* 0x002fc800000006ff */
/*0070*/ IADD3 R4, R3, 0xf, RZ ; /* 0x0000000f03047810 */
/* 0x000fe40007ffe0ff */
/*0080*/ IADD3 R2, R0, 0xf, RZ ; /* 0x0000000f00027810 */
/* 0x000fe40007ffe0ff */
/*0090*/ @P0 BRA 0x400 ; /* 0x0000036000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R5, R0.reuse, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x040fe40007ffe0ff */
/*00b0*/ IADD3 R8, R0.reuse, 0x2, RZ ; /* 0x0000000200087810 */
/* 0x040fe40007ffe0ff */
/*00c0*/ IADD3 R9, R0.reuse, 0x3, RZ ; /* 0x0000000300097810 */
/* 0x040fe40007ffe0ff */
/*00d0*/ IADD3 R10, R0, 0x4, RZ ; /* 0x00000004000a7810 */
/* 0x000fc40007ffe0ff */
/*00e0*/ IADD3 R11, R0.reuse, 0x5, RZ ; /* 0x00000005000b7810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ IADD3 R12, R0.reuse, 0x6, RZ ; /* 0x00000006000c7810 */
/* 0x040fe40007ffe0ff */
/*0100*/ IADD3 R13, R0.reuse, 0x7, RZ ; /* 0x00000007000d7810 */
/* 0x040fe40007ffe0ff */
/*0110*/ IADD3 R14, R0.reuse, 0x8, RZ ; /* 0x00000008000e7810 */
/* 0x040fe40007ffe0ff */
/*0120*/ IADD3 R15, R0.reuse, 0x9, RZ ; /* 0x00000009000f7810 */
/* 0x040fe40007ffe0ff */
/*0130*/ IADD3 R16, R0, 0xa, RZ ; /* 0x0000000a00107810 */
/* 0x000fc40007ffe0ff */
/*0140*/ IADD3 R17, R0.reuse, 0xb, RZ ; /* 0x0000000b00117810 */
/* 0x040fe40007ffe0ff */
/*0150*/ IADD3 R18, R0.reuse, 0xc, RZ ; /* 0x0000000c00127810 */
/* 0x040fe40007ffe0ff */
/*0160*/ IADD3 R19, R0.reuse, 0xd, RZ ; /* 0x0000000d00137810 */
/* 0x040fe40007ffe0ff */
/*0170*/ IADD3 R20, R0, 0xe, RZ ; /* 0x0000000e00147810 */
/* 0x000fe40007ffe0ff */
/*0180*/ ISETP.GE.AND P0, PT, R3.reuse, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x040fe20003f06270 */
/*0190*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*01a0*/ IMAD R6, R3, c[0x0][0x178], R0 ; /* 0x00005e0003067a24 */
/* 0x000fe400078e0200 */
/*01b0*/ ISETP.GE.OR P3, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fc40000766670 */
/*01c0*/ ISETP.GE.OR P2, PT, R5, c[0x0][0x178], P0 ; /* 0x00005e0005007a0c */
/* 0x000fe40000746670 */
/*01d0*/ ISETP.GE.OR P1, PT, R8, c[0x0][0x178], P0 ; /* 0x00005e0008007a0c */
/* 0x000fe40000726670 */
/*01e0*/ ISETP.GE.OR P6, PT, R9, c[0x0][0x178], P0 ; /* 0x00005e0009007a0c */
/* 0x000fe200007c6670 */
/*01f0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0200*/ ISETP.GE.OR P5, PT, R10, c[0x0][0x178], P0 ; /* 0x00005e000a007a0c */
/* 0x000fe400007a6670 */
/*0210*/ ISETP.GE.OR P4, PT, R11, c[0x0][0x178], P0 ; /* 0x00005e000b007a0c */
/* 0x000fc60000786670 */
/*0220*/ @!P3 STG.E [R6.64], RZ ; /* 0x000000ff0600b986 */
/* 0x0001e2000c101904 */
/*0230*/ ISETP.GE.OR P3, PT, R12, c[0x0][0x178], P0 ; /* 0x00005e000c007a0c */
/* 0x000fc60000766670 */
/*0240*/ @!P2 STG.E [R6.64+0x4], RZ ; /* 0x000004ff0600a986 */
/* 0x0001e2000c101904 */
/*0250*/ ISETP.GE.OR P2, PT, R13, c[0x0][0x178], P0 ; /* 0x00005e000d007a0c */
/* 0x000fc60000746670 */
/*0260*/ @!P1 STG.E [R6.64+0x8], RZ ; /* 0x000008ff06009986 */
/* 0x0001e2000c101904 */
/*0270*/ ISETP.GE.OR P1, PT, R14, c[0x0][0x178], P0 ; /* 0x00005e000e007a0c */
/* 0x000fc60000726670 */
/*0280*/ @!P6 STG.E [R6.64+0xc], RZ ; /* 0x00000cff0600e986 */
/* 0x0001e2000c101904 */
/*0290*/ ISETP.GE.OR P6, PT, R15, c[0x0][0x178], P0 ; /* 0x00005e000f007a0c */
/* 0x000fc600007c6670 */
/*02a0*/ @!P5 STG.E [R6.64+0x10], RZ ; /* 0x000010ff0600d986 */
/* 0x0001e2000c101904 */
/*02b0*/ ISETP.GE.OR P5, PT, R16, c[0x0][0x178], P0 ; /* 0x00005e0010007a0c */
/* 0x000fc600007a6670 */
/*02c0*/ @!P4 STG.E [R6.64+0x14], RZ ; /* 0x000014ff0600c986 */
/* 0x0001e2000c101904 */
/*02d0*/ ISETP.GE.OR P4, PT, R17, c[0x0][0x178], P0 ; /* 0x00005e0011007a0c */
/* 0x000fc60000786670 */
/*02e0*/ @!P3 STG.E [R6.64+0x18], RZ ; /* 0x000018ff0600b986 */
/* 0x0001e2000c101904 */
/*02f0*/ ISETP.GE.OR P3, PT, R18, c[0x0][0x178], P0 ; /* 0x00005e0012007a0c */
/* 0x000fc60000766670 */
/*0300*/ @!P2 STG.E [R6.64+0x1c], RZ ; /* 0x00001cff0600a986 */
/* 0x0001e2000c101904 */
/*0310*/ ISETP.GE.OR P2, PT, R19, c[0x0][0x178], P0 ; /* 0x00005e0013007a0c */
/* 0x000fc60000746670 */
/*0320*/ @!P1 STG.E [R6.64+0x20], RZ ; /* 0x000020ff06009986 */
/* 0x0001e2000c101904 */
/*0330*/ ISETP.GE.OR P1, PT, R20, c[0x0][0x178], P0 ; /* 0x00005e0014007a0c */
/* 0x000fe40000726670 */
/*0340*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x178], P0 ; /* 0x00005e0002007a0c */
/* 0x000fe20000706670 */
/*0350*/ @!P6 STG.E [R6.64+0x24], RZ ; /* 0x000024ff0600e986 */
/* 0x0001e8000c101904 */
/*0360*/ @!P5 STG.E [R6.64+0x28], RZ ; /* 0x000028ff0600d986 */
/* 0x0001e8000c101904 */
/*0370*/ @!P4 STG.E [R6.64+0x2c], RZ ; /* 0x00002cff0600c986 */
/* 0x0001e8000c101904 */
/*0380*/ @!P3 STG.E [R6.64+0x30], RZ ; /* 0x000030ff0600b986 */
/* 0x0001e8000c101904 */
/*0390*/ @!P2 STG.E [R6.64+0x34], RZ ; /* 0x000034ff0600a986 */
/* 0x0001e8000c101904 */
/*03a0*/ @!P1 STG.E [R6.64+0x38], RZ ; /* 0x000038ff06009986 */
/* 0x0001e8000c101904 */
/*03b0*/ @!P0 STG.E [R6.64+0x3c], RZ ; /* 0x00003cff06008986 */
/* 0x0001e2000c101904 */
/*03c0*/ ISETP.GE.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fc40003f06270 */
/*03d0*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fd60007ffe0ff */
/*03e0*/ @!P0 BRA 0x180 ; /* 0xfffffd9000008947 */
/* 0x001fea000383ffff */
/*03f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0400*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff057624 */
/* 0x000fca00078e00ff */
/*0410*/ IADD3 R6, R5.reuse, -0x1, RZ ; /* 0xffffffff05067810 */
/* 0x040fe40007ffe0ff */
/*0420*/ LOP3.LUT R5, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305057812 */
/* 0x000fe400078ec0ff */
/*0430*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f26070 */
/*0440*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe40007ffe1ff */
/*0450*/ MOV R12, 0x4 ; /* 0x00000004000c7802 */
/* 0x000fe20000000f00 */
/*0460*/ IMAD R7, R3, c[0x0][0x178], RZ ; /* 0x00005e0003077a24 */
/* 0x000fe200078e02ff */
/*0470*/ BSSY B0, 0x10f0 ; /* 0x00000c7000007945 */
/* 0x000fe20003800000 */
/*0480*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0490*/ MOV R8, R0 ; /* 0x0000000000087202 */
/* 0x000fe20000000f00 */
/*04a0*/ IMAD.WIDE R12, R7, R12, c[0x0][0x168] ; /* 0x00005a00070c7625 */
/* 0x001fc800078e020c */
/*04b0*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fe20003f06270 */
/*04c0*/ BSSY B1, 0x10a0 ; /* 0x00000bd000017945 */
/* 0x000fe60003800000 */
/*04d0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*04e0*/ @P0 BRA 0x1090 ; /* 0x00000ba000000947 */
/* 0x001fea0003800000 */
/*04f0*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*0500*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fe200078e00ff */
/*0510*/ @!P1 BRA 0xee0 ; /* 0x000009c000009947 */
/* 0x000fea0003800000 */
/*0520*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*0530*/ IMAD.IADD R16, R0, 0x1, R9 ; /* 0x0000000100107824 */
/* 0x000fe200078e0209 */
/*0540*/ MOV R17, 0x4 ; /* 0x0000000400117802 */
/* 0x000fe20000000f00 */
/*0550*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fe200078e00ff */
/*0560*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fe20000000f00 */
/*0570*/ IMAD.MOV.U32 R11, RZ, RZ, R6 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0006 */
/*0580*/ MOV R14, R12 ; /* 0x0000000c000e7202 */
/* 0x000fe20000000f00 */
/*0590*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e000d */
/*05a0*/ IMAD.WIDE R16, R16, R17, c[0x0][0x170] ; /* 0x00005c0010107625 */
/* 0x000fc800078e0211 */
/*05b0*/ @!P0 BRA 0xd50 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*05c0*/ ISETP.GT.AND P2, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe40003f44270 */
/*05d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*05e0*/ @!P2 BRA 0xa90 ; /* 0x000004a00000a947 */
/* 0x000fea0003800000 */
/*05f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0600*/ LDG.E R29, [R16.64] ; /* 0x00000004101d7981 */
/* 0x000ea8000c1e1900 */
/*0610*/ LDG.E R28, [R14.64] ; /* 0x000000040e1c7981 */
/* 0x000ea2000c1e1900 */
/*0620*/ MOV R25, c[0x0][0x178] ; /* 0x00005e0000197a02 */
/* 0x000fc60000000f00 */
/*0630*/ LDG.E R26, [R14.64+0x4] ; /* 0x000004040e1a7981 */
/* 0x000ee4000c1e1900 */
/*0640*/ IMAD.WIDE R22, R25, 0x4, R16 ; /* 0x0000000419167825 */
/* 0x000fca00078e0210 */
/*0650*/ LDG.E R27, [R22.64] ; /* 0x00000004161b7981 */
/* 0x0000e2000c1e1900 */
/*0660*/ IMAD.WIDE R20, R25, 0x4, R22 ; /* 0x0000000419147825 */
/* 0x000fcc00078e0216 */
/*0670*/ IMAD.WIDE R18, R25, 0x4, R20 ; /* 0x0000000419127825 */
/* 0x000fe200078e0214 */
/*0680*/ LDG.E R23, [R14.64+0x8] ; /* 0x000008040e177981 */
/* 0x001f28000c1e1900 */
/*0690*/ LDG.E R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000122000c1e1900 */
/*06a0*/ FFMA R28, R29, R28, R24 ; /* 0x0000001c1d1c7223 */
/* 0x004fc60000000018 */
/*06b0*/ LDG.E R29, [R14.64+0xc] ; /* 0x00000c040e1d7981 */
/* 0x000ea8000c1e1900 */
/*06c0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x0006a2000c1e1900 */
/*06d0*/ IMAD.WIDE R16, R25, 0x4, R18 ; /* 0x0000000419107825 */
/* 0x000fc800078e0212 */
/*06e0*/ FFMA R18, R27, R26, R28 ; /* 0x0000001a1b127223 */
/* 0x008fe2000000001c */
/*06f0*/ LDG.E R19, [R14.64+0x10] ; /* 0x000010040e137981 */
/* 0x000ee2000c1e1900 */
/*0700*/ IMAD.WIDE R26, R25, 0x4, R16 ; /* 0x00000004191a7825 */
/* 0x000fc600078e0210 */
/*0710*/ LDG.E R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x0002e6000c1e1900 */
/*0720*/ IMAD.WIDE R20, R25, 0x4, R26 ; /* 0x0000000419147825 */
/* 0x001fc800078e021a */
/*0730*/ FFMA R22, R22, R23, R18 ; /* 0x0000001716167223 */
/* 0x010fe20000000012 */
/*0740*/ LDG.E R17, [R14.64+0x14] ; /* 0x000014040e117981 */
/* 0x002f28000c1e1900 */
/*0750*/ LDG.E R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x000f22000c1e1900 */
/*0760*/ FFMA R18, R24, R29, R22 ; /* 0x0000001d18127223 */
/* 0x004fc60000000016 */
/*0770*/ LDG.E R29, [R14.64+0x18] ; /* 0x000018040e1d7981 */
/* 0x000ea8000c1e1900 */
/*0780*/ LDG.E R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x0006a2000c1e1900 */
/*0790*/ IMAD.WIDE R22, R25, 0x4, R20 ; /* 0x0000000419167825 */
/* 0x000fc800078e0214 */
/*07a0*/ FFMA R20, R28, R19, R18 ; /* 0x000000131c147223 */
/* 0x008fe20000000012 */
/*07b0*/ LDG.E R21, [R14.64+0x1c] ; /* 0x00001c040e157981 */
/* 0x000ee2000c1e1900 */
/*07c0*/ IMAD.WIDE R18, R25, 0x4, R22 ; /* 0x0000000419127825 */
/* 0x000fc600078e0216 */
/*07d0*/ LDG.E R28, [R22.64] ; /* 0x00000004161c7981 */
/* 0x0008e4000c1e1900 */
/*07e0*/ FFMA R22, R16, R17, R20 ; /* 0x0000001110167223 */
/* 0x010fe40000000014 */
/*07f0*/ LDG.E R23, [R14.64+0x20] ; /* 0x000020040e177981 */
/* 0x000f22000c1e1900 */
/*0800*/ IMAD.WIDE R16, R25, 0x4, R18 ; /* 0x0000000419107825 */
/* 0x000fc600078e0212 */
/*0810*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000128000c1e1900 */
/*0820*/ LDG.E R19, [R14.64+0x24] ; /* 0x000024040e137981 */
/* 0x001f62000c1e1900 */
/*0830*/ FFMA R29, R24, R29, R22 ; /* 0x0000001d181d7223 */
/* 0x004fc60000000016 */
/*0840*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000162000c1e1900 */
/*0850*/ IMAD.WIDE R26, R25, 0x4, R16 ; /* 0x00000004191a7825 */
/* 0x000fca00078e0210 */
/*0860*/ LDG.E R22, [R26.64] ; /* 0x000000041a167981 */
/* 0x0002a8000c1e1900 */
/*0870*/ LDG.E R17, [R14.64+0x28] ; /* 0x000028040e117981 */
/* 0x001ea2000c1e1900 */
/*0880*/ FFMA R21, R28, R21, R29 ; /* 0x000000151c157223 */
/* 0x008fe4000000001d */
/*0890*/ IMAD.WIDE R28, R25, 0x4, R26 ; /* 0x00000004191c7825 */
/* 0x000fe400078e021a */
/*08a0*/ LDG.E R26, [R14.64+0x2c] ; /* 0x00002c040e1a7981 */
/* 0x002ee8000c1e1900 */
/*08b0*/ LDG.E R27, [R14.64+0x30] ; /* 0x000030040e1b7981 */
/* 0x000ee2000c1e1900 */
/*08c0*/ FFMA R16, R20, R23, R21 ; /* 0x0000001714107223 */
/* 0x010fc60000000015 */
/*08d0*/ LDG.E R23, [R28.64] ; /* 0x000000041c177981 */
/* 0x0000e2000c1e1900 */
/*08e0*/ IMAD.WIDE R20, R25, 0x4, R28 ; /* 0x0000000419147825 */
/* 0x000fc600078e021c */
/*08f0*/ LDG.E R29, [R14.64+0x38] ; /* 0x000038040e1d7981 */
/* 0x001122000c1e1900 */
/*0900*/ FFMA R16, R24, R19, R16 ; /* 0x0000001318107223 */
/* 0x020fc60000000010 */
/*0910*/ LDG.E R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x000362000c1e1900 */
/*0920*/ IMAD.WIDE R18, R25, 0x4, R20 ; /* 0x0000000419127825 */
/* 0x000fc800078e0214 */
/*0930*/ FFMA R22, R22, R17, R16 ; /* 0x0000001116167223 */
/* 0x004fe40000000010 */
/*0940*/ IMAD.WIDE R16, R25, 0x4, R18 ; /* 0x0000000419107825 */
/* 0x000fe200078e0212 */
/*0950*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x0022a8000c1e1900 */
/*0960*/ LDG.E R21, [R14.64+0x3c] ; /* 0x00003c040e157981 */
/* 0x0000a8000c1e1900 */
/*0970*/ LDG.E R19, [R14.64+0x34] ; /* 0x000034040e137981 */
/* 0x0020a2000c1e1900 */
/*0980*/ FFMA R28, R23, R26, R22 ; /* 0x0000001a171c7223 */
/* 0x008fc40000000016 */
/*0990*/ IMAD.WIDE R22, R25, 0x4, R16 ; /* 0x0000000419167825 */
/* 0x000fe200078e0210 */
/*09a0*/ LDG.E R26, [R16.64] ; /* 0x00000004101a7981 */
/* 0x000326000c1e1900 */
/*09b0*/ FFMA R27, R24, R27, R28 ; /* 0x0000001b181b7223 */
/* 0x020fe4000000001c */
/*09c0*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x000ee2000c1e1900 */
/*09d0*/ IADD3 R11, R11, -0x10, RZ ; /* 0xfffffff00b0b7810 */
/* 0x000fc80007ffe0ff */
/*09e0*/ ISETP.GT.AND P2, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe40003f44270 */
/*09f0*/ IADD3 R18, P3, R14, 0x40, RZ ; /* 0x000000400e127810 */
/* 0x000fe20007f7e0ff */
/*0a00*/ IMAD.WIDE R16, R25, 0x4, R22 ; /* 0x0000000419107825 */
/* 0x002fe200078e0216 */
/*0a10*/ IADD3 R10, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fe40007ffe0ff */
/*0a20*/ MOV R14, R18 ; /* 0x00000012000e7202 */
/* 0x001fe20000000f00 */
/*0a30*/ FFMA R20, R20, R19, R27 ; /* 0x0000001314147223 */
/* 0x004fe4000000001b */
/*0a40*/ IMAD.X R19, RZ, RZ, R15, P3 ; /* 0x000000ffff137224 */
/* 0x000fc800018e060f */
/*0a50*/ IMAD.MOV.U32 R15, RZ, RZ, R19 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0013 */
/*0a60*/ FFMA R20, R26, R29, R20 ; /* 0x0000001d1a147223 */
/* 0x010fc80000000014 */
/*0a70*/ FFMA R24, R24, R21, R20 ; /* 0x0000001518187223 */
/* 0x008fe20000000014 */
/*0a80*/ @P2 BRA 0x600 ; /* 0xfffffb7000002947 */
/* 0x000fea000383ffff */
/*0a90*/ ISETP.GT.AND P2, PT, R11, 0x4, PT ; /* 0x000000040b00780c */
/* 0x000fda0003f44270 */
/*0aa0*/ @!P2 BRA 0xd30 ; /* 0x000002800000a947 */
/* 0x000fea0003800000 */
/*0ab0*/ MOV R25, c[0x0][0x178] ; /* 0x00005e0000197a02 */
/* 0x000fe20000000f00 */
/*0ac0*/ LDG.E R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x0000a8000c1e1900 */
/*0ad0*/ LDG.E R29, [R14.64] ; /* 0x000000040e1d7981 */
/* 0x000ea2000c1e1900 */
/*0ae0*/ IMAD.WIDE R18, R25, 0x4, R16 ; /* 0x0000000419127825 */
/* 0x000fc600078e0210 */
/*0af0*/ LDG.E R26, [R14.64+0x4] ; /* 0x000004040e1a7981 */
/* 0x000ee8000c1e1900 */
/*0b00*/ LDG.E R27, [R18.64] ; /* 0x00000004121b7981 */
/* 0x0002e2000c1e1900 */
/*0b10*/ IMAD.WIDE R20, R25, 0x4, R18 ; /* 0x0000000419147825 */
/* 0x000fcc00078e0212 */
/*0b20*/ IMAD.WIDE R22, R25.reuse, 0x4, R20 ; /* 0x0000000419167825 */
/* 0x040fe200078e0214 */
/*0b30*/ LDG.E R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x002328000c1e1900 */
/*0b40*/ LDG.E R19, [R14.64+0x8] ; /* 0x000008040e137981 */
/* 0x000f22000c1e1900 */
/*0b50*/ IMAD.WIDE R16, R25, 0x4, R22 ; /* 0x0000000419107825 */
/* 0x001fc600078e0216 */
/*0b60*/ LDG.E R21, [R14.64+0x10] ; /* 0x000010040e157981 */
/* 0x002f62000c1e1900 */
/*0b70*/ FFMA R28, R28, R29, R24 ; /* 0x0000001d1c1c7223 */
/* 0x004fc60000000018 */
/*0b80*/ LDG.E R29, [R14.64+0xc] ; /* 0x00000c040e1d7981 */
/* 0x000ea8000c1e1900 */
/*0b90*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0000a2000c1e1900 */
/*0ba0*/ FFMA R20, R27, R26, R28 ; /* 0x0000001a1b147223 */
/* 0x008fc6000000001c */
/*0bb0*/ LDG.E R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x000362000c1e1900 */
/*0bc0*/ IMAD.WIDE R26, R25, 0x4, R16 ; /* 0x00000004191a7825 */
/* 0x000fc600078e0210 */
/*0bd0*/ LDG.E R17, [R14.64+0x18] ; /* 0x000018040e117981 */
/* 0x002ee2000c1e1900 */
/*0be0*/ FFMA R16, R18, R19, R20 ; /* 0x0000001312107223 */
/* 0x010fe40000000014 */
/*0bf0*/ IMAD.WIDE R18, R25.reuse, 0x4, R26 ; /* 0x0000000419127825 */
/* 0x040fe200078e021a */
/*0c00*/ LDG.E R20, [R26.64] ; /* 0x000000041a147981 */
/* 0x000f2a000c1e1900 */
/*0c10*/ IMAD.WIDE R22, R25, 0x4, R18 ; /* 0x0000000419167825 */
/* 0x001fc800078e0212 */
/*0c20*/ FFMA R16, R24, R29, R16 ; /* 0x0000001d18107223 */
/* 0x004fe40000000010 */
/*0c30*/ LDG.E R29, [R14.64+0x14] ; /* 0x000014040e1d7981 */
/* 0x000f28000c1e1900 */
/*0c40*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000ee2000c1e1900 */
/*0c50*/ FFMA R16, R28, R21, R16 ; /* 0x000000151c107223 */
/* 0x020fc60000000010 */
/*0c60*/ LDG.E R28, [R14.64+0x1c] ; /* 0x00001c040e1c7981 */
/* 0x0000a8000c1e1900 */
/*0c70*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x000ea2000c1e1900 */
/*0c80*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0c90*/ IADD3 R10, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fe40007ffe0ff */
/*0ca0*/ IADD3 R11, R11, -0x8, RZ ; /* 0xfffffff80b0b7810 */
/* 0x000fe20007ffe0ff */
/*0cb0*/ FFMA R16, R20, R29, R16 ; /* 0x0000001d14107223 */
/* 0x010fe20000000010 */
/*0cc0*/ IADD3 R20, P2, R14, 0x20, RZ ; /* 0x000000200e147810 */
/* 0x000fc60007f5e0ff */
/*0cd0*/ FFMA R24, R24, R17, R16 ; /* 0x0000001118187223 */
/* 0x008fe40000000010 */
/*0ce0*/ IMAD.X R27, RZ, RZ, R15, P2 ; /* 0x000000ffff1b7224 */
/* 0x000fe200010e060f */
/*0cf0*/ MOV R14, R20 ; /* 0x00000014000e7202 */
/* 0x001fe20000000f00 */
/*0d00*/ IMAD.WIDE R16, R25, 0x4, R22 ; /* 0x0000000419107825 */
/* 0x000fc800078e0216 */
/*0d10*/ FFMA R24, R21, R28, R24 ; /* 0x0000001c15187223 */
/* 0x004fe40000000018 */
/*0d20*/ IMAD.MOV.U32 R15, RZ, RZ, R27 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e001b */
/*0d30*/ ISETP.NE.OR P0, PT, R11, RZ, P0 ; /* 0x000000ff0b00720c */
/* 0x000fda0000705670 */
/*0d40*/ @!P0 BRA 0xee0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0d50*/ LDG.E R26, [R16.64] ; /* 0x00000004101a7981 */
/* 0x0000a8000c1e1900 */
/*0d60*/ LDG.E R25, [R14.64] ; /* 0x000000040e197981 */
/* 0x000ea2000c1e1900 */
/*0d70*/ MOV R27, c[0x0][0x178] ; /* 0x00005e00001b7a02 */
/* 0x000fc60000000f00 */
/*0d80*/ LDG.E R29, [R14.64+0x4] ; /* 0x000004040e1d7981 */
/* 0x000ee4000c1e1900 */
/*0d90*/ IMAD.WIDE R22, R27.reuse, 0x4, R16 ; /* 0x000000041b167825 */
/* 0x040fe400078e0210 */
/*0da0*/ LDG.E R17, [R14.64+0x8] ; /* 0x000008040e117981 */
/* 0x001f28000c1e1900 */
/*0db0*/ IMAD.WIDE R20, R27.reuse, 0x4, R22 ; /* 0x000000041b147825 */
/* 0x040fe200078e0216 */
/*0dc0*/ LDG.E R28, [R22.64] ; /* 0x00000004161c7981 */
/* 0x0000e8000c1e1900 */
/*0dd0*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000f22000c1e1900 */
/*0de0*/ IMAD.WIDE R18, R27, 0x4, R20 ; /* 0x000000041b127825 */
/* 0x000fc800078e0214 */
/*0df0*/ FFMA R26, R26, R25, R24 ; /* 0x000000191a1a7223 */
/* 0x004fe40000000018 */
/*0e00*/ LDG.E R25, [R14.64+0xc] ; /* 0x00000c040e197981 */
/* 0x0002a8000c1e1900 */
/*0e10*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000ea2000c1e1900 */
/*0e20*/ IADD3 R11, R11, -0x4, RZ ; /* 0xfffffffc0b0b7810 */
/* 0x000fc80007ffe0ff */
/*0e30*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f05270 */
/*0e40*/ IADD3 R22, P2, R14, 0x10, RZ ; /* 0x000000100e167810 */
/* 0x001fe20007f5e0ff */
/*0e50*/ FFMA R26, R28, R29, R26 ; /* 0x0000001d1c1a7223 */
/* 0x008fc8000000001a */
/*0e60*/ FFMA R26, R16, R17, R26 ; /* 0x00000011101a7223 */
/* 0x010fe4000000001a */
/*0e70*/ IMAD.X R23, RZ, RZ, R15, P2 ; /* 0x000000ffff177224 */
/* 0x000fe200010e060f */
/*0e80*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe20007ffe0ff */
/*0e90*/ IMAD.WIDE R16, R27, 0x4, R18 ; /* 0x000000041b107825 */
/* 0x000fe200078e0212 */
/*0ea0*/ MOV R14, R22 ; /* 0x00000016000e7202 */
/* 0x002fc60000000f00 */
/*0eb0*/ IMAD.MOV.U32 R15, RZ, RZ, R23 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0017 */
/*0ec0*/ FFMA R24, R24, R25, R26 ; /* 0x0000001918187223 */
/* 0x004fe2000000001a */
/*0ed0*/ @P0 BRA 0xd50 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ee0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ef0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe200078e00ff */
/*0f00*/ IADD3 R14, R7, R8, RZ ; /* 0x00000008070e7210 */
/* 0x000fca0007ffe0ff */
/*0f10*/ IMAD.WIDE R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fcc00078e020f */
/*0f20*/ @!P0 BRA 0x1080 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*0f30*/ IADD3 R11, R7, R10, RZ ; /* 0x0000000a070b7210 */
/* 0x000fe20007ffe0ff */
/*0f40*/ IMAD.MOV.U32 R22, RZ, RZ, 0x4 ; /* 0x00000004ff167424 */
/* 0x000fe400078e00ff */
/*0f50*/ IMAD R19, R10, c[0x0][0x178], R8 ; /* 0x00005e000a137a24 */
/* 0x000fe400078e0208 */
/*0f60*/ IMAD.WIDE R10, R11, R22, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fc800078e0216 */
/*0f70*/ IMAD.WIDE R16, R19, R22, c[0x0][0x170] ; /* 0x00005c0013107625 */
/* 0x000fe200078e0216 */
/*0f80*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000eaa000c1e1900 */
/*0f90*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ea2000c1e1900 */
/*0fa0*/ ISETP.NE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe20003f05270 */
/*0fb0*/ FFMA R24, R17, R18, R24 ; /* 0x0000001211187223 */
/* 0x004fd80000000018 */
/*0fc0*/ @!P0 BRA 0x1080 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0fd0*/ ISETP.NE.AND P0, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe20003f05270 */
/*0fe0*/ LDG.E R20, [R10.64+0x4] ; /* 0x000004040a147981 */
/* 0x000ea2000c1e1900 */
/*0ff0*/ IADD3 R19, R19, c[0x0][0x178], RZ ; /* 0x00005e0013137a10 */
/* 0x000fd60007ffe0ff */
/*1000*/ @P0 IADD3 R16, R19.reuse, c[0x0][0x178], RZ ; /* 0x00005e0013100a10 */
/* 0x040fe20007ffe0ff */
/*1010*/ IMAD.WIDE R18, R19, R22.reuse, c[0x0][0x170] ; /* 0x00005c0013127625 */
/* 0x080fe200078e0216 */
/*1020*/ @P0 LDG.E R21, [R10.64+0x8] ; /* 0x000008040a150981 */
/* 0x000ee6000c1e1900 */
/*1030*/ @P0 IMAD.WIDE R16, R16, R22, c[0x0][0x170] ; /* 0x00005c0010100625 */
/* 0x000fe400078e0216 */
/*1040*/ LDG.E R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x000ea8000c1e1900 */
/*1050*/ @P0 LDG.E R17, [R16.64] ; /* 0x0000000410110981 */
/* 0x000ee2000c1e1900 */
/*1060*/ FFMA R24, R19, R20, R24 ; /* 0x0000001413187223 */
/* 0x004fc80000000018 */
/*1070*/ @P0 FFMA R24, R17, R21, R24 ; /* 0x0000001511180223 */
/* 0x008fca0000000018 */
/*1080*/ STG.E [R14.64], R24 ; /* 0x000000180e007986 */
/* 0x0001e4000c101904 */
/*1090*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*10a0*/ ISETP.GE.AND P0, PT, R8.reuse, R2, PT ; /* 0x000000020800720c */
/* 0x040fe40003f06270 */
/*10b0*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe40007ffe0ff */
/*10c0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fd20007ffe0ff */
/*10d0*/ @!P0 BRA 0x4b0 ; /* 0xfffff3d000008947 */
/* 0x000fea000383ffff */
/*10e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*10f0*/ ISETP.GE.AND P0, PT, R3.reuse, R4, PT ; /* 0x000000040300720c */
/* 0x040fe40003f06270 */
/*1100*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fd60007ffe0ff */
/*1110*/ @!P0 BRA 0x450 ; /* 0xfffff33000008947 */
/* 0x000fea000383ffff */
/*1120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1130*/ BRA 0x1130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14matrixMulCUDA2PfS_S_i
.globl _Z14matrixMulCUDA2PfS_S_i
.p2align 8
.type _Z14matrixMulCUDA2PfS_S_i,@function
_Z14matrixMulCUDA2PfS_S_i:
s_clause 0x2
s_load_b32 s8, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b32_e32 v1, 4, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v7, 0x3ff0, v1
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v10, 4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v8, 15, v7
v_or_b32_e32 v9, 15, v10
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v2, v0, s8
s_cmp_gt_i32 s8, 0
s_cselect_b32 s1, -1, 0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 4, v2
s_branch .LBB0_2
.LBB0_1:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v0, 1, v10
v_cmp_eq_u32_e32 vcc_lo, v10, v9
v_add_nc_u32_e32 v2, s8, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v10, v0
s_or_b32 s9, vcc_lo, s9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execz .LBB0_9
.LBB0_2:
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v12, v7
v_mul_lo_u32 v11, v10, s8
v_cmp_gt_i32_e64 s0, s8, v10
s_mov_b32 s10, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_3:
v_add_nc_u32_e32 v5, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_store_b32 v[5:6], v13, off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v0, 1, v12
v_cmp_eq_u32_e32 vcc_lo, v12, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v12, v0
s_or_b32 s10, vcc_lo, s10
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB0_1
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s8, v12
s_and_b32 s12, s0, vcc_lo
s_and_saveexec_b32 s11, s12
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v13, 0
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_3
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
v_mov_b32_e32 v0, v12
s_mov_b32 s12, s8
.p2align 6
.LBB0_8:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[14:15], 2, v[0:1]
s_add_i32 s12, s12, -1
s_cmp_eq_u32 s12, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v14, vcc_lo, s2, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
global_load_b32 v16, v[5:6], off
global_load_b32 v14, v[14:15], off
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_nc_u32_e32 v0, s8, v0
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v13, v16, v14
s_cbranch_scc0 .LBB0_8
s_branch .LBB0_3
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14matrixMulCUDA2PfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 13
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14matrixMulCUDA2PfS_S_i, .Lfunc_end0-_Z14matrixMulCUDA2PfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14matrixMulCUDA2PfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 15
.sgpr_spill_count: 0
.symbol: _Z14matrixMulCUDA2PfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c59e0_00000000-6_matrixMulCUDA2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14matrixMulCUDA2PfS_S_iPfS_S_i
.type _Z39__device_stub__Z14matrixMulCUDA2PfS_S_iPfS_S_i, @function
_Z39__device_stub__Z14matrixMulCUDA2PfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14matrixMulCUDA2PfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z14matrixMulCUDA2PfS_S_iPfS_S_i, .-_Z39__device_stub__Z14matrixMulCUDA2PfS_S_iPfS_S_i
.globl _Z14matrixMulCUDA2PfS_S_i
.type _Z14matrixMulCUDA2PfS_S_i, @function
_Z14matrixMulCUDA2PfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14matrixMulCUDA2PfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14matrixMulCUDA2PfS_S_i, .-_Z14matrixMulCUDA2PfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14matrixMulCUDA2PfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14matrixMulCUDA2PfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixMulCUDA2.hip"
.globl _Z29__device_stub__matrixMulCUDA2PfS_S_i # -- Begin function _Z29__device_stub__matrixMulCUDA2PfS_S_i
.p2align 4, 0x90
.type _Z29__device_stub__matrixMulCUDA2PfS_S_i,@function
_Z29__device_stub__matrixMulCUDA2PfS_S_i: # @_Z29__device_stub__matrixMulCUDA2PfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14matrixMulCUDA2PfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__matrixMulCUDA2PfS_S_i, .Lfunc_end0-_Z29__device_stub__matrixMulCUDA2PfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14matrixMulCUDA2PfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14matrixMulCUDA2PfS_S_i,@object # @_Z14matrixMulCUDA2PfS_S_i
.section .rodata,"a",@progbits
.globl _Z14matrixMulCUDA2PfS_S_i
.p2align 3, 0x0
_Z14matrixMulCUDA2PfS_S_i:
.quad _Z29__device_stub__matrixMulCUDA2PfS_S_i
.size _Z14matrixMulCUDA2PfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14matrixMulCUDA2PfS_S_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__matrixMulCUDA2PfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14matrixMulCUDA2PfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void kernel(float *a) {
int i = gridDim.x;
a[i] = i;
} | code for sm_80
Function : _Z6kernelPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ I2F R5, c[0x0][0xc] ; /* 0x0000030000057b06 */
/* 0x000e220000201400 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R2, c[0x0][0xc] ; /* 0x0000030000027a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0050*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void kernel(float *a) {
int i = gridDim.x;
a[i] = i;
} | .file "tmpxft_0012df45_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z6kernelPfPf
.type _Z25__device_stub__Z6kernelPfPf, @function
_Z25__device_stub__Z6kernelPfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z6kernelPfPf, .-_Z25__device_stub__Z6kernelPfPf
.globl _Z6kernelPf
.type _Z6kernelPf, @function
_Z6kernelPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6kernelPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kernelPf, .-_Z6kernelPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void kernel(float *a) {
int i = gridDim.x;
a[i] = i;
} | #include <hip/hip_runtime.h>
__global__ void kernel(float *a) {
int i = gridDim.x;
a[i] = i;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void kernel(float *a) {
int i = gridDim.x;
a[i] = i;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPf
.globl _Z6kernelPf
.p2align 8
.type _Z6kernelPf,@function
_Z6kernelPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s2, 31
v_cvt_f32_i32_e32 v0, s2
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPf, .Lfunc_end0-_Z6kernelPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPf
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z6kernelPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void kernel(float *a) {
int i = gridDim.x;
a[i] = i;
} | .text
.file "kernel.hip"
.globl _Z21__device_stub__kernelPf # -- Begin function _Z21__device_stub__kernelPf
.p2align 4, 0x90
.type _Z21__device_stub__kernelPf,@function
_Z21__device_stub__kernelPf: # @_Z21__device_stub__kernelPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6kernelPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPf, .Lfunc_end0-_Z21__device_stub__kernelPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPf,@object # @_Z6kernelPf
.section .rodata,"a",@progbits
.globl _Z6kernelPf
.p2align 3, 0x0
_Z6kernelPf:
.quad _Z21__device_stub__kernelPf
.size _Z6kernelPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPf"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ I2F R5, c[0x0][0xc] ; /* 0x0000030000057b06 */
/* 0x000e220000201400 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R2, c[0x0][0xc] ; /* 0x0000030000027a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0050*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPf
.globl _Z6kernelPf
.p2align 8
.type _Z6kernelPf,@function
_Z6kernelPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s2, 31
v_cvt_f32_i32_e32 v0, s2
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPf, .Lfunc_end0-_Z6kernelPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPf
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z6kernelPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012df45_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z6kernelPfPf
.type _Z25__device_stub__Z6kernelPfPf, @function
_Z25__device_stub__Z6kernelPfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z6kernelPfPf, .-_Z25__device_stub__Z6kernelPfPf
.globl _Z6kernelPf
.type _Z6kernelPf, @function
_Z6kernelPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6kernelPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kernelPf, .-_Z6kernelPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z21__device_stub__kernelPf # -- Begin function _Z21__device_stub__kernelPf
.p2align 4, 0x90
.type _Z21__device_stub__kernelPf,@function
_Z21__device_stub__kernelPf: # @_Z21__device_stub__kernelPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6kernelPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPf, .Lfunc_end0-_Z21__device_stub__kernelPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPf,@object # @_Z6kernelPf
.section .rodata,"a",@progbits
.globl _Z6kernelPf
.p2align 3, 0x0
_Z6kernelPf:
.quad _Z21__device_stub__kernelPf
.size _Z6kernelPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPf"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void matrixMultiply2(float* A, float* C, int size)
{
float sum = 0;
int Col = blockIdx.x * TILE_WIDTH + threadIdx.x;
int Row = blockIdx.y * TILE_WIDTH + threadIdx.y;
if(Col < size && Row < size) {
for (int k = 0; k < size; k++)
sum += A[k * size + Row] * A[k * size + Col];
C[Row * size + Col] = sum;
}
} | code for sm_80
Function : _Z15matrixMultiply2PfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e620000002100 */
/*0050*/ LEA R7, R3, R4, 0x5 ; /* 0x0000000403077211 */
/* 0x001fc800078e28ff */
/*0060*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fe40003f06270 */
/*0070*/ LEA R8, R5, R6, 0x5 ; /* 0x0000000605087211 */
/* 0x002fc800078e28ff */
/*0080*/ ISETP.GE.OR P0, PT, R8, c[0x0][0x170], P0 ; /* 0x00005c0008007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R9, c[0x0][0x170] ; /* 0x00005c0000097a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R14, -RZ, RZ, 0, 0 ; /* 0x00000000ff0e7435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xcd0 ; /* 0x00000be000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R0, R9.reuse, -0x1, RZ ; /* 0xffffffff09007810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R10, R9, 0x3, RZ, 0xc0, !PT ; /* 0x00000003090a7812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R14, RZ ; /* 0x000000ff000e7202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xbc0 ; /* 0x00000a7000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R0, -R10, c[0x0][0x170], RZ ; /* 0x00005c000a007a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R28, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff1c7435 */
/* 0x000fe200000001ff */
/*0170*/ MOV R14, RZ ; /* 0x000000ff000e7202 */
/* 0x000fe20000000f00 */
/*0180*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f04270 */
/*01a0*/ IMAD.WIDE R20, R7, R28, c[0x0][0x160] ; /* 0x0000580007147625 */
/* 0x000fc800078e021c */
/*01b0*/ IMAD.WIDE R28, R8, R28, c[0x0][0x160] ; /* 0x00005800081c7625 */
/* 0x000fe400078e021c */
/*01c0*/ @!P0 BRA 0xa40 ; /* 0x0000087000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R0, 0xc, PT ; /* 0x0000000c0000780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x750 ; /* 0x0000055000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ IMAD.WIDE R18, R9.reuse, 0x4, R28 ; /* 0x0000000409127825 */
/* 0x040fe200078e021c */
/*0220*/ LDG.E R16, [R28.64] ; /* 0x000000041c107981 */
/* 0x0000a6000c1e1900 */
/*0230*/ IMAD.WIDE R26, R9.reuse, 0x4, R20 ; /* 0x00000004091a7825 */
/* 0x040fe200078e0214 */
/*0240*/ LDG.E R17, [R20.64] ; /* 0x0000000414117981 */
/* 0x0002a8000c1e1900 */
/*0250*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000722000c1e1900 */
/*0260*/ IMAD.WIDE R24, R9, 0x4, R26 ; /* 0x0000000409187825 */
/* 0x000fc600078e021a */
/*0270*/ LDG.E R13, [R26.64] ; /* 0x000000041a0d7981 */
/* 0x000b28000c1e1900 */
/*0280*/ LDG.E R20, [R24.64] ; /* 0x0000000418147981 */
/* 0x002322000c1e1900 */
/*0290*/ IMAD.WIDE R18, R9, 0x4, R18 ; /* 0x0000000409127825 */
/* 0x008fca00078e0212 */
/*02a0*/ LDG.E R15, [R18.64] ; /* 0x00000004120f7981 */
/* 0x000722000c1e1900 */
/*02b0*/ IMAD.WIDE R22, R9, 0x4, R18 ; /* 0x0000000409167825 */
/* 0x000fc800078e0212 */
/*02c0*/ IMAD.WIDE R24, R9.reuse, 0x4, R24 ; /* 0x0000000409187825 */
/* 0x042fe200078e0218 */
/*02d0*/ LDG.E R28, [R22.64] ; /* 0x00000004161c7981 */
/* 0x001128000c1e1900 */
/*02e0*/ LDG.E R11, [R24.64] ; /* 0x00000004180b7981 */
/* 0x000322000c1e1900 */
/*02f0*/ IMAD.WIDE R18, R9, 0x4, R24 ; /* 0x0000000409127825 */
/* 0x008fc800078e0218 */
/*0300*/ IMAD.WIDE R22, R9.reuse, 0x4, R22 ; /* 0x0000000409167825 */
/* 0x041fe200078e0216 */
/*0310*/ LDG.E R27, [R18.64] ; /* 0x00000004121b7981 */
/* 0x0200e8000c1e1900 */
/*0320*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000ae2000c1e1900 */
/*0330*/ IMAD.WIDE R18, R9, 0x4, R18 ; /* 0x0000000409127825 */
/* 0x001fc800078e0212 */
/*0340*/ IMAD.WIDE R22, R9, 0x4, R22 ; /* 0x0000000409167825 */
/* 0x020fe200078e0216 */
/*0350*/ LDG.E R21, [R18.64] ; /* 0x0000000412157981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x002362000c1e1900 */
/*0370*/ FFMA R16, R16, R17, R14 ; /* 0x0000001110107223 */
/* 0x004fc8000000000e */
/*0380*/ FFMA R14, R12, R13, R16 ; /* 0x0000000d0c0e7223 */
/* 0x010fe40000000010 */
/*0390*/ IMAD.WIDE R12, R9, 0x4, R22 ; /* 0x00000004090c7825 */
/* 0x000fc800078e0216 */
/*03a0*/ IMAD.WIDE R16, R9, 0x4, R18 ; /* 0x0000000409107825 */
/* 0x000fc800078e0212 */
/*03b0*/ FFMA R29, R15, R20, R14 ; /* 0x000000140f1d7223 */
/* 0x000fe2000000000e */
/*03c0*/ LDG.E R25, [R16.64] ; /* 0x0000000410197981 */
/* 0x000522000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R9, 0x4, R12 ; /* 0x00000004090e7825 */
/* 0x000fc600078e020c */
/*03e0*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000122000c1e1900 */
/*03f0*/ IMAD.WIDE R16, R9, 0x4, R16 ; /* 0x0000000409107825 */
/* 0x004fc800078e0210 */
/*0400*/ IMAD.WIDE R12, R9.reuse, 0x4, R14 ; /* 0x00000004090c7825 */
/* 0x041fe400078e020e */
/*0410*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0420*/ FFMA R28, R28, R11, R29 ; /* 0x0000000b1c1c7223 */
/* 0x000fe4000000001d */
/*0430*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x0000a2000c1e1900 */
/*0440*/ IMAD.WIDE R18, R9, 0x4, R16 ; /* 0x0000000409127825 */
/* 0x000fc600078e0210 */
/*0450*/ LDG.E R29, [R12.64] ; /* 0x000000040c1d7981 */
/* 0x0000a2000c1e1900 */
/*0460*/ IMAD.WIDE R22, R9, 0x4, R12 ; /* 0x0000000409167825 */
/* 0x002fc600078e020c */
/*0470*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x0010a2000c1e1900 */
/*0480*/ FFMA R15, R26, R27, R28 ; /* 0x0000001b1a0f7223 */
/* 0x008fc6000000001c */
/*0490*/ LDG.E R13, [R22.64] ; /* 0x00000004160d7981 */
/* 0x0002e2000c1e1900 */
/*04a0*/ IMAD.WIDE R18, R9, 0x4, R18 ; /* 0x0000000409127825 */
/* 0x001fca00078e0212 */
/*04b0*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x0000e2000c1e1900 */
/*04c0*/ IMAD.WIDE R26, R9, 0x4, R22 ; /* 0x00000004091a7825 */
/* 0x000fc800078e0216 */
/*04d0*/ IMAD.WIDE R16, R9.reuse, 0x4, R18 ; /* 0x0000000409107825 */
/* 0x040fe200078e0212 */
/*04e0*/ LDG.E R22, [R26.64] ; /* 0x000000041a167981 */
/* 0x0022e6000c1e1900 */
/*04f0*/ FFMA R21, R24, R21, R15 ; /* 0x0000001518157223 */
/* 0x020fe4000000000f */
/*0500*/ LDG.E R15, [R16.64] ; /* 0x00000004100f7981 */
/* 0x000ae4000c1e1900 */
/*0510*/ FFMA R23, R20, R25, R21 ; /* 0x0000001914177223 */
/* 0x010fe40000000015 */
/*0520*/ IMAD.WIDE R20, R9, 0x4, R16 ; /* 0x0000000409147825 */
/* 0x000fc800078e0210 */
/*0530*/ IMAD.WIDE R24, R9.reuse, 0x4, R26 ; /* 0x0000000409187825 */
/* 0x040fe200078e021a */
/*0540*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x02096a000c1e1900 */
/*0550*/ IMAD.WIDE R18, R9, 0x4, R24 ; /* 0x0000000409127825 */
/* 0x001fe400078e0218 */
/*0560*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000164000c1e1900 */
/*0570*/ FFMA R11, R14, R11, R23 ; /* 0x0000000b0e0b7223 */
/* 0x004fc40000000017 */
/*0580*/ IMAD.WIDE R20, R9, 0x4, R20 ; /* 0x0000000409147825 */
/* 0x010fca00078e0214 */
/*0590*/ LDG.E R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x000522000c1e1900 */
/*05a0*/ IMAD.WIDE R26, R9, 0x4, R20 ; /* 0x00000004091a7825 */
/* 0x002fc800078e0214 */
/*05b0*/ FFMA R12, R29, R12, R11 ; /* 0x0000000c1d0c7223 */
/* 0x000fe4000000000b */
/*05c0*/ LDG.E R11, [R18.64] ; /* 0x00000004120b7981 */
/* 0x000324000c1e1900 */
/*05d0*/ IMAD.WIDE R18, R9, 0x4, R18 ; /* 0x0000000409127825 */
/* 0x002fc800078e0212 */
/*05e0*/ FFMA R23, R13, R28, R12 ; /* 0x0000001c0d177223 */
/* 0x008fe2000000000c */
/*05f0*/ LDG.E R17, [R18.64] ; /* 0x0000000412117981 */
/* 0x000ee2000c1e1900 */
/*0600*/ IMAD.WIDE R12, R9, 0x4, R26 ; /* 0x00000004090c7825 */
/* 0x000fc600078e021a */
/*0610*/ LDG.E R26, [R26.64] ; /* 0x000000041a1a7981 */
/* 0x000ee2000c1e1900 */
/*0620*/ IMAD.WIDE R28, R9, 0x4, R18 ; /* 0x00000004091c7825 */
/* 0x000fc600078e0212 */
/*0630*/ LDG.E R24, [R12.64] ; /* 0x000000040c187981 */
/* 0x0010e8000c1e1900 */
/*0640*/ LDG.E R21, [R28.64] ; /* 0x000000041c157981 */
/* 0x0042a2000c1e1900 */
/*0650*/ FFMA R15, R22, R15, R23 ; /* 0x0000000f160f7223 */
/* 0x000fe40000000017 */
/*0660*/ IMAD.WIDE R12, R9, 0x4, R12 ; /* 0x00000004090c7825 */
/* 0x001fc800078e020c */
/*0670*/ IMAD.WIDE R28, R9, 0x4, R28 ; /* 0x00000004091c7825 */
/* 0x002fe200078e021c */
/*0680*/ LDG.E R22, [R12.64] ; /* 0x000000040c167981 */
/* 0x000ea8000c1e1900 */
/*0690*/ LDG.E R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x0000a2000c1e1900 */
/*06a0*/ IADD3 R0, R0, -0x10, RZ ; /* 0xfffffff000007810 */
/* 0x000fc80007ffe0ff */
/*06b0*/ ISETP.GT.AND P1, PT, R0, 0xc, PT ; /* 0x0000000c0000780c */
/* 0x000fe40003f24270 */
/*06c0*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*06d0*/ IMAD.WIDE R28, R9, 0x4, R28 ; /* 0x00000004091c7825 */
/* 0x001fc800078e021c */
/*06e0*/ FFMA R15, R25, R16, R15 ; /* 0x00000010190f7223 */
/* 0x020fc8000000000f */
/*06f0*/ FFMA R11, R11, R14, R15 ; /* 0x0000000e0b0b7223 */
/* 0x010fc8000000000f */
/*0700*/ FFMA R11, R17, R26, R11 ; /* 0x0000001a110b7223 */
/* 0x008fc8000000000b */
/*0710*/ FFMA R11, R21, R24, R11 ; /* 0x00000018150b7223 */
/* 0x004fc8000000000b */
/*0720*/ FFMA R14, R20, R22, R11 ; /* 0x00000016140e7223 */
/* 0x000fe4000000000b */
/*0730*/ IMAD.WIDE R20, R9, 0x4, R12 ; /* 0x0000000409147825 */
/* 0x000fe200078e020c */
/*0740*/ @P1 BRA 0x210 ; /* 0xfffffac000001947 */
/* 0x000fea000383ffff */
/*0750*/ ISETP.GT.AND P1, PT, R0, 0x4, PT ; /* 0x000000040000780c */
/* 0x000fda0003f24270 */
/*0760*/ @!P1 BRA 0xa20 ; /* 0x000002b000009947 */
/* 0x000fea0003800000 */
/*0770*/ LDG.E R15, [R28.64] ; /* 0x000000041c0f7981 */
/* 0x0000a2000c1e1900 */
/*0780*/ IMAD.WIDE R16, R9, 0x4, R28 ; /* 0x0000000409107825 */
/* 0x000fc600078e021c */
/*0790*/ LDG.E R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x0002a2000c1e1900 */
/*07a0*/ IMAD.WIDE R24, R9, 0x4, R20 ; /* 0x0000000409187825 */
/* 0x000fc600078e0214 */
/*07b0*/ LDG.E R19, [R16.64] ; /* 0x0000000410137981 */
/* 0x000728000c1e1900 */
/*07c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x001122000c1e1900 */
/*07d0*/ IMAD.WIDE R22, R9, 0x4, R16 ; /* 0x0000000409167825 */
/* 0x000fc800078e0210 */
/*07e0*/ IMAD.WIDE R12, R9.reuse, 0x4, R24 ; /* 0x00000004090c7825 */
/* 0x040fe200078e0218 */
/*07f0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000b28000c1e1900 */
/*0800*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000122000c1e1900 */
/*0810*/ IMAD.WIDE R20, R9, 0x4, R12 ; /* 0x0000000409147825 */
/* 0x002fc800078e020c */
/*0820*/ IMAD.WIDE R22, R9, 0x4, R22 ; /* 0x0000000409167825 */
/* 0x020fc800078e0216 */
/*0830*/ IMAD.WIDE R12, R9.reuse, 0x4, R20 ; /* 0x00000004090c7825 */
/* 0x041fe200078e0214 */
/*0840*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x000166000c1e1900 */
/*0850*/ IMAD.WIDE R16, R9.reuse, 0x4, R22 ; /* 0x0000000409107825 */
/* 0x048fe200078e0216 */
/*0860*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000368000c1e1900 */
/*0870*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000768000c1e1900 */
/*0880*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x000162000c1e1900 */
/*0890*/ IMAD.WIDE R16, R9, 0x4, R16 ; /* 0x0000000409107825 */
/* 0x008fca00078e0210 */
/*08a0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x002ee2000c1e1900 */
/*08b0*/ FFMA R18, R15, R18, R14 ; /* 0x000000120f127223 */
/* 0x004fe4000000000e */
/*08c0*/ IMAD.WIDE R14, R9, 0x4, R12 ; /* 0x00000004090e7825 */
/* 0x000fc800078e020c */
/*08d0*/ FFMA R28, R19, R28, R18 ; /* 0x0000001c131c7223 */
/* 0x010fe40000000012 */
/*08e0*/ IMAD.WIDE R12, R9.reuse, 0x4, R14 ; /* 0x00000004090c7825 */
/* 0x041fe400078e020e */
/*08f0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e4000c1e1900 */
/*0900*/ IMAD.WIDE R18, R9.reuse, 0x4, R16 ; /* 0x0000000409127825 */
/* 0x040fe400078e0210 */
/*0910*/ LDG.E R29, [R12.64] ; /* 0x000000040c1d7981 */
/* 0x000ea4000c1e1900 */
/*0920*/ IMAD.WIDE R22, R9, 0x4, R12 ; /* 0x0000000409167825 */
/* 0x000fc400078e020c */
/*0930*/ LDG.E R15, [R18.64] ; /* 0x00000004120f7981 */
/* 0x0010a4000c1e1900 */
/*0940*/ FFMA R26, R26, R27, R28 ; /* 0x0000001b1a1a7223 */
/* 0x000fe4000000001c */
/*0950*/ LDG.E R27, [R22.64] ; /* 0x00000004161b7981 */
/* 0x000f22000c1e1900 */
/*0960*/ IMAD.WIDE R18, R9, 0x4, R18 ; /* 0x0000000409127825 */
/* 0x001fca00078e0212 */
/*0970*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x000f22000c1e1900 */
/*0980*/ FFMA R11, R11, R20, R26 ; /* 0x000000140b0b7223 */
/* 0x020fc8000000001a */
/*0990*/ FFMA R11, R24, R25, R11 ; /* 0x00000019180b7223 */
/* 0x000fe2000000000b */
/*09a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*09b0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*09c0*/ IADD3 R0, R0, -0x8, RZ ; /* 0xfffffff800007810 */
/* 0x000fe20007ffe0ff */
/*09d0*/ FFMA R16, R21, R14, R11 ; /* 0x0000000e15107223 */
/* 0x008fe4000000000b */
/*09e0*/ IMAD.WIDE R20, R9, 0x4, R22 ; /* 0x0000000409147825 */
/* 0x000fc800078e0216 */
/*09f0*/ FFMA R15, R15, R29, R16 ; /* 0x0000001d0f0f7223 */
/* 0x004fc80000000010 */
/*0a00*/ FFMA R14, R28, R27, R15 ; /* 0x0000001b1c0e7223 */
/* 0x010fe4000000000f */
/*0a10*/ IMAD.WIDE R28, R9, 0x4, R18 ; /* 0x00000004091c7825 */
/* 0x000fc800078e0212 */
/*0a20*/ ISETP.NE.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000705670 */
/*0a30*/ @!P0 BRA 0xbc0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0a40*/ IMAD.WIDE R16, R9.reuse, 0x4, R20 ; /* 0x0000000409107825 */
/* 0x040fe400078e0214 */
/*0a50*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea4000c1e1900 */
/*0a60*/ IMAD.WIDE R12, R9.reuse, 0x4, R28 ; /* 0x00000004090c7825 */
/* 0x040fe400078e021c */
/*0a70*/ LDG.E R29, [R28.64] ; /* 0x000000041c1d7981 */
/* 0x0000a4000c1e1900 */
/*0a80*/ IMAD.WIDE R22, R9.reuse, 0x4, R16 ; /* 0x0000000409167825 */
/* 0x040fe400078e0210 */
/*0a90*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee4000c1e1900 */
/*0aa0*/ IMAD.WIDE R18, R9, 0x4, R12 ; /* 0x0000000409127825 */
/* 0x000fc400078e020c */
/*0ab0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x0002e4000c1e1900 */
/*0ac0*/ IMAD.WIDE R24, R9.reuse, 0x4, R22 ; /* 0x0000000409187825 */
/* 0x040fe400078e0216 */
/*0ad0*/ LDG.E R15, [R22.64] ; /* 0x00000004160f7981 */
/* 0x000f24000c1e1900 */
/*0ae0*/ IMAD.WIDE R26, R9, 0x4, R18 ; /* 0x00000004091a7825 */
/* 0x000fe400078e0212 */
/*0af0*/ LDG.E R11, [R18.64] ; /* 0x00000004120b7981 */
/* 0x000f28000c1e1900 */
/*0b00*/ LDG.E R13, [R24.64] ; /* 0x00000004180d7981 */
/* 0x002f68000c1e1900 */
/*0b10*/ LDG.E R28, [R26.64] ; /* 0x000000041a1c7981 */
/* 0x001f62000c1e1900 */
/*0b20*/ IADD3 R0, R0, -0x4, RZ ; /* 0xfffffffc00007810 */
/* 0x000fc80007ffe0ff */
/*0b30*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0b40*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fe20007ffe0ff */
/*0b50*/ FFMA R29, R29, R20, R14 ; /* 0x000000141d1d7223 */
/* 0x004fc8000000000e */
/*0b60*/ FFMA R29, R12, R16, R29 ; /* 0x000000100c1d7223 */
/* 0x008fe4000000001d */
/*0b70*/ IMAD.WIDE R20, R9, 0x4, R24 ; /* 0x0000000409147825 */
/* 0x000fc800078e0218 */
/*0b80*/ FFMA R11, R11, R15, R29 ; /* 0x0000000f0b0b7223 */
/* 0x010fc8000000001d */
/*0b90*/ FFMA R14, R28, R13, R11 ; /* 0x0000000d1c0e7223 */
/* 0x020fe4000000000b */
/*0ba0*/ IMAD.WIDE R28, R9, 0x4, R26 ; /* 0x00000004091c7825 */
/* 0x000fe200078e021a */
/*0bb0*/ @P0 BRA 0xa40 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0bc0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05270 */
/*0bd0*/ @!P0 BRA 0xcd0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0be0*/ IMAD R6, R2.reuse, c[0x0][0x170], R6 ; /* 0x00005c0002067a24 */
/* 0x040fe200078e0206 */
/*0bf0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0c00*/ IMAD R2, R2, c[0x0][0x170], R4 ; /* 0x00005c0002027a24 */
/* 0x000fc600078e0204 */
/*0c10*/ LEA R6, R5, R6, 0x5 ; /* 0x0000000605067211 */
/* 0x000fe400078e28ff */
/*0c20*/ LEA R4, R3, R2, 0x5 ; /* 0x0000000203047211 */
/* 0x000fc800078e28ff */
/*0c30*/ IMAD.WIDE R2, R6, R11, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e020b */
/*0c40*/ IMAD.WIDE R4, R4, R11, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e020b */
/*0c50*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x0000a8000c1e1900 */
/*0c60*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x0002a2000c1e1900 */
/*0c70*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x000fc80007ffe0ff */
/*0c80*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*0c90*/ IMAD.WIDE R2, R9, 0x4, R2 ; /* 0x0000000409027825 */
/* 0x001fc800078e0202 */
/*0ca0*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x002fc800078e0204 */
/*0cb0*/ FFMA R14, R11, R0, R14 ; /* 0x000000000b0e7223 */
/* 0x004fc8000000000e */
/*0cc0*/ @P0 BRA 0xc50 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0cd0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*0ce0*/ IMAD R2, R7, c[0x0][0x170], R8 ; /* 0x00005c0007027a24 */
/* 0x000fc800078e0208 */
/*0cf0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*0d00*/ STG.E [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x000fe2000c101904 */
/*0d10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d20*/ BRA 0xd20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void matrixMultiply2(float* A, float* C, int size)
{
float sum = 0;
int Col = blockIdx.x * TILE_WIDTH + threadIdx.x;
int Row = blockIdx.y * TILE_WIDTH + threadIdx.y;
if(Col < size && Row < size) {
for (int k = 0; k < size; k++)
sum += A[k * size + Row] * A[k * size + Col];
C[Row * size + Col] = sum;
}
} | .file "tmpxft_0015c204_00000000-6_matrixMultiply2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i
.type _Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i, @function
_Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixMultiply2PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i, .-_Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i
.globl _Z15matrixMultiply2PfS_i
.type _Z15matrixMultiply2PfS_i, @function
_Z15matrixMultiply2PfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15matrixMultiply2PfS_i, .-_Z15matrixMultiply2PfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15matrixMultiply2PfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixMultiply2PfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void matrixMultiply2(float* A, float* C, int size)
{
float sum = 0;
int Col = blockIdx.x * TILE_WIDTH + threadIdx.x;
int Row = blockIdx.y * TILE_WIDTH + threadIdx.y;
if(Col < size && Row < size) {
for (int k = 0; k < size; k++)
sum += A[k * size + Row] * A[k * size + Col];
C[Row * size + Col] = sum;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMultiply2(float* A, float* C, int size)
{
float sum = 0;
int Col = blockIdx.x * TILE_WIDTH + threadIdx.x;
int Row = blockIdx.y * TILE_WIDTH + threadIdx.y;
if(Col < size && Row < size) {
for (int k = 0; k < size; k++)
sum += A[k * size + Row] * A[k * size + Col];
C[Row * size + Col] = sum;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMultiply2(float* A, float* C, int size)
{
float sum = 0;
int Col = blockIdx.x * TILE_WIDTH + threadIdx.x;
int Row = blockIdx.y * TILE_WIDTH + threadIdx.y;
if(Col < size && Row < size) {
for (int k = 0; k < size; k++)
sum += A[k * size + Row] * A[k * size + Col];
C[Row * size + Col] = sum;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrixMultiply2PfS_i
.globl _Z15matrixMultiply2PfS_i
.p2align 8
.type _Z15matrixMultiply2PfS_i,@function
_Z15matrixMultiply2PfS_i:
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v0, s14, 5, v1
v_lshl_add_u32 v1, s15, 5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_max_i32_e32 v2, v0, v1
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_mov_b32 s5, 0
s_mov_b32 s6, s4
.p2align 6
.LBB0_3:
v_add_nc_u32_e32 v3, s5, v1
v_add_nc_u32_e32 v5, s5, v0
s_add_i32 s6, s6, -1
s_add_i32 s5, s5, s4
s_cmp_eq_u32 s6, 0
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[5:6], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, v3, v4
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[3:4], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixMultiply2PfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrixMultiply2PfS_i, .Lfunc_end0-_Z15matrixMultiply2PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixMultiply2PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrixMultiply2PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMultiply2(float* A, float* C, int size)
{
float sum = 0;
int Col = blockIdx.x * TILE_WIDTH + threadIdx.x;
int Row = blockIdx.y * TILE_WIDTH + threadIdx.y;
if(Col < size && Row < size) {
for (int k = 0; k < size; k++)
sum += A[k * size + Row] * A[k * size + Col];
C[Row * size + Col] = sum;
}
} | .text
.file "matrixMultiply2.hip"
.globl _Z30__device_stub__matrixMultiply2PfS_i # -- Begin function _Z30__device_stub__matrixMultiply2PfS_i
.p2align 4, 0x90
.type _Z30__device_stub__matrixMultiply2PfS_i,@function
_Z30__device_stub__matrixMultiply2PfS_i: # @_Z30__device_stub__matrixMultiply2PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixMultiply2PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__matrixMultiply2PfS_i, .Lfunc_end0-_Z30__device_stub__matrixMultiply2PfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixMultiply2PfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matrixMultiply2PfS_i,@object # @_Z15matrixMultiply2PfS_i
.section .rodata,"a",@progbits
.globl _Z15matrixMultiply2PfS_i
.p2align 3, 0x0
_Z15matrixMultiply2PfS_i:
.quad _Z30__device_stub__matrixMultiply2PfS_i
.size _Z15matrixMultiply2PfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15matrixMultiply2PfS_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrixMultiply2PfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrixMultiply2PfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15matrixMultiply2PfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e620000002100 */
/*0050*/ LEA R7, R3, R4, 0x5 ; /* 0x0000000403077211 */
/* 0x001fc800078e28ff */
/*0060*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fe40003f06270 */
/*0070*/ LEA R8, R5, R6, 0x5 ; /* 0x0000000605087211 */
/* 0x002fc800078e28ff */
/*0080*/ ISETP.GE.OR P0, PT, R8, c[0x0][0x170], P0 ; /* 0x00005c0008007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R9, c[0x0][0x170] ; /* 0x00005c0000097a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R14, -RZ, RZ, 0, 0 ; /* 0x00000000ff0e7435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xcd0 ; /* 0x00000be000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R0, R9.reuse, -0x1, RZ ; /* 0xffffffff09007810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R10, R9, 0x3, RZ, 0xc0, !PT ; /* 0x00000003090a7812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R14, RZ ; /* 0x000000ff000e7202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xbc0 ; /* 0x00000a7000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R0, -R10, c[0x0][0x170], RZ ; /* 0x00005c000a007a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R28, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff1c7435 */
/* 0x000fe200000001ff */
/*0170*/ MOV R14, RZ ; /* 0x000000ff000e7202 */
/* 0x000fe20000000f00 */
/*0180*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f04270 */
/*01a0*/ IMAD.WIDE R20, R7, R28, c[0x0][0x160] ; /* 0x0000580007147625 */
/* 0x000fc800078e021c */
/*01b0*/ IMAD.WIDE R28, R8, R28, c[0x0][0x160] ; /* 0x00005800081c7625 */
/* 0x000fe400078e021c */
/*01c0*/ @!P0 BRA 0xa40 ; /* 0x0000087000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R0, 0xc, PT ; /* 0x0000000c0000780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x750 ; /* 0x0000055000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ IMAD.WIDE R18, R9.reuse, 0x4, R28 ; /* 0x0000000409127825 */
/* 0x040fe200078e021c */
/*0220*/ LDG.E R16, [R28.64] ; /* 0x000000041c107981 */
/* 0x0000a6000c1e1900 */
/*0230*/ IMAD.WIDE R26, R9.reuse, 0x4, R20 ; /* 0x00000004091a7825 */
/* 0x040fe200078e0214 */
/*0240*/ LDG.E R17, [R20.64] ; /* 0x0000000414117981 */
/* 0x0002a8000c1e1900 */
/*0250*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000722000c1e1900 */
/*0260*/ IMAD.WIDE R24, R9, 0x4, R26 ; /* 0x0000000409187825 */
/* 0x000fc600078e021a */
/*0270*/ LDG.E R13, [R26.64] ; /* 0x000000041a0d7981 */
/* 0x000b28000c1e1900 */
/*0280*/ LDG.E R20, [R24.64] ; /* 0x0000000418147981 */
/* 0x002322000c1e1900 */
/*0290*/ IMAD.WIDE R18, R9, 0x4, R18 ; /* 0x0000000409127825 */
/* 0x008fca00078e0212 */
/*02a0*/ LDG.E R15, [R18.64] ; /* 0x00000004120f7981 */
/* 0x000722000c1e1900 */
/*02b0*/ IMAD.WIDE R22, R9, 0x4, R18 ; /* 0x0000000409167825 */
/* 0x000fc800078e0212 */
/*02c0*/ IMAD.WIDE R24, R9.reuse, 0x4, R24 ; /* 0x0000000409187825 */
/* 0x042fe200078e0218 */
/*02d0*/ LDG.E R28, [R22.64] ; /* 0x00000004161c7981 */
/* 0x001128000c1e1900 */
/*02e0*/ LDG.E R11, [R24.64] ; /* 0x00000004180b7981 */
/* 0x000322000c1e1900 */
/*02f0*/ IMAD.WIDE R18, R9, 0x4, R24 ; /* 0x0000000409127825 */
/* 0x008fc800078e0218 */
/*0300*/ IMAD.WIDE R22, R9.reuse, 0x4, R22 ; /* 0x0000000409167825 */
/* 0x041fe200078e0216 */
/*0310*/ LDG.E R27, [R18.64] ; /* 0x00000004121b7981 */
/* 0x0200e8000c1e1900 */
/*0320*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000ae2000c1e1900 */
/*0330*/ IMAD.WIDE R18, R9, 0x4, R18 ; /* 0x0000000409127825 */
/* 0x001fc800078e0212 */
/*0340*/ IMAD.WIDE R22, R9, 0x4, R22 ; /* 0x0000000409167825 */
/* 0x020fe200078e0216 */
/*0350*/ LDG.E R21, [R18.64] ; /* 0x0000000412157981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x002362000c1e1900 */
/*0370*/ FFMA R16, R16, R17, R14 ; /* 0x0000001110107223 */
/* 0x004fc8000000000e */
/*0380*/ FFMA R14, R12, R13, R16 ; /* 0x0000000d0c0e7223 */
/* 0x010fe40000000010 */
/*0390*/ IMAD.WIDE R12, R9, 0x4, R22 ; /* 0x00000004090c7825 */
/* 0x000fc800078e0216 */
/*03a0*/ IMAD.WIDE R16, R9, 0x4, R18 ; /* 0x0000000409107825 */
/* 0x000fc800078e0212 */
/*03b0*/ FFMA R29, R15, R20, R14 ; /* 0x000000140f1d7223 */
/* 0x000fe2000000000e */
/*03c0*/ LDG.E R25, [R16.64] ; /* 0x0000000410197981 */
/* 0x000522000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R9, 0x4, R12 ; /* 0x00000004090e7825 */
/* 0x000fc600078e020c */
/*03e0*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000122000c1e1900 */
/*03f0*/ IMAD.WIDE R16, R9, 0x4, R16 ; /* 0x0000000409107825 */
/* 0x004fc800078e0210 */
/*0400*/ IMAD.WIDE R12, R9.reuse, 0x4, R14 ; /* 0x00000004090c7825 */
/* 0x041fe400078e020e */
/*0410*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0420*/ FFMA R28, R28, R11, R29 ; /* 0x0000000b1c1c7223 */
/* 0x000fe4000000001d */
/*0430*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x0000a2000c1e1900 */
/*0440*/ IMAD.WIDE R18, R9, 0x4, R16 ; /* 0x0000000409127825 */
/* 0x000fc600078e0210 */
/*0450*/ LDG.E R29, [R12.64] ; /* 0x000000040c1d7981 */
/* 0x0000a2000c1e1900 */
/*0460*/ IMAD.WIDE R22, R9, 0x4, R12 ; /* 0x0000000409167825 */
/* 0x002fc600078e020c */
/*0470*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x0010a2000c1e1900 */
/*0480*/ FFMA R15, R26, R27, R28 ; /* 0x0000001b1a0f7223 */
/* 0x008fc6000000001c */
/*0490*/ LDG.E R13, [R22.64] ; /* 0x00000004160d7981 */
/* 0x0002e2000c1e1900 */
/*04a0*/ IMAD.WIDE R18, R9, 0x4, R18 ; /* 0x0000000409127825 */
/* 0x001fca00078e0212 */
/*04b0*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x0000e2000c1e1900 */
/*04c0*/ IMAD.WIDE R26, R9, 0x4, R22 ; /* 0x00000004091a7825 */
/* 0x000fc800078e0216 */
/*04d0*/ IMAD.WIDE R16, R9.reuse, 0x4, R18 ; /* 0x0000000409107825 */
/* 0x040fe200078e0212 */
/*04e0*/ LDG.E R22, [R26.64] ; /* 0x000000041a167981 */
/* 0x0022e6000c1e1900 */
/*04f0*/ FFMA R21, R24, R21, R15 ; /* 0x0000001518157223 */
/* 0x020fe4000000000f */
/*0500*/ LDG.E R15, [R16.64] ; /* 0x00000004100f7981 */
/* 0x000ae4000c1e1900 */
/*0510*/ FFMA R23, R20, R25, R21 ; /* 0x0000001914177223 */
/* 0x010fe40000000015 */
/*0520*/ IMAD.WIDE R20, R9, 0x4, R16 ; /* 0x0000000409147825 */
/* 0x000fc800078e0210 */
/*0530*/ IMAD.WIDE R24, R9.reuse, 0x4, R26 ; /* 0x0000000409187825 */
/* 0x040fe200078e021a */
/*0540*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x02096a000c1e1900 */
/*0550*/ IMAD.WIDE R18, R9, 0x4, R24 ; /* 0x0000000409127825 */
/* 0x001fe400078e0218 */
/*0560*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000164000c1e1900 */
/*0570*/ FFMA R11, R14, R11, R23 ; /* 0x0000000b0e0b7223 */
/* 0x004fc40000000017 */
/*0580*/ IMAD.WIDE R20, R9, 0x4, R20 ; /* 0x0000000409147825 */
/* 0x010fca00078e0214 */
/*0590*/ LDG.E R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x000522000c1e1900 */
/*05a0*/ IMAD.WIDE R26, R9, 0x4, R20 ; /* 0x00000004091a7825 */
/* 0x002fc800078e0214 */
/*05b0*/ FFMA R12, R29, R12, R11 ; /* 0x0000000c1d0c7223 */
/* 0x000fe4000000000b */
/*05c0*/ LDG.E R11, [R18.64] ; /* 0x00000004120b7981 */
/* 0x000324000c1e1900 */
/*05d0*/ IMAD.WIDE R18, R9, 0x4, R18 ; /* 0x0000000409127825 */
/* 0x002fc800078e0212 */
/*05e0*/ FFMA R23, R13, R28, R12 ; /* 0x0000001c0d177223 */
/* 0x008fe2000000000c */
/*05f0*/ LDG.E R17, [R18.64] ; /* 0x0000000412117981 */
/* 0x000ee2000c1e1900 */
/*0600*/ IMAD.WIDE R12, R9, 0x4, R26 ; /* 0x00000004090c7825 */
/* 0x000fc600078e021a */
/*0610*/ LDG.E R26, [R26.64] ; /* 0x000000041a1a7981 */
/* 0x000ee2000c1e1900 */
/*0620*/ IMAD.WIDE R28, R9, 0x4, R18 ; /* 0x00000004091c7825 */
/* 0x000fc600078e0212 */
/*0630*/ LDG.E R24, [R12.64] ; /* 0x000000040c187981 */
/* 0x0010e8000c1e1900 */
/*0640*/ LDG.E R21, [R28.64] ; /* 0x000000041c157981 */
/* 0x0042a2000c1e1900 */
/*0650*/ FFMA R15, R22, R15, R23 ; /* 0x0000000f160f7223 */
/* 0x000fe40000000017 */
/*0660*/ IMAD.WIDE R12, R9, 0x4, R12 ; /* 0x00000004090c7825 */
/* 0x001fc800078e020c */
/*0670*/ IMAD.WIDE R28, R9, 0x4, R28 ; /* 0x00000004091c7825 */
/* 0x002fe200078e021c */
/*0680*/ LDG.E R22, [R12.64] ; /* 0x000000040c167981 */
/* 0x000ea8000c1e1900 */
/*0690*/ LDG.E R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x0000a2000c1e1900 */
/*06a0*/ IADD3 R0, R0, -0x10, RZ ; /* 0xfffffff000007810 */
/* 0x000fc80007ffe0ff */
/*06b0*/ ISETP.GT.AND P1, PT, R0, 0xc, PT ; /* 0x0000000c0000780c */
/* 0x000fe40003f24270 */
/*06c0*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*06d0*/ IMAD.WIDE R28, R9, 0x4, R28 ; /* 0x00000004091c7825 */
/* 0x001fc800078e021c */
/*06e0*/ FFMA R15, R25, R16, R15 ; /* 0x00000010190f7223 */
/* 0x020fc8000000000f */
/*06f0*/ FFMA R11, R11, R14, R15 ; /* 0x0000000e0b0b7223 */
/* 0x010fc8000000000f */
/*0700*/ FFMA R11, R17, R26, R11 ; /* 0x0000001a110b7223 */
/* 0x008fc8000000000b */
/*0710*/ FFMA R11, R21, R24, R11 ; /* 0x00000018150b7223 */
/* 0x004fc8000000000b */
/*0720*/ FFMA R14, R20, R22, R11 ; /* 0x00000016140e7223 */
/* 0x000fe4000000000b */
/*0730*/ IMAD.WIDE R20, R9, 0x4, R12 ; /* 0x0000000409147825 */
/* 0x000fe200078e020c */
/*0740*/ @P1 BRA 0x210 ; /* 0xfffffac000001947 */
/* 0x000fea000383ffff */
/*0750*/ ISETP.GT.AND P1, PT, R0, 0x4, PT ; /* 0x000000040000780c */
/* 0x000fda0003f24270 */
/*0760*/ @!P1 BRA 0xa20 ; /* 0x000002b000009947 */
/* 0x000fea0003800000 */
/*0770*/ LDG.E R15, [R28.64] ; /* 0x000000041c0f7981 */
/* 0x0000a2000c1e1900 */
/*0780*/ IMAD.WIDE R16, R9, 0x4, R28 ; /* 0x0000000409107825 */
/* 0x000fc600078e021c */
/*0790*/ LDG.E R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x0002a2000c1e1900 */
/*07a0*/ IMAD.WIDE R24, R9, 0x4, R20 ; /* 0x0000000409187825 */
/* 0x000fc600078e0214 */
/*07b0*/ LDG.E R19, [R16.64] ; /* 0x0000000410137981 */
/* 0x000728000c1e1900 */
/*07c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x001122000c1e1900 */
/*07d0*/ IMAD.WIDE R22, R9, 0x4, R16 ; /* 0x0000000409167825 */
/* 0x000fc800078e0210 */
/*07e0*/ IMAD.WIDE R12, R9.reuse, 0x4, R24 ; /* 0x00000004090c7825 */
/* 0x040fe200078e0218 */
/*07f0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000b28000c1e1900 */
/*0800*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000122000c1e1900 */
/*0810*/ IMAD.WIDE R20, R9, 0x4, R12 ; /* 0x0000000409147825 */
/* 0x002fc800078e020c */
/*0820*/ IMAD.WIDE R22, R9, 0x4, R22 ; /* 0x0000000409167825 */
/* 0x020fc800078e0216 */
/*0830*/ IMAD.WIDE R12, R9.reuse, 0x4, R20 ; /* 0x00000004090c7825 */
/* 0x041fe200078e0214 */
/*0840*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x000166000c1e1900 */
/*0850*/ IMAD.WIDE R16, R9.reuse, 0x4, R22 ; /* 0x0000000409107825 */
/* 0x048fe200078e0216 */
/*0860*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000368000c1e1900 */
/*0870*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000768000c1e1900 */
/*0880*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x000162000c1e1900 */
/*0890*/ IMAD.WIDE R16, R9, 0x4, R16 ; /* 0x0000000409107825 */
/* 0x008fca00078e0210 */
/*08a0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x002ee2000c1e1900 */
/*08b0*/ FFMA R18, R15, R18, R14 ; /* 0x000000120f127223 */
/* 0x004fe4000000000e */
/*08c0*/ IMAD.WIDE R14, R9, 0x4, R12 ; /* 0x00000004090e7825 */
/* 0x000fc800078e020c */
/*08d0*/ FFMA R28, R19, R28, R18 ; /* 0x0000001c131c7223 */
/* 0x010fe40000000012 */
/*08e0*/ IMAD.WIDE R12, R9.reuse, 0x4, R14 ; /* 0x00000004090c7825 */
/* 0x041fe400078e020e */
/*08f0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e4000c1e1900 */
/*0900*/ IMAD.WIDE R18, R9.reuse, 0x4, R16 ; /* 0x0000000409127825 */
/* 0x040fe400078e0210 */
/*0910*/ LDG.E R29, [R12.64] ; /* 0x000000040c1d7981 */
/* 0x000ea4000c1e1900 */
/*0920*/ IMAD.WIDE R22, R9, 0x4, R12 ; /* 0x0000000409167825 */
/* 0x000fc400078e020c */
/*0930*/ LDG.E R15, [R18.64] ; /* 0x00000004120f7981 */
/* 0x0010a4000c1e1900 */
/*0940*/ FFMA R26, R26, R27, R28 ; /* 0x0000001b1a1a7223 */
/* 0x000fe4000000001c */
/*0950*/ LDG.E R27, [R22.64] ; /* 0x00000004161b7981 */
/* 0x000f22000c1e1900 */
/*0960*/ IMAD.WIDE R18, R9, 0x4, R18 ; /* 0x0000000409127825 */
/* 0x001fca00078e0212 */
/*0970*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x000f22000c1e1900 */
/*0980*/ FFMA R11, R11, R20, R26 ; /* 0x000000140b0b7223 */
/* 0x020fc8000000001a */
/*0990*/ FFMA R11, R24, R25, R11 ; /* 0x00000019180b7223 */
/* 0x000fe2000000000b */
/*09a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*09b0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*09c0*/ IADD3 R0, R0, -0x8, RZ ; /* 0xfffffff800007810 */
/* 0x000fe20007ffe0ff */
/*09d0*/ FFMA R16, R21, R14, R11 ; /* 0x0000000e15107223 */
/* 0x008fe4000000000b */
/*09e0*/ IMAD.WIDE R20, R9, 0x4, R22 ; /* 0x0000000409147825 */
/* 0x000fc800078e0216 */
/*09f0*/ FFMA R15, R15, R29, R16 ; /* 0x0000001d0f0f7223 */
/* 0x004fc80000000010 */
/*0a00*/ FFMA R14, R28, R27, R15 ; /* 0x0000001b1c0e7223 */
/* 0x010fe4000000000f */
/*0a10*/ IMAD.WIDE R28, R9, 0x4, R18 ; /* 0x00000004091c7825 */
/* 0x000fc800078e0212 */
/*0a20*/ ISETP.NE.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000705670 */
/*0a30*/ @!P0 BRA 0xbc0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0a40*/ IMAD.WIDE R16, R9.reuse, 0x4, R20 ; /* 0x0000000409107825 */
/* 0x040fe400078e0214 */
/*0a50*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea4000c1e1900 */
/*0a60*/ IMAD.WIDE R12, R9.reuse, 0x4, R28 ; /* 0x00000004090c7825 */
/* 0x040fe400078e021c */
/*0a70*/ LDG.E R29, [R28.64] ; /* 0x000000041c1d7981 */
/* 0x0000a4000c1e1900 */
/*0a80*/ IMAD.WIDE R22, R9.reuse, 0x4, R16 ; /* 0x0000000409167825 */
/* 0x040fe400078e0210 */
/*0a90*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee4000c1e1900 */
/*0aa0*/ IMAD.WIDE R18, R9, 0x4, R12 ; /* 0x0000000409127825 */
/* 0x000fc400078e020c */
/*0ab0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x0002e4000c1e1900 */
/*0ac0*/ IMAD.WIDE R24, R9.reuse, 0x4, R22 ; /* 0x0000000409187825 */
/* 0x040fe400078e0216 */
/*0ad0*/ LDG.E R15, [R22.64] ; /* 0x00000004160f7981 */
/* 0x000f24000c1e1900 */
/*0ae0*/ IMAD.WIDE R26, R9, 0x4, R18 ; /* 0x00000004091a7825 */
/* 0x000fe400078e0212 */
/*0af0*/ LDG.E R11, [R18.64] ; /* 0x00000004120b7981 */
/* 0x000f28000c1e1900 */
/*0b00*/ LDG.E R13, [R24.64] ; /* 0x00000004180d7981 */
/* 0x002f68000c1e1900 */
/*0b10*/ LDG.E R28, [R26.64] ; /* 0x000000041a1c7981 */
/* 0x001f62000c1e1900 */
/*0b20*/ IADD3 R0, R0, -0x4, RZ ; /* 0xfffffffc00007810 */
/* 0x000fc80007ffe0ff */
/*0b30*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0b40*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fe20007ffe0ff */
/*0b50*/ FFMA R29, R29, R20, R14 ; /* 0x000000141d1d7223 */
/* 0x004fc8000000000e */
/*0b60*/ FFMA R29, R12, R16, R29 ; /* 0x000000100c1d7223 */
/* 0x008fe4000000001d */
/*0b70*/ IMAD.WIDE R20, R9, 0x4, R24 ; /* 0x0000000409147825 */
/* 0x000fc800078e0218 */
/*0b80*/ FFMA R11, R11, R15, R29 ; /* 0x0000000f0b0b7223 */
/* 0x010fc8000000001d */
/*0b90*/ FFMA R14, R28, R13, R11 ; /* 0x0000000d1c0e7223 */
/* 0x020fe4000000000b */
/*0ba0*/ IMAD.WIDE R28, R9, 0x4, R26 ; /* 0x00000004091c7825 */
/* 0x000fe200078e021a */
/*0bb0*/ @P0 BRA 0xa40 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0bc0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05270 */
/*0bd0*/ @!P0 BRA 0xcd0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0be0*/ IMAD R6, R2.reuse, c[0x0][0x170], R6 ; /* 0x00005c0002067a24 */
/* 0x040fe200078e0206 */
/*0bf0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0c00*/ IMAD R2, R2, c[0x0][0x170], R4 ; /* 0x00005c0002027a24 */
/* 0x000fc600078e0204 */
/*0c10*/ LEA R6, R5, R6, 0x5 ; /* 0x0000000605067211 */
/* 0x000fe400078e28ff */
/*0c20*/ LEA R4, R3, R2, 0x5 ; /* 0x0000000203047211 */
/* 0x000fc800078e28ff */
/*0c30*/ IMAD.WIDE R2, R6, R11, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e020b */
/*0c40*/ IMAD.WIDE R4, R4, R11, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e020b */
/*0c50*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x0000a8000c1e1900 */
/*0c60*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x0002a2000c1e1900 */
/*0c70*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x000fc80007ffe0ff */
/*0c80*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*0c90*/ IMAD.WIDE R2, R9, 0x4, R2 ; /* 0x0000000409027825 */
/* 0x001fc800078e0202 */
/*0ca0*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x002fc800078e0204 */
/*0cb0*/ FFMA R14, R11, R0, R14 ; /* 0x000000000b0e7223 */
/* 0x004fc8000000000e */
/*0cc0*/ @P0 BRA 0xc50 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0cd0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*0ce0*/ IMAD R2, R7, c[0x0][0x170], R8 ; /* 0x00005c0007027a24 */
/* 0x000fc800078e0208 */
/*0cf0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*0d00*/ STG.E [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x000fe2000c101904 */
/*0d10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d20*/ BRA 0xd20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrixMultiply2PfS_i
.globl _Z15matrixMultiply2PfS_i
.p2align 8
.type _Z15matrixMultiply2PfS_i,@function
_Z15matrixMultiply2PfS_i:
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v0, s14, 5, v1
v_lshl_add_u32 v1, s15, 5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_max_i32_e32 v2, v0, v1
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_mov_b32 s5, 0
s_mov_b32 s6, s4
.p2align 6
.LBB0_3:
v_add_nc_u32_e32 v3, s5, v1
v_add_nc_u32_e32 v5, s5, v0
s_add_i32 s6, s6, -1
s_add_i32 s5, s5, s4
s_cmp_eq_u32 s6, 0
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[5:6], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, v3, v4
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[3:4], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixMultiply2PfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrixMultiply2PfS_i, .Lfunc_end0-_Z15matrixMultiply2PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixMultiply2PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrixMultiply2PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015c204_00000000-6_matrixMultiply2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i
.type _Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i, @function
_Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixMultiply2PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i, .-_Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i
.globl _Z15matrixMultiply2PfS_i
.type _Z15matrixMultiply2PfS_i, @function
_Z15matrixMultiply2PfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15matrixMultiply2PfS_i, .-_Z15matrixMultiply2PfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15matrixMultiply2PfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixMultiply2PfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixMultiply2.hip"
.globl _Z30__device_stub__matrixMultiply2PfS_i # -- Begin function _Z30__device_stub__matrixMultiply2PfS_i
.p2align 4, 0x90
.type _Z30__device_stub__matrixMultiply2PfS_i,@function
_Z30__device_stub__matrixMultiply2PfS_i: # @_Z30__device_stub__matrixMultiply2PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixMultiply2PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__matrixMultiply2PfS_i, .Lfunc_end0-_Z30__device_stub__matrixMultiply2PfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixMultiply2PfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matrixMultiply2PfS_i,@object # @_Z15matrixMultiply2PfS_i
.section .rodata,"a",@progbits
.globl _Z15matrixMultiply2PfS_i
.p2align 3, 0x0
_Z15matrixMultiply2PfS_i:
.quad _Z30__device_stub__matrixMultiply2PfS_i
.size _Z15matrixMultiply2PfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15matrixMultiply2PfS_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrixMultiply2PfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrixMultiply2PfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
int const N = 32;
int const THREADS = 12;
int const BSZ = 3;
float const EPS2 = 0.0001;
double get_time()
{ struct timeval tim;
cudaThreadSynchronize();
gettimeofday(&tim, NULL);
return (double) tim.tv_sec+(tim.tv_usec/1000000.0);
}
__global__ void direct_sh(float4 *sourceGlob, float *targetGlob)
{
__shared__ float4 p_sh[THREADS];
int tx = threadIdx.x;
int bx = blockIdx.x;
int I = bx * THREADS + tx;
float dx,dy,dz,r;
float4 p1 = sourceGlob[I];
float p = - p1.w/ sqrtf(EPS2);
float4 p2;
for (unsigned int m = 0; m < BSZ-1; m++ ){
p_sh[tx] = sourceGlob[m * THREADS + tx];
__syncthreads();
#pragma unroll 10
for (unsigned int i = 0; i < THREADS; i++){
p2 = p_sh[i];
dx = p1.x - p2.x;
dy = p1.y - p2.y;
dz = p1.z - p2.z;
r = sqrtf(dx * dx + dy * dy + dz * dz + EPS2);
p += p1.w / r;
}
__syncthreads();
}
int m = BSZ-1;
p_sh[tx] = sourceGlob[m*THREADS + tx];
__syncthreads();
int lastDim = N%THREADS;
for ( unsigned int i = 0; i < lastDim; i++){
p2 = p_sh[i];
dx = p1.x - p2.x;
dy = p1.y - p2.y;
dz = p1.z - p2.z;
r = sqrtf(dx * dx + dy * dy + dz * dz + EPS2);
p += p1.w / r;
}
__syncthreads();
targetGlob[I] = p;
}
__global__ void direct(float4 *sourceGlob, float *targetGlob)
{ /*** wirte your kernel here! *****/
int tx = threadIdx.x;
float dx,dy,dz,r;
float4 p1,p2;
p1 = sourceGlob[tx];
float p = - p1.w / sqrtf(EPS2);
for ( int j = 0; j < N; j++ ){
p2 = sourceGlob[j];
dx = p1.x - p2.x;
dy = p1.y - p2.y;
dz = p1.z - p2.z;
r = sqrtf(dx * dx + dy * dy + dz * dz + EPS2);
p += p1.w / r;
}
targetGlob[tx] = p;
}
int main() {
float4 *sourceHost,*sourceDevc;
float *targetHost,*targetDevc;
// Allocate memory on host and device
sourceHost = (float4*) malloc( N*sizeof(float4) );
targetHost = (float *) malloc( N*sizeof(float ) );
cudaMalloc( (void**) &sourceDevc, N*sizeof(float4) );
cudaMalloc( (void**) &targetDevc, N*sizeof(float ) );
// Initialize
for( int i=0; i<N; i++ ) {
sourceHost[i].x = rand()/(1.+RAND_MAX);
sourceHost[i].y = rand()/(1.+RAND_MAX);
sourceHost[i].z = rand()/(1.+RAND_MAX);
sourceHost[i].w = 1.0/N;
}
// Direct summation on device
cudaMemcpy(sourceDevc,sourceHost,N*sizeof(float4),cudaMemcpyHostToDevice);
double start = get_time();
direct_sh<<< int(N-0.5/THREADS)+1, THREADS >>>(sourceDevc,targetDevc);
double stop = get_time();
cudaMemcpy(targetHost,targetDevc,N*sizeof(float ),cudaMemcpyDeviceToHost);
double time = stop - start;
std::cout<<"Kernel execution time: "<<time<<std::endl;
// Direct summation on host
float dx,dy,dz,r;
for( int i=0; i<N; i++ ) {
float p = - sourceHost[i].w / sqrtf(EPS2);
for( int j=0; j<N; j++ ) {
dx = sourceHost[i].x - sourceHost[j].x;
dy = sourceHost[i].y - sourceHost[j].y;
dz = sourceHost[i].z - sourceHost[j].z;
r = sqrtf(dx * dx + dy * dy + dz * dz + EPS2);
p += sourceHost[j].w / r;
}
printf("%d %f %f\n",i,p,targetHost[i]);
}
} | .file "tmpxft_00151afe_00000000-6_lab8_nbody.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8get_timev
.type _Z8get_timev, @function
_Z8get_timev:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
call cudaThreadSynchronize@PLT
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z8get_timev, .-_Z8get_timev
.globl _Z36__device_stub__Z9direct_shP6float4PfP6float4Pf
.type _Z36__device_stub__Z9direct_shP6float4PfP6float4Pf, @function
_Z36__device_stub__Z9direct_shP6float4PfP6float4Pf:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9direct_shP6float4Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z36__device_stub__Z9direct_shP6float4PfP6float4Pf, .-_Z36__device_stub__Z9direct_shP6float4PfP6float4Pf
.globl _Z9direct_shP6float4Pf
.type _Z9direct_shP6float4Pf, @function
_Z9direct_shP6float4Pf:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z9direct_shP6float4PfP6float4Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z9direct_shP6float4Pf, .-_Z9direct_shP6float4Pf
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Kernel execution time: "
.LC7:
.string "%d %f %f\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $512, %edi
call malloc@PLT
movq %rax, %r13
movl $128, %edi
call malloc@PLT
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 512(%r13), %rbx
movq %r13, %rbp
movl .LC2(%rip), %r12d
.L16:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 4(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 8(%rbp)
movl %r12d, 12(%rbp)
addq $16, %rbp
cmpq %rbx, %rbp
jne .L16
movl $1, %ecx
movl $512, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call _Z8get_timev
movsd %xmm0, (%rsp)
movl $12, 44(%rsp)
movl $1, 48(%rsp)
movl $32, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L17:
call _Z8get_timev
movsd %xmm0, 8(%rsp)
movl $2, %ecx
movl $128, %edx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movsd 8(%rsp), %xmm7
subsd (%rsp), %xmm7
movq %xmm7, %rbp
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %rbp
movl $0, %r12d
leaq .LC7(%rip), %r15
.L19:
movl %r12d, %edx
movss 12(%rbp), %xmm0
xorps .LC4(%rip), %xmm0
divss .LC5(%rip), %xmm0
movss 0(%rbp), %xmm6
movss 4(%rbp), %xmm5
movss 8(%rbp), %xmm4
movq %r13, %rax
.L18:
movaps %xmm6, %xmm1
subss (%rax), %xmm1
movaps %xmm5, %xmm3
subss 4(%rax), %xmm3
movaps %xmm4, %xmm2
subss 8(%rax), %xmm2
mulss %xmm1, %xmm1
mulss %xmm3, %xmm3
addss %xmm3, %xmm1
mulss %xmm2, %xmm2
addss %xmm2, %xmm1
addss .LC6(%rip), %xmm1
sqrtss %xmm1, %xmm1
movss 12(%rax), %xmm2
divss %xmm1, %xmm2
addss %xmm2, %xmm0
addq $16, %rax
cmpq %rbx, %rax
jne .L18
cvtss2sd %xmm0, %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%r14,%r12,4), %xmm1
movq %r15, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $1, %r12
addq $16, %rbp
cmpq $32, %r12
jne .L19
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z36__device_stub__Z9direct_shP6float4PfP6float4Pf
jmp .L17
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.globl _Z33__device_stub__Z6directP6float4PfP6float4Pf
.type _Z33__device_stub__Z6directP6float4PfP6float4Pf, @function
_Z33__device_stub__Z6directP6float4PfP6float4Pf:
.LFB3697:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6directP6float4Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z33__device_stub__Z6directP6float4PfP6float4Pf, .-_Z33__device_stub__Z6directP6float4PfP6float4Pf
.globl _Z6directP6float4Pf
.type _Z6directP6float4Pf, @function
_Z6directP6float4Pf:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z6directP6float4PfP6float4Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z6directP6float4Pf, .-_Z6directP6float4Pf
.section .rodata.str1.1
.LC8:
.string "_Z6directP6float4Pf"
.LC9:
.string "_Z9direct_shP6float4Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z6directP6float4Pf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z9direct_shP6float4Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.align 8
.LC1:
.long 0
.long 1040187392
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1023410176
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long -2147483648
.long 0
.long 0
.long 0
.section .rodata.cst4
.align 4
.LC5:
.long 1008981770
.align 4
.LC6:
.long 953267991
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
int const N = 32;
int const THREADS = 12;
int const BSZ = 3;
float const EPS2 = 0.0001;
double get_time()
{ struct timeval tim;
cudaThreadSynchronize();
gettimeofday(&tim, NULL);
return (double) tim.tv_sec+(tim.tv_usec/1000000.0);
}
__global__ void direct_sh(float4 *sourceGlob, float *targetGlob)
{
__shared__ float4 p_sh[THREADS];
int tx = threadIdx.x;
int bx = blockIdx.x;
int I = bx * THREADS + tx;
float dx,dy,dz,r;
float4 p1 = sourceGlob[I];
float p = - p1.w/ sqrtf(EPS2);
float4 p2;
for (unsigned int m = 0; m < BSZ-1; m++ ){
p_sh[tx] = sourceGlob[m * THREADS + tx];
__syncthreads();
#pragma unroll 10
for (unsigned int i = 0; i < THREADS; i++){
p2 = p_sh[i];
dx = p1.x - p2.x;
dy = p1.y - p2.y;
dz = p1.z - p2.z;
r = sqrtf(dx * dx + dy * dy + dz * dz + EPS2);
p += p1.w / r;
}
__syncthreads();
}
int m = BSZ-1;
p_sh[tx] = sourceGlob[m*THREADS + tx];
__syncthreads();
int lastDim = N%THREADS;
for ( unsigned int i = 0; i < lastDim; i++){
p2 = p_sh[i];
dx = p1.x - p2.x;
dy = p1.y - p2.y;
dz = p1.z - p2.z;
r = sqrtf(dx * dx + dy * dy + dz * dz + EPS2);
p += p1.w / r;
}
__syncthreads();
targetGlob[I] = p;
}
__global__ void direct(float4 *sourceGlob, float *targetGlob)
{ /*** wirte your kernel here! *****/
int tx = threadIdx.x;
float dx,dy,dz,r;
float4 p1,p2;
p1 = sourceGlob[tx];
float p = - p1.w / sqrtf(EPS2);
for ( int j = 0; j < N; j++ ){
p2 = sourceGlob[j];
dx = p1.x - p2.x;
dy = p1.y - p2.y;
dz = p1.z - p2.z;
r = sqrtf(dx * dx + dy * dy + dz * dz + EPS2);
p += p1.w / r;
}
targetGlob[tx] = p;
}
int main() {
float4 *sourceHost,*sourceDevc;
float *targetHost,*targetDevc;
// Allocate memory on host and device
sourceHost = (float4*) malloc( N*sizeof(float4) );
targetHost = (float *) malloc( N*sizeof(float ) );
cudaMalloc( (void**) &sourceDevc, N*sizeof(float4) );
cudaMalloc( (void**) &targetDevc, N*sizeof(float ) );
// Initialize
for( int i=0; i<N; i++ ) {
sourceHost[i].x = rand()/(1.+RAND_MAX);
sourceHost[i].y = rand()/(1.+RAND_MAX);
sourceHost[i].z = rand()/(1.+RAND_MAX);
sourceHost[i].w = 1.0/N;
}
// Direct summation on device
cudaMemcpy(sourceDevc,sourceHost,N*sizeof(float4),cudaMemcpyHostToDevice);
double start = get_time();
direct_sh<<< int(N-0.5/THREADS)+1, THREADS >>>(sourceDevc,targetDevc);
double stop = get_time();
cudaMemcpy(targetHost,targetDevc,N*sizeof(float ),cudaMemcpyDeviceToHost);
double time = stop - start;
std::cout<<"Kernel execution time: "<<time<<std::endl;
// Direct summation on host
float dx,dy,dz,r;
for( int i=0; i<N; i++ ) {
float p = - sourceHost[i].w / sqrtf(EPS2);
for( int j=0; j<N; j++ ) {
dx = sourceHost[i].x - sourceHost[j].x;
dy = sourceHost[i].y - sourceHost[j].y;
dz = sourceHost[i].z - sourceHost[j].z;
r = sqrtf(dx * dx + dy * dy + dz * dz + EPS2);
p += sourceHost[j].w / r;
}
printf("%d %f %f\n",i,p,targetHost[i]);
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
int const N = 32;
int const THREADS = 12;
int const BSZ = 3;
float const EPS2 = 0.0001;
double get_time()
{ struct timeval tim;
hipDeviceSynchronize();
gettimeofday(&tim, NULL);
return (double) tim.tv_sec+(tim.tv_usec/1000000.0);
}
__global__ void direct_sh(float4 *sourceGlob, float *targetGlob)
{
__shared__ float4 p_sh[THREADS];
int tx = threadIdx.x;
int bx = blockIdx.x;
int I = bx * THREADS + tx;
float dx,dy,dz,r;
float4 p1 = sourceGlob[I];
float p = - p1.w/ sqrtf(EPS2);
float4 p2;
for (unsigned int m = 0; m < BSZ-1; m++ ){
p_sh[tx] = sourceGlob[m * THREADS + tx];
__syncthreads();
#pragma unroll 10
for (unsigned int i = 0; i < THREADS; i++){
p2 = p_sh[i];
dx = p1.x - p2.x;
dy = p1.y - p2.y;
dz = p1.z - p2.z;
r = sqrtf(dx * dx + dy * dy + dz * dz + EPS2);
p += p1.w / r;
}
__syncthreads();
}
int m = BSZ-1;
p_sh[tx] = sourceGlob[m*THREADS + tx];
__syncthreads();
int lastDim = N%THREADS;
for ( unsigned int i = 0; i < lastDim; i++){
p2 = p_sh[i];
dx = p1.x - p2.x;
dy = p1.y - p2.y;
dz = p1.z - p2.z;
r = sqrtf(dx * dx + dy * dy + dz * dz + EPS2);
p += p1.w / r;
}
__syncthreads();
targetGlob[I] = p;
}
__global__ void direct(float4 *sourceGlob, float *targetGlob)
{ /*** wirte your kernel here! *****/
int tx = threadIdx.x;
float dx,dy,dz,r;
float4 p1,p2;
p1 = sourceGlob[tx];
float p = - p1.w / sqrtf(EPS2);
for ( int j = 0; j < N; j++ ){
p2 = sourceGlob[j];
dx = p1.x - p2.x;
dy = p1.y - p2.y;
dz = p1.z - p2.z;
r = sqrtf(dx * dx + dy * dy + dz * dz + EPS2);
p += p1.w / r;
}
targetGlob[tx] = p;
}
int main() {
float4 *sourceHost,*sourceDevc;
float *targetHost,*targetDevc;
// Allocate memory on host and device
sourceHost = (float4*) malloc( N*sizeof(float4) );
targetHost = (float *) malloc( N*sizeof(float ) );
hipMalloc( (void**) &sourceDevc, N*sizeof(float4) );
hipMalloc( (void**) &targetDevc, N*sizeof(float ) );
// Initialize
for( int i=0; i<N; i++ ) {
sourceHost[i].x = rand()/(1.+RAND_MAX);
sourceHost[i].y = rand()/(1.+RAND_MAX);
sourceHost[i].z = rand()/(1.+RAND_MAX);
sourceHost[i].w = 1.0/N;
}
// Direct summation on device
hipMemcpy(sourceDevc,sourceHost,N*sizeof(float4),hipMemcpyHostToDevice);
double start = get_time();
direct_sh<<< int(N-0.5/THREADS)+1, THREADS >>>(sourceDevc,targetDevc);
double stop = get_time();
hipMemcpy(targetHost,targetDevc,N*sizeof(float ),hipMemcpyDeviceToHost);
double time = stop - start;
std::cout<<"Kernel execution time: "<<time<<std::endl;
// Direct summation on host
float dx,dy,dz,r;
for( int i=0; i<N; i++ ) {
float p = - sourceHost[i].w / sqrtf(EPS2);
for( int j=0; j<N; j++ ) {
dx = sourceHost[i].x - sourceHost[j].x;
dy = sourceHost[i].y - sourceHost[j].y;
dz = sourceHost[i].z - sourceHost[j].z;
r = sqrtf(dx * dx + dy * dy + dz * dz + EPS2);
p += sourceHost[j].w / r;
}
printf("%d %f %f\n",i,p,targetHost[i]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
int const N = 32;
int const THREADS = 12;
int const BSZ = 3;
float const EPS2 = 0.0001;
double get_time()
{ struct timeval tim;
hipDeviceSynchronize();
gettimeofday(&tim, NULL);
return (double) tim.tv_sec+(tim.tv_usec/1000000.0);
}
__global__ void direct_sh(float4 *sourceGlob, float *targetGlob)
{
__shared__ float4 p_sh[THREADS];
int tx = threadIdx.x;
int bx = blockIdx.x;
int I = bx * THREADS + tx;
float dx,dy,dz,r;
float4 p1 = sourceGlob[I];
float p = - p1.w/ sqrtf(EPS2);
float4 p2;
for (unsigned int m = 0; m < BSZ-1; m++ ){
p_sh[tx] = sourceGlob[m * THREADS + tx];
__syncthreads();
#pragma unroll 10
for (unsigned int i = 0; i < THREADS; i++){
p2 = p_sh[i];
dx = p1.x - p2.x;
dy = p1.y - p2.y;
dz = p1.z - p2.z;
r = sqrtf(dx * dx + dy * dy + dz * dz + EPS2);
p += p1.w / r;
}
__syncthreads();
}
int m = BSZ-1;
p_sh[tx] = sourceGlob[m*THREADS + tx];
__syncthreads();
int lastDim = N%THREADS;
for ( unsigned int i = 0; i < lastDim; i++){
p2 = p_sh[i];
dx = p1.x - p2.x;
dy = p1.y - p2.y;
dz = p1.z - p2.z;
r = sqrtf(dx * dx + dy * dy + dz * dz + EPS2);
p += p1.w / r;
}
__syncthreads();
targetGlob[I] = p;
}
__global__ void direct(float4 *sourceGlob, float *targetGlob)
{ /*** wirte your kernel here! *****/
int tx = threadIdx.x;
float dx,dy,dz,r;
float4 p1,p2;
p1 = sourceGlob[tx];
float p = - p1.w / sqrtf(EPS2);
for ( int j = 0; j < N; j++ ){
p2 = sourceGlob[j];
dx = p1.x - p2.x;
dy = p1.y - p2.y;
dz = p1.z - p2.z;
r = sqrtf(dx * dx + dy * dy + dz * dz + EPS2);
p += p1.w / r;
}
targetGlob[tx] = p;
}
int main() {
float4 *sourceHost,*sourceDevc;
float *targetHost,*targetDevc;
// Allocate memory on host and device
sourceHost = (float4*) malloc( N*sizeof(float4) );
targetHost = (float *) malloc( N*sizeof(float ) );
hipMalloc( (void**) &sourceDevc, N*sizeof(float4) );
hipMalloc( (void**) &targetDevc, N*sizeof(float ) );
// Initialize
for( int i=0; i<N; i++ ) {
sourceHost[i].x = rand()/(1.+RAND_MAX);
sourceHost[i].y = rand()/(1.+RAND_MAX);
sourceHost[i].z = rand()/(1.+RAND_MAX);
sourceHost[i].w = 1.0/N;
}
// Direct summation on device
hipMemcpy(sourceDevc,sourceHost,N*sizeof(float4),hipMemcpyHostToDevice);
double start = get_time();
direct_sh<<< int(N-0.5/THREADS)+1, THREADS >>>(sourceDevc,targetDevc);
double stop = get_time();
hipMemcpy(targetHost,targetDevc,N*sizeof(float ),hipMemcpyDeviceToHost);
double time = stop - start;
std::cout<<"Kernel execution time: "<<time<<std::endl;
// Direct summation on host
float dx,dy,dz,r;
for( int i=0; i<N; i++ ) {
float p = - sourceHost[i].w / sqrtf(EPS2);
for( int j=0; j<N; j++ ) {
dx = sourceHost[i].x - sourceHost[j].x;
dy = sourceHost[i].y - sourceHost[j].y;
dz = sourceHost[i].z - sourceHost[j].z;
r = sqrtf(dx * dx + dy * dy + dz * dz + EPS2);
p += sourceHost[j].w / r;
}
printf("%d %f %f\n",i,p,targetHost[i]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9direct_shP15HIP_vector_typeIfLj4EEPf
.globl _Z9direct_shP15HIP_vector_typeIfLj4EEPf
.p2align 8
.type _Z9direct_shP15HIP_vector_typeIfLj4EEPf,@function
_Z9direct_shP15HIP_vector_typeIfLj4EEPf:
s_load_b64 s[6:7], s[0:1], 0x0
v_mad_u64_u32 v[5:6], null, s15, 12, v[0:1]
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[1:2], 4, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b128 v[1:4], v[1:2], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v7, null, 0xbc23d70a, 0xbc23d70a, v4
v_div_scale_f32 v10, vcc_lo, v4, 0xbc23d70a, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v8, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v7, v8, 1.0
v_fmac_f32_e32 v8, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, v10, v8
v_fma_f32 v11, -v7, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v11, v8
v_fma_f32 v7, -v7, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v8, v7, v8, v9
v_lshlrev_b32_e32 v7, 4, v0
v_div_fixup_f32 v9, v8, 0xbc23d70a, v4
v_mov_b32_e32 v8, 0
.LBB0_1:
v_mad_u64_u32 v[10:11], null, s8, 12, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mov_b32_e32 v11, v8
s_mov_b32 s9, 0
v_lshlrev_b64 v[10:11], 4, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
global_load_b128 v[11:14], v[10:11], off
v_mov_b32_e32 v10, v9
s_waitcnt vmcnt(0)
ds_store_b128 v7, v[11:14]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB0_3
.LBB0_2:
s_branch .LBB0_5
.LBB0_3:
v_mov_b32_e32 v9, s9
s_cmpk_eq_i32 s9, 0xa0
ds_load_2addr_b32 v[11:12], v9 offset1:1
ds_load_2addr_b32 v[13:14], v9 offset0:5 offset1:6
ds_load_2addr_b32 v[15:16], v9 offset0:2 offset1:4
s_waitcnt lgkmcnt(2)
v_sub_f32_e32 v9, v2, v12
s_waitcnt lgkmcnt(1)
v_dual_sub_f32 v12, v2, v13 :: v_dual_sub_f32 v11, v1, v11
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v13, v3, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v9, v9, v9 :: v_dual_mul_f32 v12, v12, v12
v_fmac_f32_e32 v9, v11, v11
v_sub_f32_e32 v11, v1, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, v13, v13
v_sub_f32_e32 v13, v3, v14
v_dual_fmac_f32 v12, v11, v11 :: v_dual_add_f32 v9, 0x38d1b717, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v12, v13, v13
v_mul_f32_e32 v11, 0x4f800000, v9
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v12, 0x38d1b717, v12 :: v_dual_cndmask_b32 v9, v9, v11
v_mul_f32_e32 v11, 0x4f800000, v12
v_cmp_gt_f32_e64 s2, 0xf800000, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sqrt_f32_e32 v13, v9
v_cndmask_b32_e64 v11, v12, v11, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v12, v11
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v14, -1, v13
v_add_nc_u32_e32 v15, 1, v13
v_fma_f32 v16, -v14, v13, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v18, -v15, v13, v9
v_add_nc_u32_e32 v17, -1, v12
v_cmp_ge_f32_e64 s3, 0, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v16, -v17, v12, v11
v_cndmask_b32_e64 v13, v13, v14, s3
v_add_nc_u32_e32 v14, 1, v12
v_cmp_lt_f32_e64 s3, 0, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v13, v13, v15, s3
v_fma_f32 v15, -v14, v12, v11
v_cmp_ge_f32_e64 s3, 0, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v16, 0x37800000, v13
v_cndmask_b32_e64 v12, v12, v17, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_f32_e64 s3, 0, v15
v_cndmask_b32_e32 v13, v13, v16, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v9, 0x260
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v12, v12, v14, s3
v_cndmask_b32_e32 v9, v13, v9, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v11, 0x260
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v14, 0x37800000, v12
v_div_scale_f32 v13, null, v9, v9, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v12, v12, v14, s2
v_cndmask_b32_e32 v11, v12, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v12, v13
v_div_scale_f32 v17, vcc_lo, v4, v9, v4
v_div_scale_f32 v14, null, v11, v11, v4
v_div_scale_f32 v19, s2, v4, v11, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v15, v14
s_waitcnt_depctr 0xfff
v_fma_f32 v16, -v13, v12, 1.0
v_fmac_f32_e32 v12, v16, v12
v_fma_f32 v16, -v14, v15, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v18, v17, v12 :: v_dual_fmac_f32 v15, v16, v15
v_fma_f32 v16, -v13, v18, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v20, v19, v15
v_fmac_f32_e32 v18, v16, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v16, -v14, v20, v19
v_fma_f32 v13, -v13, v18, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v20, v16, v15
v_div_fmas_f32 v12, v13, v12, v18
s_mov_b32 vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v13, -v14, v20, v19
v_div_fixup_f32 v9, v12, v9, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f32 v12, v13, v15, v20
v_add_f32_e32 v9, v10, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v10, v12, v11, v4
v_add_f32_e32 v9, v9, v10
s_cbranch_scc1 .LBB0_2
v_mov_b32_e32 v10, s9
s_addk_i32 s9, 0xa0
ds_load_2addr_b32 v[11:12], v10 offset0:8 offset1:9
ds_load_2addr_b32 v[13:14], v10 offset0:10 offset1:12
ds_load_2addr_b32 v[15:16], v10 offset0:13 offset1:14
ds_load_2addr_b32 v[17:18], v10 offset0:16 offset1:17
ds_load_2addr_b32 v[19:20], v10 offset0:18 offset1:20
ds_load_2addr_b32 v[21:22], v10 offset0:21 offset1:22
ds_load_2addr_b32 v[23:24], v10 offset0:26 offset1:28
s_waitcnt lgkmcnt(6)
v_dual_sub_f32 v25, v1, v11 :: v_dual_sub_f32 v26, v2, v12
s_waitcnt lgkmcnt(5)
v_sub_f32_e32 v27, v3, v13
s_waitcnt lgkmcnt(4)
v_dual_sub_f32 v13, v1, v14 :: v_dual_sub_f32 v14, v2, v15
s_waitcnt lgkmcnt(3)
v_dual_sub_f32 v28, v3, v16 :: v_dual_sub_f32 v15, v1, v17
s_waitcnt lgkmcnt(2)
v_dual_sub_f32 v16, v2, v18 :: v_dual_sub_f32 v19, v3, v19
ds_load_2addr_b32 v[11:12], v10 offset0:24 offset1:25
s_waitcnt lgkmcnt(2)
v_dual_sub_f32 v17, v2, v21 :: v_dual_sub_f32 v18, v1, v20
v_mul_f32_e32 v20, v26, v26
v_dual_mul_f32 v21, v14, v14 :: v_dual_mul_f32 v26, v16, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mul_f32 v29, v17, v17 :: v_dual_sub_f32 v22, v3, v22
v_fmac_f32_e32 v20, v25, v25
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_fmac_f32 v21, v13, v13 :: v_dual_fmac_f32 v26, v15, v15
v_fmac_f32_e32 v29, v18, v18
ds_load_2addr_b32 v[13:14], v10 offset0:29 offset1:30
ds_load_2addr_b32 v[15:16], v10 offset0:32 offset1:33
ds_load_2addr_b32 v[17:18], v10 offset0:37 offset1:38
v_dual_fmac_f32 v20, v27, v27 :: v_dual_fmac_f32 v21, v28, v28
s_waitcnt lgkmcnt(4)
v_sub_f32_e32 v23, v3, v23
v_dual_fmac_f32 v29, v22, v22 :: v_dual_fmac_f32 v26, v19, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_add_f32 v19, 0x38d1b717, v20 :: v_dual_add_f32 v20, 0x38d1b717, v21
s_waitcnt lgkmcnt(3)
v_dual_sub_f32 v11, v1, v11 :: v_dual_add_f32 v22, 0x38d1b717, v29
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_add_f32 v21, 0x38d1b717, v26 :: v_dual_sub_f32 v12, v2, v12
v_mul_f32_e32 v25, 0x4f800000, v19
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v19
s_delay_alu instid0(VALU_DEP_3)
v_dual_mul_f32 v26, 0x4f800000, v20 :: v_dual_mul_f32 v27, 0x4f800000, v21
v_mul_f32_e32 v28, 0x4f800000, v22
v_cmp_gt_f32_e64 s2, 0xf800000, v20
v_dual_cndmask_b32 v19, v19, v25 :: v_dual_mul_f32 v12, v12, v12
v_cmp_gt_f32_e64 s4, 0xf800000, v22
v_cmp_gt_f32_e64 s3, 0xf800000, v21
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v20, v20, v26, s2
v_sqrt_f32_e32 v25, v19
v_fmac_f32_e32 v12, v11, v11
v_cndmask_b32_e64 v22, v22, v28, s4
v_cndmask_b32_e64 v21, v21, v27, s3
v_sqrt_f32_e32 v26, v20
s_waitcnt lgkmcnt(0)
v_dual_sub_f32 v18, v3, v18 :: v_dual_sub_f32 v13, v2, v13
v_sqrt_f32_e32 v28, v22
v_sqrt_f32_e32 v27, v21
v_sub_f32_e32 v15, v1, v15
v_add_nc_u32_e32 v11, -1, v25
v_dual_fmac_f32 v12, v23, v23 :: v_dual_add_nc_u32 v29, 1, v25
s_delay_alu instid0(TRANS32_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v30, -1, v26
v_fma_f32 v36, -v11, v25, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_2)
v_fma_f32 v37, -v29, v25, v19
v_add_nc_u32_e32 v35, 1, v28
s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v33, 1, v27
v_fma_f32 v38, -v30, v26, v20
v_cmp_ge_f32_e64 s5, 0, v36
v_fma_f32 v41, -v33, v27, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v11, v25, v11, s5
v_cmp_ge_f32_e64 s5, 0, v38
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v25, v26, v30, s5
v_cmp_lt_f32_e64 s5, 0, v37
v_cndmask_b32_e64 v11, v11, v29, s5
v_fma_f32 v29, -v35, v28, v22
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v30, 0x37800000, v11
v_dual_cndmask_b32 v11, v11, v30 :: v_dual_add_nc_u32 v32, -1, v27
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cmp_lt_f32_e32 vcc_lo, 0, v29
v_add_nc_u32_e32 v31, 1, v26
v_add_nc_u32_e32 v34, -1, v28
v_fma_f32 v40, -v32, v27, v21
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v39, -v31, v26, v20
v_fma_f32 v26, -v34, v28, v22
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s5, 0, v39
v_cndmask_b32_e64 v25, v25, v31, s5
v_cmp_ge_f32_e64 s5, 0, v40
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v31, 0x37800000, v25
v_cndmask_b32_e64 v27, v27, v32, s5
v_cmp_ge_f32_e64 s5, 0, v26
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v25, v25, v31, s2
v_cndmask_b32_e64 v26, v28, v34, s5
v_cmp_lt_f32_e64 s5, 0, v41
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v26, v26, v35, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v19, 0x260
v_cndmask_b32_e64 v27, v27, v33, s5
v_cndmask_b32_e32 v11, v11, v19, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v20, 0x260
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v19, v25, v20 :: v_dual_mul_f32 v20, 0x37800000, v27
v_div_scale_f32 v25, null, v11, v11, v4
v_cmp_class_f32_e64 vcc_lo, v21, 0x260
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_div_scale_f32 v28, null, v19, v19, v4
v_cndmask_b32_e64 v20, v27, v20, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_rcp_f32_e32 v27, v25
v_cmp_class_f32_e64 s3, v22, 0x260
v_rcp_f32_e32 v29, v28
v_div_scale_f32 v33, s2, v4, v19, v4
v_cndmask_b32_e32 v20, v20, v21, vcc_lo
s_waitcnt_depctr 0xfff
v_fma_f32 v30, -v25, v27, 1.0
v_add_f32_e32 v12, 0x38d1b717, v12
v_fma_f32 v31, -v28, v29, 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v27, v30, v27
v_mul_f32_e32 v23, 0x37800000, v26
v_dual_fmac_f32 v29, v31, v29 :: v_dual_mul_f32 v30, 0x4f800000, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v21, v26, v23, s4
v_div_scale_f32 v23, null, v20, v20, v4
v_div_scale_f32 v26, vcc_lo, v4, v11, v4
v_cndmask_b32_e64 v21, v21, v22, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_rcp_f32_e32 v32, v23
v_div_scale_f32 v35, s3, v4, v20, v4
v_mul_f32_e32 v22, v26, v27
v_cmp_gt_f32_e64 s4, 0xf800000, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v36, -v25, v22, v26
v_cndmask_b32_e64 v12, v12, v30, s4
s_waitcnt_depctr 0xfff
v_fma_f32 v34, -v23, v32, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v31, v33, v29 :: v_dual_fmac_f32 v32, v34, v32
v_fma_f32 v37, -v28, v31, v33
v_fmac_f32_e32 v22, v36, v27
v_div_scale_f32 v34, null, v21, v21, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mul_f32 v36, v35, v32 :: v_dual_fmac_f32 v31, v37, v29
v_fma_f32 v25, -v25, v22, v26
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v30, v34
v_fma_f32 v26, -v28, v31, v33
s_delay_alu instid0(VALU_DEP_3)
v_fma_f32 v28, -v23, v36, v35
v_sqrt_f32_e32 v33, v12
v_div_fmas_f32 v22, v25, v27, v22
s_mov_b32 vcc_lo, s2
v_sub_f32_e32 v24, v1, v24
v_div_fmas_f32 v25, v26, v29, v31
v_dual_mul_f32 v13, v13, v13 :: v_dual_fmac_f32 v36, v28, v32
v_div_fixup_f32 v11, v22, v11, v4
s_mov_b32 vcc_lo, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_1)
v_div_fixup_f32 v19, v25, v19, v4
v_dual_sub_f32 v14, v3, v14 :: v_dual_add_nc_u32 v25, -1, v33
s_delay_alu instid0(VALU_DEP_3)
v_dual_fmac_f32 v13, v24, v24 :: v_dual_add_f32 v22, v9, v11
v_fma_f32 v23, -v23, v36, v35
ds_load_2addr_b32 v[10:11], v10 offset0:34 offset1:36
v_fma_f32 v24, -v34, v30, 1.0
v_fmac_f32_e32 v13, v14, v14
v_cmp_class_f32_e64 s3, v12, 0x260
v_div_fmas_f32 v14, v23, v32, v36
v_fma_f32 v23, -v25, v33, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_dual_fmac_f32 v30, v24, v30 :: v_dual_add_f32 v13, 0x38d1b717, v13
v_add_nc_u32_e32 v24, 1, v33
v_div_fixup_f32 v14, v14, v20, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_ge_f32_e32 vcc_lo, 0, v23
v_sub_f32_e32 v16, v2, v16
v_fma_f32 v26, -v24, v33, v12
v_cndmask_b32_e32 v23, v33, v25, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_dual_mul_f32 v25, 0x4f800000, v13 :: v_dual_mul_f32 v16, v16, v16
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v13
v_cmp_lt_f32_e64 s2, 0, v26
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v10, v3, v10
v_dual_fmac_f32 v16, v15, v15 :: v_dual_sub_f32 v15, v2, v17
v_cndmask_b32_e32 v13, v13, v25, vcc_lo
v_cndmask_b32_e64 v17, v23, v24, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v16, v10, v10
v_sub_f32_e32 v10, v1, v11
v_sqrt_f32_e32 v23, v13
v_mul_f32_e32 v11, v15, v15
v_div_scale_f32 v15, s2, v4, v21, v4
v_add_f32_e32 v16, 0x38d1b717, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f32_e32 v25, 0x4f800000, v16
v_dual_mul_f32 v24, 0x37800000, v17 :: v_dual_fmac_f32 v11, v10, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v10, v15, v30
v_cndmask_b32_e64 v17, v17, v24, s4
s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_3)
v_dual_fmac_f32 v11, v18, v18 :: v_dual_add_nc_u32 v24, -1, v23
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v12, v17, v12, s3
v_fma_f32 v17, -v24, v23, v13
v_cmp_gt_f32_e64 s3, 0xf800000, v16
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f32_e32 v11, 0x38d1b717, v11
v_div_scale_f32 v18, null, v12, v12, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v16, v16, v25, s3
v_add_nc_u32_e32 v25, 1, v23
v_cmp_ge_f32_e64 s4, 0, v17
v_sqrt_f32_e32 v26, v16
v_add_f32_e32 v19, v22, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v17, v23, v24, s4
v_fma_f32 v23, -v25, v23, v13
v_cmp_gt_f32_e64 s4, 0xf800000, v11
v_fma_f32 v24, -v34, v10, v15
v_mul_f32_e32 v27, 0x4f800000, v11
v_cmp_lt_f32_e64 s5, 0, v23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v10, v24, v30
v_cndmask_b32_e64 v11, v11, v27, s4
v_add_nc_u32_e32 v28, 1, v26
s_delay_alu instid0(VALU_DEP_4)
v_cndmask_b32_e64 v17, v17, v25, s5
v_add_nc_u32_e32 v25, -1, v26
v_rcp_f32_e32 v27, v18
v_sqrt_f32_e32 v23, v11
v_fma_f32 v15, -v34, v10, v15
v_mul_f32_e32 v20, 0x37800000, v17
v_fma_f32 v22, -v25, v26, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v17, v17, v20, vcc_lo
v_cmp_ge_f32_e32 vcc_lo, 0, v22
s_delay_alu instid0(TRANS32_DEP_2)
v_fma_f32 v24, -v18, v27, 1.0
v_cndmask_b32_e32 v22, v26, v25, vcc_lo
v_fma_f32 v25, -v28, v26, v16
v_cmp_class_f32_e64 vcc_lo, v13, 0x260
v_add_nc_u32_e32 v20, -1, v23
v_add_nc_u32_e32 v26, 1, v23
v_fmac_f32_e32 v27, v24, v27
v_cndmask_b32_e32 v13, v17, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v17, -v20, v23, v11
v_cmp_lt_f32_e32 vcc_lo, 0, v25
v_div_scale_f32 v25, null, v13, v13, v4
v_cndmask_b32_e32 v22, v22, v28, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_cmp_ge_f32_e32 vcc_lo, 0, v17
v_fma_f32 v28, -v26, v23, v11
v_cndmask_b32_e32 v17, v23, v20, vcc_lo
v_rcp_f32_e32 v23, v25
v_cmp_lt_f32_e32 vcc_lo, 0, v28
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v17, v17, v26, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v16, 0x260
s_waitcnt_depctr 0xfff
v_fma_f32 v26, -v25, v23, 1.0
v_dual_mul_f32 v20, 0x37800000, v22 :: v_dual_fmac_f32 v23, v26, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v20, v22, v20, s3
v_div_scale_f32 v22, s3, v4, v12, v4
v_cndmask_b32_e32 v16, v20, v16, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v11, 0x260
v_mul_f32_e32 v24, 0x37800000, v17
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v20, v22, v27
v_cndmask_b32_e64 v17, v17, v24, s4
v_div_scale_f32 v24, null, v16, v16, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f32 v28, -v18, v20, v22
v_div_scale_f32 v26, s4, v4, v13, v4
v_cndmask_b32_e32 v11, v17, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_rcp_f32_e32 v17, v24
s_mov_b32 vcc_lo, s2
v_fmac_f32_e32 v20, v28, v27
v_div_fmas_f32 v10, v15, v30, v10
v_div_scale_f32 v29, null, v11, v11, v4
v_mul_f32_e32 v28, v26, v23
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v18, -v18, v20, v22
v_div_fixup_f32 v10, v10, v21, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(TRANS32_DEP_2)
v_rcp_f32_e32 v15, v29
v_fma_f32 v30, -v24, v17, 1.0
v_div_scale_f32 v21, s2, v4, v16, v4
s_mov_b32 vcc_lo, s3
s_delay_alu instid0(VALU_DEP_2)
v_fmac_f32_e32 v17, v30, v17
v_div_fmas_f32 v18, v18, v27, v20
s_mov_b32 vcc_lo, s4
s_waitcnt_depctr 0xfff
v_fma_f32 v22, -v29, v15, 1.0
v_add_f32_e32 v14, v19, v14
v_fma_f32 v19, -v25, v28, v26
v_mul_f32_e32 v20, v21, v17
v_div_fixup_f32 v12, v18, v12, v4
v_fmac_f32_e32 v15, v22, v15
v_add_f32_e32 v10, v14, v10
v_fmac_f32_e32 v28, v19, v23
v_div_scale_f32 v19, s3, v4, v11, v4
v_fma_f32 v22, -v24, v20, v21
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f32_e32 v10, v10, v12
v_fma_f32 v14, -v25, v28, v26
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f32_e32 v18, v19, v15
v_fmac_f32_e32 v20, v22, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fmas_f32 v14, v14, v23, v28
v_fma_f32 v22, -v29, v18, v19
s_mov_b32 vcc_lo, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v12, -v24, v20, v21
v_div_fixup_f32 v13, v14, v13, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v18, v22, v15
v_div_fmas_f32 v12, v12, v17, v20
s_mov_b32 vcc_lo, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v10, v10, v13
v_fma_f32 v14, -v29, v18, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v12, v12, v16, v4
v_div_fmas_f32 v13, v14, v15, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v10, v10, v12
v_div_fixup_f32 v11, v13, v11, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v10, v10, v11
s_cbranch_execnz .LBB0_3
.LBB0_5:
s_add_i32 s2, s8, 1
s_cmp_lg_u32 s8, 0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
s_mov_b32 s8, s2
s_branch .LBB0_1
.LBB0_7:
v_lshlrev_b32_e32 v0, 4, v0
s_mov_b32 s3, 0
global_load_b128 v[10:13], v0, s[6:7] offset:384
s_waitcnt vmcnt(0)
ds_store_b128 v0, v[10:13]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_8:
v_mov_b32_e32 v0, s3
s_add_i32 s3, s3, 16
ds_load_2addr_b32 v[7:8], v0 offset1:1
ds_load_b32 v0, v0 offset:8
s_cmpk_eq_i32 s3, 0x80
s_waitcnt lgkmcnt(1)
v_dual_sub_f32 v7, v1, v7 :: v_dual_sub_f32 v8, v2, v8
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v8, v8
v_fmac_f32_e32 v8, v7, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v0, v0
v_add_f32_e32 v0, 0x38d1b717, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v7, 0x4f800000, v0
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
v_cndmask_b32_e32 v0, v0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v7, v0
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v8, -1, v7
v_add_nc_u32_e32 v10, 1, v7
v_fma_f32 v11, -v8, v7, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v12, -v10, v7, v0
v_cmp_ge_f32_e64 s2, 0, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v7, v7, v8, s2
v_cmp_lt_f32_e64 s2, 0, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, v7, v10, s2
v_mul_f32_e32 v8, 0x37800000, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v7, v7, v8, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x260
v_cndmask_b32_e32 v0, v7, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v7, null, v0, v0, v4
v_div_scale_f32 v11, vcc_lo, v4, v0, v4
v_rcp_f32_e32 v8, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v10, -v7, v8, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v10, v8
v_mul_f32_e32 v10, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, -v7, v10, v11
v_fmac_f32_e32 v10, v12, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v7, v10, v11
v_div_fmas_f32 v7, v7, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v0, v7, v0, v4
v_add_f32_e32 v9, v9, v0
s_cbranch_scc0 .LBB0_8
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v9, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9direct_shP15HIP_vector_typeIfLj4EEPf
.amdhsa_group_segment_fixed_size 192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 42
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9direct_shP15HIP_vector_typeIfLj4EEPf, .Lfunc_end0-_Z9direct_shP15HIP_vector_typeIfLj4EEPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6directP15HIP_vector_typeIfLj4EEPf
.globl _Z6directP15HIP_vector_typeIfLj4EEPf
.p2align 8
.type _Z6directP15HIP_vector_typeIfLj4EEPf,@function
_Z6directP15HIP_vector_typeIfLj4EEPf:
s_load_b64 s[4:5], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 4, v0
s_mov_b64 s[6:7], 0
s_waitcnt lgkmcnt(0)
global_load_b128 v[1:4], v1, s[4:5]
s_waitcnt vmcnt(0)
v_div_scale_f32 v5, null, 0xbc23d70a, 0xbc23d70a, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
v_fmac_f32_e32 v6, v7, v6
v_div_scale_f32 v7, vcc_lo, v4, 0xbc23d70a, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v7, v6
v_fma_f32 v9, -v5, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v9, v6
v_fma_f32 v5, -v5, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v5, v5, v6, v8
v_div_fixup_f32 v5, v5, 0xbc23d70a, v4
.LBB1_1:
s_add_u32 s2, s4, s6
s_addc_u32 s3, s5, s7
s_add_u32 s6, s6, 16
s_clause 0x1
s_load_b64 s[8:9], s[2:3], 0x0
s_load_b32 s2, s[2:3], 0x8
s_addc_u32 s7, s7, 0
s_cmpk_eq_i32 s6, 0x200
s_waitcnt lgkmcnt(0)
v_dual_subrev_f32 v6, s9, v2 :: v_dual_subrev_f32 v7, s8, v1
v_subrev_f32_e32 v8, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v6, v6
v_fmac_f32_e32 v6, v7, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v8
v_add_f32_e32 v6, 0x38d1b717, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v7, 0x4f800000, v6
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v6
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v8, -1, v7
v_add_nc_u32_e32 v9, 1, v7
v_fma_f32 v10, -v8, v7, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v11, -v9, v7, v6
v_cmp_ge_f32_e64 s2, 0, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v7, v7, v8, s2
v_cmp_lt_f32_e64 s2, 0, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, v7, v9, s2
v_mul_f32_e32 v8, 0x37800000, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v7, v7, v8, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v6, 0x260
v_cndmask_b32_e32 v6, v7, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v7, null, v6, v6, v4
v_div_scale_f32 v10, vcc_lo, v4, v6, v4
v_rcp_f32_e32 v8, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v7, v8, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v9, v8
v_mul_f32_e32 v9, v10, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v11, -v7, v9, v10
v_fmac_f32_e32 v9, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v7, v9, v10
v_div_fmas_f32 v7, v7, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v6, v7, v6, v4
v_add_f32_e32 v5, v5, v6
s_cbranch_scc0 .LBB1_1
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v5, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6directP15HIP_vector_typeIfLj4EEPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z6directP15HIP_vector_typeIfLj4EEPf, .Lfunc_end1-_Z6directP15HIP_vector_typeIfLj4EEPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 192
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9direct_shP15HIP_vector_typeIfLj4EEPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9direct_shP15HIP_vector_typeIfLj4EEPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 42
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6directP15HIP_vector_typeIfLj4EEPf
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z6directP15HIP_vector_typeIfLj4EEPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
int const N = 32;
int const THREADS = 12;
int const BSZ = 3;
float const EPS2 = 0.0001;
double get_time()
{ struct timeval tim;
hipDeviceSynchronize();
gettimeofday(&tim, NULL);
return (double) tim.tv_sec+(tim.tv_usec/1000000.0);
}
__global__ void direct_sh(float4 *sourceGlob, float *targetGlob)
{
__shared__ float4 p_sh[THREADS];
int tx = threadIdx.x;
int bx = blockIdx.x;
int I = bx * THREADS + tx;
float dx,dy,dz,r;
float4 p1 = sourceGlob[I];
float p = - p1.w/ sqrtf(EPS2);
float4 p2;
for (unsigned int m = 0; m < BSZ-1; m++ ){
p_sh[tx] = sourceGlob[m * THREADS + tx];
__syncthreads();
#pragma unroll 10
for (unsigned int i = 0; i < THREADS; i++){
p2 = p_sh[i];
dx = p1.x - p2.x;
dy = p1.y - p2.y;
dz = p1.z - p2.z;
r = sqrtf(dx * dx + dy * dy + dz * dz + EPS2);
p += p1.w / r;
}
__syncthreads();
}
int m = BSZ-1;
p_sh[tx] = sourceGlob[m*THREADS + tx];
__syncthreads();
int lastDim = N%THREADS;
for ( unsigned int i = 0; i < lastDim; i++){
p2 = p_sh[i];
dx = p1.x - p2.x;
dy = p1.y - p2.y;
dz = p1.z - p2.z;
r = sqrtf(dx * dx + dy * dy + dz * dz + EPS2);
p += p1.w / r;
}
__syncthreads();
targetGlob[I] = p;
}
__global__ void direct(float4 *sourceGlob, float *targetGlob)
{ /*** wirte your kernel here! *****/
int tx = threadIdx.x;
float dx,dy,dz,r;
float4 p1,p2;
p1 = sourceGlob[tx];
float p = - p1.w / sqrtf(EPS2);
for ( int j = 0; j < N; j++ ){
p2 = sourceGlob[j];
dx = p1.x - p2.x;
dy = p1.y - p2.y;
dz = p1.z - p2.z;
r = sqrtf(dx * dx + dy * dy + dz * dz + EPS2);
p += p1.w / r;
}
targetGlob[tx] = p;
}
int main() {
float4 *sourceHost,*sourceDevc;
float *targetHost,*targetDevc;
// Allocate memory on host and device
sourceHost = (float4*) malloc( N*sizeof(float4) );
targetHost = (float *) malloc( N*sizeof(float ) );
hipMalloc( (void**) &sourceDevc, N*sizeof(float4) );
hipMalloc( (void**) &targetDevc, N*sizeof(float ) );
// Initialize
for( int i=0; i<N; i++ ) {
sourceHost[i].x = rand()/(1.+RAND_MAX);
sourceHost[i].y = rand()/(1.+RAND_MAX);
sourceHost[i].z = rand()/(1.+RAND_MAX);
sourceHost[i].w = 1.0/N;
}
// Direct summation on device
hipMemcpy(sourceDevc,sourceHost,N*sizeof(float4),hipMemcpyHostToDevice);
double start = get_time();
direct_sh<<< int(N-0.5/THREADS)+1, THREADS >>>(sourceDevc,targetDevc);
double stop = get_time();
hipMemcpy(targetHost,targetDevc,N*sizeof(float ),hipMemcpyDeviceToHost);
double time = stop - start;
std::cout<<"Kernel execution time: "<<time<<std::endl;
// Direct summation on host
float dx,dy,dz,r;
for( int i=0; i<N; i++ ) {
float p = - sourceHost[i].w / sqrtf(EPS2);
for( int j=0; j<N; j++ ) {
dx = sourceHost[i].x - sourceHost[j].x;
dy = sourceHost[i].y - sourceHost[j].y;
dz = sourceHost[i].z - sourceHost[j].z;
r = sqrtf(dx * dx + dy * dy + dz * dz + EPS2);
p += sourceHost[j].w / r;
}
printf("%d %f %f\n",i,p,targetHost[i]);
}
} | .text
.file "lab8_nbody.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8get_timev
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z8get_timev
.p2align 4, 0x90
.type _Z8get_timev,@function
_Z8get_timev: # @_Z8get_timev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
callq hipDeviceSynchronize
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
divsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z8get_timev, .Lfunc_end0-_Z8get_timev
.cfi_endproc
# -- End function
.globl _Z24__device_stub__direct_shP15HIP_vector_typeIfLj4EEPf # -- Begin function _Z24__device_stub__direct_shP15HIP_vector_typeIfLj4EEPf
.p2align 4, 0x90
.type _Z24__device_stub__direct_shP15HIP_vector_typeIfLj4EEPf,@function
_Z24__device_stub__direct_shP15HIP_vector_typeIfLj4EEPf: # @_Z24__device_stub__direct_shP15HIP_vector_typeIfLj4EEPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9direct_shP15HIP_vector_typeIfLj4EEPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z24__device_stub__direct_shP15HIP_vector_typeIfLj4EEPf, .Lfunc_end1-_Z24__device_stub__direct_shP15HIP_vector_typeIfLj4EEPf
.cfi_endproc
# -- End function
.globl _Z21__device_stub__directP15HIP_vector_typeIfLj4EEPf # -- Begin function _Z21__device_stub__directP15HIP_vector_typeIfLj4EEPf
.p2align 4, 0x90
.type _Z21__device_stub__directP15HIP_vector_typeIfLj4EEPf,@function
_Z21__device_stub__directP15HIP_vector_typeIfLj4EEPf: # @_Z21__device_stub__directP15HIP_vector_typeIfLj4EEPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6directP15HIP_vector_typeIfLj4EEPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z21__device_stub__directP15HIP_vector_typeIfLj4EEPf, .Lfunc_end2-_Z21__device_stub__directP15HIP_vector_typeIfLj4EEPf
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3e00000000000000 # double 4.6566128730773926E-10
.LCPI3_1:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_2:
.long 0xbc23d70a # float -0.00999999977
.LCPI3_3:
.long 0x38d1b717 # float 9.99999974E-5
.LCPI3_4:
.long 0x00000000 # float 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $512, %edi # imm = 0x200
callq malloc
movq %rax, %rbx
movl $128, %edi
callq malloc
movq %rax, %r14
leaq 40(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
leaq 32(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movl $12, %r15d
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, -12(%rbx,%r15)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI3_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, -8(%rbx,%r15)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI3_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, -4(%rbx,%r15)
movl $1023410176, (%rbx,%r15) # imm = 0x3D000000
addq $16, %r15
cmpq $524, %r15 # imm = 0x20C
jne .LBB3_1
# %bb.2:
movq 40(%rsp), %rdi
movl $512, %edx # imm = 0x200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 24(%rsp), %xmm1
divsd .LCPI3_1(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
movabsq $4294967308, %rdx # imm = 0x10000000C
leaq 20(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 16(%rsp)
leaq 96(%rsp), %rax
movq %rax, 24(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9direct_shP15HIP_vector_typeIfLj4EEPf, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 24(%rsp), %xmm1
divsd .LCPI3_1(%rip), %xmm1
addsd %xmm0, %xmm1
subsd 8(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 8(%rsp) # 8-byte Spill
movq 32(%rsp), %rsi
movl $128, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB3_16
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB3_7
# %bb.6:
movzbl 67(%r15), %ecx
jmp .LBB3_8
.LBB3_7:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB3_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r15d, %r15d
jmp .LBB3_9
.p2align 4, 0x90
.LBB3_12: # in Loop: Header=BB3_9 Depth=1
xorps %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
movss (%r14,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.1, %edi
movl %r15d, %esi
movb $2, %al
callq printf
incq %r15
cmpq $32, %r15
je .LBB3_13
.LBB3_9: # =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
movq %r15, %rax
shlq $4, %rax
leaq (%rbx,%rax), %r12
movss 12(%rbx,%rax), %xmm3 # xmm3 = mem[0],zero,zero,zero
divss .LCPI3_2(%rip), %xmm3
xorl %r13d, %r13d
jmp .LBB3_10
.p2align 4, 0x90
.LBB3_14: # %call.sqrt
# in Loop: Header=BB3_10 Depth=2
movss %xmm3, 8(%rsp) # 4-byte Spill
callq sqrtf
movss 8(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
.LBB3_15: # %.split
# in Loop: Header=BB3_10 Depth=2
movss 12(%rbx,%r13), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
addss %xmm1, %xmm3
addq $16, %r13
cmpq $512, %r13 # imm = 0x200
je .LBB3_12
.LBB3_10: # Parent Loop BB3_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss 4(%r12), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%rbx,%r13), %xmm1
subss 4(%rbx,%r13), %xmm2
movss 8(%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss 8(%rbx,%r13), %xmm0
mulss %xmm1, %xmm1
mulss %xmm2, %xmm2
addss %xmm1, %xmm2
mulss %xmm0, %xmm0
addss %xmm2, %xmm0
addss .LCPI3_3(%rip), %xmm0
ucomiss .LCPI3_4(%rip), %xmm0
jb .LBB3_14
# %bb.11: # in Loop: Header=BB3_10 Depth=2
sqrtss %xmm0, %xmm0
jmp .LBB3_15
.LBB3_13:
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_16:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9direct_shP15HIP_vector_typeIfLj4EEPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6directP15HIP_vector_typeIfLj4EEPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9direct_shP15HIP_vector_typeIfLj4EEPf,@object # @_Z9direct_shP15HIP_vector_typeIfLj4EEPf
.section .rodata,"a",@progbits
.globl _Z9direct_shP15HIP_vector_typeIfLj4EEPf
.p2align 3, 0x0
_Z9direct_shP15HIP_vector_typeIfLj4EEPf:
.quad _Z24__device_stub__direct_shP15HIP_vector_typeIfLj4EEPf
.size _Z9direct_shP15HIP_vector_typeIfLj4EEPf, 8
.type _Z6directP15HIP_vector_typeIfLj4EEPf,@object # @_Z6directP15HIP_vector_typeIfLj4EEPf
.globl _Z6directP15HIP_vector_typeIfLj4EEPf
.p2align 3, 0x0
_Z6directP15HIP_vector_typeIfLj4EEPf:
.quad _Z21__device_stub__directP15HIP_vector_typeIfLj4EEPf
.size _Z6directP15HIP_vector_typeIfLj4EEPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Kernel execution time: "
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d %f %f\n"
.size .L.str.1, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9direct_shP15HIP_vector_typeIfLj4EEPf"
.size .L__unnamed_1, 40
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6directP15HIP_vector_typeIfLj4EEPf"
.size .L__unnamed_2, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__direct_shP15HIP_vector_typeIfLj4EEPf
.addrsig_sym _Z21__device_stub__directP15HIP_vector_typeIfLj4EEPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9direct_shP15HIP_vector_typeIfLj4EEPf
.addrsig_sym _Z6directP15HIP_vector_typeIfLj4EEPf
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00151afe_00000000-6_lab8_nbody.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8get_timev
.type _Z8get_timev, @function
_Z8get_timev:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
call cudaThreadSynchronize@PLT
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z8get_timev, .-_Z8get_timev
.globl _Z36__device_stub__Z9direct_shP6float4PfP6float4Pf
.type _Z36__device_stub__Z9direct_shP6float4PfP6float4Pf, @function
_Z36__device_stub__Z9direct_shP6float4PfP6float4Pf:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9direct_shP6float4Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z36__device_stub__Z9direct_shP6float4PfP6float4Pf, .-_Z36__device_stub__Z9direct_shP6float4PfP6float4Pf
.globl _Z9direct_shP6float4Pf
.type _Z9direct_shP6float4Pf, @function
_Z9direct_shP6float4Pf:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z9direct_shP6float4PfP6float4Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z9direct_shP6float4Pf, .-_Z9direct_shP6float4Pf
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Kernel execution time: "
.LC7:
.string "%d %f %f\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $512, %edi
call malloc@PLT
movq %rax, %r13
movl $128, %edi
call malloc@PLT
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 512(%r13), %rbx
movq %r13, %rbp
movl .LC2(%rip), %r12d
.L16:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 4(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 8(%rbp)
movl %r12d, 12(%rbp)
addq $16, %rbp
cmpq %rbx, %rbp
jne .L16
movl $1, %ecx
movl $512, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call _Z8get_timev
movsd %xmm0, (%rsp)
movl $12, 44(%rsp)
movl $1, 48(%rsp)
movl $32, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L17:
call _Z8get_timev
movsd %xmm0, 8(%rsp)
movl $2, %ecx
movl $128, %edx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movsd 8(%rsp), %xmm7
subsd (%rsp), %xmm7
movq %xmm7, %rbp
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %rbp
movl $0, %r12d
leaq .LC7(%rip), %r15
.L19:
movl %r12d, %edx
movss 12(%rbp), %xmm0
xorps .LC4(%rip), %xmm0
divss .LC5(%rip), %xmm0
movss 0(%rbp), %xmm6
movss 4(%rbp), %xmm5
movss 8(%rbp), %xmm4
movq %r13, %rax
.L18:
movaps %xmm6, %xmm1
subss (%rax), %xmm1
movaps %xmm5, %xmm3
subss 4(%rax), %xmm3
movaps %xmm4, %xmm2
subss 8(%rax), %xmm2
mulss %xmm1, %xmm1
mulss %xmm3, %xmm3
addss %xmm3, %xmm1
mulss %xmm2, %xmm2
addss %xmm2, %xmm1
addss .LC6(%rip), %xmm1
sqrtss %xmm1, %xmm1
movss 12(%rax), %xmm2
divss %xmm1, %xmm2
addss %xmm2, %xmm0
addq $16, %rax
cmpq %rbx, %rax
jne .L18
cvtss2sd %xmm0, %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%r14,%r12,4), %xmm1
movq %r15, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $1, %r12
addq $16, %rbp
cmpq $32, %r12
jne .L19
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z36__device_stub__Z9direct_shP6float4PfP6float4Pf
jmp .L17
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.globl _Z33__device_stub__Z6directP6float4PfP6float4Pf
.type _Z33__device_stub__Z6directP6float4PfP6float4Pf, @function
_Z33__device_stub__Z6directP6float4PfP6float4Pf:
.LFB3697:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6directP6float4Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z33__device_stub__Z6directP6float4PfP6float4Pf, .-_Z33__device_stub__Z6directP6float4PfP6float4Pf
.globl _Z6directP6float4Pf
.type _Z6directP6float4Pf, @function
_Z6directP6float4Pf:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z6directP6float4PfP6float4Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z6directP6float4Pf, .-_Z6directP6float4Pf
.section .rodata.str1.1
.LC8:
.string "_Z6directP6float4Pf"
.LC9:
.string "_Z9direct_shP6float4Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z6directP6float4Pf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z9direct_shP6float4Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.align 8
.LC1:
.long 0
.long 1040187392
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1023410176
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long -2147483648
.long 0
.long 0
.long 0
.section .rodata.cst4
.align 4
.LC5:
.long 1008981770
.align 4
.LC6:
.long 953267991
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lab8_nbody.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8get_timev
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z8get_timev
.p2align 4, 0x90
.type _Z8get_timev,@function
_Z8get_timev: # @_Z8get_timev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
callq hipDeviceSynchronize
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
divsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z8get_timev, .Lfunc_end0-_Z8get_timev
.cfi_endproc
# -- End function
.globl _Z24__device_stub__direct_shP15HIP_vector_typeIfLj4EEPf # -- Begin function _Z24__device_stub__direct_shP15HIP_vector_typeIfLj4EEPf
.p2align 4, 0x90
.type _Z24__device_stub__direct_shP15HIP_vector_typeIfLj4EEPf,@function
_Z24__device_stub__direct_shP15HIP_vector_typeIfLj4EEPf: # @_Z24__device_stub__direct_shP15HIP_vector_typeIfLj4EEPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9direct_shP15HIP_vector_typeIfLj4EEPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z24__device_stub__direct_shP15HIP_vector_typeIfLj4EEPf, .Lfunc_end1-_Z24__device_stub__direct_shP15HIP_vector_typeIfLj4EEPf
.cfi_endproc
# -- End function
.globl _Z21__device_stub__directP15HIP_vector_typeIfLj4EEPf # -- Begin function _Z21__device_stub__directP15HIP_vector_typeIfLj4EEPf
.p2align 4, 0x90
.type _Z21__device_stub__directP15HIP_vector_typeIfLj4EEPf,@function
_Z21__device_stub__directP15HIP_vector_typeIfLj4EEPf: # @_Z21__device_stub__directP15HIP_vector_typeIfLj4EEPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6directP15HIP_vector_typeIfLj4EEPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z21__device_stub__directP15HIP_vector_typeIfLj4EEPf, .Lfunc_end2-_Z21__device_stub__directP15HIP_vector_typeIfLj4EEPf
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3e00000000000000 # double 4.6566128730773926E-10
.LCPI3_1:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_2:
.long 0xbc23d70a # float -0.00999999977
.LCPI3_3:
.long 0x38d1b717 # float 9.99999974E-5
.LCPI3_4:
.long 0x00000000 # float 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $512, %edi # imm = 0x200
callq malloc
movq %rax, %rbx
movl $128, %edi
callq malloc
movq %rax, %r14
leaq 40(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
leaq 32(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movl $12, %r15d
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, -12(%rbx,%r15)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI3_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, -8(%rbx,%r15)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI3_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, -4(%rbx,%r15)
movl $1023410176, (%rbx,%r15) # imm = 0x3D000000
addq $16, %r15
cmpq $524, %r15 # imm = 0x20C
jne .LBB3_1
# %bb.2:
movq 40(%rsp), %rdi
movl $512, %edx # imm = 0x200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 24(%rsp), %xmm1
divsd .LCPI3_1(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
movabsq $4294967308, %rdx # imm = 0x10000000C
leaq 20(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 16(%rsp)
leaq 96(%rsp), %rax
movq %rax, 24(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9direct_shP15HIP_vector_typeIfLj4EEPf, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 24(%rsp), %xmm1
divsd .LCPI3_1(%rip), %xmm1
addsd %xmm0, %xmm1
subsd 8(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 8(%rsp) # 8-byte Spill
movq 32(%rsp), %rsi
movl $128, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB3_16
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB3_7
# %bb.6:
movzbl 67(%r15), %ecx
jmp .LBB3_8
.LBB3_7:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB3_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r15d, %r15d
jmp .LBB3_9
.p2align 4, 0x90
.LBB3_12: # in Loop: Header=BB3_9 Depth=1
xorps %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
movss (%r14,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.1, %edi
movl %r15d, %esi
movb $2, %al
callq printf
incq %r15
cmpq $32, %r15
je .LBB3_13
.LBB3_9: # =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
movq %r15, %rax
shlq $4, %rax
leaq (%rbx,%rax), %r12
movss 12(%rbx,%rax), %xmm3 # xmm3 = mem[0],zero,zero,zero
divss .LCPI3_2(%rip), %xmm3
xorl %r13d, %r13d
jmp .LBB3_10
.p2align 4, 0x90
.LBB3_14: # %call.sqrt
# in Loop: Header=BB3_10 Depth=2
movss %xmm3, 8(%rsp) # 4-byte Spill
callq sqrtf
movss 8(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
.LBB3_15: # %.split
# in Loop: Header=BB3_10 Depth=2
movss 12(%rbx,%r13), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
addss %xmm1, %xmm3
addq $16, %r13
cmpq $512, %r13 # imm = 0x200
je .LBB3_12
.LBB3_10: # Parent Loop BB3_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss 4(%r12), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%rbx,%r13), %xmm1
subss 4(%rbx,%r13), %xmm2
movss 8(%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss 8(%rbx,%r13), %xmm0
mulss %xmm1, %xmm1
mulss %xmm2, %xmm2
addss %xmm1, %xmm2
mulss %xmm0, %xmm0
addss %xmm2, %xmm0
addss .LCPI3_3(%rip), %xmm0
ucomiss .LCPI3_4(%rip), %xmm0
jb .LBB3_14
# %bb.11: # in Loop: Header=BB3_10 Depth=2
sqrtss %xmm0, %xmm0
jmp .LBB3_15
.LBB3_13:
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_16:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9direct_shP15HIP_vector_typeIfLj4EEPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6directP15HIP_vector_typeIfLj4EEPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9direct_shP15HIP_vector_typeIfLj4EEPf,@object # @_Z9direct_shP15HIP_vector_typeIfLj4EEPf
.section .rodata,"a",@progbits
.globl _Z9direct_shP15HIP_vector_typeIfLj4EEPf
.p2align 3, 0x0
_Z9direct_shP15HIP_vector_typeIfLj4EEPf:
.quad _Z24__device_stub__direct_shP15HIP_vector_typeIfLj4EEPf
.size _Z9direct_shP15HIP_vector_typeIfLj4EEPf, 8
.type _Z6directP15HIP_vector_typeIfLj4EEPf,@object # @_Z6directP15HIP_vector_typeIfLj4EEPf
.globl _Z6directP15HIP_vector_typeIfLj4EEPf
.p2align 3, 0x0
_Z6directP15HIP_vector_typeIfLj4EEPf:
.quad _Z21__device_stub__directP15HIP_vector_typeIfLj4EEPf
.size _Z6directP15HIP_vector_typeIfLj4EEPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Kernel execution time: "
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d %f %f\n"
.size .L.str.1, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9direct_shP15HIP_vector_typeIfLj4EEPf"
.size .L__unnamed_1, 40
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6directP15HIP_vector_typeIfLj4EEPf"
.size .L__unnamed_2, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__direct_shP15HIP_vector_typeIfLj4EEPf
.addrsig_sym _Z21__device_stub__directP15HIP_vector_typeIfLj4EEPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9direct_shP15HIP_vector_typeIfLj4EEPf
.addrsig_sym _Z6directP15HIP_vector_typeIfLj4EEPf
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
int deviceCount;
cudaGetDeviceCount(&deviceCount);
if (deviceCount == 0)
printf("There is no device supporting CUDA\n");
int dev;
for (dev = 0; dev < deviceCount; ++dev)
{
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
if (dev == 0)
{
if (deviceProp.major == 9999 && deviceProp.minor == 9999)
printf("There is no device supporting CUDA.\n");
else if (deviceCount == 1)
printf("There is 1 device supporting CUDA\n");
else
printf("There are %d devices supporting CUDA\n", deviceCount);
}
printf("\nDevice %d: \"%s\"\n", dev, deviceProp.name);
printf(" Major revision number: %d\n",
deviceProp.major);
printf(" Minor revision number: %d\n",
deviceProp.minor);
#if CUDART_VERSION >= 2000
printf(" Number of cores: %d\n",
8 * deviceProp.multiProcessorCount);
printf(" Number of multiprocessors: %d\n",
deviceProp.multiProcessorCount);
printf(" Warp size: %d\n",
deviceProp.warpSize);
printf(" Maximum number of blocks per multiprocessor %d\n",
deviceProp.maxBlocksPerMultiProcessor);
printf(" Maximum number of threads per multiprocessor %d\n",
deviceProp.maxThreadsPerMultiProcessor);
printf(" Maximum number of threads per block: %d\n",
deviceProp.maxThreadsPerBlock);
#endif
printf(" Total amount of constant memory: %u bytes\n",
deviceProp.totalConstMem);
printf(" Total amount of global memory: %u bytes\n",
deviceProp.totalGlobalMem);
printf(" Total amount of shared memory per block: %u bytes\n",
deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n",
deviceProp.regsPerBlock);
printf(" Maximum sizes of each dimension of a block: %d x %d x %d\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of a grid: %d x %d x %d\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Maximum memory pitch: %u bytes\n",
deviceProp.memPitch);
printf(" Texture alignment: %u bytes\n",
deviceProp.textureAlignment);
printf(" Clock rate: %.2f GHz\n",
deviceProp.clockRate * 1e-6f);
#if CUDART_VERSION >= 2000
printf(" Concurrent copy and execution: %s\n",
deviceProp.deviceOverlap ? "Yes" : "No");
#endif
}
printf("\nTEST PASSED\n");
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
int deviceCount;
cudaGetDeviceCount(&deviceCount);
if (deviceCount == 0)
printf("There is no device supporting CUDA\n");
int dev;
for (dev = 0; dev < deviceCount; ++dev)
{
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
if (dev == 0)
{
if (deviceProp.major == 9999 && deviceProp.minor == 9999)
printf("There is no device supporting CUDA.\n");
else if (deviceCount == 1)
printf("There is 1 device supporting CUDA\n");
else
printf("There are %d devices supporting CUDA\n", deviceCount);
}
printf("\nDevice %d: \"%s\"\n", dev, deviceProp.name);
printf(" Major revision number: %d\n",
deviceProp.major);
printf(" Minor revision number: %d\n",
deviceProp.minor);
#if CUDART_VERSION >= 2000
printf(" Number of cores: %d\n",
8 * deviceProp.multiProcessorCount);
printf(" Number of multiprocessors: %d\n",
deviceProp.multiProcessorCount);
printf(" Warp size: %d\n",
deviceProp.warpSize);
printf(" Maximum number of blocks per multiprocessor %d\n",
deviceProp.maxBlocksPerMultiProcessor);
printf(" Maximum number of threads per multiprocessor %d\n",
deviceProp.maxThreadsPerMultiProcessor);
printf(" Maximum number of threads per block: %d\n",
deviceProp.maxThreadsPerBlock);
#endif
printf(" Total amount of constant memory: %u bytes\n",
deviceProp.totalConstMem);
printf(" Total amount of global memory: %u bytes\n",
deviceProp.totalGlobalMem);
printf(" Total amount of shared memory per block: %u bytes\n",
deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n",
deviceProp.regsPerBlock);
printf(" Maximum sizes of each dimension of a block: %d x %d x %d\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of a grid: %d x %d x %d\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Maximum memory pitch: %u bytes\n",
deviceProp.memPitch);
printf(" Texture alignment: %u bytes\n",
deviceProp.textureAlignment);
printf(" Clock rate: %.2f GHz\n",
deviceProp.clockRate * 1e-6f);
#if CUDART_VERSION >= 2000
printf(" Concurrent copy and execution: %s\n",
deviceProp.deviceOverlap ? "Yes" : "No");
#endif
}
printf("\nTEST PASSED\n");
} | .file "tmpxft_000079d1_00000000-6_cuda_info.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Yes"
.LC1:
.string "No"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "There is no device supporting CUDA\n"
.align 8
.LC3:
.string "There is no device supporting CUDA.\n"
.align 8
.LC4:
.string "There is 1 device supporting CUDA\n"
.align 8
.LC5:
.string "There are %d devices supporting CUDA\n"
.section .rodata.str1.1
.LC6:
.string "\nDevice %d: \"%s\"\n"
.section .rodata.str1.8
.align 8
.LC7:
.string " Major revision number: %d\n"
.align 8
.LC8:
.string " Minor revision number: %d\n"
.align 8
.LC9:
.string " Number of cores: %d\n"
.align 8
.LC10:
.string " Number of multiprocessors: %d\n"
.align 8
.LC11:
.string " Warp size: %d\n"
.align 8
.LC12:
.string " Maximum number of blocks per multiprocessor %d\n"
.align 8
.LC13:
.string " Maximum number of threads per multiprocessor %d\n"
.align 8
.LC14:
.string " Maximum number of threads per block: %d\n"
.align 8
.LC15:
.string " Total amount of constant memory: %u bytes\n"
.align 8
.LC16:
.string " Total amount of global memory: %u bytes\n"
.align 8
.LC17:
.string " Total amount of shared memory per block: %u bytes\n"
.align 8
.LC18:
.string " Total number of registers available per block: %d\n"
.align 8
.LC19:
.string " Maximum sizes of each dimension of a block: %d x %d x %d\n"
.align 8
.LC20:
.string " Maximum sizes of each dimension of a grid: %d x %d x %d\n"
.align 8
.LC21:
.string " Maximum memory pitch: %u bytes\n"
.align 8
.LC22:
.string " Texture alignment: %u bytes\n"
.align 8
.LC24:
.string " Clock rate: %.2f GHz\n"
.align 8
.LC25:
.string " Concurrent copy and execution: %s\n"
.section .rodata.str1.1
.LC26:
.string "\nTEST PASSED\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1064, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
je .L15
.L4:
cmpl $0, 12(%rsp)
jle .L5
movl $0, %ebx
leaq 16(%rsp), %rbp
movabsq $42945378002703, %r12
leaq .LC5(%rip), %r13
jmp .L10
.L15:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.L16:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L6
.L17:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L6:
movq %rbp, %rcx
movl %ebx, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 376(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %eax
leal 0(,%rax,8), %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 728(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 640(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 384(%rsp), %rdx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 364(%rsp), %xmm0
mulss .LC23(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $0, 400(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L5
.L10:
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
testl %ebx, %ebx
jne .L6
cmpq %r12, 376(%rsp)
je .L16
movl 12(%rsp), %edx
cmpl $1, %edx
je .L17
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L6
.L5:
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC23:
.long 897988541
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
int deviceCount;
cudaGetDeviceCount(&deviceCount);
if (deviceCount == 0)
printf("There is no device supporting CUDA\n");
int dev;
for (dev = 0; dev < deviceCount; ++dev)
{
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
if (dev == 0)
{
if (deviceProp.major == 9999 && deviceProp.minor == 9999)
printf("There is no device supporting CUDA.\n");
else if (deviceCount == 1)
printf("There is 1 device supporting CUDA\n");
else
printf("There are %d devices supporting CUDA\n", deviceCount);
}
printf("\nDevice %d: \"%s\"\n", dev, deviceProp.name);
printf(" Major revision number: %d\n",
deviceProp.major);
printf(" Minor revision number: %d\n",
deviceProp.minor);
#if CUDART_VERSION >= 2000
printf(" Number of cores: %d\n",
8 * deviceProp.multiProcessorCount);
printf(" Number of multiprocessors: %d\n",
deviceProp.multiProcessorCount);
printf(" Warp size: %d\n",
deviceProp.warpSize);
printf(" Maximum number of blocks per multiprocessor %d\n",
deviceProp.maxBlocksPerMultiProcessor);
printf(" Maximum number of threads per multiprocessor %d\n",
deviceProp.maxThreadsPerMultiProcessor);
printf(" Maximum number of threads per block: %d\n",
deviceProp.maxThreadsPerBlock);
#endif
printf(" Total amount of constant memory: %u bytes\n",
deviceProp.totalConstMem);
printf(" Total amount of global memory: %u bytes\n",
deviceProp.totalGlobalMem);
printf(" Total amount of shared memory per block: %u bytes\n",
deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n",
deviceProp.regsPerBlock);
printf(" Maximum sizes of each dimension of a block: %d x %d x %d\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of a grid: %d x %d x %d\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Maximum memory pitch: %u bytes\n",
deviceProp.memPitch);
printf(" Texture alignment: %u bytes\n",
deviceProp.textureAlignment);
printf(" Clock rate: %.2f GHz\n",
deviceProp.clockRate * 1e-6f);
#if CUDART_VERSION >= 2000
printf(" Concurrent copy and execution: %s\n",
deviceProp.deviceOverlap ? "Yes" : "No");
#endif
}
printf("\nTEST PASSED\n");
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
int deviceCount;
hipGetDeviceCount(&deviceCount);
if (deviceCount == 0)
printf("There is no device supporting CUDA\n");
int dev;
for (dev = 0; dev < deviceCount; ++dev)
{
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
if (dev == 0)
{
if (deviceProp.major == 9999 && deviceProp.minor == 9999)
printf("There is no device supporting CUDA.\n");
else if (deviceCount == 1)
printf("There is 1 device supporting CUDA\n");
else
printf("There are %d devices supporting CUDA\n", deviceCount);
}
printf("\nDevice %d: \"%s\"\n", dev, deviceProp.name);
printf(" Major revision number: %d\n",
deviceProp.major);
printf(" Minor revision number: %d\n",
deviceProp.minor);
#if CUDART_VERSION >= 2000
printf(" Number of cores: %d\n",
8 * deviceProp.multiProcessorCount);
printf(" Number of multiprocessors: %d\n",
deviceProp.multiProcessorCount);
printf(" Warp size: %d\n",
deviceProp.warpSize);
printf(" Maximum number of blocks per multiprocessor %d\n",
deviceProp.maxBlocksPerMultiProcessor);
printf(" Maximum number of threads per multiprocessor %d\n",
deviceProp.maxThreadsPerMultiProcessor);
printf(" Maximum number of threads per block: %d\n",
deviceProp.maxThreadsPerBlock);
#endif
printf(" Total amount of constant memory: %u bytes\n",
deviceProp.totalConstMem);
printf(" Total amount of global memory: %u bytes\n",
deviceProp.totalGlobalMem);
printf(" Total amount of shared memory per block: %u bytes\n",
deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n",
deviceProp.regsPerBlock);
printf(" Maximum sizes of each dimension of a block: %d x %d x %d\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of a grid: %d x %d x %d\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Maximum memory pitch: %u bytes\n",
deviceProp.memPitch);
printf(" Texture alignment: %u bytes\n",
deviceProp.textureAlignment);
printf(" Clock rate: %.2f GHz\n",
deviceProp.clockRate * 1e-6f);
#if CUDART_VERSION >= 2000
printf(" Concurrent copy and execution: %s\n",
deviceProp.deviceOverlap ? "Yes" : "No");
#endif
}
printf("\nTEST PASSED\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
int deviceCount;
hipGetDeviceCount(&deviceCount);
if (deviceCount == 0)
printf("There is no device supporting CUDA\n");
int dev;
for (dev = 0; dev < deviceCount; ++dev)
{
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
if (dev == 0)
{
if (deviceProp.major == 9999 && deviceProp.minor == 9999)
printf("There is no device supporting CUDA.\n");
else if (deviceCount == 1)
printf("There is 1 device supporting CUDA\n");
else
printf("There are %d devices supporting CUDA\n", deviceCount);
}
printf("\nDevice %d: \"%s\"\n", dev, deviceProp.name);
printf(" Major revision number: %d\n",
deviceProp.major);
printf(" Minor revision number: %d\n",
deviceProp.minor);
#if CUDART_VERSION >= 2000
printf(" Number of cores: %d\n",
8 * deviceProp.multiProcessorCount);
printf(" Number of multiprocessors: %d\n",
deviceProp.multiProcessorCount);
printf(" Warp size: %d\n",
deviceProp.warpSize);
printf(" Maximum number of blocks per multiprocessor %d\n",
deviceProp.maxBlocksPerMultiProcessor);
printf(" Maximum number of threads per multiprocessor %d\n",
deviceProp.maxThreadsPerMultiProcessor);
printf(" Maximum number of threads per block: %d\n",
deviceProp.maxThreadsPerBlock);
#endif
printf(" Total amount of constant memory: %u bytes\n",
deviceProp.totalConstMem);
printf(" Total amount of global memory: %u bytes\n",
deviceProp.totalGlobalMem);
printf(" Total amount of shared memory per block: %u bytes\n",
deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n",
deviceProp.regsPerBlock);
printf(" Maximum sizes of each dimension of a block: %d x %d x %d\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of a grid: %d x %d x %d\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Maximum memory pitch: %u bytes\n",
deviceProp.memPitch);
printf(" Texture alignment: %u bytes\n",
deviceProp.textureAlignment);
printf(" Clock rate: %.2f GHz\n",
deviceProp.clockRate * 1e-6f);
#if CUDART_VERSION >= 2000
printf(" Concurrent copy and execution: %s\n",
deviceProp.deviceOverlap ? "Yes" : "No");
#endif
}
printf("\nTEST PASSED\n");
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
int deviceCount;
hipGetDeviceCount(&deviceCount);
if (deviceCount == 0)
printf("There is no device supporting CUDA\n");
int dev;
for (dev = 0; dev < deviceCount; ++dev)
{
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
if (dev == 0)
{
if (deviceProp.major == 9999 && deviceProp.minor == 9999)
printf("There is no device supporting CUDA.\n");
else if (deviceCount == 1)
printf("There is 1 device supporting CUDA\n");
else
printf("There are %d devices supporting CUDA\n", deviceCount);
}
printf("\nDevice %d: \"%s\"\n", dev, deviceProp.name);
printf(" Major revision number: %d\n",
deviceProp.major);
printf(" Minor revision number: %d\n",
deviceProp.minor);
#if CUDART_VERSION >= 2000
printf(" Number of cores: %d\n",
8 * deviceProp.multiProcessorCount);
printf(" Number of multiprocessors: %d\n",
deviceProp.multiProcessorCount);
printf(" Warp size: %d\n",
deviceProp.warpSize);
printf(" Maximum number of blocks per multiprocessor %d\n",
deviceProp.maxBlocksPerMultiProcessor);
printf(" Maximum number of threads per multiprocessor %d\n",
deviceProp.maxThreadsPerMultiProcessor);
printf(" Maximum number of threads per block: %d\n",
deviceProp.maxThreadsPerBlock);
#endif
printf(" Total amount of constant memory: %u bytes\n",
deviceProp.totalConstMem);
printf(" Total amount of global memory: %u bytes\n",
deviceProp.totalGlobalMem);
printf(" Total amount of shared memory per block: %u bytes\n",
deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n",
deviceProp.regsPerBlock);
printf(" Maximum sizes of each dimension of a block: %d x %d x %d\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of a grid: %d x %d x %d\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Maximum memory pitch: %u bytes\n",
deviceProp.memPitch);
printf(" Texture alignment: %u bytes\n",
deviceProp.textureAlignment);
printf(" Clock rate: %.2f GHz\n",
deviceProp.clockRate * 1e-6f);
#if CUDART_VERSION >= 2000
printf(" Concurrent copy and execution: %s\n",
deviceProp.deviceOverlap ? "Yes" : "No");
#endif
}
printf("\nTEST PASSED\n");
} | .text
.file "cuda_info.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x358637bd # float 9.99999997E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jne .LBB0_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
.LBB0_2:
cmpl $0, 4(%rsp)
jle .LBB0_13
# %bb.3: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
jmp .LBB0_7
.LBB0_4: # in Loop: Header=BB0_7 Depth=1
movl $.Lstr.3, %edi
.LBB0_5: # in Loop: Header=BB0_7 Depth=1
callq puts@PLT
.LBB0_6: # in Loop: Header=BB0_7 Depth=1
movl $.L.str.4, %edi
movl %ebp, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
movl 368(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 372(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 360(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movq 296(%rsp), %rsi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 312(%rsp), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl 336(%rsp), %edx
movl 340(%rsp), %ecx
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl 348(%rsp), %edx
movl 352(%rsp), %ecx
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movq 320(%rsp), %rsi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movq 376(%rsp), %rsi
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
xorps %xmm0, %xmm0
cvtsi2ssl 356(%rsp), %xmm0
mulss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.15, %edi
movb $1, %al
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jge .LBB0_13
.LBB0_7: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
testl %ebp, %ebp
jne .LBB0_6
# %bb.8: # in Loop: Header=BB0_7 Depth=1
cmpl $9999, 368(%rsp) # imm = 0x270F
jne .LBB0_10
# %bb.9: # in Loop: Header=BB0_7 Depth=1
cmpl $9999, 372(%rsp) # imm = 0x270F
je .LBB0_4
.LBB0_10: # in Loop: Header=BB0_7 Depth=1
movl 4(%rsp), %esi
cmpl $1, %esi
jne .LBB0_12
# %bb.11: # in Loop: Header=BB0_7 Depth=1
movl $.Lstr.2, %edi
jmp .LBB0_5
.LBB0_12: # in Loop: Header=BB0_7 Depth=1
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
jmp .LBB0_6
.LBB0_13: # %._crit_edge
movl $.Lstr.1, %edi
callq puts@PLT
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "There are %d devices supporting CUDA\n"
.size .L.str.3, 38
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nDevice %d: \"%s\"\n"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " Major revision number: %d\n"
.size .L.str.5, 53
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " Minor revision number: %d\n"
.size .L.str.6, 53
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " Total amount of constant memory: %u bytes\n"
.size .L.str.7, 59
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " Total amount of global memory: %u bytes\n"
.size .L.str.8, 59
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " Total amount of shared memory per block: %u bytes\n"
.size .L.str.9, 59
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " Total number of registers available per block: %d\n"
.size .L.str.10, 53
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " Maximum sizes of each dimension of a block: %d x %d x %d\n"
.size .L.str.11, 63
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " Maximum sizes of each dimension of a grid: %d x %d x %d\n"
.size .L.str.12, 63
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " Maximum memory pitch: %u bytes\n"
.size .L.str.13, 59
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " Texture alignment: %u bytes\n"
.size .L.str.14, 59
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz " Clock rate: %.2f GHz\n"
.size .L.str.15, 59
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "There is no device supporting CUDA"
.size .Lstr, 35
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nTEST PASSED"
.size .Lstr.1, 13
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "There is 1 device supporting CUDA"
.size .Lstr.2, 34
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "There is no device supporting CUDA."
.size .Lstr.3, 36
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000079d1_00000000-6_cuda_info.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Yes"
.LC1:
.string "No"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "There is no device supporting CUDA\n"
.align 8
.LC3:
.string "There is no device supporting CUDA.\n"
.align 8
.LC4:
.string "There is 1 device supporting CUDA\n"
.align 8
.LC5:
.string "There are %d devices supporting CUDA\n"
.section .rodata.str1.1
.LC6:
.string "\nDevice %d: \"%s\"\n"
.section .rodata.str1.8
.align 8
.LC7:
.string " Major revision number: %d\n"
.align 8
.LC8:
.string " Minor revision number: %d\n"
.align 8
.LC9:
.string " Number of cores: %d\n"
.align 8
.LC10:
.string " Number of multiprocessors: %d\n"
.align 8
.LC11:
.string " Warp size: %d\n"
.align 8
.LC12:
.string " Maximum number of blocks per multiprocessor %d\n"
.align 8
.LC13:
.string " Maximum number of threads per multiprocessor %d\n"
.align 8
.LC14:
.string " Maximum number of threads per block: %d\n"
.align 8
.LC15:
.string " Total amount of constant memory: %u bytes\n"
.align 8
.LC16:
.string " Total amount of global memory: %u bytes\n"
.align 8
.LC17:
.string " Total amount of shared memory per block: %u bytes\n"
.align 8
.LC18:
.string " Total number of registers available per block: %d\n"
.align 8
.LC19:
.string " Maximum sizes of each dimension of a block: %d x %d x %d\n"
.align 8
.LC20:
.string " Maximum sizes of each dimension of a grid: %d x %d x %d\n"
.align 8
.LC21:
.string " Maximum memory pitch: %u bytes\n"
.align 8
.LC22:
.string " Texture alignment: %u bytes\n"
.align 8
.LC24:
.string " Clock rate: %.2f GHz\n"
.align 8
.LC25:
.string " Concurrent copy and execution: %s\n"
.section .rodata.str1.1
.LC26:
.string "\nTEST PASSED\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1064, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
je .L15
.L4:
cmpl $0, 12(%rsp)
jle .L5
movl $0, %ebx
leaq 16(%rsp), %rbp
movabsq $42945378002703, %r12
leaq .LC5(%rip), %r13
jmp .L10
.L15:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.L16:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L6
.L17:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L6:
movq %rbp, %rcx
movl %ebx, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 376(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %eax
leal 0(,%rax,8), %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 728(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 640(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 384(%rsp), %rdx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 364(%rsp), %xmm0
mulss .LC23(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $0, 400(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L5
.L10:
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
testl %ebx, %ebx
jne .L6
cmpq %r12, 376(%rsp)
je .L16
movl 12(%rsp), %edx
cmpl $1, %edx
je .L17
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L6
.L5:
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC23:
.long 897988541
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_info.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x358637bd # float 9.99999997E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jne .LBB0_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
.LBB0_2:
cmpl $0, 4(%rsp)
jle .LBB0_13
# %bb.3: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
jmp .LBB0_7
.LBB0_4: # in Loop: Header=BB0_7 Depth=1
movl $.Lstr.3, %edi
.LBB0_5: # in Loop: Header=BB0_7 Depth=1
callq puts@PLT
.LBB0_6: # in Loop: Header=BB0_7 Depth=1
movl $.L.str.4, %edi
movl %ebp, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
movl 368(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 372(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 360(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movq 296(%rsp), %rsi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 312(%rsp), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl 336(%rsp), %edx
movl 340(%rsp), %ecx
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl 348(%rsp), %edx
movl 352(%rsp), %ecx
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movq 320(%rsp), %rsi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movq 376(%rsp), %rsi
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
xorps %xmm0, %xmm0
cvtsi2ssl 356(%rsp), %xmm0
mulss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.15, %edi
movb $1, %al
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jge .LBB0_13
.LBB0_7: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
testl %ebp, %ebp
jne .LBB0_6
# %bb.8: # in Loop: Header=BB0_7 Depth=1
cmpl $9999, 368(%rsp) # imm = 0x270F
jne .LBB0_10
# %bb.9: # in Loop: Header=BB0_7 Depth=1
cmpl $9999, 372(%rsp) # imm = 0x270F
je .LBB0_4
.LBB0_10: # in Loop: Header=BB0_7 Depth=1
movl 4(%rsp), %esi
cmpl $1, %esi
jne .LBB0_12
# %bb.11: # in Loop: Header=BB0_7 Depth=1
movl $.Lstr.2, %edi
jmp .LBB0_5
.LBB0_12: # in Loop: Header=BB0_7 Depth=1
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
jmp .LBB0_6
.LBB0_13: # %._crit_edge
movl $.Lstr.1, %edi
callq puts@PLT
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "There are %d devices supporting CUDA\n"
.size .L.str.3, 38
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nDevice %d: \"%s\"\n"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " Major revision number: %d\n"
.size .L.str.5, 53
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " Minor revision number: %d\n"
.size .L.str.6, 53
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " Total amount of constant memory: %u bytes\n"
.size .L.str.7, 59
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " Total amount of global memory: %u bytes\n"
.size .L.str.8, 59
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " Total amount of shared memory per block: %u bytes\n"
.size .L.str.9, 59
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " Total number of registers available per block: %d\n"
.size .L.str.10, 53
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " Maximum sizes of each dimension of a block: %d x %d x %d\n"
.size .L.str.11, 63
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " Maximum sizes of each dimension of a grid: %d x %d x %d\n"
.size .L.str.12, 63
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " Maximum memory pitch: %u bytes\n"
.size .L.str.13, 59
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " Texture alignment: %u bytes\n"
.size .L.str.14, 59
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz " Clock rate: %.2f GHz\n"
.size .L.str.15, 59
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "There is no device supporting CUDA"
.size .Lstr, 35
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nTEST PASSED"
.size .Lstr.1, 13
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "There is 1 device supporting CUDA"
.size .Lstr.2, 34
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "There is no device supporting CUDA."
.size .Lstr.3, 36
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
#ifndef gpuAssert
#define gpuAssert( condition ) { if( (condition) != cudaSuccess ) { fprintf( stderr, "\n FAILURE %s in %s, line %d\n", cudaGetErrorString(condition), __FILE__, __LINE__ ); exit( 1 ); } }
#endif
#define PREC 8
// I've used a snippet of someone elses code, and one condition of use is
// to retain this licensing message
// I obtained the code from:
// https://github.com/parallel-forall/code-samples/blob/master/posts/cuda-aware-mpi-example/src/Device.cu
/* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of NVIDIA CORPORATION nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************/
/* borrowed just one function for AtomicMax on floats from github */
/**
* @brief Compute the maximum of 2 single-precision floating point values using an atomic operation
*
* @param[in] address The address of the reference value which might get updated with the maximum
* @param[in] value The value that is compared to the reference in order to determine the maximum
*/
static __device__ void AtomicMax(float * const address, float value)
{
if (*address >= value)
{
return;
}
int * const address_as_i = (int *)address;
int old = *address_as_i, assumed;
do
{
assumed = old;
if (__int_as_float(assumed) >= value)
{
break;
}
old = atomicCAS(address_as_i, assumed, __float_as_int(value));
} while (assumed != old);
}
/******************************************************************/
// don't actually need this, as you can & with offsets instead
//#define B01_MASK 0b0000000000000001
//#define B02_MASK 0b0000000000000011
//#define B03_MASK 0b0000000000000111
//#define B04_MASK 0b0000000000001111
//#define B05_MASK 0b0000000000011111
//#define B06_MASK 0b0000000000111111
//#define B07_MASK 0b0000000001111111
//#define B08_MASK 0b0000000011111111
//#define B09_MASK 0b0000000111111111
//#define B10_MASK 0b0000001111111111
// * bitwise div of power 2 num (i\n): i >> log2(n)
// * bitwise modulo of power of 2 num(i % n) : i & (n - 1)
// much of the efficiency of this implementation hinges of being able to apply
// very fast bitwise manipulations which will only be reliable in cases where
// the fundamental dimensionality of the data is strictly by powers of 2
// happily this is the case in this application, and for fft in general
// more specifically, exploiting the luxury of powers of 2 enables the construction
// of blocks that should be (theoretically) entirely divergence free, which also means
// that the __syncthreads statements, though necessary to ensure correctness, are in practice
// often a "formality", as all warps should be finishing at the same time, provided all
// memory accesses to shared and constant memory can be performed in the same number of
// clock cycles, this is also one of the reasons behind using constant and shared memory.
// though this implementation fixes on 2048 point fft, it could easily be generalised
// to any 2^s point fft needed. There is a happy coincidence, where my particular GPU
// is limited to 1024 threads per block, and a 2048 point iterative fft unrolls its
// two inner loops to 1024 every time. This is optimal, but only by coincidence. Were
// this happy coincidence not to be relied upon, then further optimisations which take
// intra-block synchronisation, and possibly where warp boundaries will cross, might need
// to be included.
// precision: it must also be mentioned that a loss of precision is being spent on performance
// Nvidia GPUs with Compute Cabaility 5.0 can only assure atomic arithmetic for single precision
// floats, and the registers available to the threads are also 32 bit registers. For this reason,
// the decision was made to reduce the precision from double to single
#define TWIDDLES_LEN 2047
#define LGSAMP 11
#define WSAMP 2048
#define HWSAMP (WSAMP / 2)
#define IDX_SHIFT (32 - LGSAMP)
//typedef float3 Complex; // padding to avoid bank conflicts - might not be needed in CUDA 9.0
typedef float2 Complex;
static __device__ inline Complex ComplexCast(float a, float b);
static __device__ inline Complex ComplexAdd(Complex a, Complex b);
static __device__ inline Complex ComplexSub(Complex a, Complex b);
static __device__ inline Complex ComplexMul(Complex a, Complex b);
static __device__ inline float ComplexNorm(Complex a);
static __device__ inline Complex ComplexCast(float a, float b)
{
Complex c;
c.x = a; c.y = b;
//c.z = 0;
return c;
}
// Complex addition
static __device__ inline Complex ComplexAdd(Complex a, Complex b)
{
Complex c;
c.x = a.x + b.x;
c.y = a.y + b.y;
//c.z = 0; // padding to avoid bank conflicts - might not be needed in CUDA 9.0
return c;
}
// Complex subtraction
static __device__ inline Complex ComplexSub(Complex a, Complex b)
{
Complex c;
c.x = a.x - b.x;
c.y = a.y - b.y;
//c.z = 0; // padding to avoid bank conflicts - might not be needed in CUDA 9.0
return c;
}
// Complex multiplication
static __device__ inline Complex ComplexMul(Complex a, Complex b)
{
Complex c;
c.x = a.x * b.x - a.y * b.y;
c.y = a.x * b.y + a.y * b.x;
//c.z = 0; // padding to avoid bank conflicts - might not be needed in CUDA 9.0
return c;
}
// Fast calc of Norm of a Complex Number
static __device__ inline float ComplexNorm(Complex a) { return sqrt(a.x*a.x + a.y*a.y); }
__device__ __constant__ int offsets[LGSAMP];
__device__ __constant__ float twiddles_re[TWIDDLES_LEN];
__device__ __constant__ float twiddles_im[TWIDDLES_LEN];
__device__ float * in_re;
__device__ float * in_im;
static __device__ float maxFFT = 0;
// would be really good to use this with Pinned Memory
__global__ void core(float * out, int size, int gridNum, int gridWidth)
{
extern __shared__ Complex signalChunk[]; // twice the size of 1024 threads in block
int tidx0, tidx1, rtidx0, rtidx1, stridx0, stridx1, idx_twid;
Complex radius;
int start = (gridNum * gridWidth + blockIdx.x) * blockDim.x; // start of the block, threadIdx.x == 0
tidx0 = threadIdx.x;
tidx1 = threadIdx.x + HWSAMP;
rtidx0 = __brev(tidx0) >> IDX_SHIFT;
rtidx1 = __brev(tidx1) >> IDX_SHIFT;
stridx0 = rtidx0 + start;
stridx1 = rtidx1 + start;
if(tidx0 + start < size){
// permutation by bit reversal of array indices as 11 bit numbers, requires 32-11 bit shift
signalChunk[tidx0] = ComplexCast(in_re[stridx0], in_im[stridx0]);
signalChunk[tidx1] = ComplexCast(in_re[stridx1], in_im[stridx1]);
__syncthreads();
for (unsigned int s = 0; s < LGSAMP; s++) // 11 values of s as per iterative algorithm for fft (2048 point)
{
tidx0 = threadIdx.x + (threadIdx.x & (~offsets[s]));
tidx1 = tidx0 + offsets[s] + 1;
idx_twid = offsets[s] + (threadIdx.x & offsets[s]);
radius = ComplexMul(signalChunk[tidx1], ComplexCast(twiddles_re[idx_twid], twiddles_im[idx_twid])); // A[j + k + m/2]*w
signalChunk[tidx0] = ComplexAdd(signalChunk[tidx0], radius); // A[j + k] = A[j + k] + A[j + k + m/2]*w
signalChunk[tidx1] = ComplexSub(signalChunk[tidx0], radius); // A[j + k + m/2] = A[j + k] - A[j + k + m/2]*w
__syncthreads();
}
tidx0 = threadIdx.x;
out[tidx0 + start] = ComplexNorm(signalChunk[tidx0]);
// eval for maxFFT, use AtomicMax() here
AtomicMax(&maxFFT, out[tidx0 + start]);
}
}
// use kernel termination as sync point to launch this next kernel named normaliseFinal
__global__ void normaliseFinal(float * out, int size, int gridNum, int gridWidth)
{
int tidx = (gridNum * gridWidth + blockIdx.x) * blockDim.x + threadIdx.x;
if(tidx < size){
out[tidx] = out[tidx] / maxFFT;
}
}
// would be really good to use this with Pinned Memory
// since CPU will be busy reading in wavefile while this is happening
// this doesn't need to be all that optimised, it could even be as sequential
// as the CPU version
// NOTE: this should be 1 block, 11 threads
__global__ void calcTwiddles(float * out_re, float * out_im, float * zerothTwiddles_re, float * zerothTwiddles_im)
{
int tid = threadIdx.x;
Complex runVal; runVal.x = 1; runVal.y = 0; //runVal.z = 0;
for (int i = offsets[tid]; i < 2 * offsets[tid] + 1; i++)
{
out_re[i] = runVal.x;
out_im[i] = runVal.y;
runVal = ComplexMul(runVal, ComplexCast(zerothTwiddles_re[tid], zerothTwiddles_im[tid]));
}
}
void writeBinFile(const char * file_name, float * bin_data, size_t nmemb){
FILE * fp = fopen(file_name, "wb");
printf("writing %s is writing %d in %lu bytes\n",file_name, nmemb, sizeof(float) * nmemb);
fflush(stdout);
fwrite(bin_data, sizeof(float), nmemb, fp);
fflush(fp);
fclose(fp);
}
size_t readBinFile(const char * file_name, float ** bin_data){
FILE * fp = fopen(file_name,"r");
fseek(fp, 0, SEEK_END);
size_t sz = ftell(fp);
size_t nmemb = sz/sizeof(**bin_data);
printf("file %s is %lu elements in %lu bytes\n", file_name, nmemb, sz);
fflush(stdout);
rewind(fp);
*bin_data = (float*)malloc(sz);
fread(*bin_data, sizeof(float), nmemb, fp);
fflush(fp);
fclose(fp);
return nmemb;
}
int main(int argc, char ** argv){
printf("hello\n");
fflush(stdout);
const float pi = 3.1415927410;
const char * wave_bin = "wave_out";
const char * timefreq_ref = "timefreq_out";
const char * timefreq_cmp = "timefreq_done";
const int h_offsets[LGSAMP] = {0,1,3,7,15,31,63,127,255,511,1023};
for(int i = 0; i < LGSAMP; i++) printf("h_offsets[%d] = %d, ", i, h_offsets[i]);
printf("\n");
fflush(stdout);
float h_zerothTwiddles_re[LGSAMP];
float h_zerothTwiddles_im[LGSAMP];
float h_twiddles_re[TWIDDLES_LEN];
float h_twiddles_im[TWIDDLES_LEN];
float a;
float * h_wave_data;
float * h_timefreq_ref_data;
size_t wave_num_els = readBinFile(wave_bin, &h_wave_data);
size_t timefreq_num_els = readBinFile(timefreq_ref, &h_timefreq_ref_data);
// testing bit reversal
float * out;
if((out = (float*)malloc(timefreq_num_els * sizeof(*out))) == NULL)
printf("failed to allocate out");
float * h_timefreq_cmp_data;
printf("Allocating h_timefreq_cmp_data\n");
fflush(stdout);
if((h_timefreq_cmp_data = (float*)malloc(timefreq_num_els * sizeof(*h_timefreq_cmp_data))) == NULL)
printf("failed to allocate h_timefreq_cmp_data");
size_t wave_num_pels = ((size_t)ceil((double)wave_num_els / (double)WSAMP)) * WSAMP;
printf("wave_num_els = %d, wave_num_pels = %d\n", wave_num_els, wave_num_pels);
fflush(stdout);
float ** h_sig_data;
printf("Allocating h_sig_data\n");
fflush(stdout);
if(h_sig_data = (float**)malloc(2 * sizeof(*h_sig_data))){
for(int i = 0; i < 2; i++){
printf("Allocating h_sig_data[%d]\n", i);
if((h_sig_data[i] = (float*)malloc(wave_num_pels * sizeof(**h_sig_data))) == NULL)
printf("failed to allocate h_sig_data[%d]\n", i);
}
}
else printf("failed to allocate h_sig_data\n");
// cast wave data to complex and add padding
printf("Casting wave to complex and padding with zeros\n");
fflush(stdout);
for(int i = 0; i < wave_num_pels; i++)
{
h_sig_data[1][i] = 0;
if(i < wave_num_els){
h_sig_data[0][i] = h_wave_data[i];
}
else h_sig_data[0][i] = 0;
}
// calc zerothTwiddles
printf("Calculating the zeroth twiddles\n");
fflush(stdout);
for (int ii = 0; ii < LGSAMP; ii++)
{
a = -2 * pi / ((double)(2*(h_offsets[ii] + 1)));
//printf("2 * pi * ii = %f, (float)h_offsets[ii] + 1 = %f\n", 2 * pi * ii, (float)h_offsets[ii] + 1);
//fflush(stdout);
h_zerothTwiddles_re[ii] = (float)cos(a);
h_zerothTwiddles_im[ii] = (float)sin(a);
//printf("a = %f, h_zerothTwiddles_re[%d] = %f, h_zerothTwiddles_im[%d] = %f\n",a,ii,h_zerothTwiddles_re[ii],ii,h_zerothTwiddles_im[ii]);
//fflush(stdout);
}
//float chk_twiddles_re[TWIDDLES_LEN];
//float chk_twiddles_im[TWIDDLES_LEN];
//
//for(int s = 0; s < LGSAMP; s++){
// float runVal_re = 1.0f; float temp1;
// float runVal_im = 0.0f;
// for (int i = h_offsets[s]; i < 2 * h_offsets[s] + 1; i++)
// {
// chk_twiddles_re[i] = runVal_re;
// chk_twiddles_im[i] = runVal_im;
// temp1 = runVal_re;
// runVal_re = runVal_re * h_zerothTwiddles_re[s] - runVal_im * h_zerothTwiddles_im[s];
// runVal_im = temp1 * h_zerothTwiddles_im[s] + runVal_im * h_zerothTwiddles_re[s];
// }
//}
/********************** kernel stuff **********************/
// wave data in
printf("Allocating memory on device\n");
fflush(stdout);
float * d_sig_data_re; cudaMalloc(&d_sig_data_re, wave_num_pels * sizeof(*d_sig_data_re));
float * d_sig_data_im; cudaMalloc(&d_sig_data_im, wave_num_pels * sizeof(*d_sig_data_im));
// timefreq data out
//float * d_timefreq_cmp_data; cudaMalloc(&d_timefreq_cmp_data, timefreq_num_els * sizeof(*d_timefreq_cmp_data));
float * d_out; cudaMalloc(&d_out, timefreq_num_els * sizeof(*d_out));
// supporting structures
float * d_zerothTwiddles_re; cudaMalloc(&d_zerothTwiddles_re, TWIDDLES_LEN * sizeof(*d_zerothTwiddles_re));
float * d_zerothTwiddles_im; cudaMalloc(&d_zerothTwiddles_im, TWIDDLES_LEN * sizeof(*d_zerothTwiddles_im));
float * d_twiddles_re; cudaMalloc(&d_twiddles_re, TWIDDLES_LEN * sizeof(*d_twiddles_re));
float * d_twiddles_im; cudaMalloc(&d_twiddles_im, TWIDDLES_LEN * sizeof(*d_twiddles_im));
//int * d_offsets; cudaMalloc(&d_offsets, LGSAMP * sizeof(*d_offsets));
// copy to device
printf("Copying data over to device\n");
fflush(stdout);
gpuAssert( cudaMemcpyToSymbol(offsets, h_offsets, LGSAMP * sizeof(*h_offsets), 0, cudaMemcpyHostToDevice) );
//cudaMemcpy( d_offsets, h_offsets, LGSAMP * sizeof(*d_offsets), cudaMemcpyHostToDevice );
gpuAssert( cudaMemcpy( d_zerothTwiddles_re, h_zerothTwiddles_re, LGSAMP * sizeof(*d_zerothTwiddles_re), cudaMemcpyHostToDevice ) );
gpuAssert( cudaMemcpy( d_zerothTwiddles_im, h_zerothTwiddles_im, LGSAMP * sizeof(*d_zerothTwiddles_im), cudaMemcpyHostToDevice ) );
gpuAssert( cudaMemcpy( d_sig_data_re, h_sig_data[0], wave_num_pels * sizeof(*d_sig_data_re), cudaMemcpyHostToDevice ) );
gpuAssert( cudaMemcpy( d_sig_data_im, h_sig_data[1], wave_num_pels * sizeof(*d_sig_data_im), cudaMemcpyHostToDevice ) );
gpuAssert( cudaMemcpyToSymbol(in_re, &d_sig_data_re, sizeof(float *)) );
gpuAssert( cudaMemcpyToSymbol(in_im, &d_sig_data_im, sizeof(float *)) );
// launch prep kernel
printf("Launching kernel to calc twiddles\n");
fflush(stdout);
calcTwiddles<<<1,11>>>(d_twiddles_re, d_twiddles_im, d_zerothTwiddles_re, d_zerothTwiddles_im);
cudaDeviceSynchronize();
/* this copy to host then back to device may not be necessary */
// copy twiddles back to host
gpuAssert( cudaMemcpy(h_twiddles_re, d_twiddles_re, TWIDDLES_LEN * sizeof(*h_twiddles_re), cudaMemcpyDeviceToHost ) );
gpuAssert( cudaMemcpy(h_twiddles_im, d_twiddles_im, TWIDDLES_LEN * sizeof(*h_twiddles_im), cudaMemcpyDeviceToHost ) );
// copy twiddles back to device
gpuAssert( cudaMemcpyToSymbol(twiddles_re, h_twiddles_re, TWIDDLES_LEN * sizeof(*d_twiddles_re), 0, cudaMemcpyHostToDevice) );
gpuAssert( cudaMemcpyToSymbol(twiddles_im, h_twiddles_im, TWIDDLES_LEN * sizeof(*d_twiddles_im), 0, cudaMemcpyHostToDevice) );
// launch core kernel
int threadsPerBlock = HWSAMP;
int blocksPerGrid = wave_num_pels / (2 * threadsPerBlock);
printf("launching kernel with %d blocks and %d threads per block\n", blocksPerGrid, threadsPerBlock);
fflush(stdout);
int blockEachLaunch = 32;
int iter = 0;
for(; iter < blocksPerGrid/blockEachLaunch; iter++){
core<<<blockEachLaunch, threadsPerBlock, WSAMP * PREC>>>(d_out, timefreq_num_els, iter, blockEachLaunch);
}
if(blocksPerGrid % blockEachLaunch > 0) core<<<blocksPerGrid % blockEachLaunch, threadsPerBlock, WSAMP * PREC>>>(d_out, timefreq_num_els, iter, blockEachLaunch);
cudaDeviceSynchronize();
/* this copy to host then back to device may not be necessary */
//// copy results back from device
//cudaMemcpy(h_timefreq_cmp_data, d_timefreq_cmp_data, timefreq_num_els * sizeof(*h_timefreq_cmp_data), cudaMemcpyDeviceToHost );
//
//// copy results back to device
//cudaMemcpy(d_timefreq_cmp_data, h_timefreq_data, timefreq_num_els * sizeof(*d_timefreq_cmp_data), cudaMemcpyHostToDevice );
// launch kernel to normalise the data
iter = 0;
for(; iter < blocksPerGrid/blockEachLaunch; iter++){
normaliseFinal<<<blockEachLaunch, threadsPerBlock>>>(d_out, timefreq_num_els, iter, blockEachLaunch);
}
if(blocksPerGrid % blockEachLaunch > 0) normaliseFinal<<<blocksPerGrid % blockEachLaunch, threadsPerBlock>>>(d_out, timefreq_num_els, iter, blockEachLaunch);
cudaDeviceSynchronize();
// copy final results back to host
//cudaMemcpy(h_timefreq_cmp_data, d_timefreq_cmp_data, timefreq_num_els * sizeof(*h_timefreq_cmp_data), cudaMemcpyDeviceToHost );
gpuAssert( cudaMemcpy(out, d_out, timefreq_num_els * sizeof(*out), cudaMemcpyDeviceToHost ) );
gpuAssert( cudaFree(d_out) );
// clean up device memory
gpuAssert( cudaFree(d_sig_data_re) );
gpuAssert( cudaFree(d_sig_data_im) );
gpuAssert( cudaFree(d_zerothTwiddles_re) );
gpuAssert( cudaFree(d_zerothTwiddles_im) );
gpuAssert( cudaFree(d_twiddles_re) );
gpuAssert( cudaFree(d_twiddles_im) );
/********************** /kernel stuff **********************/
//for(int i = 0; i < timefreq_num_els; i++) printf("%f ", out[i]);
//printf("Writing results to timefreq_done. int is %lu bytes.\n", sizeof(int));
writeBinFile(timefreq_cmp, out, timefreq_num_els);
free(out);
free(h_timefreq_ref_data);
free(h_timefreq_cmp_data);
free(h_wave_data);
}
// -gencode arch=compute_50,code=sm_50 | .file "tmpxft_000555db_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "wb"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "writing %s is writing %d in %lu bytes\n"
.text
.globl _Z12writeBinFilePKcPfm
.type _Z12writeBinFilePKcPfm, @function
_Z12writeBinFilePKcPfm:
.LFB2063:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movq %rsi, %r13
movq %rdx, %rbp
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %rbx
leaq 0(,%rbp,4), %r8
movq %rbp, %rcx
movq %r12, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movq %rbx, %rcx
movq %rbp, %rdx
movl $4, %esi
movq %r13, %rdi
call fwrite@PLT
movq %rbx, %rdi
call fflush@PLT
movq %rbx, %rdi
call fclose@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z12writeBinFilePKcPfm, .-_Z12writeBinFilePKcPfm
.section .rodata.str1.1
.LC2:
.string "r"
.section .rodata.str1.8
.align 8
.LC3:
.string "file %s is %lu elements in %lu bytes\n"
.text
.globl _Z11readBinFilePKcPPf
.type _Z11readBinFilePKcPPf, @function
_Z11readBinFilePKcPPf:
.LFB2064:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r14
movq %rsi, %r13
leaq .LC2(%rip), %rsi
call fopen@PLT
movq %rax, %rbx
movl $2, %edx
movl $0, %esi
movq %rax, %rdi
call fseek@PLT
movq %rbx, %rdi
call ftell@PLT
movq %rax, %rbp
movq %rax, %r12
shrq $2, %r12
movq %rax, %r8
movq %r12, %rcx
movq %r14, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movq %rbx, %rdi
call rewind@PLT
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rdi
movq %rax, 0(%r13)
movq %rbx, %r8
movq %r12, %rcx
movl $4, %edx
movq %rbp, %rsi
call __fread_chk@PLT
movq %rbx, %rdi
call fflush@PLT
movq %rbx, %rdi
call fclose@PLT
movq %r12, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _Z11readBinFilePKcPPf, .-_Z11readBinFilePKcPPf
.globl _Z26__device_stub__Z4corePfiiiPfiii
.type _Z26__device_stub__Z4corePfiiiPfiii, @function
_Z26__device_stub__Z4corePfiiiPfiii:
.LFB2090:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4corePfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z26__device_stub__Z4corePfiiiPfiii, .-_Z26__device_stub__Z4corePfiiiPfiii
.globl _Z4corePfiii
.type _Z4corePfiii, @function
_Z4corePfiii:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4corePfiiiPfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z4corePfiii, .-_Z4corePfiii
.globl _Z37__device_stub__Z14normaliseFinalPfiiiPfiii
.type _Z37__device_stub__Z14normaliseFinalPfiiiPfiii, @function
_Z37__device_stub__Z14normaliseFinalPfiiiPfiii:
.LFB2092:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14normaliseFinalPfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z37__device_stub__Z14normaliseFinalPfiiiPfiii, .-_Z37__device_stub__Z14normaliseFinalPfiiiPfiii
.globl _Z14normaliseFinalPfiii
.type _Z14normaliseFinalPfiii, @function
_Z14normaliseFinalPfiii:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14normaliseFinalPfiiiPfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z14normaliseFinalPfiii, .-_Z14normaliseFinalPfiii
.globl _Z38__device_stub__Z12calcTwiddlesPfS_S_S_PfS_S_S_
.type _Z38__device_stub__Z12calcTwiddlesPfS_S_S_PfS_S_S_, @function
_Z38__device_stub__Z12calcTwiddlesPfS_S_S_PfS_S_S_:
.LFB2094:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12calcTwiddlesPfS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2094:
.size _Z38__device_stub__Z12calcTwiddlesPfS_S_S_PfS_S_S_, .-_Z38__device_stub__Z12calcTwiddlesPfS_S_S_PfS_S_S_
.globl _Z12calcTwiddlesPfS_S_S_
.type _Z12calcTwiddlesPfS_S_S_, @function
_Z12calcTwiddlesPfS_S_S_:
.LFB2095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12calcTwiddlesPfS_S_S_PfS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _Z12calcTwiddlesPfS_S_S_, .-_Z12calcTwiddlesPfS_S_S_
.section .rodata.str1.1
.LC4:
.string "hello\n"
.LC5:
.string "h_offsets[%d] = %d, "
.LC6:
.string "\n"
.LC7:
.string "wave_out"
.LC8:
.string "timefreq_out"
.LC9:
.string "failed to allocate out"
.section .rodata.str1.8
.align 8
.LC10:
.string "Allocating h_timefreq_cmp_data\n"
.align 8
.LC11:
.string "failed to allocate h_timefreq_cmp_data"
.align 8
.LC17:
.string "wave_num_els = %d, wave_num_pels = %d\n"
.section .rodata.str1.1
.LC18:
.string "Allocating h_sig_data\n"
.LC19:
.string "Allocating h_sig_data[%d]\n"
.section .rodata.str1.8
.align 8
.LC20:
.string "failed to allocate h_sig_data[%d]\n"
.align 8
.LC21:
.string "failed to allocate h_sig_data\n"
.align 8
.LC22:
.string "Casting wave to complex and padding with zeros\n"
.align 8
.LC24:
.string "Calculating the zeroth twiddles\n"
.section .rodata.str1.1
.LC26:
.string "Allocating memory on device\n"
.LC27:
.string "Copying data over to device\n"
.section .rodata.str1.8
.align 8
.LC28:
.string "/home/ubuntu/Datasets/stackv2/train-structured/stephen-hannam/CUDA_impl_2048pt_TukeyCooley_Iterative_FFT/master/soln_single_prec/kernel.cu"
.section .rodata.str1.1
.LC29:
.string "\n FAILURE %s in %s, line %d\n"
.section .rodata.str1.8
.align 8
.LC30:
.string "Launching kernel to calc twiddles\n"
.align 8
.LC31:
.string "launching kernel with %d blocks and %d threads per block\n"
.section .rodata.str1.1
.LC32:
.string "timefreq_done"
.text
.globl main
.type main, @function
main:
.LFB2065:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -16384(%rsp), %r11
.cfi_def_cfa 11, 16440
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $296, %rsp
.cfi_def_cfa_offset 16736
movq %fs:40, %rax
movq %rax, 16664(%rsp)
xorl %eax, %eax
leaq .LC4(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movl $0, 128(%rsp)
movl $1, 132(%rsp)
movl $3, 136(%rsp)
movl $7, 140(%rsp)
movl $15, 144(%rsp)
movl $31, 148(%rsp)
movl $63, 152(%rsp)
movl $127, 156(%rsp)
movl $255, 160(%rsp)
movl $511, 164(%rsp)
movl $1023, 168(%rsp)
movl $0, %ebx
leaq .LC5(%rip), %rbp
.L32:
movl 128(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $11, %rbx
jne .L32
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
leaq 32(%rsp), %rsi
leaq .LC7(%rip), %rdi
call _Z11readBinFilePKcPPf
movq %rax, %rbp
leaq 40(%rsp), %rsi
leaq .LC8(%rip), %rdi
call _Z11readBinFilePKcPPf
movq %rax, (%rsp)
leaq 0(,%rax,4), %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
testq %rax, %rax
je .L93
.L33:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movq %r15, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
testq %rax, %rax
je .L94
.L34:
testq %rbp, %rbp
js .L35
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
.L36:
mulsd .LC12(%rip), %xmm0
movapd %xmm0, %xmm1
movsd .LC33(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC13(%rip), %xmm4
ucomisd %xmm2, %xmm4
jbe .L37
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm1
movsd .LC15(%rip), %xmm4
andpd %xmm4, %xmm1
addsd %xmm2, %xmm1
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm1
.L37:
comisd .LC16(%rip), %xmm1
jnb .L38
cvttsd2siq %xmm1, %r14
.L39:
movq %r14, %r12
salq $11, %r12
movq %r12, %rcx
movq %rbp, %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movl $16, %edi
call malloc@PLT
movq %rax, %rbx
testq %rax, %rax
je .L40
movq %r14, %rax
salq $13, %rax
movq %rax, 8(%rsp)
movl $0, %edx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call malloc@PLT
movq %rax, (%rbx)
testq %rax, %rax
je .L95
.L41:
movl $1, %edx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call malloc@PLT
movq %rax, 8(%rbx)
testq %rax, %rax
je .L96
.L43:
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
testq %r12, %r12
je .L44
movq 8(%rbx), %rdx
movq 32(%rsp), %rsi
movl $0, %eax
jmp .L47
.L93:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L33
.L94:
leaq .LC11(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
jmp .L34
.L35:
movq %rbp, %rax
shrq %rax
movq %rbp, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L36
.L38:
subsd .LC16(%rip), %xmm1
cvttsd2siq %xmm1, %r14
btcq $63, %r14
jmp .L39
.L95:
movl $0, %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
jmp .L41
.L96:
movl $1, %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
jmp .L43
.L40:
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L43
.L45:
movq (%rbx), %rcx
movl $0x00000000, (%rcx,%rax,4)
.L46:
addq $1, %rax
cmpq %r12, %rax
je .L44
.L47:
movl $0x00000000, (%rdx,%rax,4)
cmpq %rbp, %rax
jnb .L45
movss (%rsi,%rax,4), %xmm0
movq (%rbx), %rcx
movss %xmm0, (%rcx,%rax,4)
jmp .L46
.L44:
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movl $0, %ebp
.L48:
leaq 28(%rsp), %rdi
leaq 24(%rsp), %rsi
movl 128(%rsp,%rbp), %eax
leal 2(%rax,%rax), %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
movsd .LC25(%rip), %xmm0
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
call sincosf@PLT
movss 28(%rsp), %xmm0
movss 24(%rsp), %xmm1
movss %xmm1, 176(%rsp,%rbp)
movss %xmm0, 224(%rsp,%rbp)
addq $4, %rbp
cmpq $44, %rbp
jne .L48
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movq %r14, %rbp
salq $13, %rbp
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $8188, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movl $8188, %esi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movl $8188, %esi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movl $8188, %esi
call cudaMalloc@PLT
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
leaq 128(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $44, %edx
leaq _ZL7offsets(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
jne .L97
leaq 176(%rsp), %rsi
movl $1, %ecx
movl $44, %edx
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L98
leaq 224(%rsp), %rsi
movl $1, %ecx
movl $44, %edx
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L99
movq (%rbx), %r12
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L100
movq 8(%rbx), %rbx
movl $1, %ecx
movq %rbp, %rdx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L101
leaq 48(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq _ZL5in_re(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
jne .L102
leaq 56(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq _ZL5in_im(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
jne .L103
leaq .LC30(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movl $11, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 116(%rsp), %rdx
movl $1, %ecx
movq 104(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L104
.L56:
call cudaDeviceSynchronize@PLT
leaq 272(%rsp), %rdi
movl $2, %ecx
movl $8188, %edx
movq 88(%rsp), %rsi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L105
leaq 8464(%rsp), %rdi
movl $2, %ecx
movl $8188, %edx
movq 96(%rsp), %rsi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L106
leaq 272(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8188, %edx
leaq _ZL11twiddles_re(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
jne .L107
leaq 8464(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8188, %edx
leaq _ZL11twiddles_im(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
jne .L108
movabsq $9007199254740991, %r12
andq %r14, %r12
movl $1024, %ecx
movl %r12d, %edx
leaq .LC31(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
leal 31(%r12), %ebp
testl %r12d, %r12d
cmovns %r12d, %ebp
sarl $5, %ebp
cmpl $31, %r12d
jle .L61
movl $0, %ebx
movl (%rsp), %r14d
jmp .L63
.L97:
leaq 128(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $44, %edx
leaq _ZL7offsets(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $389, %r9d
leaq .LC28(%rip), %r8
leaq .LC29(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L98:
leaq 176(%rsp), %rsi
movl $1, %ecx
movl $44, %edx
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $391, %r9d
leaq .LC28(%rip), %r8
leaq .LC29(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L99:
leaq 224(%rsp), %rsi
movl $1, %ecx
movl $44, %edx
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $392, %r9d
leaq .LC28(%rip), %r8
leaq .LC29(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L100:
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $394, %r9d
leaq .LC28(%rip), %r8
leaq .LC29(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L101:
movl $1, %ecx
movq %rbp, %rdx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $395, %r9d
leaq .LC28(%rip), %r8
leaq .LC29(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L102:
leaq 48(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq _ZL5in_re(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $396, %r9d
leaq .LC28(%rip), %r8
leaq .LC29(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L103:
leaq 56(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq _ZL5in_im(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $397, %r9d
leaq .LC28(%rip), %r8
leaq .LC29(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L104:
movq 80(%rsp), %rcx
movq 72(%rsp), %rdx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z38__device_stub__Z12calcTwiddlesPfS_S_S_PfS_S_S_
jmp .L56
.L105:
leaq 272(%rsp), %rdi
movl $2, %ecx
movl $8188, %edx
movq 88(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $407, %r9d
leaq .LC28(%rip), %r8
leaq .LC29(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L106:
leaq 8464(%rsp), %rdi
movl $2, %ecx
movl $8188, %edx
movq 96(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $408, %r9d
leaq .LC28(%rip), %r8
leaq .LC29(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L107:
leaq 272(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8188, %edx
leaq _ZL11twiddles_re(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $411, %r9d
leaq .LC28(%rip), %r8
leaq .LC29(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L108:
leaq 8464(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8188, %edx
leaq _ZL11twiddles_im(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $412, %r9d
leaq .LC28(%rip), %r8
leaq .LC29(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L62:
addl $1, %ebx
cmpl %ebx, %ebp
jle .L109
.L63:
movl $1024, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $32, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $0, %r9d
movl $16384, %r8d
movq 116(%rsp), %rdx
movl $1, %ecx
movq 104(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L62
movl $32, %ecx
movl %ebx, %edx
movl %r14d, %esi
movq 64(%rsp), %rdi
call _Z26__device_stub__Z4corePfiiiPfiii
jmp .L62
.L109:
movl %r12d, %edx
sarl $31, %edx
shrl $27, %edx
leal (%rdx,%r12), %eax
andl $31, %eax
subl %edx, %eax
movl %eax, %r14d
testl %eax, %eax
jg .L110
call cudaDeviceSynchronize@PLT
.L79:
movl $0, %ebx
movl (%rsp), %r12d
jmp .L68
.L110:
testl %ebp, %ebp
movl $1, %ebx
cmovg %ebp, %ebx
.L80:
movl $1024, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl %r14d, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $0, %r9d
movl $16384, %r8d
movq 116(%rsp), %rdx
movl $1, %ecx
movq 104(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L111
.L65:
call cudaDeviceSynchronize@PLT
cmpl $31, %r12d
jg .L79
movl $0, %ebx
jmp .L66
.L123:
movl $0, %ebx
jmp .L80
.L111:
movl $32, %ecx
movl %ebx, %edx
movl (%rsp), %esi
movq 64(%rsp), %rdi
call _Z26__device_stub__Z4corePfiiiPfiii
jmp .L65
.L67:
addl $1, %ebx
cmpl %ebx, %ebp
jle .L112
.L68:
movl $1024, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $32, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 116(%rsp), %rdx
movl $1, %ecx
movq 104(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L67
movl $32, %ecx
movl %ebx, %edx
movl %r12d, %esi
movq 64(%rsp), %rdi
call _Z37__device_stub__Z14normaliseFinalPfiiiPfiii
jmp .L67
.L112:
testl %r14d, %r14d
jg .L113
.L69:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r15, %rdx
movq 64(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L114
movq 64(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L115
movq 48(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L116
movq 56(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L117
movq 72(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L118
movq 80(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L119
movq 88(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L120
movq 96(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L121
movq (%rsp), %rdx
movq %r13, %rsi
leaq .LC32(%rip), %rdi
call _Z12writeBinFilePKcPfm
movq %r13, %rdi
call free@PLT
movq 40(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 32(%rsp), %rdi
call free@PLT
movq 16664(%rsp), %rax
subq %fs:40, %rax
jne .L122
movl $0, %eax
addq $16680, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L113:
.cfi_restore_state
testl %ebp, %ebp
movl $1, %ebx
cmovg %ebp, %ebx
.L66:
movl $1024, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl %r14d, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 116(%rsp), %rdx
movl $1, %ecx
movq 104(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L69
movl $32, %ecx
movl %ebx, %edx
movl (%rsp), %esi
movq 64(%rsp), %rdi
call _Z37__device_stub__Z14normaliseFinalPfiiiPfiii
jmp .L69
.L114:
movl $2, %ecx
movq %r15, %rdx
movq 64(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $447, %r9d
leaq .LC28(%rip), %r8
leaq .LC29(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L115:
movq 64(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $449, %r9d
leaq .LC28(%rip), %r8
leaq .LC29(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L116:
movq 48(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $451, %r9d
leaq .LC28(%rip), %r8
leaq .LC29(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L117:
movq 56(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $452, %r9d
leaq .LC28(%rip), %r8
leaq .LC29(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L118:
movq 72(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $453, %r9d
leaq .LC28(%rip), %r8
leaq .LC29(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L119:
movq 80(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $454, %r9d
leaq .LC28(%rip), %r8
leaq .LC29(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L120:
movq 88(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $455, %r9d
leaq .LC28(%rip), %r8
leaq .LC29(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L121:
movq 96(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $456, %r9d
leaq .LC28(%rip), %r8
leaq .LC29(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L61:
movl $32, %ecx
movl %r12d, %eax
cltd
idivl %ecx
movl %edx, %r14d
testl %edx, %edx
jg .L123
call cudaDeviceSynchronize@PLT
jmp .L69
.L122:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size main, .-main
.section .rodata.str1.1
.LC34:
.string "_Z12calcTwiddlesPfS_S_S_"
.LC35:
.string "_Z14normaliseFinalPfiii"
.LC36:
.string "_Z4corePfiii"
.LC37:
.string "offsets"
.LC38:
.string "twiddles_re"
.LC39:
.string "twiddles_im"
.LC40:
.string "in_re"
.LC41:
.string "in_im"
.LC42:
.string "maxFFT"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2097:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC34(%rip), %rdx
movq %rdx, %rcx
leaq _Z12calcTwiddlesPfS_S_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC35(%rip), %rdx
movq %rdx, %rcx
leaq _Z14normaliseFinalPfiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC36(%rip), %rdx
movq %rdx, %rcx
leaq _Z4corePfiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $44, %r9d
movl $0, %r8d
leaq .LC37(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7offsets(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8188, %r9d
movl $0, %r8d
leaq .LC38(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11twiddles_re(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8188, %r9d
movl $0, %r8d
leaq .LC39(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11twiddles_im(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC40(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5in_re(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC41(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5in_im(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC42(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6maxFFT(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL6maxFFT
.comm _ZL6maxFFT,4,4
.local _ZL5in_im
.comm _ZL5in_im,8,8
.local _ZL5in_re
.comm _ZL5in_re,8,8
.local _ZL11twiddles_im
.comm _ZL11twiddles_im,8188,32
.local _ZL11twiddles_re
.comm _ZL11twiddles_re,8188,32
.local _ZL7offsets
.comm _ZL7offsets,44,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC12:
.long 0
.long 1061158912
.align 8
.LC13:
.long 0
.long 1127219200
.align 8
.LC15:
.long 0
.long 1072693248
.align 8
.LC16:
.long 0
.long 1138753536
.align 8
.LC25:
.long 1610612736
.long -1072094725
.align 8
.LC33:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
#ifndef gpuAssert
#define gpuAssert( condition ) { if( (condition) != cudaSuccess ) { fprintf( stderr, "\n FAILURE %s in %s, line %d\n", cudaGetErrorString(condition), __FILE__, __LINE__ ); exit( 1 ); } }
#endif
#define PREC 8
// I've used a snippet of someone elses code, and one condition of use is
// to retain this licensing message
// I obtained the code from:
// https://github.com/parallel-forall/code-samples/blob/master/posts/cuda-aware-mpi-example/src/Device.cu
/* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of NVIDIA CORPORATION nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************/
/* borrowed just one function for AtomicMax on floats from github */
/**
* @brief Compute the maximum of 2 single-precision floating point values using an atomic operation
*
* @param[in] address The address of the reference value which might get updated with the maximum
* @param[in] value The value that is compared to the reference in order to determine the maximum
*/
static __device__ void AtomicMax(float * const address, float value)
{
if (*address >= value)
{
return;
}
int * const address_as_i = (int *)address;
int old = *address_as_i, assumed;
do
{
assumed = old;
if (__int_as_float(assumed) >= value)
{
break;
}
old = atomicCAS(address_as_i, assumed, __float_as_int(value));
} while (assumed != old);
}
/******************************************************************/
// don't actually need this, as you can & with offsets instead
//#define B01_MASK 0b0000000000000001
//#define B02_MASK 0b0000000000000011
//#define B03_MASK 0b0000000000000111
//#define B04_MASK 0b0000000000001111
//#define B05_MASK 0b0000000000011111
//#define B06_MASK 0b0000000000111111
//#define B07_MASK 0b0000000001111111
//#define B08_MASK 0b0000000011111111
//#define B09_MASK 0b0000000111111111
//#define B10_MASK 0b0000001111111111
// * bitwise div of power 2 num (i\n): i >> log2(n)
// * bitwise modulo of power of 2 num(i % n) : i & (n - 1)
// much of the efficiency of this implementation hinges of being able to apply
// very fast bitwise manipulations which will only be reliable in cases where
// the fundamental dimensionality of the data is strictly by powers of 2
// happily this is the case in this application, and for fft in general
// more specifically, exploiting the luxury of powers of 2 enables the construction
// of blocks that should be (theoretically) entirely divergence free, which also means
// that the __syncthreads statements, though necessary to ensure correctness, are in practice
// often a "formality", as all warps should be finishing at the same time, provided all
// memory accesses to shared and constant memory can be performed in the same number of
// clock cycles, this is also one of the reasons behind using constant and shared memory.
// though this implementation fixes on 2048 point fft, it could easily be generalised
// to any 2^s point fft needed. There is a happy coincidence, where my particular GPU
// is limited to 1024 threads per block, and a 2048 point iterative fft unrolls its
// two inner loops to 1024 every time. This is optimal, but only by coincidence. Were
// this happy coincidence not to be relied upon, then further optimisations which take
// intra-block synchronisation, and possibly where warp boundaries will cross, might need
// to be included.
// precision: it must also be mentioned that a loss of precision is being spent on performance
// Nvidia GPUs with Compute Cabaility 5.0 can only assure atomic arithmetic for single precision
// floats, and the registers available to the threads are also 32 bit registers. For this reason,
// the decision was made to reduce the precision from double to single
#define TWIDDLES_LEN 2047
#define LGSAMP 11
#define WSAMP 2048
#define HWSAMP (WSAMP / 2)
#define IDX_SHIFT (32 - LGSAMP)
//typedef float3 Complex; // padding to avoid bank conflicts - might not be needed in CUDA 9.0
typedef float2 Complex;
static __device__ inline Complex ComplexCast(float a, float b);
static __device__ inline Complex ComplexAdd(Complex a, Complex b);
static __device__ inline Complex ComplexSub(Complex a, Complex b);
static __device__ inline Complex ComplexMul(Complex a, Complex b);
static __device__ inline float ComplexNorm(Complex a);
static __device__ inline Complex ComplexCast(float a, float b)
{
Complex c;
c.x = a; c.y = b;
//c.z = 0;
return c;
}
// Complex addition
static __device__ inline Complex ComplexAdd(Complex a, Complex b)
{
Complex c;
c.x = a.x + b.x;
c.y = a.y + b.y;
//c.z = 0; // padding to avoid bank conflicts - might not be needed in CUDA 9.0
return c;
}
// Complex subtraction
static __device__ inline Complex ComplexSub(Complex a, Complex b)
{
Complex c;
c.x = a.x - b.x;
c.y = a.y - b.y;
//c.z = 0; // padding to avoid bank conflicts - might not be needed in CUDA 9.0
return c;
}
// Complex multiplication
static __device__ inline Complex ComplexMul(Complex a, Complex b)
{
Complex c;
c.x = a.x * b.x - a.y * b.y;
c.y = a.x * b.y + a.y * b.x;
//c.z = 0; // padding to avoid bank conflicts - might not be needed in CUDA 9.0
return c;
}
// Fast calc of Norm of a Complex Number
static __device__ inline float ComplexNorm(Complex a) { return sqrt(a.x*a.x + a.y*a.y); }
__device__ __constant__ int offsets[LGSAMP];
__device__ __constant__ float twiddles_re[TWIDDLES_LEN];
__device__ __constant__ float twiddles_im[TWIDDLES_LEN];
__device__ float * in_re;
__device__ float * in_im;
static __device__ float maxFFT = 0;
// would be really good to use this with Pinned Memory
__global__ void core(float * out, int size, int gridNum, int gridWidth)
{
extern __shared__ Complex signalChunk[]; // twice the size of 1024 threads in block
int tidx0, tidx1, rtidx0, rtidx1, stridx0, stridx1, idx_twid;
Complex radius;
int start = (gridNum * gridWidth + blockIdx.x) * blockDim.x; // start of the block, threadIdx.x == 0
tidx0 = threadIdx.x;
tidx1 = threadIdx.x + HWSAMP;
rtidx0 = __brev(tidx0) >> IDX_SHIFT;
rtidx1 = __brev(tidx1) >> IDX_SHIFT;
stridx0 = rtidx0 + start;
stridx1 = rtidx1 + start;
if(tidx0 + start < size){
// permutation by bit reversal of array indices as 11 bit numbers, requires 32-11 bit shift
signalChunk[tidx0] = ComplexCast(in_re[stridx0], in_im[stridx0]);
signalChunk[tidx1] = ComplexCast(in_re[stridx1], in_im[stridx1]);
__syncthreads();
for (unsigned int s = 0; s < LGSAMP; s++) // 11 values of s as per iterative algorithm for fft (2048 point)
{
tidx0 = threadIdx.x + (threadIdx.x & (~offsets[s]));
tidx1 = tidx0 + offsets[s] + 1;
idx_twid = offsets[s] + (threadIdx.x & offsets[s]);
radius = ComplexMul(signalChunk[tidx1], ComplexCast(twiddles_re[idx_twid], twiddles_im[idx_twid])); // A[j + k + m/2]*w
signalChunk[tidx0] = ComplexAdd(signalChunk[tidx0], radius); // A[j + k] = A[j + k] + A[j + k + m/2]*w
signalChunk[tidx1] = ComplexSub(signalChunk[tidx0], radius); // A[j + k + m/2] = A[j + k] - A[j + k + m/2]*w
__syncthreads();
}
tidx0 = threadIdx.x;
out[tidx0 + start] = ComplexNorm(signalChunk[tidx0]);
// eval for maxFFT, use AtomicMax() here
AtomicMax(&maxFFT, out[tidx0 + start]);
}
}
// use kernel termination as sync point to launch this next kernel named normaliseFinal
__global__ void normaliseFinal(float * out, int size, int gridNum, int gridWidth)
{
int tidx = (gridNum * gridWidth + blockIdx.x) * blockDim.x + threadIdx.x;
if(tidx < size){
out[tidx] = out[tidx] / maxFFT;
}
}
// would be really good to use this with Pinned Memory
// since CPU will be busy reading in wavefile while this is happening
// this doesn't need to be all that optimised, it could even be as sequential
// as the CPU version
// NOTE: this should be 1 block, 11 threads
__global__ void calcTwiddles(float * out_re, float * out_im, float * zerothTwiddles_re, float * zerothTwiddles_im)
{
int tid = threadIdx.x;
Complex runVal; runVal.x = 1; runVal.y = 0; //runVal.z = 0;
for (int i = offsets[tid]; i < 2 * offsets[tid] + 1; i++)
{
out_re[i] = runVal.x;
out_im[i] = runVal.y;
runVal = ComplexMul(runVal, ComplexCast(zerothTwiddles_re[tid], zerothTwiddles_im[tid]));
}
}
void writeBinFile(const char * file_name, float * bin_data, size_t nmemb){
FILE * fp = fopen(file_name, "wb");
printf("writing %s is writing %d in %lu bytes\n",file_name, nmemb, sizeof(float) * nmemb);
fflush(stdout);
fwrite(bin_data, sizeof(float), nmemb, fp);
fflush(fp);
fclose(fp);
}
size_t readBinFile(const char * file_name, float ** bin_data){
FILE * fp = fopen(file_name,"r");
fseek(fp, 0, SEEK_END);
size_t sz = ftell(fp);
size_t nmemb = sz/sizeof(**bin_data);
printf("file %s is %lu elements in %lu bytes\n", file_name, nmemb, sz);
fflush(stdout);
rewind(fp);
*bin_data = (float*)malloc(sz);
fread(*bin_data, sizeof(float), nmemb, fp);
fflush(fp);
fclose(fp);
return nmemb;
}
int main(int argc, char ** argv){
printf("hello\n");
fflush(stdout);
const float pi = 3.1415927410;
const char * wave_bin = "wave_out";
const char * timefreq_ref = "timefreq_out";
const char * timefreq_cmp = "timefreq_done";
const int h_offsets[LGSAMP] = {0,1,3,7,15,31,63,127,255,511,1023};
for(int i = 0; i < LGSAMP; i++) printf("h_offsets[%d] = %d, ", i, h_offsets[i]);
printf("\n");
fflush(stdout);
float h_zerothTwiddles_re[LGSAMP];
float h_zerothTwiddles_im[LGSAMP];
float h_twiddles_re[TWIDDLES_LEN];
float h_twiddles_im[TWIDDLES_LEN];
float a;
float * h_wave_data;
float * h_timefreq_ref_data;
size_t wave_num_els = readBinFile(wave_bin, &h_wave_data);
size_t timefreq_num_els = readBinFile(timefreq_ref, &h_timefreq_ref_data);
// testing bit reversal
float * out;
if((out = (float*)malloc(timefreq_num_els * sizeof(*out))) == NULL)
printf("failed to allocate out");
float * h_timefreq_cmp_data;
printf("Allocating h_timefreq_cmp_data\n");
fflush(stdout);
if((h_timefreq_cmp_data = (float*)malloc(timefreq_num_els * sizeof(*h_timefreq_cmp_data))) == NULL)
printf("failed to allocate h_timefreq_cmp_data");
size_t wave_num_pels = ((size_t)ceil((double)wave_num_els / (double)WSAMP)) * WSAMP;
printf("wave_num_els = %d, wave_num_pels = %d\n", wave_num_els, wave_num_pels);
fflush(stdout);
float ** h_sig_data;
printf("Allocating h_sig_data\n");
fflush(stdout);
if(h_sig_data = (float**)malloc(2 * sizeof(*h_sig_data))){
for(int i = 0; i < 2; i++){
printf("Allocating h_sig_data[%d]\n", i);
if((h_sig_data[i] = (float*)malloc(wave_num_pels * sizeof(**h_sig_data))) == NULL)
printf("failed to allocate h_sig_data[%d]\n", i);
}
}
else printf("failed to allocate h_sig_data\n");
// cast wave data to complex and add padding
printf("Casting wave to complex and padding with zeros\n");
fflush(stdout);
for(int i = 0; i < wave_num_pels; i++)
{
h_sig_data[1][i] = 0;
if(i < wave_num_els){
h_sig_data[0][i] = h_wave_data[i];
}
else h_sig_data[0][i] = 0;
}
// calc zerothTwiddles
printf("Calculating the zeroth twiddles\n");
fflush(stdout);
for (int ii = 0; ii < LGSAMP; ii++)
{
a = -2 * pi / ((double)(2*(h_offsets[ii] + 1)));
//printf("2 * pi * ii = %f, (float)h_offsets[ii] + 1 = %f\n", 2 * pi * ii, (float)h_offsets[ii] + 1);
//fflush(stdout);
h_zerothTwiddles_re[ii] = (float)cos(a);
h_zerothTwiddles_im[ii] = (float)sin(a);
//printf("a = %f, h_zerothTwiddles_re[%d] = %f, h_zerothTwiddles_im[%d] = %f\n",a,ii,h_zerothTwiddles_re[ii],ii,h_zerothTwiddles_im[ii]);
//fflush(stdout);
}
//float chk_twiddles_re[TWIDDLES_LEN];
//float chk_twiddles_im[TWIDDLES_LEN];
//
//for(int s = 0; s < LGSAMP; s++){
// float runVal_re = 1.0f; float temp1;
// float runVal_im = 0.0f;
// for (int i = h_offsets[s]; i < 2 * h_offsets[s] + 1; i++)
// {
// chk_twiddles_re[i] = runVal_re;
// chk_twiddles_im[i] = runVal_im;
// temp1 = runVal_re;
// runVal_re = runVal_re * h_zerothTwiddles_re[s] - runVal_im * h_zerothTwiddles_im[s];
// runVal_im = temp1 * h_zerothTwiddles_im[s] + runVal_im * h_zerothTwiddles_re[s];
// }
//}
/********************** kernel stuff **********************/
// wave data in
printf("Allocating memory on device\n");
fflush(stdout);
float * d_sig_data_re; cudaMalloc(&d_sig_data_re, wave_num_pels * sizeof(*d_sig_data_re));
float * d_sig_data_im; cudaMalloc(&d_sig_data_im, wave_num_pels * sizeof(*d_sig_data_im));
// timefreq data out
//float * d_timefreq_cmp_data; cudaMalloc(&d_timefreq_cmp_data, timefreq_num_els * sizeof(*d_timefreq_cmp_data));
float * d_out; cudaMalloc(&d_out, timefreq_num_els * sizeof(*d_out));
// supporting structures
float * d_zerothTwiddles_re; cudaMalloc(&d_zerothTwiddles_re, TWIDDLES_LEN * sizeof(*d_zerothTwiddles_re));
float * d_zerothTwiddles_im; cudaMalloc(&d_zerothTwiddles_im, TWIDDLES_LEN * sizeof(*d_zerothTwiddles_im));
float * d_twiddles_re; cudaMalloc(&d_twiddles_re, TWIDDLES_LEN * sizeof(*d_twiddles_re));
float * d_twiddles_im; cudaMalloc(&d_twiddles_im, TWIDDLES_LEN * sizeof(*d_twiddles_im));
//int * d_offsets; cudaMalloc(&d_offsets, LGSAMP * sizeof(*d_offsets));
// copy to device
printf("Copying data over to device\n");
fflush(stdout);
gpuAssert( cudaMemcpyToSymbol(offsets, h_offsets, LGSAMP * sizeof(*h_offsets), 0, cudaMemcpyHostToDevice) );
//cudaMemcpy( d_offsets, h_offsets, LGSAMP * sizeof(*d_offsets), cudaMemcpyHostToDevice );
gpuAssert( cudaMemcpy( d_zerothTwiddles_re, h_zerothTwiddles_re, LGSAMP * sizeof(*d_zerothTwiddles_re), cudaMemcpyHostToDevice ) );
gpuAssert( cudaMemcpy( d_zerothTwiddles_im, h_zerothTwiddles_im, LGSAMP * sizeof(*d_zerothTwiddles_im), cudaMemcpyHostToDevice ) );
gpuAssert( cudaMemcpy( d_sig_data_re, h_sig_data[0], wave_num_pels * sizeof(*d_sig_data_re), cudaMemcpyHostToDevice ) );
gpuAssert( cudaMemcpy( d_sig_data_im, h_sig_data[1], wave_num_pels * sizeof(*d_sig_data_im), cudaMemcpyHostToDevice ) );
gpuAssert( cudaMemcpyToSymbol(in_re, &d_sig_data_re, sizeof(float *)) );
gpuAssert( cudaMemcpyToSymbol(in_im, &d_sig_data_im, sizeof(float *)) );
// launch prep kernel
printf("Launching kernel to calc twiddles\n");
fflush(stdout);
calcTwiddles<<<1,11>>>(d_twiddles_re, d_twiddles_im, d_zerothTwiddles_re, d_zerothTwiddles_im);
cudaDeviceSynchronize();
/* this copy to host then back to device may not be necessary */
// copy twiddles back to host
gpuAssert( cudaMemcpy(h_twiddles_re, d_twiddles_re, TWIDDLES_LEN * sizeof(*h_twiddles_re), cudaMemcpyDeviceToHost ) );
gpuAssert( cudaMemcpy(h_twiddles_im, d_twiddles_im, TWIDDLES_LEN * sizeof(*h_twiddles_im), cudaMemcpyDeviceToHost ) );
// copy twiddles back to device
gpuAssert( cudaMemcpyToSymbol(twiddles_re, h_twiddles_re, TWIDDLES_LEN * sizeof(*d_twiddles_re), 0, cudaMemcpyHostToDevice) );
gpuAssert( cudaMemcpyToSymbol(twiddles_im, h_twiddles_im, TWIDDLES_LEN * sizeof(*d_twiddles_im), 0, cudaMemcpyHostToDevice) );
// launch core kernel
int threadsPerBlock = HWSAMP;
int blocksPerGrid = wave_num_pels / (2 * threadsPerBlock);
printf("launching kernel with %d blocks and %d threads per block\n", blocksPerGrid, threadsPerBlock);
fflush(stdout);
int blockEachLaunch = 32;
int iter = 0;
for(; iter < blocksPerGrid/blockEachLaunch; iter++){
core<<<blockEachLaunch, threadsPerBlock, WSAMP * PREC>>>(d_out, timefreq_num_els, iter, blockEachLaunch);
}
if(blocksPerGrid % blockEachLaunch > 0) core<<<blocksPerGrid % blockEachLaunch, threadsPerBlock, WSAMP * PREC>>>(d_out, timefreq_num_els, iter, blockEachLaunch);
cudaDeviceSynchronize();
/* this copy to host then back to device may not be necessary */
//// copy results back from device
//cudaMemcpy(h_timefreq_cmp_data, d_timefreq_cmp_data, timefreq_num_els * sizeof(*h_timefreq_cmp_data), cudaMemcpyDeviceToHost );
//
//// copy results back to device
//cudaMemcpy(d_timefreq_cmp_data, h_timefreq_data, timefreq_num_els * sizeof(*d_timefreq_cmp_data), cudaMemcpyHostToDevice );
// launch kernel to normalise the data
iter = 0;
for(; iter < blocksPerGrid/blockEachLaunch; iter++){
normaliseFinal<<<blockEachLaunch, threadsPerBlock>>>(d_out, timefreq_num_els, iter, blockEachLaunch);
}
if(blocksPerGrid % blockEachLaunch > 0) normaliseFinal<<<blocksPerGrid % blockEachLaunch, threadsPerBlock>>>(d_out, timefreq_num_els, iter, blockEachLaunch);
cudaDeviceSynchronize();
// copy final results back to host
//cudaMemcpy(h_timefreq_cmp_data, d_timefreq_cmp_data, timefreq_num_els * sizeof(*h_timefreq_cmp_data), cudaMemcpyDeviceToHost );
gpuAssert( cudaMemcpy(out, d_out, timefreq_num_els * sizeof(*out), cudaMemcpyDeviceToHost ) );
gpuAssert( cudaFree(d_out) );
// clean up device memory
gpuAssert( cudaFree(d_sig_data_re) );
gpuAssert( cudaFree(d_sig_data_im) );
gpuAssert( cudaFree(d_zerothTwiddles_re) );
gpuAssert( cudaFree(d_zerothTwiddles_im) );
gpuAssert( cudaFree(d_twiddles_re) );
gpuAssert( cudaFree(d_twiddles_im) );
/********************** /kernel stuff **********************/
//for(int i = 0; i < timefreq_num_els; i++) printf("%f ", out[i]);
//printf("Writing results to timefreq_done. int is %lu bytes.\n", sizeof(int));
writeBinFile(timefreq_cmp, out, timefreq_num_els);
free(out);
free(h_timefreq_ref_data);
free(h_timefreq_cmp_data);
free(h_wave_data);
}
// -gencode arch=compute_50,code=sm_50 | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#ifndef gpuAssert
#define gpuAssert( condition ) { if( (condition) != hipSuccess ) { fprintf( stderr, "\n FAILURE %s in %s, line %d\n", hipGetErrorString(condition), __FILE__, __LINE__ ); exit( 1 ); } }
#endif
#define PREC 8
// I've used a snippet of someone elses code, and one condition of use is
// to retain this licensing message
// I obtained the code from:
// https://github.com/parallel-forall/code-samples/blob/master/posts/cuda-aware-mpi-example/src/Device.cu
/* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of NVIDIA CORPORATION nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************/
/* borrowed just one function for AtomicMax on floats from github */
/**
* @brief Compute the maximum of 2 single-precision floating point values using an atomic operation
*
* @param[in] address The address of the reference value which might get updated with the maximum
* @param[in] value The value that is compared to the reference in order to determine the maximum
*/
static __device__ void AtomicMax(float * const address, float value)
{
if (*address >= value)
{
return;
}
int * const address_as_i = (int *)address;
int old = *address_as_i, assumed;
do
{
assumed = old;
if (__int_as_float(assumed) >= value)
{
break;
}
old = atomicCAS(address_as_i, assumed, __float_as_int(value));
} while (assumed != old);
}
/******************************************************************/
// don't actually need this, as you can & with offsets instead
//#define B01_MASK 0b0000000000000001
//#define B02_MASK 0b0000000000000011
//#define B03_MASK 0b0000000000000111
//#define B04_MASK 0b0000000000001111
//#define B05_MASK 0b0000000000011111
//#define B06_MASK 0b0000000000111111
//#define B07_MASK 0b0000000001111111
//#define B08_MASK 0b0000000011111111
//#define B09_MASK 0b0000000111111111
//#define B10_MASK 0b0000001111111111
// * bitwise div of power 2 num (i\n): i >> log2(n)
// * bitwise modulo of power of 2 num(i % n) : i & (n - 1)
// much of the efficiency of this implementation hinges of being able to apply
// very fast bitwise manipulations which will only be reliable in cases where
// the fundamental dimensionality of the data is strictly by powers of 2
// happily this is the case in this application, and for fft in general
// more specifically, exploiting the luxury of powers of 2 enables the construction
// of blocks that should be (theoretically) entirely divergence free, which also means
// that the __syncthreads statements, though necessary to ensure correctness, are in practice
// often a "formality", as all warps should be finishing at the same time, provided all
// memory accesses to shared and constant memory can be performed in the same number of
// clock cycles, this is also one of the reasons behind using constant and shared memory.
// though this implementation fixes on 2048 point fft, it could easily be generalised
// to any 2^s point fft needed. There is a happy coincidence, where my particular GPU
// is limited to 1024 threads per block, and a 2048 point iterative fft unrolls its
// two inner loops to 1024 every time. This is optimal, but only by coincidence. Were
// this happy coincidence not to be relied upon, then further optimisations which take
// intra-block synchronisation, and possibly where warp boundaries will cross, might need
// to be included.
// precision: it must also be mentioned that a loss of precision is being spent on performance
// Nvidia GPUs with Compute Cabaility 5.0 can only assure atomic arithmetic for single precision
// floats, and the registers available to the threads are also 32 bit registers. For this reason,
// the decision was made to reduce the precision from double to single
#define TWIDDLES_LEN 2047
#define LGSAMP 11
#define WSAMP 2048
#define HWSAMP (WSAMP / 2)
#define IDX_SHIFT (32 - LGSAMP)
//typedef float3 Complex; // padding to avoid bank conflicts - might not be needed in CUDA 9.0
typedef float2 Complex;
static __device__ inline Complex ComplexCast(float a, float b);
static __device__ inline Complex ComplexAdd(Complex a, Complex b);
static __device__ inline Complex ComplexSub(Complex a, Complex b);
static __device__ inline Complex ComplexMul(Complex a, Complex b);
static __device__ inline float ComplexNorm(Complex a);
static __device__ inline Complex ComplexCast(float a, float b)
{
Complex c;
c.x = a; c.y = b;
//c.z = 0;
return c;
}
// Complex addition
static __device__ inline Complex ComplexAdd(Complex a, Complex b)
{
Complex c;
c.x = a.x + b.x;
c.y = a.y + b.y;
//c.z = 0; // padding to avoid bank conflicts - might not be needed in CUDA 9.0
return c;
}
// Complex subtraction
static __device__ inline Complex ComplexSub(Complex a, Complex b)
{
Complex c;
c.x = a.x - b.x;
c.y = a.y - b.y;
//c.z = 0; // padding to avoid bank conflicts - might not be needed in CUDA 9.0
return c;
}
// Complex multiplication
static __device__ inline Complex ComplexMul(Complex a, Complex b)
{
Complex c;
c.x = a.x * b.x - a.y * b.y;
c.y = a.x * b.y + a.y * b.x;
//c.z = 0; // padding to avoid bank conflicts - might not be needed in CUDA 9.0
return c;
}
// Fast calc of Norm of a Complex Number
static __device__ inline float ComplexNorm(Complex a) { return sqrt(a.x*a.x + a.y*a.y); }
__device__ __constant__ int offsets[LGSAMP];
__device__ __constant__ float twiddles_re[TWIDDLES_LEN];
__device__ __constant__ float twiddles_im[TWIDDLES_LEN];
__device__ float * in_re;
__device__ float * in_im;
static __device__ float maxFFT = 0;
// would be really good to use this with Pinned Memory
__global__ void core(float * out, int size, int gridNum, int gridWidth)
{
extern __shared__ Complex signalChunk[]; // twice the size of 1024 threads in block
int tidx0, tidx1, rtidx0, rtidx1, stridx0, stridx1, idx_twid;
Complex radius;
int start = (gridNum * gridWidth + blockIdx.x) * blockDim.x; // start of the block, threadIdx.x == 0
tidx0 = threadIdx.x;
tidx1 = threadIdx.x + HWSAMP;
rtidx0 = __brev(tidx0) >> IDX_SHIFT;
rtidx1 = __brev(tidx1) >> IDX_SHIFT;
stridx0 = rtidx0 + start;
stridx1 = rtidx1 + start;
if(tidx0 + start < size){
// permutation by bit reversal of array indices as 11 bit numbers, requires 32-11 bit shift
signalChunk[tidx0] = ComplexCast(in_re[stridx0], in_im[stridx0]);
signalChunk[tidx1] = ComplexCast(in_re[stridx1], in_im[stridx1]);
__syncthreads();
for (unsigned int s = 0; s < LGSAMP; s++) // 11 values of s as per iterative algorithm for fft (2048 point)
{
tidx0 = threadIdx.x + (threadIdx.x & (~offsets[s]));
tidx1 = tidx0 + offsets[s] + 1;
idx_twid = offsets[s] + (threadIdx.x & offsets[s]);
radius = ComplexMul(signalChunk[tidx1], ComplexCast(twiddles_re[idx_twid], twiddles_im[idx_twid])); // A[j + k + m/2]*w
signalChunk[tidx0] = ComplexAdd(signalChunk[tidx0], radius); // A[j + k] = A[j + k] + A[j + k + m/2]*w
signalChunk[tidx1] = ComplexSub(signalChunk[tidx0], radius); // A[j + k + m/2] = A[j + k] - A[j + k + m/2]*w
__syncthreads();
}
tidx0 = threadIdx.x;
out[tidx0 + start] = ComplexNorm(signalChunk[tidx0]);
// eval for maxFFT, use AtomicMax() here
AtomicMax(&maxFFT, out[tidx0 + start]);
}
}
// use kernel termination as sync point to launch this next kernel named normaliseFinal
__global__ void normaliseFinal(float * out, int size, int gridNum, int gridWidth)
{
int tidx = (gridNum * gridWidth + blockIdx.x) * blockDim.x + threadIdx.x;
if(tidx < size){
out[tidx] = out[tidx] / maxFFT;
}
}
// would be really good to use this with Pinned Memory
// since CPU will be busy reading in wavefile while this is happening
// this doesn't need to be all that optimised, it could even be as sequential
// as the CPU version
// NOTE: this should be 1 block, 11 threads
__global__ void calcTwiddles(float * out_re, float * out_im, float * zerothTwiddles_re, float * zerothTwiddles_im)
{
int tid = threadIdx.x;
Complex runVal; runVal.x = 1; runVal.y = 0; //runVal.z = 0;
for (int i = offsets[tid]; i < 2 * offsets[tid] + 1; i++)
{
out_re[i] = runVal.x;
out_im[i] = runVal.y;
runVal = ComplexMul(runVal, ComplexCast(zerothTwiddles_re[tid], zerothTwiddles_im[tid]));
}
}
void writeBinFile(const char * file_name, float * bin_data, size_t nmemb){
FILE * fp = fopen(file_name, "wb");
printf("writing %s is writing %d in %lu bytes\n",file_name, nmemb, sizeof(float) * nmemb);
fflush(stdout);
fwrite(bin_data, sizeof(float), nmemb, fp);
fflush(fp);
fclose(fp);
}
size_t readBinFile(const char * file_name, float ** bin_data){
FILE * fp = fopen(file_name,"r");
fseek(fp, 0, SEEK_END);
size_t sz = ftell(fp);
size_t nmemb = sz/sizeof(**bin_data);
printf("file %s is %lu elements in %lu bytes\n", file_name, nmemb, sz);
fflush(stdout);
rewind(fp);
*bin_data = (float*)malloc(sz);
fread(*bin_data, sizeof(float), nmemb, fp);
fflush(fp);
fclose(fp);
return nmemb;
}
int main(int argc, char ** argv){
printf("hello\n");
fflush(stdout);
const float pi = 3.1415927410;
const char * wave_bin = "wave_out";
const char * timefreq_ref = "timefreq_out";
const char * timefreq_cmp = "timefreq_done";
const int h_offsets[LGSAMP] = {0,1,3,7,15,31,63,127,255,511,1023};
for(int i = 0; i < LGSAMP; i++) printf("h_offsets[%d] = %d, ", i, h_offsets[i]);
printf("\n");
fflush(stdout);
float h_zerothTwiddles_re[LGSAMP];
float h_zerothTwiddles_im[LGSAMP];
float h_twiddles_re[TWIDDLES_LEN];
float h_twiddles_im[TWIDDLES_LEN];
float a;
float * h_wave_data;
float * h_timefreq_ref_data;
size_t wave_num_els = readBinFile(wave_bin, &h_wave_data);
size_t timefreq_num_els = readBinFile(timefreq_ref, &h_timefreq_ref_data);
// testing bit reversal
float * out;
if((out = (float*)malloc(timefreq_num_els * sizeof(*out))) == NULL)
printf("failed to allocate out");
float * h_timefreq_cmp_data;
printf("Allocating h_timefreq_cmp_data\n");
fflush(stdout);
if((h_timefreq_cmp_data = (float*)malloc(timefreq_num_els * sizeof(*h_timefreq_cmp_data))) == NULL)
printf("failed to allocate h_timefreq_cmp_data");
size_t wave_num_pels = ((size_t)ceil((double)wave_num_els / (double)WSAMP)) * WSAMP;
printf("wave_num_els = %d, wave_num_pels = %d\n", wave_num_els, wave_num_pels);
fflush(stdout);
float ** h_sig_data;
printf("Allocating h_sig_data\n");
fflush(stdout);
if(h_sig_data = (float**)malloc(2 * sizeof(*h_sig_data))){
for(int i = 0; i < 2; i++){
printf("Allocating h_sig_data[%d]\n", i);
if((h_sig_data[i] = (float*)malloc(wave_num_pels * sizeof(**h_sig_data))) == NULL)
printf("failed to allocate h_sig_data[%d]\n", i);
}
}
else printf("failed to allocate h_sig_data\n");
// cast wave data to complex and add padding
printf("Casting wave to complex and padding with zeros\n");
fflush(stdout);
for(int i = 0; i < wave_num_pels; i++)
{
h_sig_data[1][i] = 0;
if(i < wave_num_els){
h_sig_data[0][i] = h_wave_data[i];
}
else h_sig_data[0][i] = 0;
}
// calc zerothTwiddles
printf("Calculating the zeroth twiddles\n");
fflush(stdout);
for (int ii = 0; ii < LGSAMP; ii++)
{
a = -2 * pi / ((double)(2*(h_offsets[ii] + 1)));
//printf("2 * pi * ii = %f, (float)h_offsets[ii] + 1 = %f\n", 2 * pi * ii, (float)h_offsets[ii] + 1);
//fflush(stdout);
h_zerothTwiddles_re[ii] = (float)cos(a);
h_zerothTwiddles_im[ii] = (float)sin(a);
//printf("a = %f, h_zerothTwiddles_re[%d] = %f, h_zerothTwiddles_im[%d] = %f\n",a,ii,h_zerothTwiddles_re[ii],ii,h_zerothTwiddles_im[ii]);
//fflush(stdout);
}
//float chk_twiddles_re[TWIDDLES_LEN];
//float chk_twiddles_im[TWIDDLES_LEN];
//
//for(int s = 0; s < LGSAMP; s++){
// float runVal_re = 1.0f; float temp1;
// float runVal_im = 0.0f;
// for (int i = h_offsets[s]; i < 2 * h_offsets[s] + 1; i++)
// {
// chk_twiddles_re[i] = runVal_re;
// chk_twiddles_im[i] = runVal_im;
// temp1 = runVal_re;
// runVal_re = runVal_re * h_zerothTwiddles_re[s] - runVal_im * h_zerothTwiddles_im[s];
// runVal_im = temp1 * h_zerothTwiddles_im[s] + runVal_im * h_zerothTwiddles_re[s];
// }
//}
/********************** kernel stuff **********************/
// wave data in
printf("Allocating memory on device\n");
fflush(stdout);
float * d_sig_data_re; hipMalloc(&d_sig_data_re, wave_num_pels * sizeof(*d_sig_data_re));
float * d_sig_data_im; hipMalloc(&d_sig_data_im, wave_num_pels * sizeof(*d_sig_data_im));
// timefreq data out
//float * d_timefreq_cmp_data; cudaMalloc(&d_timefreq_cmp_data, timefreq_num_els * sizeof(*d_timefreq_cmp_data));
float * d_out; hipMalloc(&d_out, timefreq_num_els * sizeof(*d_out));
// supporting structures
float * d_zerothTwiddles_re; hipMalloc(&d_zerothTwiddles_re, TWIDDLES_LEN * sizeof(*d_zerothTwiddles_re));
float * d_zerothTwiddles_im; hipMalloc(&d_zerothTwiddles_im, TWIDDLES_LEN * sizeof(*d_zerothTwiddles_im));
float * d_twiddles_re; hipMalloc(&d_twiddles_re, TWIDDLES_LEN * sizeof(*d_twiddles_re));
float * d_twiddles_im; hipMalloc(&d_twiddles_im, TWIDDLES_LEN * sizeof(*d_twiddles_im));
//int * d_offsets; cudaMalloc(&d_offsets, LGSAMP * sizeof(*d_offsets));
// copy to device
printf("Copying data over to device\n");
fflush(stdout);
gpuAssert( hipMemcpyToSymbol(HIP_SYMBOL(offsets), h_offsets, LGSAMP * sizeof(*h_offsets), 0, hipMemcpyHostToDevice) );
//cudaMemcpy( d_offsets, h_offsets, LGSAMP * sizeof(*d_offsets), cudaMemcpyHostToDevice );
gpuAssert( hipMemcpy( d_zerothTwiddles_re, h_zerothTwiddles_re, LGSAMP * sizeof(*d_zerothTwiddles_re), hipMemcpyHostToDevice ) );
gpuAssert( hipMemcpy( d_zerothTwiddles_im, h_zerothTwiddles_im, LGSAMP * sizeof(*d_zerothTwiddles_im), hipMemcpyHostToDevice ) );
gpuAssert( hipMemcpy( d_sig_data_re, h_sig_data[0], wave_num_pels * sizeof(*d_sig_data_re), hipMemcpyHostToDevice ) );
gpuAssert( hipMemcpy( d_sig_data_im, h_sig_data[1], wave_num_pels * sizeof(*d_sig_data_im), hipMemcpyHostToDevice ) );
gpuAssert( hipMemcpyToSymbol(HIP_SYMBOL(in_re), &d_sig_data_re, sizeof(float *)) );
gpuAssert( hipMemcpyToSymbol(HIP_SYMBOL(in_im), &d_sig_data_im, sizeof(float *)) );
// launch prep kernel
printf("Launching kernel to calc twiddles\n");
fflush(stdout);
calcTwiddles<<<1,11>>>(d_twiddles_re, d_twiddles_im, d_zerothTwiddles_re, d_zerothTwiddles_im);
hipDeviceSynchronize();
/* this copy to host then back to device may not be necessary */
// copy twiddles back to host
gpuAssert( hipMemcpy(h_twiddles_re, d_twiddles_re, TWIDDLES_LEN * sizeof(*h_twiddles_re), hipMemcpyDeviceToHost ) );
gpuAssert( hipMemcpy(h_twiddles_im, d_twiddles_im, TWIDDLES_LEN * sizeof(*h_twiddles_im), hipMemcpyDeviceToHost ) );
// copy twiddles back to device
gpuAssert( hipMemcpyToSymbol(HIP_SYMBOL(twiddles_re), h_twiddles_re, TWIDDLES_LEN * sizeof(*d_twiddles_re), 0, hipMemcpyHostToDevice) );
gpuAssert( hipMemcpyToSymbol(HIP_SYMBOL(twiddles_im), h_twiddles_im, TWIDDLES_LEN * sizeof(*d_twiddles_im), 0, hipMemcpyHostToDevice) );
// launch core kernel
int threadsPerBlock = HWSAMP;
int blocksPerGrid = wave_num_pels / (2 * threadsPerBlock);
printf("launching kernel with %d blocks and %d threads per block\n", blocksPerGrid, threadsPerBlock);
fflush(stdout);
int blockEachLaunch = 32;
int iter = 0;
for(; iter < blocksPerGrid/blockEachLaunch; iter++){
core<<<blockEachLaunch, threadsPerBlock, WSAMP * PREC>>>(d_out, timefreq_num_els, iter, blockEachLaunch);
}
if(blocksPerGrid % blockEachLaunch > 0) core<<<blocksPerGrid % blockEachLaunch, threadsPerBlock, WSAMP * PREC>>>(d_out, timefreq_num_els, iter, blockEachLaunch);
hipDeviceSynchronize();
/* this copy to host then back to device may not be necessary */
//// copy results back from device
//cudaMemcpy(h_timefreq_cmp_data, d_timefreq_cmp_data, timefreq_num_els * sizeof(*h_timefreq_cmp_data), cudaMemcpyDeviceToHost );
//
//// copy results back to device
//cudaMemcpy(d_timefreq_cmp_data, h_timefreq_data, timefreq_num_els * sizeof(*d_timefreq_cmp_data), cudaMemcpyHostToDevice );
// launch kernel to normalise the data
iter = 0;
for(; iter < blocksPerGrid/blockEachLaunch; iter++){
normaliseFinal<<<blockEachLaunch, threadsPerBlock>>>(d_out, timefreq_num_els, iter, blockEachLaunch);
}
if(blocksPerGrid % blockEachLaunch > 0) normaliseFinal<<<blocksPerGrid % blockEachLaunch, threadsPerBlock>>>(d_out, timefreq_num_els, iter, blockEachLaunch);
hipDeviceSynchronize();
// copy final results back to host
//cudaMemcpy(h_timefreq_cmp_data, d_timefreq_cmp_data, timefreq_num_els * sizeof(*h_timefreq_cmp_data), cudaMemcpyDeviceToHost );
gpuAssert( hipMemcpy(out, d_out, timefreq_num_els * sizeof(*out), hipMemcpyDeviceToHost ) );
gpuAssert( hipFree(d_out) );
// clean up device memory
gpuAssert( hipFree(d_sig_data_re) );
gpuAssert( hipFree(d_sig_data_im) );
gpuAssert( hipFree(d_zerothTwiddles_re) );
gpuAssert( hipFree(d_zerothTwiddles_im) );
gpuAssert( hipFree(d_twiddles_re) );
gpuAssert( hipFree(d_twiddles_im) );
/********************** /kernel stuff **********************/
//for(int i = 0; i < timefreq_num_els; i++) printf("%f ", out[i]);
//printf("Writing results to timefreq_done. int is %lu bytes.\n", sizeof(int));
writeBinFile(timefreq_cmp, out, timefreq_num_els);
free(out);
free(h_timefreq_ref_data);
free(h_timefreq_cmp_data);
free(h_wave_data);
}
// -gencode arch=compute_50,code=sm_50 |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#ifndef gpuAssert
#define gpuAssert( condition ) { if( (condition) != hipSuccess ) { fprintf( stderr, "\n FAILURE %s in %s, line %d\n", hipGetErrorString(condition), __FILE__, __LINE__ ); exit( 1 ); } }
#endif
#define PREC 8
// I've used a snippet of someone elses code, and one condition of use is
// to retain this licensing message
// I obtained the code from:
// https://github.com/parallel-forall/code-samples/blob/master/posts/cuda-aware-mpi-example/src/Device.cu
/* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of NVIDIA CORPORATION nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************/
/* borrowed just one function for AtomicMax on floats from github */
/**
* @brief Compute the maximum of 2 single-precision floating point values using an atomic operation
*
* @param[in] address The address of the reference value which might get updated with the maximum
* @param[in] value The value that is compared to the reference in order to determine the maximum
*/
static __device__ void AtomicMax(float * const address, float value)
{
if (*address >= value)
{
return;
}
int * const address_as_i = (int *)address;
int old = *address_as_i, assumed;
do
{
assumed = old;
if (__int_as_float(assumed) >= value)
{
break;
}
old = atomicCAS(address_as_i, assumed, __float_as_int(value));
} while (assumed != old);
}
/******************************************************************/
// don't actually need this, as you can & with offsets instead
//#define B01_MASK 0b0000000000000001
//#define B02_MASK 0b0000000000000011
//#define B03_MASK 0b0000000000000111
//#define B04_MASK 0b0000000000001111
//#define B05_MASK 0b0000000000011111
//#define B06_MASK 0b0000000000111111
//#define B07_MASK 0b0000000001111111
//#define B08_MASK 0b0000000011111111
//#define B09_MASK 0b0000000111111111
//#define B10_MASK 0b0000001111111111
// * bitwise div of power 2 num (i\n): i >> log2(n)
// * bitwise modulo of power of 2 num(i % n) : i & (n - 1)
// much of the efficiency of this implementation hinges of being able to apply
// very fast bitwise manipulations which will only be reliable in cases where
// the fundamental dimensionality of the data is strictly by powers of 2
// happily this is the case in this application, and for fft in general
// more specifically, exploiting the luxury of powers of 2 enables the construction
// of blocks that should be (theoretically) entirely divergence free, which also means
// that the __syncthreads statements, though necessary to ensure correctness, are in practice
// often a "formality", as all warps should be finishing at the same time, provided all
// memory accesses to shared and constant memory can be performed in the same number of
// clock cycles, this is also one of the reasons behind using constant and shared memory.
// though this implementation fixes on 2048 point fft, it could easily be generalised
// to any 2^s point fft needed. There is a happy coincidence, where my particular GPU
// is limited to 1024 threads per block, and a 2048 point iterative fft unrolls its
// two inner loops to 1024 every time. This is optimal, but only by coincidence. Were
// this happy coincidence not to be relied upon, then further optimisations which take
// intra-block synchronisation, and possibly where warp boundaries will cross, might need
// to be included.
// precision: it must also be mentioned that a loss of precision is being spent on performance
// Nvidia GPUs with Compute Cabaility 5.0 can only assure atomic arithmetic for single precision
// floats, and the registers available to the threads are also 32 bit registers. For this reason,
// the decision was made to reduce the precision from double to single
#define TWIDDLES_LEN 2047
#define LGSAMP 11
#define WSAMP 2048
#define HWSAMP (WSAMP / 2)
#define IDX_SHIFT (32 - LGSAMP)
//typedef float3 Complex; // padding to avoid bank conflicts - might not be needed in CUDA 9.0
typedef float2 Complex;
static __device__ inline Complex ComplexCast(float a, float b);
static __device__ inline Complex ComplexAdd(Complex a, Complex b);
static __device__ inline Complex ComplexSub(Complex a, Complex b);
static __device__ inline Complex ComplexMul(Complex a, Complex b);
static __device__ inline float ComplexNorm(Complex a);
static __device__ inline Complex ComplexCast(float a, float b)
{
Complex c;
c.x = a; c.y = b;
//c.z = 0;
return c;
}
// Complex addition
static __device__ inline Complex ComplexAdd(Complex a, Complex b)
{
Complex c;
c.x = a.x + b.x;
c.y = a.y + b.y;
//c.z = 0; // padding to avoid bank conflicts - might not be needed in CUDA 9.0
return c;
}
// Complex subtraction
static __device__ inline Complex ComplexSub(Complex a, Complex b)
{
Complex c;
c.x = a.x - b.x;
c.y = a.y - b.y;
//c.z = 0; // padding to avoid bank conflicts - might not be needed in CUDA 9.0
return c;
}
// Complex multiplication
static __device__ inline Complex ComplexMul(Complex a, Complex b)
{
Complex c;
c.x = a.x * b.x - a.y * b.y;
c.y = a.x * b.y + a.y * b.x;
//c.z = 0; // padding to avoid bank conflicts - might not be needed in CUDA 9.0
return c;
}
// Fast calc of Norm of a Complex Number
static __device__ inline float ComplexNorm(Complex a) { return sqrt(a.x*a.x + a.y*a.y); }
__device__ __constant__ int offsets[LGSAMP];
__device__ __constant__ float twiddles_re[TWIDDLES_LEN];
__device__ __constant__ float twiddles_im[TWIDDLES_LEN];
__device__ float * in_re;
__device__ float * in_im;
static __device__ float maxFFT = 0;
// would be really good to use this with Pinned Memory
__global__ void core(float * out, int size, int gridNum, int gridWidth)
{
extern __shared__ Complex signalChunk[]; // twice the size of 1024 threads in block
int tidx0, tidx1, rtidx0, rtidx1, stridx0, stridx1, idx_twid;
Complex radius;
int start = (gridNum * gridWidth + blockIdx.x) * blockDim.x; // start of the block, threadIdx.x == 0
tidx0 = threadIdx.x;
tidx1 = threadIdx.x + HWSAMP;
rtidx0 = __brev(tidx0) >> IDX_SHIFT;
rtidx1 = __brev(tidx1) >> IDX_SHIFT;
stridx0 = rtidx0 + start;
stridx1 = rtidx1 + start;
if(tidx0 + start < size){
// permutation by bit reversal of array indices as 11 bit numbers, requires 32-11 bit shift
signalChunk[tidx0] = ComplexCast(in_re[stridx0], in_im[stridx0]);
signalChunk[tidx1] = ComplexCast(in_re[stridx1], in_im[stridx1]);
__syncthreads();
for (unsigned int s = 0; s < LGSAMP; s++) // 11 values of s as per iterative algorithm for fft (2048 point)
{
tidx0 = threadIdx.x + (threadIdx.x & (~offsets[s]));
tidx1 = tidx0 + offsets[s] + 1;
idx_twid = offsets[s] + (threadIdx.x & offsets[s]);
radius = ComplexMul(signalChunk[tidx1], ComplexCast(twiddles_re[idx_twid], twiddles_im[idx_twid])); // A[j + k + m/2]*w
signalChunk[tidx0] = ComplexAdd(signalChunk[tidx0], radius); // A[j + k] = A[j + k] + A[j + k + m/2]*w
signalChunk[tidx1] = ComplexSub(signalChunk[tidx0], radius); // A[j + k + m/2] = A[j + k] - A[j + k + m/2]*w
__syncthreads();
}
tidx0 = threadIdx.x;
out[tidx0 + start] = ComplexNorm(signalChunk[tidx0]);
// eval for maxFFT, use AtomicMax() here
AtomicMax(&maxFFT, out[tidx0 + start]);
}
}
// use kernel termination as sync point to launch this next kernel named normaliseFinal
__global__ void normaliseFinal(float * out, int size, int gridNum, int gridWidth)
{
int tidx = (gridNum * gridWidth + blockIdx.x) * blockDim.x + threadIdx.x;
if(tidx < size){
out[tidx] = out[tidx] / maxFFT;
}
}
// would be really good to use this with Pinned Memory
// since CPU will be busy reading in wavefile while this is happening
// this doesn't need to be all that optimised, it could even be as sequential
// as the CPU version
// NOTE: this should be 1 block, 11 threads
__global__ void calcTwiddles(float * out_re, float * out_im, float * zerothTwiddles_re, float * zerothTwiddles_im)
{
int tid = threadIdx.x;
Complex runVal; runVal.x = 1; runVal.y = 0; //runVal.z = 0;
for (int i = offsets[tid]; i < 2 * offsets[tid] + 1; i++)
{
out_re[i] = runVal.x;
out_im[i] = runVal.y;
runVal = ComplexMul(runVal, ComplexCast(zerothTwiddles_re[tid], zerothTwiddles_im[tid]));
}
}
void writeBinFile(const char * file_name, float * bin_data, size_t nmemb){
FILE * fp = fopen(file_name, "wb");
printf("writing %s is writing %d in %lu bytes\n",file_name, nmemb, sizeof(float) * nmemb);
fflush(stdout);
fwrite(bin_data, sizeof(float), nmemb, fp);
fflush(fp);
fclose(fp);
}
size_t readBinFile(const char * file_name, float ** bin_data){
FILE * fp = fopen(file_name,"r");
fseek(fp, 0, SEEK_END);
size_t sz = ftell(fp);
size_t nmemb = sz/sizeof(**bin_data);
printf("file %s is %lu elements in %lu bytes\n", file_name, nmemb, sz);
fflush(stdout);
rewind(fp);
*bin_data = (float*)malloc(sz);
fread(*bin_data, sizeof(float), nmemb, fp);
fflush(fp);
fclose(fp);
return nmemb;
}
int main(int argc, char ** argv){
printf("hello\n");
fflush(stdout);
const float pi = 3.1415927410;
const char * wave_bin = "wave_out";
const char * timefreq_ref = "timefreq_out";
const char * timefreq_cmp = "timefreq_done";
const int h_offsets[LGSAMP] = {0,1,3,7,15,31,63,127,255,511,1023};
for(int i = 0; i < LGSAMP; i++) printf("h_offsets[%d] = %d, ", i, h_offsets[i]);
printf("\n");
fflush(stdout);
float h_zerothTwiddles_re[LGSAMP];
float h_zerothTwiddles_im[LGSAMP];
float h_twiddles_re[TWIDDLES_LEN];
float h_twiddles_im[TWIDDLES_LEN];
float a;
float * h_wave_data;
float * h_timefreq_ref_data;
size_t wave_num_els = readBinFile(wave_bin, &h_wave_data);
size_t timefreq_num_els = readBinFile(timefreq_ref, &h_timefreq_ref_data);
// testing bit reversal
float * out;
if((out = (float*)malloc(timefreq_num_els * sizeof(*out))) == NULL)
printf("failed to allocate out");
float * h_timefreq_cmp_data;
printf("Allocating h_timefreq_cmp_data\n");
fflush(stdout);
if((h_timefreq_cmp_data = (float*)malloc(timefreq_num_els * sizeof(*h_timefreq_cmp_data))) == NULL)
printf("failed to allocate h_timefreq_cmp_data");
size_t wave_num_pels = ((size_t)ceil((double)wave_num_els / (double)WSAMP)) * WSAMP;
printf("wave_num_els = %d, wave_num_pels = %d\n", wave_num_els, wave_num_pels);
fflush(stdout);
float ** h_sig_data;
printf("Allocating h_sig_data\n");
fflush(stdout);
if(h_sig_data = (float**)malloc(2 * sizeof(*h_sig_data))){
for(int i = 0; i < 2; i++){
printf("Allocating h_sig_data[%d]\n", i);
if((h_sig_data[i] = (float*)malloc(wave_num_pels * sizeof(**h_sig_data))) == NULL)
printf("failed to allocate h_sig_data[%d]\n", i);
}
}
else printf("failed to allocate h_sig_data\n");
// cast wave data to complex and add padding
printf("Casting wave to complex and padding with zeros\n");
fflush(stdout);
for(int i = 0; i < wave_num_pels; i++)
{
h_sig_data[1][i] = 0;
if(i < wave_num_els){
h_sig_data[0][i] = h_wave_data[i];
}
else h_sig_data[0][i] = 0;
}
// calc zerothTwiddles
printf("Calculating the zeroth twiddles\n");
fflush(stdout);
for (int ii = 0; ii < LGSAMP; ii++)
{
a = -2 * pi / ((double)(2*(h_offsets[ii] + 1)));
//printf("2 * pi * ii = %f, (float)h_offsets[ii] + 1 = %f\n", 2 * pi * ii, (float)h_offsets[ii] + 1);
//fflush(stdout);
h_zerothTwiddles_re[ii] = (float)cos(a);
h_zerothTwiddles_im[ii] = (float)sin(a);
//printf("a = %f, h_zerothTwiddles_re[%d] = %f, h_zerothTwiddles_im[%d] = %f\n",a,ii,h_zerothTwiddles_re[ii],ii,h_zerothTwiddles_im[ii]);
//fflush(stdout);
}
//float chk_twiddles_re[TWIDDLES_LEN];
//float chk_twiddles_im[TWIDDLES_LEN];
//
//for(int s = 0; s < LGSAMP; s++){
// float runVal_re = 1.0f; float temp1;
// float runVal_im = 0.0f;
// for (int i = h_offsets[s]; i < 2 * h_offsets[s] + 1; i++)
// {
// chk_twiddles_re[i] = runVal_re;
// chk_twiddles_im[i] = runVal_im;
// temp1 = runVal_re;
// runVal_re = runVal_re * h_zerothTwiddles_re[s] - runVal_im * h_zerothTwiddles_im[s];
// runVal_im = temp1 * h_zerothTwiddles_im[s] + runVal_im * h_zerothTwiddles_re[s];
// }
//}
/********************** kernel stuff **********************/
// wave data in
printf("Allocating memory on device\n");
fflush(stdout);
float * d_sig_data_re; hipMalloc(&d_sig_data_re, wave_num_pels * sizeof(*d_sig_data_re));
float * d_sig_data_im; hipMalloc(&d_sig_data_im, wave_num_pels * sizeof(*d_sig_data_im));
// timefreq data out
//float * d_timefreq_cmp_data; cudaMalloc(&d_timefreq_cmp_data, timefreq_num_els * sizeof(*d_timefreq_cmp_data));
float * d_out; hipMalloc(&d_out, timefreq_num_els * sizeof(*d_out));
// supporting structures
float * d_zerothTwiddles_re; hipMalloc(&d_zerothTwiddles_re, TWIDDLES_LEN * sizeof(*d_zerothTwiddles_re));
float * d_zerothTwiddles_im; hipMalloc(&d_zerothTwiddles_im, TWIDDLES_LEN * sizeof(*d_zerothTwiddles_im));
float * d_twiddles_re; hipMalloc(&d_twiddles_re, TWIDDLES_LEN * sizeof(*d_twiddles_re));
float * d_twiddles_im; hipMalloc(&d_twiddles_im, TWIDDLES_LEN * sizeof(*d_twiddles_im));
//int * d_offsets; cudaMalloc(&d_offsets, LGSAMP * sizeof(*d_offsets));
// copy to device
printf("Copying data over to device\n");
fflush(stdout);
gpuAssert( hipMemcpyToSymbol(HIP_SYMBOL(offsets), h_offsets, LGSAMP * sizeof(*h_offsets), 0, hipMemcpyHostToDevice) );
//cudaMemcpy( d_offsets, h_offsets, LGSAMP * sizeof(*d_offsets), cudaMemcpyHostToDevice );
gpuAssert( hipMemcpy( d_zerothTwiddles_re, h_zerothTwiddles_re, LGSAMP * sizeof(*d_zerothTwiddles_re), hipMemcpyHostToDevice ) );
gpuAssert( hipMemcpy( d_zerothTwiddles_im, h_zerothTwiddles_im, LGSAMP * sizeof(*d_zerothTwiddles_im), hipMemcpyHostToDevice ) );
gpuAssert( hipMemcpy( d_sig_data_re, h_sig_data[0], wave_num_pels * sizeof(*d_sig_data_re), hipMemcpyHostToDevice ) );
gpuAssert( hipMemcpy( d_sig_data_im, h_sig_data[1], wave_num_pels * sizeof(*d_sig_data_im), hipMemcpyHostToDevice ) );
gpuAssert( hipMemcpyToSymbol(HIP_SYMBOL(in_re), &d_sig_data_re, sizeof(float *)) );
gpuAssert( hipMemcpyToSymbol(HIP_SYMBOL(in_im), &d_sig_data_im, sizeof(float *)) );
// launch prep kernel
printf("Launching kernel to calc twiddles\n");
fflush(stdout);
calcTwiddles<<<1,11>>>(d_twiddles_re, d_twiddles_im, d_zerothTwiddles_re, d_zerothTwiddles_im);
hipDeviceSynchronize();
/* this copy to host then back to device may not be necessary */
// copy twiddles back to host
gpuAssert( hipMemcpy(h_twiddles_re, d_twiddles_re, TWIDDLES_LEN * sizeof(*h_twiddles_re), hipMemcpyDeviceToHost ) );
gpuAssert( hipMemcpy(h_twiddles_im, d_twiddles_im, TWIDDLES_LEN * sizeof(*h_twiddles_im), hipMemcpyDeviceToHost ) );
// copy twiddles back to device
gpuAssert( hipMemcpyToSymbol(HIP_SYMBOL(twiddles_re), h_twiddles_re, TWIDDLES_LEN * sizeof(*d_twiddles_re), 0, hipMemcpyHostToDevice) );
gpuAssert( hipMemcpyToSymbol(HIP_SYMBOL(twiddles_im), h_twiddles_im, TWIDDLES_LEN * sizeof(*d_twiddles_im), 0, hipMemcpyHostToDevice) );
// launch core kernel
int threadsPerBlock = HWSAMP;
int blocksPerGrid = wave_num_pels / (2 * threadsPerBlock);
printf("launching kernel with %d blocks and %d threads per block\n", blocksPerGrid, threadsPerBlock);
fflush(stdout);
int blockEachLaunch = 32;
int iter = 0;
for(; iter < blocksPerGrid/blockEachLaunch; iter++){
core<<<blockEachLaunch, threadsPerBlock, WSAMP * PREC>>>(d_out, timefreq_num_els, iter, blockEachLaunch);
}
if(blocksPerGrid % blockEachLaunch > 0) core<<<blocksPerGrid % blockEachLaunch, threadsPerBlock, WSAMP * PREC>>>(d_out, timefreq_num_els, iter, blockEachLaunch);
hipDeviceSynchronize();
/* this copy to host then back to device may not be necessary */
//// copy results back from device
//cudaMemcpy(h_timefreq_cmp_data, d_timefreq_cmp_data, timefreq_num_els * sizeof(*h_timefreq_cmp_data), cudaMemcpyDeviceToHost );
//
//// copy results back to device
//cudaMemcpy(d_timefreq_cmp_data, h_timefreq_data, timefreq_num_els * sizeof(*d_timefreq_cmp_data), cudaMemcpyHostToDevice );
// launch kernel to normalise the data
iter = 0;
for(; iter < blocksPerGrid/blockEachLaunch; iter++){
normaliseFinal<<<blockEachLaunch, threadsPerBlock>>>(d_out, timefreq_num_els, iter, blockEachLaunch);
}
if(blocksPerGrid % blockEachLaunch > 0) normaliseFinal<<<blocksPerGrid % blockEachLaunch, threadsPerBlock>>>(d_out, timefreq_num_els, iter, blockEachLaunch);
hipDeviceSynchronize();
// copy final results back to host
//cudaMemcpy(h_timefreq_cmp_data, d_timefreq_cmp_data, timefreq_num_els * sizeof(*h_timefreq_cmp_data), cudaMemcpyDeviceToHost );
gpuAssert( hipMemcpy(out, d_out, timefreq_num_els * sizeof(*out), hipMemcpyDeviceToHost ) );
gpuAssert( hipFree(d_out) );
// clean up device memory
gpuAssert( hipFree(d_sig_data_re) );
gpuAssert( hipFree(d_sig_data_im) );
gpuAssert( hipFree(d_zerothTwiddles_re) );
gpuAssert( hipFree(d_zerothTwiddles_im) );
gpuAssert( hipFree(d_twiddles_re) );
gpuAssert( hipFree(d_twiddles_im) );
/********************** /kernel stuff **********************/
//for(int i = 0; i < timefreq_num_els; i++) printf("%f ", out[i]);
//printf("Writing results to timefreq_done. int is %lu bytes.\n", sizeof(int));
writeBinFile(timefreq_cmp, out, timefreq_num_els);
free(out);
free(h_timefreq_ref_data);
free(h_timefreq_cmp_data);
free(h_wave_data);
}
// -gencode arch=compute_50,code=sm_50 | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4corePfiii
.globl _Z4corePfiii
.p2align 8
.type _Z4corePfiii,@function
_Z4corePfiii:
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x10
s_load_b32 s3, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s5
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s2, s2, s3
s_mov_b32 s3, exec_lo
v_add_nc_u32_e32 v1, s2, v0
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_8
v_bfrev_b32_e32 v2, v0
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, in_re@rel32@lo+4
s_addc_u32 s5, s5, in_re@rel32@hi+12
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, in_im@rel32@lo+4
s_addc_u32 s7, s7, in_im@rel32@hi+12
s_load_b64 s[4:5], s[4:5], 0x0
s_load_b64 s[6:7], s[6:7], 0x0
v_lshrrev_b32_e32 v2, 21, v2
v_or_b32_e32 v9, 0x400, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s2, v2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
flat_load_b32 v7, v[4:5]
flat_load_b32 v8, v[2:3]
v_bfrev_b32_e32 v2, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 21, v2
v_add_nc_u32_e32 v2, s2, v2
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_lshl_add_u32 v2, v0, 3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, twiddles_im@rel32@lo+4
s_addc_u32 s7, s7, twiddles_im@rel32@hi+12
s_waitcnt vmcnt(0) lgkmcnt(0)
ds_store_2addr_b32 v2, v7, v8 offset1:1
flat_load_b32 v5, v[5:6]
flat_load_b32 v3, v[3:4]
v_lshl_add_u32 v4, v9, 3, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
ds_store_2addr_b32 v4, v5, v3 offset1:1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_2:
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, offsets@rel32@lo+4
s_addc_u32 s5, s5, offsets@rel32@hi+12
s_add_u32 s4, s2, s4
s_addc_u32 s5, s3, s5
s_load_b32 s8, s[4:5], 0x0
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, twiddles_re@rel32@lo+4
s_addc_u32 s5, s5, twiddles_re@rel32@hi+12
s_waitcnt lgkmcnt(0)
v_and_b32_e32 v3, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s8, v3
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v5, vcc_lo, v3, s6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, s4
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_not_b32 s4, s8
global_load_b32 v7, v[5:6], off
global_load_b32 v8, v[3:4], off
v_and_b32_e32 v3, s4, v0
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 44
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v3, v0
v_add3_u32 v3, s8, 1, v5
v_lshl_add_u32 v10, v5, 3, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v9, v3, 3, 0
ds_load_2addr_b32 v[5:6], v10 offset1:1
ds_load_2addr_b32 v[3:4], v9 offset1:1
s_waitcnt vmcnt(1) lgkmcnt(0)
v_mul_f32_e32 v11, v4, v7
v_mul_f32_e32 v7, v3, v7
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, v3, v8, -v11
v_dual_fmac_f32 v7, v4, v8 :: v_dual_add_f32 v4, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v5, v6, v7
v_sub_f32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_2)
v_sub_f32_e32 v6, v5, v7
ds_store_2addr_b32 v10, v4, v5 offset1:1
ds_store_2addr_b32 v9, v3, v6 offset1:1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
ds_load_2addr_b32 v[2:3], v2 offset1:1
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v0, v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v0, v2, v2
v_mul_f32_e32 v2, 0x4f800000, v0
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v0, v2, vcc_lo
v_sqrt_f32_e32 v0, v5
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v2, -1, v0
v_add_nc_u32_e32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v4, -v2, v0, v5
v_fma_f32 v6, -v3, v0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v4
v_cndmask_b32_e64 v0, v0, v2, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_f32_e64 s0, 0, v6
v_ashrrev_i32_e32 v2, 31, v1
v_cndmask_b32_e64 v3, v0, v3, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, _ZL6maxFFT@rel32@lo+4
s_addc_u32 s1, s1, _ZL6maxFFT@rel32@hi+12
v_mul_f32_e32 v4, 0x37800000, v3
v_cndmask_b32_e32 v2, v3, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v1, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v5, 0x260
s_mov_b32 s2, 0
v_cndmask_b32_e32 v0, v2, v5, vcc_lo
v_mov_b32_e32 v2, 0
global_store_b32 v[3:4], v0, off
global_load_b32 v1, v2, s[0:1]
s_waitcnt vmcnt(0)
v_cmp_nge_f32_e32 vcc_lo, v1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b32 s0, s[0:1], 0x0
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, _ZL6maxFFT@rel32@lo+4
s_addc_u32 s5, s5, _ZL6maxFFT@rel32@hi+12
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s0
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, exec_lo, s0
s_or_b32 s2, s1, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_8
.LBB0_6:
s_or_b32 s0, s0, exec_lo
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_nle_f32_e32 v0, v1
s_cbranch_execz .LBB0_5
global_atomic_cmpswap_b32 v3, v2, v[0:1], s[4:5] glc
s_and_not1_b32 s0, s0, exec_lo
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v1, v3
v_mov_b32_e32 v1, v3
s_and_b32 s3, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s0, s0, s3
s_branch .LBB0_5
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4corePfiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4corePfiii, .Lfunc_end0-_Z4corePfiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14normaliseFinalPfiii
.globl _Z14normaliseFinalPfiii
.p2align 8
.type _Z14normaliseFinalPfiii,@function
_Z14normaliseFinalPfiii:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s4, s3
s_and_b32 s4, s5, 0xffff
s_add_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, _ZL6maxFFT@rel32@lo+4
s_addc_u32 s1, s1, _ZL6maxFFT@rel32@hi+12
s_load_b32 s0, s[0:1], 0x0
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_div_scale_f32 v3, null, s0, s0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
v_fmac_f32_e32 v4, v5, v4
v_div_scale_f32 v5, vcc_lo, v2, s0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v5, v4
v_fma_f32 v7, -v3, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v4
v_fma_f32 v3, -v3, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v3, v3, v4, v6
v_div_fixup_f32 v2, v3, s0, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14normaliseFinalPfiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z14normaliseFinalPfiii, .Lfunc_end1-_Z14normaliseFinalPfiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12calcTwiddlesPfS_S_S_
.globl _Z12calcTwiddlesPfS_S_S_
.p2align 8
.type _Z12calcTwiddlesPfS_S_S_,@function
_Z12calcTwiddlesPfS_S_S_:
v_lshlrev_b32_e32 v1, 2, v0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, offsets@rel32@lo+4
s_addc_u32 s3, s3, offsets@rel32@hi+12
global_load_b32 v4, v1, s[2:3]
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v1, 1, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_le_i32_e64 v4, v1
s_cbranch_execz .LBB2_3
s_load_b256 s[0:7], s[0:1], 0x0
v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v2, 2, v0
v_dual_mov_b32 v7, 1.0 :: v_dual_add_nc_u32 v6, 1, v4
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s4, s4, v2
v_add_co_ci_u32_e64 v1, null, s5, 0, s4
v_add_co_u32 v2, s4, s6, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, null, s7, 0, s4
s_mov_b32 s4, 0
s_mov_b32 s5, 0
.p2align 6
.LBB2_2:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v8, s5, v4
s_add_i32 s5, s5, 1
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v10, vcc_lo, s0, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s1, v9, vcc_lo
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s5, v6
global_store_b32 v[10:11], v7, off
global_store_b32 v[8:9], v5, off
global_load_b32 v8, v[2:3], off
global_load_b32 v9, v[0:1], off
s_or_b32 s4, vcc_lo, s4
s_waitcnt vmcnt(1)
v_mul_f32_e32 v10, v7, v8
v_mul_f32_e32 v8, v5, v8
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v10, v5, v9
v_fma_f32 v7, v7, v9, -v8
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v5, v10
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB2_2
.LBB2_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12calcTwiddlesPfS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z12calcTwiddlesPfS_S_S_, .Lfunc_end2-_Z12calcTwiddlesPfS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected offsets
.type offsets,@object
.section .bss,"aw",@nobits
.globl offsets
.p2align 4, 0x0
offsets:
.zero 44
.size offsets, 44
.protected twiddles_re
.type twiddles_re,@object
.globl twiddles_re
.p2align 4, 0x0
twiddles_re:
.zero 8188
.size twiddles_re, 8188
.protected twiddles_im
.type twiddles_im,@object
.globl twiddles_im
.p2align 4, 0x0
twiddles_im:
.zero 8188
.size twiddles_im, 8188
.protected in_re
.type in_re,@object
.globl in_re
.p2align 3, 0x0
in_re:
.quad 0
.size in_re, 8
.protected in_im
.type in_im,@object
.globl in_im
.p2align 3, 0x0
in_im:
.quad 0
.size in_im, 8
.type _ZL6maxFFT,@object
.local _ZL6maxFFT
.comm _ZL6maxFFT,4,2
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym offsets
.addrsig_sym twiddles_re
.addrsig_sym twiddles_im
.addrsig_sym in_re
.addrsig_sym in_im
.addrsig_sym _ZL6maxFFT
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4corePfiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4corePfiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14normaliseFinalPfiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14normaliseFinalPfiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12calcTwiddlesPfS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z12calcTwiddlesPfS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* vadd.cu:
*
*/
#include <stdio.h>
#include <sys/time.h>
#include <cuda_runtime.h>
enum {
NELEMS = 1024 * 1024
};
__global__ void vadd(const float *a, const float *b, float *c, int n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < n)
c[i] = a[i] + b[i];
}
int main()
{
size_t size = sizeof(float) * NELEMS;
/* Allocate vectors on host */
float *h_A = (float *)malloc(size);
float *h_B = (float *)malloc(size);
float *h_C = (float *)malloc(size);
if (h_A == NULL || h_B == NULL || h_C == NULL) {
fprintf(stderr, "Allocation error.\n");
exit(EXIT_FAILURE);
}
for (int i = 0; i < NELEMS; ++i) {
h_A[i] = rand() / (float)RAND_MAX;
h_B[i] = rand() / (float)RAND_MAX;
}
/* Allocate vectors on device */
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
if (cudaMalloc((void **)&d_A, size) != cudaSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
if (cudaMalloc((void **)&d_B, size) != cudaSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
if (cudaMalloc((void **)&d_C, size) != cudaSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
/* Copy the host vectors to device */
if (cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice) != cudaSuccess) {
fprintf(stderr, "Host to device copying failed\n");
exit(EXIT_FAILURE);
}
if (cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice) != cudaSuccess) {
fprintf(stderr, "Host to device copying failed\n");
exit(EXIT_FAILURE);
}
/* Launch the kernel */
int threadsPerBlock = 256;
int blocksPerGrid =(NELEMS + threadsPerBlock - 1) / threadsPerBlock;
vadd<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, NELEMS);
if (cudaGetLastError() != cudaSuccess) {
fprintf(stderr, "Failed to launch kernel!\n");
exit(EXIT_FAILURE);
}
/* Copy the device vectors to host */
if (cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost) != cudaSuccess) {
fprintf(stderr, "Device to host copying failed\n");
exit(EXIT_FAILURE);
}
for (int i = 0; i < NELEMS; ++i) {
if (fabs(h_A[i] + h_B[i] - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z4vaddPKfS0_Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* vadd.cu:
*
*/
#include <stdio.h>
#include <sys/time.h>
#include <cuda_runtime.h>
enum {
NELEMS = 1024 * 1024
};
__global__ void vadd(const float *a, const float *b, float *c, int n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < n)
c[i] = a[i] + b[i];
}
int main()
{
size_t size = sizeof(float) * NELEMS;
/* Allocate vectors on host */
float *h_A = (float *)malloc(size);
float *h_B = (float *)malloc(size);
float *h_C = (float *)malloc(size);
if (h_A == NULL || h_B == NULL || h_C == NULL) {
fprintf(stderr, "Allocation error.\n");
exit(EXIT_FAILURE);
}
for (int i = 0; i < NELEMS; ++i) {
h_A[i] = rand() / (float)RAND_MAX;
h_B[i] = rand() / (float)RAND_MAX;
}
/* Allocate vectors on device */
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
if (cudaMalloc((void **)&d_A, size) != cudaSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
if (cudaMalloc((void **)&d_B, size) != cudaSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
if (cudaMalloc((void **)&d_C, size) != cudaSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
/* Copy the host vectors to device */
if (cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice) != cudaSuccess) {
fprintf(stderr, "Host to device copying failed\n");
exit(EXIT_FAILURE);
}
if (cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice) != cudaSuccess) {
fprintf(stderr, "Host to device copying failed\n");
exit(EXIT_FAILURE);
}
/* Launch the kernel */
int threadsPerBlock = 256;
int blocksPerGrid =(NELEMS + threadsPerBlock - 1) / threadsPerBlock;
vadd<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, NELEMS);
if (cudaGetLastError() != cudaSuccess) {
fprintf(stderr, "Failed to launch kernel!\n");
exit(EXIT_FAILURE);
}
/* Copy the device vectors to host */
if (cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost) != cudaSuccess) {
fprintf(stderr, "Device to host copying failed\n");
exit(EXIT_FAILURE);
}
for (int i = 0; i < NELEMS; ++i) {
if (fabs(h_A[i] + h_B[i] - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
cudaDeviceReset();
return 0;
} | .file "tmpxft_001887d6_00000000-6_vadd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi
.type _Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi, @function
_Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4vaddPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi, .-_Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi
.globl _Z4vaddPKfS0_Pfi
.type _Z4vaddPKfS0_Pfi, @function
_Z4vaddPKfS0_Pfi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4vaddPKfS0_Pfi, .-_Z4vaddPKfS0_Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Allocation error.\n"
.LC2:
.string "Allocation error\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Host to device copying failed\n"
.section .rodata.str1.1
.LC4:
.string "Failed to launch kernel!\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "Device to host copying failed\n"
.align 8
.LC8:
.string "Result verification failed at element %d!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
testq %rbp, %rbp
sete %al
testq %rbx, %rbx
sete %dl
orb %dl, %al
jne .L27
testq %r12, %r12
je .L27
movl $0, %r13d
.L12:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, 0(%rbp,%r13)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, (%rbx,%r13)
addq $4, %r13
cmpq $4194304, %r13
jne .L12
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L33
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L34
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L35
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L36
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L37
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $4096, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L19:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L39
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L40
movl $0, %eax
movss .LC6(%rip), %xmm2
movsd .LC7(%rip), %xmm1
.L21:
movss 0(%rbp,%rax,4), %xmm0
addss (%rbx,%rax,4), %xmm0
subss (%r12,%rax,4), %xmm0
andps %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm1, %xmm0
ja .L41
addq $1, %rax
cmpq $1048576, %rax
jne .L21
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl $1048576, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi
jmp .L19
.L39:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z4vaddPKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z4vaddPKfS0_Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 805306368
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC6:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* vadd.cu:
*
*/
#include <stdio.h>
#include <sys/time.h>
#include <cuda_runtime.h>
enum {
NELEMS = 1024 * 1024
};
__global__ void vadd(const float *a, const float *b, float *c, int n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < n)
c[i] = a[i] + b[i];
}
int main()
{
size_t size = sizeof(float) * NELEMS;
/* Allocate vectors on host */
float *h_A = (float *)malloc(size);
float *h_B = (float *)malloc(size);
float *h_C = (float *)malloc(size);
if (h_A == NULL || h_B == NULL || h_C == NULL) {
fprintf(stderr, "Allocation error.\n");
exit(EXIT_FAILURE);
}
for (int i = 0; i < NELEMS; ++i) {
h_A[i] = rand() / (float)RAND_MAX;
h_B[i] = rand() / (float)RAND_MAX;
}
/* Allocate vectors on device */
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
if (cudaMalloc((void **)&d_A, size) != cudaSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
if (cudaMalloc((void **)&d_B, size) != cudaSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
if (cudaMalloc((void **)&d_C, size) != cudaSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
/* Copy the host vectors to device */
if (cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice) != cudaSuccess) {
fprintf(stderr, "Host to device copying failed\n");
exit(EXIT_FAILURE);
}
if (cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice) != cudaSuccess) {
fprintf(stderr, "Host to device copying failed\n");
exit(EXIT_FAILURE);
}
/* Launch the kernel */
int threadsPerBlock = 256;
int blocksPerGrid =(NELEMS + threadsPerBlock - 1) / threadsPerBlock;
vadd<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, NELEMS);
if (cudaGetLastError() != cudaSuccess) {
fprintf(stderr, "Failed to launch kernel!\n");
exit(EXIT_FAILURE);
}
/* Copy the device vectors to host */
if (cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost) != cudaSuccess) {
fprintf(stderr, "Device to host copying failed\n");
exit(EXIT_FAILURE);
}
for (int i = 0; i < NELEMS; ++i) {
if (fabs(h_A[i] + h_B[i] - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
cudaDeviceReset();
return 0;
} | /*
* vadd.cu:
*
*/
#include <stdio.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
enum {
NELEMS = 1024 * 1024
};
__global__ void vadd(const float *a, const float *b, float *c, int n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < n)
c[i] = a[i] + b[i];
}
int main()
{
size_t size = sizeof(float) * NELEMS;
/* Allocate vectors on host */
float *h_A = (float *)malloc(size);
float *h_B = (float *)malloc(size);
float *h_C = (float *)malloc(size);
if (h_A == NULL || h_B == NULL || h_C == NULL) {
fprintf(stderr, "Allocation error.\n");
exit(EXIT_FAILURE);
}
for (int i = 0; i < NELEMS; ++i) {
h_A[i] = rand() / (float)RAND_MAX;
h_B[i] = rand() / (float)RAND_MAX;
}
/* Allocate vectors on device */
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
if (hipMalloc((void **)&d_A, size) != hipSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
if (hipMalloc((void **)&d_B, size) != hipSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
if (hipMalloc((void **)&d_C, size) != hipSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
/* Copy the host vectors to device */
if (hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice) != hipSuccess) {
fprintf(stderr, "Host to device copying failed\n");
exit(EXIT_FAILURE);
}
if (hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice) != hipSuccess) {
fprintf(stderr, "Host to device copying failed\n");
exit(EXIT_FAILURE);
}
/* Launch the kernel */
int threadsPerBlock = 256;
int blocksPerGrid =(NELEMS + threadsPerBlock - 1) / threadsPerBlock;
vadd<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, NELEMS);
if (hipGetLastError() != hipSuccess) {
fprintf(stderr, "Failed to launch kernel!\n");
exit(EXIT_FAILURE);
}
/* Copy the device vectors to host */
if (hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost) != hipSuccess) {
fprintf(stderr, "Device to host copying failed\n");
exit(EXIT_FAILURE);
}
for (int i = 0; i < NELEMS; ++i) {
if (fabs(h_A[i] + h_B[i] - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* vadd.cu:
*
*/
#include <stdio.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
enum {
NELEMS = 1024 * 1024
};
__global__ void vadd(const float *a, const float *b, float *c, int n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < n)
c[i] = a[i] + b[i];
}
int main()
{
size_t size = sizeof(float) * NELEMS;
/* Allocate vectors on host */
float *h_A = (float *)malloc(size);
float *h_B = (float *)malloc(size);
float *h_C = (float *)malloc(size);
if (h_A == NULL || h_B == NULL || h_C == NULL) {
fprintf(stderr, "Allocation error.\n");
exit(EXIT_FAILURE);
}
for (int i = 0; i < NELEMS; ++i) {
h_A[i] = rand() / (float)RAND_MAX;
h_B[i] = rand() / (float)RAND_MAX;
}
/* Allocate vectors on device */
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
if (hipMalloc((void **)&d_A, size) != hipSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
if (hipMalloc((void **)&d_B, size) != hipSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
if (hipMalloc((void **)&d_C, size) != hipSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
/* Copy the host vectors to device */
if (hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice) != hipSuccess) {
fprintf(stderr, "Host to device copying failed\n");
exit(EXIT_FAILURE);
}
if (hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice) != hipSuccess) {
fprintf(stderr, "Host to device copying failed\n");
exit(EXIT_FAILURE);
}
/* Launch the kernel */
int threadsPerBlock = 256;
int blocksPerGrid =(NELEMS + threadsPerBlock - 1) / threadsPerBlock;
vadd<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, NELEMS);
if (hipGetLastError() != hipSuccess) {
fprintf(stderr, "Failed to launch kernel!\n");
exit(EXIT_FAILURE);
}
/* Copy the device vectors to host */
if (hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost) != hipSuccess) {
fprintf(stderr, "Device to host copying failed\n");
exit(EXIT_FAILURE);
}
for (int i = 0; i < NELEMS; ++i) {
if (fabs(h_A[i] + h_B[i] - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4vaddPKfS0_Pfi
.globl _Z4vaddPKfS0_Pfi
.p2align 8
.type _Z4vaddPKfS0_Pfi,@function
_Z4vaddPKfS0_Pfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4vaddPKfS0_Pfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4vaddPKfS0_Pfi, .Lfunc_end0-_Z4vaddPKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4vaddPKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4vaddPKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* vadd.cu:
*
*/
#include <stdio.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
enum {
NELEMS = 1024 * 1024
};
__global__ void vadd(const float *a, const float *b, float *c, int n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < n)
c[i] = a[i] + b[i];
}
int main()
{
size_t size = sizeof(float) * NELEMS;
/* Allocate vectors on host */
float *h_A = (float *)malloc(size);
float *h_B = (float *)malloc(size);
float *h_C = (float *)malloc(size);
if (h_A == NULL || h_B == NULL || h_C == NULL) {
fprintf(stderr, "Allocation error.\n");
exit(EXIT_FAILURE);
}
for (int i = 0; i < NELEMS; ++i) {
h_A[i] = rand() / (float)RAND_MAX;
h_B[i] = rand() / (float)RAND_MAX;
}
/* Allocate vectors on device */
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
if (hipMalloc((void **)&d_A, size) != hipSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
if (hipMalloc((void **)&d_B, size) != hipSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
if (hipMalloc((void **)&d_C, size) != hipSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
/* Copy the host vectors to device */
if (hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice) != hipSuccess) {
fprintf(stderr, "Host to device copying failed\n");
exit(EXIT_FAILURE);
}
if (hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice) != hipSuccess) {
fprintf(stderr, "Host to device copying failed\n");
exit(EXIT_FAILURE);
}
/* Launch the kernel */
int threadsPerBlock = 256;
int blocksPerGrid =(NELEMS + threadsPerBlock - 1) / threadsPerBlock;
vadd<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, NELEMS);
if (hipGetLastError() != hipSuccess) {
fprintf(stderr, "Failed to launch kernel!\n");
exit(EXIT_FAILURE);
}
/* Copy the device vectors to host */
if (hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost) != hipSuccess) {
fprintf(stderr, "Device to host copying failed\n");
exit(EXIT_FAILURE);
}
for (int i = 0; i < NELEMS; ++i) {
if (fabs(h_A[i] + h_B[i] - h_C[i]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
hipDeviceReset();
return 0;
} | .text
.file "vadd.hip"
.globl _Z19__device_stub__vaddPKfS0_Pfi # -- Begin function _Z19__device_stub__vaddPKfS0_Pfi
.p2align 4, 0x90
.type _Z19__device_stub__vaddPKfS0_Pfi,@function
_Z19__device_stub__vaddPKfS0_Pfi: # @_Z19__device_stub__vaddPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4vaddPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__vaddPKfS0_Pfi, .Lfunc_end0-_Z19__device_stub__vaddPKfS0_Pfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
testq %rbx, %rbx
je .LBB1_25
# %bb.1:
testq %r14, %r14
je .LBB1_25
# %bb.2:
movq %rax, %r15
testq %rax, %rax
je .LBB1_25
# %bb.3: # %.preheader55.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_4: # %.preheader55
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r12,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $1048576, %r12 # imm = 0x100000
jne .LBB1_4
# %bb.5:
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movq $0, 8(%rsp)
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7:
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.8:
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.9:
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_10
# %bb.13:
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_10
# %bb.14:
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_16
# %bb.15:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1048576, 36(%rsp) # imm = 0x100000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z4vaddPKfS0_Pfi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_16:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_17
# %bb.18:
movq 8(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_22
# %bb.19: # %.preheader.preheader
xorl %edx, %edx
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI1_2(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB1_20: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss (%r14,%rdx,4), %xmm2
subss (%r15,%rdx,4), %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm1, %xmm2
ja .LBB1_21
# %bb.23: # in Loop: Header=BB1_20 Depth=1
incq %rdx
cmpq $1048576, %rdx # imm = 0x100000
jne .LBB1_20
# %bb.24:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
callq hipDeviceReset
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_21:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rdi
movl $.L.str.5, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_6:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $17, %esi
jmp .LBB1_12
.LBB1_10:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
jmp .LBB1_11
.LBB1_25:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $18, %esi
jmp .LBB1_12
.LBB1_17:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $25, %esi
jmp .LBB1_12
.LBB1_22:
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
.LBB1_11:
movl $30, %esi
.LBB1_12:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4vaddPKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4vaddPKfS0_Pfi,@object # @_Z4vaddPKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z4vaddPKfS0_Pfi
.p2align 3, 0x0
_Z4vaddPKfS0_Pfi:
.quad _Z19__device_stub__vaddPKfS0_Pfi
.size _Z4vaddPKfS0_Pfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Allocation error.\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Allocation error\n"
.size .L.str.1, 18
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Host to device copying failed\n"
.size .L.str.2, 31
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to launch kernel!\n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Device to host copying failed\n"
.size .L.str.4, 31
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Result verification failed at element %d!\n"
.size .L.str.5, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4vaddPKfS0_Pfi"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__vaddPKfS0_Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4vaddPKfS0_Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4vaddPKfS0_Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4vaddPKfS0_Pfi
.globl _Z4vaddPKfS0_Pfi
.p2align 8
.type _Z4vaddPKfS0_Pfi,@function
_Z4vaddPKfS0_Pfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4vaddPKfS0_Pfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4vaddPKfS0_Pfi, .Lfunc_end0-_Z4vaddPKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4vaddPKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4vaddPKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001887d6_00000000-6_vadd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi
.type _Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi, @function
_Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4vaddPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi, .-_Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi
.globl _Z4vaddPKfS0_Pfi
.type _Z4vaddPKfS0_Pfi, @function
_Z4vaddPKfS0_Pfi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4vaddPKfS0_Pfi, .-_Z4vaddPKfS0_Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Allocation error.\n"
.LC2:
.string "Allocation error\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Host to device copying failed\n"
.section .rodata.str1.1
.LC4:
.string "Failed to launch kernel!\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "Device to host copying failed\n"
.align 8
.LC8:
.string "Result verification failed at element %d!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
testq %rbp, %rbp
sete %al
testq %rbx, %rbx
sete %dl
orb %dl, %al
jne .L27
testq %r12, %r12
je .L27
movl $0, %r13d
.L12:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, 0(%rbp,%r13)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, (%rbx,%r13)
addq $4, %r13
cmpq $4194304, %r13
jne .L12
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L33
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L34
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L35
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L36
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L37
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $4096, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L19:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L39
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L40
movl $0, %eax
movss .LC6(%rip), %xmm2
movsd .LC7(%rip), %xmm1
.L21:
movss 0(%rbp,%rax,4), %xmm0
addss (%rbx,%rax,4), %xmm0
subss (%r12,%rax,4), %xmm0
andps %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm1, %xmm0
ja .L41
addq $1, %rax
cmpq $1048576, %rax
jne .L21
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl $1048576, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z4vaddPKfS0_PfiPKfS0_Pfi
jmp .L19
.L39:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z4vaddPKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z4vaddPKfS0_Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 805306368
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC6:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vadd.hip"
.globl _Z19__device_stub__vaddPKfS0_Pfi # -- Begin function _Z19__device_stub__vaddPKfS0_Pfi
.p2align 4, 0x90
.type _Z19__device_stub__vaddPKfS0_Pfi,@function
_Z19__device_stub__vaddPKfS0_Pfi: # @_Z19__device_stub__vaddPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4vaddPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__vaddPKfS0_Pfi, .Lfunc_end0-_Z19__device_stub__vaddPKfS0_Pfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
testq %rbx, %rbx
je .LBB1_25
# %bb.1:
testq %r14, %r14
je .LBB1_25
# %bb.2:
movq %rax, %r15
testq %rax, %rax
je .LBB1_25
# %bb.3: # %.preheader55.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_4: # %.preheader55
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r12,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $1048576, %r12 # imm = 0x100000
jne .LBB1_4
# %bb.5:
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movq $0, 8(%rsp)
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7:
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.8:
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.9:
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_10
# %bb.13:
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_10
# %bb.14:
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_16
# %bb.15:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1048576, 36(%rsp) # imm = 0x100000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z4vaddPKfS0_Pfi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_16:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_17
# %bb.18:
movq 8(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_22
# %bb.19: # %.preheader.preheader
xorl %edx, %edx
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI1_2(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB1_20: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss (%r14,%rdx,4), %xmm2
subss (%r15,%rdx,4), %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm1, %xmm2
ja .LBB1_21
# %bb.23: # in Loop: Header=BB1_20 Depth=1
incq %rdx
cmpq $1048576, %rdx # imm = 0x100000
jne .LBB1_20
# %bb.24:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
callq hipDeviceReset
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_21:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rdi
movl $.L.str.5, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_6:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $17, %esi
jmp .LBB1_12
.LBB1_10:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
jmp .LBB1_11
.LBB1_25:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $18, %esi
jmp .LBB1_12
.LBB1_17:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $25, %esi
jmp .LBB1_12
.LBB1_22:
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
.LBB1_11:
movl $30, %esi
.LBB1_12:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4vaddPKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4vaddPKfS0_Pfi,@object # @_Z4vaddPKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z4vaddPKfS0_Pfi
.p2align 3, 0x0
_Z4vaddPKfS0_Pfi:
.quad _Z19__device_stub__vaddPKfS0_Pfi
.size _Z4vaddPKfS0_Pfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Allocation error.\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Allocation error\n"
.size .L.str.1, 18
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Host to device copying failed\n"
.size .L.str.2, 31
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to launch kernel!\n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Device to host copying failed\n"
.size .L.str.4, 31
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Result verification failed at element %d!\n"
.size .L.str.5, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4vaddPKfS0_Pfi"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__vaddPKfS0_Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4vaddPKfS0_Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void computePositionParallel(float *agentsX, float *agentsY, float *destX, float *destY, float *destR, int n, int *reached) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride) {
// if there is no destination to go to
if (destX[i] == -1 || destY[i] == -1) {
continue;
}
// compute and update next position
double diffX = destX[i] - agentsX[i];
double diffY = destY[i] - agentsY[i];
double length = sqrtf(diffX * diffX + diffY * diffY);
agentsX[i] = (float)llrintf(agentsX[i] + diffX / length);
agentsY[i] = (float)llrintf(agentsY[i] + diffY / length);
// check if next position is inside the destination radius
diffX = destX[i] - agentsX[i];
diffY = destY[i] - agentsY[i];
length = sqrtf(diffX * diffX + diffY * diffY);
if (length < destR[i]) {
reached[i] = 1;
}
}
} | .file "tmpxft_00018d9b_00000000-6_computePositionParallel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z23computePositionParallelPfS_S_S_S_iPiPfS_S_S_S_iPi
.type _Z54__device_stub__Z23computePositionParallelPfS_S_S_S_iPiPfS_S_S_S_iPi, @function
_Z54__device_stub__Z23computePositionParallelPfS_S_S_S_iPiPfS_S_S_S_iPi:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movl %r9d, 20(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z23computePositionParallelPfS_S_S_S_iPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z54__device_stub__Z23computePositionParallelPfS_S_S_S_iPiPfS_S_S_S_iPi, .-_Z54__device_stub__Z23computePositionParallelPfS_S_S_S_iPiPfS_S_S_S_iPi
.globl _Z23computePositionParallelPfS_S_S_S_iPi
.type _Z23computePositionParallelPfS_S_S_S_iPi, @function
_Z23computePositionParallelPfS_S_S_S_iPi:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z54__device_stub__Z23computePositionParallelPfS_S_S_S_iPiPfS_S_S_S_iPi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23computePositionParallelPfS_S_S_S_iPi, .-_Z23computePositionParallelPfS_S_S_S_iPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23computePositionParallelPfS_S_S_S_iPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23computePositionParallelPfS_S_S_S_iPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void computePositionParallel(float *agentsX, float *agentsY, float *destX, float *destY, float *destR, int n, int *reached) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride) {
// if there is no destination to go to
if (destX[i] == -1 || destY[i] == -1) {
continue;
}
// compute and update next position
double diffX = destX[i] - agentsX[i];
double diffY = destY[i] - agentsY[i];
double length = sqrtf(diffX * diffX + diffY * diffY);
agentsX[i] = (float)llrintf(agentsX[i] + diffX / length);
agentsY[i] = (float)llrintf(agentsY[i] + diffY / length);
// check if next position is inside the destination radius
diffX = destX[i] - agentsX[i];
diffY = destY[i] - agentsY[i];
length = sqrtf(diffX * diffX + diffY * diffY);
if (length < destR[i]) {
reached[i] = 1;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void computePositionParallel(float *agentsX, float *agentsY, float *destX, float *destY, float *destR, int n, int *reached) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride) {
// if there is no destination to go to
if (destX[i] == -1 || destY[i] == -1) {
continue;
}
// compute and update next position
double diffX = destX[i] - agentsX[i];
double diffY = destY[i] - agentsY[i];
double length = sqrtf(diffX * diffX + diffY * diffY);
agentsX[i] = (float)llrintf(agentsX[i] + diffX / length);
agentsY[i] = (float)llrintf(agentsY[i] + diffY / length);
// check if next position is inside the destination radius
diffX = destX[i] - agentsX[i];
diffY = destY[i] - agentsY[i];
length = sqrtf(diffX * diffX + diffY * diffY);
if (length < destR[i]) {
reached[i] = 1;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void computePositionParallel(float *agentsX, float *agentsY, float *destX, float *destY, float *destR, int n, int *reached) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride) {
// if there is no destination to go to
if (destX[i] == -1 || destY[i] == -1) {
continue;
}
// compute and update next position
double diffX = destX[i] - agentsX[i];
double diffY = destY[i] - agentsY[i];
double length = sqrtf(diffX * diffX + diffY * diffY);
agentsX[i] = (float)llrintf(agentsX[i] + diffX / length);
agentsY[i] = (float)llrintf(agentsY[i] + diffY / length);
// check if next position is inside the destination radius
diffX = destX[i] - agentsX[i];
diffY = destY[i] - agentsY[i];
length = sqrtf(diffX * diffX + diffY * diffY);
if (length < destR[i]) {
reached[i] = 1;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23computePositionParallelPfS_S_S_S_iPi
.globl _Z23computePositionParallelPfS_S_S_S_iPi
.p2align 8
.type _Z23computePositionParallelPfS_S_S_S_iPi,@function
_Z23computePositionParallelPfS_S_S_S_iPi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b32 s18, s[0:1], 0x28
s_add_u32 s2, s0, 56
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s14, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s14, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s18, v1
s_cbranch_execz .LBB0_7
s_load_b32 s15, s[2:3], 0x0
s_clause 0x2
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b64 s[12:13], s[0:1], 0x30
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s14, s15, s14
s_ashr_i32 s15, s14, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[16:17], s[14:15], 2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s15
v_add_nc_u32_e32 v1, s14, v1
v_add_co_u32 v2, s0, v2, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s0, s17, v3, s0
v_cmp_le_i32_e32 vcc_lo, s18, v1
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_7
.LBB0_3:
v_add_co_u32 v4, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
s_mov_b32 s15, exec_lo
global_load_b32 v8, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_neq_f32_e32 -1.0, v8
s_cbranch_execz .LBB0_2
v_add_co_u32 v6, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v3, vcc_lo
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e32 vcc_lo, -1.0, v9
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
v_add_co_u32 v10, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v12, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v3, vcc_lo
global_load_b32 v14, v[10:11], off
global_load_b32 v26, v[12:13], off
s_waitcnt vmcnt(1)
v_sub_f32_e32 v9, v9, v14
s_waitcnt vmcnt(0)
v_sub_f32_e32 v8, v8, v26
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_f32_e32 v[14:15], v9
v_cvt_f64_f32_e32 v[8:9], v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[16:17], v[14:15], v[14:15]
v_fma_f64 v[16:17], v[8:9], v[8:9], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v16, v[16:17]
v_mul_f32_e32 v17, 0x4f800000, v16
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v16, v16, v17, vcc_lo
v_sqrt_f32_e32 v17, v16
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v18, -1, v17
v_add_nc_u32_e32 v19, 1, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v20, -v18, v17, v16
v_fma_f32 v21, -v19, v17, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v20
v_cndmask_b32_e64 v17, v17, v18, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v21
v_cndmask_b32_e64 v17, v17, v19, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v18, 0x37800000, v17
v_cndmask_b32_e32 v17, v17, v18, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v16, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v16, v17, v16, vcc_lo
v_cvt_f64_f32_e32 v[16:17], v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[18:19], null, v[16:17], v[16:17], v[8:9]
v_div_scale_f64 v[24:25], vcc_lo, v[8:9], v[16:17], v[8:9]
v_rcp_f64_e32 v[20:21], v[18:19]
s_waitcnt_depctr 0xfff
v_fma_f64 v[22:23], -v[18:19], v[20:21], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
v_fma_f64 v[22:23], -v[18:19], v[20:21], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
v_mul_f64 v[22:23], v[24:25], v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[18:19], -v[18:19], v[22:23], v[24:25]
v_div_fmas_f64 v[18:19], v[18:19], v[20:21], v[22:23]
v_cvt_f64_f32_e32 v[20:21], v26
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[8:9], v[18:19], v[16:17], v[8:9]
v_add_f64 v[8:9], v[8:9], v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v8, v[8:9]
v_rndne_f32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e64 v9, 0x2f800000, |v8|
v_ashrrev_i32_e32 v19, 31, v8
v_floor_f32_e32 v9, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v18, v9, 0xcf800000, |v8|
v_cvt_u32_f32_e32 v9, v9
v_cvt_u32_f32_e32 v8, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v9, v9, v19
v_xor_b32_e32 v8, v8, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_co_u32 v8, vcc_lo, v8, v19
v_sub_co_ci_u32_e32 v9, vcc_lo, v9, v19, vcc_lo
v_div_scale_f64 v[22:23], vcc_lo, v[14:15], v[16:17], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v18, v8, v9
v_cls_i32_e32 v19, v9
v_ashrrev_i32_e32 v18, 31, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v19, -1, v19
v_add_nc_u32_e32 v18, 32, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_min_u32_e32 v20, v19, v18
v_div_scale_f64 v[18:19], null, v[16:17], v[16:17], v[14:15]
v_lshlrev_b64 v[8:9], v20, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v8, 1, v8
v_or_b32_e32 v8, v9, v8
v_sub_nc_u32_e32 v9, 32, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v8, v8
v_ldexp_f32 v8, v8, v9
global_store_b32 v[12:13], v8, off
global_load_b32 v24, v[10:11], off
v_rcp_f64_e32 v[8:9], v[18:19]
s_waitcnt_depctr 0xfff
v_fma_f64 v[20:21], -v[18:19], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[20:21], v[8:9]
v_fma_f64 v[20:21], -v[18:19], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[20:21], v[8:9]
v_mul_f64 v[20:21], v[22:23], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[18:19], -v[18:19], v[20:21], v[22:23]
v_div_fmas_f64 v[8:9], v[18:19], v[8:9], v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[8:9], v[8:9], v[16:17], v[14:15]
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[14:15], v24
v_add_f64 v[8:9], v[8:9], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v8, v[8:9]
v_rndne_f32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e64 v9, 0x2f800000, |v8|
v_ashrrev_i32_e32 v15, 31, v8
v_floor_f32_e32 v9, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v14, v9, 0xcf800000, |v8|
v_cvt_u32_f32_e32 v9, v9
v_cvt_u32_f32_e32 v8, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v9, v9, v15
v_xor_b32_e32 v8, v8, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_co_u32 v8, vcc_lo, v8, v15
v_sub_co_ci_u32_e32 v9, vcc_lo, v9, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v14, v8, v9
v_cls_i32_e32 v15, v9
v_ashrrev_i32_e32 v14, 31, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v15, -1, v15
v_add_nc_u32_e32 v14, 32, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v14, v15, v14
v_lshlrev_b64 v[8:9], v14, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v8, 1, v8
v_or_b32_e32 v8, v9, v8
v_sub_nc_u32_e32 v9, 32, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v8, v8
v_ldexp_f32 v8, v8, v9
global_store_b32 v[10:11], v8, off
global_load_b32 v6, v[6:7], off
global_load_b32 v7, v[4:5], off
global_load_b32 v9, v[12:13], off
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
global_load_b32 v10, v[4:5], off
s_waitcnt vmcnt(3)
v_sub_f32_e32 v4, v6, v8
s_waitcnt vmcnt(1)
v_sub_f32_e32 v6, v7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_f32_e32 v[4:5], v4
v_cvt_f64_f32_e32 v[6:7], v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[4:5], v[4:5], v[4:5]
v_fma_f64 v[4:5], v[6:7], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v4, v[4:5]
v_mul_f32_e32 v5, 0x4f800000, v4
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_sqrt_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v6, -1, v5
v_add_nc_u32_e32 v7, 1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v6, v5, v4
v_fma_f32 v9, -v7, v5, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v8
v_cndmask_b32_e64 v5, v5, v6, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v9
v_cndmask_b32_e64 v5, v5, v7, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, 0x37800000, v5
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v4, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v5, v4, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, v4, v10
s_delay_alu instid0(VALU_DEP_3)
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
v_add_co_u32 v4, vcc_lo, s12, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s13, v3, vcc_lo
global_store_b32 v[4:5], v0, off
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23computePositionParallelPfS_S_S_S_iPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 27
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23computePositionParallelPfS_S_S_S_iPi, .Lfunc_end0-_Z23computePositionParallelPfS_S_S_S_iPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23computePositionParallelPfS_S_S_S_iPi
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z23computePositionParallelPfS_S_S_S_iPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 27
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void computePositionParallel(float *agentsX, float *agentsY, float *destX, float *destY, float *destR, int n, int *reached) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride) {
// if there is no destination to go to
if (destX[i] == -1 || destY[i] == -1) {
continue;
}
// compute and update next position
double diffX = destX[i] - agentsX[i];
double diffY = destY[i] - agentsY[i];
double length = sqrtf(diffX * diffX + diffY * diffY);
agentsX[i] = (float)llrintf(agentsX[i] + diffX / length);
agentsY[i] = (float)llrintf(agentsY[i] + diffY / length);
// check if next position is inside the destination radius
diffX = destX[i] - agentsX[i];
diffY = destY[i] - agentsY[i];
length = sqrtf(diffX * diffX + diffY * diffY);
if (length < destR[i]) {
reached[i] = 1;
}
}
} | .text
.file "computePositionParallel.hip"
.globl _Z38__device_stub__computePositionParallelPfS_S_S_S_iPi # -- Begin function _Z38__device_stub__computePositionParallelPfS_S_S_S_iPi
.p2align 4, 0x90
.type _Z38__device_stub__computePositionParallelPfS_S_S_S_iPi,@function
_Z38__device_stub__computePositionParallelPfS_S_S_S_iPi: # @_Z38__device_stub__computePositionParallelPfS_S_S_S_iPi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23computePositionParallelPfS_S_S_S_iPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z38__device_stub__computePositionParallelPfS_S_S_S_iPi, .Lfunc_end0-_Z38__device_stub__computePositionParallelPfS_S_S_S_iPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23computePositionParallelPfS_S_S_S_iPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23computePositionParallelPfS_S_S_S_iPi,@object # @_Z23computePositionParallelPfS_S_S_S_iPi
.section .rodata,"a",@progbits
.globl _Z23computePositionParallelPfS_S_S_S_iPi
.p2align 3, 0x0
_Z23computePositionParallelPfS_S_S_S_iPi:
.quad _Z38__device_stub__computePositionParallelPfS_S_S_S_iPi
.size _Z23computePositionParallelPfS_S_S_S_iPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23computePositionParallelPfS_S_S_S_iPi"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__computePositionParallelPfS_S_S_S_iPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23computePositionParallelPfS_S_S_S_iPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00018d9b_00000000-6_computePositionParallel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z23computePositionParallelPfS_S_S_S_iPiPfS_S_S_S_iPi
.type _Z54__device_stub__Z23computePositionParallelPfS_S_S_S_iPiPfS_S_S_S_iPi, @function
_Z54__device_stub__Z23computePositionParallelPfS_S_S_S_iPiPfS_S_S_S_iPi:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movl %r9d, 20(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z23computePositionParallelPfS_S_S_S_iPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z54__device_stub__Z23computePositionParallelPfS_S_S_S_iPiPfS_S_S_S_iPi, .-_Z54__device_stub__Z23computePositionParallelPfS_S_S_S_iPiPfS_S_S_S_iPi
.globl _Z23computePositionParallelPfS_S_S_S_iPi
.type _Z23computePositionParallelPfS_S_S_S_iPi, @function
_Z23computePositionParallelPfS_S_S_S_iPi:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z54__device_stub__Z23computePositionParallelPfS_S_S_S_iPiPfS_S_S_S_iPi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23computePositionParallelPfS_S_S_S_iPi, .-_Z23computePositionParallelPfS_S_S_S_iPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23computePositionParallelPfS_S_S_S_iPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23computePositionParallelPfS_S_S_S_iPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "computePositionParallel.hip"
.globl _Z38__device_stub__computePositionParallelPfS_S_S_S_iPi # -- Begin function _Z38__device_stub__computePositionParallelPfS_S_S_S_iPi
.p2align 4, 0x90
.type _Z38__device_stub__computePositionParallelPfS_S_S_S_iPi,@function
_Z38__device_stub__computePositionParallelPfS_S_S_S_iPi: # @_Z38__device_stub__computePositionParallelPfS_S_S_S_iPi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23computePositionParallelPfS_S_S_S_iPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z38__device_stub__computePositionParallelPfS_S_S_S_iPi, .Lfunc_end0-_Z38__device_stub__computePositionParallelPfS_S_S_S_iPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23computePositionParallelPfS_S_S_S_iPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23computePositionParallelPfS_S_S_S_iPi,@object # @_Z23computePositionParallelPfS_S_S_S_iPi
.section .rodata,"a",@progbits
.globl _Z23computePositionParallelPfS_S_S_S_iPi
.p2align 3, 0x0
_Z23computePositionParallelPfS_S_S_S_iPi:
.quad _Z38__device_stub__computePositionParallelPfS_S_S_S_iPi
.size _Z23computePositionParallelPfS_S_S_S_iPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23computePositionParallelPfS_S_S_S_iPi"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__computePositionParallelPfS_S_S_S_iPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23computePositionParallelPfS_S_S_S_iPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cstdio>
#include <ctime>
#include <math.h>
//CUDA kernel function to add the elements of two arrays
__global__
void matvec(float *a, float *x, float *y, int n)
{
//Set index per block and sum variable
int row = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.0f;
//Perform the matrix-vector multiplication
for(unsigned int i = 0; i < n; i++)
{
if (row < n)
{
sum += x[i]*a[row*n+i];
}
}
//Synchronize the various threads working
__syncthreads();
//Put the results in the output vector
if(row < n)
{
y[row] = sum;
__syncthreads();
}
}
int main(void)
{
//Initializae the clock timer
clock_t start = clock();
//Set matrix and vector dimensions
int N = 10000;
//Allocate unified memory -- accessible from cpu or gpu
float *x, *y, *a;
cudaMallocManaged(&x, N*sizeof(float));
cudaMallocManaged(&y, N*sizeof(float));
cudaMallocManaged(&a, N*N*sizeof(float));
// initialize x and y arrays on the host
for (unsigned int i = 0; i < N*N; ++i)
a[i] = 0.0;
for (unsigned int i = 0; i < N; i++) {
a[i*N+i] = 4.0;
if (i > 0) a[i*N+i-1] = -1.0;
if (i < N-1) a[i*N+i+1] = -1.0;
x[i] = 1.0;
y[i] = 0.0;
}
//Set the block size and run the kernel
int blockSize = 1024;
int numBlocks = (N + blockSize - 1) / blockSize;
matvec<<<numBlocks, blockSize>>>(a, x, y, N);
//Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
//Finish the timer
double el = double(clock() - start) / CLOCKS_PER_SEC;
//Print the results
printf("y[0]=%8.4e and y[1]=%8.4e\n", y[0], y[1]);
printf("Number of elements in array %8.0f\n", float(N));
printf("Elapsed time: %8.8f seconds\n", el);
// Free memory
cudaFree(x);
cudaFree(y);
cudaFree(a);
return 0;
} | code for sm_80
Function : _Z6matvecPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f05270 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fd000078e0203 */
/*0070*/ @!P0 BRA 0x4c0 ; /* 0x0000044000008947 */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff037624 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc600078e00ff */
/*00a0*/ IADD3 R0, R3, -0x1, RZ ; /* 0xffffffff03007810 */
/* 0x000fc80007ffe0ff */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*00c0*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fd60000000f00 */
/*00d0*/ @!P0 BRA 0x360 ; /* 0x0000028000008947 */
/* 0x000fea0003800000 */
/*00e0*/ LOP3.LUT R10, R3, 0x3, RZ, 0xc0, !PT ; /* 0x00000003030a7812 */
/* 0x000fe200078ec0ff */
/*00f0*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0100*/ ISETP.GE.AND P0, PT, R4.reuse, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x040fe20003f06270 */
/*0110*/ IMAD R6, R4, R3.reuse, 0x3 ; /* 0x0000000304067424 */
/* 0x080fe200078e0203 */
/*0120*/ IADD3 R10, R10, -c[0x0][0x178], RZ ; /* 0x80005e000a0a7a10 */
/* 0x000fe20007ffe0ff */
/*0130*/ IMAD R8, R4, R3, 0x1 ; /* 0x0000000104087424 */
/* 0x000fe400078e0203 */
/*0140*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*0150*/ MOV R11, 0x4 ; /* 0x00000004000b7802 */
/* 0x000fe20000000f00 */
/*0160*/ BSSY B0, 0x240 ; /* 0x000000d000007945 */
/* 0x000fe80003800000 */
/*0170*/ IMAD.WIDE.U32 R2, R5, R11, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x000fe200078e000b */
/*0180*/ @P0 BRA 0x230 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0190*/ IMAD R12, R4, c[0x0][0x178], R5.reuse ; /* 0x00005e00040c7a24 */
/* 0x100fe200078e0205 */
/*01a0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IMAD.IADD R14, R8, 0x1, R5 ; /* 0x00000001080e7824 */
/* 0x000fc400078e0205 */
/*01c0*/ IMAD.WIDE.U32 R12, R12, R11.reuse, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x080fe200078e000b */
/*01d0*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ee6000c1e1900 */
/*01e0*/ IMAD.WIDE.U32 R14, R14, R11, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fe400078e000b */
/*01f0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1900 */
/*0200*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ee2000c1e1900 */
/*0210*/ FFMA R0, R7, R12, R0 ; /* 0x0000000c07007223 */
/* 0x004fc80000000000 */
/*0220*/ FFMA R0, R15, R9, R0 ; /* 0x000000090f007223 */
/* 0x008fe40000000000 */
/*0230*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0240*/ BSSY B0, 0x310 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0250*/ @P0 BRA 0x300 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0260*/ IADD3 R12, R6, -0x1, RZ ; /* 0xffffffff060c7810 */
/* 0x000fe20007ffe0ff */
/*0270*/ LDG.E R7, [R2.64+0x8] ; /* 0x0000080402077981 */
/* 0x000ea8000c1e1900 */
/*0280*/ IMAD.WIDE.U32 R12, R12, R11, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fcc00078e000b */
/*0290*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea4000c1e1900 */
/*02a0*/ FFMA R0, R13, R7, R0 ; /* 0x000000070d007223 */
/* 0x004fe20000000000 */
/*02b0*/ @P0 BRA 0x300 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*02c0*/ IMAD.WIDE.U32 R12, R6, R11, c[0x0][0x160] ; /* 0x00005800060c7625 */
/* 0x000fe200078e000b */
/*02d0*/ LDG.E R2, [R2.64+0xc] ; /* 0x00000c0402027981 */
/* 0x000eaa000c1e1900 */
/*02e0*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ FFMA R0, R13, R2, R0 ; /* 0x000000020d007223 */
/* 0x004fc40000000000 */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0310*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe40007ffe0ff */
/*0320*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc40007ffe0ff */
/*0330*/ IADD3 R2, R10, R5, RZ ; /* 0x000000050a027210 */
/* 0x000fc80007ffe0ff */
/*0340*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f25270 */
/*0350*/ @P1 BRA 0x150 ; /* 0xfffffdf000001947 */
/* 0x000fea000383ffff */
/*0360*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff067624 */
/* 0x000fca00078e00ff */
/*0370*/ LOP3.LUT P0, R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fda000780c0ff */
/*0380*/ @!P0 BRA 0x4c0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0390*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*03a0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0006 */
/*03b0*/ IMAD.WIDE.U32 R2, R5, R2, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x000fc800078e0002 */
/*03c0*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0003 */
/*03d0*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fe20000000f00 */
/*03e0*/ IMAD R5, R4, c[0x0][0x178], R5 ; /* 0x00005e0004057a24 */
/* 0x000fe400078e0205 */
/*03f0*/ ISETP.GE.AND P2, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f46270 */
/*0400*/ @!P2 MOV R2, 0x4 ; /* 0x000000040002a802 */
/* 0x000fe20000000f00 */
/*0410*/ @!P2 IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff07a224 */
/* 0x000fc800078e0009 */
/*0420*/ @!P2 IMAD.WIDE.U32 R2, R5.reuse, R2, c[0x0][0x160] ; /* 0x000058000502a625 */
/* 0x040fe400078e0002 */
/*0430*/ @!P2 LDG.E R7, [R6.64] ; /* 0x000000040607a981 */
/* 0x0000a8000c1e1900 */
/*0440*/ @!P2 LDG.E R2, [R2.64] ; /* 0x000000040202a981 */
/* 0x000ea2000c1e1900 */
/*0450*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe40007ffe0ff */
/*0460*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe40007ffe0ff */
/*0470*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc40003f25270 */
/*0480*/ IADD3 R6, P0, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x001fc80007f1e0ff */
/*0490*/ IADD3.X R9, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff097210 */
/* 0x000fe200007fe4ff */
/*04a0*/ @!P2 FFMA R0, R7, R2, R0 ; /* 0x000000020700a223 */
/* 0x004fcc0000000000 */
/*04b0*/ @P1 BRA 0x3f0 ; /* 0xffffff3000001947 */
/* 0x000fea000383ffff */
/*04c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04d0*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f06270 */
/*04e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0500*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0205 */
/*0510*/ STG.E [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x000fe8000c101904 */
/*0520*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cstdio>
#include <ctime>
#include <math.h>
//CUDA kernel function to add the elements of two arrays
__global__
void matvec(float *a, float *x, float *y, int n)
{
//Set index per block and sum variable
int row = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.0f;
//Perform the matrix-vector multiplication
for(unsigned int i = 0; i < n; i++)
{
if (row < n)
{
sum += x[i]*a[row*n+i];
}
}
//Synchronize the various threads working
__syncthreads();
//Put the results in the output vector
if(row < n)
{
y[row] = sum;
__syncthreads();
}
}
int main(void)
{
//Initializae the clock timer
clock_t start = clock();
//Set matrix and vector dimensions
int N = 10000;
//Allocate unified memory -- accessible from cpu or gpu
float *x, *y, *a;
cudaMallocManaged(&x, N*sizeof(float));
cudaMallocManaged(&y, N*sizeof(float));
cudaMallocManaged(&a, N*N*sizeof(float));
// initialize x and y arrays on the host
for (unsigned int i = 0; i < N*N; ++i)
a[i] = 0.0;
for (unsigned int i = 0; i < N; i++) {
a[i*N+i] = 4.0;
if (i > 0) a[i*N+i-1] = -1.0;
if (i < N-1) a[i*N+i+1] = -1.0;
x[i] = 1.0;
y[i] = 0.0;
}
//Set the block size and run the kernel
int blockSize = 1024;
int numBlocks = (N + blockSize - 1) / blockSize;
matvec<<<numBlocks, blockSize>>>(a, x, y, N);
//Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
//Finish the timer
double el = double(clock() - start) / CLOCKS_PER_SEC;
//Print the results
printf("y[0]=%8.4e and y[1]=%8.4e\n", y[0], y[1]);
printf("Number of elements in array %8.0f\n", float(N));
printf("Elapsed time: %8.8f seconds\n", el);
// Free memory
cudaFree(x);
cudaFree(y);
cudaFree(a);
return 0;
} | .file "tmpxft_001730a2_00000000-6_mat_vec_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6matvecPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6matvecPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6matvecPfS_S_iPfS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matvecPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z30__device_stub__Z6matvecPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6matvecPfS_S_iPfS_S_i
.globl _Z6matvecPfS_S_i
.type _Z6matvecPfS_S_i, @function
_Z6matvecPfS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6matvecPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6matvecPfS_S_i, .-_Z6matvecPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "y[0]=%8.4e and y[1]=%8.4e\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Number of elements in array %8.0f\n"
.section .rodata.str1.1
.LC8:
.string "Elapsed time: %8.8f seconds\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $1, %edx
movl $40000, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $40000, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $400000000, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L12:
movq 24(%rsp), %rdx
movl $0x00000000, (%rdx,%rax)
addq $4, %rax
cmpq $400000000, %rax
jne .L12
movl $-1, %ecx
movl $0, %edx
movl $0, %eax
movss .LC1(%rip), %xmm0
movss .LC2(%rip), %xmm3
movaps %xmm3, %xmm2
movss .LC3(%rip), %xmm1
jmp .L15
.L13:
movq 24(%rsp), %rsi
movss %xmm2, 4(%rsi,%rdx)
movq 8(%rsp), %rsi
movss %xmm1, (%rsi,%rax,4)
movq 16(%rsp), %rsi
movl $0x00000000, (%rsi,%rax,4)
addq $1, %rax
addq $40004, %rdx
addl $10001, %ecx
.L15:
movq 24(%rsp), %rsi
movss %xmm0, (%rsi,%rdx)
testl %eax, %eax
je .L13
movl %ecx, %esi
movq 24(%rsp), %rdi
movss %xmm3, (%rdi,%rsi,4)
cmpl $9998, %eax
jbe .L13
movl %eax, %eax
movq 8(%rsp), %rdx
movl $0x3f800000, (%rdx,%rax,4)
movq 16(%rsp), %rdx
movl $0x00000000, (%rdx,%rax,4)
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L16:
call cudaDeviceSynchronize@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
movq %xmm0, %rbx
movq 16(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 4(%rax), %xmm1
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movsd .LC6(%rip), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $10000, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z30__device_stub__Z6matvecPfS_S_iPfS_S_i
jmp .L16
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z6matvecPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matvecPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1082130432
.align 4
.LC2:
.long -1082130432
.align 4
.LC3:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1093567616
.align 8
.LC6:
.long 0
.long 1086556160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdio>
#include <ctime>
#include <math.h>
//CUDA kernel function to add the elements of two arrays
__global__
void matvec(float *a, float *x, float *y, int n)
{
//Set index per block and sum variable
int row = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.0f;
//Perform the matrix-vector multiplication
for(unsigned int i = 0; i < n; i++)
{
if (row < n)
{
sum += x[i]*a[row*n+i];
}
}
//Synchronize the various threads working
__syncthreads();
//Put the results in the output vector
if(row < n)
{
y[row] = sum;
__syncthreads();
}
}
int main(void)
{
//Initializae the clock timer
clock_t start = clock();
//Set matrix and vector dimensions
int N = 10000;
//Allocate unified memory -- accessible from cpu or gpu
float *x, *y, *a;
cudaMallocManaged(&x, N*sizeof(float));
cudaMallocManaged(&y, N*sizeof(float));
cudaMallocManaged(&a, N*N*sizeof(float));
// initialize x and y arrays on the host
for (unsigned int i = 0; i < N*N; ++i)
a[i] = 0.0;
for (unsigned int i = 0; i < N; i++) {
a[i*N+i] = 4.0;
if (i > 0) a[i*N+i-1] = -1.0;
if (i < N-1) a[i*N+i+1] = -1.0;
x[i] = 1.0;
y[i] = 0.0;
}
//Set the block size and run the kernel
int blockSize = 1024;
int numBlocks = (N + blockSize - 1) / blockSize;
matvec<<<numBlocks, blockSize>>>(a, x, y, N);
//Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
//Finish the timer
double el = double(clock() - start) / CLOCKS_PER_SEC;
//Print the results
printf("y[0]=%8.4e and y[1]=%8.4e\n", y[0], y[1]);
printf("Number of elements in array %8.0f\n", float(N));
printf("Elapsed time: %8.8f seconds\n", el);
// Free memory
cudaFree(x);
cudaFree(y);
cudaFree(a);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
#include <ctime>
#include <math.h>
//CUDA kernel function to add the elements of two arrays
__global__
void matvec(float *a, float *x, float *y, int n)
{
//Set index per block and sum variable
int row = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.0f;
//Perform the matrix-vector multiplication
for(unsigned int i = 0; i < n; i++)
{
if (row < n)
{
sum += x[i]*a[row*n+i];
}
}
//Synchronize the various threads working
__syncthreads();
//Put the results in the output vector
if(row < n)
{
y[row] = sum;
__syncthreads();
}
}
int main(void)
{
//Initializae the clock timer
clock_t start = clock();
//Set matrix and vector dimensions
int N = 10000;
//Allocate unified memory -- accessible from cpu or gpu
float *x, *y, *a;
hipMallocManaged(&x, N*sizeof(float));
hipMallocManaged(&y, N*sizeof(float));
hipMallocManaged(&a, N*N*sizeof(float));
// initialize x and y arrays on the host
for (unsigned int i = 0; i < N*N; ++i)
a[i] = 0.0;
for (unsigned int i = 0; i < N; i++) {
a[i*N+i] = 4.0;
if (i > 0) a[i*N+i-1] = -1.0;
if (i < N-1) a[i*N+i+1] = -1.0;
x[i] = 1.0;
y[i] = 0.0;
}
//Set the block size and run the kernel
int blockSize = 1024;
int numBlocks = (N + blockSize - 1) / blockSize;
matvec<<<numBlocks, blockSize>>>(a, x, y, N);
//Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
//Finish the timer
double el = double(clock() - start) / CLOCKS_PER_SEC;
//Print the results
printf("y[0]=%8.4e and y[1]=%8.4e\n", y[0], y[1]);
printf("Number of elements in array %8.0f\n", float(N));
printf("Elapsed time: %8.8f seconds\n", el);
// Free memory
hipFree(x);
hipFree(y);
hipFree(a);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
#include <ctime>
#include <math.h>
//CUDA kernel function to add the elements of two arrays
__global__
void matvec(float *a, float *x, float *y, int n)
{
//Set index per block and sum variable
int row = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.0f;
//Perform the matrix-vector multiplication
for(unsigned int i = 0; i < n; i++)
{
if (row < n)
{
sum += x[i]*a[row*n+i];
}
}
//Synchronize the various threads working
__syncthreads();
//Put the results in the output vector
if(row < n)
{
y[row] = sum;
__syncthreads();
}
}
int main(void)
{
//Initializae the clock timer
clock_t start = clock();
//Set matrix and vector dimensions
int N = 10000;
//Allocate unified memory -- accessible from cpu or gpu
float *x, *y, *a;
hipMallocManaged(&x, N*sizeof(float));
hipMallocManaged(&y, N*sizeof(float));
hipMallocManaged(&a, N*N*sizeof(float));
// initialize x and y arrays on the host
for (unsigned int i = 0; i < N*N; ++i)
a[i] = 0.0;
for (unsigned int i = 0; i < N; i++) {
a[i*N+i] = 4.0;
if (i > 0) a[i*N+i-1] = -1.0;
if (i < N-1) a[i*N+i+1] = -1.0;
x[i] = 1.0;
y[i] = 0.0;
}
//Set the block size and run the kernel
int blockSize = 1024;
int numBlocks = (N + blockSize - 1) / blockSize;
matvec<<<numBlocks, blockSize>>>(a, x, y, N);
//Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
//Finish the timer
double el = double(clock() - start) / CLOCKS_PER_SEC;
//Print the results
printf("y[0]=%8.4e and y[1]=%8.4e\n", y[0], y[1]);
printf("Number of elements in array %8.0f\n", float(N));
printf("Elapsed time: %8.8f seconds\n", el);
// Free memory
hipFree(x);
hipFree(y);
hipFree(a);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matvecPfS_S_i
.globl _Z6matvecPfS_S_i
.p2align 8
.type _Z6matvecPfS_S_i,@function
_Z6matvecPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_eq_u32 s3, 0
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v3, 0
v_mul_lo_u32 v2, v1, s3
s_mov_b32 s8, s3
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v0, v3
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s9
s_add_i32 s8, s8, -1
v_add_nc_u32_e32 v2, 1, v2
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, s2, s4, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s2, s5, v5, s2
s_load_b32 s2, s[6:7], 0x0
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s2, v4
s_branch .LBB0_2
.LBB0_5:
v_mov_b32_e32 v0, 0
.LBB0_6:
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_8
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_8:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matvecPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matvecPfS_S_i, .Lfunc_end0-_Z6matvecPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matvecPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matvecPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
#include <ctime>
#include <math.h>
//CUDA kernel function to add the elements of two arrays
__global__
void matvec(float *a, float *x, float *y, int n)
{
//Set index per block and sum variable
int row = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.0f;
//Perform the matrix-vector multiplication
for(unsigned int i = 0; i < n; i++)
{
if (row < n)
{
sum += x[i]*a[row*n+i];
}
}
//Synchronize the various threads working
__syncthreads();
//Put the results in the output vector
if(row < n)
{
y[row] = sum;
__syncthreads();
}
}
int main(void)
{
//Initializae the clock timer
clock_t start = clock();
//Set matrix and vector dimensions
int N = 10000;
//Allocate unified memory -- accessible from cpu or gpu
float *x, *y, *a;
hipMallocManaged(&x, N*sizeof(float));
hipMallocManaged(&y, N*sizeof(float));
hipMallocManaged(&a, N*N*sizeof(float));
// initialize x and y arrays on the host
for (unsigned int i = 0; i < N*N; ++i)
a[i] = 0.0;
for (unsigned int i = 0; i < N; i++) {
a[i*N+i] = 4.0;
if (i > 0) a[i*N+i-1] = -1.0;
if (i < N-1) a[i*N+i+1] = -1.0;
x[i] = 1.0;
y[i] = 0.0;
}
//Set the block size and run the kernel
int blockSize = 1024;
int numBlocks = (N + blockSize - 1) / blockSize;
matvec<<<numBlocks, blockSize>>>(a, x, y, N);
//Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
//Finish the timer
double el = double(clock() - start) / CLOCKS_PER_SEC;
//Print the results
printf("y[0]=%8.4e and y[1]=%8.4e\n", y[0], y[1]);
printf("Number of elements in array %8.0f\n", float(N));
printf("Elapsed time: %8.8f seconds\n", el);
// Free memory
hipFree(x);
hipFree(y);
hipFree(a);
return 0;
} | .text
.file "mat_vec_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__matvecPfS_S_i # -- Begin function _Z21__device_stub__matvecPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__matvecPfS_S_i,@function
_Z21__device_stub__matvecPfS_S_i: # @_Z21__device_stub__matvecPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matvecPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__matvecPfS_S_i, .Lfunc_end0-_Z21__device_stub__matvecPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI1_1:
.quad 0x40c3880000000000 # double 1.0E+4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4294967295, %r14d # imm = 0xFFFFFFFF
callq clock
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
movl $1, %edx
callq hipMallocManaged
movq %rsp, %rdi
movl $40000, %esi # imm = 0x9C40
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %r15
xorl %r12d, %r12d
movl $400000000, %edx # imm = 0x17D78400
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
movq 16(%rsp), %rax
movq (%rsp), %rcx
leaq 4(%r15), %rdx
movl $4294967295, %esi # imm = 0xFFFFFFFF
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movl $-1082130432, (%rdx) # imm = 0xBF800000
.LBB1_4: # in Loop: Header=BB1_1 Depth=1
movl $1065353216, (%rax,%r12) # imm = 0x3F800000
movl $0, (%rcx,%r12)
addq $4, %r12
addq $10001, %rsi # imm = 0x2711
addq $40004, %rdx # imm = 0x9C44
cmpq $40000, %r12 # imm = 0x9C40
je .LBB1_5
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1082130432, -4(%rdx) # imm = 0x40800000
testq %r12, %r12
je .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movl %esi, %edi
movl $-1082130432, (%r15,%rdi,4) # imm = 0xBF800000
cmpq $39996, %r12 # imm = 0x9C3C
jne .LBB1_3
jmp .LBB1_4
.LBB1_5:
leaq 11(%r14), %rdi
addq $1025, %r14 # imm = 0x401
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $10000, 28(%rsp) # imm = 0x2710
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6matvecPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
callq hipDeviceSynchronize
callq clock
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
movq (%rsp), %rax
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 4(%rax), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movb $2, %al
callq printf
movsd .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $.L.str.2, %edi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matvecPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matvecPfS_S_i,@object # @_Z6matvecPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6matvecPfS_S_i
.p2align 3, 0x0
_Z6matvecPfS_S_i:
.quad _Z21__device_stub__matvecPfS_S_i
.size _Z6matvecPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "y[0]=%8.4e and y[1]=%8.4e\n"
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Number of elements in array %8.0f\n"
.size .L.str.1, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Elapsed time: %8.8f seconds\n"
.size .L.str.2, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6matvecPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matvecPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matvecPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6matvecPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f05270 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fd000078e0203 */
/*0070*/ @!P0 BRA 0x4c0 ; /* 0x0000044000008947 */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff037624 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc600078e00ff */
/*00a0*/ IADD3 R0, R3, -0x1, RZ ; /* 0xffffffff03007810 */
/* 0x000fc80007ffe0ff */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*00c0*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fd60000000f00 */
/*00d0*/ @!P0 BRA 0x360 ; /* 0x0000028000008947 */
/* 0x000fea0003800000 */
/*00e0*/ LOP3.LUT R10, R3, 0x3, RZ, 0xc0, !PT ; /* 0x00000003030a7812 */
/* 0x000fe200078ec0ff */
/*00f0*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0100*/ ISETP.GE.AND P0, PT, R4.reuse, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x040fe20003f06270 */
/*0110*/ IMAD R6, R4, R3.reuse, 0x3 ; /* 0x0000000304067424 */
/* 0x080fe200078e0203 */
/*0120*/ IADD3 R10, R10, -c[0x0][0x178], RZ ; /* 0x80005e000a0a7a10 */
/* 0x000fe20007ffe0ff */
/*0130*/ IMAD R8, R4, R3, 0x1 ; /* 0x0000000104087424 */
/* 0x000fe400078e0203 */
/*0140*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*0150*/ MOV R11, 0x4 ; /* 0x00000004000b7802 */
/* 0x000fe20000000f00 */
/*0160*/ BSSY B0, 0x240 ; /* 0x000000d000007945 */
/* 0x000fe80003800000 */
/*0170*/ IMAD.WIDE.U32 R2, R5, R11, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x000fe200078e000b */
/*0180*/ @P0 BRA 0x230 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0190*/ IMAD R12, R4, c[0x0][0x178], R5.reuse ; /* 0x00005e00040c7a24 */
/* 0x100fe200078e0205 */
/*01a0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IMAD.IADD R14, R8, 0x1, R5 ; /* 0x00000001080e7824 */
/* 0x000fc400078e0205 */
/*01c0*/ IMAD.WIDE.U32 R12, R12, R11.reuse, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x080fe200078e000b */
/*01d0*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ee6000c1e1900 */
/*01e0*/ IMAD.WIDE.U32 R14, R14, R11, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fe400078e000b */
/*01f0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1900 */
/*0200*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ee2000c1e1900 */
/*0210*/ FFMA R0, R7, R12, R0 ; /* 0x0000000c07007223 */
/* 0x004fc80000000000 */
/*0220*/ FFMA R0, R15, R9, R0 ; /* 0x000000090f007223 */
/* 0x008fe40000000000 */
/*0230*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0240*/ BSSY B0, 0x310 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0250*/ @P0 BRA 0x300 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0260*/ IADD3 R12, R6, -0x1, RZ ; /* 0xffffffff060c7810 */
/* 0x000fe20007ffe0ff */
/*0270*/ LDG.E R7, [R2.64+0x8] ; /* 0x0000080402077981 */
/* 0x000ea8000c1e1900 */
/*0280*/ IMAD.WIDE.U32 R12, R12, R11, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fcc00078e000b */
/*0290*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea4000c1e1900 */
/*02a0*/ FFMA R0, R13, R7, R0 ; /* 0x000000070d007223 */
/* 0x004fe20000000000 */
/*02b0*/ @P0 BRA 0x300 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*02c0*/ IMAD.WIDE.U32 R12, R6, R11, c[0x0][0x160] ; /* 0x00005800060c7625 */
/* 0x000fe200078e000b */
/*02d0*/ LDG.E R2, [R2.64+0xc] ; /* 0x00000c0402027981 */
/* 0x000eaa000c1e1900 */
/*02e0*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ FFMA R0, R13, R2, R0 ; /* 0x000000020d007223 */
/* 0x004fc40000000000 */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0310*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe40007ffe0ff */
/*0320*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc40007ffe0ff */
/*0330*/ IADD3 R2, R10, R5, RZ ; /* 0x000000050a027210 */
/* 0x000fc80007ffe0ff */
/*0340*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f25270 */
/*0350*/ @P1 BRA 0x150 ; /* 0xfffffdf000001947 */
/* 0x000fea000383ffff */
/*0360*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff067624 */
/* 0x000fca00078e00ff */
/*0370*/ LOP3.LUT P0, R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fda000780c0ff */
/*0380*/ @!P0 BRA 0x4c0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0390*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*03a0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0006 */
/*03b0*/ IMAD.WIDE.U32 R2, R5, R2, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x000fc800078e0002 */
/*03c0*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0003 */
/*03d0*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fe20000000f00 */
/*03e0*/ IMAD R5, R4, c[0x0][0x178], R5 ; /* 0x00005e0004057a24 */
/* 0x000fe400078e0205 */
/*03f0*/ ISETP.GE.AND P2, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f46270 */
/*0400*/ @!P2 MOV R2, 0x4 ; /* 0x000000040002a802 */
/* 0x000fe20000000f00 */
/*0410*/ @!P2 IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff07a224 */
/* 0x000fc800078e0009 */
/*0420*/ @!P2 IMAD.WIDE.U32 R2, R5.reuse, R2, c[0x0][0x160] ; /* 0x000058000502a625 */
/* 0x040fe400078e0002 */
/*0430*/ @!P2 LDG.E R7, [R6.64] ; /* 0x000000040607a981 */
/* 0x0000a8000c1e1900 */
/*0440*/ @!P2 LDG.E R2, [R2.64] ; /* 0x000000040202a981 */
/* 0x000ea2000c1e1900 */
/*0450*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe40007ffe0ff */
/*0460*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe40007ffe0ff */
/*0470*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc40003f25270 */
/*0480*/ IADD3 R6, P0, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x001fc80007f1e0ff */
/*0490*/ IADD3.X R9, RZ, R9, RZ, P0, !PT ; /* 0x00000009ff097210 */
/* 0x000fe200007fe4ff */
/*04a0*/ @!P2 FFMA R0, R7, R2, R0 ; /* 0x000000020700a223 */
/* 0x004fcc0000000000 */
/*04b0*/ @P1 BRA 0x3f0 ; /* 0xffffff3000001947 */
/* 0x000fea000383ffff */
/*04c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04d0*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f06270 */
/*04e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0500*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0205 */
/*0510*/ STG.E [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x000fe8000c101904 */
/*0520*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matvecPfS_S_i
.globl _Z6matvecPfS_S_i
.p2align 8
.type _Z6matvecPfS_S_i,@function
_Z6matvecPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_eq_u32 s3, 0
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_cbranch_scc1 .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v3, 0
v_mul_lo_u32 v2, v1, s3
s_mov_b32 s8, s3
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v0, v3
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s9
s_add_i32 s8, s8, -1
v_add_nc_u32_e32 v2, 1, v2
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, s2, s4, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s2, s5, v5, s2
s_load_b32 s2, s[6:7], 0x0
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s2, v4
s_branch .LBB0_2
.LBB0_5:
v_mov_b32_e32 v0, 0
.LBB0_6:
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_8
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_8:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matvecPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matvecPfS_S_i, .Lfunc_end0-_Z6matvecPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matvecPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matvecPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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