system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define N 10
#define num_threads 10000
__global__ void increment_naive(int *d)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
tid = tid % N;
d[tid] += 1;
}
__global__ void increment_atomic(int *d)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
tid = tid % N;
atomicAdd(&d[tid], 1);
}
int main()
{
int h[N], *d;
cudaMalloc(&d, sizeof(int)*N);
cudaMemset(d, 0, sizeof(int)*N);
increment_naive<<<(num_threads/N), N>>>(d);
cudaMemcpy(h, d, sizeof(int)*N, cudaMemcpyDeviceToHost);
for(int i=0; i<N; i++)
std::cout << h[i] << "\n";
cudaMemset(d, 0, sizeof(int)*N);
increment_atomic<<<(num_threads/N), N>>>(d);
cudaMemcpy(h, d, sizeof(int)*N, cudaMemcpyDeviceToHost);
for(int i=0; i<N; i++)
std::cout << h[i] << "\n";
}
//12
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//1000 | #include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define N 10
#define num_threads 10000
__global__ void increment_naive(int *d)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
tid = tid % N;
d[tid] += 1;
}
__global__ void increment_atomic(int *d)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
tid = tid % N;
atomicAdd(&d[tid], 1);
}
int main()
{
int h[N], *d;
hipMalloc(&d, sizeof(int)*N);
hipMemset(d, 0, sizeof(int)*N);
increment_naive<<<(num_threads/N), N>>>(d);
hipMemcpy(h, d, sizeof(int)*N, hipMemcpyDeviceToHost);
for(int i=0; i<N; i++)
std::cout << h[i] << "\n";
hipMemset(d, 0, sizeof(int)*N);
increment_atomic<<<(num_threads/N), N>>>(d);
hipMemcpy(h, d, sizeof(int)*N, hipMemcpyDeviceToHost);
for(int i=0; i<N; i++)
std::cout << h[i] << "\n";
}
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You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define N 10
#define num_threads 10000
__global__ void increment_naive(int *d)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
tid = tid % N;
d[tid] += 1;
}
__global__ void increment_atomic(int *d)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
tid = tid % N;
atomicAdd(&d[tid], 1);
}
int main()
{
int h[N], *d;
hipMalloc(&d, sizeof(int)*N);
hipMemset(d, 0, sizeof(int)*N);
increment_naive<<<(num_threads/N), N>>>(d);
hipMemcpy(h, d, sizeof(int)*N, hipMemcpyDeviceToHost);
for(int i=0; i<N; i++)
std::cout << h[i] << "\n";
hipMemset(d, 0, sizeof(int)*N);
increment_atomic<<<(num_threads/N), N>>>(d);
hipMemcpy(h, d, sizeof(int)*N, hipMemcpyDeviceToHost);
for(int i=0; i<N; i++)
std::cout << h[i] << "\n";
}
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//1000 | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15increment_naivePi
.globl _Z15increment_naivePi
.p2align 8
.type _Z15increment_naivePi,@function
_Z15increment_naivePi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mul_hi_i32 v0, v1, 0x66666667
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 31, v0
v_ashrrev_i32_e32 v0, 2, v0
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, 10
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15increment_naivePi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15increment_naivePi, .Lfunc_end0-_Z15increment_naivePi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16increment_atomicPi
.globl _Z16increment_atomicPi
.p2align 8
.type _Z16increment_atomicPi,@function
_Z16increment_atomicPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mul_hi_i32 v0, v1, 0x66666667
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 31, v0
v_ashrrev_i32_e32 v0, 2, v0
v_add_nc_u32_e32 v0, v0, v2
v_mov_b32_e32 v2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, 10
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16increment_atomicPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16increment_atomicPi, .Lfunc_end1-_Z16increment_atomicPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15increment_naivePi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15increment_naivePi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16increment_atomicPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16increment_atomicPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define N 10
#define num_threads 10000
__global__ void increment_naive(int *d)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
tid = tid % N;
d[tid] += 1;
}
__global__ void increment_atomic(int *d)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
tid = tid % N;
atomicAdd(&d[tid], 1);
}
int main()
{
int h[N], *d;
hipMalloc(&d, sizeof(int)*N);
hipMemset(d, 0, sizeof(int)*N);
increment_naive<<<(num_threads/N), N>>>(d);
hipMemcpy(h, d, sizeof(int)*N, hipMemcpyDeviceToHost);
for(int i=0; i<N; i++)
std::cout << h[i] << "\n";
hipMemset(d, 0, sizeof(int)*N);
increment_atomic<<<(num_threads/N), N>>>(d);
hipMemcpy(h, d, sizeof(int)*N, hipMemcpyDeviceToHost);
for(int i=0; i<N; i++)
std::cout << h[i] << "\n";
}
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//12
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//12
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//1000
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//1000
//1000
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//1000
//1000
//1000 | .text
.file "9_atomic_operations.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__increment_naivePi # -- Begin function _Z30__device_stub__increment_naivePi
.p2align 4, 0x90
.type _Z30__device_stub__increment_naivePi,@function
_Z30__device_stub__increment_naivePi: # @_Z30__device_stub__increment_naivePi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15increment_naivePi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z30__device_stub__increment_naivePi, .Lfunc_end0-_Z30__device_stub__increment_naivePi
.cfi_endproc
# -- End function
.globl _Z31__device_stub__increment_atomicPi # -- Begin function _Z31__device_stub__increment_atomicPi
.p2align 4, 0x90
.type _Z31__device_stub__increment_atomicPi,@function
_Z31__device_stub__increment_atomicPi: # @_Z31__device_stub__increment_atomicPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z16increment_atomicPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z31__device_stub__increment_atomicPi, .Lfunc_end1-_Z31__device_stub__increment_atomicPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294967306, %rbx # imm = 0x10000000A
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $40, %edx
xorl %esi, %esi
callq hipMemset
leaq 990(%rbx), %r14
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 16(%rsp)
leaq 96(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z15increment_naivePi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
cmpq $10, %r15
jne .LBB2_3
# %bb.4:
movq 8(%rsp), %rdi
movl $40, %edx
xorl %esi, %esi
callq hipMemset
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16increment_atomicPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $10, %rbx
jne .LBB2_7
# %bb.8:
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15increment_naivePi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16increment_atomicPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15increment_naivePi,@object # @_Z15increment_naivePi
.section .rodata,"a",@progbits
.globl _Z15increment_naivePi
.p2align 3, 0x0
_Z15increment_naivePi:
.quad _Z30__device_stub__increment_naivePi
.size _Z15increment_naivePi, 8
.type _Z16increment_atomicPi,@object # @_Z16increment_atomicPi
.globl _Z16increment_atomicPi
.p2align 3, 0x0
_Z16increment_atomicPi:
.quad _Z31__device_stub__increment_atomicPi
.size _Z16increment_atomicPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n"
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15increment_naivePi"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16increment_atomicPi"
.size .L__unnamed_2, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__increment_naivePi
.addrsig_sym _Z31__device_stub__increment_atomicPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15increment_naivePi
.addrsig_sym _Z16increment_atomicPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16increment_atomicPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ MOV R5, 0x1 ; /* 0x0000000100057802 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*0060*/ IMAD.HI R2, R0, 0x66666667, RZ ; /* 0x6666666700027827 */
/* 0x000fca00078e02ff */
/*0070*/ SHF.R.U32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011602 */
/*0080*/ LEA.HI.SX32 R3, R2, R3, 0x1e ; /* 0x0000000302037211 */
/* 0x000fe200078ff2ff */
/*0090*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fc800000001ff */
/*00a0*/ IMAD R3, R3, -0xa, R0 ; /* 0xfffffff603037824 */
/* 0x000fcc00078e0200 */
/*00b0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*00c0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e184 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15increment_naivePi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0040*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*0050*/ IMAD.HI R2, R0, 0x66666667, RZ ; /* 0x6666666700027827 */
/* 0x000fca00078e02ff */
/*0060*/ SHF.R.U32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011602 */
/*0070*/ LEA.HI.SX32 R3, R2, R3, 0x1e ; /* 0x0000000302037211 */
/* 0x000fe200078ff2ff */
/*0080*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fc800000001ff */
/*0090*/ IMAD R3, R3, -0xa, R0 ; /* 0xfffffff603037824 */
/* 0x000fcc00078e0200 */
/*00a0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*00d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15increment_naivePi
.globl _Z15increment_naivePi
.p2align 8
.type _Z15increment_naivePi,@function
_Z15increment_naivePi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mul_hi_i32 v0, v1, 0x66666667
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 31, v0
v_ashrrev_i32_e32 v0, 2, v0
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, 10
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15increment_naivePi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15increment_naivePi, .Lfunc_end0-_Z15increment_naivePi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16increment_atomicPi
.globl _Z16increment_atomicPi
.p2align 8
.type _Z16increment_atomicPi,@function
_Z16increment_atomicPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mul_hi_i32 v0, v1, 0x66666667
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 31, v0
v_ashrrev_i32_e32 v0, 2, v0
v_add_nc_u32_e32 v0, v0, v2
v_mov_b32_e32 v2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, 10
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16increment_atomicPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16increment_atomicPi, .Lfunc_end1-_Z16increment_atomicPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15increment_naivePi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15increment_naivePi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16increment_atomicPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16increment_atomicPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d46a5_00000000-6_9_atomic_operations.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z15increment_naivePiPi
.type _Z35__device_stub__Z15increment_naivePiPi, @function
_Z35__device_stub__Z15increment_naivePiPi:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15increment_naivePi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z35__device_stub__Z15increment_naivePiPi, .-_Z35__device_stub__Z15increment_naivePiPi
.globl _Z15increment_naivePi
.type _Z15increment_naivePi, @function
_Z15increment_naivePi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z15increment_naivePiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z15increment_naivePi, .-_Z15increment_naivePi
.globl _Z36__device_stub__Z16increment_atomicPiPi
.type _Z36__device_stub__Z16increment_atomicPiPi, @function
_Z36__device_stub__Z16increment_atomicPiPi:
.LFB3696:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16increment_atomicPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z36__device_stub__Z16increment_atomicPiPi, .-_Z36__device_stub__Z16increment_atomicPiPi
.globl _Z16increment_atomicPi
.type _Z16increment_atomicPi, @function
_Z16increment_atomicPi:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z16increment_atomicPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z16increment_atomicPi, .-_Z16increment_atomicPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $40, %edx
movl $0, %esi
movq (%rsp), %rdi
call cudaMemset@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1000, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L20:
leaq 32(%rsp), %rbx
movl $2, %ecx
movl $40, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rbp
leaq 72(%rsp), %r12
leaq _ZSt4cout(%rip), %r14
leaq .LC0(%rip), %r13
.L21:
movl (%rbx), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %r12
jne .L21
movl $40, %edx
movl $0, %esi
movq (%rsp), %rdi
call cudaMemset@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1000, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L22:
leaq 32(%rsp), %rdi
movl $2, %ecx
movl $40, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
leaq _ZSt4cout(%rip), %r13
leaq .LC0(%rip), %rbx
.L23:
movl 0(%rbp), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbx, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbp
cmpq %rbp, %r12
jne .L23
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq (%rsp), %rdi
call _Z35__device_stub__Z15increment_naivePiPi
jmp .L20
.L29:
movq (%rsp), %rdi
call _Z36__device_stub__Z16increment_atomicPiPi
jmp .L22
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z16increment_atomicPi"
.LC2:
.string "_Z15increment_naivePi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z16increment_atomicPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15increment_naivePi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "9_atomic_operations.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__increment_naivePi # -- Begin function _Z30__device_stub__increment_naivePi
.p2align 4, 0x90
.type _Z30__device_stub__increment_naivePi,@function
_Z30__device_stub__increment_naivePi: # @_Z30__device_stub__increment_naivePi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15increment_naivePi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z30__device_stub__increment_naivePi, .Lfunc_end0-_Z30__device_stub__increment_naivePi
.cfi_endproc
# -- End function
.globl _Z31__device_stub__increment_atomicPi # -- Begin function _Z31__device_stub__increment_atomicPi
.p2align 4, 0x90
.type _Z31__device_stub__increment_atomicPi,@function
_Z31__device_stub__increment_atomicPi: # @_Z31__device_stub__increment_atomicPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z16increment_atomicPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z31__device_stub__increment_atomicPi, .Lfunc_end1-_Z31__device_stub__increment_atomicPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294967306, %rbx # imm = 0x10000000A
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $40, %edx
xorl %esi, %esi
callq hipMemset
leaq 990(%rbx), %r14
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 16(%rsp)
leaq 96(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z15increment_naivePi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
cmpq $10, %r15
jne .LBB2_3
# %bb.4:
movq 8(%rsp), %rdi
movl $40, %edx
xorl %esi, %esi
callq hipMemset
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16increment_atomicPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $10, %rbx
jne .LBB2_7
# %bb.8:
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15increment_naivePi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16increment_atomicPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15increment_naivePi,@object # @_Z15increment_naivePi
.section .rodata,"a",@progbits
.globl _Z15increment_naivePi
.p2align 3, 0x0
_Z15increment_naivePi:
.quad _Z30__device_stub__increment_naivePi
.size _Z15increment_naivePi, 8
.type _Z16increment_atomicPi,@object # @_Z16increment_atomicPi
.globl _Z16increment_atomicPi
.p2align 3, 0x0
_Z16increment_atomicPi:
.quad _Z31__device_stub__increment_atomicPi
.size _Z16increment_atomicPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n"
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15increment_naivePi"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16increment_atomicPi"
.size .L__unnamed_2, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__increment_naivePi
.addrsig_sym _Z31__device_stub__increment_atomicPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15increment_naivePi
.addrsig_sym _Z16increment_atomicPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
#include <cuda.h>
#include <math.h>
#include<stdio.h>
#include<stdlib.h>
#include <sys/types.h>
#include <time.h>
using namespace std;
__device__ int mymin(int a, int b)
{
int m = a;
if(m > b)
m=b;
return m;
}
__device__ int min1(int a,int b,int c)
{
int m=a;
if(m>b)
m=b;
if(m>c)
m=c;
return m;
}
int min2(int a,int b,int c)
{
int m=a;
if(m>b)
m=b;
if(m>c)
m=c;
return m;
}
void swapDiagnolPointers(int **prev,int **current)
{
int * temp = *prev;
*prev = *current;
*current = temp;
}
void swapDiagnolPointersForG(int **prevprev, int **prev,int **current)
{
int * temp = *prevprev;
*prevprev = *prev;
*prev = *current;
*current = temp;
}
__global__ void less_than_n(int k,int numElements,int * D1,int * D2,int * I1,int * I2,int * G0,int *G1,int * G2,char *s1,char *s2, int gi, int ge)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int s =0;
if( i > numElements ) return ;
if(i == 0)
{
G2[i]=gi+ge*k;
I2[i]=G2[i]+ge;
}
if(i == k)
{
G2[i]=gi+ge*k;
D2[i]=G2[i]+ge;
}
if( i>0 && i<k)
{
D2[i]=min(D1[i],G1[i]+gi)+ge;
I2[i]=min(I1[i-1],G1[i-1]+gi)+ge;
if(s1[i]!=s2[k-i])
s=1;
else
s=0;
G2[i]=min1(D2[i],I2[i],G0[i-1]+s);
}
}
__global__ void greater_than_n(int k,int numElements,int * D1,int * D2,int * I1,int * I2,int * G0,int *G1,int * G2,char *s1,char *s2,int n, int gi, int ge)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int s =0;
if( i > numElements ) return ;
D2[i]=min(D1[i+1],G1[i+1]+gi)+ge;
I2[i]=min(I1[i],G1[i]+gi)+ge;
if(s1[i+(k-n)]!=s2[k-(i+k-n)])
s=1;
else
s=0;
if((k-n)==1)
G2[i]=min1(D2[i],I2[i],G0[i]+s);
else
G2[i]=min1(D2[i],I2[i],G0[i+1]+s);
}
int main(int argc, char** argv)
{
int i,j,n,k,l;
time_t t0, t1;
clock_t c0,c1;
char skip;
scanf("%d",&n);
printf("%d \n",n);
while(1)
{
scanf("%c",&skip);
if(skip == '\n')
break;
}
size_t size = (n+1) * sizeof(char);
size_t size1 = (n+1)*sizeof(int);
char* h_s1 = (char*)malloc(size);
char* h_s2 = (char*)malloc(size);
for(i=1; i<=n; i++)
{
scanf("%c",&h_s1[i]);
}
while(1)
{
scanf("%c",&skip);
if(skip == '\n')
break;
}
for(i=1; i<=n; i++)
{
scanf("%c",&h_s2[i]);
}
/* t0=time(NULL);
c0=clock();
printf ("\tbegin (wall): %ld\n", (long) t0);
printf ("\tbegin (CPU): %d\n", (int) c0);
*/
int* h_D0 = (int*)malloc(size1);
int* h_D1 = (int*)malloc(size1);
int* h_D2 = (int*)malloc(size1);
int* h_G0 = (int*)malloc(size1);
int* h_G1 = (int*)malloc(size1);
int* h_G2 = (int*)malloc(size1);
int* h_I0 = (int*)malloc(size1);
int* h_I1 = (int*)malloc(size1);
int* h_I2 = (int*)malloc(size1);
// int D0[n+1],D1[n+1],D2[n+1],G0[n+1],G1[n+1],G2[n+1],I0[n+1],I1[n+1],I2[n+1]; //--- declaration of functions
int gi,ge,s,cost;
gi=2;ge=1;
int *d_D0, *d_D1, *d_D2;
cudaMalloc(&d_D0, size1);
cudaMalloc(&d_D1, size1);
cudaMalloc(&d_D2, size1);
int *d_G0, *d_G1, *d_G2;
cudaMalloc(&d_G0, size1);
cudaMalloc(&d_G1, size1);
cudaMalloc(&d_G2, size1);
int *d_I0, *d_I1, *d_I2;
cudaMalloc(&d_I0, size1);
cudaMalloc(&d_I1, size1);
cudaMalloc(&d_I2, size1);
char *d_s1, *d_s2;
cudaMalloc(&d_s1, size);
cudaMalloc(&d_s2, size);
cudaMemcpy(d_s1, h_s1, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_s2, h_s2, size, cudaMemcpyHostToDevice);
h_G1[0]=0;
cudaMemcpy(d_G1, h_G1, size1, cudaMemcpyHostToDevice);
int num_threads;
int num_blocks;
int numElements;
for(k=1;k<=2*n;k++)
{
if(k <=n)
{
numElements = k+1;
if( numElements <= 256) {
num_threads = numElements;
num_blocks =1 ;
}
else
{
num_threads = 256 ;
num_blocks = numElements/num_threads + ((numElements/num_threads == 0) ? 0 : 1) ;
}
less_than_n<<<num_blocks,num_threads>>>( k, numElements, d_D1, d_D2, d_I1,d_I2, d_G0, d_G1, d_G2, d_s1, d_s2, gi, ge);
}
if(k > n)
{
numElements = n-(k-n)+1;
if( numElements <= 256) {
num_threads = numElements;
num_blocks =1 ;
}
else
{
num_threads = 256 ;
num_blocks = numElements/num_threads + ((numElements/num_threads == 0) ? 0 : 1) ;
}
greater_than_n<<<num_blocks,num_threads>>>( k, numElements, d_D1, d_D2, d_I1,d_I2, d_G0, d_G1, d_G2, d_s1, d_s2, n, gi, ge);
}
swapDiagnolPointers(&d_D1,&d_D2);
swapDiagnolPointers(&d_I1,&d_I2);
swapDiagnolPointersForG(&d_G0,&d_G1, &d_G2);
}
cudaMemcpy(h_D2, d_D2, size1, cudaMemcpyDeviceToHost);
cudaMemcpy(h_G2, d_G2, size1, cudaMemcpyDeviceToHost);
cudaMemcpy(h_I2, d_I2, size1, cudaMemcpyDeviceToHost);
cudaMemcpy(h_D1, d_D1, size1, cudaMemcpyDeviceToHost);
cudaMemcpy(h_G1, d_G1, size1, cudaMemcpyDeviceToHost);
cudaMemcpy(h_I1, d_I1, size1, cudaMemcpyDeviceToHost);
cost=min2(h_D1[0],h_I1[0],h_G1[0]); //--- allignment cost
cout<<"Optimal Allignment cost: "<<cost<<endl;
/*
t1=time(NULL);
c1=clock();
printf ("\telapsed wall clock time: %ld\n", (long) (t1 - t0));
printf ("\telapsed CPU time: %f\n", (float) (c1 - c0)/CLOCKS_PER_SEC);
cudaFree(d_G0);
cudaFree(d_G1);
cudaFree(d_G2);
cudaFree(d_D0);
cudaFree(d_D1);
cudaFree(d_D2);
cudaFree(d_I0);
cudaFree(d_I1);
cudaFree(d_I2);
cudaFree(d_s1);
cudaFree(d_s2);
free(h_s1);
free(h_s2);
free(h_G1);
free(h_G2);
free(h_D1);
free(h_D2);
free(h_I1);
free(h_I2);
*/
return 0;
} | code for sm_80
Function : _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GT.AND P0, PT, R5, c[0x0][0x164], PT ; /* 0x0000590005007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R8, R5, R0, c[0x0][0x190] ; /* 0x0000640005087625 */
/* 0x000fc800078e0200 */
/*0090*/ IMAD.WIDE R6, R5.reuse, R0.reuse, c[0x0][0x168] ; /* 0x00005a0005067625 */
/* 0x0c0fe200078e0200 */
/*00a0*/ LDG.E R2, [R8.64+0x4] ; /* 0x0000040408027981 */
/* 0x000eaa000c1e1900 */
/*00b0*/ LDG.E R7, [R6.64+0x4] ; /* 0x0000040406077981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ IMAD.WIDE R10, R5, R0, c[0x0][0x178] ; /* 0x00005e00050a7625 */
/* 0x000fe200078e0200 */
/*00d0*/ IADD3 R2, R2, c[0x0][0x1b4], RZ ; /* 0x00006d0002027a10 */
/* 0x004fc80007ffe0ff */
/*00e0*/ IMNMX R4, R2, R7, PT ; /* 0x0000000702047217 */
/* 0x008fe20003800200 */
/*00f0*/ IMAD.WIDE R2, R5, R0, c[0x0][0x170] ; /* 0x00005c0005027625 */
/* 0x000fc600078e0200 */
/*0100*/ IADD3 R17, R4, c[0x0][0x1b8], RZ ; /* 0x00006e0004117a10 */
/* 0x000fca0007ffe0ff */
/*0110*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001e8000c101904 */
/*0120*/ LDG.E R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x0002a8000c1e1900 */
/*0130*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ee2000c1e1900 */
/*0140*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff107624 */
/* 0x000fe200078e00ff */
/*0150*/ IADD3 R13, -R5.reuse, c[0x0][0x1b0], RZ ; /* 0x00006c00050d7a10 */
/* 0x040fe20007ffe1ff */
/*0160*/ IMAD.WIDE R6, R5, R0, c[0x0][0x180] ; /* 0x0000600005067625 */
/* 0x000fc600078e0200 */
/*0170*/ IADD3 R16, R16, -c[0x0][0x1b0], RZ ; /* 0x80006c0010107a10 */
/* 0x000fe40007ffe0ff */
/*0180*/ IADD3 R12, P1, R13, c[0x0][0x1a8], RZ ; /* 0x00006a000d0c7a10 */
/* 0x000fc60007f3e0ff */
/*0190*/ IMAD.IADD R15, R5, 0x1, R16 ; /* 0x00000001050f7824 */
/* 0x000fe200078e0210 */
/*01a0*/ LEA.HI.X.SX32 R13, R13, c[0x0][0x1ac], 0x1, P1 ; /* 0x00006b000d0d7a11 */
/* 0x000fe400008f0eff */
/*01b0*/ ISETP.NE.AND P1, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x000fe40003f25270 */
/*01c0*/ IADD3 R14, P0, R15, c[0x0][0x1a0], RZ ; /* 0x000068000f0e7a10 */
/* 0x000fc80007f1e0ff */
/*01d0*/ LEA.HI.X.SX32 R15, R15, c[0x0][0x1a4], 0x1, P0 ; /* 0x000069000f0f7a11 */
/* 0x000fe200000f0eff */
/*01e0*/ IMAD.WIDE R8, R5, R0, c[0x0][0x188] ; /* 0x0000620005087625 */
/* 0x002fe200078e0200 */
/*01f0*/ IADD3 R4, R4, c[0x0][0x1b4], RZ ; /* 0x00006d0004047a10 */
/* 0x004fc80007ffe0ff */
/*0200*/ IMNMX R4, R4, R11, PT ; /* 0x0000000b04047217 */
/* 0x008fc80003800200 */
/*0210*/ IADD3 R17, R4, c[0x0][0x1b8], RZ ; /* 0x00006e0004117a10 */
/* 0x001fca0007ffe0ff */
/*0220*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e8000c101904 */
/*0230*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1100 */
/*0240*/ LDG.E.U8 R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ea8000c1e1100 */
/*0250*/ @P1 LDG.E R11, [R8.64+0x4] ; /* 0x00000404080b1981 */
/* 0x000ee8000c1e1900 */
/*0260*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f22000c1e1900 */
/*0270*/ IMAD.WIDE R4, R5, R0, c[0x0][0x198] ; /* 0x0000660005047625 */
/* 0x000fe200078e0200 */
/*0280*/ ISETP.NE.AND P0, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fc80003f05270 */
/*0290*/ SEL R10, RZ, 0x1, !P0 ; /* 0x00000001ff0a7807 */
/* 0x000fe40004000000 */
/*02a0*/ @P1 IMNMX R16, R17, R2, PT ; /* 0x0000000211101217 */
/* 0x010fc60003800200 */
/*02b0*/ @P1 IMAD.IADD R11, R10, 0x1, R11 ; /* 0x000000010a0b1824 */
/* 0x008fca00078e020b */
/*02c0*/ @P1 IMNMX R11, R11, R16, PT ; /* 0x000000100b0b1217 */
/* 0x000fca0003800200 */
/*02d0*/ @P1 STG.E [R4.64], R11 ; /* 0x0000000b04001986 */
/* 0x0001e2000c101904 */
/*02e0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*02f0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0300*/ IMNMX R3, R17, R2, PT ; /* 0x0000000211037217 */
/* 0x000fe20003800200 */
/*0310*/ IMAD.IADD R10, R10, 0x1, R9 ; /* 0x000000010a0a7824 */
/* 0x004fca00078e0209 */
/*0320*/ IMNMX R3, R10, R3, PT ; /* 0x000000030a037217 */
/* 0x000fca0003800200 */
/*0330*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*0340*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0350*/ BRA 0x350; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.NE.AND P1, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe20003f25270 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.NE.AND P2, PT, R0.reuse, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x040fe20003f45270 */
/*0090*/ BSSY B0, 0x210 ; /* 0x0000017000007945 */
/* 0x000fe20003800000 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fc80003f06270 */
/*00b0*/ ISETP.LT.OR P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fca0000701670 */
/*00c0*/ @!P1 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x1b4] ; /* 0x00006d00ff079624 */
/* 0x000fe200078e00ff */
/*00d0*/ @!P1 MOV R5, c[0x0][0x184] ; /* 0x0000610000059a02 */
/* 0x000fe20000000f00 */
/*00e0*/ @!P1 IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff029624 */
/* 0x000fe400078e00ff */
/*00f0*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x19c] ; /* 0x00006700ff039624 */
/* 0x000fe400078e00ff */
/*0100*/ @!P1 IMAD R7, R7, R2, c[0x0][0x1b0] ; /* 0x00006c0007079624 */
/* 0x000fe400078e0202 */
/*0110*/ @!P1 IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x198] ; /* 0x00006600ff029624 */
/* 0x000fe400078e00ff */
/*0120*/ @!P1 IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff049624 */
/* 0x000fe200078e00ff */
/*0130*/ @!P1 IADD3 R9, R7, c[0x0][0x1b4], RZ ; /* 0x00006d0007099a10 */
/* 0x000fc40007ffe0ff */
/*0140*/ @!P1 STG.E [R2.64], R7 ; /* 0x0000000702009986 */
/* 0x0001e8000c101904 */
/*0150*/ @!P1 STG.E [R4.64], R9 ; /* 0x0000000904009986 */
/* 0x0001e2000c101904 */
/*0160*/ @P2 BRA 0x200 ; /* 0x0000009000002947 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x1b4] ; /* 0x00006d00ff027624 */
/* 0x001fe400078e00ff */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff057624 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe400078e00ff */
/*01a0*/ IMAD R7, R2, R5, c[0x0][0x1b0] ; /* 0x00006c0002077624 */
/* 0x000fc400078e0205 */
/*01b0*/ IMAD.WIDE R2, R5, R4, c[0x0][0x198] ; /* 0x0000660005027625 */
/* 0x000fc600078e0204 */
/*01c0*/ IADD3 R9, R7, c[0x0][0x1b4], RZ ; /* 0x00006d0007097a10 */
/* 0x000fe20007ffe0ff */
/*01d0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x000fe200078e0204 */
/*01e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*01f0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0220*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x001fd400000001ff */
/*0230*/ IMAD.WIDE R8, R0, R5, c[0x0][0x190] ; /* 0x0000640000087625 */
/* 0x000fc800078e0205 */
/*0240*/ IMAD.WIDE R6, R0.reuse, R5, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x040fe200078e0205 */
/*0250*/ LDG.E R2, [R8.64] ; /* 0x0000000408027981 */
/* 0x000eaa000c1e1900 */
/*0260*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee2000c1e1900 */
/*0270*/ IADD3 R16, R0, -0x1, RZ ; /* 0xffffffff00107810 */
/* 0x000fca0007ffe0ff */
/*0280*/ IMAD.WIDE R10, R16, R5, c[0x0][0x178] ; /* 0x00005e00100a7625 */
/* 0x000fe200078e0205 */
/*0290*/ IADD3 R2, R2, c[0x0][0x1b0], RZ ; /* 0x00006c0002027a10 */
/* 0x004fc80007ffe0ff */
/*02a0*/ IMNMX R4, R2, R7, PT ; /* 0x0000000702047217 */
/* 0x008fe20003800200 */
/*02b0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc600078e0205 */
/*02c0*/ IADD3 R17, R4, c[0x0][0x1b4], RZ ; /* 0x00006d0004117a10 */
/* 0x000fca0007ffe0ff */
/*02d0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001e8000c101904 */
/*02e0*/ LDG.E R4, [R8.64+-0x4] ; /* 0xfffffc0408047981 */
/* 0x0002a8000c1e1900 */
/*02f0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ee2000c1e1900 */
/*0300*/ IADD3 R13, -R0.reuse, c[0x0][0x160], RZ ; /* 0x00005800000d7a10 */
/* 0x040fe20007ffe1ff */
/*0310*/ IMAD.WIDE R6, R0.reuse, R5, c[0x0][0x180] ; /* 0x0000600000067625 */
/* 0x040fe200078e0205 */
/*0320*/ IADD3 R14, P0, R0, c[0x0][0x1a0], RZ ; /* 0x00006800000e7a10 */
/* 0x000fc40007f1e0ff */
/*0330*/ IADD3 R12, P1, R13.reuse, c[0x0][0x1a8], RZ ; /* 0x00006a000d0c7a10 */
/* 0x040fe40007f3e0ff */
/*0340*/ LEA.HI.X.SX32 R15, R0, c[0x0][0x1a4], 0x1, P0 ; /* 0x00006900000f7a11 */
/* 0x000fe400000f0eff */
/*0350*/ LEA.HI.X.SX32 R13, R13, c[0x0][0x1ac], 0x1, P1 ; /* 0x00006b000d0d7a11 */
/* 0x000fe200008f0eff */
/*0360*/ IMAD.WIDE R8, R16, R5, c[0x0][0x188] ; /* 0x0000620010087625 */
/* 0x002fe200078e0205 */
/*0370*/ IADD3 R4, R4, c[0x0][0x1b0], RZ ; /* 0x00006c0004047a10 */
/* 0x004fc80007ffe0ff */
/*0380*/ IMNMX R4, R4, R11, PT ; /* 0x0000000b04047217 */
/* 0x008fc80003800200 */
/*0390*/ IADD3 R17, R4, c[0x0][0x1b4], RZ ; /* 0x00006d0004117a10 */
/* 0x001fca0007ffe0ff */
/*03a0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e8000c101904 */
/*03b0*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1100 */
/*03c0*/ LDG.E.U8 R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ea8000c1e1100 */
/*03d0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee8000c1e1900 */
/*03e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f22000c1e1900 */
/*03f0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x198] ; /* 0x0000660000047625 */
/* 0x000fe200078e0205 */
/*0400*/ ISETP.NE.AND P0, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fc40003f05270 */
/*0410*/ IADD3 R11, R8, 0x1, RZ ; /* 0x00000001080b7810 */
/* 0x008fe40007ffe0ff */
/*0420*/ IMNMX R10, R17, R2, PT ; /* 0x00000002110a7217 */
/* 0x010fd20003800200 */
/*0430*/ @!P0 IMAD.MOV R11, RZ, RZ, R8 ; /* 0x000000ffff0b8224 */
/* 0x000fca00078e0208 */
/*0440*/ IMNMX R7, R10, R11, PT ; /* 0x0000000b0a077217 */
/* 0x001fca0003800200 */
/*0450*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0460*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0470*/ BRA 0x470; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
#include <cuda.h>
#include <math.h>
#include<stdio.h>
#include<stdlib.h>
#include <sys/types.h>
#include <time.h>
using namespace std;
__device__ int mymin(int a, int b)
{
int m = a;
if(m > b)
m=b;
return m;
}
__device__ int min1(int a,int b,int c)
{
int m=a;
if(m>b)
m=b;
if(m>c)
m=c;
return m;
}
int min2(int a,int b,int c)
{
int m=a;
if(m>b)
m=b;
if(m>c)
m=c;
return m;
}
void swapDiagnolPointers(int **prev,int **current)
{
int * temp = *prev;
*prev = *current;
*current = temp;
}
void swapDiagnolPointersForG(int **prevprev, int **prev,int **current)
{
int * temp = *prevprev;
*prevprev = *prev;
*prev = *current;
*current = temp;
}
__global__ void less_than_n(int k,int numElements,int * D1,int * D2,int * I1,int * I2,int * G0,int *G1,int * G2,char *s1,char *s2, int gi, int ge)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int s =0;
if( i > numElements ) return ;
if(i == 0)
{
G2[i]=gi+ge*k;
I2[i]=G2[i]+ge;
}
if(i == k)
{
G2[i]=gi+ge*k;
D2[i]=G2[i]+ge;
}
if( i>0 && i<k)
{
D2[i]=min(D1[i],G1[i]+gi)+ge;
I2[i]=min(I1[i-1],G1[i-1]+gi)+ge;
if(s1[i]!=s2[k-i])
s=1;
else
s=0;
G2[i]=min1(D2[i],I2[i],G0[i-1]+s);
}
}
__global__ void greater_than_n(int k,int numElements,int * D1,int * D2,int * I1,int * I2,int * G0,int *G1,int * G2,char *s1,char *s2,int n, int gi, int ge)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int s =0;
if( i > numElements ) return ;
D2[i]=min(D1[i+1],G1[i+1]+gi)+ge;
I2[i]=min(I1[i],G1[i]+gi)+ge;
if(s1[i+(k-n)]!=s2[k-(i+k-n)])
s=1;
else
s=0;
if((k-n)==1)
G2[i]=min1(D2[i],I2[i],G0[i]+s);
else
G2[i]=min1(D2[i],I2[i],G0[i+1]+s);
}
int main(int argc, char** argv)
{
int i,j,n,k,l;
time_t t0, t1;
clock_t c0,c1;
char skip;
scanf("%d",&n);
printf("%d \n",n);
while(1)
{
scanf("%c",&skip);
if(skip == '\n')
break;
}
size_t size = (n+1) * sizeof(char);
size_t size1 = (n+1)*sizeof(int);
char* h_s1 = (char*)malloc(size);
char* h_s2 = (char*)malloc(size);
for(i=1; i<=n; i++)
{
scanf("%c",&h_s1[i]);
}
while(1)
{
scanf("%c",&skip);
if(skip == '\n')
break;
}
for(i=1; i<=n; i++)
{
scanf("%c",&h_s2[i]);
}
/* t0=time(NULL);
c0=clock();
printf ("\tbegin (wall): %ld\n", (long) t0);
printf ("\tbegin (CPU): %d\n", (int) c0);
*/
int* h_D0 = (int*)malloc(size1);
int* h_D1 = (int*)malloc(size1);
int* h_D2 = (int*)malloc(size1);
int* h_G0 = (int*)malloc(size1);
int* h_G1 = (int*)malloc(size1);
int* h_G2 = (int*)malloc(size1);
int* h_I0 = (int*)malloc(size1);
int* h_I1 = (int*)malloc(size1);
int* h_I2 = (int*)malloc(size1);
// int D0[n+1],D1[n+1],D2[n+1],G0[n+1],G1[n+1],G2[n+1],I0[n+1],I1[n+1],I2[n+1]; //--- declaration of functions
int gi,ge,s,cost;
gi=2;ge=1;
int *d_D0, *d_D1, *d_D2;
cudaMalloc(&d_D0, size1);
cudaMalloc(&d_D1, size1);
cudaMalloc(&d_D2, size1);
int *d_G0, *d_G1, *d_G2;
cudaMalloc(&d_G0, size1);
cudaMalloc(&d_G1, size1);
cudaMalloc(&d_G2, size1);
int *d_I0, *d_I1, *d_I2;
cudaMalloc(&d_I0, size1);
cudaMalloc(&d_I1, size1);
cudaMalloc(&d_I2, size1);
char *d_s1, *d_s2;
cudaMalloc(&d_s1, size);
cudaMalloc(&d_s2, size);
cudaMemcpy(d_s1, h_s1, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_s2, h_s2, size, cudaMemcpyHostToDevice);
h_G1[0]=0;
cudaMemcpy(d_G1, h_G1, size1, cudaMemcpyHostToDevice);
int num_threads;
int num_blocks;
int numElements;
for(k=1;k<=2*n;k++)
{
if(k <=n)
{
numElements = k+1;
if( numElements <= 256) {
num_threads = numElements;
num_blocks =1 ;
}
else
{
num_threads = 256 ;
num_blocks = numElements/num_threads + ((numElements/num_threads == 0) ? 0 : 1) ;
}
less_than_n<<<num_blocks,num_threads>>>( k, numElements, d_D1, d_D2, d_I1,d_I2, d_G0, d_G1, d_G2, d_s1, d_s2, gi, ge);
}
if(k > n)
{
numElements = n-(k-n)+1;
if( numElements <= 256) {
num_threads = numElements;
num_blocks =1 ;
}
else
{
num_threads = 256 ;
num_blocks = numElements/num_threads + ((numElements/num_threads == 0) ? 0 : 1) ;
}
greater_than_n<<<num_blocks,num_threads>>>( k, numElements, d_D1, d_D2, d_I1,d_I2, d_G0, d_G1, d_G2, d_s1, d_s2, n, gi, ge);
}
swapDiagnolPointers(&d_D1,&d_D2);
swapDiagnolPointers(&d_I1,&d_I2);
swapDiagnolPointersForG(&d_G0,&d_G1, &d_G2);
}
cudaMemcpy(h_D2, d_D2, size1, cudaMemcpyDeviceToHost);
cudaMemcpy(h_G2, d_G2, size1, cudaMemcpyDeviceToHost);
cudaMemcpy(h_I2, d_I2, size1, cudaMemcpyDeviceToHost);
cudaMemcpy(h_D1, d_D1, size1, cudaMemcpyDeviceToHost);
cudaMemcpy(h_G1, d_G1, size1, cudaMemcpyDeviceToHost);
cudaMemcpy(h_I1, d_I1, size1, cudaMemcpyDeviceToHost);
cost=min2(h_D1[0],h_I1[0],h_G1[0]); //--- allignment cost
cout<<"Optimal Allignment cost: "<<cost<<endl;
/*
t1=time(NULL);
c1=clock();
printf ("\telapsed wall clock time: %ld\n", (long) (t1 - t0));
printf ("\telapsed CPU time: %f\n", (float) (c1 - c0)/CLOCKS_PER_SEC);
cudaFree(d_G0);
cudaFree(d_G1);
cudaFree(d_G2);
cudaFree(d_D0);
cudaFree(d_D1);
cudaFree(d_D2);
cudaFree(d_I0);
cudaFree(d_I1);
cudaFree(d_I2);
cudaFree(d_s1);
cudaFree(d_s2);
free(h_s1);
free(h_s2);
free(h_G1);
free(h_G2);
free(h_D1);
free(h_D2);
free(h_I1);
free(h_I2);
*/
return 0;
} | .file "tmpxft_00175133_00000000-6_diag-new.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3677:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5myminii
.type _Z5myminii, @function
_Z5myminii:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z5myminii, .-_Z5myminii
.globl _Z4min1iii
.type _Z4min1iii, @function
_Z4min1iii:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z4min1iii, .-_Z4min1iii
.globl _Z4min2iii
.type _Z4min2iii, @function
_Z4min2iii:
.LFB3671:
.cfi_startproc
endbr64
cmpl %edx, %esi
cmovg %edx, %esi
cmpl %edi, %esi
movl %edi, %eax
cmovle %esi, %eax
ret
.cfi_endproc
.LFE3671:
.size _Z4min2iii, .-_Z4min2iii
.globl _Z19swapDiagnolPointersPPiS0_
.type _Z19swapDiagnolPointersPPiS0_, @function
_Z19swapDiagnolPointersPPiS0_:
.LFB3672:
.cfi_startproc
endbr64
movq (%rdi), %rax
movq (%rsi), %rdx
movq %rdx, (%rdi)
movq %rax, (%rsi)
ret
.cfi_endproc
.LFE3672:
.size _Z19swapDiagnolPointersPPiS0_, .-_Z19swapDiagnolPointersPPiS0_
.globl _Z23swapDiagnolPointersForGPPiS0_S0_
.type _Z23swapDiagnolPointersForGPPiS0_S0_, @function
_Z23swapDiagnolPointersForGPPiS0_S0_:
.LFB3673:
.cfi_startproc
endbr64
movq (%rdi), %rax
movq (%rsi), %rcx
movq %rcx, (%rdi)
movq (%rdx), %rcx
movq %rcx, (%rsi)
movq %rax, (%rdx)
ret
.cfi_endproc
.LFE3673:
.size _Z23swapDiagnolPointersForGPPiS0_S0_, .-_Z23swapDiagnolPointersForGPPiS0_S0_
.globl _Z52__device_stub__Z11less_than_niiPiS_S_S_S_S_S_PcS0_iiiiPiS_S_S_S_S_S_PcS0_ii
.type _Z52__device_stub__Z11less_than_niiPiS_S_S_S_S_S_PcS0_iiiiPiS_S_S_S_S_S_PcS0_ii, @function
_Z52__device_stub__Z11less_than_niiPiS_S_S_S_S_S_PcS0_iiiiPiS_S_S_S_S_S_PcS0_ii:
.LFB3699:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movl %edi, 76(%rsp)
movl %esi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
movq %r8, 48(%rsp)
movq %r9, 40(%rsp)
movq 272(%rsp), %rax
movq %rax, 32(%rsp)
movq 280(%rsp), %rax
movq %rax, 24(%rsp)
movq 288(%rsp), %rax
movq %rax, 16(%rsp)
movq 296(%rsp), %rax
movq %rax, 8(%rsp)
movq 304(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 8(%rsp), %rax
movq %rax, 216(%rsp)
movq %rsp, %rax
movq %rax, 224(%rsp)
leaq 312(%rsp), %rax
movq %rax, 232(%rsp)
leaq 320(%rsp), %rax
movq %rax, 240(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 280
pushq 88(%rsp)
.cfi_def_cfa_offset 288
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z52__device_stub__Z11less_than_niiPiS_S_S_S_S_S_PcS0_iiiiPiS_S_S_S_S_S_PcS0_ii, .-_Z52__device_stub__Z11less_than_niiPiS_S_S_S_S_S_PcS0_iiiiPiS_S_S_S_S_S_PcS0_ii
.globl _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii
.type _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii, @function
_Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii:
.LFB3700:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 72(%rsp)
.cfi_def_cfa_offset 48
pushq 72(%rsp)
.cfi_def_cfa_offset 56
pushq 72(%rsp)
.cfi_def_cfa_offset 64
pushq 72(%rsp)
.cfi_def_cfa_offset 72
pushq 72(%rsp)
.cfi_def_cfa_offset 80
call _Z52__device_stub__Z11less_than_niiPiS_S_S_S_S_S_PcS0_iiiiPiS_S_S_S_S_S_PcS0_ii
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii, .-_Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii
.globl _Z56__device_stub__Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iiiiiPiS_S_S_S_S_S_PcS0_iii
.type _Z56__device_stub__Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iiiiiPiS_S_S_S_S_S_PcS0_iii, @function
_Z56__device_stub__Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iiiiiPiS_S_S_S_S_S_PcS0_iii:
.LFB3701:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movl %edi, 76(%rsp)
movl %esi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
movq %r8, 48(%rsp)
movq %r9, 40(%rsp)
movq 288(%rsp), %rax
movq %rax, 32(%rsp)
movq 296(%rsp), %rax
movq %rax, 24(%rsp)
movq 304(%rsp), %rax
movq %rax, 16(%rsp)
movq 312(%rsp), %rax
movq %rax, 8(%rsp)
movq 320(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 8(%rsp), %rax
movq %rax, 216(%rsp)
movq %rsp, %rax
movq %rax, 224(%rsp)
leaq 328(%rsp), %rax
movq %rax, 232(%rsp)
leaq 336(%rsp), %rax
movq %rax, 240(%rsp)
leaq 344(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 296
pushq 88(%rsp)
.cfi_def_cfa_offset 304
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z56__device_stub__Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iiiiiPiS_S_S_S_S_S_PcS0_iii, .-_Z56__device_stub__Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iiiiiPiS_S_S_S_S_S_PcS0_iii
.globl _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.type _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii, @function
_Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 72(%rsp)
.cfi_def_cfa_offset 48
pushq 72(%rsp)
.cfi_def_cfa_offset 56
pushq 72(%rsp)
.cfi_def_cfa_offset 64
pushq 72(%rsp)
.cfi_def_cfa_offset 72
pushq 72(%rsp)
.cfi_def_cfa_offset 80
call _Z56__device_stub__Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iiiiiPiS_S_S_S_S_S_PcS0_iii
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii, .-_Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC1:
.string "%d \n"
.LC2:
.string "%c"
.LC3:
.string "Optimal Allignment cost: "
.text
.globl main
.type main, @function
main:
.LFB3674:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $184, %rsp
.cfi_def_cfa_offset 240
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 52(%rsp), %rsi
leaq .LC0(%rip), %rdi
call __isoc23_scanf@PLT
movl 52(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rbx
.L27:
leaq 51(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
cmpb $10, 51(%rsp)
jne .L27
movl 52(%rsp), %ebx
leal 1(%rbx), %r13d
movslq %r13d, %r13
leaq 0(,%r13,4), %rbp
movq %r13, %rdi
call malloc@PLT
movq %rax, %r14
movq %rax, 16(%rsp)
movq %r13, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
testl %ebx, %ebx
jle .L28
leaq 1(%r14), %rax
movq %rax, %rbx
leaq .LC2(%rip), %r15
movl $1, %r12d
subl %eax, %r12d
.L29:
movq %rbx, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addq $1, %rbx
leal (%r12,%rbx), %eax
cmpl %eax, 52(%rsp)
jge .L29
.L28:
leaq .LC2(%rip), %rbx
.L30:
leaq 51(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
cmpb $10, 51(%rsp)
jne .L30
cmpl $0, 52(%rsp)
jle .L31
movq 8(%rsp), %rax
addq $1, %rax
movq %rax, %rbx
leaq .LC2(%rip), %r15
movl $1, %r12d
subl %eax, %r12d
.L32:
movq %rbx, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addq $1, %rbx
leal (%r12,%rbx), %eax
cmpl %eax, 52(%rsp)
jge .L32
.L31:
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbp, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rbp, %rdi
call malloc@PLT
movq %rax, 32(%rsp)
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
call malloc@PLT
movq %rax, 40(%rsp)
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 112(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 128(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 136(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq 16(%rsp), %rsi
movq 128(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq 136(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, (%rbx)
movl $1, %ecx
movq %rbp, %rdx
movq %rbx, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl 52(%rsp), %eax
testl %eax, %eax
jle .L33
movl $1, %r13d
movl $256, %r15d
movq %rbp, 8(%rsp)
jmp .L40
.L42:
movl %ebp, %edx
movl $1, %eax
jmp .L35
.L52:
subq $8, %rsp
.cfi_def_cfa_offset 248
pushq $1
.cfi_def_cfa_offset 256
pushq $2
.cfi_def_cfa_offset 264
pushq 160(%rsp)
.cfi_def_cfa_offset 272
pushq 160(%rsp)
.cfi_def_cfa_offset 280
pushq 136(%rsp)
.cfi_def_cfa_offset 288
pushq 136(%rsp)
.cfi_def_cfa_offset 296
pushq 136(%rsp)
.cfi_def_cfa_offset 304
movq 184(%rsp), %r9
movq 176(%rsp), %r8
movq 136(%rsp), %rcx
movq 128(%rsp), %rdx
movl %ebp, %esi
movl %r13d, %edi
call _Z52__device_stub__Z11less_than_niiPiS_S_S_S_S_S_PcS0_iiiiPiS_S_S_S_S_S_PcS0_ii
addq $64, %rsp
.cfi_def_cfa_offset 240
jmp .L34
.L43:
movl %ebp, %edx
movl $1, %eax
.L38:
movl %edx, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl %eax, 144(%rsp)
movl $1, 148(%rsp)
movl $1, 152(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L37:
movq 64(%rsp), %rax
movq 72(%rsp), %rdx
movq %rdx, 64(%rsp)
movq %rax, 72(%rsp)
movq 112(%rsp), %rax
movq 120(%rsp), %rdx
movq %rdx, 112(%rsp)
movq %rax, 120(%rsp)
movq 80(%rsp), %rax
movq 88(%rsp), %rdx
movq %rdx, 80(%rsp)
movq 96(%rsp), %rdx
movq %rdx, 88(%rsp)
movq %rax, 96(%rsp)
addl $1, %r13d
movl 52(%rsp), %eax
leal (%rax,%rax), %edx
cmpl %r13d, %edx
jl .L51
.L40:
cmpl %r13d, %eax
jl .L34
leal 1(%r13), %ebp
cmpl $256, %ebp
jle .L42
leal 255(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $8, %eax
addl $1, %eax
movl %r15d, %edx
.L35:
movl %edx, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl %eax, 144(%rsp)
movl $1, 148(%rsp)
movl $1, 152(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L34:
movl 52(%rsp), %ebp
cmpl %r13d, %ebp
jge .L37
movl %r13d, %eax
subl %ebp, %eax
subl %eax, %ebp
addl $1, %ebp
cmpl $256, %ebp
jle .L43
leal 255(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $8, %eax
addl $1, %eax
movl %r15d, %edx
jmp .L38
.L50:
pushq $1
.cfi_def_cfa_offset 248
pushq $2
.cfi_def_cfa_offset 256
movl 68(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 264
pushq 160(%rsp)
.cfi_def_cfa_offset 272
pushq 160(%rsp)
.cfi_def_cfa_offset 280
pushq 136(%rsp)
.cfi_def_cfa_offset 288
pushq 136(%rsp)
.cfi_def_cfa_offset 296
pushq 136(%rsp)
.cfi_def_cfa_offset 304
movq 184(%rsp), %r9
movq 176(%rsp), %r8
movq 136(%rsp), %rcx
movq 128(%rsp), %rdx
movl %ebp, %esi
movl %r13d, %edi
call _Z56__device_stub__Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iiiiiPiS_S_S_S_S_S_PcS0_iii
addq $64, %rsp
.cfi_def_cfa_offset 240
jmp .L37
.L51:
movq 8(%rsp), %rbp
.L33:
movl $2, %ecx
movq %rbp, %rdx
movq 72(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 96(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 120(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 64(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 88(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 112(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl (%rbx), %eax
movl (%r12), %edx
cmpl %edx, %eax
cmovg %edx, %eax
movl (%r14), %edx
cmpl %edx, %eax
movl %edx, %ebx
cmovle %eax, %ebx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl $0, %eax
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3674:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "_Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii"
.align 8
.LC5:
.string "_Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3704:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
#include <cuda.h>
#include <math.h>
#include<stdio.h>
#include<stdlib.h>
#include <sys/types.h>
#include <time.h>
using namespace std;
__device__ int mymin(int a, int b)
{
int m = a;
if(m > b)
m=b;
return m;
}
__device__ int min1(int a,int b,int c)
{
int m=a;
if(m>b)
m=b;
if(m>c)
m=c;
return m;
}
int min2(int a,int b,int c)
{
int m=a;
if(m>b)
m=b;
if(m>c)
m=c;
return m;
}
void swapDiagnolPointers(int **prev,int **current)
{
int * temp = *prev;
*prev = *current;
*current = temp;
}
void swapDiagnolPointersForG(int **prevprev, int **prev,int **current)
{
int * temp = *prevprev;
*prevprev = *prev;
*prev = *current;
*current = temp;
}
__global__ void less_than_n(int k,int numElements,int * D1,int * D2,int * I1,int * I2,int * G0,int *G1,int * G2,char *s1,char *s2, int gi, int ge)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int s =0;
if( i > numElements ) return ;
if(i == 0)
{
G2[i]=gi+ge*k;
I2[i]=G2[i]+ge;
}
if(i == k)
{
G2[i]=gi+ge*k;
D2[i]=G2[i]+ge;
}
if( i>0 && i<k)
{
D2[i]=min(D1[i],G1[i]+gi)+ge;
I2[i]=min(I1[i-1],G1[i-1]+gi)+ge;
if(s1[i]!=s2[k-i])
s=1;
else
s=0;
G2[i]=min1(D2[i],I2[i],G0[i-1]+s);
}
}
__global__ void greater_than_n(int k,int numElements,int * D1,int * D2,int * I1,int * I2,int * G0,int *G1,int * G2,char *s1,char *s2,int n, int gi, int ge)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int s =0;
if( i > numElements ) return ;
D2[i]=min(D1[i+1],G1[i+1]+gi)+ge;
I2[i]=min(I1[i],G1[i]+gi)+ge;
if(s1[i+(k-n)]!=s2[k-(i+k-n)])
s=1;
else
s=0;
if((k-n)==1)
G2[i]=min1(D2[i],I2[i],G0[i]+s);
else
G2[i]=min1(D2[i],I2[i],G0[i+1]+s);
}
int main(int argc, char** argv)
{
int i,j,n,k,l;
time_t t0, t1;
clock_t c0,c1;
char skip;
scanf("%d",&n);
printf("%d \n",n);
while(1)
{
scanf("%c",&skip);
if(skip == '\n')
break;
}
size_t size = (n+1) * sizeof(char);
size_t size1 = (n+1)*sizeof(int);
char* h_s1 = (char*)malloc(size);
char* h_s2 = (char*)malloc(size);
for(i=1; i<=n; i++)
{
scanf("%c",&h_s1[i]);
}
while(1)
{
scanf("%c",&skip);
if(skip == '\n')
break;
}
for(i=1; i<=n; i++)
{
scanf("%c",&h_s2[i]);
}
/* t0=time(NULL);
c0=clock();
printf ("\tbegin (wall): %ld\n", (long) t0);
printf ("\tbegin (CPU): %d\n", (int) c0);
*/
int* h_D0 = (int*)malloc(size1);
int* h_D1 = (int*)malloc(size1);
int* h_D2 = (int*)malloc(size1);
int* h_G0 = (int*)malloc(size1);
int* h_G1 = (int*)malloc(size1);
int* h_G2 = (int*)malloc(size1);
int* h_I0 = (int*)malloc(size1);
int* h_I1 = (int*)malloc(size1);
int* h_I2 = (int*)malloc(size1);
// int D0[n+1],D1[n+1],D2[n+1],G0[n+1],G1[n+1],G2[n+1],I0[n+1],I1[n+1],I2[n+1]; //--- declaration of functions
int gi,ge,s,cost;
gi=2;ge=1;
int *d_D0, *d_D1, *d_D2;
cudaMalloc(&d_D0, size1);
cudaMalloc(&d_D1, size1);
cudaMalloc(&d_D2, size1);
int *d_G0, *d_G1, *d_G2;
cudaMalloc(&d_G0, size1);
cudaMalloc(&d_G1, size1);
cudaMalloc(&d_G2, size1);
int *d_I0, *d_I1, *d_I2;
cudaMalloc(&d_I0, size1);
cudaMalloc(&d_I1, size1);
cudaMalloc(&d_I2, size1);
char *d_s1, *d_s2;
cudaMalloc(&d_s1, size);
cudaMalloc(&d_s2, size);
cudaMemcpy(d_s1, h_s1, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_s2, h_s2, size, cudaMemcpyHostToDevice);
h_G1[0]=0;
cudaMemcpy(d_G1, h_G1, size1, cudaMemcpyHostToDevice);
int num_threads;
int num_blocks;
int numElements;
for(k=1;k<=2*n;k++)
{
if(k <=n)
{
numElements = k+1;
if( numElements <= 256) {
num_threads = numElements;
num_blocks =1 ;
}
else
{
num_threads = 256 ;
num_blocks = numElements/num_threads + ((numElements/num_threads == 0) ? 0 : 1) ;
}
less_than_n<<<num_blocks,num_threads>>>( k, numElements, d_D1, d_D2, d_I1,d_I2, d_G0, d_G1, d_G2, d_s1, d_s2, gi, ge);
}
if(k > n)
{
numElements = n-(k-n)+1;
if( numElements <= 256) {
num_threads = numElements;
num_blocks =1 ;
}
else
{
num_threads = 256 ;
num_blocks = numElements/num_threads + ((numElements/num_threads == 0) ? 0 : 1) ;
}
greater_than_n<<<num_blocks,num_threads>>>( k, numElements, d_D1, d_D2, d_I1,d_I2, d_G0, d_G1, d_G2, d_s1, d_s2, n, gi, ge);
}
swapDiagnolPointers(&d_D1,&d_D2);
swapDiagnolPointers(&d_I1,&d_I2);
swapDiagnolPointersForG(&d_G0,&d_G1, &d_G2);
}
cudaMemcpy(h_D2, d_D2, size1, cudaMemcpyDeviceToHost);
cudaMemcpy(h_G2, d_G2, size1, cudaMemcpyDeviceToHost);
cudaMemcpy(h_I2, d_I2, size1, cudaMemcpyDeviceToHost);
cudaMemcpy(h_D1, d_D1, size1, cudaMemcpyDeviceToHost);
cudaMemcpy(h_G1, d_G1, size1, cudaMemcpyDeviceToHost);
cudaMemcpy(h_I1, d_I1, size1, cudaMemcpyDeviceToHost);
cost=min2(h_D1[0],h_I1[0],h_G1[0]); //--- allignment cost
cout<<"Optimal Allignment cost: "<<cost<<endl;
/*
t1=time(NULL);
c1=clock();
printf ("\telapsed wall clock time: %ld\n", (long) (t1 - t0));
printf ("\telapsed CPU time: %f\n", (float) (c1 - c0)/CLOCKS_PER_SEC);
cudaFree(d_G0);
cudaFree(d_G1);
cudaFree(d_G2);
cudaFree(d_D0);
cudaFree(d_D1);
cudaFree(d_D2);
cudaFree(d_I0);
cudaFree(d_I1);
cudaFree(d_I2);
cudaFree(d_s1);
cudaFree(d_s2);
free(h_s1);
free(h_s2);
free(h_G1);
free(h_G2);
free(h_D1);
free(h_D2);
free(h_I1);
free(h_I2);
*/
return 0;
} | #include<iostream>
#include <hip/hip_runtime.h>
#include <math.h>
#include<stdio.h>
#include<stdlib.h>
#include <sys/types.h>
#include <time.h>
using namespace std;
__device__ int mymin(int a, int b)
{
int m = a;
if(m > b)
m=b;
return m;
}
__device__ int min1(int a,int b,int c)
{
int m=a;
if(m>b)
m=b;
if(m>c)
m=c;
return m;
}
int min2(int a,int b,int c)
{
int m=a;
if(m>b)
m=b;
if(m>c)
m=c;
return m;
}
void swapDiagnolPointers(int **prev,int **current)
{
int * temp = *prev;
*prev = *current;
*current = temp;
}
void swapDiagnolPointersForG(int **prevprev, int **prev,int **current)
{
int * temp = *prevprev;
*prevprev = *prev;
*prev = *current;
*current = temp;
}
__global__ void less_than_n(int k,int numElements,int * D1,int * D2,int * I1,int * I2,int * G0,int *G1,int * G2,char *s1,char *s2, int gi, int ge)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int s =0;
if( i > numElements ) return ;
if(i == 0)
{
G2[i]=gi+ge*k;
I2[i]=G2[i]+ge;
}
if(i == k)
{
G2[i]=gi+ge*k;
D2[i]=G2[i]+ge;
}
if( i>0 && i<k)
{
D2[i]=min(D1[i],G1[i]+gi)+ge;
I2[i]=min(I1[i-1],G1[i-1]+gi)+ge;
if(s1[i]!=s2[k-i])
s=1;
else
s=0;
G2[i]=min1(D2[i],I2[i],G0[i-1]+s);
}
}
__global__ void greater_than_n(int k,int numElements,int * D1,int * D2,int * I1,int * I2,int * G0,int *G1,int * G2,char *s1,char *s2,int n, int gi, int ge)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int s =0;
if( i > numElements ) return ;
D2[i]=min(D1[i+1],G1[i+1]+gi)+ge;
I2[i]=min(I1[i],G1[i]+gi)+ge;
if(s1[i+(k-n)]!=s2[k-(i+k-n)])
s=1;
else
s=0;
if((k-n)==1)
G2[i]=min1(D2[i],I2[i],G0[i]+s);
else
G2[i]=min1(D2[i],I2[i],G0[i+1]+s);
}
int main(int argc, char** argv)
{
int i,j,n,k,l;
time_t t0, t1;
clock_t c0,c1;
char skip;
scanf("%d",&n);
printf("%d \n",n);
while(1)
{
scanf("%c",&skip);
if(skip == '\n')
break;
}
size_t size = (n+1) * sizeof(char);
size_t size1 = (n+1)*sizeof(int);
char* h_s1 = (char*)malloc(size);
char* h_s2 = (char*)malloc(size);
for(i=1; i<=n; i++)
{
scanf("%c",&h_s1[i]);
}
while(1)
{
scanf("%c",&skip);
if(skip == '\n')
break;
}
for(i=1; i<=n; i++)
{
scanf("%c",&h_s2[i]);
}
/* t0=time(NULL);
c0=clock();
printf ("\tbegin (wall): %ld\n", (long) t0);
printf ("\tbegin (CPU): %d\n", (int) c0);
*/
int* h_D0 = (int*)malloc(size1);
int* h_D1 = (int*)malloc(size1);
int* h_D2 = (int*)malloc(size1);
int* h_G0 = (int*)malloc(size1);
int* h_G1 = (int*)malloc(size1);
int* h_G2 = (int*)malloc(size1);
int* h_I0 = (int*)malloc(size1);
int* h_I1 = (int*)malloc(size1);
int* h_I2 = (int*)malloc(size1);
// int D0[n+1],D1[n+1],D2[n+1],G0[n+1],G1[n+1],G2[n+1],I0[n+1],I1[n+1],I2[n+1]; //--- declaration of functions
int gi,ge,s,cost;
gi=2;ge=1;
int *d_D0, *d_D1, *d_D2;
hipMalloc(&d_D0, size1);
hipMalloc(&d_D1, size1);
hipMalloc(&d_D2, size1);
int *d_G0, *d_G1, *d_G2;
hipMalloc(&d_G0, size1);
hipMalloc(&d_G1, size1);
hipMalloc(&d_G2, size1);
int *d_I0, *d_I1, *d_I2;
hipMalloc(&d_I0, size1);
hipMalloc(&d_I1, size1);
hipMalloc(&d_I2, size1);
char *d_s1, *d_s2;
hipMalloc(&d_s1, size);
hipMalloc(&d_s2, size);
hipMemcpy(d_s1, h_s1, size, hipMemcpyHostToDevice);
hipMemcpy(d_s2, h_s2, size, hipMemcpyHostToDevice);
h_G1[0]=0;
hipMemcpy(d_G1, h_G1, size1, hipMemcpyHostToDevice);
int num_threads;
int num_blocks;
int numElements;
for(k=1;k<=2*n;k++)
{
if(k <=n)
{
numElements = k+1;
if( numElements <= 256) {
num_threads = numElements;
num_blocks =1 ;
}
else
{
num_threads = 256 ;
num_blocks = numElements/num_threads + ((numElements/num_threads == 0) ? 0 : 1) ;
}
less_than_n<<<num_blocks,num_threads>>>( k, numElements, d_D1, d_D2, d_I1,d_I2, d_G0, d_G1, d_G2, d_s1, d_s2, gi, ge);
}
if(k > n)
{
numElements = n-(k-n)+1;
if( numElements <= 256) {
num_threads = numElements;
num_blocks =1 ;
}
else
{
num_threads = 256 ;
num_blocks = numElements/num_threads + ((numElements/num_threads == 0) ? 0 : 1) ;
}
greater_than_n<<<num_blocks,num_threads>>>( k, numElements, d_D1, d_D2, d_I1,d_I2, d_G0, d_G1, d_G2, d_s1, d_s2, n, gi, ge);
}
swapDiagnolPointers(&d_D1,&d_D2);
swapDiagnolPointers(&d_I1,&d_I2);
swapDiagnolPointersForG(&d_G0,&d_G1, &d_G2);
}
hipMemcpy(h_D2, d_D2, size1, hipMemcpyDeviceToHost);
hipMemcpy(h_G2, d_G2, size1, hipMemcpyDeviceToHost);
hipMemcpy(h_I2, d_I2, size1, hipMemcpyDeviceToHost);
hipMemcpy(h_D1, d_D1, size1, hipMemcpyDeviceToHost);
hipMemcpy(h_G1, d_G1, size1, hipMemcpyDeviceToHost);
hipMemcpy(h_I1, d_I1, size1, hipMemcpyDeviceToHost);
cost=min2(h_D1[0],h_I1[0],h_G1[0]); //--- allignment cost
cout<<"Optimal Allignment cost: "<<cost<<endl;
/*
t1=time(NULL);
c1=clock();
printf ("\telapsed wall clock time: %ld\n", (long) (t1 - t0));
printf ("\telapsed CPU time: %f\n", (float) (c1 - c0)/CLOCKS_PER_SEC);
cudaFree(d_G0);
cudaFree(d_G1);
cudaFree(d_G2);
cudaFree(d_D0);
cudaFree(d_D1);
cudaFree(d_D2);
cudaFree(d_I0);
cudaFree(d_I1);
cudaFree(d_I2);
cudaFree(d_s1);
cudaFree(d_s2);
free(h_s1);
free(h_s2);
free(h_G1);
free(h_G2);
free(h_D1);
free(h_D2);
free(h_I1);
free(h_I2);
*/
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<iostream>
#include <hip/hip_runtime.h>
#include <math.h>
#include<stdio.h>
#include<stdlib.h>
#include <sys/types.h>
#include <time.h>
using namespace std;
__device__ int mymin(int a, int b)
{
int m = a;
if(m > b)
m=b;
return m;
}
__device__ int min1(int a,int b,int c)
{
int m=a;
if(m>b)
m=b;
if(m>c)
m=c;
return m;
}
int min2(int a,int b,int c)
{
int m=a;
if(m>b)
m=b;
if(m>c)
m=c;
return m;
}
void swapDiagnolPointers(int **prev,int **current)
{
int * temp = *prev;
*prev = *current;
*current = temp;
}
void swapDiagnolPointersForG(int **prevprev, int **prev,int **current)
{
int * temp = *prevprev;
*prevprev = *prev;
*prev = *current;
*current = temp;
}
__global__ void less_than_n(int k,int numElements,int * D1,int * D2,int * I1,int * I2,int * G0,int *G1,int * G2,char *s1,char *s2, int gi, int ge)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int s =0;
if( i > numElements ) return ;
if(i == 0)
{
G2[i]=gi+ge*k;
I2[i]=G2[i]+ge;
}
if(i == k)
{
G2[i]=gi+ge*k;
D2[i]=G2[i]+ge;
}
if( i>0 && i<k)
{
D2[i]=min(D1[i],G1[i]+gi)+ge;
I2[i]=min(I1[i-1],G1[i-1]+gi)+ge;
if(s1[i]!=s2[k-i])
s=1;
else
s=0;
G2[i]=min1(D2[i],I2[i],G0[i-1]+s);
}
}
__global__ void greater_than_n(int k,int numElements,int * D1,int * D2,int * I1,int * I2,int * G0,int *G1,int * G2,char *s1,char *s2,int n, int gi, int ge)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int s =0;
if( i > numElements ) return ;
D2[i]=min(D1[i+1],G1[i+1]+gi)+ge;
I2[i]=min(I1[i],G1[i]+gi)+ge;
if(s1[i+(k-n)]!=s2[k-(i+k-n)])
s=1;
else
s=0;
if((k-n)==1)
G2[i]=min1(D2[i],I2[i],G0[i]+s);
else
G2[i]=min1(D2[i],I2[i],G0[i+1]+s);
}
int main(int argc, char** argv)
{
int i,j,n,k,l;
time_t t0, t1;
clock_t c0,c1;
char skip;
scanf("%d",&n);
printf("%d \n",n);
while(1)
{
scanf("%c",&skip);
if(skip == '\n')
break;
}
size_t size = (n+1) * sizeof(char);
size_t size1 = (n+1)*sizeof(int);
char* h_s1 = (char*)malloc(size);
char* h_s2 = (char*)malloc(size);
for(i=1; i<=n; i++)
{
scanf("%c",&h_s1[i]);
}
while(1)
{
scanf("%c",&skip);
if(skip == '\n')
break;
}
for(i=1; i<=n; i++)
{
scanf("%c",&h_s2[i]);
}
/* t0=time(NULL);
c0=clock();
printf ("\tbegin (wall): %ld\n", (long) t0);
printf ("\tbegin (CPU): %d\n", (int) c0);
*/
int* h_D0 = (int*)malloc(size1);
int* h_D1 = (int*)malloc(size1);
int* h_D2 = (int*)malloc(size1);
int* h_G0 = (int*)malloc(size1);
int* h_G1 = (int*)malloc(size1);
int* h_G2 = (int*)malloc(size1);
int* h_I0 = (int*)malloc(size1);
int* h_I1 = (int*)malloc(size1);
int* h_I2 = (int*)malloc(size1);
// int D0[n+1],D1[n+1],D2[n+1],G0[n+1],G1[n+1],G2[n+1],I0[n+1],I1[n+1],I2[n+1]; //--- declaration of functions
int gi,ge,s,cost;
gi=2;ge=1;
int *d_D0, *d_D1, *d_D2;
hipMalloc(&d_D0, size1);
hipMalloc(&d_D1, size1);
hipMalloc(&d_D2, size1);
int *d_G0, *d_G1, *d_G2;
hipMalloc(&d_G0, size1);
hipMalloc(&d_G1, size1);
hipMalloc(&d_G2, size1);
int *d_I0, *d_I1, *d_I2;
hipMalloc(&d_I0, size1);
hipMalloc(&d_I1, size1);
hipMalloc(&d_I2, size1);
char *d_s1, *d_s2;
hipMalloc(&d_s1, size);
hipMalloc(&d_s2, size);
hipMemcpy(d_s1, h_s1, size, hipMemcpyHostToDevice);
hipMemcpy(d_s2, h_s2, size, hipMemcpyHostToDevice);
h_G1[0]=0;
hipMemcpy(d_G1, h_G1, size1, hipMemcpyHostToDevice);
int num_threads;
int num_blocks;
int numElements;
for(k=1;k<=2*n;k++)
{
if(k <=n)
{
numElements = k+1;
if( numElements <= 256) {
num_threads = numElements;
num_blocks =1 ;
}
else
{
num_threads = 256 ;
num_blocks = numElements/num_threads + ((numElements/num_threads == 0) ? 0 : 1) ;
}
less_than_n<<<num_blocks,num_threads>>>( k, numElements, d_D1, d_D2, d_I1,d_I2, d_G0, d_G1, d_G2, d_s1, d_s2, gi, ge);
}
if(k > n)
{
numElements = n-(k-n)+1;
if( numElements <= 256) {
num_threads = numElements;
num_blocks =1 ;
}
else
{
num_threads = 256 ;
num_blocks = numElements/num_threads + ((numElements/num_threads == 0) ? 0 : 1) ;
}
greater_than_n<<<num_blocks,num_threads>>>( k, numElements, d_D1, d_D2, d_I1,d_I2, d_G0, d_G1, d_G2, d_s1, d_s2, n, gi, ge);
}
swapDiagnolPointers(&d_D1,&d_D2);
swapDiagnolPointers(&d_I1,&d_I2);
swapDiagnolPointersForG(&d_G0,&d_G1, &d_G2);
}
hipMemcpy(h_D2, d_D2, size1, hipMemcpyDeviceToHost);
hipMemcpy(h_G2, d_G2, size1, hipMemcpyDeviceToHost);
hipMemcpy(h_I2, d_I2, size1, hipMemcpyDeviceToHost);
hipMemcpy(h_D1, d_D1, size1, hipMemcpyDeviceToHost);
hipMemcpy(h_G1, d_G1, size1, hipMemcpyDeviceToHost);
hipMemcpy(h_I1, d_I1, size1, hipMemcpyDeviceToHost);
cost=min2(h_D1[0],h_I1[0],h_G1[0]); //--- allignment cost
cout<<"Optimal Allignment cost: "<<cost<<endl;
/*
t1=time(NULL);
c1=clock();
printf ("\telapsed wall clock time: %ld\n", (long) (t1 - t0));
printf ("\telapsed CPU time: %f\n", (float) (c1 - c0)/CLOCKS_PER_SEC);
cudaFree(d_G0);
cudaFree(d_G1);
cudaFree(d_G2);
cudaFree(d_D0);
cudaFree(d_D1);
cudaFree(d_D2);
cudaFree(d_I0);
cudaFree(d_I1);
cudaFree(d_I2);
cudaFree(d_s1);
cudaFree(d_s2);
free(h_s1);
free(h_s2);
free(h_G1);
free(h_G2);
free(h_D1);
free(h_D2);
free(h_I1);
free(h_I2);
*/
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii
.globl _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii
.p2align 8
.type _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii,@function
_Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x64
s_load_b32 s3, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ge_i32_e64 s3, v1
s_cbranch_execz .LBB0_7
s_clause 0x3
s_load_b64 s[10:11], s[0:1], 0x50
s_load_b32 s16, s[0:1], 0x0
s_load_b64 s[12:13], s[0:1], 0x20
s_load_b64 s[8:9], s[0:1], 0x38
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s11, s16
v_cmpx_eq_u32_e32 0, v1
s_add_i32 s4, s3, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s4, s11
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, s5
v_mov_b32_e32 v2, s4
s_clause 0x1
global_store_b32 v0, v2, s[8:9]
global_store_b32 v0, v3, s[12:13]
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[14:15], s[0:1], 0x10
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e64 s16, v1
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s3, s3, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
s_add_i32 s4, s3, s11
v_mov_b32_e32 v0, s3
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_mov_b32_e32 v6, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s14, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
global_store_b32 v[4:5], v0, off
global_store_b32 v[2:3], v6, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_lt_i32_e32 vcc_lo, 0, v1
v_cmp_gt_i32_e64 s2, s16, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x28
s_load_b64 s[18:19], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_clause 0x1
s_load_b64 s[20:21], s[0:1], 0x18
s_load_b128 s[0:3], s[0:1], 0x40
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s18, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s19, v4, vcc_lo
global_load_b32 v0, v[5:6], off
global_load_b32 v9, v[7:8], off
v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v5, -1, v1
v_add_co_u32 v7, vcc_lo, s14, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s15, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v0, s10, v0
s_waitcnt vmcnt(0)
v_min_i32_e32 v0, v9, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v6, vcc_lo
v_add_nc_u32_e32 v0, s11, v0
v_add_co_u32 v11, vcc_lo, s20, v5
v_add_co_ci_u32_e32 v12, vcc_lo, s21, v6, vcc_lo
global_store_b32 v[7:8], v0, off
global_load_b32 v0, v[9:10], off
global_load_b32 v2, v[11:12], off
v_sub_nc_u32_e32 v11, s16, v1
v_add_co_u32 v9, vcc_lo, s12, v3
v_add_co_ci_u32_e32 v10, vcc_lo, s13, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
v_add_co_u32 v11, vcc_lo, s2, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v0, s10, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_i32_e32 v0, v2, v0
v_add_nc_u32_e32 v0, s11, v0
global_store_b32 v[9:10], v0, off
global_load_u8 v1, v1, s[0:1]
global_load_u8 v2, v[11:12], off
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[7:8], off
s_waitcnt vmcnt(2)
v_cmp_ne_u16_e32 vcc_lo, v1, v2
s_waitcnt vmcnt(1)
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_min3_i32 v2, v6, v0, v1
v_add_co_u32 v0, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v4, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 344
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii, .Lfunc_end0-_Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.globl _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.p2align 8
.type _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii,@function
_Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x6c
s_load_b32 s3, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ge_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x28
s_load_b256 s[12:19], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s12, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s13, v6, vcc_lo
global_load_b32 v0, v[7:8], off
global_load_b32 v7, v[5:6], off
s_clause 0x1
s_load_b128 s[20:23], s[0:1], 0x48
s_load_b32 s2, s[0:1], 0x58
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_sub_nc_u32_e32 v12, s22, v1
s_sub_i32 s0, s0, s22
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s0, 1
v_add_nc_u32_e32 v13, s0, v1
v_ashrrev_i32_e32 v14, 31, v13
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v0, s23, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_min_i32_e32 v0, v7, v0
v_add_co_u32 v7, vcc_lo, s14, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s15, v6, vcc_lo
v_add_co_u32 v9, vcc_lo, s6, v5
v_add_nc_u32_e32 v0, s2, v0
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v6, vcc_lo
global_store_b32 v[7:8], v0, off
global_load_b32 v0, v[9:10], off
v_add_co_u32 v9, vcc_lo, s16, v5
v_add_co_ci_u32_e32 v10, vcc_lo, s17, v6, vcc_lo
global_load_b32 v11, v[9:10], off
v_add_co_u32 v9, vcc_lo, s18, v5
v_add_co_ci_u32_e32 v10, vcc_lo, s19, v6, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
v_dual_cndmask_b32 v2, v4, v2 :: v_dual_cndmask_b32 v1, v3, v1
v_ashrrev_i32_e32 v4, 31, v12
v_add_co_u32 v3, vcc_lo, s20, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s21, v4, vcc_lo
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v15, s23, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt vmcnt(0)
v_min_i32_e32 v2, v11, v15
v_add_co_u32 v11, vcc_lo, s10, v13
v_add_co_ci_u32_e32 v12, vcc_lo, s11, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v2, s2, v2
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[9:10], v2, off
global_load_u8 v9, v[11:12], off
global_load_u8 v3, v[3:4], off
global_load_b32 v0, v[0:1], off
global_load_b32 v4, v[7:8], off
s_waitcnt vmcnt(2)
v_cmp_ne_u16_e32 vcc_lo, v9, v3
s_waitcnt vmcnt(1)
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v0, vcc_lo
v_add_co_u32 v0, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v6, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_min3_i32 v2, v4, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 352
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii, .Lfunc_end1-_Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .offset: 80
.size: 4
.value_kind: by_value
- .offset: 84
.size: 4
.value_kind: by_value
- .offset: 88
.size: 4
.value_kind: hidden_block_count_x
- .offset: 92
.size: 4
.value_kind: hidden_block_count_y
- .offset: 96
.size: 4
.value_kind: hidden_block_count_z
- .offset: 100
.size: 2
.value_kind: hidden_group_size_x
- .offset: 102
.size: 2
.value_kind: hidden_group_size_y
- .offset: 104
.size: 2
.value_kind: hidden_group_size_z
- .offset: 106
.size: 2
.value_kind: hidden_remainder_x
- .offset: 108
.size: 2
.value_kind: hidden_remainder_y
- .offset: 110
.size: 2
.value_kind: hidden_remainder_z
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 152
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 344
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .offset: 80
.size: 4
.value_kind: by_value
- .offset: 84
.size: 4
.value_kind: by_value
- .offset: 88
.size: 4
.value_kind: by_value
- .offset: 96
.size: 4
.value_kind: hidden_block_count_x
- .offset: 100
.size: 4
.value_kind: hidden_block_count_y
- .offset: 104
.size: 4
.value_kind: hidden_block_count_z
- .offset: 108
.size: 2
.value_kind: hidden_group_size_x
- .offset: 110
.size: 2
.value_kind: hidden_group_size_y
- .offset: 112
.size: 2
.value_kind: hidden_group_size_z
- .offset: 114
.size: 2
.value_kind: hidden_remainder_x
- .offset: 116
.size: 2
.value_kind: hidden_remainder_y
- .offset: 118
.size: 2
.value_kind: hidden_remainder_z
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 152
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 160
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 352
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<iostream>
#include <hip/hip_runtime.h>
#include <math.h>
#include<stdio.h>
#include<stdlib.h>
#include <sys/types.h>
#include <time.h>
using namespace std;
__device__ int mymin(int a, int b)
{
int m = a;
if(m > b)
m=b;
return m;
}
__device__ int min1(int a,int b,int c)
{
int m=a;
if(m>b)
m=b;
if(m>c)
m=c;
return m;
}
int min2(int a,int b,int c)
{
int m=a;
if(m>b)
m=b;
if(m>c)
m=c;
return m;
}
void swapDiagnolPointers(int **prev,int **current)
{
int * temp = *prev;
*prev = *current;
*current = temp;
}
void swapDiagnolPointersForG(int **prevprev, int **prev,int **current)
{
int * temp = *prevprev;
*prevprev = *prev;
*prev = *current;
*current = temp;
}
__global__ void less_than_n(int k,int numElements,int * D1,int * D2,int * I1,int * I2,int * G0,int *G1,int * G2,char *s1,char *s2, int gi, int ge)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int s =0;
if( i > numElements ) return ;
if(i == 0)
{
G2[i]=gi+ge*k;
I2[i]=G2[i]+ge;
}
if(i == k)
{
G2[i]=gi+ge*k;
D2[i]=G2[i]+ge;
}
if( i>0 && i<k)
{
D2[i]=min(D1[i],G1[i]+gi)+ge;
I2[i]=min(I1[i-1],G1[i-1]+gi)+ge;
if(s1[i]!=s2[k-i])
s=1;
else
s=0;
G2[i]=min1(D2[i],I2[i],G0[i-1]+s);
}
}
__global__ void greater_than_n(int k,int numElements,int * D1,int * D2,int * I1,int * I2,int * G0,int *G1,int * G2,char *s1,char *s2,int n, int gi, int ge)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int s =0;
if( i > numElements ) return ;
D2[i]=min(D1[i+1],G1[i+1]+gi)+ge;
I2[i]=min(I1[i],G1[i]+gi)+ge;
if(s1[i+(k-n)]!=s2[k-(i+k-n)])
s=1;
else
s=0;
if((k-n)==1)
G2[i]=min1(D2[i],I2[i],G0[i]+s);
else
G2[i]=min1(D2[i],I2[i],G0[i+1]+s);
}
int main(int argc, char** argv)
{
int i,j,n,k,l;
time_t t0, t1;
clock_t c0,c1;
char skip;
scanf("%d",&n);
printf("%d \n",n);
while(1)
{
scanf("%c",&skip);
if(skip == '\n')
break;
}
size_t size = (n+1) * sizeof(char);
size_t size1 = (n+1)*sizeof(int);
char* h_s1 = (char*)malloc(size);
char* h_s2 = (char*)malloc(size);
for(i=1; i<=n; i++)
{
scanf("%c",&h_s1[i]);
}
while(1)
{
scanf("%c",&skip);
if(skip == '\n')
break;
}
for(i=1; i<=n; i++)
{
scanf("%c",&h_s2[i]);
}
/* t0=time(NULL);
c0=clock();
printf ("\tbegin (wall): %ld\n", (long) t0);
printf ("\tbegin (CPU): %d\n", (int) c0);
*/
int* h_D0 = (int*)malloc(size1);
int* h_D1 = (int*)malloc(size1);
int* h_D2 = (int*)malloc(size1);
int* h_G0 = (int*)malloc(size1);
int* h_G1 = (int*)malloc(size1);
int* h_G2 = (int*)malloc(size1);
int* h_I0 = (int*)malloc(size1);
int* h_I1 = (int*)malloc(size1);
int* h_I2 = (int*)malloc(size1);
// int D0[n+1],D1[n+1],D2[n+1],G0[n+1],G1[n+1],G2[n+1],I0[n+1],I1[n+1],I2[n+1]; //--- declaration of functions
int gi,ge,s,cost;
gi=2;ge=1;
int *d_D0, *d_D1, *d_D2;
hipMalloc(&d_D0, size1);
hipMalloc(&d_D1, size1);
hipMalloc(&d_D2, size1);
int *d_G0, *d_G1, *d_G2;
hipMalloc(&d_G0, size1);
hipMalloc(&d_G1, size1);
hipMalloc(&d_G2, size1);
int *d_I0, *d_I1, *d_I2;
hipMalloc(&d_I0, size1);
hipMalloc(&d_I1, size1);
hipMalloc(&d_I2, size1);
char *d_s1, *d_s2;
hipMalloc(&d_s1, size);
hipMalloc(&d_s2, size);
hipMemcpy(d_s1, h_s1, size, hipMemcpyHostToDevice);
hipMemcpy(d_s2, h_s2, size, hipMemcpyHostToDevice);
h_G1[0]=0;
hipMemcpy(d_G1, h_G1, size1, hipMemcpyHostToDevice);
int num_threads;
int num_blocks;
int numElements;
for(k=1;k<=2*n;k++)
{
if(k <=n)
{
numElements = k+1;
if( numElements <= 256) {
num_threads = numElements;
num_blocks =1 ;
}
else
{
num_threads = 256 ;
num_blocks = numElements/num_threads + ((numElements/num_threads == 0) ? 0 : 1) ;
}
less_than_n<<<num_blocks,num_threads>>>( k, numElements, d_D1, d_D2, d_I1,d_I2, d_G0, d_G1, d_G2, d_s1, d_s2, gi, ge);
}
if(k > n)
{
numElements = n-(k-n)+1;
if( numElements <= 256) {
num_threads = numElements;
num_blocks =1 ;
}
else
{
num_threads = 256 ;
num_blocks = numElements/num_threads + ((numElements/num_threads == 0) ? 0 : 1) ;
}
greater_than_n<<<num_blocks,num_threads>>>( k, numElements, d_D1, d_D2, d_I1,d_I2, d_G0, d_G1, d_G2, d_s1, d_s2, n, gi, ge);
}
swapDiagnolPointers(&d_D1,&d_D2);
swapDiagnolPointers(&d_I1,&d_I2);
swapDiagnolPointersForG(&d_G0,&d_G1, &d_G2);
}
hipMemcpy(h_D2, d_D2, size1, hipMemcpyDeviceToHost);
hipMemcpy(h_G2, d_G2, size1, hipMemcpyDeviceToHost);
hipMemcpy(h_I2, d_I2, size1, hipMemcpyDeviceToHost);
hipMemcpy(h_D1, d_D1, size1, hipMemcpyDeviceToHost);
hipMemcpy(h_G1, d_G1, size1, hipMemcpyDeviceToHost);
hipMemcpy(h_I1, d_I1, size1, hipMemcpyDeviceToHost);
cost=min2(h_D1[0],h_I1[0],h_G1[0]); //--- allignment cost
cout<<"Optimal Allignment cost: "<<cost<<endl;
/*
t1=time(NULL);
c1=clock();
printf ("\telapsed wall clock time: %ld\n", (long) (t1 - t0));
printf ("\telapsed CPU time: %f\n", (float) (c1 - c0)/CLOCKS_PER_SEC);
cudaFree(d_G0);
cudaFree(d_G1);
cudaFree(d_G2);
cudaFree(d_D0);
cudaFree(d_D1);
cudaFree(d_D2);
cudaFree(d_I0);
cudaFree(d_I1);
cudaFree(d_I2);
cudaFree(d_s1);
cudaFree(d_s2);
free(h_s1);
free(h_s2);
free(h_G1);
free(h_G2);
free(h_D1);
free(h_D2);
free(h_I1);
free(h_I2);
*/
return 0;
} | .text
.file "diag-new.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z4min2iii # -- Begin function _Z4min2iii
.p2align 4, 0x90
.type _Z4min2iii,@function
_Z4min2iii: # @_Z4min2iii
.cfi_startproc
# %bb.0:
movl %esi, %eax
cmpl %esi, %edi
cmovll %edi, %eax
cmpl %edx, %eax
cmovgel %edx, %eax
retq
.Lfunc_end0:
.size _Z4min2iii, .Lfunc_end0-_Z4min2iii
.cfi_endproc
# -- End function
.globl _Z19swapDiagnolPointersPPiS0_ # -- Begin function _Z19swapDiagnolPointersPPiS0_
.p2align 4, 0x90
.type _Z19swapDiagnolPointersPPiS0_,@function
_Z19swapDiagnolPointersPPiS0_: # @_Z19swapDiagnolPointersPPiS0_
.cfi_startproc
# %bb.0:
movq (%rdi), %rax
movq (%rsi), %rcx
movq %rcx, (%rdi)
movq %rax, (%rsi)
retq
.Lfunc_end1:
.size _Z19swapDiagnolPointersPPiS0_, .Lfunc_end1-_Z19swapDiagnolPointersPPiS0_
.cfi_endproc
# -- End function
.globl _Z23swapDiagnolPointersForGPPiS0_S0_ # -- Begin function _Z23swapDiagnolPointersForGPPiS0_S0_
.p2align 4, 0x90
.type _Z23swapDiagnolPointersForGPPiS0_S0_,@function
_Z23swapDiagnolPointersForGPPiS0_S0_: # @_Z23swapDiagnolPointersForGPPiS0_S0_
.cfi_startproc
# %bb.0:
movq (%rdi), %rax
movq (%rsi), %rcx
movq %rcx, (%rdi)
movq (%rdx), %rcx
movq %rcx, (%rsi)
movq %rax, (%rdx)
retq
.Lfunc_end2:
.size _Z23swapDiagnolPointersForGPPiS0_S0_, .Lfunc_end2-_Z23swapDiagnolPointersForGPPiS0_S0_
.cfi_endproc
# -- End function
.globl _Z26__device_stub__less_than_niiPiS_S_S_S_S_S_PcS0_ii # -- Begin function _Z26__device_stub__less_than_niiPiS_S_S_S_S_S_PcS0_ii
.p2align 4, 0x90
.type _Z26__device_stub__less_than_niiPiS_S_S_S_S_S_PcS0_ii,@function
_Z26__device_stub__less_than_niiPiS_S_S_S_S_S_PcS0_ii: # @_Z26__device_stub__less_than_niiPiS_S_S_S_S_S_PcS0_ii
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end3:
.size _Z26__device_stub__less_than_niiPiS_S_S_S_S_S_PcS0_ii, .Lfunc_end3-_Z26__device_stub__less_than_niiPiS_S_S_S_S_S_PcS0_ii
.cfi_endproc
# -- End function
.globl _Z29__device_stub__greater_than_niiPiS_S_S_S_S_S_PcS0_iii # -- Begin function _Z29__device_stub__greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.p2align 4, 0x90
.type _Z29__device_stub__greater_than_niiPiS_S_S_S_S_S_PcS0_iii,@function
_Z29__device_stub__greater_than_niiPiS_S_S_S_S_S_PcS0_iii: # @_Z29__device_stub__greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end4:
.size _Z29__device_stub__greater_than_niiPiS_S_S_S_S_S_PcS0_iii, .Lfunc_end4-_Z29__device_stub__greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $408, %rsp # imm = 0x198
.cfi_def_cfa_offset 464
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 4(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
leaq 3(%rsp), %rbx
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
cmpb $10, 3(%rsp)
jne .LBB5_1
# %bb.2:
movslq 4(%rsp), %rbx
leaq 1(%rbx), %r14
movq %r14, %rdi
callq malloc
movq %rax, %r12
movq %r14, %rdi
callq malloc
movq %rax, %r15
testq %rbx, %rbx
jle .LBB5_5
# %bb.3: # %.lr.ph.preheader
leaq 1(%r12), %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB5_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r13, %rsi
addq %rbp, %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 4(%rsp), %rax
incq %rbp
cmpq %rax, %rbp
jl .LBB5_4
.LBB5_5: # %.preheader118.preheader
leaq 4(,%rbx,4), %rbx
leaq 3(%rsp), %r13
.p2align 4, 0x90
.LBB5_6: # %.preheader118
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
cmpb $10, 3(%rsp)
jne .LBB5_6
# %bb.7: # %.preheader
cmpl $0, 4(%rsp)
jle .LBB5_10
# %bb.8: # %.lr.ph123.preheader
movq %r15, %r13
incq %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB5_9: # %.lr.ph123
# =>This Inner Loop Header: Depth=1
movq %r13, %rsi
addq %rbp, %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 4(%rsp), %rax
incq %rbp
cmpq %rax, %rbp
jl .LBB5_9
.LBB5_10: # %._crit_edge
movq %rbx, %rdi
callq malloc
movq %rax, 384(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 360(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, %r13
movq %rbx, %rdi
callq malloc
movq %rax, 352(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 368(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 344(%rsp) # 8-byte Spill
leaq 400(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 64(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 72(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 392(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 88(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 80(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 88(%rsp), %rdi
movl $1, %ebp
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 80(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $0, (%r13)
movq 24(%rsp), %rdi
movq %r13, 376(%rsp) # 8-byte Spill
movq %r13, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB5_19
# %bb.11: # %.lr.ph127
xorl %r15d, %r15d
movl $-1, %r13d
movabsq $4294967296, %r14 # imm = 0x100000000
jmp .LBB5_12
.p2align 4, 0x90
.LBB5_18: # in Loop: Header=BB5_12 Depth=1
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq %rcx, 64(%rsp)
movq %rax, 56(%rsp)
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq %rcx, 40(%rsp)
movq %rax, 32(%rsp)
movq 72(%rsp), %rax
movq 24(%rsp), %rcx
movq %rcx, 72(%rsp)
movq 48(%rsp), %rcx
movq %rcx, 24(%rsp)
movq %rax, 48(%rsp)
movl 4(%rsp), %eax
leal (%rax,%rax), %ecx
decl %r13d
cmpl %ecx, %r15d
jge .LBB5_19
.LBB5_12: # =>This Inner Loop Header: Depth=1
movl %r15d, %r12d
leal 1(%r12), %r15d
cmpl %eax, %r15d
jg .LBB5_15
# %bb.13: # in Loop: Header=BB5_12 Depth=1
addl $2, %r12d
movl %r12d, %edi
shrl $8, %edi
incl %edi
cmpl $256, %r15d # imm = 0x100
cmovbl %ebp, %edi
movl $256, %edx # imm = 0x100
cmovbl %r12d, %edx
orq %r14, %rdi
orq %r14, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_15
# %bb.14: # in Loop: Header=BB5_12 Depth=1
movl %r12d, 16(%rsp)
movq 64(%rsp), %rax
movq %rax, 208(%rsp)
movq 56(%rsp), %rax
movq %rax, 200(%rsp)
movq 40(%rsp), %rax
movq %rax, 192(%rsp)
movq 32(%rsp), %rax
movq %rax, 184(%rsp)
movq 72(%rsp), %rax
movq %rax, 176(%rsp)
movq 24(%rsp), %rax
movq %rax, 168(%rsp)
movq 48(%rsp), %rax
movq %rax, 160(%rsp)
movq 88(%rsp), %rax
movq %rax, 152(%rsp)
movq 80(%rsp), %rax
movq %rax, 144(%rsp)
movl %r15d, 20(%rsp)
movl $2, 12(%rsp)
movl $1, 8(%rsp)
leaq 20(%rsp), %rax
movq %rax, 224(%rsp)
leaq 16(%rsp), %rax
movq %rax, 232(%rsp)
leaq 208(%rsp), %rax
movq %rax, 240(%rsp)
leaq 200(%rsp), %rax
movq %rax, 248(%rsp)
leaq 192(%rsp), %rax
movq %rax, 256(%rsp)
leaq 184(%rsp), %rax
movq %rax, 264(%rsp)
leaq 176(%rsp), %rax
movq %rax, 272(%rsp)
leaq 168(%rsp), %rax
movq %rax, 280(%rsp)
leaq 160(%rsp), %rax
movq %rax, 288(%rsp)
leaq 152(%rsp), %rax
movq %rax, 296(%rsp)
leaq 144(%rsp), %rax
movq %rax, 304(%rsp)
leaq 12(%rsp), %rax
movq %rax, 312(%rsp)
leaq 8(%rsp), %rax
movq %rax, 320(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movl $_Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii, %edi
leaq 224(%rsp), %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.p2align 4, 0x90
.LBB5_15: # in Loop: Header=BB5_12 Depth=1
movl 4(%rsp), %eax
cmpl %eax, %r15d
jle .LBB5_18
# %bb.16: # in Loop: Header=BB5_12 Depth=1
leal (%r13,%rax,2), %ecx
leal 1(%r13,%rax,2), %r12d
movl %r12d, %edi
shrl $8, %edi
incl %edi
cmpl $256, %ecx # imm = 0x100
cmovll %ebp, %edi
movl $256, %edx # imm = 0x100
cmovll %r12d, %edx
orq %r14, %rdi
orq %r14, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_18
# %bb.17: # in Loop: Header=BB5_12 Depth=1
movl %r12d, 16(%rsp)
movq 64(%rsp), %rax
movq %rax, 208(%rsp)
movq 56(%rsp), %rax
movq %rax, 200(%rsp)
movq 40(%rsp), %rax
movq %rax, 192(%rsp)
movq 32(%rsp), %rax
movq %rax, 184(%rsp)
movq 72(%rsp), %rax
movq %rax, 176(%rsp)
movq 24(%rsp), %rax
movq %rax, 168(%rsp)
movq 48(%rsp), %rax
movq %rax, 160(%rsp)
movq 88(%rsp), %rax
movq %rax, 152(%rsp)
movq 80(%rsp), %rax
movq %rax, 144(%rsp)
movl 4(%rsp), %eax
movl %eax, 12(%rsp)
movl %r15d, 20(%rsp)
movl $2, 8(%rsp)
movl $1, 220(%rsp)
leaq 20(%rsp), %rax
movq %rax, 224(%rsp)
leaq 16(%rsp), %rax
movq %rax, 232(%rsp)
leaq 208(%rsp), %rax
movq %rax, 240(%rsp)
leaq 200(%rsp), %rax
movq %rax, 248(%rsp)
leaq 192(%rsp), %rax
movq %rax, 256(%rsp)
leaq 184(%rsp), %rax
movq %rax, 264(%rsp)
leaq 176(%rsp), %rax
movq %rax, 272(%rsp)
leaq 168(%rsp), %rax
movq %rax, 280(%rsp)
leaq 160(%rsp), %rax
movq %rax, 288(%rsp)
leaq 152(%rsp), %rax
movq %rax, 296(%rsp)
leaq 144(%rsp), %rax
movq %rax, 304(%rsp)
leaq 12(%rsp), %rax
movq %rax, 312(%rsp)
leaq 8(%rsp), %rax
movq %rax, 320(%rsp)
leaq 220(%rsp), %rax
movq %rax, 328(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movl $_Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii, %edi
leaq 224(%rsp), %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_18
.LBB5_19: # %._crit_edge128
movq 56(%rsp), %rsi
movq 360(%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rsi
movq 352(%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rsi
movq 344(%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 64(%rsp), %rsi
movq 384(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movq 376(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rsi
movq 368(%rsp), %r12 # 8-byte Reload
movq %r12, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movl (%r14), %eax
movl (%r12), %ebx
cmpl %ebx, %eax
cmovll %eax, %ebx
movl (%r15), %eax
cmpl %eax, %ebx
cmovgel %eax, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB5_24
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB5_22
# %bb.21:
movzbl 67(%rbx), %ecx
jmp .LBB5_23
.LBB5_22:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB5_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $408, %rsp # imm = 0x198
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_24:
.cfi_def_cfa_offset 464
callq _ZSt16__throw_bad_castv
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii,@object # @_Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii
.section .rodata,"a",@progbits
.globl _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii
.p2align 3, 0x0
_Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii:
.quad _Z26__device_stub__less_than_niiPiS_S_S_S_S_S_PcS0_ii
.size _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii, 8
.type _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii,@object # @_Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.globl _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.p2align 3, 0x0
_Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii:
.quad _Z29__device_stub__greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.size _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d \n"
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%c"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Optimal Allignment cost: "
.size .L.str.3, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii"
.size .L__unnamed_1, 39
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii"
.size .L__unnamed_2, 43
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__less_than_niiPiS_S_S_S_S_S_PcS0_ii
.addrsig_sym _Z29__device_stub__greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii
.addrsig_sym _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GT.AND P0, PT, R5, c[0x0][0x164], PT ; /* 0x0000590005007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R8, R5, R0, c[0x0][0x190] ; /* 0x0000640005087625 */
/* 0x000fc800078e0200 */
/*0090*/ IMAD.WIDE R6, R5.reuse, R0.reuse, c[0x0][0x168] ; /* 0x00005a0005067625 */
/* 0x0c0fe200078e0200 */
/*00a0*/ LDG.E R2, [R8.64+0x4] ; /* 0x0000040408027981 */
/* 0x000eaa000c1e1900 */
/*00b0*/ LDG.E R7, [R6.64+0x4] ; /* 0x0000040406077981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ IMAD.WIDE R10, R5, R0, c[0x0][0x178] ; /* 0x00005e00050a7625 */
/* 0x000fe200078e0200 */
/*00d0*/ IADD3 R2, R2, c[0x0][0x1b4], RZ ; /* 0x00006d0002027a10 */
/* 0x004fc80007ffe0ff */
/*00e0*/ IMNMX R4, R2, R7, PT ; /* 0x0000000702047217 */
/* 0x008fe20003800200 */
/*00f0*/ IMAD.WIDE R2, R5, R0, c[0x0][0x170] ; /* 0x00005c0005027625 */
/* 0x000fc600078e0200 */
/*0100*/ IADD3 R17, R4, c[0x0][0x1b8], RZ ; /* 0x00006e0004117a10 */
/* 0x000fca0007ffe0ff */
/*0110*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001e8000c101904 */
/*0120*/ LDG.E R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x0002a8000c1e1900 */
/*0130*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ee2000c1e1900 */
/*0140*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff107624 */
/* 0x000fe200078e00ff */
/*0150*/ IADD3 R13, -R5.reuse, c[0x0][0x1b0], RZ ; /* 0x00006c00050d7a10 */
/* 0x040fe20007ffe1ff */
/*0160*/ IMAD.WIDE R6, R5, R0, c[0x0][0x180] ; /* 0x0000600005067625 */
/* 0x000fc600078e0200 */
/*0170*/ IADD3 R16, R16, -c[0x0][0x1b0], RZ ; /* 0x80006c0010107a10 */
/* 0x000fe40007ffe0ff */
/*0180*/ IADD3 R12, P1, R13, c[0x0][0x1a8], RZ ; /* 0x00006a000d0c7a10 */
/* 0x000fc60007f3e0ff */
/*0190*/ IMAD.IADD R15, R5, 0x1, R16 ; /* 0x00000001050f7824 */
/* 0x000fe200078e0210 */
/*01a0*/ LEA.HI.X.SX32 R13, R13, c[0x0][0x1ac], 0x1, P1 ; /* 0x00006b000d0d7a11 */
/* 0x000fe400008f0eff */
/*01b0*/ ISETP.NE.AND P1, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x000fe40003f25270 */
/*01c0*/ IADD3 R14, P0, R15, c[0x0][0x1a0], RZ ; /* 0x000068000f0e7a10 */
/* 0x000fc80007f1e0ff */
/*01d0*/ LEA.HI.X.SX32 R15, R15, c[0x0][0x1a4], 0x1, P0 ; /* 0x000069000f0f7a11 */
/* 0x000fe200000f0eff */
/*01e0*/ IMAD.WIDE R8, R5, R0, c[0x0][0x188] ; /* 0x0000620005087625 */
/* 0x002fe200078e0200 */
/*01f0*/ IADD3 R4, R4, c[0x0][0x1b4], RZ ; /* 0x00006d0004047a10 */
/* 0x004fc80007ffe0ff */
/*0200*/ IMNMX R4, R4, R11, PT ; /* 0x0000000b04047217 */
/* 0x008fc80003800200 */
/*0210*/ IADD3 R17, R4, c[0x0][0x1b8], RZ ; /* 0x00006e0004117a10 */
/* 0x001fca0007ffe0ff */
/*0220*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e8000c101904 */
/*0230*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1100 */
/*0240*/ LDG.E.U8 R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ea8000c1e1100 */
/*0250*/ @P1 LDG.E R11, [R8.64+0x4] ; /* 0x00000404080b1981 */
/* 0x000ee8000c1e1900 */
/*0260*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f22000c1e1900 */
/*0270*/ IMAD.WIDE R4, R5, R0, c[0x0][0x198] ; /* 0x0000660005047625 */
/* 0x000fe200078e0200 */
/*0280*/ ISETP.NE.AND P0, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fc80003f05270 */
/*0290*/ SEL R10, RZ, 0x1, !P0 ; /* 0x00000001ff0a7807 */
/* 0x000fe40004000000 */
/*02a0*/ @P1 IMNMX R16, R17, R2, PT ; /* 0x0000000211101217 */
/* 0x010fc60003800200 */
/*02b0*/ @P1 IMAD.IADD R11, R10, 0x1, R11 ; /* 0x000000010a0b1824 */
/* 0x008fca00078e020b */
/*02c0*/ @P1 IMNMX R11, R11, R16, PT ; /* 0x000000100b0b1217 */
/* 0x000fca0003800200 */
/*02d0*/ @P1 STG.E [R4.64], R11 ; /* 0x0000000b04001986 */
/* 0x0001e2000c101904 */
/*02e0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*02f0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0300*/ IMNMX R3, R17, R2, PT ; /* 0x0000000211037217 */
/* 0x000fe20003800200 */
/*0310*/ IMAD.IADD R10, R10, 0x1, R9 ; /* 0x000000010a0a7824 */
/* 0x004fca00078e0209 */
/*0320*/ IMNMX R3, R10, R3, PT ; /* 0x000000030a037217 */
/* 0x000fca0003800200 */
/*0330*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*0340*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0350*/ BRA 0x350; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.NE.AND P1, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe20003f25270 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.NE.AND P2, PT, R0.reuse, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x040fe20003f45270 */
/*0090*/ BSSY B0, 0x210 ; /* 0x0000017000007945 */
/* 0x000fe20003800000 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fc80003f06270 */
/*00b0*/ ISETP.LT.OR P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fca0000701670 */
/*00c0*/ @!P1 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x1b4] ; /* 0x00006d00ff079624 */
/* 0x000fe200078e00ff */
/*00d0*/ @!P1 MOV R5, c[0x0][0x184] ; /* 0x0000610000059a02 */
/* 0x000fe20000000f00 */
/*00e0*/ @!P1 IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff029624 */
/* 0x000fe400078e00ff */
/*00f0*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x19c] ; /* 0x00006700ff039624 */
/* 0x000fe400078e00ff */
/*0100*/ @!P1 IMAD R7, R7, R2, c[0x0][0x1b0] ; /* 0x00006c0007079624 */
/* 0x000fe400078e0202 */
/*0110*/ @!P1 IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x198] ; /* 0x00006600ff029624 */
/* 0x000fe400078e00ff */
/*0120*/ @!P1 IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff049624 */
/* 0x000fe200078e00ff */
/*0130*/ @!P1 IADD3 R9, R7, c[0x0][0x1b4], RZ ; /* 0x00006d0007099a10 */
/* 0x000fc40007ffe0ff */
/*0140*/ @!P1 STG.E [R2.64], R7 ; /* 0x0000000702009986 */
/* 0x0001e8000c101904 */
/*0150*/ @!P1 STG.E [R4.64], R9 ; /* 0x0000000904009986 */
/* 0x0001e2000c101904 */
/*0160*/ @P2 BRA 0x200 ; /* 0x0000009000002947 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x1b4] ; /* 0x00006d00ff027624 */
/* 0x001fe400078e00ff */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff057624 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe400078e00ff */
/*01a0*/ IMAD R7, R2, R5, c[0x0][0x1b0] ; /* 0x00006c0002077624 */
/* 0x000fc400078e0205 */
/*01b0*/ IMAD.WIDE R2, R5, R4, c[0x0][0x198] ; /* 0x0000660005027625 */
/* 0x000fc600078e0204 */
/*01c0*/ IADD3 R9, R7, c[0x0][0x1b4], RZ ; /* 0x00006d0007097a10 */
/* 0x000fe20007ffe0ff */
/*01d0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x000fe200078e0204 */
/*01e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*01f0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0220*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x001fd400000001ff */
/*0230*/ IMAD.WIDE R8, R0, R5, c[0x0][0x190] ; /* 0x0000640000087625 */
/* 0x000fc800078e0205 */
/*0240*/ IMAD.WIDE R6, R0.reuse, R5, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x040fe200078e0205 */
/*0250*/ LDG.E R2, [R8.64] ; /* 0x0000000408027981 */
/* 0x000eaa000c1e1900 */
/*0260*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee2000c1e1900 */
/*0270*/ IADD3 R16, R0, -0x1, RZ ; /* 0xffffffff00107810 */
/* 0x000fca0007ffe0ff */
/*0280*/ IMAD.WIDE R10, R16, R5, c[0x0][0x178] ; /* 0x00005e00100a7625 */
/* 0x000fe200078e0205 */
/*0290*/ IADD3 R2, R2, c[0x0][0x1b0], RZ ; /* 0x00006c0002027a10 */
/* 0x004fc80007ffe0ff */
/*02a0*/ IMNMX R4, R2, R7, PT ; /* 0x0000000702047217 */
/* 0x008fe20003800200 */
/*02b0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc600078e0205 */
/*02c0*/ IADD3 R17, R4, c[0x0][0x1b4], RZ ; /* 0x00006d0004117a10 */
/* 0x000fca0007ffe0ff */
/*02d0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001e8000c101904 */
/*02e0*/ LDG.E R4, [R8.64+-0x4] ; /* 0xfffffc0408047981 */
/* 0x0002a8000c1e1900 */
/*02f0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ee2000c1e1900 */
/*0300*/ IADD3 R13, -R0.reuse, c[0x0][0x160], RZ ; /* 0x00005800000d7a10 */
/* 0x040fe20007ffe1ff */
/*0310*/ IMAD.WIDE R6, R0.reuse, R5, c[0x0][0x180] ; /* 0x0000600000067625 */
/* 0x040fe200078e0205 */
/*0320*/ IADD3 R14, P0, R0, c[0x0][0x1a0], RZ ; /* 0x00006800000e7a10 */
/* 0x000fc40007f1e0ff */
/*0330*/ IADD3 R12, P1, R13.reuse, c[0x0][0x1a8], RZ ; /* 0x00006a000d0c7a10 */
/* 0x040fe40007f3e0ff */
/*0340*/ LEA.HI.X.SX32 R15, R0, c[0x0][0x1a4], 0x1, P0 ; /* 0x00006900000f7a11 */
/* 0x000fe400000f0eff */
/*0350*/ LEA.HI.X.SX32 R13, R13, c[0x0][0x1ac], 0x1, P1 ; /* 0x00006b000d0d7a11 */
/* 0x000fe200008f0eff */
/*0360*/ IMAD.WIDE R8, R16, R5, c[0x0][0x188] ; /* 0x0000620010087625 */
/* 0x002fe200078e0205 */
/*0370*/ IADD3 R4, R4, c[0x0][0x1b0], RZ ; /* 0x00006c0004047a10 */
/* 0x004fc80007ffe0ff */
/*0380*/ IMNMX R4, R4, R11, PT ; /* 0x0000000b04047217 */
/* 0x008fc80003800200 */
/*0390*/ IADD3 R17, R4, c[0x0][0x1b4], RZ ; /* 0x00006d0004117a10 */
/* 0x001fca0007ffe0ff */
/*03a0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e8000c101904 */
/*03b0*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1100 */
/*03c0*/ LDG.E.U8 R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ea8000c1e1100 */
/*03d0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee8000c1e1900 */
/*03e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f22000c1e1900 */
/*03f0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x198] ; /* 0x0000660000047625 */
/* 0x000fe200078e0205 */
/*0400*/ ISETP.NE.AND P0, PT, R15, R12, PT ; /* 0x0000000c0f00720c */
/* 0x004fc40003f05270 */
/*0410*/ IADD3 R11, R8, 0x1, RZ ; /* 0x00000001080b7810 */
/* 0x008fe40007ffe0ff */
/*0420*/ IMNMX R10, R17, R2, PT ; /* 0x00000002110a7217 */
/* 0x010fd20003800200 */
/*0430*/ @!P0 IMAD.MOV R11, RZ, RZ, R8 ; /* 0x000000ffff0b8224 */
/* 0x000fca00078e0208 */
/*0440*/ IMNMX R7, R10, R11, PT ; /* 0x0000000b0a077217 */
/* 0x001fca0003800200 */
/*0450*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0460*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0470*/ BRA 0x470; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii
.globl _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii
.p2align 8
.type _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii,@function
_Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x64
s_load_b32 s3, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ge_i32_e64 s3, v1
s_cbranch_execz .LBB0_7
s_clause 0x3
s_load_b64 s[10:11], s[0:1], 0x50
s_load_b32 s16, s[0:1], 0x0
s_load_b64 s[12:13], s[0:1], 0x20
s_load_b64 s[8:9], s[0:1], 0x38
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s11, s16
v_cmpx_eq_u32_e32 0, v1
s_add_i32 s4, s3, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s4, s11
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, s5
v_mov_b32_e32 v2, s4
s_clause 0x1
global_store_b32 v0, v2, s[8:9]
global_store_b32 v0, v3, s[12:13]
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[14:15], s[0:1], 0x10
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e64 s16, v1
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s3, s3, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
s_add_i32 s4, s3, s11
v_mov_b32_e32 v0, s3
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_mov_b32_e32 v6, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s14, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
global_store_b32 v[4:5], v0, off
global_store_b32 v[2:3], v6, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_lt_i32_e32 vcc_lo, 0, v1
v_cmp_gt_i32_e64 s2, s16, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x28
s_load_b64 s[18:19], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_clause 0x1
s_load_b64 s[20:21], s[0:1], 0x18
s_load_b128 s[0:3], s[0:1], 0x40
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s18, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s19, v4, vcc_lo
global_load_b32 v0, v[5:6], off
global_load_b32 v9, v[7:8], off
v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v5, -1, v1
v_add_co_u32 v7, vcc_lo, s14, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s15, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v0, s10, v0
s_waitcnt vmcnt(0)
v_min_i32_e32 v0, v9, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v6, vcc_lo
v_add_nc_u32_e32 v0, s11, v0
v_add_co_u32 v11, vcc_lo, s20, v5
v_add_co_ci_u32_e32 v12, vcc_lo, s21, v6, vcc_lo
global_store_b32 v[7:8], v0, off
global_load_b32 v0, v[9:10], off
global_load_b32 v2, v[11:12], off
v_sub_nc_u32_e32 v11, s16, v1
v_add_co_u32 v9, vcc_lo, s12, v3
v_add_co_ci_u32_e32 v10, vcc_lo, s13, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
v_add_co_u32 v11, vcc_lo, s2, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v0, s10, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_i32_e32 v0, v2, v0
v_add_nc_u32_e32 v0, s11, v0
global_store_b32 v[9:10], v0, off
global_load_u8 v1, v1, s[0:1]
global_load_u8 v2, v[11:12], off
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[7:8], off
s_waitcnt vmcnt(2)
v_cmp_ne_u16_e32 vcc_lo, v1, v2
s_waitcnt vmcnt(1)
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_min3_i32 v2, v6, v0, v1
v_add_co_u32 v0, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v4, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 344
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii, .Lfunc_end0-_Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.globl _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.p2align 8
.type _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii,@function
_Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x6c
s_load_b32 s3, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ge_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x28
s_load_b256 s[12:19], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s12, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s13, v6, vcc_lo
global_load_b32 v0, v[7:8], off
global_load_b32 v7, v[5:6], off
s_clause 0x1
s_load_b128 s[20:23], s[0:1], 0x48
s_load_b32 s2, s[0:1], 0x58
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_sub_nc_u32_e32 v12, s22, v1
s_sub_i32 s0, s0, s22
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s0, 1
v_add_nc_u32_e32 v13, s0, v1
v_ashrrev_i32_e32 v14, 31, v13
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v0, s23, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_min_i32_e32 v0, v7, v0
v_add_co_u32 v7, vcc_lo, s14, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s15, v6, vcc_lo
v_add_co_u32 v9, vcc_lo, s6, v5
v_add_nc_u32_e32 v0, s2, v0
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v6, vcc_lo
global_store_b32 v[7:8], v0, off
global_load_b32 v0, v[9:10], off
v_add_co_u32 v9, vcc_lo, s16, v5
v_add_co_ci_u32_e32 v10, vcc_lo, s17, v6, vcc_lo
global_load_b32 v11, v[9:10], off
v_add_co_u32 v9, vcc_lo, s18, v5
v_add_co_ci_u32_e32 v10, vcc_lo, s19, v6, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
v_dual_cndmask_b32 v2, v4, v2 :: v_dual_cndmask_b32 v1, v3, v1
v_ashrrev_i32_e32 v4, 31, v12
v_add_co_u32 v3, vcc_lo, s20, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s21, v4, vcc_lo
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v15, s23, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt vmcnt(0)
v_min_i32_e32 v2, v11, v15
v_add_co_u32 v11, vcc_lo, s10, v13
v_add_co_ci_u32_e32 v12, vcc_lo, s11, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v2, s2, v2
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[9:10], v2, off
global_load_u8 v9, v[11:12], off
global_load_u8 v3, v[3:4], off
global_load_b32 v0, v[0:1], off
global_load_b32 v4, v[7:8], off
s_waitcnt vmcnt(2)
v_cmp_ne_u16_e32 vcc_lo, v9, v3
s_waitcnt vmcnt(1)
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v0, vcc_lo
v_add_co_u32 v0, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v6, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_min3_i32 v2, v4, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 352
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii, .Lfunc_end1-_Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .offset: 80
.size: 4
.value_kind: by_value
- .offset: 84
.size: 4
.value_kind: by_value
- .offset: 88
.size: 4
.value_kind: hidden_block_count_x
- .offset: 92
.size: 4
.value_kind: hidden_block_count_y
- .offset: 96
.size: 4
.value_kind: hidden_block_count_z
- .offset: 100
.size: 2
.value_kind: hidden_group_size_x
- .offset: 102
.size: 2
.value_kind: hidden_group_size_y
- .offset: 104
.size: 2
.value_kind: hidden_group_size_z
- .offset: 106
.size: 2
.value_kind: hidden_remainder_x
- .offset: 108
.size: 2
.value_kind: hidden_remainder_y
- .offset: 110
.size: 2
.value_kind: hidden_remainder_z
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 152
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 344
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .offset: 80
.size: 4
.value_kind: by_value
- .offset: 84
.size: 4
.value_kind: by_value
- .offset: 88
.size: 4
.value_kind: by_value
- .offset: 96
.size: 4
.value_kind: hidden_block_count_x
- .offset: 100
.size: 4
.value_kind: hidden_block_count_y
- .offset: 104
.size: 4
.value_kind: hidden_block_count_z
- .offset: 108
.size: 2
.value_kind: hidden_group_size_x
- .offset: 110
.size: 2
.value_kind: hidden_group_size_y
- .offset: 112
.size: 2
.value_kind: hidden_group_size_z
- .offset: 114
.size: 2
.value_kind: hidden_remainder_x
- .offset: 116
.size: 2
.value_kind: hidden_remainder_y
- .offset: 118
.size: 2
.value_kind: hidden_remainder_z
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 152
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 160
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 352
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00175133_00000000-6_diag-new.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3677:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5myminii
.type _Z5myminii, @function
_Z5myminii:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z5myminii, .-_Z5myminii
.globl _Z4min1iii
.type _Z4min1iii, @function
_Z4min1iii:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z4min1iii, .-_Z4min1iii
.globl _Z4min2iii
.type _Z4min2iii, @function
_Z4min2iii:
.LFB3671:
.cfi_startproc
endbr64
cmpl %edx, %esi
cmovg %edx, %esi
cmpl %edi, %esi
movl %edi, %eax
cmovle %esi, %eax
ret
.cfi_endproc
.LFE3671:
.size _Z4min2iii, .-_Z4min2iii
.globl _Z19swapDiagnolPointersPPiS0_
.type _Z19swapDiagnolPointersPPiS0_, @function
_Z19swapDiagnolPointersPPiS0_:
.LFB3672:
.cfi_startproc
endbr64
movq (%rdi), %rax
movq (%rsi), %rdx
movq %rdx, (%rdi)
movq %rax, (%rsi)
ret
.cfi_endproc
.LFE3672:
.size _Z19swapDiagnolPointersPPiS0_, .-_Z19swapDiagnolPointersPPiS0_
.globl _Z23swapDiagnolPointersForGPPiS0_S0_
.type _Z23swapDiagnolPointersForGPPiS0_S0_, @function
_Z23swapDiagnolPointersForGPPiS0_S0_:
.LFB3673:
.cfi_startproc
endbr64
movq (%rdi), %rax
movq (%rsi), %rcx
movq %rcx, (%rdi)
movq (%rdx), %rcx
movq %rcx, (%rsi)
movq %rax, (%rdx)
ret
.cfi_endproc
.LFE3673:
.size _Z23swapDiagnolPointersForGPPiS0_S0_, .-_Z23swapDiagnolPointersForGPPiS0_S0_
.globl _Z52__device_stub__Z11less_than_niiPiS_S_S_S_S_S_PcS0_iiiiPiS_S_S_S_S_S_PcS0_ii
.type _Z52__device_stub__Z11less_than_niiPiS_S_S_S_S_S_PcS0_iiiiPiS_S_S_S_S_S_PcS0_ii, @function
_Z52__device_stub__Z11less_than_niiPiS_S_S_S_S_S_PcS0_iiiiPiS_S_S_S_S_S_PcS0_ii:
.LFB3699:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movl %edi, 76(%rsp)
movl %esi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
movq %r8, 48(%rsp)
movq %r9, 40(%rsp)
movq 272(%rsp), %rax
movq %rax, 32(%rsp)
movq 280(%rsp), %rax
movq %rax, 24(%rsp)
movq 288(%rsp), %rax
movq %rax, 16(%rsp)
movq 296(%rsp), %rax
movq %rax, 8(%rsp)
movq 304(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 8(%rsp), %rax
movq %rax, 216(%rsp)
movq %rsp, %rax
movq %rax, 224(%rsp)
leaq 312(%rsp), %rax
movq %rax, 232(%rsp)
leaq 320(%rsp), %rax
movq %rax, 240(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 280
pushq 88(%rsp)
.cfi_def_cfa_offset 288
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z52__device_stub__Z11less_than_niiPiS_S_S_S_S_S_PcS0_iiiiPiS_S_S_S_S_S_PcS0_ii, .-_Z52__device_stub__Z11less_than_niiPiS_S_S_S_S_S_PcS0_iiiiPiS_S_S_S_S_S_PcS0_ii
.globl _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii
.type _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii, @function
_Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii:
.LFB3700:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 72(%rsp)
.cfi_def_cfa_offset 48
pushq 72(%rsp)
.cfi_def_cfa_offset 56
pushq 72(%rsp)
.cfi_def_cfa_offset 64
pushq 72(%rsp)
.cfi_def_cfa_offset 72
pushq 72(%rsp)
.cfi_def_cfa_offset 80
call _Z52__device_stub__Z11less_than_niiPiS_S_S_S_S_S_PcS0_iiiiPiS_S_S_S_S_S_PcS0_ii
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii, .-_Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii
.globl _Z56__device_stub__Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iiiiiPiS_S_S_S_S_S_PcS0_iii
.type _Z56__device_stub__Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iiiiiPiS_S_S_S_S_S_PcS0_iii, @function
_Z56__device_stub__Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iiiiiPiS_S_S_S_S_S_PcS0_iii:
.LFB3701:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movl %edi, 76(%rsp)
movl %esi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
movq %r8, 48(%rsp)
movq %r9, 40(%rsp)
movq 288(%rsp), %rax
movq %rax, 32(%rsp)
movq 296(%rsp), %rax
movq %rax, 24(%rsp)
movq 304(%rsp), %rax
movq %rax, 16(%rsp)
movq 312(%rsp), %rax
movq %rax, 8(%rsp)
movq 320(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 8(%rsp), %rax
movq %rax, 216(%rsp)
movq %rsp, %rax
movq %rax, 224(%rsp)
leaq 328(%rsp), %rax
movq %rax, 232(%rsp)
leaq 336(%rsp), %rax
movq %rax, 240(%rsp)
leaq 344(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 296
pushq 88(%rsp)
.cfi_def_cfa_offset 304
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z56__device_stub__Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iiiiiPiS_S_S_S_S_S_PcS0_iii, .-_Z56__device_stub__Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iiiiiPiS_S_S_S_S_S_PcS0_iii
.globl _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.type _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii, @function
_Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 72(%rsp)
.cfi_def_cfa_offset 48
pushq 72(%rsp)
.cfi_def_cfa_offset 56
pushq 72(%rsp)
.cfi_def_cfa_offset 64
pushq 72(%rsp)
.cfi_def_cfa_offset 72
pushq 72(%rsp)
.cfi_def_cfa_offset 80
call _Z56__device_stub__Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iiiiiPiS_S_S_S_S_S_PcS0_iii
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii, .-_Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC1:
.string "%d \n"
.LC2:
.string "%c"
.LC3:
.string "Optimal Allignment cost: "
.text
.globl main
.type main, @function
main:
.LFB3674:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $184, %rsp
.cfi_def_cfa_offset 240
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 52(%rsp), %rsi
leaq .LC0(%rip), %rdi
call __isoc23_scanf@PLT
movl 52(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rbx
.L27:
leaq 51(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
cmpb $10, 51(%rsp)
jne .L27
movl 52(%rsp), %ebx
leal 1(%rbx), %r13d
movslq %r13d, %r13
leaq 0(,%r13,4), %rbp
movq %r13, %rdi
call malloc@PLT
movq %rax, %r14
movq %rax, 16(%rsp)
movq %r13, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
testl %ebx, %ebx
jle .L28
leaq 1(%r14), %rax
movq %rax, %rbx
leaq .LC2(%rip), %r15
movl $1, %r12d
subl %eax, %r12d
.L29:
movq %rbx, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addq $1, %rbx
leal (%r12,%rbx), %eax
cmpl %eax, 52(%rsp)
jge .L29
.L28:
leaq .LC2(%rip), %rbx
.L30:
leaq 51(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
cmpb $10, 51(%rsp)
jne .L30
cmpl $0, 52(%rsp)
jle .L31
movq 8(%rsp), %rax
addq $1, %rax
movq %rax, %rbx
leaq .LC2(%rip), %r15
movl $1, %r12d
subl %eax, %r12d
.L32:
movq %rbx, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addq $1, %rbx
leal (%r12,%rbx), %eax
cmpl %eax, 52(%rsp)
jge .L32
.L31:
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbp, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rbp, %rdi
call malloc@PLT
movq %rax, 32(%rsp)
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
call malloc@PLT
movq %rax, 40(%rsp)
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 112(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 128(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 136(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq 16(%rsp), %rsi
movq 128(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq 136(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, (%rbx)
movl $1, %ecx
movq %rbp, %rdx
movq %rbx, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl 52(%rsp), %eax
testl %eax, %eax
jle .L33
movl $1, %r13d
movl $256, %r15d
movq %rbp, 8(%rsp)
jmp .L40
.L42:
movl %ebp, %edx
movl $1, %eax
jmp .L35
.L52:
subq $8, %rsp
.cfi_def_cfa_offset 248
pushq $1
.cfi_def_cfa_offset 256
pushq $2
.cfi_def_cfa_offset 264
pushq 160(%rsp)
.cfi_def_cfa_offset 272
pushq 160(%rsp)
.cfi_def_cfa_offset 280
pushq 136(%rsp)
.cfi_def_cfa_offset 288
pushq 136(%rsp)
.cfi_def_cfa_offset 296
pushq 136(%rsp)
.cfi_def_cfa_offset 304
movq 184(%rsp), %r9
movq 176(%rsp), %r8
movq 136(%rsp), %rcx
movq 128(%rsp), %rdx
movl %ebp, %esi
movl %r13d, %edi
call _Z52__device_stub__Z11less_than_niiPiS_S_S_S_S_S_PcS0_iiiiPiS_S_S_S_S_S_PcS0_ii
addq $64, %rsp
.cfi_def_cfa_offset 240
jmp .L34
.L43:
movl %ebp, %edx
movl $1, %eax
.L38:
movl %edx, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl %eax, 144(%rsp)
movl $1, 148(%rsp)
movl $1, 152(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L37:
movq 64(%rsp), %rax
movq 72(%rsp), %rdx
movq %rdx, 64(%rsp)
movq %rax, 72(%rsp)
movq 112(%rsp), %rax
movq 120(%rsp), %rdx
movq %rdx, 112(%rsp)
movq %rax, 120(%rsp)
movq 80(%rsp), %rax
movq 88(%rsp), %rdx
movq %rdx, 80(%rsp)
movq 96(%rsp), %rdx
movq %rdx, 88(%rsp)
movq %rax, 96(%rsp)
addl $1, %r13d
movl 52(%rsp), %eax
leal (%rax,%rax), %edx
cmpl %r13d, %edx
jl .L51
.L40:
cmpl %r13d, %eax
jl .L34
leal 1(%r13), %ebp
cmpl $256, %ebp
jle .L42
leal 255(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $8, %eax
addl $1, %eax
movl %r15d, %edx
.L35:
movl %edx, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl %eax, 144(%rsp)
movl $1, 148(%rsp)
movl $1, 152(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 156(%rsp), %rdx
movl $1, %ecx
movq 144(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L34:
movl 52(%rsp), %ebp
cmpl %r13d, %ebp
jge .L37
movl %r13d, %eax
subl %ebp, %eax
subl %eax, %ebp
addl $1, %ebp
cmpl $256, %ebp
jle .L43
leal 255(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $8, %eax
addl $1, %eax
movl %r15d, %edx
jmp .L38
.L50:
pushq $1
.cfi_def_cfa_offset 248
pushq $2
.cfi_def_cfa_offset 256
movl 68(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 264
pushq 160(%rsp)
.cfi_def_cfa_offset 272
pushq 160(%rsp)
.cfi_def_cfa_offset 280
pushq 136(%rsp)
.cfi_def_cfa_offset 288
pushq 136(%rsp)
.cfi_def_cfa_offset 296
pushq 136(%rsp)
.cfi_def_cfa_offset 304
movq 184(%rsp), %r9
movq 176(%rsp), %r8
movq 136(%rsp), %rcx
movq 128(%rsp), %rdx
movl %ebp, %esi
movl %r13d, %edi
call _Z56__device_stub__Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iiiiiPiS_S_S_S_S_S_PcS0_iii
addq $64, %rsp
.cfi_def_cfa_offset 240
jmp .L37
.L51:
movq 8(%rsp), %rbp
.L33:
movl $2, %ecx
movq %rbp, %rdx
movq 72(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 96(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 120(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 64(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 88(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 112(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl (%rbx), %eax
movl (%r12), %edx
cmpl %edx, %eax
cmovg %edx, %eax
movl (%r14), %edx
cmpl %edx, %eax
movl %edx, %ebx
cmovle %eax, %ebx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl $0, %eax
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3674:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "_Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii"
.align 8
.LC5:
.string "_Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3704:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "diag-new.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z4min2iii # -- Begin function _Z4min2iii
.p2align 4, 0x90
.type _Z4min2iii,@function
_Z4min2iii: # @_Z4min2iii
.cfi_startproc
# %bb.0:
movl %esi, %eax
cmpl %esi, %edi
cmovll %edi, %eax
cmpl %edx, %eax
cmovgel %edx, %eax
retq
.Lfunc_end0:
.size _Z4min2iii, .Lfunc_end0-_Z4min2iii
.cfi_endproc
# -- End function
.globl _Z19swapDiagnolPointersPPiS0_ # -- Begin function _Z19swapDiagnolPointersPPiS0_
.p2align 4, 0x90
.type _Z19swapDiagnolPointersPPiS0_,@function
_Z19swapDiagnolPointersPPiS0_: # @_Z19swapDiagnolPointersPPiS0_
.cfi_startproc
# %bb.0:
movq (%rdi), %rax
movq (%rsi), %rcx
movq %rcx, (%rdi)
movq %rax, (%rsi)
retq
.Lfunc_end1:
.size _Z19swapDiagnolPointersPPiS0_, .Lfunc_end1-_Z19swapDiagnolPointersPPiS0_
.cfi_endproc
# -- End function
.globl _Z23swapDiagnolPointersForGPPiS0_S0_ # -- Begin function _Z23swapDiagnolPointersForGPPiS0_S0_
.p2align 4, 0x90
.type _Z23swapDiagnolPointersForGPPiS0_S0_,@function
_Z23swapDiagnolPointersForGPPiS0_S0_: # @_Z23swapDiagnolPointersForGPPiS0_S0_
.cfi_startproc
# %bb.0:
movq (%rdi), %rax
movq (%rsi), %rcx
movq %rcx, (%rdi)
movq (%rdx), %rcx
movq %rcx, (%rsi)
movq %rax, (%rdx)
retq
.Lfunc_end2:
.size _Z23swapDiagnolPointersForGPPiS0_S0_, .Lfunc_end2-_Z23swapDiagnolPointersForGPPiS0_S0_
.cfi_endproc
# -- End function
.globl _Z26__device_stub__less_than_niiPiS_S_S_S_S_S_PcS0_ii # -- Begin function _Z26__device_stub__less_than_niiPiS_S_S_S_S_S_PcS0_ii
.p2align 4, 0x90
.type _Z26__device_stub__less_than_niiPiS_S_S_S_S_S_PcS0_ii,@function
_Z26__device_stub__less_than_niiPiS_S_S_S_S_S_PcS0_ii: # @_Z26__device_stub__less_than_niiPiS_S_S_S_S_S_PcS0_ii
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end3:
.size _Z26__device_stub__less_than_niiPiS_S_S_S_S_S_PcS0_ii, .Lfunc_end3-_Z26__device_stub__less_than_niiPiS_S_S_S_S_S_PcS0_ii
.cfi_endproc
# -- End function
.globl _Z29__device_stub__greater_than_niiPiS_S_S_S_S_S_PcS0_iii # -- Begin function _Z29__device_stub__greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.p2align 4, 0x90
.type _Z29__device_stub__greater_than_niiPiS_S_S_S_S_S_PcS0_iii,@function
_Z29__device_stub__greater_than_niiPiS_S_S_S_S_S_PcS0_iii: # @_Z29__device_stub__greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end4:
.size _Z29__device_stub__greater_than_niiPiS_S_S_S_S_S_PcS0_iii, .Lfunc_end4-_Z29__device_stub__greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $408, %rsp # imm = 0x198
.cfi_def_cfa_offset 464
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 4(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
leaq 3(%rsp), %rbx
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
cmpb $10, 3(%rsp)
jne .LBB5_1
# %bb.2:
movslq 4(%rsp), %rbx
leaq 1(%rbx), %r14
movq %r14, %rdi
callq malloc
movq %rax, %r12
movq %r14, %rdi
callq malloc
movq %rax, %r15
testq %rbx, %rbx
jle .LBB5_5
# %bb.3: # %.lr.ph.preheader
leaq 1(%r12), %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB5_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r13, %rsi
addq %rbp, %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 4(%rsp), %rax
incq %rbp
cmpq %rax, %rbp
jl .LBB5_4
.LBB5_5: # %.preheader118.preheader
leaq 4(,%rbx,4), %rbx
leaq 3(%rsp), %r13
.p2align 4, 0x90
.LBB5_6: # %.preheader118
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %edi
movq %r13, %rsi
xorl %eax, %eax
callq __isoc23_scanf
cmpb $10, 3(%rsp)
jne .LBB5_6
# %bb.7: # %.preheader
cmpl $0, 4(%rsp)
jle .LBB5_10
# %bb.8: # %.lr.ph123.preheader
movq %r15, %r13
incq %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB5_9: # %.lr.ph123
# =>This Inner Loop Header: Depth=1
movq %r13, %rsi
addq %rbp, %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 4(%rsp), %rax
incq %rbp
cmpq %rax, %rbp
jl .LBB5_9
.LBB5_10: # %._crit_edge
movq %rbx, %rdi
callq malloc
movq %rax, 384(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 360(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, %r13
movq %rbx, %rdi
callq malloc
movq %rax, 352(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 368(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 344(%rsp) # 8-byte Spill
leaq 400(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 64(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 72(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 392(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 88(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 80(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 88(%rsp), %rdi
movl $1, %ebp
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 80(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $0, (%r13)
movq 24(%rsp), %rdi
movq %r13, 376(%rsp) # 8-byte Spill
movq %r13, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB5_19
# %bb.11: # %.lr.ph127
xorl %r15d, %r15d
movl $-1, %r13d
movabsq $4294967296, %r14 # imm = 0x100000000
jmp .LBB5_12
.p2align 4, 0x90
.LBB5_18: # in Loop: Header=BB5_12 Depth=1
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq %rcx, 64(%rsp)
movq %rax, 56(%rsp)
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq %rcx, 40(%rsp)
movq %rax, 32(%rsp)
movq 72(%rsp), %rax
movq 24(%rsp), %rcx
movq %rcx, 72(%rsp)
movq 48(%rsp), %rcx
movq %rcx, 24(%rsp)
movq %rax, 48(%rsp)
movl 4(%rsp), %eax
leal (%rax,%rax), %ecx
decl %r13d
cmpl %ecx, %r15d
jge .LBB5_19
.LBB5_12: # =>This Inner Loop Header: Depth=1
movl %r15d, %r12d
leal 1(%r12), %r15d
cmpl %eax, %r15d
jg .LBB5_15
# %bb.13: # in Loop: Header=BB5_12 Depth=1
addl $2, %r12d
movl %r12d, %edi
shrl $8, %edi
incl %edi
cmpl $256, %r15d # imm = 0x100
cmovbl %ebp, %edi
movl $256, %edx # imm = 0x100
cmovbl %r12d, %edx
orq %r14, %rdi
orq %r14, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_15
# %bb.14: # in Loop: Header=BB5_12 Depth=1
movl %r12d, 16(%rsp)
movq 64(%rsp), %rax
movq %rax, 208(%rsp)
movq 56(%rsp), %rax
movq %rax, 200(%rsp)
movq 40(%rsp), %rax
movq %rax, 192(%rsp)
movq 32(%rsp), %rax
movq %rax, 184(%rsp)
movq 72(%rsp), %rax
movq %rax, 176(%rsp)
movq 24(%rsp), %rax
movq %rax, 168(%rsp)
movq 48(%rsp), %rax
movq %rax, 160(%rsp)
movq 88(%rsp), %rax
movq %rax, 152(%rsp)
movq 80(%rsp), %rax
movq %rax, 144(%rsp)
movl %r15d, 20(%rsp)
movl $2, 12(%rsp)
movl $1, 8(%rsp)
leaq 20(%rsp), %rax
movq %rax, 224(%rsp)
leaq 16(%rsp), %rax
movq %rax, 232(%rsp)
leaq 208(%rsp), %rax
movq %rax, 240(%rsp)
leaq 200(%rsp), %rax
movq %rax, 248(%rsp)
leaq 192(%rsp), %rax
movq %rax, 256(%rsp)
leaq 184(%rsp), %rax
movq %rax, 264(%rsp)
leaq 176(%rsp), %rax
movq %rax, 272(%rsp)
leaq 168(%rsp), %rax
movq %rax, 280(%rsp)
leaq 160(%rsp), %rax
movq %rax, 288(%rsp)
leaq 152(%rsp), %rax
movq %rax, 296(%rsp)
leaq 144(%rsp), %rax
movq %rax, 304(%rsp)
leaq 12(%rsp), %rax
movq %rax, 312(%rsp)
leaq 8(%rsp), %rax
movq %rax, 320(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movl $_Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii, %edi
leaq 224(%rsp), %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.p2align 4, 0x90
.LBB5_15: # in Loop: Header=BB5_12 Depth=1
movl 4(%rsp), %eax
cmpl %eax, %r15d
jle .LBB5_18
# %bb.16: # in Loop: Header=BB5_12 Depth=1
leal (%r13,%rax,2), %ecx
leal 1(%r13,%rax,2), %r12d
movl %r12d, %edi
shrl $8, %edi
incl %edi
cmpl $256, %ecx # imm = 0x100
cmovll %ebp, %edi
movl $256, %edx # imm = 0x100
cmovll %r12d, %edx
orq %r14, %rdi
orq %r14, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_18
# %bb.17: # in Loop: Header=BB5_12 Depth=1
movl %r12d, 16(%rsp)
movq 64(%rsp), %rax
movq %rax, 208(%rsp)
movq 56(%rsp), %rax
movq %rax, 200(%rsp)
movq 40(%rsp), %rax
movq %rax, 192(%rsp)
movq 32(%rsp), %rax
movq %rax, 184(%rsp)
movq 72(%rsp), %rax
movq %rax, 176(%rsp)
movq 24(%rsp), %rax
movq %rax, 168(%rsp)
movq 48(%rsp), %rax
movq %rax, 160(%rsp)
movq 88(%rsp), %rax
movq %rax, 152(%rsp)
movq 80(%rsp), %rax
movq %rax, 144(%rsp)
movl 4(%rsp), %eax
movl %eax, 12(%rsp)
movl %r15d, 20(%rsp)
movl $2, 8(%rsp)
movl $1, 220(%rsp)
leaq 20(%rsp), %rax
movq %rax, 224(%rsp)
leaq 16(%rsp), %rax
movq %rax, 232(%rsp)
leaq 208(%rsp), %rax
movq %rax, 240(%rsp)
leaq 200(%rsp), %rax
movq %rax, 248(%rsp)
leaq 192(%rsp), %rax
movq %rax, 256(%rsp)
leaq 184(%rsp), %rax
movq %rax, 264(%rsp)
leaq 176(%rsp), %rax
movq %rax, 272(%rsp)
leaq 168(%rsp), %rax
movq %rax, 280(%rsp)
leaq 160(%rsp), %rax
movq %rax, 288(%rsp)
leaq 152(%rsp), %rax
movq %rax, 296(%rsp)
leaq 144(%rsp), %rax
movq %rax, 304(%rsp)
leaq 12(%rsp), %rax
movq %rax, 312(%rsp)
leaq 8(%rsp), %rax
movq %rax, 320(%rsp)
leaq 220(%rsp), %rax
movq %rax, 328(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movl $_Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii, %edi
leaq 224(%rsp), %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_18
.LBB5_19: # %._crit_edge128
movq 56(%rsp), %rsi
movq 360(%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rsi
movq 352(%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rsi
movq 344(%rsp), %rdi # 8-byte Reload
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 64(%rsp), %rsi
movq 384(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movq 376(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rsi
movq 368(%rsp), %r12 # 8-byte Reload
movq %r12, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movl (%r14), %eax
movl (%r12), %ebx
cmpl %ebx, %eax
cmovll %eax, %ebx
movl (%r15), %eax
cmpl %eax, %ebx
cmovgel %eax, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB5_24
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB5_22
# %bb.21:
movzbl 67(%rbx), %ecx
jmp .LBB5_23
.LBB5_22:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB5_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $408, %rsp # imm = 0x198
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_24:
.cfi_def_cfa_offset 464
callq _ZSt16__throw_bad_castv
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii,@object # @_Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii
.section .rodata,"a",@progbits
.globl _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii
.p2align 3, 0x0
_Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii:
.quad _Z26__device_stub__less_than_niiPiS_S_S_S_S_S_PcS0_ii
.size _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii, 8
.type _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii,@object # @_Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.globl _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.p2align 3, 0x0
_Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii:
.quad _Z29__device_stub__greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.size _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d \n"
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%c"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Optimal Allignment cost: "
.size .L.str.3, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii"
.size .L__unnamed_1, 39
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii"
.size .L__unnamed_2, 43
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__less_than_niiPiS_S_S_S_S_S_PcS0_ii
.addrsig_sym _Z29__device_stub__greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11less_than_niiPiS_S_S_S_S_S_PcS0_ii
.addrsig_sym _Z14greater_than_niiPiS_S_S_S_S_S_PcS0_iii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
typedef short WORD;
typedef int DWORD;
typedef int LONG;
#pragma pack(push, 1)
typedef struct tagBITMAPFILEHEADER
{
WORD bfType; //specifies the file type
DWORD bfSize; //specifies the size in bytes of the bitmap file
WORD bfReserved1; //reserved; must be 0
WORD bfReserved2; //reserved; must be 0
DWORD bOffBits; //species the offset in bytes from the bitmapfileheader to the bitmap bits
}BITMAPFILEHEADER;
#pragma pack(pop)
#pragma pack(push, 1)
typedef struct tagBITMAPINFOHEADER
{
DWORD biSize; //specifies the number of bytes required by the struct
LONG biWidth; //specifies width in pixels
LONG biHeight; //species height in pixels
WORD biPlanes; //specifies the number of color planes, must be 1
WORD biBitCount; //specifies the number of bit per pixel
DWORD biCompression;//spcifies the type of compression
DWORD biSizeImage; //size of image in bytes
LONG biXPelsPerMeter; //number of pixels per meter in x axis
LONG biYPelsPerMeter; //number of pixels per meter in y axis
DWORD biClrUsed; //number of colors used by th ebitmap
DWORD biClrImportant; //number of colors that are important
}BITMAPINFOHEADER;
#pragma pack(pop)
__global__ void RB_Swap(unsigned char *imageData, int size)
{
int imageIdx = threadIdx.x+blockIdx.x*blockDim.x;
if(imageIdx<size/3)
{
unsigned char tempRGB;
imageIdx = imageIdx*3;
tempRGB = imageData[imageIdx];
imageData[imageIdx] = imageData[imageIdx + 2];
imageData[imageIdx + 2] = tempRGB;
}
}
unsigned char *LoadBitmapFile(char *filename, BITMAPINFOHEADER *bitmapInfoHeader, BITMAPFILEHEADER *bitmapFileHeader)
{
FILE *filePtr; //our file pointer
unsigned char *bitmapImage; //store image data
//open filename in read binary mode
filePtr = fopen(filename,"rb");
if (filePtr == NULL)
return NULL;
//read the bitmap file header
fread(bitmapFileHeader, sizeof(BITMAPFILEHEADER),1,filePtr);
//verify that this is a bmp file by check bitmap id
if (bitmapFileHeader->bfType !=0x4D42)
{
fclose(filePtr);
return NULL;
}
//read the bitmap info header
fread(bitmapInfoHeader, sizeof(BITMAPINFOHEADER),1,filePtr); // small edit. forgot to add the closing bracket at sizeof
//move file point to the begging of bitmap data
fseek(filePtr, bitmapFileHeader->bOffBits, SEEK_SET);
//allocate enough memory for the bitmap image data
bitmapImage = (unsigned char*)malloc(bitmapInfoHeader->biSizeImage);
//verify memory allocation
if (!bitmapImage)
{
free(bitmapImage);
fclose(filePtr);
return NULL;
}
//read in the bitmap image data
fread(bitmapImage,1,bitmapInfoHeader->biSizeImage,filePtr);
//make sure bitmap image data was read
if (bitmapImage == NULL)
{
fclose(filePtr);
return NULL;
}
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t end;
cudaEventCreate(&end);
float swapTime;
//swap the r and b values to get RGB (bitmap is BGR)
unsigned char *d_bitmapImage; //store image data in device
//Allocate size to array in device memory
cudaMalloc((void**)&d_bitmapImage, bitmapInfoHeader->biSizeImage);
//Copy data from host to device
cudaMemcpy(d_bitmapImage, bitmapImage, bitmapInfoHeader->biSizeImage, cudaMemcpyHostToDevice);
int B = ceil(bitmapInfoHeader->biSizeImage/1024);
int T = 1024;
//Kernel call
cudaEventRecord(start, 0);
RB_Swap<<<B, T>>> (d_bitmapImage, bitmapInfoHeader->biSizeImage);
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaMemcpy(bitmapImage, d_bitmapImage, bitmapInfoHeader->biSizeImage, cudaMemcpyDeviceToHost);
cudaEventElapsedTime(&swapTime, start, end);
printf("Load Swap Time: %fms\n",swapTime);
cudaEventDestroy(start);
cudaEventDestroy(end);
//close file and return bitmap iamge data
fclose(filePtr);
return bitmapImage;
}
void ReloadBitmapFile(char *filename, unsigned char *bitmapImage, BITMAPFILEHEADER *bitmapFileHeader, BITMAPINFOHEADER *bitmapInfoHeader)
{
FILE *filePtr; //our file pointer
//open filename in write binary mode
filePtr = fopen(filename,"wb");
if (filePtr == NULL)
{
printf("\nERROR: Cannot open file %s", filename);
exit(1);
}
//write the bitmap file header
fwrite(bitmapFileHeader, sizeof(BITMAPFILEHEADER),1,filePtr);
//write the bitmap info header
fwrite(bitmapInfoHeader, sizeof(BITMAPINFOHEADER),1,filePtr); // small edit. forgot to add the closing bracket at sizeof
//swap the r and b values to get RGB (bitmap is BGR)
unsigned char *d_bitmapImage; //store image data in device
//Allocate size to array in device memory
cudaMalloc((void**)&d_bitmapImage, bitmapInfoHeader->biSizeImage);
//Copy data from host to device
cudaMemcpy(d_bitmapImage, bitmapImage, bitmapInfoHeader->biSizeImage, cudaMemcpyHostToDevice);
int B = ceil(bitmapInfoHeader->biSizeImage/1024);
int T = 1024;
//Kernel call
RB_Swap<<<B, T>>> (d_bitmapImage, bitmapInfoHeader->biSizeImage);
cudaMemcpy(bitmapImage, d_bitmapImage, bitmapInfoHeader->biSizeImage, cudaMemcpyDeviceToHost);
//write in the bitmap image data
fwrite(bitmapImage,bitmapInfoHeader->biSizeImage,1,filePtr);
//close file
fclose(filePtr);
}
__global__ void encrypt(unsigned char *bitmapImage, int size, int key)
{
int threadId = threadIdx.x + blockIdx.x*blockDim.x;
int half = key/2;
int index = ((threadId/half)*key) + (threadId%half);
int swap = index + (key - (2*(index%half)) - 1);
if((swap)<size)
{
unsigned char temp;
//unsigned mid = bitmapImage[((index/half)*key) + half];
temp = bitmapImage[index];
bitmapImage[index] = bitmapImage[swap];
bitmapImage[swap] = temp;
}
}
__global__ void decrypt(unsigned char *bitmapImage, int size, int key)
{
int threadId = threadIdx.x + blockIdx.x*blockDim.x;
int half = key/2;
int index = ((threadId/half)*key) + (threadId%half);
int swap = index + (key - (2*(index%half)) - 1);
if((swap)<size)
{
unsigned char temp;
//unsigned mid = bitmapImage[((index/half)*key) + half];
temp = bitmapImage[index];
bitmapImage[index] = bitmapImage[swap];
bitmapImage[swap] = temp;
}
}
int main()
{
BITMAPINFOHEADER bitmapInfoHeader;
BITMAPFILEHEADER bitmapFileHeader;
unsigned char *bitmapData;
bitmapData = LoadBitmapFile("mona_lisa.bmp",&bitmapInfoHeader, &bitmapFileHeader);
printf("%d\n",bitmapInfoHeader.biSizeImage);
/*
//Print array to file
FILE *fout = fopen("out.bmp","wb");
fwrite(bitmapData,bitmapInfoHeader.biSizeImage,1,fout);
*/
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t end;
cudaEventCreate(&end);
float encryptionTime, decryptionTime, HostToDevice, DeviceToHost;
//Encryption
int key = 8000;
unsigned char *d_bitmapImage; //store image data in device
//Allocate size to array in device memory
cudaMalloc((void**)&d_bitmapImage, bitmapInfoHeader.biSizeImage);
//Copy data from host to device
cudaEventRecord(start, 0);
cudaMemcpy(d_bitmapImage, bitmapData, bitmapInfoHeader.biSizeImage, cudaMemcpyHostToDevice);
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&HostToDevice, start, end);
printf("Host to Device Time: %fms\n",HostToDevice);
int B = ceil(bitmapInfoHeader.biSizeImage/1024);
int T = 1024;
//Kernel call
cudaEventRecord(start, 0);
encrypt<<<B, T>>> (d_bitmapImage, bitmapInfoHeader.biSizeImage, key);
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&encryptionTime, start, end);
printf("Encryption Time: %fms\n",encryptionTime);
//Copy data from device to host
cudaEventRecord(start, 0);
cudaMemcpy(bitmapData, d_bitmapImage, bitmapInfoHeader.biSizeImage, cudaMemcpyDeviceToHost);
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&DeviceToHost, start, end);
printf("Device to Host Time: %fms\n",DeviceToHost);
ReloadBitmapFile("Encrypted.bmp", bitmapData, &bitmapFileHeader, &bitmapInfoHeader);
//load encrypted image to array
bitmapData = LoadBitmapFile("Encrypted.bmp",&bitmapInfoHeader, &bitmapFileHeader);
//Decryption
cudaMemcpy(d_bitmapImage, bitmapData, bitmapInfoHeader.biSizeImage, cudaMemcpyHostToDevice);
cudaEventRecord(start, 0);
decrypt<<<B, T>>> (d_bitmapImage, bitmapInfoHeader.biSizeImage, key);
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&decryptionTime, start, end);
printf("Decryption Time: %fms\n",decryptionTime);
cudaMemcpy(bitmapData, d_bitmapImage, bitmapInfoHeader.biSizeImage, cudaMemcpyDeviceToHost);
//decrypt(bitmapData, bitmapInfoHeader.biSizeImage);
ReloadBitmapFile("Decrypted.bmp", bitmapData, &bitmapFileHeader, &bitmapInfoHeader);
cudaEventDestroy(start);
cudaEventDestroy(end);
cudaFree(d_bitmapImage);
return 0;
} | code for sm_80
Function : _Z7decryptPhii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0030*/ LEA.HI R0, R0, c[0x0][0x16c], RZ, 0x1 ; /* 0x00005b0000007a11 */
/* 0x000fe200078f08ff */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e260000002100 */
/*0050*/ SHF.R.S32.HI R5, RZ, 0x1, R0 ; /* 0x00000001ff057819 */
/* 0x000fc80000011400 */
/*0060*/ IABS R0, R5 ; /* 0x0000000500007213 */
/* 0x000fc80000000000 */
/*0070*/ I2F.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e620000209400 */
/*0080*/ IMAD R4, R4, c[0x0][0x0], R7 ; /* 0x0000000004047a24 */
/* 0x001fce00078e0207 */
/*0090*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x002e240000001000 */
/*00a0*/ IADD3 R2, R6, 0xffffffe, RZ ; /* 0x0ffffffe06027810 */
/* 0x001fe40007ffe0ff */
/*00b0*/ IABS R6, R4 ; /* 0x0000000400067213 */
/* 0x000fc80000000000 */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00e0*/ IMAD.MOV R8, RZ, RZ, -R3 ; /* 0x000000ffff087224 */
/* 0x002fc800078e0a03 */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, R8 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0008 */
/*0100*/ IABS R8, R5 ; /* 0x0000000500087213 */
/* 0x000fc60000000000 */
/*0110*/ IMAD R7, R7, R0, RZ ; /* 0x0000000007077224 */
/* 0x000fe400078e02ff */
/*0120*/ IMAD.MOV R9, RZ, RZ, -R8 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a08 */
/*0130*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0140*/ IMAD.HI.U32 R2, R3, R6, RZ ; /* 0x0000000603027227 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD R7, R2, R9, R6 ; /* 0x0000000902077224 */
/* 0x000fe200078e0206 */
/*0160*/ LOP3.LUT R6, R4, R5, RZ, 0x3c, !PT ; /* 0x0000000504067212 */
/* 0x000fc800078e3cff */
/*0170*/ ISETP.GT.U32.AND P2, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe40003f44070 */
/*0180*/ ISETP.GE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fd60003f06270 */
/*0190*/ @!P2 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x000000010707a824 */
/* 0x000fe200078e0a00 */
/*01a0*/ @!P2 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202a810 */
/* 0x000fc80007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe40003f26070 */
/*01c0*/ LOP3.LUT R7, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff077212 */
/* 0x000fd600078e33ff */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc60003f25270 */
/*01f0*/ @!P0 IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff028224 */
/* 0x000fca00078e0a02 */
/*0200*/ SEL R2, R7, R2, !P1 ; /* 0x0000000207027207 */
/* 0x000fca0004800000 */
/*0210*/ IMAD.MOV R6, RZ, RZ, -R2 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a02 */
/*0220*/ IMAD R5, R5, R6, R4 ; /* 0x0000000605057224 */
/* 0x000fc800078e0204 */
/*0230*/ IMAD R6, R2, c[0x0][0x16c], R5 ; /* 0x00005b0002067a24 */
/* 0x000fca00078e0205 */
/*0240*/ IABS R2, R6 ; /* 0x0000000600027213 */
/* 0x000fe40000000000 */
/*0250*/ ISETP.GE.AND P2, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc60003f46270 */
/*0260*/ IMAD.HI.U32 R3, R3, R2, RZ ; /* 0x0000000203037227 */
/* 0x000fc800078e00ff */
/*0270*/ IMAD R3, R3, R9, R2 ; /* 0x0000000903037224 */
/* 0x000fca00078e0202 */
/*0280*/ ISETP.GT.U32.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f04070 */
/*0290*/ @!P0 IMAD.IADD R3, R3, 0x1, -R0 ; /* 0x0000000103038824 */
/* 0x000fca00078e0a00 */
/*02a0*/ ISETP.GT.U32.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f04070 */
/*02b0*/ @!P0 IMAD.IADD R3, R3, 0x1, -R0 ; /* 0x0000000103038824 */
/* 0x000fc800078e0a00 */
/*02c0*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fca00078e0a03 */
/*02d0*/ SEL R3, R7, R3, !P1 ; /* 0x0000000307037207 */
/* 0x000fca0004800000 */
/*02e0*/ IMAD.SHL.U32 R3, R3, 0x2, RZ ; /* 0x0000000203037824 */
/* 0x000fca00078e00ff */
/*02f0*/ LOP3.LUT R3, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff037212 */
/* 0x000fc800078e33ff */
/*0300*/ IADD3 R0, R3, c[0x0][0x16c], R6 ; /* 0x00005b0003007a10 */
/* 0x000fc80007ffe006 */
/*0310*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0320*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0330*/ IADD3 R4, P1, R0, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x000fe20007f3e0ff */
/*0340*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0350*/ IADD3 R2, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006027a10 */
/* 0x000fe40007f1e0ff */
/*0360*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x164], 0x1, P1 ; /* 0x0000590000057a11 */
/* 0x000fe400008f0eff */
/*0370*/ LEA.HI.X.SX32 R3, R6, c[0x0][0x164], 0x1, P0 ; /* 0x0000590006037a11 */
/* 0x000fc600000f0eff */
/*0380*/ LDG.E.U8 R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1100 */
/*0390*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ee8000c1e1100 */
/*03a0*/ STG.E.U8 [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x004fe8000c101104 */
/*03b0*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x008fe2000c101104 */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7encryptPhii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0030*/ LEA.HI R0, R0, c[0x0][0x16c], RZ, 0x1 ; /* 0x00005b0000007a11 */
/* 0x000fe200078f08ff */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e260000002100 */
/*0050*/ SHF.R.S32.HI R5, RZ, 0x1, R0 ; /* 0x00000001ff057819 */
/* 0x000fc80000011400 */
/*0060*/ IABS R0, R5 ; /* 0x0000000500007213 */
/* 0x000fc80000000000 */
/*0070*/ I2F.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e620000209400 */
/*0080*/ IMAD R4, R4, c[0x0][0x0], R7 ; /* 0x0000000004047a24 */
/* 0x001fce00078e0207 */
/*0090*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x002e240000001000 */
/*00a0*/ IADD3 R2, R6, 0xffffffe, RZ ; /* 0x0ffffffe06027810 */
/* 0x001fe40007ffe0ff */
/*00b0*/ IABS R6, R4 ; /* 0x0000000400067213 */
/* 0x000fc80000000000 */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00e0*/ IMAD.MOV R8, RZ, RZ, -R3 ; /* 0x000000ffff087224 */
/* 0x002fc800078e0a03 */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, R8 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0008 */
/*0100*/ IABS R8, R5 ; /* 0x0000000500087213 */
/* 0x000fc60000000000 */
/*0110*/ IMAD R7, R7, R0, RZ ; /* 0x0000000007077224 */
/* 0x000fe400078e02ff */
/*0120*/ IMAD.MOV R9, RZ, RZ, -R8 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a08 */
/*0130*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0140*/ IMAD.HI.U32 R2, R3, R6, RZ ; /* 0x0000000603027227 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD R7, R2, R9, R6 ; /* 0x0000000902077224 */
/* 0x000fe200078e0206 */
/*0160*/ LOP3.LUT R6, R4, R5, RZ, 0x3c, !PT ; /* 0x0000000504067212 */
/* 0x000fc800078e3cff */
/*0170*/ ISETP.GT.U32.AND P2, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe40003f44070 */
/*0180*/ ISETP.GE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fd60003f06270 */
/*0190*/ @!P2 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x000000010707a824 */
/* 0x000fe200078e0a00 */
/*01a0*/ @!P2 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202a810 */
/* 0x000fc80007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe40003f26070 */
/*01c0*/ LOP3.LUT R7, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff077212 */
/* 0x000fd600078e33ff */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc60003f25270 */
/*01f0*/ @!P0 IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff028224 */
/* 0x000fca00078e0a02 */
/*0200*/ SEL R2, R7, R2, !P1 ; /* 0x0000000207027207 */
/* 0x000fca0004800000 */
/*0210*/ IMAD.MOV R6, RZ, RZ, -R2 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a02 */
/*0220*/ IMAD R5, R5, R6, R4 ; /* 0x0000000605057224 */
/* 0x000fc800078e0204 */
/*0230*/ IMAD R6, R2, c[0x0][0x16c], R5 ; /* 0x00005b0002067a24 */
/* 0x000fca00078e0205 */
/*0240*/ IABS R2, R6 ; /* 0x0000000600027213 */
/* 0x000fe40000000000 */
/*0250*/ ISETP.GE.AND P2, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc60003f46270 */
/*0260*/ IMAD.HI.U32 R3, R3, R2, RZ ; /* 0x0000000203037227 */
/* 0x000fc800078e00ff */
/*0270*/ IMAD R3, R3, R9, R2 ; /* 0x0000000903037224 */
/* 0x000fca00078e0202 */
/*0280*/ ISETP.GT.U32.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f04070 */
/*0290*/ @!P0 IMAD.IADD R3, R3, 0x1, -R0 ; /* 0x0000000103038824 */
/* 0x000fca00078e0a00 */
/*02a0*/ ISETP.GT.U32.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f04070 */
/*02b0*/ @!P0 IMAD.IADD R3, R3, 0x1, -R0 ; /* 0x0000000103038824 */
/* 0x000fc800078e0a00 */
/*02c0*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fca00078e0a03 */
/*02d0*/ SEL R3, R7, R3, !P1 ; /* 0x0000000307037207 */
/* 0x000fca0004800000 */
/*02e0*/ IMAD.SHL.U32 R3, R3, 0x2, RZ ; /* 0x0000000203037824 */
/* 0x000fca00078e00ff */
/*02f0*/ LOP3.LUT R3, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff037212 */
/* 0x000fc800078e33ff */
/*0300*/ IADD3 R0, R3, c[0x0][0x16c], R6 ; /* 0x00005b0003007a10 */
/* 0x000fc80007ffe006 */
/*0310*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0320*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0330*/ IADD3 R4, P1, R0, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x000fe20007f3e0ff */
/*0340*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0350*/ IADD3 R2, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006027a10 */
/* 0x000fe40007f1e0ff */
/*0360*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x164], 0x1, P1 ; /* 0x0000590000057a11 */
/* 0x000fe400008f0eff */
/*0370*/ LEA.HI.X.SX32 R3, R6, c[0x0][0x164], 0x1, P0 ; /* 0x0000590006037a11 */
/* 0x000fc600000f0eff */
/*0380*/ LDG.E.U8 R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1100 */
/*0390*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ee8000c1e1100 */
/*03a0*/ STG.E.U8 [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x004fe8000c101104 */
/*03b0*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x008fe2000c101104 */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7RB_SwapPhi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD.WIDE UR4, UR4, 0x55555556, URZ ; /* 0x55555556040478a5 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e260000002100 */
/*0050*/ ULEA.HI UR5, UR5, UR5, URZ, 0x1 ; /* 0x0000000505057291 */
/* 0x000fe2000f8f083f */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GE.AND P0, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fda000bf06270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IMAD R0, R0, 0x3, RZ ; /* 0x0000000300007824 */
/* 0x000fe200078e02ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00b0*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*00c0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f0eff */
/*00d0*/ LDG.E.U8 R7, [R2.64+0x2] ; /* 0x0000020402077981 */
/* 0x000ea8000c1e1100 */
/*00e0*/ LDG.E.U8 R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ee8000c1e1100 */
/*00f0*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x004fe8000c101104 */
/*0100*/ STG.E.U8 [R2.64+0x2], R5 ; /* 0x0000020502007986 */
/* 0x008fe2000c101104 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
typedef short WORD;
typedef int DWORD;
typedef int LONG;
#pragma pack(push, 1)
typedef struct tagBITMAPFILEHEADER
{
WORD bfType; //specifies the file type
DWORD bfSize; //specifies the size in bytes of the bitmap file
WORD bfReserved1; //reserved; must be 0
WORD bfReserved2; //reserved; must be 0
DWORD bOffBits; //species the offset in bytes from the bitmapfileheader to the bitmap bits
}BITMAPFILEHEADER;
#pragma pack(pop)
#pragma pack(push, 1)
typedef struct tagBITMAPINFOHEADER
{
DWORD biSize; //specifies the number of bytes required by the struct
LONG biWidth; //specifies width in pixels
LONG biHeight; //species height in pixels
WORD biPlanes; //specifies the number of color planes, must be 1
WORD biBitCount; //specifies the number of bit per pixel
DWORD biCompression;//spcifies the type of compression
DWORD biSizeImage; //size of image in bytes
LONG biXPelsPerMeter; //number of pixels per meter in x axis
LONG biYPelsPerMeter; //number of pixels per meter in y axis
DWORD biClrUsed; //number of colors used by th ebitmap
DWORD biClrImportant; //number of colors that are important
}BITMAPINFOHEADER;
#pragma pack(pop)
__global__ void RB_Swap(unsigned char *imageData, int size)
{
int imageIdx = threadIdx.x+blockIdx.x*blockDim.x;
if(imageIdx<size/3)
{
unsigned char tempRGB;
imageIdx = imageIdx*3;
tempRGB = imageData[imageIdx];
imageData[imageIdx] = imageData[imageIdx + 2];
imageData[imageIdx + 2] = tempRGB;
}
}
unsigned char *LoadBitmapFile(char *filename, BITMAPINFOHEADER *bitmapInfoHeader, BITMAPFILEHEADER *bitmapFileHeader)
{
FILE *filePtr; //our file pointer
unsigned char *bitmapImage; //store image data
//open filename in read binary mode
filePtr = fopen(filename,"rb");
if (filePtr == NULL)
return NULL;
//read the bitmap file header
fread(bitmapFileHeader, sizeof(BITMAPFILEHEADER),1,filePtr);
//verify that this is a bmp file by check bitmap id
if (bitmapFileHeader->bfType !=0x4D42)
{
fclose(filePtr);
return NULL;
}
//read the bitmap info header
fread(bitmapInfoHeader, sizeof(BITMAPINFOHEADER),1,filePtr); // small edit. forgot to add the closing bracket at sizeof
//move file point to the begging of bitmap data
fseek(filePtr, bitmapFileHeader->bOffBits, SEEK_SET);
//allocate enough memory for the bitmap image data
bitmapImage = (unsigned char*)malloc(bitmapInfoHeader->biSizeImage);
//verify memory allocation
if (!bitmapImage)
{
free(bitmapImage);
fclose(filePtr);
return NULL;
}
//read in the bitmap image data
fread(bitmapImage,1,bitmapInfoHeader->biSizeImage,filePtr);
//make sure bitmap image data was read
if (bitmapImage == NULL)
{
fclose(filePtr);
return NULL;
}
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t end;
cudaEventCreate(&end);
float swapTime;
//swap the r and b values to get RGB (bitmap is BGR)
unsigned char *d_bitmapImage; //store image data in device
//Allocate size to array in device memory
cudaMalloc((void**)&d_bitmapImage, bitmapInfoHeader->biSizeImage);
//Copy data from host to device
cudaMemcpy(d_bitmapImage, bitmapImage, bitmapInfoHeader->biSizeImage, cudaMemcpyHostToDevice);
int B = ceil(bitmapInfoHeader->biSizeImage/1024);
int T = 1024;
//Kernel call
cudaEventRecord(start, 0);
RB_Swap<<<B, T>>> (d_bitmapImage, bitmapInfoHeader->biSizeImage);
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaMemcpy(bitmapImage, d_bitmapImage, bitmapInfoHeader->biSizeImage, cudaMemcpyDeviceToHost);
cudaEventElapsedTime(&swapTime, start, end);
printf("Load Swap Time: %fms\n",swapTime);
cudaEventDestroy(start);
cudaEventDestroy(end);
//close file and return bitmap iamge data
fclose(filePtr);
return bitmapImage;
}
void ReloadBitmapFile(char *filename, unsigned char *bitmapImage, BITMAPFILEHEADER *bitmapFileHeader, BITMAPINFOHEADER *bitmapInfoHeader)
{
FILE *filePtr; //our file pointer
//open filename in write binary mode
filePtr = fopen(filename,"wb");
if (filePtr == NULL)
{
printf("\nERROR: Cannot open file %s", filename);
exit(1);
}
//write the bitmap file header
fwrite(bitmapFileHeader, sizeof(BITMAPFILEHEADER),1,filePtr);
//write the bitmap info header
fwrite(bitmapInfoHeader, sizeof(BITMAPINFOHEADER),1,filePtr); // small edit. forgot to add the closing bracket at sizeof
//swap the r and b values to get RGB (bitmap is BGR)
unsigned char *d_bitmapImage; //store image data in device
//Allocate size to array in device memory
cudaMalloc((void**)&d_bitmapImage, bitmapInfoHeader->biSizeImage);
//Copy data from host to device
cudaMemcpy(d_bitmapImage, bitmapImage, bitmapInfoHeader->biSizeImage, cudaMemcpyHostToDevice);
int B = ceil(bitmapInfoHeader->biSizeImage/1024);
int T = 1024;
//Kernel call
RB_Swap<<<B, T>>> (d_bitmapImage, bitmapInfoHeader->biSizeImage);
cudaMemcpy(bitmapImage, d_bitmapImage, bitmapInfoHeader->biSizeImage, cudaMemcpyDeviceToHost);
//write in the bitmap image data
fwrite(bitmapImage,bitmapInfoHeader->biSizeImage,1,filePtr);
//close file
fclose(filePtr);
}
__global__ void encrypt(unsigned char *bitmapImage, int size, int key)
{
int threadId = threadIdx.x + blockIdx.x*blockDim.x;
int half = key/2;
int index = ((threadId/half)*key) + (threadId%half);
int swap = index + (key - (2*(index%half)) - 1);
if((swap)<size)
{
unsigned char temp;
//unsigned mid = bitmapImage[((index/half)*key) + half];
temp = bitmapImage[index];
bitmapImage[index] = bitmapImage[swap];
bitmapImage[swap] = temp;
}
}
__global__ void decrypt(unsigned char *bitmapImage, int size, int key)
{
int threadId = threadIdx.x + blockIdx.x*blockDim.x;
int half = key/2;
int index = ((threadId/half)*key) + (threadId%half);
int swap = index + (key - (2*(index%half)) - 1);
if((swap)<size)
{
unsigned char temp;
//unsigned mid = bitmapImage[((index/half)*key) + half];
temp = bitmapImage[index];
bitmapImage[index] = bitmapImage[swap];
bitmapImage[swap] = temp;
}
}
int main()
{
BITMAPINFOHEADER bitmapInfoHeader;
BITMAPFILEHEADER bitmapFileHeader;
unsigned char *bitmapData;
bitmapData = LoadBitmapFile("mona_lisa.bmp",&bitmapInfoHeader, &bitmapFileHeader);
printf("%d\n",bitmapInfoHeader.biSizeImage);
/*
//Print array to file
FILE *fout = fopen("out.bmp","wb");
fwrite(bitmapData,bitmapInfoHeader.biSizeImage,1,fout);
*/
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t end;
cudaEventCreate(&end);
float encryptionTime, decryptionTime, HostToDevice, DeviceToHost;
//Encryption
int key = 8000;
unsigned char *d_bitmapImage; //store image data in device
//Allocate size to array in device memory
cudaMalloc((void**)&d_bitmapImage, bitmapInfoHeader.biSizeImage);
//Copy data from host to device
cudaEventRecord(start, 0);
cudaMemcpy(d_bitmapImage, bitmapData, bitmapInfoHeader.biSizeImage, cudaMemcpyHostToDevice);
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&HostToDevice, start, end);
printf("Host to Device Time: %fms\n",HostToDevice);
int B = ceil(bitmapInfoHeader.biSizeImage/1024);
int T = 1024;
//Kernel call
cudaEventRecord(start, 0);
encrypt<<<B, T>>> (d_bitmapImage, bitmapInfoHeader.biSizeImage, key);
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&encryptionTime, start, end);
printf("Encryption Time: %fms\n",encryptionTime);
//Copy data from device to host
cudaEventRecord(start, 0);
cudaMemcpy(bitmapData, d_bitmapImage, bitmapInfoHeader.biSizeImage, cudaMemcpyDeviceToHost);
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&DeviceToHost, start, end);
printf("Device to Host Time: %fms\n",DeviceToHost);
ReloadBitmapFile("Encrypted.bmp", bitmapData, &bitmapFileHeader, &bitmapInfoHeader);
//load encrypted image to array
bitmapData = LoadBitmapFile("Encrypted.bmp",&bitmapInfoHeader, &bitmapFileHeader);
//Decryption
cudaMemcpy(d_bitmapImage, bitmapData, bitmapInfoHeader.biSizeImage, cudaMemcpyHostToDevice);
cudaEventRecord(start, 0);
decrypt<<<B, T>>> (d_bitmapImage, bitmapInfoHeader.biSizeImage, key);
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&decryptionTime, start, end);
printf("Decryption Time: %fms\n",decryptionTime);
cudaMemcpy(bitmapData, d_bitmapImage, bitmapInfoHeader.biSizeImage, cudaMemcpyDeviceToHost);
//decrypt(bitmapData, bitmapInfoHeader.biSizeImage);
ReloadBitmapFile("Decrypted.bmp", bitmapData, &bitmapFileHeader, &bitmapInfoHeader);
cudaEventDestroy(start);
cudaEventDestroy(end);
cudaFree(d_bitmapImage);
return 0;
} | .file "tmpxft_0011bf8b_00000000-6_parallel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z7RB_SwapPhiPhi
.type _Z27__device_stub__Z7RB_SwapPhiPhi, @function
_Z27__device_stub__Z7RB_SwapPhiPhi:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7RB_SwapPhi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z27__device_stub__Z7RB_SwapPhiPhi, .-_Z27__device_stub__Z7RB_SwapPhiPhi
.globl _Z7RB_SwapPhi
.type _Z7RB_SwapPhi, @function
_Z7RB_SwapPhi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7RB_SwapPhiPhi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7RB_SwapPhi, .-_Z7RB_SwapPhi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "wb"
.LC1:
.string "\nERROR: Cannot open file %s"
.text
.globl _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER
.type _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER, @function
_Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, %r12
movq %rdx, %r14
movq %rcx, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L16
movq %rax, %rbp
movq %rax, %rcx
movl $1, %edx
movl $14, %esi
movq %r14, %rdi
call fwrite@PLT
movq %rbp, %rcx
movl $1, %edx
movl $40, %esi
movq %rbx, %rdi
call fwrite@PLT
movslq 20(%rbx), %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movslq 20(%rbx), %rdx
movl $1, %ecx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 20(%rbx), %edx
leal 1023(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $10, %eax
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movslq 20(%rbx), %rdx
movl $2, %ecx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movslq 20(%rbx), %rsi
movq %rbp, %rcx
movl $1, %edx
movq %r12, %rdi
call fwrite@PLT
movq %rbp, %rdi
call fclose@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq %r13, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L17:
movl 20(%rbx), %esi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z7RB_SwapPhiPhi
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER, .-_Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER
.section .rodata.str1.1
.LC2:
.string "rb"
.LC3:
.string "Load Swap Time: %fms\n"
.text
.globl _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER
.type _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER, @function
_Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %rbp
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC2(%rip), %rsi
call fopen@PLT
movq %rax, %rbx
testq %rax, %rax
je .L25
movq %rax, %r8
movl $1, %ecx
movl $14, %edx
movq $-1, %rsi
movq %r12, %rdi
call __fread_chk@PLT
cmpw $19778, (%r12)
jne .L27
movq %rbx, %r8
movl $1, %ecx
movl $40, %edx
movq $-1, %rsi
movq %rbp, %rdi
call __fread_chk@PLT
movslq 10(%r12), %rsi
movl $0, %edx
movq %rbx, %rdi
call fseek@PLT
movslq 20(%rbp), %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
testq %rax, %rax
je .L28
movq %rbx, %r8
movq %r13, %rcx
movl $1, %edx
movq %r13, %rsi
movq %rax, %rdi
call __fread_chk@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movslq 20(%rbp), %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movslq 20(%rbp), %rdx
movl $1, %ecx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl 20(%rbp), %eax
leal 1023(%rax), %r13d
testl %eax, %eax
cmovns %eax, %r13d
sarl $10, %r13d
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %r13d, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L23:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
movslq 20(%rbp), %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq 44(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq %rbx, %rdi
call fclose@PLT
.L19:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movq %r12, %rax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq %rbx, %rdi
call fclose@PLT
movl $0, %r12d
jmp .L19
.L28:
movq %rbx, %rdi
call fclose@PLT
jmp .L19
.L29:
movl 20(%rbp), %esi
movq 24(%rsp), %rdi
call _Z27__device_stub__Z7RB_SwapPhiPhi
jmp .L23
.L25:
movq %rax, %r12
jmp .L19
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER, .-_Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER
.globl _Z28__device_stub__Z7encryptPhiiPhii
.type _Z28__device_stub__Z7encryptPhiiPhii, @function
_Z28__device_stub__Z7encryptPhiiPhii:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7encryptPhii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z28__device_stub__Z7encryptPhiiPhii, .-_Z28__device_stub__Z7encryptPhiiPhii
.globl _Z7encryptPhii
.type _Z7encryptPhii, @function
_Z7encryptPhii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7encryptPhiiPhii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7encryptPhii, .-_Z7encryptPhii
.globl _Z28__device_stub__Z7decryptPhiiPhii
.type _Z28__device_stub__Z7decryptPhiiPhii, @function
_Z28__device_stub__Z7decryptPhiiPhii:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L43
.L39:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7decryptPhii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L39
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z28__device_stub__Z7decryptPhiiPhii, .-_Z28__device_stub__Z7decryptPhiiPhii
.globl _Z7decryptPhii
.type _Z7decryptPhii, @function
_Z7decryptPhii:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7decryptPhiiPhii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z7decryptPhii, .-_Z7decryptPhii
.section .rodata.str1.1
.LC4:
.string "mona_lisa.bmp"
.LC5:
.string "%d\n"
.LC6:
.string "Host to Device Time: %fms\n"
.LC7:
.string "Encryption Time: %fms\n"
.LC8:
.string "Device to Host Time: %fms\n"
.LC9:
.string "Encrypted.bmp"
.LC10:
.string "Decryption Time: %fms\n"
.LC11:
.string "Decrypted.bmp"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $136, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 66(%rsp), %rdx
leaq 80(%rsp), %rsi
leaq .LC4(%rip), %rdi
call _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER
movq %rax, %rbp
movl 100(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movslq 100(%rsp), %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movslq 100(%rsp), %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 8(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 100(%rsp), %eax
leal 1023(%rax), %ebx
testl %eax, %eax
cmovns %eax, %ebx
sarl $10, %ebx
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %ebx, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L48:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movslq 100(%rsp), %rdx
movl $2, %ecx
movq 32(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 80(%rsp), %r12
leaq 66(%rsp), %r13
movq %r12, %rcx
movq %r13, %rdx
movq %rbp, %rsi
leaq .LC9(%rip), %rbp
movq %rbp, %rdi
call _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER
movq %rax, %rbp
movslq 100(%rsp), %rdx
movl $1, %ecx
movq %rax, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %ebx, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L49:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 52(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq 100(%rsp), %rdx
movl $2, %ecx
movq 32(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rcx
leaq 66(%rsp), %rdx
movq %rbp, %rsi
leaq .LC11(%rip), %rdi
call _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L54
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movl $8000, %edx
movl 100(%rsp), %esi
movq 32(%rsp), %rdi
call _Z28__device_stub__Z7encryptPhiiPhii
jmp .L48
.L53:
movl $8000, %edx
movl 100(%rsp), %esi
movq 32(%rsp), %rdi
call _Z28__device_stub__Z7decryptPhiiPhii
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z7decryptPhii"
.LC13:
.string "_Z7encryptPhii"
.LC14:
.string "_Z7RB_SwapPhi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z7decryptPhii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z7encryptPhii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z7RB_SwapPhi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
typedef short WORD;
typedef int DWORD;
typedef int LONG;
#pragma pack(push, 1)
typedef struct tagBITMAPFILEHEADER
{
WORD bfType; //specifies the file type
DWORD bfSize; //specifies the size in bytes of the bitmap file
WORD bfReserved1; //reserved; must be 0
WORD bfReserved2; //reserved; must be 0
DWORD bOffBits; //species the offset in bytes from the bitmapfileheader to the bitmap bits
}BITMAPFILEHEADER;
#pragma pack(pop)
#pragma pack(push, 1)
typedef struct tagBITMAPINFOHEADER
{
DWORD biSize; //specifies the number of bytes required by the struct
LONG biWidth; //specifies width in pixels
LONG biHeight; //species height in pixels
WORD biPlanes; //specifies the number of color planes, must be 1
WORD biBitCount; //specifies the number of bit per pixel
DWORD biCompression;//spcifies the type of compression
DWORD biSizeImage; //size of image in bytes
LONG biXPelsPerMeter; //number of pixels per meter in x axis
LONG biYPelsPerMeter; //number of pixels per meter in y axis
DWORD biClrUsed; //number of colors used by th ebitmap
DWORD biClrImportant; //number of colors that are important
}BITMAPINFOHEADER;
#pragma pack(pop)
__global__ void RB_Swap(unsigned char *imageData, int size)
{
int imageIdx = threadIdx.x+blockIdx.x*blockDim.x;
if(imageIdx<size/3)
{
unsigned char tempRGB;
imageIdx = imageIdx*3;
tempRGB = imageData[imageIdx];
imageData[imageIdx] = imageData[imageIdx + 2];
imageData[imageIdx + 2] = tempRGB;
}
}
unsigned char *LoadBitmapFile(char *filename, BITMAPINFOHEADER *bitmapInfoHeader, BITMAPFILEHEADER *bitmapFileHeader)
{
FILE *filePtr; //our file pointer
unsigned char *bitmapImage; //store image data
//open filename in read binary mode
filePtr = fopen(filename,"rb");
if (filePtr == NULL)
return NULL;
//read the bitmap file header
fread(bitmapFileHeader, sizeof(BITMAPFILEHEADER),1,filePtr);
//verify that this is a bmp file by check bitmap id
if (bitmapFileHeader->bfType !=0x4D42)
{
fclose(filePtr);
return NULL;
}
//read the bitmap info header
fread(bitmapInfoHeader, sizeof(BITMAPINFOHEADER),1,filePtr); // small edit. forgot to add the closing bracket at sizeof
//move file point to the begging of bitmap data
fseek(filePtr, bitmapFileHeader->bOffBits, SEEK_SET);
//allocate enough memory for the bitmap image data
bitmapImage = (unsigned char*)malloc(bitmapInfoHeader->biSizeImage);
//verify memory allocation
if (!bitmapImage)
{
free(bitmapImage);
fclose(filePtr);
return NULL;
}
//read in the bitmap image data
fread(bitmapImage,1,bitmapInfoHeader->biSizeImage,filePtr);
//make sure bitmap image data was read
if (bitmapImage == NULL)
{
fclose(filePtr);
return NULL;
}
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t end;
cudaEventCreate(&end);
float swapTime;
//swap the r and b values to get RGB (bitmap is BGR)
unsigned char *d_bitmapImage; //store image data in device
//Allocate size to array in device memory
cudaMalloc((void**)&d_bitmapImage, bitmapInfoHeader->biSizeImage);
//Copy data from host to device
cudaMemcpy(d_bitmapImage, bitmapImage, bitmapInfoHeader->biSizeImage, cudaMemcpyHostToDevice);
int B = ceil(bitmapInfoHeader->biSizeImage/1024);
int T = 1024;
//Kernel call
cudaEventRecord(start, 0);
RB_Swap<<<B, T>>> (d_bitmapImage, bitmapInfoHeader->biSizeImage);
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaMemcpy(bitmapImage, d_bitmapImage, bitmapInfoHeader->biSizeImage, cudaMemcpyDeviceToHost);
cudaEventElapsedTime(&swapTime, start, end);
printf("Load Swap Time: %fms\n",swapTime);
cudaEventDestroy(start);
cudaEventDestroy(end);
//close file and return bitmap iamge data
fclose(filePtr);
return bitmapImage;
}
void ReloadBitmapFile(char *filename, unsigned char *bitmapImage, BITMAPFILEHEADER *bitmapFileHeader, BITMAPINFOHEADER *bitmapInfoHeader)
{
FILE *filePtr; //our file pointer
//open filename in write binary mode
filePtr = fopen(filename,"wb");
if (filePtr == NULL)
{
printf("\nERROR: Cannot open file %s", filename);
exit(1);
}
//write the bitmap file header
fwrite(bitmapFileHeader, sizeof(BITMAPFILEHEADER),1,filePtr);
//write the bitmap info header
fwrite(bitmapInfoHeader, sizeof(BITMAPINFOHEADER),1,filePtr); // small edit. forgot to add the closing bracket at sizeof
//swap the r and b values to get RGB (bitmap is BGR)
unsigned char *d_bitmapImage; //store image data in device
//Allocate size to array in device memory
cudaMalloc((void**)&d_bitmapImage, bitmapInfoHeader->biSizeImage);
//Copy data from host to device
cudaMemcpy(d_bitmapImage, bitmapImage, bitmapInfoHeader->biSizeImage, cudaMemcpyHostToDevice);
int B = ceil(bitmapInfoHeader->biSizeImage/1024);
int T = 1024;
//Kernel call
RB_Swap<<<B, T>>> (d_bitmapImage, bitmapInfoHeader->biSizeImage);
cudaMemcpy(bitmapImage, d_bitmapImage, bitmapInfoHeader->biSizeImage, cudaMemcpyDeviceToHost);
//write in the bitmap image data
fwrite(bitmapImage,bitmapInfoHeader->biSizeImage,1,filePtr);
//close file
fclose(filePtr);
}
__global__ void encrypt(unsigned char *bitmapImage, int size, int key)
{
int threadId = threadIdx.x + blockIdx.x*blockDim.x;
int half = key/2;
int index = ((threadId/half)*key) + (threadId%half);
int swap = index + (key - (2*(index%half)) - 1);
if((swap)<size)
{
unsigned char temp;
//unsigned mid = bitmapImage[((index/half)*key) + half];
temp = bitmapImage[index];
bitmapImage[index] = bitmapImage[swap];
bitmapImage[swap] = temp;
}
}
__global__ void decrypt(unsigned char *bitmapImage, int size, int key)
{
int threadId = threadIdx.x + blockIdx.x*blockDim.x;
int half = key/2;
int index = ((threadId/half)*key) + (threadId%half);
int swap = index + (key - (2*(index%half)) - 1);
if((swap)<size)
{
unsigned char temp;
//unsigned mid = bitmapImage[((index/half)*key) + half];
temp = bitmapImage[index];
bitmapImage[index] = bitmapImage[swap];
bitmapImage[swap] = temp;
}
}
int main()
{
BITMAPINFOHEADER bitmapInfoHeader;
BITMAPFILEHEADER bitmapFileHeader;
unsigned char *bitmapData;
bitmapData = LoadBitmapFile("mona_lisa.bmp",&bitmapInfoHeader, &bitmapFileHeader);
printf("%d\n",bitmapInfoHeader.biSizeImage);
/*
//Print array to file
FILE *fout = fopen("out.bmp","wb");
fwrite(bitmapData,bitmapInfoHeader.biSizeImage,1,fout);
*/
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t end;
cudaEventCreate(&end);
float encryptionTime, decryptionTime, HostToDevice, DeviceToHost;
//Encryption
int key = 8000;
unsigned char *d_bitmapImage; //store image data in device
//Allocate size to array in device memory
cudaMalloc((void**)&d_bitmapImage, bitmapInfoHeader.biSizeImage);
//Copy data from host to device
cudaEventRecord(start, 0);
cudaMemcpy(d_bitmapImage, bitmapData, bitmapInfoHeader.biSizeImage, cudaMemcpyHostToDevice);
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&HostToDevice, start, end);
printf("Host to Device Time: %fms\n",HostToDevice);
int B = ceil(bitmapInfoHeader.biSizeImage/1024);
int T = 1024;
//Kernel call
cudaEventRecord(start, 0);
encrypt<<<B, T>>> (d_bitmapImage, bitmapInfoHeader.biSizeImage, key);
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&encryptionTime, start, end);
printf("Encryption Time: %fms\n",encryptionTime);
//Copy data from device to host
cudaEventRecord(start, 0);
cudaMemcpy(bitmapData, d_bitmapImage, bitmapInfoHeader.biSizeImage, cudaMemcpyDeviceToHost);
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&DeviceToHost, start, end);
printf("Device to Host Time: %fms\n",DeviceToHost);
ReloadBitmapFile("Encrypted.bmp", bitmapData, &bitmapFileHeader, &bitmapInfoHeader);
//load encrypted image to array
bitmapData = LoadBitmapFile("Encrypted.bmp",&bitmapInfoHeader, &bitmapFileHeader);
//Decryption
cudaMemcpy(d_bitmapImage, bitmapData, bitmapInfoHeader.biSizeImage, cudaMemcpyHostToDevice);
cudaEventRecord(start, 0);
decrypt<<<B, T>>> (d_bitmapImage, bitmapInfoHeader.biSizeImage, key);
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&decryptionTime, start, end);
printf("Decryption Time: %fms\n",decryptionTime);
cudaMemcpy(bitmapData, d_bitmapImage, bitmapInfoHeader.biSizeImage, cudaMemcpyDeviceToHost);
//decrypt(bitmapData, bitmapInfoHeader.biSizeImage);
ReloadBitmapFile("Decrypted.bmp", bitmapData, &bitmapFileHeader, &bitmapInfoHeader);
cudaEventDestroy(start);
cudaEventDestroy(end);
cudaFree(d_bitmapImage);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
typedef short WORD;
typedef int DWORD;
typedef int LONG;
#pragma pack(push, 1)
typedef struct tagBITMAPFILEHEADER
{
WORD bfType; //specifies the file type
DWORD bfSize; //specifies the size in bytes of the bitmap file
WORD bfReserved1; //reserved; must be 0
WORD bfReserved2; //reserved; must be 0
DWORD bOffBits; //species the offset in bytes from the bitmapfileheader to the bitmap bits
}BITMAPFILEHEADER;
#pragma pack(pop)
#pragma pack(push, 1)
typedef struct tagBITMAPINFOHEADER
{
DWORD biSize; //specifies the number of bytes required by the struct
LONG biWidth; //specifies width in pixels
LONG biHeight; //species height in pixels
WORD biPlanes; //specifies the number of color planes, must be 1
WORD biBitCount; //specifies the number of bit per pixel
DWORD biCompression;//spcifies the type of compression
DWORD biSizeImage; //size of image in bytes
LONG biXPelsPerMeter; //number of pixels per meter in x axis
LONG biYPelsPerMeter; //number of pixels per meter in y axis
DWORD biClrUsed; //number of colors used by th ebitmap
DWORD biClrImportant; //number of colors that are important
}BITMAPINFOHEADER;
#pragma pack(pop)
__global__ void RB_Swap(unsigned char *imageData, int size)
{
int imageIdx = threadIdx.x+blockIdx.x*blockDim.x;
if(imageIdx<size/3)
{
unsigned char tempRGB;
imageIdx = imageIdx*3;
tempRGB = imageData[imageIdx];
imageData[imageIdx] = imageData[imageIdx + 2];
imageData[imageIdx + 2] = tempRGB;
}
}
unsigned char *LoadBitmapFile(char *filename, BITMAPINFOHEADER *bitmapInfoHeader, BITMAPFILEHEADER *bitmapFileHeader)
{
FILE *filePtr; //our file pointer
unsigned char *bitmapImage; //store image data
//open filename in read binary mode
filePtr = fopen(filename,"rb");
if (filePtr == NULL)
return NULL;
//read the bitmap file header
fread(bitmapFileHeader, sizeof(BITMAPFILEHEADER),1,filePtr);
//verify that this is a bmp file by check bitmap id
if (bitmapFileHeader->bfType !=0x4D42)
{
fclose(filePtr);
return NULL;
}
//read the bitmap info header
fread(bitmapInfoHeader, sizeof(BITMAPINFOHEADER),1,filePtr); // small edit. forgot to add the closing bracket at sizeof
//move file point to the begging of bitmap data
fseek(filePtr, bitmapFileHeader->bOffBits, SEEK_SET);
//allocate enough memory for the bitmap image data
bitmapImage = (unsigned char*)malloc(bitmapInfoHeader->biSizeImage);
//verify memory allocation
if (!bitmapImage)
{
free(bitmapImage);
fclose(filePtr);
return NULL;
}
//read in the bitmap image data
fread(bitmapImage,1,bitmapInfoHeader->biSizeImage,filePtr);
//make sure bitmap image data was read
if (bitmapImage == NULL)
{
fclose(filePtr);
return NULL;
}
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t end;
hipEventCreate(&end);
float swapTime;
//swap the r and b values to get RGB (bitmap is BGR)
unsigned char *d_bitmapImage; //store image data in device
//Allocate size to array in device memory
hipMalloc((void**)&d_bitmapImage, bitmapInfoHeader->biSizeImage);
//Copy data from host to device
hipMemcpy(d_bitmapImage, bitmapImage, bitmapInfoHeader->biSizeImage, hipMemcpyHostToDevice);
int B = ceil(bitmapInfoHeader->biSizeImage/1024);
int T = 1024;
//Kernel call
hipEventRecord(start, 0);
RB_Swap<<<B, T>>> (d_bitmapImage, bitmapInfoHeader->biSizeImage);
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipMemcpy(bitmapImage, d_bitmapImage, bitmapInfoHeader->biSizeImage, hipMemcpyDeviceToHost);
hipEventElapsedTime(&swapTime, start, end);
printf("Load Swap Time: %fms\n",swapTime);
hipEventDestroy(start);
hipEventDestroy(end);
//close file and return bitmap iamge data
fclose(filePtr);
return bitmapImage;
}
void ReloadBitmapFile(char *filename, unsigned char *bitmapImage, BITMAPFILEHEADER *bitmapFileHeader, BITMAPINFOHEADER *bitmapInfoHeader)
{
FILE *filePtr; //our file pointer
//open filename in write binary mode
filePtr = fopen(filename,"wb");
if (filePtr == NULL)
{
printf("\nERROR: Cannot open file %s", filename);
exit(1);
}
//write the bitmap file header
fwrite(bitmapFileHeader, sizeof(BITMAPFILEHEADER),1,filePtr);
//write the bitmap info header
fwrite(bitmapInfoHeader, sizeof(BITMAPINFOHEADER),1,filePtr); // small edit. forgot to add the closing bracket at sizeof
//swap the r and b values to get RGB (bitmap is BGR)
unsigned char *d_bitmapImage; //store image data in device
//Allocate size to array in device memory
hipMalloc((void**)&d_bitmapImage, bitmapInfoHeader->biSizeImage);
//Copy data from host to device
hipMemcpy(d_bitmapImage, bitmapImage, bitmapInfoHeader->biSizeImage, hipMemcpyHostToDevice);
int B = ceil(bitmapInfoHeader->biSizeImage/1024);
int T = 1024;
//Kernel call
RB_Swap<<<B, T>>> (d_bitmapImage, bitmapInfoHeader->biSizeImage);
hipMemcpy(bitmapImage, d_bitmapImage, bitmapInfoHeader->biSizeImage, hipMemcpyDeviceToHost);
//write in the bitmap image data
fwrite(bitmapImage,bitmapInfoHeader->biSizeImage,1,filePtr);
//close file
fclose(filePtr);
}
__global__ void encrypt(unsigned char *bitmapImage, int size, int key)
{
int threadId = threadIdx.x + blockIdx.x*blockDim.x;
int half = key/2;
int index = ((threadId/half)*key) + (threadId%half);
int swap = index + (key - (2*(index%half)) - 1);
if((swap)<size)
{
unsigned char temp;
//unsigned mid = bitmapImage[((index/half)*key) + half];
temp = bitmapImage[index];
bitmapImage[index] = bitmapImage[swap];
bitmapImage[swap] = temp;
}
}
__global__ void decrypt(unsigned char *bitmapImage, int size, int key)
{
int threadId = threadIdx.x + blockIdx.x*blockDim.x;
int half = key/2;
int index = ((threadId/half)*key) + (threadId%half);
int swap = index + (key - (2*(index%half)) - 1);
if((swap)<size)
{
unsigned char temp;
//unsigned mid = bitmapImage[((index/half)*key) + half];
temp = bitmapImage[index];
bitmapImage[index] = bitmapImage[swap];
bitmapImage[swap] = temp;
}
}
int main()
{
BITMAPINFOHEADER bitmapInfoHeader;
BITMAPFILEHEADER bitmapFileHeader;
unsigned char *bitmapData;
bitmapData = LoadBitmapFile("mona_lisa.bmp",&bitmapInfoHeader, &bitmapFileHeader);
printf("%d\n",bitmapInfoHeader.biSizeImage);
/*
//Print array to file
FILE *fout = fopen("out.bmp","wb");
fwrite(bitmapData,bitmapInfoHeader.biSizeImage,1,fout);
*/
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t end;
hipEventCreate(&end);
float encryptionTime, decryptionTime, HostToDevice, DeviceToHost;
//Encryption
int key = 8000;
unsigned char *d_bitmapImage; //store image data in device
//Allocate size to array in device memory
hipMalloc((void**)&d_bitmapImage, bitmapInfoHeader.biSizeImage);
//Copy data from host to device
hipEventRecord(start, 0);
hipMemcpy(d_bitmapImage, bitmapData, bitmapInfoHeader.biSizeImage, hipMemcpyHostToDevice);
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&HostToDevice, start, end);
printf("Host to Device Time: %fms\n",HostToDevice);
int B = ceil(bitmapInfoHeader.biSizeImage/1024);
int T = 1024;
//Kernel call
hipEventRecord(start, 0);
encrypt<<<B, T>>> (d_bitmapImage, bitmapInfoHeader.biSizeImage, key);
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&encryptionTime, start, end);
printf("Encryption Time: %fms\n",encryptionTime);
//Copy data from device to host
hipEventRecord(start, 0);
hipMemcpy(bitmapData, d_bitmapImage, bitmapInfoHeader.biSizeImage, hipMemcpyDeviceToHost);
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&DeviceToHost, start, end);
printf("Device to Host Time: %fms\n",DeviceToHost);
ReloadBitmapFile("Encrypted.bmp", bitmapData, &bitmapFileHeader, &bitmapInfoHeader);
//load encrypted image to array
bitmapData = LoadBitmapFile("Encrypted.bmp",&bitmapInfoHeader, &bitmapFileHeader);
//Decryption
hipMemcpy(d_bitmapImage, bitmapData, bitmapInfoHeader.biSizeImage, hipMemcpyHostToDevice);
hipEventRecord(start, 0);
decrypt<<<B, T>>> (d_bitmapImage, bitmapInfoHeader.biSizeImage, key);
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&decryptionTime, start, end);
printf("Decryption Time: %fms\n",decryptionTime);
hipMemcpy(bitmapData, d_bitmapImage, bitmapInfoHeader.biSizeImage, hipMemcpyDeviceToHost);
//decrypt(bitmapData, bitmapInfoHeader.biSizeImage);
ReloadBitmapFile("Decrypted.bmp", bitmapData, &bitmapFileHeader, &bitmapInfoHeader);
hipEventDestroy(start);
hipEventDestroy(end);
hipFree(d_bitmapImage);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
typedef short WORD;
typedef int DWORD;
typedef int LONG;
#pragma pack(push, 1)
typedef struct tagBITMAPFILEHEADER
{
WORD bfType; //specifies the file type
DWORD bfSize; //specifies the size in bytes of the bitmap file
WORD bfReserved1; //reserved; must be 0
WORD bfReserved2; //reserved; must be 0
DWORD bOffBits; //species the offset in bytes from the bitmapfileheader to the bitmap bits
}BITMAPFILEHEADER;
#pragma pack(pop)
#pragma pack(push, 1)
typedef struct tagBITMAPINFOHEADER
{
DWORD biSize; //specifies the number of bytes required by the struct
LONG biWidth; //specifies width in pixels
LONG biHeight; //species height in pixels
WORD biPlanes; //specifies the number of color planes, must be 1
WORD biBitCount; //specifies the number of bit per pixel
DWORD biCompression;//spcifies the type of compression
DWORD biSizeImage; //size of image in bytes
LONG biXPelsPerMeter; //number of pixels per meter in x axis
LONG biYPelsPerMeter; //number of pixels per meter in y axis
DWORD biClrUsed; //number of colors used by th ebitmap
DWORD biClrImportant; //number of colors that are important
}BITMAPINFOHEADER;
#pragma pack(pop)
__global__ void RB_Swap(unsigned char *imageData, int size)
{
int imageIdx = threadIdx.x+blockIdx.x*blockDim.x;
if(imageIdx<size/3)
{
unsigned char tempRGB;
imageIdx = imageIdx*3;
tempRGB = imageData[imageIdx];
imageData[imageIdx] = imageData[imageIdx + 2];
imageData[imageIdx + 2] = tempRGB;
}
}
unsigned char *LoadBitmapFile(char *filename, BITMAPINFOHEADER *bitmapInfoHeader, BITMAPFILEHEADER *bitmapFileHeader)
{
FILE *filePtr; //our file pointer
unsigned char *bitmapImage; //store image data
//open filename in read binary mode
filePtr = fopen(filename,"rb");
if (filePtr == NULL)
return NULL;
//read the bitmap file header
fread(bitmapFileHeader, sizeof(BITMAPFILEHEADER),1,filePtr);
//verify that this is a bmp file by check bitmap id
if (bitmapFileHeader->bfType !=0x4D42)
{
fclose(filePtr);
return NULL;
}
//read the bitmap info header
fread(bitmapInfoHeader, sizeof(BITMAPINFOHEADER),1,filePtr); // small edit. forgot to add the closing bracket at sizeof
//move file point to the begging of bitmap data
fseek(filePtr, bitmapFileHeader->bOffBits, SEEK_SET);
//allocate enough memory for the bitmap image data
bitmapImage = (unsigned char*)malloc(bitmapInfoHeader->biSizeImage);
//verify memory allocation
if (!bitmapImage)
{
free(bitmapImage);
fclose(filePtr);
return NULL;
}
//read in the bitmap image data
fread(bitmapImage,1,bitmapInfoHeader->biSizeImage,filePtr);
//make sure bitmap image data was read
if (bitmapImage == NULL)
{
fclose(filePtr);
return NULL;
}
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t end;
hipEventCreate(&end);
float swapTime;
//swap the r and b values to get RGB (bitmap is BGR)
unsigned char *d_bitmapImage; //store image data in device
//Allocate size to array in device memory
hipMalloc((void**)&d_bitmapImage, bitmapInfoHeader->biSizeImage);
//Copy data from host to device
hipMemcpy(d_bitmapImage, bitmapImage, bitmapInfoHeader->biSizeImage, hipMemcpyHostToDevice);
int B = ceil(bitmapInfoHeader->biSizeImage/1024);
int T = 1024;
//Kernel call
hipEventRecord(start, 0);
RB_Swap<<<B, T>>> (d_bitmapImage, bitmapInfoHeader->biSizeImage);
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipMemcpy(bitmapImage, d_bitmapImage, bitmapInfoHeader->biSizeImage, hipMemcpyDeviceToHost);
hipEventElapsedTime(&swapTime, start, end);
printf("Load Swap Time: %fms\n",swapTime);
hipEventDestroy(start);
hipEventDestroy(end);
//close file and return bitmap iamge data
fclose(filePtr);
return bitmapImage;
}
void ReloadBitmapFile(char *filename, unsigned char *bitmapImage, BITMAPFILEHEADER *bitmapFileHeader, BITMAPINFOHEADER *bitmapInfoHeader)
{
FILE *filePtr; //our file pointer
//open filename in write binary mode
filePtr = fopen(filename,"wb");
if (filePtr == NULL)
{
printf("\nERROR: Cannot open file %s", filename);
exit(1);
}
//write the bitmap file header
fwrite(bitmapFileHeader, sizeof(BITMAPFILEHEADER),1,filePtr);
//write the bitmap info header
fwrite(bitmapInfoHeader, sizeof(BITMAPINFOHEADER),1,filePtr); // small edit. forgot to add the closing bracket at sizeof
//swap the r and b values to get RGB (bitmap is BGR)
unsigned char *d_bitmapImage; //store image data in device
//Allocate size to array in device memory
hipMalloc((void**)&d_bitmapImage, bitmapInfoHeader->biSizeImage);
//Copy data from host to device
hipMemcpy(d_bitmapImage, bitmapImage, bitmapInfoHeader->biSizeImage, hipMemcpyHostToDevice);
int B = ceil(bitmapInfoHeader->biSizeImage/1024);
int T = 1024;
//Kernel call
RB_Swap<<<B, T>>> (d_bitmapImage, bitmapInfoHeader->biSizeImage);
hipMemcpy(bitmapImage, d_bitmapImage, bitmapInfoHeader->biSizeImage, hipMemcpyDeviceToHost);
//write in the bitmap image data
fwrite(bitmapImage,bitmapInfoHeader->biSizeImage,1,filePtr);
//close file
fclose(filePtr);
}
__global__ void encrypt(unsigned char *bitmapImage, int size, int key)
{
int threadId = threadIdx.x + blockIdx.x*blockDim.x;
int half = key/2;
int index = ((threadId/half)*key) + (threadId%half);
int swap = index + (key - (2*(index%half)) - 1);
if((swap)<size)
{
unsigned char temp;
//unsigned mid = bitmapImage[((index/half)*key) + half];
temp = bitmapImage[index];
bitmapImage[index] = bitmapImage[swap];
bitmapImage[swap] = temp;
}
}
__global__ void decrypt(unsigned char *bitmapImage, int size, int key)
{
int threadId = threadIdx.x + blockIdx.x*blockDim.x;
int half = key/2;
int index = ((threadId/half)*key) + (threadId%half);
int swap = index + (key - (2*(index%half)) - 1);
if((swap)<size)
{
unsigned char temp;
//unsigned mid = bitmapImage[((index/half)*key) + half];
temp = bitmapImage[index];
bitmapImage[index] = bitmapImage[swap];
bitmapImage[swap] = temp;
}
}
int main()
{
BITMAPINFOHEADER bitmapInfoHeader;
BITMAPFILEHEADER bitmapFileHeader;
unsigned char *bitmapData;
bitmapData = LoadBitmapFile("mona_lisa.bmp",&bitmapInfoHeader, &bitmapFileHeader);
printf("%d\n",bitmapInfoHeader.biSizeImage);
/*
//Print array to file
FILE *fout = fopen("out.bmp","wb");
fwrite(bitmapData,bitmapInfoHeader.biSizeImage,1,fout);
*/
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t end;
hipEventCreate(&end);
float encryptionTime, decryptionTime, HostToDevice, DeviceToHost;
//Encryption
int key = 8000;
unsigned char *d_bitmapImage; //store image data in device
//Allocate size to array in device memory
hipMalloc((void**)&d_bitmapImage, bitmapInfoHeader.biSizeImage);
//Copy data from host to device
hipEventRecord(start, 0);
hipMemcpy(d_bitmapImage, bitmapData, bitmapInfoHeader.biSizeImage, hipMemcpyHostToDevice);
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&HostToDevice, start, end);
printf("Host to Device Time: %fms\n",HostToDevice);
int B = ceil(bitmapInfoHeader.biSizeImage/1024);
int T = 1024;
//Kernel call
hipEventRecord(start, 0);
encrypt<<<B, T>>> (d_bitmapImage, bitmapInfoHeader.biSizeImage, key);
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&encryptionTime, start, end);
printf("Encryption Time: %fms\n",encryptionTime);
//Copy data from device to host
hipEventRecord(start, 0);
hipMemcpy(bitmapData, d_bitmapImage, bitmapInfoHeader.biSizeImage, hipMemcpyDeviceToHost);
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&DeviceToHost, start, end);
printf("Device to Host Time: %fms\n",DeviceToHost);
ReloadBitmapFile("Encrypted.bmp", bitmapData, &bitmapFileHeader, &bitmapInfoHeader);
//load encrypted image to array
bitmapData = LoadBitmapFile("Encrypted.bmp",&bitmapInfoHeader, &bitmapFileHeader);
//Decryption
hipMemcpy(d_bitmapImage, bitmapData, bitmapInfoHeader.biSizeImage, hipMemcpyHostToDevice);
hipEventRecord(start, 0);
decrypt<<<B, T>>> (d_bitmapImage, bitmapInfoHeader.biSizeImage, key);
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&decryptionTime, start, end);
printf("Decryption Time: %fms\n",decryptionTime);
hipMemcpy(bitmapData, d_bitmapImage, bitmapInfoHeader.biSizeImage, hipMemcpyDeviceToHost);
//decrypt(bitmapData, bitmapInfoHeader.biSizeImage);
ReloadBitmapFile("Decrypted.bmp", bitmapData, &bitmapFileHeader, &bitmapInfoHeader);
hipEventDestroy(start);
hipEventDestroy(end);
hipFree(d_bitmapImage);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7RB_SwapPhi
.globl _Z7RB_SwapPhi
.p2align 8
.type _Z7RB_SwapPhi,@function
_Z7RB_SwapPhi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_hi_i32 s2, s3, 0x55555556
s_lshr_b32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshl_add_u32 v0, v1, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x1
global_load_u8 v2, v[0:1], off offset:2
global_load_u8 v3, v[0:1], off
s_waitcnt vmcnt(1)
global_store_b8 v[0:1], v2, off
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v3, off offset:2
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7RB_SwapPhi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7RB_SwapPhi, .Lfunc_end0-_Z7RB_SwapPhi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7encryptPhii
.globl _Z7encryptPhii
.p2align 8
.type _Z7encryptPhii,@function
_Z7encryptPhii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s3, 31
s_and_b32 s4, s4, 0xffff
s_add_i32 s5, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_ashr_i32 s6, s5, 1
s_ashr_i32 s5, s5, 31
s_add_i32 s7, s6, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s7, s7, s5
v_cvt_f32_u32_e32 v1, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_sub_i32 s4, 0, s7
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s5, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v0
v_mul_hi_u32 v0, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v0, s7
v_sub_nc_u32_e32 v4, v4, v5
v_add_nc_u32_e32 v5, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v6, s7, v4
v_cmp_le_u32_e32 vcc_lo, s7, v4
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v4, v4, v6 :: v_dual_add_nc_u32 v5, 1, v0
v_cmp_le_u32_e32 vcc_lo, s7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v0, v2
v_mul_lo_u32 v0, v4, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v1, v0
v_mad_u64_u32 v[0:1], null, v4, s3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v1
v_mul_hi_u32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, s7
v_sub_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s7, v2
v_cmp_le_u32_e32 vcc_lo, s7, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s7, v2
v_cmp_le_u32_e32 vcc_lo, s7, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v1
v_sub_nc_u32_e32 v1, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 1, v1
v_not_b32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v1, v0, s3, v1
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_clause 0x1
global_load_u8 v0, v[1:2], off
global_load_u8 v5, v[3:4], off
s_waitcnt vmcnt(1)
global_store_b8 v[3:4], v0, off
s_waitcnt vmcnt(0)
global_store_b8 v[1:2], v5, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7encryptPhii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7encryptPhii, .Lfunc_end1-_Z7encryptPhii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7decryptPhii
.globl _Z7decryptPhii
.p2align 8
.type _Z7decryptPhii,@function
_Z7decryptPhii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s3, 31
s_and_b32 s4, s4, 0xffff
s_add_i32 s5, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_ashr_i32 s6, s5, 1
s_ashr_i32 s5, s5, 31
s_add_i32 s7, s6, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s7, s7, s5
v_cvt_f32_u32_e32 v1, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_sub_i32 s4, 0, s7
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s5, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v0
v_mul_hi_u32 v0, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v0, s7
v_sub_nc_u32_e32 v4, v4, v5
v_add_nc_u32_e32 v5, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v6, s7, v4
v_cmp_le_u32_e32 vcc_lo, s7, v4
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v4, v4, v6 :: v_dual_add_nc_u32 v5, 1, v0
v_cmp_le_u32_e32 vcc_lo, s7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v0, v2
v_mul_lo_u32 v0, v4, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v1, v0
v_mad_u64_u32 v[0:1], null, v4, s3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v1
v_mul_hi_u32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, s7
v_sub_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s7, v2
v_cmp_le_u32_e32 vcc_lo, s7, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s7, v2
v_cmp_le_u32_e32 vcc_lo, s7, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v1
v_sub_nc_u32_e32 v1, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 1, v1
v_not_b32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v1, v0, s3, v1
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_clause 0x1
global_load_u8 v0, v[1:2], off
global_load_u8 v5, v[3:4], off
s_waitcnt vmcnt(1)
global_store_b8 v[3:4], v0, off
s_waitcnt vmcnt(0)
global_store_b8 v[1:2], v5, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7decryptPhii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z7decryptPhii, .Lfunc_end2-_Z7decryptPhii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7RB_SwapPhi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7RB_SwapPhi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7encryptPhii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7encryptPhii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7decryptPhii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7decryptPhii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
typedef short WORD;
typedef int DWORD;
typedef int LONG;
#pragma pack(push, 1)
typedef struct tagBITMAPFILEHEADER
{
WORD bfType; //specifies the file type
DWORD bfSize; //specifies the size in bytes of the bitmap file
WORD bfReserved1; //reserved; must be 0
WORD bfReserved2; //reserved; must be 0
DWORD bOffBits; //species the offset in bytes from the bitmapfileheader to the bitmap bits
}BITMAPFILEHEADER;
#pragma pack(pop)
#pragma pack(push, 1)
typedef struct tagBITMAPINFOHEADER
{
DWORD biSize; //specifies the number of bytes required by the struct
LONG biWidth; //specifies width in pixels
LONG biHeight; //species height in pixels
WORD biPlanes; //specifies the number of color planes, must be 1
WORD biBitCount; //specifies the number of bit per pixel
DWORD biCompression;//spcifies the type of compression
DWORD biSizeImage; //size of image in bytes
LONG biXPelsPerMeter; //number of pixels per meter in x axis
LONG biYPelsPerMeter; //number of pixels per meter in y axis
DWORD biClrUsed; //number of colors used by th ebitmap
DWORD biClrImportant; //number of colors that are important
}BITMAPINFOHEADER;
#pragma pack(pop)
__global__ void RB_Swap(unsigned char *imageData, int size)
{
int imageIdx = threadIdx.x+blockIdx.x*blockDim.x;
if(imageIdx<size/3)
{
unsigned char tempRGB;
imageIdx = imageIdx*3;
tempRGB = imageData[imageIdx];
imageData[imageIdx] = imageData[imageIdx + 2];
imageData[imageIdx + 2] = tempRGB;
}
}
unsigned char *LoadBitmapFile(char *filename, BITMAPINFOHEADER *bitmapInfoHeader, BITMAPFILEHEADER *bitmapFileHeader)
{
FILE *filePtr; //our file pointer
unsigned char *bitmapImage; //store image data
//open filename in read binary mode
filePtr = fopen(filename,"rb");
if (filePtr == NULL)
return NULL;
//read the bitmap file header
fread(bitmapFileHeader, sizeof(BITMAPFILEHEADER),1,filePtr);
//verify that this is a bmp file by check bitmap id
if (bitmapFileHeader->bfType !=0x4D42)
{
fclose(filePtr);
return NULL;
}
//read the bitmap info header
fread(bitmapInfoHeader, sizeof(BITMAPINFOHEADER),1,filePtr); // small edit. forgot to add the closing bracket at sizeof
//move file point to the begging of bitmap data
fseek(filePtr, bitmapFileHeader->bOffBits, SEEK_SET);
//allocate enough memory for the bitmap image data
bitmapImage = (unsigned char*)malloc(bitmapInfoHeader->biSizeImage);
//verify memory allocation
if (!bitmapImage)
{
free(bitmapImage);
fclose(filePtr);
return NULL;
}
//read in the bitmap image data
fread(bitmapImage,1,bitmapInfoHeader->biSizeImage,filePtr);
//make sure bitmap image data was read
if (bitmapImage == NULL)
{
fclose(filePtr);
return NULL;
}
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t end;
hipEventCreate(&end);
float swapTime;
//swap the r and b values to get RGB (bitmap is BGR)
unsigned char *d_bitmapImage; //store image data in device
//Allocate size to array in device memory
hipMalloc((void**)&d_bitmapImage, bitmapInfoHeader->biSizeImage);
//Copy data from host to device
hipMemcpy(d_bitmapImage, bitmapImage, bitmapInfoHeader->biSizeImage, hipMemcpyHostToDevice);
int B = ceil(bitmapInfoHeader->biSizeImage/1024);
int T = 1024;
//Kernel call
hipEventRecord(start, 0);
RB_Swap<<<B, T>>> (d_bitmapImage, bitmapInfoHeader->biSizeImage);
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipMemcpy(bitmapImage, d_bitmapImage, bitmapInfoHeader->biSizeImage, hipMemcpyDeviceToHost);
hipEventElapsedTime(&swapTime, start, end);
printf("Load Swap Time: %fms\n",swapTime);
hipEventDestroy(start);
hipEventDestroy(end);
//close file and return bitmap iamge data
fclose(filePtr);
return bitmapImage;
}
void ReloadBitmapFile(char *filename, unsigned char *bitmapImage, BITMAPFILEHEADER *bitmapFileHeader, BITMAPINFOHEADER *bitmapInfoHeader)
{
FILE *filePtr; //our file pointer
//open filename in write binary mode
filePtr = fopen(filename,"wb");
if (filePtr == NULL)
{
printf("\nERROR: Cannot open file %s", filename);
exit(1);
}
//write the bitmap file header
fwrite(bitmapFileHeader, sizeof(BITMAPFILEHEADER),1,filePtr);
//write the bitmap info header
fwrite(bitmapInfoHeader, sizeof(BITMAPINFOHEADER),1,filePtr); // small edit. forgot to add the closing bracket at sizeof
//swap the r and b values to get RGB (bitmap is BGR)
unsigned char *d_bitmapImage; //store image data in device
//Allocate size to array in device memory
hipMalloc((void**)&d_bitmapImage, bitmapInfoHeader->biSizeImage);
//Copy data from host to device
hipMemcpy(d_bitmapImage, bitmapImage, bitmapInfoHeader->biSizeImage, hipMemcpyHostToDevice);
int B = ceil(bitmapInfoHeader->biSizeImage/1024);
int T = 1024;
//Kernel call
RB_Swap<<<B, T>>> (d_bitmapImage, bitmapInfoHeader->biSizeImage);
hipMemcpy(bitmapImage, d_bitmapImage, bitmapInfoHeader->biSizeImage, hipMemcpyDeviceToHost);
//write in the bitmap image data
fwrite(bitmapImage,bitmapInfoHeader->biSizeImage,1,filePtr);
//close file
fclose(filePtr);
}
__global__ void encrypt(unsigned char *bitmapImage, int size, int key)
{
int threadId = threadIdx.x + blockIdx.x*blockDim.x;
int half = key/2;
int index = ((threadId/half)*key) + (threadId%half);
int swap = index + (key - (2*(index%half)) - 1);
if((swap)<size)
{
unsigned char temp;
//unsigned mid = bitmapImage[((index/half)*key) + half];
temp = bitmapImage[index];
bitmapImage[index] = bitmapImage[swap];
bitmapImage[swap] = temp;
}
}
__global__ void decrypt(unsigned char *bitmapImage, int size, int key)
{
int threadId = threadIdx.x + blockIdx.x*blockDim.x;
int half = key/2;
int index = ((threadId/half)*key) + (threadId%half);
int swap = index + (key - (2*(index%half)) - 1);
if((swap)<size)
{
unsigned char temp;
//unsigned mid = bitmapImage[((index/half)*key) + half];
temp = bitmapImage[index];
bitmapImage[index] = bitmapImage[swap];
bitmapImage[swap] = temp;
}
}
int main()
{
BITMAPINFOHEADER bitmapInfoHeader;
BITMAPFILEHEADER bitmapFileHeader;
unsigned char *bitmapData;
bitmapData = LoadBitmapFile("mona_lisa.bmp",&bitmapInfoHeader, &bitmapFileHeader);
printf("%d\n",bitmapInfoHeader.biSizeImage);
/*
//Print array to file
FILE *fout = fopen("out.bmp","wb");
fwrite(bitmapData,bitmapInfoHeader.biSizeImage,1,fout);
*/
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t end;
hipEventCreate(&end);
float encryptionTime, decryptionTime, HostToDevice, DeviceToHost;
//Encryption
int key = 8000;
unsigned char *d_bitmapImage; //store image data in device
//Allocate size to array in device memory
hipMalloc((void**)&d_bitmapImage, bitmapInfoHeader.biSizeImage);
//Copy data from host to device
hipEventRecord(start, 0);
hipMemcpy(d_bitmapImage, bitmapData, bitmapInfoHeader.biSizeImage, hipMemcpyHostToDevice);
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&HostToDevice, start, end);
printf("Host to Device Time: %fms\n",HostToDevice);
int B = ceil(bitmapInfoHeader.biSizeImage/1024);
int T = 1024;
//Kernel call
hipEventRecord(start, 0);
encrypt<<<B, T>>> (d_bitmapImage, bitmapInfoHeader.biSizeImage, key);
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&encryptionTime, start, end);
printf("Encryption Time: %fms\n",encryptionTime);
//Copy data from device to host
hipEventRecord(start, 0);
hipMemcpy(bitmapData, d_bitmapImage, bitmapInfoHeader.biSizeImage, hipMemcpyDeviceToHost);
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&DeviceToHost, start, end);
printf("Device to Host Time: %fms\n",DeviceToHost);
ReloadBitmapFile("Encrypted.bmp", bitmapData, &bitmapFileHeader, &bitmapInfoHeader);
//load encrypted image to array
bitmapData = LoadBitmapFile("Encrypted.bmp",&bitmapInfoHeader, &bitmapFileHeader);
//Decryption
hipMemcpy(d_bitmapImage, bitmapData, bitmapInfoHeader.biSizeImage, hipMemcpyHostToDevice);
hipEventRecord(start, 0);
decrypt<<<B, T>>> (d_bitmapImage, bitmapInfoHeader.biSizeImage, key);
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&decryptionTime, start, end);
printf("Decryption Time: %fms\n",decryptionTime);
hipMemcpy(bitmapData, d_bitmapImage, bitmapInfoHeader.biSizeImage, hipMemcpyDeviceToHost);
//decrypt(bitmapData, bitmapInfoHeader.biSizeImage);
ReloadBitmapFile("Decrypted.bmp", bitmapData, &bitmapFileHeader, &bitmapInfoHeader);
hipEventDestroy(start);
hipEventDestroy(end);
hipFree(d_bitmapImage);
return 0;
} | .text
.file "parallel.hip"
.globl _Z22__device_stub__RB_SwapPhi # -- Begin function _Z22__device_stub__RB_SwapPhi
.p2align 4, 0x90
.type _Z22__device_stub__RB_SwapPhi,@function
_Z22__device_stub__RB_SwapPhi: # @_Z22__device_stub__RB_SwapPhi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7RB_SwapPhi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__RB_SwapPhi, .Lfunc_end0-_Z22__device_stub__RB_SwapPhi
.cfi_endproc
# -- End function
.globl _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER # -- Begin function _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER
.p2align 4, 0x90
.type _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER,@function
_Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER: # @_Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r15
movq %rsi, %r14
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB1_7
# %bb.1:
movq %rax, %rbx
movl $14, %esi
movl $1, %edx
movq %r15, %rdi
movq %rax, %rcx
callq fread
movzwl (%r15), %eax
cmpl $19778, %eax # imm = 0x4D42
jne .LBB1_6
# %bb.2:
movl $40, %esi
movl $1, %edx
movq %r14, %rdi
movq %rbx, %rcx
callq fread
movslq 10(%r15), %rsi
movq %rbx, %rdi
xorl %edx, %edx
callq fseek
movslq 20(%r14), %r15
movq %r15, %rdi
callq malloc
testq %rax, %rax
je .LBB1_6
# %bb.3:
movl $1, %esi
movq %rax, %rdi
movq %r15, %rdx
movq %rbx, %rcx
movq %rax, %r15
callq fread
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movslq 20(%r14), %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movq 8(%rsp), %rdi
movslq 20(%r14), %rdx
movq %r15, %r12
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl 20(%r14), %eax
leal 1023(%rax), %r15d
testl %eax, %eax
cmovnsl %eax, %r15d
sarl $10, %r15d
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r15
orq $1024, %rdx # imm = 0x400
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 8(%rsp), %rax
movl 20(%r14), %ecx
movq %rax, 96(%rsp)
movl %ecx, 28(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 28(%rsp), %rax
movq %rax, 40(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z7RB_SwapPhi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movslq 20(%r14), %rdx
movq %r12, %r14
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
movq %rbx, %rdi
callq fclose
movq %r12, %rax
jmp .LBB1_8
.LBB1_6:
movq %rbx, %rdi
callq fclose
.LBB1_7:
xorl %eax, %eax
.LBB1_8:
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER, .Lfunc_end1-_Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER
.cfi_endproc
# -- End function
.globl _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER # -- Begin function _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER
.p2align 4, 0x90
.type _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER,@function
_Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER: # @_Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %r14
movq %rdx, %r12
movq %rsi, %rbx
movq %rdi, %r13
movl $.L.str.2, %esi
callq fopen
testq %rax, %rax
je .LBB2_4
# %bb.1:
movq %rax, %r15
movl $14, %esi
movl $1, %edx
movq %r12, %rdi
movq %rax, %rcx
callq fwrite
movl $40, %esi
movl $1, %edx
movq %r14, %rdi
movq %r15, %rcx
callq fwrite
movslq 20(%r14), %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movq 8(%rsp), %rdi
movslq 20(%r14), %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl 20(%r14), %eax
leal 1023(%rax), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_3
# %bb.2:
movq 8(%rsp), %rax
movl 20(%r14), %ecx
movq %rax, 72(%rsp)
movl %ecx, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7RB_SwapPhi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_3:
movq 8(%rsp), %rsi
movslq 20(%r14), %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movslq 20(%r14), %rsi
movl $1, %edx
movq %rbx, %rdi
movq %r15, %rcx
callq fwrite
movq %r15, %rdi
callq fclose
addq $96, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_4:
.cfi_def_cfa_offset 144
movl $.L.str.3, %edi
movq %r13, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER, .Lfunc_end2-_Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER
.cfi_endproc
# -- End function
.globl _Z22__device_stub__encryptPhii # -- Begin function _Z22__device_stub__encryptPhii
.p2align 4, 0x90
.type _Z22__device_stub__encryptPhii,@function
_Z22__device_stub__encryptPhii: # @_Z22__device_stub__encryptPhii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7encryptPhii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z22__device_stub__encryptPhii, .Lfunc_end3-_Z22__device_stub__encryptPhii
.cfi_endproc
# -- End function
.globl _Z22__device_stub__decryptPhii # -- Begin function _Z22__device_stub__decryptPhii
.p2align 4, 0x90
.type _Z22__device_stub__decryptPhii,@function
_Z22__device_stub__decryptPhii: # @_Z22__device_stub__decryptPhii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7decryptPhii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z22__device_stub__decryptPhii, .Lfunc_end4-_Z22__device_stub__decryptPhii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294968320, %rbx # imm = 0x100000400
leaq 160(%rsp), %rsi
leaq 146(%rsp), %rdx
movl $.L.str.4, %edi
callq _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER
movq %rax, %r14
movslq 180(%rsp), %r15
movl $.L.str.5, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 104(%rsp), %rdi
callq hipEventElapsedTime
movss 104(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
leal 1023(%r15), %r12d
testq %r15, %r15
cmovnsl %r15d, %r12d
sarl $10, %r12d
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
addq %rbx, %r12
addq $-1024, %r12 # imm = 0xFC00
movq %r12, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 24(%rsp), %rax
movq %rax, 88(%rsp)
movl %r15d, 36(%rsp)
movl $8000, 32(%rsp) # imm = 0x1F40
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7encryptPhii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 108(%rsp), %rdi
callq hipEventElapsedTime
movss 108(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 100(%rsp), %rdi
callq hipEventElapsedTime
movss 100(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
leaq 146(%rsp), %r15
leaq 160(%rsp), %r13
movl $.L.str.9, %edi
movq %r14, %rsi
movq %r15, %rdx
movq %r13, %rcx
callq _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER
movl $.L.str.9, %edi
movq %r13, %rsi
movq %r15, %rdx
callq _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER
movq %rax, %r14
movq 24(%rsp), %rdi
movl 180(%rsp), %ebp
movslq %ebp, %r15
movq %rax, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r12, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_4
# %bb.3:
movq 24(%rsp), %rax
movq %rax, 88(%rsp)
movl %ebp, 36(%rsp)
movl $8000, 32(%rsp) # imm = 0x1F40
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7decryptPhii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
movss 112(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 146(%rsp), %rdx
leaq 160(%rsp), %rcx
movl $.L.str.11, %edi
movq %r14, %rsi
callq _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7RB_SwapPhi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7encryptPhii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7decryptPhii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7RB_SwapPhi,@object # @_Z7RB_SwapPhi
.section .rodata,"a",@progbits
.globl _Z7RB_SwapPhi
.p2align 3, 0x0
_Z7RB_SwapPhi:
.quad _Z22__device_stub__RB_SwapPhi
.size _Z7RB_SwapPhi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "rb"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Load Swap Time: %fms\n"
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "wb"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\nERROR: Cannot open file %s"
.size .L.str.3, 28
.type _Z7encryptPhii,@object # @_Z7encryptPhii
.section .rodata,"a",@progbits
.globl _Z7encryptPhii
.p2align 3, 0x0
_Z7encryptPhii:
.quad _Z22__device_stub__encryptPhii
.size _Z7encryptPhii, 8
.type _Z7decryptPhii,@object # @_Z7decryptPhii
.globl _Z7decryptPhii
.p2align 3, 0x0
_Z7decryptPhii:
.quad _Z22__device_stub__decryptPhii
.size _Z7decryptPhii, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "mona_lisa.bmp"
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d\n"
.size .L.str.5, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Host to Device Time: %fms\n"
.size .L.str.6, 27
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Encryption Time: %fms\n"
.size .L.str.7, 23
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Device to Host Time: %fms\n"
.size .L.str.8, 27
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Encrypted.bmp"
.size .L.str.9, 14
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Decryption Time: %fms\n"
.size .L.str.10, 23
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Decrypted.bmp"
.size .L.str.11, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7RB_SwapPhi"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7encryptPhii"
.size .L__unnamed_2, 15
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7decryptPhii"
.size .L__unnamed_3, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__RB_SwapPhi
.addrsig_sym _Z22__device_stub__encryptPhii
.addrsig_sym _Z22__device_stub__decryptPhii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7RB_SwapPhi
.addrsig_sym _Z7encryptPhii
.addrsig_sym _Z7decryptPhii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7decryptPhii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0030*/ LEA.HI R0, R0, c[0x0][0x16c], RZ, 0x1 ; /* 0x00005b0000007a11 */
/* 0x000fe200078f08ff */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e260000002100 */
/*0050*/ SHF.R.S32.HI R5, RZ, 0x1, R0 ; /* 0x00000001ff057819 */
/* 0x000fc80000011400 */
/*0060*/ IABS R0, R5 ; /* 0x0000000500007213 */
/* 0x000fc80000000000 */
/*0070*/ I2F.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e620000209400 */
/*0080*/ IMAD R4, R4, c[0x0][0x0], R7 ; /* 0x0000000004047a24 */
/* 0x001fce00078e0207 */
/*0090*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x002e240000001000 */
/*00a0*/ IADD3 R2, R6, 0xffffffe, RZ ; /* 0x0ffffffe06027810 */
/* 0x001fe40007ffe0ff */
/*00b0*/ IABS R6, R4 ; /* 0x0000000400067213 */
/* 0x000fc80000000000 */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00e0*/ IMAD.MOV R8, RZ, RZ, -R3 ; /* 0x000000ffff087224 */
/* 0x002fc800078e0a03 */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, R8 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0008 */
/*0100*/ IABS R8, R5 ; /* 0x0000000500087213 */
/* 0x000fc60000000000 */
/*0110*/ IMAD R7, R7, R0, RZ ; /* 0x0000000007077224 */
/* 0x000fe400078e02ff */
/*0120*/ IMAD.MOV R9, RZ, RZ, -R8 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a08 */
/*0130*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0140*/ IMAD.HI.U32 R2, R3, R6, RZ ; /* 0x0000000603027227 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD R7, R2, R9, R6 ; /* 0x0000000902077224 */
/* 0x000fe200078e0206 */
/*0160*/ LOP3.LUT R6, R4, R5, RZ, 0x3c, !PT ; /* 0x0000000504067212 */
/* 0x000fc800078e3cff */
/*0170*/ ISETP.GT.U32.AND P2, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe40003f44070 */
/*0180*/ ISETP.GE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fd60003f06270 */
/*0190*/ @!P2 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x000000010707a824 */
/* 0x000fe200078e0a00 */
/*01a0*/ @!P2 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202a810 */
/* 0x000fc80007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe40003f26070 */
/*01c0*/ LOP3.LUT R7, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff077212 */
/* 0x000fd600078e33ff */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc60003f25270 */
/*01f0*/ @!P0 IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff028224 */
/* 0x000fca00078e0a02 */
/*0200*/ SEL R2, R7, R2, !P1 ; /* 0x0000000207027207 */
/* 0x000fca0004800000 */
/*0210*/ IMAD.MOV R6, RZ, RZ, -R2 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a02 */
/*0220*/ IMAD R5, R5, R6, R4 ; /* 0x0000000605057224 */
/* 0x000fc800078e0204 */
/*0230*/ IMAD R6, R2, c[0x0][0x16c], R5 ; /* 0x00005b0002067a24 */
/* 0x000fca00078e0205 */
/*0240*/ IABS R2, R6 ; /* 0x0000000600027213 */
/* 0x000fe40000000000 */
/*0250*/ ISETP.GE.AND P2, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc60003f46270 */
/*0260*/ IMAD.HI.U32 R3, R3, R2, RZ ; /* 0x0000000203037227 */
/* 0x000fc800078e00ff */
/*0270*/ IMAD R3, R3, R9, R2 ; /* 0x0000000903037224 */
/* 0x000fca00078e0202 */
/*0280*/ ISETP.GT.U32.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f04070 */
/*0290*/ @!P0 IMAD.IADD R3, R3, 0x1, -R0 ; /* 0x0000000103038824 */
/* 0x000fca00078e0a00 */
/*02a0*/ ISETP.GT.U32.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f04070 */
/*02b0*/ @!P0 IMAD.IADD R3, R3, 0x1, -R0 ; /* 0x0000000103038824 */
/* 0x000fc800078e0a00 */
/*02c0*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fca00078e0a03 */
/*02d0*/ SEL R3, R7, R3, !P1 ; /* 0x0000000307037207 */
/* 0x000fca0004800000 */
/*02e0*/ IMAD.SHL.U32 R3, R3, 0x2, RZ ; /* 0x0000000203037824 */
/* 0x000fca00078e00ff */
/*02f0*/ LOP3.LUT R3, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff037212 */
/* 0x000fc800078e33ff */
/*0300*/ IADD3 R0, R3, c[0x0][0x16c], R6 ; /* 0x00005b0003007a10 */
/* 0x000fc80007ffe006 */
/*0310*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0320*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0330*/ IADD3 R4, P1, R0, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x000fe20007f3e0ff */
/*0340*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0350*/ IADD3 R2, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006027a10 */
/* 0x000fe40007f1e0ff */
/*0360*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x164], 0x1, P1 ; /* 0x0000590000057a11 */
/* 0x000fe400008f0eff */
/*0370*/ LEA.HI.X.SX32 R3, R6, c[0x0][0x164], 0x1, P0 ; /* 0x0000590006037a11 */
/* 0x000fc600000f0eff */
/*0380*/ LDG.E.U8 R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1100 */
/*0390*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ee8000c1e1100 */
/*03a0*/ STG.E.U8 [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x004fe8000c101104 */
/*03b0*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x008fe2000c101104 */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7encryptPhii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0030*/ LEA.HI R0, R0, c[0x0][0x16c], RZ, 0x1 ; /* 0x00005b0000007a11 */
/* 0x000fe200078f08ff */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e260000002100 */
/*0050*/ SHF.R.S32.HI R5, RZ, 0x1, R0 ; /* 0x00000001ff057819 */
/* 0x000fc80000011400 */
/*0060*/ IABS R0, R5 ; /* 0x0000000500007213 */
/* 0x000fc80000000000 */
/*0070*/ I2F.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e620000209400 */
/*0080*/ IMAD R4, R4, c[0x0][0x0], R7 ; /* 0x0000000004047a24 */
/* 0x001fce00078e0207 */
/*0090*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x002e240000001000 */
/*00a0*/ IADD3 R2, R6, 0xffffffe, RZ ; /* 0x0ffffffe06027810 */
/* 0x001fe40007ffe0ff */
/*00b0*/ IABS R6, R4 ; /* 0x0000000400067213 */
/* 0x000fc80000000000 */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00e0*/ IMAD.MOV R8, RZ, RZ, -R3 ; /* 0x000000ffff087224 */
/* 0x002fc800078e0a03 */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, R8 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0008 */
/*0100*/ IABS R8, R5 ; /* 0x0000000500087213 */
/* 0x000fc60000000000 */
/*0110*/ IMAD R7, R7, R0, RZ ; /* 0x0000000007077224 */
/* 0x000fe400078e02ff */
/*0120*/ IMAD.MOV R9, RZ, RZ, -R8 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a08 */
/*0130*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0140*/ IMAD.HI.U32 R2, R3, R6, RZ ; /* 0x0000000603027227 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD R7, R2, R9, R6 ; /* 0x0000000902077224 */
/* 0x000fe200078e0206 */
/*0160*/ LOP3.LUT R6, R4, R5, RZ, 0x3c, !PT ; /* 0x0000000504067212 */
/* 0x000fc800078e3cff */
/*0170*/ ISETP.GT.U32.AND P2, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe40003f44070 */
/*0180*/ ISETP.GE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fd60003f06270 */
/*0190*/ @!P2 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x000000010707a824 */
/* 0x000fe200078e0a00 */
/*01a0*/ @!P2 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202a810 */
/* 0x000fc80007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe40003f26070 */
/*01c0*/ LOP3.LUT R7, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff077212 */
/* 0x000fd600078e33ff */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc60003f25270 */
/*01f0*/ @!P0 IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff028224 */
/* 0x000fca00078e0a02 */
/*0200*/ SEL R2, R7, R2, !P1 ; /* 0x0000000207027207 */
/* 0x000fca0004800000 */
/*0210*/ IMAD.MOV R6, RZ, RZ, -R2 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a02 */
/*0220*/ IMAD R5, R5, R6, R4 ; /* 0x0000000605057224 */
/* 0x000fc800078e0204 */
/*0230*/ IMAD R6, R2, c[0x0][0x16c], R5 ; /* 0x00005b0002067a24 */
/* 0x000fca00078e0205 */
/*0240*/ IABS R2, R6 ; /* 0x0000000600027213 */
/* 0x000fe40000000000 */
/*0250*/ ISETP.GE.AND P2, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc60003f46270 */
/*0260*/ IMAD.HI.U32 R3, R3, R2, RZ ; /* 0x0000000203037227 */
/* 0x000fc800078e00ff */
/*0270*/ IMAD R3, R3, R9, R2 ; /* 0x0000000903037224 */
/* 0x000fca00078e0202 */
/*0280*/ ISETP.GT.U32.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f04070 */
/*0290*/ @!P0 IMAD.IADD R3, R3, 0x1, -R0 ; /* 0x0000000103038824 */
/* 0x000fca00078e0a00 */
/*02a0*/ ISETP.GT.U32.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f04070 */
/*02b0*/ @!P0 IMAD.IADD R3, R3, 0x1, -R0 ; /* 0x0000000103038824 */
/* 0x000fc800078e0a00 */
/*02c0*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fca00078e0a03 */
/*02d0*/ SEL R3, R7, R3, !P1 ; /* 0x0000000307037207 */
/* 0x000fca0004800000 */
/*02e0*/ IMAD.SHL.U32 R3, R3, 0x2, RZ ; /* 0x0000000203037824 */
/* 0x000fca00078e00ff */
/*02f0*/ LOP3.LUT R3, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff037212 */
/* 0x000fc800078e33ff */
/*0300*/ IADD3 R0, R3, c[0x0][0x16c], R6 ; /* 0x00005b0003007a10 */
/* 0x000fc80007ffe006 */
/*0310*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0320*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0330*/ IADD3 R4, P1, R0, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x000fe20007f3e0ff */
/*0340*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0350*/ IADD3 R2, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006027a10 */
/* 0x000fe40007f1e0ff */
/*0360*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x164], 0x1, P1 ; /* 0x0000590000057a11 */
/* 0x000fe400008f0eff */
/*0370*/ LEA.HI.X.SX32 R3, R6, c[0x0][0x164], 0x1, P0 ; /* 0x0000590006037a11 */
/* 0x000fc600000f0eff */
/*0380*/ LDG.E.U8 R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1100 */
/*0390*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ee8000c1e1100 */
/*03a0*/ STG.E.U8 [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x004fe8000c101104 */
/*03b0*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x008fe2000c101104 */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7RB_SwapPhi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD.WIDE UR4, UR4, 0x55555556, URZ ; /* 0x55555556040478a5 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e260000002100 */
/*0050*/ ULEA.HI UR5, UR5, UR5, URZ, 0x1 ; /* 0x0000000505057291 */
/* 0x000fe2000f8f083f */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GE.AND P0, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fda000bf06270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IMAD R0, R0, 0x3, RZ ; /* 0x0000000300007824 */
/* 0x000fe200078e02ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00b0*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*00c0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f0eff */
/*00d0*/ LDG.E.U8 R7, [R2.64+0x2] ; /* 0x0000020402077981 */
/* 0x000ea8000c1e1100 */
/*00e0*/ LDG.E.U8 R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ee8000c1e1100 */
/*00f0*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x004fe8000c101104 */
/*0100*/ STG.E.U8 [R2.64+0x2], R5 ; /* 0x0000020502007986 */
/* 0x008fe2000c101104 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7RB_SwapPhi
.globl _Z7RB_SwapPhi
.p2align 8
.type _Z7RB_SwapPhi,@function
_Z7RB_SwapPhi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_hi_i32 s2, s3, 0x55555556
s_lshr_b32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshl_add_u32 v0, v1, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x1
global_load_u8 v2, v[0:1], off offset:2
global_load_u8 v3, v[0:1], off
s_waitcnt vmcnt(1)
global_store_b8 v[0:1], v2, off
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v3, off offset:2
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7RB_SwapPhi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7RB_SwapPhi, .Lfunc_end0-_Z7RB_SwapPhi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7encryptPhii
.globl _Z7encryptPhii
.p2align 8
.type _Z7encryptPhii,@function
_Z7encryptPhii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s3, 31
s_and_b32 s4, s4, 0xffff
s_add_i32 s5, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_ashr_i32 s6, s5, 1
s_ashr_i32 s5, s5, 31
s_add_i32 s7, s6, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s7, s7, s5
v_cvt_f32_u32_e32 v1, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_sub_i32 s4, 0, s7
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s5, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v0
v_mul_hi_u32 v0, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v0, s7
v_sub_nc_u32_e32 v4, v4, v5
v_add_nc_u32_e32 v5, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v6, s7, v4
v_cmp_le_u32_e32 vcc_lo, s7, v4
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v4, v4, v6 :: v_dual_add_nc_u32 v5, 1, v0
v_cmp_le_u32_e32 vcc_lo, s7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v0, v2
v_mul_lo_u32 v0, v4, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v1, v0
v_mad_u64_u32 v[0:1], null, v4, s3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v1
v_mul_hi_u32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, s7
v_sub_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s7, v2
v_cmp_le_u32_e32 vcc_lo, s7, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s7, v2
v_cmp_le_u32_e32 vcc_lo, s7, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v1
v_sub_nc_u32_e32 v1, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 1, v1
v_not_b32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v1, v0, s3, v1
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_clause 0x1
global_load_u8 v0, v[1:2], off
global_load_u8 v5, v[3:4], off
s_waitcnt vmcnt(1)
global_store_b8 v[3:4], v0, off
s_waitcnt vmcnt(0)
global_store_b8 v[1:2], v5, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7encryptPhii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7encryptPhii, .Lfunc_end1-_Z7encryptPhii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7decryptPhii
.globl _Z7decryptPhii
.p2align 8
.type _Z7decryptPhii,@function
_Z7decryptPhii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s3, 31
s_and_b32 s4, s4, 0xffff
s_add_i32 s5, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_ashr_i32 s6, s5, 1
s_ashr_i32 s5, s5, 31
s_add_i32 s7, s6, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s7, s7, s5
v_cvt_f32_u32_e32 v1, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_sub_i32 s4, 0, s7
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s5, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v0
v_mul_hi_u32 v0, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v0, s7
v_sub_nc_u32_e32 v4, v4, v5
v_add_nc_u32_e32 v5, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v6, s7, v4
v_cmp_le_u32_e32 vcc_lo, s7, v4
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v4, v4, v6 :: v_dual_add_nc_u32 v5, 1, v0
v_cmp_le_u32_e32 vcc_lo, s7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v0, v2
v_mul_lo_u32 v0, v4, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v1, v0
v_mad_u64_u32 v[0:1], null, v4, s3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v1
v_mul_hi_u32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, s7
v_sub_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s7, v2
v_cmp_le_u32_e32 vcc_lo, s7, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s7, v2
v_cmp_le_u32_e32 vcc_lo, s7, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v1
v_sub_nc_u32_e32 v1, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 1, v1
v_not_b32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v1, v0, s3, v1
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_clause 0x1
global_load_u8 v0, v[1:2], off
global_load_u8 v5, v[3:4], off
s_waitcnt vmcnt(1)
global_store_b8 v[3:4], v0, off
s_waitcnt vmcnt(0)
global_store_b8 v[1:2], v5, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7decryptPhii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z7decryptPhii, .Lfunc_end2-_Z7decryptPhii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7RB_SwapPhi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7RB_SwapPhi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7encryptPhii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7encryptPhii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7decryptPhii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7decryptPhii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011bf8b_00000000-6_parallel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z7RB_SwapPhiPhi
.type _Z27__device_stub__Z7RB_SwapPhiPhi, @function
_Z27__device_stub__Z7RB_SwapPhiPhi:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7RB_SwapPhi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z27__device_stub__Z7RB_SwapPhiPhi, .-_Z27__device_stub__Z7RB_SwapPhiPhi
.globl _Z7RB_SwapPhi
.type _Z7RB_SwapPhi, @function
_Z7RB_SwapPhi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7RB_SwapPhiPhi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7RB_SwapPhi, .-_Z7RB_SwapPhi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "wb"
.LC1:
.string "\nERROR: Cannot open file %s"
.text
.globl _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER
.type _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER, @function
_Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, %r12
movq %rdx, %r14
movq %rcx, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L16
movq %rax, %rbp
movq %rax, %rcx
movl $1, %edx
movl $14, %esi
movq %r14, %rdi
call fwrite@PLT
movq %rbp, %rcx
movl $1, %edx
movl $40, %esi
movq %rbx, %rdi
call fwrite@PLT
movslq 20(%rbx), %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movslq 20(%rbx), %rdx
movl $1, %ecx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 20(%rbx), %edx
leal 1023(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $10, %eax
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movslq 20(%rbx), %rdx
movl $2, %ecx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movslq 20(%rbx), %rsi
movq %rbp, %rcx
movl $1, %edx
movq %r12, %rdi
call fwrite@PLT
movq %rbp, %rdi
call fclose@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq %r13, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L17:
movl 20(%rbx), %esi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z7RB_SwapPhiPhi
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER, .-_Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER
.section .rodata.str1.1
.LC2:
.string "rb"
.LC3:
.string "Load Swap Time: %fms\n"
.text
.globl _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER
.type _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER, @function
_Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %rbp
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC2(%rip), %rsi
call fopen@PLT
movq %rax, %rbx
testq %rax, %rax
je .L25
movq %rax, %r8
movl $1, %ecx
movl $14, %edx
movq $-1, %rsi
movq %r12, %rdi
call __fread_chk@PLT
cmpw $19778, (%r12)
jne .L27
movq %rbx, %r8
movl $1, %ecx
movl $40, %edx
movq $-1, %rsi
movq %rbp, %rdi
call __fread_chk@PLT
movslq 10(%r12), %rsi
movl $0, %edx
movq %rbx, %rdi
call fseek@PLT
movslq 20(%rbp), %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
testq %rax, %rax
je .L28
movq %rbx, %r8
movq %r13, %rcx
movl $1, %edx
movq %r13, %rsi
movq %rax, %rdi
call __fread_chk@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movslq 20(%rbp), %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movslq 20(%rbp), %rdx
movl $1, %ecx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl 20(%rbp), %eax
leal 1023(%rax), %r13d
testl %eax, %eax
cmovns %eax, %r13d
sarl $10, %r13d
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %r13d, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L23:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
movslq 20(%rbp), %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq 44(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq %rbx, %rdi
call fclose@PLT
.L19:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movq %r12, %rax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq %rbx, %rdi
call fclose@PLT
movl $0, %r12d
jmp .L19
.L28:
movq %rbx, %rdi
call fclose@PLT
jmp .L19
.L29:
movl 20(%rbp), %esi
movq 24(%rsp), %rdi
call _Z27__device_stub__Z7RB_SwapPhiPhi
jmp .L23
.L25:
movq %rax, %r12
jmp .L19
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER, .-_Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER
.globl _Z28__device_stub__Z7encryptPhiiPhii
.type _Z28__device_stub__Z7encryptPhiiPhii, @function
_Z28__device_stub__Z7encryptPhiiPhii:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7encryptPhii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z28__device_stub__Z7encryptPhiiPhii, .-_Z28__device_stub__Z7encryptPhiiPhii
.globl _Z7encryptPhii
.type _Z7encryptPhii, @function
_Z7encryptPhii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7encryptPhiiPhii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7encryptPhii, .-_Z7encryptPhii
.globl _Z28__device_stub__Z7decryptPhiiPhii
.type _Z28__device_stub__Z7decryptPhiiPhii, @function
_Z28__device_stub__Z7decryptPhiiPhii:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L43
.L39:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7decryptPhii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L39
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z28__device_stub__Z7decryptPhiiPhii, .-_Z28__device_stub__Z7decryptPhiiPhii
.globl _Z7decryptPhii
.type _Z7decryptPhii, @function
_Z7decryptPhii:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7decryptPhiiPhii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z7decryptPhii, .-_Z7decryptPhii
.section .rodata.str1.1
.LC4:
.string "mona_lisa.bmp"
.LC5:
.string "%d\n"
.LC6:
.string "Host to Device Time: %fms\n"
.LC7:
.string "Encryption Time: %fms\n"
.LC8:
.string "Device to Host Time: %fms\n"
.LC9:
.string "Encrypted.bmp"
.LC10:
.string "Decryption Time: %fms\n"
.LC11:
.string "Decrypted.bmp"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $136, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 66(%rsp), %rdx
leaq 80(%rsp), %rsi
leaq .LC4(%rip), %rdi
call _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER
movq %rax, %rbp
movl 100(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movslq 100(%rsp), %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movslq 100(%rsp), %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 8(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 100(%rsp), %eax
leal 1023(%rax), %ebx
testl %eax, %eax
cmovns %eax, %ebx
sarl $10, %ebx
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %ebx, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L48:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movslq 100(%rsp), %rdx
movl $2, %ecx
movq 32(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 80(%rsp), %r12
leaq 66(%rsp), %r13
movq %r12, %rcx
movq %r13, %rdx
movq %rbp, %rsi
leaq .LC9(%rip), %rbp
movq %rbp, %rdi
call _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER
movq %rax, %rbp
movslq 100(%rsp), %rdx
movl $1, %ecx
movq %rax, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %ebx, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L49:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 52(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq 100(%rsp), %rdx
movl $2, %ecx
movq 32(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rcx
leaq 66(%rsp), %rdx
movq %rbp, %rsi
leaq .LC11(%rip), %rdi
call _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L54
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movl $8000, %edx
movl 100(%rsp), %esi
movq 32(%rsp), %rdi
call _Z28__device_stub__Z7encryptPhiiPhii
jmp .L48
.L53:
movl $8000, %edx
movl 100(%rsp), %esi
movq 32(%rsp), %rdi
call _Z28__device_stub__Z7decryptPhiiPhii
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z7decryptPhii"
.LC13:
.string "_Z7encryptPhii"
.LC14:
.string "_Z7RB_SwapPhi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z7decryptPhii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z7encryptPhii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z7RB_SwapPhi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "parallel.hip"
.globl _Z22__device_stub__RB_SwapPhi # -- Begin function _Z22__device_stub__RB_SwapPhi
.p2align 4, 0x90
.type _Z22__device_stub__RB_SwapPhi,@function
_Z22__device_stub__RB_SwapPhi: # @_Z22__device_stub__RB_SwapPhi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7RB_SwapPhi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__RB_SwapPhi, .Lfunc_end0-_Z22__device_stub__RB_SwapPhi
.cfi_endproc
# -- End function
.globl _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER # -- Begin function _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER
.p2align 4, 0x90
.type _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER,@function
_Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER: # @_Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r15
movq %rsi, %r14
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB1_7
# %bb.1:
movq %rax, %rbx
movl $14, %esi
movl $1, %edx
movq %r15, %rdi
movq %rax, %rcx
callq fread
movzwl (%r15), %eax
cmpl $19778, %eax # imm = 0x4D42
jne .LBB1_6
# %bb.2:
movl $40, %esi
movl $1, %edx
movq %r14, %rdi
movq %rbx, %rcx
callq fread
movslq 10(%r15), %rsi
movq %rbx, %rdi
xorl %edx, %edx
callq fseek
movslq 20(%r14), %r15
movq %r15, %rdi
callq malloc
testq %rax, %rax
je .LBB1_6
# %bb.3:
movl $1, %esi
movq %rax, %rdi
movq %r15, %rdx
movq %rbx, %rcx
movq %rax, %r15
callq fread
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movslq 20(%r14), %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movq 8(%rsp), %rdi
movslq 20(%r14), %rdx
movq %r15, %r12
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl 20(%r14), %eax
leal 1023(%rax), %r15d
testl %eax, %eax
cmovnsl %eax, %r15d
sarl $10, %r15d
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r15
orq $1024, %rdx # imm = 0x400
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 8(%rsp), %rax
movl 20(%r14), %ecx
movq %rax, 96(%rsp)
movl %ecx, 28(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 28(%rsp), %rax
movq %rax, 40(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z7RB_SwapPhi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movslq 20(%r14), %rdx
movq %r12, %r14
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
movq %rbx, %rdi
callq fclose
movq %r12, %rax
jmp .LBB1_8
.LBB1_6:
movq %rbx, %rdi
callq fclose
.LBB1_7:
xorl %eax, %eax
.LBB1_8:
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER, .Lfunc_end1-_Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER
.cfi_endproc
# -- End function
.globl _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER # -- Begin function _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER
.p2align 4, 0x90
.type _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER,@function
_Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER: # @_Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %r14
movq %rdx, %r12
movq %rsi, %rbx
movq %rdi, %r13
movl $.L.str.2, %esi
callq fopen
testq %rax, %rax
je .LBB2_4
# %bb.1:
movq %rax, %r15
movl $14, %esi
movl $1, %edx
movq %r12, %rdi
movq %rax, %rcx
callq fwrite
movl $40, %esi
movl $1, %edx
movq %r14, %rdi
movq %r15, %rcx
callq fwrite
movslq 20(%r14), %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movq 8(%rsp), %rdi
movslq 20(%r14), %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl 20(%r14), %eax
leal 1023(%rax), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_3
# %bb.2:
movq 8(%rsp), %rax
movl 20(%r14), %ecx
movq %rax, 72(%rsp)
movl %ecx, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7RB_SwapPhi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_3:
movq 8(%rsp), %rsi
movslq 20(%r14), %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movslq 20(%r14), %rsi
movl $1, %edx
movq %rbx, %rdi
movq %r15, %rcx
callq fwrite
movq %r15, %rdi
callq fclose
addq $96, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_4:
.cfi_def_cfa_offset 144
movl $.L.str.3, %edi
movq %r13, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER, .Lfunc_end2-_Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER
.cfi_endproc
# -- End function
.globl _Z22__device_stub__encryptPhii # -- Begin function _Z22__device_stub__encryptPhii
.p2align 4, 0x90
.type _Z22__device_stub__encryptPhii,@function
_Z22__device_stub__encryptPhii: # @_Z22__device_stub__encryptPhii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7encryptPhii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z22__device_stub__encryptPhii, .Lfunc_end3-_Z22__device_stub__encryptPhii
.cfi_endproc
# -- End function
.globl _Z22__device_stub__decryptPhii # -- Begin function _Z22__device_stub__decryptPhii
.p2align 4, 0x90
.type _Z22__device_stub__decryptPhii,@function
_Z22__device_stub__decryptPhii: # @_Z22__device_stub__decryptPhii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7decryptPhii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z22__device_stub__decryptPhii, .Lfunc_end4-_Z22__device_stub__decryptPhii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294968320, %rbx # imm = 0x100000400
leaq 160(%rsp), %rsi
leaq 146(%rsp), %rdx
movl $.L.str.4, %edi
callq _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER
movq %rax, %r14
movslq 180(%rsp), %r15
movl $.L.str.5, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 104(%rsp), %rdi
callq hipEventElapsedTime
movss 104(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
leal 1023(%r15), %r12d
testq %r15, %r15
cmovnsl %r15d, %r12d
sarl $10, %r12d
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
addq %rbx, %r12
addq $-1024, %r12 # imm = 0xFC00
movq %r12, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 24(%rsp), %rax
movq %rax, 88(%rsp)
movl %r15d, 36(%rsp)
movl $8000, 32(%rsp) # imm = 0x1F40
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7encryptPhii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 108(%rsp), %rdi
callq hipEventElapsedTime
movss 108(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 100(%rsp), %rdi
callq hipEventElapsedTime
movss 100(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
leaq 146(%rsp), %r15
leaq 160(%rsp), %r13
movl $.L.str.9, %edi
movq %r14, %rsi
movq %r15, %rdx
movq %r13, %rcx
callq _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER
movl $.L.str.9, %edi
movq %r13, %rsi
movq %r15, %rdx
callq _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER
movq %rax, %r14
movq 24(%rsp), %rdi
movl 180(%rsp), %ebp
movslq %ebp, %r15
movq %rax, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r12, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_4
# %bb.3:
movq 24(%rsp), %rax
movq %rax, 88(%rsp)
movl %ebp, 36(%rsp)
movl $8000, 32(%rsp) # imm = 0x1F40
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7decryptPhii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
movss 112(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 146(%rsp), %rdx
leaq 160(%rsp), %rcx
movl $.L.str.11, %edi
movq %r14, %rsi
callq _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7RB_SwapPhi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7encryptPhii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7decryptPhii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7RB_SwapPhi,@object # @_Z7RB_SwapPhi
.section .rodata,"a",@progbits
.globl _Z7RB_SwapPhi
.p2align 3, 0x0
_Z7RB_SwapPhi:
.quad _Z22__device_stub__RB_SwapPhi
.size _Z7RB_SwapPhi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "rb"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Load Swap Time: %fms\n"
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "wb"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\nERROR: Cannot open file %s"
.size .L.str.3, 28
.type _Z7encryptPhii,@object # @_Z7encryptPhii
.section .rodata,"a",@progbits
.globl _Z7encryptPhii
.p2align 3, 0x0
_Z7encryptPhii:
.quad _Z22__device_stub__encryptPhii
.size _Z7encryptPhii, 8
.type _Z7decryptPhii,@object # @_Z7decryptPhii
.globl _Z7decryptPhii
.p2align 3, 0x0
_Z7decryptPhii:
.quad _Z22__device_stub__decryptPhii
.size _Z7decryptPhii, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "mona_lisa.bmp"
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d\n"
.size .L.str.5, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Host to Device Time: %fms\n"
.size .L.str.6, 27
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Encryption Time: %fms\n"
.size .L.str.7, 23
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Device to Host Time: %fms\n"
.size .L.str.8, 27
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Encrypted.bmp"
.size .L.str.9, 14
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Decryption Time: %fms\n"
.size .L.str.10, 23
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Decrypted.bmp"
.size .L.str.11, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7RB_SwapPhi"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7encryptPhii"
.size .L__unnamed_2, 15
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7decryptPhii"
.size .L__unnamed_3, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__RB_SwapPhi
.addrsig_sym _Z22__device_stub__encryptPhii
.addrsig_sym _Z22__device_stub__decryptPhii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7RB_SwapPhi
.addrsig_sym _Z7encryptPhii
.addrsig_sym _Z7decryptPhii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void subDiffuseKernel(float *data, int x, int y, float pressure)
{
data[NX * x + y] -= pressure;
} | code for sm_80
Function : _Z16subDiffuseKernelPfiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ HFMA2.MMA R3, -RZ, RZ, 0, 1.31130218505859375e-06 ; /* 0x00000016ff037435 */
/* 0x000fe200000001ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fce0000000f00 */
/*0050*/ IMAD R2, R2, R3, c[0x0][0x16c] ; /* 0x00005b0002027624 */
/* 0x000fc800078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ FADD R5, R0, -c[0x0][0x170] ; /* 0x80005c0000057621 */
/* 0x004fca0000000000 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void subDiffuseKernel(float *data, int x, int y, float pressure)
{
data[NX * x + y] -= pressure;
} | .file "tmpxft_000abe2e_00000000-6_subDiffuseKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16subDiffuseKernelPfiifPfiif
.type _Z39__device_stub__Z16subDiffuseKernelPfiifPfiif, @function
_Z39__device_stub__Z16subDiffuseKernelPfiifPfiif:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16subDiffuseKernelPfiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z16subDiffuseKernelPfiifPfiif, .-_Z39__device_stub__Z16subDiffuseKernelPfiifPfiif
.globl _Z16subDiffuseKernelPfiif
.type _Z16subDiffuseKernelPfiif, @function
_Z16subDiffuseKernelPfiif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16subDiffuseKernelPfiifPfiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16subDiffuseKernelPfiif, .-_Z16subDiffuseKernelPfiif
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16subDiffuseKernelPfiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16subDiffuseKernelPfiif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void subDiffuseKernel(float *data, int x, int y, float pressure)
{
data[NX * x + y] -= pressure;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void subDiffuseKernel(float *data, int x, int y, float pressure)
{
data[NX * x + y] -= pressure;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void subDiffuseKernel(float *data, int x, int y, float pressure)
{
data[NX * x + y] -= pressure;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16subDiffuseKernelPfiif
.globl _Z16subDiffuseKernelPfiif
.p2align 8
.type _Z16subDiffuseKernelPfiif,@function
_Z16subDiffuseKernelPfiif:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s6, 22
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s7
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v1, s3, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16subDiffuseKernelPfiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16subDiffuseKernelPfiif, .Lfunc_end0-_Z16subDiffuseKernelPfiif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16subDiffuseKernelPfiif
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z16subDiffuseKernelPfiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void subDiffuseKernel(float *data, int x, int y, float pressure)
{
data[NX * x + y] -= pressure;
} | .text
.file "subDiffuseKernel.hip"
.globl _Z31__device_stub__subDiffuseKernelPfiif # -- Begin function _Z31__device_stub__subDiffuseKernelPfiif
.p2align 4, 0x90
.type _Z31__device_stub__subDiffuseKernelPfiif,@function
_Z31__device_stub__subDiffuseKernelPfiif: # @_Z31__device_stub__subDiffuseKernelPfiif
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16subDiffuseKernelPfiif, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__subDiffuseKernelPfiif, .Lfunc_end0-_Z31__device_stub__subDiffuseKernelPfiif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16subDiffuseKernelPfiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16subDiffuseKernelPfiif,@object # @_Z16subDiffuseKernelPfiif
.section .rodata,"a",@progbits
.globl _Z16subDiffuseKernelPfiif
.p2align 3, 0x0
_Z16subDiffuseKernelPfiif:
.quad _Z31__device_stub__subDiffuseKernelPfiif
.size _Z16subDiffuseKernelPfiif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16subDiffuseKernelPfiif"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__subDiffuseKernelPfiif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16subDiffuseKernelPfiif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16subDiffuseKernelPfiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ HFMA2.MMA R3, -RZ, RZ, 0, 1.31130218505859375e-06 ; /* 0x00000016ff037435 */
/* 0x000fe200000001ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fce0000000f00 */
/*0050*/ IMAD R2, R2, R3, c[0x0][0x16c] ; /* 0x00005b0002027624 */
/* 0x000fc800078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ FADD R5, R0, -c[0x0][0x170] ; /* 0x80005c0000057621 */
/* 0x004fca0000000000 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16subDiffuseKernelPfiif
.globl _Z16subDiffuseKernelPfiif
.p2align 8
.type _Z16subDiffuseKernelPfiif,@function
_Z16subDiffuseKernelPfiif:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s6, 22
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s7
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v1, s3, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16subDiffuseKernelPfiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16subDiffuseKernelPfiif, .Lfunc_end0-_Z16subDiffuseKernelPfiif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16subDiffuseKernelPfiif
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z16subDiffuseKernelPfiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000abe2e_00000000-6_subDiffuseKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16subDiffuseKernelPfiifPfiif
.type _Z39__device_stub__Z16subDiffuseKernelPfiifPfiif, @function
_Z39__device_stub__Z16subDiffuseKernelPfiifPfiif:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16subDiffuseKernelPfiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z16subDiffuseKernelPfiifPfiif, .-_Z39__device_stub__Z16subDiffuseKernelPfiifPfiif
.globl _Z16subDiffuseKernelPfiif
.type _Z16subDiffuseKernelPfiif, @function
_Z16subDiffuseKernelPfiif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16subDiffuseKernelPfiifPfiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16subDiffuseKernelPfiif, .-_Z16subDiffuseKernelPfiif
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16subDiffuseKernelPfiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16subDiffuseKernelPfiif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "subDiffuseKernel.hip"
.globl _Z31__device_stub__subDiffuseKernelPfiif # -- Begin function _Z31__device_stub__subDiffuseKernelPfiif
.p2align 4, 0x90
.type _Z31__device_stub__subDiffuseKernelPfiif,@function
_Z31__device_stub__subDiffuseKernelPfiif: # @_Z31__device_stub__subDiffuseKernelPfiif
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16subDiffuseKernelPfiif, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__subDiffuseKernelPfiif, .Lfunc_end0-_Z31__device_stub__subDiffuseKernelPfiif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16subDiffuseKernelPfiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16subDiffuseKernelPfiif,@object # @_Z16subDiffuseKernelPfiif
.section .rodata,"a",@progbits
.globl _Z16subDiffuseKernelPfiif
.p2align 3, 0x0
_Z16subDiffuseKernelPfiif:
.quad _Z31__device_stub__subDiffuseKernelPfiif
.size _Z16subDiffuseKernelPfiif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16subDiffuseKernelPfiif"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__subDiffuseKernelPfiif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16subDiffuseKernelPfiif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
/* demo to show the usage of share memory*/
#define DEBUG
typedef float dataType;
void checkCudaError(cudaError_t error, const char* filename, const int linenum)
{
if(error != cudaSuccess){
printf("File: %s, line: %d, CUDA error: %s\n", filename, linenum, cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
}
#define CHECK_CUDA_ERROR(error) checkCudaError(error, __FILE__, __LINE__)
#define BLOCK_SIZE 16
typedef struct Matrix
{
int width;
int height;
int stride;
dataType* element;
}Matrix;
__device__ dataType getElement(Matrix x, int row, int col)
{
return x.element[row * x.stride + col];
}
__device__ void setElement(Matrix x, int row, int col, dataType val)
{
x.element[col + row * x.stride] = val;
}
__device__ Matrix getSubMatrix(Matrix x, int row, int col)
{
Matrix subX;
int row_ = (row + 1) * BLOCK_SIZE, col_ = (col + 1) * BLOCK_SIZE;
subX.height = ((row_ <= x.height) ? BLOCK_SIZE : x.height%BLOCK_SIZE);
subX.width = ((col_ <= x.width) ? BLOCK_SIZE : x.width%BLOCK_SIZE);
//subX.height = subX.width = BLOCK_SIZE;
subX.stride = x.stride;
subX.element = &x.element[x.stride * row * BLOCK_SIZE + col * BLOCK_SIZE];
return subX;
}
__device__ int divCeil(int x, int y)
{
return (x%y == 0) ? x/y : (x/y+1);
}
// no shared memory
__global__ void MatMulKernel(Matrix x, Matrix y, Matrix z)
{
int col = threadIdx.x + blockIdx.x * blockDim.x;
int row = threadIdx.y + blockIdx.y * blockDim.y;
dataType ret = 0;
int i = 0;
if(col < z.width && row < z.height){
for(i = 0; i < x.width; ++i)
ret += getElement(x, row, i) * getElement(y, i, col);
setElement(z, row, col, ret);
}
}
// shared memory
__global__ void MatMulSharedMemory1(Matrix x, Matrix y, Matrix z)
{
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
Matrix subZ = getSubMatrix(z, blockRow, blockCol);
int row = threadIdx.y;
int col = threadIdx.x;
if(row >= subZ.height || col >= subZ.width)
return;
dataType val = 0.0;
int i = 0;
int size = divCeil(x.width, BLOCK_SIZE);
for(; i < size; ++i){
Matrix subX = getSubMatrix(x, blockRow, i);
Matrix subY = getSubMatrix(y, i, blockCol);
__shared__ dataType tmpX[BLOCK_SIZE][BLOCK_SIZE];
__shared__ dataType tmpY[BLOCK_SIZE][BLOCK_SIZE];
tmpX[row][col] = getElement(subX, row, col);
tmpY[row][col] = getElement(subY, row, col);
__syncthreads();
int j = 0;
for(;j < subX.width; ++j)
val += tmpX[row][j] * tmpY[j][col];
__syncthreads();
}
setElement(subZ, row, col, val);
}
bool checkCorrectness(Matrix x, Matrix y, Matrix z)
{
Matrix z_;
z_.width = z.width;
z_.height = z.height;
z_.stride = z.stride;
z_.element = (dataType*)malloc(sizeof(dataType) * z_.width * z_.height);
for(int i = 0; i < z_.height; ++i){
for(int j = 0; j < z_.width; ++j){
dataType val = 0;
for(int k = 0; k < x.width; ++k)
val += x.element[i*x.stride+k] * y.element[k*y.stride+j];
z_.element[j + i * z_.stride] = val;
}
}
bool flag;
if(memcmp(z_.element, z.element, z_.width * z_.height * sizeof(dataType)) == 0)
flag = true;
else
flag = false;
free(z_.element);
return flag;
}
void MatMul(Matrix x, Matrix y, Matrix z)
{
Matrix dev_x, dev_y, dev_z;
dev_x.width = x.width;
dev_x.height = x.height;
dev_x.stride = x.stride;
dev_y.width = y.width;
dev_y.height = y.height;
dev_y.stride = y.stride;
dev_z.width = z.width;
dev_z.height = z.height;
dev_z.stride = z.stride;
int nByte = sizeof(dataType) * dev_x.width * dev_x.height;
CHECK_CUDA_ERROR(cudaMalloc((void**)(&dev_x.element), nByte));
CHECK_CUDA_ERROR(cudaMemcpy(dev_x.element, x.element, nByte, cudaMemcpyHostToDevice));
nByte = sizeof(dataType) * dev_y.width * dev_y.height;
CHECK_CUDA_ERROR(cudaMalloc((void**)&dev_y.element, nByte));
CHECK_CUDA_ERROR(cudaMemcpy(dev_y.element, y.element, nByte, cudaMemcpyHostToDevice));
nByte = sizeof(dataType) * dev_z.width * dev_z.height;
CHECK_CUDA_ERROR(cudaMalloc((void**)&dev_z.element, nByte));
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(dev_z.width/dimBlock.x + (dev_z.width%dimBlock.x == 0 ? 0 : 1), dev_z.height/dimBlock.y + (dev_z.height%dimBlock.y == 0 ? 0 : 1));
//MatMulKernel<<<dimGrid, dimBlock>>>(dev_x, dev_y, dev_z);
MatMulSharedMemory1<<<dimGrid, dimBlock>>>(dev_x, dev_y, dev_z);
CHECK_CUDA_ERROR(cudaMemcpy(z.element, dev_z.element, nByte, cudaMemcpyDeviceToHost));
if(checkCorrectness(x, y, z) == false)
printf("Error occur\n");
else
printf("Correct\n");
CHECK_CUDA_ERROR(cudaFree(dev_x.element));
CHECK_CUDA_ERROR(cudaFree(dev_y.element));
CHECK_CUDA_ERROR(cudaFree(dev_z.element));
}
void randomFillMatrix(Matrix x)
{
int size = x.width*x.height;
for(int i = 0; i < size; ++i){
srand(time(NULL)+i);
x.element[i] = rand()%100;
}
}
int main(void)
{
Matrix x, y, z;
x.width = x.height = x.stride = 32;
y.width = y.height = y.stride = 32;
z.width = z.height = z.stride = 32;
int nByte = sizeof(dataType) * x.width * x. height;
x.element = (dataType*)malloc(nByte);
y.element = (dataType*)malloc(nByte);
z.element = (dataType*)malloc(nByte);
randomFillMatrix(x);
randomFillMatrix(y);
MatMul(x, y, z);
free(x.element);
free(y.element);
free(z.element);
return 0;
} | .file "tmpxft_0015e3ec_00000000-6_MatMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "File: %s, line: %d, CUDA error: %s\n"
.text
.globl _Z14checkCudaError9cudaErrorPKci
.type _Z14checkCudaError9cudaErrorPKci, @function
_Z14checkCudaError9cudaErrorPKci:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebp, %ecx
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14checkCudaError9cudaErrorPKci, .-_Z14checkCudaError9cudaErrorPKci
.globl _Z10getElement6Matrixii
.type _Z10getElement6Matrixii, @function
_Z10getElement6Matrixii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z10getElement6Matrixii, .-_Z10getElement6Matrixii
.globl _Z10setElement6Matrixiif
.type _Z10setElement6Matrixiif, @function
_Z10setElement6Matrixiif:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z10setElement6Matrixiif, .-_Z10setElement6Matrixiif
.globl _Z12getSubMatrix6Matrixii
.type _Z12getSubMatrix6Matrixii, @function
_Z12getSubMatrix6Matrixii:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z12getSubMatrix6Matrixii, .-_Z12getSubMatrix6Matrixii
.globl _Z7divCeilii
.type _Z7divCeilii, @function
_Z7divCeilii:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z7divCeilii, .-_Z7divCeilii
.globl _Z16checkCorrectness6MatrixS_S_
.type _Z16checkCorrectness6MatrixS_S_, @function
_Z16checkCorrectness6MatrixS_S_:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl 112(%rsp), %ebx
movl 160(%rsp), %r12d
movl 164(%rsp), %r14d
movl %r14d, 4(%rsp)
movl 168(%rsp), %r15d
movslq %r12d, %rbp
movslq %r14d, %rax
imulq %rbp, %rax
salq $2, %rax
movq %rax, 40(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
testl %r14d, %r14d
jle .L18
movq 128(%rsp), %r14
movq 152(%rsp), %rax
movq %rax, 24(%rsp)
movl 120(%rsp), %eax
movl %eax, 16(%rsp)
movslq 144(%rsp), %rsi
salq $2, %rsi
movl $0, %r13d
movl $0, %r11d
movl $0, %edx
movslq %ebx, %rax
movq %rax, 32(%rsp)
movl %r12d, 20(%rsp)
jmp .L19
.L20:
movss (%rax), %xmm0
mulss (%rcx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %rsi, %rcx
cmpq %rdi, %rax
jne .L20
.L22:
movss %xmm1, (%r10,%r8,4)
addq $1, %r8
addq $4, %r9
cmpq %r8, %rbp
je .L21
.L23:
movq %r9, %rcx
movq %r12, %rax
pxor %xmm1, %xmm1
testl %ebx, %ebx
jg .L20
jmp .L22
.L21:
addl $1, %edx
addl %r15d, %r11d
movl 16(%rsp), %eax
addl %eax, %r13d
cmpl %edx, 4(%rsp)
je .L18
.L19:
cmpl $0, 20(%rsp)
jle .L21
movq 24(%rsp), %r9
movslq %r13d, %rax
leaq (%r14,%rax,4), %r12
movq 32(%rsp), %rdi
addq %rdi, %rax
leaq (%r14,%rax,4), %rdi
movslq %r11d, %rax
movq 8(%rsp), %rcx
leaq (%rcx,%rax,4), %r10
movl $0, %r8d
jmp .L23
.L18:
movq 40(%rsp), %rdx
movq 176(%rsp), %rsi
movq 8(%rsp), %r15
movq %r15, %rdi
call memcmp@PLT
movl %eax, %ebx
movq %r15, %rdi
call free@PLT
testl %ebx, %ebx
sete %al
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z16checkCorrectness6MatrixS_S_, .-_Z16checkCorrectness6MatrixS_S_
.globl _Z16randomFillMatrix6Matrix
.type _Z16randomFillMatrix6Matrix, @function
_Z16randomFillMatrix6Matrix:
.LFB2064:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl 32(%rsp), %ebp
imull 36(%rsp), %ebp
testl %ebp, %ebp
jle .L30
movslq %ebp, %rbp
movl $0, %ebx
.L32:
movl $0, %edi
call time@PLT
leal (%rax,%rbx), %edi
call srand@PLT
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movq 48(%rsp), %rax
movss %xmm0, (%rax,%rbx,4)
addq $1, %rbx
cmpq %rbp, %rbx
jne .L32
.L30:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _Z16randomFillMatrix6Matrix, .-_Z16randomFillMatrix6Matrix
.globl _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
.type _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_, @function
_Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_:
.LFB2090:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_, .-_Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
.globl _Z12MatMulKernel6MatrixS_S_
.type _Z12MatMulKernel6MatrixS_S_, @function
_Z12MatMulKernel6MatrixS_S_:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 64(%rsp), %rdx
leaq 40(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z12MatMulKernel6MatrixS_S_, .-_Z12MatMulKernel6MatrixS_S_
.globl _Z48__device_stub__Z19MatMulSharedMemory16MatrixS_S_R6MatrixS0_S0_
.type _Z48__device_stub__Z19MatMulSharedMemory16MatrixS_S_R6MatrixS0_S0_, @function
_Z48__device_stub__Z19MatMulSharedMemory16MatrixS_S_R6MatrixS0_S0_:
.LFB2092:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z19MatMulSharedMemory16MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z48__device_stub__Z19MatMulSharedMemory16MatrixS_S_R6MatrixS0_S0_, .-_Z48__device_stub__Z19MatMulSharedMemory16MatrixS_S_R6MatrixS0_S0_
.globl _Z19MatMulSharedMemory16MatrixS_S_
.type _Z19MatMulSharedMemory16MatrixS_S_, @function
_Z19MatMulSharedMemory16MatrixS_S_:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 64(%rsp), %rdx
leaq 40(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z48__device_stub__Z19MatMulSharedMemory16MatrixS_S_R6MatrixS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z19MatMulSharedMemory16MatrixS_S_, .-_Z19MatMulSharedMemory16MatrixS_S_
.section .rodata.str1.8
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/shaoguangcheng/ToyCode/master/cpp/cuda/MatMul.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Error occur\n"
.LC4:
.string "Correct\n"
.text
.globl _Z6MatMul6MatrixS_S_
.type _Z6MatMul6MatrixS_S_, @function
_Z6MatMul6MatrixS_S_:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $232, %rsp
.cfi_def_cfa_offset 256
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
movl 256(%rsp), %ebx
movl %ebx, 32(%rsp)
movl 260(%rsp), %eax
movl %eax, 36(%rsp)
movl 264(%rsp), %edx
movl %edx, 40(%rsp)
movl 280(%rsp), %edx
movl %edx, 64(%rsp)
movl 284(%rsp), %edx
movl %edx, 68(%rsp)
movl 288(%rsp), %edx
movl %edx, 72(%rsp)
movl 304(%rsp), %edx
movl %edx, 96(%rsp)
movl 308(%rsp), %edx
movl %edx, 100(%rsp)
movl 312(%rsp), %edx
movl %edx, 104(%rsp)
imull %eax, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 48(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $165, %edx
leaq .LC2(%rip), %rbp
movq %rbp, %rsi
call _Z14checkCudaError9cudaErrorPKci
movl $1, %ecx
movq %rbx, %rdx
movq 272(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $166, %edx
movq %rbp, %rsi
call _Z14checkCudaError9cudaErrorPKci
movl 68(%rsp), %ebx
imull 64(%rsp), %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $169, %edx
movq %rbp, %rsi
call _Z14checkCudaError9cudaErrorPKci
movl $1, %ecx
movq %rbx, %rdx
movq 296(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $170, %edx
movq %rbp, %rsi
call _Z14checkCudaError9cudaErrorPKci
movl 100(%rsp), %ebx
imull 96(%rsp), %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 112(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $173, %edx
movq %rbp, %rsi
call _Z14checkCudaError9cudaErrorPKci
movl 100(%rsp), %eax
movl 96(%rsp), %edx
testb $15, %dl
setne %cl
movzbl %cl, %ecx
shrl $4, %edx
addl %ecx, %edx
movl %edx, 20(%rsp)
testb $15, %al
setne %dl
movzbl %dl, %edx
shrl $4, %eax
addl %edx, %eax
movl %eax, 24(%rsp)
movl $16, 8(%rsp)
movl $16, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L57
.L52:
movl $2, %ecx
movq %rbx, %rdx
movq 112(%rsp), %rsi
movq 320(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $181, %edx
leaq .LC2(%rip), %rsi
call _Z14checkCudaError9cudaErrorPKci
subq $80, %rsp
.cfi_def_cfa_offset 336
movdqu 384(%rsp), %xmm0
movups %xmm0, 48(%rsp)
movq 400(%rsp), %rax
movq %rax, 64(%rsp)
movdqu 360(%rsp), %xmm1
movups %xmm1, 24(%rsp)
movq 376(%rsp), %rax
movq %rax, 40(%rsp)
movdqu 336(%rsp), %xmm2
movups %xmm2, (%rsp)
movq 352(%rsp), %rax
movq %rax, 16(%rsp)
call _Z16checkCorrectness6MatrixS_S_
addq $80, %rsp
.cfi_def_cfa_offset 256
testb %al, %al
jne .L53
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
.L54:
movq 48(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $188, %edx
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
call _Z14checkCudaError9cudaErrorPKci
movq 80(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $189, %edx
movq %rbx, %rsi
call _Z14checkCudaError9cudaErrorPKci
movq 112(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $190, %edx
movq %rbx, %rsi
call _Z14checkCudaError9cudaErrorPKci
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L58
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
movdqa 32(%rsp), %xmm3
movaps %xmm3, 128(%rsp)
movq 48(%rsp), %rax
movq %rax, 144(%rsp)
movdqa 64(%rsp), %xmm4
movaps %xmm4, 160(%rsp)
movq 80(%rsp), %rax
movq %rax, 176(%rsp)
movdqa 96(%rsp), %xmm5
movaps %xmm5, 192(%rsp)
movq 112(%rsp), %rax
movq %rax, 208(%rsp)
leaq 192(%rsp), %rdx
leaq 160(%rsp), %rsi
leaq 128(%rsp), %rdi
call _Z48__device_stub__Z19MatMulSharedMemory16MatrixS_S_R6MatrixS0_S0_
jmp .L52
.L53:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L54
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z6MatMul6MatrixS_S_, .-_Z6MatMul6MatrixS_S_
.globl main
.type main, @function
main:
.LFB2065:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $96, %rsp
.cfi_def_cfa_offset 128
movl $32, 32(%rsp)
movl $32, 64(%rsp)
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
movl $4096, %edi
call malloc@PLT
movq %rax, %rbx
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $32, (%rsp)
movl $32, 4(%rsp)
movl $32, 8(%rsp)
movq %rbp, 16(%rsp)
subq $32, %rsp
.cfi_def_cfa_offset 160
movdqa 32(%rsp), %xmm0
movups %xmm0, (%rsp)
movq %rbp, 16(%rsp)
call _Z16randomFillMatrix6Matrix
movl $32, 68(%rsp)
movl $32, 72(%rsp)
movq %rbx, 80(%rsp)
movdqa 64(%rsp), %xmm1
movups %xmm1, (%rsp)
movq %rbx, 16(%rsp)
call _Z16randomFillMatrix6Matrix
movl $32, 100(%rsp)
movl $32, 104(%rsp)
subq $48, %rsp
.cfi_def_cfa_offset 208
movdqa 144(%rsp), %xmm2
movups %xmm2, 48(%rsp)
movq %r12, 64(%rsp)
movdqa 112(%rsp), %xmm3
movups %xmm3, 24(%rsp)
movq 128(%rsp), %rax
movq %rax, 40(%rsp)
movdqa 80(%rsp), %xmm4
movups %xmm4, (%rsp)
movq 96(%rsp), %rax
movq %rax, 16(%rsp)
call _Z6MatMul6MatrixS_S_
addq $80, %rsp
.cfi_def_cfa_offset 128
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movl $0, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC5:
.string "_Z19MatMulSharedMemory16MatrixS_S_"
.section .rodata.str1.1
.LC6:
.string "_Z12MatMulKernel6MatrixS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z19MatMulSharedMemory16MatrixS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
/* demo to show the usage of share memory*/
#define DEBUG
typedef float dataType;
void checkCudaError(cudaError_t error, const char* filename, const int linenum)
{
if(error != cudaSuccess){
printf("File: %s, line: %d, CUDA error: %s\n", filename, linenum, cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
}
#define CHECK_CUDA_ERROR(error) checkCudaError(error, __FILE__, __LINE__)
#define BLOCK_SIZE 16
typedef struct Matrix
{
int width;
int height;
int stride;
dataType* element;
}Matrix;
__device__ dataType getElement(Matrix x, int row, int col)
{
return x.element[row * x.stride + col];
}
__device__ void setElement(Matrix x, int row, int col, dataType val)
{
x.element[col + row * x.stride] = val;
}
__device__ Matrix getSubMatrix(Matrix x, int row, int col)
{
Matrix subX;
int row_ = (row + 1) * BLOCK_SIZE, col_ = (col + 1) * BLOCK_SIZE;
subX.height = ((row_ <= x.height) ? BLOCK_SIZE : x.height%BLOCK_SIZE);
subX.width = ((col_ <= x.width) ? BLOCK_SIZE : x.width%BLOCK_SIZE);
//subX.height = subX.width = BLOCK_SIZE;
subX.stride = x.stride;
subX.element = &x.element[x.stride * row * BLOCK_SIZE + col * BLOCK_SIZE];
return subX;
}
__device__ int divCeil(int x, int y)
{
return (x%y == 0) ? x/y : (x/y+1);
}
// no shared memory
__global__ void MatMulKernel(Matrix x, Matrix y, Matrix z)
{
int col = threadIdx.x + blockIdx.x * blockDim.x;
int row = threadIdx.y + blockIdx.y * blockDim.y;
dataType ret = 0;
int i = 0;
if(col < z.width && row < z.height){
for(i = 0; i < x.width; ++i)
ret += getElement(x, row, i) * getElement(y, i, col);
setElement(z, row, col, ret);
}
}
// shared memory
__global__ void MatMulSharedMemory1(Matrix x, Matrix y, Matrix z)
{
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
Matrix subZ = getSubMatrix(z, blockRow, blockCol);
int row = threadIdx.y;
int col = threadIdx.x;
if(row >= subZ.height || col >= subZ.width)
return;
dataType val = 0.0;
int i = 0;
int size = divCeil(x.width, BLOCK_SIZE);
for(; i < size; ++i){
Matrix subX = getSubMatrix(x, blockRow, i);
Matrix subY = getSubMatrix(y, i, blockCol);
__shared__ dataType tmpX[BLOCK_SIZE][BLOCK_SIZE];
__shared__ dataType tmpY[BLOCK_SIZE][BLOCK_SIZE];
tmpX[row][col] = getElement(subX, row, col);
tmpY[row][col] = getElement(subY, row, col);
__syncthreads();
int j = 0;
for(;j < subX.width; ++j)
val += tmpX[row][j] * tmpY[j][col];
__syncthreads();
}
setElement(subZ, row, col, val);
}
bool checkCorrectness(Matrix x, Matrix y, Matrix z)
{
Matrix z_;
z_.width = z.width;
z_.height = z.height;
z_.stride = z.stride;
z_.element = (dataType*)malloc(sizeof(dataType) * z_.width * z_.height);
for(int i = 0; i < z_.height; ++i){
for(int j = 0; j < z_.width; ++j){
dataType val = 0;
for(int k = 0; k < x.width; ++k)
val += x.element[i*x.stride+k] * y.element[k*y.stride+j];
z_.element[j + i * z_.stride] = val;
}
}
bool flag;
if(memcmp(z_.element, z.element, z_.width * z_.height * sizeof(dataType)) == 0)
flag = true;
else
flag = false;
free(z_.element);
return flag;
}
void MatMul(Matrix x, Matrix y, Matrix z)
{
Matrix dev_x, dev_y, dev_z;
dev_x.width = x.width;
dev_x.height = x.height;
dev_x.stride = x.stride;
dev_y.width = y.width;
dev_y.height = y.height;
dev_y.stride = y.stride;
dev_z.width = z.width;
dev_z.height = z.height;
dev_z.stride = z.stride;
int nByte = sizeof(dataType) * dev_x.width * dev_x.height;
CHECK_CUDA_ERROR(cudaMalloc((void**)(&dev_x.element), nByte));
CHECK_CUDA_ERROR(cudaMemcpy(dev_x.element, x.element, nByte, cudaMemcpyHostToDevice));
nByte = sizeof(dataType) * dev_y.width * dev_y.height;
CHECK_CUDA_ERROR(cudaMalloc((void**)&dev_y.element, nByte));
CHECK_CUDA_ERROR(cudaMemcpy(dev_y.element, y.element, nByte, cudaMemcpyHostToDevice));
nByte = sizeof(dataType) * dev_z.width * dev_z.height;
CHECK_CUDA_ERROR(cudaMalloc((void**)&dev_z.element, nByte));
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(dev_z.width/dimBlock.x + (dev_z.width%dimBlock.x == 0 ? 0 : 1), dev_z.height/dimBlock.y + (dev_z.height%dimBlock.y == 0 ? 0 : 1));
//MatMulKernel<<<dimGrid, dimBlock>>>(dev_x, dev_y, dev_z);
MatMulSharedMemory1<<<dimGrid, dimBlock>>>(dev_x, dev_y, dev_z);
CHECK_CUDA_ERROR(cudaMemcpy(z.element, dev_z.element, nByte, cudaMemcpyDeviceToHost));
if(checkCorrectness(x, y, z) == false)
printf("Error occur\n");
else
printf("Correct\n");
CHECK_CUDA_ERROR(cudaFree(dev_x.element));
CHECK_CUDA_ERROR(cudaFree(dev_y.element));
CHECK_CUDA_ERROR(cudaFree(dev_z.element));
}
void randomFillMatrix(Matrix x)
{
int size = x.width*x.height;
for(int i = 0; i < size; ++i){
srand(time(NULL)+i);
x.element[i] = rand()%100;
}
}
int main(void)
{
Matrix x, y, z;
x.width = x.height = x.stride = 32;
y.width = y.height = y.stride = 32;
z.width = z.height = z.stride = 32;
int nByte = sizeof(dataType) * x.width * x. height;
x.element = (dataType*)malloc(nByte);
y.element = (dataType*)malloc(nByte);
z.element = (dataType*)malloc(nByte);
randomFillMatrix(x);
randomFillMatrix(y);
MatMul(x, y, z);
free(x.element);
free(y.element);
free(z.element);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
/* demo to show the usage of share memory*/
#define DEBUG
typedef float dataType;
void checkCudaError(hipError_t error, const char* filename, const int linenum)
{
if(error != hipSuccess){
printf("File: %s, line: %d, CUDA error: %s\n", filename, linenum, hipGetErrorString(error));
exit(EXIT_FAILURE);
}
}
#define CHECK_CUDA_ERROR(error) checkCudaError(error, __FILE__, __LINE__)
#define BLOCK_SIZE 16
typedef struct Matrix
{
int width;
int height;
int stride;
dataType* element;
}Matrix;
__device__ dataType getElement(Matrix x, int row, int col)
{
return x.element[row * x.stride + col];
}
__device__ void setElement(Matrix x, int row, int col, dataType val)
{
x.element[col + row * x.stride] = val;
}
__device__ Matrix getSubMatrix(Matrix x, int row, int col)
{
Matrix subX;
int row_ = (row + 1) * BLOCK_SIZE, col_ = (col + 1) * BLOCK_SIZE;
subX.height = ((row_ <= x.height) ? BLOCK_SIZE : x.height%BLOCK_SIZE);
subX.width = ((col_ <= x.width) ? BLOCK_SIZE : x.width%BLOCK_SIZE);
//subX.height = subX.width = BLOCK_SIZE;
subX.stride = x.stride;
subX.element = &x.element[x.stride * row * BLOCK_SIZE + col * BLOCK_SIZE];
return subX;
}
__device__ int divCeil(int x, int y)
{
return (x%y == 0) ? x/y : (x/y+1);
}
// no shared memory
__global__ void MatMulKernel(Matrix x, Matrix y, Matrix z)
{
int col = threadIdx.x + blockIdx.x * blockDim.x;
int row = threadIdx.y + blockIdx.y * blockDim.y;
dataType ret = 0;
int i = 0;
if(col < z.width && row < z.height){
for(i = 0; i < x.width; ++i)
ret += getElement(x, row, i) * getElement(y, i, col);
setElement(z, row, col, ret);
}
}
// shared memory
__global__ void MatMulSharedMemory1(Matrix x, Matrix y, Matrix z)
{
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
Matrix subZ = getSubMatrix(z, blockRow, blockCol);
int row = threadIdx.y;
int col = threadIdx.x;
if(row >= subZ.height || col >= subZ.width)
return;
dataType val = 0.0;
int i = 0;
int size = divCeil(x.width, BLOCK_SIZE);
for(; i < size; ++i){
Matrix subX = getSubMatrix(x, blockRow, i);
Matrix subY = getSubMatrix(y, i, blockCol);
__shared__ dataType tmpX[BLOCK_SIZE][BLOCK_SIZE];
__shared__ dataType tmpY[BLOCK_SIZE][BLOCK_SIZE];
tmpX[row][col] = getElement(subX, row, col);
tmpY[row][col] = getElement(subY, row, col);
__syncthreads();
int j = 0;
for(;j < subX.width; ++j)
val += tmpX[row][j] * tmpY[j][col];
__syncthreads();
}
setElement(subZ, row, col, val);
}
bool checkCorrectness(Matrix x, Matrix y, Matrix z)
{
Matrix z_;
z_.width = z.width;
z_.height = z.height;
z_.stride = z.stride;
z_.element = (dataType*)malloc(sizeof(dataType) * z_.width * z_.height);
for(int i = 0; i < z_.height; ++i){
for(int j = 0; j < z_.width; ++j){
dataType val = 0;
for(int k = 0; k < x.width; ++k)
val += x.element[i*x.stride+k] * y.element[k*y.stride+j];
z_.element[j + i * z_.stride] = val;
}
}
bool flag;
if(memcmp(z_.element, z.element, z_.width * z_.height * sizeof(dataType)) == 0)
flag = true;
else
flag = false;
free(z_.element);
return flag;
}
void MatMul(Matrix x, Matrix y, Matrix z)
{
Matrix dev_x, dev_y, dev_z;
dev_x.width = x.width;
dev_x.height = x.height;
dev_x.stride = x.stride;
dev_y.width = y.width;
dev_y.height = y.height;
dev_y.stride = y.stride;
dev_z.width = z.width;
dev_z.height = z.height;
dev_z.stride = z.stride;
int nByte = sizeof(dataType) * dev_x.width * dev_x.height;
CHECK_CUDA_ERROR(hipMalloc((void**)(&dev_x.element), nByte));
CHECK_CUDA_ERROR(hipMemcpy(dev_x.element, x.element, nByte, hipMemcpyHostToDevice));
nByte = sizeof(dataType) * dev_y.width * dev_y.height;
CHECK_CUDA_ERROR(hipMalloc((void**)&dev_y.element, nByte));
CHECK_CUDA_ERROR(hipMemcpy(dev_y.element, y.element, nByte, hipMemcpyHostToDevice));
nByte = sizeof(dataType) * dev_z.width * dev_z.height;
CHECK_CUDA_ERROR(hipMalloc((void**)&dev_z.element, nByte));
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(dev_z.width/dimBlock.x + (dev_z.width%dimBlock.x == 0 ? 0 : 1), dev_z.height/dimBlock.y + (dev_z.height%dimBlock.y == 0 ? 0 : 1));
//MatMulKernel<<<dimGrid, dimBlock>>>(dev_x, dev_y, dev_z);
MatMulSharedMemory1<<<dimGrid, dimBlock>>>(dev_x, dev_y, dev_z);
CHECK_CUDA_ERROR(hipMemcpy(z.element, dev_z.element, nByte, hipMemcpyDeviceToHost));
if(checkCorrectness(x, y, z) == false)
printf("Error occur\n");
else
printf("Correct\n");
CHECK_CUDA_ERROR(hipFree(dev_x.element));
CHECK_CUDA_ERROR(hipFree(dev_y.element));
CHECK_CUDA_ERROR(hipFree(dev_z.element));
}
void randomFillMatrix(Matrix x)
{
int size = x.width*x.height;
for(int i = 0; i < size; ++i){
srand(time(NULL)+i);
x.element[i] = rand()%100;
}
}
int main(void)
{
Matrix x, y, z;
x.width = x.height = x.stride = 32;
y.width = y.height = y.stride = 32;
z.width = z.height = z.stride = 32;
int nByte = sizeof(dataType) * x.width * x. height;
x.element = (dataType*)malloc(nByte);
y.element = (dataType*)malloc(nByte);
z.element = (dataType*)malloc(nByte);
randomFillMatrix(x);
randomFillMatrix(y);
MatMul(x, y, z);
free(x.element);
free(y.element);
free(z.element);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
/* demo to show the usage of share memory*/
#define DEBUG
typedef float dataType;
void checkCudaError(hipError_t error, const char* filename, const int linenum)
{
if(error != hipSuccess){
printf("File: %s, line: %d, CUDA error: %s\n", filename, linenum, hipGetErrorString(error));
exit(EXIT_FAILURE);
}
}
#define CHECK_CUDA_ERROR(error) checkCudaError(error, __FILE__, __LINE__)
#define BLOCK_SIZE 16
typedef struct Matrix
{
int width;
int height;
int stride;
dataType* element;
}Matrix;
__device__ dataType getElement(Matrix x, int row, int col)
{
return x.element[row * x.stride + col];
}
__device__ void setElement(Matrix x, int row, int col, dataType val)
{
x.element[col + row * x.stride] = val;
}
__device__ Matrix getSubMatrix(Matrix x, int row, int col)
{
Matrix subX;
int row_ = (row + 1) * BLOCK_SIZE, col_ = (col + 1) * BLOCK_SIZE;
subX.height = ((row_ <= x.height) ? BLOCK_SIZE : x.height%BLOCK_SIZE);
subX.width = ((col_ <= x.width) ? BLOCK_SIZE : x.width%BLOCK_SIZE);
//subX.height = subX.width = BLOCK_SIZE;
subX.stride = x.stride;
subX.element = &x.element[x.stride * row * BLOCK_SIZE + col * BLOCK_SIZE];
return subX;
}
__device__ int divCeil(int x, int y)
{
return (x%y == 0) ? x/y : (x/y+1);
}
// no shared memory
__global__ void MatMulKernel(Matrix x, Matrix y, Matrix z)
{
int col = threadIdx.x + blockIdx.x * blockDim.x;
int row = threadIdx.y + blockIdx.y * blockDim.y;
dataType ret = 0;
int i = 0;
if(col < z.width && row < z.height){
for(i = 0; i < x.width; ++i)
ret += getElement(x, row, i) * getElement(y, i, col);
setElement(z, row, col, ret);
}
}
// shared memory
__global__ void MatMulSharedMemory1(Matrix x, Matrix y, Matrix z)
{
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
Matrix subZ = getSubMatrix(z, blockRow, blockCol);
int row = threadIdx.y;
int col = threadIdx.x;
if(row >= subZ.height || col >= subZ.width)
return;
dataType val = 0.0;
int i = 0;
int size = divCeil(x.width, BLOCK_SIZE);
for(; i < size; ++i){
Matrix subX = getSubMatrix(x, blockRow, i);
Matrix subY = getSubMatrix(y, i, blockCol);
__shared__ dataType tmpX[BLOCK_SIZE][BLOCK_SIZE];
__shared__ dataType tmpY[BLOCK_SIZE][BLOCK_SIZE];
tmpX[row][col] = getElement(subX, row, col);
tmpY[row][col] = getElement(subY, row, col);
__syncthreads();
int j = 0;
for(;j < subX.width; ++j)
val += tmpX[row][j] * tmpY[j][col];
__syncthreads();
}
setElement(subZ, row, col, val);
}
bool checkCorrectness(Matrix x, Matrix y, Matrix z)
{
Matrix z_;
z_.width = z.width;
z_.height = z.height;
z_.stride = z.stride;
z_.element = (dataType*)malloc(sizeof(dataType) * z_.width * z_.height);
for(int i = 0; i < z_.height; ++i){
for(int j = 0; j < z_.width; ++j){
dataType val = 0;
for(int k = 0; k < x.width; ++k)
val += x.element[i*x.stride+k] * y.element[k*y.stride+j];
z_.element[j + i * z_.stride] = val;
}
}
bool flag;
if(memcmp(z_.element, z.element, z_.width * z_.height * sizeof(dataType)) == 0)
flag = true;
else
flag = false;
free(z_.element);
return flag;
}
void MatMul(Matrix x, Matrix y, Matrix z)
{
Matrix dev_x, dev_y, dev_z;
dev_x.width = x.width;
dev_x.height = x.height;
dev_x.stride = x.stride;
dev_y.width = y.width;
dev_y.height = y.height;
dev_y.stride = y.stride;
dev_z.width = z.width;
dev_z.height = z.height;
dev_z.stride = z.stride;
int nByte = sizeof(dataType) * dev_x.width * dev_x.height;
CHECK_CUDA_ERROR(hipMalloc((void**)(&dev_x.element), nByte));
CHECK_CUDA_ERROR(hipMemcpy(dev_x.element, x.element, nByte, hipMemcpyHostToDevice));
nByte = sizeof(dataType) * dev_y.width * dev_y.height;
CHECK_CUDA_ERROR(hipMalloc((void**)&dev_y.element, nByte));
CHECK_CUDA_ERROR(hipMemcpy(dev_y.element, y.element, nByte, hipMemcpyHostToDevice));
nByte = sizeof(dataType) * dev_z.width * dev_z.height;
CHECK_CUDA_ERROR(hipMalloc((void**)&dev_z.element, nByte));
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(dev_z.width/dimBlock.x + (dev_z.width%dimBlock.x == 0 ? 0 : 1), dev_z.height/dimBlock.y + (dev_z.height%dimBlock.y == 0 ? 0 : 1));
//MatMulKernel<<<dimGrid, dimBlock>>>(dev_x, dev_y, dev_z);
MatMulSharedMemory1<<<dimGrid, dimBlock>>>(dev_x, dev_y, dev_z);
CHECK_CUDA_ERROR(hipMemcpy(z.element, dev_z.element, nByte, hipMemcpyDeviceToHost));
if(checkCorrectness(x, y, z) == false)
printf("Error occur\n");
else
printf("Correct\n");
CHECK_CUDA_ERROR(hipFree(dev_x.element));
CHECK_CUDA_ERROR(hipFree(dev_y.element));
CHECK_CUDA_ERROR(hipFree(dev_z.element));
}
void randomFillMatrix(Matrix x)
{
int size = x.width*x.height;
for(int i = 0; i < size; ++i){
srand(time(NULL)+i);
x.element[i] = rand()%100;
}
}
int main(void)
{
Matrix x, y, z;
x.width = x.height = x.stride = 32;
y.width = y.height = y.stride = 32;
z.width = z.height = z.stride = 32;
int nByte = sizeof(dataType) * x.width * x. height;
x.element = (dataType*)malloc(nByte);
y.element = (dataType*)malloc(nByte);
z.element = (dataType*)malloc(nByte);
randomFillMatrix(x);
randomFillMatrix(y);
MatMul(x, y, z);
free(x.element);
free(y.element);
free(z.element);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12MatMulKernel6MatrixS_S_
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 8
.type _Z12MatMulKernel6MatrixS_S_,@function
_Z12MatMulKernel6MatrixS_S_:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x54
s_load_b64 s[2:3], s[0:1], 0x30
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_add_u32 s4, s0, 48
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s6, 0xffff
s_lshr_b32 s6, s6, 16
v_mad_u64_u32 v[0:1], null, s14, s7, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s6, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b32 s6, s[0:1], 0x0
s_load_b64 s[2:3], s[4:5], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_4
s_clause 0x3
s_load_b32 s10, s[0:1], 0x8
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s7, s[0:1], 0x20
s_load_b64 s[0:1], s[0:1], 0x28
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v2, v1, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s6, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s6, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b32 s0, s[4:5], 0x8
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s0, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12MatMulKernel6MatrixS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12MatMulKernel6MatrixS_S_, .Lfunc_end0-_Z12MatMulKernel6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19MatMulSharedMemory16MatrixS_S_
.globl _Z19MatMulSharedMemory16MatrixS_S_
.p2align 8
.type _Z19MatMulSharedMemory16MatrixS_S_,@function
_Z19MatMulSharedMemory16MatrixS_S_:
s_load_b64 s[2:3], s[0:1], 0x30
s_add_u32 s4, s0, 48
s_addc_u32 s5, s1, 0
s_lshl_b32 s7, s15, 4
s_lshl_b32 s8, s14, 4
s_add_i32 s7, s7, 16
s_add_i32 s8, s8, 16
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s6, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s6, s6, 28
s_add_i32 s6, s3, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, s6, -16
s_sub_i32 s6, s3, s6
s_cmp_gt_i32 s7, s3
s_cselect_b32 s3, s6, 16
s_ashr_i32 s6, s2, 31
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_lshr_b32 s6, s6, 28
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s2, s6
s_and_b32 s6, s6, -16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s6, s2, s6
s_cmp_gt_i32 s8, s2
s_cselect_b32 s2, s6, 16
v_cmp_gt_i32_e64 s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_12
s_load_b32 s6, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s6, 15
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_mov_b32 s2, 0
s_cbranch_scc0 .LBB1_9
s_ashr_i32 s3, s6, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s3, s3, 28
s_add_i32 s3, s6, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s3, s3, 4
s_add_i32 s7, s3, 1
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB1_4
.LBB1_3:
s_ashr_i32 s7, s6, 4
.LBB1_4:
s_load_b64 s[2:3], s[4:5], 0x10
s_cmp_lt_i32 s7, 1
s_cbranch_scc1 .LBB1_10
s_clause 0x3
s_load_b32 s8, s[0:1], 0x20
s_load_b32 s9, s[0:1], 0x8
s_load_b64 s[10:11], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x28
v_lshlrev_b32_e32 v2, 2, v0
s_ashr_i32 s12, s6, 31
v_lshlrev_b32_e32 v3, 6, v1
s_lshr_b32 s12, s12, 28
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v4, 0x400, v2
s_add_i32 s12, s6, s12
s_and_b32 s12, s12, -16
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[7:8], null, s8, v1, v[0:1]
v_mad_u64_u32 v[5:6], null, s9, v1, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 2, v[7:8]
v_lshlrev_b64 v[9:10], 2, v[5:6]
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v5, v3, v2
v_add_nc_u32_e32 v6, v4, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s10, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s0, v11
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v12, vcc_lo
s_sub_i32 s0, s6, s12
s_mul_i32 s1, s9, s15
s_mov_b32 s9, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_7
.p2align 6
.LBB1_6:
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s9, s7
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_11
.LBB1_7:
s_lshl_b32 s10, s9, 4
s_mul_i32 s11, s9, s8
s_add_i32 s10, s10, 16
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_i32 s10, s6
s_cselect_b32 s10, s0, 16
s_add_i32 s12, s9, s1
s_add_i32 s11, s11, s14
s_lshl_b32 s12, s12, 4
s_lshl_b32 s16, s11, 4
s_ashr_i32 s13, s12, 31
s_ashr_i32 s17, s16, 31
s_lshl_b64 s[12:13], s[12:13], 2
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v11, vcc_lo, v7, s12
v_add_co_ci_u32_e32 v12, vcc_lo, s13, v8, vcc_lo
s_lshl_b64 s[12:13], s[16:17], 2
s_cmp_lt_i32 s10, 1
v_add_co_u32 v13, vcc_lo, v9, s12
v_add_co_ci_u32_e32 v14, vcc_lo, s13, v10, vcc_lo
global_load_b32 v15, v[11:12], off
global_load_b32 v13, v[13:14], off
v_dual_mov_b32 v11, v4 :: v_dual_mov_b32 v12, v3
s_waitcnt vmcnt(1)
ds_store_b32 v5, v15
s_waitcnt vmcnt(0)
ds_store_b32 v6, v13
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_6
.LBB1_8:
ds_load_b32 v13, v12
ds_load_b32 v14, v11
v_add_nc_u32_e32 v12, 4, v12
v_add_nc_u32_e32 v11, 64, v11
s_add_i32 s10, s10, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s10, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v13, v14
s_cbranch_scc1 .LBB1_8
s_branch .LBB1_6
.LBB1_9:
s_branch .LBB1_3
.LBB1_10:
v_mov_b32_e32 v2, 0
.LBB1_11:
s_set_inst_prefetch_distance 0x2
s_load_b32 s0, s[4:5], 0x8
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, s0, v1, v[0:1]
s_mul_i32 s0, s0, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s14
s_lshl_b32 s0, s0, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_ashr_i32 s1, s0, 31
v_ashrrev_i32_e32 v4, 31, v3
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB1_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19MatMulSharedMemory16MatrixS_S_
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 72
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z19MatMulSharedMemory16MatrixS_S_, .Lfunc_end1-_Z19MatMulSharedMemory16MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 24
.value_kind: by_value
- .offset: 48
.size: 24
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12MatMulKernel6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12MatMulKernel6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 24
.value_kind: by_value
- .offset: 48
.size: 24
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 72
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19MatMulSharedMemory16MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z19MatMulSharedMemory16MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
/* demo to show the usage of share memory*/
#define DEBUG
typedef float dataType;
void checkCudaError(hipError_t error, const char* filename, const int linenum)
{
if(error != hipSuccess){
printf("File: %s, line: %d, CUDA error: %s\n", filename, linenum, hipGetErrorString(error));
exit(EXIT_FAILURE);
}
}
#define CHECK_CUDA_ERROR(error) checkCudaError(error, __FILE__, __LINE__)
#define BLOCK_SIZE 16
typedef struct Matrix
{
int width;
int height;
int stride;
dataType* element;
}Matrix;
__device__ dataType getElement(Matrix x, int row, int col)
{
return x.element[row * x.stride + col];
}
__device__ void setElement(Matrix x, int row, int col, dataType val)
{
x.element[col + row * x.stride] = val;
}
__device__ Matrix getSubMatrix(Matrix x, int row, int col)
{
Matrix subX;
int row_ = (row + 1) * BLOCK_SIZE, col_ = (col + 1) * BLOCK_SIZE;
subX.height = ((row_ <= x.height) ? BLOCK_SIZE : x.height%BLOCK_SIZE);
subX.width = ((col_ <= x.width) ? BLOCK_SIZE : x.width%BLOCK_SIZE);
//subX.height = subX.width = BLOCK_SIZE;
subX.stride = x.stride;
subX.element = &x.element[x.stride * row * BLOCK_SIZE + col * BLOCK_SIZE];
return subX;
}
__device__ int divCeil(int x, int y)
{
return (x%y == 0) ? x/y : (x/y+1);
}
// no shared memory
__global__ void MatMulKernel(Matrix x, Matrix y, Matrix z)
{
int col = threadIdx.x + blockIdx.x * blockDim.x;
int row = threadIdx.y + blockIdx.y * blockDim.y;
dataType ret = 0;
int i = 0;
if(col < z.width && row < z.height){
for(i = 0; i < x.width; ++i)
ret += getElement(x, row, i) * getElement(y, i, col);
setElement(z, row, col, ret);
}
}
// shared memory
__global__ void MatMulSharedMemory1(Matrix x, Matrix y, Matrix z)
{
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
Matrix subZ = getSubMatrix(z, blockRow, blockCol);
int row = threadIdx.y;
int col = threadIdx.x;
if(row >= subZ.height || col >= subZ.width)
return;
dataType val = 0.0;
int i = 0;
int size = divCeil(x.width, BLOCK_SIZE);
for(; i < size; ++i){
Matrix subX = getSubMatrix(x, blockRow, i);
Matrix subY = getSubMatrix(y, i, blockCol);
__shared__ dataType tmpX[BLOCK_SIZE][BLOCK_SIZE];
__shared__ dataType tmpY[BLOCK_SIZE][BLOCK_SIZE];
tmpX[row][col] = getElement(subX, row, col);
tmpY[row][col] = getElement(subY, row, col);
__syncthreads();
int j = 0;
for(;j < subX.width; ++j)
val += tmpX[row][j] * tmpY[j][col];
__syncthreads();
}
setElement(subZ, row, col, val);
}
bool checkCorrectness(Matrix x, Matrix y, Matrix z)
{
Matrix z_;
z_.width = z.width;
z_.height = z.height;
z_.stride = z.stride;
z_.element = (dataType*)malloc(sizeof(dataType) * z_.width * z_.height);
for(int i = 0; i < z_.height; ++i){
for(int j = 0; j < z_.width; ++j){
dataType val = 0;
for(int k = 0; k < x.width; ++k)
val += x.element[i*x.stride+k] * y.element[k*y.stride+j];
z_.element[j + i * z_.stride] = val;
}
}
bool flag;
if(memcmp(z_.element, z.element, z_.width * z_.height * sizeof(dataType)) == 0)
flag = true;
else
flag = false;
free(z_.element);
return flag;
}
void MatMul(Matrix x, Matrix y, Matrix z)
{
Matrix dev_x, dev_y, dev_z;
dev_x.width = x.width;
dev_x.height = x.height;
dev_x.stride = x.stride;
dev_y.width = y.width;
dev_y.height = y.height;
dev_y.stride = y.stride;
dev_z.width = z.width;
dev_z.height = z.height;
dev_z.stride = z.stride;
int nByte = sizeof(dataType) * dev_x.width * dev_x.height;
CHECK_CUDA_ERROR(hipMalloc((void**)(&dev_x.element), nByte));
CHECK_CUDA_ERROR(hipMemcpy(dev_x.element, x.element, nByte, hipMemcpyHostToDevice));
nByte = sizeof(dataType) * dev_y.width * dev_y.height;
CHECK_CUDA_ERROR(hipMalloc((void**)&dev_y.element, nByte));
CHECK_CUDA_ERROR(hipMemcpy(dev_y.element, y.element, nByte, hipMemcpyHostToDevice));
nByte = sizeof(dataType) * dev_z.width * dev_z.height;
CHECK_CUDA_ERROR(hipMalloc((void**)&dev_z.element, nByte));
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(dev_z.width/dimBlock.x + (dev_z.width%dimBlock.x == 0 ? 0 : 1), dev_z.height/dimBlock.y + (dev_z.height%dimBlock.y == 0 ? 0 : 1));
//MatMulKernel<<<dimGrid, dimBlock>>>(dev_x, dev_y, dev_z);
MatMulSharedMemory1<<<dimGrid, dimBlock>>>(dev_x, dev_y, dev_z);
CHECK_CUDA_ERROR(hipMemcpy(z.element, dev_z.element, nByte, hipMemcpyDeviceToHost));
if(checkCorrectness(x, y, z) == false)
printf("Error occur\n");
else
printf("Correct\n");
CHECK_CUDA_ERROR(hipFree(dev_x.element));
CHECK_CUDA_ERROR(hipFree(dev_y.element));
CHECK_CUDA_ERROR(hipFree(dev_z.element));
}
void randomFillMatrix(Matrix x)
{
int size = x.width*x.height;
for(int i = 0; i < size; ++i){
srand(time(NULL)+i);
x.element[i] = rand()%100;
}
}
int main(void)
{
Matrix x, y, z;
x.width = x.height = x.stride = 32;
y.width = y.height = y.stride = 32;
z.width = z.height = z.stride = 32;
int nByte = sizeof(dataType) * x.width * x. height;
x.element = (dataType*)malloc(nByte);
y.element = (dataType*)malloc(nByte);
z.element = (dataType*)malloc(nByte);
randomFillMatrix(x);
randomFillMatrix(y);
MatMul(x, y, z);
free(x.element);
free(y.element);
free(z.element);
return 0;
} | .text
.file "MatMul.hip"
.globl _Z14checkCudaError10hipError_tPKci # -- Begin function _Z14checkCudaError10hipError_tPKci
.p2align 4, 0x90
.type _Z14checkCudaError10hipError_tPKci,@function
_Z14checkCudaError10hipError_tPKci: # @_Z14checkCudaError10hipError_tPKci
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edx, %ebx
movq %rsi, %r14
callq hipGetErrorString
movl $.L.str, %edi
movq %r14, %rsi
movl %ebx, %edx
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z14checkCudaError10hipError_tPKci, .Lfunc_end0-_Z14checkCudaError10hipError_tPKci
.cfi_endproc
# -- End function
.globl _Z27__device_stub__MatMulKernel6MatrixS_S_ # -- Begin function _Z27__device_stub__MatMulKernel6MatrixS_S_
.p2align 4, 0x90
.type _Z27__device_stub__MatMulKernel6MatrixS_S_,@function
_Z27__device_stub__MatMulKernel6MatrixS_S_: # @_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 80(%rsp), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z27__device_stub__MatMulKernel6MatrixS_S_, .Lfunc_end1-_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z34__device_stub__MatMulSharedMemory16MatrixS_S_ # -- Begin function _Z34__device_stub__MatMulSharedMemory16MatrixS_S_
.p2align 4, 0x90
.type _Z34__device_stub__MatMulSharedMemory16MatrixS_S_,@function
_Z34__device_stub__MatMulSharedMemory16MatrixS_S_: # @_Z34__device_stub__MatMulSharedMemory16MatrixS_S_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 80(%rsp), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z19MatMulSharedMemory16MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z34__device_stub__MatMulSharedMemory16MatrixS_S_, .Lfunc_end2-_Z34__device_stub__MatMulSharedMemory16MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z16checkCorrectness6MatrixS_S_ # -- Begin function _Z16checkCorrectness6MatrixS_S_
.p2align 4, 0x90
.type _Z16checkCorrectness6MatrixS_S_,@function
_Z16checkCorrectness6MatrixS_S_: # @_Z16checkCorrectness6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movslq 112(%rsp), %rdi
movl %edi, %r15d
movslq 116(%rsp), %r14
movslq 120(%rsp), %r12
imulq %r14, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %rbx
movl %r14d, %eax
testq %r14, %r14
jle .LBB3_9
# %bb.1: # %.preheader26.lr.ph
leaq 88(%rsp), %r8
leaq 64(%rsp), %rsi
movl (%rsi), %ecx
movq 16(%rsi), %rdx
movslq 8(%rsi), %rsi
movq 16(%r8), %rdi
movslq 8(%r8), %r8
shlq $2, %rsi
shlq $2, %r8
xorl %r9d, %r9d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_8: # %._crit_edge30
# in Loop: Header=BB3_2 Depth=1
incq %r9
addq %rsi, %rdx
cmpq %rax, %r9
je .LBB3_9
.LBB3_2: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
# Child Loop BB3_6 Depth 3
testl %r15d, %r15d
jle .LBB3_8
# %bb.3: # %.preheader.lr.ph
# in Loop: Header=BB3_2 Depth=1
movq %r9, %r10
imulq %r12, %r10
leaq (%rbx,%r10,4), %r10
movq %rdi, %r11
xorl %r13d, %r13d
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_4 Depth=2
movss %xmm0, (%r10,%r13,4)
incq %r13
addq $4, %r11
cmpq %r15, %r13
je .LBB3_8
.LBB3_4: # %.preheader
# Parent Loop BB3_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_6 Depth 3
xorps %xmm0, %xmm0
testl %ecx, %ecx
jle .LBB3_7
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB3_4 Depth=2
movq %r11, %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_6: # %.lr.ph
# Parent Loop BB3_2 Depth=1
# Parent Loop BB3_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdx,%r14,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rbp), %xmm1
addss %xmm1, %xmm0
incq %r14
addq %r8, %rbp
cmpq %r14, %rcx
jne .LBB3_6
jmp .LBB3_7
.LBB3_9: # %._crit_edge32
leaq 112(%rsp), %rcx
movq 16(%rcx), %rsi
imull %r15d, %eax
movslq %eax, %rdx
shlq $2, %rdx
movq %rbx, %rdi
callq bcmp@PLT
testl %eax, %eax
sete %bpl
movq %rbx, %rdi
callq free
movl %ebp, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z16checkCorrectness6MatrixS_S_, .Lfunc_end3-_Z16checkCorrectness6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z6MatMul6MatrixS_S_ # -- Begin function _Z6MatMul6MatrixS_S_
.p2align 4, 0x90
.type _Z6MatMul6MatrixS_S_,@function
_Z6MatMul6MatrixS_S_: # @_Z6MatMul6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl 352(%rsp), %r13d
movl 356(%rsp), %eax
movl %r13d, 64(%rsp)
movl %eax, 68(%rsp)
movslq 360(%rsp), %rcx
movq %rcx, 120(%rsp) # 8-byte Spill
movl %ecx, 72(%rsp)
movq 376(%rsp), %rcx
movq %rcx, 40(%rsp)
movslq 384(%rsp), %rbp
movl %ebp, 48(%rsp)
movslq 400(%rsp), %rcx
movq %rcx, 8(%rsp) # 8-byte Spill
movl %ecx, 16(%rsp)
movslq 404(%rsp), %rcx
movq %rcx, 104(%rsp) # 8-byte Spill
movl %ecx, 20(%rsp)
movslq 408(%rsp), %rcx
movq %rcx, 112(%rsp) # 8-byte Spill
movl %ecx, 24(%rsp)
imull %r13d, %eax
shll $2, %eax
leaq 80(%rsp), %rdi
movslq %eax, %r14
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_1
# %bb.3: # %_Z14checkCudaError10hipError_tPKci.exit
leaq 352(%rsp), %rax
movq 80(%rsp), %rdi
movq 16(%rax), %rbx
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_4
# %bb.5: # %_Z14checkCudaError10hipError_tPKci.exit14
movl 40(%rsp), %eax
imull 44(%rsp), %eax
shll $2, %eax
leaq 56(%rsp), %rdi
movslq %eax, %r15
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_6
# %bb.7: # %_Z14checkCudaError10hipError_tPKci.exit16
leaq 376(%rsp), %rax
movq 56(%rsp), %rdi
movq 16(%rax), %r14
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_8
# %bb.9: # %_Z14checkCudaError10hipError_tPKci.exit18
movl 16(%rsp), %eax
imull 20(%rsp), %eax
shll $2, %eax
leaq 32(%rsp), %rdi
movslq %eax, %r12
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_10
# %bb.11: # %_Z14checkCudaError10hipError_tPKci.exit20
leaq 400(%rsp), %r15
movl 16(%rsp), %eax
movl 20(%rsp), %ecx
movl %eax, %edx
shrl $4, %edx
andl $15, %eax
cmpl $1, %eax
sbbl $-1, %edx
movl %ecx, %edi
shrl $4, %edi
andl $15, %ecx
cmpl $1, %ecx
sbbl $-1, %edi
shlq $32, %rdi
orq %rdx, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_13
# %bb.12:
movq 80(%rsp), %rax
movq %rax, 224(%rsp)
movups 64(%rsp), %xmm0
movaps %xmm0, 208(%rsp)
movq 56(%rsp), %rax
movq %rax, 256(%rsp)
movups 40(%rsp), %xmm0
movaps %xmm0, 240(%rsp)
movq 32(%rsp), %rax
movq %rax, 288(%rsp)
movups 16(%rsp), %xmm0
movaps %xmm0, 272(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
leaq 240(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 160(%rsp), %rdi
leaq 144(%rsp), %rsi
leaq 136(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
movq 144(%rsp), %rcx
movl 152(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z19MatMulSharedMemory16MatrixS_S_, %edi
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_13:
movq %r14, 96(%rsp) # 8-byte Spill
movq 16(%r15), %rdi
movq 32(%rsp), %rsi
movq %rdi, 88(%rsp) # 8-byte Spill
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_14
# %bb.15: # %_Z14checkCudaError10hipError_tPKci.exit22
movq 104(%rsp), %r14 # 8-byte Reload
movl %r14d, %r15d
movq %r14, %rdi
imulq 8(%rsp), %rdi # 8-byte Folded Reload
shlq $2, %rdi
callq malloc
movq %rax, %r12
testl %r14d, %r14d
movq 120(%rsp), %r10 # 8-byte Reload
movq 112(%rsp), %r11 # 8-byte Reload
movq 96(%rsp), %r14 # 8-byte Reload
jle .LBB4_22
# %bb.16: # %.preheader26.lr.ph.i
movl 8(%rsp), %eax # 4-byte Reload
shlq $2, %rbp
shlq $2, %r10
xorl %ecx, %ecx
jmp .LBB4_17
.p2align 4, 0x90
.LBB4_21: # %._crit_edge30.i
# in Loop: Header=BB4_17 Depth=1
incq %rcx
addq %r10, %rbx
cmpq %r15, %rcx
je .LBB4_22
.LBB4_17: # %.preheader26.i
# =>This Loop Header: Depth=1
# Child Loop BB4_19 Depth 2
# Child Loop BB4_25 Depth 3
testl %eax, %eax
jle .LBB4_21
# %bb.18: # %.preheader.lr.ph.i
# in Loop: Header=BB4_17 Depth=1
movq %rcx, %rdx
imulq %r11, %rdx
leaq (%r12,%rdx,4), %rdx
movq %r14, %rsi
xorl %edi, %edi
jmp .LBB4_19
.p2align 4, 0x90
.LBB4_20: # %._crit_edge.i
# in Loop: Header=BB4_19 Depth=2
movss %xmm0, (%rdx,%rdi,4)
incq %rdi
addq $4, %rsi
cmpq %rax, %rdi
je .LBB4_21
.LBB4_19: # %.preheader.i
# Parent Loop BB4_17 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_25 Depth 3
xorps %xmm0, %xmm0
testl %r13d, %r13d
jle .LBB4_20
# %bb.24: # %.lr.ph.preheader.i
# in Loop: Header=BB4_19 Depth=2
movq %rsi, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB4_25: # %.lr.ph.i
# Parent Loop BB4_17 Depth=1
# Parent Loop BB4_19 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rbx,%r9,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r8), %xmm1
addss %xmm1, %xmm0
incq %r9
addq %rbp, %r8
cmpq %r9, %r13
jne .LBB4_25
jmp .LBB4_20
.LBB4_22: # %_Z16checkCorrectness6MatrixS_S_.exit
movq 8(%rsp), %rax # 8-byte Reload
imull %r15d, %eax
movslq %eax, %rdx
shlq $2, %rdx
movq %r12, %rdi
movq 88(%rsp), %rsi # 8-byte Reload
callq bcmp@PLT
movl %eax, %ebx
movq %r12, %rdi
callq free
testl %ebx, %ebx
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq 80(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_23
# %bb.26: # %_Z14checkCudaError10hipError_tPKci.exit24
movq 56(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_27
# %bb.28: # %_Z14checkCudaError10hipError_tPKci.exit26
movq 32(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_29
# %bb.30: # %_Z14checkCudaError10hipError_tPKci.exit28
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 352
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $167, %edx
jmp .LBB4_2
.LBB4_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $168, %edx
jmp .LBB4_2
.LBB4_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $171, %edx
jmp .LBB4_2
.LBB4_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $172, %edx
jmp .LBB4_2
.LBB4_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $175, %edx
jmp .LBB4_2
.LBB4_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $183, %edx
jmp .LBB4_2
.LBB4_23:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $190, %edx
jmp .LBB4_2
.LBB4_27:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $191, %edx
jmp .LBB4_2
.LBB4_29:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $192, %edx
.LBB4_2:
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end4:
.size _Z6MatMul6MatrixS_S_, .Lfunc_end4-_Z6MatMul6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z16randomFillMatrix6Matrix # -- Begin function _Z16randomFillMatrix6Matrix
.p2align 4, 0x90
.type _Z16randomFillMatrix6Matrix,@function
_Z16randomFillMatrix6Matrix: # @_Z16randomFillMatrix6Matrix
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl 36(%rsp), %eax
imull 32(%rsp), %eax
testl %eax, %eax
jle .LBB5_3
# %bb.1: # %.lr.ph
leaq 32(%rsp), %rcx
movq 16(%rcx), %rbx
movl %eax, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_2: # =>This Inner Loop Header: Depth=1
xorl %edi, %edi
callq time
leal (%r15,%rax), %edi
callq srand
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB5_2
.LBB5_3: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z16randomFillMatrix6Matrix, .Lfunc_end5-_Z16randomFillMatrix6Matrix
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.lr.ph.i
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB6_1: # =>This Inner Loop Header: Depth=1
xorl %edi, %edi
callq time
leal (%r12,%rax), %edi
callq srand
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB6_1
# %bb.2: # %.lr.ph.i29.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB6_3: # %.lr.ph.i29
# =>This Inner Loop Header: Depth=1
xorl %edi, %edi
callq time
leal (%r12,%rax), %edi
callq srand
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB6_3
# %bb.4: # %_Z16randomFillMatrix6Matrix.exit34
movabsq $137438953504, %rax # imm = 0x2000000020
movq %rax, 104(%rsp)
movl $32, 112(%rsp)
movq %rbx, 120(%rsp)
movq %rax, 80(%rsp)
movl $32, 88(%rsp)
movq %r14, 96(%rsp)
movq %rax, 128(%rsp)
movl $32, 136(%rsp)
movq %r15, 144(%rsp)
movq %r15, 64(%rsp)
movups 128(%rsp), %xmm0
movups %xmm0, 48(%rsp)
movq 96(%rsp), %rax
movq %rax, 40(%rsp)
movups 80(%rsp), %xmm0
movups %xmm0, 24(%rsp)
movq 120(%rsp), %rax
movq %rax, 16(%rsp)
movups 104(%rsp), %xmm0
movups %xmm0, (%rsp)
callq _Z6MatMul6MatrixS_S_
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12MatMulKernel6MatrixS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19MatMulSharedMemory16MatrixS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "File: %s, line: %d, CUDA error: %s\n"
.size .L.str, 36
.type _Z12MatMulKernel6MatrixS_S_,@object # @_Z12MatMulKernel6MatrixS_S_
.section .rodata,"a",@progbits
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 3, 0x0
_Z12MatMulKernel6MatrixS_S_:
.quad _Z27__device_stub__MatMulKernel6MatrixS_S_
.size _Z12MatMulKernel6MatrixS_S_, 8
.type _Z19MatMulSharedMemory16MatrixS_S_,@object # @_Z19MatMulSharedMemory16MatrixS_S_
.globl _Z19MatMulSharedMemory16MatrixS_S_
.p2align 3, 0x0
_Z19MatMulSharedMemory16MatrixS_S_:
.quad _Z34__device_stub__MatMulSharedMemory16MatrixS_S_
.size _Z19MatMulSharedMemory16MatrixS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/shaoguangcheng/ToyCode/master/cpp/cuda/MatMul.hip"
.size .L.str.1, 107
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12MatMulKernel6MatrixS_S_"
.size .L__unnamed_1, 28
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19MatMulSharedMemory16MatrixS_S_"
.size .L__unnamed_2, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Correct"
.size .Lstr, 8
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Error occur"
.size .Lstr.1, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__MatMulKernel6MatrixS_S_
.addrsig_sym _Z34__device_stub__MatMulSharedMemory16MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12MatMulKernel6MatrixS_S_
.addrsig_sym _Z19MatMulSharedMemory16MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015e3ec_00000000-6_MatMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "File: %s, line: %d, CUDA error: %s\n"
.text
.globl _Z14checkCudaError9cudaErrorPKci
.type _Z14checkCudaError9cudaErrorPKci, @function
_Z14checkCudaError9cudaErrorPKci:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebp, %ecx
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14checkCudaError9cudaErrorPKci, .-_Z14checkCudaError9cudaErrorPKci
.globl _Z10getElement6Matrixii
.type _Z10getElement6Matrixii, @function
_Z10getElement6Matrixii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z10getElement6Matrixii, .-_Z10getElement6Matrixii
.globl _Z10setElement6Matrixiif
.type _Z10setElement6Matrixiif, @function
_Z10setElement6Matrixiif:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z10setElement6Matrixiif, .-_Z10setElement6Matrixiif
.globl _Z12getSubMatrix6Matrixii
.type _Z12getSubMatrix6Matrixii, @function
_Z12getSubMatrix6Matrixii:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z12getSubMatrix6Matrixii, .-_Z12getSubMatrix6Matrixii
.globl _Z7divCeilii
.type _Z7divCeilii, @function
_Z7divCeilii:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z7divCeilii, .-_Z7divCeilii
.globl _Z16checkCorrectness6MatrixS_S_
.type _Z16checkCorrectness6MatrixS_S_, @function
_Z16checkCorrectness6MatrixS_S_:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl 112(%rsp), %ebx
movl 160(%rsp), %r12d
movl 164(%rsp), %r14d
movl %r14d, 4(%rsp)
movl 168(%rsp), %r15d
movslq %r12d, %rbp
movslq %r14d, %rax
imulq %rbp, %rax
salq $2, %rax
movq %rax, 40(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
testl %r14d, %r14d
jle .L18
movq 128(%rsp), %r14
movq 152(%rsp), %rax
movq %rax, 24(%rsp)
movl 120(%rsp), %eax
movl %eax, 16(%rsp)
movslq 144(%rsp), %rsi
salq $2, %rsi
movl $0, %r13d
movl $0, %r11d
movl $0, %edx
movslq %ebx, %rax
movq %rax, 32(%rsp)
movl %r12d, 20(%rsp)
jmp .L19
.L20:
movss (%rax), %xmm0
mulss (%rcx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %rsi, %rcx
cmpq %rdi, %rax
jne .L20
.L22:
movss %xmm1, (%r10,%r8,4)
addq $1, %r8
addq $4, %r9
cmpq %r8, %rbp
je .L21
.L23:
movq %r9, %rcx
movq %r12, %rax
pxor %xmm1, %xmm1
testl %ebx, %ebx
jg .L20
jmp .L22
.L21:
addl $1, %edx
addl %r15d, %r11d
movl 16(%rsp), %eax
addl %eax, %r13d
cmpl %edx, 4(%rsp)
je .L18
.L19:
cmpl $0, 20(%rsp)
jle .L21
movq 24(%rsp), %r9
movslq %r13d, %rax
leaq (%r14,%rax,4), %r12
movq 32(%rsp), %rdi
addq %rdi, %rax
leaq (%r14,%rax,4), %rdi
movslq %r11d, %rax
movq 8(%rsp), %rcx
leaq (%rcx,%rax,4), %r10
movl $0, %r8d
jmp .L23
.L18:
movq 40(%rsp), %rdx
movq 176(%rsp), %rsi
movq 8(%rsp), %r15
movq %r15, %rdi
call memcmp@PLT
movl %eax, %ebx
movq %r15, %rdi
call free@PLT
testl %ebx, %ebx
sete %al
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z16checkCorrectness6MatrixS_S_, .-_Z16checkCorrectness6MatrixS_S_
.globl _Z16randomFillMatrix6Matrix
.type _Z16randomFillMatrix6Matrix, @function
_Z16randomFillMatrix6Matrix:
.LFB2064:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl 32(%rsp), %ebp
imull 36(%rsp), %ebp
testl %ebp, %ebp
jle .L30
movslq %ebp, %rbp
movl $0, %ebx
.L32:
movl $0, %edi
call time@PLT
leal (%rax,%rbx), %edi
call srand@PLT
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movq 48(%rsp), %rax
movss %xmm0, (%rax,%rbx,4)
addq $1, %rbx
cmpq %rbp, %rbx
jne .L32
.L30:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _Z16randomFillMatrix6Matrix, .-_Z16randomFillMatrix6Matrix
.globl _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
.type _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_, @function
_Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_:
.LFB2090:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_, .-_Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
.globl _Z12MatMulKernel6MatrixS_S_
.type _Z12MatMulKernel6MatrixS_S_, @function
_Z12MatMulKernel6MatrixS_S_:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 64(%rsp), %rdx
leaq 40(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z12MatMulKernel6MatrixS_S_, .-_Z12MatMulKernel6MatrixS_S_
.globl _Z48__device_stub__Z19MatMulSharedMemory16MatrixS_S_R6MatrixS0_S0_
.type _Z48__device_stub__Z19MatMulSharedMemory16MatrixS_S_R6MatrixS0_S0_, @function
_Z48__device_stub__Z19MatMulSharedMemory16MatrixS_S_R6MatrixS0_S0_:
.LFB2092:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z19MatMulSharedMemory16MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z48__device_stub__Z19MatMulSharedMemory16MatrixS_S_R6MatrixS0_S0_, .-_Z48__device_stub__Z19MatMulSharedMemory16MatrixS_S_R6MatrixS0_S0_
.globl _Z19MatMulSharedMemory16MatrixS_S_
.type _Z19MatMulSharedMemory16MatrixS_S_, @function
_Z19MatMulSharedMemory16MatrixS_S_:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 64(%rsp), %rdx
leaq 40(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z48__device_stub__Z19MatMulSharedMemory16MatrixS_S_R6MatrixS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z19MatMulSharedMemory16MatrixS_S_, .-_Z19MatMulSharedMemory16MatrixS_S_
.section .rodata.str1.8
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/shaoguangcheng/ToyCode/master/cpp/cuda/MatMul.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Error occur\n"
.LC4:
.string "Correct\n"
.text
.globl _Z6MatMul6MatrixS_S_
.type _Z6MatMul6MatrixS_S_, @function
_Z6MatMul6MatrixS_S_:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $232, %rsp
.cfi_def_cfa_offset 256
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
movl 256(%rsp), %ebx
movl %ebx, 32(%rsp)
movl 260(%rsp), %eax
movl %eax, 36(%rsp)
movl 264(%rsp), %edx
movl %edx, 40(%rsp)
movl 280(%rsp), %edx
movl %edx, 64(%rsp)
movl 284(%rsp), %edx
movl %edx, 68(%rsp)
movl 288(%rsp), %edx
movl %edx, 72(%rsp)
movl 304(%rsp), %edx
movl %edx, 96(%rsp)
movl 308(%rsp), %edx
movl %edx, 100(%rsp)
movl 312(%rsp), %edx
movl %edx, 104(%rsp)
imull %eax, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 48(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $165, %edx
leaq .LC2(%rip), %rbp
movq %rbp, %rsi
call _Z14checkCudaError9cudaErrorPKci
movl $1, %ecx
movq %rbx, %rdx
movq 272(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $166, %edx
movq %rbp, %rsi
call _Z14checkCudaError9cudaErrorPKci
movl 68(%rsp), %ebx
imull 64(%rsp), %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $169, %edx
movq %rbp, %rsi
call _Z14checkCudaError9cudaErrorPKci
movl $1, %ecx
movq %rbx, %rdx
movq 296(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $170, %edx
movq %rbp, %rsi
call _Z14checkCudaError9cudaErrorPKci
movl 100(%rsp), %ebx
imull 96(%rsp), %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 112(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $173, %edx
movq %rbp, %rsi
call _Z14checkCudaError9cudaErrorPKci
movl 100(%rsp), %eax
movl 96(%rsp), %edx
testb $15, %dl
setne %cl
movzbl %cl, %ecx
shrl $4, %edx
addl %ecx, %edx
movl %edx, 20(%rsp)
testb $15, %al
setne %dl
movzbl %dl, %edx
shrl $4, %eax
addl %edx, %eax
movl %eax, 24(%rsp)
movl $16, 8(%rsp)
movl $16, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L57
.L52:
movl $2, %ecx
movq %rbx, %rdx
movq 112(%rsp), %rsi
movq 320(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $181, %edx
leaq .LC2(%rip), %rsi
call _Z14checkCudaError9cudaErrorPKci
subq $80, %rsp
.cfi_def_cfa_offset 336
movdqu 384(%rsp), %xmm0
movups %xmm0, 48(%rsp)
movq 400(%rsp), %rax
movq %rax, 64(%rsp)
movdqu 360(%rsp), %xmm1
movups %xmm1, 24(%rsp)
movq 376(%rsp), %rax
movq %rax, 40(%rsp)
movdqu 336(%rsp), %xmm2
movups %xmm2, (%rsp)
movq 352(%rsp), %rax
movq %rax, 16(%rsp)
call _Z16checkCorrectness6MatrixS_S_
addq $80, %rsp
.cfi_def_cfa_offset 256
testb %al, %al
jne .L53
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
.L54:
movq 48(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $188, %edx
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
call _Z14checkCudaError9cudaErrorPKci
movq 80(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $189, %edx
movq %rbx, %rsi
call _Z14checkCudaError9cudaErrorPKci
movq 112(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $190, %edx
movq %rbx, %rsi
call _Z14checkCudaError9cudaErrorPKci
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L58
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
movdqa 32(%rsp), %xmm3
movaps %xmm3, 128(%rsp)
movq 48(%rsp), %rax
movq %rax, 144(%rsp)
movdqa 64(%rsp), %xmm4
movaps %xmm4, 160(%rsp)
movq 80(%rsp), %rax
movq %rax, 176(%rsp)
movdqa 96(%rsp), %xmm5
movaps %xmm5, 192(%rsp)
movq 112(%rsp), %rax
movq %rax, 208(%rsp)
leaq 192(%rsp), %rdx
leaq 160(%rsp), %rsi
leaq 128(%rsp), %rdi
call _Z48__device_stub__Z19MatMulSharedMemory16MatrixS_S_R6MatrixS0_S0_
jmp .L52
.L53:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L54
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z6MatMul6MatrixS_S_, .-_Z6MatMul6MatrixS_S_
.globl main
.type main, @function
main:
.LFB2065:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $96, %rsp
.cfi_def_cfa_offset 128
movl $32, 32(%rsp)
movl $32, 64(%rsp)
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
movl $4096, %edi
call malloc@PLT
movq %rax, %rbx
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $32, (%rsp)
movl $32, 4(%rsp)
movl $32, 8(%rsp)
movq %rbp, 16(%rsp)
subq $32, %rsp
.cfi_def_cfa_offset 160
movdqa 32(%rsp), %xmm0
movups %xmm0, (%rsp)
movq %rbp, 16(%rsp)
call _Z16randomFillMatrix6Matrix
movl $32, 68(%rsp)
movl $32, 72(%rsp)
movq %rbx, 80(%rsp)
movdqa 64(%rsp), %xmm1
movups %xmm1, (%rsp)
movq %rbx, 16(%rsp)
call _Z16randomFillMatrix6Matrix
movl $32, 100(%rsp)
movl $32, 104(%rsp)
subq $48, %rsp
.cfi_def_cfa_offset 208
movdqa 144(%rsp), %xmm2
movups %xmm2, 48(%rsp)
movq %r12, 64(%rsp)
movdqa 112(%rsp), %xmm3
movups %xmm3, 24(%rsp)
movq 128(%rsp), %rax
movq %rax, 40(%rsp)
movdqa 80(%rsp), %xmm4
movups %xmm4, (%rsp)
movq 96(%rsp), %rax
movq %rax, 16(%rsp)
call _Z6MatMul6MatrixS_S_
addq $80, %rsp
.cfi_def_cfa_offset 128
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movl $0, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC5:
.string "_Z19MatMulSharedMemory16MatrixS_S_"
.section .rodata.str1.1
.LC6:
.string "_Z12MatMulKernel6MatrixS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z19MatMulSharedMemory16MatrixS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MatMul.hip"
.globl _Z14checkCudaError10hipError_tPKci # -- Begin function _Z14checkCudaError10hipError_tPKci
.p2align 4, 0x90
.type _Z14checkCudaError10hipError_tPKci,@function
_Z14checkCudaError10hipError_tPKci: # @_Z14checkCudaError10hipError_tPKci
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edx, %ebx
movq %rsi, %r14
callq hipGetErrorString
movl $.L.str, %edi
movq %r14, %rsi
movl %ebx, %edx
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z14checkCudaError10hipError_tPKci, .Lfunc_end0-_Z14checkCudaError10hipError_tPKci
.cfi_endproc
# -- End function
.globl _Z27__device_stub__MatMulKernel6MatrixS_S_ # -- Begin function _Z27__device_stub__MatMulKernel6MatrixS_S_
.p2align 4, 0x90
.type _Z27__device_stub__MatMulKernel6MatrixS_S_,@function
_Z27__device_stub__MatMulKernel6MatrixS_S_: # @_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 80(%rsp), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z27__device_stub__MatMulKernel6MatrixS_S_, .Lfunc_end1-_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z34__device_stub__MatMulSharedMemory16MatrixS_S_ # -- Begin function _Z34__device_stub__MatMulSharedMemory16MatrixS_S_
.p2align 4, 0x90
.type _Z34__device_stub__MatMulSharedMemory16MatrixS_S_,@function
_Z34__device_stub__MatMulSharedMemory16MatrixS_S_: # @_Z34__device_stub__MatMulSharedMemory16MatrixS_S_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 80(%rsp), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z19MatMulSharedMemory16MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z34__device_stub__MatMulSharedMemory16MatrixS_S_, .Lfunc_end2-_Z34__device_stub__MatMulSharedMemory16MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z16checkCorrectness6MatrixS_S_ # -- Begin function _Z16checkCorrectness6MatrixS_S_
.p2align 4, 0x90
.type _Z16checkCorrectness6MatrixS_S_,@function
_Z16checkCorrectness6MatrixS_S_: # @_Z16checkCorrectness6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movslq 112(%rsp), %rdi
movl %edi, %r15d
movslq 116(%rsp), %r14
movslq 120(%rsp), %r12
imulq %r14, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %rbx
movl %r14d, %eax
testq %r14, %r14
jle .LBB3_9
# %bb.1: # %.preheader26.lr.ph
leaq 88(%rsp), %r8
leaq 64(%rsp), %rsi
movl (%rsi), %ecx
movq 16(%rsi), %rdx
movslq 8(%rsi), %rsi
movq 16(%r8), %rdi
movslq 8(%r8), %r8
shlq $2, %rsi
shlq $2, %r8
xorl %r9d, %r9d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_8: # %._crit_edge30
# in Loop: Header=BB3_2 Depth=1
incq %r9
addq %rsi, %rdx
cmpq %rax, %r9
je .LBB3_9
.LBB3_2: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
# Child Loop BB3_6 Depth 3
testl %r15d, %r15d
jle .LBB3_8
# %bb.3: # %.preheader.lr.ph
# in Loop: Header=BB3_2 Depth=1
movq %r9, %r10
imulq %r12, %r10
leaq (%rbx,%r10,4), %r10
movq %rdi, %r11
xorl %r13d, %r13d
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_4 Depth=2
movss %xmm0, (%r10,%r13,4)
incq %r13
addq $4, %r11
cmpq %r15, %r13
je .LBB3_8
.LBB3_4: # %.preheader
# Parent Loop BB3_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_6 Depth 3
xorps %xmm0, %xmm0
testl %ecx, %ecx
jle .LBB3_7
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB3_4 Depth=2
movq %r11, %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_6: # %.lr.ph
# Parent Loop BB3_2 Depth=1
# Parent Loop BB3_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdx,%r14,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rbp), %xmm1
addss %xmm1, %xmm0
incq %r14
addq %r8, %rbp
cmpq %r14, %rcx
jne .LBB3_6
jmp .LBB3_7
.LBB3_9: # %._crit_edge32
leaq 112(%rsp), %rcx
movq 16(%rcx), %rsi
imull %r15d, %eax
movslq %eax, %rdx
shlq $2, %rdx
movq %rbx, %rdi
callq bcmp@PLT
testl %eax, %eax
sete %bpl
movq %rbx, %rdi
callq free
movl %ebp, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z16checkCorrectness6MatrixS_S_, .Lfunc_end3-_Z16checkCorrectness6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z6MatMul6MatrixS_S_ # -- Begin function _Z6MatMul6MatrixS_S_
.p2align 4, 0x90
.type _Z6MatMul6MatrixS_S_,@function
_Z6MatMul6MatrixS_S_: # @_Z6MatMul6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl 352(%rsp), %r13d
movl 356(%rsp), %eax
movl %r13d, 64(%rsp)
movl %eax, 68(%rsp)
movslq 360(%rsp), %rcx
movq %rcx, 120(%rsp) # 8-byte Spill
movl %ecx, 72(%rsp)
movq 376(%rsp), %rcx
movq %rcx, 40(%rsp)
movslq 384(%rsp), %rbp
movl %ebp, 48(%rsp)
movslq 400(%rsp), %rcx
movq %rcx, 8(%rsp) # 8-byte Spill
movl %ecx, 16(%rsp)
movslq 404(%rsp), %rcx
movq %rcx, 104(%rsp) # 8-byte Spill
movl %ecx, 20(%rsp)
movslq 408(%rsp), %rcx
movq %rcx, 112(%rsp) # 8-byte Spill
movl %ecx, 24(%rsp)
imull %r13d, %eax
shll $2, %eax
leaq 80(%rsp), %rdi
movslq %eax, %r14
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_1
# %bb.3: # %_Z14checkCudaError10hipError_tPKci.exit
leaq 352(%rsp), %rax
movq 80(%rsp), %rdi
movq 16(%rax), %rbx
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_4
# %bb.5: # %_Z14checkCudaError10hipError_tPKci.exit14
movl 40(%rsp), %eax
imull 44(%rsp), %eax
shll $2, %eax
leaq 56(%rsp), %rdi
movslq %eax, %r15
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_6
# %bb.7: # %_Z14checkCudaError10hipError_tPKci.exit16
leaq 376(%rsp), %rax
movq 56(%rsp), %rdi
movq 16(%rax), %r14
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_8
# %bb.9: # %_Z14checkCudaError10hipError_tPKci.exit18
movl 16(%rsp), %eax
imull 20(%rsp), %eax
shll $2, %eax
leaq 32(%rsp), %rdi
movslq %eax, %r12
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_10
# %bb.11: # %_Z14checkCudaError10hipError_tPKci.exit20
leaq 400(%rsp), %r15
movl 16(%rsp), %eax
movl 20(%rsp), %ecx
movl %eax, %edx
shrl $4, %edx
andl $15, %eax
cmpl $1, %eax
sbbl $-1, %edx
movl %ecx, %edi
shrl $4, %edi
andl $15, %ecx
cmpl $1, %ecx
sbbl $-1, %edi
shlq $32, %rdi
orq %rdx, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_13
# %bb.12:
movq 80(%rsp), %rax
movq %rax, 224(%rsp)
movups 64(%rsp), %xmm0
movaps %xmm0, 208(%rsp)
movq 56(%rsp), %rax
movq %rax, 256(%rsp)
movups 40(%rsp), %xmm0
movaps %xmm0, 240(%rsp)
movq 32(%rsp), %rax
movq %rax, 288(%rsp)
movups 16(%rsp), %xmm0
movaps %xmm0, 272(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
leaq 240(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 160(%rsp), %rdi
leaq 144(%rsp), %rsi
leaq 136(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
movq 144(%rsp), %rcx
movl 152(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z19MatMulSharedMemory16MatrixS_S_, %edi
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_13:
movq %r14, 96(%rsp) # 8-byte Spill
movq 16(%r15), %rdi
movq 32(%rsp), %rsi
movq %rdi, 88(%rsp) # 8-byte Spill
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_14
# %bb.15: # %_Z14checkCudaError10hipError_tPKci.exit22
movq 104(%rsp), %r14 # 8-byte Reload
movl %r14d, %r15d
movq %r14, %rdi
imulq 8(%rsp), %rdi # 8-byte Folded Reload
shlq $2, %rdi
callq malloc
movq %rax, %r12
testl %r14d, %r14d
movq 120(%rsp), %r10 # 8-byte Reload
movq 112(%rsp), %r11 # 8-byte Reload
movq 96(%rsp), %r14 # 8-byte Reload
jle .LBB4_22
# %bb.16: # %.preheader26.lr.ph.i
movl 8(%rsp), %eax # 4-byte Reload
shlq $2, %rbp
shlq $2, %r10
xorl %ecx, %ecx
jmp .LBB4_17
.p2align 4, 0x90
.LBB4_21: # %._crit_edge30.i
# in Loop: Header=BB4_17 Depth=1
incq %rcx
addq %r10, %rbx
cmpq %r15, %rcx
je .LBB4_22
.LBB4_17: # %.preheader26.i
# =>This Loop Header: Depth=1
# Child Loop BB4_19 Depth 2
# Child Loop BB4_25 Depth 3
testl %eax, %eax
jle .LBB4_21
# %bb.18: # %.preheader.lr.ph.i
# in Loop: Header=BB4_17 Depth=1
movq %rcx, %rdx
imulq %r11, %rdx
leaq (%r12,%rdx,4), %rdx
movq %r14, %rsi
xorl %edi, %edi
jmp .LBB4_19
.p2align 4, 0x90
.LBB4_20: # %._crit_edge.i
# in Loop: Header=BB4_19 Depth=2
movss %xmm0, (%rdx,%rdi,4)
incq %rdi
addq $4, %rsi
cmpq %rax, %rdi
je .LBB4_21
.LBB4_19: # %.preheader.i
# Parent Loop BB4_17 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_25 Depth 3
xorps %xmm0, %xmm0
testl %r13d, %r13d
jle .LBB4_20
# %bb.24: # %.lr.ph.preheader.i
# in Loop: Header=BB4_19 Depth=2
movq %rsi, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB4_25: # %.lr.ph.i
# Parent Loop BB4_17 Depth=1
# Parent Loop BB4_19 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rbx,%r9,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r8), %xmm1
addss %xmm1, %xmm0
incq %r9
addq %rbp, %r8
cmpq %r9, %r13
jne .LBB4_25
jmp .LBB4_20
.LBB4_22: # %_Z16checkCorrectness6MatrixS_S_.exit
movq 8(%rsp), %rax # 8-byte Reload
imull %r15d, %eax
movslq %eax, %rdx
shlq $2, %rdx
movq %r12, %rdi
movq 88(%rsp), %rsi # 8-byte Reload
callq bcmp@PLT
movl %eax, %ebx
movq %r12, %rdi
callq free
testl %ebx, %ebx
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq 80(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_23
# %bb.26: # %_Z14checkCudaError10hipError_tPKci.exit24
movq 56(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_27
# %bb.28: # %_Z14checkCudaError10hipError_tPKci.exit26
movq 32(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_29
# %bb.30: # %_Z14checkCudaError10hipError_tPKci.exit28
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 352
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $167, %edx
jmp .LBB4_2
.LBB4_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $168, %edx
jmp .LBB4_2
.LBB4_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $171, %edx
jmp .LBB4_2
.LBB4_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $172, %edx
jmp .LBB4_2
.LBB4_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $175, %edx
jmp .LBB4_2
.LBB4_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $183, %edx
jmp .LBB4_2
.LBB4_23:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $190, %edx
jmp .LBB4_2
.LBB4_27:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $191, %edx
jmp .LBB4_2
.LBB4_29:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $192, %edx
.LBB4_2:
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end4:
.size _Z6MatMul6MatrixS_S_, .Lfunc_end4-_Z6MatMul6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z16randomFillMatrix6Matrix # -- Begin function _Z16randomFillMatrix6Matrix
.p2align 4, 0x90
.type _Z16randomFillMatrix6Matrix,@function
_Z16randomFillMatrix6Matrix: # @_Z16randomFillMatrix6Matrix
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl 36(%rsp), %eax
imull 32(%rsp), %eax
testl %eax, %eax
jle .LBB5_3
# %bb.1: # %.lr.ph
leaq 32(%rsp), %rcx
movq 16(%rcx), %rbx
movl %eax, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_2: # =>This Inner Loop Header: Depth=1
xorl %edi, %edi
callq time
leal (%r15,%rax), %edi
callq srand
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB5_2
.LBB5_3: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z16randomFillMatrix6Matrix, .Lfunc_end5-_Z16randomFillMatrix6Matrix
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.lr.ph.i
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB6_1: # =>This Inner Loop Header: Depth=1
xorl %edi, %edi
callq time
leal (%r12,%rax), %edi
callq srand
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB6_1
# %bb.2: # %.lr.ph.i29.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB6_3: # %.lr.ph.i29
# =>This Inner Loop Header: Depth=1
xorl %edi, %edi
callq time
leal (%r12,%rax), %edi
callq srand
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB6_3
# %bb.4: # %_Z16randomFillMatrix6Matrix.exit34
movabsq $137438953504, %rax # imm = 0x2000000020
movq %rax, 104(%rsp)
movl $32, 112(%rsp)
movq %rbx, 120(%rsp)
movq %rax, 80(%rsp)
movl $32, 88(%rsp)
movq %r14, 96(%rsp)
movq %rax, 128(%rsp)
movl $32, 136(%rsp)
movq %r15, 144(%rsp)
movq %r15, 64(%rsp)
movups 128(%rsp), %xmm0
movups %xmm0, 48(%rsp)
movq 96(%rsp), %rax
movq %rax, 40(%rsp)
movups 80(%rsp), %xmm0
movups %xmm0, 24(%rsp)
movq 120(%rsp), %rax
movq %rax, 16(%rsp)
movups 104(%rsp), %xmm0
movups %xmm0, (%rsp)
callq _Z6MatMul6MatrixS_S_
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12MatMulKernel6MatrixS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19MatMulSharedMemory16MatrixS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "File: %s, line: %d, CUDA error: %s\n"
.size .L.str, 36
.type _Z12MatMulKernel6MatrixS_S_,@object # @_Z12MatMulKernel6MatrixS_S_
.section .rodata,"a",@progbits
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 3, 0x0
_Z12MatMulKernel6MatrixS_S_:
.quad _Z27__device_stub__MatMulKernel6MatrixS_S_
.size _Z12MatMulKernel6MatrixS_S_, 8
.type _Z19MatMulSharedMemory16MatrixS_S_,@object # @_Z19MatMulSharedMemory16MatrixS_S_
.globl _Z19MatMulSharedMemory16MatrixS_S_
.p2align 3, 0x0
_Z19MatMulSharedMemory16MatrixS_S_:
.quad _Z34__device_stub__MatMulSharedMemory16MatrixS_S_
.size _Z19MatMulSharedMemory16MatrixS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/shaoguangcheng/ToyCode/master/cpp/cuda/MatMul.hip"
.size .L.str.1, 107
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12MatMulKernel6MatrixS_S_"
.size .L__unnamed_1, 28
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19MatMulSharedMemory16MatrixS_S_"
.size .L__unnamed_2, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Correct"
.size .Lstr, 8
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Error occur"
.size .Lstr.1, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__MatMulKernel6MatrixS_S_
.addrsig_sym _Z34__device_stub__MatMulSharedMemory16MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12MatMulKernel6MatrixS_S_
.addrsig_sym _Z19MatMulSharedMemory16MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
#define N 32
__global__ void iwarp(int* out)
{
__shared__ volatile int smem[32];
volatile int* vout = out;
int idx = threadIdx.x;
smem[idx] = vout[idx];
if(idx % 2 == 0)
smem[idx] = 1;
else
smem[idx-1] = 0;
vout[idx] = smem[idx];
}
int main()
{
int* din;
cudaMalloc((void**)&din, N*sizeof(int));
int in[N];
for(int i = 0; i < N; i++)
in[i] = 0;
cudaMemcpy(din, &in, N*sizeof(int), cudaMemcpyHostToDevice);
iwarp<<<1,N>>>(din);
int output[N];
cudaMemcpy(&output, din, N*sizeof(int), cudaMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d ", output[i]);
printf("\n");
} | code for sm_80
Function : _Z5iwarpPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x001fca00078e0202 */
/*0050*/ LDG.E.STRONG.SYS R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1f5900 */
/*0060*/ LOP3.LUT R4, R7, 0x1, RZ, 0xc0, !PT ; /* 0x0000000107047812 */
/* 0x000fc800078ec0ff */
/*0070*/ ISETP.NE.U32.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f05070 */
/*0080*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff040424 */
/* 0x000fe200078e00ff */
/*0090*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x004fe80000004800 */
/*00a0*/ @!P0 STS [R7.X4+-0x4], RZ ; /* 0xfffffcff07008388 */
/* 0x000fe80000004800 */
/*00b0*/ @P0 STS [R7.X4], R4 ; /* 0x0000000407000388 */
/* 0x000fe80000004800 */
/*00c0*/ LDS R5, [R7.X4] ; /* 0x0000000007057984 */
/* 0x000e280000004800 */
/*00d0*/ STG.E.STRONG.SYS [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c115904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#define N 32
__global__ void iwarp(int* out)
{
__shared__ volatile int smem[32];
volatile int* vout = out;
int idx = threadIdx.x;
smem[idx] = vout[idx];
if(idx % 2 == 0)
smem[idx] = 1;
else
smem[idx-1] = 0;
vout[idx] = smem[idx];
}
int main()
{
int* din;
cudaMalloc((void**)&din, N*sizeof(int));
int in[N];
for(int i = 0; i < N; i++)
in[i] = 0;
cudaMemcpy(din, &in, N*sizeof(int), cudaMemcpyHostToDevice);
iwarp<<<1,N>>>(din);
int output[N];
cudaMemcpy(&output, din, N*sizeof(int), cudaMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d ", output[i]);
printf("\n");
} | .file "tmpxft_0004e3cf_00000000-6_interwarp_1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z5iwarpPiPi
.type _Z24__device_stub__Z5iwarpPiPi, @function
_Z24__device_stub__Z5iwarpPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5iwarpPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z5iwarpPiPi, .-_Z24__device_stub__Z5iwarpPiPi
.globl _Z5iwarpPi
.type _Z5iwarpPi, @function
_Z5iwarpPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z5iwarpPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5iwarpPi, .-_Z5iwarpPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $304, %rsp
.cfi_def_cfa_offset 336
movq %fs:40, %rax
movq %rax, 296(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rax
leaq 160(%rsp), %rdx
.L12:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $128, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 160(%rsp), %rbx
movl $2, %ecx
movl $128, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 288(%rsp), %r12
leaq .LC0(%rip), %rbp
.L14:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $304, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq (%rsp), %rdi
call _Z24__device_stub__Z5iwarpPiPi
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z5iwarpPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z5iwarpPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#define N 32
__global__ void iwarp(int* out)
{
__shared__ volatile int smem[32];
volatile int* vout = out;
int idx = threadIdx.x;
smem[idx] = vout[idx];
if(idx % 2 == 0)
smem[idx] = 1;
else
smem[idx-1] = 0;
vout[idx] = smem[idx];
}
int main()
{
int* din;
cudaMalloc((void**)&din, N*sizeof(int));
int in[N];
for(int i = 0; i < N; i++)
in[i] = 0;
cudaMemcpy(din, &in, N*sizeof(int), cudaMemcpyHostToDevice);
iwarp<<<1,N>>>(din);
int output[N];
cudaMemcpy(&output, din, N*sizeof(int), cudaMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d ", output[i]);
printf("\n");
} | #include <hip/hip_runtime.h>
#include <cstdio>
#define N 32
__global__ void iwarp(int* out)
{
__shared__ volatile int smem[32];
volatile int* vout = out;
int idx = threadIdx.x;
smem[idx] = vout[idx];
if(idx % 2 == 0)
smem[idx] = 1;
else
smem[idx-1] = 0;
vout[idx] = smem[idx];
}
int main()
{
int* din;
hipMalloc((void**)&din, N*sizeof(int));
int in[N];
for(int i = 0; i < N; i++)
in[i] = 0;
hipMemcpy(din, &in, N*sizeof(int), hipMemcpyHostToDevice);
iwarp<<<1,N>>>(din);
int output[N];
hipMemcpy(&output, din, N*sizeof(int), hipMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d ", output[i]);
printf("\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#define N 32
__global__ void iwarp(int* out)
{
__shared__ volatile int smem[32];
volatile int* vout = out;
int idx = threadIdx.x;
smem[idx] = vout[idx];
if(idx % 2 == 0)
smem[idx] = 1;
else
smem[idx-1] = 0;
vout[idx] = smem[idx];
}
int main()
{
int* din;
hipMalloc((void**)&din, N*sizeof(int));
int in[N];
for(int i = 0; i < N; i++)
in[i] = 0;
hipMemcpy(din, &in, N*sizeof(int), hipMemcpyHostToDevice);
iwarp<<<1,N>>>(din);
int output[N];
hipMemcpy(&output, din, N*sizeof(int), hipMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d ", output[i]);
printf("\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5iwarpPi
.globl _Z5iwarpPi
.p2align 8
.type _Z5iwarpPi,@function
_Z5iwarpPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
v_and_b32_e32 v7, 1, v0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, s0, s0, v3
v_add_co_ci_u32_e64 v2, null, s1, 0, s0
s_mov_b64 s[0:1], src_shared_base
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cndmask_b32_e64 v4, 0, s1, vcc_lo
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[3:4], v6 dlc
s_waitcnt_vscnt null, 0x0
v_cmpx_eq_u32_e32 1, v7
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_2
v_lshl_add_u32 v0, v0, 2, -4
s_mov_b64 s[2:3], src_shared_base
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v0
v_cndmask_b32_e32 v6, 0, v0, vcc_lo
v_cndmask_b32_e64 v7, 0, s3, vcc_lo
flat_store_b32 v[6:7], v5 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_2:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v0, 1
flat_store_b32 v[3:4], v0 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
flat_load_b32 v0, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b32 v[1:2], v0 dlc
s_waitcnt_vscnt null, 0x0
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5iwarpPi
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5iwarpPi, .Lfunc_end0-_Z5iwarpPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5iwarpPi
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z5iwarpPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#define N 32
__global__ void iwarp(int* out)
{
__shared__ volatile int smem[32];
volatile int* vout = out;
int idx = threadIdx.x;
smem[idx] = vout[idx];
if(idx % 2 == 0)
smem[idx] = 1;
else
smem[idx-1] = 0;
vout[idx] = smem[idx];
}
int main()
{
int* din;
hipMalloc((void**)&din, N*sizeof(int));
int in[N];
for(int i = 0; i < N; i++)
in[i] = 0;
hipMemcpy(din, &in, N*sizeof(int), hipMemcpyHostToDevice);
iwarp<<<1,N>>>(din);
int output[N];
hipMemcpy(&output, din, N*sizeof(int), hipMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d ", output[i]);
printf("\n");
} | .text
.file "interwarp_1.hip"
.globl _Z20__device_stub__iwarpPi # -- Begin function _Z20__device_stub__iwarpPi
.p2align 4, 0x90
.type _Z20__device_stub__iwarpPi,@function
_Z20__device_stub__iwarpPi: # @_Z20__device_stub__iwarpPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z5iwarpPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z20__device_stub__iwarpPi, .Lfunc_end0-_Z20__device_stub__iwarpPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $320, %rsp # imm = 0x140
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
xorps %xmm0, %xmm0
movaps %xmm0, 176(%rsp)
movaps %xmm0, 160(%rsp)
movaps %xmm0, 144(%rsp)
movaps %xmm0, 128(%rsp)
movaps %xmm0, 112(%rsp)
movaps %xmm0, 96(%rsp)
movaps %xmm0, 80(%rsp)
movaps %xmm0, 64(%rsp)
movq 8(%rsp), %rdi
leaq 64(%rsp), %rsi
movl $128, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
leaq 192(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 192(%rsp), %rsi
movl 200(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z5iwarpPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 192(%rsp), %rdi
movl $128, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl 192(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $32, %rbx
jne .LBB1_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $320, %rsp # imm = 0x140
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5iwarpPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5iwarpPi,@object # @_Z5iwarpPi
.section .rodata,"a",@progbits
.globl _Z5iwarpPi
.p2align 3, 0x0
_Z5iwarpPi:
.quad _Z20__device_stub__iwarpPi
.size _Z5iwarpPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5iwarpPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__iwarpPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5iwarpPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5iwarpPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x001fca00078e0202 */
/*0050*/ LDG.E.STRONG.SYS R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1f5900 */
/*0060*/ LOP3.LUT R4, R7, 0x1, RZ, 0xc0, !PT ; /* 0x0000000107047812 */
/* 0x000fc800078ec0ff */
/*0070*/ ISETP.NE.U32.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f05070 */
/*0080*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff040424 */
/* 0x000fe200078e00ff */
/*0090*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x004fe80000004800 */
/*00a0*/ @!P0 STS [R7.X4+-0x4], RZ ; /* 0xfffffcff07008388 */
/* 0x000fe80000004800 */
/*00b0*/ @P0 STS [R7.X4], R4 ; /* 0x0000000407000388 */
/* 0x000fe80000004800 */
/*00c0*/ LDS R5, [R7.X4] ; /* 0x0000000007057984 */
/* 0x000e280000004800 */
/*00d0*/ STG.E.STRONG.SYS [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c115904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5iwarpPi
.globl _Z5iwarpPi
.p2align 8
.type _Z5iwarpPi,@function
_Z5iwarpPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
v_and_b32_e32 v7, 1, v0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, s0, s0, v3
v_add_co_ci_u32_e64 v2, null, s1, 0, s0
s_mov_b64 s[0:1], src_shared_base
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cndmask_b32_e64 v4, 0, s1, vcc_lo
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0)
s_mov_b32 s0, exec_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[3:4], v6 dlc
s_waitcnt_vscnt null, 0x0
v_cmpx_eq_u32_e32 1, v7
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_2
v_lshl_add_u32 v0, v0, 2, -4
s_mov_b64 s[2:3], src_shared_base
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v0
v_cndmask_b32_e32 v6, 0, v0, vcc_lo
v_cndmask_b32_e64 v7, 0, s3, vcc_lo
flat_store_b32 v[6:7], v5 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_2:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v0, 1
flat_store_b32 v[3:4], v0 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
flat_load_b32 v0, v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b32 v[1:2], v0 dlc
s_waitcnt_vscnt null, 0x0
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5iwarpPi
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5iwarpPi, .Lfunc_end0-_Z5iwarpPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5iwarpPi
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z5iwarpPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004e3cf_00000000-6_interwarp_1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z5iwarpPiPi
.type _Z24__device_stub__Z5iwarpPiPi, @function
_Z24__device_stub__Z5iwarpPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5iwarpPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z5iwarpPiPi, .-_Z24__device_stub__Z5iwarpPiPi
.globl _Z5iwarpPi
.type _Z5iwarpPi, @function
_Z5iwarpPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z5iwarpPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5iwarpPi, .-_Z5iwarpPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $304, %rsp
.cfi_def_cfa_offset 336
movq %fs:40, %rax
movq %rax, 296(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rax
leaq 160(%rsp), %rdx
.L12:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $128, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 160(%rsp), %rbx
movl $2, %ecx
movl $128, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 288(%rsp), %r12
leaq .LC0(%rip), %rbp
.L14:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $304, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq (%rsp), %rdi
call _Z24__device_stub__Z5iwarpPiPi
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z5iwarpPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z5iwarpPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "interwarp_1.hip"
.globl _Z20__device_stub__iwarpPi # -- Begin function _Z20__device_stub__iwarpPi
.p2align 4, 0x90
.type _Z20__device_stub__iwarpPi,@function
_Z20__device_stub__iwarpPi: # @_Z20__device_stub__iwarpPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z5iwarpPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z20__device_stub__iwarpPi, .Lfunc_end0-_Z20__device_stub__iwarpPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $320, %rsp # imm = 0x140
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
xorps %xmm0, %xmm0
movaps %xmm0, 176(%rsp)
movaps %xmm0, 160(%rsp)
movaps %xmm0, 144(%rsp)
movaps %xmm0, 128(%rsp)
movaps %xmm0, 112(%rsp)
movaps %xmm0, 96(%rsp)
movaps %xmm0, 80(%rsp)
movaps %xmm0, 64(%rsp)
movq 8(%rsp), %rdi
leaq 64(%rsp), %rsi
movl $128, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
leaq 192(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 192(%rsp), %rsi
movl 200(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z5iwarpPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 192(%rsp), %rdi
movl $128, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl 192(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $32, %rbx
jne .LBB1_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $320, %rsp # imm = 0x140
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5iwarpPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5iwarpPi,@object # @_Z5iwarpPi
.section .rodata,"a",@progbits
.globl _Z5iwarpPi
.p2align 3, 0x0
_Z5iwarpPi:
.quad _Z20__device_stub__iwarpPi
.size _Z5iwarpPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5iwarpPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__iwarpPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5iwarpPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //#include <cudaDefs.h>
//#include <time.h>
//#include <math.h>
//#include <random>
//
////WARNING!!! Do not change TPB and NO_FORCES for this demo !!!
//constexpr unsigned int TPB = 128; //thred per block
//constexpr unsigned int NO_FORCES = 256;
//constexpr unsigned int NO_RAIN_DROPS = 1 << 20;
//
//constexpr unsigned int MEM_BLOCKS_PER_THREAD_BLOCK = 8;
//constexpr unsigned int THREAD_PER_BLOCK = 50;
//
//cudaError_t error = cudaSuccess;
//cudaDeviceProp deviceProp = cudaDeviceProp();
//
//using namespace std;
//
//float3 *createData(const unsigned int length)
//{
// //TODO: Generate float3 vectors. You can use 'make_float3' method.
// float3 *data = static_cast<float3*>(::operator new(sizeof(float3)*length));
///*
// std::random_device rd;
// std::mt19937 gen(rd());
// std::uniform_int_distribution<float> dis(0.0f, 1.0f);
//*/
// for (unsigned int i = 0; i < length; i++)
// {
///*
//
// data[i].x = dis(gen);
// data[i].y = dis(gen);
// data[i].z = dis(gen);
// */
// data[i] = make_float3(1, 1, 1);
//
// }
//
// return data;
//}
//
//void printData(const float3 *data, const unsigned int length)
//{
// if (data == 0) return;
// const float3 *ptr = data;
// for (unsigned int i = 0; i<length; i++, ptr++)
// {
// printf("%5.2f %5.2f %5.2f ", ptr->x, ptr->y, ptr->z);
// }
//}
//
//////////////////////////////////////////////////////////////////////////////////////////////////////
///// <summary> Sums the forces to get the final one using parallel reduction.
///// WARNING!!! The method was written to meet input requirements of our example, i.e. 128 threads and 256 forces </summary>
///// <param name="dForces"> The forces. </param>
///// <param name="noForces"> The number of forces. </param>
///// <param name="dFinalForce"> [in,out] If non-null, the final force. </param>
//////////////////////////////////////////////////////////////////////////////////////////////////////
//__global__ void reduce(const float3 * __restrict__ dForces, const unsigned int noForces, float3* __restrict__ dFinalForce)
//{
// __shared__ float3 sForces[TPB]; //SEE THE WARNING MESSAGE !!!
// unsigned int tid = threadIdx.x;
// unsigned int next = TPB; //SEE THE WARNING MESSAGE !!!
//
//
//
//
// float3* src = (float3*)&sForces[tid];
// float3* src2 = (float3*)&dForces[tid + next];
//
//
// *src = dForces[tid];
//
//
//
// src->x += src2->x;
// src->y += src2->y;
// src->z += src2->z;
//
// __syncthreads();
//
// next >>= 1; // 64
// if (tid >= next) return;
//
// src2 = src + next;
//
// src->x += src2->x;
// src->y += src2->y;
// src->z += src2->z;
//
// __syncthreads();
//
// next >>= 1; // 32
// if (tid >= next) return;
//
// src2 = src + next;
//
// src->x += src2->x;
// src->y += src2->y;
// src->z += src2->z;
//
//
// volatile float3 *vsrc = &sForces[tid];
// volatile float3 *vsrc2 = vsrc + next;
//
// next >>= 1; // 16
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 8
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 4
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 2
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 1
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// if (tid == 0)
// {
// dFinalForce->x = vsrc->x;
// dFinalForce->y = vsrc->y;
// dFinalForce->z = vsrc->z;
// }
//}
//
//////////////////////////////////////////////////////////////////////////////////////////////////////
///// <summary> Adds the FinalForce to every Rain drops position. </summary>
///// <param name="dFinalForce"> The final force. </param>
///// <param name="noRainDrops"> The number of rain drops. </param>
///// <param name="dRainDrops"> [in,out] If non-null, the rain drops positions. </param>
//////////////////////////////////////////////////////////////////////////////////////////////////////
//__global__ void add(const float3* __restrict__ dFinalForce, const unsigned int noRainDrops, float3* __restrict__ dRainDrops)
//{
//
// unsigned int bid = blockIdx.x * MEM_BLOCKS_PER_THREAD_BLOCK + threadIdx.x;
//#pragma unroll MEM_BLOCKS_PER_THREAD_BLOCK
// for (size_t i = 0; i < MEM_BLOCKS_PER_THREAD_BLOCK; i++)
// {
// auto tid = bid + i;
// if (tid >= noRainDrops)
// return;
// dRainDrops[tid].x += dFinalForce->x;
// dRainDrops[tid].y += dFinalForce->y;
// dRainDrops[tid].z += dFinalForce->z;
// }
//}
//
//
//int main(int argc, char *argv[])
//{
// initializeCUDA(deviceProp);
//
// cudaEvent_t startEvent, stopEvent;
// float elapsedTime;
//
// cudaEventCreate(&startEvent);
// cudaEventCreate(&stopEvent);
// cudaEventRecord(startEvent, 0);
//
// float3 *hForces = createData(NO_FORCES);
// float3 *hDrops = createData(NO_RAIN_DROPS);
//
// float3 *dForces = nullptr;
// float3 *dDrops = nullptr;
// float3 *dFinalForce = nullptr;
//
// error = cudaMalloc((void**)&dForces, NO_FORCES * sizeof(float3));
// error = cudaMemcpy(dForces, hForces, NO_FORCES * sizeof(float3), cudaMemcpyHostToDevice);
//
// error = cudaMalloc((void**)&dDrops, NO_RAIN_DROPS * sizeof(float3));
// error = cudaMemcpy(dDrops, hDrops, NO_RAIN_DROPS * sizeof(float3), cudaMemcpyHostToDevice);
//
// error = cudaMalloc((void**)&dFinalForce, sizeof(float3));
//
// KernelSetting ksReduce;
//
// ksReduce.dimGrid = dim3(1, 1,1);
// ksReduce.dimBlock = dim3(TPB, 1, 1);
//
//
// KernelSetting ksAdd;
// ksAdd.dimGrid = dim3(TPB, 1,1);
// ksAdd.dimBlock = dim3(getNumberOfParts(NO_RAIN_DROPS, TPB * MEM_BLOCKS_PER_THREAD_BLOCK), 1, 1);
//
// for (unsigned int i = 0; i<1000; i++)
// {
// reduce<<<ksReduce.dimGrid, ksReduce.dimBlock>>>(dForces, NO_FORCES, dFinalForce);
// add<<<ksAdd.dimGrid, ksAdd.dimBlock>>>(dFinalForce, NO_RAIN_DROPS, dDrops);
// }
//
// checkDeviceMatrix<float>((float*)dFinalForce, sizeof(float3), 1, 3, "%5.2f ", "Final force");
// checkDeviceMatrix<float>((float*)dDrops, sizeof(float3), NO_RAIN_DROPS, 3, "%5.2f ", "Final Rain Drops");
//
// if (hForces)
// free(hForces);
// if (hDrops)
// free(hDrops);
//
// cudaFree(dForces);
// cudaFree(dDrops);
//
// cudaEventRecord(stopEvent, 0);
// cudaEventSynchronize(stopEvent);
//
// cudaEventElapsedTime(&elapsedTime, startEvent, stopEvent);
// cudaEventDestroy(startEvent);
// cudaEventDestroy(stopEvent);
//
// printf("Time to get device properties: %f ms", elapsedTime);
//} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //#include <cudaDefs.h>
//#include <time.h>
//#include <math.h>
//#include <random>
//
////WARNING!!! Do not change TPB and NO_FORCES for this demo !!!
//constexpr unsigned int TPB = 128; //thred per block
//constexpr unsigned int NO_FORCES = 256;
//constexpr unsigned int NO_RAIN_DROPS = 1 << 20;
//
//constexpr unsigned int MEM_BLOCKS_PER_THREAD_BLOCK = 8;
//constexpr unsigned int THREAD_PER_BLOCK = 50;
//
//cudaError_t error = cudaSuccess;
//cudaDeviceProp deviceProp = cudaDeviceProp();
//
//using namespace std;
//
//float3 *createData(const unsigned int length)
//{
// //TODO: Generate float3 vectors. You can use 'make_float3' method.
// float3 *data = static_cast<float3*>(::operator new(sizeof(float3)*length));
///*
// std::random_device rd;
// std::mt19937 gen(rd());
// std::uniform_int_distribution<float> dis(0.0f, 1.0f);
//*/
// for (unsigned int i = 0; i < length; i++)
// {
///*
//
// data[i].x = dis(gen);
// data[i].y = dis(gen);
// data[i].z = dis(gen);
// */
// data[i] = make_float3(1, 1, 1);
//
// }
//
// return data;
//}
//
//void printData(const float3 *data, const unsigned int length)
//{
// if (data == 0) return;
// const float3 *ptr = data;
// for (unsigned int i = 0; i<length; i++, ptr++)
// {
// printf("%5.2f %5.2f %5.2f ", ptr->x, ptr->y, ptr->z);
// }
//}
//
//////////////////////////////////////////////////////////////////////////////////////////////////////
///// <summary> Sums the forces to get the final one using parallel reduction.
///// WARNING!!! The method was written to meet input requirements of our example, i.e. 128 threads and 256 forces </summary>
///// <param name="dForces"> The forces. </param>
///// <param name="noForces"> The number of forces. </param>
///// <param name="dFinalForce"> [in,out] If non-null, the final force. </param>
//////////////////////////////////////////////////////////////////////////////////////////////////////
//__global__ void reduce(const float3 * __restrict__ dForces, const unsigned int noForces, float3* __restrict__ dFinalForce)
//{
// __shared__ float3 sForces[TPB]; //SEE THE WARNING MESSAGE !!!
// unsigned int tid = threadIdx.x;
// unsigned int next = TPB; //SEE THE WARNING MESSAGE !!!
//
//
//
//
// float3* src = (float3*)&sForces[tid];
// float3* src2 = (float3*)&dForces[tid + next];
//
//
// *src = dForces[tid];
//
//
//
// src->x += src2->x;
// src->y += src2->y;
// src->z += src2->z;
//
// __syncthreads();
//
// next >>= 1; // 64
// if (tid >= next) return;
//
// src2 = src + next;
//
// src->x += src2->x;
// src->y += src2->y;
// src->z += src2->z;
//
// __syncthreads();
//
// next >>= 1; // 32
// if (tid >= next) return;
//
// src2 = src + next;
//
// src->x += src2->x;
// src->y += src2->y;
// src->z += src2->z;
//
//
// volatile float3 *vsrc = &sForces[tid];
// volatile float3 *vsrc2 = vsrc + next;
//
// next >>= 1; // 16
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 8
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 4
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 2
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 1
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// if (tid == 0)
// {
// dFinalForce->x = vsrc->x;
// dFinalForce->y = vsrc->y;
// dFinalForce->z = vsrc->z;
// }
//}
//
//////////////////////////////////////////////////////////////////////////////////////////////////////
///// <summary> Adds the FinalForce to every Rain drops position. </summary>
///// <param name="dFinalForce"> The final force. </param>
///// <param name="noRainDrops"> The number of rain drops. </param>
///// <param name="dRainDrops"> [in,out] If non-null, the rain drops positions. </param>
//////////////////////////////////////////////////////////////////////////////////////////////////////
//__global__ void add(const float3* __restrict__ dFinalForce, const unsigned int noRainDrops, float3* __restrict__ dRainDrops)
//{
//
// unsigned int bid = blockIdx.x * MEM_BLOCKS_PER_THREAD_BLOCK + threadIdx.x;
//#pragma unroll MEM_BLOCKS_PER_THREAD_BLOCK
// for (size_t i = 0; i < MEM_BLOCKS_PER_THREAD_BLOCK; i++)
// {
// auto tid = bid + i;
// if (tid >= noRainDrops)
// return;
// dRainDrops[tid].x += dFinalForce->x;
// dRainDrops[tid].y += dFinalForce->y;
// dRainDrops[tid].z += dFinalForce->z;
// }
//}
//
//
//int main(int argc, char *argv[])
//{
// initializeCUDA(deviceProp);
//
// cudaEvent_t startEvent, stopEvent;
// float elapsedTime;
//
// cudaEventCreate(&startEvent);
// cudaEventCreate(&stopEvent);
// cudaEventRecord(startEvent, 0);
//
// float3 *hForces = createData(NO_FORCES);
// float3 *hDrops = createData(NO_RAIN_DROPS);
//
// float3 *dForces = nullptr;
// float3 *dDrops = nullptr;
// float3 *dFinalForce = nullptr;
//
// error = cudaMalloc((void**)&dForces, NO_FORCES * sizeof(float3));
// error = cudaMemcpy(dForces, hForces, NO_FORCES * sizeof(float3), cudaMemcpyHostToDevice);
//
// error = cudaMalloc((void**)&dDrops, NO_RAIN_DROPS * sizeof(float3));
// error = cudaMemcpy(dDrops, hDrops, NO_RAIN_DROPS * sizeof(float3), cudaMemcpyHostToDevice);
//
// error = cudaMalloc((void**)&dFinalForce, sizeof(float3));
//
// KernelSetting ksReduce;
//
// ksReduce.dimGrid = dim3(1, 1,1);
// ksReduce.dimBlock = dim3(TPB, 1, 1);
//
//
// KernelSetting ksAdd;
// ksAdd.dimGrid = dim3(TPB, 1,1);
// ksAdd.dimBlock = dim3(getNumberOfParts(NO_RAIN_DROPS, TPB * MEM_BLOCKS_PER_THREAD_BLOCK), 1, 1);
//
// for (unsigned int i = 0; i<1000; i++)
// {
// reduce<<<ksReduce.dimGrid, ksReduce.dimBlock>>>(dForces, NO_FORCES, dFinalForce);
// add<<<ksAdd.dimGrid, ksAdd.dimBlock>>>(dFinalForce, NO_RAIN_DROPS, dDrops);
// }
//
// checkDeviceMatrix<float>((float*)dFinalForce, sizeof(float3), 1, 3, "%5.2f ", "Final force");
// checkDeviceMatrix<float>((float*)dDrops, sizeof(float3), NO_RAIN_DROPS, 3, "%5.2f ", "Final Rain Drops");
//
// if (hForces)
// free(hForces);
// if (hDrops)
// free(hDrops);
//
// cudaFree(dForces);
// cudaFree(dDrops);
//
// cudaEventRecord(stopEvent, 0);
// cudaEventSynchronize(stopEvent);
//
// cudaEventElapsedTime(&elapsedTime, startEvent, stopEvent);
// cudaEventDestroy(startEvent);
// cudaEventDestroy(stopEvent);
//
// printf("Time to get device properties: %f ms", elapsedTime);
//} | .file "tmpxft_0014a27a_00000000-6_Runner_3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //#include <cudaDefs.h>
//#include <time.h>
//#include <math.h>
//#include <random>
//
////WARNING!!! Do not change TPB and NO_FORCES for this demo !!!
//constexpr unsigned int TPB = 128; //thred per block
//constexpr unsigned int NO_FORCES = 256;
//constexpr unsigned int NO_RAIN_DROPS = 1 << 20;
//
//constexpr unsigned int MEM_BLOCKS_PER_THREAD_BLOCK = 8;
//constexpr unsigned int THREAD_PER_BLOCK = 50;
//
//cudaError_t error = cudaSuccess;
//cudaDeviceProp deviceProp = cudaDeviceProp();
//
//using namespace std;
//
//float3 *createData(const unsigned int length)
//{
// //TODO: Generate float3 vectors. You can use 'make_float3' method.
// float3 *data = static_cast<float3*>(::operator new(sizeof(float3)*length));
///*
// std::random_device rd;
// std::mt19937 gen(rd());
// std::uniform_int_distribution<float> dis(0.0f, 1.0f);
//*/
// for (unsigned int i = 0; i < length; i++)
// {
///*
//
// data[i].x = dis(gen);
// data[i].y = dis(gen);
// data[i].z = dis(gen);
// */
// data[i] = make_float3(1, 1, 1);
//
// }
//
// return data;
//}
//
//void printData(const float3 *data, const unsigned int length)
//{
// if (data == 0) return;
// const float3 *ptr = data;
// for (unsigned int i = 0; i<length; i++, ptr++)
// {
// printf("%5.2f %5.2f %5.2f ", ptr->x, ptr->y, ptr->z);
// }
//}
//
//////////////////////////////////////////////////////////////////////////////////////////////////////
///// <summary> Sums the forces to get the final one using parallel reduction.
///// WARNING!!! The method was written to meet input requirements of our example, i.e. 128 threads and 256 forces </summary>
///// <param name="dForces"> The forces. </param>
///// <param name="noForces"> The number of forces. </param>
///// <param name="dFinalForce"> [in,out] If non-null, the final force. </param>
//////////////////////////////////////////////////////////////////////////////////////////////////////
//__global__ void reduce(const float3 * __restrict__ dForces, const unsigned int noForces, float3* __restrict__ dFinalForce)
//{
// __shared__ float3 sForces[TPB]; //SEE THE WARNING MESSAGE !!!
// unsigned int tid = threadIdx.x;
// unsigned int next = TPB; //SEE THE WARNING MESSAGE !!!
//
//
//
//
// float3* src = (float3*)&sForces[tid];
// float3* src2 = (float3*)&dForces[tid + next];
//
//
// *src = dForces[tid];
//
//
//
// src->x += src2->x;
// src->y += src2->y;
// src->z += src2->z;
//
// __syncthreads();
//
// next >>= 1; // 64
// if (tid >= next) return;
//
// src2 = src + next;
//
// src->x += src2->x;
// src->y += src2->y;
// src->z += src2->z;
//
// __syncthreads();
//
// next >>= 1; // 32
// if (tid >= next) return;
//
// src2 = src + next;
//
// src->x += src2->x;
// src->y += src2->y;
// src->z += src2->z;
//
//
// volatile float3 *vsrc = &sForces[tid];
// volatile float3 *vsrc2 = vsrc + next;
//
// next >>= 1; // 16
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 8
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 4
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 2
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 1
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// if (tid == 0)
// {
// dFinalForce->x = vsrc->x;
// dFinalForce->y = vsrc->y;
// dFinalForce->z = vsrc->z;
// }
//}
//
//////////////////////////////////////////////////////////////////////////////////////////////////////
///// <summary> Adds the FinalForce to every Rain drops position. </summary>
///// <param name="dFinalForce"> The final force. </param>
///// <param name="noRainDrops"> The number of rain drops. </param>
///// <param name="dRainDrops"> [in,out] If non-null, the rain drops positions. </param>
//////////////////////////////////////////////////////////////////////////////////////////////////////
//__global__ void add(const float3* __restrict__ dFinalForce, const unsigned int noRainDrops, float3* __restrict__ dRainDrops)
//{
//
// unsigned int bid = blockIdx.x * MEM_BLOCKS_PER_THREAD_BLOCK + threadIdx.x;
//#pragma unroll MEM_BLOCKS_PER_THREAD_BLOCK
// for (size_t i = 0; i < MEM_BLOCKS_PER_THREAD_BLOCK; i++)
// {
// auto tid = bid + i;
// if (tid >= noRainDrops)
// return;
// dRainDrops[tid].x += dFinalForce->x;
// dRainDrops[tid].y += dFinalForce->y;
// dRainDrops[tid].z += dFinalForce->z;
// }
//}
//
//
//int main(int argc, char *argv[])
//{
// initializeCUDA(deviceProp);
//
// cudaEvent_t startEvent, stopEvent;
// float elapsedTime;
//
// cudaEventCreate(&startEvent);
// cudaEventCreate(&stopEvent);
// cudaEventRecord(startEvent, 0);
//
// float3 *hForces = createData(NO_FORCES);
// float3 *hDrops = createData(NO_RAIN_DROPS);
//
// float3 *dForces = nullptr;
// float3 *dDrops = nullptr;
// float3 *dFinalForce = nullptr;
//
// error = cudaMalloc((void**)&dForces, NO_FORCES * sizeof(float3));
// error = cudaMemcpy(dForces, hForces, NO_FORCES * sizeof(float3), cudaMemcpyHostToDevice);
//
// error = cudaMalloc((void**)&dDrops, NO_RAIN_DROPS * sizeof(float3));
// error = cudaMemcpy(dDrops, hDrops, NO_RAIN_DROPS * sizeof(float3), cudaMemcpyHostToDevice);
//
// error = cudaMalloc((void**)&dFinalForce, sizeof(float3));
//
// KernelSetting ksReduce;
//
// ksReduce.dimGrid = dim3(1, 1,1);
// ksReduce.dimBlock = dim3(TPB, 1, 1);
//
//
// KernelSetting ksAdd;
// ksAdd.dimGrid = dim3(TPB, 1,1);
// ksAdd.dimBlock = dim3(getNumberOfParts(NO_RAIN_DROPS, TPB * MEM_BLOCKS_PER_THREAD_BLOCK), 1, 1);
//
// for (unsigned int i = 0; i<1000; i++)
// {
// reduce<<<ksReduce.dimGrid, ksReduce.dimBlock>>>(dForces, NO_FORCES, dFinalForce);
// add<<<ksAdd.dimGrid, ksAdd.dimBlock>>>(dFinalForce, NO_RAIN_DROPS, dDrops);
// }
//
// checkDeviceMatrix<float>((float*)dFinalForce, sizeof(float3), 1, 3, "%5.2f ", "Final force");
// checkDeviceMatrix<float>((float*)dDrops, sizeof(float3), NO_RAIN_DROPS, 3, "%5.2f ", "Final Rain Drops");
//
// if (hForces)
// free(hForces);
// if (hDrops)
// free(hDrops);
//
// cudaFree(dForces);
// cudaFree(dDrops);
//
// cudaEventRecord(stopEvent, 0);
// cudaEventSynchronize(stopEvent);
//
// cudaEventElapsedTime(&elapsedTime, startEvent, stopEvent);
// cudaEventDestroy(startEvent);
// cudaEventDestroy(stopEvent);
//
// printf("Time to get device properties: %f ms", elapsedTime);
//} | #include <hip/hip_runtime.h>
//#include <cudaDefs.h>
//#include <time.h>
//#include <math.h>
//#include <random>
//
////WARNING!!! Do not change TPB and NO_FORCES for this demo !!!
//constexpr unsigned int TPB = 128; //thred per block
//constexpr unsigned int NO_FORCES = 256;
//constexpr unsigned int NO_RAIN_DROPS = 1 << 20;
//
//constexpr unsigned int MEM_BLOCKS_PER_THREAD_BLOCK = 8;
//constexpr unsigned int THREAD_PER_BLOCK = 50;
//
//cudaError_t error = cudaSuccess;
//cudaDeviceProp deviceProp = cudaDeviceProp();
//
//using namespace std;
//
//float3 *createData(const unsigned int length)
//{
// //TODO: Generate float3 vectors. You can use 'make_float3' method.
// float3 *data = static_cast<float3*>(::operator new(sizeof(float3)*length));
///*
// std::random_device rd;
// std::mt19937 gen(rd());
// std::uniform_int_distribution<float> dis(0.0f, 1.0f);
//*/
// for (unsigned int i = 0; i < length; i++)
// {
///*
//
// data[i].x = dis(gen);
// data[i].y = dis(gen);
// data[i].z = dis(gen);
// */
// data[i] = make_float3(1, 1, 1);
//
// }
//
// return data;
//}
//
//void printData(const float3 *data, const unsigned int length)
//{
// if (data == 0) return;
// const float3 *ptr = data;
// for (unsigned int i = 0; i<length; i++, ptr++)
// {
// printf("%5.2f %5.2f %5.2f ", ptr->x, ptr->y, ptr->z);
// }
//}
//
//////////////////////////////////////////////////////////////////////////////////////////////////////
///// <summary> Sums the forces to get the final one using parallel reduction.
///// WARNING!!! The method was written to meet input requirements of our example, i.e. 128 threads and 256 forces </summary>
///// <param name="dForces"> The forces. </param>
///// <param name="noForces"> The number of forces. </param>
///// <param name="dFinalForce"> [in,out] If non-null, the final force. </param>
//////////////////////////////////////////////////////////////////////////////////////////////////////
//__global__ void reduce(const float3 * __restrict__ dForces, const unsigned int noForces, float3* __restrict__ dFinalForce)
//{
// __shared__ float3 sForces[TPB]; //SEE THE WARNING MESSAGE !!!
// unsigned int tid = threadIdx.x;
// unsigned int next = TPB; //SEE THE WARNING MESSAGE !!!
//
//
//
//
// float3* src = (float3*)&sForces[tid];
// float3* src2 = (float3*)&dForces[tid + next];
//
//
// *src = dForces[tid];
//
//
//
// src->x += src2->x;
// src->y += src2->y;
// src->z += src2->z;
//
// __syncthreads();
//
// next >>= 1; // 64
// if (tid >= next) return;
//
// src2 = src + next;
//
// src->x += src2->x;
// src->y += src2->y;
// src->z += src2->z;
//
// __syncthreads();
//
// next >>= 1; // 32
// if (tid >= next) return;
//
// src2 = src + next;
//
// src->x += src2->x;
// src->y += src2->y;
// src->z += src2->z;
//
//
// volatile float3 *vsrc = &sForces[tid];
// volatile float3 *vsrc2 = vsrc + next;
//
// next >>= 1; // 16
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 8
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 4
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 2
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 1
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// if (tid == 0)
// {
// dFinalForce->x = vsrc->x;
// dFinalForce->y = vsrc->y;
// dFinalForce->z = vsrc->z;
// }
//}
//
//////////////////////////////////////////////////////////////////////////////////////////////////////
///// <summary> Adds the FinalForce to every Rain drops position. </summary>
///// <param name="dFinalForce"> The final force. </param>
///// <param name="noRainDrops"> The number of rain drops. </param>
///// <param name="dRainDrops"> [in,out] If non-null, the rain drops positions. </param>
//////////////////////////////////////////////////////////////////////////////////////////////////////
//__global__ void add(const float3* __restrict__ dFinalForce, const unsigned int noRainDrops, float3* __restrict__ dRainDrops)
//{
//
// unsigned int bid = blockIdx.x * MEM_BLOCKS_PER_THREAD_BLOCK + threadIdx.x;
//#pragma unroll MEM_BLOCKS_PER_THREAD_BLOCK
// for (size_t i = 0; i < MEM_BLOCKS_PER_THREAD_BLOCK; i++)
// {
// auto tid = bid + i;
// if (tid >= noRainDrops)
// return;
// dRainDrops[tid].x += dFinalForce->x;
// dRainDrops[tid].y += dFinalForce->y;
// dRainDrops[tid].z += dFinalForce->z;
// }
//}
//
//
//int main(int argc, char *argv[])
//{
// initializeCUDA(deviceProp);
//
// cudaEvent_t startEvent, stopEvent;
// float elapsedTime;
//
// cudaEventCreate(&startEvent);
// cudaEventCreate(&stopEvent);
// cudaEventRecord(startEvent, 0);
//
// float3 *hForces = createData(NO_FORCES);
// float3 *hDrops = createData(NO_RAIN_DROPS);
//
// float3 *dForces = nullptr;
// float3 *dDrops = nullptr;
// float3 *dFinalForce = nullptr;
//
// error = cudaMalloc((void**)&dForces, NO_FORCES * sizeof(float3));
// error = cudaMemcpy(dForces, hForces, NO_FORCES * sizeof(float3), cudaMemcpyHostToDevice);
//
// error = cudaMalloc((void**)&dDrops, NO_RAIN_DROPS * sizeof(float3));
// error = cudaMemcpy(dDrops, hDrops, NO_RAIN_DROPS * sizeof(float3), cudaMemcpyHostToDevice);
//
// error = cudaMalloc((void**)&dFinalForce, sizeof(float3));
//
// KernelSetting ksReduce;
//
// ksReduce.dimGrid = dim3(1, 1,1);
// ksReduce.dimBlock = dim3(TPB, 1, 1);
//
//
// KernelSetting ksAdd;
// ksAdd.dimGrid = dim3(TPB, 1,1);
// ksAdd.dimBlock = dim3(getNumberOfParts(NO_RAIN_DROPS, TPB * MEM_BLOCKS_PER_THREAD_BLOCK), 1, 1);
//
// for (unsigned int i = 0; i<1000; i++)
// {
// reduce<<<ksReduce.dimGrid, ksReduce.dimBlock>>>(dForces, NO_FORCES, dFinalForce);
// add<<<ksAdd.dimGrid, ksAdd.dimBlock>>>(dFinalForce, NO_RAIN_DROPS, dDrops);
// }
//
// checkDeviceMatrix<float>((float*)dFinalForce, sizeof(float3), 1, 3, "%5.2f ", "Final force");
// checkDeviceMatrix<float>((float*)dDrops, sizeof(float3), NO_RAIN_DROPS, 3, "%5.2f ", "Final Rain Drops");
//
// if (hForces)
// free(hForces);
// if (hDrops)
// free(hDrops);
//
// cudaFree(dForces);
// cudaFree(dDrops);
//
// cudaEventRecord(stopEvent, 0);
// cudaEventSynchronize(stopEvent);
//
// cudaEventElapsedTime(&elapsedTime, startEvent, stopEvent);
// cudaEventDestroy(startEvent);
// cudaEventDestroy(stopEvent);
//
// printf("Time to get device properties: %f ms", elapsedTime);
//} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//#include <cudaDefs.h>
//#include <time.h>
//#include <math.h>
//#include <random>
//
////WARNING!!! Do not change TPB and NO_FORCES for this demo !!!
//constexpr unsigned int TPB = 128; //thred per block
//constexpr unsigned int NO_FORCES = 256;
//constexpr unsigned int NO_RAIN_DROPS = 1 << 20;
//
//constexpr unsigned int MEM_BLOCKS_PER_THREAD_BLOCK = 8;
//constexpr unsigned int THREAD_PER_BLOCK = 50;
//
//cudaError_t error = cudaSuccess;
//cudaDeviceProp deviceProp = cudaDeviceProp();
//
//using namespace std;
//
//float3 *createData(const unsigned int length)
//{
// //TODO: Generate float3 vectors. You can use 'make_float3' method.
// float3 *data = static_cast<float3*>(::operator new(sizeof(float3)*length));
///*
// std::random_device rd;
// std::mt19937 gen(rd());
// std::uniform_int_distribution<float> dis(0.0f, 1.0f);
//*/
// for (unsigned int i = 0; i < length; i++)
// {
///*
//
// data[i].x = dis(gen);
// data[i].y = dis(gen);
// data[i].z = dis(gen);
// */
// data[i] = make_float3(1, 1, 1);
//
// }
//
// return data;
//}
//
//void printData(const float3 *data, const unsigned int length)
//{
// if (data == 0) return;
// const float3 *ptr = data;
// for (unsigned int i = 0; i<length; i++, ptr++)
// {
// printf("%5.2f %5.2f %5.2f ", ptr->x, ptr->y, ptr->z);
// }
//}
//
//////////////////////////////////////////////////////////////////////////////////////////////////////
///// <summary> Sums the forces to get the final one using parallel reduction.
///// WARNING!!! The method was written to meet input requirements of our example, i.e. 128 threads and 256 forces </summary>
///// <param name="dForces"> The forces. </param>
///// <param name="noForces"> The number of forces. </param>
///// <param name="dFinalForce"> [in,out] If non-null, the final force. </param>
//////////////////////////////////////////////////////////////////////////////////////////////////////
//__global__ void reduce(const float3 * __restrict__ dForces, const unsigned int noForces, float3* __restrict__ dFinalForce)
//{
// __shared__ float3 sForces[TPB]; //SEE THE WARNING MESSAGE !!!
// unsigned int tid = threadIdx.x;
// unsigned int next = TPB; //SEE THE WARNING MESSAGE !!!
//
//
//
//
// float3* src = (float3*)&sForces[tid];
// float3* src2 = (float3*)&dForces[tid + next];
//
//
// *src = dForces[tid];
//
//
//
// src->x += src2->x;
// src->y += src2->y;
// src->z += src2->z;
//
// __syncthreads();
//
// next >>= 1; // 64
// if (tid >= next) return;
//
// src2 = src + next;
//
// src->x += src2->x;
// src->y += src2->y;
// src->z += src2->z;
//
// __syncthreads();
//
// next >>= 1; // 32
// if (tid >= next) return;
//
// src2 = src + next;
//
// src->x += src2->x;
// src->y += src2->y;
// src->z += src2->z;
//
//
// volatile float3 *vsrc = &sForces[tid];
// volatile float3 *vsrc2 = vsrc + next;
//
// next >>= 1; // 16
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 8
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 4
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 2
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 1
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// if (tid == 0)
// {
// dFinalForce->x = vsrc->x;
// dFinalForce->y = vsrc->y;
// dFinalForce->z = vsrc->z;
// }
//}
//
//////////////////////////////////////////////////////////////////////////////////////////////////////
///// <summary> Adds the FinalForce to every Rain drops position. </summary>
///// <param name="dFinalForce"> The final force. </param>
///// <param name="noRainDrops"> The number of rain drops. </param>
///// <param name="dRainDrops"> [in,out] If non-null, the rain drops positions. </param>
//////////////////////////////////////////////////////////////////////////////////////////////////////
//__global__ void add(const float3* __restrict__ dFinalForce, const unsigned int noRainDrops, float3* __restrict__ dRainDrops)
//{
//
// unsigned int bid = blockIdx.x * MEM_BLOCKS_PER_THREAD_BLOCK + threadIdx.x;
//#pragma unroll MEM_BLOCKS_PER_THREAD_BLOCK
// for (size_t i = 0; i < MEM_BLOCKS_PER_THREAD_BLOCK; i++)
// {
// auto tid = bid + i;
// if (tid >= noRainDrops)
// return;
// dRainDrops[tid].x += dFinalForce->x;
// dRainDrops[tid].y += dFinalForce->y;
// dRainDrops[tid].z += dFinalForce->z;
// }
//}
//
//
//int main(int argc, char *argv[])
//{
// initializeCUDA(deviceProp);
//
// cudaEvent_t startEvent, stopEvent;
// float elapsedTime;
//
// cudaEventCreate(&startEvent);
// cudaEventCreate(&stopEvent);
// cudaEventRecord(startEvent, 0);
//
// float3 *hForces = createData(NO_FORCES);
// float3 *hDrops = createData(NO_RAIN_DROPS);
//
// float3 *dForces = nullptr;
// float3 *dDrops = nullptr;
// float3 *dFinalForce = nullptr;
//
// error = cudaMalloc((void**)&dForces, NO_FORCES * sizeof(float3));
// error = cudaMemcpy(dForces, hForces, NO_FORCES * sizeof(float3), cudaMemcpyHostToDevice);
//
// error = cudaMalloc((void**)&dDrops, NO_RAIN_DROPS * sizeof(float3));
// error = cudaMemcpy(dDrops, hDrops, NO_RAIN_DROPS * sizeof(float3), cudaMemcpyHostToDevice);
//
// error = cudaMalloc((void**)&dFinalForce, sizeof(float3));
//
// KernelSetting ksReduce;
//
// ksReduce.dimGrid = dim3(1, 1,1);
// ksReduce.dimBlock = dim3(TPB, 1, 1);
//
//
// KernelSetting ksAdd;
// ksAdd.dimGrid = dim3(TPB, 1,1);
// ksAdd.dimBlock = dim3(getNumberOfParts(NO_RAIN_DROPS, TPB * MEM_BLOCKS_PER_THREAD_BLOCK), 1, 1);
//
// for (unsigned int i = 0; i<1000; i++)
// {
// reduce<<<ksReduce.dimGrid, ksReduce.dimBlock>>>(dForces, NO_FORCES, dFinalForce);
// add<<<ksAdd.dimGrid, ksAdd.dimBlock>>>(dFinalForce, NO_RAIN_DROPS, dDrops);
// }
//
// checkDeviceMatrix<float>((float*)dFinalForce, sizeof(float3), 1, 3, "%5.2f ", "Final force");
// checkDeviceMatrix<float>((float*)dDrops, sizeof(float3), NO_RAIN_DROPS, 3, "%5.2f ", "Final Rain Drops");
//
// if (hForces)
// free(hForces);
// if (hDrops)
// free(hDrops);
//
// cudaFree(dForces);
// cudaFree(dDrops);
//
// cudaEventRecord(stopEvent, 0);
// cudaEventSynchronize(stopEvent);
//
// cudaEventElapsedTime(&elapsedTime, startEvent, stopEvent);
// cudaEventDestroy(startEvent);
// cudaEventDestroy(stopEvent);
//
// printf("Time to get device properties: %f ms", elapsedTime);
//} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//#include <cudaDefs.h>
//#include <time.h>
//#include <math.h>
//#include <random>
//
////WARNING!!! Do not change TPB and NO_FORCES for this demo !!!
//constexpr unsigned int TPB = 128; //thred per block
//constexpr unsigned int NO_FORCES = 256;
//constexpr unsigned int NO_RAIN_DROPS = 1 << 20;
//
//constexpr unsigned int MEM_BLOCKS_PER_THREAD_BLOCK = 8;
//constexpr unsigned int THREAD_PER_BLOCK = 50;
//
//cudaError_t error = cudaSuccess;
//cudaDeviceProp deviceProp = cudaDeviceProp();
//
//using namespace std;
//
//float3 *createData(const unsigned int length)
//{
// //TODO: Generate float3 vectors. You can use 'make_float3' method.
// float3 *data = static_cast<float3*>(::operator new(sizeof(float3)*length));
///*
// std::random_device rd;
// std::mt19937 gen(rd());
// std::uniform_int_distribution<float> dis(0.0f, 1.0f);
//*/
// for (unsigned int i = 0; i < length; i++)
// {
///*
//
// data[i].x = dis(gen);
// data[i].y = dis(gen);
// data[i].z = dis(gen);
// */
// data[i] = make_float3(1, 1, 1);
//
// }
//
// return data;
//}
//
//void printData(const float3 *data, const unsigned int length)
//{
// if (data == 0) return;
// const float3 *ptr = data;
// for (unsigned int i = 0; i<length; i++, ptr++)
// {
// printf("%5.2f %5.2f %5.2f ", ptr->x, ptr->y, ptr->z);
// }
//}
//
//////////////////////////////////////////////////////////////////////////////////////////////////////
///// <summary> Sums the forces to get the final one using parallel reduction.
///// WARNING!!! The method was written to meet input requirements of our example, i.e. 128 threads and 256 forces </summary>
///// <param name="dForces"> The forces. </param>
///// <param name="noForces"> The number of forces. </param>
///// <param name="dFinalForce"> [in,out] If non-null, the final force. </param>
//////////////////////////////////////////////////////////////////////////////////////////////////////
//__global__ void reduce(const float3 * __restrict__ dForces, const unsigned int noForces, float3* __restrict__ dFinalForce)
//{
// __shared__ float3 sForces[TPB]; //SEE THE WARNING MESSAGE !!!
// unsigned int tid = threadIdx.x;
// unsigned int next = TPB; //SEE THE WARNING MESSAGE !!!
//
//
//
//
// float3* src = (float3*)&sForces[tid];
// float3* src2 = (float3*)&dForces[tid + next];
//
//
// *src = dForces[tid];
//
//
//
// src->x += src2->x;
// src->y += src2->y;
// src->z += src2->z;
//
// __syncthreads();
//
// next >>= 1; // 64
// if (tid >= next) return;
//
// src2 = src + next;
//
// src->x += src2->x;
// src->y += src2->y;
// src->z += src2->z;
//
// __syncthreads();
//
// next >>= 1; // 32
// if (tid >= next) return;
//
// src2 = src + next;
//
// src->x += src2->x;
// src->y += src2->y;
// src->z += src2->z;
//
//
// volatile float3 *vsrc = &sForces[tid];
// volatile float3 *vsrc2 = vsrc + next;
//
// next >>= 1; // 16
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 8
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 4
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 2
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// next >>= 1; // 1
// if (tid >= next) return;
//
// vsrc2 = vsrc + next;
//
// vsrc->x += vsrc2->x;
// vsrc->y += vsrc2->y;
// vsrc->z += vsrc2->z;
//
// if (tid == 0)
// {
// dFinalForce->x = vsrc->x;
// dFinalForce->y = vsrc->y;
// dFinalForce->z = vsrc->z;
// }
//}
//
//////////////////////////////////////////////////////////////////////////////////////////////////////
///// <summary> Adds the FinalForce to every Rain drops position. </summary>
///// <param name="dFinalForce"> The final force. </param>
///// <param name="noRainDrops"> The number of rain drops. </param>
///// <param name="dRainDrops"> [in,out] If non-null, the rain drops positions. </param>
//////////////////////////////////////////////////////////////////////////////////////////////////////
//__global__ void add(const float3* __restrict__ dFinalForce, const unsigned int noRainDrops, float3* __restrict__ dRainDrops)
//{
//
// unsigned int bid = blockIdx.x * MEM_BLOCKS_PER_THREAD_BLOCK + threadIdx.x;
//#pragma unroll MEM_BLOCKS_PER_THREAD_BLOCK
// for (size_t i = 0; i < MEM_BLOCKS_PER_THREAD_BLOCK; i++)
// {
// auto tid = bid + i;
// if (tid >= noRainDrops)
// return;
// dRainDrops[tid].x += dFinalForce->x;
// dRainDrops[tid].y += dFinalForce->y;
// dRainDrops[tid].z += dFinalForce->z;
// }
//}
//
//
//int main(int argc, char *argv[])
//{
// initializeCUDA(deviceProp);
//
// cudaEvent_t startEvent, stopEvent;
// float elapsedTime;
//
// cudaEventCreate(&startEvent);
// cudaEventCreate(&stopEvent);
// cudaEventRecord(startEvent, 0);
//
// float3 *hForces = createData(NO_FORCES);
// float3 *hDrops = createData(NO_RAIN_DROPS);
//
// float3 *dForces = nullptr;
// float3 *dDrops = nullptr;
// float3 *dFinalForce = nullptr;
//
// error = cudaMalloc((void**)&dForces, NO_FORCES * sizeof(float3));
// error = cudaMemcpy(dForces, hForces, NO_FORCES * sizeof(float3), cudaMemcpyHostToDevice);
//
// error = cudaMalloc((void**)&dDrops, NO_RAIN_DROPS * sizeof(float3));
// error = cudaMemcpy(dDrops, hDrops, NO_RAIN_DROPS * sizeof(float3), cudaMemcpyHostToDevice);
//
// error = cudaMalloc((void**)&dFinalForce, sizeof(float3));
//
// KernelSetting ksReduce;
//
// ksReduce.dimGrid = dim3(1, 1,1);
// ksReduce.dimBlock = dim3(TPB, 1, 1);
//
//
// KernelSetting ksAdd;
// ksAdd.dimGrid = dim3(TPB, 1,1);
// ksAdd.dimBlock = dim3(getNumberOfParts(NO_RAIN_DROPS, TPB * MEM_BLOCKS_PER_THREAD_BLOCK), 1, 1);
//
// for (unsigned int i = 0; i<1000; i++)
// {
// reduce<<<ksReduce.dimGrid, ksReduce.dimBlock>>>(dForces, NO_FORCES, dFinalForce);
// add<<<ksAdd.dimGrid, ksAdd.dimBlock>>>(dFinalForce, NO_RAIN_DROPS, dDrops);
// }
//
// checkDeviceMatrix<float>((float*)dFinalForce, sizeof(float3), 1, 3, "%5.2f ", "Final force");
// checkDeviceMatrix<float>((float*)dDrops, sizeof(float3), NO_RAIN_DROPS, 3, "%5.2f ", "Final Rain Drops");
//
// if (hForces)
// free(hForces);
// if (hDrops)
// free(hDrops);
//
// cudaFree(dForces);
// cudaFree(dDrops);
//
// cudaEventRecord(stopEvent, 0);
// cudaEventSynchronize(stopEvent);
//
// cudaEventElapsedTime(&elapsedTime, startEvent, stopEvent);
// cudaEventDestroy(startEvent);
// cudaEventDestroy(stopEvent);
//
// printf("Time to get device properties: %f ms", elapsedTime);
//} | .text
.file "Runner_3.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014a27a_00000000-6_Runner_3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Runner_3.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cstdlib>
#include <cstdio>
#include <time.h>
#include <sys/time.h>
#include <cuda.h>
#include<cuda_runtime.h>
#include<device_launch_parameters.h>
#define BLOCKSIZE_x 32
#define BLOCKSIZE_y 32
#define l 100
#define dt 0.01
#define D 10.0
#define d 0.4
//using namespace std;
double my_gettimeofday(){
struct timeval tmp_time;
gettimeofday(&tmp_time, NULL);
return tmp_time.tv_sec + (tmp_time.tv_usec * 1.0e-6L);
}
/*****************/
/* CUDA MEMCHECK */
/*****************/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, char *file, int line, bool abort = true)
{
if (code != cudaSuccess)
{
fprintf(stderr, "GPUassert: %s %s %dn", cudaGetErrorString(code), file, line);
if (abort) { exit(code); }
}
}
int iDivUp(int hostPtr, int b){ return ((hostPtr % b) != 0) ? (hostPtr / b + 1) : (hostPtr / b); }
__global__ void solve(double A[l][l])
{
int i = threadIdx.x+blockIdx.x * blockDim.x;
int j = threadIdx.y+blockIdx.y * blockDim.y;
if( i < l-1 && j < l-1 && (i!=0) && (j!=0) )
{
A[i][j] = A[i][j]*(1-d*dt)/l+(A[i-1][j] + A[i+1][j] + A[i][j+1] + A[i][j-1] - 4*A[i][j])*D*dt/l;
}
}
int main(){
float phi0=0.4;
double cpu_mesh[l][l];
double cpu_res[l][l];
double (*gpu_mesh)[l]; //pointers to arrays of dimension N
double (*gpu_res)[l];
/* Initializing cpu_mesh with source at the center*/
for(int i=0 ; i< l; i++){
for(int j=0 ; j<l ; ++j){
cpu_mesh[i][j]=0.0;
}
}
cpu_mesh[l/2-1][l/2 -1]=phi0;
cpu_mesh[l/2][l/2 -1]=phi0;
cpu_mesh[l/2][l/2]=phi0;
cpu_mesh[l/2-1][l/2]=phi0;
/* Allocation */
cudaMalloc((void**)&gpu_mesh, (l*l)*sizeof(double));
cudaMalloc((void**)&gpu_res, (l*l)*sizeof(double));
//copying from host to device
double debut = my_gettimeofday();
double debutTransfert = my_gettimeofday();
gpuErrchk(cudaMemcpy(gpu_mesh, cpu_mesh, (l*l)*sizeof(double), cudaMemcpyHostToDevice));
double finTransfert = my_gettimeofday();
std::cout << "Transfert CPU vers GPU :" << finTransfert-debutTransfert << std::endl;
dim3 gridSize(iDivUp(l, BLOCKSIZE_x), iDivUp(l, BLOCKSIZE_y));
dim3 blockSize(BLOCKSIZE_y, BLOCKSIZE_x);
//solve <<<gridSize, blockSize>>> (gpu_mesh, gpu_res, D, dt, d);
for(int i=0; i<1000; ++i){
solve<<<gridSize, blockSize>>> (gpu_mesh);
}
debutTransfert = my_gettimeofday();
cudaMemcpy(cpu_res, gpu_mesh, (l*l)*sizeof(double), cudaMemcpyDeviceToHost);
std::cout << "Transfert GPU vers CPU :" << finTransfert-debutTransfert << std::endl;
finTransfert = my_gettimeofday();
double fin= my_gettimeofday();
std::cout << "Temps calcul :" << fin-debut << std::endl;
/*for (int i = 0; i < l; i++){
for (int j = 0; j < l; j++){
std::cout << cpu_res[i][j] << " ";
}
std::cout << std::endl;
}*/
return 0;
} | code for sm_80
Function : _Z5solvePA100_d
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R0 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GT.AND P0, PT, R5, 0x62, PT ; /* 0x000000620500780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GT.OR P0, PT, R2, 0x62, P0 ; /* 0x000000620200780c */
/* 0x000fc80000704670 */
/*0090*/ ISETP.EQ.OR P0, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */
/* 0x000fc80000702670 */
/*00a0*/ ISETP.EQ.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000702670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x320 ; /* 0x00000320ff037424 */
/* 0x000fe200078e00ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00e0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*00f0*/ IMAD.WIDE R2, R5, 0x8, R2 ; /* 0x0000000805027825 */
/* 0x000fca00078e0202 */
/*0100*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1b00 */
/*0110*/ MUFU.RCP64H R7, 100 ; /* 0x4059000000077908 */
/* 0x000e220000001800 */
/*0120*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe200078e00ff */
/*0130*/ BSSY B0, 0x2c0 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*0140*/ IMAD.MOV.U32 R11, RZ, RZ, 0x40590000 ; /* 0x40590000ff0b7424 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fcc00078e00ff */
/*0160*/ DFMA R8, R6, -R10, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c000000080a */
/*0170*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0180*/ DFMA R6, R6, R8, R6 ; /* 0x000000080606722b */
/* 0x001e0c0000000006 */
/*0190*/ DFMA R10, R6, -R10, 1 ; /* 0x3ff00000060a742b */
/* 0x001e0c000000080a */
/*01a0*/ DFMA R6, R6, R10, R6 ; /* 0x0000000a0606722b */
/* 0x001fc80000000006 */
/*01b0*/ DMUL R8, R4, c[0x2][0x0] ; /* 0x0080000004087a28 */
/* 0x004e0c0000000000 */
/*01c0*/ DMUL R10, R8, R6 ; /* 0x00000006080a7228 */
/* 0x001e080000000000 */
/*01d0*/ FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT ; /* 0x036000000900780b */
/* 0x000fe40003f2e200 */
/*01e0*/ DFMA R12, R10, -100, R8 ; /* 0xc05900000a0c782b */
/* 0x001e0c0000000008 */
/*01f0*/ DFMA R6, R6, R12, R10 ; /* 0x0000000c0606722b */
/* 0x001e14000000000a */
/*0200*/ FFMA R0, RZ, 3.390625, R7 ; /* 0x40590000ff007823 */
/* 0x001fca0000000007 */
/*0210*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0220*/ @P0 BRA P1, 0x2b0 ; /* 0x0000008000000947 */
/* 0x000fea0000800000 */
/*0230*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*0240*/ MOV R0, 0x290 ; /* 0x0000029000007802 */
/* 0x000fe20000000f00 */
/*0250*/ IMAD.MOV.U32 R13, RZ, RZ, R9 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0009 */
/*0260*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*0270*/ IMAD.MOV.U32 R11, RZ, RZ, 0x40590000 ; /* 0x40590000ff0b7424 */
/* 0x000fe400078e00ff */
/*0280*/ CALL.REL.NOINC 0x530 ; /* 0x000002a000007944 */
/* 0x000fea0003c00000 */
/*0290*/ IMAD.MOV.U32 R6, RZ, RZ, R16 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0010 */
/*02a0*/ IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0011 */
/*02b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02c0*/ LDG.E.64 R10, [R2.64+0x320] ; /* 0x00032004020a7981 */
/* 0x000ea8000c1e1b00 */
/*02d0*/ LDG.E.64 R12, [R2.64+-0x320] ; /* 0xfffce004020c7981 */
/* 0x000ea8000c1e1b00 */
/*02e0*/ LDG.E.64 R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x000ee8000c1e1b00 */
/*02f0*/ LDG.E.64 R16, [R2.64+-0x8] ; /* 0xfffff80402107981 */
/* 0x000f22000c1e1b00 */
/*0300*/ MUFU.RCP64H R19, 100 ; /* 0x4059000000137908 */
/* 0x000e220000001800 */
/*0310*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x000fe200078e00ff */
/*0320*/ BSSY B0, 0x500 ; /* 0x000001d000007945 */
/* 0x000fe20003800000 */
/*0330*/ IMAD.MOV.U32 R9, RZ, RZ, 0x40590000 ; /* 0x40590000ff097424 */
/* 0x000fc400078e00ff */
/*0340*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fe200078e00ff */
/*0350*/ DADD R10, R10, R12 ; /* 0x000000000a0a7229 */
/* 0x004eca000000000c */
/*0360*/ DFMA R12, R18, -R8, 1 ; /* 0x3ff00000120c742b */
/* 0x001e080000000808 */
/*0370*/ DADD R10, R10, R14 ; /* 0x000000000a0a7229 */
/* 0x008f08000000000e */
/*0380*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e08000000000c */
/*0390*/ DADD R10, R10, R16 ; /* 0x000000000a0a7229 */
/* 0x010e480000000010 */
/*03a0*/ DFMA R12, R18, R12, R18 ; /* 0x0000000c120c722b */
/* 0x001e080000000012 */
/*03b0*/ DFMA R10, R4, -4, R10 ; /* 0xc0100000040a782b */
/* 0x002e48000000000a */
/*03c0*/ DFMA R8, R12, -R8, 1 ; /* 0x3ff000000c08742b */
/* 0x001e080000000808 */
/*03d0*/ DMUL R10, R10, 10 ; /* 0x402400000a0a7828 */
/* 0x002e480000000000 */
/*03e0*/ DFMA R12, R12, R8, R12 ; /* 0x000000080c0c722b */
/* 0x001fc8000000000c */
/*03f0*/ DMUL R10, R10, c[0x2][0x8] ; /* 0x008002000a0a7a28 */
/* 0x002e0c0000000000 */
/*0400*/ DMUL R4, R12, R10 ; /* 0x0000000a0c047228 */
/* 0x001e080000000000 */
/*0410*/ FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; /* 0x036000000b00780b */
/* 0x000fe40003f2e200 */
/*0420*/ DFMA R8, R4, -100, R10 ; /* 0xc05900000408782b */
/* 0x001e0c000000000a */
/*0430*/ DFMA R4, R12, R8, R4 ; /* 0x000000080c04722b */
/* 0x001e140000000004 */
/*0440*/ FFMA R0, RZ, 3.390625, R5 ; /* 0x40590000ff007823 */
/* 0x001fca0000000005 */
/*0450*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0460*/ @P0 BRA P1, 0x4f0 ; /* 0x0000008000000947 */
/* 0x000fea0000800000 */
/*0470*/ IMAD.MOV.U32 R12, RZ, RZ, R10 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e000a */
/*0480*/ MOV R0, 0x4d0 ; /* 0x000004d000007802 */
/* 0x000fe20000000f00 */
/*0490*/ IMAD.MOV.U32 R13, RZ, RZ, R11 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e000b */
/*04a0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*04b0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x40590000 ; /* 0x40590000ff0b7424 */
/* 0x000fe400078e00ff */
/*04c0*/ CALL.REL.NOINC 0x530 ; /* 0x0000006000007944 */
/* 0x000fea0003c00000 */
/*04d0*/ IMAD.MOV.U32 R4, RZ, RZ, R16 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0010 */
/*04e0*/ IMAD.MOV.U32 R5, RZ, RZ, R17 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0011 */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ DADD R4, R4, R6 ; /* 0x0000000004047229 */
/* 0x000e0e0000000006 */
/*0510*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ FSETP.GEU.AND P0, PT, |R11|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x040fe20003f0e200 */
/*0540*/ IMAD.MOV.U32 R17, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff117424 */
/* 0x000fe200078e00ff */
/*0550*/ LOP3.LUT R8, R11, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff0b087812 */
/* 0x000fe200078ec0ff */
/*0560*/ IMAD.MOV.U32 R20, RZ, RZ, 0x1 ; /* 0x00000001ff147424 */
/* 0x000fe200078e00ff */
/*0570*/ FSETP.GEU.AND P2, PT, |R13|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x040fe20003f4e200 */
/*0580*/ IMAD.MOV.U32 R14, RZ, RZ, R12 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e000c */
/*0590*/ LOP3.LUT R9, R8, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000008097812 */
/* 0x000fe200078efcff */
/*05a0*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000a */
/*05b0*/ LOP3.LUT R16, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d107812 */
/* 0x000fe200078ec0ff */
/*05c0*/ BSSY B1, 0xad0 ; /* 0x0000050000017945 */
/* 0x000fe20003800000 */
/*05d0*/ LOP3.LUT R23, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b177812 */
/* 0x000fc600078ec0ff */
/*05e0*/ @!P0 DMUL R8, R10, 8.98846567431157953865e+307 ; /* 0x7fe000000a088828 */
/* 0x000e220000000000 */
/*05f0*/ ISETP.GE.U32.AND P1, PT, R16, R23, PT ; /* 0x000000171000720c */
/* 0x000fc60003f26070 */
/*0600*/ @!P2 LOP3.LUT R15, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0fa812 */
/* 0x000fe200078ec0ff */
/*0610*/ @!P2 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff12a224 */
/* 0x000fe200078e00ff */
/*0620*/ MUFU.RCP64H R21, R9 ; /* 0x0000000900157308 */
/* 0x001e240000001800 */
/*0630*/ @!P2 ISETP.GE.U32.AND P3, PT, R16, R15, PT ; /* 0x0000000f1000a20c */
/* 0x000fe40003f66070 */
/*0640*/ SEL R15, R17.reuse, 0x63400000, !P1 ; /* 0x63400000110f7807 */
/* 0x040fe40004800000 */
/*0650*/ @!P2 SEL R19, R17, 0x63400000, !P3 ; /* 0x634000001113a807 */
/* 0x000fe40005800000 */
/*0660*/ LOP3.LUT R15, R15, 0x800fffff, R13, 0xf8, !PT ; /* 0x800fffff0f0f7812 */
/* 0x000fc400078ef80d */
/*0670*/ @!P2 LOP3.LUT R19, R19, 0x80000000, R13, 0xf8, !PT ; /* 0x800000001313a812 */
/* 0x000fc800078ef80d */
/*0680*/ @!P2 LOP3.LUT R19, R19, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001313a812 */
/* 0x000fe200078efcff */
/*0690*/ DFMA R24, R20, -R8, 1 ; /* 0x3ff000001418742b */
/* 0x001e0a0000000808 */
/*06a0*/ @!P2 DFMA R14, R14, 2, -R18 ; /* 0x400000000e0ea82b */
/* 0x000fc80000000812 */
/*06b0*/ DFMA R24, R24, R24, R24 ; /* 0x000000181818722b */
/* 0x001e0c0000000018 */
/*06c0*/ DFMA R24, R20, R24, R20 ; /* 0x000000181418722b */
/* 0x0010640000000014 */
/*06d0*/ IMAD.MOV.U32 R20, RZ, RZ, R16 ; /* 0x000000ffff147224 */
/* 0x001fe200078e0010 */
/*06e0*/ @!P2 LOP3.LUT R20, R15, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000f14a812 */
/* 0x000fe200078ec0ff */
/*06f0*/ IMAD.MOV.U32 R21, RZ, RZ, R23 ; /* 0x000000ffff157224 */
/* 0x000fe200078e0017 */
/*0700*/ @!P0 LOP3.LUT R21, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009158812 */
/* 0x000fe200078ec0ff */
/*0710*/ DFMA R18, R24, -R8, 1 ; /* 0x3ff000001812742b */
/* 0x002e060000000808 */
/*0720*/ IADD3 R26, R21, -0x1, RZ ; /* 0xffffffff151a7810 */
/* 0x000fc60007ffe0ff */
/*0730*/ DFMA R18, R24, R18, R24 ; /* 0x000000121812722b */
/* 0x0010640000000018 */
/*0740*/ IADD3 R24, R20, -0x1, RZ ; /* 0xffffffff14187810 */
/* 0x001fc80007ffe0ff */
/*0750*/ ISETP.GT.U32.AND P0, PT, R24, 0x7feffffe, PT ; /* 0x7feffffe1800780c */
/* 0x000fe20003f04070 */
/*0760*/ DMUL R22, R18, R14 ; /* 0x0000000e12167228 */
/* 0x002e060000000000 */
/*0770*/ ISETP.GT.U32.OR P0, PT, R26, 0x7feffffe, P0 ; /* 0x7feffffe1a00780c */
/* 0x000fc60000704470 */
/*0780*/ DFMA R24, R22, -R8, R14 ; /* 0x800000081618722b */
/* 0x001e0c000000000e */
/*0790*/ DFMA R18, R18, R24, R22 ; /* 0x000000181212722b */
/* 0x0010480000000016 */
/*07a0*/ @P0 BRA 0x970 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*07b0*/ LOP3.LUT R13, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0d7812 */
/* 0x003fe200078ec0ff */
/*07c0*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fc600078e00ff */
/*07d0*/ ISETP.GE.U32.AND P0, PT, R16.reuse, R13, PT ; /* 0x0000000d1000720c */
/* 0x040fe20003f06070 */
/*07e0*/ IMAD.IADD R12, R16, 0x1, -R13 ; /* 0x00000001100c7824 */
/* 0x000fc600078e0a0d */
/*07f0*/ SEL R17, R17, 0x63400000, !P0 ; /* 0x6340000011117807 */
/* 0x000fe40004000000 */
/*0800*/ IMNMX R12, R12, -0x46a00000, !PT ; /* 0xb96000000c0c7817 */
/* 0x000fc80007800200 */
/*0810*/ IMNMX R12, R12, 0x46a00000, PT ; /* 0x46a000000c0c7817 */
/* 0x000fca0003800200 */
/*0820*/ IMAD.IADD R12, R12, 0x1, -R17 ; /* 0x000000010c0c7824 */
/* 0x000fca00078e0a11 */
/*0830*/ IADD3 R21, R12, 0x7fe00000, RZ ; /* 0x7fe000000c157810 */
/* 0x000fcc0007ffe0ff */
/*0840*/ DMUL R16, R18, R20 ; /* 0x0000001412107228 */
/* 0x000e140000000000 */
/*0850*/ FSETP.GTU.AND P0, PT, |R17|, 1.469367938527859385e-39, PT ; /* 0x001000001100780b */
/* 0x001fda0003f0c200 */
/*0860*/ @P0 BRA 0xac0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0870*/ DFMA R8, R18, -R8, R14 ; /* 0x800000081208722b */
/* 0x000e22000000000e */
/*0880*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fd200078e00ff */
/*0890*/ FSETP.NEU.AND P0, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720b */
/* 0x041fe40003f0d000 */
/*08a0*/ LOP3.LUT R11, R9, 0x80000000, R11, 0x48, !PT ; /* 0x80000000090b7812 */
/* 0x000fc800078e480b */
/*08b0*/ LOP3.LUT R21, R11, R21, RZ, 0xfc, !PT ; /* 0x000000150b157212 */
/* 0x000fce00078efcff */
/*08c0*/ @!P0 BRA 0xac0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*08d0*/ IMAD.MOV R9, RZ, RZ, -R12 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a0c */
/*08e0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fcc00078e00ff */
/*08f0*/ DFMA R8, R16, -R8, R18 ; /* 0x800000081008722b */
/* 0x000e080000000012 */
/*0900*/ DMUL.RP R18, R18, R20 ; /* 0x0000001412127228 */
/* 0x000e640000008000 */
/*0910*/ IADD3 R8, -R12, -0x43300000, RZ ; /* 0xbcd000000c087810 */
/* 0x001fc80007ffe1ff */
/*0920*/ FSETP.NEU.AND P0, PT, |R9|, R8, PT ; /* 0x000000080900720b */
/* 0x000fc80003f0d200 */
/*0930*/ LOP3.LUT R11, R19, R11, RZ, 0x3c, !PT ; /* 0x0000000b130b7212 */
/* 0x002fe400078e3cff */
/*0940*/ FSEL R16, R18, R16, !P0 ; /* 0x0000001012107208 */
/* 0x000fe40004000000 */
/*0950*/ FSEL R17, R11, R17, !P0 ; /* 0x000000110b117208 */
/* 0x000fe20004000000 */
/*0960*/ BRA 0xac0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0970*/ DSETP.NAN.AND P0, PT, R12, R12, PT ; /* 0x0000000c0c00722a */
/* 0x003e1c0003f08000 */
/*0980*/ @P0 BRA 0xaa0 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0990*/ DSETP.NAN.AND P0, PT, R10, R10, PT ; /* 0x0000000a0a00722a */
/* 0x000e1c0003f08000 */
/*09a0*/ @P0 BRA 0xa70 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*09b0*/ ISETP.NE.AND P0, PT, R20, R21, PT ; /* 0x000000151400720c */
/* 0x000fe20003f05270 */
/*09c0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x0 ; /* 0x00000000ff107424 */
/* 0x000fe400078e00ff */
/*09d0*/ IMAD.MOV.U32 R17, RZ, RZ, -0x80000 ; /* 0xfff80000ff117424 */
/* 0x000fd400078e00ff */
/*09e0*/ @!P0 BRA 0xac0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*09f0*/ ISETP.NE.AND P0, PT, R20, 0x7ff00000, PT ; /* 0x7ff000001400780c */
/* 0x000fe40003f05270 */
/*0a00*/ LOP3.LUT R17, R13, 0x80000000, R11, 0x48, !PT ; /* 0x800000000d117812 */
/* 0x000fe400078e480b */
/*0a10*/ ISETP.EQ.OR P0, PT, R21, RZ, !P0 ; /* 0x000000ff1500720c */
/* 0x000fda0004702670 */
/*0a20*/ @P0 LOP3.LUT R8, R17, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000011080812 */
/* 0x000fe200078efcff */
/*0a30*/ @!P0 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff108224 */
/* 0x000fe400078e00ff */
/*0a40*/ @P0 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff100224 */
/* 0x000fe400078e00ff */
/*0a50*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, R8 ; /* 0x000000ffff110224 */
/* 0x000fe200078e0008 */
/*0a60*/ BRA 0xac0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0a70*/ LOP3.LUT R17, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b117812 */
/* 0x000fe200078efcff */
/*0a80*/ IMAD.MOV.U32 R16, RZ, RZ, R10 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000a */
/*0a90*/ BRA 0xac0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0aa0*/ LOP3.LUT R17, R13, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000d117812 */
/* 0x000fe200078efcff */
/*0ab0*/ IMAD.MOV.U32 R16, RZ, RZ, R12 ; /* 0x000000ffff107224 */
/* 0x000fe400078e000c */
/*0ac0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ad0*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0000 */
/*0ae0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fc800078e00ff */
/*0af0*/ RET.REL.NODEC R8 0x0 ; /* 0xfffff50008007950 */
/* 0x000fea0003c3ffff */
/*0b00*/ BRA 0xb00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cstdlib>
#include <cstdio>
#include <time.h>
#include <sys/time.h>
#include <cuda.h>
#include<cuda_runtime.h>
#include<device_launch_parameters.h>
#define BLOCKSIZE_x 32
#define BLOCKSIZE_y 32
#define l 100
#define dt 0.01
#define D 10.0
#define d 0.4
//using namespace std;
double my_gettimeofday(){
struct timeval tmp_time;
gettimeofday(&tmp_time, NULL);
return tmp_time.tv_sec + (tmp_time.tv_usec * 1.0e-6L);
}
/*****************/
/* CUDA MEMCHECK */
/*****************/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, char *file, int line, bool abort = true)
{
if (code != cudaSuccess)
{
fprintf(stderr, "GPUassert: %s %s %dn", cudaGetErrorString(code), file, line);
if (abort) { exit(code); }
}
}
int iDivUp(int hostPtr, int b){ return ((hostPtr % b) != 0) ? (hostPtr / b + 1) : (hostPtr / b); }
__global__ void solve(double A[l][l])
{
int i = threadIdx.x+blockIdx.x * blockDim.x;
int j = threadIdx.y+blockIdx.y * blockDim.y;
if( i < l-1 && j < l-1 && (i!=0) && (j!=0) )
{
A[i][j] = A[i][j]*(1-d*dt)/l+(A[i-1][j] + A[i+1][j] + A[i][j+1] + A[i][j-1] - 4*A[i][j])*D*dt/l;
}
}
int main(){
float phi0=0.4;
double cpu_mesh[l][l];
double cpu_res[l][l];
double (*gpu_mesh)[l]; //pointers to arrays of dimension N
double (*gpu_res)[l];
/* Initializing cpu_mesh with source at the center*/
for(int i=0 ; i< l; i++){
for(int j=0 ; j<l ; ++j){
cpu_mesh[i][j]=0.0;
}
}
cpu_mesh[l/2-1][l/2 -1]=phi0;
cpu_mesh[l/2][l/2 -1]=phi0;
cpu_mesh[l/2][l/2]=phi0;
cpu_mesh[l/2-1][l/2]=phi0;
/* Allocation */
cudaMalloc((void**)&gpu_mesh, (l*l)*sizeof(double));
cudaMalloc((void**)&gpu_res, (l*l)*sizeof(double));
//copying from host to device
double debut = my_gettimeofday();
double debutTransfert = my_gettimeofday();
gpuErrchk(cudaMemcpy(gpu_mesh, cpu_mesh, (l*l)*sizeof(double), cudaMemcpyHostToDevice));
double finTransfert = my_gettimeofday();
std::cout << "Transfert CPU vers GPU :" << finTransfert-debutTransfert << std::endl;
dim3 gridSize(iDivUp(l, BLOCKSIZE_x), iDivUp(l, BLOCKSIZE_y));
dim3 blockSize(BLOCKSIZE_y, BLOCKSIZE_x);
//solve <<<gridSize, blockSize>>> (gpu_mesh, gpu_res, D, dt, d);
for(int i=0; i<1000; ++i){
solve<<<gridSize, blockSize>>> (gpu_mesh);
}
debutTransfert = my_gettimeofday();
cudaMemcpy(cpu_res, gpu_mesh, (l*l)*sizeof(double), cudaMemcpyDeviceToHost);
std::cout << "Transfert GPU vers CPU :" << finTransfert-debutTransfert << std::endl;
finTransfert = my_gettimeofday();
double fin= my_gettimeofday();
std::cout << "Temps calcul :" << fin-debut << std::endl;
/*for (int i = 0; i < l; i++){
for (int j = 0; j < l; j++){
std::cout << cpu_res[i][j] << " ";
}
std::cout << std::endl;
}*/
return 0;
} | .file "tmpxft_000e84fe_00000000-6_nvidiatest.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15my_gettimeofdayv
.type _Z15my_gettimeofdayv, @function
_Z15my_gettimeofdayv:
.LFB3669:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
fildq 24(%rsp)
fldt .LC0(%rip)
fmulp %st, %st(1)
fildq 16(%rsp)
faddp %st, %st(1)
fstpl 8(%rsp)
movsd 8(%rsp), %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z15my_gettimeofdayv, .-_Z15my_gettimeofdayv
.globl _Z6iDivUpii
.type _Z6iDivUpii, @function
_Z6iDivUpii:
.LFB3671:
.cfi_startproc
endbr64
movl %edi, %eax
cltd
idivl %esi
testl %edx, %edx
je .L8
movl %edi, %eax
cltd
idivl %esi
addl $1, %eax
ret
.L8:
movl %edi, %eax
cltd
idivl %esi
ret
.cfi_endproc
.LFE3671:
.size _Z6iDivUpii, .-_Z6iDivUpii
.globl _Z29__device_stub__Z5solvePA100_dPA100_d
.type _Z29__device_stub__Z5solvePA100_dPA100_d, @function
_Z29__device_stub__Z5solvePA100_dPA100_d:
.LFB3697:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5solvePA100_d(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z29__device_stub__Z5solvePA100_dPA100_d, .-_Z29__device_stub__Z5solvePA100_dPA100_d
.globl _Z5solvePA100_d
.type _Z5solvePA100_d, @function
_Z5solvePA100_d:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5solvePA100_dPA100_d
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z5solvePA100_d, .-_Z5solvePA100_d
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Adahn/Project-CUBIOSIM/master/fdm/nvidiatest.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "GPUassert: %s %s %dn"
.LC6:
.string "Transfert CPU vers GPU :"
.LC7:
.string "Transfert GPU vers CPU :"
.LC8:
.string "Temps calcul :"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq -159744(%rsp), %r11
.cfi_def_cfa 11, 159760
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $352, %rsp
.cfi_def_cfa_offset 160112
movq %fs:40, %rax
movq %rax, 160088(%rsp)
xorl %eax, %eax
leaq 880(%rsp), %rdx
leaq 80880(%rsp), %rcx
.L19:
leaq -800(%rdx), %rax
.L20:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L20
addq $800, %rdx
cmpq %rcx, %rdx
jne .L19
movsd .LC3(%rip), %xmm0
movsd %xmm0, 39672(%rsp)
movsd %xmm0, 40472(%rsp)
movsd %xmm0, 40480(%rsp)
movsd %xmm0, 39680(%rsp)
leaq 40(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
call _Z15my_gettimeofdayv
movsd %xmm0, 16(%rsp)
call _Z15my_gettimeofdayv
movsd %xmm0, 24(%rsp)
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $80000, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L29
call _Z15my_gettimeofdayv
movsd %xmm0, 8(%rsp)
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
subsd 24(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $4, 56(%rsp)
movl $4, 60(%rsp)
movl $1, 64(%rsp)
movl $32, 68(%rsp)
movl $32, 72(%rsp)
movl $1, 76(%rsp)
movl $1000, %ebx
jmp .L24
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $88, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L23:
subl $1, %ebx
je .L30
.L24:
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L23
movq 40(%rsp), %rdi
call _Z29__device_stub__Z5solvePA100_dPA100_d
jmp .L23
.L30:
call _Z15my_gettimeofdayv
movsd %xmm0, 24(%rsp)
leaq 80080(%rsp), %rdi
movl $2, %ecx
movl $80000, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm1
subsd 24(%rsp), %xmm1
movapd %xmm1, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call _Z15my_gettimeofdayv
call _Z15my_gettimeofdayv
movsd %xmm0, 8(%rsp)
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
subsd 16(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 160088(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $160096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z5solvePA100_d"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z5solvePA100_d(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC0:
.long -1351849546
.long -2043167483
.long 16363
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long -1610612736
.long 1071225241
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdlib>
#include <cstdio>
#include <time.h>
#include <sys/time.h>
#include <cuda.h>
#include<cuda_runtime.h>
#include<device_launch_parameters.h>
#define BLOCKSIZE_x 32
#define BLOCKSIZE_y 32
#define l 100
#define dt 0.01
#define D 10.0
#define d 0.4
//using namespace std;
double my_gettimeofday(){
struct timeval tmp_time;
gettimeofday(&tmp_time, NULL);
return tmp_time.tv_sec + (tmp_time.tv_usec * 1.0e-6L);
}
/*****************/
/* CUDA MEMCHECK */
/*****************/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, char *file, int line, bool abort = true)
{
if (code != cudaSuccess)
{
fprintf(stderr, "GPUassert: %s %s %dn", cudaGetErrorString(code), file, line);
if (abort) { exit(code); }
}
}
int iDivUp(int hostPtr, int b){ return ((hostPtr % b) != 0) ? (hostPtr / b + 1) : (hostPtr / b); }
__global__ void solve(double A[l][l])
{
int i = threadIdx.x+blockIdx.x * blockDim.x;
int j = threadIdx.y+blockIdx.y * blockDim.y;
if( i < l-1 && j < l-1 && (i!=0) && (j!=0) )
{
A[i][j] = A[i][j]*(1-d*dt)/l+(A[i-1][j] + A[i+1][j] + A[i][j+1] + A[i][j-1] - 4*A[i][j])*D*dt/l;
}
}
int main(){
float phi0=0.4;
double cpu_mesh[l][l];
double cpu_res[l][l];
double (*gpu_mesh)[l]; //pointers to arrays of dimension N
double (*gpu_res)[l];
/* Initializing cpu_mesh with source at the center*/
for(int i=0 ; i< l; i++){
for(int j=0 ; j<l ; ++j){
cpu_mesh[i][j]=0.0;
}
}
cpu_mesh[l/2-1][l/2 -1]=phi0;
cpu_mesh[l/2][l/2 -1]=phi0;
cpu_mesh[l/2][l/2]=phi0;
cpu_mesh[l/2-1][l/2]=phi0;
/* Allocation */
cudaMalloc((void**)&gpu_mesh, (l*l)*sizeof(double));
cudaMalloc((void**)&gpu_res, (l*l)*sizeof(double));
//copying from host to device
double debut = my_gettimeofday();
double debutTransfert = my_gettimeofday();
gpuErrchk(cudaMemcpy(gpu_mesh, cpu_mesh, (l*l)*sizeof(double), cudaMemcpyHostToDevice));
double finTransfert = my_gettimeofday();
std::cout << "Transfert CPU vers GPU :" << finTransfert-debutTransfert << std::endl;
dim3 gridSize(iDivUp(l, BLOCKSIZE_x), iDivUp(l, BLOCKSIZE_y));
dim3 blockSize(BLOCKSIZE_y, BLOCKSIZE_x);
//solve <<<gridSize, blockSize>>> (gpu_mesh, gpu_res, D, dt, d);
for(int i=0; i<1000; ++i){
solve<<<gridSize, blockSize>>> (gpu_mesh);
}
debutTransfert = my_gettimeofday();
cudaMemcpy(cpu_res, gpu_mesh, (l*l)*sizeof(double), cudaMemcpyDeviceToHost);
std::cout << "Transfert GPU vers CPU :" << finTransfert-debutTransfert << std::endl;
finTransfert = my_gettimeofday();
double fin= my_gettimeofday();
std::cout << "Temps calcul :" << fin-debut << std::endl;
/*for (int i = 0; i < l; i++){
for (int j = 0; j < l; j++){
std::cout << cpu_res[i][j] << " ";
}
std::cout << std::endl;
}*/
return 0;
} | #include <iostream>
#include <cstdlib>
#include <cstdio>
#include <time.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#define BLOCKSIZE_x 32
#define BLOCKSIZE_y 32
#define l 100
#define dt 0.01
#define D 10.0
#define d 0.4
//using namespace std;
double my_gettimeofday(){
struct timeval tmp_time;
gettimeofday(&tmp_time, NULL);
return tmp_time.tv_sec + (tmp_time.tv_usec * 1.0e-6L);
}
/*****************/
/* CUDA MEMCHECK */
/*****************/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, char *file, int line, bool abort = true)
{
if (code != hipSuccess)
{
fprintf(stderr, "GPUassert: %s %s %dn", hipGetErrorString(code), file, line);
if (abort) { exit(code); }
}
}
int iDivUp(int hostPtr, int b){ return ((hostPtr % b) != 0) ? (hostPtr / b + 1) : (hostPtr / b); }
__global__ void solve(double A[l][l])
{
int i = threadIdx.x+blockIdx.x * blockDim.x;
int j = threadIdx.y+blockIdx.y * blockDim.y;
if( i < l-1 && j < l-1 && (i!=0) && (j!=0) )
{
A[i][j] = A[i][j]*(1-d*dt)/l+(A[i-1][j] + A[i+1][j] + A[i][j+1] + A[i][j-1] - 4*A[i][j])*D*dt/l;
}
}
int main(){
float phi0=0.4;
double cpu_mesh[l][l];
double cpu_res[l][l];
double (*gpu_mesh)[l]; //pointers to arrays of dimension N
double (*gpu_res)[l];
/* Initializing cpu_mesh with source at the center*/
for(int i=0 ; i< l; i++){
for(int j=0 ; j<l ; ++j){
cpu_mesh[i][j]=0.0;
}
}
cpu_mesh[l/2-1][l/2 -1]=phi0;
cpu_mesh[l/2][l/2 -1]=phi0;
cpu_mesh[l/2][l/2]=phi0;
cpu_mesh[l/2-1][l/2]=phi0;
/* Allocation */
hipMalloc((void**)&gpu_mesh, (l*l)*sizeof(double));
hipMalloc((void**)&gpu_res, (l*l)*sizeof(double));
//copying from host to device
double debut = my_gettimeofday();
double debutTransfert = my_gettimeofday();
gpuErrchk(hipMemcpy(gpu_mesh, cpu_mesh, (l*l)*sizeof(double), hipMemcpyHostToDevice));
double finTransfert = my_gettimeofday();
std::cout << "Transfert CPU vers GPU :" << finTransfert-debutTransfert << std::endl;
dim3 gridSize(iDivUp(l, BLOCKSIZE_x), iDivUp(l, BLOCKSIZE_y));
dim3 blockSize(BLOCKSIZE_y, BLOCKSIZE_x);
//solve <<<gridSize, blockSize>>> (gpu_mesh, gpu_res, D, dt, d);
for(int i=0; i<1000; ++i){
solve<<<gridSize, blockSize>>> (gpu_mesh);
}
debutTransfert = my_gettimeofday();
hipMemcpy(cpu_res, gpu_mesh, (l*l)*sizeof(double), hipMemcpyDeviceToHost);
std::cout << "Transfert GPU vers CPU :" << finTransfert-debutTransfert << std::endl;
finTransfert = my_gettimeofday();
double fin= my_gettimeofday();
std::cout << "Temps calcul :" << fin-debut << std::endl;
/*for (int i = 0; i < l; i++){
for (int j = 0; j < l; j++){
std::cout << cpu_res[i][j] << " ";
}
std::cout << std::endl;
}*/
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <cstdlib>
#include <cstdio>
#include <time.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#define BLOCKSIZE_x 32
#define BLOCKSIZE_y 32
#define l 100
#define dt 0.01
#define D 10.0
#define d 0.4
//using namespace std;
double my_gettimeofday(){
struct timeval tmp_time;
gettimeofday(&tmp_time, NULL);
return tmp_time.tv_sec + (tmp_time.tv_usec * 1.0e-6L);
}
/*****************/
/* CUDA MEMCHECK */
/*****************/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, char *file, int line, bool abort = true)
{
if (code != hipSuccess)
{
fprintf(stderr, "GPUassert: %s %s %dn", hipGetErrorString(code), file, line);
if (abort) { exit(code); }
}
}
int iDivUp(int hostPtr, int b){ return ((hostPtr % b) != 0) ? (hostPtr / b + 1) : (hostPtr / b); }
__global__ void solve(double A[l][l])
{
int i = threadIdx.x+blockIdx.x * blockDim.x;
int j = threadIdx.y+blockIdx.y * blockDim.y;
if( i < l-1 && j < l-1 && (i!=0) && (j!=0) )
{
A[i][j] = A[i][j]*(1-d*dt)/l+(A[i-1][j] + A[i+1][j] + A[i][j+1] + A[i][j-1] - 4*A[i][j])*D*dt/l;
}
}
int main(){
float phi0=0.4;
double cpu_mesh[l][l];
double cpu_res[l][l];
double (*gpu_mesh)[l]; //pointers to arrays of dimension N
double (*gpu_res)[l];
/* Initializing cpu_mesh with source at the center*/
for(int i=0 ; i< l; i++){
for(int j=0 ; j<l ; ++j){
cpu_mesh[i][j]=0.0;
}
}
cpu_mesh[l/2-1][l/2 -1]=phi0;
cpu_mesh[l/2][l/2 -1]=phi0;
cpu_mesh[l/2][l/2]=phi0;
cpu_mesh[l/2-1][l/2]=phi0;
/* Allocation */
hipMalloc((void**)&gpu_mesh, (l*l)*sizeof(double));
hipMalloc((void**)&gpu_res, (l*l)*sizeof(double));
//copying from host to device
double debut = my_gettimeofday();
double debutTransfert = my_gettimeofday();
gpuErrchk(hipMemcpy(gpu_mesh, cpu_mesh, (l*l)*sizeof(double), hipMemcpyHostToDevice));
double finTransfert = my_gettimeofday();
std::cout << "Transfert CPU vers GPU :" << finTransfert-debutTransfert << std::endl;
dim3 gridSize(iDivUp(l, BLOCKSIZE_x), iDivUp(l, BLOCKSIZE_y));
dim3 blockSize(BLOCKSIZE_y, BLOCKSIZE_x);
//solve <<<gridSize, blockSize>>> (gpu_mesh, gpu_res, D, dt, d);
for(int i=0; i<1000; ++i){
solve<<<gridSize, blockSize>>> (gpu_mesh);
}
debutTransfert = my_gettimeofday();
hipMemcpy(cpu_res, gpu_mesh, (l*l)*sizeof(double), hipMemcpyDeviceToHost);
std::cout << "Transfert GPU vers CPU :" << finTransfert-debutTransfert << std::endl;
finTransfert = my_gettimeofday();
double fin= my_gettimeofday();
std::cout << "Temps calcul :" << fin-debut << std::endl;
/*for (int i = 0; i < l; i++){
for (int j = 0; j < l; j++){
std::cout << cpu_res[i][j] << " ";
}
std::cout << std::endl;
}*/
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5solvePA100_d
.globl _Z5solvePA100_d
.p2align 8
.type _Z5solvePA100_d,@function
_Z5solvePA100_d:
s_load_b32 s2, s[0:1], 0x14
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_ne_u32_e32 vcc_lo, 0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_max_i32_e32 v2, v0, v1
v_cmp_ne_u32_e64 s2, 0, v1
v_cmp_gt_i32_e64 s3, 0x63, v2
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s3, 0x3f847ae1
s_mov_b32 s2, 0x47ae147b
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[3:4], null, v0, 0x320, s[0:1]
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_mov_b32 s1, 0x3fefdf3b
s_mov_b32 s0, 0x645a1cac
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v3, v0
v_add_co_ci_u32_e32 v6, vcc_lo, v4, v1, vcc_lo
s_clause 0x3
global_load_b64 v[7:8], v[5:6], off offset:800
global_load_b64 v[9:10], v[5:6], off offset:-800
global_load_b128 v[0:3], v[5:6], off
global_load_b64 v[11:12], v[5:6], off offset:-8
s_waitcnt vmcnt(2)
v_add_f64 v[7:8], v[9:10], v[7:8]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[7:8], v[2:3]
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[2:3], v[0:1], -4.0, v[2:3]
v_mul_f64 v[0:1], v[0:1], s[0:1]
v_mul_f64 v[2:3], v[2:3], 0x40240000
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_scale_f64 v[7:8], null, 0x40590000, 0x40590000, v[0:1]
v_div_scale_f64 v[19:20], vcc_lo, v[0:1], 0x40590000, v[0:1]
v_mul_f64 v[2:3], v[2:3], s[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[11:12], v[7:8]
v_div_scale_f64 v[9:10], null, 0x40590000, 0x40590000, v[2:3]
s_waitcnt_depctr 0xfff
v_fma_f64 v[15:16], -v[7:8], v[11:12], 1.0
v_rcp_f64_e32 v[13:14], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f64 v[11:12], v[11:12], v[15:16], v[11:12]
s_waitcnt_depctr 0xfff
v_fma_f64 v[17:18], -v[9:10], v[13:14], 1.0
v_fma_f64 v[15:16], -v[7:8], v[11:12], 1.0
v_fma_f64 v[13:14], v[13:14], v[17:18], v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[11:12], v[11:12], v[15:16], v[11:12]
v_div_scale_f64 v[15:16], s0, v[2:3], 0x40590000, v[2:3]
v_fma_f64 v[17:18], -v[9:10], v[13:14], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[13:14], v[13:14], v[17:18], v[13:14]
v_mul_f64 v[17:18], v[19:20], v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[21:22], v[15:16], v[13:14]
v_fma_f64 v[7:8], -v[7:8], v[17:18], v[19:20]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[9:10], -v[9:10], v[21:22], v[15:16]
v_div_fmas_f64 v[7:8], v[7:8], v[11:12], v[17:18]
s_mov_b32 vcc_lo, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[9:10], v[9:10], v[13:14], v[21:22]
v_div_fixup_f64 v[0:1], v[7:8], 0x40590000, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[2:3], v[9:10], 0x40590000, v[2:3]
v_add_f64 v[0:1], v[0:1], v[2:3]
global_store_b64 v[5:6], v[0:1], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5solvePA100_d
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5solvePA100_d, .Lfunc_end0-_Z5solvePA100_d
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5solvePA100_d
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5solvePA100_d.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <cstdlib>
#include <cstdio>
#include <time.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#define BLOCKSIZE_x 32
#define BLOCKSIZE_y 32
#define l 100
#define dt 0.01
#define D 10.0
#define d 0.4
//using namespace std;
double my_gettimeofday(){
struct timeval tmp_time;
gettimeofday(&tmp_time, NULL);
return tmp_time.tv_sec + (tmp_time.tv_usec * 1.0e-6L);
}
/*****************/
/* CUDA MEMCHECK */
/*****************/
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, char *file, int line, bool abort = true)
{
if (code != hipSuccess)
{
fprintf(stderr, "GPUassert: %s %s %dn", hipGetErrorString(code), file, line);
if (abort) { exit(code); }
}
}
int iDivUp(int hostPtr, int b){ return ((hostPtr % b) != 0) ? (hostPtr / b + 1) : (hostPtr / b); }
__global__ void solve(double A[l][l])
{
int i = threadIdx.x+blockIdx.x * blockDim.x;
int j = threadIdx.y+blockIdx.y * blockDim.y;
if( i < l-1 && j < l-1 && (i!=0) && (j!=0) )
{
A[i][j] = A[i][j]*(1-d*dt)/l+(A[i-1][j] + A[i+1][j] + A[i][j+1] + A[i][j-1] - 4*A[i][j])*D*dt/l;
}
}
int main(){
float phi0=0.4;
double cpu_mesh[l][l];
double cpu_res[l][l];
double (*gpu_mesh)[l]; //pointers to arrays of dimension N
double (*gpu_res)[l];
/* Initializing cpu_mesh with source at the center*/
for(int i=0 ; i< l; i++){
for(int j=0 ; j<l ; ++j){
cpu_mesh[i][j]=0.0;
}
}
cpu_mesh[l/2-1][l/2 -1]=phi0;
cpu_mesh[l/2][l/2 -1]=phi0;
cpu_mesh[l/2][l/2]=phi0;
cpu_mesh[l/2-1][l/2]=phi0;
/* Allocation */
hipMalloc((void**)&gpu_mesh, (l*l)*sizeof(double));
hipMalloc((void**)&gpu_res, (l*l)*sizeof(double));
//copying from host to device
double debut = my_gettimeofday();
double debutTransfert = my_gettimeofday();
gpuErrchk(hipMemcpy(gpu_mesh, cpu_mesh, (l*l)*sizeof(double), hipMemcpyHostToDevice));
double finTransfert = my_gettimeofday();
std::cout << "Transfert CPU vers GPU :" << finTransfert-debutTransfert << std::endl;
dim3 gridSize(iDivUp(l, BLOCKSIZE_x), iDivUp(l, BLOCKSIZE_y));
dim3 blockSize(BLOCKSIZE_y, BLOCKSIZE_x);
//solve <<<gridSize, blockSize>>> (gpu_mesh, gpu_res, D, dt, d);
for(int i=0; i<1000; ++i){
solve<<<gridSize, blockSize>>> (gpu_mesh);
}
debutTransfert = my_gettimeofday();
hipMemcpy(cpu_res, gpu_mesh, (l*l)*sizeof(double), hipMemcpyDeviceToHost);
std::cout << "Transfert GPU vers CPU :" << finTransfert-debutTransfert << std::endl;
finTransfert = my_gettimeofday();
double fin= my_gettimeofday();
std::cout << "Temps calcul :" << fin-debut << std::endl;
/*for (int i = 0; i < l; i++){
for (int j = 0; j < l; j++){
std::cout << cpu_res[i][j] << " ";
}
std::cout << std::endl;
}*/
return 0;
} | .text
.file "nvidiatest.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z15my_gettimeofdayv
.LCPI0_0:
.quad 0x8637bd05af6c69b6 # x86_fp80 1.00000000000000000004E-6
.short 0x3feb
.zero 6
.text
.globl _Z15my_gettimeofdayv
.p2align 4, 0x90
.type _Z15my_gettimeofdayv,@function
_Z15my_gettimeofdayv: # @_Z15my_gettimeofdayv
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq 24(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 24(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 8(%rsp)
fildll 8(%rsp)
movq %rcx, 16(%rsp)
fildll 16(%rsp)
fldt .LCPI0_0(%rip)
fmulp %st, %st(1)
faddp %st, %st(1)
fstpl (%rsp)
movsd (%rsp), %xmm0 # xmm0 = mem[0],zero
addq $40, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z15my_gettimeofdayv, .Lfunc_end0-_Z15my_gettimeofdayv
.cfi_endproc
# -- End function
.globl _Z6iDivUpii # -- Begin function _Z6iDivUpii
.p2align 4, 0x90
.type _Z6iDivUpii,@function
_Z6iDivUpii: # @_Z6iDivUpii
.cfi_startproc
# %bb.0:
movl %edi, %eax
cltd
idivl %esi
cmpl $1, %edx
sbbl $-1, %eax
retq
.Lfunc_end1:
.size _Z6iDivUpii, .Lfunc_end1-_Z6iDivUpii
.cfi_endproc
# -- End function
.globl _Z20__device_stub__solvePA100_d # -- Begin function _Z20__device_stub__solvePA100_d
.p2align 4, 0x90
.type _Z20__device_stub__solvePA100_d,@function
_Z20__device_stub__solvePA100_d: # @_Z20__device_stub__solvePA100_d
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z5solvePA100_d, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z20__device_stub__solvePA100_d, .Lfunc_end2-_Z20__device_stub__solvePA100_d
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x8637bd05af6c69b6 # x86_fp80 1.00000000000000000004E-6
.short 0x3feb
.zero 6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $160232, %rsp # imm = 0x271E8
.cfi_def_cfa_offset 160288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 80224(%rsp), %rbx
movl $80000, %edx # imm = 0x13880
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movabsq $4600877379429072896, %rax # imm = 0x3FD99999A0000000
movq %rax, 119816(%rsp)
movq %rax, 120616(%rsp)
movq %rax, 120624(%rsp)
movq %rax, 119824(%rsp)
leaq 16(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
leaq 216(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
leaq 224(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 224(%rsp), %rax
movq 232(%rsp), %rcx
movq %rax, 176(%rsp)
fildll 176(%rsp)
movq %rcx, 184(%rsp)
fildll 184(%rsp)
fldt .LCPI3_0(%rip)
fld %st(0)
fstpt (%rsp) # 10-byte Folded Spill
fmulp %st, %st(1)
faddp %st, %st(1)
fstpl 168(%rsp)
movsd 168(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 64(%rsp) # 8-byte Spill
leaq 224(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 224(%rsp), %r14
movq 232(%rsp), %r15
movq 16(%rsp), %rdi
movl $80000, %edx # imm = 0x13880
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_18
# %bb.1: # %_Z9gpuAssert10hipError_tPcib.exit
movq %r15, 136(%rsp)
fildll 136(%rsp)
fldt (%rsp) # 10-byte Folded Reload
fmulp %st, %st(1)
movq %r14, 144(%rsp)
fildll 144(%rsp)
faddp %st, %st(1)
fstpl 128(%rsp)
leaq 224(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 224(%rsp), %rax
movq 232(%rsp), %rcx
movq %rax, 152(%rsp)
fildll 152(%rsp)
movq %rcx, 160(%rsp)
fildll 160(%rsp)
fldt (%rsp) # 10-byte Folded Reload
fmulp %st, %st(1)
faddp %st, %st(1)
fstpl 120(%rsp)
movsd 120(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 40(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 128(%rsp), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_19
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_4
# %bb.3:
movzbl 67(%rbx), %ecx
jmp .LBB3_5
.LBB3_4:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $1000, %r12d # imm = 0x3E8
movabsq $17179869188, %rbx # imm = 0x400000004
movabsq $137438953504, %r14 # imm = 0x2000000020
leaq 200(%rsp), %r13
leaq 192(%rsp), %rbp
leaq 48(%rsp), %r15
jmp .LBB3_6
.p2align 4, 0x90
.LBB3_8: # in Loop: Header=BB3_6 Depth=1
decl %r12d
je .LBB3_9
.LBB3_6: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7: # in Loop: Header=BB3_6 Depth=1
movq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 208(%rsp), %rax
movq %rax, 48(%rsp)
leaq 224(%rsp), %rdi
leaq 24(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 224(%rsp), %rsi
movl 232(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z5solvePA100_d, %edi
movq %r15, %r9
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
pushq 208(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_8
.LBB3_9:
leaq 224(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 224(%rsp), %rax
movq 232(%rsp), %rcx
movq %rax, 104(%rsp)
fildll 104(%rsp)
movq %rcx, 112(%rsp)
fildll 112(%rsp)
fldt (%rsp) # 10-byte Folded Reload
fmulp %st, %st(1)
faddp %st, %st(1)
fstpl 96(%rsp)
movq 16(%rsp), %rsi
leaq 224(%rsp), %rdi
movl $80000, %edx # imm = 0x13880
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 96(%rsp), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_19
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i27
cmpb $0, 56(%rbx)
je .LBB3_12
# %bb.11:
movzbl 67(%rbx), %ecx
jmp .LBB3_13
.LBB3_12:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit30
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 24(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
leaq 24(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 24(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 80(%rsp)
fildll 80(%rsp)
movq %rcx, 88(%rsp)
fildll 88(%rsp)
fldt (%rsp) # 10-byte Folded Reload
fmulp %st, %st(1)
faddp %st, %st(1)
fstpl 72(%rsp)
movsd 72(%rsp), %xmm0 # xmm0 = mem[0],zero
subsd 64(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_19
# %bb.14: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i32
cmpb $0, 56(%rbx)
je .LBB3_16
# %bb.15:
movzbl 67(%rbx), %ecx
jmp .LBB3_17
.LBB3_16:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit35
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $160232, %rsp # imm = 0x271E8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_19:
.cfi_def_cfa_offset 160288
callq _ZSt16__throw_bad_castv
.LBB3_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $88, %r8d
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5solvePA100_d, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5solvePA100_d,@object # @_Z5solvePA100_d
.section .rodata,"a",@progbits
.globl _Z5solvePA100_d
.p2align 3, 0x0
_Z5solvePA100_d:
.quad _Z20__device_stub__solvePA100_d
.size _Z5solvePA100_d, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Adahn/Project-CUBIOSIM/master/fdm/nvidiatest.hip"
.size .L.str, 106
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Transfert CPU vers GPU :"
.size .L.str.1, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Transfert GPU vers CPU :"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Temps calcul :"
.size .L.str.3, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPUassert: %s %s %dn"
.size .L.str.4, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5solvePA100_d"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__solvePA100_d
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5solvePA100_d
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5solvePA100_d
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R0 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GT.AND P0, PT, R5, 0x62, PT ; /* 0x000000620500780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GT.OR P0, PT, R2, 0x62, P0 ; /* 0x000000620200780c */
/* 0x000fc80000704670 */
/*0090*/ ISETP.EQ.OR P0, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */
/* 0x000fc80000702670 */
/*00a0*/ ISETP.EQ.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000702670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x320 ; /* 0x00000320ff037424 */
/* 0x000fe200078e00ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00e0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*00f0*/ IMAD.WIDE R2, R5, 0x8, R2 ; /* 0x0000000805027825 */
/* 0x000fca00078e0202 */
/*0100*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1b00 */
/*0110*/ MUFU.RCP64H R7, 100 ; /* 0x4059000000077908 */
/* 0x000e220000001800 */
/*0120*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe200078e00ff */
/*0130*/ BSSY B0, 0x2c0 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*0140*/ IMAD.MOV.U32 R11, RZ, RZ, 0x40590000 ; /* 0x40590000ff0b7424 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fcc00078e00ff */
/*0160*/ DFMA R8, R6, -R10, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c000000080a */
/*0170*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0180*/ DFMA R6, R6, R8, R6 ; /* 0x000000080606722b */
/* 0x001e0c0000000006 */
/*0190*/ DFMA R10, R6, -R10, 1 ; /* 0x3ff00000060a742b */
/* 0x001e0c000000080a */
/*01a0*/ DFMA R6, R6, R10, R6 ; /* 0x0000000a0606722b */
/* 0x001fc80000000006 */
/*01b0*/ DMUL R8, R4, c[0x2][0x0] ; /* 0x0080000004087a28 */
/* 0x004e0c0000000000 */
/*01c0*/ DMUL R10, R8, R6 ; /* 0x00000006080a7228 */
/* 0x001e080000000000 */
/*01d0*/ FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT ; /* 0x036000000900780b */
/* 0x000fe40003f2e200 */
/*01e0*/ DFMA R12, R10, -100, R8 ; /* 0xc05900000a0c782b */
/* 0x001e0c0000000008 */
/*01f0*/ DFMA R6, R6, R12, R10 ; /* 0x0000000c0606722b */
/* 0x001e14000000000a */
/*0200*/ FFMA R0, RZ, 3.390625, R7 ; /* 0x40590000ff007823 */
/* 0x001fca0000000007 */
/*0210*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0220*/ @P0 BRA P1, 0x2b0 ; /* 0x0000008000000947 */
/* 0x000fea0000800000 */
/*0230*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*0240*/ MOV R0, 0x290 ; /* 0x0000029000007802 */
/* 0x000fe20000000f00 */
/*0250*/ IMAD.MOV.U32 R13, RZ, RZ, R9 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0009 */
/*0260*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*0270*/ IMAD.MOV.U32 R11, RZ, RZ, 0x40590000 ; /* 0x40590000ff0b7424 */
/* 0x000fe400078e00ff */
/*0280*/ CALL.REL.NOINC 0x530 ; /* 0x000002a000007944 */
/* 0x000fea0003c00000 */
/*0290*/ IMAD.MOV.U32 R6, RZ, RZ, R16 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0010 */
/*02a0*/ IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0011 */
/*02b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02c0*/ LDG.E.64 R10, [R2.64+0x320] ; /* 0x00032004020a7981 */
/* 0x000ea8000c1e1b00 */
/*02d0*/ LDG.E.64 R12, [R2.64+-0x320] ; /* 0xfffce004020c7981 */
/* 0x000ea8000c1e1b00 */
/*02e0*/ LDG.E.64 R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x000ee8000c1e1b00 */
/*02f0*/ LDG.E.64 R16, [R2.64+-0x8] ; /* 0xfffff80402107981 */
/* 0x000f22000c1e1b00 */
/*0300*/ MUFU.RCP64H R19, 100 ; /* 0x4059000000137908 */
/* 0x000e220000001800 */
/*0310*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x000fe200078e00ff */
/*0320*/ BSSY B0, 0x500 ; /* 0x000001d000007945 */
/* 0x000fe20003800000 */
/*0330*/ IMAD.MOV.U32 R9, RZ, RZ, 0x40590000 ; /* 0x40590000ff097424 */
/* 0x000fc400078e00ff */
/*0340*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fe200078e00ff */
/*0350*/ DADD R10, R10, R12 ; /* 0x000000000a0a7229 */
/* 0x004eca000000000c */
/*0360*/ DFMA R12, R18, -R8, 1 ; /* 0x3ff00000120c742b */
/* 0x001e080000000808 */
/*0370*/ DADD R10, R10, R14 ; /* 0x000000000a0a7229 */
/* 0x008f08000000000e */
/*0380*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e08000000000c */
/*0390*/ DADD R10, R10, R16 ; /* 0x000000000a0a7229 */
/* 0x010e480000000010 */
/*03a0*/ DFMA R12, R18, R12, R18 ; /* 0x0000000c120c722b */
/* 0x001e080000000012 */
/*03b0*/ DFMA R10, R4, -4, R10 ; /* 0xc0100000040a782b */
/* 0x002e48000000000a */
/*03c0*/ DFMA R8, R12, -R8, 1 ; /* 0x3ff000000c08742b */
/* 0x001e080000000808 */
/*03d0*/ DMUL R10, R10, 10 ; /* 0x402400000a0a7828 */
/* 0x002e480000000000 */
/*03e0*/ DFMA R12, R12, R8, R12 ; /* 0x000000080c0c722b */
/* 0x001fc8000000000c */
/*03f0*/ DMUL R10, R10, c[0x2][0x8] ; /* 0x008002000a0a7a28 */
/* 0x002e0c0000000000 */
/*0400*/ DMUL R4, R12, R10 ; /* 0x0000000a0c047228 */
/* 0x001e080000000000 */
/*0410*/ FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; /* 0x036000000b00780b */
/* 0x000fe40003f2e200 */
/*0420*/ DFMA R8, R4, -100, R10 ; /* 0xc05900000408782b */
/* 0x001e0c000000000a */
/*0430*/ DFMA R4, R12, R8, R4 ; /* 0x000000080c04722b */
/* 0x001e140000000004 */
/*0440*/ FFMA R0, RZ, 3.390625, R5 ; /* 0x40590000ff007823 */
/* 0x001fca0000000005 */
/*0450*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0460*/ @P0 BRA P1, 0x4f0 ; /* 0x0000008000000947 */
/* 0x000fea0000800000 */
/*0470*/ IMAD.MOV.U32 R12, RZ, RZ, R10 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e000a */
/*0480*/ MOV R0, 0x4d0 ; /* 0x000004d000007802 */
/* 0x000fe20000000f00 */
/*0490*/ IMAD.MOV.U32 R13, RZ, RZ, R11 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e000b */
/*04a0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*04b0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x40590000 ; /* 0x40590000ff0b7424 */
/* 0x000fe400078e00ff */
/*04c0*/ CALL.REL.NOINC 0x530 ; /* 0x0000006000007944 */
/* 0x000fea0003c00000 */
/*04d0*/ IMAD.MOV.U32 R4, RZ, RZ, R16 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0010 */
/*04e0*/ IMAD.MOV.U32 R5, RZ, RZ, R17 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0011 */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ DADD R4, R4, R6 ; /* 0x0000000004047229 */
/* 0x000e0e0000000006 */
/*0510*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ FSETP.GEU.AND P0, PT, |R11|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x040fe20003f0e200 */
/*0540*/ IMAD.MOV.U32 R17, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff117424 */
/* 0x000fe200078e00ff */
/*0550*/ LOP3.LUT R8, R11, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff0b087812 */
/* 0x000fe200078ec0ff */
/*0560*/ IMAD.MOV.U32 R20, RZ, RZ, 0x1 ; /* 0x00000001ff147424 */
/* 0x000fe200078e00ff */
/*0570*/ FSETP.GEU.AND P2, PT, |R13|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x040fe20003f4e200 */
/*0580*/ IMAD.MOV.U32 R14, RZ, RZ, R12 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e000c */
/*0590*/ LOP3.LUT R9, R8, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000008097812 */
/* 0x000fe200078efcff */
/*05a0*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000a */
/*05b0*/ LOP3.LUT R16, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d107812 */
/* 0x000fe200078ec0ff */
/*05c0*/ BSSY B1, 0xad0 ; /* 0x0000050000017945 */
/* 0x000fe20003800000 */
/*05d0*/ LOP3.LUT R23, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b177812 */
/* 0x000fc600078ec0ff */
/*05e0*/ @!P0 DMUL R8, R10, 8.98846567431157953865e+307 ; /* 0x7fe000000a088828 */
/* 0x000e220000000000 */
/*05f0*/ ISETP.GE.U32.AND P1, PT, R16, R23, PT ; /* 0x000000171000720c */
/* 0x000fc60003f26070 */
/*0600*/ @!P2 LOP3.LUT R15, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0fa812 */
/* 0x000fe200078ec0ff */
/*0610*/ @!P2 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff12a224 */
/* 0x000fe200078e00ff */
/*0620*/ MUFU.RCP64H R21, R9 ; /* 0x0000000900157308 */
/* 0x001e240000001800 */
/*0630*/ @!P2 ISETP.GE.U32.AND P3, PT, R16, R15, PT ; /* 0x0000000f1000a20c */
/* 0x000fe40003f66070 */
/*0640*/ SEL R15, R17.reuse, 0x63400000, !P1 ; /* 0x63400000110f7807 */
/* 0x040fe40004800000 */
/*0650*/ @!P2 SEL R19, R17, 0x63400000, !P3 ; /* 0x634000001113a807 */
/* 0x000fe40005800000 */
/*0660*/ LOP3.LUT R15, R15, 0x800fffff, R13, 0xf8, !PT ; /* 0x800fffff0f0f7812 */
/* 0x000fc400078ef80d */
/*0670*/ @!P2 LOP3.LUT R19, R19, 0x80000000, R13, 0xf8, !PT ; /* 0x800000001313a812 */
/* 0x000fc800078ef80d */
/*0680*/ @!P2 LOP3.LUT R19, R19, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001313a812 */
/* 0x000fe200078efcff */
/*0690*/ DFMA R24, R20, -R8, 1 ; /* 0x3ff000001418742b */
/* 0x001e0a0000000808 */
/*06a0*/ @!P2 DFMA R14, R14, 2, -R18 ; /* 0x400000000e0ea82b */
/* 0x000fc80000000812 */
/*06b0*/ DFMA R24, R24, R24, R24 ; /* 0x000000181818722b */
/* 0x001e0c0000000018 */
/*06c0*/ DFMA R24, R20, R24, R20 ; /* 0x000000181418722b */
/* 0x0010640000000014 */
/*06d0*/ IMAD.MOV.U32 R20, RZ, RZ, R16 ; /* 0x000000ffff147224 */
/* 0x001fe200078e0010 */
/*06e0*/ @!P2 LOP3.LUT R20, R15, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000f14a812 */
/* 0x000fe200078ec0ff */
/*06f0*/ IMAD.MOV.U32 R21, RZ, RZ, R23 ; /* 0x000000ffff157224 */
/* 0x000fe200078e0017 */
/*0700*/ @!P0 LOP3.LUT R21, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009158812 */
/* 0x000fe200078ec0ff */
/*0710*/ DFMA R18, R24, -R8, 1 ; /* 0x3ff000001812742b */
/* 0x002e060000000808 */
/*0720*/ IADD3 R26, R21, -0x1, RZ ; /* 0xffffffff151a7810 */
/* 0x000fc60007ffe0ff */
/*0730*/ DFMA R18, R24, R18, R24 ; /* 0x000000121812722b */
/* 0x0010640000000018 */
/*0740*/ IADD3 R24, R20, -0x1, RZ ; /* 0xffffffff14187810 */
/* 0x001fc80007ffe0ff */
/*0750*/ ISETP.GT.U32.AND P0, PT, R24, 0x7feffffe, PT ; /* 0x7feffffe1800780c */
/* 0x000fe20003f04070 */
/*0760*/ DMUL R22, R18, R14 ; /* 0x0000000e12167228 */
/* 0x002e060000000000 */
/*0770*/ ISETP.GT.U32.OR P0, PT, R26, 0x7feffffe, P0 ; /* 0x7feffffe1a00780c */
/* 0x000fc60000704470 */
/*0780*/ DFMA R24, R22, -R8, R14 ; /* 0x800000081618722b */
/* 0x001e0c000000000e */
/*0790*/ DFMA R18, R18, R24, R22 ; /* 0x000000181212722b */
/* 0x0010480000000016 */
/*07a0*/ @P0 BRA 0x970 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*07b0*/ LOP3.LUT R13, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0d7812 */
/* 0x003fe200078ec0ff */
/*07c0*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fc600078e00ff */
/*07d0*/ ISETP.GE.U32.AND P0, PT, R16.reuse, R13, PT ; /* 0x0000000d1000720c */
/* 0x040fe20003f06070 */
/*07e0*/ IMAD.IADD R12, R16, 0x1, -R13 ; /* 0x00000001100c7824 */
/* 0x000fc600078e0a0d */
/*07f0*/ SEL R17, R17, 0x63400000, !P0 ; /* 0x6340000011117807 */
/* 0x000fe40004000000 */
/*0800*/ IMNMX R12, R12, -0x46a00000, !PT ; /* 0xb96000000c0c7817 */
/* 0x000fc80007800200 */
/*0810*/ IMNMX R12, R12, 0x46a00000, PT ; /* 0x46a000000c0c7817 */
/* 0x000fca0003800200 */
/*0820*/ IMAD.IADD R12, R12, 0x1, -R17 ; /* 0x000000010c0c7824 */
/* 0x000fca00078e0a11 */
/*0830*/ IADD3 R21, R12, 0x7fe00000, RZ ; /* 0x7fe000000c157810 */
/* 0x000fcc0007ffe0ff */
/*0840*/ DMUL R16, R18, R20 ; /* 0x0000001412107228 */
/* 0x000e140000000000 */
/*0850*/ FSETP.GTU.AND P0, PT, |R17|, 1.469367938527859385e-39, PT ; /* 0x001000001100780b */
/* 0x001fda0003f0c200 */
/*0860*/ @P0 BRA 0xac0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0870*/ DFMA R8, R18, -R8, R14 ; /* 0x800000081208722b */
/* 0x000e22000000000e */
/*0880*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fd200078e00ff */
/*0890*/ FSETP.NEU.AND P0, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720b */
/* 0x041fe40003f0d000 */
/*08a0*/ LOP3.LUT R11, R9, 0x80000000, R11, 0x48, !PT ; /* 0x80000000090b7812 */
/* 0x000fc800078e480b */
/*08b0*/ LOP3.LUT R21, R11, R21, RZ, 0xfc, !PT ; /* 0x000000150b157212 */
/* 0x000fce00078efcff */
/*08c0*/ @!P0 BRA 0xac0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*08d0*/ IMAD.MOV R9, RZ, RZ, -R12 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a0c */
/*08e0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fcc00078e00ff */
/*08f0*/ DFMA R8, R16, -R8, R18 ; /* 0x800000081008722b */
/* 0x000e080000000012 */
/*0900*/ DMUL.RP R18, R18, R20 ; /* 0x0000001412127228 */
/* 0x000e640000008000 */
/*0910*/ IADD3 R8, -R12, -0x43300000, RZ ; /* 0xbcd000000c087810 */
/* 0x001fc80007ffe1ff */
/*0920*/ FSETP.NEU.AND P0, PT, |R9|, R8, PT ; /* 0x000000080900720b */
/* 0x000fc80003f0d200 */
/*0930*/ LOP3.LUT R11, R19, R11, RZ, 0x3c, !PT ; /* 0x0000000b130b7212 */
/* 0x002fe400078e3cff */
/*0940*/ FSEL R16, R18, R16, !P0 ; /* 0x0000001012107208 */
/* 0x000fe40004000000 */
/*0950*/ FSEL R17, R11, R17, !P0 ; /* 0x000000110b117208 */
/* 0x000fe20004000000 */
/*0960*/ BRA 0xac0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0970*/ DSETP.NAN.AND P0, PT, R12, R12, PT ; /* 0x0000000c0c00722a */
/* 0x003e1c0003f08000 */
/*0980*/ @P0 BRA 0xaa0 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0990*/ DSETP.NAN.AND P0, PT, R10, R10, PT ; /* 0x0000000a0a00722a */
/* 0x000e1c0003f08000 */
/*09a0*/ @P0 BRA 0xa70 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*09b0*/ ISETP.NE.AND P0, PT, R20, R21, PT ; /* 0x000000151400720c */
/* 0x000fe20003f05270 */
/*09c0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x0 ; /* 0x00000000ff107424 */
/* 0x000fe400078e00ff */
/*09d0*/ IMAD.MOV.U32 R17, RZ, RZ, -0x80000 ; /* 0xfff80000ff117424 */
/* 0x000fd400078e00ff */
/*09e0*/ @!P0 BRA 0xac0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*09f0*/ ISETP.NE.AND P0, PT, R20, 0x7ff00000, PT ; /* 0x7ff000001400780c */
/* 0x000fe40003f05270 */
/*0a00*/ LOP3.LUT R17, R13, 0x80000000, R11, 0x48, !PT ; /* 0x800000000d117812 */
/* 0x000fe400078e480b */
/*0a10*/ ISETP.EQ.OR P0, PT, R21, RZ, !P0 ; /* 0x000000ff1500720c */
/* 0x000fda0004702670 */
/*0a20*/ @P0 LOP3.LUT R8, R17, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000011080812 */
/* 0x000fe200078efcff */
/*0a30*/ @!P0 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff108224 */
/* 0x000fe400078e00ff */
/*0a40*/ @P0 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff100224 */
/* 0x000fe400078e00ff */
/*0a50*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, R8 ; /* 0x000000ffff110224 */
/* 0x000fe200078e0008 */
/*0a60*/ BRA 0xac0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0a70*/ LOP3.LUT R17, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b117812 */
/* 0x000fe200078efcff */
/*0a80*/ IMAD.MOV.U32 R16, RZ, RZ, R10 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000a */
/*0a90*/ BRA 0xac0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0aa0*/ LOP3.LUT R17, R13, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000d117812 */
/* 0x000fe200078efcff */
/*0ab0*/ IMAD.MOV.U32 R16, RZ, RZ, R12 ; /* 0x000000ffff107224 */
/* 0x000fe400078e000c */
/*0ac0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ad0*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0000 */
/*0ae0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fc800078e00ff */
/*0af0*/ RET.REL.NODEC R8 0x0 ; /* 0xfffff50008007950 */
/* 0x000fea0003c3ffff */
/*0b00*/ BRA 0xb00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5solvePA100_d
.globl _Z5solvePA100_d
.p2align 8
.type _Z5solvePA100_d,@function
_Z5solvePA100_d:
s_load_b32 s2, s[0:1], 0x14
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_ne_u32_e32 vcc_lo, 0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_max_i32_e32 v2, v0, v1
v_cmp_ne_u32_e64 s2, 0, v1
v_cmp_gt_i32_e64 s3, 0x63, v2
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s3, 0x3f847ae1
s_mov_b32 s2, 0x47ae147b
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[3:4], null, v0, 0x320, s[0:1]
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_mov_b32 s1, 0x3fefdf3b
s_mov_b32 s0, 0x645a1cac
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, v3, v0
v_add_co_ci_u32_e32 v6, vcc_lo, v4, v1, vcc_lo
s_clause 0x3
global_load_b64 v[7:8], v[5:6], off offset:800
global_load_b64 v[9:10], v[5:6], off offset:-800
global_load_b128 v[0:3], v[5:6], off
global_load_b64 v[11:12], v[5:6], off offset:-8
s_waitcnt vmcnt(2)
v_add_f64 v[7:8], v[9:10], v[7:8]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[7:8], v[2:3]
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[2:3], v[0:1], -4.0, v[2:3]
v_mul_f64 v[0:1], v[0:1], s[0:1]
v_mul_f64 v[2:3], v[2:3], 0x40240000
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_scale_f64 v[7:8], null, 0x40590000, 0x40590000, v[0:1]
v_div_scale_f64 v[19:20], vcc_lo, v[0:1], 0x40590000, v[0:1]
v_mul_f64 v[2:3], v[2:3], s[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[11:12], v[7:8]
v_div_scale_f64 v[9:10], null, 0x40590000, 0x40590000, v[2:3]
s_waitcnt_depctr 0xfff
v_fma_f64 v[15:16], -v[7:8], v[11:12], 1.0
v_rcp_f64_e32 v[13:14], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f64 v[11:12], v[11:12], v[15:16], v[11:12]
s_waitcnt_depctr 0xfff
v_fma_f64 v[17:18], -v[9:10], v[13:14], 1.0
v_fma_f64 v[15:16], -v[7:8], v[11:12], 1.0
v_fma_f64 v[13:14], v[13:14], v[17:18], v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[11:12], v[11:12], v[15:16], v[11:12]
v_div_scale_f64 v[15:16], s0, v[2:3], 0x40590000, v[2:3]
v_fma_f64 v[17:18], -v[9:10], v[13:14], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[13:14], v[13:14], v[17:18], v[13:14]
v_mul_f64 v[17:18], v[19:20], v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[21:22], v[15:16], v[13:14]
v_fma_f64 v[7:8], -v[7:8], v[17:18], v[19:20]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[9:10], -v[9:10], v[21:22], v[15:16]
v_div_fmas_f64 v[7:8], v[7:8], v[11:12], v[17:18]
s_mov_b32 vcc_lo, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[9:10], v[9:10], v[13:14], v[21:22]
v_div_fixup_f64 v[0:1], v[7:8], 0x40590000, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[2:3], v[9:10], 0x40590000, v[2:3]
v_add_f64 v[0:1], v[0:1], v[2:3]
global_store_b64 v[5:6], v[0:1], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5solvePA100_d
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5solvePA100_d, .Lfunc_end0-_Z5solvePA100_d
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5solvePA100_d
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5solvePA100_d.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e84fe_00000000-6_nvidiatest.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15my_gettimeofdayv
.type _Z15my_gettimeofdayv, @function
_Z15my_gettimeofdayv:
.LFB3669:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
fildq 24(%rsp)
fldt .LC0(%rip)
fmulp %st, %st(1)
fildq 16(%rsp)
faddp %st, %st(1)
fstpl 8(%rsp)
movsd 8(%rsp), %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z15my_gettimeofdayv, .-_Z15my_gettimeofdayv
.globl _Z6iDivUpii
.type _Z6iDivUpii, @function
_Z6iDivUpii:
.LFB3671:
.cfi_startproc
endbr64
movl %edi, %eax
cltd
idivl %esi
testl %edx, %edx
je .L8
movl %edi, %eax
cltd
idivl %esi
addl $1, %eax
ret
.L8:
movl %edi, %eax
cltd
idivl %esi
ret
.cfi_endproc
.LFE3671:
.size _Z6iDivUpii, .-_Z6iDivUpii
.globl _Z29__device_stub__Z5solvePA100_dPA100_d
.type _Z29__device_stub__Z5solvePA100_dPA100_d, @function
_Z29__device_stub__Z5solvePA100_dPA100_d:
.LFB3697:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5solvePA100_d(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z29__device_stub__Z5solvePA100_dPA100_d, .-_Z29__device_stub__Z5solvePA100_dPA100_d
.globl _Z5solvePA100_d
.type _Z5solvePA100_d, @function
_Z5solvePA100_d:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5solvePA100_dPA100_d
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z5solvePA100_d, .-_Z5solvePA100_d
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Adahn/Project-CUBIOSIM/master/fdm/nvidiatest.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "GPUassert: %s %s %dn"
.LC6:
.string "Transfert CPU vers GPU :"
.LC7:
.string "Transfert GPU vers CPU :"
.LC8:
.string "Temps calcul :"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq -159744(%rsp), %r11
.cfi_def_cfa 11, 159760
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $352, %rsp
.cfi_def_cfa_offset 160112
movq %fs:40, %rax
movq %rax, 160088(%rsp)
xorl %eax, %eax
leaq 880(%rsp), %rdx
leaq 80880(%rsp), %rcx
.L19:
leaq -800(%rdx), %rax
.L20:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L20
addq $800, %rdx
cmpq %rcx, %rdx
jne .L19
movsd .LC3(%rip), %xmm0
movsd %xmm0, 39672(%rsp)
movsd %xmm0, 40472(%rsp)
movsd %xmm0, 40480(%rsp)
movsd %xmm0, 39680(%rsp)
leaq 40(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
call _Z15my_gettimeofdayv
movsd %xmm0, 16(%rsp)
call _Z15my_gettimeofdayv
movsd %xmm0, 24(%rsp)
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $80000, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L29
call _Z15my_gettimeofdayv
movsd %xmm0, 8(%rsp)
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
subsd 24(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $4, 56(%rsp)
movl $4, 60(%rsp)
movl $1, 64(%rsp)
movl $32, 68(%rsp)
movl $32, 72(%rsp)
movl $1, 76(%rsp)
movl $1000, %ebx
jmp .L24
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $88, %r9d
leaq .LC4(%rip), %r8
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L23:
subl $1, %ebx
je .L30
.L24:
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L23
movq 40(%rsp), %rdi
call _Z29__device_stub__Z5solvePA100_dPA100_d
jmp .L23
.L30:
call _Z15my_gettimeofdayv
movsd %xmm0, 24(%rsp)
leaq 80080(%rsp), %rdi
movl $2, %ecx
movl $80000, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm1
subsd 24(%rsp), %xmm1
movapd %xmm1, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call _Z15my_gettimeofdayv
call _Z15my_gettimeofdayv
movsd %xmm0, 8(%rsp)
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
subsd 16(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 160088(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $160096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z5solvePA100_d"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z5solvePA100_d(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC0:
.long -1351849546
.long -2043167483
.long 16363
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long -1610612736
.long 1071225241
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "nvidiatest.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z15my_gettimeofdayv
.LCPI0_0:
.quad 0x8637bd05af6c69b6 # x86_fp80 1.00000000000000000004E-6
.short 0x3feb
.zero 6
.text
.globl _Z15my_gettimeofdayv
.p2align 4, 0x90
.type _Z15my_gettimeofdayv,@function
_Z15my_gettimeofdayv: # @_Z15my_gettimeofdayv
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq 24(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 24(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 8(%rsp)
fildll 8(%rsp)
movq %rcx, 16(%rsp)
fildll 16(%rsp)
fldt .LCPI0_0(%rip)
fmulp %st, %st(1)
faddp %st, %st(1)
fstpl (%rsp)
movsd (%rsp), %xmm0 # xmm0 = mem[0],zero
addq $40, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z15my_gettimeofdayv, .Lfunc_end0-_Z15my_gettimeofdayv
.cfi_endproc
# -- End function
.globl _Z6iDivUpii # -- Begin function _Z6iDivUpii
.p2align 4, 0x90
.type _Z6iDivUpii,@function
_Z6iDivUpii: # @_Z6iDivUpii
.cfi_startproc
# %bb.0:
movl %edi, %eax
cltd
idivl %esi
cmpl $1, %edx
sbbl $-1, %eax
retq
.Lfunc_end1:
.size _Z6iDivUpii, .Lfunc_end1-_Z6iDivUpii
.cfi_endproc
# -- End function
.globl _Z20__device_stub__solvePA100_d # -- Begin function _Z20__device_stub__solvePA100_d
.p2align 4, 0x90
.type _Z20__device_stub__solvePA100_d,@function
_Z20__device_stub__solvePA100_d: # @_Z20__device_stub__solvePA100_d
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z5solvePA100_d, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z20__device_stub__solvePA100_d, .Lfunc_end2-_Z20__device_stub__solvePA100_d
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x8637bd05af6c69b6 # x86_fp80 1.00000000000000000004E-6
.short 0x3feb
.zero 6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $160232, %rsp # imm = 0x271E8
.cfi_def_cfa_offset 160288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 80224(%rsp), %rbx
movl $80000, %edx # imm = 0x13880
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movabsq $4600877379429072896, %rax # imm = 0x3FD99999A0000000
movq %rax, 119816(%rsp)
movq %rax, 120616(%rsp)
movq %rax, 120624(%rsp)
movq %rax, 119824(%rsp)
leaq 16(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
leaq 216(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
leaq 224(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 224(%rsp), %rax
movq 232(%rsp), %rcx
movq %rax, 176(%rsp)
fildll 176(%rsp)
movq %rcx, 184(%rsp)
fildll 184(%rsp)
fldt .LCPI3_0(%rip)
fld %st(0)
fstpt (%rsp) # 10-byte Folded Spill
fmulp %st, %st(1)
faddp %st, %st(1)
fstpl 168(%rsp)
movsd 168(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 64(%rsp) # 8-byte Spill
leaq 224(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 224(%rsp), %r14
movq 232(%rsp), %r15
movq 16(%rsp), %rdi
movl $80000, %edx # imm = 0x13880
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_18
# %bb.1: # %_Z9gpuAssert10hipError_tPcib.exit
movq %r15, 136(%rsp)
fildll 136(%rsp)
fldt (%rsp) # 10-byte Folded Reload
fmulp %st, %st(1)
movq %r14, 144(%rsp)
fildll 144(%rsp)
faddp %st, %st(1)
fstpl 128(%rsp)
leaq 224(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 224(%rsp), %rax
movq 232(%rsp), %rcx
movq %rax, 152(%rsp)
fildll 152(%rsp)
movq %rcx, 160(%rsp)
fildll 160(%rsp)
fldt (%rsp) # 10-byte Folded Reload
fmulp %st, %st(1)
faddp %st, %st(1)
fstpl 120(%rsp)
movsd 120(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 40(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 128(%rsp), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_19
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_4
# %bb.3:
movzbl 67(%rbx), %ecx
jmp .LBB3_5
.LBB3_4:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $1000, %r12d # imm = 0x3E8
movabsq $17179869188, %rbx # imm = 0x400000004
movabsq $137438953504, %r14 # imm = 0x2000000020
leaq 200(%rsp), %r13
leaq 192(%rsp), %rbp
leaq 48(%rsp), %r15
jmp .LBB3_6
.p2align 4, 0x90
.LBB3_8: # in Loop: Header=BB3_6 Depth=1
decl %r12d
je .LBB3_9
.LBB3_6: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7: # in Loop: Header=BB3_6 Depth=1
movq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 208(%rsp), %rax
movq %rax, 48(%rsp)
leaq 224(%rsp), %rdi
leaq 24(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 224(%rsp), %rsi
movl 232(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z5solvePA100_d, %edi
movq %r15, %r9
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
pushq 208(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_8
.LBB3_9:
leaq 224(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 224(%rsp), %rax
movq 232(%rsp), %rcx
movq %rax, 104(%rsp)
fildll 104(%rsp)
movq %rcx, 112(%rsp)
fildll 112(%rsp)
fldt (%rsp) # 10-byte Folded Reload
fmulp %st, %st(1)
faddp %st, %st(1)
fstpl 96(%rsp)
movq 16(%rsp), %rsi
leaq 224(%rsp), %rdi
movl $80000, %edx # imm = 0x13880
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 96(%rsp), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_19
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i27
cmpb $0, 56(%rbx)
je .LBB3_12
# %bb.11:
movzbl 67(%rbx), %ecx
jmp .LBB3_13
.LBB3_12:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit30
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 24(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
leaq 24(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 24(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 80(%rsp)
fildll 80(%rsp)
movq %rcx, 88(%rsp)
fildll 88(%rsp)
fldt (%rsp) # 10-byte Folded Reload
fmulp %st, %st(1)
faddp %st, %st(1)
fstpl 72(%rsp)
movsd 72(%rsp), %xmm0 # xmm0 = mem[0],zero
subsd 64(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_19
# %bb.14: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i32
cmpb $0, 56(%rbx)
je .LBB3_16
# %bb.15:
movzbl 67(%rbx), %ecx
jmp .LBB3_17
.LBB3_16:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit35
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $160232, %rsp # imm = 0x271E8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_19:
.cfi_def_cfa_offset 160288
callq _ZSt16__throw_bad_castv
.LBB3_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $88, %r8d
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5solvePA100_d, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5solvePA100_d,@object # @_Z5solvePA100_d
.section .rodata,"a",@progbits
.globl _Z5solvePA100_d
.p2align 3, 0x0
_Z5solvePA100_d:
.quad _Z20__device_stub__solvePA100_d
.size _Z5solvePA100_d, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Adahn/Project-CUBIOSIM/master/fdm/nvidiatest.hip"
.size .L.str, 106
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Transfert CPU vers GPU :"
.size .L.str.1, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Transfert GPU vers CPU :"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Temps calcul :"
.size .L.str.3, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPUassert: %s %s %dn"
.size .L.str.4, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5solvePA100_d"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__solvePA100_d
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5solvePA100_d
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //////////////////////////////////////////////////////////////////////////
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Author: M. Winters (2016)
// Institution: Chalmers Universtiy of Technology (MC2)
// email: mesoic@protonmail.com
//
//////////////////////////////////////////////////////////////////////////
//
// Graphene CV Modeling Kernel
//
// Compile with: nvcc -c -arch=sm_20 <filename>.cu
//
// Compilation will create CV_kernel.cubin which provides the
// functions below. The .cubin can then be imported into
// Python(PyCUDA) or C/C++ code.
//
//////////////////////////////////////////////////////////////////////////
//
// This kernel provides GPU methods to calculate the monolayer and bilayer
// DOS, eF, Capacitance, and other related quantities. Dit and surface
// potential fluctuations are also included.
//
// Characterization and physical modeling of MOS capacitors in epitaxial
// graphene monolayers and bilayers on 6H-SiC
//
// AIP Advances 6, 085010 (2016); https://doi.org/10.1063/1.4961361
//
#include <stdio.h>
#include <curand.h>
#include <curand_kernel.h>
#include <math.h>
///////////////////////
// CONSTANTS //
///////////////////////
__device__ __constant__ float PI = 3.141592654f;
__device__ __constant__ float HB = 6.58211e-16f;
__device__ __constant__ float KB = 8.617332e-5f;
__device__ __constant__ float VF = 1.000000e+8f;
__device__ __constant__ float G = 0.400f;
__device__ __constant__ float GS = 4.000f;
__device__ __constant__ float e = 1.602e-19f;
__device__ __constant__ float R = 1.414213562f;
//////////////////////////////////
// ATOMIC OPERATIONS //
//////////////////////////////////
extern "C" {
__device__ void addToC(float *r, float* rx, float* a, float n, int INT) {
for (int i=0; i<INT;i ++){
atomicAdd(&r[i], rx[i] + n*a[i]);
}
}
}
//////////////////////////////////////////
// CALCULATION OF DOS/CARRIERS //
//////////////////////////////////////////
// Monolayer
extern "C"{
__device__ float mlDOS_PW(float eF){
return (GS/(2.0*PI))*(1.0/(HB*HB*VF*VF))*abs(eF);
}
}
extern "C" {
__device__ float mlCarriers_PW(float ef, float T){
int INT = 1024;
float n = 0.0;
float p = 0.0;
for(int i = 0; i<INT; i++){
n += mlDOS_PW(float(i)/float(INT))*(1.0/(1.0 + exp( ((float(i)/float(INT)) -ef )/(KB*T))))*(1.0/INT);
p += mlDOS_PW(float(i)/float(INT))*(1.0/(1.0 + exp( ef + (float(i)/float(INT)) )/(KB*T)))*(1.0/INT);
}
return n-p;
}
}
// Bilayer. DOS includes energy gap model
extern "C" {
__device__ float blDOS_PW(float eF, float eG, float eGs){
if (eG < 0.0){ return (GS/(2.0*PI))*(1.0/(HB*HB*VF*VF))*(abs(eF) + (G/2.0));}
double dFp;
double dFm;
dFp = float( 0.5* (1 - erf ( double( (eF+eG)/(R*eGs) ) )));
dFm = 1.0 - float( 0.5* (1 - erf ( double ( (eF-eG)/(R*eGs) ) )));
return (float(dFm)+float(dFp)) * (GS/(2.0*PI)) * (1.0/(HB*HB*VF*VF))*(abs(eF) + (G/2.0));
}
}
extern "C" {
__device__ float blCarriers_PW(float ef, float eG, float eGs, float T){
int INT = 1024;
float n = 0.0;
float p = 0.0;
for(int i = 0; i<INT; i++){
n += blDOS_PW(float(i)/float(INT), eG, eGs) * (1.0/(1.0 + exp(( (float(i)/float(INT)) -ef )/(KB*T))))*(1.0/INT);
p += blDOS_PW(float(i)/float(INT), eG, eGs) * (1.0/(1.0 + exp(( ef + (float(i)/float(INT)) )/(KB*T))))*(1.0/INT);
}
return n-p;
}
}
//////////////////////////////////////////////////
// MONTE CARLO SIMULATION of CAPACITANCE //
//////////////////////////////////////////////////
extern "C" {
__global__ void gen_rand(float* eF, float* eFr, float deF, unsigned long SEED){
const int tid = threadIdx.x;
curandState state;
curand_init(SEED, tid, 0, &state);
eF[tid] = eF[tid];
eFr[tid] = deF*curand_normal(&state) + eF[tid];
}
}
extern "C" {
__global__ void gen_capMC(float* eF, float* eFr, float* eG, float* deF, float* Dit,
float*C, float COX, float M, int DEPTH, unsigned long SEED){
const int tid = threadIdx.x;
curandState state;
curand_init(SEED, tid, 0, &state);
float num;
float den;
for (int i = 0; i<DEPTH; i++){
eFr[tid] = deF[0]*( exp(-1* (eF[tid]*eF[tid])/(2*deF[1]*deF[1])) )*curand_normal(&state) + eF[tid];
num = (e*COX * ( M*mlDOS_PW(eFr[tid]) + (1.0-M)*blDOS_PW(eFr[tid], eG[0], eG[1]) + Dit[tid]));
den = (COX + e*M*mlDOS_PW(eFr[tid]) + e*(1.0-M)*blDOS_PW(eFr[tid], eG[0], eG[1]) + e*Dit[tid]);
C[tid] += num/den;
}
C[tid] = C[tid]/float(DEPTH);
}
}
///////////////////////////////////////////
// NEWTONS METHOD //
///////////////////////////////////////////
extern "C"{
__device__ float integrate(int v_i, int vD_i, float* Dit, float DELTA){
float _int = 0;
// Some bad coding to take care of return sweep
if (v_i == 200){
v_i = 0;
}
if (v_i > 100){
v_i -= 2*(v_i%100);
}
// Otherwise just integrate like normal
if (v_i < vD_i){
for(int i = v_i; i < vD_i; i++){
_int += Dit[i]*DELTA ;
}
}
else{
for(int i = vD_i; i < v_i; i++){
_int -= Dit[i]*DELTA ;
}
}
return _int;
}
}
extern "C"{
__global__ void solve_eF(float* v, float* vD, float* Dit, float* eF, float* eG,
float COX, float T, float M, float FLYWHEEL){
const int tid = threadIdx.x;
const float DELTA = v[1]-v[0];
float lhs = v[tid] - vD[0] - ((e/COX)*integrate(tid, int(vD[1]), Dit, DELTA));
float rhs = ( eF[tid] + M*(e/COX)*mlCarriers_PW(eF[tid], T) + (1-M)*(e/COX)*blCarriers_PW(eF[tid], eG[0], eG[1], T) );
float dhs;
if (tid == int(vD[1])){
eF[tid] = 0.0;
return;
}
if (tid - 2*(tid%100) == int(vD[1])){
eF[tid] = 0.0;
return;
}
for (int i = 0; i < 100; i++){
float conv = (lhs - rhs);
if (abs(conv) < 1e-6){
return;
}
else{
rhs = ( eF[tid] + M*(e/COX)*mlCarriers_PW(eF[tid], T) + (1-M)*(e/COX)*blCarriers_PW(eF[tid], eG[0], eG[1], T) );
dhs = ( 1 + M*(e/COX)*mlDOS_PW(eF[tid]) + (1-M)*(e/COX)*blDOS_PW(eF[tid], eG[0], eG[1]) );
eF[tid] += FLYWHEEL*(lhs - rhs)/(dhs);
}
}
return;
}
}
//////////////////////////////////////////
// VECTORWISE CARRIERS/DOS //
//////////////////////////////////////////
extern "C"{
__global__ void mlDOS_vec(float* eF, float* RO){
const int tid = threadIdx.x;
RO[tid] = mlDOS_PW(eF[tid]);
return;
}
}
extern "C"{
__global__ void blDOS_vec(float* eF, float* eG, float* RO){
const int tid = threadIdx.x;
RO[tid] = blDOS_PW(eF[tid], eG[0], eG[1]);
return;
}
}
extern "C"{
__global__ void mlCarriers_vec(float* eF, float* n, float* p, float t){
const int tid = threadIdx.x;
int INT = 1024;
for(int i = 0; i<INT; i++){
n[tid] += mlDOS_PW(float(i)/float(INT))*(1.0 / (1.0 + exp( ((float(i)/float(INT)) -eF[tid]) /(KB*t))))*(1.0/INT);
}
for(int i = 0; i<INT; i++){
p[tid] += mlDOS_PW(float(i)/float(INT))*(1.0 / (1.0 + exp( ((float(i)/float(INT)) +eF[tid]) /(KB*t))))*(1.0/INT);
}
return;
}
}
extern "C"{
__global__ void blCarriers_vec(float* eF, float* eG, float* n, float* p, float t){
const int tid = threadIdx.x;
int INT = 1024;
for(int i = 0; i<INT; i++){
n[tid] += blDOS_PW(float(i)/float(INT), eG[0], eG[1])*(1.0 / (1.0 + exp( ((float(i)/float(INT)) -eF[tid]) /(KB*t))))*(1.0/INT);
}
for(int i = 0; i<INT; i++){
p[tid] += blDOS_PW(float(i)/float(INT), eG[0], eG[1])*(1.0 / (1.0 + exp( ((float(i)/float(INT)) +eF[tid]) /(KB*t))))*(1.0/INT);
}
return;
}
} | .file "tmpxft_0005255a_00000000-6_grapheneMOS.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2279:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2279:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl addToC
.type addToC, @function
addToC:
.LFB2271:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2271:
.size addToC, .-addToC
.globl mlDOS_PW
.type mlDOS_PW, @function
mlDOS_PW:
.LFB2272:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2272:
.size mlDOS_PW, .-mlDOS_PW
.globl mlCarriers_PW
.type mlCarriers_PW, @function
mlCarriers_PW:
.LFB2273:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2273:
.size mlCarriers_PW, .-mlCarriers_PW
.globl blDOS_PW
.type blDOS_PW, @function
blDOS_PW:
.LFB2274:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2274:
.size blDOS_PW, .-blDOS_PW
.globl blCarriers_PW
.type blCarriers_PW, @function
blCarriers_PW:
.LFB2275:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2275:
.size blCarriers_PW, .-blCarriers_PW
.globl integrate
.type integrate, @function
integrate:
.LFB2276:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2276:
.size integrate, .-integrate
.globl _Z31__device_stub__Z8gen_randPfS_fmPfS_fm
.type _Z31__device_stub__Z8gen_randPfS_fmPfS_fm, @function
_Z31__device_stub__Z8gen_randPfS_fmPfS_fm:
.LFB2301:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq gen_rand(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2301:
.size _Z31__device_stub__Z8gen_randPfS_fmPfS_fm, .-_Z31__device_stub__Z8gen_randPfS_fmPfS_fm
.globl gen_rand
.type gen_rand, @function
gen_rand:
.LFB2302:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8gen_randPfS_fmPfS_fm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2302:
.size gen_rand, .-gen_rand
.globl _Z42__device_stub__Z9gen_capMCPfS_S_S_S_S_ffimPfS_S_S_S_S_ffim
.type _Z42__device_stub__Z9gen_capMCPfS_S_S_S_S_ffimPfS_S_S_S_S_ffim, @function
_Z42__device_stub__Z9gen_capMCPfS_S_S_S_S_ffimPfS_S_S_S_S_ffim:
.LFB2303:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 240(%rsp), %rax
movq %rax, 192(%rsp)
leaq 248(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq gen_capMC(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2303:
.size _Z42__device_stub__Z9gen_capMCPfS_S_S_S_S_ffimPfS_S_S_S_S_ffim, .-_Z42__device_stub__Z9gen_capMCPfS_S_S_S_S_ffimPfS_S_S_S_S_ffim
.globl gen_capMC
.type gen_capMC, @function
gen_capMC:
.LFB2304:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z42__device_stub__Z9gen_capMCPfS_S_S_S_S_ffimPfS_S_S_S_S_ffim
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2304:
.size gen_capMC, .-gen_capMC
.globl _Z39__device_stub__Z8solve_eFPfS_S_S_S_ffffPfS_S_S_S_ffff
.type _Z39__device_stub__Z8solve_eFPfS_S_S_S_ffffPfS_S_S_S_ffff, @function
_Z39__device_stub__Z8solve_eFPfS_S_S_S_ffffPfS_S_S_S_ffff:
.LFB2305:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq solve_eF(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2305:
.size _Z39__device_stub__Z8solve_eFPfS_S_S_S_ffffPfS_S_S_S_ffff, .-_Z39__device_stub__Z8solve_eFPfS_S_S_S_ffffPfS_S_S_S_ffff
.globl solve_eF
.type solve_eF, @function
solve_eF:
.LFB2306:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z8solve_eFPfS_S_S_S_ffffPfS_S_S_S_ffff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2306:
.size solve_eF, .-solve_eF
.globl _Z30__device_stub__Z9mlDOS_vecPfS_PfS_
.type _Z30__device_stub__Z9mlDOS_vecPfS_PfS_, @function
_Z30__device_stub__Z9mlDOS_vecPfS_PfS_:
.LFB2307:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L43
.L39:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq mlDOS_vec(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L39
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2307:
.size _Z30__device_stub__Z9mlDOS_vecPfS_PfS_, .-_Z30__device_stub__Z9mlDOS_vecPfS_PfS_
.globl mlDOS_vec
.type mlDOS_vec, @function
mlDOS_vec:
.LFB2308:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9mlDOS_vecPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2308:
.size mlDOS_vec, .-mlDOS_vec
.globl _Z32__device_stub__Z9blDOS_vecPfS_S_PfS_S_
.type _Z32__device_stub__Z9blDOS_vecPfS_S_PfS_S_, @function
_Z32__device_stub__Z9blDOS_vecPfS_S_PfS_S_:
.LFB2309:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L51
.L47:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L52
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq blDOS_vec(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L47
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2309:
.size _Z32__device_stub__Z9blDOS_vecPfS_S_PfS_S_, .-_Z32__device_stub__Z9blDOS_vecPfS_S_PfS_S_
.globl blDOS_vec
.type blDOS_vec, @function
blDOS_vec:
.LFB2310:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9blDOS_vecPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2310:
.size blDOS_vec, .-blDOS_vec
.globl _Z39__device_stub__Z14mlCarriers_vecPfS_S_fPfS_S_f
.type _Z39__device_stub__Z14mlCarriers_vecPfS_S_fPfS_S_f, @function
_Z39__device_stub__Z14mlCarriers_vecPfS_S_fPfS_S_f:
.LFB2311:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L59
.L55:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L60
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq mlCarriers_vec(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L55
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2311:
.size _Z39__device_stub__Z14mlCarriers_vecPfS_S_fPfS_S_f, .-_Z39__device_stub__Z14mlCarriers_vecPfS_S_fPfS_S_f
.globl mlCarriers_vec
.type mlCarriers_vec, @function
mlCarriers_vec:
.LFB2312:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14mlCarriers_vecPfS_S_fPfS_S_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2312:
.size mlCarriers_vec, .-mlCarriers_vec
.globl _Z41__device_stub__Z14blCarriers_vecPfS_S_S_fPfS_S_S_f
.type _Z41__device_stub__Z14blCarriers_vecPfS_S_S_fPfS_S_S_f, @function
_Z41__device_stub__Z14blCarriers_vecPfS_S_S_fPfS_S_S_f:
.LFB2313:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L67
.L63:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L68
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq blCarriers_vec(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L63
.L68:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2313:
.size _Z41__device_stub__Z14blCarriers_vecPfS_S_S_fPfS_S_S_f, .-_Z41__device_stub__Z14blCarriers_vecPfS_S_S_fPfS_S_S_f
.globl blCarriers_vec
.type blCarriers_vec, @function
blCarriers_vec:
.LFB2314:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14blCarriers_vecPfS_S_S_fPfS_S_S_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2314:
.size blCarriers_vec, .-blCarriers_vec
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "blCarriers_vec"
.LC1:
.string "mlCarriers_vec"
.LC2:
.string "blDOS_vec"
.LC3:
.string "mlDOS_vec"
.LC4:
.string "solve_eF"
.LC5:
.string "gen_capMC"
.LC6:
.string "gen_rand"
.LC7:
.string "precalc_xorwow_matrix"
.LC8:
.string "precalc_xorwow_offset_matrix"
.LC9:
.string "mrg32k3aM1"
.LC10:
.string "mrg32k3aM2"
.LC11:
.string "mrg32k3aM1SubSeq"
.LC12:
.string "mrg32k3aM2SubSeq"
.LC13:
.string "mrg32k3aM1Seq"
.LC14:
.string "mrg32k3aM2Seq"
.LC15:
.string "__cr_lgamma_table"
.LC16:
.string "PI"
.LC17:
.string "HB"
.LC18:
.string "KB"
.LC19:
.string "VF"
.LC20:
.string "G"
.LC21:
.string "GS"
.LC22:
.string "e"
.LC23:
.string "R"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2316:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq blCarriers_vec(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq mlCarriers_vec(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq blDOS_vec(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq mlDOS_vec(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq solve_eF(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq gen_capMC(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq gen_rand(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2PI(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2HB(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2KB(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2VF(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1G(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2GS(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1e(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1R(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2316:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL1R
.comm _ZL1R,4,4
.local _ZL1e
.comm _ZL1e,4,4
.local _ZL2GS
.comm _ZL2GS,4,4
.local _ZL1G
.comm _ZL1G,4,4
.local _ZL2VF
.comm _ZL2VF,4,4
.local _ZL2KB
.comm _ZL2KB,4,4
.local _ZL2HB
.comm _ZL2HB,4,4
.local _ZL2PI
.comm _ZL2PI,4,4
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //////////////////////////////////////////////////////////////////////////
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Author: M. Winters (2016)
// Institution: Chalmers Universtiy of Technology (MC2)
// email: mesoic@protonmail.com
//
//////////////////////////////////////////////////////////////////////////
//
// Graphene CV Modeling Kernel
//
// Compile with: nvcc -c -arch=sm_20 <filename>.cu
//
// Compilation will create CV_kernel.cubin which provides the
// functions below. The .cubin can then be imported into
// Python(PyCUDA) or C/C++ code.
//
//////////////////////////////////////////////////////////////////////////
//
// This kernel provides GPU methods to calculate the monolayer and bilayer
// DOS, eF, Capacitance, and other related quantities. Dit and surface
// potential fluctuations are also included.
//
// Characterization and physical modeling of MOS capacitors in epitaxial
// graphene monolayers and bilayers on 6H-SiC
//
// AIP Advances 6, 085010 (2016); https://doi.org/10.1063/1.4961361
//
#include <stdio.h>
#include <curand.h>
#include <curand_kernel.h>
#include <math.h>
///////////////////////
// CONSTANTS //
///////////////////////
__device__ __constant__ float PI = 3.141592654f;
__device__ __constant__ float HB = 6.58211e-16f;
__device__ __constant__ float KB = 8.617332e-5f;
__device__ __constant__ float VF = 1.000000e+8f;
__device__ __constant__ float G = 0.400f;
__device__ __constant__ float GS = 4.000f;
__device__ __constant__ float e = 1.602e-19f;
__device__ __constant__ float R = 1.414213562f;
//////////////////////////////////
// ATOMIC OPERATIONS //
//////////////////////////////////
extern "C" {
__device__ void addToC(float *r, float* rx, float* a, float n, int INT) {
for (int i=0; i<INT;i ++){
atomicAdd(&r[i], rx[i] + n*a[i]);
}
}
}
//////////////////////////////////////////
// CALCULATION OF DOS/CARRIERS //
//////////////////////////////////////////
// Monolayer
extern "C"{
__device__ float mlDOS_PW(float eF){
return (GS/(2.0*PI))*(1.0/(HB*HB*VF*VF))*abs(eF);
}
}
extern "C" {
__device__ float mlCarriers_PW(float ef, float T){
int INT = 1024;
float n = 0.0;
float p = 0.0;
for(int i = 0; i<INT; i++){
n += mlDOS_PW(float(i)/float(INT))*(1.0/(1.0 + exp( ((float(i)/float(INT)) -ef )/(KB*T))))*(1.0/INT);
p += mlDOS_PW(float(i)/float(INT))*(1.0/(1.0 + exp( ef + (float(i)/float(INT)) )/(KB*T)))*(1.0/INT);
}
return n-p;
}
}
// Bilayer. DOS includes energy gap model
extern "C" {
__device__ float blDOS_PW(float eF, float eG, float eGs){
if (eG < 0.0){ return (GS/(2.0*PI))*(1.0/(HB*HB*VF*VF))*(abs(eF) + (G/2.0));}
double dFp;
double dFm;
dFp = float( 0.5* (1 - erf ( double( (eF+eG)/(R*eGs) ) )));
dFm = 1.0 - float( 0.5* (1 - erf ( double ( (eF-eG)/(R*eGs) ) )));
return (float(dFm)+float(dFp)) * (GS/(2.0*PI)) * (1.0/(HB*HB*VF*VF))*(abs(eF) + (G/2.0));
}
}
extern "C" {
__device__ float blCarriers_PW(float ef, float eG, float eGs, float T){
int INT = 1024;
float n = 0.0;
float p = 0.0;
for(int i = 0; i<INT; i++){
n += blDOS_PW(float(i)/float(INT), eG, eGs) * (1.0/(1.0 + exp(( (float(i)/float(INT)) -ef )/(KB*T))))*(1.0/INT);
p += blDOS_PW(float(i)/float(INT), eG, eGs) * (1.0/(1.0 + exp(( ef + (float(i)/float(INT)) )/(KB*T))))*(1.0/INT);
}
return n-p;
}
}
//////////////////////////////////////////////////
// MONTE CARLO SIMULATION of CAPACITANCE //
//////////////////////////////////////////////////
extern "C" {
__global__ void gen_rand(float* eF, float* eFr, float deF, unsigned long SEED){
const int tid = threadIdx.x;
curandState state;
curand_init(SEED, tid, 0, &state);
eF[tid] = eF[tid];
eFr[tid] = deF*curand_normal(&state) + eF[tid];
}
}
extern "C" {
__global__ void gen_capMC(float* eF, float* eFr, float* eG, float* deF, float* Dit,
float*C, float COX, float M, int DEPTH, unsigned long SEED){
const int tid = threadIdx.x;
curandState state;
curand_init(SEED, tid, 0, &state);
float num;
float den;
for (int i = 0; i<DEPTH; i++){
eFr[tid] = deF[0]*( exp(-1* (eF[tid]*eF[tid])/(2*deF[1]*deF[1])) )*curand_normal(&state) + eF[tid];
num = (e*COX * ( M*mlDOS_PW(eFr[tid]) + (1.0-M)*blDOS_PW(eFr[tid], eG[0], eG[1]) + Dit[tid]));
den = (COX + e*M*mlDOS_PW(eFr[tid]) + e*(1.0-M)*blDOS_PW(eFr[tid], eG[0], eG[1]) + e*Dit[tid]);
C[tid] += num/den;
}
C[tid] = C[tid]/float(DEPTH);
}
}
///////////////////////////////////////////
// NEWTONS METHOD //
///////////////////////////////////////////
extern "C"{
__device__ float integrate(int v_i, int vD_i, float* Dit, float DELTA){
float _int = 0;
// Some bad coding to take care of return sweep
if (v_i == 200){
v_i = 0;
}
if (v_i > 100){
v_i -= 2*(v_i%100);
}
// Otherwise just integrate like normal
if (v_i < vD_i){
for(int i = v_i; i < vD_i; i++){
_int += Dit[i]*DELTA ;
}
}
else{
for(int i = vD_i; i < v_i; i++){
_int -= Dit[i]*DELTA ;
}
}
return _int;
}
}
extern "C"{
__global__ void solve_eF(float* v, float* vD, float* Dit, float* eF, float* eG,
float COX, float T, float M, float FLYWHEEL){
const int tid = threadIdx.x;
const float DELTA = v[1]-v[0];
float lhs = v[tid] - vD[0] - ((e/COX)*integrate(tid, int(vD[1]), Dit, DELTA));
float rhs = ( eF[tid] + M*(e/COX)*mlCarriers_PW(eF[tid], T) + (1-M)*(e/COX)*blCarriers_PW(eF[tid], eG[0], eG[1], T) );
float dhs;
if (tid == int(vD[1])){
eF[tid] = 0.0;
return;
}
if (tid - 2*(tid%100) == int(vD[1])){
eF[tid] = 0.0;
return;
}
for (int i = 0; i < 100; i++){
float conv = (lhs - rhs);
if (abs(conv) < 1e-6){
return;
}
else{
rhs = ( eF[tid] + M*(e/COX)*mlCarriers_PW(eF[tid], T) + (1-M)*(e/COX)*blCarriers_PW(eF[tid], eG[0], eG[1], T) );
dhs = ( 1 + M*(e/COX)*mlDOS_PW(eF[tid]) + (1-M)*(e/COX)*blDOS_PW(eF[tid], eG[0], eG[1]) );
eF[tid] += FLYWHEEL*(lhs - rhs)/(dhs);
}
}
return;
}
}
//////////////////////////////////////////
// VECTORWISE CARRIERS/DOS //
//////////////////////////////////////////
extern "C"{
__global__ void mlDOS_vec(float* eF, float* RO){
const int tid = threadIdx.x;
RO[tid] = mlDOS_PW(eF[tid]);
return;
}
}
extern "C"{
__global__ void blDOS_vec(float* eF, float* eG, float* RO){
const int tid = threadIdx.x;
RO[tid] = blDOS_PW(eF[tid], eG[0], eG[1]);
return;
}
}
extern "C"{
__global__ void mlCarriers_vec(float* eF, float* n, float* p, float t){
const int tid = threadIdx.x;
int INT = 1024;
for(int i = 0; i<INT; i++){
n[tid] += mlDOS_PW(float(i)/float(INT))*(1.0 / (1.0 + exp( ((float(i)/float(INT)) -eF[tid]) /(KB*t))))*(1.0/INT);
}
for(int i = 0; i<INT; i++){
p[tid] += mlDOS_PW(float(i)/float(INT))*(1.0 / (1.0 + exp( ((float(i)/float(INT)) +eF[tid]) /(KB*t))))*(1.0/INT);
}
return;
}
}
extern "C"{
__global__ void blCarriers_vec(float* eF, float* eG, float* n, float* p, float t){
const int tid = threadIdx.x;
int INT = 1024;
for(int i = 0; i<INT; i++){
n[tid] += blDOS_PW(float(i)/float(INT), eG[0], eG[1])*(1.0 / (1.0 + exp( ((float(i)/float(INT)) -eF[tid]) /(KB*t))))*(1.0/INT);
}
for(int i = 0; i<INT; i++){
p[tid] += blDOS_PW(float(i)/float(INT), eG[0], eG[1])*(1.0 / (1.0 + exp( ((float(i)/float(INT)) +eF[tid]) /(KB*t))))*(1.0/INT);
}
return;
}
} | //////////////////////////////////////////////////////////////////////////
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Author: M. Winters (2016)
// Institution: Chalmers Universtiy of Technology (MC2)
// email: mesoic@protonmail.com
//
//////////////////////////////////////////////////////////////////////////
//
// Graphene CV Modeling Kernel
//
// Compile with: nvcc -c -arch=sm_20 <filename>.cu
//
// Compilation will create CV_kernel.cubin which provides the
// functions below. The .cubin can then be imported into
// Python(PyCUDA) or C/C++ code.
//
//////////////////////////////////////////////////////////////////////////
//
// This kernel provides GPU methods to calculate the monolayer and bilayer
// DOS, eF, Capacitance, and other related quantities. Dit and surface
// potential fluctuations are also included.
//
// Characterization and physical modeling of MOS capacitors in epitaxial
// graphene monolayers and bilayers on 6H-SiC
//
// AIP Advances 6, 085010 (2016); https://doi.org/10.1063/1.4961361
//
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <math.h>
///////////////////////
// CONSTANTS //
///////////////////////
__device__ __constant__ float PI = 3.141592654f;
__device__ __constant__ float HB = 6.58211e-16f;
__device__ __constant__ float KB = 8.617332e-5f;
__device__ __constant__ float VF = 1.000000e+8f;
__device__ __constant__ float G = 0.400f;
__device__ __constant__ float GS = 4.000f;
__device__ __constant__ float e = 1.602e-19f;
__device__ __constant__ float R = 1.414213562f;
//////////////////////////////////
// ATOMIC OPERATIONS //
//////////////////////////////////
extern "C" {
__device__ void addToC(float *r, float* rx, float* a, float n, int INT) {
for (int i=0; i<INT;i ++){
atomicAdd(&r[i], rx[i] + n*a[i]);
}
}
}
//////////////////////////////////////////
// CALCULATION OF DOS/CARRIERS //
//////////////////////////////////////////
// Monolayer
extern "C"{
__device__ float mlDOS_PW(float eF){
return (GS/(2.0*PI))*(1.0/(HB*HB*VF*VF))*abs(eF);
}
}
extern "C" {
__device__ float mlCarriers_PW(float ef, float T){
int INT = 1024;
float n = 0.0;
float p = 0.0;
for(int i = 0; i<INT; i++){
n += mlDOS_PW(float(i)/float(INT))*(1.0/(1.0 + exp( ((float(i)/float(INT)) -ef )/(KB*T))))*(1.0/INT);
p += mlDOS_PW(float(i)/float(INT))*(1.0/(1.0 + exp( ef + (float(i)/float(INT)) )/(KB*T)))*(1.0/INT);
}
return n-p;
}
}
// Bilayer. DOS includes energy gap model
extern "C" {
__device__ float blDOS_PW(float eF, float eG, float eGs){
if (eG < 0.0){ return (GS/(2.0*PI))*(1.0/(HB*HB*VF*VF))*(abs(eF) + (G/2.0));}
double dFp;
double dFm;
dFp = float( 0.5* (1 - erf ( double( (eF+eG)/(R*eGs) ) )));
dFm = 1.0 - float( 0.5* (1 - erf ( double ( (eF-eG)/(R*eGs) ) )));
return (float(dFm)+float(dFp)) * (GS/(2.0*PI)) * (1.0/(HB*HB*VF*VF))*(abs(eF) + (G/2.0));
}
}
extern "C" {
__device__ float blCarriers_PW(float ef, float eG, float eGs, float T){
int INT = 1024;
float n = 0.0;
float p = 0.0;
for(int i = 0; i<INT; i++){
n += blDOS_PW(float(i)/float(INT), eG, eGs) * (1.0/(1.0 + exp(( (float(i)/float(INT)) -ef )/(KB*T))))*(1.0/INT);
p += blDOS_PW(float(i)/float(INT), eG, eGs) * (1.0/(1.0 + exp(( ef + (float(i)/float(INT)) )/(KB*T))))*(1.0/INT);
}
return n-p;
}
}
//////////////////////////////////////////////////
// MONTE CARLO SIMULATION of CAPACITANCE //
//////////////////////////////////////////////////
extern "C" {
__global__ void gen_rand(float* eF, float* eFr, float deF, unsigned long SEED){
const int tid = threadIdx.x;
hiprandState state;
hiprand_init(SEED, tid, 0, &state);
eF[tid] = eF[tid];
eFr[tid] = deF*hiprand_normal(&state) + eF[tid];
}
}
extern "C" {
__global__ void gen_capMC(float* eF, float* eFr, float* eG, float* deF, float* Dit,
float*C, float COX, float M, int DEPTH, unsigned long SEED){
const int tid = threadIdx.x;
hiprandState state;
hiprand_init(SEED, tid, 0, &state);
float num;
float den;
for (int i = 0; i<DEPTH; i++){
eFr[tid] = deF[0]*( exp(-1* (eF[tid]*eF[tid])/(2*deF[1]*deF[1])) )*hiprand_normal(&state) + eF[tid];
num = (e*COX * ( M*mlDOS_PW(eFr[tid]) + (1.0-M)*blDOS_PW(eFr[tid], eG[0], eG[1]) + Dit[tid]));
den = (COX + e*M*mlDOS_PW(eFr[tid]) + e*(1.0-M)*blDOS_PW(eFr[tid], eG[0], eG[1]) + e*Dit[tid]);
C[tid] += num/den;
}
C[tid] = C[tid]/float(DEPTH);
}
}
///////////////////////////////////////////
// NEWTONS METHOD //
///////////////////////////////////////////
extern "C"{
__device__ float integrate(int v_i, int vD_i, float* Dit, float DELTA){
float _int = 0;
// Some bad coding to take care of return sweep
if (v_i == 200){
v_i = 0;
}
if (v_i > 100){
v_i -= 2*(v_i%100);
}
// Otherwise just integrate like normal
if (v_i < vD_i){
for(int i = v_i; i < vD_i; i++){
_int += Dit[i]*DELTA ;
}
}
else{
for(int i = vD_i; i < v_i; i++){
_int -= Dit[i]*DELTA ;
}
}
return _int;
}
}
extern "C"{
__global__ void solve_eF(float* v, float* vD, float* Dit, float* eF, float* eG,
float COX, float T, float M, float FLYWHEEL){
const int tid = threadIdx.x;
const float DELTA = v[1]-v[0];
float lhs = v[tid] - vD[0] - ((e/COX)*integrate(tid, int(vD[1]), Dit, DELTA));
float rhs = ( eF[tid] + M*(e/COX)*mlCarriers_PW(eF[tid], T) + (1-M)*(e/COX)*blCarriers_PW(eF[tid], eG[0], eG[1], T) );
float dhs;
if (tid == int(vD[1])){
eF[tid] = 0.0;
return;
}
if (tid - 2*(tid%100) == int(vD[1])){
eF[tid] = 0.0;
return;
}
for (int i = 0; i < 100; i++){
float conv = (lhs - rhs);
if (abs(conv) < 1e-6){
return;
}
else{
rhs = ( eF[tid] + M*(e/COX)*mlCarriers_PW(eF[tid], T) + (1-M)*(e/COX)*blCarriers_PW(eF[tid], eG[0], eG[1], T) );
dhs = ( 1 + M*(e/COX)*mlDOS_PW(eF[tid]) + (1-M)*(e/COX)*blDOS_PW(eF[tid], eG[0], eG[1]) );
eF[tid] += FLYWHEEL*(lhs - rhs)/(dhs);
}
}
return;
}
}
//////////////////////////////////////////
// VECTORWISE CARRIERS/DOS //
//////////////////////////////////////////
extern "C"{
__global__ void mlDOS_vec(float* eF, float* RO){
const int tid = threadIdx.x;
RO[tid] = mlDOS_PW(eF[tid]);
return;
}
}
extern "C"{
__global__ void blDOS_vec(float* eF, float* eG, float* RO){
const int tid = threadIdx.x;
RO[tid] = blDOS_PW(eF[tid], eG[0], eG[1]);
return;
}
}
extern "C"{
__global__ void mlCarriers_vec(float* eF, float* n, float* p, float t){
const int tid = threadIdx.x;
int INT = 1024;
for(int i = 0; i<INT; i++){
n[tid] += mlDOS_PW(float(i)/float(INT))*(1.0 / (1.0 + exp( ((float(i)/float(INT)) -eF[tid]) /(KB*t))))*(1.0/INT);
}
for(int i = 0; i<INT; i++){
p[tid] += mlDOS_PW(float(i)/float(INT))*(1.0 / (1.0 + exp( ((float(i)/float(INT)) +eF[tid]) /(KB*t))))*(1.0/INT);
}
return;
}
}
extern "C"{
__global__ void blCarriers_vec(float* eF, float* eG, float* n, float* p, float t){
const int tid = threadIdx.x;
int INT = 1024;
for(int i = 0; i<INT; i++){
n[tid] += blDOS_PW(float(i)/float(INT), eG[0], eG[1])*(1.0 / (1.0 + exp( ((float(i)/float(INT)) -eF[tid]) /(KB*t))))*(1.0/INT);
}
for(int i = 0; i<INT; i++){
p[tid] += blDOS_PW(float(i)/float(INT), eG[0], eG[1])*(1.0 / (1.0 + exp( ((float(i)/float(INT)) +eF[tid]) /(KB*t))))*(1.0/INT);
}
return;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //////////////////////////////////////////////////////////////////////////
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Author: M. Winters (2016)
// Institution: Chalmers Universtiy of Technology (MC2)
// email: mesoic@protonmail.com
//
//////////////////////////////////////////////////////////////////////////
//
// Graphene CV Modeling Kernel
//
// Compile with: nvcc -c -arch=sm_20 <filename>.cu
//
// Compilation will create CV_kernel.cubin which provides the
// functions below. The .cubin can then be imported into
// Python(PyCUDA) or C/C++ code.
//
//////////////////////////////////////////////////////////////////////////
//
// This kernel provides GPU methods to calculate the monolayer and bilayer
// DOS, eF, Capacitance, and other related quantities. Dit and surface
// potential fluctuations are also included.
//
// Characterization and physical modeling of MOS capacitors in epitaxial
// graphene monolayers and bilayers on 6H-SiC
//
// AIP Advances 6, 085010 (2016); https://doi.org/10.1063/1.4961361
//
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <math.h>
///////////////////////
// CONSTANTS //
///////////////////////
__device__ __constant__ float PI = 3.141592654f;
__device__ __constant__ float HB = 6.58211e-16f;
__device__ __constant__ float KB = 8.617332e-5f;
__device__ __constant__ float VF = 1.000000e+8f;
__device__ __constant__ float G = 0.400f;
__device__ __constant__ float GS = 4.000f;
__device__ __constant__ float e = 1.602e-19f;
__device__ __constant__ float R = 1.414213562f;
//////////////////////////////////
// ATOMIC OPERATIONS //
//////////////////////////////////
extern "C" {
__device__ void addToC(float *r, float* rx, float* a, float n, int INT) {
for (int i=0; i<INT;i ++){
atomicAdd(&r[i], rx[i] + n*a[i]);
}
}
}
//////////////////////////////////////////
// CALCULATION OF DOS/CARRIERS //
//////////////////////////////////////////
// Monolayer
extern "C"{
__device__ float mlDOS_PW(float eF){
return (GS/(2.0*PI))*(1.0/(HB*HB*VF*VF))*abs(eF);
}
}
extern "C" {
__device__ float mlCarriers_PW(float ef, float T){
int INT = 1024;
float n = 0.0;
float p = 0.0;
for(int i = 0; i<INT; i++){
n += mlDOS_PW(float(i)/float(INT))*(1.0/(1.0 + exp( ((float(i)/float(INT)) -ef )/(KB*T))))*(1.0/INT);
p += mlDOS_PW(float(i)/float(INT))*(1.0/(1.0 + exp( ef + (float(i)/float(INT)) )/(KB*T)))*(1.0/INT);
}
return n-p;
}
}
// Bilayer. DOS includes energy gap model
extern "C" {
__device__ float blDOS_PW(float eF, float eG, float eGs){
if (eG < 0.0){ return (GS/(2.0*PI))*(1.0/(HB*HB*VF*VF))*(abs(eF) + (G/2.0));}
double dFp;
double dFm;
dFp = float( 0.5* (1 - erf ( double( (eF+eG)/(R*eGs) ) )));
dFm = 1.0 - float( 0.5* (1 - erf ( double ( (eF-eG)/(R*eGs) ) )));
return (float(dFm)+float(dFp)) * (GS/(2.0*PI)) * (1.0/(HB*HB*VF*VF))*(abs(eF) + (G/2.0));
}
}
extern "C" {
__device__ float blCarriers_PW(float ef, float eG, float eGs, float T){
int INT = 1024;
float n = 0.0;
float p = 0.0;
for(int i = 0; i<INT; i++){
n += blDOS_PW(float(i)/float(INT), eG, eGs) * (1.0/(1.0 + exp(( (float(i)/float(INT)) -ef )/(KB*T))))*(1.0/INT);
p += blDOS_PW(float(i)/float(INT), eG, eGs) * (1.0/(1.0 + exp(( ef + (float(i)/float(INT)) )/(KB*T))))*(1.0/INT);
}
return n-p;
}
}
//////////////////////////////////////////////////
// MONTE CARLO SIMULATION of CAPACITANCE //
//////////////////////////////////////////////////
extern "C" {
__global__ void gen_rand(float* eF, float* eFr, float deF, unsigned long SEED){
const int tid = threadIdx.x;
hiprandState state;
hiprand_init(SEED, tid, 0, &state);
eF[tid] = eF[tid];
eFr[tid] = deF*hiprand_normal(&state) + eF[tid];
}
}
extern "C" {
__global__ void gen_capMC(float* eF, float* eFr, float* eG, float* deF, float* Dit,
float*C, float COX, float M, int DEPTH, unsigned long SEED){
const int tid = threadIdx.x;
hiprandState state;
hiprand_init(SEED, tid, 0, &state);
float num;
float den;
for (int i = 0; i<DEPTH; i++){
eFr[tid] = deF[0]*( exp(-1* (eF[tid]*eF[tid])/(2*deF[1]*deF[1])) )*hiprand_normal(&state) + eF[tid];
num = (e*COX * ( M*mlDOS_PW(eFr[tid]) + (1.0-M)*blDOS_PW(eFr[tid], eG[0], eG[1]) + Dit[tid]));
den = (COX + e*M*mlDOS_PW(eFr[tid]) + e*(1.0-M)*blDOS_PW(eFr[tid], eG[0], eG[1]) + e*Dit[tid]);
C[tid] += num/den;
}
C[tid] = C[tid]/float(DEPTH);
}
}
///////////////////////////////////////////
// NEWTONS METHOD //
///////////////////////////////////////////
extern "C"{
__device__ float integrate(int v_i, int vD_i, float* Dit, float DELTA){
float _int = 0;
// Some bad coding to take care of return sweep
if (v_i == 200){
v_i = 0;
}
if (v_i > 100){
v_i -= 2*(v_i%100);
}
// Otherwise just integrate like normal
if (v_i < vD_i){
for(int i = v_i; i < vD_i; i++){
_int += Dit[i]*DELTA ;
}
}
else{
for(int i = vD_i; i < v_i; i++){
_int -= Dit[i]*DELTA ;
}
}
return _int;
}
}
extern "C"{
__global__ void solve_eF(float* v, float* vD, float* Dit, float* eF, float* eG,
float COX, float T, float M, float FLYWHEEL){
const int tid = threadIdx.x;
const float DELTA = v[1]-v[0];
float lhs = v[tid] - vD[0] - ((e/COX)*integrate(tid, int(vD[1]), Dit, DELTA));
float rhs = ( eF[tid] + M*(e/COX)*mlCarriers_PW(eF[tid], T) + (1-M)*(e/COX)*blCarriers_PW(eF[tid], eG[0], eG[1], T) );
float dhs;
if (tid == int(vD[1])){
eF[tid] = 0.0;
return;
}
if (tid - 2*(tid%100) == int(vD[1])){
eF[tid] = 0.0;
return;
}
for (int i = 0; i < 100; i++){
float conv = (lhs - rhs);
if (abs(conv) < 1e-6){
return;
}
else{
rhs = ( eF[tid] + M*(e/COX)*mlCarriers_PW(eF[tid], T) + (1-M)*(e/COX)*blCarriers_PW(eF[tid], eG[0], eG[1], T) );
dhs = ( 1 + M*(e/COX)*mlDOS_PW(eF[tid]) + (1-M)*(e/COX)*blDOS_PW(eF[tid], eG[0], eG[1]) );
eF[tid] += FLYWHEEL*(lhs - rhs)/(dhs);
}
}
return;
}
}
//////////////////////////////////////////
// VECTORWISE CARRIERS/DOS //
//////////////////////////////////////////
extern "C"{
__global__ void mlDOS_vec(float* eF, float* RO){
const int tid = threadIdx.x;
RO[tid] = mlDOS_PW(eF[tid]);
return;
}
}
extern "C"{
__global__ void blDOS_vec(float* eF, float* eG, float* RO){
const int tid = threadIdx.x;
RO[tid] = blDOS_PW(eF[tid], eG[0], eG[1]);
return;
}
}
extern "C"{
__global__ void mlCarriers_vec(float* eF, float* n, float* p, float t){
const int tid = threadIdx.x;
int INT = 1024;
for(int i = 0; i<INT; i++){
n[tid] += mlDOS_PW(float(i)/float(INT))*(1.0 / (1.0 + exp( ((float(i)/float(INT)) -eF[tid]) /(KB*t))))*(1.0/INT);
}
for(int i = 0; i<INT; i++){
p[tid] += mlDOS_PW(float(i)/float(INT))*(1.0 / (1.0 + exp( ((float(i)/float(INT)) +eF[tid]) /(KB*t))))*(1.0/INT);
}
return;
}
}
extern "C"{
__global__ void blCarriers_vec(float* eF, float* eG, float* n, float* p, float t){
const int tid = threadIdx.x;
int INT = 1024;
for(int i = 0; i<INT; i++){
n[tid] += blDOS_PW(float(i)/float(INT), eG[0], eG[1])*(1.0 / (1.0 + exp( ((float(i)/float(INT)) -eF[tid]) /(KB*t))))*(1.0/INT);
}
for(int i = 0; i<INT; i++){
p[tid] += blDOS_PW(float(i)/float(INT), eG[0], eG[1])*(1.0 / (1.0 + exp( ((float(i)/float(INT)) +eF[tid]) /(KB*t))))*(1.0/INT);
}
return;
}
} | .text
.file "grapheneMOS.hip"
.globl __device_stub__gen_rand # -- Begin function __device_stub__gen_rand
.p2align 4, 0x90
.type __device_stub__gen_rand,@function
__device_stub__gen_rand: # @__device_stub__gen_rand
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 4(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $gen_rand, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__gen_rand, .Lfunc_end0-__device_stub__gen_rand
.cfi_endproc
# -- End function
.globl __device_stub__gen_capMC # -- Begin function __device_stub__gen_capMC
.p2align 4, 0x90
.type __device_stub__gen_capMC,@function
__device_stub__gen_capMC: # @__device_stub__gen_capMC
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
leaq 216(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $gen_capMC, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end1:
.size __device_stub__gen_capMC, .Lfunc_end1-__device_stub__gen_capMC
.cfi_endproc
# -- End function
.globl __device_stub__solve_eF # -- Begin function __device_stub__solve_eF
.p2align 4, 0x90
.type __device_stub__solve_eF,@function
__device_stub__solve_eF: # @__device_stub__solve_eF
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $solve_eF, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end2:
.size __device_stub__solve_eF, .Lfunc_end2-__device_stub__solve_eF
.cfi_endproc
# -- End function
.globl __device_stub__mlDOS_vec # -- Begin function __device_stub__mlDOS_vec
.p2align 4, 0x90
.type __device_stub__mlDOS_vec,@function
__device_stub__mlDOS_vec: # @__device_stub__mlDOS_vec
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $mlDOS_vec, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size __device_stub__mlDOS_vec, .Lfunc_end3-__device_stub__mlDOS_vec
.cfi_endproc
# -- End function
.globl __device_stub__blDOS_vec # -- Begin function __device_stub__blDOS_vec
.p2align 4, 0x90
.type __device_stub__blDOS_vec,@function
__device_stub__blDOS_vec: # @__device_stub__blDOS_vec
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $blDOS_vec, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size __device_stub__blDOS_vec, .Lfunc_end4-__device_stub__blDOS_vec
.cfi_endproc
# -- End function
.globl __device_stub__mlCarriers_vec # -- Begin function __device_stub__mlCarriers_vec
.p2align 4, 0x90
.type __device_stub__mlCarriers_vec,@function
__device_stub__mlCarriers_vec: # @__device_stub__mlCarriers_vec
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $mlCarriers_vec, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size __device_stub__mlCarriers_vec, .Lfunc_end5-__device_stub__mlCarriers_vec
.cfi_endproc
# -- End function
.globl __device_stub__blCarriers_vec # -- Begin function __device_stub__blCarriers_vec
.p2align 4, 0x90
.type __device_stub__blCarriers_vec,@function
__device_stub__blCarriers_vec: # @__device_stub__blCarriers_vec
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $blCarriers_vec, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end6:
.size __device_stub__blCarriers_vec, .Lfunc_end6-__device_stub__blCarriers_vec
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $gen_rand, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $gen_capMC, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $solve_eF, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $mlDOS_vec, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $blDOS_vec, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $mlCarriers_vec, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $blCarriers_vec, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $PI, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $HB, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $KB, %esi
movl $.L__unnamed_10, %edx
movl $.L__unnamed_10, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $VF, %esi
movl $.L__unnamed_11, %edx
movl $.L__unnamed_11, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $G, %esi
movl $.L__unnamed_12, %edx
movl $.L__unnamed_12, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $GS, %esi
movl $.L__unnamed_13, %edx
movl $.L__unnamed_13, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $e, %esi
movl $.L__unnamed_14, %edx
movl $.L__unnamed_14, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $R, %esi
movl $.L__unnamed_15, %edx
movl $.L__unnamed_15, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type PI,@object # @PI
.local PI
.comm PI,4,4
.type HB,@object # @HB
.local HB
.comm HB,4,4
.type KB,@object # @KB
.local KB
.comm KB,4,4
.type VF,@object # @VF
.local VF
.comm VF,4,4
.type G,@object # @G
.local G
.comm G,4,4
.type GS,@object # @GS
.local GS
.comm GS,4,4
.type e,@object # @e
.local e
.comm e,4,4
.type R,@object # @R
.local R
.comm R,4,4
.type gen_rand,@object # @gen_rand
.section .rodata,"a",@progbits
.globl gen_rand
.p2align 3, 0x0
gen_rand:
.quad __device_stub__gen_rand
.size gen_rand, 8
.type gen_capMC,@object # @gen_capMC
.globl gen_capMC
.p2align 3, 0x0
gen_capMC:
.quad __device_stub__gen_capMC
.size gen_capMC, 8
.type solve_eF,@object # @solve_eF
.globl solve_eF
.p2align 3, 0x0
solve_eF:
.quad __device_stub__solve_eF
.size solve_eF, 8
.type mlDOS_vec,@object # @mlDOS_vec
.globl mlDOS_vec
.p2align 3, 0x0
mlDOS_vec:
.quad __device_stub__mlDOS_vec
.size mlDOS_vec, 8
.type blDOS_vec,@object # @blDOS_vec
.globl blDOS_vec
.p2align 3, 0x0
blDOS_vec:
.quad __device_stub__blDOS_vec
.size blDOS_vec, 8
.type mlCarriers_vec,@object # @mlCarriers_vec
.globl mlCarriers_vec
.p2align 3, 0x0
mlCarriers_vec:
.quad __device_stub__mlCarriers_vec
.size mlCarriers_vec, 8
.type blCarriers_vec,@object # @blCarriers_vec
.globl blCarriers_vec
.p2align 3, 0x0
blCarriers_vec:
.quad __device_stub__blCarriers_vec
.size blCarriers_vec, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "gen_rand"
.size .L__unnamed_1, 9
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "gen_capMC"
.size .L__unnamed_2, 10
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "solve_eF"
.size .L__unnamed_3, 9
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "mlDOS_vec"
.size .L__unnamed_4, 10
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "blDOS_vec"
.size .L__unnamed_5, 10
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "mlCarriers_vec"
.size .L__unnamed_6, 15
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "blCarriers_vec"
.size .L__unnamed_7, 15
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "PI"
.size .L__unnamed_8, 3
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "HB"
.size .L__unnamed_9, 3
.type .L__unnamed_10,@object # @9
.L__unnamed_10:
.asciz "KB"
.size .L__unnamed_10, 3
.type .L__unnamed_11,@object # @10
.L__unnamed_11:
.asciz "VF"
.size .L__unnamed_11, 3
.type .L__unnamed_12,@object # @11
.L__unnamed_12:
.asciz "G"
.size .L__unnamed_12, 2
.type .L__unnamed_13,@object # @12
.L__unnamed_13:
.asciz "GS"
.size .L__unnamed_13, 3
.type .L__unnamed_14,@object # @13
.L__unnamed_14:
.asciz "e"
.size .L__unnamed_14, 2
.type .L__unnamed_15,@object # @14
.L__unnamed_15:
.asciz "R"
.size .L__unnamed_15, 2
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__gen_rand
.addrsig_sym __device_stub__gen_capMC
.addrsig_sym __device_stub__solve_eF
.addrsig_sym __device_stub__mlDOS_vec
.addrsig_sym __device_stub__blDOS_vec
.addrsig_sym __device_stub__mlCarriers_vec
.addrsig_sym __device_stub__blCarriers_vec
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym PI
.addrsig_sym HB
.addrsig_sym KB
.addrsig_sym VF
.addrsig_sym G
.addrsig_sym GS
.addrsig_sym e
.addrsig_sym R
.addrsig_sym gen_rand
.addrsig_sym gen_capMC
.addrsig_sym solve_eF
.addrsig_sym mlDOS_vec
.addrsig_sym blDOS_vec
.addrsig_sym mlCarriers_vec
.addrsig_sym blCarriers_vec
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005255a_00000000-6_grapheneMOS.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2279:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2279:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl addToC
.type addToC, @function
addToC:
.LFB2271:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2271:
.size addToC, .-addToC
.globl mlDOS_PW
.type mlDOS_PW, @function
mlDOS_PW:
.LFB2272:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2272:
.size mlDOS_PW, .-mlDOS_PW
.globl mlCarriers_PW
.type mlCarriers_PW, @function
mlCarriers_PW:
.LFB2273:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2273:
.size mlCarriers_PW, .-mlCarriers_PW
.globl blDOS_PW
.type blDOS_PW, @function
blDOS_PW:
.LFB2274:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2274:
.size blDOS_PW, .-blDOS_PW
.globl blCarriers_PW
.type blCarriers_PW, @function
blCarriers_PW:
.LFB2275:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2275:
.size blCarriers_PW, .-blCarriers_PW
.globl integrate
.type integrate, @function
integrate:
.LFB2276:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2276:
.size integrate, .-integrate
.globl _Z31__device_stub__Z8gen_randPfS_fmPfS_fm
.type _Z31__device_stub__Z8gen_randPfS_fmPfS_fm, @function
_Z31__device_stub__Z8gen_randPfS_fmPfS_fm:
.LFB2301:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq gen_rand(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2301:
.size _Z31__device_stub__Z8gen_randPfS_fmPfS_fm, .-_Z31__device_stub__Z8gen_randPfS_fmPfS_fm
.globl gen_rand
.type gen_rand, @function
gen_rand:
.LFB2302:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8gen_randPfS_fmPfS_fm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2302:
.size gen_rand, .-gen_rand
.globl _Z42__device_stub__Z9gen_capMCPfS_S_S_S_S_ffimPfS_S_S_S_S_ffim
.type _Z42__device_stub__Z9gen_capMCPfS_S_S_S_S_ffimPfS_S_S_S_S_ffim, @function
_Z42__device_stub__Z9gen_capMCPfS_S_S_S_S_ffimPfS_S_S_S_S_ffim:
.LFB2303:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 240(%rsp), %rax
movq %rax, 192(%rsp)
leaq 248(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq gen_capMC(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2303:
.size _Z42__device_stub__Z9gen_capMCPfS_S_S_S_S_ffimPfS_S_S_S_S_ffim, .-_Z42__device_stub__Z9gen_capMCPfS_S_S_S_S_ffimPfS_S_S_S_S_ffim
.globl gen_capMC
.type gen_capMC, @function
gen_capMC:
.LFB2304:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z42__device_stub__Z9gen_capMCPfS_S_S_S_S_ffimPfS_S_S_S_S_ffim
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2304:
.size gen_capMC, .-gen_capMC
.globl _Z39__device_stub__Z8solve_eFPfS_S_S_S_ffffPfS_S_S_S_ffff
.type _Z39__device_stub__Z8solve_eFPfS_S_S_S_ffffPfS_S_S_S_ffff, @function
_Z39__device_stub__Z8solve_eFPfS_S_S_S_ffffPfS_S_S_S_ffff:
.LFB2305:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq solve_eF(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2305:
.size _Z39__device_stub__Z8solve_eFPfS_S_S_S_ffffPfS_S_S_S_ffff, .-_Z39__device_stub__Z8solve_eFPfS_S_S_S_ffffPfS_S_S_S_ffff
.globl solve_eF
.type solve_eF, @function
solve_eF:
.LFB2306:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z8solve_eFPfS_S_S_S_ffffPfS_S_S_S_ffff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2306:
.size solve_eF, .-solve_eF
.globl _Z30__device_stub__Z9mlDOS_vecPfS_PfS_
.type _Z30__device_stub__Z9mlDOS_vecPfS_PfS_, @function
_Z30__device_stub__Z9mlDOS_vecPfS_PfS_:
.LFB2307:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L43
.L39:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq mlDOS_vec(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L39
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2307:
.size _Z30__device_stub__Z9mlDOS_vecPfS_PfS_, .-_Z30__device_stub__Z9mlDOS_vecPfS_PfS_
.globl mlDOS_vec
.type mlDOS_vec, @function
mlDOS_vec:
.LFB2308:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9mlDOS_vecPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2308:
.size mlDOS_vec, .-mlDOS_vec
.globl _Z32__device_stub__Z9blDOS_vecPfS_S_PfS_S_
.type _Z32__device_stub__Z9blDOS_vecPfS_S_PfS_S_, @function
_Z32__device_stub__Z9blDOS_vecPfS_S_PfS_S_:
.LFB2309:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L51
.L47:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L52
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq blDOS_vec(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L47
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2309:
.size _Z32__device_stub__Z9blDOS_vecPfS_S_PfS_S_, .-_Z32__device_stub__Z9blDOS_vecPfS_S_PfS_S_
.globl blDOS_vec
.type blDOS_vec, @function
blDOS_vec:
.LFB2310:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9blDOS_vecPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2310:
.size blDOS_vec, .-blDOS_vec
.globl _Z39__device_stub__Z14mlCarriers_vecPfS_S_fPfS_S_f
.type _Z39__device_stub__Z14mlCarriers_vecPfS_S_fPfS_S_f, @function
_Z39__device_stub__Z14mlCarriers_vecPfS_S_fPfS_S_f:
.LFB2311:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L59
.L55:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L60
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq mlCarriers_vec(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L55
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2311:
.size _Z39__device_stub__Z14mlCarriers_vecPfS_S_fPfS_S_f, .-_Z39__device_stub__Z14mlCarriers_vecPfS_S_fPfS_S_f
.globl mlCarriers_vec
.type mlCarriers_vec, @function
mlCarriers_vec:
.LFB2312:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14mlCarriers_vecPfS_S_fPfS_S_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2312:
.size mlCarriers_vec, .-mlCarriers_vec
.globl _Z41__device_stub__Z14blCarriers_vecPfS_S_S_fPfS_S_S_f
.type _Z41__device_stub__Z14blCarriers_vecPfS_S_S_fPfS_S_S_f, @function
_Z41__device_stub__Z14blCarriers_vecPfS_S_S_fPfS_S_S_f:
.LFB2313:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L67
.L63:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L68
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq blCarriers_vec(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L63
.L68:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2313:
.size _Z41__device_stub__Z14blCarriers_vecPfS_S_S_fPfS_S_S_f, .-_Z41__device_stub__Z14blCarriers_vecPfS_S_S_fPfS_S_S_f
.globl blCarriers_vec
.type blCarriers_vec, @function
blCarriers_vec:
.LFB2314:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14blCarriers_vecPfS_S_S_fPfS_S_S_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2314:
.size blCarriers_vec, .-blCarriers_vec
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "blCarriers_vec"
.LC1:
.string "mlCarriers_vec"
.LC2:
.string "blDOS_vec"
.LC3:
.string "mlDOS_vec"
.LC4:
.string "solve_eF"
.LC5:
.string "gen_capMC"
.LC6:
.string "gen_rand"
.LC7:
.string "precalc_xorwow_matrix"
.LC8:
.string "precalc_xorwow_offset_matrix"
.LC9:
.string "mrg32k3aM1"
.LC10:
.string "mrg32k3aM2"
.LC11:
.string "mrg32k3aM1SubSeq"
.LC12:
.string "mrg32k3aM2SubSeq"
.LC13:
.string "mrg32k3aM1Seq"
.LC14:
.string "mrg32k3aM2Seq"
.LC15:
.string "__cr_lgamma_table"
.LC16:
.string "PI"
.LC17:
.string "HB"
.LC18:
.string "KB"
.LC19:
.string "VF"
.LC20:
.string "G"
.LC21:
.string "GS"
.LC22:
.string "e"
.LC23:
.string "R"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2316:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq blCarriers_vec(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq mlCarriers_vec(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq blDOS_vec(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq mlDOS_vec(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq solve_eF(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq gen_capMC(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq gen_rand(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2PI(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2HB(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2KB(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2VF(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1G(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2GS(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1e(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1R(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2316:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL1R
.comm _ZL1R,4,4
.local _ZL1e
.comm _ZL1e,4,4
.local _ZL2GS
.comm _ZL2GS,4,4
.local _ZL1G
.comm _ZL1G,4,4
.local _ZL2VF
.comm _ZL2VF,4,4
.local _ZL2KB
.comm _ZL2KB,4,4
.local _ZL2HB
.comm _ZL2HB,4,4
.local _ZL2PI
.comm _ZL2PI,4,4
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "grapheneMOS.hip"
.globl __device_stub__gen_rand # -- Begin function __device_stub__gen_rand
.p2align 4, 0x90
.type __device_stub__gen_rand,@function
__device_stub__gen_rand: # @__device_stub__gen_rand
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 4(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $gen_rand, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__gen_rand, .Lfunc_end0-__device_stub__gen_rand
.cfi_endproc
# -- End function
.globl __device_stub__gen_capMC # -- Begin function __device_stub__gen_capMC
.p2align 4, 0x90
.type __device_stub__gen_capMC,@function
__device_stub__gen_capMC: # @__device_stub__gen_capMC
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
leaq 216(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $gen_capMC, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end1:
.size __device_stub__gen_capMC, .Lfunc_end1-__device_stub__gen_capMC
.cfi_endproc
# -- End function
.globl __device_stub__solve_eF # -- Begin function __device_stub__solve_eF
.p2align 4, 0x90
.type __device_stub__solve_eF,@function
__device_stub__solve_eF: # @__device_stub__solve_eF
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $solve_eF, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end2:
.size __device_stub__solve_eF, .Lfunc_end2-__device_stub__solve_eF
.cfi_endproc
# -- End function
.globl __device_stub__mlDOS_vec # -- Begin function __device_stub__mlDOS_vec
.p2align 4, 0x90
.type __device_stub__mlDOS_vec,@function
__device_stub__mlDOS_vec: # @__device_stub__mlDOS_vec
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $mlDOS_vec, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size __device_stub__mlDOS_vec, .Lfunc_end3-__device_stub__mlDOS_vec
.cfi_endproc
# -- End function
.globl __device_stub__blDOS_vec # -- Begin function __device_stub__blDOS_vec
.p2align 4, 0x90
.type __device_stub__blDOS_vec,@function
__device_stub__blDOS_vec: # @__device_stub__blDOS_vec
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $blDOS_vec, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size __device_stub__blDOS_vec, .Lfunc_end4-__device_stub__blDOS_vec
.cfi_endproc
# -- End function
.globl __device_stub__mlCarriers_vec # -- Begin function __device_stub__mlCarriers_vec
.p2align 4, 0x90
.type __device_stub__mlCarriers_vec,@function
__device_stub__mlCarriers_vec: # @__device_stub__mlCarriers_vec
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $mlCarriers_vec, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size __device_stub__mlCarriers_vec, .Lfunc_end5-__device_stub__mlCarriers_vec
.cfi_endproc
# -- End function
.globl __device_stub__blCarriers_vec # -- Begin function __device_stub__blCarriers_vec
.p2align 4, 0x90
.type __device_stub__blCarriers_vec,@function
__device_stub__blCarriers_vec: # @__device_stub__blCarriers_vec
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $blCarriers_vec, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end6:
.size __device_stub__blCarriers_vec, .Lfunc_end6-__device_stub__blCarriers_vec
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $gen_rand, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $gen_capMC, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $solve_eF, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $mlDOS_vec, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $blDOS_vec, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $mlCarriers_vec, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $blCarriers_vec, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $PI, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $HB, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $KB, %esi
movl $.L__unnamed_10, %edx
movl $.L__unnamed_10, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $VF, %esi
movl $.L__unnamed_11, %edx
movl $.L__unnamed_11, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $G, %esi
movl $.L__unnamed_12, %edx
movl $.L__unnamed_12, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $GS, %esi
movl $.L__unnamed_13, %edx
movl $.L__unnamed_13, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $e, %esi
movl $.L__unnamed_14, %edx
movl $.L__unnamed_14, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $R, %esi
movl $.L__unnamed_15, %edx
movl $.L__unnamed_15, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type PI,@object # @PI
.local PI
.comm PI,4,4
.type HB,@object # @HB
.local HB
.comm HB,4,4
.type KB,@object # @KB
.local KB
.comm KB,4,4
.type VF,@object # @VF
.local VF
.comm VF,4,4
.type G,@object # @G
.local G
.comm G,4,4
.type GS,@object # @GS
.local GS
.comm GS,4,4
.type e,@object # @e
.local e
.comm e,4,4
.type R,@object # @R
.local R
.comm R,4,4
.type gen_rand,@object # @gen_rand
.section .rodata,"a",@progbits
.globl gen_rand
.p2align 3, 0x0
gen_rand:
.quad __device_stub__gen_rand
.size gen_rand, 8
.type gen_capMC,@object # @gen_capMC
.globl gen_capMC
.p2align 3, 0x0
gen_capMC:
.quad __device_stub__gen_capMC
.size gen_capMC, 8
.type solve_eF,@object # @solve_eF
.globl solve_eF
.p2align 3, 0x0
solve_eF:
.quad __device_stub__solve_eF
.size solve_eF, 8
.type mlDOS_vec,@object # @mlDOS_vec
.globl mlDOS_vec
.p2align 3, 0x0
mlDOS_vec:
.quad __device_stub__mlDOS_vec
.size mlDOS_vec, 8
.type blDOS_vec,@object # @blDOS_vec
.globl blDOS_vec
.p2align 3, 0x0
blDOS_vec:
.quad __device_stub__blDOS_vec
.size blDOS_vec, 8
.type mlCarriers_vec,@object # @mlCarriers_vec
.globl mlCarriers_vec
.p2align 3, 0x0
mlCarriers_vec:
.quad __device_stub__mlCarriers_vec
.size mlCarriers_vec, 8
.type blCarriers_vec,@object # @blCarriers_vec
.globl blCarriers_vec
.p2align 3, 0x0
blCarriers_vec:
.quad __device_stub__blCarriers_vec
.size blCarriers_vec, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "gen_rand"
.size .L__unnamed_1, 9
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "gen_capMC"
.size .L__unnamed_2, 10
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "solve_eF"
.size .L__unnamed_3, 9
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "mlDOS_vec"
.size .L__unnamed_4, 10
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "blDOS_vec"
.size .L__unnamed_5, 10
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "mlCarriers_vec"
.size .L__unnamed_6, 15
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "blCarriers_vec"
.size .L__unnamed_7, 15
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "PI"
.size .L__unnamed_8, 3
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "HB"
.size .L__unnamed_9, 3
.type .L__unnamed_10,@object # @9
.L__unnamed_10:
.asciz "KB"
.size .L__unnamed_10, 3
.type .L__unnamed_11,@object # @10
.L__unnamed_11:
.asciz "VF"
.size .L__unnamed_11, 3
.type .L__unnamed_12,@object # @11
.L__unnamed_12:
.asciz "G"
.size .L__unnamed_12, 2
.type .L__unnamed_13,@object # @12
.L__unnamed_13:
.asciz "GS"
.size .L__unnamed_13, 3
.type .L__unnamed_14,@object # @13
.L__unnamed_14:
.asciz "e"
.size .L__unnamed_14, 2
.type .L__unnamed_15,@object # @14
.L__unnamed_15:
.asciz "R"
.size .L__unnamed_15, 2
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__gen_rand
.addrsig_sym __device_stub__gen_capMC
.addrsig_sym __device_stub__solve_eF
.addrsig_sym __device_stub__mlDOS_vec
.addrsig_sym __device_stub__blDOS_vec
.addrsig_sym __device_stub__mlCarriers_vec
.addrsig_sym __device_stub__blCarriers_vec
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym PI
.addrsig_sym HB
.addrsig_sym KB
.addrsig_sym VF
.addrsig_sym G
.addrsig_sym GS
.addrsig_sym e
.addrsig_sym R
.addrsig_sym gen_rand
.addrsig_sym gen_capMC
.addrsig_sym solve_eF
.addrsig_sym mlDOS_vec
.addrsig_sym blDOS_vec
.addrsig_sym mlCarriers_vec
.addrsig_sym blCarriers_vec
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void unique_idx_calc_threadIdx(int *input) {
int tid = threadIdx.x;
printf("threadIdx: %d, value: %d, \n", tid, input[tid]);
}
__global__ void unique_gid_calculation(int *input) {
int tid = threadIdx.x;
int offset = blockIdx.x * blockDim.x;
int gid = tid + offset;
printf("blockIdx.x: %d, threadIdx.x: %d, gid: %d, value : %d \n", blockIdx.x,
tid, gid, input[gid]);
}
int main() {
int array_size = 16;
int array_byte_size = sizeof(int) * array_size;
int h_data[] = {23, 9, 4, 53, 65, 12, 1, 33, 87, 45, 23, 12, 342, 56, 44, 99};
for (int i = 0; i < array_size; i++) {
printf("%d ", h_data[i]);
}
printf("\n \n");
int *d_data;
cudaMalloc((void **)&d_data, array_byte_size);
cudaMemcpy(d_data, h_data, array_byte_size, cudaMemcpyHostToDevice);
dim3 block(4);
dim3 grid(4);
// unique_idx_calc_threadIdx<<<grid, block>>>(d_data);
unique_gid_calculation<<<grid, block>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z22unique_gid_calculationPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R12, SR_CTAID.X ; /* 0x00000000000c7919 */
/* 0x000e240000002500 */
/*0060*/ IMAD R14, R12, c[0x0][0x0], R13 ; /* 0x000000000c0e7a24 */
/* 0x001fc800078e020d */
/*0070*/ IMAD.WIDE R2, R14, R3, c[0x0][0x160] ; /* 0x000058000e027625 */
/* 0x000fca00078e0203 */
/*0080*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea2000c1e1900 */
/*0090*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe200078e00ff */
/*00b0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe200078e00ff */
/*00d0*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000660000000a00 */
/*00e0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00f0*/ STL.128 [R1], R12 ; /* 0x0000000c01007387 */
/* 0x0041e80000100c00 */
/*0100*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x002fc60000000000 */
/*0110*/ MOV R11, 0x180 ; /* 0x00000180000b7802 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R20, 0x100 ; /* 0x0000010000147802 */
/* 0x000fc40000000f00 */
/*0130*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe40000000f00 */
/*0150*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0160*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0170*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z25unique_idx_calc_threadIdxPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe40007ffe0ff */
/*0050*/ IMAD.WIDE R2, R10, R3, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x001fca00078e0203 */
/*0060*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea2000c1e1900 */
/*0070*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0090*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*00b0*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000660000000a00 */
/*00c0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00d0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100a00 */
/*00e0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x002fc60000000000 */
/*00f0*/ MOV R11, 0x160 ; /* 0x00000160000b7802 */
/* 0x001fe40000000f00 */
/*0100*/ MOV R20, 0xe0 ; /* 0x000000e000147802 */
/* 0x000fc40000000f00 */
/*0110*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0130*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0140*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0150*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void unique_idx_calc_threadIdx(int *input) {
int tid = threadIdx.x;
printf("threadIdx: %d, value: %d, \n", tid, input[tid]);
}
__global__ void unique_gid_calculation(int *input) {
int tid = threadIdx.x;
int offset = blockIdx.x * blockDim.x;
int gid = tid + offset;
printf("blockIdx.x: %d, threadIdx.x: %d, gid: %d, value : %d \n", blockIdx.x,
tid, gid, input[gid]);
}
int main() {
int array_size = 16;
int array_byte_size = sizeof(int) * array_size;
int h_data[] = {23, 9, 4, 53, 65, 12, 1, 33, 87, 45, 23, 12, 342, 56, 44, 99};
for (int i = 0; i < array_size; i++) {
printf("%d ", h_data[i]);
}
printf("\n \n");
int *d_data;
cudaMalloc((void **)&d_data, array_byte_size);
cudaMemcpy(d_data, h_data, array_byte_size, cudaMemcpyHostToDevice);
dim3 block(4);
dim3 grid(4);
// unique_idx_calc_threadIdx<<<grid, block>>>(d_data);
unique_gid_calculation<<<grid, block>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | .file "tmpxft_00067464_00000000-6_unique_index_calculation_using_threadIdx_blockIdx_blockDim.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi
.type _Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi, @function
_Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z25unique_idx_calc_threadIdxPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi, .-_Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi
.globl _Z25unique_idx_calc_threadIdxPi
.type _Z25unique_idx_calc_threadIdxPi, @function
_Z25unique_idx_calc_threadIdxPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z25unique_idx_calc_threadIdxPi, .-_Z25unique_idx_calc_threadIdxPi
.globl _Z42__device_stub__Z22unique_gid_calculationPiPi
.type _Z42__device_stub__Z22unique_gid_calculationPiPi, @function
_Z42__device_stub__Z22unique_gid_calculationPiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z22unique_gid_calculationPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z42__device_stub__Z22unique_gid_calculationPiPi, .-_Z42__device_stub__Z22unique_gid_calculationPiPi
.globl _Z22unique_gid_calculationPi
.type _Z22unique_gid_calculationPi, @function
_Z22unique_gid_calculationPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z22unique_gid_calculationPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z22unique_gid_calculationPi, .-_Z22unique_gid_calculationPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $23, 32(%rsp)
movl $9, 36(%rsp)
movl $4, 40(%rsp)
movl $53, 44(%rsp)
movl $65, 48(%rsp)
movl $12, 52(%rsp)
movl $1, 56(%rsp)
movl $33, 60(%rsp)
movl $87, 64(%rsp)
movl $45, 68(%rsp)
movl $23, 72(%rsp)
movl $12, 76(%rsp)
movl $342, 80(%rsp)
movl $56, 84(%rsp)
movl $44, 88(%rsp)
movl $99, 92(%rsp)
leaq 32(%rsp), %rbx
leaq 96(%rsp), %r12
leaq .LC0(%rip), %rbp
.L20:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L20
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 8(%rsp)
movl $1, 12(%rsp)
movl $4, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq (%rsp), %rdi
call _Z42__device_stub__Z22unique_gid_calculationPiPi
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z22unique_gid_calculationPi"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "_Z25unique_idx_calc_threadIdxPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z22unique_gid_calculationPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z25unique_idx_calc_threadIdxPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void unique_idx_calc_threadIdx(int *input) {
int tid = threadIdx.x;
printf("threadIdx: %d, value: %d, \n", tid, input[tid]);
}
__global__ void unique_gid_calculation(int *input) {
int tid = threadIdx.x;
int offset = blockIdx.x * blockDim.x;
int gid = tid + offset;
printf("blockIdx.x: %d, threadIdx.x: %d, gid: %d, value : %d \n", blockIdx.x,
tid, gid, input[gid]);
}
int main() {
int array_size = 16;
int array_byte_size = sizeof(int) * array_size;
int h_data[] = {23, 9, 4, 53, 65, 12, 1, 33, 87, 45, 23, 12, 342, 56, 44, 99};
for (int i = 0; i < array_size; i++) {
printf("%d ", h_data[i]);
}
printf("\n \n");
int *d_data;
cudaMalloc((void **)&d_data, array_byte_size);
cudaMemcpy(d_data, h_data, array_byte_size, cudaMemcpyHostToDevice);
dim3 block(4);
dim3 grid(4);
// unique_idx_calc_threadIdx<<<grid, block>>>(d_data);
unique_gid_calculation<<<grid, block>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void unique_idx_calc_threadIdx(int *input) {
int tid = threadIdx.x;
printf("threadIdx: %d, value: %d, \n", tid, input[tid]);
}
__global__ void unique_gid_calculation(int *input) {
int tid = threadIdx.x;
int offset = blockIdx.x * blockDim.x;
int gid = tid + offset;
printf("blockIdx.x: %d, threadIdx.x: %d, gid: %d, value : %d \n", blockIdx.x,
tid, gid, input[gid]);
}
int main() {
int array_size = 16;
int array_byte_size = sizeof(int) * array_size;
int h_data[] = {23, 9, 4, 53, 65, 12, 1, 33, 87, 45, 23, 12, 342, 56, 44, 99};
for (int i = 0; i < array_size; i++) {
printf("%d ", h_data[i]);
}
printf("\n \n");
int *d_data;
hipMalloc((void **)&d_data, array_byte_size);
hipMemcpy(d_data, h_data, array_byte_size, hipMemcpyHostToDevice);
dim3 block(4);
dim3 grid(4);
// unique_idx_calc_threadIdx<<<grid, block>>>(d_data);
unique_gid_calculation<<<grid, block>>>(d_data);
hipDeviceSynchronize();
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void unique_idx_calc_threadIdx(int *input) {
int tid = threadIdx.x;
printf("threadIdx: %d, value: %d, \n", tid, input[tid]);
}
__global__ void unique_gid_calculation(int *input) {
int tid = threadIdx.x;
int offset = blockIdx.x * blockDim.x;
int gid = tid + offset;
printf("blockIdx.x: %d, threadIdx.x: %d, gid: %d, value : %d \n", blockIdx.x,
tid, gid, input[gid]);
}
int main() {
int array_size = 16;
int array_byte_size = sizeof(int) * array_size;
int h_data[] = {23, 9, 4, 53, 65, 12, 1, 33, 87, 45, 23, 12, 342, 56, 44, 99};
for (int i = 0; i < array_size; i++) {
printf("%d ", h_data[i]);
}
printf("\n \n");
int *d_data;
hipMalloc((void **)&d_data, array_byte_size);
hipMemcpy(d_data, h_data, array_byte_size, hipMemcpyHostToDevice);
dim3 block(4);
dim3 grid(4);
// unique_idx_calc_threadIdx<<<grid, block>>>(d_data);
unique_gid_calculation<<<grid, block>>>(d_data);
hipDeviceSynchronize();
hipDeviceReset();
return 0;
} | .text
.file "unique_index_calculation_using_threadIdx_blockIdx_blockDim.hip"
.globl _Z40__device_stub__unique_idx_calc_threadIdxPi # -- Begin function _Z40__device_stub__unique_idx_calc_threadIdxPi
.p2align 4, 0x90
.type _Z40__device_stub__unique_idx_calc_threadIdxPi,@function
_Z40__device_stub__unique_idx_calc_threadIdxPi: # @_Z40__device_stub__unique_idx_calc_threadIdxPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z25unique_idx_calc_threadIdxPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z40__device_stub__unique_idx_calc_threadIdxPi, .Lfunc_end0-_Z40__device_stub__unique_idx_calc_threadIdxPi
.cfi_endproc
# -- End function
.globl _Z37__device_stub__unique_gid_calculationPi # -- Begin function _Z37__device_stub__unique_gid_calculationPi
.p2align 4, 0x90
.type _Z37__device_stub__unique_gid_calculationPi,@function
_Z37__device_stub__unique_gid_calculationPi: # @_Z37__device_stub__unique_gid_calculationPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z22unique_gid_calculationPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z37__device_stub__unique_gid_calculationPi, .Lfunc_end1-_Z37__device_stub__unique_gid_calculationPi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 23 # 0x17
.long 9 # 0x9
.long 4 # 0x4
.long 53 # 0x35
.LCPI2_1:
.long 65 # 0x41
.long 12 # 0xc
.long 1 # 0x1
.long 33 # 0x21
.LCPI2_2:
.long 87 # 0x57
.long 45 # 0x2d
.long 23 # 0x17
.long 12 # 0xc
.LCPI2_3:
.long 342 # 0x156
.long 56 # 0x38
.long 44 # 0x2c
.long 99 # 0x63
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [23,9,4,53]
movaps %xmm0, 80(%rsp)
movaps .LCPI2_1(%rip), %xmm0 # xmm0 = [65,12,1,33]
movaps %xmm0, 96(%rsp)
movaps .LCPI2_2(%rip), %xmm0 # xmm0 = [87,45,23,12]
movaps %xmm0, 112(%rsp)
movaps .LCPI2_3(%rip), %xmm0 # xmm0 = [342,56,44,99]
movaps %xmm0, 128(%rsp)
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB2_1
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z22unique_gid_calculationPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25unique_idx_calc_threadIdxPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22unique_gid_calculationPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25unique_idx_calc_threadIdxPi,@object # @_Z25unique_idx_calc_threadIdxPi
.section .rodata,"a",@progbits
.globl _Z25unique_idx_calc_threadIdxPi
.p2align 3, 0x0
_Z25unique_idx_calc_threadIdxPi:
.quad _Z40__device_stub__unique_idx_calc_threadIdxPi
.size _Z25unique_idx_calc_threadIdxPi, 8
.type _Z22unique_gid_calculationPi,@object # @_Z22unique_gid_calculationPi
.globl _Z22unique_gid_calculationPi
.p2align 3, 0x0
_Z22unique_gid_calculationPi:
.quad _Z37__device_stub__unique_gid_calculationPi
.size _Z22unique_gid_calculationPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z25unique_idx_calc_threadIdxPi"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z22unique_gid_calculationPi"
.size .L__unnamed_2, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n "
.size .Lstr, 3
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__unique_idx_calc_threadIdxPi
.addrsig_sym _Z37__device_stub__unique_gid_calculationPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25unique_idx_calc_threadIdxPi
.addrsig_sym _Z22unique_gid_calculationPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00067464_00000000-6_unique_index_calculation_using_threadIdx_blockIdx_blockDim.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi
.type _Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi, @function
_Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z25unique_idx_calc_threadIdxPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi, .-_Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi
.globl _Z25unique_idx_calc_threadIdxPi
.type _Z25unique_idx_calc_threadIdxPi, @function
_Z25unique_idx_calc_threadIdxPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z25unique_idx_calc_threadIdxPi, .-_Z25unique_idx_calc_threadIdxPi
.globl _Z42__device_stub__Z22unique_gid_calculationPiPi
.type _Z42__device_stub__Z22unique_gid_calculationPiPi, @function
_Z42__device_stub__Z22unique_gid_calculationPiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z22unique_gid_calculationPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z42__device_stub__Z22unique_gid_calculationPiPi, .-_Z42__device_stub__Z22unique_gid_calculationPiPi
.globl _Z22unique_gid_calculationPi
.type _Z22unique_gid_calculationPi, @function
_Z22unique_gid_calculationPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z22unique_gid_calculationPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z22unique_gid_calculationPi, .-_Z22unique_gid_calculationPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $23, 32(%rsp)
movl $9, 36(%rsp)
movl $4, 40(%rsp)
movl $53, 44(%rsp)
movl $65, 48(%rsp)
movl $12, 52(%rsp)
movl $1, 56(%rsp)
movl $33, 60(%rsp)
movl $87, 64(%rsp)
movl $45, 68(%rsp)
movl $23, 72(%rsp)
movl $12, 76(%rsp)
movl $342, 80(%rsp)
movl $56, 84(%rsp)
movl $44, 88(%rsp)
movl $99, 92(%rsp)
leaq 32(%rsp), %rbx
leaq 96(%rsp), %r12
leaq .LC0(%rip), %rbp
.L20:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L20
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 8(%rsp)
movl $1, 12(%rsp)
movl $4, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq (%rsp), %rdi
call _Z42__device_stub__Z22unique_gid_calculationPiPi
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z22unique_gid_calculationPi"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "_Z25unique_idx_calc_threadIdxPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z22unique_gid_calculationPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z25unique_idx_calc_threadIdxPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "unique_index_calculation_using_threadIdx_blockIdx_blockDim.hip"
.globl _Z40__device_stub__unique_idx_calc_threadIdxPi # -- Begin function _Z40__device_stub__unique_idx_calc_threadIdxPi
.p2align 4, 0x90
.type _Z40__device_stub__unique_idx_calc_threadIdxPi,@function
_Z40__device_stub__unique_idx_calc_threadIdxPi: # @_Z40__device_stub__unique_idx_calc_threadIdxPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z25unique_idx_calc_threadIdxPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z40__device_stub__unique_idx_calc_threadIdxPi, .Lfunc_end0-_Z40__device_stub__unique_idx_calc_threadIdxPi
.cfi_endproc
# -- End function
.globl _Z37__device_stub__unique_gid_calculationPi # -- Begin function _Z37__device_stub__unique_gid_calculationPi
.p2align 4, 0x90
.type _Z37__device_stub__unique_gid_calculationPi,@function
_Z37__device_stub__unique_gid_calculationPi: # @_Z37__device_stub__unique_gid_calculationPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z22unique_gid_calculationPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z37__device_stub__unique_gid_calculationPi, .Lfunc_end1-_Z37__device_stub__unique_gid_calculationPi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 23 # 0x17
.long 9 # 0x9
.long 4 # 0x4
.long 53 # 0x35
.LCPI2_1:
.long 65 # 0x41
.long 12 # 0xc
.long 1 # 0x1
.long 33 # 0x21
.LCPI2_2:
.long 87 # 0x57
.long 45 # 0x2d
.long 23 # 0x17
.long 12 # 0xc
.LCPI2_3:
.long 342 # 0x156
.long 56 # 0x38
.long 44 # 0x2c
.long 99 # 0x63
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [23,9,4,53]
movaps %xmm0, 80(%rsp)
movaps .LCPI2_1(%rip), %xmm0 # xmm0 = [65,12,1,33]
movaps %xmm0, 96(%rsp)
movaps .LCPI2_2(%rip), %xmm0 # xmm0 = [87,45,23,12]
movaps %xmm0, 112(%rsp)
movaps .LCPI2_3(%rip), %xmm0 # xmm0 = [342,56,44,99]
movaps %xmm0, 128(%rsp)
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB2_1
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z22unique_gid_calculationPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25unique_idx_calc_threadIdxPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22unique_gid_calculationPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25unique_idx_calc_threadIdxPi,@object # @_Z25unique_idx_calc_threadIdxPi
.section .rodata,"a",@progbits
.globl _Z25unique_idx_calc_threadIdxPi
.p2align 3, 0x0
_Z25unique_idx_calc_threadIdxPi:
.quad _Z40__device_stub__unique_idx_calc_threadIdxPi
.size _Z25unique_idx_calc_threadIdxPi, 8
.type _Z22unique_gid_calculationPi,@object # @_Z22unique_gid_calculationPi
.globl _Z22unique_gid_calculationPi
.p2align 3, 0x0
_Z22unique_gid_calculationPi:
.quad _Z37__device_stub__unique_gid_calculationPi
.size _Z22unique_gid_calculationPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z25unique_idx_calc_threadIdxPi"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z22unique_gid_calculationPi"
.size .L__unnamed_2, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n "
.size .Lstr, 3
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__unique_idx_calc_threadIdxPi
.addrsig_sym _Z37__device_stub__unique_gid_calculationPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25unique_idx_calc_threadIdxPi
.addrsig_sym _Z22unique_gid_calculationPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
int reverseInt(int i) {
unsigned char ch1, ch2, ch3, ch4;
ch1 = i & 255;
ch2 = (i >> 8) & 255;
ch3 = (i >> 16) & 255;
ch4 = (i >> 24) & 255;
return ((int)ch1 << 24) + ((int)ch2 << 16) + ((int)ch3 << 8) + ch4;
}
void readMNIST(const char *imagefile,const char *labelfile, int num_images, int **imagedata, int **labeldata) {
/* read digits */
FILE *file = fopen(imagefile, "r");
if (file == NULL) {
fprintf(stderr, "%s open failure\n", imagefile);
exit(1);
}
int header = 0;
int count = 0;
int num_rows = 0;
int num_cols = 0;
fread(&header, sizeof(header), 1, file);
header = reverseInt(header);
if (header != 2051) {
fprintf(stderr, "Invalid image file header\n");
exit(1);
}
fread(&count, sizeof(count), 1, file);
count = reverseInt(count);
if (count < num_images) {
fprintf(stderr, "Trying to read too many digits\n");
exit(1);
}
fread(&num_rows, sizeof(num_rows), 1, file);
num_rows = reverseInt(num_rows);
fread(&num_cols, sizeof(num_cols), 1, file);
num_cols = reverseInt(num_cols);
/* int **images = (int**)malloc(sizeof(int*) * num_images); */
/* for (int i = 0; i < num_images; i++) { */
/* images[i] = (int*)malloc(sizeof(int) * num_rows * num_cols); */
/* } */
int *images = (int*)malloc(sizeof(int) * num_images * num_rows * num_cols);
int i, j , k;
for (i = 0; i < num_images; i++) {
for (j = 0; j < num_rows; j++) {
for (k = 0; k < num_cols; k++) {
unsigned char temp = 0;
fread(&temp, sizeof(temp), 1, file);
/* images[i][num_rows * j + k] = ((double)temp / 255) > 0.5 ? 1 : 0; */
images[num_rows * num_cols * i + num_rows * j + k] = ((double)temp / 255) > 0.5 ? 1 : 0;
}
}
}
fclose(file);
/* read labes */
file = fopen(labelfile, "r");
if (file == NULL) {
fprintf(stderr, "%s open failure\n", labelfile);
exit(1);
}
fread(&header, sizeof(header), 1, file);
header = reverseInt(header);
if (header != 2049) {
fprintf(stderr, "Invalid label file header\n");
exit(1);
}
fread(&count, sizeof(count), 1, file);
if (count < num_images) {
fprintf(stderr, "Trying to read too many digits\n");
exit(1);
}
int *labels = (int*)malloc(sizeof(int) * num_images);
for (i = 0; i < num_images; i++) {
unsigned char temp = 0;
fread(&temp, sizeof(temp), 1, file);
labels[i] = (int)temp;
}
fclose(file);
*imagedata = images;
*labeldata = labels;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
int reverseInt(int i) {
unsigned char ch1, ch2, ch3, ch4;
ch1 = i & 255;
ch2 = (i >> 8) & 255;
ch3 = (i >> 16) & 255;
ch4 = (i >> 24) & 255;
return ((int)ch1 << 24) + ((int)ch2 << 16) + ((int)ch3 << 8) + ch4;
}
void readMNIST(const char *imagefile,const char *labelfile, int num_images, int **imagedata, int **labeldata) {
/* read digits */
FILE *file = fopen(imagefile, "r");
if (file == NULL) {
fprintf(stderr, "%s open failure\n", imagefile);
exit(1);
}
int header = 0;
int count = 0;
int num_rows = 0;
int num_cols = 0;
fread(&header, sizeof(header), 1, file);
header = reverseInt(header);
if (header != 2051) {
fprintf(stderr, "Invalid image file header\n");
exit(1);
}
fread(&count, sizeof(count), 1, file);
count = reverseInt(count);
if (count < num_images) {
fprintf(stderr, "Trying to read too many digits\n");
exit(1);
}
fread(&num_rows, sizeof(num_rows), 1, file);
num_rows = reverseInt(num_rows);
fread(&num_cols, sizeof(num_cols), 1, file);
num_cols = reverseInt(num_cols);
/* int **images = (int**)malloc(sizeof(int*) * num_images); */
/* for (int i = 0; i < num_images; i++) { */
/* images[i] = (int*)malloc(sizeof(int) * num_rows * num_cols); */
/* } */
int *images = (int*)malloc(sizeof(int) * num_images * num_rows * num_cols);
int i, j , k;
for (i = 0; i < num_images; i++) {
for (j = 0; j < num_rows; j++) {
for (k = 0; k < num_cols; k++) {
unsigned char temp = 0;
fread(&temp, sizeof(temp), 1, file);
/* images[i][num_rows * j + k] = ((double)temp / 255) > 0.5 ? 1 : 0; */
images[num_rows * num_cols * i + num_rows * j + k] = ((double)temp / 255) > 0.5 ? 1 : 0;
}
}
}
fclose(file);
/* read labes */
file = fopen(labelfile, "r");
if (file == NULL) {
fprintf(stderr, "%s open failure\n", labelfile);
exit(1);
}
fread(&header, sizeof(header), 1, file);
header = reverseInt(header);
if (header != 2049) {
fprintf(stderr, "Invalid label file header\n");
exit(1);
}
fread(&count, sizeof(count), 1, file);
if (count < num_images) {
fprintf(stderr, "Trying to read too many digits\n");
exit(1);
}
int *labels = (int*)malloc(sizeof(int) * num_images);
for (i = 0; i < num_images; i++) {
unsigned char temp = 0;
fread(&temp, sizeof(temp), 1, file);
labels[i] = (int)temp;
}
fclose(file);
*imagedata = images;
*labeldata = labels;
} | .file "tmpxft_0009b6ee_00000000-6_utils.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10reverseInti
.type _Z10reverseInti, @function
_Z10reverseInti:
.LFB2057:
.cfi_startproc
endbr64
movl %edi, %eax
sall $8, %eax
andl $16711680, %eax
movl %edi, %edx
sall $24, %edx
addl %edx, %eax
movl %edi, %edx
shrl $8, %edx
andl $65280, %edx
addl %edx, %eax
shrl $24, %edi
addl %edi, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z10reverseInti, .-_Z10reverseInti
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%s open failure\n"
.LC2:
.string "Invalid image file header\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Trying to read too many digits\n"
.section .rodata.str1.1
.LC6:
.string "Invalid label file header\n"
.text
.globl _Z9readMNISTPKcS0_iPPiS2_
.type _Z9readMNISTPKcS0_iPPiS2_, @function
_Z9readMNISTPKcS0_iPPiS2_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %rbx
movq %rsi, (%rsp)
movl %edx, %r15d
movq %rcx, 16(%rsp)
movq %r8, 24(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L29
movq %rax, %r13
movl $0, 40(%rsp)
movl $0, 44(%rsp)
movl $0, 48(%rsp)
movl $0, 52(%rsp)
leaq 40(%rsp), %rdi
movq %rax, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl 40(%rsp), %edi
call _Z10reverseInti
movl %eax, 40(%rsp)
cmpl $2051, %eax
jne .L30
leaq 44(%rsp), %rdi
movq %r13, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl 44(%rsp), %edi
call _Z10reverseInti
movl %eax, 44(%rsp)
cmpl %r15d, %eax
jl .L31
leaq 48(%rsp), %rdi
movq %r13, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl 48(%rsp), %edi
call _Z10reverseInti
movl %eax, 48(%rsp)
leaq 52(%rsp), %rdi
movq %r13, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl 52(%rsp), %edi
call _Z10reverseInti
movl %eax, 52(%rsp)
movslq %r15d, %rsi
movq %rsi, 8(%rsp)
movslq 48(%rsp), %rdi
imulq %rsi, %rdi
cltq
imulq %rax, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r14
movl $0, %r12d
testl %r15d, %r15d
jg .L8
.L9:
movq %r13, %rdi
call fclose@PLT
leaq .LC0(%rip), %rsi
movq (%rsp), %rdi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L32
leaq 40(%rsp), %rdi
movq %rax, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl 40(%rsp), %edi
call _Z10reverseInti
movl %eax, 40(%rsp)
cmpl $2049, %eax
jne .L33
leaq 44(%rsp), %rdi
movq %rbp, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
cmpl %r15d, 44(%rsp)
jl .L34
movq 8(%rsp), %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %r13
testl %r15d, %r15d
jle .L17
movq %rax, %rbx
addq %rax, %r12
leaq 39(%rsp), %r15
.L18:
movb $0, 39(%rsp)
movq %rbp, %r8
movl $1, %ecx
movl $1, %edx
movl $1, %esi
movq %r15, %rdi
call __fread_chk@PLT
movzbl 39(%rsp), %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbx, %r12
jne .L18
.L17:
movq %rbp, %rdi
call fclose@PLT
movq 16(%rsp), %rax
movq %r14, (%rax)
movq 24(%rsp), %rax
movq %r13, (%rax)
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq %rbx, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L10:
movb $0, 39(%rsp)
leaq 39(%rsp), %rdi
movq %r13, %r8
movl $1, %ecx
movl $1, %edx
movl $1, %esi
call __fread_chk@PLT
movl 48(%rsp), %edx
movl 52(%rsp), %ecx
movl %edx, %eax
imull %ecx, %eax
imull %r12d, %eax
imull %ebp, %edx
addl %edx, %eax
addl %ebx, %eax
cltq
movzbl 39(%rsp), %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
divsd .LC4(%rip), %xmm0
comisd .LC5(%rip), %xmm0
seta %dl
movzbl %dl, %edx
movl %edx, (%r14,%rax,4)
addl $1, %ebx
cmpl %ebx, %ecx
jg .L10
.L12:
addl $1, %ebp
cmpl %ebp, 48(%rsp)
jle .L11
.L13:
movl $0, %ebx
cmpl $0, 52(%rsp)
jg .L10
jmp .L12
.L11:
addl $1, %r12d
cmpl %r12d, %r15d
je .L9
.L8:
movl $0, %ebp
cmpl $0, 48(%rsp)
jg .L13
jmp .L11
.L32:
movq (%rsp), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9readMNISTPKcS0_iPPiS2_, .-_Z9readMNISTPKcS0_iPPiS2_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1081073664
.align 8
.LC5:
.long 0
.long 1071644672
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
int reverseInt(int i) {
unsigned char ch1, ch2, ch3, ch4;
ch1 = i & 255;
ch2 = (i >> 8) & 255;
ch3 = (i >> 16) & 255;
ch4 = (i >> 24) & 255;
return ((int)ch1 << 24) + ((int)ch2 << 16) + ((int)ch3 << 8) + ch4;
}
void readMNIST(const char *imagefile,const char *labelfile, int num_images, int **imagedata, int **labeldata) {
/* read digits */
FILE *file = fopen(imagefile, "r");
if (file == NULL) {
fprintf(stderr, "%s open failure\n", imagefile);
exit(1);
}
int header = 0;
int count = 0;
int num_rows = 0;
int num_cols = 0;
fread(&header, sizeof(header), 1, file);
header = reverseInt(header);
if (header != 2051) {
fprintf(stderr, "Invalid image file header\n");
exit(1);
}
fread(&count, sizeof(count), 1, file);
count = reverseInt(count);
if (count < num_images) {
fprintf(stderr, "Trying to read too many digits\n");
exit(1);
}
fread(&num_rows, sizeof(num_rows), 1, file);
num_rows = reverseInt(num_rows);
fread(&num_cols, sizeof(num_cols), 1, file);
num_cols = reverseInt(num_cols);
/* int **images = (int**)malloc(sizeof(int*) * num_images); */
/* for (int i = 0; i < num_images; i++) { */
/* images[i] = (int*)malloc(sizeof(int) * num_rows * num_cols); */
/* } */
int *images = (int*)malloc(sizeof(int) * num_images * num_rows * num_cols);
int i, j , k;
for (i = 0; i < num_images; i++) {
for (j = 0; j < num_rows; j++) {
for (k = 0; k < num_cols; k++) {
unsigned char temp = 0;
fread(&temp, sizeof(temp), 1, file);
/* images[i][num_rows * j + k] = ((double)temp / 255) > 0.5 ? 1 : 0; */
images[num_rows * num_cols * i + num_rows * j + k] = ((double)temp / 255) > 0.5 ? 1 : 0;
}
}
}
fclose(file);
/* read labes */
file = fopen(labelfile, "r");
if (file == NULL) {
fprintf(stderr, "%s open failure\n", labelfile);
exit(1);
}
fread(&header, sizeof(header), 1, file);
header = reverseInt(header);
if (header != 2049) {
fprintf(stderr, "Invalid label file header\n");
exit(1);
}
fread(&count, sizeof(count), 1, file);
if (count < num_images) {
fprintf(stderr, "Trying to read too many digits\n");
exit(1);
}
int *labels = (int*)malloc(sizeof(int) * num_images);
for (i = 0; i < num_images; i++) {
unsigned char temp = 0;
fread(&temp, sizeof(temp), 1, file);
labels[i] = (int)temp;
}
fclose(file);
*imagedata = images;
*labeldata = labels;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int reverseInt(int i) {
unsigned char ch1, ch2, ch3, ch4;
ch1 = i & 255;
ch2 = (i >> 8) & 255;
ch3 = (i >> 16) & 255;
ch4 = (i >> 24) & 255;
return ((int)ch1 << 24) + ((int)ch2 << 16) + ((int)ch3 << 8) + ch4;
}
void readMNIST(const char *imagefile,const char *labelfile, int num_images, int **imagedata, int **labeldata) {
/* read digits */
FILE *file = fopen(imagefile, "r");
if (file == NULL) {
fprintf(stderr, "%s open failure\n", imagefile);
exit(1);
}
int header = 0;
int count = 0;
int num_rows = 0;
int num_cols = 0;
fread(&header, sizeof(header), 1, file);
header = reverseInt(header);
if (header != 2051) {
fprintf(stderr, "Invalid image file header\n");
exit(1);
}
fread(&count, sizeof(count), 1, file);
count = reverseInt(count);
if (count < num_images) {
fprintf(stderr, "Trying to read too many digits\n");
exit(1);
}
fread(&num_rows, sizeof(num_rows), 1, file);
num_rows = reverseInt(num_rows);
fread(&num_cols, sizeof(num_cols), 1, file);
num_cols = reverseInt(num_cols);
/* int **images = (int**)malloc(sizeof(int*) * num_images); */
/* for (int i = 0; i < num_images; i++) { */
/* images[i] = (int*)malloc(sizeof(int) * num_rows * num_cols); */
/* } */
int *images = (int*)malloc(sizeof(int) * num_images * num_rows * num_cols);
int i, j , k;
for (i = 0; i < num_images; i++) {
for (j = 0; j < num_rows; j++) {
for (k = 0; k < num_cols; k++) {
unsigned char temp = 0;
fread(&temp, sizeof(temp), 1, file);
/* images[i][num_rows * j + k] = ((double)temp / 255) > 0.5 ? 1 : 0; */
images[num_rows * num_cols * i + num_rows * j + k] = ((double)temp / 255) > 0.5 ? 1 : 0;
}
}
}
fclose(file);
/* read labes */
file = fopen(labelfile, "r");
if (file == NULL) {
fprintf(stderr, "%s open failure\n", labelfile);
exit(1);
}
fread(&header, sizeof(header), 1, file);
header = reverseInt(header);
if (header != 2049) {
fprintf(stderr, "Invalid label file header\n");
exit(1);
}
fread(&count, sizeof(count), 1, file);
if (count < num_images) {
fprintf(stderr, "Trying to read too many digits\n");
exit(1);
}
int *labels = (int*)malloc(sizeof(int) * num_images);
for (i = 0; i < num_images; i++) {
unsigned char temp = 0;
fread(&temp, sizeof(temp), 1, file);
labels[i] = (int)temp;
}
fclose(file);
*imagedata = images;
*labeldata = labels;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int reverseInt(int i) {
unsigned char ch1, ch2, ch3, ch4;
ch1 = i & 255;
ch2 = (i >> 8) & 255;
ch3 = (i >> 16) & 255;
ch4 = (i >> 24) & 255;
return ((int)ch1 << 24) + ((int)ch2 << 16) + ((int)ch3 << 8) + ch4;
}
void readMNIST(const char *imagefile,const char *labelfile, int num_images, int **imagedata, int **labeldata) {
/* read digits */
FILE *file = fopen(imagefile, "r");
if (file == NULL) {
fprintf(stderr, "%s open failure\n", imagefile);
exit(1);
}
int header = 0;
int count = 0;
int num_rows = 0;
int num_cols = 0;
fread(&header, sizeof(header), 1, file);
header = reverseInt(header);
if (header != 2051) {
fprintf(stderr, "Invalid image file header\n");
exit(1);
}
fread(&count, sizeof(count), 1, file);
count = reverseInt(count);
if (count < num_images) {
fprintf(stderr, "Trying to read too many digits\n");
exit(1);
}
fread(&num_rows, sizeof(num_rows), 1, file);
num_rows = reverseInt(num_rows);
fread(&num_cols, sizeof(num_cols), 1, file);
num_cols = reverseInt(num_cols);
/* int **images = (int**)malloc(sizeof(int*) * num_images); */
/* for (int i = 0; i < num_images; i++) { */
/* images[i] = (int*)malloc(sizeof(int) * num_rows * num_cols); */
/* } */
int *images = (int*)malloc(sizeof(int) * num_images * num_rows * num_cols);
int i, j , k;
for (i = 0; i < num_images; i++) {
for (j = 0; j < num_rows; j++) {
for (k = 0; k < num_cols; k++) {
unsigned char temp = 0;
fread(&temp, sizeof(temp), 1, file);
/* images[i][num_rows * j + k] = ((double)temp / 255) > 0.5 ? 1 : 0; */
images[num_rows * num_cols * i + num_rows * j + k] = ((double)temp / 255) > 0.5 ? 1 : 0;
}
}
}
fclose(file);
/* read labes */
file = fopen(labelfile, "r");
if (file == NULL) {
fprintf(stderr, "%s open failure\n", labelfile);
exit(1);
}
fread(&header, sizeof(header), 1, file);
header = reverseInt(header);
if (header != 2049) {
fprintf(stderr, "Invalid label file header\n");
exit(1);
}
fread(&count, sizeof(count), 1, file);
if (count < num_images) {
fprintf(stderr, "Trying to read too many digits\n");
exit(1);
}
int *labels = (int*)malloc(sizeof(int) * num_images);
for (i = 0; i < num_images; i++) {
unsigned char temp = 0;
fread(&temp, sizeof(temp), 1, file);
labels[i] = (int)temp;
}
fclose(file);
*imagedata = images;
*labeldata = labels;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int reverseInt(int i) {
unsigned char ch1, ch2, ch3, ch4;
ch1 = i & 255;
ch2 = (i >> 8) & 255;
ch3 = (i >> 16) & 255;
ch4 = (i >> 24) & 255;
return ((int)ch1 << 24) + ((int)ch2 << 16) + ((int)ch3 << 8) + ch4;
}
void readMNIST(const char *imagefile,const char *labelfile, int num_images, int **imagedata, int **labeldata) {
/* read digits */
FILE *file = fopen(imagefile, "r");
if (file == NULL) {
fprintf(stderr, "%s open failure\n", imagefile);
exit(1);
}
int header = 0;
int count = 0;
int num_rows = 0;
int num_cols = 0;
fread(&header, sizeof(header), 1, file);
header = reverseInt(header);
if (header != 2051) {
fprintf(stderr, "Invalid image file header\n");
exit(1);
}
fread(&count, sizeof(count), 1, file);
count = reverseInt(count);
if (count < num_images) {
fprintf(stderr, "Trying to read too many digits\n");
exit(1);
}
fread(&num_rows, sizeof(num_rows), 1, file);
num_rows = reverseInt(num_rows);
fread(&num_cols, sizeof(num_cols), 1, file);
num_cols = reverseInt(num_cols);
/* int **images = (int**)malloc(sizeof(int*) * num_images); */
/* for (int i = 0; i < num_images; i++) { */
/* images[i] = (int*)malloc(sizeof(int) * num_rows * num_cols); */
/* } */
int *images = (int*)malloc(sizeof(int) * num_images * num_rows * num_cols);
int i, j , k;
for (i = 0; i < num_images; i++) {
for (j = 0; j < num_rows; j++) {
for (k = 0; k < num_cols; k++) {
unsigned char temp = 0;
fread(&temp, sizeof(temp), 1, file);
/* images[i][num_rows * j + k] = ((double)temp / 255) > 0.5 ? 1 : 0; */
images[num_rows * num_cols * i + num_rows * j + k] = ((double)temp / 255) > 0.5 ? 1 : 0;
}
}
}
fclose(file);
/* read labes */
file = fopen(labelfile, "r");
if (file == NULL) {
fprintf(stderr, "%s open failure\n", labelfile);
exit(1);
}
fread(&header, sizeof(header), 1, file);
header = reverseInt(header);
if (header != 2049) {
fprintf(stderr, "Invalid label file header\n");
exit(1);
}
fread(&count, sizeof(count), 1, file);
if (count < num_images) {
fprintf(stderr, "Trying to read too many digits\n");
exit(1);
}
int *labels = (int*)malloc(sizeof(int) * num_images);
for (i = 0; i < num_images; i++) {
unsigned char temp = 0;
fread(&temp, sizeof(temp), 1, file);
labels[i] = (int)temp;
}
fclose(file);
*imagedata = images;
*labeldata = labels;
} | .text
.file "utils.hip"
.globl _Z10reverseInti # -- Begin function _Z10reverseInti
.p2align 4, 0x90
.type _Z10reverseInti,@function
_Z10reverseInti: # @_Z10reverseInti
.cfi_startproc
# %bb.0:
movl %edi, %eax
bswapl %eax
retq
.Lfunc_end0:
.size _Z10reverseInti, .Lfunc_end0-_Z10reverseInti
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9readMNISTPKcS0_iPPiS2_
.LCPI1_0:
.quad 0x406fe00000000000 # double 255
.LCPI1_1:
.quad 0x3fe0000000000000 # double 0.5
.text
.globl _Z9readMNISTPKcS0_iPPiS2_
.p2align 4, 0x90
.type _Z9readMNISTPKcS0_iPPiS2_,@function
_Z9readMNISTPKcS0_iPPiS2_: # @_Z9readMNISTPKcS0_iPPiS2_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %r14
movq %rcx, %r15
movl %edx, %ebp
movq %rsi, 72(%rsp) # 8-byte Spill
movq %rdi, %rbx
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB1_24
# %bb.1:
movq %rax, %r13
movl $0, 4(%rsp)
movl $0, 8(%rsp)
movl $0, 24(%rsp)
movl $0, 20(%rsp)
leaq 4(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %rax, %rcx
callq fread
movl 4(%rsp), %eax
movl %eax, %ecx
bswapl %ecx
movl %ecx, 4(%rsp)
cmpl $50855936, %eax # imm = 0x3080000
jne .LBB1_2
# %bb.5:
movq %r15, 56(%rsp) # 8-byte Spill
movq %r14, 64(%rsp) # 8-byte Spill
leaq 8(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %r13, %rcx
callq fread
movl 8(%rsp), %eax
bswapl %eax
movl %eax, 8(%rsp)
cmpl %ebp, %eax
jl .LBB1_6
# %bb.7:
leaq 24(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %r13, %rcx
callq fread
movl 24(%rsp), %ebx
bswapl %ebx
movl %ebx, 24(%rsp)
leaq 20(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %r13, %rcx
callq fread
movl 20(%rsp), %edx
bswapl %edx
movl %edx, 20(%rsp)
movslq %ebp, %rcx
shlq $2, %rcx
movl %ebx, 16(%rsp) # 4-byte Spill
movslq %ebx, %rax
movq %rcx, 48(%rsp) # 8-byte Spill
imulq %rcx, %rax
movl %edx, 28(%rsp) # 4-byte Spill
movslq %edx, %rdi
imulq %rax, %rdi
callq malloc
movq %rax, %r12
testl %ebp, %ebp
jle .LBB1_16
# %bb.8: # %.preheader45.lr.ph
movl 28(%rsp), %eax # 4-byte Reload
movl %eax, %ecx
movq %rcx, 80(%rsp) # 8-byte Spill
imull 16(%rsp), %eax # 4-byte Folded Reload
movl %eax, 36(%rsp) # 4-byte Spill
movl $0, 12(%rsp) # 4-byte Folded Spill
leaq 3(%rsp), %r14
xorl %ecx, %ecx
movl %ebp, 40(%rsp) # 4-byte Spill
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_15: # %._crit_edge48
# in Loop: Header=BB1_9 Depth=1
movl 44(%rsp), %ecx # 4-byte Reload
incl %ecx
movl 12(%rsp), %eax # 4-byte Reload
addl 36(%rsp), %eax # 4-byte Folded Reload
movl %eax, 12(%rsp) # 4-byte Spill
movl 40(%rsp), %ebp # 4-byte Reload
cmpl %ebp, %ecx
je .LBB1_16
.LBB1_9: # %.preheader45
# =>This Loop Header: Depth=1
# Child Loop BB1_11 Depth 2
# Child Loop BB1_13 Depth 3
movl %ecx, 44(%rsp) # 4-byte Spill
cmpl $0, 16(%rsp) # 4-byte Folded Reload
jle .LBB1_15
# %bb.10: # %.preheader.lr.ph
# in Loop: Header=BB1_9 Depth=1
xorl %ebp, %ebp
movl 12(%rsp), %eax # 4-byte Reload
movl %eax, 32(%rsp) # 4-byte Spill
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_14: # %._crit_edge
# in Loop: Header=BB1_11 Depth=2
incl %ebp
movl 16(%rsp), %eax # 4-byte Reload
addl %eax, 32(%rsp) # 4-byte Folded Spill
cmpl %eax, %ebp
je .LBB1_15
.LBB1_11: # %.preheader
# Parent Loop BB1_9 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_13 Depth 3
cmpl $0, 28(%rsp) # 4-byte Folded Reload
jle .LBB1_14
# %bb.12: # %.lr.ph
# in Loop: Header=BB1_11 Depth=2
movq 80(%rsp), %r15 # 8-byte Reload
movl 32(%rsp), %eax # 4-byte Reload
movl %eax, %ebx
.p2align 4, 0x90
.LBB1_13: # Parent Loop BB1_9 Depth=1
# Parent Loop BB1_11 Depth=2
# => This Inner Loop Header: Depth=3
movb $0, 3(%rsp)
movl $1, %esi
movl $1, %edx
movq %r14, %rdi
movq %r13, %rcx
callq fread
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
movzbl 3(%rsp), %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
xorl %eax, %eax
ucomisd .LCPI1_1(%rip), %xmm0
seta %al
movslq %ebx, %rbx
movl %eax, (%r12,%rbx,4)
incl %ebx
decq %r15
jne .LBB1_13
jmp .LBB1_14
.LBB1_16: # %._crit_edge50
movq %r13, %rdi
callq fclose
movl $.L.str, %esi
movq 72(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
callq fopen
testq %rax, %rax
je .LBB1_24
# %bb.17:
movq %rax, %r14
leaq 4(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %rax, %rcx
callq fread
movl 4(%rsp), %eax
movl %eax, %ecx
bswapl %ecx
movl %ecx, 4(%rsp)
cmpl $17301504, %eax # imm = 0x1080000
jne .LBB1_18
# %bb.19:
leaq 8(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %r14, %rcx
callq fread
cmpl %ebp, 8(%rsp)
jl .LBB1_6
# %bb.20:
movq 48(%rsp), %rdi # 8-byte Reload
callq malloc
movq %rax, %rbx
testl %ebp, %ebp
jle .LBB1_23
# %bb.21: # %.lr.ph53.preheader
movl %ebp, %r13d
xorl %ebp, %ebp
leaq 3(%rsp), %r15
.p2align 4, 0x90
.LBB1_22: # %.lr.ph53
# =>This Inner Loop Header: Depth=1
movb $0, 3(%rsp)
movl $1, %esi
movl $1, %edx
movq %r15, %rdi
movq %r14, %rcx
callq fread
movzbl 3(%rsp), %eax
movl %eax, (%rbx,%rbp,4)
incq %rbp
cmpq %rbp, %r13
jne .LBB1_22
.LBB1_23: # %._crit_edge54
movq %r14, %rdi
callq fclose
movq 56(%rsp), %rax # 8-byte Reload
movq %r12, (%rax)
movq 64(%rsp), %rax # 8-byte Reload
movq %rbx, (%rax)
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_24:
.cfi_def_cfa_offset 144
movq stderr(%rip), %rdi
movl $.L.str.1, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_6:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $31, %esi
jmp .LBB1_4
.LBB1_2:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
jmp .LBB1_3
.LBB1_18:
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
.LBB1_3:
movl $26, %esi
.LBB1_4:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z9readMNISTPKcS0_iPPiS2_, .Lfunc_end1-_Z9readMNISTPKcS0_iPPiS2_
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s open failure\n"
.size .L.str.1, 17
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Invalid image file header\n"
.size .L.str.2, 27
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Trying to read too many digits\n"
.size .L.str.3, 32
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Invalid label file header\n"
.size .L.str.4, 27
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009b6ee_00000000-6_utils.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10reverseInti
.type _Z10reverseInti, @function
_Z10reverseInti:
.LFB2057:
.cfi_startproc
endbr64
movl %edi, %eax
sall $8, %eax
andl $16711680, %eax
movl %edi, %edx
sall $24, %edx
addl %edx, %eax
movl %edi, %edx
shrl $8, %edx
andl $65280, %edx
addl %edx, %eax
shrl $24, %edi
addl %edi, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z10reverseInti, .-_Z10reverseInti
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%s open failure\n"
.LC2:
.string "Invalid image file header\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Trying to read too many digits\n"
.section .rodata.str1.1
.LC6:
.string "Invalid label file header\n"
.text
.globl _Z9readMNISTPKcS0_iPPiS2_
.type _Z9readMNISTPKcS0_iPPiS2_, @function
_Z9readMNISTPKcS0_iPPiS2_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %rbx
movq %rsi, (%rsp)
movl %edx, %r15d
movq %rcx, 16(%rsp)
movq %r8, 24(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L29
movq %rax, %r13
movl $0, 40(%rsp)
movl $0, 44(%rsp)
movl $0, 48(%rsp)
movl $0, 52(%rsp)
leaq 40(%rsp), %rdi
movq %rax, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl 40(%rsp), %edi
call _Z10reverseInti
movl %eax, 40(%rsp)
cmpl $2051, %eax
jne .L30
leaq 44(%rsp), %rdi
movq %r13, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl 44(%rsp), %edi
call _Z10reverseInti
movl %eax, 44(%rsp)
cmpl %r15d, %eax
jl .L31
leaq 48(%rsp), %rdi
movq %r13, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl 48(%rsp), %edi
call _Z10reverseInti
movl %eax, 48(%rsp)
leaq 52(%rsp), %rdi
movq %r13, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl 52(%rsp), %edi
call _Z10reverseInti
movl %eax, 52(%rsp)
movslq %r15d, %rsi
movq %rsi, 8(%rsp)
movslq 48(%rsp), %rdi
imulq %rsi, %rdi
cltq
imulq %rax, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r14
movl $0, %r12d
testl %r15d, %r15d
jg .L8
.L9:
movq %r13, %rdi
call fclose@PLT
leaq .LC0(%rip), %rsi
movq (%rsp), %rdi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L32
leaq 40(%rsp), %rdi
movq %rax, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl 40(%rsp), %edi
call _Z10reverseInti
movl %eax, 40(%rsp)
cmpl $2049, %eax
jne .L33
leaq 44(%rsp), %rdi
movq %rbp, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
cmpl %r15d, 44(%rsp)
jl .L34
movq 8(%rsp), %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %r13
testl %r15d, %r15d
jle .L17
movq %rax, %rbx
addq %rax, %r12
leaq 39(%rsp), %r15
.L18:
movb $0, 39(%rsp)
movq %rbp, %r8
movl $1, %ecx
movl $1, %edx
movl $1, %esi
movq %r15, %rdi
call __fread_chk@PLT
movzbl 39(%rsp), %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbx, %r12
jne .L18
.L17:
movq %rbp, %rdi
call fclose@PLT
movq 16(%rsp), %rax
movq %r14, (%rax)
movq 24(%rsp), %rax
movq %r13, (%rax)
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq %rbx, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L10:
movb $0, 39(%rsp)
leaq 39(%rsp), %rdi
movq %r13, %r8
movl $1, %ecx
movl $1, %edx
movl $1, %esi
call __fread_chk@PLT
movl 48(%rsp), %edx
movl 52(%rsp), %ecx
movl %edx, %eax
imull %ecx, %eax
imull %r12d, %eax
imull %ebp, %edx
addl %edx, %eax
addl %ebx, %eax
cltq
movzbl 39(%rsp), %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
divsd .LC4(%rip), %xmm0
comisd .LC5(%rip), %xmm0
seta %dl
movzbl %dl, %edx
movl %edx, (%r14,%rax,4)
addl $1, %ebx
cmpl %ebx, %ecx
jg .L10
.L12:
addl $1, %ebp
cmpl %ebp, 48(%rsp)
jle .L11
.L13:
movl $0, %ebx
cmpl $0, 52(%rsp)
jg .L10
jmp .L12
.L11:
addl $1, %r12d
cmpl %r12d, %r15d
je .L9
.L8:
movl $0, %ebp
cmpl $0, 48(%rsp)
jg .L13
jmp .L11
.L32:
movq (%rsp), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9readMNISTPKcS0_iPPiS2_, .-_Z9readMNISTPKcS0_iPPiS2_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1081073664
.align 8
.LC5:
.long 0
.long 1071644672
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "utils.hip"
.globl _Z10reverseInti # -- Begin function _Z10reverseInti
.p2align 4, 0x90
.type _Z10reverseInti,@function
_Z10reverseInti: # @_Z10reverseInti
.cfi_startproc
# %bb.0:
movl %edi, %eax
bswapl %eax
retq
.Lfunc_end0:
.size _Z10reverseInti, .Lfunc_end0-_Z10reverseInti
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9readMNISTPKcS0_iPPiS2_
.LCPI1_0:
.quad 0x406fe00000000000 # double 255
.LCPI1_1:
.quad 0x3fe0000000000000 # double 0.5
.text
.globl _Z9readMNISTPKcS0_iPPiS2_
.p2align 4, 0x90
.type _Z9readMNISTPKcS0_iPPiS2_,@function
_Z9readMNISTPKcS0_iPPiS2_: # @_Z9readMNISTPKcS0_iPPiS2_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %r14
movq %rcx, %r15
movl %edx, %ebp
movq %rsi, 72(%rsp) # 8-byte Spill
movq %rdi, %rbx
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB1_24
# %bb.1:
movq %rax, %r13
movl $0, 4(%rsp)
movl $0, 8(%rsp)
movl $0, 24(%rsp)
movl $0, 20(%rsp)
leaq 4(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %rax, %rcx
callq fread
movl 4(%rsp), %eax
movl %eax, %ecx
bswapl %ecx
movl %ecx, 4(%rsp)
cmpl $50855936, %eax # imm = 0x3080000
jne .LBB1_2
# %bb.5:
movq %r15, 56(%rsp) # 8-byte Spill
movq %r14, 64(%rsp) # 8-byte Spill
leaq 8(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %r13, %rcx
callq fread
movl 8(%rsp), %eax
bswapl %eax
movl %eax, 8(%rsp)
cmpl %ebp, %eax
jl .LBB1_6
# %bb.7:
leaq 24(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %r13, %rcx
callq fread
movl 24(%rsp), %ebx
bswapl %ebx
movl %ebx, 24(%rsp)
leaq 20(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %r13, %rcx
callq fread
movl 20(%rsp), %edx
bswapl %edx
movl %edx, 20(%rsp)
movslq %ebp, %rcx
shlq $2, %rcx
movl %ebx, 16(%rsp) # 4-byte Spill
movslq %ebx, %rax
movq %rcx, 48(%rsp) # 8-byte Spill
imulq %rcx, %rax
movl %edx, 28(%rsp) # 4-byte Spill
movslq %edx, %rdi
imulq %rax, %rdi
callq malloc
movq %rax, %r12
testl %ebp, %ebp
jle .LBB1_16
# %bb.8: # %.preheader45.lr.ph
movl 28(%rsp), %eax # 4-byte Reload
movl %eax, %ecx
movq %rcx, 80(%rsp) # 8-byte Spill
imull 16(%rsp), %eax # 4-byte Folded Reload
movl %eax, 36(%rsp) # 4-byte Spill
movl $0, 12(%rsp) # 4-byte Folded Spill
leaq 3(%rsp), %r14
xorl %ecx, %ecx
movl %ebp, 40(%rsp) # 4-byte Spill
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_15: # %._crit_edge48
# in Loop: Header=BB1_9 Depth=1
movl 44(%rsp), %ecx # 4-byte Reload
incl %ecx
movl 12(%rsp), %eax # 4-byte Reload
addl 36(%rsp), %eax # 4-byte Folded Reload
movl %eax, 12(%rsp) # 4-byte Spill
movl 40(%rsp), %ebp # 4-byte Reload
cmpl %ebp, %ecx
je .LBB1_16
.LBB1_9: # %.preheader45
# =>This Loop Header: Depth=1
# Child Loop BB1_11 Depth 2
# Child Loop BB1_13 Depth 3
movl %ecx, 44(%rsp) # 4-byte Spill
cmpl $0, 16(%rsp) # 4-byte Folded Reload
jle .LBB1_15
# %bb.10: # %.preheader.lr.ph
# in Loop: Header=BB1_9 Depth=1
xorl %ebp, %ebp
movl 12(%rsp), %eax # 4-byte Reload
movl %eax, 32(%rsp) # 4-byte Spill
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_14: # %._crit_edge
# in Loop: Header=BB1_11 Depth=2
incl %ebp
movl 16(%rsp), %eax # 4-byte Reload
addl %eax, 32(%rsp) # 4-byte Folded Spill
cmpl %eax, %ebp
je .LBB1_15
.LBB1_11: # %.preheader
# Parent Loop BB1_9 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_13 Depth 3
cmpl $0, 28(%rsp) # 4-byte Folded Reload
jle .LBB1_14
# %bb.12: # %.lr.ph
# in Loop: Header=BB1_11 Depth=2
movq 80(%rsp), %r15 # 8-byte Reload
movl 32(%rsp), %eax # 4-byte Reload
movl %eax, %ebx
.p2align 4, 0x90
.LBB1_13: # Parent Loop BB1_9 Depth=1
# Parent Loop BB1_11 Depth=2
# => This Inner Loop Header: Depth=3
movb $0, 3(%rsp)
movl $1, %esi
movl $1, %edx
movq %r14, %rdi
movq %r13, %rcx
callq fread
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
movzbl 3(%rsp), %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
xorl %eax, %eax
ucomisd .LCPI1_1(%rip), %xmm0
seta %al
movslq %ebx, %rbx
movl %eax, (%r12,%rbx,4)
incl %ebx
decq %r15
jne .LBB1_13
jmp .LBB1_14
.LBB1_16: # %._crit_edge50
movq %r13, %rdi
callq fclose
movl $.L.str, %esi
movq 72(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
callq fopen
testq %rax, %rax
je .LBB1_24
# %bb.17:
movq %rax, %r14
leaq 4(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %rax, %rcx
callq fread
movl 4(%rsp), %eax
movl %eax, %ecx
bswapl %ecx
movl %ecx, 4(%rsp)
cmpl $17301504, %eax # imm = 0x1080000
jne .LBB1_18
# %bb.19:
leaq 8(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %r14, %rcx
callq fread
cmpl %ebp, 8(%rsp)
jl .LBB1_6
# %bb.20:
movq 48(%rsp), %rdi # 8-byte Reload
callq malloc
movq %rax, %rbx
testl %ebp, %ebp
jle .LBB1_23
# %bb.21: # %.lr.ph53.preheader
movl %ebp, %r13d
xorl %ebp, %ebp
leaq 3(%rsp), %r15
.p2align 4, 0x90
.LBB1_22: # %.lr.ph53
# =>This Inner Loop Header: Depth=1
movb $0, 3(%rsp)
movl $1, %esi
movl $1, %edx
movq %r15, %rdi
movq %r14, %rcx
callq fread
movzbl 3(%rsp), %eax
movl %eax, (%rbx,%rbp,4)
incq %rbp
cmpq %rbp, %r13
jne .LBB1_22
.LBB1_23: # %._crit_edge54
movq %r14, %rdi
callq fclose
movq 56(%rsp), %rax # 8-byte Reload
movq %r12, (%rax)
movq 64(%rsp), %rax # 8-byte Reload
movq %rbx, (%rax)
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_24:
.cfi_def_cfa_offset 144
movq stderr(%rip), %rdi
movl $.L.str.1, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_6:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $31, %esi
jmp .LBB1_4
.LBB1_2:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
jmp .LBB1_3
.LBB1_18:
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
.LBB1_3:
movl $26, %esi
.LBB1_4:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z9readMNISTPKcS0_iPPiS2_, .Lfunc_end1-_Z9readMNISTPKcS0_iPPiS2_
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s open failure\n"
.size .L.str.1, 17
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Invalid image file header\n"
.size .L.str.2, 27
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Trying to read too many digits\n"
.size .L.str.3, 32
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Invalid label file header\n"
.size .L.str.4, 27
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void SweHInit(double *var_in1, double *var_in2, double *var_out, int size) {
// Get thread id
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < size) {
// Transfer data and memory and calculation
var_out[tid] = var_in1[tid] - var_in2[tid];
// Thread id update
tid += blockDim.x * gridDim.x;
}
} | code for sm_80
Function : _Z8SweHInitPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x170] ; /* 0x00005c0000087625 */
/* 0x000fe200078e0209 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0100*/ DADD R6, -R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000102 */
/*0110*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x0011ea000c101b04 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void SweHInit(double *var_in1, double *var_in2, double *var_out, int size) {
// Get thread id
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < size) {
// Transfer data and memory and calculation
var_out[tid] = var_in1[tid] - var_in2[tid];
// Thread id update
tid += blockDim.x * gridDim.x;
}
} | .file "tmpxft_000f0c31_00000000-6_SweHInit.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8SweHInitPdS_S_iPdS_S_i
.type _Z32__device_stub__Z8SweHInitPdS_S_iPdS_S_i, @function
_Z32__device_stub__Z8SweHInitPdS_S_iPdS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8SweHInitPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z8SweHInitPdS_S_iPdS_S_i, .-_Z32__device_stub__Z8SweHInitPdS_S_iPdS_S_i
.globl _Z8SweHInitPdS_S_i
.type _Z8SweHInitPdS_S_i, @function
_Z8SweHInitPdS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8SweHInitPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8SweHInitPdS_S_i, .-_Z8SweHInitPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8SweHInitPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8SweHInitPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void SweHInit(double *var_in1, double *var_in2, double *var_out, int size) {
// Get thread id
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < size) {
// Transfer data and memory and calculation
var_out[tid] = var_in1[tid] - var_in2[tid];
// Thread id update
tid += blockDim.x * gridDim.x;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void SweHInit(double *var_in1, double *var_in2, double *var_out, int size) {
// Get thread id
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < size) {
// Transfer data and memory and calculation
var_out[tid] = var_in1[tid] - var_in2[tid];
// Thread id update
tid += blockDim.x * gridDim.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void SweHInit(double *var_in1, double *var_in2, double *var_out, int size) {
// Get thread id
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < size) {
// Transfer data and memory and calculation
var_out[tid] = var_in1[tid] - var_in2[tid];
// Thread id update
tid += blockDim.x * gridDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8SweHInitPdS_S_i
.globl _Z8SweHInitPdS_S_i
.p2align 8
.type _Z8SweHInitPdS_S_i,@function
_Z8SweHInitPdS_S_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s10, s9
s_mov_b32 s9, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[6:7], v[6:7], off
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], -v[6:7]
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8SweHInitPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8SweHInitPdS_S_i, .Lfunc_end0-_Z8SweHInitPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8SweHInitPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8SweHInitPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void SweHInit(double *var_in1, double *var_in2, double *var_out, int size) {
// Get thread id
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < size) {
// Transfer data and memory and calculation
var_out[tid] = var_in1[tid] - var_in2[tid];
// Thread id update
tid += blockDim.x * gridDim.x;
}
} | .text
.file "SweHInit.hip"
.globl _Z23__device_stub__SweHInitPdS_S_i # -- Begin function _Z23__device_stub__SweHInitPdS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__SweHInitPdS_S_i,@function
_Z23__device_stub__SweHInitPdS_S_i: # @_Z23__device_stub__SweHInitPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8SweHInitPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__SweHInitPdS_S_i, .Lfunc_end0-_Z23__device_stub__SweHInitPdS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8SweHInitPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8SweHInitPdS_S_i,@object # @_Z8SweHInitPdS_S_i
.section .rodata,"a",@progbits
.globl _Z8SweHInitPdS_S_i
.p2align 3, 0x0
_Z8SweHInitPdS_S_i:
.quad _Z23__device_stub__SweHInitPdS_S_i
.size _Z8SweHInitPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8SweHInitPdS_S_i"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__SweHInitPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8SweHInitPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8SweHInitPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x170] ; /* 0x00005c0000087625 */
/* 0x000fe200078e0209 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0100*/ DADD R6, -R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000102 */
/*0110*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x0011ea000c101b04 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8SweHInitPdS_S_i
.globl _Z8SweHInitPdS_S_i
.p2align 8
.type _Z8SweHInitPdS_S_i,@function
_Z8SweHInitPdS_S_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s10, s9
s_mov_b32 s9, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[6:7], v[6:7], off
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], -v[6:7]
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8SweHInitPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8SweHInitPdS_S_i, .Lfunc_end0-_Z8SweHInitPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8SweHInitPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8SweHInitPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f0c31_00000000-6_SweHInit.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8SweHInitPdS_S_iPdS_S_i
.type _Z32__device_stub__Z8SweHInitPdS_S_iPdS_S_i, @function
_Z32__device_stub__Z8SweHInitPdS_S_iPdS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8SweHInitPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z8SweHInitPdS_S_iPdS_S_i, .-_Z32__device_stub__Z8SweHInitPdS_S_iPdS_S_i
.globl _Z8SweHInitPdS_S_i
.type _Z8SweHInitPdS_S_i, @function
_Z8SweHInitPdS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8SweHInitPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8SweHInitPdS_S_i, .-_Z8SweHInitPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8SweHInitPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8SweHInitPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "SweHInit.hip"
.globl _Z23__device_stub__SweHInitPdS_S_i # -- Begin function _Z23__device_stub__SweHInitPdS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__SweHInitPdS_S_i,@function
_Z23__device_stub__SweHInitPdS_S_i: # @_Z23__device_stub__SweHInitPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8SweHInitPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__SweHInitPdS_S_i, .Lfunc_end0-_Z23__device_stub__SweHInitPdS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8SweHInitPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8SweHInitPdS_S_i,@object # @_Z8SweHInitPdS_S_i
.section .rodata,"a",@progbits
.globl _Z8SweHInitPdS_S_i
.p2align 3, 0x0
_Z8SweHInitPdS_S_i:
.quad _Z23__device_stub__SweHInitPdS_S_i
.size _Z8SweHInitPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8SweHInitPdS_S_i"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__SweHInitPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8SweHInitPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <math.h>
//#include <cuda_runtime.h>
// function to copy the elements of an array and decrement to the compiler not override it
__global__
void newtonKernel(int n, float4* x, float4* y, float4* z){
float4 result = make_float4 (1.0f,1.0f,1.0f,1.0f);
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride){
for (int k =0; k < 40; k++){
result.x = result.x * k * x[i].x * y[i].x + x[i].x + y[i].x;
result.y = result.y * k * x[i].y * y[i].y + x[i].y + y[i].y;
result.z = result.z * k * x[i].z * y[i].z + x[i].z + y[i].z;
result.w = result.w * k * x[i].w * y[i].w + x[i].w + y[i].w;
}
z[i] = result ;
y[i].x = z[i].x ;
y[i].y = z[i].y ;
y[i].z = z[i].z ;
y[i].w = z[i].w ;
x[i].x = y[i].x ;
x[i].y = y[i].y ;
x[i].z = y[i].z ;
x[i].w = y[i].w ;
}
}
int main(void){
int N = 1<<20;
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
float4 *x, *y, *z;
//variable allocation on GPU memory
cudaMallocManaged (&x, N*sizeof(float4));
cudaMallocManaged (&y, N* sizeof(float4));
cudaMallocManaged (&z, N*sizeof(float4));
// initialize x and y arrays on the device
//float val = 3.0f;
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = make_float4(1.0f,1.0f,1.0f, 1.0f);
y[i] = make_float4(2.0f,2.0f,2.0f, 2.0f);
z[i] = make_float4(1.0f,1.0f,1.0f, 1.0f);;
}
// Run kernel on 1M parallel elements on the GPU
newtonKernel<<<numBlocks, blockSize>>>(N, x, y, z);
// wait for the GPU to finish the results
cudaDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++){
maxError = fmax(maxError, fabs(x[i].x - 1.0f));
maxError = fmax(maxError, fabs(x[i].y - 1.0f));
maxError = fmax(maxError, fabs(x[i].z - 1.0f));
maxError = fmax(maxError, fabs(x[i].w - 1.0f));
maxError = fmax(maxError, fabs(y[i].x - 1.0f));
maxError = fmax(maxError, fabs(y[i].y - 1.0f));
maxError = fmax(maxError, fabs(y[i].z - 1.0f));
maxError = fmax(maxError, fabs(y[i].w - 1.0f));
maxError = fmax(maxError, fabs(z[i].x - 1.0f));
maxError = fmax(maxError, fabs(z[i].y - 1.0f));
maxError = fmax(maxError, fabs(z[i].z - 1.0f));
maxError = fmax(maxError, fabs(z[i].w - 1.0f));
}
std::cout << "Max error: " << maxError << std::endl;
// Free GPU memory
cudaFree(x);
cudaFree(y);
cudaFree(z);
return 0;
} | .file "tmpxft_0012eff2_00000000-6_24.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z12newtonKerneliP6float4S0_S0_iP6float4S0_S0_
.type _Z45__device_stub__Z12newtonKerneliP6float4S0_S0_iP6float4S0_S0_, @function
_Z45__device_stub__Z12newtonKerneliP6float4S0_S0_iP6float4S0_S0_:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12newtonKerneliP6float4S0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z45__device_stub__Z12newtonKerneliP6float4S0_S0_iP6float4S0_S0_, .-_Z45__device_stub__Z12newtonKerneliP6float4S0_S0_iP6float4S0_S0_
.globl _Z12newtonKerneliP6float4S0_S0_
.type _Z12newtonKerneliP6float4S0_S0_, @function
_Z12newtonKerneliP6float4S0_S0_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z12newtonKerneliP6float4S0_S0_iP6float4S0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z12newtonKerneliP6float4S0_S0_, .-_Z12newtonKerneliP6float4S0_S0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Max error: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
leaq 32(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
leaq 40(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC1(%rip), %xmm0
movss .LC2(%rip), %xmm1
.L12:
movq %rax, %rdx
addq 24(%rsp), %rdx
movss %xmm0, (%rdx)
movss %xmm0, 4(%rdx)
movss %xmm0, 8(%rdx)
movss %xmm0, 12(%rdx)
movq %rax, %rdx
addq 32(%rsp), %rdx
movss %xmm1, (%rdx)
movss %xmm1, 4(%rdx)
movss %xmm1, 8(%rdx)
movss %xmm1, 12(%rdx)
movq %rax, %rdx
addq 40(%rsp), %rdx
movss %xmm0, (%rdx)
movss %xmm0, 4(%rdx)
movss %xmm0, 8(%rdx)
movss %xmm0, 12(%rdx)
addq $16, %rax
cmpq $16777216, %rax
jne .L12
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $4096, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rbx
movq 32(%rsp), %r12
movq 40(%rsp), %rbp
leaq 16777216(%rbx), %r13
movl $0x00000000, 12(%rsp)
.L14:
movss (%rbx), %xmm0
subss .LC1(%rip), %xmm0
andps .LC3(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movaps %xmm0, %xmm1
movss 4(%rbx), %xmm2
subss .LC1(%rip), %xmm2
andps .LC3(%rip), %xmm2
movaps %xmm2, %xmm0
call fmaxf@PLT
movss 8(%rbx), %xmm1
subss .LC1(%rip), %xmm1
andps .LC3(%rip), %xmm1
call fmaxf@PLT
movss 12(%rbx), %xmm1
subss .LC1(%rip), %xmm1
andps .LC3(%rip), %xmm1
call fmaxf@PLT
movss (%r12), %xmm1
subss .LC1(%rip), %xmm1
andps .LC3(%rip), %xmm1
call fmaxf@PLT
movss 4(%r12), %xmm1
subss .LC1(%rip), %xmm1
andps .LC3(%rip), %xmm1
call fmaxf@PLT
movss 8(%r12), %xmm1
subss .LC1(%rip), %xmm1
andps .LC3(%rip), %xmm1
call fmaxf@PLT
movss 12(%r12), %xmm1
subss .LC1(%rip), %xmm1
andps .LC3(%rip), %xmm1
call fmaxf@PLT
movss 0(%rbp), %xmm1
subss .LC1(%rip), %xmm1
andps .LC3(%rip), %xmm1
call fmaxf@PLT
movss 4(%rbp), %xmm1
subss .LC1(%rip), %xmm1
andps .LC3(%rip), %xmm1
call fmaxf@PLT
movss 8(%rbp), %xmm1
subss .LC1(%rip), %xmm1
andps .LC3(%rip), %xmm1
call fmaxf@PLT
movss 12(%rbp), %xmm1
subss .LC1(%rip), %xmm1
andps .LC3(%rip), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $16, %rbx
addq $16, %r12
addq $16, %rbp
cmpq %r13, %rbx
jne .L14
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movl $1048576, %edi
call _Z45__device_stub__Z12newtonKerneliP6float4S0_S0_iP6float4S0_S0_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z12newtonKerneliP6float4S0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z12newtonKerneliP6float4S0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC3:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <math.h>
//#include <cuda_runtime.h>
// function to copy the elements of an array and decrement to the compiler not override it
__global__
void newtonKernel(int n, float4* x, float4* y, float4* z){
float4 result = make_float4 (1.0f,1.0f,1.0f,1.0f);
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride){
for (int k =0; k < 40; k++){
result.x = result.x * k * x[i].x * y[i].x + x[i].x + y[i].x;
result.y = result.y * k * x[i].y * y[i].y + x[i].y + y[i].y;
result.z = result.z * k * x[i].z * y[i].z + x[i].z + y[i].z;
result.w = result.w * k * x[i].w * y[i].w + x[i].w + y[i].w;
}
z[i] = result ;
y[i].x = z[i].x ;
y[i].y = z[i].y ;
y[i].z = z[i].z ;
y[i].w = z[i].w ;
x[i].x = y[i].x ;
x[i].y = y[i].y ;
x[i].z = y[i].z ;
x[i].w = y[i].w ;
}
}
int main(void){
int N = 1<<20;
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
float4 *x, *y, *z;
//variable allocation on GPU memory
cudaMallocManaged (&x, N*sizeof(float4));
cudaMallocManaged (&y, N* sizeof(float4));
cudaMallocManaged (&z, N*sizeof(float4));
// initialize x and y arrays on the device
//float val = 3.0f;
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = make_float4(1.0f,1.0f,1.0f, 1.0f);
y[i] = make_float4(2.0f,2.0f,2.0f, 2.0f);
z[i] = make_float4(1.0f,1.0f,1.0f, 1.0f);;
}
// Run kernel on 1M parallel elements on the GPU
newtonKernel<<<numBlocks, blockSize>>>(N, x, y, z);
// wait for the GPU to finish the results
cudaDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++){
maxError = fmax(maxError, fabs(x[i].x - 1.0f));
maxError = fmax(maxError, fabs(x[i].y - 1.0f));
maxError = fmax(maxError, fabs(x[i].z - 1.0f));
maxError = fmax(maxError, fabs(x[i].w - 1.0f));
maxError = fmax(maxError, fabs(y[i].x - 1.0f));
maxError = fmax(maxError, fabs(y[i].y - 1.0f));
maxError = fmax(maxError, fabs(y[i].z - 1.0f));
maxError = fmax(maxError, fabs(y[i].w - 1.0f));
maxError = fmax(maxError, fabs(z[i].x - 1.0f));
maxError = fmax(maxError, fabs(z[i].y - 1.0f));
maxError = fmax(maxError, fabs(z[i].z - 1.0f));
maxError = fmax(maxError, fabs(z[i].w - 1.0f));
}
std::cout << "Max error: " << maxError << std::endl;
// Free GPU memory
cudaFree(x);
cudaFree(y);
cudaFree(z);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
//#include <cuda_runtime.h>
// function to copy the elements of an array and decrement to the compiler not override it
__global__
void newtonKernel(int n, float4* x, float4* y, float4* z){
float4 result = make_float4 (1.0f,1.0f,1.0f,1.0f);
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride){
for (int k =0; k < 40; k++){
result.x = result.x * k * x[i].x * y[i].x + x[i].x + y[i].x;
result.y = result.y * k * x[i].y * y[i].y + x[i].y + y[i].y;
result.z = result.z * k * x[i].z * y[i].z + x[i].z + y[i].z;
result.w = result.w * k * x[i].w * y[i].w + x[i].w + y[i].w;
}
z[i] = result ;
y[i].x = z[i].x ;
y[i].y = z[i].y ;
y[i].z = z[i].z ;
y[i].w = z[i].w ;
x[i].x = y[i].x ;
x[i].y = y[i].y ;
x[i].z = y[i].z ;
x[i].w = y[i].w ;
}
}
int main(void){
int N = 1<<20;
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
float4 *x, *y, *z;
//variable allocation on GPU memory
hipMallocManaged (&x, N*sizeof(float4));
hipMallocManaged (&y, N* sizeof(float4));
hipMallocManaged (&z, N*sizeof(float4));
// initialize x and y arrays on the device
//float val = 3.0f;
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = make_float4(1.0f,1.0f,1.0f, 1.0f);
y[i] = make_float4(2.0f,2.0f,2.0f, 2.0f);
z[i] = make_float4(1.0f,1.0f,1.0f, 1.0f);;
}
// Run kernel on 1M parallel elements on the GPU
newtonKernel<<<numBlocks, blockSize>>>(N, x, y, z);
// wait for the GPU to finish the results
hipDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++){
maxError = fmax(maxError, fabs(x[i].x - 1.0f));
maxError = fmax(maxError, fabs(x[i].y - 1.0f));
maxError = fmax(maxError, fabs(x[i].z - 1.0f));
maxError = fmax(maxError, fabs(x[i].w - 1.0f));
maxError = fmax(maxError, fabs(y[i].x - 1.0f));
maxError = fmax(maxError, fabs(y[i].y - 1.0f));
maxError = fmax(maxError, fabs(y[i].z - 1.0f));
maxError = fmax(maxError, fabs(y[i].w - 1.0f));
maxError = fmax(maxError, fabs(z[i].x - 1.0f));
maxError = fmax(maxError, fabs(z[i].y - 1.0f));
maxError = fmax(maxError, fabs(z[i].z - 1.0f));
maxError = fmax(maxError, fabs(z[i].w - 1.0f));
}
std::cout << "Max error: " << maxError << std::endl;
// Free GPU memory
hipFree(x);
hipFree(y);
hipFree(z);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
//#include <cuda_runtime.h>
// function to copy the elements of an array and decrement to the compiler not override it
__global__
void newtonKernel(int n, float4* x, float4* y, float4* z){
float4 result = make_float4 (1.0f,1.0f,1.0f,1.0f);
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride){
for (int k =0; k < 40; k++){
result.x = result.x * k * x[i].x * y[i].x + x[i].x + y[i].x;
result.y = result.y * k * x[i].y * y[i].y + x[i].y + y[i].y;
result.z = result.z * k * x[i].z * y[i].z + x[i].z + y[i].z;
result.w = result.w * k * x[i].w * y[i].w + x[i].w + y[i].w;
}
z[i] = result ;
y[i].x = z[i].x ;
y[i].y = z[i].y ;
y[i].z = z[i].z ;
y[i].w = z[i].w ;
x[i].x = y[i].x ;
x[i].y = y[i].y ;
x[i].z = y[i].z ;
x[i].w = y[i].w ;
}
}
int main(void){
int N = 1<<20;
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
float4 *x, *y, *z;
//variable allocation on GPU memory
hipMallocManaged (&x, N*sizeof(float4));
hipMallocManaged (&y, N* sizeof(float4));
hipMallocManaged (&z, N*sizeof(float4));
// initialize x and y arrays on the device
//float val = 3.0f;
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = make_float4(1.0f,1.0f,1.0f, 1.0f);
y[i] = make_float4(2.0f,2.0f,2.0f, 2.0f);
z[i] = make_float4(1.0f,1.0f,1.0f, 1.0f);;
}
// Run kernel on 1M parallel elements on the GPU
newtonKernel<<<numBlocks, blockSize>>>(N, x, y, z);
// wait for the GPU to finish the results
hipDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++){
maxError = fmax(maxError, fabs(x[i].x - 1.0f));
maxError = fmax(maxError, fabs(x[i].y - 1.0f));
maxError = fmax(maxError, fabs(x[i].z - 1.0f));
maxError = fmax(maxError, fabs(x[i].w - 1.0f));
maxError = fmax(maxError, fabs(y[i].x - 1.0f));
maxError = fmax(maxError, fabs(y[i].y - 1.0f));
maxError = fmax(maxError, fabs(y[i].z - 1.0f));
maxError = fmax(maxError, fabs(y[i].w - 1.0f));
maxError = fmax(maxError, fabs(z[i].x - 1.0f));
maxError = fmax(maxError, fabs(z[i].y - 1.0f));
maxError = fmax(maxError, fabs(z[i].z - 1.0f));
maxError = fmax(maxError, fabs(z[i].w - 1.0f));
}
std::cout << "Max error: " << maxError << std::endl;
// Free GPU memory
hipFree(x);
hipFree(y);
hipFree(z);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_
.globl _Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_
.p2align 8
.type _Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_,@function
_Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x0
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[12:13], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v12
s_cbranch_execz .LBB0_5
s_load_b32 s2, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x18
v_mov_b32_e32 v0, 1.0
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v1, v0
v_mov_b32_e32 v2, v0
v_mov_b32_e32 v3, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s9
.LBB0_2:
v_ashrrev_i32_e32 v13, 31, v12
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 4, v[12:13]
v_add_co_u32 v6, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v5, vcc_lo
global_load_b128 v[4:7], v[6:7], off
global_load_b128 v[8:11], v[8:9], off
.p2align 6
.LBB0_3:
v_cvt_f32_i32_e32 v14, s9
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s9, 40
v_mul_f32_e32 v1, v1, v14
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v0, v0, v14 :: v_dual_mul_f32 v1, v1, v5
v_mul_f32_e32 v0, v0, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v1, v1, v9, v5
v_fma_f32 v0, v0, v8, v4
v_mul_f32_e32 v3, v3, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v1, v9, v1 :: v_dual_add_f32 v0, v8, v0
v_dual_mul_f32 v2, v2, v14 :: v_dual_mul_f32 v3, v3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v2, v2, v6
v_fma_f32 v3, v3, v11, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, v2, v10, v6
v_dual_add_f32 v3, v11, v3 :: v_dual_add_f32 v2, v10, v2
s_cbranch_scc0 .LBB0_3
v_lshlrev_b64 v[4:5], 4, v[12:13]
v_add_nc_u32_e32 v12, s2, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v5, vcc_lo
global_store_b128 v[6:7], v[0:3], off
global_load_b32 v10, v[6:7], off
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v12
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
global_store_b32 v[8:9], v10, off
global_load_b32 v11, v[6:7], off offset:4
s_waitcnt vmcnt(0)
global_store_b32 v[8:9], v11, off offset:4
global_load_b32 v11, v[6:7], off offset:8
s_waitcnt vmcnt(0)
global_store_b32 v[8:9], v11, off offset:8
global_load_b32 v6, v[6:7], off offset:12
s_waitcnt vmcnt(0)
global_store_b32 v[8:9], v6, off offset:12
global_store_b32 v[4:5], v10, off
global_load_b32 v6, v[8:9], off offset:4
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v6, off offset:4
global_load_b32 v6, v[8:9], off offset:8
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v6, off offset:8
global_load_b32 v6, v[8:9], off offset:12
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v6, off offset:12
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_, .Lfunc_end0-_Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
//#include <cuda_runtime.h>
// function to copy the elements of an array and decrement to the compiler not override it
__global__
void newtonKernel(int n, float4* x, float4* y, float4* z){
float4 result = make_float4 (1.0f,1.0f,1.0f,1.0f);
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride){
for (int k =0; k < 40; k++){
result.x = result.x * k * x[i].x * y[i].x + x[i].x + y[i].x;
result.y = result.y * k * x[i].y * y[i].y + x[i].y + y[i].y;
result.z = result.z * k * x[i].z * y[i].z + x[i].z + y[i].z;
result.w = result.w * k * x[i].w * y[i].w + x[i].w + y[i].w;
}
z[i] = result ;
y[i].x = z[i].x ;
y[i].y = z[i].y ;
y[i].z = z[i].z ;
y[i].w = z[i].w ;
x[i].x = y[i].x ;
x[i].y = y[i].y ;
x[i].z = y[i].z ;
x[i].w = y[i].w ;
}
}
int main(void){
int N = 1<<20;
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
float4 *x, *y, *z;
//variable allocation on GPU memory
hipMallocManaged (&x, N*sizeof(float4));
hipMallocManaged (&y, N* sizeof(float4));
hipMallocManaged (&z, N*sizeof(float4));
// initialize x and y arrays on the device
//float val = 3.0f;
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = make_float4(1.0f,1.0f,1.0f, 1.0f);
y[i] = make_float4(2.0f,2.0f,2.0f, 2.0f);
z[i] = make_float4(1.0f,1.0f,1.0f, 1.0f);;
}
// Run kernel on 1M parallel elements on the GPU
newtonKernel<<<numBlocks, blockSize>>>(N, x, y, z);
// wait for the GPU to finish the results
hipDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++){
maxError = fmax(maxError, fabs(x[i].x - 1.0f));
maxError = fmax(maxError, fabs(x[i].y - 1.0f));
maxError = fmax(maxError, fabs(x[i].z - 1.0f));
maxError = fmax(maxError, fabs(x[i].w - 1.0f));
maxError = fmax(maxError, fabs(y[i].x - 1.0f));
maxError = fmax(maxError, fabs(y[i].y - 1.0f));
maxError = fmax(maxError, fabs(y[i].z - 1.0f));
maxError = fmax(maxError, fabs(y[i].w - 1.0f));
maxError = fmax(maxError, fabs(z[i].x - 1.0f));
maxError = fmax(maxError, fabs(z[i].y - 1.0f));
maxError = fmax(maxError, fabs(z[i].z - 1.0f));
maxError = fmax(maxError, fabs(z[i].w - 1.0f));
}
std::cout << "Max error: " << maxError << std::endl;
// Free GPU memory
hipFree(x);
hipFree(y);
hipFree(z);
return 0;
} | .text
.file "24.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_ # -- Begin function _Z27__device_stub__newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_
.p2align 4, 0x90
.type _Z27__device_stub__newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_,@function
_Z27__device_stub__newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_: # @_Z27__device_stub__newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_, .Lfunc_end0-_Z27__device_stub__newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xbf800000 # float -1
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $168, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 24(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
movabsq $4575657222473777152, %rcx # imm = 0x3F8000003F800000
movabsq $4611686019501129728, %rdx # imm = 0x4000000040000000
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rsi
movq %rcx, (%rsi,%rax)
movq %rcx, 8(%rsi,%rax)
movq 16(%rsp), %rsi
movq %rdx, (%rsi,%rax)
movq %rdx, 8(%rsi,%rax)
movq 8(%rsp), %rsi
movq %rcx, (%rsi,%rax)
movq %rcx, 8(%rsi,%rax)
addq $16, %rax
cmpq $16777216, %rax # imm = 0x1000000
jne .LBB1_1
# %bb.2:
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $1048576, 36(%rsp) # imm = 0x100000
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
xorps %xmm2, %xmm2
xorl %edx, %edx
movq 8(%rsp), %rsi
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rax,%rdx), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
movss 4(%rax,%rdx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss 8(%rax,%rdx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss 12(%rax,%rdx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss (%rcx,%rdx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss 4(%rcx,%rdx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss 8(%rcx,%rdx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss 12(%rcx,%rdx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss (%rsi,%rdx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss 4(%rsi,%rdx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss 8(%rsi,%rdx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss 12(%rsi,%rdx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
addq $16, %rdx
movaps %xmm5, %xmm2
cmpq $16777216, %rdx # imm = 0x1000000
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
movaps %xmm5, 144(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 144(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB1_10
.LBB1_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_,@object # @_Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_
.section .rodata,"a",@progbits
.globl _Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_
.p2align 3, 0x0
_Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_:
.quad _Z27__device_stub__newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_
.size _Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max error: "
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_"
.size .L__unnamed_1, 49
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012eff2_00000000-6_24.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z12newtonKerneliP6float4S0_S0_iP6float4S0_S0_
.type _Z45__device_stub__Z12newtonKerneliP6float4S0_S0_iP6float4S0_S0_, @function
_Z45__device_stub__Z12newtonKerneliP6float4S0_S0_iP6float4S0_S0_:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12newtonKerneliP6float4S0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z45__device_stub__Z12newtonKerneliP6float4S0_S0_iP6float4S0_S0_, .-_Z45__device_stub__Z12newtonKerneliP6float4S0_S0_iP6float4S0_S0_
.globl _Z12newtonKerneliP6float4S0_S0_
.type _Z12newtonKerneliP6float4S0_S0_, @function
_Z12newtonKerneliP6float4S0_S0_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z12newtonKerneliP6float4S0_S0_iP6float4S0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z12newtonKerneliP6float4S0_S0_, .-_Z12newtonKerneliP6float4S0_S0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Max error: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
leaq 32(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
leaq 40(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC1(%rip), %xmm0
movss .LC2(%rip), %xmm1
.L12:
movq %rax, %rdx
addq 24(%rsp), %rdx
movss %xmm0, (%rdx)
movss %xmm0, 4(%rdx)
movss %xmm0, 8(%rdx)
movss %xmm0, 12(%rdx)
movq %rax, %rdx
addq 32(%rsp), %rdx
movss %xmm1, (%rdx)
movss %xmm1, 4(%rdx)
movss %xmm1, 8(%rdx)
movss %xmm1, 12(%rdx)
movq %rax, %rdx
addq 40(%rsp), %rdx
movss %xmm0, (%rdx)
movss %xmm0, 4(%rdx)
movss %xmm0, 8(%rdx)
movss %xmm0, 12(%rdx)
addq $16, %rax
cmpq $16777216, %rax
jne .L12
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $4096, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rbx
movq 32(%rsp), %r12
movq 40(%rsp), %rbp
leaq 16777216(%rbx), %r13
movl $0x00000000, 12(%rsp)
.L14:
movss (%rbx), %xmm0
subss .LC1(%rip), %xmm0
andps .LC3(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movaps %xmm0, %xmm1
movss 4(%rbx), %xmm2
subss .LC1(%rip), %xmm2
andps .LC3(%rip), %xmm2
movaps %xmm2, %xmm0
call fmaxf@PLT
movss 8(%rbx), %xmm1
subss .LC1(%rip), %xmm1
andps .LC3(%rip), %xmm1
call fmaxf@PLT
movss 12(%rbx), %xmm1
subss .LC1(%rip), %xmm1
andps .LC3(%rip), %xmm1
call fmaxf@PLT
movss (%r12), %xmm1
subss .LC1(%rip), %xmm1
andps .LC3(%rip), %xmm1
call fmaxf@PLT
movss 4(%r12), %xmm1
subss .LC1(%rip), %xmm1
andps .LC3(%rip), %xmm1
call fmaxf@PLT
movss 8(%r12), %xmm1
subss .LC1(%rip), %xmm1
andps .LC3(%rip), %xmm1
call fmaxf@PLT
movss 12(%r12), %xmm1
subss .LC1(%rip), %xmm1
andps .LC3(%rip), %xmm1
call fmaxf@PLT
movss 0(%rbp), %xmm1
subss .LC1(%rip), %xmm1
andps .LC3(%rip), %xmm1
call fmaxf@PLT
movss 4(%rbp), %xmm1
subss .LC1(%rip), %xmm1
andps .LC3(%rip), %xmm1
call fmaxf@PLT
movss 8(%rbp), %xmm1
subss .LC1(%rip), %xmm1
andps .LC3(%rip), %xmm1
call fmaxf@PLT
movss 12(%rbp), %xmm1
subss .LC1(%rip), %xmm1
andps .LC3(%rip), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $16, %rbx
addq $16, %r12
addq $16, %rbp
cmpq %r13, %rbx
jne .L14
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movl $1048576, %edi
call _Z45__device_stub__Z12newtonKerneliP6float4S0_S0_iP6float4S0_S0_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z12newtonKerneliP6float4S0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z12newtonKerneliP6float4S0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC3:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "24.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_ # -- Begin function _Z27__device_stub__newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_
.p2align 4, 0x90
.type _Z27__device_stub__newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_,@function
_Z27__device_stub__newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_: # @_Z27__device_stub__newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_, .Lfunc_end0-_Z27__device_stub__newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xbf800000 # float -1
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $168, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 24(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
movabsq $4575657222473777152, %rcx # imm = 0x3F8000003F800000
movabsq $4611686019501129728, %rdx # imm = 0x4000000040000000
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rsi
movq %rcx, (%rsi,%rax)
movq %rcx, 8(%rsi,%rax)
movq 16(%rsp), %rsi
movq %rdx, (%rsi,%rax)
movq %rdx, 8(%rsi,%rax)
movq 8(%rsp), %rsi
movq %rcx, (%rsi,%rax)
movq %rcx, 8(%rsi,%rax)
addq $16, %rax
cmpq $16777216, %rax # imm = 0x1000000
jne .LBB1_1
# %bb.2:
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $1048576, 36(%rsp) # imm = 0x100000
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
xorps %xmm2, %xmm2
xorl %edx, %edx
movq 8(%rsp), %rsi
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rax,%rdx), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
movss 4(%rax,%rdx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss 8(%rax,%rdx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss 12(%rax,%rdx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss (%rcx,%rdx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss 4(%rcx,%rdx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss 8(%rcx,%rdx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss 12(%rcx,%rdx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss (%rsi,%rdx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss 4(%rsi,%rdx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss 8(%rsi,%rdx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss 12(%rsi,%rdx), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
addq $16, %rdx
movaps %xmm5, %xmm2
cmpq $16777216, %rdx # imm = 0x1000000
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
movaps %xmm5, 144(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 144(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB1_10
.LBB1_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_,@object # @_Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_
.section .rodata,"a",@progbits
.globl _Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_
.p2align 3, 0x0
_Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_:
.quad _Z27__device_stub__newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_
.size _Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max error: "
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_"
.size .L__unnamed_1, 49
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12newtonKerneliP15HIP_vector_typeIfLj4EES1_S1_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdlib>
#include <iostream>
#include <math.h>
#include <ctime>
#include <chrono>
#include <vector>
using namespace std;
#define N 4000
#define count N*N
#define threadsPerBlock 1000
#define numberBlocks N*N/threadsPerBlock
// __device__ int partition(double* input, int start, int end)
// {
// double pivot = input[end];
//
// while(start < end){
// while(input[start] < pivot)
// start++;
// while (input[end] > pivot)
// end--;
// if (input[start] == inpucout<<"time: "<<endTime<<" "<<startTime<<" "<<CLOCKS_PER_SEC<<endl;t[end])
// start++;
// else if(start < end){
// double tmp = input[start];
// input[start] = input[end];
// input[end] = tmp;
// }
// }
// return end;
// }
//
// __device__ double quickSelect(double* input, int p, int r, int k){
// if(p == r){
// return input[p];
// }
// int j = partition(input, p, r);
// int length = j - p + 1;
// if (length == k){
// return input[j];
// }cout<<"time: "<<endTime<<" "<<startTime<<" "<<CLOCKS_PER_SEC<<endl;
// else if( k < length ){
// return quickSelect(input, p, j - 1, k);
// }
// else{
// return quickSelect(input, j + 1, r, k - length);
// }
// }
__device__ void sort(double* input){
for(int i=0;i<5;i++){
for(int j=i;j<5;j++){
if(input[j]<input[i]){
double new_temp = input[i];
input[i] = input[j];
input[j] = new_temp;
}
}
}
}
__global__ void median (double *a, double *b) {
int number = blockIdx.x*blockDim.x + threadIdx.x;
// if((number <N) || (number>=N*N-N)||(number/N==0)||(number/N==N-1)){
// b[number]=a[number];
// }
// if((number > N-1) && (threadIdx.x > 0) && (threadIdx.x < N-1) && (number < N*N-N)){
if((number > N-1) && (number%N > 0) && (number%N < N-1) && (number < N*N-N)){
double tempCompare[5];
tempCompare[0] = a[number];
tempCompare[1] = a[number-1];
tempCompare[2] = a[number+1];
tempCompare[3] = a[number-N];
tempCompare[4] = a[number+N];
// b[number] = quickSelect(tempCompare,0,4,2);
// a[number] = tempCompare[2];
sort(tempCompare);
b[number]=tempCompare[2];
}
else if(number < N*N){
b[number]=a[number];
}
__syncthreads();
}
__global__ void move (double *b, double *a) {
int number = blockIdx.x*blockDim.x + threadIdx.x;
a[number] = b[number];
}
__global__ void reduction (double *in, double *out) {
__shared__ double temp[threadsPerBlock];
int id = threadIdx.x;
temp[id] = in[blockIdx.x*blockDim.x + id];
__syncthreads();
if(id<500 && id>11){
temp[id] += temp[id+500]; __syncthreads();
}
__syncthreads();
if(id<256){
temp[id] += temp[id+256]; __syncthreads();
}
if(id<128){
temp[id] += temp[id+128]; __syncthreads();
}
if(id<64){
temp[id] += temp[id+64]; __syncthreads();
}
if(id<32){
temp[id] += temp[id+32]; __syncthreads();
}
if(id<16){
temp[id] += temp[id+16]; __syncthreads();
}
if(id<8){
temp[id] += temp[id+8]; __syncthreads();
}
if(id<4){
temp[id] += temp[id+4]; __syncthreads();
}
if(id<2){
temp[id] += temp[id+2]; __syncthreads();
}
if(id<1){
temp[id] += temp[id+1]; __syncthreads();
}
if(id<1){out[blockIdx.x] = temp[id];}
}
__global__ void sumGen (double *in, double *out) {
for(int i=0;i<(N/threadsPerBlock)*(N/threadsPerBlock);i++){
out[0]+=in[i];
}
}
__global__ void assign (double *a, double *spe) {
spe[0] = a[count/2+N/2];
spe[1] = a[17*N+31];
}
int main(){
double A[count], B[count];
double sum[1], speNum[2];
double *d_a, *d_b, *d_partSum, *d_ppartSum, *d_sum, *d_speNum;
int size = N*N*sizeof(double);
int twosize = 2*sizeof(double);
sum[0]=0;
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
A[i*N+j] = sin(i*i+j)*sin(i*i+j)+cos(i-j);
// A[i*N+j] = j;
B[i*N+j] = 0;
}
}
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_partSum, size/threadsPerBlock);
cudaMalloc((void **)&d_ppartSum, size/threadsPerBlock/threadsPerBlock);
cudaMalloc((void **)&d_sum, sizeof(double));
cudaMalloc((void **)&d_speNum,twosize);
cudaMemcpy(d_a, A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_sum, sum, sizeof(double), cudaMemcpyHostToDevice);
// clock_t startaaa = clock();
// cudaEvent_t startTime=0, endTime=0;
// cudaEventCreate(&startTime);
// cudaEventCreate(&endTime);
auto start = std::chrono::system_clock::now();
// cudaEventRecord(startTime, 0);
for(int i=0;i<10;i++){
median<<<numberBlocks,threadsPerBlock>>>(d_a,d_b);
cudaDeviceSynchronize();
move<<<numberBlocks,threadsPerBlock>>>(d_b,d_a);
cudaDeviceSynchronize();
}
reduction<<<count/threadsPerBlock, threadsPerBlock>>>(d_a,d_partSum);
reduction<<<(count/threadsPerBlock/threadsPerBlock),threadsPerBlock>>>(d_partSum,d_ppartSum);
sumGen<<<1,1>>>(d_ppartSum,d_sum);
assign<<<1,1>>>(d_a, d_speNum);
cudaDeviceSynchronize();
// clock_t endbbb = clock();
// cudaEventRecord(endTime, 0);
// cudaEventSynchronize(endTime) ;
// float time;
// cudaEventElapsedTime(&time,startTime,endTime);
auto end = std::chrono::system_clock::now();
std::chrono::duration<double> elapsed_seconds = end-start;
cudaMemcpy(sum, d_sum, sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(speNum, d_speNum, twosize, cudaMemcpyDeviceToHost);
cudaMemcpy(B, d_a, size, cudaMemcpyDeviceToHost);
cudaFree(d_a);cudaFree(d_b);cudaFree(d_partSum);cudaFree(d_ppartSum);cudaFree(d_sum);cudaFree(d_speNum);
cout.precision(8);
// cout<<"time: "<<endbbb<<" "<<startaaa<<" "<<CLOCKS_PER_SEC<<endl;
// cout<<"time: "<<(endTime-startTime)/CLOCKS_PER_SEC<<endl;
// cout<<"time: "<<time<<endl;
// cout<<"time: "<<elapsed_seconds<<endl;
printf("time :%f\n",elapsed_seconds);
cout<<"Sum: "<<sum[0]<<endl;
cout<<"A[n/2][n/2]: "<<speNum[0]<<" "<<A[count/2+N/2]<<" "<<B[count/2+N/2]<<endl;
cout<<"A[17][31]: "<<speNum[1]<<" "<<A[17*N+31]<<" "<<B[17*N+31]<<endl;
cout<<"A[999][999]: "<<A[999*N+999]<<" "<<B[999*N+999]<<endl;
cout<<"A[999][500]: "<<A[999*N+500]<<" "<<B[999*N+500]<<endl;
cout<<"A[500][999]: "<<A[500*N+999]<<" "<<B[500*N+999]<<endl;
cout<<"A[500][0]: "<<A[500*N]<<" "<<B[500*N]<<endl;
cout<<"A[501][0]: "<<A[501*N]<<" "<<B[501*N]<<endl;
return 0;
} | code for sm_80
Function : _Z6assignPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000a00 */
/*0020*/ UIADD3 UR4, UP0, UR4, 0x4000000, URZ ; /* 0x0400000004047890 */
/* 0x000fc8000ff1e03f */
/*0030*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*0040*/ MOV R2, UR4 ; /* 0x0000000400027c02 */
/* 0x000fc80008000f00 */
/*0050*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fe2000f8e00ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*0070*/ LDG.E.64 R2, [R2.64+-0x2f3180] ; /* 0xd0ce800402027981 */
/* 0x000ea2000c1e1b00 */
/*0080*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*00a0*/ MOV R6, c[0x0][0x160] ; /* 0x0000580000067a02 */
/* 0x000fe20000000f00 */
/*00b0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff077624 */
/* 0x000fc600078e00ff */
/*00c0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe8000c101b04 */
/*00d0*/ LDG.E.64 R6, [R6.64+0x84df8] ; /* 0x084df80406067981 */
/* 0x000ea8000c1e1b00 */
/*00e0*/ STG.E.64 [R4.64+0x8], R6 ; /* 0x0000080604007986 */
/* 0x004fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6sumGenPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0060*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1b00 */
/*0070*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea4000c1e1b00 */
/*0080*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x004e0e0000000008 */
/*0090*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0011e8000c101b04 */
/*00a0*/ LDG.E.64 R8, [R4.64+0x8] ; /* 0x0000080404087981 */
/* 0x000ea4000c1e1b00 */
/*00b0*/ DADD R8, R6, R8 ; /* 0x0000000006087229 */
/* 0x004e4e0000000008 */
/*00c0*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b04 */
/*00d0*/ LDG.E.64 R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000ea4000c1e1b00 */
/*00e0*/ DADD R10, R8, R10 ; /* 0x00000000080a7229 */
/* 0x004e8e000000000a */
/*00f0*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0045e8000c101b04 */
/*0100*/ LDG.E.64 R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000ee4000c1e1b00 */
/*0110*/ DADD R12, R10, R12 ; /* 0x000000000a0c7229 */
/* 0x008ece000000000c */
/*0120*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0087e8000c101b04 */
/*0130*/ LDG.E.64 R14, [R4.64+0x20] ; /* 0x00002004040e7981 */
/* 0x000f24000c1e1b00 */
/*0140*/ DADD R14, R12, R14 ; /* 0x000000000c0e7229 */
/* 0x010f0e000000000e */
/*0150*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0109e8000c101b04 */
/*0160*/ LDG.E.64 R6, [R4.64+0x28] ; /* 0x0000280404067981 */
/* 0x001f64000c1e1b00 */
/*0170*/ DADD R6, R14, R6 ; /* 0x000000000e067229 */
/* 0x020e0e0000000006 */
/*0180*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0011e8000c101b04 */
/*0190*/ LDG.E.64 R8, [R4.64+0x30] ; /* 0x0000300404087981 */
/* 0x002f64000c1e1b00 */
/*01a0*/ DADD R8, R6, R8 ; /* 0x0000000006087229 */
/* 0x020e4e0000000008 */
/*01b0*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b04 */
/*01c0*/ LDG.E.64 R10, [R4.64+0x38] ; /* 0x00003804040a7981 */
/* 0x004ea4000c1e1b00 */
/*01d0*/ DADD R10, R8, R10 ; /* 0x00000000080a7229 */
/* 0x004e8e000000000a */
/*01e0*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0045e8000c101b04 */
/*01f0*/ LDG.E.64 R12, [R4.64+0x40] ; /* 0x00004004040c7981 */
/* 0x008ee4000c1e1b00 */
/*0200*/ DADD R12, R10, R12 ; /* 0x000000000a0c7229 */
/* 0x008ece000000000c */
/*0210*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0087e8000c101b04 */
/*0220*/ LDG.E.64 R14, [R4.64+0x48] ; /* 0x00004804040e7981 */
/* 0x010f24000c1e1b00 */
/*0230*/ DADD R14, R12, R14 ; /* 0x000000000c0e7229 */
/* 0x010f0e000000000e */
/*0240*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0109e8000c101b04 */
/*0250*/ LDG.E.64 R6, [R4.64+0x50] ; /* 0x0000500404067981 */
/* 0x001f64000c1e1b00 */
/*0260*/ DADD R6, R14, R6 ; /* 0x000000000e067229 */
/* 0x020e0e0000000006 */
/*0270*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0011e8000c101b04 */
/*0280*/ LDG.E.64 R8, [R4.64+0x58] ; /* 0x0000580404087981 */
/* 0x002f64000c1e1b00 */
/*0290*/ DADD R8, R6, R8 ; /* 0x0000000006087229 */
/* 0x020e4e0000000008 */
/*02a0*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe8000c101b04 */
/*02b0*/ LDG.E.64 R10, [R4.64+0x60] ; /* 0x00006004040a7981 */
/* 0x004ea4000c1e1b00 */
/*02c0*/ DADD R10, R8, R10 ; /* 0x00000000080a7229 */
/* 0x004e4e000000000a */
/*02d0*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x002fe8000c101b04 */
/*02e0*/ LDG.E.64 R12, [R4.64+0x68] ; /* 0x00006804040c7981 */
/* 0x008ea4000c1e1b00 */
/*02f0*/ DADD R12, R10, R12 ; /* 0x000000000a0c7229 */
/* 0x004e4e000000000c */
/*0300*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x002fe8000c101b04 */
/*0310*/ LDG.E.64 R14, [R4.64+0x70] ; /* 0x00007004040e7981 */
/* 0x010ea4000c1e1b00 */
/*0320*/ DADD R14, R12, R14 ; /* 0x000000000c0e7229 */
/* 0x004e4e000000000e */
/*0330*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x002fe8000c101b04 */
/*0340*/ LDG.E.64 R6, [R4.64+0x78] ; /* 0x0000780404067981 */
/* 0x001ea4000c1e1b00 */
/*0350*/ DADD R6, R14, R6 ; /* 0x000000000e067229 */
/* 0x004e0e0000000006 */
/*0360*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x001fe2000c101b04 */
/*0370*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0380*/ BRA 0x380; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9reductionPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R0, c[0x0][0x0], R3 ; /* 0x0000000000067a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE.U32 R6, R6, R5, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fcc00078e0005 */
/*0070*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*0080*/ IADD3 R2, R3.reuse, -0xc, RZ ; /* 0xfffffff403027810 */
/* 0x040fe40007ffe0ff */
/*0090*/ ISETP.GT.AND P1, PT, R3, 0xff, PT ; /* 0x000000ff0300780c */
/* 0x000fe40003f24270 */
/*00a0*/ ISETP.GT.U32.AND P0, PT, R2, 0x1e7, PT ; /* 0x000001e70200780c */
/* 0x000fe20003f04070 */
/*00b0*/ STS.64 [R3.X8], R6 ; /* 0x0000000603007388 */
/* 0x004fe80000008a00 */
/*00c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00d0*/ @!P0 WARPSYNC 0xffffffff ; /* 0xffffffff00008948 */
/* 0x000fe20003800000 */
/*00e0*/ @!P0 LDS.64 R8, [R3.X8] ; /* 0x0000000003088984 */
/* 0x000fe80000008a00 */
/*00f0*/ @!P0 LDS.64 R10, [R3.X8+0xfa0] ; /* 0x000fa000030a8984 */
/* 0x000e240000008a00 */
/*0100*/ @!P0 DADD R8, R8, R10 ; /* 0x0000000008088229 */
/* 0x001e0e000000000a */
/*0110*/ @!P0 STS.64 [R3.X8], R8 ; /* 0x0000000803008388 */
/* 0x001fe80000008a00 */
/*0120*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fec0000010000 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0140*/ ISETP.GT.AND P0, PT, R3, 0x7f, PT ; /* 0x0000007f0300780c */
/* 0x000fca0003f04270 */
/*0150*/ @!P1 WARPSYNC 0xffffffff ; /* 0xffffffff00009948 */
/* 0x000fe20003800000 */
/*0160*/ @!P1 LDS.64 R10, [R3.X8] ; /* 0x00000000030a9984 */
/* 0x000fe80000008a00 */
/*0170*/ @!P1 LDS.64 R6, [R3.X8+0x800] ; /* 0x0008000003069984 */
/* 0x000e240000008a00 */
/*0180*/ @!P1 DADD R6, R10, R6 ; /* 0x000000000a069229 */
/* 0x001e0e0000000006 */
/*0190*/ @!P1 STS.64 [R3.X8], R6 ; /* 0x0000000603009388 */
/* 0x001fe80000008a00 */
/*01a0*/ @!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000009b1d */
/* 0x000fe20000010000 */
/*01b0*/ ISETP.GT.AND P1, PT, R3, 0x3f, PT ; /* 0x0000003f0300780c */
/* 0x000fca0003f24270 */
/*01c0*/ @!P0 WARPSYNC 0xffffffff ; /* 0xffffffff00008948 */
/* 0x000fe20003800000 */
/*01d0*/ @!P0 LDS.64 R10, [R3.X8] ; /* 0x00000000030a8984 */
/* 0x000fe80000008a00 */
/*01e0*/ @!P0 LDS.64 R8, [R3.X8+0x400] ; /* 0x0004000003088984 */
/* 0x000e240000008a00 */
/*01f0*/ @!P0 DADD R8, R10, R8 ; /* 0x000000000a088229 */
/* 0x001e0e0000000008 */
/*0200*/ @!P0 STS.64 [R3.X8], R8 ; /* 0x0000000803008388 */
/* 0x001fe80000008a00 */
/*0210*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fe20000010000 */
/*0220*/ ISETP.GT.AND P0, PT, R3, 0x1f, PT ; /* 0x0000001f0300780c */
/* 0x000fca0003f04270 */
/*0230*/ @!P1 WARPSYNC 0xffffffff ; /* 0xffffffff00009948 */
/* 0x000fe20003800000 */
/*0240*/ @!P1 LDS.64 R10, [R3.X8] ; /* 0x00000000030a9984 */
/* 0x000fe80000008a00 */
/*0250*/ @!P1 LDS.64 R12, [R3.X8+0x200] ; /* 0x00020000030c9984 */
/* 0x000e240000008a00 */
/*0260*/ @!P1 DADD R10, R10, R12 ; /* 0x000000000a0a9229 */
/* 0x001e0e000000000c */
/*0270*/ @!P1 STS.64 [R3.X8], R10 ; /* 0x0000000a03009388 */
/* 0x001fe80000008a00 */
/*0280*/ @!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000009b1d */
/* 0x000fe20000010000 */
/*0290*/ ISETP.GT.AND P1, PT, R3, 0xf, PT ; /* 0x0000000f0300780c */
/* 0x000fca0003f24270 */
/*02a0*/ @!P0 WARPSYNC 0xffffffff ; /* 0xffffffff00008948 */
/* 0x000fe20003800000 */
/*02b0*/ @!P0 LDS.64 R6, [R3.X8] ; /* 0x0000000003068984 */
/* 0x000fe80000008a00 */
/*02c0*/ @!P0 LDS.64 R12, [R3.X8+0x100] ; /* 0x00010000030c8984 */
/* 0x000e240000008a00 */
/*02d0*/ @!P0 DADD R6, R6, R12 ; /* 0x0000000006068229 */
/* 0x001e0e000000000c */
/*02e0*/ @!P0 STS.64 [R3.X8], R6 ; /* 0x0000000603008388 */
/* 0x001fe80000008a00 */
/*02f0*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fe20000010000 */
/*0300*/ ISETP.GT.AND P0, PT, R3, 0x7, PT ; /* 0x000000070300780c */
/* 0x000fca0003f04270 */
/*0310*/ @!P1 WARPSYNC 0xffffffff ; /* 0xffffffff00009948 */
/* 0x000fe20003800000 */
/*0320*/ @!P1 LDS.64 R8, [R3.X8] ; /* 0x0000000003089984 */
/* 0x000fe80000008a00 */
/*0330*/ @!P1 LDS.64 R12, [R3.X8+0x80] ; /* 0x00008000030c9984 */
/* 0x000e240000008a00 */
/*0340*/ @!P1 DADD R8, R8, R12 ; /* 0x0000000008089229 */
/* 0x001e0e000000000c */
/*0350*/ @!P1 STS.64 [R3.X8], R8 ; /* 0x0000000803009388 */
/* 0x001fe80000008a00 */
/*0360*/ @!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000009b1d */
/* 0x000fe20000010000 */
/*0370*/ ISETP.GT.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fca0003f24270 */
/*0380*/ @!P0 WARPSYNC 0xffffffff ; /* 0xffffffff00008948 */
/* 0x000fe20003800000 */
/*0390*/ @!P0 LDS.64 R10, [R3.X8] ; /* 0x00000000030a8984 */
/* 0x000fe80000008a00 */
/*03a0*/ @!P0 LDS.64 R12, [R3.X8+0x40] ; /* 0x00004000030c8984 */
/* 0x000e240000008a00 */
/*03b0*/ @!P0 DADD R10, R10, R12 ; /* 0x000000000a0a8229 */
/* 0x001e0e000000000c */
/*03c0*/ @!P0 STS.64 [R3.X8], R10 ; /* 0x0000000a03008388 */
/* 0x001fe80000008a00 */
/*03d0*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fe20000010000 */
/*03e0*/ ISETP.GT.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fca0003f04270 */
/*03f0*/ @!P1 WARPSYNC 0xffffffff ; /* 0xffffffff00009948 */
/* 0x000fe20003800000 */
/*0400*/ @!P1 LDS.64 R6, [R3.X8] ; /* 0x0000000003069984 */
/* 0x000fe80000008a00 */
/*0410*/ @!P1 LDS.64 R12, [R3.X8+0x20] ; /* 0x00002000030c9984 */
/* 0x000e240000008a00 */
/*0420*/ @!P1 DADD R6, R6, R12 ; /* 0x0000000006069229 */
/* 0x001e0e000000000c */
/*0430*/ @!P1 STS.64 [R3.X8], R6 ; /* 0x0000000603009388 */
/* 0x001fe80000008a00 */
/*0440*/ @!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000009b1d */
/* 0x000fe20000010000 */
/*0450*/ ISETP.GT.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fca0003f24270 */
/*0460*/ @!P0 WARPSYNC 0xffffffff ; /* 0xffffffff00008948 */
/* 0x000fe20003800000 */
/*0470*/ @!P0 LDS.64 R8, [R3.X8] ; /* 0x0000000003088984 */
/* 0x000fe80000008a00 */
/*0480*/ @!P0 LDS.64 R12, [R3.X8+0x10] ; /* 0x00001000030c8984 */
/* 0x000e240000008a00 */
/*0490*/ @!P0 DADD R8, R8, R12 ; /* 0x0000000008088229 */
/* 0x001e0e000000000c */
/*04a0*/ @!P0 STS.64 [R3.X8], R8 ; /* 0x0000000803008388 */
/* 0x0011e80000008a00 */
/*04b0*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fec0000010000 */
/*04c0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*04d0*/ LDS.64 R6, [R3.X8] ; /* 0x0000000003067984 */
/* 0x001fe20000008a00 */
/*04e0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*04f0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe200078e0005 */
/*0500*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0510*/ LDS.64 R8, [R3.X8+0x8] ; /* 0x0000080003087984 */
/* 0x000e240000008a00 */
/*0520*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x001e0e0000000008 */
/*0530*/ STS.64 [R3.X8], R6 ; /* 0x0000000603007388 */
/* 0x001fe80000008a00 */
/*0540*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0550*/ LDS.64 R8, [R3.X8] ; /* 0x0000000003087984 */
/* 0x000e280000008a00 */
/*0560*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x001fe2000c101b04 */
/*0570*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0580*/ BRA 0x580; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4movePdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*0090*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6medianPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x420 ; /* 0x000003e000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0.reuse, 0xfa0, PT ; /* 0x00000fa00000780c */
/* 0x040fe40003f06270 */
/*0070*/ ISETP.LT.AND P1, PT, R0, 0xf41460, PT ; /* 0x00f414600000780c */
/* 0x000fd60003f21270 */
/*0080*/ @P0 IMAD.WIDE.U32 R2, R0, 0x10624dd3, RZ ; /* 0x10624dd300020825 */
/* 0x000fca00078e00ff */
/*0090*/ @P0 SHF.R.U32.HI R3, RZ, 0x8, R3 ; /* 0x00000008ff030819 */
/* 0x000fca0000011603 */
/*00a0*/ @P0 IMAD R2, R3, -0xfa0, R0 ; /* 0xfffff06003020824 */
/* 0x000fe400078e0200 */
/*00b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc600078e00ff */
/*00c0*/ @P0 IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02020810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD.WIDE R6, R0, R3, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc600078e0203 */
/*00e0*/ ISETP.LT.U32.AND P0, PT, R2, 0xf9e, P0 ; /* 0x00000f9e0200780c */
/* 0x000fe20000701070 */
/*00f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fd800078e0203 */
/*0100*/ @P0 BRA P1, 0x160 ; /* 0x0000005000000947 */
/* 0x000fea0000800000 */
/*0110*/ ISETP.GT.AND P0, PT, R0, 0xf423ff, PT ; /* 0x00f423ff0000780c */
/* 0x000fda0003f04270 */
/*0120*/ @P0 BRA 0x410 ; /* 0x000002e000000947 */
/* 0x000fea0003800000 */
/*0130*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1b00 */
/*0140*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0041e2000c101b04 */
/*0150*/ BRA 0x410 ; /* 0x000002b000007947 */
/* 0x000fea0003800000 */
/*0160*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea8000c1e1b00 */
/*0170*/ LDG.E.64 R10, [R6.64+-0x8] ; /* 0xfffff804060a7981 */
/* 0x000ea8000c1e1b00 */
/*0180*/ LDG.E.64 R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ee8000c1e1b00 */
/*0190*/ LDG.E.64 R14, [R6.64+-0x7d00] ; /* 0xff830004060e7981 */
/* 0x000f28000c1e1b00 */
/*01a0*/ LDG.E.64 R4, [R6.64+0x7d00] ; /* 0x007d000406047981 */
/* 0x000162000c1e1b00 */
/*01b0*/ DSETP.GEU.AND P0, PT, R10, R8, PT ; /* 0x000000080a00722a */
/* 0x004e4c0003f0e000 */
/*01c0*/ FSEL R16, R10, R8, !P0 ; /* 0x000000080a107208 */
/* 0x002fe40004000000 */
/*01d0*/ FSEL R17, R11, R9, !P0 ; /* 0x000000090b117208 */
/* 0x000fe40004000000 */
/*01e0*/ FSEL R18, R8, R10, !P0 ; /* 0x0000000a08127208 */
/* 0x000fe40004000000 */
/*01f0*/ FSEL R19, R9, R11, !P0 ; /* 0x0000000b09137208 */
/* 0x000fe40004000000 */
/*0200*/ DSETP.GEU.AND P1, PT, R12, R16, PT ; /* 0x000000100c00722a */
/* 0x008e4c0003f2e000 */
/*0210*/ FSEL R10, R16, R12, !P1 ; /* 0x0000000c100a7208 */
/* 0x002fe40004800000 */
/*0220*/ FSEL R11, R17, R13, !P1 ; /* 0x0000000d110b7208 */
/* 0x000fe40004800000 */
/*0230*/ FSEL R8, R12, R16, !P1 ; /* 0x000000100c087208 */
/* 0x000fe40004800000 */
/*0240*/ FSEL R9, R13, R17, !P1 ; /* 0x000000110d097208 */
/* 0x000fe40004800000 */
/*0250*/ DSETP.GEU.AND P0, PT, R10, R18, PT ; /* 0x000000120a00722a */
/* 0x000e480003f0e000 */
/*0260*/ DSETP.GEU.AND P1, PT, R14, R8, PT ; /* 0x000000080e00722a */
/* 0x010ea40003f2e000 */
/*0270*/ FSEL R16, R10, R18, !P0 ; /* 0x000000120a107208 */
/* 0x002fe40004000000 */
/*0280*/ FSEL R17, R11, R19, !P0 ; /* 0x000000130b117208 */
/* 0x000fe40004000000 */
/*0290*/ FSEL R12, R8, R14, !P1 ; /* 0x0000000e080c7208 */
/* 0x004fe40004800000 */
/*02a0*/ FSEL R13, R9, R15, !P1 ; /* 0x0000000f090d7208 */
/* 0x000fe40004800000 */
/*02b0*/ FSEL R6, R14, R8, !P1 ; /* 0x000000080e067208 */
/* 0x001fc40004800000 */
/*02c0*/ FSEL R7, R15, R9, !P1 ; /* 0x000000090f077208 */
/* 0x000fe40004800000 */
/*02d0*/ DSETP.GEU.AND P2, PT, R12, R16, PT ; /* 0x000000100c00722a */
/* 0x000e220003f4e000 */
/*02e0*/ FSEL R14, R18, R10, !P0 ; /* 0x0000000a120e7208 */
/* 0x000fe40004000000 */
/*02f0*/ FSEL R15, R19, R11, !P0 ; /* 0x0000000b130f7208 */
/* 0x000fe20004000000 */
/*0300*/ DSETP.GEU.AND P1, PT, R4, R6, PT ; /* 0x000000060400722a */
/* 0x020e640003f2e000 */
/*0310*/ FSEL R10, R16, R12, !P2 ; /* 0x0000000c100a7208 */
/* 0x001fe40005000000 */
/*0320*/ FSEL R8, R12, R16, !P2 ; /* 0x000000100c087208 */
/* 0x000fc40005000000 */
/*0330*/ FSEL R11, R17, R13, !P2 ; /* 0x0000000d110b7208 */
/* 0x000fe40005000000 */
/*0340*/ FSEL R9, R13, R17, !P2 ; /* 0x000000110d097208 */
/* 0x000fe40005000000 */
/*0350*/ FSEL R4, R6, R4, !P1 ; /* 0x0000000406047208 */
/* 0x002fe40004800000 */
/*0360*/ FSEL R5, R7, R5, !P1 ; /* 0x0000000507057208 */
/* 0x000fe20004800000 */
/*0370*/ DSETP.GEU.AND P1, PT, R10, R14, PT ; /* 0x0000000e0a00722a */
/* 0x000e0a0003f2e000 */
/*0380*/ DSETP.GEU.AND P0, PT, R4, R8, PT ; /* 0x000000080400722a */
/* 0x000e620003f0e000 */
/*0390*/ FSEL R6, R10, R14, !P1 ; /* 0x0000000e0a067208 */
/* 0x001fe40004800000 */
/*03a0*/ FSEL R7, R11, R15, !P1 ; /* 0x0000000f0b077208 */
/* 0x000fc60004800000 */
/*03b0*/ FSEL R4, R8, R4, !P0 ; /* 0x0000000408047208 */
/* 0x002fe40004000000 */
/*03c0*/ FSEL R5, R9, R5, !P0 ; /* 0x0000000509057208 */
/* 0x000fcc0004000000 */
/*03d0*/ DSETP.GEU.AND P0, PT, R4, R6, PT ; /* 0x000000060400722a */
/* 0x000e0c0003f0e000 */
/*03e0*/ FSEL R4, R4, R6, !P0 ; /* 0x0000000604047208 */
/* 0x001fe40004000000 */
/*03f0*/ FSEL R5, R5, R7, !P0 ; /* 0x0000000705057208 */
/* 0x000fca0004000000 */
/*0400*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0001e4000c101b04 */
/*0410*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0420*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0430*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0440*/ BRA 0x440; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdlib>
#include <iostream>
#include <math.h>
#include <ctime>
#include <chrono>
#include <vector>
using namespace std;
#define N 4000
#define count N*N
#define threadsPerBlock 1000
#define numberBlocks N*N/threadsPerBlock
// __device__ int partition(double* input, int start, int end)
// {
// double pivot = input[end];
//
// while(start < end){
// while(input[start] < pivot)
// start++;
// while (input[end] > pivot)
// end--;
// if (input[start] == inpucout<<"time: "<<endTime<<" "<<startTime<<" "<<CLOCKS_PER_SEC<<endl;t[end])
// start++;
// else if(start < end){
// double tmp = input[start];
// input[start] = input[end];
// input[end] = tmp;
// }
// }
// return end;
// }
//
// __device__ double quickSelect(double* input, int p, int r, int k){
// if(p == r){
// return input[p];
// }
// int j = partition(input, p, r);
// int length = j - p + 1;
// if (length == k){
// return input[j];
// }cout<<"time: "<<endTime<<" "<<startTime<<" "<<CLOCKS_PER_SEC<<endl;
// else if( k < length ){
// return quickSelect(input, p, j - 1, k);
// }
// else{
// return quickSelect(input, j + 1, r, k - length);
// }
// }
__device__ void sort(double* input){
for(int i=0;i<5;i++){
for(int j=i;j<5;j++){
if(input[j]<input[i]){
double new_temp = input[i];
input[i] = input[j];
input[j] = new_temp;
}
}
}
}
__global__ void median (double *a, double *b) {
int number = blockIdx.x*blockDim.x + threadIdx.x;
// if((number <N) || (number>=N*N-N)||(number/N==0)||(number/N==N-1)){
// b[number]=a[number];
// }
// if((number > N-1) && (threadIdx.x > 0) && (threadIdx.x < N-1) && (number < N*N-N)){
if((number > N-1) && (number%N > 0) && (number%N < N-1) && (number < N*N-N)){
double tempCompare[5];
tempCompare[0] = a[number];
tempCompare[1] = a[number-1];
tempCompare[2] = a[number+1];
tempCompare[3] = a[number-N];
tempCompare[4] = a[number+N];
// b[number] = quickSelect(tempCompare,0,4,2);
// a[number] = tempCompare[2];
sort(tempCompare);
b[number]=tempCompare[2];
}
else if(number < N*N){
b[number]=a[number];
}
__syncthreads();
}
__global__ void move (double *b, double *a) {
int number = blockIdx.x*blockDim.x + threadIdx.x;
a[number] = b[number];
}
__global__ void reduction (double *in, double *out) {
__shared__ double temp[threadsPerBlock];
int id = threadIdx.x;
temp[id] = in[blockIdx.x*blockDim.x + id];
__syncthreads();
if(id<500 && id>11){
temp[id] += temp[id+500]; __syncthreads();
}
__syncthreads();
if(id<256){
temp[id] += temp[id+256]; __syncthreads();
}
if(id<128){
temp[id] += temp[id+128]; __syncthreads();
}
if(id<64){
temp[id] += temp[id+64]; __syncthreads();
}
if(id<32){
temp[id] += temp[id+32]; __syncthreads();
}
if(id<16){
temp[id] += temp[id+16]; __syncthreads();
}
if(id<8){
temp[id] += temp[id+8]; __syncthreads();
}
if(id<4){
temp[id] += temp[id+4]; __syncthreads();
}
if(id<2){
temp[id] += temp[id+2]; __syncthreads();
}
if(id<1){
temp[id] += temp[id+1]; __syncthreads();
}
if(id<1){out[blockIdx.x] = temp[id];}
}
__global__ void sumGen (double *in, double *out) {
for(int i=0;i<(N/threadsPerBlock)*(N/threadsPerBlock);i++){
out[0]+=in[i];
}
}
__global__ void assign (double *a, double *spe) {
spe[0] = a[count/2+N/2];
spe[1] = a[17*N+31];
}
int main(){
double A[count], B[count];
double sum[1], speNum[2];
double *d_a, *d_b, *d_partSum, *d_ppartSum, *d_sum, *d_speNum;
int size = N*N*sizeof(double);
int twosize = 2*sizeof(double);
sum[0]=0;
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
A[i*N+j] = sin(i*i+j)*sin(i*i+j)+cos(i-j);
// A[i*N+j] = j;
B[i*N+j] = 0;
}
}
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_partSum, size/threadsPerBlock);
cudaMalloc((void **)&d_ppartSum, size/threadsPerBlock/threadsPerBlock);
cudaMalloc((void **)&d_sum, sizeof(double));
cudaMalloc((void **)&d_speNum,twosize);
cudaMemcpy(d_a, A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_sum, sum, sizeof(double), cudaMemcpyHostToDevice);
// clock_t startaaa = clock();
// cudaEvent_t startTime=0, endTime=0;
// cudaEventCreate(&startTime);
// cudaEventCreate(&endTime);
auto start = std::chrono::system_clock::now();
// cudaEventRecord(startTime, 0);
for(int i=0;i<10;i++){
median<<<numberBlocks,threadsPerBlock>>>(d_a,d_b);
cudaDeviceSynchronize();
move<<<numberBlocks,threadsPerBlock>>>(d_b,d_a);
cudaDeviceSynchronize();
}
reduction<<<count/threadsPerBlock, threadsPerBlock>>>(d_a,d_partSum);
reduction<<<(count/threadsPerBlock/threadsPerBlock),threadsPerBlock>>>(d_partSum,d_ppartSum);
sumGen<<<1,1>>>(d_ppartSum,d_sum);
assign<<<1,1>>>(d_a, d_speNum);
cudaDeviceSynchronize();
// clock_t endbbb = clock();
// cudaEventRecord(endTime, 0);
// cudaEventSynchronize(endTime) ;
// float time;
// cudaEventElapsedTime(&time,startTime,endTime);
auto end = std::chrono::system_clock::now();
std::chrono::duration<double> elapsed_seconds = end-start;
cudaMemcpy(sum, d_sum, sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(speNum, d_speNum, twosize, cudaMemcpyDeviceToHost);
cudaMemcpy(B, d_a, size, cudaMemcpyDeviceToHost);
cudaFree(d_a);cudaFree(d_b);cudaFree(d_partSum);cudaFree(d_ppartSum);cudaFree(d_sum);cudaFree(d_speNum);
cout.precision(8);
// cout<<"time: "<<endbbb<<" "<<startaaa<<" "<<CLOCKS_PER_SEC<<endl;
// cout<<"time: "<<(endTime-startTime)/CLOCKS_PER_SEC<<endl;
// cout<<"time: "<<time<<endl;
// cout<<"time: "<<elapsed_seconds<<endl;
printf("time :%f\n",elapsed_seconds);
cout<<"Sum: "<<sum[0]<<endl;
cout<<"A[n/2][n/2]: "<<speNum[0]<<" "<<A[count/2+N/2]<<" "<<B[count/2+N/2]<<endl;
cout<<"A[17][31]: "<<speNum[1]<<" "<<A[17*N+31]<<" "<<B[17*N+31]<<endl;
cout<<"A[999][999]: "<<A[999*N+999]<<" "<<B[999*N+999]<<endl;
cout<<"A[999][500]: "<<A[999*N+500]<<" "<<B[999*N+500]<<endl;
cout<<"A[500][999]: "<<A[500*N+999]<<" "<<B[500*N+999]<<endl;
cout<<"A[500][0]: "<<A[500*N]<<" "<<B[500*N]<<endl;
cout<<"A[501][0]: "<<A[501*N]<<" "<<B[501*N]<<endl;
return 0;
} | .file "tmpxft_000b5214_00000000-6_p5test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4138:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4138:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4sortPd
.type _Z4sortPd, @function
_Z4sortPd:
.LFB4131:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4131:
.size _Z4sortPd, .-_Z4sortPd
.globl _Z27__device_stub__Z6medianPdS_PdS_
.type _Z27__device_stub__Z6medianPdS_PdS_, @function
_Z27__device_stub__Z6medianPdS_PdS_:
.LFB4160:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6medianPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4160:
.size _Z27__device_stub__Z6medianPdS_PdS_, .-_Z27__device_stub__Z6medianPdS_PdS_
.globl _Z6medianPdS_
.type _Z6medianPdS_, @function
_Z6medianPdS_:
.LFB4161:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6medianPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4161:
.size _Z6medianPdS_, .-_Z6medianPdS_
.globl _Z25__device_stub__Z4movePdS_PdS_
.type _Z25__device_stub__Z4movePdS_PdS_, @function
_Z25__device_stub__Z4movePdS_PdS_:
.LFB4162:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4movePdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4162:
.size _Z25__device_stub__Z4movePdS_PdS_, .-_Z25__device_stub__Z4movePdS_PdS_
.globl _Z4movePdS_
.type _Z4movePdS_, @function
_Z4movePdS_:
.LFB4163:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4movePdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4163:
.size _Z4movePdS_, .-_Z4movePdS_
.globl _Z30__device_stub__Z9reductionPdS_PdS_
.type _Z30__device_stub__Z9reductionPdS_PdS_, @function
_Z30__device_stub__Z9reductionPdS_PdS_:
.LFB4164:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9reductionPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4164:
.size _Z30__device_stub__Z9reductionPdS_PdS_, .-_Z30__device_stub__Z9reductionPdS_PdS_
.globl _Z9reductionPdS_
.type _Z9reductionPdS_, @function
_Z9reductionPdS_:
.LFB4165:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9reductionPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4165:
.size _Z9reductionPdS_, .-_Z9reductionPdS_
.globl _Z27__device_stub__Z6sumGenPdS_PdS_
.type _Z27__device_stub__Z6sumGenPdS_PdS_, @function
_Z27__device_stub__Z6sumGenPdS_PdS_:
.LFB4166:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6sumGenPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4166:
.size _Z27__device_stub__Z6sumGenPdS_PdS_, .-_Z27__device_stub__Z6sumGenPdS_PdS_
.globl _Z6sumGenPdS_
.type _Z6sumGenPdS_, @function
_Z6sumGenPdS_:
.LFB4167:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6sumGenPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4167:
.size _Z6sumGenPdS_, .-_Z6sumGenPdS_
.globl _Z27__device_stub__Z6assignPdS_PdS_
.type _Z27__device_stub__Z6assignPdS_PdS_, @function
_Z27__device_stub__Z6assignPdS_PdS_:
.LFB4168:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6assignPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4168:
.size _Z27__device_stub__Z6assignPdS_PdS_, .-_Z27__device_stub__Z6assignPdS_PdS_
.globl _Z6assignPdS_
.type _Z6assignPdS_, @function
_Z6assignPdS_:
.LFB4169:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6assignPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4169:
.size _Z6assignPdS_, .-_Z6assignPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "time :%f\n"
.LC3:
.string "Sum: "
.LC4:
.string "A[n/2][n/2]: "
.LC5:
.string " "
.LC6:
.string "A[17][31]: "
.LC7:
.string "A[999][999]: "
.LC8:
.string "A[999][500]: "
.LC9:
.string "A[500][999]: "
.LC10:
.string "A[500][0]: "
.LC11:
.string "A[501][0]: "
.text
.globl main
.type main, @function
main:
.LFB4132:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -256000000(%rsp), %r11
.cfi_def_cfa 11, 256000056
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $136, %rsp
.cfi_def_cfa_offset 256000192
movq %fs:40, %rax
movq %rax, 256000120(%rsp)
xorl %eax, %eax
movq $0x000000000, 88(%rsp)
movl $0, %r15d
movl $0, %r14d
.L46:
movl %r14d, %r12d
imull %r14d, %r12d
leal 4000(%r12), %r13d
movq %r15, %rbp
movl %r12d, %ebx
addl %r14d, %r12d
.L47:
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
call sin@PLT
movsd %xmm0, 8(%rsp)
movl %r12d, %eax
subl %ebx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
call cos@PLT
movapd %xmm0, %xmm1
movsd 8(%rsp), %xmm0
mulsd %xmm0, %xmm0
addsd %xmm1, %xmm0
movsd %xmm0, 112(%rsp,%rbp)
movq $0x000000000, 128000112(%rsp,%rbp)
addl $1, %ebx
addq $8, %rbp
cmpl %r13d, %ebx
jne .L47
addl $1, %r14d
addq $32000, %r15
cmpl $4000, %r14d
jne .L46
leaq 16(%rsp), %rdi
movl $128000000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $128000000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $128000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $128000000, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 88(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl $10, %ebp
jmp .L51
.L61:
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z27__device_stub__Z6medianPdS_PdS_
jmp .L49
.L50:
call cudaDeviceSynchronize@PLT
subl $1, %ebp
je .L60
.L51:
movl $1000, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $16000, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L61
.L49:
call cudaDeviceSynchronize@PLT
movl $1000, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $16000, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L50
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z25__device_stub__Z4movePdS_PdS_
jmp .L50
.L60:
movl $1000, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $16000, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L52:
movl $1000, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $16, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L63
.L53:
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L64
.L54:
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L55:
call cudaDeviceSynchronize@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC1(%rip), %xmm0
movq %xmm0, %rbx
leaq 88(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq 48(%rsp), %rsi
call cudaMemcpy@PLT
leaq 96(%rsp), %rdi
movl $2, %ecx
movl $16, %edx
movq 56(%rsp), %rsi
call cudaMemcpy@PLT
leaq 128000112(%rsp), %rdi
movl $2, %ecx
movl $128000000, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
leaq _ZSt4cout(%rip), %rbp
movq $8, 16+_ZSt4cout(%rip)
movq %rbx, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 88(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC4(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 96(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rbx
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 64016112(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 192016112(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC6(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 104(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 544360(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 128544360(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC7(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 31976104(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 159976104(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC8(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 31972112(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 159972112(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC9(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 16008104(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 144008104(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC10(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 16000112(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 144000112(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC11(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 16032112(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 144032112(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 256000120(%rsp), %rax
subq %fs:40, %rax
jne .L66
movl $0, %eax
addq $256000136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
movq 32(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z9reductionPdS_PdS_
jmp .L52
.L63:
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z30__device_stub__Z9reductionPdS_PdS_
jmp .L53
.L64:
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z27__device_stub__Z6sumGenPdS_PdS_
jmp .L54
.L65:
movq 56(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z27__device_stub__Z6assignPdS_PdS_
jmp .L55
.L66:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4132:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z6assignPdS_"
.LC13:
.string "_Z6sumGenPdS_"
.LC14:
.string "_Z9reductionPdS_"
.LC15:
.string "_Z4movePdS_"
.LC16:
.string "_Z6medianPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4171:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z6assignPdS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z6sumGenPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reductionPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z4movePdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z6medianPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4171:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdlib>
#include <iostream>
#include <math.h>
#include <ctime>
#include <chrono>
#include <vector>
using namespace std;
#define N 4000
#define count N*N
#define threadsPerBlock 1000
#define numberBlocks N*N/threadsPerBlock
// __device__ int partition(double* input, int start, int end)
// {
// double pivot = input[end];
//
// while(start < end){
// while(input[start] < pivot)
// start++;
// while (input[end] > pivot)
// end--;
// if (input[start] == inpucout<<"time: "<<endTime<<" "<<startTime<<" "<<CLOCKS_PER_SEC<<endl;t[end])
// start++;
// else if(start < end){
// double tmp = input[start];
// input[start] = input[end];
// input[end] = tmp;
// }
// }
// return end;
// }
//
// __device__ double quickSelect(double* input, int p, int r, int k){
// if(p == r){
// return input[p];
// }
// int j = partition(input, p, r);
// int length = j - p + 1;
// if (length == k){
// return input[j];
// }cout<<"time: "<<endTime<<" "<<startTime<<" "<<CLOCKS_PER_SEC<<endl;
// else if( k < length ){
// return quickSelect(input, p, j - 1, k);
// }
// else{
// return quickSelect(input, j + 1, r, k - length);
// }
// }
__device__ void sort(double* input){
for(int i=0;i<5;i++){
for(int j=i;j<5;j++){
if(input[j]<input[i]){
double new_temp = input[i];
input[i] = input[j];
input[j] = new_temp;
}
}
}
}
__global__ void median (double *a, double *b) {
int number = blockIdx.x*blockDim.x + threadIdx.x;
// if((number <N) || (number>=N*N-N)||(number/N==0)||(number/N==N-1)){
// b[number]=a[number];
// }
// if((number > N-1) && (threadIdx.x > 0) && (threadIdx.x < N-1) && (number < N*N-N)){
if((number > N-1) && (number%N > 0) && (number%N < N-1) && (number < N*N-N)){
double tempCompare[5];
tempCompare[0] = a[number];
tempCompare[1] = a[number-1];
tempCompare[2] = a[number+1];
tempCompare[3] = a[number-N];
tempCompare[4] = a[number+N];
// b[number] = quickSelect(tempCompare,0,4,2);
// a[number] = tempCompare[2];
sort(tempCompare);
b[number]=tempCompare[2];
}
else if(number < N*N){
b[number]=a[number];
}
__syncthreads();
}
__global__ void move (double *b, double *a) {
int number = blockIdx.x*blockDim.x + threadIdx.x;
a[number] = b[number];
}
__global__ void reduction (double *in, double *out) {
__shared__ double temp[threadsPerBlock];
int id = threadIdx.x;
temp[id] = in[blockIdx.x*blockDim.x + id];
__syncthreads();
if(id<500 && id>11){
temp[id] += temp[id+500]; __syncthreads();
}
__syncthreads();
if(id<256){
temp[id] += temp[id+256]; __syncthreads();
}
if(id<128){
temp[id] += temp[id+128]; __syncthreads();
}
if(id<64){
temp[id] += temp[id+64]; __syncthreads();
}
if(id<32){
temp[id] += temp[id+32]; __syncthreads();
}
if(id<16){
temp[id] += temp[id+16]; __syncthreads();
}
if(id<8){
temp[id] += temp[id+8]; __syncthreads();
}
if(id<4){
temp[id] += temp[id+4]; __syncthreads();
}
if(id<2){
temp[id] += temp[id+2]; __syncthreads();
}
if(id<1){
temp[id] += temp[id+1]; __syncthreads();
}
if(id<1){out[blockIdx.x] = temp[id];}
}
__global__ void sumGen (double *in, double *out) {
for(int i=0;i<(N/threadsPerBlock)*(N/threadsPerBlock);i++){
out[0]+=in[i];
}
}
__global__ void assign (double *a, double *spe) {
spe[0] = a[count/2+N/2];
spe[1] = a[17*N+31];
}
int main(){
double A[count], B[count];
double sum[1], speNum[2];
double *d_a, *d_b, *d_partSum, *d_ppartSum, *d_sum, *d_speNum;
int size = N*N*sizeof(double);
int twosize = 2*sizeof(double);
sum[0]=0;
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
A[i*N+j] = sin(i*i+j)*sin(i*i+j)+cos(i-j);
// A[i*N+j] = j;
B[i*N+j] = 0;
}
}
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_partSum, size/threadsPerBlock);
cudaMalloc((void **)&d_ppartSum, size/threadsPerBlock/threadsPerBlock);
cudaMalloc((void **)&d_sum, sizeof(double));
cudaMalloc((void **)&d_speNum,twosize);
cudaMemcpy(d_a, A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_sum, sum, sizeof(double), cudaMemcpyHostToDevice);
// clock_t startaaa = clock();
// cudaEvent_t startTime=0, endTime=0;
// cudaEventCreate(&startTime);
// cudaEventCreate(&endTime);
auto start = std::chrono::system_clock::now();
// cudaEventRecord(startTime, 0);
for(int i=0;i<10;i++){
median<<<numberBlocks,threadsPerBlock>>>(d_a,d_b);
cudaDeviceSynchronize();
move<<<numberBlocks,threadsPerBlock>>>(d_b,d_a);
cudaDeviceSynchronize();
}
reduction<<<count/threadsPerBlock, threadsPerBlock>>>(d_a,d_partSum);
reduction<<<(count/threadsPerBlock/threadsPerBlock),threadsPerBlock>>>(d_partSum,d_ppartSum);
sumGen<<<1,1>>>(d_ppartSum,d_sum);
assign<<<1,1>>>(d_a, d_speNum);
cudaDeviceSynchronize();
// clock_t endbbb = clock();
// cudaEventRecord(endTime, 0);
// cudaEventSynchronize(endTime) ;
// float time;
// cudaEventElapsedTime(&time,startTime,endTime);
auto end = std::chrono::system_clock::now();
std::chrono::duration<double> elapsed_seconds = end-start;
cudaMemcpy(sum, d_sum, sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(speNum, d_speNum, twosize, cudaMemcpyDeviceToHost);
cudaMemcpy(B, d_a, size, cudaMemcpyDeviceToHost);
cudaFree(d_a);cudaFree(d_b);cudaFree(d_partSum);cudaFree(d_ppartSum);cudaFree(d_sum);cudaFree(d_speNum);
cout.precision(8);
// cout<<"time: "<<endbbb<<" "<<startaaa<<" "<<CLOCKS_PER_SEC<<endl;
// cout<<"time: "<<(endTime-startTime)/CLOCKS_PER_SEC<<endl;
// cout<<"time: "<<time<<endl;
// cout<<"time: "<<elapsed_seconds<<endl;
printf("time :%f\n",elapsed_seconds);
cout<<"Sum: "<<sum[0]<<endl;
cout<<"A[n/2][n/2]: "<<speNum[0]<<" "<<A[count/2+N/2]<<" "<<B[count/2+N/2]<<endl;
cout<<"A[17][31]: "<<speNum[1]<<" "<<A[17*N+31]<<" "<<B[17*N+31]<<endl;
cout<<"A[999][999]: "<<A[999*N+999]<<" "<<B[999*N+999]<<endl;
cout<<"A[999][500]: "<<A[999*N+500]<<" "<<B[999*N+500]<<endl;
cout<<"A[500][999]: "<<A[500*N+999]<<" "<<B[500*N+999]<<endl;
cout<<"A[500][0]: "<<A[500*N]<<" "<<B[500*N]<<endl;
cout<<"A[501][0]: "<<A[501*N]<<" "<<B[501*N]<<endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <cstdlib>
#include <iostream>
#include <math.h>
#include <ctime>
#include <chrono>
#include <vector>
using namespace std;
#define N 4000
#define count N*N
#define threadsPerBlock 1000
#define numberBlocks N*N/threadsPerBlock
// __device__ int partition(double* input, int start, int end)
// {
// double pivot = input[end];
//
// while(start < end){
// while(input[start] < pivot)
// start++;
// while (input[end] > pivot)
// end--;
// if (input[start] == inpucout<<"time: "<<endTime<<" "<<startTime<<" "<<CLOCKS_PER_SEC<<endl;t[end])
// start++;
// else if(start < end){
// double tmp = input[start];
// input[start] = input[end];
// input[end] = tmp;
// }
// }
// return end;
// }
//
// __device__ double quickSelect(double* input, int p, int r, int k){
// if(p == r){
// return input[p];
// }
// int j = partition(input, p, r);
// int length = j - p + 1;
// if (length == k){
// return input[j];
// }cout<<"time: "<<endTime<<" "<<startTime<<" "<<CLOCKS_PER_SEC<<endl;
// else if( k < length ){
// return quickSelect(input, p, j - 1, k);
// }
// else{
// return quickSelect(input, j + 1, r, k - length);
// }
// }
__device__ void sort(double* input){
for(int i=0;i<5;i++){
for(int j=i;j<5;j++){
if(input[j]<input[i]){
double new_temp = input[i];
input[i] = input[j];
input[j] = new_temp;
}
}
}
}
__global__ void median (double *a, double *b) {
int number = blockIdx.x*blockDim.x + threadIdx.x;
// if((number <N) || (number>=N*N-N)||(number/N==0)||(number/N==N-1)){
// b[number]=a[number];
// }
// if((number > N-1) && (threadIdx.x > 0) && (threadIdx.x < N-1) && (number < N*N-N)){
if((number > N-1) && (number%N > 0) && (number%N < N-1) && (number < N*N-N)){
double tempCompare[5];
tempCompare[0] = a[number];
tempCompare[1] = a[number-1];
tempCompare[2] = a[number+1];
tempCompare[3] = a[number-N];
tempCompare[4] = a[number+N];
// b[number] = quickSelect(tempCompare,0,4,2);
// a[number] = tempCompare[2];
sort(tempCompare);
b[number]=tempCompare[2];
}
else if(number < N*N){
b[number]=a[number];
}
__syncthreads();
}
__global__ void move (double *b, double *a) {
int number = blockIdx.x*blockDim.x + threadIdx.x;
a[number] = b[number];
}
__global__ void reduction (double *in, double *out) {
__shared__ double temp[threadsPerBlock];
int id = threadIdx.x;
temp[id] = in[blockIdx.x*blockDim.x + id];
__syncthreads();
if(id<500 && id>11){
temp[id] += temp[id+500]; __syncthreads();
}
__syncthreads();
if(id<256){
temp[id] += temp[id+256]; __syncthreads();
}
if(id<128){
temp[id] += temp[id+128]; __syncthreads();
}
if(id<64){
temp[id] += temp[id+64]; __syncthreads();
}
if(id<32){
temp[id] += temp[id+32]; __syncthreads();
}
if(id<16){
temp[id] += temp[id+16]; __syncthreads();
}
if(id<8){
temp[id] += temp[id+8]; __syncthreads();
}
if(id<4){
temp[id] += temp[id+4]; __syncthreads();
}
if(id<2){
temp[id] += temp[id+2]; __syncthreads();
}
if(id<1){
temp[id] += temp[id+1]; __syncthreads();
}
if(id<1){out[blockIdx.x] = temp[id];}
}
__global__ void sumGen (double *in, double *out) {
for(int i=0;i<(N/threadsPerBlock)*(N/threadsPerBlock);i++){
out[0]+=in[i];
}
}
__global__ void assign (double *a, double *spe) {
spe[0] = a[count/2+N/2];
spe[1] = a[17*N+31];
}
int main(){
double A[count], B[count];
double sum[1], speNum[2];
double *d_a, *d_b, *d_partSum, *d_ppartSum, *d_sum, *d_speNum;
int size = N*N*sizeof(double);
int twosize = 2*sizeof(double);
sum[0]=0;
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
A[i*N+j] = sin(i*i+j)*sin(i*i+j)+cos(i-j);
// A[i*N+j] = j;
B[i*N+j] = 0;
}
}
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_partSum, size/threadsPerBlock);
hipMalloc((void **)&d_ppartSum, size/threadsPerBlock/threadsPerBlock);
hipMalloc((void **)&d_sum, sizeof(double));
hipMalloc((void **)&d_speNum,twosize);
hipMemcpy(d_a, A, size, hipMemcpyHostToDevice);
hipMemcpy(d_sum, sum, sizeof(double), hipMemcpyHostToDevice);
// clock_t startaaa = clock();
// cudaEvent_t startTime=0, endTime=0;
// cudaEventCreate(&startTime);
// cudaEventCreate(&endTime);
auto start = std::chrono::system_clock::now();
// cudaEventRecord(startTime, 0);
for(int i=0;i<10;i++){
median<<<numberBlocks,threadsPerBlock>>>(d_a,d_b);
hipDeviceSynchronize();
move<<<numberBlocks,threadsPerBlock>>>(d_b,d_a);
hipDeviceSynchronize();
}
reduction<<<count/threadsPerBlock, threadsPerBlock>>>(d_a,d_partSum);
reduction<<<(count/threadsPerBlock/threadsPerBlock),threadsPerBlock>>>(d_partSum,d_ppartSum);
sumGen<<<1,1>>>(d_ppartSum,d_sum);
assign<<<1,1>>>(d_a, d_speNum);
hipDeviceSynchronize();
// clock_t endbbb = clock();
// cudaEventRecord(endTime, 0);
// cudaEventSynchronize(endTime) ;
// float time;
// cudaEventElapsedTime(&time,startTime,endTime);
auto end = std::chrono::system_clock::now();
std::chrono::duration<double> elapsed_seconds = end-start;
hipMemcpy(sum, d_sum, sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(speNum, d_speNum, twosize, hipMemcpyDeviceToHost);
hipMemcpy(B, d_a, size, hipMemcpyDeviceToHost);
hipFree(d_a);hipFree(d_b);hipFree(d_partSum);hipFree(d_ppartSum);hipFree(d_sum);hipFree(d_speNum);
cout.precision(8);
// cout<<"time: "<<endbbb<<" "<<startaaa<<" "<<CLOCKS_PER_SEC<<endl;
// cout<<"time: "<<(endTime-startTime)/CLOCKS_PER_SEC<<endl;
// cout<<"time: "<<time<<endl;
// cout<<"time: "<<elapsed_seconds<<endl;
printf("time :%f\n",elapsed_seconds);
cout<<"Sum: "<<sum[0]<<endl;
cout<<"A[n/2][n/2]: "<<speNum[0]<<" "<<A[count/2+N/2]<<" "<<B[count/2+N/2]<<endl;
cout<<"A[17][31]: "<<speNum[1]<<" "<<A[17*N+31]<<" "<<B[17*N+31]<<endl;
cout<<"A[999][999]: "<<A[999*N+999]<<" "<<B[999*N+999]<<endl;
cout<<"A[999][500]: "<<A[999*N+500]<<" "<<B[999*N+500]<<endl;
cout<<"A[500][999]: "<<A[500*N+999]<<" "<<B[500*N+999]<<endl;
cout<<"A[500][0]: "<<A[500*N]<<" "<<B[500*N]<<endl;
cout<<"A[501][0]: "<<A[501*N]<<" "<<B[501*N]<<endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdlib>
#include <iostream>
#include <math.h>
#include <ctime>
#include <chrono>
#include <vector>
using namespace std;
#define N 4000
#define count N*N
#define threadsPerBlock 1000
#define numberBlocks N*N/threadsPerBlock
// __device__ int partition(double* input, int start, int end)
// {
// double pivot = input[end];
//
// while(start < end){
// while(input[start] < pivot)
// start++;
// while (input[end] > pivot)
// end--;
// if (input[start] == inpucout<<"time: "<<endTime<<" "<<startTime<<" "<<CLOCKS_PER_SEC<<endl;t[end])
// start++;
// else if(start < end){
// double tmp = input[start];
// input[start] = input[end];
// input[end] = tmp;
// }
// }
// return end;
// }
//
// __device__ double quickSelect(double* input, int p, int r, int k){
// if(p == r){
// return input[p];
// }
// int j = partition(input, p, r);
// int length = j - p + 1;
// if (length == k){
// return input[j];
// }cout<<"time: "<<endTime<<" "<<startTime<<" "<<CLOCKS_PER_SEC<<endl;
// else if( k < length ){
// return quickSelect(input, p, j - 1, k);
// }
// else{
// return quickSelect(input, j + 1, r, k - length);
// }
// }
__device__ void sort(double* input){
for(int i=0;i<5;i++){
for(int j=i;j<5;j++){
if(input[j]<input[i]){
double new_temp = input[i];
input[i] = input[j];
input[j] = new_temp;
}
}
}
}
__global__ void median (double *a, double *b) {
int number = blockIdx.x*blockDim.x + threadIdx.x;
// if((number <N) || (number>=N*N-N)||(number/N==0)||(number/N==N-1)){
// b[number]=a[number];
// }
// if((number > N-1) && (threadIdx.x > 0) && (threadIdx.x < N-1) && (number < N*N-N)){
if((number > N-1) && (number%N > 0) && (number%N < N-1) && (number < N*N-N)){
double tempCompare[5];
tempCompare[0] = a[number];
tempCompare[1] = a[number-1];
tempCompare[2] = a[number+1];
tempCompare[3] = a[number-N];
tempCompare[4] = a[number+N];
// b[number] = quickSelect(tempCompare,0,4,2);
// a[number] = tempCompare[2];
sort(tempCompare);
b[number]=tempCompare[2];
}
else if(number < N*N){
b[number]=a[number];
}
__syncthreads();
}
__global__ void move (double *b, double *a) {
int number = blockIdx.x*blockDim.x + threadIdx.x;
a[number] = b[number];
}
__global__ void reduction (double *in, double *out) {
__shared__ double temp[threadsPerBlock];
int id = threadIdx.x;
temp[id] = in[blockIdx.x*blockDim.x + id];
__syncthreads();
if(id<500 && id>11){
temp[id] += temp[id+500]; __syncthreads();
}
__syncthreads();
if(id<256){
temp[id] += temp[id+256]; __syncthreads();
}
if(id<128){
temp[id] += temp[id+128]; __syncthreads();
}
if(id<64){
temp[id] += temp[id+64]; __syncthreads();
}
if(id<32){
temp[id] += temp[id+32]; __syncthreads();
}
if(id<16){
temp[id] += temp[id+16]; __syncthreads();
}
if(id<8){
temp[id] += temp[id+8]; __syncthreads();
}
if(id<4){
temp[id] += temp[id+4]; __syncthreads();
}
if(id<2){
temp[id] += temp[id+2]; __syncthreads();
}
if(id<1){
temp[id] += temp[id+1]; __syncthreads();
}
if(id<1){out[blockIdx.x] = temp[id];}
}
__global__ void sumGen (double *in, double *out) {
for(int i=0;i<(N/threadsPerBlock)*(N/threadsPerBlock);i++){
out[0]+=in[i];
}
}
__global__ void assign (double *a, double *spe) {
spe[0] = a[count/2+N/2];
spe[1] = a[17*N+31];
}
int main(){
double A[count], B[count];
double sum[1], speNum[2];
double *d_a, *d_b, *d_partSum, *d_ppartSum, *d_sum, *d_speNum;
int size = N*N*sizeof(double);
int twosize = 2*sizeof(double);
sum[0]=0;
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
A[i*N+j] = sin(i*i+j)*sin(i*i+j)+cos(i-j);
// A[i*N+j] = j;
B[i*N+j] = 0;
}
}
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_partSum, size/threadsPerBlock);
hipMalloc((void **)&d_ppartSum, size/threadsPerBlock/threadsPerBlock);
hipMalloc((void **)&d_sum, sizeof(double));
hipMalloc((void **)&d_speNum,twosize);
hipMemcpy(d_a, A, size, hipMemcpyHostToDevice);
hipMemcpy(d_sum, sum, sizeof(double), hipMemcpyHostToDevice);
// clock_t startaaa = clock();
// cudaEvent_t startTime=0, endTime=0;
// cudaEventCreate(&startTime);
// cudaEventCreate(&endTime);
auto start = std::chrono::system_clock::now();
// cudaEventRecord(startTime, 0);
for(int i=0;i<10;i++){
median<<<numberBlocks,threadsPerBlock>>>(d_a,d_b);
hipDeviceSynchronize();
move<<<numberBlocks,threadsPerBlock>>>(d_b,d_a);
hipDeviceSynchronize();
}
reduction<<<count/threadsPerBlock, threadsPerBlock>>>(d_a,d_partSum);
reduction<<<(count/threadsPerBlock/threadsPerBlock),threadsPerBlock>>>(d_partSum,d_ppartSum);
sumGen<<<1,1>>>(d_ppartSum,d_sum);
assign<<<1,1>>>(d_a, d_speNum);
hipDeviceSynchronize();
// clock_t endbbb = clock();
// cudaEventRecord(endTime, 0);
// cudaEventSynchronize(endTime) ;
// float time;
// cudaEventElapsedTime(&time,startTime,endTime);
auto end = std::chrono::system_clock::now();
std::chrono::duration<double> elapsed_seconds = end-start;
hipMemcpy(sum, d_sum, sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(speNum, d_speNum, twosize, hipMemcpyDeviceToHost);
hipMemcpy(B, d_a, size, hipMemcpyDeviceToHost);
hipFree(d_a);hipFree(d_b);hipFree(d_partSum);hipFree(d_ppartSum);hipFree(d_sum);hipFree(d_speNum);
cout.precision(8);
// cout<<"time: "<<endbbb<<" "<<startaaa<<" "<<CLOCKS_PER_SEC<<endl;
// cout<<"time: "<<(endTime-startTime)/CLOCKS_PER_SEC<<endl;
// cout<<"time: "<<time<<endl;
// cout<<"time: "<<elapsed_seconds<<endl;
printf("time :%f\n",elapsed_seconds);
cout<<"Sum: "<<sum[0]<<endl;
cout<<"A[n/2][n/2]: "<<speNum[0]<<" "<<A[count/2+N/2]<<" "<<B[count/2+N/2]<<endl;
cout<<"A[17][31]: "<<speNum[1]<<" "<<A[17*N+31]<<" "<<B[17*N+31]<<endl;
cout<<"A[999][999]: "<<A[999*N+999]<<" "<<B[999*N+999]<<endl;
cout<<"A[999][500]: "<<A[999*N+500]<<" "<<B[999*N+500]<<endl;
cout<<"A[500][999]: "<<A[500*N+999]<<" "<<B[500*N+999]<<endl;
cout<<"A[500][0]: "<<A[500*N]<<" "<<B[500*N]<<endl;
cout<<"A[501][0]: "<<A[501*N]<<" "<<B[501*N]<<endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6medianPdS_
.globl _Z6medianPdS_
.p2align 8
.type _Z6medianPdS_,@function
_Z6medianPdS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[12:13], s[0:1], 0x0
s_mov_b32 s18, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, 0
v_cmp_gt_i32_e64 s11, 0xfa0, v1
v_cmpx_lt_i32_e32 0xf9f, v1
s_cbranch_execz .LBB0_10
v_mul_hi_u32 v0, v1, 0x10624dd3
s_mov_b32 s3, 0
s_mov_b32 s19, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v0, 8, v0
v_mul_u32_u24_e32 v0, 0xfa0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v1, v0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_cmp_gt_u32_e64 s2, 0xf9f, v0
v_cmp_gt_i32_e64 s3, 0xf41460, v1
s_mov_b32 s4, -1
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s3, s3, s2
s_mov_b32 s2, 0
s_and_saveexec_b32 s20, s3
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v2, 0
s_mov_b64 s[14:15], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_co_u32 v3, s2, s12, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v4, s2, s13, v4, s2
v_add_co_u32 v7, s2, 0xffff9000, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s2, -1, v4, s2
v_add_co_u32 v9, s2, 0x7000, v3
global_load_b128 v[11:14], v[3:4], off
v_add_co_ci_u32_e64 v10, s2, 0, v4, s2
s_clause 0x2
global_load_b64 v[5:6], v[3:4], off offset:-8
global_load_b64 v[7:8], v[7:8], off offset:-3328
global_load_b64 v[9:10], v[9:10], off offset:3328
s_waitcnt vmcnt(3)
v_dual_mov_b32 v0, v11 :: v_dual_mov_b32 v3, v13
v_dual_mov_b32 v11, v12 :: v_dual_mov_b32 v4, v14
.LBB0_4:
s_mov_b64 s[16:17], s[14:15]
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s16, 1
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s16, 2
s_waitcnt vmcnt(2)
v_cndmask_b32_e64 v12, v11, v6, s2
v_cndmask_b32_e64 v13, v0, v5, s2
s_cselect_b32 s3, -1, 0
s_cmp_eq_u32 s16, 3
s_cselect_b32 s4, -1, 0
s_cmp_eq_u32 s16, 4
v_cndmask_b32_e64 v12, v12, v4, s3
v_cndmask_b32_e64 v13, v13, v3, s3
s_cselect_b32 s5, -1, 0
s_cmp_eq_u32 s14, 1
s_cselect_b32 s6, -1, 0
s_waitcnt vmcnt(1)
v_cndmask_b32_e64 v12, v12, v8, s4
v_cndmask_b32_e64 v14, v13, v7, s4
v_cndmask_b32_e64 v15, v11, v6, s6
v_cndmask_b32_e64 v16, v0, v5, s6
s_cmp_eq_u32 s14, 2
s_waitcnt vmcnt(0)
v_cndmask_b32_e64 v13, v12, v10, s5
s_cselect_b32 s7, -1, 0
v_cndmask_b32_e64 v12, v14, v9, s5
v_cndmask_b32_e64 v14, v15, v4, s7
v_cndmask_b32_e64 v15, v16, v3, s7
s_cmp_eq_u32 s14, 3
v_cndmask_b32_e64 v18, v6, v13, s6
s_cselect_b32 s8, -1, 0
s_cmp_eq_u32 s14, 4
v_cndmask_b32_e64 v14, v14, v8, s8
v_cndmask_b32_e64 v16, v15, v7, s8
s_cselect_b32 s9, -1, 0
s_cmp_eq_u32 s14, 0
v_cndmask_b32_e64 v17, v10, v13, s9
v_cndmask_b32_e64 v15, v14, v10, s9
v_cndmask_b32_e64 v14, v16, v9, s9
v_cndmask_b32_e64 v22, v5, v12, s6
s_cselect_b32 s6, -1, 0
v_cndmask_b32_e64 v19, v8, v13, s8
v_cndmask_b32_e64 v16, v17, v15, s5
v_cmp_lt_f64_e64 s10, v[12:13], v[14:15]
v_cndmask_b32_e64 v17, v4, v13, s7
v_cndmask_b32_e64 v20, v7, v12, s8
v_cndmask_b32_e64 v21, v3, v12, s7
v_cndmask_b32_e64 v13, v11, v13, s6
v_cndmask_b32_e64 v23, v0, v12, s6
v_cndmask_b32_e64 v12, v9, v12, s9
s_cmp_eq_u32 s16, 0
v_cndmask_b32_e64 v18, v18, v15, s2
s_cselect_b32 s6, -1, 0
v_cndmask_b32_e64 v17, v17, v15, s3
v_cndmask_b32_e64 v19, v19, v15, s4
v_cndmask_b32_e64 v23, v23, v14, s6
v_cndmask_b32_e64 v13, v13, v15, s6
v_cndmask_b32_e64 v12, v12, v14, s5
v_cndmask_b32_e64 v15, v22, v14, s2
v_cndmask_b32_e64 v20, v20, v14, s4
v_cndmask_b32_e64 v14, v21, v14, s3
s_add_u32 s16, s16, 1
s_addc_u32 s17, s17, 0
s_add_i32 s7, s16, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s7, 3
v_cndmask_b32_e64 v10, v10, v16, s10
v_cndmask_b32_e64 v9, v9, v12, s10
v_cndmask_b32_e64 v8, v8, v19, s10
v_cndmask_b32_e64 v7, v7, v20, s10
v_cndmask_b32_e64 v4, v4, v17, s10
v_cndmask_b32_e64 v3, v3, v14, s10
v_cndmask_b32_e64 v6, v6, v18, s10
v_cndmask_b32_e64 v5, v5, v15, s10
v_cndmask_b32_e64 v11, v11, v13, s10
v_cndmask_b32_e64 v0, v0, v23, s10
s_cbranch_scc0 .LBB0_5
s_add_u32 s14, s14, 1
s_addc_u32 s15, s15, 0
s_cmp_eq_u32 s14, 5
s_cbranch_scc0 .LBB0_4
s_mov_b32 s2, exec_lo
s_xor_b32 s4, exec_lo, -1
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s20
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s5, vcc_lo, exec_lo
s_and_b32 s4, s4, exec_lo
s_and_b32 s3, s2, exec_lo
s_or_b32 vcc_lo, s5, s4
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s19
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s4, s11, exec_lo
s_and_b32 s5, vcc_lo, exec_lo
s_and_b32 s2, s3, exec_lo
s_or_b32 s11, s4, s5
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s18
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s3, s11
s_cbranch_execz .LBB0_14
s_mov_b32 s5, s2
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e32 0xf42400, v1
s_cbranch_execz .LBB0_13
v_ashrrev_i32_e32 v2, 31, v1
s_or_b32 s5, s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_co_u32 v3, vcc_lo, s12, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s13, v4, vcc_lo
global_load_b64 v[3:4], v[3:4], off
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s2, exec_lo
s_and_b32 s4, s5, exec_lo
s_or_b32 s2, s2, s4
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_16
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[3:4], off
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt vmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6medianPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 24
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6medianPdS_, .Lfunc_end0-_Z6medianPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4movePdS_
.globl _Z4movePdS_
.p2align 8
.type _Z4movePdS_,@function
_Z4movePdS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4movePdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z4movePdS_, .Lfunc_end1-_Z4movePdS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9reductionPdS_
.globl _Z9reductionPdS_
.p2align 8
.type _Z9reductionPdS_,@function
_Z9reductionPdS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
v_add_nc_u32_e32 v4, -12, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s3, exec_lo
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b64 v[2:3], v[1:2], off
v_lshlrev_b32_e32 v1, 3, v0
s_waitcnt vmcnt(0)
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x1e8, v4
s_cbranch_execz .LBB2_2
ds_load_b64 v[2:3], v1 offset:4000
ds_load_b64 v[4:5], v1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x100, v0
s_cbranch_execz .LBB2_4
v_lshlrev_b32_e32 v2, 3, v0
ds_load_b64 v[2:3], v2 offset:2048
ds_load_b64 v[4:5], v1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB2_4:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e32 0x80, v0
s_cbranch_execz .LBB2_6
v_lshlrev_b32_e32 v2, 3, v0
ds_load_b64 v[2:3], v2 offset:1024
ds_load_b64 v[4:5], v1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB2_6:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB2_8
v_lshlrev_b32_e32 v2, 3, v0
ds_load_b64 v[2:3], v2 offset:512
ds_load_b64 v[4:5], v1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB2_8:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB2_10
v_lshlrev_b32_e32 v2, 3, v0
ds_load_b64 v[2:3], v2 offset:256
ds_load_b64 v[4:5], v1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB2_10:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e32 16, v0
s_cbranch_execz .LBB2_12
v_lshlrev_b32_e32 v2, 3, v0
ds_load_b64 v[2:3], v2 offset:128
ds_load_b64 v[4:5], v1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB2_12:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e32 8, v0
s_cbranch_execz .LBB2_14
v_lshlrev_b32_e32 v2, 3, v0
ds_load_b64 v[2:3], v2 offset:64
ds_load_b64 v[4:5], v1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB2_14:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e32 4, v0
s_cbranch_execz .LBB2_16
v_lshlrev_b32_e32 v2, 3, v0
ds_load_b64 v[2:3], v2 offset:32
ds_load_b64 v[4:5], v1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB2_16:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e32 2, v0
s_cbranch_execz .LBB2_18
v_lshlrev_b32_e32 v2, 3, v0
ds_load_b64 v[2:3], v2 offset:16
ds_load_b64 v[4:5], v1
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB2_18:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB2_20
v_mov_b32_e32 v6, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 3
ds_load_b64 v[2:3], v1
ds_load_b64 v[4:5], v6 offset:8
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
v_add_f64 v[2:3], v[4:5], v[2:3]
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b64 v[0:1], v1
s_waitcnt lgkmcnt(0)
global_store_b64 v6, v[0:1], s[0:1]
.LBB2_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reductionPdS_
.amdhsa_group_segment_fixed_size 8000
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z9reductionPdS_, .Lfunc_end2-_Z9reductionPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6sumGenPdS_
.globl _Z6sumGenPdS_
.p2align 8
.type _Z6sumGenPdS_,@function
_Z6sumGenPdS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_load_b64 s[4:5], s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
s_mov_b64 s[4:5], 0
.LBB3_1:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s6, s0, s4
s_addc_u32 s7, s1, s5
s_add_u32 s4, s4, 8
global_load_b64 v[3:4], v2, s[6:7]
s_addc_u32 s5, s5, 0
s_cmpk_eq_i32 s4, 0x80
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[3:4], v[0:1]
global_store_b64 v2, v[0:1], s[2:3]
s_cbranch_scc0 .LBB3_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6sumGenPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z6sumGenPdS_, .Lfunc_end3-_Z6sumGenPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6assignPdS_
.globl _Z6assignPdS_
.p2align 8
.type _Z6assignPdS_,@function
_Z6assignPdS_:
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, 0x3d0ce80
v_mov_b32_e32 v3, 0x84000
s_waitcnt lgkmcnt(0)
s_load_b64 s[4:5], s[0:1], s4 offset:0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
global_store_b64 v2, v[0:1], s[2:3]
global_load_b64 v[0:1], v3, s[0:1] offset:3576
s_waitcnt vmcnt(0)
global_store_b64 v2, v[0:1], s[2:3] offset:8
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6assignPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 6
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z6assignPdS_, .Lfunc_end4-_Z6assignPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6medianPdS_
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _Z6medianPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 24
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4movePdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4movePdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8000
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reductionPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reductionPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6sumGenPdS_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6sumGenPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6assignPdS_
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z6assignPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdlib>
#include <iostream>
#include <math.h>
#include <ctime>
#include <chrono>
#include <vector>
using namespace std;
#define N 4000
#define count N*N
#define threadsPerBlock 1000
#define numberBlocks N*N/threadsPerBlock
// __device__ int partition(double* input, int start, int end)
// {
// double pivot = input[end];
//
// while(start < end){
// while(input[start] < pivot)
// start++;
// while (input[end] > pivot)
// end--;
// if (input[start] == inpucout<<"time: "<<endTime<<" "<<startTime<<" "<<CLOCKS_PER_SEC<<endl;t[end])
// start++;
// else if(start < end){
// double tmp = input[start];
// input[start] = input[end];
// input[end] = tmp;
// }
// }
// return end;
// }
//
// __device__ double quickSelect(double* input, int p, int r, int k){
// if(p == r){
// return input[p];
// }
// int j = partition(input, p, r);
// int length = j - p + 1;
// if (length == k){
// return input[j];
// }cout<<"time: "<<endTime<<" "<<startTime<<" "<<CLOCKS_PER_SEC<<endl;
// else if( k < length ){
// return quickSelect(input, p, j - 1, k);
// }
// else{
// return quickSelect(input, j + 1, r, k - length);
// }
// }
__device__ void sort(double* input){
for(int i=0;i<5;i++){
for(int j=i;j<5;j++){
if(input[j]<input[i]){
double new_temp = input[i];
input[i] = input[j];
input[j] = new_temp;
}
}
}
}
__global__ void median (double *a, double *b) {
int number = blockIdx.x*blockDim.x + threadIdx.x;
// if((number <N) || (number>=N*N-N)||(number/N==0)||(number/N==N-1)){
// b[number]=a[number];
// }
// if((number > N-1) && (threadIdx.x > 0) && (threadIdx.x < N-1) && (number < N*N-N)){
if((number > N-1) && (number%N > 0) && (number%N < N-1) && (number < N*N-N)){
double tempCompare[5];
tempCompare[0] = a[number];
tempCompare[1] = a[number-1];
tempCompare[2] = a[number+1];
tempCompare[3] = a[number-N];
tempCompare[4] = a[number+N];
// b[number] = quickSelect(tempCompare,0,4,2);
// a[number] = tempCompare[2];
sort(tempCompare);
b[number]=tempCompare[2];
}
else if(number < N*N){
b[number]=a[number];
}
__syncthreads();
}
__global__ void move (double *b, double *a) {
int number = blockIdx.x*blockDim.x + threadIdx.x;
a[number] = b[number];
}
__global__ void reduction (double *in, double *out) {
__shared__ double temp[threadsPerBlock];
int id = threadIdx.x;
temp[id] = in[blockIdx.x*blockDim.x + id];
__syncthreads();
if(id<500 && id>11){
temp[id] += temp[id+500]; __syncthreads();
}
__syncthreads();
if(id<256){
temp[id] += temp[id+256]; __syncthreads();
}
if(id<128){
temp[id] += temp[id+128]; __syncthreads();
}
if(id<64){
temp[id] += temp[id+64]; __syncthreads();
}
if(id<32){
temp[id] += temp[id+32]; __syncthreads();
}
if(id<16){
temp[id] += temp[id+16]; __syncthreads();
}
if(id<8){
temp[id] += temp[id+8]; __syncthreads();
}
if(id<4){
temp[id] += temp[id+4]; __syncthreads();
}
if(id<2){
temp[id] += temp[id+2]; __syncthreads();
}
if(id<1){
temp[id] += temp[id+1]; __syncthreads();
}
if(id<1){out[blockIdx.x] = temp[id];}
}
__global__ void sumGen (double *in, double *out) {
for(int i=0;i<(N/threadsPerBlock)*(N/threadsPerBlock);i++){
out[0]+=in[i];
}
}
__global__ void assign (double *a, double *spe) {
spe[0] = a[count/2+N/2];
spe[1] = a[17*N+31];
}
int main(){
double A[count], B[count];
double sum[1], speNum[2];
double *d_a, *d_b, *d_partSum, *d_ppartSum, *d_sum, *d_speNum;
int size = N*N*sizeof(double);
int twosize = 2*sizeof(double);
sum[0]=0;
for(int i=0;i<N;i++){
for(int j=0;j<N;j++){
A[i*N+j] = sin(i*i+j)*sin(i*i+j)+cos(i-j);
// A[i*N+j] = j;
B[i*N+j] = 0;
}
}
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_partSum, size/threadsPerBlock);
hipMalloc((void **)&d_ppartSum, size/threadsPerBlock/threadsPerBlock);
hipMalloc((void **)&d_sum, sizeof(double));
hipMalloc((void **)&d_speNum,twosize);
hipMemcpy(d_a, A, size, hipMemcpyHostToDevice);
hipMemcpy(d_sum, sum, sizeof(double), hipMemcpyHostToDevice);
// clock_t startaaa = clock();
// cudaEvent_t startTime=0, endTime=0;
// cudaEventCreate(&startTime);
// cudaEventCreate(&endTime);
auto start = std::chrono::system_clock::now();
// cudaEventRecord(startTime, 0);
for(int i=0;i<10;i++){
median<<<numberBlocks,threadsPerBlock>>>(d_a,d_b);
hipDeviceSynchronize();
move<<<numberBlocks,threadsPerBlock>>>(d_b,d_a);
hipDeviceSynchronize();
}
reduction<<<count/threadsPerBlock, threadsPerBlock>>>(d_a,d_partSum);
reduction<<<(count/threadsPerBlock/threadsPerBlock),threadsPerBlock>>>(d_partSum,d_ppartSum);
sumGen<<<1,1>>>(d_ppartSum,d_sum);
assign<<<1,1>>>(d_a, d_speNum);
hipDeviceSynchronize();
// clock_t endbbb = clock();
// cudaEventRecord(endTime, 0);
// cudaEventSynchronize(endTime) ;
// float time;
// cudaEventElapsedTime(&time,startTime,endTime);
auto end = std::chrono::system_clock::now();
std::chrono::duration<double> elapsed_seconds = end-start;
hipMemcpy(sum, d_sum, sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(speNum, d_speNum, twosize, hipMemcpyDeviceToHost);
hipMemcpy(B, d_a, size, hipMemcpyDeviceToHost);
hipFree(d_a);hipFree(d_b);hipFree(d_partSum);hipFree(d_ppartSum);hipFree(d_sum);hipFree(d_speNum);
cout.precision(8);
// cout<<"time: "<<endbbb<<" "<<startaaa<<" "<<CLOCKS_PER_SEC<<endl;
// cout<<"time: "<<(endTime-startTime)/CLOCKS_PER_SEC<<endl;
// cout<<"time: "<<time<<endl;
// cout<<"time: "<<elapsed_seconds<<endl;
printf("time :%f\n",elapsed_seconds);
cout<<"Sum: "<<sum[0]<<endl;
cout<<"A[n/2][n/2]: "<<speNum[0]<<" "<<A[count/2+N/2]<<" "<<B[count/2+N/2]<<endl;
cout<<"A[17][31]: "<<speNum[1]<<" "<<A[17*N+31]<<" "<<B[17*N+31]<<endl;
cout<<"A[999][999]: "<<A[999*N+999]<<" "<<B[999*N+999]<<endl;
cout<<"A[999][500]: "<<A[999*N+500]<<" "<<B[999*N+500]<<endl;
cout<<"A[500][999]: "<<A[500*N+999]<<" "<<B[500*N+999]<<endl;
cout<<"A[500][0]: "<<A[500*N]<<" "<<B[500*N]<<endl;
cout<<"A[501][0]: "<<A[501*N]<<" "<<B[501*N]<<endl;
return 0;
} | .text
.file "p5test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__medianPdS_ # -- Begin function _Z21__device_stub__medianPdS_
.p2align 4, 0x90
.type _Z21__device_stub__medianPdS_,@function
_Z21__device_stub__medianPdS_: # @_Z21__device_stub__medianPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6medianPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__medianPdS_, .Lfunc_end0-_Z21__device_stub__medianPdS_
.cfi_endproc
# -- End function
.globl _Z19__device_stub__movePdS_ # -- Begin function _Z19__device_stub__movePdS_
.p2align 4, 0x90
.type _Z19__device_stub__movePdS_,@function
_Z19__device_stub__movePdS_: # @_Z19__device_stub__movePdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4movePdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z19__device_stub__movePdS_, .Lfunc_end1-_Z19__device_stub__movePdS_
.cfi_endproc
# -- End function
.globl _Z24__device_stub__reductionPdS_ # -- Begin function _Z24__device_stub__reductionPdS_
.p2align 4, 0x90
.type _Z24__device_stub__reductionPdS_,@function
_Z24__device_stub__reductionPdS_: # @_Z24__device_stub__reductionPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9reductionPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z24__device_stub__reductionPdS_, .Lfunc_end2-_Z24__device_stub__reductionPdS_
.cfi_endproc
# -- End function
.globl _Z21__device_stub__sumGenPdS_ # -- Begin function _Z21__device_stub__sumGenPdS_
.p2align 4, 0x90
.type _Z21__device_stub__sumGenPdS_,@function
_Z21__device_stub__sumGenPdS_: # @_Z21__device_stub__sumGenPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6sumGenPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z21__device_stub__sumGenPdS_, .Lfunc_end3-_Z21__device_stub__sumGenPdS_
.cfi_endproc
# -- End function
.globl _Z21__device_stub__assignPdS_ # -- Begin function _Z21__device_stub__assignPdS_
.p2align 4, 0x90
.type _Z21__device_stub__assignPdS_,@function
_Z21__device_stub__assignPdS_: # @_Z21__device_stub__assignPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6assignPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z21__device_stub__assignPdS_, .Lfunc_end4-_Z21__device_stub__assignPdS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI5_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $256000168, %rsp # imm = 0xF4240A8
.cfi_def_cfa_offset 256000224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq $0, 136(%rsp)
leaq 160(%rsp), %rbx
leaq 128000160(%rsp), %r14
movl $1, %eax
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB5_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_2 Depth 2
movq %rax, 144(%rsp) # 8-byte Spill
movl %r13d, %ebp
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_2: # Parent Loop BB5_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%r12,%r15), %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, 152(%rsp) # 8-byte Spill
callq sin
movsd %xmm0, 80(%rsp) # 8-byte Spill
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
mulsd 80(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 80(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
callq cos
addsd 80(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%r14,%r15,8)
movq $0, (%rbx,%r15,8)
incq %r15
decl %ebp
cmpq $4000, %r15 # imm = 0xFA0
jne .LBB5_2
# %bb.3: # in Loop: Header=BB5_1 Depth=1
incq %r13
addq $32000, %rbx # imm = 0x7D00
addq $32000, %r14 # imm = 0x7D00
movq 144(%rsp), %rax # 8-byte Reload
addq %rax, %r12
addq $2, %rax
cmpq $4000, %r13 # imm = 0xFA0
jne .LBB5_1
# %bb.4:
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 88(%rsp), %rdi
movl $128000000, %esi # imm = 0x7A12000
callq hipMalloc
leaq 128(%rsp), %rdi
movl $128000000, %esi # imm = 0x7A12000
callq hipMalloc
leaq 120(%rsp), %rdi
movl $128000, %esi # imm = 0x1F400
callq hipMalloc
leaq 112(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 96(%rsp), %rdi
movl $8, %esi
callq hipMalloc
leaq 104(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq 88(%rsp), %rdi
leaq 128000160(%rsp), %rsi
movl $128000000, %edx # imm = 0x7A12000
movl $1, %ecx
callq hipMemcpy
movq 96(%rsp), %rdi
leaq 136(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movl $10, %ebp
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 80(%rsp) # 8-byte Spill
leaq 999(%rbx), %r15
leaq 15999(%rbx), %r12
leaq 56(%rsp), %r14
leaq 48(%rsp), %rbx
leaq 64(%rsp), %r13
jmp .LBB5_5
.p2align 4, 0x90
.LBB5_9: # in Loop: Header=BB5_5 Depth=1
callq hipDeviceSynchronize
decl %ebp
je .LBB5_10
.LBB5_5: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_7
# %bb.6: # in Loop: Header=BB5_5 Depth=1
movq 88(%rsp), %rax
movq 128(%rsp), %rcx
movq %rax, 40(%rsp)
movq %rcx, 32(%rsp)
leaq 40(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rax
movq %rax, 72(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
movq %r14, %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
movl $_Z6medianPdS_, %edi
movq %r13, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_7: # in Loop: Header=BB5_5 Depth=1
callq hipDeviceSynchronize
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_9
# %bb.8: # in Loop: Header=BB5_5 Depth=1
movq 128(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 40(%rsp)
movq %rcx, 32(%rsp)
leaq 40(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rax
movq %rax, 72(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
movq %r14, %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
movl $_Z4movePdS_, %edi
movq %r13, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_9
.LBB5_10:
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_12
# %bb.11:
movq 88(%rsp), %rax
movq 120(%rsp), %rcx
movq %rax, 40(%rsp)
movq %rcx, 32(%rsp)
leaq 40(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rax
movq %rax, 72(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9reductionPdS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_12:
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 15(%rbx), %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_14
# %bb.13:
movq 120(%rsp), %rax
movq 112(%rsp), %rcx
movq %rax, 40(%rsp)
movq %rcx, 32(%rsp)
leaq 40(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rax
movq %rax, 72(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9reductionPdS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_14:
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_16
# %bb.15:
movq 112(%rsp), %rax
movq 96(%rsp), %rcx
movq %rax, 40(%rsp)
movq %rcx, 32(%rsp)
leaq 40(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rax
movq %rax, 72(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6sumGenPdS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_16:
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_18
# %bb.17:
movq 88(%rsp), %rax
movq 104(%rsp), %rcx
movq %rax, 40(%rsp)
movq %rcx, 32(%rsp)
leaq 40(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rax
movq %rax, 72(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6assignPdS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_18:
callq hipDeviceSynchronize
callq _ZNSt6chrono3_V212system_clock3nowEv
subq 80(%rsp), %rax # 8-byte Folded Reload
cvtsi2sd %rax, %xmm0
divsd .LCPI5_0(%rip), %xmm0
movsd %xmm0, 80(%rsp) # 8-byte Spill
movq 96(%rsp), %rsi
leaq 136(%rsp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
movq 104(%rsp), %rsi
leaq 64(%rsp), %rdi
movl $16, %edx
movl $2, %ecx
callq hipMemcpy
movq 88(%rsp), %rsi
leaq 160(%rsp), %rdi
movl $128000000, %edx # imm = 0x7A12000
movl $2, %ecx
callq hipMemcpy
movq 88(%rsp), %rdi
callq hipFree
movq 128(%rsp), %rdi
callq hipFree
movq 120(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi
callq hipFree
movq 96(%rsp), %rdi
callq hipFree
movq 104(%rsp), %rdi
callq hipFree
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $8, _ZSt4cout+8(%rax)
movl $.L.str, %edi
movsd 80(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 136(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB5_51
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB5_21
# %bb.20:
movzbl 67(%rbx), %ecx
jmp .LBB5_22
.LBB5_21:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB5_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 64(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.3, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 192016160(%rsp), %xmm0 # xmm0 = mem[0],zero
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.3, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 64016160(%rsp), %xmm0 # xmm0 = mem[0],zero
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB5_51
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i88
cmpb $0, 56(%rbx)
je .LBB5_25
# %bb.24:
movzbl 67(%rbx), %ecx
jmp .LBB5_26
.LBB5_25:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB5_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit91
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 72(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.3, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 128544408(%rsp), %xmm0 # xmm0 = mem[0],zero
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.3, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 544408(%rsp), %xmm0 # xmm0 = mem[0],zero
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB5_51
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i93
cmpb $0, 56(%rbx)
je .LBB5_29
# %bb.28:
movzbl 67(%rbx), %ecx
jmp .LBB5_30
.LBB5_29:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB5_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit96
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 159976152(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.3, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 31976152(%rsp), %xmm0 # xmm0 = mem[0],zero
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB5_51
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i98
cmpb $0, 56(%rbx)
je .LBB5_33
# %bb.32:
movzbl 67(%rbx), %ecx
jmp .LBB5_34
.LBB5_33:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB5_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit101
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 159972160(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.3, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 31972160(%rsp), %xmm0 # xmm0 = mem[0],zero
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB5_51
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i103
cmpb $0, 56(%rbx)
je .LBB5_37
# %bb.36:
movzbl 67(%rbx), %ecx
jmp .LBB5_38
.LBB5_37:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB5_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit106
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 144008152(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.3, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 16008152(%rsp), %xmm0 # xmm0 = mem[0],zero
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB5_51
# %bb.39: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i108
cmpb $0, 56(%rbx)
je .LBB5_41
# %bb.40:
movzbl 67(%rbx), %ecx
jmp .LBB5_42
.LBB5_41:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB5_42: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit111
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 144000160(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.3, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 16000160(%rsp), %xmm0 # xmm0 = mem[0],zero
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB5_51
# %bb.43: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i113
cmpb $0, 56(%rbx)
je .LBB5_45
# %bb.44:
movzbl 67(%rbx), %ecx
jmp .LBB5_46
.LBB5_45:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB5_46: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit116
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 144032160(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.3, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 16032160(%rsp), %xmm0 # xmm0 = mem[0],zero
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB5_51
# %bb.47: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i118
cmpb $0, 56(%rbx)
je .LBB5_49
# %bb.48:
movzbl 67(%rbx), %ecx
jmp .LBB5_50
.LBB5_49:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB5_50: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit121
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $256000168, %rsp # imm = 0xF4240A8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_51:
.cfi_def_cfa_offset 256000224
callq _ZSt16__throw_bad_castv
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6medianPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4movePdS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reductionPdS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6sumGenPdS_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6assignPdS_, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6medianPdS_,@object # @_Z6medianPdS_
.section .rodata,"a",@progbits
.globl _Z6medianPdS_
.p2align 3, 0x0
_Z6medianPdS_:
.quad _Z21__device_stub__medianPdS_
.size _Z6medianPdS_, 8
.type _Z4movePdS_,@object # @_Z4movePdS_
.globl _Z4movePdS_
.p2align 3, 0x0
_Z4movePdS_:
.quad _Z19__device_stub__movePdS_
.size _Z4movePdS_, 8
.type _Z9reductionPdS_,@object # @_Z9reductionPdS_
.globl _Z9reductionPdS_
.p2align 3, 0x0
_Z9reductionPdS_:
.quad _Z24__device_stub__reductionPdS_
.size _Z9reductionPdS_, 8
.type _Z6sumGenPdS_,@object # @_Z6sumGenPdS_
.globl _Z6sumGenPdS_
.p2align 3, 0x0
_Z6sumGenPdS_:
.quad _Z21__device_stub__sumGenPdS_
.size _Z6sumGenPdS_, 8
.type _Z6assignPdS_,@object # @_Z6assignPdS_
.globl _Z6assignPdS_
.p2align 3, 0x0
_Z6assignPdS_:
.quad _Z21__device_stub__assignPdS_
.size _Z6assignPdS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "time :%f\n"
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Sum: "
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "A[n/2][n/2]: "
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " "
.size .L.str.3, 5
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "A[17][31]: "
.size .L.str.4, 12
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "A[999][999]: "
.size .L.str.5, 14
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "A[999][500]: "
.size .L.str.6, 14
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "A[500][999]: "
.size .L.str.7, 14
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "A[500][0]: "
.size .L.str.8, 12
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "A[501][0]: "
.size .L.str.9, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6medianPdS_"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z4movePdS_"
.size .L__unnamed_2, 12
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z9reductionPdS_"
.size .L__unnamed_3, 17
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z6sumGenPdS_"
.size .L__unnamed_4, 14
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z6assignPdS_"
.size .L__unnamed_5, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__medianPdS_
.addrsig_sym _Z19__device_stub__movePdS_
.addrsig_sym _Z24__device_stub__reductionPdS_
.addrsig_sym _Z21__device_stub__sumGenPdS_
.addrsig_sym _Z21__device_stub__assignPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6medianPdS_
.addrsig_sym _Z4movePdS_
.addrsig_sym _Z9reductionPdS_
.addrsig_sym _Z6sumGenPdS_
.addrsig_sym _Z6assignPdS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
//resolvi usar o mesmo tamanho de "bloco" que foi usado no exemplo do slide (slide 68, "CudaBasics")
#define TILE_WIDTH 16
__global__ void addMatrix(int *A, int *B,int *C, int *rows, int *cols){
//variaveis necessarias para computar o indice corretamente
int col = (blockDim.x * blockIdx.x) + threadIdx.x;
int row = (blockDim.y * blockIdx.y) + threadIdx.y;
/*
* como alguma das dimensoes da matriz pode nao ser divisivel pelo o tamanho do bloco (TILE_WIDTH =16)
* entao e existem indices em alguns blocos que estao mapeados em "nada" (não mapeam algum elemento na matriz).
* Portanto é necessario esse condicional para evitar acessos a posições de memorias indesejaveis.
* */
if(col < (*cols) && row < (*rows)){
/*
* A expressão
*
* (row * (*cols)) + col
*
* computa o indice da corretamente
* */
C[ (row * (*cols)) + col] = A[ (row * (*cols)) + col] + B[ (row * (*cols)) + col] ;
}
}
int main()
{
//copias das variaveis da CPU
int *A, *B, *C;
//copias das variaveis da GPU
int *D_A, *D_B, *D_C;
int *D_ROWS, *D_COLS;
int i, j;
//Input
int linhas, colunas;
scanf("%d", &linhas);
scanf("%d", &colunas);
int size = sizeof(int) * linhas * colunas;
//Alocando memória na CPU
A = (int *)malloc(size);
B = (int *)malloc(size);
C = (int *)malloc(size);
//Alocando memória na GPU
cudaMalloc( (void **)&D_A, size);
cudaMalloc( (void **)&D_B, size);
cudaMalloc( (void **)&D_C, size);
cudaMalloc( (void **)&D_ROWS, sizeof(int));
cudaMalloc( (void **)&D_COLS, sizeof(int));
//Inicializar
for(i = 0; i < linhas; i++){
for(j = 0; j < colunas; j++){
A[i*colunas+j] = B[i*colunas+j] = i+j;
}
}
//enviando os dados para a GPU
cudaMemcpy(D_A, A, size, cudaMemcpyHostToDevice);
cudaMemcpy(D_B, B, size, cudaMemcpyHostToDevice);
cudaMemcpy(D_ROWS, &linhas, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(D_COLS, &colunas, sizeof(int), cudaMemcpyHostToDevice);
//crieando as variaveis necessarias para fazer o mapeamento 2D
dim3 numeroDeBlocosNaMatriz( ceil((float)colunas/TILE_WIDTH),ceil((float)linhas/TILE_WIDTH), 1 );
dim3 numeroDeThreadsPorBloco( TILE_WIDTH,TILE_WIDTH, 1 );
//executanto a soma de matriz na GPU
addMatrix<<<numeroDeBlocosNaMatriz,numeroDeThreadsPorBloco>>>(D_A,D_B,D_C, D_ROWS, D_COLS);
//transferindo o resultado da soma, que esta na GPU, para a CPU.
cudaMemcpy(C, D_C, size, cudaMemcpyDeviceToHost);
long long int somador=0;
//Manter esta computação na CPU
for(i = 0; i < linhas; i++){
for(j = 0; j < colunas; j++){
somador+=C[i*colunas+j];
}
}
printf("%lli\n", somador);
free(A);
free(B);
free(C);
//desalocando a memoria na GPU
cudaFree(D_A);
cudaFree(D_B);
cudaFree(D_C);
cudaFree(D_ROWS);
cudaFree(D_COLS);
return 0;
} | code for sm_80
Function : _Z9addMatrixPiS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x180] ; /* 0x0000600000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x184] ; /* 0x0000610000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0205 */
/*0080*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e260000002600 */
/*0090*/ ISETP.GE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x004fda0003f06270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x001fe40000000f00 */
/*00c0*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fca0000000f00 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e240000002200 */
/*00f0*/ IMAD R5, R5, c[0x0][0x4], R4 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0204 */
/*0100*/ ISETP.GE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x004fda0003f06270 */
/*0110*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0120*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*0130*/ IMAD R7, R5, R7, R0 ; /* 0x0000000705077224 */
/* 0x000fd200078e0200 */
/*0140*/ IMAD.WIDE R4, R7, R6, c[0x0][0x168] ; /* 0x00005a0007047625 */
/* 0x000fc800078e0206 */
/*0150*/ IMAD.WIDE R2, R7.reuse, R6.reuse, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x0c0fe400078e0206 */
/*0160*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IMAD.WIDE R6, R7, R6, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x000fe200078e0206 */
/*0190*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*01a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
//resolvi usar o mesmo tamanho de "bloco" que foi usado no exemplo do slide (slide 68, "CudaBasics")
#define TILE_WIDTH 16
__global__ void addMatrix(int *A, int *B,int *C, int *rows, int *cols){
//variaveis necessarias para computar o indice corretamente
int col = (blockDim.x * blockIdx.x) + threadIdx.x;
int row = (blockDim.y * blockIdx.y) + threadIdx.y;
/*
* como alguma das dimensoes da matriz pode nao ser divisivel pelo o tamanho do bloco (TILE_WIDTH =16)
* entao e existem indices em alguns blocos que estao mapeados em "nada" (não mapeam algum elemento na matriz).
* Portanto é necessario esse condicional para evitar acessos a posições de memorias indesejaveis.
* */
if(col < (*cols) && row < (*rows)){
/*
* A expressão
*
* (row * (*cols)) + col
*
* computa o indice da corretamente
* */
C[ (row * (*cols)) + col] = A[ (row * (*cols)) + col] + B[ (row * (*cols)) + col] ;
}
}
int main()
{
//copias das variaveis da CPU
int *A, *B, *C;
//copias das variaveis da GPU
int *D_A, *D_B, *D_C;
int *D_ROWS, *D_COLS;
int i, j;
//Input
int linhas, colunas;
scanf("%d", &linhas);
scanf("%d", &colunas);
int size = sizeof(int) * linhas * colunas;
//Alocando memória na CPU
A = (int *)malloc(size);
B = (int *)malloc(size);
C = (int *)malloc(size);
//Alocando memória na GPU
cudaMalloc( (void **)&D_A, size);
cudaMalloc( (void **)&D_B, size);
cudaMalloc( (void **)&D_C, size);
cudaMalloc( (void **)&D_ROWS, sizeof(int));
cudaMalloc( (void **)&D_COLS, sizeof(int));
//Inicializar
for(i = 0; i < linhas; i++){
for(j = 0; j < colunas; j++){
A[i*colunas+j] = B[i*colunas+j] = i+j;
}
}
//enviando os dados para a GPU
cudaMemcpy(D_A, A, size, cudaMemcpyHostToDevice);
cudaMemcpy(D_B, B, size, cudaMemcpyHostToDevice);
cudaMemcpy(D_ROWS, &linhas, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(D_COLS, &colunas, sizeof(int), cudaMemcpyHostToDevice);
//crieando as variaveis necessarias para fazer o mapeamento 2D
dim3 numeroDeBlocosNaMatriz( ceil((float)colunas/TILE_WIDTH),ceil((float)linhas/TILE_WIDTH), 1 );
dim3 numeroDeThreadsPorBloco( TILE_WIDTH,TILE_WIDTH, 1 );
//executanto a soma de matriz na GPU
addMatrix<<<numeroDeBlocosNaMatriz,numeroDeThreadsPorBloco>>>(D_A,D_B,D_C, D_ROWS, D_COLS);
//transferindo o resultado da soma, que esta na GPU, para a CPU.
cudaMemcpy(C, D_C, size, cudaMemcpyDeviceToHost);
long long int somador=0;
//Manter esta computação na CPU
for(i = 0; i < linhas; i++){
for(j = 0; j < colunas; j++){
somador+=C[i*colunas+j];
}
}
printf("%lli\n", somador);
free(A);
free(B);
free(C);
//desalocando a memoria na GPU
cudaFree(D_A);
cudaFree(D_B);
cudaFree(D_C);
cudaFree(D_ROWS);
cudaFree(D_COLS);
return 0;
} | .file "tmpxft_000446f0_00000000-6_matrix_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z9addMatrixPiS_S_S_S_PiS_S_S_S_
.type _Z36__device_stub__Z9addMatrixPiS_S_S_S_PiS_S_S_S_, @function
_Z36__device_stub__Z9addMatrixPiS_S_S_S_PiS_S_S_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9addMatrixPiS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z36__device_stub__Z9addMatrixPiS_S_S_S_PiS_S_S_S_, .-_Z36__device_stub__Z9addMatrixPiS_S_S_S_PiS_S_S_S_
.globl _Z9addMatrixPiS_S_S_S_
.type _Z9addMatrixPiS_S_S_S_, @function
_Z9addMatrixPiS_S_S_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z9addMatrixPiS_S_S_S_PiS_S_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9addMatrixPiS_S_S_S_, .-_Z9addMatrixPiS_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC5:
.string "%lli\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
leaq .LC0(%rip), %rbx
movq %rbx, %rdi
call __isoc23_scanf@PLT
leaq 4(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 4(%rsp), %r13d
imull (%rsp), %r13d
sall $2, %r13d
movslq %r13d, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl (%rsp), %r9d
testl %r9d, %r9d
jle .L12
movl 4(%rsp), %r8d
movl %r8d, %ecx
movl $0, %edi
movl $0, %esi
jmp .L13
.L14:
movl %eax, (%rbx,%rdx)
movl %eax, 0(%rbp,%rdx)
addl $1, %eax
addq $4, %rdx
cmpl %ecx, %eax
jne .L14
.L16:
addl $1, %esi
addl %r8d, %edi
addl $1, %ecx
cmpl %r9d, %esi
je .L12
.L13:
movl %esi, %eax
movslq %edi, %rdx
salq $2, %rdx
testl %r8d, %r8d
jg .L14
jmp .L16
.L12:
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl (%rsp), %xmm0
mulss .LC1(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC6(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC2(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L17
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC4(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L17:
pxor %xmm0, %xmm0
cvtsi2ssl 4(%rsp), %xmm0
mulss .LC1(%rip), %xmm0
movaps %xmm0, %xmm4
movss .LC6(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC2(%rip), %xmm5
ucomiss %xmm2, %xmm5
jbe .L18
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm4
movss .LC4(%rip), %xmm5
andps %xmm5, %xmm4
addss %xmm2, %xmm4
andnps %xmm0, %xmm3
orps %xmm3, %xmm4
.L18:
cvttss2siq %xmm4, %rax
movl %eax, 48(%rsp)
cvttss2siq %xmm1, %rax
movl %eax, 52(%rsp)
movl $16, 60(%rsp)
movl $16, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L19:
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl (%rsp), %r10d
testl %r10d, %r10d
jle .L26
movl 4(%rsp), %r9d
movl $0, %r8d
movl $0, %edx
movl $0, %edi
movslq %r9d, %r11
jmp .L21
.L31:
movq 40(%rsp), %r8
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z36__device_stub__Z9addMatrixPiS_S_S_S_PiS_S_S_S_
jmp .L19
.L23:
movslq %r8d, %rcx
leaq (%r12,%rcx,4), %rax
addq %r11, %rcx
leaq (%r12,%rcx,4), %rsi
.L22:
movslq (%rax), %rcx
addq %rcx, %rdx
addq $4, %rax
cmpq %rsi, %rax
jne .L22
.L24:
addl $1, %edi
addl %r9d, %r8d
cmpl %r10d, %edi
je .L20
.L21:
testl %r9d, %r9d
jg .L23
jmp .L24
.L26:
movl $0, %edx
.L20:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z9addMatrixPiS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addMatrixPiS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1031798784
.align 4
.LC2:
.long 1258291200
.align 4
.LC4:
.long 1065353216
.align 4
.LC6:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
//resolvi usar o mesmo tamanho de "bloco" que foi usado no exemplo do slide (slide 68, "CudaBasics")
#define TILE_WIDTH 16
__global__ void addMatrix(int *A, int *B,int *C, int *rows, int *cols){
//variaveis necessarias para computar o indice corretamente
int col = (blockDim.x * blockIdx.x) + threadIdx.x;
int row = (blockDim.y * blockIdx.y) + threadIdx.y;
/*
* como alguma das dimensoes da matriz pode nao ser divisivel pelo o tamanho do bloco (TILE_WIDTH =16)
* entao e existem indices em alguns blocos que estao mapeados em "nada" (não mapeam algum elemento na matriz).
* Portanto é necessario esse condicional para evitar acessos a posições de memorias indesejaveis.
* */
if(col < (*cols) && row < (*rows)){
/*
* A expressão
*
* (row * (*cols)) + col
*
* computa o indice da corretamente
* */
C[ (row * (*cols)) + col] = A[ (row * (*cols)) + col] + B[ (row * (*cols)) + col] ;
}
}
int main()
{
//copias das variaveis da CPU
int *A, *B, *C;
//copias das variaveis da GPU
int *D_A, *D_B, *D_C;
int *D_ROWS, *D_COLS;
int i, j;
//Input
int linhas, colunas;
scanf("%d", &linhas);
scanf("%d", &colunas);
int size = sizeof(int) * linhas * colunas;
//Alocando memória na CPU
A = (int *)malloc(size);
B = (int *)malloc(size);
C = (int *)malloc(size);
//Alocando memória na GPU
cudaMalloc( (void **)&D_A, size);
cudaMalloc( (void **)&D_B, size);
cudaMalloc( (void **)&D_C, size);
cudaMalloc( (void **)&D_ROWS, sizeof(int));
cudaMalloc( (void **)&D_COLS, sizeof(int));
//Inicializar
for(i = 0; i < linhas; i++){
for(j = 0; j < colunas; j++){
A[i*colunas+j] = B[i*colunas+j] = i+j;
}
}
//enviando os dados para a GPU
cudaMemcpy(D_A, A, size, cudaMemcpyHostToDevice);
cudaMemcpy(D_B, B, size, cudaMemcpyHostToDevice);
cudaMemcpy(D_ROWS, &linhas, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(D_COLS, &colunas, sizeof(int), cudaMemcpyHostToDevice);
//crieando as variaveis necessarias para fazer o mapeamento 2D
dim3 numeroDeBlocosNaMatriz( ceil((float)colunas/TILE_WIDTH),ceil((float)linhas/TILE_WIDTH), 1 );
dim3 numeroDeThreadsPorBloco( TILE_WIDTH,TILE_WIDTH, 1 );
//executanto a soma de matriz na GPU
addMatrix<<<numeroDeBlocosNaMatriz,numeroDeThreadsPorBloco>>>(D_A,D_B,D_C, D_ROWS, D_COLS);
//transferindo o resultado da soma, que esta na GPU, para a CPU.
cudaMemcpy(C, D_C, size, cudaMemcpyDeviceToHost);
long long int somador=0;
//Manter esta computação na CPU
for(i = 0; i < linhas; i++){
for(j = 0; j < colunas; j++){
somador+=C[i*colunas+j];
}
}
printf("%lli\n", somador);
free(A);
free(B);
free(C);
//desalocando a memoria na GPU
cudaFree(D_A);
cudaFree(D_B);
cudaFree(D_C);
cudaFree(D_ROWS);
cudaFree(D_COLS);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
//resolvi usar o mesmo tamanho de "bloco" que foi usado no exemplo do slide (slide 68, "CudaBasics")
#define TILE_WIDTH 16
__global__ void addMatrix(int *A, int *B,int *C, int *rows, int *cols){
//variaveis necessarias para computar o indice corretamente
int col = (blockDim.x * blockIdx.x) + threadIdx.x;
int row = (blockDim.y * blockIdx.y) + threadIdx.y;
/*
* como alguma das dimensoes da matriz pode nao ser divisivel pelo o tamanho do bloco (TILE_WIDTH =16)
* entao e existem indices em alguns blocos que estao mapeados em "nada" (não mapeam algum elemento na matriz).
* Portanto é necessario esse condicional para evitar acessos a posições de memorias indesejaveis.
* */
if(col < (*cols) && row < (*rows)){
/*
* A expressão
*
* (row * (*cols)) + col
*
* computa o indice da corretamente
* */
C[ (row * (*cols)) + col] = A[ (row * (*cols)) + col] + B[ (row * (*cols)) + col] ;
}
}
int main()
{
//copias das variaveis da CPU
int *A, *B, *C;
//copias das variaveis da GPU
int *D_A, *D_B, *D_C;
int *D_ROWS, *D_COLS;
int i, j;
//Input
int linhas, colunas;
scanf("%d", &linhas);
scanf("%d", &colunas);
int size = sizeof(int) * linhas * colunas;
//Alocando memória na CPU
A = (int *)malloc(size);
B = (int *)malloc(size);
C = (int *)malloc(size);
//Alocando memória na GPU
hipMalloc( (void **)&D_A, size);
hipMalloc( (void **)&D_B, size);
hipMalloc( (void **)&D_C, size);
hipMalloc( (void **)&D_ROWS, sizeof(int));
hipMalloc( (void **)&D_COLS, sizeof(int));
//Inicializar
for(i = 0; i < linhas; i++){
for(j = 0; j < colunas; j++){
A[i*colunas+j] = B[i*colunas+j] = i+j;
}
}
//enviando os dados para a GPU
hipMemcpy(D_A, A, size, hipMemcpyHostToDevice);
hipMemcpy(D_B, B, size, hipMemcpyHostToDevice);
hipMemcpy(D_ROWS, &linhas, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(D_COLS, &colunas, sizeof(int), hipMemcpyHostToDevice);
//crieando as variaveis necessarias para fazer o mapeamento 2D
dim3 numeroDeBlocosNaMatriz( ceil((float)colunas/TILE_WIDTH),ceil((float)linhas/TILE_WIDTH), 1 );
dim3 numeroDeThreadsPorBloco( TILE_WIDTH,TILE_WIDTH, 1 );
//executanto a soma de matriz na GPU
addMatrix<<<numeroDeBlocosNaMatriz,numeroDeThreadsPorBloco>>>(D_A,D_B,D_C, D_ROWS, D_COLS);
//transferindo o resultado da soma, que esta na GPU, para a CPU.
hipMemcpy(C, D_C, size, hipMemcpyDeviceToHost);
long long int somador=0;
//Manter esta computação na CPU
for(i = 0; i < linhas; i++){
for(j = 0; j < colunas; j++){
somador+=C[i*colunas+j];
}
}
printf("%lli\n", somador);
free(A);
free(B);
free(C);
//desalocando a memoria na GPU
hipFree(D_A);
hipFree(D_B);
hipFree(D_C);
hipFree(D_ROWS);
hipFree(D_COLS);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
//resolvi usar o mesmo tamanho de "bloco" que foi usado no exemplo do slide (slide 68, "CudaBasics")
#define TILE_WIDTH 16
__global__ void addMatrix(int *A, int *B,int *C, int *rows, int *cols){
//variaveis necessarias para computar o indice corretamente
int col = (blockDim.x * blockIdx.x) + threadIdx.x;
int row = (blockDim.y * blockIdx.y) + threadIdx.y;
/*
* como alguma das dimensoes da matriz pode nao ser divisivel pelo o tamanho do bloco (TILE_WIDTH =16)
* entao e existem indices em alguns blocos que estao mapeados em "nada" (não mapeam algum elemento na matriz).
* Portanto é necessario esse condicional para evitar acessos a posições de memorias indesejaveis.
* */
if(col < (*cols) && row < (*rows)){
/*
* A expressão
*
* (row * (*cols)) + col
*
* computa o indice da corretamente
* */
C[ (row * (*cols)) + col] = A[ (row * (*cols)) + col] + B[ (row * (*cols)) + col] ;
}
}
int main()
{
//copias das variaveis da CPU
int *A, *B, *C;
//copias das variaveis da GPU
int *D_A, *D_B, *D_C;
int *D_ROWS, *D_COLS;
int i, j;
//Input
int linhas, colunas;
scanf("%d", &linhas);
scanf("%d", &colunas);
int size = sizeof(int) * linhas * colunas;
//Alocando memória na CPU
A = (int *)malloc(size);
B = (int *)malloc(size);
C = (int *)malloc(size);
//Alocando memória na GPU
hipMalloc( (void **)&D_A, size);
hipMalloc( (void **)&D_B, size);
hipMalloc( (void **)&D_C, size);
hipMalloc( (void **)&D_ROWS, sizeof(int));
hipMalloc( (void **)&D_COLS, sizeof(int));
//Inicializar
for(i = 0; i < linhas; i++){
for(j = 0; j < colunas; j++){
A[i*colunas+j] = B[i*colunas+j] = i+j;
}
}
//enviando os dados para a GPU
hipMemcpy(D_A, A, size, hipMemcpyHostToDevice);
hipMemcpy(D_B, B, size, hipMemcpyHostToDevice);
hipMemcpy(D_ROWS, &linhas, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(D_COLS, &colunas, sizeof(int), hipMemcpyHostToDevice);
//crieando as variaveis necessarias para fazer o mapeamento 2D
dim3 numeroDeBlocosNaMatriz( ceil((float)colunas/TILE_WIDTH),ceil((float)linhas/TILE_WIDTH), 1 );
dim3 numeroDeThreadsPorBloco( TILE_WIDTH,TILE_WIDTH, 1 );
//executanto a soma de matriz na GPU
addMatrix<<<numeroDeBlocosNaMatriz,numeroDeThreadsPorBloco>>>(D_A,D_B,D_C, D_ROWS, D_COLS);
//transferindo o resultado da soma, que esta na GPU, para a CPU.
hipMemcpy(C, D_C, size, hipMemcpyDeviceToHost);
long long int somador=0;
//Manter esta computação na CPU
for(i = 0; i < linhas; i++){
for(j = 0; j < colunas; j++){
somador+=C[i*colunas+j];
}
}
printf("%lli\n", somador);
free(A);
free(B);
free(C);
//desalocando a memoria na GPU
hipFree(D_A);
hipFree(D_B);
hipFree(D_C);
hipFree(D_ROWS);
hipFree(D_COLS);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addMatrixPiS_S_S_S_
.globl _Z9addMatrixPiS_S_S_S_
.p2align 8
.type _Z9addMatrixPiS_S_S_S_,@function
_Z9addMatrixPiS_S_S_S_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b32 s5, s[0:1], 0x34
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_load_b32 s4, s[2:3], 0x0
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s5, v[3:4]
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x18
s_load_b32 s2, s[2:3], 0xc
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_load_b32 s3, s[6:7], 0x0
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b128 s[8:11], s[0:1], 0x0
v_mad_u64_u32 v[3:4], null, v2, s4, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addMatrixPiS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addMatrixPiS_S_S_S_, .Lfunc_end0-_Z9addMatrixPiS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addMatrixPiS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9addMatrixPiS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
//resolvi usar o mesmo tamanho de "bloco" que foi usado no exemplo do slide (slide 68, "CudaBasics")
#define TILE_WIDTH 16
__global__ void addMatrix(int *A, int *B,int *C, int *rows, int *cols){
//variaveis necessarias para computar o indice corretamente
int col = (blockDim.x * blockIdx.x) + threadIdx.x;
int row = (blockDim.y * blockIdx.y) + threadIdx.y;
/*
* como alguma das dimensoes da matriz pode nao ser divisivel pelo o tamanho do bloco (TILE_WIDTH =16)
* entao e existem indices em alguns blocos que estao mapeados em "nada" (não mapeam algum elemento na matriz).
* Portanto é necessario esse condicional para evitar acessos a posições de memorias indesejaveis.
* */
if(col < (*cols) && row < (*rows)){
/*
* A expressão
*
* (row * (*cols)) + col
*
* computa o indice da corretamente
* */
C[ (row * (*cols)) + col] = A[ (row * (*cols)) + col] + B[ (row * (*cols)) + col] ;
}
}
int main()
{
//copias das variaveis da CPU
int *A, *B, *C;
//copias das variaveis da GPU
int *D_A, *D_B, *D_C;
int *D_ROWS, *D_COLS;
int i, j;
//Input
int linhas, colunas;
scanf("%d", &linhas);
scanf("%d", &colunas);
int size = sizeof(int) * linhas * colunas;
//Alocando memória na CPU
A = (int *)malloc(size);
B = (int *)malloc(size);
C = (int *)malloc(size);
//Alocando memória na GPU
hipMalloc( (void **)&D_A, size);
hipMalloc( (void **)&D_B, size);
hipMalloc( (void **)&D_C, size);
hipMalloc( (void **)&D_ROWS, sizeof(int));
hipMalloc( (void **)&D_COLS, sizeof(int));
//Inicializar
for(i = 0; i < linhas; i++){
for(j = 0; j < colunas; j++){
A[i*colunas+j] = B[i*colunas+j] = i+j;
}
}
//enviando os dados para a GPU
hipMemcpy(D_A, A, size, hipMemcpyHostToDevice);
hipMemcpy(D_B, B, size, hipMemcpyHostToDevice);
hipMemcpy(D_ROWS, &linhas, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(D_COLS, &colunas, sizeof(int), hipMemcpyHostToDevice);
//crieando as variaveis necessarias para fazer o mapeamento 2D
dim3 numeroDeBlocosNaMatriz( ceil((float)colunas/TILE_WIDTH),ceil((float)linhas/TILE_WIDTH), 1 );
dim3 numeroDeThreadsPorBloco( TILE_WIDTH,TILE_WIDTH, 1 );
//executanto a soma de matriz na GPU
addMatrix<<<numeroDeBlocosNaMatriz,numeroDeThreadsPorBloco>>>(D_A,D_B,D_C, D_ROWS, D_COLS);
//transferindo o resultado da soma, que esta na GPU, para a CPU.
hipMemcpy(C, D_C, size, hipMemcpyDeviceToHost);
long long int somador=0;
//Manter esta computação na CPU
for(i = 0; i < linhas; i++){
for(j = 0; j < colunas; j++){
somador+=C[i*colunas+j];
}
}
printf("%lli\n", somador);
free(A);
free(B);
free(C);
//desalocando a memoria na GPU
hipFree(D_A);
hipFree(D_B);
hipFree(D_C);
hipFree(D_ROWS);
hipFree(D_COLS);
return 0;
} | .text
.file "matrix_add.hip"
.globl _Z24__device_stub__addMatrixPiS_S_S_S_ # -- Begin function _Z24__device_stub__addMatrixPiS_S_S_S_
.p2align 4, 0x90
.type _Z24__device_stub__addMatrixPiS_S_S_S_,@function
_Z24__device_stub__addMatrixPiS_S_S_S_: # @_Z24__device_stub__addMatrixPiS_S_S_S_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9addMatrixPiS_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z24__device_stub__addMatrixPiS_S_S_S_, .Lfunc_end0-_Z24__device_stub__addMatrixPiS_S_S_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3d800000 # float 0.0625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $192, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r13d, %r13d
leaq 12(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
leaq 8(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 12(%rsp), %eax
imull 8(%rsp), %eax
shll $2, %eax
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
leaq 48(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_6
# %bb.1: # %.preheader49.lr.ph
movl 8(%rsp), %ecx
xorl %edx, %edx
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rdx
addl %ecx, %r13d
cmpq %rax, %rdx
je .LBB1_6
.LBB1_2: # %.preheader49
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %ecx, %ecx
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r13d, %edi
leaq (%rbx,%rdi,4), %rsi
leaq (%r14,%rdi,4), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rdx,%r8), %r9d
movl %r9d, (%rdi,%r8,4)
movl %r9d, (%rsi,%r8,4)
incq %r8
cmpq %r8, %rcx
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge52
movq 48(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 8(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
cvtsi2ssl 8(%rsp), %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r13
xorps %xmm0, %xmm0
cvtsi2ssl 12(%rsp), %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rdi
movl %r13d, %eax
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdi, 104(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z9addMatrixPiS_S_S_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 32(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl 12(%rsp), %eax
xorl %ecx, %ecx
testl %eax, %eax
jle .LBB1_9
# %bb.10: # %.preheader.lr.ph
movl 8(%rsp), %edx
xorl %edi, %edi
xorl %esi, %esi
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_14: # %._crit_edge56
# in Loop: Header=BB1_11 Depth=1
incq %rdi
addl %edx, %ecx
cmpq %rax, %rdi
je .LBB1_15
.LBB1_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_13 Depth 2
testl %edx, %edx
jle .LBB1_14
# %bb.12: # %.lr.ph55
# in Loop: Header=BB1_11 Depth=1
movl %ecx, %r8d
leaq (%r15,%r8,4), %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB1_13: # Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movslq (%r8,%r9,4), %r10
addq %r10, %rsi
incq %r9
cmpq %r9, %rdx
jne .LBB1_13
jmp .LBB1_14
.LBB1_9:
xorl %esi, %esi
.LBB1_15: # %._crit_edge59
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $192, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addMatrixPiS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addMatrixPiS_S_S_S_,@object # @_Z9addMatrixPiS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z9addMatrixPiS_S_S_S_
.p2align 3, 0x0
_Z9addMatrixPiS_S_S_S_:
.quad _Z24__device_stub__addMatrixPiS_S_S_S_
.size _Z9addMatrixPiS_S_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%lli\n"
.size .L.str.1, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addMatrixPiS_S_S_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addMatrixPiS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addMatrixPiS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9addMatrixPiS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x180] ; /* 0x0000600000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x184] ; /* 0x0000610000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0205 */
/*0080*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e260000002600 */
/*0090*/ ISETP.GE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x004fda0003f06270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x001fe40000000f00 */
/*00c0*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fca0000000f00 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e240000002200 */
/*00f0*/ IMAD R5, R5, c[0x0][0x4], R4 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0204 */
/*0100*/ ISETP.GE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x004fda0003f06270 */
/*0110*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0120*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*0130*/ IMAD R7, R5, R7, R0 ; /* 0x0000000705077224 */
/* 0x000fd200078e0200 */
/*0140*/ IMAD.WIDE R4, R7, R6, c[0x0][0x168] ; /* 0x00005a0007047625 */
/* 0x000fc800078e0206 */
/*0150*/ IMAD.WIDE R2, R7.reuse, R6.reuse, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x0c0fe400078e0206 */
/*0160*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IMAD.WIDE R6, R7, R6, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x000fe200078e0206 */
/*0190*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*01a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addMatrixPiS_S_S_S_
.globl _Z9addMatrixPiS_S_S_S_
.p2align 8
.type _Z9addMatrixPiS_S_S_S_,@function
_Z9addMatrixPiS_S_S_S_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b32 s5, s[0:1], 0x34
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_load_b32 s4, s[2:3], 0x0
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s5, v[3:4]
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x18
s_load_b32 s2, s[2:3], 0xc
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_load_b32 s3, s[6:7], 0x0
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b128 s[8:11], s[0:1], 0x0
v_mad_u64_u32 v[3:4], null, v2, s4, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addMatrixPiS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addMatrixPiS_S_S_S_, .Lfunc_end0-_Z9addMatrixPiS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addMatrixPiS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9addMatrixPiS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000446f0_00000000-6_matrix_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z9addMatrixPiS_S_S_S_PiS_S_S_S_
.type _Z36__device_stub__Z9addMatrixPiS_S_S_S_PiS_S_S_S_, @function
_Z36__device_stub__Z9addMatrixPiS_S_S_S_PiS_S_S_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9addMatrixPiS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z36__device_stub__Z9addMatrixPiS_S_S_S_PiS_S_S_S_, .-_Z36__device_stub__Z9addMatrixPiS_S_S_S_PiS_S_S_S_
.globl _Z9addMatrixPiS_S_S_S_
.type _Z9addMatrixPiS_S_S_S_, @function
_Z9addMatrixPiS_S_S_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z9addMatrixPiS_S_S_S_PiS_S_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9addMatrixPiS_S_S_S_, .-_Z9addMatrixPiS_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC5:
.string "%lli\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
leaq .LC0(%rip), %rbx
movq %rbx, %rdi
call __isoc23_scanf@PLT
leaq 4(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 4(%rsp), %r13d
imull (%rsp), %r13d
sall $2, %r13d
movslq %r13d, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl (%rsp), %r9d
testl %r9d, %r9d
jle .L12
movl 4(%rsp), %r8d
movl %r8d, %ecx
movl $0, %edi
movl $0, %esi
jmp .L13
.L14:
movl %eax, (%rbx,%rdx)
movl %eax, 0(%rbp,%rdx)
addl $1, %eax
addq $4, %rdx
cmpl %ecx, %eax
jne .L14
.L16:
addl $1, %esi
addl %r8d, %edi
addl $1, %ecx
cmpl %r9d, %esi
je .L12
.L13:
movl %esi, %eax
movslq %edi, %rdx
salq $2, %rdx
testl %r8d, %r8d
jg .L14
jmp .L16
.L12:
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl (%rsp), %xmm0
mulss .LC1(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC6(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC2(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L17
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC4(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L17:
pxor %xmm0, %xmm0
cvtsi2ssl 4(%rsp), %xmm0
mulss .LC1(%rip), %xmm0
movaps %xmm0, %xmm4
movss .LC6(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC2(%rip), %xmm5
ucomiss %xmm2, %xmm5
jbe .L18
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm4
movss .LC4(%rip), %xmm5
andps %xmm5, %xmm4
addss %xmm2, %xmm4
andnps %xmm0, %xmm3
orps %xmm3, %xmm4
.L18:
cvttss2siq %xmm4, %rax
movl %eax, 48(%rsp)
cvttss2siq %xmm1, %rax
movl %eax, 52(%rsp)
movl $16, 60(%rsp)
movl $16, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L19:
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl (%rsp), %r10d
testl %r10d, %r10d
jle .L26
movl 4(%rsp), %r9d
movl $0, %r8d
movl $0, %edx
movl $0, %edi
movslq %r9d, %r11
jmp .L21
.L31:
movq 40(%rsp), %r8
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z36__device_stub__Z9addMatrixPiS_S_S_S_PiS_S_S_S_
jmp .L19
.L23:
movslq %r8d, %rcx
leaq (%r12,%rcx,4), %rax
addq %r11, %rcx
leaq (%r12,%rcx,4), %rsi
.L22:
movslq (%rax), %rcx
addq %rcx, %rdx
addq $4, %rax
cmpq %rsi, %rax
jne .L22
.L24:
addl $1, %edi
addl %r9d, %r8d
cmpl %r10d, %edi
je .L20
.L21:
testl %r9d, %r9d
jg .L23
jmp .L24
.L26:
movl $0, %edx
.L20:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z9addMatrixPiS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addMatrixPiS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1031798784
.align 4
.LC2:
.long 1258291200
.align 4
.LC4:
.long 1065353216
.align 4
.LC6:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_add.hip"
.globl _Z24__device_stub__addMatrixPiS_S_S_S_ # -- Begin function _Z24__device_stub__addMatrixPiS_S_S_S_
.p2align 4, 0x90
.type _Z24__device_stub__addMatrixPiS_S_S_S_,@function
_Z24__device_stub__addMatrixPiS_S_S_S_: # @_Z24__device_stub__addMatrixPiS_S_S_S_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9addMatrixPiS_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z24__device_stub__addMatrixPiS_S_S_S_, .Lfunc_end0-_Z24__device_stub__addMatrixPiS_S_S_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3d800000 # float 0.0625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $192, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r13d, %r13d
leaq 12(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
leaq 8(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 12(%rsp), %eax
imull 8(%rsp), %eax
shll $2, %eax
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
leaq 48(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_6
# %bb.1: # %.preheader49.lr.ph
movl 8(%rsp), %ecx
xorl %edx, %edx
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rdx
addl %ecx, %r13d
cmpq %rax, %rdx
je .LBB1_6
.LBB1_2: # %.preheader49
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %ecx, %ecx
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r13d, %edi
leaq (%rbx,%rdi,4), %rsi
leaq (%r14,%rdi,4), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rdx,%r8), %r9d
movl %r9d, (%rdi,%r8,4)
movl %r9d, (%rsi,%r8,4)
incq %r8
cmpq %r8, %rcx
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge52
movq 48(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 8(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
cvtsi2ssl 8(%rsp), %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r13
xorps %xmm0, %xmm0
cvtsi2ssl 12(%rsp), %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rdi
movl %r13d, %eax
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdi, 104(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z9addMatrixPiS_S_S_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 32(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl 12(%rsp), %eax
xorl %ecx, %ecx
testl %eax, %eax
jle .LBB1_9
# %bb.10: # %.preheader.lr.ph
movl 8(%rsp), %edx
xorl %edi, %edi
xorl %esi, %esi
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_14: # %._crit_edge56
# in Loop: Header=BB1_11 Depth=1
incq %rdi
addl %edx, %ecx
cmpq %rax, %rdi
je .LBB1_15
.LBB1_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_13 Depth 2
testl %edx, %edx
jle .LBB1_14
# %bb.12: # %.lr.ph55
# in Loop: Header=BB1_11 Depth=1
movl %ecx, %r8d
leaq (%r15,%r8,4), %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB1_13: # Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movslq (%r8,%r9,4), %r10
addq %r10, %rsi
incq %r9
cmpq %r9, %rdx
jne .LBB1_13
jmp .LBB1_14
.LBB1_9:
xorl %esi, %esi
.LBB1_15: # %._crit_edge59
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $192, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addMatrixPiS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addMatrixPiS_S_S_S_,@object # @_Z9addMatrixPiS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z9addMatrixPiS_S_S_S_
.p2align 3, 0x0
_Z9addMatrixPiS_S_S_S_:
.quad _Z24__device_stub__addMatrixPiS_S_S_S_
.size _Z9addMatrixPiS_S_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%lli\n"
.size .L.str.1, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addMatrixPiS_S_S_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addMatrixPiS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addMatrixPiS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<cuda_runtime.h>
#include<device_launch_parameters.h>
#include<stdlib.h>
#include<stdio.h>
#include<iostream>
#include<math.h>
#include<assert.h>
using namespace std;
__global__ void array_sum(int* v, int* r)
{
__shared__ int partial_sum[1024];
int tid = blockIdx.x*blockDim.x + threadIdx.x;
partial_sum[threadIdx.x] = v[tid];
__syncthreads();
for(int s = blockDim.x/2; s>0; s>>=1)
{
if(threadIdx.x<s)
{
partial_sum[threadIdx.x] += partial_sum[threadIdx.x+s];
}
__syncthreads();
}
if(threadIdx.x == 0)
{
r[blockIdx.x] = partial_sum[0];
}
}
int main(int argc, char const *argv[])
{
int n;
srand(0);
cout<<"Enter value for n"<<endl;
cin>>n;
int *v, *r;
int *d_v, *d_r;
v = (int*)malloc(n*sizeof(int));
r = (int*)malloc(n*sizeof(int));
cudaMalloc(&d_v, n*sizeof(int));
cudaMalloc(&d_r, n*sizeof(int));
for(int i=0;i<n;i++)
{
v[i] = rand()%100;
}
cudaMemcpy(d_v, v, n*sizeof(int), cudaMemcpyHostToDevice);
int num_threads = 256;
int num_blocks = n/num_threads;
array_sum<<<num_blocks, num_threads>>> (d_v, d_r);
array_sum<<<1, num_threads>>> (d_r, d_r);
cudaMemcpy(r, d_r, n*sizeof(int), cudaMemcpyDeviceToHost);
cout<<"Array Sum: "<<r[0]<<endl;
return 0;
} | code for sm_80
Function : _Z9array_sumPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0090*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00b0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00c0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00e0*/ @!P1 BRA 0x1b0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe200078e00ff */
/*0100*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0110*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0120*/ @!P1 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x000fe200078e0200 */
/*0130*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0140*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0150*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0160*/ @!P1 IADD3 R4, R4, R5, RZ ; /* 0x0000000504049210 */
/* 0x001fca0007ffe0ff */
/*0170*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01a0*/ @P1 BRA 0x110 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01c0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*01d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<cuda_runtime.h>
#include<device_launch_parameters.h>
#include<stdlib.h>
#include<stdio.h>
#include<iostream>
#include<math.h>
#include<assert.h>
using namespace std;
__global__ void array_sum(int* v, int* r)
{
__shared__ int partial_sum[1024];
int tid = blockIdx.x*blockDim.x + threadIdx.x;
partial_sum[threadIdx.x] = v[tid];
__syncthreads();
for(int s = blockDim.x/2; s>0; s>>=1)
{
if(threadIdx.x<s)
{
partial_sum[threadIdx.x] += partial_sum[threadIdx.x+s];
}
__syncthreads();
}
if(threadIdx.x == 0)
{
r[blockIdx.x] = partial_sum[0];
}
}
int main(int argc, char const *argv[])
{
int n;
srand(0);
cout<<"Enter value for n"<<endl;
cin>>n;
int *v, *r;
int *d_v, *d_r;
v = (int*)malloc(n*sizeof(int));
r = (int*)malloc(n*sizeof(int));
cudaMalloc(&d_v, n*sizeof(int));
cudaMalloc(&d_r, n*sizeof(int));
for(int i=0;i<n;i++)
{
v[i] = rand()%100;
}
cudaMemcpy(d_v, v, n*sizeof(int), cudaMemcpyHostToDevice);
int num_threads = 256;
int num_blocks = n/num_threads;
array_sum<<<num_blocks, num_threads>>> (d_v, d_r);
array_sum<<<1, num_threads>>> (d_r, d_r);
cudaMemcpy(r, d_r, n*sizeof(int), cudaMemcpyDeviceToHost);
cout<<"Array Sum: "<<r[0]<<endl;
return 0;
} | .file "tmpxft_00120224_00000000-6_array_sum.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9array_sumPiS_PiS_
.type _Z30__device_stub__Z9array_sumPiS_PiS_, @function
_Z30__device_stub__Z9array_sumPiS_PiS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9array_sumPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z30__device_stub__Z9array_sumPiS_PiS_, .-_Z30__device_stub__Z9array_sumPiS_PiS_
.globl _Z9array_sumPiS_
.type _Z9array_sumPiS_, @function
_Z9array_sumPiS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9array_sumPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9array_sumPiS_, .-_Z9array_sumPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter value for n"
.LC1:
.string "Array Sum: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $0, %edi
call srand@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 12(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movslq 12(%rsp), %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movslq 12(%rsp), %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl 12(%rsp), %edx
testl %edx, %edx
jle .L12
movl $0, %ebx
.L13:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, 0(%rbp,%rbx,4)
movl 12(%rsp), %edx
addq $1, %rbx
cmpl %ebx, %edx
jg .L13
.L12:
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %edx
leal 255(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $8, %eax
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L14:
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L15:
movslq 12(%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl (%r12), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z9array_sumPiS_PiS_
jmp .L14
.L20:
movq 24(%rsp), %rdi
movq %rdi, %rsi
call _Z30__device_stub__Z9array_sumPiS_PiS_
jmp .L15
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z9array_sumPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9array_sumPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<cuda_runtime.h>
#include<device_launch_parameters.h>
#include<stdlib.h>
#include<stdio.h>
#include<iostream>
#include<math.h>
#include<assert.h>
using namespace std;
__global__ void array_sum(int* v, int* r)
{
__shared__ int partial_sum[1024];
int tid = blockIdx.x*blockDim.x + threadIdx.x;
partial_sum[threadIdx.x] = v[tid];
__syncthreads();
for(int s = blockDim.x/2; s>0; s>>=1)
{
if(threadIdx.x<s)
{
partial_sum[threadIdx.x] += partial_sum[threadIdx.x+s];
}
__syncthreads();
}
if(threadIdx.x == 0)
{
r[blockIdx.x] = partial_sum[0];
}
}
int main(int argc, char const *argv[])
{
int n;
srand(0);
cout<<"Enter value for n"<<endl;
cin>>n;
int *v, *r;
int *d_v, *d_r;
v = (int*)malloc(n*sizeof(int));
r = (int*)malloc(n*sizeof(int));
cudaMalloc(&d_v, n*sizeof(int));
cudaMalloc(&d_r, n*sizeof(int));
for(int i=0;i<n;i++)
{
v[i] = rand()%100;
}
cudaMemcpy(d_v, v, n*sizeof(int), cudaMemcpyHostToDevice);
int num_threads = 256;
int num_blocks = n/num_threads;
array_sum<<<num_blocks, num_threads>>> (d_v, d_r);
array_sum<<<1, num_threads>>> (d_r, d_r);
cudaMemcpy(r, d_r, n*sizeof(int), cudaMemcpyDeviceToHost);
cout<<"Array Sum: "<<r[0]<<endl;
return 0;
} | #include<hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include<iostream>
#include<math.h>
#include<assert.h>
using namespace std;
__global__ void array_sum(int* v, int* r)
{
__shared__ int partial_sum[1024];
int tid = blockIdx.x*blockDim.x + threadIdx.x;
partial_sum[threadIdx.x] = v[tid];
__syncthreads();
for(int s = blockDim.x/2; s>0; s>>=1)
{
if(threadIdx.x<s)
{
partial_sum[threadIdx.x] += partial_sum[threadIdx.x+s];
}
__syncthreads();
}
if(threadIdx.x == 0)
{
r[blockIdx.x] = partial_sum[0];
}
}
int main(int argc, char const *argv[])
{
int n;
srand(0);
cout<<"Enter value for n"<<endl;
cin>>n;
int *v, *r;
int *d_v, *d_r;
v = (int*)malloc(n*sizeof(int));
r = (int*)malloc(n*sizeof(int));
hipMalloc(&d_v, n*sizeof(int));
hipMalloc(&d_r, n*sizeof(int));
for(int i=0;i<n;i++)
{
v[i] = rand()%100;
}
hipMemcpy(d_v, v, n*sizeof(int), hipMemcpyHostToDevice);
int num_threads = 256;
int num_blocks = n/num_threads;
array_sum<<<num_blocks, num_threads>>> (d_v, d_r);
array_sum<<<1, num_threads>>> (d_r, d_r);
hipMemcpy(r, d_r, n*sizeof(int), hipMemcpyDeviceToHost);
cout<<"Array Sum: "<<r[0]<<endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include<iostream>
#include<math.h>
#include<assert.h>
using namespace std;
__global__ void array_sum(int* v, int* r)
{
__shared__ int partial_sum[1024];
int tid = blockIdx.x*blockDim.x + threadIdx.x;
partial_sum[threadIdx.x] = v[tid];
__syncthreads();
for(int s = blockDim.x/2; s>0; s>>=1)
{
if(threadIdx.x<s)
{
partial_sum[threadIdx.x] += partial_sum[threadIdx.x+s];
}
__syncthreads();
}
if(threadIdx.x == 0)
{
r[blockIdx.x] = partial_sum[0];
}
}
int main(int argc, char const *argv[])
{
int n;
srand(0);
cout<<"Enter value for n"<<endl;
cin>>n;
int *v, *r;
int *d_v, *d_r;
v = (int*)malloc(n*sizeof(int));
r = (int*)malloc(n*sizeof(int));
hipMalloc(&d_v, n*sizeof(int));
hipMalloc(&d_r, n*sizeof(int));
for(int i=0;i<n;i++)
{
v[i] = rand()%100;
}
hipMemcpy(d_v, v, n*sizeof(int), hipMemcpyHostToDevice);
int num_threads = 256;
int num_blocks = n/num_threads;
array_sum<<<num_blocks, num_threads>>> (d_v, d_r);
array_sum<<<1, num_threads>>> (d_r, d_r);
hipMemcpy(r, d_r, n*sizeof(int), hipMemcpyDeviceToHost);
cout<<"Array Sum: "<<r[0]<<endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9array_sumPiS_
.globl _Z9array_sumPiS_
.p2align 8
.type _Z9array_sumPiS_,@function
_Z9array_sumPiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_cmp_lt_u32 s3, 2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB0_2:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_1
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_1
.LBB0_5:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9array_sumPiS_
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9array_sumPiS_, .Lfunc_end0-_Z9array_sumPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9array_sumPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9array_sumPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include<iostream>
#include<math.h>
#include<assert.h>
using namespace std;
__global__ void array_sum(int* v, int* r)
{
__shared__ int partial_sum[1024];
int tid = blockIdx.x*blockDim.x + threadIdx.x;
partial_sum[threadIdx.x] = v[tid];
__syncthreads();
for(int s = blockDim.x/2; s>0; s>>=1)
{
if(threadIdx.x<s)
{
partial_sum[threadIdx.x] += partial_sum[threadIdx.x+s];
}
__syncthreads();
}
if(threadIdx.x == 0)
{
r[blockIdx.x] = partial_sum[0];
}
}
int main(int argc, char const *argv[])
{
int n;
srand(0);
cout<<"Enter value for n"<<endl;
cin>>n;
int *v, *r;
int *d_v, *d_r;
v = (int*)malloc(n*sizeof(int));
r = (int*)malloc(n*sizeof(int));
hipMalloc(&d_v, n*sizeof(int));
hipMalloc(&d_r, n*sizeof(int));
for(int i=0;i<n;i++)
{
v[i] = rand()%100;
}
hipMemcpy(d_v, v, n*sizeof(int), hipMemcpyHostToDevice);
int num_threads = 256;
int num_blocks = n/num_threads;
array_sum<<<num_blocks, num_threads>>> (d_v, d_r);
array_sum<<<1, num_threads>>> (d_r, d_r);
hipMemcpy(r, d_r, n*sizeof(int), hipMemcpyDeviceToHost);
cout<<"Array Sum: "<<r[0]<<endl;
return 0;
} | .text
.file "array_sum.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__array_sumPiS_ # -- Begin function _Z24__device_stub__array_sumPiS_
.p2align 4, 0x90
.type _Z24__device_stub__array_sumPiS_,@function
_Z24__device_stub__array_sumPiS_: # @_Z24__device_stub__array_sumPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9array_sumPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__array_sumPiS_, .Lfunc_end0-_Z24__device_stub__array_sumPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %edi, %edi
callq srand
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_16
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 4(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movslq 4(%rsp), %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq %r14, %rdi
callq malloc
movq %rax, %rbx
leaq 104(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movslq 4(%rsp), %rsi
shlq $2, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_7
# %bb.5: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r15,%r14,4)
incq %r14
movslq 4(%rsp), %rax
cmpq %rax, %r14
jl .LBB1_6
.LBB1_7: # %._crit_edge
movabsq $4294967552, %r14 # imm = 0x100000100
movq 104(%rsp), %rdi
movslq %eax, %rdx
shlq $2, %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %eax
leal 255(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $8, %ecx
leaq (%rcx,%r14), %rdi
addq $-256, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8:
movq 104(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9array_sumPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_9:
leaq -255(%r14), %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movq %rax, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9array_sumPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11:
movq 8(%rsp), %rsi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_16
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i25
cmpb $0, 56(%rbx)
je .LBB1_14
# %bb.13:
movzbl 67(%rbx), %ecx
jmp .LBB1_15
.LBB1_14:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit28
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_16:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9array_sumPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9array_sumPiS_,@object # @_Z9array_sumPiS_
.section .rodata,"a",@progbits
.globl _Z9array_sumPiS_
.p2align 3, 0x0
_Z9array_sumPiS_:
.quad _Z24__device_stub__array_sumPiS_
.size _Z9array_sumPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter value for n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Array Sum: "
.size .L.str.1, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9array_sumPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__array_sumPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9array_sumPiS_
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9array_sumPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0090*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00b0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00c0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00e0*/ @!P1 BRA 0x1b0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe200078e00ff */
/*0100*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0110*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0120*/ @!P1 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x000fe200078e0200 */
/*0130*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0140*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0150*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0160*/ @!P1 IADD3 R4, R4, R5, RZ ; /* 0x0000000504049210 */
/* 0x001fca0007ffe0ff */
/*0170*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01a0*/ @P1 BRA 0x110 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01c0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*01d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9array_sumPiS_
.globl _Z9array_sumPiS_
.p2align 8
.type _Z9array_sumPiS_,@function
_Z9array_sumPiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_cmp_lt_u32 s3, 2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB0_2:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_1
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_1
.LBB0_5:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9array_sumPiS_
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9array_sumPiS_, .Lfunc_end0-_Z9array_sumPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9array_sumPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9array_sumPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00120224_00000000-6_array_sum.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9array_sumPiS_PiS_
.type _Z30__device_stub__Z9array_sumPiS_PiS_, @function
_Z30__device_stub__Z9array_sumPiS_PiS_:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9array_sumPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z30__device_stub__Z9array_sumPiS_PiS_, .-_Z30__device_stub__Z9array_sumPiS_PiS_
.globl _Z9array_sumPiS_
.type _Z9array_sumPiS_, @function
_Z9array_sumPiS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9array_sumPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9array_sumPiS_, .-_Z9array_sumPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter value for n"
.LC1:
.string "Array Sum: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $0, %edi
call srand@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 12(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movslq 12(%rsp), %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movslq 12(%rsp), %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl 12(%rsp), %edx
testl %edx, %edx
jle .L12
movl $0, %ebx
.L13:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, 0(%rbp,%rbx,4)
movl 12(%rsp), %edx
addq $1, %rbx
cmpl %ebx, %edx
jg .L13
.L12:
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %edx
leal 255(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $8, %eax
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L14:
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L15:
movslq 12(%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl (%r12), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z9array_sumPiS_PiS_
jmp .L14
.L20:
movq 24(%rsp), %rdi
movq %rdi, %rsi
call _Z30__device_stub__Z9array_sumPiS_PiS_
jmp .L15
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z9array_sumPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9array_sumPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "array_sum.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__array_sumPiS_ # -- Begin function _Z24__device_stub__array_sumPiS_
.p2align 4, 0x90
.type _Z24__device_stub__array_sumPiS_,@function
_Z24__device_stub__array_sumPiS_: # @_Z24__device_stub__array_sumPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9array_sumPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__array_sumPiS_, .Lfunc_end0-_Z24__device_stub__array_sumPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %edi, %edi
callq srand
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_16
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 4(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movslq 4(%rsp), %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq %r14, %rdi
callq malloc
movq %rax, %rbx
leaq 104(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movslq 4(%rsp), %rsi
shlq $2, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_7
# %bb.5: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r15,%r14,4)
incq %r14
movslq 4(%rsp), %rax
cmpq %rax, %r14
jl .LBB1_6
.LBB1_7: # %._crit_edge
movabsq $4294967552, %r14 # imm = 0x100000100
movq 104(%rsp), %rdi
movslq %eax, %rdx
shlq $2, %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %eax
leal 255(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $8, %ecx
leaq (%rcx,%r14), %rdi
addq $-256, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8:
movq 104(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9array_sumPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_9:
leaq -255(%r14), %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movq %rax, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9array_sumPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11:
movq 8(%rsp), %rsi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_16
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i25
cmpb $0, 56(%rbx)
je .LBB1_14
# %bb.13:
movzbl 67(%rbx), %ecx
jmp .LBB1_15
.LBB1_14:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit28
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_16:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9array_sumPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9array_sumPiS_,@object # @_Z9array_sumPiS_
.section .rodata,"a",@progbits
.globl _Z9array_sumPiS_
.p2align 3, 0x0
_Z9array_sumPiS_:
.quad _Z24__device_stub__array_sumPiS_
.size _Z9array_sumPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter value for n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Array Sum: "
.size .L.str.1, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9array_sumPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__array_sumPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9array_sumPiS_
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#define NUM_THREADS_PER_BLOCK 256
__global__
void print_hello()
{
int idx = threadIdx.x;
printf("Hello World! My threadId is %d\n", idx);
}
int main()
{
print_hello<<<1, NUM_THREADS_PER_BLOCK>>>();
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z11print_hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f1e0ff */
/*0070*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0090*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100800 */
/*00a0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00b0*/ MOV R11, 0x120 ; /* 0x00000120000b7802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R20, 0xa0 ; /* 0x000000a000147802 */
/* 0x000fc40000000f00 */
/*00d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0100*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0110*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
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