system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#define NUM_THREADS_PER_BLOCK 256
__global__
void print_hello()
{
int idx = threadIdx.x;
printf("Hello World! My threadId is %d\n", idx);
}
int main()
{
print_hello<<<1, NUM_THREADS_PER_BLOCK>>>();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_00185772_00000000-6_hello_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z11print_hellovv
.type _Z30__device_stub__Z11print_hellovv, @function
_Z30__device_stub__Z11print_hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11print_hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z11print_hellovv, .-_Z30__device_stub__Z11print_hellovv
.globl _Z11print_hellov
.type _Z11print_hellov, @function
_Z11print_hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11print_hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11print_hellov, .-_Z11print_hellov
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z30__device_stub__Z11print_hellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11print_hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11print_hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#define NUM_THREADS_PER_BLOCK 256
__global__
void print_hello()
{
int idx = threadIdx.x;
printf("Hello World! My threadId is %d\n", idx);
}
int main()
{
print_hello<<<1, NUM_THREADS_PER_BLOCK>>>();
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#define NUM_THREADS_PER_BLOCK 256
__global__
void print_hello()
{
int idx = threadIdx.x;
printf("Hello World! My threadId is %d\n", idx);
}
int main()
{
print_hello<<<1, NUM_THREADS_PER_BLOCK>>>();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#define NUM_THREADS_PER_BLOCK 256
__global__
void print_hello()
{
int idx = threadIdx.x;
printf("Hello World! My threadId is %d\n", idx);
}
int main()
{
print_hello<<<1, NUM_THREADS_PER_BLOCK>>>();
hipDeviceSynchronize();
return 0;
} | .text
.file "hello_world.hip"
.globl _Z26__device_stub__print_hellov # -- Begin function _Z26__device_stub__print_hellov
.p2align 4, 0x90
.type _Z26__device_stub__print_hellov,@function
_Z26__device_stub__print_hellov: # @_Z26__device_stub__print_hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11print_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z26__device_stub__print_hellov, .Lfunc_end0-_Z26__device_stub__print_hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11print_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11print_hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11print_hellov,@object # @_Z11print_hellov
.section .rodata,"a",@progbits
.globl _Z11print_hellov
.p2align 3, 0x0
_Z11print_hellov:
.quad _Z26__device_stub__print_hellov
.size _Z11print_hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11print_hellov"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__print_hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11print_hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00185772_00000000-6_hello_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z11print_hellovv
.type _Z30__device_stub__Z11print_hellovv, @function
_Z30__device_stub__Z11print_hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11print_hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z11print_hellovv, .-_Z30__device_stub__Z11print_hellovv
.globl _Z11print_hellov
.type _Z11print_hellov, @function
_Z11print_hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11print_hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11print_hellov, .-_Z11print_hellov
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z30__device_stub__Z11print_hellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11print_hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11print_hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello_world.hip"
.globl _Z26__device_stub__print_hellov # -- Begin function _Z26__device_stub__print_hellov
.p2align 4, 0x90
.type _Z26__device_stub__print_hellov,@function
_Z26__device_stub__print_hellov: # @_Z26__device_stub__print_hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11print_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z26__device_stub__print_hellov, .Lfunc_end0-_Z26__device_stub__print_hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11print_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11print_hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11print_hellov,@object # @_Z11print_hellov
.section .rodata,"a",@progbits
.globl _Z11print_hellov
.p2align 3, 0x0
_Z11print_hellov:
.quad _Z26__device_stub__print_hellov
.size _Z11print_hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11print_hellov"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__print_hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11print_hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <string>
#include <fstream>
#include <sstream>
#include <list>
#include <iterator>
#include "file_handler.cuh"
void prepareFile(std::string fileName, bool truncate) {
std::ofstream resFile (fileName, (truncate ? std::ofstream::out | std::ofstream::trunc : std::ios_base::app));
resFile << "[";
resFile.close();
}
void finishFile(std::string fileName, bool removeLast) {
std::ifstream resFile1 (fileName);
std::stringstream buffer;
buffer << resFile1.rdbuf();
std::string contents = buffer.str();
resFile1.close();
if(removeLast)
contents.pop_back();
contents += "]\n";
std::ofstream resFile2 (fileName, std::ofstream::out | std::ofstream::trunc);
resFile2 << contents;
resFile2.close();
}
void writeLogNormConstToFile(double logNormConstant) {
// std::ofstream resFile (fileName);
std::ofstream resFile (Z_FILE_NAME, std::ios_base::app); // If append to file is wanted
if(resFile.is_open()) {
resFile << logNormConstant << ",";
resFile.close();
} else {
printf("Could not open file %s\n", Z_FILE_NAME.c_str());
}
}
void writeESSToFile(std::list<double> essList) {
// std::ofstream resFile (fileName);
std::ofstream resFile (ESS_FILE_NAME, std::ios_base::app); // If append to file is wanted
if(resFile.is_open()) {
resFile << "[";
std::list <double> :: iterator it;
for(it = essList.begin(); it != essList.end(); ++it)
resFile << *it << " ";
resFile << "],\n";
resFile.close();
} else {
printf("Could not open file %s\n", ESS_FILE_NAME.c_str());
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <string>
#include <fstream>
#include <sstream>
#include <list>
#include <iterator>
#include "file_handler.cuh"
void prepareFile(std::string fileName, bool truncate) {
std::ofstream resFile (fileName, (truncate ? std::ofstream::out | std::ofstream::trunc : std::ios_base::app));
resFile << "[";
resFile.close();
}
void finishFile(std::string fileName, bool removeLast) {
std::ifstream resFile1 (fileName);
std::stringstream buffer;
buffer << resFile1.rdbuf();
std::string contents = buffer.str();
resFile1.close();
if(removeLast)
contents.pop_back();
contents += "]\n";
std::ofstream resFile2 (fileName, std::ofstream::out | std::ofstream::trunc);
resFile2 << contents;
resFile2.close();
}
void writeLogNormConstToFile(double logNormConstant) {
// std::ofstream resFile (fileName);
std::ofstream resFile (Z_FILE_NAME, std::ios_base::app); // If append to file is wanted
if(resFile.is_open()) {
resFile << logNormConstant << ",";
resFile.close();
} else {
printf("Could not open file %s\n", Z_FILE_NAME.c_str());
}
}
void writeESSToFile(std::list<double> essList) {
// std::ofstream resFile (fileName);
std::ofstream resFile (ESS_FILE_NAME, std::ios_base::app); // If append to file is wanted
if(resFile.is_open()) {
resFile << "[";
std::list <double> :: iterator it;
for(it = essList.begin(); it != essList.end(); ++it)
resFile << *it << " ";
resFile << "],\n";
resFile.close();
} else {
printf("Could not open file %s\n", ESS_FILE_NAME.c_str());
}
} | #ifndef FILE_HANDLER_INCLUDED
#define FILE_HANDLER_INCLUDED
#include <string>
#include <list>
const std::string Z_FILE_NAME = "log_norm_const.txt";
const std::string ESS_FILE_NAME = "ess.txt";
/**
* Optionally clears the file, and writes an opening bracket to it.
*
* @param fileName the name of the file to save to.
* @param truncate if the file should be cleared first.
*/
void prepareFile(std::string fileName, bool truncate);
/**
* Optionally removes the last character of the file, and writes a closing bracket and new line to it.
*
* @param fileName the name of the file to save to.
* @param removeLast if the last character of the file should be deleted before closing it.
*/
void finishFile(std::string fileName, bool removeLast);
/**
* Writes the approximated log normalization constant to file. The file is cleared before the
* program starts and if multiple runs is performed, the values from each run is appended to this file.
*
* @param logNormConstant
*/
void writeLogNormConstToFile(double logNormConstant);
/**
* Writes the effective sample size (ESS) to file. The file is cleared before the program
* starts.
*
* @param ess
*/
void writeESSToFile(std::list<double> essList);
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef FILE_HANDLER_INCLUDED
#define FILE_HANDLER_INCLUDED
#include <string>
#include <list>
const std::string Z_FILE_NAME = "log_norm_const.txt";
const std::string ESS_FILE_NAME = "ess.txt";
/**
* Optionally clears the file, and writes an opening bracket to it.
*
* @param fileName the name of the file to save to.
* @param truncate if the file should be cleared first.
*/
void prepareFile(std::string fileName, bool truncate);
/**
* Optionally removes the last character of the file, and writes a closing bracket and new line to it.
*
* @param fileName the name of the file to save to.
* @param removeLast if the last character of the file should be deleted before closing it.
*/
void finishFile(std::string fileName, bool removeLast);
/**
* Writes the approximated log normalization constant to file. The file is cleared before the
* program starts and if multiple runs is performed, the values from each run is appended to this file.
*
* @param logNormConstant
*/
void writeLogNormConstToFile(double logNormConstant);
/**
* Writes the effective sample size (ESS) to file. The file is cleared before the program
* starts.
*
* @param ess
*/
void writeESSToFile(std::list<double> essList);
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef FILE_HANDLER_INCLUDED
#define FILE_HANDLER_INCLUDED
#include <string>
#include <list>
const std::string Z_FILE_NAME = "log_norm_const.txt";
const std::string ESS_FILE_NAME = "ess.txt";
/**
* Optionally clears the file, and writes an opening bracket to it.
*
* @param fileName the name of the file to save to.
* @param truncate if the file should be cleared first.
*/
void prepareFile(std::string fileName, bool truncate);
/**
* Optionally removes the last character of the file, and writes a closing bracket and new line to it.
*
* @param fileName the name of the file to save to.
* @param removeLast if the last character of the file should be deleted before closing it.
*/
void finishFile(std::string fileName, bool removeLast);
/**
* Writes the approximated log normalization constant to file. The file is cleared before the
* program starts and if multiple runs is performed, the values from each run is appended to this file.
*
* @param logNormConstant
*/
void writeLogNormConstToFile(double logNormConstant);
/**
* Writes the effective sample size (ESS) to file. The file is cleared before the program
* starts.
*
* @param ess
*/
void writeESSToFile(std::list<double> essList);
#endif | .text
.file "file_handler.hip"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev
.p2align 4, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev
.cfi_startproc
# %bb.0:
movq %rdi, %rax
movq (%rdi), %rdi
addq $16, %rax
cmpq %rax, %rdi
jne _ZdlPv # TAILCALL
# %bb.1: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv.exit
retq
.Lfunc_end0:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev, .Lfunc_end0-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev
.cfi_endproc
# -- End function
.section .text.startup,"ax",@progbits
.p2align 4, 0x90 # -- Begin function _GLOBAL__sub_I_file_handler.hip
.type _GLOBAL__sub_I_file_handler.hip,@function
_GLOBAL__sub_I_file_handler.hip: # @_GLOBAL__sub_I_file_handler.hip
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq $_ZL11Z_FILE_NAMEB5cxx11+16, _ZL11Z_FILE_NAMEB5cxx11(%rip)
movl $19, %edi
callq _Znwm
movq %rax, _ZL11Z_FILE_NAMEB5cxx11(%rip)
movq $18, _ZL11Z_FILE_NAMEB5cxx11+16(%rip)
movups .L.str(%rip), %xmm0
movups %xmm0, (%rax)
movw $29816, 16(%rax) # imm = 0x7478
movq $18, _ZL11Z_FILE_NAMEB5cxx11+8(%rip)
movb $0, 18(%rax)
movl $_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev, %edi
movl $_ZL11Z_FILE_NAMEB5cxx11, %esi
movl $__dso_handle, %edx
popq %rax
.cfi_def_cfa_offset 8
jmp __cxa_atexit # TAILCALL
.Lfunc_end1:
.size _GLOBAL__sub_I_file_handler.hip, .Lfunc_end1-_GLOBAL__sub_I_file_handler.hip
.cfi_endproc
# -- End function
.type _ZL11Z_FILE_NAMEB5cxx11,@object # @_ZL11Z_FILE_NAMEB5cxx11
.local _ZL11Z_FILE_NAMEB5cxx11
.comm _ZL11Z_FILE_NAMEB5cxx11,32,8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "log_norm_const.txt"
.size .L.str, 19
.hidden __dso_handle
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad _GLOBAL__sub_I_file_handler.hip
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _GLOBAL__sub_I_file_handler.hip
.addrsig_sym _ZL11Z_FILE_NAMEB5cxx11
.addrsig_sym __dso_handle
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <sys/time.h>
#include <time.h>
#include <cuda.h>
#include <curand.h>
#include <curand_kernel.h>
const int boardSize = 21;
const int totalSize = boardSize * boardSize;
struct BoardPoint{
int color;
int groupID;
int libertyNumber;
bool isBlackLegal;
bool isWhiteLegal;
};
__global__
void randomInit(curandState *state, long randSeed){
int index = threadIdx.y*boardSize + threadIdx.x;
//curandState state;
// long seed = 123456;
curand_init(randSeed, index, 0, &state[index]);
// boardPoint[index].color = curand(&state);
}
__global__
void randomTest(BoardPoint *boardPoint, curandState *state){
int index = threadIdx.y*boardSize + threadIdx.x;
// curandState state;
// long seed = 123456;
// curand_init(seed, index, 0, &state);
boardPoint[index].color = (curand(&state[index])>>16)%361;
}
int main()
{
BoardPoint boardHost[totalSize];
BoardPoint *boardDevice;
curandState *stateDevice;
// DebugFlag debugFlagHost[totalSize];
// DebugFlag *debugFlagDevice;
//
const int valueSizeDevice = totalSize*sizeof(BoardPoint);
// const int debugFlagSize = totalSize*sizeof(DebugFlag);
//
cudaMalloc( (void**)&boardDevice, valueSizeDevice );
cudaMalloc( (void**)&stateDevice, valueSizeDevice );
// cudaMalloc( (void**)&debugFlagDevice, debugFlagSize );
//
//
dim3 threadShape( boardSize, boardSize );
int numberOfBlock = 1;
srand((unsigned int)time(NULL));
randomInit<<<numberOfBlock, threadShape>>>(stateDevice, rand());
struct timeval start_tv;
gettimeofday(&start_tv,NULL);
randomTest<<<numberOfBlock, threadShape>>>(boardDevice, stateDevice);
// for (int i=0; i<19; i++){
// playBoard<<<numberOfBlock, threadShape>>>(boardDevice, globalFlag, i, i, 2);
// }
cudaDeviceSynchronize();
cudaMemcpy( boardHost, boardDevice, valueSizeDevice, cudaMemcpyDeviceToHost );
// cudaMemcpy( debugFlagHost, debugFlagDevice, debugFlagSize, cudaMemcpyDeviceToHost );
//
//
cudaFree( boardDevice );
// cudaFree( debugFlagDevice );
//
cudaDeviceSynchronize();
//
struct timeval end_tv;
gettimeofday(&end_tv,NULL);
for (int i=boardSize-1; i>=0; i--){
for (int j=0; j<boardSize; j++){
int index = i*boardSize + j;
printf("%d| ",boardHost[index].color);
}
printf("\n");
}
if(end_tv.tv_usec >= start_tv.tv_usec){
printf("time %lu:%lu\n",end_tv.tv_sec - start_tv.tv_sec, end_tv.tv_usec - start_tv.tv_usec);
}else{
printf("time %lu:%lu\n",end_tv.tv_sec - start_tv.tv_sec - 1, 1000000 - start_tv.tv_usec + end_tv.tv_usec);
}
return EXIT_SUCCESS;
} | .file "tmpxft_0003d616_00000000-6_random_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z10randomInitP17curandStateXORWOWlP17curandStateXORWOWl
.type _Z49__device_stub__Z10randomInitP17curandStateXORWOWlP17curandStateXORWOWl, @function
_Z49__device_stub__Z10randomInitP17curandStateXORWOWlP17curandStateXORWOWl:
.LFB2296:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10randomInitP17curandStateXORWOWl(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z49__device_stub__Z10randomInitP17curandStateXORWOWlP17curandStateXORWOWl, .-_Z49__device_stub__Z10randomInitP17curandStateXORWOWlP17curandStateXORWOWl
.globl _Z10randomInitP17curandStateXORWOWl
.type _Z10randomInitP17curandStateXORWOWl, @function
_Z10randomInitP17curandStateXORWOWl:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z10randomInitP17curandStateXORWOWlP17curandStateXORWOWl
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z10randomInitP17curandStateXORWOWl, .-_Z10randomInitP17curandStateXORWOWl
.globl _Z61__device_stub__Z10randomTestP10BoardPointP17curandStateXORWOWP10BoardPointP17curandStateXORWOW
.type _Z61__device_stub__Z10randomTestP10BoardPointP17curandStateXORWOWP10BoardPointP17curandStateXORWOW, @function
_Z61__device_stub__Z10randomTestP10BoardPointP17curandStateXORWOWP10BoardPointP17curandStateXORWOW:
.LFB2298:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10randomTestP10BoardPointP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2298:
.size _Z61__device_stub__Z10randomTestP10BoardPointP17curandStateXORWOWP10BoardPointP17curandStateXORWOW, .-_Z61__device_stub__Z10randomTestP10BoardPointP17curandStateXORWOWP10BoardPointP17curandStateXORWOW
.globl _Z10randomTestP10BoardPointP17curandStateXORWOW
.type _Z10randomTestP10BoardPointP17curandStateXORWOW, @function
_Z10randomTestP10BoardPointP17curandStateXORWOW:
.LFB2299:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z61__device_stub__Z10randomTestP10BoardPointP17curandStateXORWOWP10BoardPointP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _Z10randomTestP10BoardPointP17curandStateXORWOW, .-_Z10randomTestP10BoardPointP17curandStateXORWOW
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d| "
.LC1:
.string "\n"
.LC2:
.string "time %lu:%lu\n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $4096, %rsp
.cfi_def_cfa_offset 4144
orq $0, (%rsp)
subq $3040, %rsp
.cfi_def_cfa_offset 7184
movq %fs:40, %rax
movq %rax, 7128(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $7056, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $7056, %esi
call cudaMalloc@PLT
movl $21, 20(%rsp)
movl $21, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L20:
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L21:
call cudaDeviceSynchronize@PLT
leaq 64(%rsp), %r13
movl $2, %ecx
movl $7056, %edx
movq (%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
call cudaDeviceSynchronize@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 7120(%rsp), %rbp
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r14
.L22:
leaq -336(%rbp), %rbx
.L23:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rbx
cmpq %rbp, %rbx
jne .L23
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subq $336, %rbp
cmpq %r13, %rbp
jne .L22
movq 56(%rsp), %rax
movq 40(%rsp), %rdx
cmpq %rdx, %rax
jl .L25
subq %rdx, %rax
movq %rax, %rcx
movq 48(%rsp), %rdx
subq 32(%rsp), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L26:
movq 7128(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $7136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call rand@PLT
movslq %eax, %rsi
movq 8(%rsp), %rdi
call _Z49__device_stub__Z10randomInitP17curandStateXORWOWlP17curandStateXORWOWl
jmp .L20
.L31:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z61__device_stub__Z10randomTestP10BoardPointP17curandStateXORWOWP10BoardPointP17curandStateXORWOW
jmp .L21
.L25:
subq %rdx, %rax
leaq 1000000(%rax), %rcx
movq 48(%rsp), %rdx
subq 32(%rsp), %rdx
subq $1, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "_Z10randomTestP10BoardPointP17curandStateXORWOW"
.align 8
.LC4:
.string "_Z10randomInitP17curandStateXORWOWl"
.section .rodata.str1.1
.LC5:
.string "precalc_xorwow_matrix"
.LC6:
.string "precalc_xorwow_offset_matrix"
.LC7:
.string "mrg32k3aM1"
.LC8:
.string "mrg32k3aM2"
.LC9:
.string "mrg32k3aM1SubSeq"
.LC10:
.string "mrg32k3aM2SubSeq"
.LC11:
.string "mrg32k3aM1Seq"
.LC12:
.string "mrg32k3aM2Seq"
.LC13:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2301:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10randomTestP10BoardPointP17curandStateXORWOW(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10randomInitP17curandStateXORWOWl(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2301:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <sys/time.h>
#include <time.h>
#include <cuda.h>
#include <curand.h>
#include <curand_kernel.h>
const int boardSize = 21;
const int totalSize = boardSize * boardSize;
struct BoardPoint{
int color;
int groupID;
int libertyNumber;
bool isBlackLegal;
bool isWhiteLegal;
};
__global__
void randomInit(curandState *state, long randSeed){
int index = threadIdx.y*boardSize + threadIdx.x;
//curandState state;
// long seed = 123456;
curand_init(randSeed, index, 0, &state[index]);
// boardPoint[index].color = curand(&state);
}
__global__
void randomTest(BoardPoint *boardPoint, curandState *state){
int index = threadIdx.y*boardSize + threadIdx.x;
// curandState state;
// long seed = 123456;
// curand_init(seed, index, 0, &state);
boardPoint[index].color = (curand(&state[index])>>16)%361;
}
int main()
{
BoardPoint boardHost[totalSize];
BoardPoint *boardDevice;
curandState *stateDevice;
// DebugFlag debugFlagHost[totalSize];
// DebugFlag *debugFlagDevice;
//
const int valueSizeDevice = totalSize*sizeof(BoardPoint);
// const int debugFlagSize = totalSize*sizeof(DebugFlag);
//
cudaMalloc( (void**)&boardDevice, valueSizeDevice );
cudaMalloc( (void**)&stateDevice, valueSizeDevice );
// cudaMalloc( (void**)&debugFlagDevice, debugFlagSize );
//
//
dim3 threadShape( boardSize, boardSize );
int numberOfBlock = 1;
srand((unsigned int)time(NULL));
randomInit<<<numberOfBlock, threadShape>>>(stateDevice, rand());
struct timeval start_tv;
gettimeofday(&start_tv,NULL);
randomTest<<<numberOfBlock, threadShape>>>(boardDevice, stateDevice);
// for (int i=0; i<19; i++){
// playBoard<<<numberOfBlock, threadShape>>>(boardDevice, globalFlag, i, i, 2);
// }
cudaDeviceSynchronize();
cudaMemcpy( boardHost, boardDevice, valueSizeDevice, cudaMemcpyDeviceToHost );
// cudaMemcpy( debugFlagHost, debugFlagDevice, debugFlagSize, cudaMemcpyDeviceToHost );
//
//
cudaFree( boardDevice );
// cudaFree( debugFlagDevice );
//
cudaDeviceSynchronize();
//
struct timeval end_tv;
gettimeofday(&end_tv,NULL);
for (int i=boardSize-1; i>=0; i--){
for (int j=0; j<boardSize; j++){
int index = i*boardSize + j;
printf("%d| ",boardHost[index].color);
}
printf("\n");
}
if(end_tv.tv_usec >= start_tv.tv_usec){
printf("time %lu:%lu\n",end_tv.tv_sec - start_tv.tv_sec, end_tv.tv_usec - start_tv.tv_usec);
}else{
printf("time %lu:%lu\n",end_tv.tv_sec - start_tv.tv_sec - 1, 1000000 - start_tv.tv_usec + end_tv.tv_usec);
}
return EXIT_SUCCESS;
} | #include <stdio.h>
#include <sys/time.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
const int boardSize = 21;
const int totalSize = boardSize * boardSize;
struct BoardPoint{
int color;
int groupID;
int libertyNumber;
bool isBlackLegal;
bool isWhiteLegal;
};
__global__
void randomInit(hiprandState *state, long randSeed){
int index = threadIdx.y*boardSize + threadIdx.x;
//curandState state;
// long seed = 123456;
hiprand_init(randSeed, index, 0, &state[index]);
// boardPoint[index].color = curand(&state);
}
__global__
void randomTest(BoardPoint *boardPoint, hiprandState *state){
int index = threadIdx.y*boardSize + threadIdx.x;
// curandState state;
// long seed = 123456;
// curand_init(seed, index, 0, &state);
boardPoint[index].color = (hiprand(&state[index])>>16)%361;
}
int main()
{
BoardPoint boardHost[totalSize];
BoardPoint *boardDevice;
hiprandState *stateDevice;
// DebugFlag debugFlagHost[totalSize];
// DebugFlag *debugFlagDevice;
//
const int valueSizeDevice = totalSize*sizeof(BoardPoint);
// const int debugFlagSize = totalSize*sizeof(DebugFlag);
//
hipMalloc( (void**)&boardDevice, valueSizeDevice );
hipMalloc( (void**)&stateDevice, valueSizeDevice );
// cudaMalloc( (void**)&debugFlagDevice, debugFlagSize );
//
//
dim3 threadShape( boardSize, boardSize );
int numberOfBlock = 1;
srand((unsigned int)time(NULL));
randomInit<<<numberOfBlock, threadShape>>>(stateDevice, rand());
struct timeval start_tv;
gettimeofday(&start_tv,NULL);
randomTest<<<numberOfBlock, threadShape>>>(boardDevice, stateDevice);
// for (int i=0; i<19; i++){
// playBoard<<<numberOfBlock, threadShape>>>(boardDevice, globalFlag, i, i, 2);
// }
hipDeviceSynchronize();
hipMemcpy( boardHost, boardDevice, valueSizeDevice, hipMemcpyDeviceToHost );
// cudaMemcpy( debugFlagHost, debugFlagDevice, debugFlagSize, cudaMemcpyDeviceToHost );
//
//
hipFree( boardDevice );
// cudaFree( debugFlagDevice );
//
hipDeviceSynchronize();
//
struct timeval end_tv;
gettimeofday(&end_tv,NULL);
for (int i=boardSize-1; i>=0; i--){
for (int j=0; j<boardSize; j++){
int index = i*boardSize + j;
printf("%d| ",boardHost[index].color);
}
printf("\n");
}
if(end_tv.tv_usec >= start_tv.tv_usec){
printf("time %lu:%lu\n",end_tv.tv_sec - start_tv.tv_sec, end_tv.tv_usec - start_tv.tv_usec);
}else{
printf("time %lu:%lu\n",end_tv.tv_sec - start_tv.tv_sec - 1, 1000000 - start_tv.tv_usec + end_tv.tv_usec);
}
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <sys/time.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
const int boardSize = 21;
const int totalSize = boardSize * boardSize;
struct BoardPoint{
int color;
int groupID;
int libertyNumber;
bool isBlackLegal;
bool isWhiteLegal;
};
__global__
void randomInit(hiprandState *state, long randSeed){
int index = threadIdx.y*boardSize + threadIdx.x;
//curandState state;
// long seed = 123456;
hiprand_init(randSeed, index, 0, &state[index]);
// boardPoint[index].color = curand(&state);
}
__global__
void randomTest(BoardPoint *boardPoint, hiprandState *state){
int index = threadIdx.y*boardSize + threadIdx.x;
// curandState state;
// long seed = 123456;
// curand_init(seed, index, 0, &state);
boardPoint[index].color = (hiprand(&state[index])>>16)%361;
}
int main()
{
BoardPoint boardHost[totalSize];
BoardPoint *boardDevice;
hiprandState *stateDevice;
// DebugFlag debugFlagHost[totalSize];
// DebugFlag *debugFlagDevice;
//
const int valueSizeDevice = totalSize*sizeof(BoardPoint);
// const int debugFlagSize = totalSize*sizeof(DebugFlag);
//
hipMalloc( (void**)&boardDevice, valueSizeDevice );
hipMalloc( (void**)&stateDevice, valueSizeDevice );
// cudaMalloc( (void**)&debugFlagDevice, debugFlagSize );
//
//
dim3 threadShape( boardSize, boardSize );
int numberOfBlock = 1;
srand((unsigned int)time(NULL));
randomInit<<<numberOfBlock, threadShape>>>(stateDevice, rand());
struct timeval start_tv;
gettimeofday(&start_tv,NULL);
randomTest<<<numberOfBlock, threadShape>>>(boardDevice, stateDevice);
// for (int i=0; i<19; i++){
// playBoard<<<numberOfBlock, threadShape>>>(boardDevice, globalFlag, i, i, 2);
// }
hipDeviceSynchronize();
hipMemcpy( boardHost, boardDevice, valueSizeDevice, hipMemcpyDeviceToHost );
// cudaMemcpy( debugFlagHost, debugFlagDevice, debugFlagSize, cudaMemcpyDeviceToHost );
//
//
hipFree( boardDevice );
// cudaFree( debugFlagDevice );
//
hipDeviceSynchronize();
//
struct timeval end_tv;
gettimeofday(&end_tv,NULL);
for (int i=boardSize-1; i>=0; i--){
for (int j=0; j<boardSize; j++){
int index = i*boardSize + j;
printf("%d| ",boardHost[index].color);
}
printf("\n");
}
if(end_tv.tv_usec >= start_tv.tv_usec){
printf("time %lu:%lu\n",end_tv.tv_sec - start_tv.tv_sec, end_tv.tv_usec - start_tv.tv_usec);
}else{
printf("time %lu:%lu\n",end_tv.tv_sec - start_tv.tv_sec - 1, 1000000 - start_tv.tv_usec + end_tv.tv_usec);
}
return EXIT_SUCCESS;
} | .text
.file "random_test.hip"
.globl _Z25__device_stub__randomInitP12hiprandStatel # -- Begin function _Z25__device_stub__randomInitP12hiprandStatel
.p2align 4, 0x90
.type _Z25__device_stub__randomInitP12hiprandStatel,@function
_Z25__device_stub__randomInitP12hiprandStatel: # @_Z25__device_stub__randomInitP12hiprandStatel
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10randomInitP12hiprandStatel, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__randomInitP12hiprandStatel, .Lfunc_end0-_Z25__device_stub__randomInitP12hiprandStatel
.cfi_endproc
# -- End function
.globl _Z25__device_stub__randomTestP10BoardPointP12hiprandState # -- Begin function _Z25__device_stub__randomTestP10BoardPointP12hiprandState
.p2align 4, 0x90
.type _Z25__device_stub__randomTestP10BoardPointP12hiprandState,@function
_Z25__device_stub__randomTestP10BoardPointP12hiprandState: # @_Z25__device_stub__randomTestP10BoardPointP12hiprandState
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10randomTestP10BoardPointP12hiprandState, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z25__device_stub__randomTestP10BoardPointP12hiprandState, .Lfunc_end1-_Z25__device_stub__randomTestP10BoardPointP12hiprandState
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $7152, %rsp # imm = 0x1BF0
.cfi_def_cfa_offset 7184
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $90194313237, %rbx # imm = 0x1500000015
movabsq $4294967297, %r14 # imm = 0x100000001
leaq 16(%rsp), %rdi
movl $7056, %esi # imm = 0x1B90
callq hipMalloc
leaq 80(%rsp), %rdi
movl $7056, %esi # imm = 0x1B90
callq hipMalloc
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 80(%rsp), %r15
callq rand
cltq
movq %r15, 48(%rsp)
movq %rax, 40(%rsp)
leaq 48(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
movq %rsp, %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10randomInitP12hiprandStatel, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rax
movq 80(%rsp), %rcx
movq %rax, 40(%rsp)
movq %rcx, 32(%rsp)
leaq 40(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rdi
leaq 48(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10randomTestP10BoardPointP12hiprandState, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $7056, %edx # imm = 0x1B90
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
callq hipDeviceSynchronize
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movl $20, %ebx
leaq 6816(%rsp), %r14
.p2align 4, 0x90
.LBB2_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r15), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
addq $16, %r15
cmpq $336, %r15 # imm = 0x150
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=1
movl $10, %edi
callq putchar@PLT
addq $-336, %r14 # imm = 0xFEB0
subq $1, %rbx
jae .LBB2_5
# %bb.8:
movq 8(%rsp), %rax
movq 64(%rsp), %rsi
movq 72(%rsp), %rcx
leaq 1000000(%rax), %rdx
movq %rsi, %rdi
negq %rdi
cmpq %rcx, %rax
notq %rsi
cmovgeq %rax, %rdx
cmovgeq %rdi, %rsi
addq (%rsp), %rsi
subq %rcx, %rdx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $7152, %rsp # imm = 0x1BF0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10randomInitP12hiprandStatel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10randomTestP10BoardPointP12hiprandState, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10randomInitP12hiprandStatel,@object # @_Z10randomInitP12hiprandStatel
.section .rodata,"a",@progbits
.globl _Z10randomInitP12hiprandStatel
.p2align 3, 0x0
_Z10randomInitP12hiprandStatel:
.quad _Z25__device_stub__randomInitP12hiprandStatel
.size _Z10randomInitP12hiprandStatel, 8
.type _Z10randomTestP10BoardPointP12hiprandState,@object # @_Z10randomTestP10BoardPointP12hiprandState
.globl _Z10randomTestP10BoardPointP12hiprandState
.p2align 3, 0x0
_Z10randomTestP10BoardPointP12hiprandState:
.quad _Z25__device_stub__randomTestP10BoardPointP12hiprandState
.size _Z10randomTestP10BoardPointP12hiprandState, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d| "
.size .L.str, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "time %lu:%lu\n"
.size .L.str.2, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10randomInitP12hiprandStatel"
.size .L__unnamed_1, 31
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10randomTestP10BoardPointP12hiprandState"
.size .L__unnamed_2, 43
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__randomInitP12hiprandStatel
.addrsig_sym _Z25__device_stub__randomTestP10BoardPointP12hiprandState
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10randomInitP12hiprandStatel
.addrsig_sym _Z10randomTestP10BoardPointP12hiprandState
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003d616_00000000-6_random_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z10randomInitP17curandStateXORWOWlP17curandStateXORWOWl
.type _Z49__device_stub__Z10randomInitP17curandStateXORWOWlP17curandStateXORWOWl, @function
_Z49__device_stub__Z10randomInitP17curandStateXORWOWlP17curandStateXORWOWl:
.LFB2296:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10randomInitP17curandStateXORWOWl(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z49__device_stub__Z10randomInitP17curandStateXORWOWlP17curandStateXORWOWl, .-_Z49__device_stub__Z10randomInitP17curandStateXORWOWlP17curandStateXORWOWl
.globl _Z10randomInitP17curandStateXORWOWl
.type _Z10randomInitP17curandStateXORWOWl, @function
_Z10randomInitP17curandStateXORWOWl:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z10randomInitP17curandStateXORWOWlP17curandStateXORWOWl
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z10randomInitP17curandStateXORWOWl, .-_Z10randomInitP17curandStateXORWOWl
.globl _Z61__device_stub__Z10randomTestP10BoardPointP17curandStateXORWOWP10BoardPointP17curandStateXORWOW
.type _Z61__device_stub__Z10randomTestP10BoardPointP17curandStateXORWOWP10BoardPointP17curandStateXORWOW, @function
_Z61__device_stub__Z10randomTestP10BoardPointP17curandStateXORWOWP10BoardPointP17curandStateXORWOW:
.LFB2298:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10randomTestP10BoardPointP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2298:
.size _Z61__device_stub__Z10randomTestP10BoardPointP17curandStateXORWOWP10BoardPointP17curandStateXORWOW, .-_Z61__device_stub__Z10randomTestP10BoardPointP17curandStateXORWOWP10BoardPointP17curandStateXORWOW
.globl _Z10randomTestP10BoardPointP17curandStateXORWOW
.type _Z10randomTestP10BoardPointP17curandStateXORWOW, @function
_Z10randomTestP10BoardPointP17curandStateXORWOW:
.LFB2299:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z61__device_stub__Z10randomTestP10BoardPointP17curandStateXORWOWP10BoardPointP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _Z10randomTestP10BoardPointP17curandStateXORWOW, .-_Z10randomTestP10BoardPointP17curandStateXORWOW
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d| "
.LC1:
.string "\n"
.LC2:
.string "time %lu:%lu\n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $4096, %rsp
.cfi_def_cfa_offset 4144
orq $0, (%rsp)
subq $3040, %rsp
.cfi_def_cfa_offset 7184
movq %fs:40, %rax
movq %rax, 7128(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $7056, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $7056, %esi
call cudaMalloc@PLT
movl $21, 20(%rsp)
movl $21, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L20:
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L21:
call cudaDeviceSynchronize@PLT
leaq 64(%rsp), %r13
movl $2, %ecx
movl $7056, %edx
movq (%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
call cudaDeviceSynchronize@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 7120(%rsp), %rbp
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r14
.L22:
leaq -336(%rbp), %rbx
.L23:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rbx
cmpq %rbp, %rbx
jne .L23
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subq $336, %rbp
cmpq %r13, %rbp
jne .L22
movq 56(%rsp), %rax
movq 40(%rsp), %rdx
cmpq %rdx, %rax
jl .L25
subq %rdx, %rax
movq %rax, %rcx
movq 48(%rsp), %rdx
subq 32(%rsp), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L26:
movq 7128(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $7136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call rand@PLT
movslq %eax, %rsi
movq 8(%rsp), %rdi
call _Z49__device_stub__Z10randomInitP17curandStateXORWOWlP17curandStateXORWOWl
jmp .L20
.L31:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z61__device_stub__Z10randomTestP10BoardPointP17curandStateXORWOWP10BoardPointP17curandStateXORWOW
jmp .L21
.L25:
subq %rdx, %rax
leaq 1000000(%rax), %rcx
movq 48(%rsp), %rdx
subq 32(%rsp), %rdx
subq $1, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "_Z10randomTestP10BoardPointP17curandStateXORWOW"
.align 8
.LC4:
.string "_Z10randomInitP17curandStateXORWOWl"
.section .rodata.str1.1
.LC5:
.string "precalc_xorwow_matrix"
.LC6:
.string "precalc_xorwow_offset_matrix"
.LC7:
.string "mrg32k3aM1"
.LC8:
.string "mrg32k3aM2"
.LC9:
.string "mrg32k3aM1SubSeq"
.LC10:
.string "mrg32k3aM2SubSeq"
.LC11:
.string "mrg32k3aM1Seq"
.LC12:
.string "mrg32k3aM2Seq"
.LC13:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2301:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10randomTestP10BoardPointP17curandStateXORWOW(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10randomInitP17curandStateXORWOWl(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2301:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "random_test.hip"
.globl _Z25__device_stub__randomInitP12hiprandStatel # -- Begin function _Z25__device_stub__randomInitP12hiprandStatel
.p2align 4, 0x90
.type _Z25__device_stub__randomInitP12hiprandStatel,@function
_Z25__device_stub__randomInitP12hiprandStatel: # @_Z25__device_stub__randomInitP12hiprandStatel
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10randomInitP12hiprandStatel, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__randomInitP12hiprandStatel, .Lfunc_end0-_Z25__device_stub__randomInitP12hiprandStatel
.cfi_endproc
# -- End function
.globl _Z25__device_stub__randomTestP10BoardPointP12hiprandState # -- Begin function _Z25__device_stub__randomTestP10BoardPointP12hiprandState
.p2align 4, 0x90
.type _Z25__device_stub__randomTestP10BoardPointP12hiprandState,@function
_Z25__device_stub__randomTestP10BoardPointP12hiprandState: # @_Z25__device_stub__randomTestP10BoardPointP12hiprandState
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10randomTestP10BoardPointP12hiprandState, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z25__device_stub__randomTestP10BoardPointP12hiprandState, .Lfunc_end1-_Z25__device_stub__randomTestP10BoardPointP12hiprandState
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $7152, %rsp # imm = 0x1BF0
.cfi_def_cfa_offset 7184
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $90194313237, %rbx # imm = 0x1500000015
movabsq $4294967297, %r14 # imm = 0x100000001
leaq 16(%rsp), %rdi
movl $7056, %esi # imm = 0x1B90
callq hipMalloc
leaq 80(%rsp), %rdi
movl $7056, %esi # imm = 0x1B90
callq hipMalloc
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 80(%rsp), %r15
callq rand
cltq
movq %r15, 48(%rsp)
movq %rax, 40(%rsp)
leaq 48(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
movq %rsp, %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10randomInitP12hiprandStatel, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rax
movq 80(%rsp), %rcx
movq %rax, 40(%rsp)
movq %rcx, 32(%rsp)
leaq 40(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rdi
leaq 48(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10randomTestP10BoardPointP12hiprandState, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $7056, %edx # imm = 0x1B90
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
callq hipDeviceSynchronize
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movl $20, %ebx
leaq 6816(%rsp), %r14
.p2align 4, 0x90
.LBB2_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r15), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
addq $16, %r15
cmpq $336, %r15 # imm = 0x150
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=1
movl $10, %edi
callq putchar@PLT
addq $-336, %r14 # imm = 0xFEB0
subq $1, %rbx
jae .LBB2_5
# %bb.8:
movq 8(%rsp), %rax
movq 64(%rsp), %rsi
movq 72(%rsp), %rcx
leaq 1000000(%rax), %rdx
movq %rsi, %rdi
negq %rdi
cmpq %rcx, %rax
notq %rsi
cmovgeq %rax, %rdx
cmovgeq %rdi, %rsi
addq (%rsp), %rsi
subq %rcx, %rdx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $7152, %rsp # imm = 0x1BF0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10randomInitP12hiprandStatel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10randomTestP10BoardPointP12hiprandState, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10randomInitP12hiprandStatel,@object # @_Z10randomInitP12hiprandStatel
.section .rodata,"a",@progbits
.globl _Z10randomInitP12hiprandStatel
.p2align 3, 0x0
_Z10randomInitP12hiprandStatel:
.quad _Z25__device_stub__randomInitP12hiprandStatel
.size _Z10randomInitP12hiprandStatel, 8
.type _Z10randomTestP10BoardPointP12hiprandState,@object # @_Z10randomTestP10BoardPointP12hiprandState
.globl _Z10randomTestP10BoardPointP12hiprandState
.p2align 3, 0x0
_Z10randomTestP10BoardPointP12hiprandState:
.quad _Z25__device_stub__randomTestP10BoardPointP12hiprandState
.size _Z10randomTestP10BoardPointP12hiprandState, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d| "
.size .L.str, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "time %lu:%lu\n"
.size .L.str.2, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10randomInitP12hiprandStatel"
.size .L__unnamed_1, 31
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10randomTestP10BoardPointP12hiprandState"
.size .L__unnamed_2, 43
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__randomInitP12hiprandStatel
.addrsig_sym _Z25__device_stub__randomTestP10BoardPointP12hiprandState
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10randomInitP12hiprandStatel
.addrsig_sym _Z10randomTestP10BoardPointP12hiprandState
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cmath>
__global__ void my_copysign(double* v)
{
int i = threadIdx.x;
*v = std::pow(-1, i) * (*v);
} | code for sm_80
Function : _Z11my_copysignPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ BSSY B0, 0xd0 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0030*/ I2F.F64 R2, R8 ; /* 0x0000000800027312 */
/* 0x001e240000201c00 */
/*0040*/ LOP3.LUT R0, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003007812 */
/* 0x001fc800078ec0ff */
/*0050*/ LEA.HI R5, R0, 0xfffffc0c, RZ, 0xc ; /* 0xfffffc0c00057811 */
/* 0x000fc800078f60ff */
/*0060*/ SHF.L.U32 R0, R2.reuse, R5.reuse, RZ ; /* 0x0000000502007219 */
/* 0x0c0fe400000006ff */
/*0070*/ SHF.L.U64.HI R5, R2, R5, R3 ; /* 0x0000000502057219 */
/* 0x000fe40000010203 */
/*0080*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05070 */
/*0090*/ MOV R0, 0xc0 ; /* 0x000000c000007802 */
/* 0x000fe40000000f00 */
/*00a0*/ ISETP.NE.AND.EX P0, PT, R5, -0x80000000, PT, P0 ; /* 0x800000000500780c */
/* 0x000fd00003f05300 */
/*00b0*/ CALL.REL.NOINC 0x2f0 ; /* 0x0000023000007944 */
/* 0x000fea0003c00000 */
/*00c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*00d0*/ FRND.F64.TRUNC R4, R2 ; /* 0x0000000200047313 */
/* 0x000e62000030d800 */
/*00e0*/ DADD R6, R2, -1 ; /* 0xbff0000002067429 */
/* 0x000ea20000000000 */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ BSSY B0, 0x260 ; /* 0x0000015000007945 */
/* 0x000ff00003800000 */
/*0110*/ LOP3.LUT R6, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007067812 */
/* 0x004fc800078ec0ff */
/*0120*/ ISETP.NE.AND P2, PT, R6, 0x7ff00000, PT ; /* 0x7ff000000600780c */
/* 0x000fe20003f45270 */
/*0130*/ DSETP.NEU.AND P1, PT, R4, R2, PT ; /* 0x000000020400722a */
/* 0x0022a40003f2d000 */
/*0140*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x002fe400078e000f */
/*0150*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fc600078e000e */
/*0160*/ @!P0 LOP3.LUT R7, R5, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000005078812 */
/* 0x000fca00078e3cff */
/*0170*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff058224 */
/* 0x000fe400078e0007 */
/*0180*/ @P1 IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff041424 */
/* 0x004fe400078e00ff */
/*0190*/ @P1 IMAD.MOV.U32 R5, RZ, RZ, -0x80000 ; /* 0xfff80000ff051424 */
/* 0x000fe200078e00ff */
/*01a0*/ @P2 BRA 0x250 ; /* 0x000000a000002947 */
/* 0x000fea0003800000 */
/*01b0*/ DSETP.GTU.AND P0, PT, |R2|, +INF , PT ; /* 0x7ff000000200742a */
/* 0x000e5c0003f0c200 */
/*01c0*/ @P0 BRA 0x240 ; /* 0x0000007000000947 */
/* 0x002fea0003800000 */
/*01d0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f05270 */
/*01e0*/ LOP3.LUT R2, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03027812 */
/* 0x000fc800078ec0ff */
/*01f0*/ ISETP.EQ.AND P0, PT, R2, 0x7ff00000, !P0 ; /* 0x7ff000000200780c */
/* 0x000fda0004702270 */
/*0200*/ @!P0 BRA 0x250 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x000fe400078e00ff */
/*0220*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3ff00000 ; /* 0x3ff00000ff057424 */
/* 0x000fe200078e00ff */
/*0230*/ BRA 0x250 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0240*/ DADD R4, R2, -1 ; /* 0xbff0000002047429 */
/* 0x00028c0000000000 */
/*0250*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0260*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x002fe400078e00ff */
/*0270*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0280*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ee2000c1e1b00 */
/*0290*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc80003f05270 */
/*02a0*/ FSEL R4, R4, RZ, P0 ; /* 0x000000ff04047208 */
/* 0x004fe40000000000 */
/*02b0*/ FSEL R5, R5, 1.875, P0 ; /* 0x3ff0000005057808 */
/* 0x000fcc0000000000 */
/*02c0*/ DMUL R6, R6, R4 ; /* 0x0000000406067228 */
/* 0x008e4e0000000000 */
/*02d0*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x002fe2000c101b04 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ MUFU.RCP64H R11, 2 ; /* 0x40000000000b7908 */
/* 0x000e220000001800 */
/*0300*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x000fe400078e00ff */
/*0310*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3ff00000 ; /* 0x3ff00000ff057424 */
/* 0x000fe400078e00ff */
/*0320*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*0330*/ IMAD.MOV.U32 R6, RZ, RZ, 0x7d2cafe2 ; /* 0x7d2cafe2ff067424 */
/* 0x000fe400078e00ff */
/*0340*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3eb0f5ff ; /* 0x3eb0f5ffff077424 */
/* 0x000fc400078e00ff */
/*0350*/ IMAD.SHL.U32 R9, R3, 0x2, RZ ; /* 0x0000000203097824 */
/* 0x000fe200078e00ff */
/*0360*/ DFMA R4, R10, -2, R4 ; /* 0xc00000000a04782b */
/* 0x001e080000000004 */
/*0370*/ ISETP.GT.U32.AND P1, PT, R9, -0x2000001, PT ; /* 0xfdffffff0900780c */
/* 0x000fe40003f24070 */
/*0380*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x001e0c0000000004 */
/*0390*/ DFMA R10, R10, R4, R10 ; /* 0x000000040a0a722b */
/* 0x001e0c000000000a */
/*03a0*/ DMUL R4, RZ, R10 ; /* 0x0000000aff047228 */
/* 0x001e0c0000000000 */
/*03b0*/ DFMA R4, RZ, R10, R4 ; /* 0x0000000aff04722b */
/* 0x001e0c0000000004 */
/*03c0*/ DMUL R12, R4, R4 ; /* 0x00000004040c7228 */
/* 0x001e080000000000 */
/*03d0*/ DADD R14, RZ, -R4 ; /* 0x00000000ff0e7229 */
/* 0x000e480000000804 */
/*03e0*/ DFMA R6, R12, R6, c[0x2][0x0] ; /* 0x008000000c06762b */
/* 0x001e080000000006 */
/*03f0*/ DADD R16, R14, R14 ; /* 0x000000000e107229 */
/* 0x002fc8000000000e */
/*0400*/ DFMA R6, R12, R6, c[0x2][0x8] ; /* 0x008002000c06762b */
/* 0x001e080000000006 */
/*0410*/ DMUL R14, R4, R4 ; /* 0x00000004040e7228 */
/* 0x000fc80000000000 */
/*0420*/ DFMA R6, R12, R6, c[0x2][0x10] ; /* 0x008004000c06762b */
/* 0x001e080000000006 */
/*0430*/ DFMA R20, RZ, -R4, R16 ; /* 0x80000004ff14722b */
/* 0x000e480000000010 */
/*0440*/ DFMA R6, R12, R6, c[0x2][0x18] ; /* 0x008006000c06762b */
/* 0x001e080000000006 */
/*0450*/ DMUL R10, R10, R20 ; /* 0x000000140a0a7228 */
/* 0x002fc80000000000 */
/*0460*/ DFMA R6, R12, R6, c[0x2][0x20] ; /* 0x008008000c06762b */
/* 0x001e080000000006 */
/*0470*/ DFMA R16, R4, R4, -R14 ; /* 0x000000040410722b */
/* 0x000fc8000000080e */
/*0480*/ DFMA R18, R12, R6, c[0x2][0x28] ; /* 0x00800a000c12762b */
/* 0x001e0c0000000006 */
/*0490*/ DFMA R6, R12, R18, c[0x2][0x30] ; /* 0x00800c000c06762b */
/* 0x001e0c0000000012 */
/*04a0*/ DADD R22, -R6, c[0x2][0x30] ; /* 0x00800c0006167629 */
/* 0x001e0c0000000100 */
/*04b0*/ DFMA R22, R12, R18, R22 ; /* 0x000000120c16722b */
/* 0x001e080000000016 */
/*04c0*/ DMUL R12, R4, R14 ; /* 0x0000000e040c7228 */
/* 0x000e480000000000 */
/*04d0*/ DADD R18, RZ, R22 ; /* 0x00000000ff127229 */
/* 0x001e080000000016 */
/*04e0*/ DFMA R20, R4, R14, -R12 ; /* 0x0000000e0414722b */
/* 0x002e48000000080c */
/*04f0*/ DADD R18, R18, c[0x2][0x38] ; /* 0x00800e0012127629 */
/* 0x001e080000000000 */
/*0500*/ DFMA R22, R10, R14, R20 ; /* 0x0000000e0a16722b */
/* 0x0023e40000000014 */
/*0510*/ IADD3 R21, R11, 0x100000, RZ ; /* 0x001000000b157810 */
/* 0x002fe20007ffe0ff */
/*0520*/ IMAD.MOV.U32 R20, RZ, RZ, R10 ; /* 0x000000ffff147224 */
/* 0x000fe200078e000a */
/*0530*/ DADD R14, R6, R18 ; /* 0x00000000060e7229 */
/* 0x001e0a0000000012 */
/*0540*/ DFMA R20, R4, R20, R16 ; /* 0x000000140414722b */
/* 0x000e480000000010 */
/*0550*/ DMUL R16, R14, R12 ; /* 0x0000000c0e107228 */
/* 0x001e080000000000 */
/*0560*/ DFMA R20, R4, R20, R22 ; /* 0x000000140414722b */
/* 0x002fc80000000016 */
/*0570*/ DADD R6, R6, -R14 ; /* 0x0000000006067229 */
/* 0x000e48000000080e */
/*0580*/ DFMA R22, R14, R12, -R16 ; /* 0x0000000c0e16722b */
/* 0x001e080000000810 */
/*0590*/ DADD R6, R18, R6 ; /* 0x0000000012067229 */
/* 0x0023e40000000006 */
/*05a0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff127424 */
/* 0x002fe400078e00ff */
/*05b0*/ DFMA R20, R14, R20, R22 ; /* 0x000000140e14722b */
/* 0x001e220000000016 */
/*05c0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff137424 */
/* 0x000fca00078e00ff */
/*05d0*/ DFMA R20, R6, R12, R20 ; /* 0x0000000c0614722b */
/* 0x001e0c0000000014 */
/*05e0*/ DADD R12, R16, R20 ; /* 0x00000000100c7229 */
/* 0x001e0c0000000014 */
/*05f0*/ DADD R6, R4, R12 ; /* 0x0000000004067229 */
/* 0x001e08000000000c */
/*0600*/ DADD R16, R16, -R12 ; /* 0x0000000010107229 */
/* 0x000e48000000080c */
/*0610*/ DADD R4, R4, -R6 ; /* 0x0000000004047229 */
/* 0x001e080000000806 */
/*0620*/ DADD R16, R20, R16 ; /* 0x0000000014107229 */
/* 0x002fc80000000010 */
/*0630*/ DADD R4, R12, R4 ; /* 0x000000000c047229 */
/* 0x001e0c0000000004 */
/*0640*/ DADD R4, R16, R4 ; /* 0x0000000010047229 */
/* 0x001e0c0000000004 */
/*0650*/ DADD R10, R10, R4 ; /* 0x000000000a0a7229 */
/* 0x001e0c0000000004 */
/*0660*/ DADD R12, R6, R10 ; /* 0x00000000060c7229 */
/* 0x001e0c000000000a */
/*0670*/ DFMA R4, RZ, c[0x2][0x40], R12 ; /* 0x00801000ff047a2b */
/* 0x001e08000000000c */
/*0680*/ DADD R6, R6, -R12 ; /* 0x0000000006067229 */
/* 0x000e48000000080c */
/*0690*/ DFMA R14, -RZ, c[0x2][0x40], R4 ; /* 0x00801000ff0e7a2b */
/* 0x001e080000000104 */
/*06a0*/ DADD R6, R10, R6 ; /* 0x000000000a067229 */
/* 0x002fc80000000006 */
/*06b0*/ DADD R14, -R12, R14 ; /* 0x000000000c0e7229 */
/* 0x001e0c000000010e */
/*06c0*/ DADD R6, R6, -R14 ; /* 0x0000000006067229 */
/* 0x001064000000080e */
/*06d0*/ LOP3.LUT R15, R3, 0xff0fffff, RZ, 0xc0, !PT ; /* 0xff0fffff030f7812 */
/* 0x001fe200078ec0ff */
/*06e0*/ IMAD.MOV.U32 R14, RZ, RZ, R2 ; /* 0x000000ffff0e7224 */
/* 0x000fc600078e0002 */
/*06f0*/ DFMA R6, RZ, c[0x2][0x48], R6 ; /* 0x00801200ff067a2b */
/* 0x002e220000000006 */
/*0700*/ SEL R15, R15, R3, P1 ; /* 0x000000030f0f7207 */
/* 0x000fca0000800000 */
/*0710*/ DADD R10, R4, R6 ; /* 0x00000000040a7229 */
/* 0x001e0c0000000006 */
/*0720*/ DADD R12, R4, -R10 ; /* 0x00000000040c7229 */
/* 0x001e08000000080a */
/*0730*/ DMUL R4, R10, R14 ; /* 0x0000000e0a047228 */
/* 0x000e480000000000 */
/*0740*/ DADD R6, R6, R12 ; /* 0x0000000006067229 */
/* 0x0011e4000000000c */
/*0750*/ IMAD.MOV.U32 R12, RZ, RZ, 0x652b82fe ; /* 0x652b82feff0c7424 */
/* 0x001fe400078e00ff */
/*0760*/ DFMA R10, R10, R14, -R4 ; /* 0x0000000e0a0a722b */
/* 0x002e220000000804 */
/*0770*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff0d7424 */
/* 0x000fca00078e00ff */
/*0780*/ DFMA R6, R6, R14, R10 ; /* 0x0000000e0606722b */
/* 0x001e0c000000000a */
/*0790*/ DADD R10, R4, R6 ; /* 0x00000000040a7229 */
/* 0x001e0c0000000006 */
/*07a0*/ DFMA R12, R10, R12, 6.75539944105574400000e+15 ; /* 0x433800000a0c742b */
/* 0x001e08000000000c */
/*07b0*/ FSETP.GEU.AND P1, PT, |R11|, 4.1917929649353027344, PT ; /* 0x4086232b0b00780b */
/* 0x000fe40003f2e200 */
/*07c0*/ DADD R14, R12, -6.75539944105574400000e+15 ; /* 0xc33800000c0e7429 */
/* 0x001e0c0000000000 */
/*07d0*/ DFMA R16, R14, c[0x2][0x50], R10 ; /* 0x008014000e107a2b */
/* 0x001e0c000000000a */
/*07e0*/ DFMA R14, R14, c[0x2][0x58], R16 ; /* 0x008016000e0e7a2b */
/* 0x001e0c0000000010 */
/*07f0*/ DFMA R16, R14, R18, c[0x2][0x60] ; /* 0x008018000e10762b */
/* 0x001e0c0000000012 */
/*0800*/ DFMA R16, R14, R16, c[0x2][0x68] ; /* 0x00801a000e10762b */
/* 0x001e0c0000000010 */
/*0810*/ DFMA R16, R14, R16, c[0x2][0x70] ; /* 0x00801c000e10762b */
/* 0x001e0c0000000010 */
/*0820*/ DFMA R16, R14, R16, c[0x2][0x78] ; /* 0x00801e000e10762b */
/* 0x001e0c0000000010 */
/*0830*/ DFMA R16, R14, R16, c[0x2][0x80] ; /* 0x008020000e10762b */
/* 0x001e0c0000000010 */
/*0840*/ DFMA R16, R14, R16, c[0x2][0x88] ; /* 0x008022000e10762b */
/* 0x001e0c0000000010 */
/*0850*/ DFMA R16, R14, R16, c[0x2][0x90] ; /* 0x008024000e10762b */
/* 0x001e0c0000000010 */
/*0860*/ DFMA R16, R14, R16, c[0x2][0x98] ; /* 0x008026000e10762b */
/* 0x001e0c0000000010 */
/*0870*/ DFMA R16, R14, R16, c[0x2][0xa0] ; /* 0x008028000e10762b */
/* 0x001e0c0000000010 */
/*0880*/ DFMA R16, R14, R16, 1 ; /* 0x3ff000000e10742b */
/* 0x001e0c0000000010 */
/*0890*/ DFMA R16, R14, R16, 1 ; /* 0x3ff000000e10742b */
/* 0x001e140000000010 */
/*08a0*/ IMAD R15, R12, 0x100000, R17 ; /* 0x001000000c0f7824 */
/* 0x001fe400078e0211 */
/*08b0*/ IMAD.MOV.U32 R14, RZ, RZ, R16 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0010 */
/*08c0*/ @!P1 BRA 0x990 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*08d0*/ FSETP.GEU.AND P2, PT, |R11|, 4.2275390625, PT ; /* 0x408748000b00780b */
/* 0x000fe20003f4e200 */
/*08e0*/ DADD R14, R10, +INF ; /* 0x7ff000000a0e7429 */
/* 0x000fc80000000000 */
/*08f0*/ DSETP.GEU.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00722a */
/* 0x000e0c0003f2e000 */
/*0900*/ FSEL R14, R14, RZ, P1 ; /* 0x000000ff0e0e7208 */
/* 0x001fe40000800000 */
/*0910*/ @!P2 LEA.HI R9, R12, R12, RZ, 0x1 ; /* 0x0000000c0c09a211 */
/* 0x000fe400078f08ff */
/*0920*/ FSEL R15, R15, RZ, P1 ; /* 0x000000ff0f0f7208 */
/* 0x000fe40000800000 */
/*0930*/ @!P2 SHF.R.S32.HI R9, RZ, 0x1, R9 ; /* 0x00000001ff09a819 */
/* 0x000fca0000011409 */
/*0940*/ @!P2 IMAD.IADD R12, R12, 0x1, -R9 ; /* 0x000000010c0ca824 */
/* 0x000fe400078e0a09 */
/*0950*/ @!P2 IMAD R17, R9, 0x100000, R17 ; /* 0x001000000911a824 */
/* 0x000fc600078e0211 */
/*0960*/ @!P2 LEA R13, R12, 0x3ff00000, 0x14 ; /* 0x3ff000000c0da811 */
/* 0x000fe200078ea0ff */
/*0970*/ @!P2 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0ca224 */
/* 0x000fcc00078e00ff */
/*0980*/ @!P2 DMUL R14, R16, R12 ; /* 0x0000000c100ea228 */
/* 0x0000540000000000 */
/*0990*/ LOP3.LUT R9, R15, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0f097812 */
/* 0x002fe200078ec0ff */
/*09a0*/ DADD R4, R4, -R10 ; /* 0x0000000004047229 */
/* 0x000e46000000080a */
/*09b0*/ ISETP.NE.AND P1, PT, R9, 0x7ff00000, PT ; /* 0x7ff000000900780c */
/* 0x000fc60003f25270 */
/*09c0*/ DADD R4, R6, R4 ; /* 0x0000000006047229 */
/* 0x002e620000000004 */
/*09d0*/ ISETP.EQ.AND P1, PT, R14, RZ, !P1 ; /* 0x000000ff0e00720c */
/* 0x000fda0004f22270 */
/*09e0*/ @!P1 DFMA R14, R4, R14, R14 ; /* 0x0000000e040e922b */
/* 0x0022a4000000000e */
/*09f0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x002fe400078e0000 */
/*0a00*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0a10*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff5e004007950 */
/* 0x004fea0003c3ffff */
/*0a20*/ BRA 0xa20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cmath>
__global__ void my_copysign(double* v)
{
int i = threadIdx.x;
*v = std::pow(-1, i) * (*v);
} | .file "tmpxft_0013d6ca_00000000-6_pow.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z11my_copysignPdPd
.type _Z31__device_stub__Z11my_copysignPdPd, @function
_Z31__device_stub__Z11my_copysignPdPd:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11my_copysignPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z11my_copysignPdPd, .-_Z31__device_stub__Z11my_copysignPdPd
.globl _Z11my_copysignPd
.type _Z11my_copysignPd, @function
_Z11my_copysignPd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z11my_copysignPdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11my_copysignPd, .-_Z11my_copysignPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11my_copysignPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11my_copysignPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cmath>
__global__ void my_copysign(double* v)
{
int i = threadIdx.x;
*v = std::pow(-1, i) * (*v);
} | #include <hip/hip_runtime.h>
#include <cmath>
__global__ void my_copysign(double* v)
{
int i = threadIdx.x;
*v = std::pow(-1, i) * (*v);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cmath>
__global__ void my_copysign(double* v)
{
int i = threadIdx.x;
*v = std::pow(-1, i) * (*v);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11my_copysignPd
.globl _Z11my_copysignPd
.p2align 8
.type _Z11my_copysignPd,@function
_Z11my_copysignPd:
v_cvt_f64_i32_e32 v[1:2], v0
s_mov_b32 s3, 0x3ff71547
s_mov_b32 s2, 0x652b82fe
s_mov_b32 s5, 0x3e5ade15
s_mov_b32 s4, 0x6a5dcb37
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[3:4], v[1:2], 0
v_fma_f64 v[5:6], v[1:2], 0, -v[3:4]
v_cmp_class_f64_e64 vcc_lo, v[3:4], 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[5:6], v[1:2], 0, v[5:6]
v_mul_f64 v[1:2], v[1:2], 0.5
v_add_f64 v[7:8], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v10, v8, v4 :: v_dual_cndmask_b32 v9, v7, v3
v_add_f64 v[3:4], v[7:8], -v[3:4]
v_mul_f64 v[11:12], v[9:10], s[2:3]
s_mov_b32 s3, 0xbfe62e42
s_mov_b32 s2, 0xfefa39ef
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[9:10]|
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[3:4], v[5:6], -v[3:4]
v_rndne_f64_e32 v[11:12], v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v4, 0, v4 :: v_dual_cndmask_b32 v3, 0, v3
v_fma_f64 v[13:14], v[11:12], s[2:3], v[9:10]
s_mov_b32 s3, 0xbc7abc9e
s_mov_b32 s2, 0x3b39803f
v_cvt_i32_f64_e32 v17, v[11:12]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[13:14], v[11:12], s[2:3], v[13:14]
s_mov_b32 s3, 0x3e928af3
s_mov_b32 s2, 0xfca7ab0c
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], s[4:5], s[2:3]
s_mov_b32 s3, 0x3ec71dee
s_mov_b32 s2, 0x623fde64
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
s_mov_b32 s3, 0x3efa0199
s_mov_b32 s2, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
s_mov_b32 s3, 0x3f2a01a0
s_mov_b32 s2, 0x14761f6e
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
s_mov_b32 s3, 0x3f56c16c
s_mov_b32 s2, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
s_mov_b32 s3, 0x3f811111
s_mov_b32 s2, 0x11122322
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
s_mov_b32 s3, 0x3fa55555
s_mov_b32 s2, 0x555502a1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
s_mov_b32 s3, 0x3fc55555
s_mov_b32 s2, 0x55555511
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
s_mov_b32 s3, 0x3fe00000
s_mov_b32 s2, 11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
v_cmp_nlt_f64_e64 s2, 0x40900000, v[9:10]
v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[15:16], v[13:14], v[15:16], 1.0
s_and_b32 vcc_lo, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], v[13:14], v[15:16], 1.0
v_ldexp_f64 v[7:8], v[11:12], v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v5, 0x7ff00000, v8, s2
v_cndmask_b32_e64 v6, 0, v5, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, 0, v7, vcc_lo
v_trunc_f64_e32 v[7:8], v[1:2]
s_load_b64 s[2:3], s[0:1], 0x0
v_cmp_eq_u32_e64 s0, 0, v0
v_fma_f64 v[3:4], v[5:6], v[3:4], v[5:6]
v_cmp_class_f64_e64 vcc_lo, v[5:6], 0x204
v_mov_b32_e32 v9, 0x3ff00000
s_waitcnt lgkmcnt(0)
s_load_b64 s[4:5], s[2:3], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v0, v3, v5 :: v_dual_cndmask_b32 v3, v4, v6
v_cmp_neq_f64_e32 vcc_lo, v[7:8], v[1:2]
v_cndmask_b32_e64 v9, 0xbff00000, v9, s0
v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v1, 0x3ff00000, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_bfi_b32 v1, 0x7fffffff, v3, v1
s_waitcnt lgkmcnt(0)
v_mul_f64 v[0:1], v[0:1], s[4:5]
global_store_b64 v2, v[0:1], s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11my_copysignPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11my_copysignPd, .Lfunc_end0-_Z11my_copysignPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11my_copysignPd
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z11my_copysignPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cmath>
__global__ void my_copysign(double* v)
{
int i = threadIdx.x;
*v = std::pow(-1, i) * (*v);
} | .text
.file "pow.hip"
.globl _Z26__device_stub__my_copysignPd # -- Begin function _Z26__device_stub__my_copysignPd
.p2align 4, 0x90
.type _Z26__device_stub__my_copysignPd,@function
_Z26__device_stub__my_copysignPd: # @_Z26__device_stub__my_copysignPd
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z11my_copysignPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z26__device_stub__my_copysignPd, .Lfunc_end0-_Z26__device_stub__my_copysignPd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11my_copysignPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11my_copysignPd,@object # @_Z11my_copysignPd
.section .rodata,"a",@progbits
.globl _Z11my_copysignPd
.p2align 3, 0x0
_Z11my_copysignPd:
.quad _Z26__device_stub__my_copysignPd
.size _Z11my_copysignPd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11my_copysignPd"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__my_copysignPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11my_copysignPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11my_copysignPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ BSSY B0, 0xd0 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0030*/ I2F.F64 R2, R8 ; /* 0x0000000800027312 */
/* 0x001e240000201c00 */
/*0040*/ LOP3.LUT R0, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003007812 */
/* 0x001fc800078ec0ff */
/*0050*/ LEA.HI R5, R0, 0xfffffc0c, RZ, 0xc ; /* 0xfffffc0c00057811 */
/* 0x000fc800078f60ff */
/*0060*/ SHF.L.U32 R0, R2.reuse, R5.reuse, RZ ; /* 0x0000000502007219 */
/* 0x0c0fe400000006ff */
/*0070*/ SHF.L.U64.HI R5, R2, R5, R3 ; /* 0x0000000502057219 */
/* 0x000fe40000010203 */
/*0080*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05070 */
/*0090*/ MOV R0, 0xc0 ; /* 0x000000c000007802 */
/* 0x000fe40000000f00 */
/*00a0*/ ISETP.NE.AND.EX P0, PT, R5, -0x80000000, PT, P0 ; /* 0x800000000500780c */
/* 0x000fd00003f05300 */
/*00b0*/ CALL.REL.NOINC 0x2f0 ; /* 0x0000023000007944 */
/* 0x000fea0003c00000 */
/*00c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*00d0*/ FRND.F64.TRUNC R4, R2 ; /* 0x0000000200047313 */
/* 0x000e62000030d800 */
/*00e0*/ DADD R6, R2, -1 ; /* 0xbff0000002067429 */
/* 0x000ea20000000000 */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ BSSY B0, 0x260 ; /* 0x0000015000007945 */
/* 0x000ff00003800000 */
/*0110*/ LOP3.LUT R6, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007067812 */
/* 0x004fc800078ec0ff */
/*0120*/ ISETP.NE.AND P2, PT, R6, 0x7ff00000, PT ; /* 0x7ff000000600780c */
/* 0x000fe20003f45270 */
/*0130*/ DSETP.NEU.AND P1, PT, R4, R2, PT ; /* 0x000000020400722a */
/* 0x0022a40003f2d000 */
/*0140*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x002fe400078e000f */
/*0150*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fc600078e000e */
/*0160*/ @!P0 LOP3.LUT R7, R5, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000005078812 */
/* 0x000fca00078e3cff */
/*0170*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff058224 */
/* 0x000fe400078e0007 */
/*0180*/ @P1 IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff041424 */
/* 0x004fe400078e00ff */
/*0190*/ @P1 IMAD.MOV.U32 R5, RZ, RZ, -0x80000 ; /* 0xfff80000ff051424 */
/* 0x000fe200078e00ff */
/*01a0*/ @P2 BRA 0x250 ; /* 0x000000a000002947 */
/* 0x000fea0003800000 */
/*01b0*/ DSETP.GTU.AND P0, PT, |R2|, +INF , PT ; /* 0x7ff000000200742a */
/* 0x000e5c0003f0c200 */
/*01c0*/ @P0 BRA 0x240 ; /* 0x0000007000000947 */
/* 0x002fea0003800000 */
/*01d0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f05270 */
/*01e0*/ LOP3.LUT R2, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03027812 */
/* 0x000fc800078ec0ff */
/*01f0*/ ISETP.EQ.AND P0, PT, R2, 0x7ff00000, !P0 ; /* 0x7ff000000200780c */
/* 0x000fda0004702270 */
/*0200*/ @!P0 BRA 0x250 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x000fe400078e00ff */
/*0220*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3ff00000 ; /* 0x3ff00000ff057424 */
/* 0x000fe200078e00ff */
/*0230*/ BRA 0x250 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0240*/ DADD R4, R2, -1 ; /* 0xbff0000002047429 */
/* 0x00028c0000000000 */
/*0250*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0260*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x002fe400078e00ff */
/*0270*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0280*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ee2000c1e1b00 */
/*0290*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc80003f05270 */
/*02a0*/ FSEL R4, R4, RZ, P0 ; /* 0x000000ff04047208 */
/* 0x004fe40000000000 */
/*02b0*/ FSEL R5, R5, 1.875, P0 ; /* 0x3ff0000005057808 */
/* 0x000fcc0000000000 */
/*02c0*/ DMUL R6, R6, R4 ; /* 0x0000000406067228 */
/* 0x008e4e0000000000 */
/*02d0*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x002fe2000c101b04 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ MUFU.RCP64H R11, 2 ; /* 0x40000000000b7908 */
/* 0x000e220000001800 */
/*0300*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x000fe400078e00ff */
/*0310*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3ff00000 ; /* 0x3ff00000ff057424 */
/* 0x000fe400078e00ff */
/*0320*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*0330*/ IMAD.MOV.U32 R6, RZ, RZ, 0x7d2cafe2 ; /* 0x7d2cafe2ff067424 */
/* 0x000fe400078e00ff */
/*0340*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3eb0f5ff ; /* 0x3eb0f5ffff077424 */
/* 0x000fc400078e00ff */
/*0350*/ IMAD.SHL.U32 R9, R3, 0x2, RZ ; /* 0x0000000203097824 */
/* 0x000fe200078e00ff */
/*0360*/ DFMA R4, R10, -2, R4 ; /* 0xc00000000a04782b */
/* 0x001e080000000004 */
/*0370*/ ISETP.GT.U32.AND P1, PT, R9, -0x2000001, PT ; /* 0xfdffffff0900780c */
/* 0x000fe40003f24070 */
/*0380*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x001e0c0000000004 */
/*0390*/ DFMA R10, R10, R4, R10 ; /* 0x000000040a0a722b */
/* 0x001e0c000000000a */
/*03a0*/ DMUL R4, RZ, R10 ; /* 0x0000000aff047228 */
/* 0x001e0c0000000000 */
/*03b0*/ DFMA R4, RZ, R10, R4 ; /* 0x0000000aff04722b */
/* 0x001e0c0000000004 */
/*03c0*/ DMUL R12, R4, R4 ; /* 0x00000004040c7228 */
/* 0x001e080000000000 */
/*03d0*/ DADD R14, RZ, -R4 ; /* 0x00000000ff0e7229 */
/* 0x000e480000000804 */
/*03e0*/ DFMA R6, R12, R6, c[0x2][0x0] ; /* 0x008000000c06762b */
/* 0x001e080000000006 */
/*03f0*/ DADD R16, R14, R14 ; /* 0x000000000e107229 */
/* 0x002fc8000000000e */
/*0400*/ DFMA R6, R12, R6, c[0x2][0x8] ; /* 0x008002000c06762b */
/* 0x001e080000000006 */
/*0410*/ DMUL R14, R4, R4 ; /* 0x00000004040e7228 */
/* 0x000fc80000000000 */
/*0420*/ DFMA R6, R12, R6, c[0x2][0x10] ; /* 0x008004000c06762b */
/* 0x001e080000000006 */
/*0430*/ DFMA R20, RZ, -R4, R16 ; /* 0x80000004ff14722b */
/* 0x000e480000000010 */
/*0440*/ DFMA R6, R12, R6, c[0x2][0x18] ; /* 0x008006000c06762b */
/* 0x001e080000000006 */
/*0450*/ DMUL R10, R10, R20 ; /* 0x000000140a0a7228 */
/* 0x002fc80000000000 */
/*0460*/ DFMA R6, R12, R6, c[0x2][0x20] ; /* 0x008008000c06762b */
/* 0x001e080000000006 */
/*0470*/ DFMA R16, R4, R4, -R14 ; /* 0x000000040410722b */
/* 0x000fc8000000080e */
/*0480*/ DFMA R18, R12, R6, c[0x2][0x28] ; /* 0x00800a000c12762b */
/* 0x001e0c0000000006 */
/*0490*/ DFMA R6, R12, R18, c[0x2][0x30] ; /* 0x00800c000c06762b */
/* 0x001e0c0000000012 */
/*04a0*/ DADD R22, -R6, c[0x2][0x30] ; /* 0x00800c0006167629 */
/* 0x001e0c0000000100 */
/*04b0*/ DFMA R22, R12, R18, R22 ; /* 0x000000120c16722b */
/* 0x001e080000000016 */
/*04c0*/ DMUL R12, R4, R14 ; /* 0x0000000e040c7228 */
/* 0x000e480000000000 */
/*04d0*/ DADD R18, RZ, R22 ; /* 0x00000000ff127229 */
/* 0x001e080000000016 */
/*04e0*/ DFMA R20, R4, R14, -R12 ; /* 0x0000000e0414722b */
/* 0x002e48000000080c */
/*04f0*/ DADD R18, R18, c[0x2][0x38] ; /* 0x00800e0012127629 */
/* 0x001e080000000000 */
/*0500*/ DFMA R22, R10, R14, R20 ; /* 0x0000000e0a16722b */
/* 0x0023e40000000014 */
/*0510*/ IADD3 R21, R11, 0x100000, RZ ; /* 0x001000000b157810 */
/* 0x002fe20007ffe0ff */
/*0520*/ IMAD.MOV.U32 R20, RZ, RZ, R10 ; /* 0x000000ffff147224 */
/* 0x000fe200078e000a */
/*0530*/ DADD R14, R6, R18 ; /* 0x00000000060e7229 */
/* 0x001e0a0000000012 */
/*0540*/ DFMA R20, R4, R20, R16 ; /* 0x000000140414722b */
/* 0x000e480000000010 */
/*0550*/ DMUL R16, R14, R12 ; /* 0x0000000c0e107228 */
/* 0x001e080000000000 */
/*0560*/ DFMA R20, R4, R20, R22 ; /* 0x000000140414722b */
/* 0x002fc80000000016 */
/*0570*/ DADD R6, R6, -R14 ; /* 0x0000000006067229 */
/* 0x000e48000000080e */
/*0580*/ DFMA R22, R14, R12, -R16 ; /* 0x0000000c0e16722b */
/* 0x001e080000000810 */
/*0590*/ DADD R6, R18, R6 ; /* 0x0000000012067229 */
/* 0x0023e40000000006 */
/*05a0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff127424 */
/* 0x002fe400078e00ff */
/*05b0*/ DFMA R20, R14, R20, R22 ; /* 0x000000140e14722b */
/* 0x001e220000000016 */
/*05c0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff137424 */
/* 0x000fca00078e00ff */
/*05d0*/ DFMA R20, R6, R12, R20 ; /* 0x0000000c0614722b */
/* 0x001e0c0000000014 */
/*05e0*/ DADD R12, R16, R20 ; /* 0x00000000100c7229 */
/* 0x001e0c0000000014 */
/*05f0*/ DADD R6, R4, R12 ; /* 0x0000000004067229 */
/* 0x001e08000000000c */
/*0600*/ DADD R16, R16, -R12 ; /* 0x0000000010107229 */
/* 0x000e48000000080c */
/*0610*/ DADD R4, R4, -R6 ; /* 0x0000000004047229 */
/* 0x001e080000000806 */
/*0620*/ DADD R16, R20, R16 ; /* 0x0000000014107229 */
/* 0x002fc80000000010 */
/*0630*/ DADD R4, R12, R4 ; /* 0x000000000c047229 */
/* 0x001e0c0000000004 */
/*0640*/ DADD R4, R16, R4 ; /* 0x0000000010047229 */
/* 0x001e0c0000000004 */
/*0650*/ DADD R10, R10, R4 ; /* 0x000000000a0a7229 */
/* 0x001e0c0000000004 */
/*0660*/ DADD R12, R6, R10 ; /* 0x00000000060c7229 */
/* 0x001e0c000000000a */
/*0670*/ DFMA R4, RZ, c[0x2][0x40], R12 ; /* 0x00801000ff047a2b */
/* 0x001e08000000000c */
/*0680*/ DADD R6, R6, -R12 ; /* 0x0000000006067229 */
/* 0x000e48000000080c */
/*0690*/ DFMA R14, -RZ, c[0x2][0x40], R4 ; /* 0x00801000ff0e7a2b */
/* 0x001e080000000104 */
/*06a0*/ DADD R6, R10, R6 ; /* 0x000000000a067229 */
/* 0x002fc80000000006 */
/*06b0*/ DADD R14, -R12, R14 ; /* 0x000000000c0e7229 */
/* 0x001e0c000000010e */
/*06c0*/ DADD R6, R6, -R14 ; /* 0x0000000006067229 */
/* 0x001064000000080e */
/*06d0*/ LOP3.LUT R15, R3, 0xff0fffff, RZ, 0xc0, !PT ; /* 0xff0fffff030f7812 */
/* 0x001fe200078ec0ff */
/*06e0*/ IMAD.MOV.U32 R14, RZ, RZ, R2 ; /* 0x000000ffff0e7224 */
/* 0x000fc600078e0002 */
/*06f0*/ DFMA R6, RZ, c[0x2][0x48], R6 ; /* 0x00801200ff067a2b */
/* 0x002e220000000006 */
/*0700*/ SEL R15, R15, R3, P1 ; /* 0x000000030f0f7207 */
/* 0x000fca0000800000 */
/*0710*/ DADD R10, R4, R6 ; /* 0x00000000040a7229 */
/* 0x001e0c0000000006 */
/*0720*/ DADD R12, R4, -R10 ; /* 0x00000000040c7229 */
/* 0x001e08000000080a */
/*0730*/ DMUL R4, R10, R14 ; /* 0x0000000e0a047228 */
/* 0x000e480000000000 */
/*0740*/ DADD R6, R6, R12 ; /* 0x0000000006067229 */
/* 0x0011e4000000000c */
/*0750*/ IMAD.MOV.U32 R12, RZ, RZ, 0x652b82fe ; /* 0x652b82feff0c7424 */
/* 0x001fe400078e00ff */
/*0760*/ DFMA R10, R10, R14, -R4 ; /* 0x0000000e0a0a722b */
/* 0x002e220000000804 */
/*0770*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff0d7424 */
/* 0x000fca00078e00ff */
/*0780*/ DFMA R6, R6, R14, R10 ; /* 0x0000000e0606722b */
/* 0x001e0c000000000a */
/*0790*/ DADD R10, R4, R6 ; /* 0x00000000040a7229 */
/* 0x001e0c0000000006 */
/*07a0*/ DFMA R12, R10, R12, 6.75539944105574400000e+15 ; /* 0x433800000a0c742b */
/* 0x001e08000000000c */
/*07b0*/ FSETP.GEU.AND P1, PT, |R11|, 4.1917929649353027344, PT ; /* 0x4086232b0b00780b */
/* 0x000fe40003f2e200 */
/*07c0*/ DADD R14, R12, -6.75539944105574400000e+15 ; /* 0xc33800000c0e7429 */
/* 0x001e0c0000000000 */
/*07d0*/ DFMA R16, R14, c[0x2][0x50], R10 ; /* 0x008014000e107a2b */
/* 0x001e0c000000000a */
/*07e0*/ DFMA R14, R14, c[0x2][0x58], R16 ; /* 0x008016000e0e7a2b */
/* 0x001e0c0000000010 */
/*07f0*/ DFMA R16, R14, R18, c[0x2][0x60] ; /* 0x008018000e10762b */
/* 0x001e0c0000000012 */
/*0800*/ DFMA R16, R14, R16, c[0x2][0x68] ; /* 0x00801a000e10762b */
/* 0x001e0c0000000010 */
/*0810*/ DFMA R16, R14, R16, c[0x2][0x70] ; /* 0x00801c000e10762b */
/* 0x001e0c0000000010 */
/*0820*/ DFMA R16, R14, R16, c[0x2][0x78] ; /* 0x00801e000e10762b */
/* 0x001e0c0000000010 */
/*0830*/ DFMA R16, R14, R16, c[0x2][0x80] ; /* 0x008020000e10762b */
/* 0x001e0c0000000010 */
/*0840*/ DFMA R16, R14, R16, c[0x2][0x88] ; /* 0x008022000e10762b */
/* 0x001e0c0000000010 */
/*0850*/ DFMA R16, R14, R16, c[0x2][0x90] ; /* 0x008024000e10762b */
/* 0x001e0c0000000010 */
/*0860*/ DFMA R16, R14, R16, c[0x2][0x98] ; /* 0x008026000e10762b */
/* 0x001e0c0000000010 */
/*0870*/ DFMA R16, R14, R16, c[0x2][0xa0] ; /* 0x008028000e10762b */
/* 0x001e0c0000000010 */
/*0880*/ DFMA R16, R14, R16, 1 ; /* 0x3ff000000e10742b */
/* 0x001e0c0000000010 */
/*0890*/ DFMA R16, R14, R16, 1 ; /* 0x3ff000000e10742b */
/* 0x001e140000000010 */
/*08a0*/ IMAD R15, R12, 0x100000, R17 ; /* 0x001000000c0f7824 */
/* 0x001fe400078e0211 */
/*08b0*/ IMAD.MOV.U32 R14, RZ, RZ, R16 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0010 */
/*08c0*/ @!P1 BRA 0x990 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*08d0*/ FSETP.GEU.AND P2, PT, |R11|, 4.2275390625, PT ; /* 0x408748000b00780b */
/* 0x000fe20003f4e200 */
/*08e0*/ DADD R14, R10, +INF ; /* 0x7ff000000a0e7429 */
/* 0x000fc80000000000 */
/*08f0*/ DSETP.GEU.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00722a */
/* 0x000e0c0003f2e000 */
/*0900*/ FSEL R14, R14, RZ, P1 ; /* 0x000000ff0e0e7208 */
/* 0x001fe40000800000 */
/*0910*/ @!P2 LEA.HI R9, R12, R12, RZ, 0x1 ; /* 0x0000000c0c09a211 */
/* 0x000fe400078f08ff */
/*0920*/ FSEL R15, R15, RZ, P1 ; /* 0x000000ff0f0f7208 */
/* 0x000fe40000800000 */
/*0930*/ @!P2 SHF.R.S32.HI R9, RZ, 0x1, R9 ; /* 0x00000001ff09a819 */
/* 0x000fca0000011409 */
/*0940*/ @!P2 IMAD.IADD R12, R12, 0x1, -R9 ; /* 0x000000010c0ca824 */
/* 0x000fe400078e0a09 */
/*0950*/ @!P2 IMAD R17, R9, 0x100000, R17 ; /* 0x001000000911a824 */
/* 0x000fc600078e0211 */
/*0960*/ @!P2 LEA R13, R12, 0x3ff00000, 0x14 ; /* 0x3ff000000c0da811 */
/* 0x000fe200078ea0ff */
/*0970*/ @!P2 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0ca224 */
/* 0x000fcc00078e00ff */
/*0980*/ @!P2 DMUL R14, R16, R12 ; /* 0x0000000c100ea228 */
/* 0x0000540000000000 */
/*0990*/ LOP3.LUT R9, R15, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0f097812 */
/* 0x002fe200078ec0ff */
/*09a0*/ DADD R4, R4, -R10 ; /* 0x0000000004047229 */
/* 0x000e46000000080a */
/*09b0*/ ISETP.NE.AND P1, PT, R9, 0x7ff00000, PT ; /* 0x7ff000000900780c */
/* 0x000fc60003f25270 */
/*09c0*/ DADD R4, R6, R4 ; /* 0x0000000006047229 */
/* 0x002e620000000004 */
/*09d0*/ ISETP.EQ.AND P1, PT, R14, RZ, !P1 ; /* 0x000000ff0e00720c */
/* 0x000fda0004f22270 */
/*09e0*/ @!P1 DFMA R14, R4, R14, R14 ; /* 0x0000000e040e922b */
/* 0x0022a4000000000e */
/*09f0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x002fe400078e0000 */
/*0a00*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0a10*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff5e004007950 */
/* 0x004fea0003c3ffff */
/*0a20*/ BRA 0xa20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11my_copysignPd
.globl _Z11my_copysignPd
.p2align 8
.type _Z11my_copysignPd,@function
_Z11my_copysignPd:
v_cvt_f64_i32_e32 v[1:2], v0
s_mov_b32 s3, 0x3ff71547
s_mov_b32 s2, 0x652b82fe
s_mov_b32 s5, 0x3e5ade15
s_mov_b32 s4, 0x6a5dcb37
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[3:4], v[1:2], 0
v_fma_f64 v[5:6], v[1:2], 0, -v[3:4]
v_cmp_class_f64_e64 vcc_lo, v[3:4], 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[5:6], v[1:2], 0, v[5:6]
v_mul_f64 v[1:2], v[1:2], 0.5
v_add_f64 v[7:8], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v10, v8, v4 :: v_dual_cndmask_b32 v9, v7, v3
v_add_f64 v[3:4], v[7:8], -v[3:4]
v_mul_f64 v[11:12], v[9:10], s[2:3]
s_mov_b32 s3, 0xbfe62e42
s_mov_b32 s2, 0xfefa39ef
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[9:10]|
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[3:4], v[5:6], -v[3:4]
v_rndne_f64_e32 v[11:12], v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v4, 0, v4 :: v_dual_cndmask_b32 v3, 0, v3
v_fma_f64 v[13:14], v[11:12], s[2:3], v[9:10]
s_mov_b32 s3, 0xbc7abc9e
s_mov_b32 s2, 0x3b39803f
v_cvt_i32_f64_e32 v17, v[11:12]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[13:14], v[11:12], s[2:3], v[13:14]
s_mov_b32 s3, 0x3e928af3
s_mov_b32 s2, 0xfca7ab0c
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], s[4:5], s[2:3]
s_mov_b32 s3, 0x3ec71dee
s_mov_b32 s2, 0x623fde64
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
s_mov_b32 s3, 0x3efa0199
s_mov_b32 s2, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
s_mov_b32 s3, 0x3f2a01a0
s_mov_b32 s2, 0x14761f6e
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
s_mov_b32 s3, 0x3f56c16c
s_mov_b32 s2, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
s_mov_b32 s3, 0x3f811111
s_mov_b32 s2, 0x11122322
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
s_mov_b32 s3, 0x3fa55555
s_mov_b32 s2, 0x555502a1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
s_mov_b32 s3, 0x3fc55555
s_mov_b32 s2, 0x55555511
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
s_mov_b32 s3, 0x3fe00000
s_mov_b32 s2, 11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
v_cmp_nlt_f64_e64 s2, 0x40900000, v[9:10]
v_cmp_ngt_f64_e64 s3, 0xc090cc00, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[15:16], v[13:14], v[15:16], 1.0
s_and_b32 vcc_lo, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], v[13:14], v[15:16], 1.0
v_ldexp_f64 v[7:8], v[11:12], v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v5, 0x7ff00000, v8, s2
v_cndmask_b32_e64 v6, 0, v5, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, 0, v7, vcc_lo
v_trunc_f64_e32 v[7:8], v[1:2]
s_load_b64 s[2:3], s[0:1], 0x0
v_cmp_eq_u32_e64 s0, 0, v0
v_fma_f64 v[3:4], v[5:6], v[3:4], v[5:6]
v_cmp_class_f64_e64 vcc_lo, v[5:6], 0x204
v_mov_b32_e32 v9, 0x3ff00000
s_waitcnt lgkmcnt(0)
s_load_b64 s[4:5], s[2:3], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v0, v3, v5 :: v_dual_cndmask_b32 v3, v4, v6
v_cmp_neq_f64_e32 vcc_lo, v[7:8], v[1:2]
v_cndmask_b32_e64 v9, 0xbff00000, v9, s0
v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v1, 0x3ff00000, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_bfi_b32 v1, 0x7fffffff, v3, v1
s_waitcnt lgkmcnt(0)
v_mul_f64 v[0:1], v[0:1], s[4:5]
global_store_b64 v2, v[0:1], s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11my_copysignPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11my_copysignPd, .Lfunc_end0-_Z11my_copysignPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11my_copysignPd
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z11my_copysignPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013d6ca_00000000-6_pow.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z11my_copysignPdPd
.type _Z31__device_stub__Z11my_copysignPdPd, @function
_Z31__device_stub__Z11my_copysignPdPd:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11my_copysignPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z11my_copysignPdPd, .-_Z31__device_stub__Z11my_copysignPdPd
.globl _Z11my_copysignPd
.type _Z11my_copysignPd, @function
_Z11my_copysignPd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z11my_copysignPdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11my_copysignPd, .-_Z11my_copysignPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11my_copysignPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11my_copysignPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pow.hip"
.globl _Z26__device_stub__my_copysignPd # -- Begin function _Z26__device_stub__my_copysignPd
.p2align 4, 0x90
.type _Z26__device_stub__my_copysignPd,@function
_Z26__device_stub__my_copysignPd: # @_Z26__device_stub__my_copysignPd
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z11my_copysignPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z26__device_stub__my_copysignPd, .Lfunc_end0-_Z26__device_stub__my_copysignPd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11my_copysignPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11my_copysignPd,@object # @_Z11my_copysignPd
.section .rodata,"a",@progbits
.globl _Z11my_copysignPd
.p2align 3, 0x0
_Z11my_copysignPd:
.quad _Z26__device_stub__my_copysignPd
.size _Z11my_copysignPd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11my_copysignPd"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__my_copysignPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11my_copysignPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void KernelTilesMul(int *Mat1,int *Mat2,int *Mat3,int rowM1,int colM1,int colM2){
__shared__ int Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ int Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * TILE_WIDTH + ty;
int col = bx * TILE_WIDTH + tx;
int Pvalue = 0;
for(int k = 0; k < (colM1+TILE_WIDTH-1)/(TILE_WIDTH); ++k){
if(k*TILE_WIDTH + tx < colM1 && row < rowM1){
Mds[ty][tx] = Mat1[row*colM1 + k*TILE_WIDTH + tx];
}else{
Mds[ty][tx] = 0;
}
if(k*TILE_WIDTH + ty < colM1 && col < colM2){
Nds[ty][tx] = Mat2[(k*TILE_WIDTH + ty) * colM2 + col];
}else{
Nds[ty][tx] =0;
}
__syncthreads();
for(int k = 0; k < TILE_WIDTH; ++k){
Pvalue += Mds[ty][k] * Nds[k][tx];
}
__syncthreads();
}
if (row < rowM1 && col < colM2){
Mat3[row*colM2+col] = Pvalue;
}
} | code for sm_80
Function : _Z14KernelTilesMulPiS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff067624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000e240000002100 */
/*0060*/ ISETP.GE.AND P1, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe40003f26270 */
/*0070*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0080*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0090*/ LEA R0, R9, R12, 0x4 ; /* 0x0000000c09007211 */
/* 0x001fc800078e20ff */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe40003f06270 */
/*00b0*/ LEA R3, R3, R2, 0x4 ; /* 0x0000000203037211 */
/* 0x002fc800078e20ff */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe20000706670 */
/*00d0*/ @!P1 BRA 0x5b0 ; /* 0x000004d000009947 */
/* 0x000fd80003800000 */
/*00e0*/ IADD3 R6, R6, 0xf, RZ ; /* 0x0000000f06067810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0100*/ SHF.L.U32 R15, R2.reuse, 0x6, RZ ; /* 0x00000006020f7819 */
/* 0x040fe200000006ff */
/*0110*/ IMAD R4, R3, c[0x0][0x17c], R12 ; /* 0x00005f0003047a24 */
/* 0x000fe200078e020c */
/*0120*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fe20000011406 */
/*0130*/ IMAD R16, R2, c[0x0][0x180], R12 ; /* 0x0000600002107a24 */
/* 0x000fe200078e020c */
/*0140*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*0160*/ LEA.HI R7, R7, R6, RZ, 0x4 ; /* 0x0000000607077211 */
/* 0x000fe200078f20ff */
/*0170*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0180*/ LEA R16, R9, R16, 0x4 ; /* 0x0000001009107211 */
/* 0x000fe200078e20ff */
/*0190*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0004 */
/*01a0*/ MOV R13, R5 ; /* 0x00000005000d7202 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD R19, R12.reuse, 0x4, R15 ; /* 0x000000040c137824 */
/* 0x040fe200078e020f */
/*01c0*/ LEA R18, R12, 0x400, 0x2 ; /* 0x000004000c127811 */
/* 0x000fc400078e10ff */
/*01d0*/ SHF.R.S32.HI R17, RZ, 0x4, R7 ; /* 0x00000004ff117819 */
/* 0x000fe40000011407 */
/*01e0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x17c], PT ; /* 0x00005f0002007a0c */
/* 0x000fe20003f26270 */
/*01f0*/ HFMA2.MMA R22, -RZ, RZ, 0, 0 ; /* 0x00000000ff167435 */
/* 0x000fe200000001ff */
/*0200*/ ISETP.GE.AND P2, PT, R12, c[0x0][0x17c], PT ; /* 0x00005f000c007a0c */
/* 0x000fe20003f46270 */
/*0210*/ IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c7224 */
/* 0x000fe200078e00ff */
/*0220*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x180], P1 ; /* 0x0000600000007a0c */
/* 0x000fe40000f26670 */
/*0230*/ ISETP.GE.OR P2, PT, R3, c[0x0][0x178], P2 ; /* 0x00005e0003007a0c */
/* 0x000fd60001746670 */
/*0240*/ @!P1 MOV R25, 0x4 ; /* 0x0000000400199802 */
/* 0x000fe40000000f00 */
/*0250*/ @!P2 MOV R4, R14 ; /* 0x0000000e0004a202 */
/* 0x000fe40000000f00 */
/*0260*/ @!P2 MOV R5, R13 ; /* 0x0000000d0005a202 */
/* 0x000fe20000000f00 */
/*0270*/ @!P1 IMAD.WIDE R24, R16, R25, c[0x0][0x168] ; /* 0x00005a0010189625 */
/* 0x000fc800078e0219 */
/*0280*/ @!P2 LDG.E R22, [R4.64] ; /* 0x000000060416a981 */
/* 0x000ea8000c1e1900 */
/*0290*/ @!P1 LDG.E R28, [R24.64] ; /* 0x00000006181c9981 */
/* 0x000ee2000c1e1900 */
/*02a0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*02b0*/ IADD3 R14, P2, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x000fe40007f5e0ff */
/*02c0*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe40007ffe0ff */
/*02d0*/ IADD3 R12, R12, 0x10, RZ ; /* 0x000000100c0c7810 */
/* 0x000fc40007ffe0ff */
/*02e0*/ ISETP.LE.AND P1, PT, R17, UR4, PT ; /* 0x0000000411007c0c */
/* 0x000fe4000bf23270 */
/*02f0*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*0300*/ STS [R19], R22 ; /* 0x0000001613007388 */
/* 0x004fe80000000800 */
/*0310*/ STS [R19+0x400], R28 ; /* 0x0004001c13007388 */
/* 0x008fe80000000800 */
/*0320*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0330*/ LDS R29, [R18] ; /* 0x00000000121d7984 */
/* 0x000fe80000000800 */
/*0340*/ LDS.128 R8, [R15] ; /* 0x000000000f087984 */
/* 0x000e280000000c00 */
/*0350*/ LDS R24, [R18+0x40] ; /* 0x0000400012187984 */
/* 0x000e680000000800 */
/*0360*/ LDS R27, [R18+0x80] ; /* 0x00008000121b7984 */
/* 0x000ea80000000800 */
/*0370*/ LDS R26, [R18+0xc0] ; /* 0x0000c000121a7984 */
/* 0x000ee80000000800 */
/*0380*/ LDS R23, [R18+0x100] ; /* 0x0001000012177984 */
/* 0x000fe80000000800 */
/*0390*/ LDS.128 R4, [R15+0x10] ; /* 0x000010000f047984 */
/* 0x000f280000000c00 */
/*03a0*/ LDS R20, [R18+0x140] ; /* 0x0001400012147984 */
/* 0x000f680000000800 */
/*03b0*/ LDS R25, [R18+0x180] ; /* 0x0001800012197984 */
/* 0x000f680000000800 */
/*03c0*/ LDS R22, [R18+0x1c0] ; /* 0x0001c00012167984 */
/* 0x000f620000000800 */
/*03d0*/ IMAD R8, R29, R8, R21 ; /* 0x000000081d087224 */
/* 0x001fc600078e0215 */
/*03e0*/ LDS R21, [R18+0x200] ; /* 0x0002000012157984 */
/* 0x000fe20000000800 */
/*03f0*/ IMAD R8, R24, R9, R8 ; /* 0x0000000918087224 */
/* 0x002fc600078e0208 */
/*0400*/ LDS R24, [R18+0x240] ; /* 0x0002400012187984 */
/* 0x000fe20000000800 */
/*0410*/ IMAD R8, R27, R10, R8 ; /* 0x0000000a1b087224 */
/* 0x004fc800078e0208 */
/*0420*/ IMAD R26, R26, R11, R8 ; /* 0x0000000b1a1a7224 */
/* 0x008fe400078e0208 */
/*0430*/ LDS.128 R8, [R15+0x20] ; /* 0x000020000f087984 */
/* 0x000e240000000c00 */
/*0440*/ IMAD R4, R23, R4, R26 ; /* 0x0000000417047224 */
/* 0x010fe400078e021a */
/*0450*/ LDS R23, [R18+0x280] ; /* 0x0002800012177984 */
/* 0x000e640000000800 */
/*0460*/ IMAD R4, R20, R5, R4 ; /* 0x0000000514047224 */
/* 0x020fe400078e0204 */
/*0470*/ LDS R20, [R18+0x2c0] ; /* 0x0002c00012147984 */
/* 0x000ea40000000800 */
/*0480*/ IMAD R4, R25, R6, R4 ; /* 0x0000000619047224 */
/* 0x000fc400078e0204 */
/*0490*/ LDS R25, [R18+0x300] ; /* 0x0003000012197984 */
/* 0x000fe40000000800 */
/*04a0*/ IMAD R26, R22, R7, R4 ; /* 0x00000007161a7224 */
/* 0x000fe400078e0204 */
/*04b0*/ LDS.128 R4, [R15+0x30] ; /* 0x000030000f047984 */
/* 0x000ee80000000c00 */
/*04c0*/ LDS R22, [R18+0x340] ; /* 0x0003400012167984 */
/* 0x000f220000000800 */
/*04d0*/ IMAD R26, R21, R8, R26 ; /* 0x00000008151a7224 */
/* 0x001fc600078e021a */
/*04e0*/ LDS R21, [R18+0x380] ; /* 0x0003800012157984 */
/* 0x000e220000000800 */
/*04f0*/ IMAD R9, R24, R9, R26 ; /* 0x0000000918097224 */
/* 0x000fc600078e021a */
/*0500*/ LDS R8, [R18+0x3c0] ; /* 0x0003c00012087984 */
/* 0x000f620000000800 */
/*0510*/ IMAD R9, R23, R10, R9 ; /* 0x0000000a17097224 */
/* 0x002fc800078e0209 */
/*0520*/ IMAD R9, R20, R11, R9 ; /* 0x0000000b14097224 */
/* 0x004fc800078e0209 */
/*0530*/ IMAD R4, R25, R4, R9 ; /* 0x0000000419047224 */
/* 0x008fc800078e0209 */
/*0540*/ IMAD R4, R22, R5, R4 ; /* 0x0000000516047224 */
/* 0x010fe400078e0204 */
/*0550*/ IMAD.MOV.U32 R5, RZ, RZ, 0x10 ; /* 0x00000010ff057424 */
/* 0x000fc800078e00ff */
/*0560*/ IMAD R16, R5, c[0x0][0x180], R16 ; /* 0x0000600005107a24 */
/* 0x000fe400078e0210 */
/*0570*/ IMAD R21, R21, R6, R4 ; /* 0x0000000615157224 */
/* 0x001fc800078e0204 */
/*0580*/ IMAD R21, R8, R7, R21 ; /* 0x0000000708157224 */
/* 0x020fe200078e0215 */
/*0590*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05a0*/ @!P1 BRA 0x1e0 ; /* 0xfffffc3000009947 */
/* 0x000fea000383ffff */
/*05b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*05c0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*05d0*/ IMAD R3, R3, c[0x0][0x180], R0 ; /* 0x0000600003037a24 */
/* 0x000fd200078e0200 */
/*05e0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*05f0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*0600*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0610*/ BRA 0x610; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void KernelTilesMul(int *Mat1,int *Mat2,int *Mat3,int rowM1,int colM1,int colM2){
__shared__ int Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ int Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * TILE_WIDTH + ty;
int col = bx * TILE_WIDTH + tx;
int Pvalue = 0;
for(int k = 0; k < (colM1+TILE_WIDTH-1)/(TILE_WIDTH); ++k){
if(k*TILE_WIDTH + tx < colM1 && row < rowM1){
Mds[ty][tx] = Mat1[row*colM1 + k*TILE_WIDTH + tx];
}else{
Mds[ty][tx] = 0;
}
if(k*TILE_WIDTH + ty < colM1 && col < colM2){
Nds[ty][tx] = Mat2[(k*TILE_WIDTH + ty) * colM2 + col];
}else{
Nds[ty][tx] =0;
}
__syncthreads();
for(int k = 0; k < TILE_WIDTH; ++k){
Pvalue += Mds[ty][k] * Nds[k][tx];
}
__syncthreads();
}
if (row < rowM1 && col < colM2){
Mat3[row*colM2+col] = Pvalue;
}
} | .file "tmpxft_000b4cbc_00000000-6_KernelTilesMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z14KernelTilesMulPiS_S_iiiPiS_S_iii
.type _Z41__device_stub__Z14KernelTilesMulPiS_S_iiiPiS_S_iii, @function
_Z41__device_stub__Z14KernelTilesMulPiS_S_iiiPiS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14KernelTilesMulPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z14KernelTilesMulPiS_S_iiiPiS_S_iii, .-_Z41__device_stub__Z14KernelTilesMulPiS_S_iiiPiS_S_iii
.globl _Z14KernelTilesMulPiS_S_iii
.type _Z14KernelTilesMulPiS_S_iii, @function
_Z14KernelTilesMulPiS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14KernelTilesMulPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14KernelTilesMulPiS_S_iii, .-_Z14KernelTilesMulPiS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14KernelTilesMulPiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14KernelTilesMulPiS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void KernelTilesMul(int *Mat1,int *Mat2,int *Mat3,int rowM1,int colM1,int colM2){
__shared__ int Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ int Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * TILE_WIDTH + ty;
int col = bx * TILE_WIDTH + tx;
int Pvalue = 0;
for(int k = 0; k < (colM1+TILE_WIDTH-1)/(TILE_WIDTH); ++k){
if(k*TILE_WIDTH + tx < colM1 && row < rowM1){
Mds[ty][tx] = Mat1[row*colM1 + k*TILE_WIDTH + tx];
}else{
Mds[ty][tx] = 0;
}
if(k*TILE_WIDTH + ty < colM1 && col < colM2){
Nds[ty][tx] = Mat2[(k*TILE_WIDTH + ty) * colM2 + col];
}else{
Nds[ty][tx] =0;
}
__syncthreads();
for(int k = 0; k < TILE_WIDTH; ++k){
Pvalue += Mds[ty][k] * Nds[k][tx];
}
__syncthreads();
}
if (row < rowM1 && col < colM2){
Mat3[row*colM2+col] = Pvalue;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void KernelTilesMul(int *Mat1,int *Mat2,int *Mat3,int rowM1,int colM1,int colM2){
__shared__ int Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ int Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * TILE_WIDTH + ty;
int col = bx * TILE_WIDTH + tx;
int Pvalue = 0;
for(int k = 0; k < (colM1+TILE_WIDTH-1)/(TILE_WIDTH); ++k){
if(k*TILE_WIDTH + tx < colM1 && row < rowM1){
Mds[ty][tx] = Mat1[row*colM1 + k*TILE_WIDTH + tx];
}else{
Mds[ty][tx] = 0;
}
if(k*TILE_WIDTH + ty < colM1 && col < colM2){
Nds[ty][tx] = Mat2[(k*TILE_WIDTH + ty) * colM2 + col];
}else{
Nds[ty][tx] =0;
}
__syncthreads();
for(int k = 0; k < TILE_WIDTH; ++k){
Pvalue += Mds[ty][k] * Nds[k][tx];
}
__syncthreads();
}
if (row < rowM1 && col < colM2){
Mat3[row*colM2+col] = Pvalue;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void KernelTilesMul(int *Mat1,int *Mat2,int *Mat3,int rowM1,int colM1,int colM2){
__shared__ int Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ int Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * TILE_WIDTH + ty;
int col = bx * TILE_WIDTH + tx;
int Pvalue = 0;
for(int k = 0; k < (colM1+TILE_WIDTH-1)/(TILE_WIDTH); ++k){
if(k*TILE_WIDTH + tx < colM1 && row < rowM1){
Mds[ty][tx] = Mat1[row*colM1 + k*TILE_WIDTH + tx];
}else{
Mds[ty][tx] = 0;
}
if(k*TILE_WIDTH + ty < colM1 && col < colM2){
Nds[ty][tx] = Mat2[(k*TILE_WIDTH + ty) * colM2 + col];
}else{
Nds[ty][tx] =0;
}
__syncthreads();
for(int k = 0; k < TILE_WIDTH; ++k){
Pvalue += Mds[ty][k] * Nds[k][tx];
}
__syncthreads();
}
if (row < rowM1 && col < colM2){
Mat3[row*colM2+col] = Pvalue;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14KernelTilesMulPiS_S_iii
.globl _Z14KernelTilesMulPiS_S_iii
.p2align 8
.type _Z14KernelTilesMulPiS_S_iii,@function
_Z14KernelTilesMulPiS_S_iii:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
v_bfe_u32 v6, v0, 10, 10
v_and_b32_e32 v1, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v5, s15, 4, v6
v_lshl_add_u32 v0, s14, 4, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v5
v_cmp_gt_i32_e64 s2, s3, v0
s_cmp_lt_i32 s9, 1
s_cbranch_scc1 .LBB0_13
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v1
v_lshlrev_b32_e32 v7, 6, v6
s_add_i32 s10, s9, 15
s_mov_b32 s11, 0
v_mov_b32_e32 v10, 0
v_add_nc_u32_e32 v8, 0x400, v2
v_mad_u64_u32 v[3:4], null, v5, s9, v[1:2]
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v9, v7, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v4, v8, v7
s_lshr_b32 s10, s10, 4
s_xor_b32 s12, vcc_lo, -1
s_max_i32 s10, s10, 1
s_xor_b32 s2, s2, -1
.LBB0_2:
s_lshl_b32 s13, s11, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v11, s13, v1
v_cmp_le_i32_e32 vcc_lo, s9, v11
s_or_b32 s14, vcc_lo, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s15, s14
s_xor_b32 s14, exec_lo, s15
s_cbranch_execz .LBB0_4
ds_store_b32 v9, v10
.LBB0_4:
s_and_not1_saveexec_b32 s14, s14
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v11, s13, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
global_load_b32 v11, v[11:12], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v11
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s14
v_add_nc_u32_e32 v11, s13, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s9, v11
s_or_b32 s13, vcc_lo, s2
s_and_saveexec_b32 s14, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s13, exec_lo, s14
s_cbranch_execz .LBB0_8
ds_store_b32 v4, v10
.LBB0_8:
s_and_not1_saveexec_b32 s13, s13
s_cbranch_execz .LBB0_10
v_mad_u64_u32 v[12:13], null, v11, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[11:12], 2, v[12:13]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v11, v[11:12], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v11
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s13
v_mov_b32_e32 v11, v8
s_mov_b32 s13, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_11:
v_add_nc_u32_e32 v12, s13, v7
s_add_i32 s13, s13, 4
ds_load_b32 v14, v11
ds_load_b32 v15, v12
s_cmp_eq_u32 s13, 64
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[12:13], null, v14, v15, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v2, v12 :: v_dual_add_nc_u32 v11, 64, v11
s_cbranch_scc0 .LBB0_11
s_add_i32 s11, s11, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s11, s10
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_14
.LBB0_13:
v_mov_b32_e32 v2, 0
.LBB0_14:
v_cmp_gt_i32_e32 vcc_lo, s8, v5
v_cmp_gt_i32_e64 s2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_16
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v5, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14KernelTilesMulPiS_S_iii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14KernelTilesMulPiS_S_iii, .Lfunc_end0-_Z14KernelTilesMulPiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14KernelTilesMulPiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14KernelTilesMulPiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void KernelTilesMul(int *Mat1,int *Mat2,int *Mat3,int rowM1,int colM1,int colM2){
__shared__ int Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ int Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * TILE_WIDTH + ty;
int col = bx * TILE_WIDTH + tx;
int Pvalue = 0;
for(int k = 0; k < (colM1+TILE_WIDTH-1)/(TILE_WIDTH); ++k){
if(k*TILE_WIDTH + tx < colM1 && row < rowM1){
Mds[ty][tx] = Mat1[row*colM1 + k*TILE_WIDTH + tx];
}else{
Mds[ty][tx] = 0;
}
if(k*TILE_WIDTH + ty < colM1 && col < colM2){
Nds[ty][tx] = Mat2[(k*TILE_WIDTH + ty) * colM2 + col];
}else{
Nds[ty][tx] =0;
}
__syncthreads();
for(int k = 0; k < TILE_WIDTH; ++k){
Pvalue += Mds[ty][k] * Nds[k][tx];
}
__syncthreads();
}
if (row < rowM1 && col < colM2){
Mat3[row*colM2+col] = Pvalue;
}
} | .text
.file "KernelTilesMul.hip"
.globl _Z29__device_stub__KernelTilesMulPiS_S_iii # -- Begin function _Z29__device_stub__KernelTilesMulPiS_S_iii
.p2align 4, 0x90
.type _Z29__device_stub__KernelTilesMulPiS_S_iii,@function
_Z29__device_stub__KernelTilesMulPiS_S_iii: # @_Z29__device_stub__KernelTilesMulPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14KernelTilesMulPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z29__device_stub__KernelTilesMulPiS_S_iii, .Lfunc_end0-_Z29__device_stub__KernelTilesMulPiS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14KernelTilesMulPiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14KernelTilesMulPiS_S_iii,@object # @_Z14KernelTilesMulPiS_S_iii
.section .rodata,"a",@progbits
.globl _Z14KernelTilesMulPiS_S_iii
.p2align 3, 0x0
_Z14KernelTilesMulPiS_S_iii:
.quad _Z29__device_stub__KernelTilesMulPiS_S_iii
.size _Z14KernelTilesMulPiS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14KernelTilesMulPiS_S_iii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__KernelTilesMulPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14KernelTilesMulPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14KernelTilesMulPiS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff067624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000e240000002100 */
/*0060*/ ISETP.GE.AND P1, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe40003f26270 */
/*0070*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0080*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0090*/ LEA R0, R9, R12, 0x4 ; /* 0x0000000c09007211 */
/* 0x001fc800078e20ff */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe40003f06270 */
/*00b0*/ LEA R3, R3, R2, 0x4 ; /* 0x0000000203037211 */
/* 0x002fc800078e20ff */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe20000706670 */
/*00d0*/ @!P1 BRA 0x5b0 ; /* 0x000004d000009947 */
/* 0x000fd80003800000 */
/*00e0*/ IADD3 R6, R6, 0xf, RZ ; /* 0x0000000f06067810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0100*/ SHF.L.U32 R15, R2.reuse, 0x6, RZ ; /* 0x00000006020f7819 */
/* 0x040fe200000006ff */
/*0110*/ IMAD R4, R3, c[0x0][0x17c], R12 ; /* 0x00005f0003047a24 */
/* 0x000fe200078e020c */
/*0120*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fe20000011406 */
/*0130*/ IMAD R16, R2, c[0x0][0x180], R12 ; /* 0x0000600002107a24 */
/* 0x000fe200078e020c */
/*0140*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*0160*/ LEA.HI R7, R7, R6, RZ, 0x4 ; /* 0x0000000607077211 */
/* 0x000fe200078f20ff */
/*0170*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0180*/ LEA R16, R9, R16, 0x4 ; /* 0x0000001009107211 */
/* 0x000fe200078e20ff */
/*0190*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0004 */
/*01a0*/ MOV R13, R5 ; /* 0x00000005000d7202 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD R19, R12.reuse, 0x4, R15 ; /* 0x000000040c137824 */
/* 0x040fe200078e020f */
/*01c0*/ LEA R18, R12, 0x400, 0x2 ; /* 0x000004000c127811 */
/* 0x000fc400078e10ff */
/*01d0*/ SHF.R.S32.HI R17, RZ, 0x4, R7 ; /* 0x00000004ff117819 */
/* 0x000fe40000011407 */
/*01e0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x17c], PT ; /* 0x00005f0002007a0c */
/* 0x000fe20003f26270 */
/*01f0*/ HFMA2.MMA R22, -RZ, RZ, 0, 0 ; /* 0x00000000ff167435 */
/* 0x000fe200000001ff */
/*0200*/ ISETP.GE.AND P2, PT, R12, c[0x0][0x17c], PT ; /* 0x00005f000c007a0c */
/* 0x000fe20003f46270 */
/*0210*/ IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c7224 */
/* 0x000fe200078e00ff */
/*0220*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x180], P1 ; /* 0x0000600000007a0c */
/* 0x000fe40000f26670 */
/*0230*/ ISETP.GE.OR P2, PT, R3, c[0x0][0x178], P2 ; /* 0x00005e0003007a0c */
/* 0x000fd60001746670 */
/*0240*/ @!P1 MOV R25, 0x4 ; /* 0x0000000400199802 */
/* 0x000fe40000000f00 */
/*0250*/ @!P2 MOV R4, R14 ; /* 0x0000000e0004a202 */
/* 0x000fe40000000f00 */
/*0260*/ @!P2 MOV R5, R13 ; /* 0x0000000d0005a202 */
/* 0x000fe20000000f00 */
/*0270*/ @!P1 IMAD.WIDE R24, R16, R25, c[0x0][0x168] ; /* 0x00005a0010189625 */
/* 0x000fc800078e0219 */
/*0280*/ @!P2 LDG.E R22, [R4.64] ; /* 0x000000060416a981 */
/* 0x000ea8000c1e1900 */
/*0290*/ @!P1 LDG.E R28, [R24.64] ; /* 0x00000006181c9981 */
/* 0x000ee2000c1e1900 */
/*02a0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*02b0*/ IADD3 R14, P2, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x000fe40007f5e0ff */
/*02c0*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe40007ffe0ff */
/*02d0*/ IADD3 R12, R12, 0x10, RZ ; /* 0x000000100c0c7810 */
/* 0x000fc40007ffe0ff */
/*02e0*/ ISETP.LE.AND P1, PT, R17, UR4, PT ; /* 0x0000000411007c0c */
/* 0x000fe4000bf23270 */
/*02f0*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*0300*/ STS [R19], R22 ; /* 0x0000001613007388 */
/* 0x004fe80000000800 */
/*0310*/ STS [R19+0x400], R28 ; /* 0x0004001c13007388 */
/* 0x008fe80000000800 */
/*0320*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0330*/ LDS R29, [R18] ; /* 0x00000000121d7984 */
/* 0x000fe80000000800 */
/*0340*/ LDS.128 R8, [R15] ; /* 0x000000000f087984 */
/* 0x000e280000000c00 */
/*0350*/ LDS R24, [R18+0x40] ; /* 0x0000400012187984 */
/* 0x000e680000000800 */
/*0360*/ LDS R27, [R18+0x80] ; /* 0x00008000121b7984 */
/* 0x000ea80000000800 */
/*0370*/ LDS R26, [R18+0xc0] ; /* 0x0000c000121a7984 */
/* 0x000ee80000000800 */
/*0380*/ LDS R23, [R18+0x100] ; /* 0x0001000012177984 */
/* 0x000fe80000000800 */
/*0390*/ LDS.128 R4, [R15+0x10] ; /* 0x000010000f047984 */
/* 0x000f280000000c00 */
/*03a0*/ LDS R20, [R18+0x140] ; /* 0x0001400012147984 */
/* 0x000f680000000800 */
/*03b0*/ LDS R25, [R18+0x180] ; /* 0x0001800012197984 */
/* 0x000f680000000800 */
/*03c0*/ LDS R22, [R18+0x1c0] ; /* 0x0001c00012167984 */
/* 0x000f620000000800 */
/*03d0*/ IMAD R8, R29, R8, R21 ; /* 0x000000081d087224 */
/* 0x001fc600078e0215 */
/*03e0*/ LDS R21, [R18+0x200] ; /* 0x0002000012157984 */
/* 0x000fe20000000800 */
/*03f0*/ IMAD R8, R24, R9, R8 ; /* 0x0000000918087224 */
/* 0x002fc600078e0208 */
/*0400*/ LDS R24, [R18+0x240] ; /* 0x0002400012187984 */
/* 0x000fe20000000800 */
/*0410*/ IMAD R8, R27, R10, R8 ; /* 0x0000000a1b087224 */
/* 0x004fc800078e0208 */
/*0420*/ IMAD R26, R26, R11, R8 ; /* 0x0000000b1a1a7224 */
/* 0x008fe400078e0208 */
/*0430*/ LDS.128 R8, [R15+0x20] ; /* 0x000020000f087984 */
/* 0x000e240000000c00 */
/*0440*/ IMAD R4, R23, R4, R26 ; /* 0x0000000417047224 */
/* 0x010fe400078e021a */
/*0450*/ LDS R23, [R18+0x280] ; /* 0x0002800012177984 */
/* 0x000e640000000800 */
/*0460*/ IMAD R4, R20, R5, R4 ; /* 0x0000000514047224 */
/* 0x020fe400078e0204 */
/*0470*/ LDS R20, [R18+0x2c0] ; /* 0x0002c00012147984 */
/* 0x000ea40000000800 */
/*0480*/ IMAD R4, R25, R6, R4 ; /* 0x0000000619047224 */
/* 0x000fc400078e0204 */
/*0490*/ LDS R25, [R18+0x300] ; /* 0x0003000012197984 */
/* 0x000fe40000000800 */
/*04a0*/ IMAD R26, R22, R7, R4 ; /* 0x00000007161a7224 */
/* 0x000fe400078e0204 */
/*04b0*/ LDS.128 R4, [R15+0x30] ; /* 0x000030000f047984 */
/* 0x000ee80000000c00 */
/*04c0*/ LDS R22, [R18+0x340] ; /* 0x0003400012167984 */
/* 0x000f220000000800 */
/*04d0*/ IMAD R26, R21, R8, R26 ; /* 0x00000008151a7224 */
/* 0x001fc600078e021a */
/*04e0*/ LDS R21, [R18+0x380] ; /* 0x0003800012157984 */
/* 0x000e220000000800 */
/*04f0*/ IMAD R9, R24, R9, R26 ; /* 0x0000000918097224 */
/* 0x000fc600078e021a */
/*0500*/ LDS R8, [R18+0x3c0] ; /* 0x0003c00012087984 */
/* 0x000f620000000800 */
/*0510*/ IMAD R9, R23, R10, R9 ; /* 0x0000000a17097224 */
/* 0x002fc800078e0209 */
/*0520*/ IMAD R9, R20, R11, R9 ; /* 0x0000000b14097224 */
/* 0x004fc800078e0209 */
/*0530*/ IMAD R4, R25, R4, R9 ; /* 0x0000000419047224 */
/* 0x008fc800078e0209 */
/*0540*/ IMAD R4, R22, R5, R4 ; /* 0x0000000516047224 */
/* 0x010fe400078e0204 */
/*0550*/ IMAD.MOV.U32 R5, RZ, RZ, 0x10 ; /* 0x00000010ff057424 */
/* 0x000fc800078e00ff */
/*0560*/ IMAD R16, R5, c[0x0][0x180], R16 ; /* 0x0000600005107a24 */
/* 0x000fe400078e0210 */
/*0570*/ IMAD R21, R21, R6, R4 ; /* 0x0000000615157224 */
/* 0x001fc800078e0204 */
/*0580*/ IMAD R21, R8, R7, R21 ; /* 0x0000000708157224 */
/* 0x020fe200078e0215 */
/*0590*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05a0*/ @!P1 BRA 0x1e0 ; /* 0xfffffc3000009947 */
/* 0x000fea000383ffff */
/*05b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*05c0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*05d0*/ IMAD R3, R3, c[0x0][0x180], R0 ; /* 0x0000600003037a24 */
/* 0x000fd200078e0200 */
/*05e0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*05f0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*0600*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0610*/ BRA 0x610; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14KernelTilesMulPiS_S_iii
.globl _Z14KernelTilesMulPiS_S_iii
.p2align 8
.type _Z14KernelTilesMulPiS_S_iii,@function
_Z14KernelTilesMulPiS_S_iii:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
v_bfe_u32 v6, v0, 10, 10
v_and_b32_e32 v1, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v5, s15, 4, v6
v_lshl_add_u32 v0, s14, 4, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v5
v_cmp_gt_i32_e64 s2, s3, v0
s_cmp_lt_i32 s9, 1
s_cbranch_scc1 .LBB0_13
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v1
v_lshlrev_b32_e32 v7, 6, v6
s_add_i32 s10, s9, 15
s_mov_b32 s11, 0
v_mov_b32_e32 v10, 0
v_add_nc_u32_e32 v8, 0x400, v2
v_mad_u64_u32 v[3:4], null, v5, s9, v[1:2]
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v9, v7, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v4, v8, v7
s_lshr_b32 s10, s10, 4
s_xor_b32 s12, vcc_lo, -1
s_max_i32 s10, s10, 1
s_xor_b32 s2, s2, -1
.LBB0_2:
s_lshl_b32 s13, s11, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v11, s13, v1
v_cmp_le_i32_e32 vcc_lo, s9, v11
s_or_b32 s14, vcc_lo, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s15, s14
s_xor_b32 s14, exec_lo, s15
s_cbranch_execz .LBB0_4
ds_store_b32 v9, v10
.LBB0_4:
s_and_not1_saveexec_b32 s14, s14
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v11, s13, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
global_load_b32 v11, v[11:12], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v11
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s14
v_add_nc_u32_e32 v11, s13, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s9, v11
s_or_b32 s13, vcc_lo, s2
s_and_saveexec_b32 s14, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s13, exec_lo, s14
s_cbranch_execz .LBB0_8
ds_store_b32 v4, v10
.LBB0_8:
s_and_not1_saveexec_b32 s13, s13
s_cbranch_execz .LBB0_10
v_mad_u64_u32 v[12:13], null, v11, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[11:12], 2, v[12:13]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v11, v[11:12], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v11
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s13
v_mov_b32_e32 v11, v8
s_mov_b32 s13, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_11:
v_add_nc_u32_e32 v12, s13, v7
s_add_i32 s13, s13, 4
ds_load_b32 v14, v11
ds_load_b32 v15, v12
s_cmp_eq_u32 s13, 64
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[12:13], null, v14, v15, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v2, v12 :: v_dual_add_nc_u32 v11, 64, v11
s_cbranch_scc0 .LBB0_11
s_add_i32 s11, s11, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s11, s10
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_14
.LBB0_13:
v_mov_b32_e32 v2, 0
.LBB0_14:
v_cmp_gt_i32_e32 vcc_lo, s8, v5
v_cmp_gt_i32_e64 s2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_16
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v5, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14KernelTilesMulPiS_S_iii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14KernelTilesMulPiS_S_iii, .Lfunc_end0-_Z14KernelTilesMulPiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14KernelTilesMulPiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14KernelTilesMulPiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b4cbc_00000000-6_KernelTilesMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z14KernelTilesMulPiS_S_iiiPiS_S_iii
.type _Z41__device_stub__Z14KernelTilesMulPiS_S_iiiPiS_S_iii, @function
_Z41__device_stub__Z14KernelTilesMulPiS_S_iiiPiS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14KernelTilesMulPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z14KernelTilesMulPiS_S_iiiPiS_S_iii, .-_Z41__device_stub__Z14KernelTilesMulPiS_S_iiiPiS_S_iii
.globl _Z14KernelTilesMulPiS_S_iii
.type _Z14KernelTilesMulPiS_S_iii, @function
_Z14KernelTilesMulPiS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14KernelTilesMulPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14KernelTilesMulPiS_S_iii, .-_Z14KernelTilesMulPiS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14KernelTilesMulPiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14KernelTilesMulPiS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "KernelTilesMul.hip"
.globl _Z29__device_stub__KernelTilesMulPiS_S_iii # -- Begin function _Z29__device_stub__KernelTilesMulPiS_S_iii
.p2align 4, 0x90
.type _Z29__device_stub__KernelTilesMulPiS_S_iii,@function
_Z29__device_stub__KernelTilesMulPiS_S_iii: # @_Z29__device_stub__KernelTilesMulPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14KernelTilesMulPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z29__device_stub__KernelTilesMulPiS_S_iii, .Lfunc_end0-_Z29__device_stub__KernelTilesMulPiS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14KernelTilesMulPiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14KernelTilesMulPiS_S_iii,@object # @_Z14KernelTilesMulPiS_S_iii
.section .rodata,"a",@progbits
.globl _Z14KernelTilesMulPiS_S_iii
.p2align 3, 0x0
_Z14KernelTilesMulPiS_S_iii:
.quad _Z29__device_stub__KernelTilesMulPiS_S_iii
.size _Z14KernelTilesMulPiS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14KernelTilesMulPiS_S_iii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__KernelTilesMulPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14KernelTilesMulPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
__global__ void add(int n, float *ax, float *ay, float *bx, float *by, float *sumx, float *sumy)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
sumx[i] = ax[i] + bx[i];
sumy[i] = ay[i] + by[i];
}
} | code for sm_80
Function : add
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R12, SR_CTAID.X ; /* 0x00000000000c7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R12, R12, c[0x0][0x0], R3 ; /* 0x000000000c0c7a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R12, c[0x0][0x160], PT ; /* 0x000058000c007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R12, R13, c[0x0][0x178] ; /* 0x00005e000c047625 */
/* 0x000fc800078e020d */
/*0090*/ IMAD.WIDE R2, R12.reuse, R13.reuse, c[0x0][0x168] ; /* 0x00005a000c027625 */
/* 0x0c0fe400078e020d */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R12, R13, c[0x0][0x188] ; /* 0x000062000c067625 */
/* 0x000fc800078e020d */
/*00d0*/ IMAD.WIDE R10, R12, R13, c[0x0][0x180] ; /* 0x000060000c0a7625 */
/* 0x000fc800078e020d */
/*00e0*/ IMAD.WIDE R8, R12, R13, c[0x0][0x170] ; /* 0x00005c000c087625 */
/* 0x000fc800078e020d */
/*00f0*/ FADD R15, R4, R3 ; /* 0x00000003040f7221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x000fe8000c101904 */
/*0110*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IMAD.WIDE R12, R12, R13, c[0x0][0x190] ; /* 0x000064000c0c7625 */
/* 0x000fc800078e020d */
/*0140*/ FADD R17, R10, R9 ; /* 0x000000090a117221 */
/* 0x004fca0000000000 */
/*0150*/ STG.E [R12.64], R17 ; /* 0x000000110c007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
__global__ void add(int n, float *ax, float *ay, float *bx, float *by, float *sumx, float *sumy)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
sumx[i] = ax[i] + bx[i];
sumy[i] = ay[i] + by[i];
}
} | .file "tmpxft_00104bc7_00000000-6_JCudaVectorAddKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z3addiPfS_S_S_S_S_iPfS_S_S_S_S_
.type _Z33__device_stub__Z3addiPfS_S_S_S_S_iPfS_S_S_S_S_, @function
_Z33__device_stub__Z3addiPfS_S_S_S_S_iPfS_S_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 60(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq add(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z3addiPfS_S_S_S_S_iPfS_S_S_S_S_, .-_Z33__device_stub__Z3addiPfS_S_S_S_S_iPfS_S_S_S_S_
.globl add
.type add, @function
add:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z33__device_stub__Z3addiPfS_S_S_S_S_iPfS_S_S_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size add, .-add
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "add"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq add(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
__global__ void add(int n, float *ax, float *ay, float *bx, float *by, float *sumx, float *sumy)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
sumx[i] = ax[i] + bx[i];
sumy[i] = ay[i] + by[i];
}
} | #include <hip/hip_runtime.h>
extern "C"
__global__ void add(int n, float *ax, float *ay, float *bx, float *by, float *sumx, float *sumy)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
sumx[i] = ax[i] + bx[i];
sumy[i] = ay[i] + by[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void add(int n, float *ax, float *ay, float *bx, float *by, float *sumx, float *sumy)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
sumx[i] = ax[i] + bx[i];
sumy[i] = ay[i] + by[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected add
.globl add
.p2align 8
.type add,@function
add:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[4:11], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b128 s[0:3], s[0:1], 0x28
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v1, vcc_lo
global_load_b32 v6, v[2:3], off
global_load_b32 v7, v[4:5], off
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v8, v6, v7
v_add_co_u32 v6, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v1, vcc_lo
global_store_b32 v[2:3], v8, off
global_load_b32 v2, v[4:5], off
global_load_b32 v3, v[6:7], off
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel add
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size add, .Lfunc_end0-add
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: add
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: add.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void add(int n, float *ax, float *ay, float *bx, float *by, float *sumx, float *sumy)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n)
{
sumx[i] = ax[i] + bx[i];
sumy[i] = ay[i] + by[i];
}
} | .text
.file "JCudaVectorAddKernel.hip"
.globl __device_stub__add # -- Begin function __device_stub__add
.p2align 4, 0x90
.type __device_stub__add,@function
__device_stub__add: # @__device_stub__add
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $add, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__add, .Lfunc_end0-__device_stub__add
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $add, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type add,@object # @add
.section .rodata,"a",@progbits
.globl add
.p2align 3, 0x0
add:
.quad __device_stub__add
.size add, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "add"
.size .L__unnamed_1, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__add
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym add
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : add
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R12, SR_CTAID.X ; /* 0x00000000000c7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R12, R12, c[0x0][0x0], R3 ; /* 0x000000000c0c7a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R12, c[0x0][0x160], PT ; /* 0x000058000c007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R12, R13, c[0x0][0x178] ; /* 0x00005e000c047625 */
/* 0x000fc800078e020d */
/*0090*/ IMAD.WIDE R2, R12.reuse, R13.reuse, c[0x0][0x168] ; /* 0x00005a000c027625 */
/* 0x0c0fe400078e020d */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R12, R13, c[0x0][0x188] ; /* 0x000062000c067625 */
/* 0x000fc800078e020d */
/*00d0*/ IMAD.WIDE R10, R12, R13, c[0x0][0x180] ; /* 0x000060000c0a7625 */
/* 0x000fc800078e020d */
/*00e0*/ IMAD.WIDE R8, R12, R13, c[0x0][0x170] ; /* 0x00005c000c087625 */
/* 0x000fc800078e020d */
/*00f0*/ FADD R15, R4, R3 ; /* 0x00000003040f7221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x000fe8000c101904 */
/*0110*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IMAD.WIDE R12, R12, R13, c[0x0][0x190] ; /* 0x000064000c0c7625 */
/* 0x000fc800078e020d */
/*0140*/ FADD R17, R10, R9 ; /* 0x000000090a117221 */
/* 0x004fca0000000000 */
/*0150*/ STG.E [R12.64], R17 ; /* 0x000000110c007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected add
.globl add
.p2align 8
.type add,@function
add:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[4:11], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b128 s[0:3], s[0:1], 0x28
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v1, vcc_lo
global_load_b32 v6, v[2:3], off
global_load_b32 v7, v[4:5], off
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v8, v6, v7
v_add_co_u32 v6, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v1, vcc_lo
global_store_b32 v[2:3], v8, off
global_load_b32 v2, v[4:5], off
global_load_b32 v3, v[6:7], off
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel add
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size add, .Lfunc_end0-add
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: add
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: add.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00104bc7_00000000-6_JCudaVectorAddKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z3addiPfS_S_S_S_S_iPfS_S_S_S_S_
.type _Z33__device_stub__Z3addiPfS_S_S_S_S_iPfS_S_S_S_S_, @function
_Z33__device_stub__Z3addiPfS_S_S_S_S_iPfS_S_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 60(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq add(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z3addiPfS_S_S_S_S_iPfS_S_S_S_S_, .-_Z33__device_stub__Z3addiPfS_S_S_S_S_iPfS_S_S_S_S_
.globl add
.type add, @function
add:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z33__device_stub__Z3addiPfS_S_S_S_S_iPfS_S_S_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size add, .-add
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "add"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq add(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "JCudaVectorAddKernel.hip"
.globl __device_stub__add # -- Begin function __device_stub__add
.p2align 4, 0x90
.type __device_stub__add,@function
__device_stub__add: # @__device_stub__add
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $add, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__add, .Lfunc_end0-__device_stub__add
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $add, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type add,@object # @add
.section .rodata,"a",@progbits
.globl add
.p2align 3, 0x0
add:
.quad __device_stub__add
.size add, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "add"
.size .L__unnamed_1, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__add
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym add
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Matrix_getRow_FloatPointer_naive(const float * A , int Acount, int Acols, const float * rowId , int empty_par1, int empty_par2, float * out0 , int out0count, int out0cols)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id<Acols)
{
out0[id] = A[id + (int)rowId[0]*Acols];
}
} | code for sm_80
Function : _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe20000000f00 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*00d0*/ F2I.TRUNC.NTZ R5, R2 ; /* 0x0000000200057305 */
/* 0x004e24000020f100 */
/*00e0*/ IMAD R5, R5, c[0x0][0x16c], R0 ; /* 0x00005b0005057a24 */
/* 0x001fce00078e0200 */
/*00f0*/ IMAD.WIDE R4, R5, R6, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fcc00078e0206 */
/*0100*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R6, c[0x0][0x180] ; /* 0x0000600000067625 */
/* 0x000fca00078e0206 */
/*0120*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x004fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Matrix_getRow_FloatPointer_naive(const float * A , int Acount, int Acols, const float * rowId , int empty_par1, int empty_par2, float * out0 , int out0count, int out0cols)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id<Acols)
{
out0[id] = A[id + (int)rowId[0]*Acols];
}
} | .file "tmpxft_0001f87a_00000000-6_Matrix_getRow_FloatPointer_naive.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z64__device_stub__Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfiiPKfiiS0_iiPfii
.type _Z64__device_stub__Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfiiPKfiiS0_iiPfii, @function
_Z64__device_stub__Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfiiPKfiiS0_iiPfii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z64__device_stub__Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfiiPKfiiS0_iiPfii, .-_Z64__device_stub__Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfiiPKfiiS0_iiPfii
.globl _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.type _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii, @function
_Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z64__device_stub__Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfiiPKfiiS0_iiPfii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii, .-_Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Matrix_getRow_FloatPointer_naive(const float * A , int Acount, int Acols, const float * rowId , int empty_par1, int empty_par2, float * out0 , int out0count, int out0cols)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id<Acols)
{
out0[id] = A[id + (int)rowId[0]*Acols];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Matrix_getRow_FloatPointer_naive(const float * A , int Acount, int Acols, const float * rowId , int empty_par1, int empty_par2, float * out0 , int out0count, int out0cols)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id<Acols)
{
out0[id] = A[id + (int)rowId[0]*Acols];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Matrix_getRow_FloatPointer_naive(const float * A , int Acount, int Acols, const float * rowId , int empty_par1, int empty_par2, float * out0 , int out0count, int out0cols)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id<Acols)
{
out0[id] = A[id + (int)rowId[0]*Acols];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.globl _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.p2align 8
.type _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii,@function
_Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x30
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s2, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_and_b32 s4, s4, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x20
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s3, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_cvt_i32_f32_e32 v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii, .Lfunc_end0-_Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Matrix_getRow_FloatPointer_naive(const float * A , int Acount, int Acols, const float * rowId , int empty_par1, int empty_par2, float * out0 , int out0count, int out0cols)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id<Acols)
{
out0[id] = A[id + (int)rowId[0]*Acols];
}
} | .text
.file "Matrix_getRow_FloatPointer_naive.hip"
.globl _Z47__device_stub__Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii # -- Begin function _Z47__device_stub__Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.p2align 4, 0x90
.type _Z47__device_stub__Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii,@function
_Z47__device_stub__Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii: # @_Z47__device_stub__Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z47__device_stub__Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii, .Lfunc_end0-_Z47__device_stub__Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii,@object # @_Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.section .rodata,"a",@progbits
.globl _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.p2align 3, 0x0
_Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii:
.quad _Z47__device_stub__Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.size _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii"
.size .L__unnamed_1, 51
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z47__device_stub__Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe20000000f00 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*00d0*/ F2I.TRUNC.NTZ R5, R2 ; /* 0x0000000200057305 */
/* 0x004e24000020f100 */
/*00e0*/ IMAD R5, R5, c[0x0][0x16c], R0 ; /* 0x00005b0005057a24 */
/* 0x001fce00078e0200 */
/*00f0*/ IMAD.WIDE R4, R5, R6, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fcc00078e0206 */
/*0100*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R6, c[0x0][0x180] ; /* 0x0000600000067625 */
/* 0x000fca00078e0206 */
/*0120*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x004fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.globl _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.p2align 8
.type _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii,@function
_Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x30
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s2, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_and_b32 s4, s4, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x20
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s3, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_cvt_i32_f32_e32 v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii, .Lfunc_end0-_Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001f87a_00000000-6_Matrix_getRow_FloatPointer_naive.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z64__device_stub__Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfiiPKfiiS0_iiPfii
.type _Z64__device_stub__Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfiiPKfiiS0_iiPfii, @function
_Z64__device_stub__Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfiiPKfiiS0_iiPfii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z64__device_stub__Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfiiPKfiiS0_iiPfii, .-_Z64__device_stub__Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfiiPKfiiS0_iiPfii
.globl _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.type _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii, @function
_Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z64__device_stub__Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfiiPKfiiS0_iiPfii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii, .-_Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Matrix_getRow_FloatPointer_naive.hip"
.globl _Z47__device_stub__Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii # -- Begin function _Z47__device_stub__Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.p2align 4, 0x90
.type _Z47__device_stub__Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii,@function
_Z47__device_stub__Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii: # @_Z47__device_stub__Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z47__device_stub__Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii, .Lfunc_end0-_Z47__device_stub__Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii,@object # @_Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.section .rodata,"a",@progbits
.globl _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.p2align 3, 0x0
_Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii:
.quad _Z47__device_stub__Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.size _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii"
.size .L__unnamed_1, 51
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z47__device_stub__Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z32Matrix_getRow_FloatPointer_naivePKfiiS0_iiPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // compute.cu
//
// driver and kernel call
#include <stdio.h>
#define THREADS_PER_BLOCK 128
// __global__ void compute_2d (int secondArrSize, float *arr[])
__global__ void compute_2d ( int firstArrSize, int secondArrSize, float **arr)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x == 0 && x < firstArrSize && y == 0 && y < firstArrSize)
{
printf("Hello. I'm a thread %d in block %d \n", threadIdx.x, blockIdx.x);
// printf("%lf \n", arr[x][y]);
}
// if (x <= arrSize) {
// if (x % 2 == timeStep % 2 && x <= timeStep)
// {
// if (timeStep > timeSteps && x <= (timeStep - timeSteps - arrSize))
// {
// } else
// {
// if (x == 0)
// {
// c_d[x] = (100.0 + c_d[x + 1]) / 2.0;
// } else if (x == arrSize - 1)
// {
// c_d[x] = (c_d[x - 1] + c_d[x]) / 2.0;
// } else
// {
// c_d[x] = (c_d[x - 1] + c_d[x + 1]) / 2.0;
// }
// }
// }
__syncthreads();
// }
}
extern "C" void compute2DArr (int firstArrSize, int secondArrSize, float *metalRod, int timeSteps)
{
int i = 0, j = 0;
int size=firstArrSize*secondArrSize*sizeof(float);
//allocate resources
float **cell=(float**)malloc(size * 2);
float **cell2=(float**)malloc(size * 2);
for (i = 0; i < firstArrSize; i ++)
{
cell[i] = (float*)malloc(size);
cell2[i] = (float*)malloc(size);
for (j = 0; j < secondArrSize; j ++)
{
cell[i][j] = 23.0;
}
}
size_t pitch;
float **d_cell;
cudaMallocPitch((void**) &d_cell, &pitch, secondArrSize * sizeof(float), firstArrSize);
cudaError_t tmp = cudaMemcpy2D(d_cell, pitch, cell, secondArrSize * sizeof(float), secondArrSize * sizeof(float), firstArrSize, cudaMemcpyHostToDevice);
if (cudaSuccess != tmp)
{
printf("\n copy to GPU \n");
printf(cudaGetErrorString(tmp));
}
dim3 dimBlock(8,8);
dim3 dimGrid(1,1);
compute_2d<<<dimGrid, dimBlock>>>( firstArrSize, secondArrSize, d_cell);
if (cudaSuccess != tmp)
{
printf("\n compute \n");
printf(cudaGetErrorString(tmp));
}
tmp = cudaMemcpy2D(cell2, secondArrSize * sizeof(float), d_cell, pitch, secondArrSize * sizeof(float), firstArrSize, cudaMemcpyDeviceToHost);
if (cudaSuccess != tmp)
{
printf("\n copy to CPU \n");
printf(cudaGetErrorString(tmp));
}
for (i = 0; i < firstArrSize; i++)
{
for (j = 0; j < secondArrSize; j ++)
{
printf("\n %lf ", cell2[i][j]);
}
}
// for (i = 0; i < (2*(timeSteps - 1)) + secondArrSize; i ++)
// {
// //compute_2d <<< ceil((float) secondArrSize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (c_d, secondArrSize, i, timeSteps);
// }
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess)
printf ("CUDA error: %s\n", cudaGetErrorString(err));
} | code for sm_80
Function : _Z10compute_2diiPPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0040*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fc60007f3e0ff */
/*0050*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e640000002500 */
/*0060*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe400008e06ff */
/*0070*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e620000002100 */
/*0080*/ IMAD R3, R3, c[0x0][0x4], R0 ; /* 0x0000010003037a24 */
/* 0x001fe400078e0200 */
/*0090*/ IMAD R0, R9, c[0x0][0x0], R8 ; /* 0x0000000009007a24 */
/* 0x002fca00078e0208 */
/*00a0*/ LOP3.LUT P0, RZ, R0, R3, RZ, 0xfc, !PT ; /* 0x0000000300ff7212 */
/* 0x000fc8000780fcff */
/*00b0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fc80000706670 */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x160], P0 ; /* 0x0000580003007a0c */
/* 0x000fda0000706670 */
/*00d0*/ @P0 BRA 0x1b0 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*00f0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0001e20000100a00 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0110*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0000620000000a00 */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fce00078e00ff */
/*0130*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x001fe40000000000 */
/*0140*/ MOV R11, 0x1b0 ; /* 0x000001b0000b7802 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R20, 0x130 ; /* 0x0000013000147802 */
/* 0x000fe40000000f00 */
/*0160*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0170*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fc40000000f00 */
/*0180*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0190*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*01a0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*01b0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // compute.cu
//
// driver and kernel call
#include <stdio.h>
#define THREADS_PER_BLOCK 128
// __global__ void compute_2d (int secondArrSize, float *arr[])
__global__ void compute_2d ( int firstArrSize, int secondArrSize, float **arr)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x == 0 && x < firstArrSize && y == 0 && y < firstArrSize)
{
printf("Hello. I'm a thread %d in block %d \n", threadIdx.x, blockIdx.x);
// printf("%lf \n", arr[x][y]);
}
// if (x <= arrSize) {
// if (x % 2 == timeStep % 2 && x <= timeStep)
// {
// if (timeStep > timeSteps && x <= (timeStep - timeSteps - arrSize))
// {
// } else
// {
// if (x == 0)
// {
// c_d[x] = (100.0 + c_d[x + 1]) / 2.0;
// } else if (x == arrSize - 1)
// {
// c_d[x] = (c_d[x - 1] + c_d[x]) / 2.0;
// } else
// {
// c_d[x] = (c_d[x - 1] + c_d[x + 1]) / 2.0;
// }
// }
// }
__syncthreads();
// }
}
extern "C" void compute2DArr (int firstArrSize, int secondArrSize, float *metalRod, int timeSteps)
{
int i = 0, j = 0;
int size=firstArrSize*secondArrSize*sizeof(float);
//allocate resources
float **cell=(float**)malloc(size * 2);
float **cell2=(float**)malloc(size * 2);
for (i = 0; i < firstArrSize; i ++)
{
cell[i] = (float*)malloc(size);
cell2[i] = (float*)malloc(size);
for (j = 0; j < secondArrSize; j ++)
{
cell[i][j] = 23.0;
}
}
size_t pitch;
float **d_cell;
cudaMallocPitch((void**) &d_cell, &pitch, secondArrSize * sizeof(float), firstArrSize);
cudaError_t tmp = cudaMemcpy2D(d_cell, pitch, cell, secondArrSize * sizeof(float), secondArrSize * sizeof(float), firstArrSize, cudaMemcpyHostToDevice);
if (cudaSuccess != tmp)
{
printf("\n copy to GPU \n");
printf(cudaGetErrorString(tmp));
}
dim3 dimBlock(8,8);
dim3 dimGrid(1,1);
compute_2d<<<dimGrid, dimBlock>>>( firstArrSize, secondArrSize, d_cell);
if (cudaSuccess != tmp)
{
printf("\n compute \n");
printf(cudaGetErrorString(tmp));
}
tmp = cudaMemcpy2D(cell2, secondArrSize * sizeof(float), d_cell, pitch, secondArrSize * sizeof(float), firstArrSize, cudaMemcpyDeviceToHost);
if (cudaSuccess != tmp)
{
printf("\n copy to CPU \n");
printf(cudaGetErrorString(tmp));
}
for (i = 0; i < firstArrSize; i++)
{
for (j = 0; j < secondArrSize; j ++)
{
printf("\n %lf ", cell2[i][j]);
}
}
// for (i = 0; i < (2*(timeSteps - 1)) + secondArrSize; i ++)
// {
// //compute_2d <<< ceil((float) secondArrSize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (c_d, secondArrSize, i, timeSteps);
// }
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess)
printf ("CUDA error: %s\n", cudaGetErrorString(err));
} | .file "tmpxft_0010f075_00000000-6_compute_2D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10compute_2diiPPfiiPPf
.type _Z33__device_stub__Z10compute_2diiPPfiiPPf, @function
_Z33__device_stub__Z10compute_2diiPPfiiPPf:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10compute_2diiPPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z10compute_2diiPPfiiPPf, .-_Z33__device_stub__Z10compute_2diiPPfiiPPf
.globl _Z10compute_2diiPPf
.type _Z10compute_2diiPPf, @function
_Z10compute_2diiPPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10compute_2diiPPfiiPPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10compute_2diiPPf, .-_Z10compute_2diiPPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\n copy to GPU \n"
.LC2:
.string "\n compute \n"
.LC3:
.string "\n copy to CPU \n"
.LC4:
.string "\n %lf "
.LC5:
.string "CUDA error: %s\n"
.text
.globl compute2DArr
.type compute2DArr, @function
compute2DArr:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, %ebp
movl %edi, 28(%rsp)
movl %esi, %r15d
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl %edi, %eax
imull %esi, %eax
leal 0(,%rax,4), %ecx
movl %ecx, 24(%rsp)
sall $3, %eax
movslq %eax, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rax, 40(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 32(%rsp)
testl %ebp, %ebp
jle .L12
movq %rax, %r14
movslq %ebp, %rax
leaq 0(%r13,%rax,8), %rax
movq %rax, 16(%rsp)
movslq %r15d, %rbp
salq $2, %rbp
movl .LC0(%rip), %r12d
.L15:
movslq 24(%rsp), %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %r13, %rbx
movq %rax, 0(%r13)
movq 8(%rsp), %rdi
call malloc@PLT
movq %rax, (%r14)
testl %r15d, %r15d
jle .L13
movl $0, %eax
.L14:
movq (%rbx), %rdx
movl %r12d, (%rdx,%rax)
addq $4, %rax
cmpq %rbp, %rax
jne .L14
.L13:
addq $8, %r13
addq $8, %r14
movq 16(%rsp), %rax
cmpq %rax, %r13
jne .L15
.L12:
movslq 28(%rsp), %rbx
movslq %r15d, %rbp
salq $2, %rbp
leaq 48(%rsp), %rsi
leaq 56(%rsp), %rdi
movq %rbx, %rcx
movq %rbp, %rdx
call cudaMallocPitch@PLT
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq $1
.cfi_def_cfa_offset 176
movq %rbx, %r9
movq %rbp, %r8
movq %rbp, %rcx
movq 56(%rsp), %rdx
movq 64(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy2D@PLT
movl %eax, %r12d
addq $16, %rsp
.cfi_def_cfa_offset 160
testl %eax, %eax
jne .L35
movl $8, 64(%rsp)
movl $8, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L24:
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq $2
.cfi_def_cfa_offset 176
movq %rbx, %r9
movq %rbp, %r8
movq 64(%rsp), %rcx
movq 72(%rsp), %rdx
movq %rbp, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy2D@PLT
movl %eax, %r12d
addq $16, %rsp
.cfi_def_cfa_offset 160
testl %eax, %eax
jne .L37
.L18:
cmpl $0, 28(%rsp)
jle .L19
movq 32(%rsp), %rax
movq %rax, %r12
leaq (%rax,%rbx,8), %r14
leaq .LC4(%rip), %r13
jmp .L20
.L35:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $8, 64(%rsp)
movl $8, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L26:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.L37:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.L21:
movq (%r12), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbx, %rbp
jne .L21
.L22:
addq $8, %r12
cmpq %r12, %r14
je .L19
.L20:
movl $0, %ebx
testl %r15d, %r15d
jg .L21
jmp .L22
.L19:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L38
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.L17:
movq 56(%rsp), %rdx
movl %r15d, %esi
movl 28(%rsp), %edi
call _Z33__device_stub__Z10compute_2diiPPfiiPPf
jmp .L26
.L36:
movq 56(%rsp), %rdx
movl %r15d, %esi
movl 28(%rsp), %edi
call _Z33__device_stub__Z10compute_2diiPPfiiPPf
jmp .L24
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size compute2DArr, .-compute2DArr
.section .rodata.str1.1
.LC6:
.string "_Z10compute_2diiPPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z10compute_2diiPPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1102577664
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // compute.cu
//
// driver and kernel call
#include <stdio.h>
#define THREADS_PER_BLOCK 128
// __global__ void compute_2d (int secondArrSize, float *arr[])
__global__ void compute_2d ( int firstArrSize, int secondArrSize, float **arr)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x == 0 && x < firstArrSize && y == 0 && y < firstArrSize)
{
printf("Hello. I'm a thread %d in block %d \n", threadIdx.x, blockIdx.x);
// printf("%lf \n", arr[x][y]);
}
// if (x <= arrSize) {
// if (x % 2 == timeStep % 2 && x <= timeStep)
// {
// if (timeStep > timeSteps && x <= (timeStep - timeSteps - arrSize))
// {
// } else
// {
// if (x == 0)
// {
// c_d[x] = (100.0 + c_d[x + 1]) / 2.0;
// } else if (x == arrSize - 1)
// {
// c_d[x] = (c_d[x - 1] + c_d[x]) / 2.0;
// } else
// {
// c_d[x] = (c_d[x - 1] + c_d[x + 1]) / 2.0;
// }
// }
// }
__syncthreads();
// }
}
extern "C" void compute2DArr (int firstArrSize, int secondArrSize, float *metalRod, int timeSteps)
{
int i = 0, j = 0;
int size=firstArrSize*secondArrSize*sizeof(float);
//allocate resources
float **cell=(float**)malloc(size * 2);
float **cell2=(float**)malloc(size * 2);
for (i = 0; i < firstArrSize; i ++)
{
cell[i] = (float*)malloc(size);
cell2[i] = (float*)malloc(size);
for (j = 0; j < secondArrSize; j ++)
{
cell[i][j] = 23.0;
}
}
size_t pitch;
float **d_cell;
cudaMallocPitch((void**) &d_cell, &pitch, secondArrSize * sizeof(float), firstArrSize);
cudaError_t tmp = cudaMemcpy2D(d_cell, pitch, cell, secondArrSize * sizeof(float), secondArrSize * sizeof(float), firstArrSize, cudaMemcpyHostToDevice);
if (cudaSuccess != tmp)
{
printf("\n copy to GPU \n");
printf(cudaGetErrorString(tmp));
}
dim3 dimBlock(8,8);
dim3 dimGrid(1,1);
compute_2d<<<dimGrid, dimBlock>>>( firstArrSize, secondArrSize, d_cell);
if (cudaSuccess != tmp)
{
printf("\n compute \n");
printf(cudaGetErrorString(tmp));
}
tmp = cudaMemcpy2D(cell2, secondArrSize * sizeof(float), d_cell, pitch, secondArrSize * sizeof(float), firstArrSize, cudaMemcpyDeviceToHost);
if (cudaSuccess != tmp)
{
printf("\n copy to CPU \n");
printf(cudaGetErrorString(tmp));
}
for (i = 0; i < firstArrSize; i++)
{
for (j = 0; j < secondArrSize; j ++)
{
printf("\n %lf ", cell2[i][j]);
}
}
// for (i = 0; i < (2*(timeSteps - 1)) + secondArrSize; i ++)
// {
// //compute_2d <<< ceil((float) secondArrSize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (c_d, secondArrSize, i, timeSteps);
// }
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess)
printf ("CUDA error: %s\n", cudaGetErrorString(err));
} | // compute.cu
//
// driver and kernel call
#include <hip/hip_runtime.h>
#include <stdio.h>
#define THREADS_PER_BLOCK 128
// __global__ void compute_2d (int secondArrSize, float *arr[])
__global__ void compute_2d ( int firstArrSize, int secondArrSize, float **arr)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x == 0 && x < firstArrSize && y == 0 && y < firstArrSize)
{
printf("Hello. I'm a thread %d in block %d \n", threadIdx.x, blockIdx.x);
// printf("%lf \n", arr[x][y]);
}
// if (x <= arrSize) {
// if (x % 2 == timeStep % 2 && x <= timeStep)
// {
// if (timeStep > timeSteps && x <= (timeStep - timeSteps - arrSize))
// {
// } else
// {
// if (x == 0)
// {
// c_d[x] = (100.0 + c_d[x + 1]) / 2.0;
// } else if (x == arrSize - 1)
// {
// c_d[x] = (c_d[x - 1] + c_d[x]) / 2.0;
// } else
// {
// c_d[x] = (c_d[x - 1] + c_d[x + 1]) / 2.0;
// }
// }
// }
__syncthreads();
// }
}
extern "C" void compute2DArr (int firstArrSize, int secondArrSize, float *metalRod, int timeSteps)
{
int i = 0, j = 0;
int size=firstArrSize*secondArrSize*sizeof(float);
//allocate resources
float **cell=(float**)malloc(size * 2);
float **cell2=(float**)malloc(size * 2);
for (i = 0; i < firstArrSize; i ++)
{
cell[i] = (float*)malloc(size);
cell2[i] = (float*)malloc(size);
for (j = 0; j < secondArrSize; j ++)
{
cell[i][j] = 23.0;
}
}
size_t pitch;
float **d_cell;
hipMallocPitch((void**) &d_cell, &pitch, secondArrSize * sizeof(float), firstArrSize);
hipError_t tmp = hipMemcpy2D(d_cell, pitch, cell, secondArrSize * sizeof(float), secondArrSize * sizeof(float), firstArrSize, hipMemcpyHostToDevice);
if (hipSuccess != tmp)
{
printf("\n copy to GPU \n");
printf(hipGetErrorString(tmp));
}
dim3 dimBlock(8,8);
dim3 dimGrid(1,1);
compute_2d<<<dimGrid, dimBlock>>>( firstArrSize, secondArrSize, d_cell);
if (hipSuccess != tmp)
{
printf("\n compute \n");
printf(hipGetErrorString(tmp));
}
tmp = hipMemcpy2D(cell2, secondArrSize * sizeof(float), d_cell, pitch, secondArrSize * sizeof(float), firstArrSize, hipMemcpyDeviceToHost);
if (hipSuccess != tmp)
{
printf("\n copy to CPU \n");
printf(hipGetErrorString(tmp));
}
for (i = 0; i < firstArrSize; i++)
{
for (j = 0; j < secondArrSize; j ++)
{
printf("\n %lf ", cell2[i][j]);
}
}
// for (i = 0; i < (2*(timeSteps - 1)) + secondArrSize; i ++)
// {
// //compute_2d <<< ceil((float) secondArrSize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (c_d, secondArrSize, i, timeSteps);
// }
hipError_t err = hipGetLastError();
if (err != hipSuccess)
printf ("CUDA error: %s\n", hipGetErrorString(err));
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // compute.cu
//
// driver and kernel call
#include <hip/hip_runtime.h>
#include <stdio.h>
#define THREADS_PER_BLOCK 128
// __global__ void compute_2d (int secondArrSize, float *arr[])
__global__ void compute_2d ( int firstArrSize, int secondArrSize, float **arr)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x == 0 && x < firstArrSize && y == 0 && y < firstArrSize)
{
printf("Hello. I'm a thread %d in block %d \n", threadIdx.x, blockIdx.x);
// printf("%lf \n", arr[x][y]);
}
// if (x <= arrSize) {
// if (x % 2 == timeStep % 2 && x <= timeStep)
// {
// if (timeStep > timeSteps && x <= (timeStep - timeSteps - arrSize))
// {
// } else
// {
// if (x == 0)
// {
// c_d[x] = (100.0 + c_d[x + 1]) / 2.0;
// } else if (x == arrSize - 1)
// {
// c_d[x] = (c_d[x - 1] + c_d[x]) / 2.0;
// } else
// {
// c_d[x] = (c_d[x - 1] + c_d[x + 1]) / 2.0;
// }
// }
// }
__syncthreads();
// }
}
extern "C" void compute2DArr (int firstArrSize, int secondArrSize, float *metalRod, int timeSteps)
{
int i = 0, j = 0;
int size=firstArrSize*secondArrSize*sizeof(float);
//allocate resources
float **cell=(float**)malloc(size * 2);
float **cell2=(float**)malloc(size * 2);
for (i = 0; i < firstArrSize; i ++)
{
cell[i] = (float*)malloc(size);
cell2[i] = (float*)malloc(size);
for (j = 0; j < secondArrSize; j ++)
{
cell[i][j] = 23.0;
}
}
size_t pitch;
float **d_cell;
hipMallocPitch((void**) &d_cell, &pitch, secondArrSize * sizeof(float), firstArrSize);
hipError_t tmp = hipMemcpy2D(d_cell, pitch, cell, secondArrSize * sizeof(float), secondArrSize * sizeof(float), firstArrSize, hipMemcpyHostToDevice);
if (hipSuccess != tmp)
{
printf("\n copy to GPU \n");
printf(hipGetErrorString(tmp));
}
dim3 dimBlock(8,8);
dim3 dimGrid(1,1);
compute_2d<<<dimGrid, dimBlock>>>( firstArrSize, secondArrSize, d_cell);
if (hipSuccess != tmp)
{
printf("\n compute \n");
printf(hipGetErrorString(tmp));
}
tmp = hipMemcpy2D(cell2, secondArrSize * sizeof(float), d_cell, pitch, secondArrSize * sizeof(float), firstArrSize, hipMemcpyDeviceToHost);
if (hipSuccess != tmp)
{
printf("\n copy to CPU \n");
printf(hipGetErrorString(tmp));
}
for (i = 0; i < firstArrSize; i++)
{
for (j = 0; j < secondArrSize; j ++)
{
printf("\n %lf ", cell2[i][j]);
}
}
// for (i = 0; i < (2*(timeSteps - 1)) + secondArrSize; i ++)
// {
// //compute_2d <<< ceil((float) secondArrSize/THREADS_PER_BLOCK), THREADS_PER_BLOCK >>> (c_d, secondArrSize, i, timeSteps);
// }
hipError_t err = hipGetLastError();
if (err != hipSuccess)
printf ("CUDA error: %s\n", hipGetErrorString(err));
} | .text
.file "compute_2D.hip"
.globl _Z25__device_stub__compute_2diiPPf # -- Begin function _Z25__device_stub__compute_2diiPPf
.p2align 4, 0x90
.type _Z25__device_stub__compute_2diiPPf,@function
_Z25__device_stub__compute_2diiPPf: # @_Z25__device_stub__compute_2diiPPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10compute_2diiPPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__compute_2diiPPf, .Lfunc_end0-_Z25__device_stub__compute_2diiPPf
.cfi_endproc
# -- End function
.globl compute2DArr # -- Begin function compute2DArr
.p2align 4, 0x90
.type compute2DArr,@function
compute2DArr: # @compute2DArr
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %r15d
movl %esi, %ebx
imull %edi, %ebx
leal (,%rbx,8), %eax
movslq %eax, %r14
movq %r14, %rdi
callq malloc
movq %rax, %r13
movq %r14, %rdi
callq malloc
movq %rax, %r14
movl %r15d, %eax
movq %rax, 56(%rsp) # 8-byte Spill
movl %ebp, 28(%rsp) # 4-byte Spill
movl %ebp, %ebp
movl %r15d, 44(%rsp) # 4-byte Spill
testl %r15d, %r15d
jle .LBB1_6
# %bb.1: # %.lr.ph70
shll $2, %ebx
movslq %ebx, %r15
xorl %ebx, %ebx
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rbx
cmpq 56(%rsp), %rbx # 8-byte Folded Reload
je .LBB1_6
.LBB1_2: # =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movq %r15, %rdi
callq malloc
movq %rax, %r12
movq %rax, (%r13,%rbx,8)
movq %r15, %rdi
callq malloc
movq %rax, (%r14,%rbx,8)
cmpl $0, 28(%rsp) # 4-byte Folded Reload
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB1_2 Depth=1
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $1102577664, (%r12,%rax,4) # imm = 0x41B80000
incq %rax
cmpq %rax, %rbp
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge71
movslq 28(%rsp), %r15 # 4-byte Folded Reload
shlq $2, %r15
movl 44(%rsp), %ebx # 4-byte Reload
movslq %ebx, %r12
leaq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
movq %r15, %rdx
movq %r12, %rcx
callq hipMallocPitch
movq 32(%rsp), %rdi
movq 64(%rsp), %rsi
movl $1, (%rsp)
movq %r13, %rdx
movq %r15, %rcx
movq %r15, %r8
movq %r12, %r9
callq hipMemcpy2D
movl %eax, %r13d
testl %eax, %eax
je .LBB1_8
# %bb.7:
movl $.Lstr, %edi
callq puts@PLT
movl %r13d, %edi
callq hipGetErrorString
movq %rax, %rdi
xorl %eax, %eax
callq printf
.LBB1_8:
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 32(%rsp), %rax
movl %ebx, 52(%rsp)
movl 28(%rsp), %ecx # 4-byte Reload
movl %ecx, 48(%rsp)
movq %rax, 120(%rsp)
leaq 52(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 120(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rax
movq 72(%rsp), %rdi
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
leaq 128(%rsp), %r9
movl $_Z10compute_2diiPPf, %edi
callq hipLaunchKernel
.LBB1_10:
testl %r13d, %r13d
je .LBB1_12
# %bb.11:
movl $.Lstr.1, %edi
callq puts@PLT
movl %r13d, %edi
callq hipGetErrorString
movq %rax, %rdi
xorl %eax, %eax
callq printf
.LBB1_12:
movq 32(%rsp), %rdx
movq 64(%rsp), %rcx
movl $2, (%rsp)
movq %r14, %rdi
movq %r15, %rsi
movq %r15, %r8
movq %r12, %r9
callq hipMemcpy2D
testl %eax, %eax
je .LBB1_14
# %bb.13:
movl %eax, %r15d
movl $.Lstr.2, %edi
callq puts@PLT
movl %r15d, %edi
callq hipGetErrorString
movq %rax, %rdi
xorl %eax, %eax
callq printf
.LBB1_14:
testl %ebx, %ebx
jle .LBB1_20
# %bb.15: # %.preheader.lr.ph
xorl %ebx, %ebx
jmp .LBB1_16
.p2align 4, 0x90
.LBB1_19: # %._crit_edge74
# in Loop: Header=BB1_16 Depth=1
incq %rbx
cmpq 56(%rsp), %rbx # 8-byte Folded Reload
je .LBB1_20
.LBB1_16: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_18 Depth 2
cmpl $0, 28(%rsp) # 4-byte Folded Reload
jle .LBB1_19
# %bb.17: # %.lr.ph73
# in Loop: Header=BB1_16 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_18: # Parent Loop BB1_16 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r14,%rbx,8), %rax
movss (%rax,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %rbp
jne .LBB1_18
jmp .LBB1_19
.LBB1_20: # %._crit_edge76
callq hipGetLastError
testl %eax, %eax
je .LBB1_22
# %bb.21:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_22:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size compute2DArr, .Lfunc_end1-compute2DArr
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10compute_2diiPPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10compute_2diiPPf,@object # @_Z10compute_2diiPPf
.section .rodata,"a",@progbits
.globl _Z10compute_2diiPPf
.p2align 3, 0x0
_Z10compute_2diiPPf:
.quad _Z25__device_stub__compute_2diiPPf
.size _Z10compute_2diiPPf, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "\n %lf "
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CUDA error: %s\n"
.size .L.str.4, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10compute_2diiPPf"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n copy to GPU "
.size .Lstr, 15
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n compute "
.size .Lstr.1, 11
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n copy to CPU "
.size .Lstr.2, 15
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__compute_2diiPPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10compute_2diiPPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010f075_00000000-6_compute_2D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10compute_2diiPPfiiPPf
.type _Z33__device_stub__Z10compute_2diiPPfiiPPf, @function
_Z33__device_stub__Z10compute_2diiPPfiiPPf:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10compute_2diiPPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z10compute_2diiPPfiiPPf, .-_Z33__device_stub__Z10compute_2diiPPfiiPPf
.globl _Z10compute_2diiPPf
.type _Z10compute_2diiPPf, @function
_Z10compute_2diiPPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10compute_2diiPPfiiPPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10compute_2diiPPf, .-_Z10compute_2diiPPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\n copy to GPU \n"
.LC2:
.string "\n compute \n"
.LC3:
.string "\n copy to CPU \n"
.LC4:
.string "\n %lf "
.LC5:
.string "CUDA error: %s\n"
.text
.globl compute2DArr
.type compute2DArr, @function
compute2DArr:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, %ebp
movl %edi, 28(%rsp)
movl %esi, %r15d
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl %edi, %eax
imull %esi, %eax
leal 0(,%rax,4), %ecx
movl %ecx, 24(%rsp)
sall $3, %eax
movslq %eax, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rax, 40(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 32(%rsp)
testl %ebp, %ebp
jle .L12
movq %rax, %r14
movslq %ebp, %rax
leaq 0(%r13,%rax,8), %rax
movq %rax, 16(%rsp)
movslq %r15d, %rbp
salq $2, %rbp
movl .LC0(%rip), %r12d
.L15:
movslq 24(%rsp), %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %r13, %rbx
movq %rax, 0(%r13)
movq 8(%rsp), %rdi
call malloc@PLT
movq %rax, (%r14)
testl %r15d, %r15d
jle .L13
movl $0, %eax
.L14:
movq (%rbx), %rdx
movl %r12d, (%rdx,%rax)
addq $4, %rax
cmpq %rbp, %rax
jne .L14
.L13:
addq $8, %r13
addq $8, %r14
movq 16(%rsp), %rax
cmpq %rax, %r13
jne .L15
.L12:
movslq 28(%rsp), %rbx
movslq %r15d, %rbp
salq $2, %rbp
leaq 48(%rsp), %rsi
leaq 56(%rsp), %rdi
movq %rbx, %rcx
movq %rbp, %rdx
call cudaMallocPitch@PLT
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq $1
.cfi_def_cfa_offset 176
movq %rbx, %r9
movq %rbp, %r8
movq %rbp, %rcx
movq 56(%rsp), %rdx
movq 64(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy2D@PLT
movl %eax, %r12d
addq $16, %rsp
.cfi_def_cfa_offset 160
testl %eax, %eax
jne .L35
movl $8, 64(%rsp)
movl $8, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L24:
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq $2
.cfi_def_cfa_offset 176
movq %rbx, %r9
movq %rbp, %r8
movq 64(%rsp), %rcx
movq 72(%rsp), %rdx
movq %rbp, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy2D@PLT
movl %eax, %r12d
addq $16, %rsp
.cfi_def_cfa_offset 160
testl %eax, %eax
jne .L37
.L18:
cmpl $0, 28(%rsp)
jle .L19
movq 32(%rsp), %rax
movq %rax, %r12
leaq (%rax,%rbx,8), %r14
leaq .LC4(%rip), %r13
jmp .L20
.L35:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $8, 64(%rsp)
movl $8, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L26:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.L37:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.L21:
movq (%r12), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbx, %rbp
jne .L21
.L22:
addq $8, %r12
cmpq %r12, %r14
je .L19
.L20:
movl $0, %ebx
testl %r15d, %r15d
jg .L21
jmp .L22
.L19:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L38
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.L17:
movq 56(%rsp), %rdx
movl %r15d, %esi
movl 28(%rsp), %edi
call _Z33__device_stub__Z10compute_2diiPPfiiPPf
jmp .L26
.L36:
movq 56(%rsp), %rdx
movl %r15d, %esi
movl 28(%rsp), %edi
call _Z33__device_stub__Z10compute_2diiPPfiiPPf
jmp .L24
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size compute2DArr, .-compute2DArr
.section .rodata.str1.1
.LC6:
.string "_Z10compute_2diiPPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z10compute_2diiPPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1102577664
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "compute_2D.hip"
.globl _Z25__device_stub__compute_2diiPPf # -- Begin function _Z25__device_stub__compute_2diiPPf
.p2align 4, 0x90
.type _Z25__device_stub__compute_2diiPPf,@function
_Z25__device_stub__compute_2diiPPf: # @_Z25__device_stub__compute_2diiPPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10compute_2diiPPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__compute_2diiPPf, .Lfunc_end0-_Z25__device_stub__compute_2diiPPf
.cfi_endproc
# -- End function
.globl compute2DArr # -- Begin function compute2DArr
.p2align 4, 0x90
.type compute2DArr,@function
compute2DArr: # @compute2DArr
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %r15d
movl %esi, %ebx
imull %edi, %ebx
leal (,%rbx,8), %eax
movslq %eax, %r14
movq %r14, %rdi
callq malloc
movq %rax, %r13
movq %r14, %rdi
callq malloc
movq %rax, %r14
movl %r15d, %eax
movq %rax, 56(%rsp) # 8-byte Spill
movl %ebp, 28(%rsp) # 4-byte Spill
movl %ebp, %ebp
movl %r15d, 44(%rsp) # 4-byte Spill
testl %r15d, %r15d
jle .LBB1_6
# %bb.1: # %.lr.ph70
shll $2, %ebx
movslq %ebx, %r15
xorl %ebx, %ebx
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rbx
cmpq 56(%rsp), %rbx # 8-byte Folded Reload
je .LBB1_6
.LBB1_2: # =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movq %r15, %rdi
callq malloc
movq %rax, %r12
movq %rax, (%r13,%rbx,8)
movq %r15, %rdi
callq malloc
movq %rax, (%r14,%rbx,8)
cmpl $0, 28(%rsp) # 4-byte Folded Reload
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB1_2 Depth=1
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $1102577664, (%r12,%rax,4) # imm = 0x41B80000
incq %rax
cmpq %rax, %rbp
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge71
movslq 28(%rsp), %r15 # 4-byte Folded Reload
shlq $2, %r15
movl 44(%rsp), %ebx # 4-byte Reload
movslq %ebx, %r12
leaq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
movq %r15, %rdx
movq %r12, %rcx
callq hipMallocPitch
movq 32(%rsp), %rdi
movq 64(%rsp), %rsi
movl $1, (%rsp)
movq %r13, %rdx
movq %r15, %rcx
movq %r15, %r8
movq %r12, %r9
callq hipMemcpy2D
movl %eax, %r13d
testl %eax, %eax
je .LBB1_8
# %bb.7:
movl $.Lstr, %edi
callq puts@PLT
movl %r13d, %edi
callq hipGetErrorString
movq %rax, %rdi
xorl %eax, %eax
callq printf
.LBB1_8:
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 32(%rsp), %rax
movl %ebx, 52(%rsp)
movl 28(%rsp), %ecx # 4-byte Reload
movl %ecx, 48(%rsp)
movq %rax, 120(%rsp)
leaq 52(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 120(%rsp), %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rax
movq 72(%rsp), %rdi
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
leaq 128(%rsp), %r9
movl $_Z10compute_2diiPPf, %edi
callq hipLaunchKernel
.LBB1_10:
testl %r13d, %r13d
je .LBB1_12
# %bb.11:
movl $.Lstr.1, %edi
callq puts@PLT
movl %r13d, %edi
callq hipGetErrorString
movq %rax, %rdi
xorl %eax, %eax
callq printf
.LBB1_12:
movq 32(%rsp), %rdx
movq 64(%rsp), %rcx
movl $2, (%rsp)
movq %r14, %rdi
movq %r15, %rsi
movq %r15, %r8
movq %r12, %r9
callq hipMemcpy2D
testl %eax, %eax
je .LBB1_14
# %bb.13:
movl %eax, %r15d
movl $.Lstr.2, %edi
callq puts@PLT
movl %r15d, %edi
callq hipGetErrorString
movq %rax, %rdi
xorl %eax, %eax
callq printf
.LBB1_14:
testl %ebx, %ebx
jle .LBB1_20
# %bb.15: # %.preheader.lr.ph
xorl %ebx, %ebx
jmp .LBB1_16
.p2align 4, 0x90
.LBB1_19: # %._crit_edge74
# in Loop: Header=BB1_16 Depth=1
incq %rbx
cmpq 56(%rsp), %rbx # 8-byte Folded Reload
je .LBB1_20
.LBB1_16: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_18 Depth 2
cmpl $0, 28(%rsp) # 4-byte Folded Reload
jle .LBB1_19
# %bb.17: # %.lr.ph73
# in Loop: Header=BB1_16 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_18: # Parent Loop BB1_16 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r14,%rbx,8), %rax
movss (%rax,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %rbp
jne .LBB1_18
jmp .LBB1_19
.LBB1_20: # %._crit_edge76
callq hipGetLastError
testl %eax, %eax
je .LBB1_22
# %bb.21:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_22:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size compute2DArr, .Lfunc_end1-compute2DArr
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10compute_2diiPPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10compute_2diiPPf,@object # @_Z10compute_2diiPPf
.section .rodata,"a",@progbits
.globl _Z10compute_2diiPPf
.p2align 3, 0x0
_Z10compute_2diiPPf:
.quad _Z25__device_stub__compute_2diiPPf
.size _Z10compute_2diiPPf, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "\n %lf "
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CUDA error: %s\n"
.size .L.str.4, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10compute_2diiPPf"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n copy to GPU "
.size .Lstr, 15
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n compute "
.size .Lstr.1, 11
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n copy to CPU "
.size .Lstr.2, 15
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__compute_2diiPPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10compute_2diiPPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ void softmax_device(float *input, int n, float temp, int stride, float *output)
{
int i;
float sum = 0;
float largest = -INFINITY;
for(i = 0; i < n; ++i){
int val = input[i*stride];
largest = (val>largest) ? val : largest;
}
for(i = 0; i < n; ++i){
float e = expf(input[i*stride]/temp - largest/temp);
sum += e;
output[i*stride] = e;
}
for(i = 0; i < n; ++i){
output[i*stride] /= sum;
}
}
__device__ void softmax_device(int n, float *input, float temp, float *output)
{
int i;
float sum = 0;
float largest = -INFINITY;
for(i = 0; i < n; ++i){
int val = input[i];
largest = (val>largest) ? val : largest;
}
for(i = 0; i < n; ++i){
float e = exp(input[i]/temp - largest/temp);
sum += e;
output[i] = e;
}
for(i = 0; i < n; ++i){
output[i] /= sum;
}
}
__global__ void softmax_kernel(float *input, int n, int batch, int batch_offset, int groups, int group_offset, int stride, float temp, float *output)
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if (id >= batch*groups) return;
int b = id / groups;
int g = id % groups;
softmax_device(input + b*batch_offset + g*group_offset, n, temp, stride, output + b*batch_offset + g*group_offset);
} | .file "tmpxft_0009d388_00000000-6_softmax_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14softmax_devicePfifiS_
.type _Z14softmax_devicePfifiS_, @function
_Z14softmax_devicePfifiS_:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z14softmax_devicePfifiS_, .-_Z14softmax_devicePfifiS_
.globl _Z14softmax_deviceiPffS_
.type _Z14softmax_deviceiPffS_, @function
_Z14softmax_deviceiPffS_:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z14softmax_deviceiPffS_, .-_Z14softmax_deviceiPffS_
.globl _Z43__device_stub__Z14softmax_kernelPfiiiiiifS_PfiiiiiifS_
.type _Z43__device_stub__Z14softmax_kernelPfiiiiiifS_PfiiiiiifS_, @function
_Z43__device_stub__Z14softmax_kernelPfiiiiiifS_PfiiiiiifS_:
.LFB2053:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movl %r8d, 24(%rsp)
movl %r9d, 20(%rsp)
movss %xmm0, 16(%rsp)
movq 216(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14softmax_kernelPfiiiiiifS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z43__device_stub__Z14softmax_kernelPfiiiiiifS_PfiiiiiifS_, .-_Z43__device_stub__Z14softmax_kernelPfiiiiiifS_PfiiiiiifS_
.globl _Z14softmax_kernelPfiiiiiifS_
.type _Z14softmax_kernelPfiiiiiifS_, @function
_Z14softmax_kernelPfiiiiiifS_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z14softmax_kernelPfiiiiiifS_PfiiiiiifS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z14softmax_kernelPfiiiiiifS_, .-_Z14softmax_kernelPfiiiiiifS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14softmax_kernelPfiiiiiifS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14softmax_kernelPfiiiiiifS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ void softmax_device(float *input, int n, float temp, int stride, float *output)
{
int i;
float sum = 0;
float largest = -INFINITY;
for(i = 0; i < n; ++i){
int val = input[i*stride];
largest = (val>largest) ? val : largest;
}
for(i = 0; i < n; ++i){
float e = expf(input[i*stride]/temp - largest/temp);
sum += e;
output[i*stride] = e;
}
for(i = 0; i < n; ++i){
output[i*stride] /= sum;
}
}
__device__ void softmax_device(int n, float *input, float temp, float *output)
{
int i;
float sum = 0;
float largest = -INFINITY;
for(i = 0; i < n; ++i){
int val = input[i];
largest = (val>largest) ? val : largest;
}
for(i = 0; i < n; ++i){
float e = exp(input[i]/temp - largest/temp);
sum += e;
output[i] = e;
}
for(i = 0; i < n; ++i){
output[i] /= sum;
}
}
__global__ void softmax_kernel(float *input, int n, int batch, int batch_offset, int groups, int group_offset, int stride, float temp, float *output)
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if (id >= batch*groups) return;
int b = id / groups;
int g = id % groups;
softmax_device(input + b*batch_offset + g*group_offset, n, temp, stride, output + b*batch_offset + g*group_offset);
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void softmax_device(float *input, int n, float temp, int stride, float *output)
{
int i;
float sum = 0;
float largest = -INFINITY;
for(i = 0; i < n; ++i){
int val = input[i*stride];
largest = (val>largest) ? val : largest;
}
for(i = 0; i < n; ++i){
float e = expf(input[i*stride]/temp - largest/temp);
sum += e;
output[i*stride] = e;
}
for(i = 0; i < n; ++i){
output[i*stride] /= sum;
}
}
__device__ void softmax_device(int n, float *input, float temp, float *output)
{
int i;
float sum = 0;
float largest = -INFINITY;
for(i = 0; i < n; ++i){
int val = input[i];
largest = (val>largest) ? val : largest;
}
for(i = 0; i < n; ++i){
float e = exp(input[i]/temp - largest/temp);
sum += e;
output[i] = e;
}
for(i = 0; i < n; ++i){
output[i] /= sum;
}
}
__global__ void softmax_kernel(float *input, int n, int batch, int batch_offset, int groups, int group_offset, int stride, float temp, float *output)
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if (id >= batch*groups) return;
int b = id / groups;
int g = id % groups;
softmax_device(input + b*batch_offset + g*group_offset, n, temp, stride, output + b*batch_offset + g*group_offset);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void softmax_device(float *input, int n, float temp, int stride, float *output)
{
int i;
float sum = 0;
float largest = -INFINITY;
for(i = 0; i < n; ++i){
int val = input[i*stride];
largest = (val>largest) ? val : largest;
}
for(i = 0; i < n; ++i){
float e = expf(input[i*stride]/temp - largest/temp);
sum += e;
output[i*stride] = e;
}
for(i = 0; i < n; ++i){
output[i*stride] /= sum;
}
}
__device__ void softmax_device(int n, float *input, float temp, float *output)
{
int i;
float sum = 0;
float largest = -INFINITY;
for(i = 0; i < n; ++i){
int val = input[i];
largest = (val>largest) ? val : largest;
}
for(i = 0; i < n; ++i){
float e = exp(input[i]/temp - largest/temp);
sum += e;
output[i] = e;
}
for(i = 0; i < n; ++i){
output[i] /= sum;
}
}
__global__ void softmax_kernel(float *input, int n, int batch, int batch_offset, int groups, int group_offset, int stride, float temp, float *output)
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if (id >= batch*groups) return;
int b = id / groups;
int g = id % groups;
softmax_device(input + b*batch_offset + g*group_offset, n, temp, stride, output + b*batch_offset + g*group_offset);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14softmax_kernelPfiiiiiifS_
.globl _Z14softmax_kernelPfiiiiiifS_
.p2align 8
.type _Z14softmax_kernelPfiiiiiifS_,@function
_Z14softmax_kernelPfiiiiiifS_:
s_clause 0x3
s_load_b32 s2, s[0:1], 0x30
s_load_b32 s3, s[0:1], 0x3c
s_load_b32 s5, s[0:1], 0xc
s_load_b32 s4, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mul_i32 s2, s4, s5
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_12
s_ashr_i32 s2, s4, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s3, s4, s2
s_load_b32 s10, s[0:1], 0x8
s_xor_b32 s3, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s5, 0, s3
v_xor_b32_e32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s2, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s5, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v0, s3
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v5, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_clause 0x1
s_load_b32 s6, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x18
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v3
v_mul_lo_u32 v2, v0, s4
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, v0, s6
s_cmp_gt_i32 s10, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v1, v2
v_mul_lo_u32 v2, v1, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_cselect_b32 s2, -1, 0
s_cmp_lt_i32 s10, 1
v_ashrrev_i32_e32 v3, 31, v2
s_cbranch_scc1 .LBB0_4
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[2:3]
s_ashr_i32 s7, s3, 31
s_mov_b32 s6, s3
s_mov_b32 s8, s10
s_lshl_b64 s[6:7], s[6:7], 2
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v4, v6
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v7, vcc_lo
v_mov_b32_e32 v6, 0xff800000
.LBB0_3:
global_load_b32 v7, v[4:5], off
v_add_co_u32 v4, vcc_lo, v4, s6
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s8, 0
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v7, v7
v_cvt_f32_i32_e32 v7, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_f32_e32 vcc_lo, v6, v7
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0xff800000
.LBB0_5:
s_load_b64 s[6:7], s[0:1], 0x28
v_cndmask_b32_e64 v5, 0, 1, s2
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_8
s_load_b32 s1, s[0:1], 0x20
v_lshlrev_b64 v[9:10], 2, v[0:1]
s_ashr_i32 s9, s3, 31
s_mov_b32 s8, s3
s_mov_b32 s2, s10
s_lshl_b64 s[8:9], s[8:9], 2
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v4, null, s1, s1, v6
v_div_scale_f32 v12, vcc_lo, v6, s1, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v11, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v4, v11, 1.0
v_fmac_f32_e32 v11, v7, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v13, v12, v11
v_fma_f32 v7, -v4, v13, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v13, v7, v11
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_fma_f32 v4, -v4, v13, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fmas_f32 v4, v4, v11, v13
v_add_co_u32 v7, vcc_lo, v7, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, v8, v10, vcc_lo
v_div_fixup_f32 v6, v4, s1, v6
v_mov_b32_e32 v4, 0
.LBB0_7:
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v8, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s2, 0
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v10, null, s1, s1, v9
v_div_scale_f32 v13, vcc_lo, v9, s1, v9
v_rcp_f32_e32 v11, v10
s_waitcnt_depctr 0xfff
v_fma_f32 v12, -v10, v11, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, v12, v11
v_mul_f32_e32 v12, v13, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v14, -v10, v12, v13
v_fmac_f32_e32 v12, v14, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, -v10, v12, v13
v_div_fmas_f32 v10, v10, v11, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v9, v10, s1, v9
v_sub_f32_e32 v11, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v9, 0x3fb8aa3b, v11
v_cmp_ngt_f32_e64 s0, 0xc2ce8ed0, v11
v_fma_f32 v10, v11, 0x3fb8aa3b, -v9
v_rndne_f32_e32 v12, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v10, 0x32a5705f, v11 :: v_dual_sub_f32 v9, v9, v12
v_add_f32_e32 v9, v9, v10
v_cvt_i32_f32_e32 v10, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_exp_f32_e32 v9, v9
s_waitcnt_depctr 0xfff
v_ldexp_f32 v10, v9, v10
v_add_co_u32 v9, vcc_lo, s6, v7
v_cndmask_b32_e64 v12, 0, v10, s0
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v8, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v11, 0x7f800000, v12, vcc_lo
v_add_co_u32 v7, vcc_lo, v7, s8
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
v_add_f32_e32 v4, v4, v11
global_store_b32 v[9:10], v11, off
s_cbranch_scc0 .LBB0_7
s_branch .LBB0_9
.LBB0_8:
v_mov_b32_e32 v4, 0
.LBB0_9:
s_delay_alu instid0(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, 1, v5
s_cbranch_vccnz .LBB0_12
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_ashr_i32 s1, s3, 31
s_mov_b32 s0, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_lshl_b64 s[0:1], s[0:1], 2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, v0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
.p2align 6
.LBB0_11:
global_load_b32 v2, v[0:1], off
s_add_i32 s10, s10, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s10, 0
s_waitcnt vmcnt(0)
v_div_scale_f32 v3, null, v4, v4, v2
v_div_scale_f32 v7, vcc_lo, v2, v4, v2
v_rcp_f32_e32 v5, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v3, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_mul_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v3, v6, v7
v_fmac_f32_e32 v6, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v6, v7
v_div_fmas_f32 v3, v3, v5, v6
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v2, v3, v4, v2
global_store_b32 v[0:1], v2, off
v_add_co_u32 v0, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_cbranch_scc1 .LBB0_11
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14softmax_kernelPfiiiiiifS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14softmax_kernelPfiiiiiifS_, .Lfunc_end0-_Z14softmax_kernelPfiiiiiifS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14softmax_kernelPfiiiiiifS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14softmax_kernelPfiiiiiifS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void softmax_device(float *input, int n, float temp, int stride, float *output)
{
int i;
float sum = 0;
float largest = -INFINITY;
for(i = 0; i < n; ++i){
int val = input[i*stride];
largest = (val>largest) ? val : largest;
}
for(i = 0; i < n; ++i){
float e = expf(input[i*stride]/temp - largest/temp);
sum += e;
output[i*stride] = e;
}
for(i = 0; i < n; ++i){
output[i*stride] /= sum;
}
}
__device__ void softmax_device(int n, float *input, float temp, float *output)
{
int i;
float sum = 0;
float largest = -INFINITY;
for(i = 0; i < n; ++i){
int val = input[i];
largest = (val>largest) ? val : largest;
}
for(i = 0; i < n; ++i){
float e = exp(input[i]/temp - largest/temp);
sum += e;
output[i] = e;
}
for(i = 0; i < n; ++i){
output[i] /= sum;
}
}
__global__ void softmax_kernel(float *input, int n, int batch, int batch_offset, int groups, int group_offset, int stride, float temp, float *output)
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if (id >= batch*groups) return;
int b = id / groups;
int g = id % groups;
softmax_device(input + b*batch_offset + g*group_offset, n, temp, stride, output + b*batch_offset + g*group_offset);
} | .text
.file "softmax_kernel.hip"
.globl _Z29__device_stub__softmax_kernelPfiiiiiifS_ # -- Begin function _Z29__device_stub__softmax_kernelPfiiiiiifS_
.p2align 4, 0x90
.type _Z29__device_stub__softmax_kernelPfiiiiiifS_,@function
_Z29__device_stub__softmax_kernelPfiiiiiifS_: # @_Z29__device_stub__softmax_kernelPfiiiiiifS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movss %xmm0, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 168(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14softmax_kernelPfiiiiiifS_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z29__device_stub__softmax_kernelPfiiiiiifS_, .Lfunc_end0-_Z29__device_stub__softmax_kernelPfiiiiiifS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14softmax_kernelPfiiiiiifS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14softmax_kernelPfiiiiiifS_,@object # @_Z14softmax_kernelPfiiiiiifS_
.section .rodata,"a",@progbits
.globl _Z14softmax_kernelPfiiiiiifS_
.p2align 3, 0x0
_Z14softmax_kernelPfiiiiiifS_:
.quad _Z29__device_stub__softmax_kernelPfiiiiiifS_
.size _Z14softmax_kernelPfiiiiiifS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14softmax_kernelPfiiiiiifS_"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__softmax_kernelPfiiiiiifS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14softmax_kernelPfiiiiiifS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009d388_00000000-6_softmax_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14softmax_devicePfifiS_
.type _Z14softmax_devicePfifiS_, @function
_Z14softmax_devicePfifiS_:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z14softmax_devicePfifiS_, .-_Z14softmax_devicePfifiS_
.globl _Z14softmax_deviceiPffS_
.type _Z14softmax_deviceiPffS_, @function
_Z14softmax_deviceiPffS_:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z14softmax_deviceiPffS_, .-_Z14softmax_deviceiPffS_
.globl _Z43__device_stub__Z14softmax_kernelPfiiiiiifS_PfiiiiiifS_
.type _Z43__device_stub__Z14softmax_kernelPfiiiiiifS_PfiiiiiifS_, @function
_Z43__device_stub__Z14softmax_kernelPfiiiiiifS_PfiiiiiifS_:
.LFB2053:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movl %r8d, 24(%rsp)
movl %r9d, 20(%rsp)
movss %xmm0, 16(%rsp)
movq 216(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14softmax_kernelPfiiiiiifS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z43__device_stub__Z14softmax_kernelPfiiiiiifS_PfiiiiiifS_, .-_Z43__device_stub__Z14softmax_kernelPfiiiiiifS_PfiiiiiifS_
.globl _Z14softmax_kernelPfiiiiiifS_
.type _Z14softmax_kernelPfiiiiiifS_, @function
_Z14softmax_kernelPfiiiiiifS_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z14softmax_kernelPfiiiiiifS_PfiiiiiifS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z14softmax_kernelPfiiiiiifS_, .-_Z14softmax_kernelPfiiiiiifS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14softmax_kernelPfiiiiiifS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14softmax_kernelPfiiiiiifS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "softmax_kernel.hip"
.globl _Z29__device_stub__softmax_kernelPfiiiiiifS_ # -- Begin function _Z29__device_stub__softmax_kernelPfiiiiiifS_
.p2align 4, 0x90
.type _Z29__device_stub__softmax_kernelPfiiiiiifS_,@function
_Z29__device_stub__softmax_kernelPfiiiiiifS_: # @_Z29__device_stub__softmax_kernelPfiiiiiifS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movss %xmm0, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 168(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14softmax_kernelPfiiiiiifS_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z29__device_stub__softmax_kernelPfiiiiiifS_, .Lfunc_end0-_Z29__device_stub__softmax_kernelPfiiiiiifS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14softmax_kernelPfiiiiiifS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14softmax_kernelPfiiiiiifS_,@object # @_Z14softmax_kernelPfiiiiiifS_
.section .rodata,"a",@progbits
.globl _Z14softmax_kernelPfiiiiiifS_
.p2align 3, 0x0
_Z14softmax_kernelPfiiiiiifS_:
.quad _Z29__device_stub__softmax_kernelPfiiiiiifS_
.size _Z14softmax_kernelPfiiiiiifS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14softmax_kernelPfiiiiiifS_"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__softmax_kernelPfiiiiiifS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14softmax_kernelPfiiiiiifS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void fill(float * w, float val, int size) {
const int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
if (tid < size) w[tid] = val;
} | code for sm_80
Function : _Z4fillPffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x16c], PT ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, c[0x0][0x168] ; /* 0x00005a0000057a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void fill(float * w, float val, int size) {
const int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
if (tid < size) w[tid] = val;
} | .file "tmpxft_00013e51_00000000-6_fill.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z4fillPffiPffi
.type _Z25__device_stub__Z4fillPffiPffi, @function
_Z25__device_stub__Z4fillPffiPffi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4fillPffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z4fillPffiPffi, .-_Z25__device_stub__Z4fillPffiPffi
.globl _Z4fillPffi
.type _Z4fillPffi, @function
_Z4fillPffi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4fillPffiPffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4fillPffi, .-_Z4fillPffi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4fillPffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4fillPffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void fill(float * w, float val, int size) {
const int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
if (tid < size) w[tid] = val;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fill(float * w, float val, int size) {
const int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
if (tid < size) w[tid] = val;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fill(float * w, float val, int size) {
const int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
if (tid < size) w[tid] = val;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4fillPffi
.globl _Z4fillPffi
.p2align 8
.type _Z4fillPffi,@function
_Z4fillPffi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4fillPffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4fillPffi, .Lfunc_end0-_Z4fillPffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4fillPffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4fillPffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fill(float * w, float val, int size) {
const int tid = (blockIdx.x * blockDim.x) + threadIdx.x;
if (tid < size) w[tid] = val;
} | .text
.file "fill.hip"
.globl _Z19__device_stub__fillPffi # -- Begin function _Z19__device_stub__fillPffi
.p2align 4, 0x90
.type _Z19__device_stub__fillPffi,@function
_Z19__device_stub__fillPffi: # @_Z19__device_stub__fillPffi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4fillPffi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__fillPffi, .Lfunc_end0-_Z19__device_stub__fillPffi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4fillPffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4fillPffi,@object # @_Z4fillPffi
.section .rodata,"a",@progbits
.globl _Z4fillPffi
.p2align 3, 0x0
_Z4fillPffi:
.quad _Z19__device_stub__fillPffi
.size _Z4fillPffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4fillPffi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__fillPffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4fillPffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4fillPffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x16c], PT ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, c[0x0][0x168] ; /* 0x00005a0000057a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4fillPffi
.globl _Z4fillPffi
.p2align 8
.type _Z4fillPffi,@function
_Z4fillPffi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4fillPffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4fillPffi, .Lfunc_end0-_Z4fillPffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4fillPffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4fillPffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00013e51_00000000-6_fill.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z4fillPffiPffi
.type _Z25__device_stub__Z4fillPffiPffi, @function
_Z25__device_stub__Z4fillPffiPffi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4fillPffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z4fillPffiPffi, .-_Z25__device_stub__Z4fillPffiPffi
.globl _Z4fillPffi
.type _Z4fillPffi, @function
_Z4fillPffi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4fillPffiPffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4fillPffi, .-_Z4fillPffi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4fillPffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4fillPffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "fill.hip"
.globl _Z19__device_stub__fillPffi # -- Begin function _Z19__device_stub__fillPffi
.p2align 4, 0x90
.type _Z19__device_stub__fillPffi,@function
_Z19__device_stub__fillPffi: # @_Z19__device_stub__fillPffi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4fillPffi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__fillPffi, .Lfunc_end0-_Z19__device_stub__fillPffi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4fillPffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4fillPffi,@object # @_Z4fillPffi
.section .rodata,"a",@progbits
.globl _Z4fillPffi
.p2align 3, 0x0
_Z4fillPffi:
.quad _Z19__device_stub__fillPffi
.size _Z4fillPffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4fillPffi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__fillPffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4fillPffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
using namespace std;
#define ITERATIONS 40000
enum pixel_position {INSIDE_MASK, BOUNDRY, OUTSIDE};
__global__ void merge_without_blend_kernel(float *srcimg, float *targetimg, float *outimg, int *boundary_array,int source_nchannel, int source_width, int source_height){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
for(int channel = 0; channel < source_nchannel; channel++){
int id = x + y*source_width + channel * source_width * source_height;
if(boundary_array[id] == INSIDE_MASK){
outimg[id] = targetimg[id];
}
else{
outimg[id] = srcimg[id];
}
}
} | code for sm_80
Function : _Z26merge_without_blend_kernelPfS_S_Piiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R4, R0.reuse, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x040fe20007ffe0ff */
/*0050*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f26070 */
/*0090*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*00a0*/ HFMA2.MMA R20, -RZ, RZ, 0, 0 ; /* 0x00000000ff147435 */
/* 0x000fe200000001ff */
/*00b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*00c0*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000ea80000002500 */
/*00d0*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000ee80000002100 */
/*00e0*/ @!P1 BRA 0x4c0 ; /* 0x000003d000009947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R7, R3, c[0x0][0x188], RZ ; /* 0x0000620003077a10 */
/* 0x002fe20007ffe0ff */
/*0100*/ IMAD R6, R2, c[0x0][0x4], R3 ; /* 0x0000010002067a24 */
/* 0x001fe200078e0203 */
/*0110*/ IADD3 R11, R0, -c[0x0][0x180], RZ ; /* 0x80006000000b7a10 */
/* 0x000fe20007ffe0ff */
/*0120*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff0d7624 */
/* 0x000fc400078e00ff */
/*0130*/ IMAD R9, R4, c[0x0][0x0], R5 ; /* 0x0000000004097a24 */
/* 0x00cfe400078e0205 */
/*0140*/ IMAD R8, R2, c[0x0][0x4], R7 ; /* 0x0000010002087a24 */
/* 0x000fe200078e0207 */
/*0150*/ LEA R10, R13.reuse, R6, 0x1 ; /* 0x000000060d0a7211 */
/* 0x040fe200078e08ff */
/*0160*/ IMAD R12, R13, 0x3, R6 ; /* 0x000000030d0c7824 */
/* 0x000fe400078e0206 */
/*0170*/ IMAD R7, R8, c[0x0][0x184], R9.reuse ; /* 0x0000610008077a24 */
/* 0x100fe400078e0209 */
/*0180*/ IMAD R6, R6, c[0x0][0x184], R9.reuse ; /* 0x0000610006067a24 */
/* 0x100fe400078e0209 */
/*0190*/ IMAD R8, R10, c[0x0][0x184], R9 ; /* 0x000061000a087a24 */
/* 0x000fc400078e0209 */
/*01a0*/ IMAD R9, R12, c[0x0][0x184], R9 ; /* 0x000061000c097a24 */
/* 0x000fe400078e0209 */
/*01b0*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD R10, R13, c[0x0][0x184], RZ ; /* 0x000061000d0a7a24 */
/* 0x000fe400078e02ff */
/*01d0*/ MOV R15, 0x4 ; /* 0x00000004000f7802 */
/* 0x001fca0000000f00 */
/*01e0*/ IMAD.WIDE R16, R6, R15, c[0x0][0x178] ; /* 0x00005e0006107625 */
/* 0x000fca00078e020f */
/*01f0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IMAD.MOV.U32 R22, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff167624 */
/* 0x000fe200078e00ff */
/*0210*/ MOV R21, c[0x0][0x16c] ; /* 0x00005b0000157a02 */
/* 0x000fe40000000f00 */
/*0220*/ ISETP.NE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x004fc80003f25270 */
/*0230*/ SEL R12, R22, c[0x0][0x160], !P1 ; /* 0x00005800160c7a07 */
/* 0x000fe40004800000 */
/*0240*/ SEL R13, R21, c[0x0][0x164], !P1 ; /* 0x00005900150d7a07 */
/* 0x000fca0004800000 */
/*0250*/ IMAD.WIDE R18, R6, 0x4, R12 ; /* 0x0000000406127825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R23, [R18.64] ; /* 0x0000000412177981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R14, R6, R15, c[0x0][0x170] ; /* 0x00005c00060e7625 */
/* 0x000fc800078e020f */
/*0280*/ IMAD.WIDE R12, R10, 0x4, R16 ; /* 0x000000040a0c7825 */
/* 0x000fe200078e0210 */
/*0290*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0041e8000c101904 */
/*02a0*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000ea4000c1e1900 */
/*02b0*/ ISETP.NE.AND P1, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x004fc80003f25270 */
/*02c0*/ SEL R16, R22, c[0x0][0x160], !P1 ; /* 0x0000580016107a07 */
/* 0x000fe40004800000 */
/*02d0*/ SEL R17, R21, c[0x0][0x164], !P1 ; /* 0x0000590015117a07 */
/* 0x000fca0004800000 */
/*02e0*/ IMAD.WIDE R24, R7, 0x4, R16 ; /* 0x0000000407187825 */
/* 0x000fca00078e0210 */
/*02f0*/ LDG.E R27, [R24.64] ; /* 0x00000004181b7981 */
/* 0x000ea2000c1e1900 */
/*0300*/ IMAD.WIDE R16, R10, 0x4, R14 ; /* 0x000000040a107825 */
/* 0x000fc800078e020e */
/*0310*/ IMAD.WIDE R18, R10, 0x4, R12 ; /* 0x000000040a127825 */
/* 0x000fe200078e020c */
/*0320*/ STG.E [R16.64], R27 ; /* 0x0000001b10007986 */
/* 0x0043e8000c101904 */
/*0330*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x000ea4000c1e1900 */
/*0340*/ ISETP.NE.AND P1, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x004fc80003f25270 */
/*0350*/ SEL R12, R22, c[0x0][0x160], !P1 ; /* 0x00005800160c7a07 */
/* 0x000fe40004800000 */
/*0360*/ SEL R13, R21, c[0x0][0x164], !P1 ; /* 0x00005900150d7a07 */
/* 0x000fca0004800000 */
/*0370*/ IMAD.WIDE R12, R8, 0x4, R12 ; /* 0x00000004080c7825 */
/* 0x000fcc00078e020c */
/*0380*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea2000c1e1900 */
/*0390*/ IMAD.WIDE R14, R10, 0x4, R16 ; /* 0x000000040a0e7825 */
/* 0x001fc800078e0210 */
/*03a0*/ IMAD.WIDE R24, R10, 0x4, R18 ; /* 0x000000040a187825 */
/* 0x000fe200078e0212 */
/*03b0*/ STG.E [R14.64], R13 ; /* 0x0000000d0e007986 */
/* 0x0041ea000c101904 */
/*03c0*/ LDG.E R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000ea2000c1e1900 */
/*03d0*/ IADD3 R20, R20, 0x4, RZ ; /* 0x0000000414147810 */
/* 0x000fe40007ffe0ff */
/*03e0*/ ISETP.NE.AND P1, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x004fc80003f25270 */
/*03f0*/ SEL R22, R22, c[0x0][0x160], !P1 ; /* 0x0000580016167a07 */
/* 0x000fe40004800000 */
/*0400*/ SEL R23, R21, c[0x0][0x164], !P1 ; /* 0x0000590015177a07 */
/* 0x000fca0004800000 */
/*0410*/ IMAD.WIDE R22, R9, 0x4, R22 ; /* 0x0000000409167825 */
/* 0x000fcc00078e0216 */
/*0420*/ LDG.E R23, [R22.64] ; /* 0x0000000416177981 */
/* 0x000ea2000c1e1900 */
/*0430*/ IMAD.IADD R12, R11, 0x1, R20 ; /* 0x000000010b0c7824 */
/* 0x000fe200078e0214 */
/*0440*/ LEA R6, R10.reuse, R6, 0x2 ; /* 0x000000060a067211 */
/* 0x040fe200078e10ff */
/*0450*/ IMAD.WIDE R16, R10.reuse, 0x4, R14 ; /* 0x000000040a107825 */
/* 0x042fe200078e020e */
/*0460*/ LEA R7, R10, R7, 0x2 ; /* 0x000000070a077211 */
/* 0x000fe400078e10ff */
/*0470*/ ISETP.NE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f25270 */
/*0480*/ IMAD R8, R10.reuse, 0x4, R8 ; /* 0x000000040a087824 */
/* 0x040fe200078e0208 */
/*0490*/ LEA R9, R10, R9, 0x2 ; /* 0x000000090a097211 */
/* 0x000fe200078e10ff */
/*04a0*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0041f4000c101904 */
/*04b0*/ @P1 BRA 0x1d0 ; /* 0xfffffd1000001947 */
/* 0x000fea000383ffff */
/*04c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*04d0*/ IMAD R3, R2, c[0x0][0x4], R3 ; /* 0x0000010002037a24 */
/* 0x003fe400078e0203 */
/*04e0*/ IMAD R5, R4, c[0x0][0x0], R5 ; /* 0x0000000004057a24 */
/* 0x00cfc400078e0205 */
/*04f0*/ IMAD R20, R20, c[0x0][0x188], R3 ; /* 0x0000620014147a24 */
/* 0x000fc800078e0203 */
/*0500*/ IMAD R9, R20, c[0x0][0x184], R5 ; /* 0x0000610014097a24 */
/* 0x000fe400078e0205 */
/*0510*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x001fd400000001ff */
/*0520*/ IMAD.WIDE R2, R9, R6, c[0x0][0x178] ; /* 0x00005e0009027625 */
/* 0x000fcc00078e0206 */
/*0530*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0540*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0550*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe40000000f00 */
/*0560*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fc80003f05270 */
/*0570*/ SEL R4, R4, c[0x0][0x160], !P0 ; /* 0x0000580004047a07 */
/* 0x000fe40004000000 */
/*0580*/ SEL R5, R5, c[0x0][0x164], !P0 ; /* 0x0000590005057a07 */
/* 0x000fca0004000000 */
/*0590*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fcc00078e0204 */
/*05a0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*05c0*/ IMAD.WIDE R6, R9, R6, c[0x0][0x170] ; /* 0x00005c0009067625 */
/* 0x000fe200078e0206 */
/*05d0*/ MOV R2, c[0x0][0x188] ; /* 0x0000620000027a02 */
/* 0x000fe40000000f00 */
/*05e0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f05270 */
/*05f0*/ IMAD R9, R2, c[0x0][0x184], R9 ; /* 0x0000610002097a24 */
/* 0x000fe200078e0209 */
/*0600*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x0041f2000c101904 */
/*0610*/ @P0 BRA 0x510 ; /* 0xfffffef000000947 */
/* 0x000fea000383ffff */
/*0620*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0630*/ BRA 0x630; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
using namespace std;
#define ITERATIONS 40000
enum pixel_position {INSIDE_MASK, BOUNDRY, OUTSIDE};
__global__ void merge_without_blend_kernel(float *srcimg, float *targetimg, float *outimg, int *boundary_array,int source_nchannel, int source_width, int source_height){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
for(int channel = 0; channel < source_nchannel; channel++){
int id = x + y*source_width + channel * source_width * source_height;
if(boundary_array[id] == INSIDE_MASK){
outimg[id] = targetimg[id];
}
else{
outimg[id] = srcimg[id];
}
}
} | .file "tmpxft_000d0fd9_00000000-6_merge_without_blend_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z55__device_stub__Z26merge_without_blend_kernelPfS_S_PiiiiPfS_S_Piiii
.type _Z55__device_stub__Z26merge_without_blend_kernelPfS_S_PiiiiPfS_S_Piiii, @function
_Z55__device_stub__Z26merge_without_blend_kernelPfS_S_PiiiiPfS_S_Piiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z26merge_without_blend_kernelPfS_S_Piiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z55__device_stub__Z26merge_without_blend_kernelPfS_S_PiiiiPfS_S_Piiii, .-_Z55__device_stub__Z26merge_without_blend_kernelPfS_S_PiiiiPfS_S_Piiii
.globl _Z26merge_without_blend_kernelPfS_S_Piiii
.type _Z26merge_without_blend_kernelPfS_S_Piiii, @function
_Z26merge_without_blend_kernelPfS_S_Piiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z55__device_stub__Z26merge_without_blend_kernelPfS_S_PiiiiPfS_S_Piiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26merge_without_blend_kernelPfS_S_Piiii, .-_Z26merge_without_blend_kernelPfS_S_Piiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26merge_without_blend_kernelPfS_S_Piiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26merge_without_blend_kernelPfS_S_Piiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
using namespace std;
#define ITERATIONS 40000
enum pixel_position {INSIDE_MASK, BOUNDRY, OUTSIDE};
__global__ void merge_without_blend_kernel(float *srcimg, float *targetimg, float *outimg, int *boundary_array,int source_nchannel, int source_width, int source_height){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
for(int channel = 0; channel < source_nchannel; channel++){
int id = x + y*source_width + channel * source_width * source_height;
if(boundary_array[id] == INSIDE_MASK){
outimg[id] = targetimg[id];
}
else{
outimg[id] = srcimg[id];
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
#define ITERATIONS 40000
enum pixel_position {INSIDE_MASK, BOUNDRY, OUTSIDE};
__global__ void merge_without_blend_kernel(float *srcimg, float *targetimg, float *outimg, int *boundary_array,int source_nchannel, int source_width, int source_height){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
for(int channel = 0; channel < source_nchannel; channel++){
int id = x + y*source_width + channel * source_width * source_height;
if(boundary_array[id] == INSIDE_MASK){
outimg[id] = targetimg[id];
}
else{
outimg[id] = srcimg[id];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
#define ITERATIONS 40000
enum pixel_position {INSIDE_MASK, BOUNDRY, OUTSIDE};
__global__ void merge_without_blend_kernel(float *srcimg, float *targetimg, float *outimg, int *boundary_array,int source_nchannel, int source_width, int source_height){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
for(int channel = 0; channel < source_nchannel; channel++){
int id = x + y*source_width + channel * source_width * source_height;
if(boundary_array[id] == INSIDE_MASK){
outimg[id] = targetimg[id];
}
else{
outimg[id] = srcimg[id];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26merge_without_blend_kernelPfS_S_Piiii
.globl _Z26merge_without_blend_kernelPfS_S_Piiii
.p2align 8
.type _Z26merge_without_blend_kernelPfS_S_Piiii,@function
_Z26merge_without_blend_kernelPfS_S_Piiii:
s_load_b32 s8, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b32 s9, s[0:1], 0x3c
s_load_b64 s[10:11], s[0:1], 0x24
v_bfe_u32 v1, v0, 10, 10
s_load_b256 s[0:7], s[0:1], 0x0
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s12, s9, 16
s_and_b32 s9, s9, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s12, v[1:2]
v_mov_b32_e32 v3, s2
s_mul_i32 s14, s14, s9
s_mul_i32 s2, s11, s10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v1, s10, v2
v_mov_b32_e32 v2, s3
v_add3_u32 v0, v0, v1, s14
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s8, s8, -1
s_cmp_eq_u32 s8, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_nc_u32_e32 v0, s2, v0
v_add_co_u32 v6, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
global_load_b32 v1, v[6:7], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v1
v_cndmask_b32_e32 v6, s0, v3, vcc_lo
v_cndmask_b32_e32 v1, s1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v6, v4
v_add_co_ci_u32_e32 v7, vcc_lo, v1, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v1, v[6:7], off
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v1, off
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26merge_without_blend_kernelPfS_S_Piiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26merge_without_blend_kernelPfS_S_Piiii, .Lfunc_end0-_Z26merge_without_blend_kernelPfS_S_Piiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26merge_without_blend_kernelPfS_S_Piiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26merge_without_blend_kernelPfS_S_Piiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
#define ITERATIONS 40000
enum pixel_position {INSIDE_MASK, BOUNDRY, OUTSIDE};
__global__ void merge_without_blend_kernel(float *srcimg, float *targetimg, float *outimg, int *boundary_array,int source_nchannel, int source_width, int source_height){
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
for(int channel = 0; channel < source_nchannel; channel++){
int id = x + y*source_width + channel * source_width * source_height;
if(boundary_array[id] == INSIDE_MASK){
outimg[id] = targetimg[id];
}
else{
outimg[id] = srcimg[id];
}
}
} | .text
.file "merge_without_blend_kernel.hip"
.globl _Z41__device_stub__merge_without_blend_kernelPfS_S_Piiii # -- Begin function _Z41__device_stub__merge_without_blend_kernelPfS_S_Piiii
.p2align 4, 0x90
.type _Z41__device_stub__merge_without_blend_kernelPfS_S_Piiii,@function
_Z41__device_stub__merge_without_blend_kernelPfS_S_Piiii: # @_Z41__device_stub__merge_without_blend_kernelPfS_S_Piiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z26merge_without_blend_kernelPfS_S_Piiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z41__device_stub__merge_without_blend_kernelPfS_S_Piiii, .Lfunc_end0-_Z41__device_stub__merge_without_blend_kernelPfS_S_Piiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26merge_without_blend_kernelPfS_S_Piiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26merge_without_blend_kernelPfS_S_Piiii,@object # @_Z26merge_without_blend_kernelPfS_S_Piiii
.section .rodata,"a",@progbits
.globl _Z26merge_without_blend_kernelPfS_S_Piiii
.p2align 3, 0x0
_Z26merge_without_blend_kernelPfS_S_Piiii:
.quad _Z41__device_stub__merge_without_blend_kernelPfS_S_Piiii
.size _Z26merge_without_blend_kernelPfS_S_Piiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26merge_without_blend_kernelPfS_S_Piiii"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__merge_without_blend_kernelPfS_S_Piiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26merge_without_blend_kernelPfS_S_Piiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26merge_without_blend_kernelPfS_S_Piiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R4, R0.reuse, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x040fe20007ffe0ff */
/*0050*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f26070 */
/*0090*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*00a0*/ HFMA2.MMA R20, -RZ, RZ, 0, 0 ; /* 0x00000000ff147435 */
/* 0x000fe200000001ff */
/*00b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*00c0*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000ea80000002500 */
/*00d0*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000ee80000002100 */
/*00e0*/ @!P1 BRA 0x4c0 ; /* 0x000003d000009947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R7, R3, c[0x0][0x188], RZ ; /* 0x0000620003077a10 */
/* 0x002fe20007ffe0ff */
/*0100*/ IMAD R6, R2, c[0x0][0x4], R3 ; /* 0x0000010002067a24 */
/* 0x001fe200078e0203 */
/*0110*/ IADD3 R11, R0, -c[0x0][0x180], RZ ; /* 0x80006000000b7a10 */
/* 0x000fe20007ffe0ff */
/*0120*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff0d7624 */
/* 0x000fc400078e00ff */
/*0130*/ IMAD R9, R4, c[0x0][0x0], R5 ; /* 0x0000000004097a24 */
/* 0x00cfe400078e0205 */
/*0140*/ IMAD R8, R2, c[0x0][0x4], R7 ; /* 0x0000010002087a24 */
/* 0x000fe200078e0207 */
/*0150*/ LEA R10, R13.reuse, R6, 0x1 ; /* 0x000000060d0a7211 */
/* 0x040fe200078e08ff */
/*0160*/ IMAD R12, R13, 0x3, R6 ; /* 0x000000030d0c7824 */
/* 0x000fe400078e0206 */
/*0170*/ IMAD R7, R8, c[0x0][0x184], R9.reuse ; /* 0x0000610008077a24 */
/* 0x100fe400078e0209 */
/*0180*/ IMAD R6, R6, c[0x0][0x184], R9.reuse ; /* 0x0000610006067a24 */
/* 0x100fe400078e0209 */
/*0190*/ IMAD R8, R10, c[0x0][0x184], R9 ; /* 0x000061000a087a24 */
/* 0x000fc400078e0209 */
/*01a0*/ IMAD R9, R12, c[0x0][0x184], R9 ; /* 0x000061000c097a24 */
/* 0x000fe400078e0209 */
/*01b0*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD R10, R13, c[0x0][0x184], RZ ; /* 0x000061000d0a7a24 */
/* 0x000fe400078e02ff */
/*01d0*/ MOV R15, 0x4 ; /* 0x00000004000f7802 */
/* 0x001fca0000000f00 */
/*01e0*/ IMAD.WIDE R16, R6, R15, c[0x0][0x178] ; /* 0x00005e0006107625 */
/* 0x000fca00078e020f */
/*01f0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IMAD.MOV.U32 R22, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff167624 */
/* 0x000fe200078e00ff */
/*0210*/ MOV R21, c[0x0][0x16c] ; /* 0x00005b0000157a02 */
/* 0x000fe40000000f00 */
/*0220*/ ISETP.NE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x004fc80003f25270 */
/*0230*/ SEL R12, R22, c[0x0][0x160], !P1 ; /* 0x00005800160c7a07 */
/* 0x000fe40004800000 */
/*0240*/ SEL R13, R21, c[0x0][0x164], !P1 ; /* 0x00005900150d7a07 */
/* 0x000fca0004800000 */
/*0250*/ IMAD.WIDE R18, R6, 0x4, R12 ; /* 0x0000000406127825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R23, [R18.64] ; /* 0x0000000412177981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R14, R6, R15, c[0x0][0x170] ; /* 0x00005c00060e7625 */
/* 0x000fc800078e020f */
/*0280*/ IMAD.WIDE R12, R10, 0x4, R16 ; /* 0x000000040a0c7825 */
/* 0x000fe200078e0210 */
/*0290*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0041e8000c101904 */
/*02a0*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000ea4000c1e1900 */
/*02b0*/ ISETP.NE.AND P1, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x004fc80003f25270 */
/*02c0*/ SEL R16, R22, c[0x0][0x160], !P1 ; /* 0x0000580016107a07 */
/* 0x000fe40004800000 */
/*02d0*/ SEL R17, R21, c[0x0][0x164], !P1 ; /* 0x0000590015117a07 */
/* 0x000fca0004800000 */
/*02e0*/ IMAD.WIDE R24, R7, 0x4, R16 ; /* 0x0000000407187825 */
/* 0x000fca00078e0210 */
/*02f0*/ LDG.E R27, [R24.64] ; /* 0x00000004181b7981 */
/* 0x000ea2000c1e1900 */
/*0300*/ IMAD.WIDE R16, R10, 0x4, R14 ; /* 0x000000040a107825 */
/* 0x000fc800078e020e */
/*0310*/ IMAD.WIDE R18, R10, 0x4, R12 ; /* 0x000000040a127825 */
/* 0x000fe200078e020c */
/*0320*/ STG.E [R16.64], R27 ; /* 0x0000001b10007986 */
/* 0x0043e8000c101904 */
/*0330*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x000ea4000c1e1900 */
/*0340*/ ISETP.NE.AND P1, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x004fc80003f25270 */
/*0350*/ SEL R12, R22, c[0x0][0x160], !P1 ; /* 0x00005800160c7a07 */
/* 0x000fe40004800000 */
/*0360*/ SEL R13, R21, c[0x0][0x164], !P1 ; /* 0x00005900150d7a07 */
/* 0x000fca0004800000 */
/*0370*/ IMAD.WIDE R12, R8, 0x4, R12 ; /* 0x00000004080c7825 */
/* 0x000fcc00078e020c */
/*0380*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea2000c1e1900 */
/*0390*/ IMAD.WIDE R14, R10, 0x4, R16 ; /* 0x000000040a0e7825 */
/* 0x001fc800078e0210 */
/*03a0*/ IMAD.WIDE R24, R10, 0x4, R18 ; /* 0x000000040a187825 */
/* 0x000fe200078e0212 */
/*03b0*/ STG.E [R14.64], R13 ; /* 0x0000000d0e007986 */
/* 0x0041ea000c101904 */
/*03c0*/ LDG.E R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000ea2000c1e1900 */
/*03d0*/ IADD3 R20, R20, 0x4, RZ ; /* 0x0000000414147810 */
/* 0x000fe40007ffe0ff */
/*03e0*/ ISETP.NE.AND P1, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x004fc80003f25270 */
/*03f0*/ SEL R22, R22, c[0x0][0x160], !P1 ; /* 0x0000580016167a07 */
/* 0x000fe40004800000 */
/*0400*/ SEL R23, R21, c[0x0][0x164], !P1 ; /* 0x0000590015177a07 */
/* 0x000fca0004800000 */
/*0410*/ IMAD.WIDE R22, R9, 0x4, R22 ; /* 0x0000000409167825 */
/* 0x000fcc00078e0216 */
/*0420*/ LDG.E R23, [R22.64] ; /* 0x0000000416177981 */
/* 0x000ea2000c1e1900 */
/*0430*/ IMAD.IADD R12, R11, 0x1, R20 ; /* 0x000000010b0c7824 */
/* 0x000fe200078e0214 */
/*0440*/ LEA R6, R10.reuse, R6, 0x2 ; /* 0x000000060a067211 */
/* 0x040fe200078e10ff */
/*0450*/ IMAD.WIDE R16, R10.reuse, 0x4, R14 ; /* 0x000000040a107825 */
/* 0x042fe200078e020e */
/*0460*/ LEA R7, R10, R7, 0x2 ; /* 0x000000070a077211 */
/* 0x000fe400078e10ff */
/*0470*/ ISETP.NE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f25270 */
/*0480*/ IMAD R8, R10.reuse, 0x4, R8 ; /* 0x000000040a087824 */
/* 0x040fe200078e0208 */
/*0490*/ LEA R9, R10, R9, 0x2 ; /* 0x000000090a097211 */
/* 0x000fe200078e10ff */
/*04a0*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0041f4000c101904 */
/*04b0*/ @P1 BRA 0x1d0 ; /* 0xfffffd1000001947 */
/* 0x000fea000383ffff */
/*04c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*04d0*/ IMAD R3, R2, c[0x0][0x4], R3 ; /* 0x0000010002037a24 */
/* 0x003fe400078e0203 */
/*04e0*/ IMAD R5, R4, c[0x0][0x0], R5 ; /* 0x0000000004057a24 */
/* 0x00cfc400078e0205 */
/*04f0*/ IMAD R20, R20, c[0x0][0x188], R3 ; /* 0x0000620014147a24 */
/* 0x000fc800078e0203 */
/*0500*/ IMAD R9, R20, c[0x0][0x184], R5 ; /* 0x0000610014097a24 */
/* 0x000fe400078e0205 */
/*0510*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x001fd400000001ff */
/*0520*/ IMAD.WIDE R2, R9, R6, c[0x0][0x178] ; /* 0x00005e0009027625 */
/* 0x000fcc00078e0206 */
/*0530*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0540*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0550*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe40000000f00 */
/*0560*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fc80003f05270 */
/*0570*/ SEL R4, R4, c[0x0][0x160], !P0 ; /* 0x0000580004047a07 */
/* 0x000fe40004000000 */
/*0580*/ SEL R5, R5, c[0x0][0x164], !P0 ; /* 0x0000590005057a07 */
/* 0x000fca0004000000 */
/*0590*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fcc00078e0204 */
/*05a0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*05c0*/ IMAD.WIDE R6, R9, R6, c[0x0][0x170] ; /* 0x00005c0009067625 */
/* 0x000fe200078e0206 */
/*05d0*/ MOV R2, c[0x0][0x188] ; /* 0x0000620000027a02 */
/* 0x000fe40000000f00 */
/*05e0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f05270 */
/*05f0*/ IMAD R9, R2, c[0x0][0x184], R9 ; /* 0x0000610002097a24 */
/* 0x000fe200078e0209 */
/*0600*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x0041f2000c101904 */
/*0610*/ @P0 BRA 0x510 ; /* 0xfffffef000000947 */
/* 0x000fea000383ffff */
/*0620*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0630*/ BRA 0x630; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26merge_without_blend_kernelPfS_S_Piiii
.globl _Z26merge_without_blend_kernelPfS_S_Piiii
.p2align 8
.type _Z26merge_without_blend_kernelPfS_S_Piiii,@function
_Z26merge_without_blend_kernelPfS_S_Piiii:
s_load_b32 s8, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b32 s9, s[0:1], 0x3c
s_load_b64 s[10:11], s[0:1], 0x24
v_bfe_u32 v1, v0, 10, 10
s_load_b256 s[0:7], s[0:1], 0x0
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s12, s9, 16
s_and_b32 s9, s9, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s12, v[1:2]
v_mov_b32_e32 v3, s2
s_mul_i32 s14, s14, s9
s_mul_i32 s2, s11, s10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v1, s10, v2
v_mov_b32_e32 v2, s3
v_add3_u32 v0, v0, v1, s14
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s8, s8, -1
s_cmp_eq_u32 s8, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_nc_u32_e32 v0, s2, v0
v_add_co_u32 v6, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
global_load_b32 v1, v[6:7], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v1
v_cndmask_b32_e32 v6, s0, v3, vcc_lo
v_cndmask_b32_e32 v1, s1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v6, v4
v_add_co_ci_u32_e32 v7, vcc_lo, v1, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v1, v[6:7], off
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v1, off
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26merge_without_blend_kernelPfS_S_Piiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26merge_without_blend_kernelPfS_S_Piiii, .Lfunc_end0-_Z26merge_without_blend_kernelPfS_S_Piiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26merge_without_blend_kernelPfS_S_Piiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26merge_without_blend_kernelPfS_S_Piiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d0fd9_00000000-6_merge_without_blend_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z55__device_stub__Z26merge_without_blend_kernelPfS_S_PiiiiPfS_S_Piiii
.type _Z55__device_stub__Z26merge_without_blend_kernelPfS_S_PiiiiPfS_S_Piiii, @function
_Z55__device_stub__Z26merge_without_blend_kernelPfS_S_PiiiiPfS_S_Piiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z26merge_without_blend_kernelPfS_S_Piiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z55__device_stub__Z26merge_without_blend_kernelPfS_S_PiiiiPfS_S_Piiii, .-_Z55__device_stub__Z26merge_without_blend_kernelPfS_S_PiiiiPfS_S_Piiii
.globl _Z26merge_without_blend_kernelPfS_S_Piiii
.type _Z26merge_without_blend_kernelPfS_S_Piiii, @function
_Z26merge_without_blend_kernelPfS_S_Piiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z55__device_stub__Z26merge_without_blend_kernelPfS_S_PiiiiPfS_S_Piiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26merge_without_blend_kernelPfS_S_Piiii, .-_Z26merge_without_blend_kernelPfS_S_Piiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26merge_without_blend_kernelPfS_S_Piiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26merge_without_blend_kernelPfS_S_Piiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "merge_without_blend_kernel.hip"
.globl _Z41__device_stub__merge_without_blend_kernelPfS_S_Piiii # -- Begin function _Z41__device_stub__merge_without_blend_kernelPfS_S_Piiii
.p2align 4, 0x90
.type _Z41__device_stub__merge_without_blend_kernelPfS_S_Piiii,@function
_Z41__device_stub__merge_without_blend_kernelPfS_S_Piiii: # @_Z41__device_stub__merge_without_blend_kernelPfS_S_Piiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z26merge_without_blend_kernelPfS_S_Piiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z41__device_stub__merge_without_blend_kernelPfS_S_Piiii, .Lfunc_end0-_Z41__device_stub__merge_without_blend_kernelPfS_S_Piiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26merge_without_blend_kernelPfS_S_Piiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26merge_without_blend_kernelPfS_S_Piiii,@object # @_Z26merge_without_blend_kernelPfS_S_Piiii
.section .rodata,"a",@progbits
.globl _Z26merge_without_blend_kernelPfS_S_Piiii
.p2align 3, 0x0
_Z26merge_without_blend_kernelPfS_S_Piiii:
.quad _Z41__device_stub__merge_without_blend_kernelPfS_S_Piiii
.size _Z26merge_without_blend_kernelPfS_S_Piiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26merge_without_blend_kernelPfS_S_Piiii"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__merge_without_blend_kernelPfS_S_Piiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26merge_without_blend_kernelPfS_S_Piiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
This file shows how to use the "gather" pattern in CUDA. This specific example is using the
Black-Scholes equation, where we parallelize over securities, but gather parameters for each
security.
*/
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "curand.h" // CUDA random number generators
#include <math.h> // standard mathematical operations (log, erf, sqrt)
#define _USE_MATH_DEFINES // common mathematical constants (`M_SQRT1_2`, used below, is equal to sqrt(1/2))
#include <cstdio>
// cumulative distribution function (CDF) of a standard normal distribution
// note the `__inline__`, which tells the compiler to just inline the function at compile time for
// performance (at the cost of larger binary size)
__device__ __host__ __inline__ float N(float x) {
return 0.5 + 0.5 * erff(x * M_SQRT1_2);
}
// options are a right to buy (call) or sell (put) an asset at a specific price/date
// k = strike price, s = underlying asset price, t = time until option expires,
// r = rate at which money can be borrowed, v = volatility of option
// c = call price, p = put price
// this kernel actually does all the calculations for each security
__device__ __host__ void price(float k, float s, float t, float r, float v, float* c, float* p) {
float srt = v * sqrtf(t);
float d1 = (logf(s/k) + (r+0.5*v*v)*t) / srt;
float d2 = d1 - srt;
float kert = k * expf(-r*t);
*c = erff(d1)*s - erff(d2)*kert;
*p = kert - s + *c;
}
// intermediate kernel which selects the index of the appropriate security and passes on
// computation to the function defined above
__global__ void price(float* k, float* s, float* t, float* r, float* v, float* c, float* p) {
int idx = threadIdx.x;
price(k[idx], s[idx], t[idx], r[idx], v[idx], &c[idx], &p[idx]);
}
int main() {
const int count = 512; // number of securities to analyze
const int size = count * sizeof(float);
float *args[5]; // array of arrays of parameters for each security (k, s, t, r, v)
// random generator for security parameters
curandGenerator_t gen;
curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_MTGP32);
// generate values for the parameters directly on device
for (int i=0; i<5; i++) {
cudaMalloc(&args[i], size);
curandGenerateUniform(gen, args[i], count);
}
float *dc, *dp; // call and put arrays
cudaMalloc(&dc, size); // allocate space on device
cudaMalloc(&dp, size);
// just realized - `&dc` and `&dp` are pointers to pointers... passing them to `cudaMalloc` allows
// the function to overwrite the pointers `dc` and `dp` to point at _new_ memory locations on the
// device, rather than the original locations on the host they were pointed at when declared
// calculate call/put values
price<<<1,count>>>(args[0], args[1], args[2], args[3], args[4], dc, dp);
// copy memory from device to host
float hc[count], hp[count];
cudaMemcpy(hc, dc, size, cudaMemcpyDeviceToHost);
cudaMemcpy(hp, dp, size, cudaMemcpyDeviceToHost);
// free memory on device
cudaFree(&dc);
cudaFree(&dp);
dc = NULL; dp = NULL; // make sure pointers can't be used or freed a second time
for (int i=0; i<5; i++) {
cudaFree(&args[i]);
args[i] = NULL;
}
// print out some values
for (int s=0; s<10; s++) {
for (int i=0; i<5; i++) {
printf("Call price: $%.2f, put price: $%.2f\n", hc[i], hp[i]);
}
}
return 0;
} | .file "tmpxft_000aff06_00000000-6_gather.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5pricefffffPfS_
.type _Z5pricefffffPfS_, @function
_Z5pricefffffPfS_:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movss %xmm0, 16(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm2, 24(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 12(%rsp)
movq %rdi, %rbp
movq %rsi, %rbx
pxor %xmm0, %xmm0
ucomiss %xmm2, %xmm0
ja .L8
sqrtss %xmm2, %xmm2
movaps %xmm2, %xmm0
.L6:
mulss 12(%rsp), %xmm0
movss %xmm0, 8(%rsp)
movss 20(%rsp), %xmm0
divss 16(%rsp), %xmm0
call logf@PLT
movaps %xmm0, %xmm2
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movapd %xmm0, %xmm1
mulsd .LC1(%rip), %xmm1
mulsd %xmm0, %xmm1
movss 28(%rsp), %xmm3
pxor %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
addsd %xmm0, %xmm1
movss 24(%rsp), %xmm8
pxor %xmm0, %xmm0
cvtss2sd %xmm8, %xmm0
mulsd %xmm0, %xmm1
pxor %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
addsd %xmm0, %xmm1
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
divsd %xmm0, %xmm1
pxor %xmm6, %xmm6
cvtsd2ss %xmm1, %xmm6
movss %xmm6, 12(%rsp)
xorps .LC2(%rip), %xmm3
movaps %xmm3, %xmm0
mulss %xmm8, %xmm0
call expf@PLT
movaps %xmm0, %xmm6
mulss 16(%rsp), %xmm6
movss %xmm6, 24(%rsp)
movss 12(%rsp), %xmm0
call erff@PLT
movss %xmm0, 16(%rsp)
movss 12(%rsp), %xmm4
subss 8(%rsp), %xmm4
movaps %xmm4, %xmm0
call erff@PLT
movss 16(%rsp), %xmm1
movss 20(%rsp), %xmm5
mulss %xmm5, %xmm1
movss 24(%rsp), %xmm6
mulss %xmm6, %xmm0
subss %xmm0, %xmm1
movss %xmm1, 0(%rbp)
subss %xmm5, %xmm6
movaps %xmm6, %xmm0
addss %xmm1, %xmm0
movss %xmm0, (%rbx)
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
movss 24(%rsp), %xmm0
call sqrtf@PLT
jmp .L6
.cfi_endproc
.LFE2058:
.size _Z5pricefffffPfS_, .-_Z5pricefffffPfS_
.globl _Z36__device_stub__Z5pricePfS_S_S_S_S_S_PfS_S_S_S_S_S_
.type _Z36__device_stub__Z5pricePfS_S_S_S_S_S_PfS_S_S_S_S_S_, @function
_Z36__device_stub__Z5pricePfS_S_S_S_S_S_PfS_S_S_S_S_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z5pricePfS_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z5pricePfS_S_S_S_S_S_PfS_S_S_S_S_S_, .-_Z36__device_stub__Z5pricePfS_S_S_S_S_S_PfS_S_S_S_S_S_
.globl _Z5pricePfS_S_S_S_S_S_
.type _Z5pricePfS_S_S_S_S_S_, @function
_Z5pricePfS_S_S_S_S_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z36__device_stub__Z5pricePfS_S_S_S_S_S_PfS_S_S_S_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z5pricePfS_S_S_S_S_S_, .-_Z5pricePfS_S_S_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Call price: $%.2f, put price: $%.2f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $4096, %rsp
.cfi_def_cfa_offset 4128
orq $0, (%rsp)
subq $112, %rsp
.cfi_def_cfa_offset 4240
movq %fs:40, %rax
movq %rax, 4200(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $141, %esi
call curandCreateGenerator@PLT
leaq 48(%rsp), %rbx
leaq 88(%rsp), %r12
movq %rbx, %rbp
.L19:
movl $2048, %esi
movq %rbp, %rdi
call cudaMalloc@PLT
movq 0(%rbp), %rsi
movl $512, %edx
movq (%rsp), %rdi
call curandGenerateUniform@PLT
addq $8, %rbp
cmpq %r12, %rbp
jne .L19
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $512, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L20:
leaq 96(%rsp), %rdi
movl $2, %ecx
movl $2048, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
leaq 2144(%rsp), %rdi
movl $2, %ecx
movl $2048, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
call cudaFree@PLT
leaq 16(%rsp), %rdi
call cudaFree@PLT
movq $0, 8(%rsp)
movq $0, 16(%rsp)
.L21:
movq %rbx, %rdi
call cudaFree@PLT
movq $0, (%rbx)
addq $8, %rbx
cmpq %r12, %rbx
jne .L21
movl $10, %r12d
leaq .LC3(%rip), %rbp
jmp .L22
.L30:
subq $8, %rsp
.cfi_def_cfa_offset 4248
pushq 24(%rsp)
.cfi_def_cfa_offset 4256
movq 24(%rsp), %r9
movq 96(%rsp), %r8
movq 88(%rsp), %rcx
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z36__device_stub__Z5pricePfS_S_S_S_S_S_PfS_S_S_S_S_S_
addq $16, %rsp
.cfi_def_cfa_offset 4240
jmp .L20
.L31:
subl $1, %r12d
je .L24
.L22:
movl $0, %ebx
.L23:
pxor %xmm0, %xmm0
cvtss2sd 96(%rsp,%rbx), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 2144(%rsp,%rbx), %xmm1
movq %rbp, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $20, %rbx
jne .L23
jmp .L31
.L24:
movq 4200(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $4208, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "_Z5pricePfS_S_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z5pricePfS_S_S_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1071644672
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC2:
.long -2147483648
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
This file shows how to use the "gather" pattern in CUDA. This specific example is using the
Black-Scholes equation, where we parallelize over securities, but gather parameters for each
security.
*/
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "curand.h" // CUDA random number generators
#include <math.h> // standard mathematical operations (log, erf, sqrt)
#define _USE_MATH_DEFINES // common mathematical constants (`M_SQRT1_2`, used below, is equal to sqrt(1/2))
#include <cstdio>
// cumulative distribution function (CDF) of a standard normal distribution
// note the `__inline__`, which tells the compiler to just inline the function at compile time for
// performance (at the cost of larger binary size)
__device__ __host__ __inline__ float N(float x) {
return 0.5 + 0.5 * erff(x * M_SQRT1_2);
}
// options are a right to buy (call) or sell (put) an asset at a specific price/date
// k = strike price, s = underlying asset price, t = time until option expires,
// r = rate at which money can be borrowed, v = volatility of option
// c = call price, p = put price
// this kernel actually does all the calculations for each security
__device__ __host__ void price(float k, float s, float t, float r, float v, float* c, float* p) {
float srt = v * sqrtf(t);
float d1 = (logf(s/k) + (r+0.5*v*v)*t) / srt;
float d2 = d1 - srt;
float kert = k * expf(-r*t);
*c = erff(d1)*s - erff(d2)*kert;
*p = kert - s + *c;
}
// intermediate kernel which selects the index of the appropriate security and passes on
// computation to the function defined above
__global__ void price(float* k, float* s, float* t, float* r, float* v, float* c, float* p) {
int idx = threadIdx.x;
price(k[idx], s[idx], t[idx], r[idx], v[idx], &c[idx], &p[idx]);
}
int main() {
const int count = 512; // number of securities to analyze
const int size = count * sizeof(float);
float *args[5]; // array of arrays of parameters for each security (k, s, t, r, v)
// random generator for security parameters
curandGenerator_t gen;
curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_MTGP32);
// generate values for the parameters directly on device
for (int i=0; i<5; i++) {
cudaMalloc(&args[i], size);
curandGenerateUniform(gen, args[i], count);
}
float *dc, *dp; // call and put arrays
cudaMalloc(&dc, size); // allocate space on device
cudaMalloc(&dp, size);
// just realized - `&dc` and `&dp` are pointers to pointers... passing them to `cudaMalloc` allows
// the function to overwrite the pointers `dc` and `dp` to point at _new_ memory locations on the
// device, rather than the original locations on the host they were pointed at when declared
// calculate call/put values
price<<<1,count>>>(args[0], args[1], args[2], args[3], args[4], dc, dp);
// copy memory from device to host
float hc[count], hp[count];
cudaMemcpy(hc, dc, size, cudaMemcpyDeviceToHost);
cudaMemcpy(hp, dp, size, cudaMemcpyDeviceToHost);
// free memory on device
cudaFree(&dc);
cudaFree(&dp);
dc = NULL; dp = NULL; // make sure pointers can't be used or freed a second time
for (int i=0; i<5; i++) {
cudaFree(&args[i]);
args[i] = NULL;
}
// print out some values
for (int s=0; s<10; s++) {
for (int i=0; i<5; i++) {
printf("Call price: $%.2f, put price: $%.2f\n", hc[i], hp[i]);
}
}
return 0;
} | /*
This file shows how to use the "gather" pattern in CUDA. This specific example is using the
Black-Scholes equation, where we parallelize over securities, but gather parameters for each
security.
*/
#include "hip/hip_runtime.h"
#include "hiprand/hiprand.h" // CUDA random number generators
#include <math.h> // standard mathematical operations (log, erf, sqrt)
#define _USE_MATH_DEFINES // common mathematical constants (`M_SQRT1_2`, used below, is equal to sqrt(1/2))
#include <cstdio>
// cumulative distribution function (CDF) of a standard normal distribution
// note the `__inline__`, which tells the compiler to just inline the function at compile time for
// performance (at the cost of larger binary size)
__device__ __host__ __inline__ float N(float x) {
return 0.5 + 0.5 * erff(x * M_SQRT1_2);
}
// options are a right to buy (call) or sell (put) an asset at a specific price/date
// k = strike price, s = underlying asset price, t = time until option expires,
// r = rate at which money can be borrowed, v = volatility of option
// c = call price, p = put price
// this kernel actually does all the calculations for each security
__device__ __host__ void price(float k, float s, float t, float r, float v, float* c, float* p) {
float srt = v * sqrtf(t);
float d1 = (logf(s/k) + (r+0.5*v*v)*t) / srt;
float d2 = d1 - srt;
float kert = k * expf(-r*t);
*c = erff(d1)*s - erff(d2)*kert;
*p = kert - s + *c;
}
// intermediate kernel which selects the index of the appropriate security and passes on
// computation to the function defined above
__global__ void price(float* k, float* s, float* t, float* r, float* v, float* c, float* p) {
int idx = threadIdx.x;
price(k[idx], s[idx], t[idx], r[idx], v[idx], &c[idx], &p[idx]);
}
int main() {
const int count = 512; // number of securities to analyze
const int size = count * sizeof(float);
float *args[5]; // array of arrays of parameters for each security (k, s, t, r, v)
// random generator for security parameters
hiprandGenerator_t gen;
hiprandCreateGenerator(&gen, HIPRAND_RNG_PSEUDO_MTGP32);
// generate values for the parameters directly on device
for (int i=0; i<5; i++) {
hipMalloc(&args[i], size);
hiprandGenerateUniform(gen, args[i], count);
}
float *dc, *dp; // call and put arrays
hipMalloc(&dc, size); // allocate space on device
hipMalloc(&dp, size);
// just realized - `&dc` and `&dp` are pointers to pointers... passing them to `cudaMalloc` allows
// the function to overwrite the pointers `dc` and `dp` to point at _new_ memory locations on the
// device, rather than the original locations on the host they were pointed at when declared
// calculate call/put values
price<<<1,count>>>(args[0], args[1], args[2], args[3], args[4], dc, dp);
// copy memory from device to host
float hc[count], hp[count];
hipMemcpy(hc, dc, size, hipMemcpyDeviceToHost);
hipMemcpy(hp, dp, size, hipMemcpyDeviceToHost);
// free memory on device
hipFree(&dc);
hipFree(&dp);
dc = NULL; dp = NULL; // make sure pointers can't be used or freed a second time
for (int i=0; i<5; i++) {
hipFree(&args[i]);
args[i] = NULL;
}
// print out some values
for (int s=0; s<10; s++) {
for (int i=0; i<5; i++) {
printf("Call price: $%.2f, put price: $%.2f\n", hc[i], hp[i]);
}
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
This file shows how to use the "gather" pattern in CUDA. This specific example is using the
Black-Scholes equation, where we parallelize over securities, but gather parameters for each
security.
*/
#include "hip/hip_runtime.h"
#include "hiprand/hiprand.h" // CUDA random number generators
#include <math.h> // standard mathematical operations (log, erf, sqrt)
#define _USE_MATH_DEFINES // common mathematical constants (`M_SQRT1_2`, used below, is equal to sqrt(1/2))
#include <cstdio>
// cumulative distribution function (CDF) of a standard normal distribution
// note the `__inline__`, which tells the compiler to just inline the function at compile time for
// performance (at the cost of larger binary size)
__device__ __host__ __inline__ float N(float x) {
return 0.5 + 0.5 * erff(x * M_SQRT1_2);
}
// options are a right to buy (call) or sell (put) an asset at a specific price/date
// k = strike price, s = underlying asset price, t = time until option expires,
// r = rate at which money can be borrowed, v = volatility of option
// c = call price, p = put price
// this kernel actually does all the calculations for each security
__device__ __host__ void price(float k, float s, float t, float r, float v, float* c, float* p) {
float srt = v * sqrtf(t);
float d1 = (logf(s/k) + (r+0.5*v*v)*t) / srt;
float d2 = d1 - srt;
float kert = k * expf(-r*t);
*c = erff(d1)*s - erff(d2)*kert;
*p = kert - s + *c;
}
// intermediate kernel which selects the index of the appropriate security and passes on
// computation to the function defined above
__global__ void price(float* k, float* s, float* t, float* r, float* v, float* c, float* p) {
int idx = threadIdx.x;
price(k[idx], s[idx], t[idx], r[idx], v[idx], &c[idx], &p[idx]);
}
int main() {
const int count = 512; // number of securities to analyze
const int size = count * sizeof(float);
float *args[5]; // array of arrays of parameters for each security (k, s, t, r, v)
// random generator for security parameters
hiprandGenerator_t gen;
hiprandCreateGenerator(&gen, HIPRAND_RNG_PSEUDO_MTGP32);
// generate values for the parameters directly on device
for (int i=0; i<5; i++) {
hipMalloc(&args[i], size);
hiprandGenerateUniform(gen, args[i], count);
}
float *dc, *dp; // call and put arrays
hipMalloc(&dc, size); // allocate space on device
hipMalloc(&dp, size);
// just realized - `&dc` and `&dp` are pointers to pointers... passing them to `cudaMalloc` allows
// the function to overwrite the pointers `dc` and `dp` to point at _new_ memory locations on the
// device, rather than the original locations on the host they were pointed at when declared
// calculate call/put values
price<<<1,count>>>(args[0], args[1], args[2], args[3], args[4], dc, dp);
// copy memory from device to host
float hc[count], hp[count];
hipMemcpy(hc, dc, size, hipMemcpyDeviceToHost);
hipMemcpy(hp, dp, size, hipMemcpyDeviceToHost);
// free memory on device
hipFree(&dc);
hipFree(&dp);
dc = NULL; dp = NULL; // make sure pointers can't be used or freed a second time
for (int i=0; i<5; i++) {
hipFree(&args[i]);
args[i] = NULL;
}
// print out some values
for (int s=0; s<10; s++) {
for (int i=0; i<5; i++) {
printf("Call price: $%.2f, put price: $%.2f\n", hc[i], hp[i]);
}
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5pricePfS_S_S_S_S_S_
.globl _Z5pricePfS_S_S_S_S_S_
.p2align 8
.type _Z5pricePfS_S_S_S_S_S_,@function
_Z5pricePfS_S_S_S_S_S_:
s_load_b256 s[4:11], s[0:1], 0x0
v_lshlrev_b32_e32 v5, 2, v0
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_clause 0x4
global_load_b32 v1, v5, s[4:5]
global_load_b32 v2, v5, s[6:7]
global_load_b32 v3, v5, s[8:9]
global_load_b32 v4, v5, s[10:11]
global_load_b32 v13, v5, s[2:3]
s_waitcnt vmcnt(2)
v_cmp_gt_f32_e64 s2, 0xf800000, v3
v_div_scale_f32 v7, null, v1, v1, v2
v_div_scale_f32 v9, vcc_lo, v2, v1, v2
v_mul_f32_e32 v15, 0x4f800000, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v8, v7
v_cndmask_b32_e64 v15, v3, v15, s2
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v7, v8, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v8, v5, v8
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[5:6], v13
v_mul_f32_e32 v10, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v11, -v7, v10, v9
v_fmac_f32_e32 v10, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v7, v10, v9
v_div_fmas_f32 v7, v7, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v7, v7, v1, v2
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v7
v_mul_f64 v[9:10], v[5:6], 0.5
v_cndmask_b32_e64 v8, 1.0, 0x4f800000, vcc_lo
v_cndmask_b32_e64 v16, 0, 0x41b17218, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v7, v8
v_log_f32_e32 v11, v7
v_cvt_f64_f32_e32 v[7:8], v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v12, 0x3f317217, v11
v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v11|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v14, v11, 0x3f317217, -v12
v_fmamk_f32 v14, v11, 0x3377d1cf, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_f32_e32 v12, v12, v14
v_sqrt_f32_e32 v14, v15
s_waitcnt_depctr 0xfff
v_dual_cndmask_b32 v11, v11, v12 :: v_dual_add_nc_u32 v18, 1, v14
v_dual_sub_f32 v16, v11, v16 :: v_dual_add_nc_u32 v17, -1, v14
v_fma_f64 v[5:6], v[9:10], v[5:6], v[7:8]
v_cvt_f64_f32_e32 v[11:12], v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v10, -v18, v14, v15
v_fma_f32 v7, -v17, v14, v15
v_cvt_f64_f32_e32 v[8:9], v16
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_ge_f32_e32 vcc_lo, 0, v7
v_cndmask_b32_e32 v7, v14, v17, vcc_lo
v_cmp_lt_f32_e32 vcc_lo, 0, v10
v_cndmask_b32_e32 v7, v7, v18, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v15, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, 0x37800000, v7
v_cndmask_b32_e64 v7, v7, v10, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v7, v7, v15, vcc_lo
v_mul_f32_e32 v7, v7, v13
v_fma_f64 v[5:6], v[5:6], v[11:12], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[13:14], v7
v_div_scale_f64 v[8:9], null, v[13:14], v[13:14], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[10:11], v[8:9]
s_waitcnt_depctr 0xfff
v_fma_f64 v[15:16], -v[8:9], v[10:11], 1.0
v_fma_f64 v[10:11], v[10:11], v[15:16], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], -v[8:9], v[10:11], 1.0
v_fma_f64 v[10:11], v[10:11], v[15:16], v[10:11]
v_div_scale_f64 v[15:16], vcc_lo, v[5:6], v[13:14], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[17:18], v[15:16], v[10:11]
v_fma_f64 v[8:9], -v[8:9], v[17:18], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[17:18]
v_div_fixup_f64 v[5:6], v[8:9], v[13:14], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v5, v[5:6]
v_cmp_nlt_f32_e64 s2, |v5|, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_xor_b32 s2, exec_lo, s3
s_cbranch_execz .LBB0_2
s_mov_b32 s3, 0x378e98ab
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, |v5|, s3, 0xb9c68948
v_fma_f32 v6, |v5|, v6, 0x3b7cd369
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, |v5|, v6, 0xbcc618b2
v_fma_f32 v6, |v5|, v6, 0x3dda74e4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, |v5|, v6, 0x3f228afd
v_fma_f32 v6, |v5|, v6, 0x3e03c728
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, |v5|, v6, |v5|
v_mul_f32_e32 v8, 0xbfb8aa3b, v6
v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v9, v6, 0xbfb8aa3b, -v8
v_rndne_f32_e32 v10, v8
v_dual_fmamk_f32 v9, v6, 0xb2a5705f, v9 :: v_dual_sub_f32 v8, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v8, v8, v9
v_cvt_i32_f32_e32 v9, v10
v_exp_f32_e32 v8, v8
s_waitcnt_depctr 0xfff
v_ldexp_f32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v8, 0, v8, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v6
v_cndmask_b32_e32 v6, 0x7f800000, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_sub_f32_e32 v6, 1.0, v6
.LBB0_2:
s_and_not1_saveexec_b32 s2, s2
v_mul_f32_e32 v6, v5, v5
s_mov_b32 s3, 0xba1345e1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fmaak_f32 v8, s3, v6, 0x3ba10414
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v8, v6, v8, 0xbcdac9b8
v_fmaak_f32 v8, v6, v8, 0x3de703be
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v8, v6, v8, 0xbec09330
v_fmaak_f32 v6, v6, v8, 0x3e0375d0
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v6, |v5|, v6, |v5|
s_or_b32 exec_lo, exec_lo, s2
v_sub_f32_e32 v7, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_nlt_f32_e64 s2, |v7|, 1.0
s_and_saveexec_b32 s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s3
s_cbranch_execz .LBB0_6
s_mov_b32 s3, 0x378e98ab
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, |v7|, s3, 0xb9c68948
v_fma_f32 v8, |v7|, v8, 0x3b7cd369
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, |v7|, v8, 0xbcc618b2
v_fma_f32 v8, |v7|, v8, 0x3dda74e4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, |v7|, v8, 0x3f228afd
v_fma_f32 v8, |v7|, v8, 0x3e03c728
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, |v7|, v8, |v7|
v_mul_f32_e32 v9, 0xbfb8aa3b, v8
v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v10, v8, 0xbfb8aa3b, -v9
v_rndne_f32_e32 v11, v9
v_dual_fmamk_f32 v10, v8, 0xb2a5705f, v10 :: v_dual_sub_f32 v9, v9, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v9, v9, v10
v_cvt_i32_f32_e32 v10, v11
v_exp_f32_e32 v9, v9
s_waitcnt_depctr 0xfff
v_ldexp_f32 v9, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v9, 0, v9, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v8
v_cndmask_b32_e32 v8, 0x7f800000, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_sub_f32_e32 v8, 1.0, v8
.LBB0_6:
s_and_not1_saveexec_b32 s2, s2
v_mul_f32_e32 v8, v7, v7
s_mov_b32 s3, 0xba1345e1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fmaak_f32 v9, s3, v8, 0x3ba10414
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v9, v8, v9, 0xbcdac9b8
v_fmaak_f32 v9, v8, v9, 0x3de703be
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v9, v8, v9, 0xbec09330
v_fmaak_f32 v8, v8, v9, 0x3e0375d0
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v8, |v7|, v8, |v7|
s_or_b32 exec_lo, exec_lo, s2
v_mul_f32_e64 v3, v3, -v4
s_load_b128 s[0:3], s[0:1], 0x28
v_bfi_b32 v5, 0x7fffffff, v6, v5
v_lshlrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v4, 0x3fb8aa3b, v3
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v3
v_fma_f32 v9, v3, 0x3fb8aa3b, -v4
v_rndne_f32_e32 v10, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmamk_f32 v9, v3, 0x32a5705f, v9 :: v_dual_sub_f32 v4, v4, v10
v_add_f32_e32 v4, v4, v9
v_cvt_i32_f32_e32 v9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_ldexp_f32 v4, v4, v9
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, 0x7f800000, v4, vcc_lo
v_bfi_b32 v4, 0x7fffffff, v8, v7
v_mul_f32_e32 v7, v1, v3
v_fma_f32 v1, v1, v3, -v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v7, v4
v_fma_f32 v4, v2, v5, -v4
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v1, v1, v4
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b32 v0, v4, s[0:1]
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5pricePfS_S_S_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 56
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 12
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5pricePfS_S_S_S_S_S_, .Lfunc_end0-_Z5pricePfS_S_S_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 56
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5pricePfS_S_S_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z5pricePfS_S_S_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
This file shows how to use the "gather" pattern in CUDA. This specific example is using the
Black-Scholes equation, where we parallelize over securities, but gather parameters for each
security.
*/
#include "hip/hip_runtime.h"
#include "hiprand/hiprand.h" // CUDA random number generators
#include <math.h> // standard mathematical operations (log, erf, sqrt)
#define _USE_MATH_DEFINES // common mathematical constants (`M_SQRT1_2`, used below, is equal to sqrt(1/2))
#include <cstdio>
// cumulative distribution function (CDF) of a standard normal distribution
// note the `__inline__`, which tells the compiler to just inline the function at compile time for
// performance (at the cost of larger binary size)
__device__ __host__ __inline__ float N(float x) {
return 0.5 + 0.5 * erff(x * M_SQRT1_2);
}
// options are a right to buy (call) or sell (put) an asset at a specific price/date
// k = strike price, s = underlying asset price, t = time until option expires,
// r = rate at which money can be borrowed, v = volatility of option
// c = call price, p = put price
// this kernel actually does all the calculations for each security
__device__ __host__ void price(float k, float s, float t, float r, float v, float* c, float* p) {
float srt = v * sqrtf(t);
float d1 = (logf(s/k) + (r+0.5*v*v)*t) / srt;
float d2 = d1 - srt;
float kert = k * expf(-r*t);
*c = erff(d1)*s - erff(d2)*kert;
*p = kert - s + *c;
}
// intermediate kernel which selects the index of the appropriate security and passes on
// computation to the function defined above
__global__ void price(float* k, float* s, float* t, float* r, float* v, float* c, float* p) {
int idx = threadIdx.x;
price(k[idx], s[idx], t[idx], r[idx], v[idx], &c[idx], &p[idx]);
}
int main() {
const int count = 512; // number of securities to analyze
const int size = count * sizeof(float);
float *args[5]; // array of arrays of parameters for each security (k, s, t, r, v)
// random generator for security parameters
hiprandGenerator_t gen;
hiprandCreateGenerator(&gen, HIPRAND_RNG_PSEUDO_MTGP32);
// generate values for the parameters directly on device
for (int i=0; i<5; i++) {
hipMalloc(&args[i], size);
hiprandGenerateUniform(gen, args[i], count);
}
float *dc, *dp; // call and put arrays
hipMalloc(&dc, size); // allocate space on device
hipMalloc(&dp, size);
// just realized - `&dc` and `&dp` are pointers to pointers... passing them to `cudaMalloc` allows
// the function to overwrite the pointers `dc` and `dp` to point at _new_ memory locations on the
// device, rather than the original locations on the host they were pointed at when declared
// calculate call/put values
price<<<1,count>>>(args[0], args[1], args[2], args[3], args[4], dc, dp);
// copy memory from device to host
float hc[count], hp[count];
hipMemcpy(hc, dc, size, hipMemcpyDeviceToHost);
hipMemcpy(hp, dp, size, hipMemcpyDeviceToHost);
// free memory on device
hipFree(&dc);
hipFree(&dp);
dc = NULL; dp = NULL; // make sure pointers can't be used or freed a second time
for (int i=0; i<5; i++) {
hipFree(&args[i]);
args[i] = NULL;
}
// print out some values
for (int s=0; s<10; s++) {
for (int i=0; i<5; i++) {
printf("Call price: $%.2f, put price: $%.2f\n", hc[i], hp[i]);
}
}
return 0;
} | .text
.file "gather.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5pricefffffPfS_
.LCPI0_0:
.quad 0x3fe0000000000000 # double 0.5
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_1:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.text
.globl _Z5pricefffffPfS_
.p2align 4, 0x90
.type _Z5pricefffffPfS_,@function
_Z5pricefffffPfS_: # @_Z5pricefffffPfS_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
movss %xmm4, 8(%rsp) # 4-byte Spill
movaps %xmm3, 32(%rsp) # 16-byte Spill
movss %xmm1, 16(%rsp) # 4-byte Spill
movss %xmm0, 12(%rsp) # 4-byte Spill
xorps %xmm0, %xmm0
ucomiss %xmm0, %xmm2
movss %xmm2, 28(%rsp) # 4-byte Spill
jb .LBB0_2
# %bb.1:
xorps %xmm0, %xmm0
sqrtss %xmm2, %xmm0
jmp .LBB0_3
.LBB0_2: # %call.sqrt
movaps %xmm2, %xmm0
callq sqrtf
.LBB0_3: # %.split
mulss 8(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, 24(%rsp) # 4-byte Spill
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
divss 12(%rsp), %xmm0 # 4-byte Folded Reload
callq logf
xorps %xmm4, %xmm4
cvtss2sd %xmm0, %xmm4
movaps 32(%rsp), %xmm0 # 16-byte Reload
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movss 8(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movsd .LCPI0_0(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm2, %xmm3
mulsd %xmm2, %xmm3
addsd %xmm1, %xmm3
movss 28(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
cvtss2sd %xmm5, %xmm1
mulsd %xmm3, %xmm1
addsd %xmm4, %xmm1
movss 24(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
xorps %xmm2, %xmm2
cvtss2sd %xmm3, %xmm2
divsd %xmm2, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, 20(%rsp) # 4-byte Spill
subss %xmm3, %xmm1
movss %xmm1, 8(%rsp) # 4-byte Spill
xorps .LCPI0_1(%rip), %xmm0
mulss %xmm5, %xmm0
callq expf
mulss 12(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, 12(%rsp) # 4-byte Spill
movss 20(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq erff
mulss 16(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, 32(%rsp) # 4-byte Spill
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq erff
movss 12(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss 32(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
subss %xmm0, %xmm2
movss %xmm2, (%r14)
subss 16(%rsp), %xmm1 # 4-byte Folded Reload
addss %xmm2, %xmm1
movss %xmm1, (%rbx)
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5pricefffffPfS_, .Lfunc_end0-_Z5pricefffffPfS_
.cfi_endproc
# -- End function
.globl _Z20__device_stub__pricePfS_S_S_S_S_S_ # -- Begin function _Z20__device_stub__pricePfS_S_S_S_S_S_
.p2align 4, 0x90
.type _Z20__device_stub__pricePfS_S_S_S_S_S_,@function
_Z20__device_stub__pricePfS_S_S_S_S_S_: # @_Z20__device_stub__pricePfS_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5pricePfS_S_S_S_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z20__device_stub__pricePfS_S_S_S_S_S_, .Lfunc_end1-_Z20__device_stub__pricePfS_S_S_S_S_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $4264, %rsp # imm = 0x10A8
.cfi_def_cfa_offset 4288
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $403, %esi # imm = 0x193
callq hiprandCreateGenerator
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rdi
addq $112, %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq 16(%rsp), %rdi
movq 112(%rsp,%rbx), %rsi
movl $512, %edx # imm = 0x200
callq hiprandGenerateUniform
addq $8, %rbx
cmpq $40, %rbx
jne .LBB2_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq %rsp, %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 511(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 112(%rsp), %rax
movq 120(%rsp), %rcx
movq 128(%rsp), %rdx
movq 136(%rsp), %rsi
movq 144(%rsp), %rdi
movq 8(%rsp), %r8
movq (%rsp), %r9
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdi, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 160(%rsp)
leaq 96(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rax
movq %rax, 176(%rsp)
leaq 80(%rsp), %rax
movq %rax, 184(%rsp)
leaq 72(%rsp), %rax
movq %rax, 192(%rsp)
leaq 64(%rsp), %rax
movq %rax, 200(%rsp)
leaq 56(%rsp), %rax
movq %rax, 208(%rsp)
leaq 2208(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 2208(%rsp), %rsi
movl 2216(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z5pricePfS_S_S_S_S_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 8(%rsp), %rsi
leaq 160(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
leaq 2208(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movl $2, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
callq hipFree
movq %rsp, %rdi
callq hipFree
movq $0, 8(%rsp)
movq $0, (%rsp)
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rdi
addq $112, %rdi
callq hipFree
movq $0, 112(%rsp,%rbx)
addq $8, %rbx
cmpq $40, %rbx
jne .LBB2_5
# %bb.6: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_8 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_8: # Parent Loop BB2_7 Depth=1
# => This Inner Loop Header: Depth=2
movss 160(%rsp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss 2208(%rsp,%r14,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movb $2, %al
callq printf
incq %r14
cmpq $5, %r14
jne .LBB2_8
# %bb.9: # in Loop: Header=BB2_7 Depth=1
incl %ebx
cmpl $10, %ebx
jne .LBB2_7
# %bb.10:
xorl %eax, %eax
addq $4264, %rsp # imm = 0x10A8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5pricePfS_S_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5pricePfS_S_S_S_S_S_,@object # @_Z5pricePfS_S_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z5pricePfS_S_S_S_S_S_
.p2align 3, 0x0
_Z5pricePfS_S_S_S_S_S_:
.quad _Z20__device_stub__pricePfS_S_S_S_S_S_
.size _Z5pricePfS_S_S_S_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Call price: $%.2f, put price: $%.2f\n"
.size .L.str, 37
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5pricePfS_S_S_S_S_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__pricePfS_S_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5pricePfS_S_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000aff06_00000000-6_gather.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5pricefffffPfS_
.type _Z5pricefffffPfS_, @function
_Z5pricefffffPfS_:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movss %xmm0, 16(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm2, 24(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 12(%rsp)
movq %rdi, %rbp
movq %rsi, %rbx
pxor %xmm0, %xmm0
ucomiss %xmm2, %xmm0
ja .L8
sqrtss %xmm2, %xmm2
movaps %xmm2, %xmm0
.L6:
mulss 12(%rsp), %xmm0
movss %xmm0, 8(%rsp)
movss 20(%rsp), %xmm0
divss 16(%rsp), %xmm0
call logf@PLT
movaps %xmm0, %xmm2
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movapd %xmm0, %xmm1
mulsd .LC1(%rip), %xmm1
mulsd %xmm0, %xmm1
movss 28(%rsp), %xmm3
pxor %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
addsd %xmm0, %xmm1
movss 24(%rsp), %xmm8
pxor %xmm0, %xmm0
cvtss2sd %xmm8, %xmm0
mulsd %xmm0, %xmm1
pxor %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
addsd %xmm0, %xmm1
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
divsd %xmm0, %xmm1
pxor %xmm6, %xmm6
cvtsd2ss %xmm1, %xmm6
movss %xmm6, 12(%rsp)
xorps .LC2(%rip), %xmm3
movaps %xmm3, %xmm0
mulss %xmm8, %xmm0
call expf@PLT
movaps %xmm0, %xmm6
mulss 16(%rsp), %xmm6
movss %xmm6, 24(%rsp)
movss 12(%rsp), %xmm0
call erff@PLT
movss %xmm0, 16(%rsp)
movss 12(%rsp), %xmm4
subss 8(%rsp), %xmm4
movaps %xmm4, %xmm0
call erff@PLT
movss 16(%rsp), %xmm1
movss 20(%rsp), %xmm5
mulss %xmm5, %xmm1
movss 24(%rsp), %xmm6
mulss %xmm6, %xmm0
subss %xmm0, %xmm1
movss %xmm1, 0(%rbp)
subss %xmm5, %xmm6
movaps %xmm6, %xmm0
addss %xmm1, %xmm0
movss %xmm0, (%rbx)
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
movss 24(%rsp), %xmm0
call sqrtf@PLT
jmp .L6
.cfi_endproc
.LFE2058:
.size _Z5pricefffffPfS_, .-_Z5pricefffffPfS_
.globl _Z36__device_stub__Z5pricePfS_S_S_S_S_S_PfS_S_S_S_S_S_
.type _Z36__device_stub__Z5pricePfS_S_S_S_S_S_PfS_S_S_S_S_S_, @function
_Z36__device_stub__Z5pricePfS_S_S_S_S_S_PfS_S_S_S_S_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z5pricePfS_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z5pricePfS_S_S_S_S_S_PfS_S_S_S_S_S_, .-_Z36__device_stub__Z5pricePfS_S_S_S_S_S_PfS_S_S_S_S_S_
.globl _Z5pricePfS_S_S_S_S_S_
.type _Z5pricePfS_S_S_S_S_S_, @function
_Z5pricePfS_S_S_S_S_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z36__device_stub__Z5pricePfS_S_S_S_S_S_PfS_S_S_S_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z5pricePfS_S_S_S_S_S_, .-_Z5pricePfS_S_S_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Call price: $%.2f, put price: $%.2f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $4096, %rsp
.cfi_def_cfa_offset 4128
orq $0, (%rsp)
subq $112, %rsp
.cfi_def_cfa_offset 4240
movq %fs:40, %rax
movq %rax, 4200(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $141, %esi
call curandCreateGenerator@PLT
leaq 48(%rsp), %rbx
leaq 88(%rsp), %r12
movq %rbx, %rbp
.L19:
movl $2048, %esi
movq %rbp, %rdi
call cudaMalloc@PLT
movq 0(%rbp), %rsi
movl $512, %edx
movq (%rsp), %rdi
call curandGenerateUniform@PLT
addq $8, %rbp
cmpq %r12, %rbp
jne .L19
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $512, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L20:
leaq 96(%rsp), %rdi
movl $2, %ecx
movl $2048, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
leaq 2144(%rsp), %rdi
movl $2, %ecx
movl $2048, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
call cudaFree@PLT
leaq 16(%rsp), %rdi
call cudaFree@PLT
movq $0, 8(%rsp)
movq $0, 16(%rsp)
.L21:
movq %rbx, %rdi
call cudaFree@PLT
movq $0, (%rbx)
addq $8, %rbx
cmpq %r12, %rbx
jne .L21
movl $10, %r12d
leaq .LC3(%rip), %rbp
jmp .L22
.L30:
subq $8, %rsp
.cfi_def_cfa_offset 4248
pushq 24(%rsp)
.cfi_def_cfa_offset 4256
movq 24(%rsp), %r9
movq 96(%rsp), %r8
movq 88(%rsp), %rcx
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z36__device_stub__Z5pricePfS_S_S_S_S_S_PfS_S_S_S_S_S_
addq $16, %rsp
.cfi_def_cfa_offset 4240
jmp .L20
.L31:
subl $1, %r12d
je .L24
.L22:
movl $0, %ebx
.L23:
pxor %xmm0, %xmm0
cvtss2sd 96(%rsp,%rbx), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 2144(%rsp,%rbx), %xmm1
movq %rbp, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $20, %rbx
jne .L23
jmp .L31
.L24:
movq 4200(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $4208, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "_Z5pricePfS_S_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z5pricePfS_S_S_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1071644672
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC2:
.long -2147483648
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gather.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5pricefffffPfS_
.LCPI0_0:
.quad 0x3fe0000000000000 # double 0.5
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_1:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.text
.globl _Z5pricefffffPfS_
.p2align 4, 0x90
.type _Z5pricefffffPfS_,@function
_Z5pricefffffPfS_: # @_Z5pricefffffPfS_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
movss %xmm4, 8(%rsp) # 4-byte Spill
movaps %xmm3, 32(%rsp) # 16-byte Spill
movss %xmm1, 16(%rsp) # 4-byte Spill
movss %xmm0, 12(%rsp) # 4-byte Spill
xorps %xmm0, %xmm0
ucomiss %xmm0, %xmm2
movss %xmm2, 28(%rsp) # 4-byte Spill
jb .LBB0_2
# %bb.1:
xorps %xmm0, %xmm0
sqrtss %xmm2, %xmm0
jmp .LBB0_3
.LBB0_2: # %call.sqrt
movaps %xmm2, %xmm0
callq sqrtf
.LBB0_3: # %.split
mulss 8(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, 24(%rsp) # 4-byte Spill
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
divss 12(%rsp), %xmm0 # 4-byte Folded Reload
callq logf
xorps %xmm4, %xmm4
cvtss2sd %xmm0, %xmm4
movaps 32(%rsp), %xmm0 # 16-byte Reload
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movss 8(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movsd .LCPI0_0(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm2, %xmm3
mulsd %xmm2, %xmm3
addsd %xmm1, %xmm3
movss 28(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
cvtss2sd %xmm5, %xmm1
mulsd %xmm3, %xmm1
addsd %xmm4, %xmm1
movss 24(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
xorps %xmm2, %xmm2
cvtss2sd %xmm3, %xmm2
divsd %xmm2, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, 20(%rsp) # 4-byte Spill
subss %xmm3, %xmm1
movss %xmm1, 8(%rsp) # 4-byte Spill
xorps .LCPI0_1(%rip), %xmm0
mulss %xmm5, %xmm0
callq expf
mulss 12(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, 12(%rsp) # 4-byte Spill
movss 20(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq erff
mulss 16(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, 32(%rsp) # 4-byte Spill
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq erff
movss 12(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss 32(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
subss %xmm0, %xmm2
movss %xmm2, (%r14)
subss 16(%rsp), %xmm1 # 4-byte Folded Reload
addss %xmm2, %xmm1
movss %xmm1, (%rbx)
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5pricefffffPfS_, .Lfunc_end0-_Z5pricefffffPfS_
.cfi_endproc
# -- End function
.globl _Z20__device_stub__pricePfS_S_S_S_S_S_ # -- Begin function _Z20__device_stub__pricePfS_S_S_S_S_S_
.p2align 4, 0x90
.type _Z20__device_stub__pricePfS_S_S_S_S_S_,@function
_Z20__device_stub__pricePfS_S_S_S_S_S_: # @_Z20__device_stub__pricePfS_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5pricePfS_S_S_S_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z20__device_stub__pricePfS_S_S_S_S_S_, .Lfunc_end1-_Z20__device_stub__pricePfS_S_S_S_S_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $4264, %rsp # imm = 0x10A8
.cfi_def_cfa_offset 4288
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $403, %esi # imm = 0x193
callq hiprandCreateGenerator
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rdi
addq $112, %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq 16(%rsp), %rdi
movq 112(%rsp,%rbx), %rsi
movl $512, %edx # imm = 0x200
callq hiprandGenerateUniform
addq $8, %rbx
cmpq $40, %rbx
jne .LBB2_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq %rsp, %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 511(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 112(%rsp), %rax
movq 120(%rsp), %rcx
movq 128(%rsp), %rdx
movq 136(%rsp), %rsi
movq 144(%rsp), %rdi
movq 8(%rsp), %r8
movq (%rsp), %r9
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdi, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 160(%rsp)
leaq 96(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rax
movq %rax, 176(%rsp)
leaq 80(%rsp), %rax
movq %rax, 184(%rsp)
leaq 72(%rsp), %rax
movq %rax, 192(%rsp)
leaq 64(%rsp), %rax
movq %rax, 200(%rsp)
leaq 56(%rsp), %rax
movq %rax, 208(%rsp)
leaq 2208(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 2208(%rsp), %rsi
movl 2216(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z5pricePfS_S_S_S_S_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 8(%rsp), %rsi
leaq 160(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
leaq 2208(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movl $2, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
callq hipFree
movq %rsp, %rdi
callq hipFree
movq $0, 8(%rsp)
movq $0, (%rsp)
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rdi
addq $112, %rdi
callq hipFree
movq $0, 112(%rsp,%rbx)
addq $8, %rbx
cmpq $40, %rbx
jne .LBB2_5
# %bb.6: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_8 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_8: # Parent Loop BB2_7 Depth=1
# => This Inner Loop Header: Depth=2
movss 160(%rsp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss 2208(%rsp,%r14,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movb $2, %al
callq printf
incq %r14
cmpq $5, %r14
jne .LBB2_8
# %bb.9: # in Loop: Header=BB2_7 Depth=1
incl %ebx
cmpl $10, %ebx
jne .LBB2_7
# %bb.10:
xorl %eax, %eax
addq $4264, %rsp # imm = 0x10A8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5pricePfS_S_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5pricePfS_S_S_S_S_S_,@object # @_Z5pricePfS_S_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z5pricePfS_S_S_S_S_S_
.p2align 3, 0x0
_Z5pricePfS_S_S_S_S_S_:
.quad _Z20__device_stub__pricePfS_S_S_S_S_S_
.size _Z5pricePfS_S_S_S_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Call price: $%.2f, put price: $%.2f\n"
.size .L.str, 37
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5pricePfS_S_S_S_S_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__pricePfS_S_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5pricePfS_S_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*#include<stdio.h>
#include<cuda.h>
#include<cuda_runtime.h>
#define N 40000; //ThreadsLaunched
__global__ void gpuArrSet(long *d_in1, long *d_in2)
{
int M = N;
long tID = blockIdx.x;
if(tID<M)
{
d_in1[tID] = (-tID);
d_in2[tID] = (2 * tID);
}
}
__global__ void gpuArrAdd(long *d_in1, long *d_in2, long*d_out)
{
int M = N;
long tID = blockIdx.x;
if (tID < M)
{
d_out[tID] = d_in2[tID] + d_in1[tID];
}
}
int main()
{
long* d_in1;
long* d_in2;
long* d_out;
int M = N;
cudaMalloc((void**)&d_in1, sizeof(long)*M);
cudaMalloc((void**)&d_in2, sizeof(long)*M);
cudaMalloc((void**)&d_out, sizeof(long)*M);
long* h_out =(long*) malloc(sizeof(long)*M);
gpuArrSet << <M , 1>> >(d_in1,d_in2);
gpuArrAdd << <M , 1>> >(d_in1, d_in2, d_out);
cudaDeviceSynchronize();
cudaMemcpy(h_out, d_out, sizeof(int)*M, cudaMemcpyDeviceToHost);
printf("Output: ");
for (int i = 0; i < M; i++)
{
printf("%ld\n", h_out[i]);
}
free(h_out);
cudaFree(d_in1);
cudaFree(d_in2);
cudaFree(d_out);
system("Pause");
return 911;
}*/ | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*#include<stdio.h>
#include<cuda.h>
#include<cuda_runtime.h>
#define N 40000; //ThreadsLaunched
__global__ void gpuArrSet(long *d_in1, long *d_in2)
{
int M = N;
long tID = blockIdx.x;
if(tID<M)
{
d_in1[tID] = (-tID);
d_in2[tID] = (2 * tID);
}
}
__global__ void gpuArrAdd(long *d_in1, long *d_in2, long*d_out)
{
int M = N;
long tID = blockIdx.x;
if (tID < M)
{
d_out[tID] = d_in2[tID] + d_in1[tID];
}
}
int main()
{
long* d_in1;
long* d_in2;
long* d_out;
int M = N;
cudaMalloc((void**)&d_in1, sizeof(long)*M);
cudaMalloc((void**)&d_in2, sizeof(long)*M);
cudaMalloc((void**)&d_out, sizeof(long)*M);
long* h_out =(long*) malloc(sizeof(long)*M);
gpuArrSet << <M , 1>> >(d_in1,d_in2);
gpuArrAdd << <M , 1>> >(d_in1, d_in2, d_out);
cudaDeviceSynchronize();
cudaMemcpy(h_out, d_out, sizeof(int)*M, cudaMemcpyDeviceToHost);
printf("Output: ");
for (int i = 0; i < M; i++)
{
printf("%ld\n", h_out[i]);
}
free(h_out);
cudaFree(d_in1);
cudaFree(d_in2);
cudaFree(d_out);
system("Pause");
return 911;
}*/ | .file "tmpxft_00037cdc_00000000-6_gpuArr.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*#include<stdio.h>
#include<cuda.h>
#include<cuda_runtime.h>
#define N 40000; //ThreadsLaunched
__global__ void gpuArrSet(long *d_in1, long *d_in2)
{
int M = N;
long tID = blockIdx.x;
if(tID<M)
{
d_in1[tID] = (-tID);
d_in2[tID] = (2 * tID);
}
}
__global__ void gpuArrAdd(long *d_in1, long *d_in2, long*d_out)
{
int M = N;
long tID = blockIdx.x;
if (tID < M)
{
d_out[tID] = d_in2[tID] + d_in1[tID];
}
}
int main()
{
long* d_in1;
long* d_in2;
long* d_out;
int M = N;
cudaMalloc((void**)&d_in1, sizeof(long)*M);
cudaMalloc((void**)&d_in2, sizeof(long)*M);
cudaMalloc((void**)&d_out, sizeof(long)*M);
long* h_out =(long*) malloc(sizeof(long)*M);
gpuArrSet << <M , 1>> >(d_in1,d_in2);
gpuArrAdd << <M , 1>> >(d_in1, d_in2, d_out);
cudaDeviceSynchronize();
cudaMemcpy(h_out, d_out, sizeof(int)*M, cudaMemcpyDeviceToHost);
printf("Output: ");
for (int i = 0; i < M; i++)
{
printf("%ld\n", h_out[i]);
}
free(h_out);
cudaFree(d_in1);
cudaFree(d_in2);
cudaFree(d_out);
system("Pause");
return 911;
}*/ | #include <hip/hip_runtime.h>
/*#include<stdio.h>
#include<cuda.h>
#include<cuda_runtime.h>
#define N 40000; //ThreadsLaunched
__global__ void gpuArrSet(long *d_in1, long *d_in2)
{
int M = N;
long tID = blockIdx.x;
if(tID<M)
{
d_in1[tID] = (-tID);
d_in2[tID] = (2 * tID);
}
}
__global__ void gpuArrAdd(long *d_in1, long *d_in2, long*d_out)
{
int M = N;
long tID = blockIdx.x;
if (tID < M)
{
d_out[tID] = d_in2[tID] + d_in1[tID];
}
}
int main()
{
long* d_in1;
long* d_in2;
long* d_out;
int M = N;
cudaMalloc((void**)&d_in1, sizeof(long)*M);
cudaMalloc((void**)&d_in2, sizeof(long)*M);
cudaMalloc((void**)&d_out, sizeof(long)*M);
long* h_out =(long*) malloc(sizeof(long)*M);
gpuArrSet << <M , 1>> >(d_in1,d_in2);
gpuArrAdd << <M , 1>> >(d_in1, d_in2, d_out);
cudaDeviceSynchronize();
cudaMemcpy(h_out, d_out, sizeof(int)*M, cudaMemcpyDeviceToHost);
printf("Output: ");
for (int i = 0; i < M; i++)
{
printf("%ld\n", h_out[i]);
}
free(h_out);
cudaFree(d_in1);
cudaFree(d_in2);
cudaFree(d_out);
system("Pause");
return 911;
}*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*#include<stdio.h>
#include<cuda.h>
#include<cuda_runtime.h>
#define N 40000; //ThreadsLaunched
__global__ void gpuArrSet(long *d_in1, long *d_in2)
{
int M = N;
long tID = blockIdx.x;
if(tID<M)
{
d_in1[tID] = (-tID);
d_in2[tID] = (2 * tID);
}
}
__global__ void gpuArrAdd(long *d_in1, long *d_in2, long*d_out)
{
int M = N;
long tID = blockIdx.x;
if (tID < M)
{
d_out[tID] = d_in2[tID] + d_in1[tID];
}
}
int main()
{
long* d_in1;
long* d_in2;
long* d_out;
int M = N;
cudaMalloc((void**)&d_in1, sizeof(long)*M);
cudaMalloc((void**)&d_in2, sizeof(long)*M);
cudaMalloc((void**)&d_out, sizeof(long)*M);
long* h_out =(long*) malloc(sizeof(long)*M);
gpuArrSet << <M , 1>> >(d_in1,d_in2);
gpuArrAdd << <M , 1>> >(d_in1, d_in2, d_out);
cudaDeviceSynchronize();
cudaMemcpy(h_out, d_out, sizeof(int)*M, cudaMemcpyDeviceToHost);
printf("Output: ");
for (int i = 0; i < M; i++)
{
printf("%ld\n", h_out[i]);
}
free(h_out);
cudaFree(d_in1);
cudaFree(d_in2);
cudaFree(d_out);
system("Pause");
return 911;
}*/ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*#include<stdio.h>
#include<cuda.h>
#include<cuda_runtime.h>
#define N 40000; //ThreadsLaunched
__global__ void gpuArrSet(long *d_in1, long *d_in2)
{
int M = N;
long tID = blockIdx.x;
if(tID<M)
{
d_in1[tID] = (-tID);
d_in2[tID] = (2 * tID);
}
}
__global__ void gpuArrAdd(long *d_in1, long *d_in2, long*d_out)
{
int M = N;
long tID = blockIdx.x;
if (tID < M)
{
d_out[tID] = d_in2[tID] + d_in1[tID];
}
}
int main()
{
long* d_in1;
long* d_in2;
long* d_out;
int M = N;
cudaMalloc((void**)&d_in1, sizeof(long)*M);
cudaMalloc((void**)&d_in2, sizeof(long)*M);
cudaMalloc((void**)&d_out, sizeof(long)*M);
long* h_out =(long*) malloc(sizeof(long)*M);
gpuArrSet << <M , 1>> >(d_in1,d_in2);
gpuArrAdd << <M , 1>> >(d_in1, d_in2, d_out);
cudaDeviceSynchronize();
cudaMemcpy(h_out, d_out, sizeof(int)*M, cudaMemcpyDeviceToHost);
printf("Output: ");
for (int i = 0; i < M; i++)
{
printf("%ld\n", h_out[i]);
}
free(h_out);
cudaFree(d_in1);
cudaFree(d_in2);
cudaFree(d_out);
system("Pause");
return 911;
}*/ | .text
.file "gpuArr.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00037cdc_00000000-6_gpuArr.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpuArr.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cmath>
#include <cstdio>
#define cudaErrchk(ans) { GPUAssert((ans), __FILE__, __LINE__); }
inline void GPUAssert(cudaError_t code, const char *file, int line, bool abort=true){
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__
void add(int n, float* x, float* y) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n) {
y[index] = 1 + 2;
}
}
int main() {
int N = 1 << 28;
size_t size = N * sizeof(float);
float *h_x = (float*)malloc(size);
float *h_y = (float*)malloc(size);
float *d_x, *d_y;
cudaMalloc(&d_x, size);
cudaMalloc(&d_y, size);
for (int i = 0; i < N; ++i) {
h_x[i] = 1.0f;
h_y[i] = 2.0f;
}
cudaMemcpy(d_x, h_x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, h_y, size, cudaMemcpyHostToDevice);
int blockSize = 1024;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, d_x, d_y);
cudaErrchk( cudaPeekAtLastError() );
// cudaDeviceSynchronize();
cudaMemcpy(h_y, d_y, size, cudaMemcpyDeviceToHost);
float maxError = 0.0f;
for (int i = 0; i < N; i++) {
maxError = fmax(maxError, fabs(h_y[i]-3.0f));
}
std::cout << "Max error: " << maxError << std::endl;
cudaFree(d_x);
cudaFree(d_y);
free(h_x);
free(h_y);
return 0;
} | code for sm_80
Function : _Z3addiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, 0x40400000 ; /* 0x4040000000057802 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cmath>
#include <cstdio>
#define cudaErrchk(ans) { GPUAssert((ans), __FILE__, __LINE__); }
inline void GPUAssert(cudaError_t code, const char *file, int line, bool abort=true){
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__
void add(int n, float* x, float* y) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n) {
y[index] = 1 + 2;
}
}
int main() {
int N = 1 << 28;
size_t size = N * sizeof(float);
float *h_x = (float*)malloc(size);
float *h_y = (float*)malloc(size);
float *d_x, *d_y;
cudaMalloc(&d_x, size);
cudaMalloc(&d_y, size);
for (int i = 0; i < N; ++i) {
h_x[i] = 1.0f;
h_y[i] = 2.0f;
}
cudaMemcpy(d_x, h_x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, h_y, size, cudaMemcpyHostToDevice);
int blockSize = 1024;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, d_x, d_y);
cudaErrchk( cudaPeekAtLastError() );
// cudaDeviceSynchronize();
cudaMemcpy(h_y, d_y, size, cudaMemcpyDeviceToHost);
float maxError = 0.0f;
for (int i = 0; i < N; i++) {
maxError = fmax(maxError, fabs(h_y[i]-3.0f));
}
std::cout << "Max error: " << maxError << std::endl;
cudaFree(d_x);
cudaFree(d_y);
free(h_x);
free(h_y);
return 0;
} | .file "tmpxft_00077741_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3addiPfS_iPfS_
.type _Z25__device_stub__Z3addiPfS_iPfS_, @function
_Z25__device_stub__Z3addiPfS_iPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z25__device_stub__Z3addiPfS_iPfS_, .-_Z25__device_stub__Z3addiPfS_iPfS_
.globl _Z3addiPfS_
.type _Z3addiPfS_, @function
_Z3addiPfS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3addiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z3addiPfS_, .-_Z3addiPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/akhtyamovpavel/ParallelComputationExamples/master/CUDA/01-intro/04-memcpy/main.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "GPUassert: %s %s %d\n"
.LC7:
.string "Max error: "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1073741824, %edi
call malloc@PLT
movq %rax, %r12
movl $1073741824, %edi
call malloc@PLT
movq %rax, %rbp
leaq 16(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movss %xmm1, (%r12,%rax)
movss %xmm0, 0(%rbp,%rax)
addq $4, %rax
cmpq $1073741824, %rax
jne .L12
movl $1, %ecx
movl $1073741824, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1073741824, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $262144, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L13:
call cudaPeekAtLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L21
movl $2, %ecx
movl $1073741824, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
leaq 1073741824(%rbp), %r13
movl $0x00000000, 12(%rsp)
.L15:
movss (%rbx), %xmm0
subss .LC5(%rip), %xmm0
andps .LC6(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %r13, %rbx
jne .L15
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl $268435456, %edi
call _Z25__device_stub__Z3addiPfS_iPfS_
jmp .L13
.L21:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $50, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z3addiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC5:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC6:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cmath>
#include <cstdio>
#define cudaErrchk(ans) { GPUAssert((ans), __FILE__, __LINE__); }
inline void GPUAssert(cudaError_t code, const char *file, int line, bool abort=true){
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__
void add(int n, float* x, float* y) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n) {
y[index] = 1 + 2;
}
}
int main() {
int N = 1 << 28;
size_t size = N * sizeof(float);
float *h_x = (float*)malloc(size);
float *h_y = (float*)malloc(size);
float *d_x, *d_y;
cudaMalloc(&d_x, size);
cudaMalloc(&d_y, size);
for (int i = 0; i < N; ++i) {
h_x[i] = 1.0f;
h_y[i] = 2.0f;
}
cudaMemcpy(d_x, h_x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, h_y, size, cudaMemcpyHostToDevice);
int blockSize = 1024;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, d_x, d_y);
cudaErrchk( cudaPeekAtLastError() );
// cudaDeviceSynchronize();
cudaMemcpy(h_y, d_y, size, cudaMemcpyDeviceToHost);
float maxError = 0.0f;
for (int i = 0; i < N; i++) {
maxError = fmax(maxError, fabs(h_y[i]-3.0f));
}
std::cout << "Max error: " << maxError << std::endl;
cudaFree(d_x);
cudaFree(d_y);
free(h_x);
free(h_y);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
#include <cstdio>
#define cudaErrchk(ans) { GPUAssert((ans), __FILE__, __LINE__); }
inline void GPUAssert(hipError_t code, const char *file, int line, bool abort=true){
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__
void add(int n, float* x, float* y) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n) {
y[index] = 1 + 2;
}
}
int main() {
int N = 1 << 28;
size_t size = N * sizeof(float);
float *h_x = (float*)malloc(size);
float *h_y = (float*)malloc(size);
float *d_x, *d_y;
hipMalloc(&d_x, size);
hipMalloc(&d_y, size);
for (int i = 0; i < N; ++i) {
h_x[i] = 1.0f;
h_y[i] = 2.0f;
}
hipMemcpy(d_x, h_x, size, hipMemcpyHostToDevice);
hipMemcpy(d_y, h_y, size, hipMemcpyHostToDevice);
int blockSize = 1024;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, d_x, d_y);
cudaErrchk( hipPeekAtLastError() );
// cudaDeviceSynchronize();
hipMemcpy(h_y, d_y, size, hipMemcpyDeviceToHost);
float maxError = 0.0f;
for (int i = 0; i < N; i++) {
maxError = fmax(maxError, fabs(h_y[i]-3.0f));
}
std::cout << "Max error: " << maxError << std::endl;
hipFree(d_x);
hipFree(d_y);
free(h_x);
free(h_y);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
#include <cstdio>
#define cudaErrchk(ans) { GPUAssert((ans), __FILE__, __LINE__); }
inline void GPUAssert(hipError_t code, const char *file, int line, bool abort=true){
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__
void add(int n, float* x, float* y) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n) {
y[index] = 1 + 2;
}
}
int main() {
int N = 1 << 28;
size_t size = N * sizeof(float);
float *h_x = (float*)malloc(size);
float *h_y = (float*)malloc(size);
float *d_x, *d_y;
hipMalloc(&d_x, size);
hipMalloc(&d_y, size);
for (int i = 0; i < N; ++i) {
h_x[i] = 1.0f;
h_y[i] = 2.0f;
}
hipMemcpy(d_x, h_x, size, hipMemcpyHostToDevice);
hipMemcpy(d_y, h_y, size, hipMemcpyHostToDevice);
int blockSize = 1024;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, d_x, d_y);
cudaErrchk( hipPeekAtLastError() );
// cudaDeviceSynchronize();
hipMemcpy(h_y, d_y, size, hipMemcpyDeviceToHost);
float maxError = 0.0f;
for (int i = 0; i < N; i++) {
maxError = fmax(maxError, fabs(h_y[i]-3.0f));
}
std::cout << "Max error: " << maxError << std::endl;
hipFree(d_x);
hipFree(d_y);
free(h_x);
free(h_y);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPfS_
.globl _Z3addiPfS_
.p2align 8
.type _Z3addiPfS_,@function
_Z3addiPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0x40400000
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPfS_, .Lfunc_end0-_Z3addiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
#include <cstdio>
#define cudaErrchk(ans) { GPUAssert((ans), __FILE__, __LINE__); }
inline void GPUAssert(hipError_t code, const char *file, int line, bool abort=true){
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__
void add(int n, float* x, float* y) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n) {
y[index] = 1 + 2;
}
}
int main() {
int N = 1 << 28;
size_t size = N * sizeof(float);
float *h_x = (float*)malloc(size);
float *h_y = (float*)malloc(size);
float *d_x, *d_y;
hipMalloc(&d_x, size);
hipMalloc(&d_y, size);
for (int i = 0; i < N; ++i) {
h_x[i] = 1.0f;
h_y[i] = 2.0f;
}
hipMemcpy(d_x, h_x, size, hipMemcpyHostToDevice);
hipMemcpy(d_y, h_y, size, hipMemcpyHostToDevice);
int blockSize = 1024;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, d_x, d_y);
cudaErrchk( hipPeekAtLastError() );
// cudaDeviceSynchronize();
hipMemcpy(h_y, d_y, size, hipMemcpyDeviceToHost);
float maxError = 0.0f;
for (int i = 0; i < N; i++) {
maxError = fmax(maxError, fabs(h_y[i]-3.0f));
}
std::cout << "Max error: " << maxError << std::endl;
hipFree(d_x);
hipFree(d_y);
free(h_x);
free(h_y);
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiPfS_ # -- Begin function _Z18__device_stub__addiPfS_
.p2align 4, 0x90
.type _Z18__device_stub__addiPfS_,@function
_Z18__device_stub__addiPfS_: # @_Z18__device_stub__addiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPfS_, .Lfunc_end0-_Z18__device_stub__addiPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %rbx
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq $268435456, %rax # imm = 0x10000000
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 261120(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $268435456, 28(%rsp) # imm = 0x10000000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_12
# %bb.5: # %_Z9GPUAssert10hipError_tPKcib.exit
movq 8(%rsp), %rsi
movl $1073741824, %edx # imm = 0x40000000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm2, %xmm2
xorl %eax, %eax
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_6: # =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $268435456, %rax # imm = 0x10000000
jne .LBB1_6
# %bb.7:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $11, %edx
movaps %xmm5, 128(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 128(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_13
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_10
# %bb.9:
movzbl 67(%r15), %ecx
jmp .LBB1_11
.LBB1_10:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_12:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $52, %r8d
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.LBB1_13:
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiPfS_,@object # @_Z3addiPfS_
.section .rodata,"a",@progbits
.globl _Z3addiPfS_
.p2align 3, 0x0
_Z3addiPfS_:
.quad _Z18__device_stub__addiPfS_
.size _Z3addiPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/akhtyamovpavel/ParallelComputationExamples/master/CUDA/01-intro/04-memcpy/main.hip"
.size .L.str, 140
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Max error: "
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.2, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiPfS_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, 0x40400000 ; /* 0x4040000000057802 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPfS_
.globl _Z3addiPfS_
.p2align 8
.type _Z3addiPfS_,@function
_Z3addiPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0x40400000
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPfS_, .Lfunc_end0-_Z3addiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00077741_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3addiPfS_iPfS_
.type _Z25__device_stub__Z3addiPfS_iPfS_, @function
_Z25__device_stub__Z3addiPfS_iPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z25__device_stub__Z3addiPfS_iPfS_, .-_Z25__device_stub__Z3addiPfS_iPfS_
.globl _Z3addiPfS_
.type _Z3addiPfS_, @function
_Z3addiPfS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3addiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z3addiPfS_, .-_Z3addiPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/akhtyamovpavel/ParallelComputationExamples/master/CUDA/01-intro/04-memcpy/main.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "GPUassert: %s %s %d\n"
.LC7:
.string "Max error: "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1073741824, %edi
call malloc@PLT
movq %rax, %r12
movl $1073741824, %edi
call malloc@PLT
movq %rax, %rbp
leaq 16(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movss %xmm1, (%r12,%rax)
movss %xmm0, 0(%rbp,%rax)
addq $4, %rax
cmpq $1073741824, %rax
jne .L12
movl $1, %ecx
movl $1073741824, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1073741824, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $262144, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L13:
call cudaPeekAtLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L21
movl $2, %ecx
movl $1073741824, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
leaq 1073741824(%rbp), %r13
movl $0x00000000, 12(%rsp)
.L15:
movss (%rbx), %xmm0
subss .LC5(%rip), %xmm0
andps .LC6(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %r13, %rbx
jne .L15
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl $268435456, %edi
call _Z25__device_stub__Z3addiPfS_iPfS_
jmp .L13
.L21:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $50, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z3addiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC5:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC6:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiPfS_ # -- Begin function _Z18__device_stub__addiPfS_
.p2align 4, 0x90
.type _Z18__device_stub__addiPfS_,@function
_Z18__device_stub__addiPfS_: # @_Z18__device_stub__addiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPfS_, .Lfunc_end0-_Z18__device_stub__addiPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %rbx
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq $268435456, %rax # imm = 0x10000000
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 261120(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $268435456, 28(%rsp) # imm = 0x10000000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_12
# %bb.5: # %_Z9GPUAssert10hipError_tPKcib.exit
movq 8(%rsp), %rsi
movl $1073741824, %edx # imm = 0x40000000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm2, %xmm2
xorl %eax, %eax
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_6: # =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $268435456, %rax # imm = 0x10000000
jne .LBB1_6
# %bb.7:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $11, %edx
movaps %xmm5, 128(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 128(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_13
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_10
# %bb.9:
movzbl 67(%r15), %ecx
jmp .LBB1_11
.LBB1_10:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_12:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $52, %r8d
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.LBB1_13:
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiPfS_,@object # @_Z3addiPfS_
.section .rodata,"a",@progbits
.globl _Z3addiPfS_
.p2align 3, 0x0
_Z3addiPfS_:
.quad _Z18__device_stub__addiPfS_
.size _Z3addiPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/akhtyamovpavel/ParallelComputationExamples/master/CUDA/01-intro/04-memcpy/main.hip"
.size .L.str, 140
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Max error: "
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.2, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiPfS_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
#include <cuda.h>
#include <curand.h>
#define CUDA_CALL(x) do { if((x)!=cudaSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define DEPTH 5 // no of layers
#define BREADTH 1000 // nodes per layer
#define RATE 0.0001 // learning rate
#define NDIM(a,b) ((a)*BREADTH+(b))
#define WDIM(a,b,c) ((a)*BREADTH*BREADTH+(b)*BREADTH+(c))
float *W, *R; // [DEPTH-1][BREADTH][BREADTH] W_kij : weight of edge b/w jth and ith node from kth layer and k+1th layer resp.
float *N; // [DEPTH][BREADTH] N_ki : jth node in kth layer
float *Y, *pY; // [BREADTH] expected and predicted output vectors
float *U, *V; // [BREADTH] vectors for backpropagation chain-rule
float Yh[BREADTH], Dh[BREADTH]; // host arrays: expected and predicted output
int count = 0;
#define f(x) (tanhf((x))) // activation function
#define df(y) (1 - (y) * (y)) // derivative of activation function in y terms
__global__ void predict_N( float *N) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i;
// erase all nodes except first layer
for ( i = tid + BREADTH ; i < BREADTH * DEPTH ; i += stride )
N[i] = 0;
}
__global__ void predict_WN( float *N, float *W, float *R, int k) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int h;
// matrix-vector multiplication W*N b/w k-1th and kth layer
int wIndex = k * BREADTH * BREADTH;
int nIndex = k * BREADTH;
for ( h = tid ; h < BREADTH * BREADTH ; h += stride ) {
int j = h % BREADTH;
R[h] = W[wIndex + h] * N[nIndex + j];
}
}
__global__ void predict_Ri( float *R, int n, int j) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i;
for ( i = tid % BREADTH ; i < BREADTH ; i += stride ) {
int itid = tid / BREADTH;
int istride = stride / BREADTH;
istride += (istride == 0);
int rIndex = i * BREADTH;
for ( int h = 2 * j * itid; h < j * (n - 1); h += 2 * j * istride)
R[rIndex + h] += R[rIndex + h + j];
}
}
__global__ void predict_Nk( float *N, float *R, int k) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i;
for ( i = tid; i < BREADTH; i += stride )
N[NDIM(k,i)] = f( R[NDIM(i,0)]);
}
__global__ void predict_Yp( float *N, float *pY) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i;
for ( i = tid; i < BREADTH; i += stride )
pY[i] = N[NDIM(DEPTH-1,i)];
}
__global__ void train_V( float *N, float *Y, float *V) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int q = DEPTH - 2;
// caching chain-rule calculation in vector to aid in backpropagation
for ( int i = tid; i < BREADTH; i += stride ) {
V[i] = (N[NDIM(q+1,i)] - Y[i]) * df( N[NDIM(q+1,i)]);
}
}
__global__ void train_Wf( float *N, float *W, float *V) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int q = DEPTH - 2, h;
// update weights of outer layer
for ( h = tid; h < BREADTH * BREADTH; h += stride ) {
int i = h / BREADTH;
int j = h % BREADTH;
W[WDIM(q,i,j)] -= (float)RATE * V[i] * N[NDIM(q,j)];
}
}
__global__ void train_WN( float *N, float *W, float *A, float *R, int k) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int h;
// matrix-vector multiplication W*N b/w k-1th and kth layer
int wIndex = k * BREADTH * BREADTH;
int nIndex = k * BREADTH;
for ( h = tid ; h < BREADTH * BREADTH ; h += stride ) {
int j = h % BREADTH;
int i = h / BREADTH;
R[NDIM(j,i)] = A[i] * W[wIndex + h] * df( N[nIndex + j]);
}
}
__global__ void train_B( float *R, float *B) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i;
for ( i = tid; i < BREADTH; i += stride )
B[i] = R[NDIM(i,0)];
}
__global__ void train_Wh( float *N, float *W, float *A, int k) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int h;
// matrix-vector multiplication W*N b/w k-1th and kth layer
int wIndex = k * BREADTH * BREADTH;
int nIndex = k * BREADTH;
for ( h = tid ; h < BREADTH * BREADTH ; h += stride ) {
int j = h % BREADTH;
int i = h / BREADTH;
W[wIndex + h] -= (float)RATE * A[i] * N[nIndex + j];
}
}
void train() {
train_V<<<128, 32>>>( N, Y, V);
cudaDeviceSynchronize();
train_Wf<<<128, 32>>>( N, W, V);
cudaDeviceSynchronize();
int q = DEPTH - 2;
float *A = &V[0], *B = &U[0];
float *temp;
// updating weights of hidden layers (backpropagation)
for ( int k = q - 1; k >= 0; k-- ) {
// chain-rule expansion by multiplying with next layer's weight matrix and
// derivative of activation function on the same layer's nodes
train_WN<<<128, 32>>>( N, W, A, R, k+1);
cudaDeviceSynchronize();
int j = 1;
int n = BREADTH;
while ( n > 1) {
predict_Ri<<<128, 32>>>( R, n, j);
cudaDeviceSynchronize();
j *= 2;
n = (n+1)/2;
}
train_B<<<128, 32>>>( R, B);
cudaDeviceSynchronize();
temp = B; B = A; A = temp;
// adjust weights by gradient descent
train_Wh<<<128, 32>>>( N, W, A, k);
cudaDeviceSynchronize();
}
}
__global__ void normalize( float *W, float *N, float *Y) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i, w = (DEPTH-1) * BREADTH * BREADTH;
for ( i = tid; i < w; i+= stride)
W[i] = 1/ (float)BREADTH;
for ( i = tid; i < BREADTH; i+= stride)
N[i] = i/ (float)BREADTH;
for ( i = tid; i < BREADTH; i+= stride)
Y[i] = i/ (float)BREADTH;
}
void initialize() {
int w = (DEPTH-1) * BREADTH * BREADTH;
// device memory allocation of global arrays
cudaMalloc( (void**)(&W), sizeof(float) * w);
cudaMalloc( (void**)(&R), sizeof(float) * BREADTH * BREADTH);
cudaMalloc( (void**)(&N), sizeof(float) * DEPTH * BREADTH);
cudaMalloc( (void**)(&Y), sizeof(float) * BREADTH);
cudaMalloc( (void**)(&pY), sizeof(float) * BREADTH);
cudaMalloc( (void**)(&U), sizeof(float) * BREADTH);
cudaMalloc( (void**)(&V), sizeof(float) * BREADTH);
/*
// random number generator
curandGenerator_t gen;
// Create pseudo-random number generator
curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_DEFAULT);
// Set seed
curandSetPseudoRandomGeneratorSeed(gen, time(0));
// Generate floats on device
curandGenerateUniform(gen, W, w);
curandGenerateUniform(gen, N, BREADTH * DEPTH);
curandGenerateUniform(gen, Y, BREADTH);
curandDestroyGenerator(gen);
*/
normalize<<<128, 32>>>(W, N, Y);
cudaDeviceSynchronize();
}
void calculateError() {
float err = 0, dY;
// dY : difference b/w expected and predicted output, and
// err : sum of squares of dY
for ( int i = 0 ; i < BREADTH ; i++ ) {
dY = (Dh[i] - Yh[i]);
err += dY * dY;
}
printf("ITERATION : %d\tLOSS : %f\t", count, err);
}
void freeResources() {
cudaFree(Y);
cudaFree(N);
cudaFree(W);
cudaFree(pY);
cudaFree(U);
cudaFree(V);
cudaFree(R);
}
void predict() {
predict_N<<<128, 32>>>(N);
cudaDeviceSynchronize();
for ( int k = 1; k < DEPTH ; k++ ) {
predict_WN<<<128, 32>>>( N, W, R, k-1);
cudaDeviceSynchronize();
int j = 1;
int n = BREADTH;
while ( n > 1) {
predict_Ri<<<128, 32>>>( R, n, j);
cudaDeviceSynchronize();
j *= 2;
n = (n+1)/2;
}
predict_Nk<<<128, 32>>>( N, R, k);
cudaDeviceSynchronize();
}
predict_Yp<<<128, 32>>>( N, pY);
cudaDeviceSynchronize();
}
int main() {
initialize();
for ( count = 0; count < 4; count++) {
clock_t begin, end;
begin = clock();
predict();
train();
end = clock();
float CpuTime = (float)(end - begin) / CLOCKS_PER_SEC;
CUDA_CALL(cudaMemcpy(Yh, Y, BREADTH * sizeof(float), cudaMemcpyDeviceToHost));
CUDA_CALL(cudaMemcpy(Dh, pY, BREADTH * sizeof(float), cudaMemcpyDeviceToHost));
calculateError();
printf("TIME: %f\n", CpuTime);
}
freeResources();
return 0;
} | .file "tmpxft_001405c6_00000000-6_deep.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "ITERATION : %d\tLOSS : %f\t"
.text
.globl _Z14calculateErrorv
.type _Z14calculateErrorv, @function
_Z14calculateErrorv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, %eax
pxor %xmm1, %xmm1
leaq Dh(%rip), %rcx
leaq Yh(%rip), %rdx
.L4:
movss (%rcx,%rax), %xmm0
subss (%rdx,%rax), %xmm0
mulss %xmm0, %xmm0
addss %xmm0, %xmm1
addq $4, %rax
cmpq $4000, %rax
jne .L4
pxor %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl count(%rip), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z14calculateErrorv, .-_Z14calculateErrorv
.globl _Z13freeResourcesv
.type _Z13freeResourcesv, @function
_Z13freeResourcesv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq Y(%rip), %rdi
call cudaFree@PLT
movq N(%rip), %rdi
call cudaFree@PLT
movq W(%rip), %rdi
call cudaFree@PLT
movq pY(%rip), %rdi
call cudaFree@PLT
movq U(%rip), %rdi
call cudaFree@PLT
movq V(%rip), %rdi
call cudaFree@PLT
movq R(%rip), %rdi
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z13freeResourcesv, .-_Z13freeResourcesv
.globl _Z28__device_stub__Z9predict_NPfPf
.type _Z28__device_stub__Z9predict_NPfPf, @function
_Z28__device_stub__Z9predict_NPfPf:
.LFB2087:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9predict_NPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z28__device_stub__Z9predict_NPfPf, .-_Z28__device_stub__Z9predict_NPfPf
.globl _Z9predict_NPf
.type _Z9predict_NPf, @function
_Z9predict_NPf:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9predict_NPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z9predict_NPf, .-_Z9predict_NPf
.globl _Z35__device_stub__Z10predict_WNPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10predict_WNPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10predict_WNPfS_S_iPfS_S_i:
.LFB2089:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10predict_WNPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z35__device_stub__Z10predict_WNPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10predict_WNPfS_S_iPfS_S_i
.globl _Z10predict_WNPfS_S_i
.type _Z10predict_WNPfS_S_i, @function
_Z10predict_WNPfS_S_i:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10predict_WNPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z10predict_WNPfS_S_i, .-_Z10predict_WNPfS_S_i
.globl _Z32__device_stub__Z10predict_RiPfiiPfii
.type _Z32__device_stub__Z10predict_RiPfiiPfii, @function
_Z32__device_stub__Z10predict_RiPfiiPfii:
.LFB2091:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10predict_RiPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z32__device_stub__Z10predict_RiPfiiPfii, .-_Z32__device_stub__Z10predict_RiPfiiPfii
.globl _Z10predict_RiPfii
.type _Z10predict_RiPfii, @function
_Z10predict_RiPfii:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10predict_RiPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z10predict_RiPfii, .-_Z10predict_RiPfii
.globl _Z33__device_stub__Z10predict_NkPfS_iPfS_i
.type _Z33__device_stub__Z10predict_NkPfS_iPfS_i, @function
_Z33__device_stub__Z10predict_NkPfS_iPfS_i:
.LFB2093:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10predict_NkPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2093:
.size _Z33__device_stub__Z10predict_NkPfS_iPfS_i, .-_Z33__device_stub__Z10predict_NkPfS_iPfS_i
.globl _Z10predict_NkPfS_i
.type _Z10predict_NkPfS_i, @function
_Z10predict_NkPfS_i:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10predict_NkPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _Z10predict_NkPfS_i, .-_Z10predict_NkPfS_i
.globl _Z32__device_stub__Z10predict_YpPfS_PfS_
.type _Z32__device_stub__Z10predict_YpPfS_PfS_, @function
_Z32__device_stub__Z10predict_YpPfS_PfS_:
.LFB2095:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10predict_YpPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z32__device_stub__Z10predict_YpPfS_PfS_, .-_Z32__device_stub__Z10predict_YpPfS_PfS_
.globl _Z10predict_YpPfS_
.type _Z10predict_YpPfS_, @function
_Z10predict_YpPfS_:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10predict_YpPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z10predict_YpPfS_, .-_Z10predict_YpPfS_
.globl _Z7predictv
.type _Z7predictv, @function
_Z7predictv:
.LFB2061:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $128, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L60
.L50:
call cudaDeviceSynchronize@PLT
movl $1, %r13d
movl $1000, %r14d
jmp .L55
.L60:
movq N(%rip), %rdi
call _Z28__device_stub__Z9predict_NPfPf
jmp .L50
.L64:
leal -1(%r13), %ecx
movq R(%rip), %rdx
movq W(%rip), %rsi
movq N(%rip), %rdi
call _Z35__device_stub__Z10predict_WNPfS_S_iPfS_S_i
jmp .L51
.L52:
call cudaDeviceSynchronize@PLT
addl %r12d, %r12d
leal 1(%rbx), %eax
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
sarl %eax
movl %eax, %ebx
subl $1, %ebp
je .L61
.L53:
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $128, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L52
movl %r12d, %edx
movl %ebx, %esi
movq R(%rip), %rdi
call _Z32__device_stub__Z10predict_RiPfiiPfii
jmp .L52
.L61:
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $128, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L54:
call cudaDeviceSynchronize@PLT
addl $1, %r13d
cmpl $5, %r13d
je .L63
.L55:
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $128, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L64
.L51:
call cudaDeviceSynchronize@PLT
movl $10, %ebp
movl %r14d, %ebx
movl $1, %r12d
jmp .L53
.L62:
movl %r13d, %edx
movq R(%rip), %rsi
movq N(%rip), %rdi
call _Z33__device_stub__Z10predict_NkPfS_iPfS_i
jmp .L54
.L63:
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $128, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L56:
call cudaDeviceSynchronize@PLT
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
movq pY(%rip), %rsi
movq N(%rip), %rdi
call _Z32__device_stub__Z10predict_YpPfS_PfS_
jmp .L56
.cfi_endproc
.LFE2061:
.size _Z7predictv, .-_Z7predictv
.globl _Z30__device_stub__Z7train_VPfS_S_PfS_S_
.type _Z30__device_stub__Z7train_VPfS_S_PfS_S_, @function
_Z30__device_stub__Z7train_VPfS_S_PfS_S_:
.LFB2097:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L70
.L66:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L71
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7train_VPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L66
.L71:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2097:
.size _Z30__device_stub__Z7train_VPfS_S_PfS_S_, .-_Z30__device_stub__Z7train_VPfS_S_PfS_S_
.globl _Z7train_VPfS_S_
.type _Z7train_VPfS_S_, @function
_Z7train_VPfS_S_:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7train_VPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _Z7train_VPfS_S_, .-_Z7train_VPfS_S_
.globl _Z31__device_stub__Z8train_WfPfS_S_PfS_S_
.type _Z31__device_stub__Z8train_WfPfS_S_PfS_S_, @function
_Z31__device_stub__Z8train_WfPfS_S_PfS_S_:
.LFB2099:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L78
.L74:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L79
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L78:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8train_WfPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L74
.L79:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2099:
.size _Z31__device_stub__Z8train_WfPfS_S_PfS_S_, .-_Z31__device_stub__Z8train_WfPfS_S_PfS_S_
.globl _Z8train_WfPfS_S_
.type _Z8train_WfPfS_S_, @function
_Z8train_WfPfS_S_:
.LFB2100:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8train_WfPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2100:
.size _Z8train_WfPfS_S_, .-_Z8train_WfPfS_S_
.globl _Z34__device_stub__Z8train_WNPfS_S_S_iPfS_S_S_i
.type _Z34__device_stub__Z8train_WNPfS_S_S_iPfS_S_S_i, @function
_Z34__device_stub__Z8train_WNPfS_S_S_iPfS_S_S_i:
.LFB2101:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L86
.L82:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L87
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L86:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8train_WNPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L82
.L87:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2101:
.size _Z34__device_stub__Z8train_WNPfS_S_S_iPfS_S_S_i, .-_Z34__device_stub__Z8train_WNPfS_S_S_iPfS_S_S_i
.globl _Z8train_WNPfS_S_S_i
.type _Z8train_WNPfS_S_S_i, @function
_Z8train_WNPfS_S_S_i:
.LFB2102:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z8train_WNPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2102:
.size _Z8train_WNPfS_S_S_i, .-_Z8train_WNPfS_S_S_i
.globl _Z28__device_stub__Z7train_BPfS_PfS_
.type _Z28__device_stub__Z7train_BPfS_PfS_, @function
_Z28__device_stub__Z7train_BPfS_PfS_:
.LFB2103:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L94
.L90:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L95
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L94:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7train_BPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L90
.L95:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2103:
.size _Z28__device_stub__Z7train_BPfS_PfS_, .-_Z28__device_stub__Z7train_BPfS_PfS_
.globl _Z7train_BPfS_
.type _Z7train_BPfS_, @function
_Z7train_BPfS_:
.LFB2104:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7train_BPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2104:
.size _Z7train_BPfS_, .-_Z7train_BPfS_
.globl _Z32__device_stub__Z8train_WhPfS_S_iPfS_S_i
.type _Z32__device_stub__Z8train_WhPfS_S_iPfS_S_i, @function
_Z32__device_stub__Z8train_WhPfS_S_iPfS_S_i:
.LFB2105:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L102
.L98:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L103
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L102:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8train_WhPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L98
.L103:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2105:
.size _Z32__device_stub__Z8train_WhPfS_S_iPfS_S_i, .-_Z32__device_stub__Z8train_WhPfS_S_iPfS_S_i
.globl _Z8train_WhPfS_S_i
.type _Z8train_WhPfS_S_i, @function
_Z8train_WhPfS_S_i:
.LFB2106:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8train_WhPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2106:
.size _Z8train_WhPfS_S_i, .-_Z8train_WhPfS_S_i
.globl _Z5trainv
.type _Z5trainv, @function
_Z5trainv:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $128, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L118
.L107:
call cudaDeviceSynchronize@PLT
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $128, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L119
.L108:
call cudaDeviceSynchronize@PLT
movq V(%rip), %r15
movq U(%rip), %r14
movl $2, %r13d
jmp .L114
.L118:
movq V(%rip), %rdx
movq Y(%rip), %rsi
movq N(%rip), %rdi
call _Z30__device_stub__Z7train_VPfS_S_PfS_S_
jmp .L107
.L119:
movq V(%rip), %rdx
movq W(%rip), %rsi
movq N(%rip), %rdi
call _Z31__device_stub__Z8train_WfPfS_S_PfS_S_
jmp .L108
.L124:
leal 1(%r13), %r8d
movq R(%rip), %rcx
movq %r15, %rdx
movq W(%rip), %rsi
movq N(%rip), %rdi
call _Z34__device_stub__Z8train_WNPfS_S_S_iPfS_S_S_i
jmp .L109
.L110:
call cudaDeviceSynchronize@PLT
addl %r12d, %r12d
leal 1(%rbx), %eax
movl %eax, %ebx
shrl $31, %ebx
addl %eax, %ebx
sarl %ebx
subl $1, %ebp
je .L120
.L111:
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $128, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L110
movl %r12d, %edx
movl %ebx, %esi
movq R(%rip), %rdi
call _Z32__device_stub__Z10predict_RiPfiiPfii
jmp .L110
.L120:
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $128, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L121
.L112:
call cudaDeviceSynchronize@PLT
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $128, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L122
.L113:
call cudaDeviceSynchronize@PLT
subl $1, %r13d
movq %r14, %rax
movq %r15, %r14
cmpl $-1, %r13d
je .L123
movq %rax, %r15
.L114:
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $128, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L124
.L109:
call cudaDeviceSynchronize@PLT
movl $10, %ebp
movl $1000, %ebx
movl $1, %r12d
jmp .L111
.L121:
movq %r14, %rsi
movq R(%rip), %rdi
call _Z28__device_stub__Z7train_BPfS_PfS_
jmp .L112
.L122:
movl %r13d, %ecx
movq %r14, %rdx
movq W(%rip), %rsi
movq N(%rip), %rdi
call _Z32__device_stub__Z8train_WhPfS_S_iPfS_S_i
jmp .L113
.L123:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z5trainv, .-_Z5trainv
.globl _Z32__device_stub__Z9normalizePfS_S_PfS_S_
.type _Z32__device_stub__Z9normalizePfS_S_PfS_S_, @function
_Z32__device_stub__Z9normalizePfS_S_PfS_S_:
.LFB2107:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L129
.L125:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L130
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L129:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9normalizePfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L125
.L130:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2107:
.size _Z32__device_stub__Z9normalizePfS_S_PfS_S_, .-_Z32__device_stub__Z9normalizePfS_S_PfS_S_
.globl _Z9normalizePfS_S_
.type _Z9normalizePfS_S_, @function
_Z9normalizePfS_S_:
.LFB2108:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9normalizePfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2108:
.size _Z9normalizePfS_S_, .-_Z9normalizePfS_S_
.globl _Z10initializev
.type _Z10initializev, @function
_Z10initializev:
.LFB2058:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $16000000, %esi
leaq W(%rip), %rdi
call cudaMalloc@PLT
movl $4000000, %esi
leaq R(%rip), %rdi
call cudaMalloc@PLT
movl $20000, %esi
leaq N(%rip), %rdi
call cudaMalloc@PLT
movl $4000, %esi
leaq Y(%rip), %rdi
call cudaMalloc@PLT
movl $4000, %esi
leaq pY(%rip), %rdi
call cudaMalloc@PLT
movl $4000, %esi
leaq U(%rip), %rdi
call cudaMalloc@PLT
movl $4000, %esi
leaq V(%rip), %rdi
call cudaMalloc@PLT
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $128, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L136
.L134:
call cudaDeviceSynchronize@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L136:
.cfi_restore_state
movq Y(%rip), %rdx
movq N(%rip), %rsi
movq W(%rip), %rdi
call _Z32__device_stub__Z9normalizePfS_S_PfS_S_
jmp .L134
.cfi_endproc
.LFE2058:
.size _Z10initializev, .-_Z10initializev
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/ShamsArfeen/Deep-Learning-with-CUDA/main/deep.cu"
.section .rodata.str1.1
.LC4:
.string "Error at %s:%d\n"
.LC5:
.string "TIME: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
call _Z10initializev
movl $0, count(%rip)
leaq Yh(%rip), %rbx
leaq Dh(%rip), %rbp
leaq .LC5(%rip), %r12
.L141:
call clock@PLT
movq %rax, %r13
call _Z7predictv
call _Z5trainv
call clock@PLT
subq %r13, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC2(%rip), %xmm0
movss %xmm0, 12(%rsp)
movl $2, %ecx
movl $4000, %edx
movq Y(%rip), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L144
movl $2, %ecx
movl $4000, %edx
movq pY(%rip), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L145
call _Z14calculateErrorv
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl count(%rip), %eax
addl $1, %eax
movl %eax, count(%rip)
cmpl $3, %eax
jle .L141
call _Z13freeResourcesv
movl $0, %eax
.L137:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L144:
.cfi_restore_state
movl $318, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L137
.L145:
movl $319, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L137
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z9normalizePfS_S_"
.LC7:
.string "_Z8train_WhPfS_S_i"
.LC8:
.string "_Z7train_BPfS_"
.LC9:
.string "_Z8train_WNPfS_S_S_i"
.LC10:
.string "_Z8train_WfPfS_S_"
.LC11:
.string "_Z7train_VPfS_S_"
.LC12:
.string "_Z10predict_YpPfS_"
.LC13:
.string "_Z10predict_NkPfS_i"
.LC14:
.string "_Z10predict_RiPfii"
.LC15:
.string "_Z10predict_WNPfS_S_i"
.LC16:
.string "_Z9predict_NPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2110:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9normalizePfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z8train_WhPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z7train_BPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z8train_WNPfS_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z8train_WfPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z7train_VPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z10predict_YpPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z10predict_NkPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z10predict_RiPfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z10predict_WNPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z9predict_NPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2110:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl count
.bss
.align 4
.type count, @object
.size count, 4
count:
.zero 4
.globl Dh
.align 32
.type Dh, @object
.size Dh, 4000
Dh:
.zero 4000
.globl Yh
.align 32
.type Yh, @object
.size Yh, 4000
Yh:
.zero 4000
.globl V
.align 8
.type V, @object
.size V, 8
V:
.zero 8
.globl U
.align 8
.type U, @object
.size U, 8
U:
.zero 8
.globl pY
.align 8
.type pY, @object
.size pY, 8
pY:
.zero 8
.globl Y
.align 8
.type Y, @object
.size Y, 8
Y:
.zero 8
.globl N
.align 8
.type N, @object
.size N, 8
N:
.zero 8
.globl R
.align 8
.type R, @object
.size R, 8
R:
.zero 8
.globl W
.align 8
.type W, @object
.size W, 8
W:
.zero 8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
#include <cuda.h>
#include <curand.h>
#define CUDA_CALL(x) do { if((x)!=cudaSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define DEPTH 5 // no of layers
#define BREADTH 1000 // nodes per layer
#define RATE 0.0001 // learning rate
#define NDIM(a,b) ((a)*BREADTH+(b))
#define WDIM(a,b,c) ((a)*BREADTH*BREADTH+(b)*BREADTH+(c))
float *W, *R; // [DEPTH-1][BREADTH][BREADTH] W_kij : weight of edge b/w jth and ith node from kth layer and k+1th layer resp.
float *N; // [DEPTH][BREADTH] N_ki : jth node in kth layer
float *Y, *pY; // [BREADTH] expected and predicted output vectors
float *U, *V; // [BREADTH] vectors for backpropagation chain-rule
float Yh[BREADTH], Dh[BREADTH]; // host arrays: expected and predicted output
int count = 0;
#define f(x) (tanhf((x))) // activation function
#define df(y) (1 - (y) * (y)) // derivative of activation function in y terms
__global__ void predict_N( float *N) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i;
// erase all nodes except first layer
for ( i = tid + BREADTH ; i < BREADTH * DEPTH ; i += stride )
N[i] = 0;
}
__global__ void predict_WN( float *N, float *W, float *R, int k) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int h;
// matrix-vector multiplication W*N b/w k-1th and kth layer
int wIndex = k * BREADTH * BREADTH;
int nIndex = k * BREADTH;
for ( h = tid ; h < BREADTH * BREADTH ; h += stride ) {
int j = h % BREADTH;
R[h] = W[wIndex + h] * N[nIndex + j];
}
}
__global__ void predict_Ri( float *R, int n, int j) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i;
for ( i = tid % BREADTH ; i < BREADTH ; i += stride ) {
int itid = tid / BREADTH;
int istride = stride / BREADTH;
istride += (istride == 0);
int rIndex = i * BREADTH;
for ( int h = 2 * j * itid; h < j * (n - 1); h += 2 * j * istride)
R[rIndex + h] += R[rIndex + h + j];
}
}
__global__ void predict_Nk( float *N, float *R, int k) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i;
for ( i = tid; i < BREADTH; i += stride )
N[NDIM(k,i)] = f( R[NDIM(i,0)]);
}
__global__ void predict_Yp( float *N, float *pY) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i;
for ( i = tid; i < BREADTH; i += stride )
pY[i] = N[NDIM(DEPTH-1,i)];
}
__global__ void train_V( float *N, float *Y, float *V) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int q = DEPTH - 2;
// caching chain-rule calculation in vector to aid in backpropagation
for ( int i = tid; i < BREADTH; i += stride ) {
V[i] = (N[NDIM(q+1,i)] - Y[i]) * df( N[NDIM(q+1,i)]);
}
}
__global__ void train_Wf( float *N, float *W, float *V) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int q = DEPTH - 2, h;
// update weights of outer layer
for ( h = tid; h < BREADTH * BREADTH; h += stride ) {
int i = h / BREADTH;
int j = h % BREADTH;
W[WDIM(q,i,j)] -= (float)RATE * V[i] * N[NDIM(q,j)];
}
}
__global__ void train_WN( float *N, float *W, float *A, float *R, int k) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int h;
// matrix-vector multiplication W*N b/w k-1th and kth layer
int wIndex = k * BREADTH * BREADTH;
int nIndex = k * BREADTH;
for ( h = tid ; h < BREADTH * BREADTH ; h += stride ) {
int j = h % BREADTH;
int i = h / BREADTH;
R[NDIM(j,i)] = A[i] * W[wIndex + h] * df( N[nIndex + j]);
}
}
__global__ void train_B( float *R, float *B) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i;
for ( i = tid; i < BREADTH; i += stride )
B[i] = R[NDIM(i,0)];
}
__global__ void train_Wh( float *N, float *W, float *A, int k) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int h;
// matrix-vector multiplication W*N b/w k-1th and kth layer
int wIndex = k * BREADTH * BREADTH;
int nIndex = k * BREADTH;
for ( h = tid ; h < BREADTH * BREADTH ; h += stride ) {
int j = h % BREADTH;
int i = h / BREADTH;
W[wIndex + h] -= (float)RATE * A[i] * N[nIndex + j];
}
}
void train() {
train_V<<<128, 32>>>( N, Y, V);
cudaDeviceSynchronize();
train_Wf<<<128, 32>>>( N, W, V);
cudaDeviceSynchronize();
int q = DEPTH - 2;
float *A = &V[0], *B = &U[0];
float *temp;
// updating weights of hidden layers (backpropagation)
for ( int k = q - 1; k >= 0; k-- ) {
// chain-rule expansion by multiplying with next layer's weight matrix and
// derivative of activation function on the same layer's nodes
train_WN<<<128, 32>>>( N, W, A, R, k+1);
cudaDeviceSynchronize();
int j = 1;
int n = BREADTH;
while ( n > 1) {
predict_Ri<<<128, 32>>>( R, n, j);
cudaDeviceSynchronize();
j *= 2;
n = (n+1)/2;
}
train_B<<<128, 32>>>( R, B);
cudaDeviceSynchronize();
temp = B; B = A; A = temp;
// adjust weights by gradient descent
train_Wh<<<128, 32>>>( N, W, A, k);
cudaDeviceSynchronize();
}
}
__global__ void normalize( float *W, float *N, float *Y) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i, w = (DEPTH-1) * BREADTH * BREADTH;
for ( i = tid; i < w; i+= stride)
W[i] = 1/ (float)BREADTH;
for ( i = tid; i < BREADTH; i+= stride)
N[i] = i/ (float)BREADTH;
for ( i = tid; i < BREADTH; i+= stride)
Y[i] = i/ (float)BREADTH;
}
void initialize() {
int w = (DEPTH-1) * BREADTH * BREADTH;
// device memory allocation of global arrays
cudaMalloc( (void**)(&W), sizeof(float) * w);
cudaMalloc( (void**)(&R), sizeof(float) * BREADTH * BREADTH);
cudaMalloc( (void**)(&N), sizeof(float) * DEPTH * BREADTH);
cudaMalloc( (void**)(&Y), sizeof(float) * BREADTH);
cudaMalloc( (void**)(&pY), sizeof(float) * BREADTH);
cudaMalloc( (void**)(&U), sizeof(float) * BREADTH);
cudaMalloc( (void**)(&V), sizeof(float) * BREADTH);
/*
// random number generator
curandGenerator_t gen;
// Create pseudo-random number generator
curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_DEFAULT);
// Set seed
curandSetPseudoRandomGeneratorSeed(gen, time(0));
// Generate floats on device
curandGenerateUniform(gen, W, w);
curandGenerateUniform(gen, N, BREADTH * DEPTH);
curandGenerateUniform(gen, Y, BREADTH);
curandDestroyGenerator(gen);
*/
normalize<<<128, 32>>>(W, N, Y);
cudaDeviceSynchronize();
}
void calculateError() {
float err = 0, dY;
// dY : difference b/w expected and predicted output, and
// err : sum of squares of dY
for ( int i = 0 ; i < BREADTH ; i++ ) {
dY = (Dh[i] - Yh[i]);
err += dY * dY;
}
printf("ITERATION : %d\tLOSS : %f\t", count, err);
}
void freeResources() {
cudaFree(Y);
cudaFree(N);
cudaFree(W);
cudaFree(pY);
cudaFree(U);
cudaFree(V);
cudaFree(R);
}
void predict() {
predict_N<<<128, 32>>>(N);
cudaDeviceSynchronize();
for ( int k = 1; k < DEPTH ; k++ ) {
predict_WN<<<128, 32>>>( N, W, R, k-1);
cudaDeviceSynchronize();
int j = 1;
int n = BREADTH;
while ( n > 1) {
predict_Ri<<<128, 32>>>( R, n, j);
cudaDeviceSynchronize();
j *= 2;
n = (n+1)/2;
}
predict_Nk<<<128, 32>>>( N, R, k);
cudaDeviceSynchronize();
}
predict_Yp<<<128, 32>>>( N, pY);
cudaDeviceSynchronize();
}
int main() {
initialize();
for ( count = 0; count < 4; count++) {
clock_t begin, end;
begin = clock();
predict();
train();
end = clock();
float CpuTime = (float)(end - begin) / CLOCKS_PER_SEC;
CUDA_CALL(cudaMemcpy(Yh, Y, BREADTH * sizeof(float), cudaMemcpyDeviceToHost));
CUDA_CALL(cudaMemcpy(Dh, pY, BREADTH * sizeof(float), cudaMemcpyDeviceToHost));
calculateError();
printf("TIME: %f\n", CpuTime);
}
freeResources();
return 0;
} | #include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#define CUDA_CALL(x) do { if((x)!=hipSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define DEPTH 5 // no of layers
#define BREADTH 1000 // nodes per layer
#define RATE 0.0001 // learning rate
#define NDIM(a,b) ((a)*BREADTH+(b))
#define WDIM(a,b,c) ((a)*BREADTH*BREADTH+(b)*BREADTH+(c))
float *W, *R; // [DEPTH-1][BREADTH][BREADTH] W_kij : weight of edge b/w jth and ith node from kth layer and k+1th layer resp.
float *N; // [DEPTH][BREADTH] N_ki : jth node in kth layer
float *Y, *pY; // [BREADTH] expected and predicted output vectors
float *U, *V; // [BREADTH] vectors for backpropagation chain-rule
float Yh[BREADTH], Dh[BREADTH]; // host arrays: expected and predicted output
int count = 0;
#define f(x) (tanhf((x))) // activation function
#define df(y) (1 - (y) * (y)) // derivative of activation function in y terms
__global__ void predict_N( float *N) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i;
// erase all nodes except first layer
for ( i = tid + BREADTH ; i < BREADTH * DEPTH ; i += stride )
N[i] = 0;
}
__global__ void predict_WN( float *N, float *W, float *R, int k) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int h;
// matrix-vector multiplication W*N b/w k-1th and kth layer
int wIndex = k * BREADTH * BREADTH;
int nIndex = k * BREADTH;
for ( h = tid ; h < BREADTH * BREADTH ; h += stride ) {
int j = h % BREADTH;
R[h] = W[wIndex + h] * N[nIndex + j];
}
}
__global__ void predict_Ri( float *R, int n, int j) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i;
for ( i = tid % BREADTH ; i < BREADTH ; i += stride ) {
int itid = tid / BREADTH;
int istride = stride / BREADTH;
istride += (istride == 0);
int rIndex = i * BREADTH;
for ( int h = 2 * j * itid; h < j * (n - 1); h += 2 * j * istride)
R[rIndex + h] += R[rIndex + h + j];
}
}
__global__ void predict_Nk( float *N, float *R, int k) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i;
for ( i = tid; i < BREADTH; i += stride )
N[NDIM(k,i)] = f( R[NDIM(i,0)]);
}
__global__ void predict_Yp( float *N, float *pY) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i;
for ( i = tid; i < BREADTH; i += stride )
pY[i] = N[NDIM(DEPTH-1,i)];
}
__global__ void train_V( float *N, float *Y, float *V) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int q = DEPTH - 2;
// caching chain-rule calculation in vector to aid in backpropagation
for ( int i = tid; i < BREADTH; i += stride ) {
V[i] = (N[NDIM(q+1,i)] - Y[i]) * df( N[NDIM(q+1,i)]);
}
}
__global__ void train_Wf( float *N, float *W, float *V) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int q = DEPTH - 2, h;
// update weights of outer layer
for ( h = tid; h < BREADTH * BREADTH; h += stride ) {
int i = h / BREADTH;
int j = h % BREADTH;
W[WDIM(q,i,j)] -= (float)RATE * V[i] * N[NDIM(q,j)];
}
}
__global__ void train_WN( float *N, float *W, float *A, float *R, int k) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int h;
// matrix-vector multiplication W*N b/w k-1th and kth layer
int wIndex = k * BREADTH * BREADTH;
int nIndex = k * BREADTH;
for ( h = tid ; h < BREADTH * BREADTH ; h += stride ) {
int j = h % BREADTH;
int i = h / BREADTH;
R[NDIM(j,i)] = A[i] * W[wIndex + h] * df( N[nIndex + j]);
}
}
__global__ void train_B( float *R, float *B) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i;
for ( i = tid; i < BREADTH; i += stride )
B[i] = R[NDIM(i,0)];
}
__global__ void train_Wh( float *N, float *W, float *A, int k) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int h;
// matrix-vector multiplication W*N b/w k-1th and kth layer
int wIndex = k * BREADTH * BREADTH;
int nIndex = k * BREADTH;
for ( h = tid ; h < BREADTH * BREADTH ; h += stride ) {
int j = h % BREADTH;
int i = h / BREADTH;
W[wIndex + h] -= (float)RATE * A[i] * N[nIndex + j];
}
}
void train() {
train_V<<<128, 32>>>( N, Y, V);
hipDeviceSynchronize();
train_Wf<<<128, 32>>>( N, W, V);
hipDeviceSynchronize();
int q = DEPTH - 2;
float *A = &V[0], *B = &U[0];
float *temp;
// updating weights of hidden layers (backpropagation)
for ( int k = q - 1; k >= 0; k-- ) {
// chain-rule expansion by multiplying with next layer's weight matrix and
// derivative of activation function on the same layer's nodes
train_WN<<<128, 32>>>( N, W, A, R, k+1);
hipDeviceSynchronize();
int j = 1;
int n = BREADTH;
while ( n > 1) {
predict_Ri<<<128, 32>>>( R, n, j);
hipDeviceSynchronize();
j *= 2;
n = (n+1)/2;
}
train_B<<<128, 32>>>( R, B);
hipDeviceSynchronize();
temp = B; B = A; A = temp;
// adjust weights by gradient descent
train_Wh<<<128, 32>>>( N, W, A, k);
hipDeviceSynchronize();
}
}
__global__ void normalize( float *W, float *N, float *Y) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i, w = (DEPTH-1) * BREADTH * BREADTH;
for ( i = tid; i < w; i+= stride)
W[i] = 1/ (float)BREADTH;
for ( i = tid; i < BREADTH; i+= stride)
N[i] = i/ (float)BREADTH;
for ( i = tid; i < BREADTH; i+= stride)
Y[i] = i/ (float)BREADTH;
}
void initialize() {
int w = (DEPTH-1) * BREADTH * BREADTH;
// device memory allocation of global arrays
hipMalloc( (void**)(&W), sizeof(float) * w);
hipMalloc( (void**)(&R), sizeof(float) * BREADTH * BREADTH);
hipMalloc( (void**)(&N), sizeof(float) * DEPTH * BREADTH);
hipMalloc( (void**)(&Y), sizeof(float) * BREADTH);
hipMalloc( (void**)(&pY), sizeof(float) * BREADTH);
hipMalloc( (void**)(&U), sizeof(float) * BREADTH);
hipMalloc( (void**)(&V), sizeof(float) * BREADTH);
/*
// random number generator
curandGenerator_t gen;
// Create pseudo-random number generator
curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_DEFAULT);
// Set seed
curandSetPseudoRandomGeneratorSeed(gen, time(0));
// Generate floats on device
curandGenerateUniform(gen, W, w);
curandGenerateUniform(gen, N, BREADTH * DEPTH);
curandGenerateUniform(gen, Y, BREADTH);
curandDestroyGenerator(gen);
*/
normalize<<<128, 32>>>(W, N, Y);
hipDeviceSynchronize();
}
void calculateError() {
float err = 0, dY;
// dY : difference b/w expected and predicted output, and
// err : sum of squares of dY
for ( int i = 0 ; i < BREADTH ; i++ ) {
dY = (Dh[i] - Yh[i]);
err += dY * dY;
}
printf("ITERATION : %d\tLOSS : %f\t", count, err);
}
void freeResources() {
hipFree(Y);
hipFree(N);
hipFree(W);
hipFree(pY);
hipFree(U);
hipFree(V);
hipFree(R);
}
void predict() {
predict_N<<<128, 32>>>(N);
hipDeviceSynchronize();
for ( int k = 1; k < DEPTH ; k++ ) {
predict_WN<<<128, 32>>>( N, W, R, k-1);
hipDeviceSynchronize();
int j = 1;
int n = BREADTH;
while ( n > 1) {
predict_Ri<<<128, 32>>>( R, n, j);
hipDeviceSynchronize();
j *= 2;
n = (n+1)/2;
}
predict_Nk<<<128, 32>>>( N, R, k);
hipDeviceSynchronize();
}
predict_Yp<<<128, 32>>>( N, pY);
hipDeviceSynchronize();
}
int main() {
initialize();
for ( count = 0; count < 4; count++) {
clock_t begin, end;
begin = clock();
predict();
train();
end = clock();
float CpuTime = (float)(end - begin) / CLOCKS_PER_SEC;
CUDA_CALL(hipMemcpy(Yh, Y, BREADTH * sizeof(float), hipMemcpyDeviceToHost));
CUDA_CALL(hipMemcpy(Dh, pY, BREADTH * sizeof(float), hipMemcpyDeviceToHost));
calculateError();
printf("TIME: %f\n", CpuTime);
}
freeResources();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#define CUDA_CALL(x) do { if((x)!=hipSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define DEPTH 5 // no of layers
#define BREADTH 1000 // nodes per layer
#define RATE 0.0001 // learning rate
#define NDIM(a,b) ((a)*BREADTH+(b))
#define WDIM(a,b,c) ((a)*BREADTH*BREADTH+(b)*BREADTH+(c))
float *W, *R; // [DEPTH-1][BREADTH][BREADTH] W_kij : weight of edge b/w jth and ith node from kth layer and k+1th layer resp.
float *N; // [DEPTH][BREADTH] N_ki : jth node in kth layer
float *Y, *pY; // [BREADTH] expected and predicted output vectors
float *U, *V; // [BREADTH] vectors for backpropagation chain-rule
float Yh[BREADTH], Dh[BREADTH]; // host arrays: expected and predicted output
int count = 0;
#define f(x) (tanhf((x))) // activation function
#define df(y) (1 - (y) * (y)) // derivative of activation function in y terms
__global__ void predict_N( float *N) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i;
// erase all nodes except first layer
for ( i = tid + BREADTH ; i < BREADTH * DEPTH ; i += stride )
N[i] = 0;
}
__global__ void predict_WN( float *N, float *W, float *R, int k) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int h;
// matrix-vector multiplication W*N b/w k-1th and kth layer
int wIndex = k * BREADTH * BREADTH;
int nIndex = k * BREADTH;
for ( h = tid ; h < BREADTH * BREADTH ; h += stride ) {
int j = h % BREADTH;
R[h] = W[wIndex + h] * N[nIndex + j];
}
}
__global__ void predict_Ri( float *R, int n, int j) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i;
for ( i = tid % BREADTH ; i < BREADTH ; i += stride ) {
int itid = tid / BREADTH;
int istride = stride / BREADTH;
istride += (istride == 0);
int rIndex = i * BREADTH;
for ( int h = 2 * j * itid; h < j * (n - 1); h += 2 * j * istride)
R[rIndex + h] += R[rIndex + h + j];
}
}
__global__ void predict_Nk( float *N, float *R, int k) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i;
for ( i = tid; i < BREADTH; i += stride )
N[NDIM(k,i)] = f( R[NDIM(i,0)]);
}
__global__ void predict_Yp( float *N, float *pY) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i;
for ( i = tid; i < BREADTH; i += stride )
pY[i] = N[NDIM(DEPTH-1,i)];
}
__global__ void train_V( float *N, float *Y, float *V) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int q = DEPTH - 2;
// caching chain-rule calculation in vector to aid in backpropagation
for ( int i = tid; i < BREADTH; i += stride ) {
V[i] = (N[NDIM(q+1,i)] - Y[i]) * df( N[NDIM(q+1,i)]);
}
}
__global__ void train_Wf( float *N, float *W, float *V) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int q = DEPTH - 2, h;
// update weights of outer layer
for ( h = tid; h < BREADTH * BREADTH; h += stride ) {
int i = h / BREADTH;
int j = h % BREADTH;
W[WDIM(q,i,j)] -= (float)RATE * V[i] * N[NDIM(q,j)];
}
}
__global__ void train_WN( float *N, float *W, float *A, float *R, int k) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int h;
// matrix-vector multiplication W*N b/w k-1th and kth layer
int wIndex = k * BREADTH * BREADTH;
int nIndex = k * BREADTH;
for ( h = tid ; h < BREADTH * BREADTH ; h += stride ) {
int j = h % BREADTH;
int i = h / BREADTH;
R[NDIM(j,i)] = A[i] * W[wIndex + h] * df( N[nIndex + j]);
}
}
__global__ void train_B( float *R, float *B) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i;
for ( i = tid; i < BREADTH; i += stride )
B[i] = R[NDIM(i,0)];
}
__global__ void train_Wh( float *N, float *W, float *A, int k) { // feedforward pass algorithm
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int h;
// matrix-vector multiplication W*N b/w k-1th and kth layer
int wIndex = k * BREADTH * BREADTH;
int nIndex = k * BREADTH;
for ( h = tid ; h < BREADTH * BREADTH ; h += stride ) {
int j = h % BREADTH;
int i = h / BREADTH;
W[wIndex + h] -= (float)RATE * A[i] * N[nIndex + j];
}
}
void train() {
train_V<<<128, 32>>>( N, Y, V);
hipDeviceSynchronize();
train_Wf<<<128, 32>>>( N, W, V);
hipDeviceSynchronize();
int q = DEPTH - 2;
float *A = &V[0], *B = &U[0];
float *temp;
// updating weights of hidden layers (backpropagation)
for ( int k = q - 1; k >= 0; k-- ) {
// chain-rule expansion by multiplying with next layer's weight matrix and
// derivative of activation function on the same layer's nodes
train_WN<<<128, 32>>>( N, W, A, R, k+1);
hipDeviceSynchronize();
int j = 1;
int n = BREADTH;
while ( n > 1) {
predict_Ri<<<128, 32>>>( R, n, j);
hipDeviceSynchronize();
j *= 2;
n = (n+1)/2;
}
train_B<<<128, 32>>>( R, B);
hipDeviceSynchronize();
temp = B; B = A; A = temp;
// adjust weights by gradient descent
train_Wh<<<128, 32>>>( N, W, A, k);
hipDeviceSynchronize();
}
}
__global__ void normalize( float *W, float *N, float *Y) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
int i, w = (DEPTH-1) * BREADTH * BREADTH;
for ( i = tid; i < w; i+= stride)
W[i] = 1/ (float)BREADTH;
for ( i = tid; i < BREADTH; i+= stride)
N[i] = i/ (float)BREADTH;
for ( i = tid; i < BREADTH; i+= stride)
Y[i] = i/ (float)BREADTH;
}
void initialize() {
int w = (DEPTH-1) * BREADTH * BREADTH;
// device memory allocation of global arrays
hipMalloc( (void**)(&W), sizeof(float) * w);
hipMalloc( (void**)(&R), sizeof(float) * BREADTH * BREADTH);
hipMalloc( (void**)(&N), sizeof(float) * DEPTH * BREADTH);
hipMalloc( (void**)(&Y), sizeof(float) * BREADTH);
hipMalloc( (void**)(&pY), sizeof(float) * BREADTH);
hipMalloc( (void**)(&U), sizeof(float) * BREADTH);
hipMalloc( (void**)(&V), sizeof(float) * BREADTH);
/*
// random number generator
curandGenerator_t gen;
// Create pseudo-random number generator
curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_DEFAULT);
// Set seed
curandSetPseudoRandomGeneratorSeed(gen, time(0));
// Generate floats on device
curandGenerateUniform(gen, W, w);
curandGenerateUniform(gen, N, BREADTH * DEPTH);
curandGenerateUniform(gen, Y, BREADTH);
curandDestroyGenerator(gen);
*/
normalize<<<128, 32>>>(W, N, Y);
hipDeviceSynchronize();
}
void calculateError() {
float err = 0, dY;
// dY : difference b/w expected and predicted output, and
// err : sum of squares of dY
for ( int i = 0 ; i < BREADTH ; i++ ) {
dY = (Dh[i] - Yh[i]);
err += dY * dY;
}
printf("ITERATION : %d\tLOSS : %f\t", count, err);
}
void freeResources() {
hipFree(Y);
hipFree(N);
hipFree(W);
hipFree(pY);
hipFree(U);
hipFree(V);
hipFree(R);
}
void predict() {
predict_N<<<128, 32>>>(N);
hipDeviceSynchronize();
for ( int k = 1; k < DEPTH ; k++ ) {
predict_WN<<<128, 32>>>( N, W, R, k-1);
hipDeviceSynchronize();
int j = 1;
int n = BREADTH;
while ( n > 1) {
predict_Ri<<<128, 32>>>( R, n, j);
hipDeviceSynchronize();
j *= 2;
n = (n+1)/2;
}
predict_Nk<<<128, 32>>>( N, R, k);
hipDeviceSynchronize();
}
predict_Yp<<<128, 32>>>( N, pY);
hipDeviceSynchronize();
}
int main() {
initialize();
for ( count = 0; count < 4; count++) {
clock_t begin, end;
begin = clock();
predict();
train();
end = clock();
float CpuTime = (float)(end - begin) / CLOCKS_PER_SEC;
CUDA_CALL(hipMemcpy(Yh, Y, BREADTH * sizeof(float), hipMemcpyDeviceToHost));
CUDA_CALL(hipMemcpy(Dh, pY, BREADTH * sizeof(float), hipMemcpyDeviceToHost));
calculateError();
printf("TIME: %f\n", CpuTime);
}
freeResources();
return 0;
} | .text
.file "deep.hip"
.globl _Z24__device_stub__predict_NPf # -- Begin function _Z24__device_stub__predict_NPf
.p2align 4, 0x90
.type _Z24__device_stub__predict_NPf,@function
_Z24__device_stub__predict_NPf: # @_Z24__device_stub__predict_NPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z9predict_NPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z24__device_stub__predict_NPf, .Lfunc_end0-_Z24__device_stub__predict_NPf
.cfi_endproc
# -- End function
.globl _Z25__device_stub__predict_WNPfS_S_i # -- Begin function _Z25__device_stub__predict_WNPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__predict_WNPfS_S_i,@function
_Z25__device_stub__predict_WNPfS_S_i: # @_Z25__device_stub__predict_WNPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10predict_WNPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__predict_WNPfS_S_i, .Lfunc_end1-_Z25__device_stub__predict_WNPfS_S_i
.cfi_endproc
# -- End function
.globl _Z25__device_stub__predict_RiPfii # -- Begin function _Z25__device_stub__predict_RiPfii
.p2align 4, 0x90
.type _Z25__device_stub__predict_RiPfii,@function
_Z25__device_stub__predict_RiPfii: # @_Z25__device_stub__predict_RiPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10predict_RiPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z25__device_stub__predict_RiPfii, .Lfunc_end2-_Z25__device_stub__predict_RiPfii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__predict_NkPfS_i # -- Begin function _Z25__device_stub__predict_NkPfS_i
.p2align 4, 0x90
.type _Z25__device_stub__predict_NkPfS_i,@function
_Z25__device_stub__predict_NkPfS_i: # @_Z25__device_stub__predict_NkPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10predict_NkPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z25__device_stub__predict_NkPfS_i, .Lfunc_end3-_Z25__device_stub__predict_NkPfS_i
.cfi_endproc
# -- End function
.globl _Z25__device_stub__predict_YpPfS_ # -- Begin function _Z25__device_stub__predict_YpPfS_
.p2align 4, 0x90
.type _Z25__device_stub__predict_YpPfS_,@function
_Z25__device_stub__predict_YpPfS_: # @_Z25__device_stub__predict_YpPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10predict_YpPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z25__device_stub__predict_YpPfS_, .Lfunc_end4-_Z25__device_stub__predict_YpPfS_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__train_VPfS_S_ # -- Begin function _Z22__device_stub__train_VPfS_S_
.p2align 4, 0x90
.type _Z22__device_stub__train_VPfS_S_,@function
_Z22__device_stub__train_VPfS_S_: # @_Z22__device_stub__train_VPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7train_VPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end5:
.size _Z22__device_stub__train_VPfS_S_, .Lfunc_end5-_Z22__device_stub__train_VPfS_S_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__train_WfPfS_S_ # -- Begin function _Z23__device_stub__train_WfPfS_S_
.p2align 4, 0x90
.type _Z23__device_stub__train_WfPfS_S_,@function
_Z23__device_stub__train_WfPfS_S_: # @_Z23__device_stub__train_WfPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8train_WfPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end6:
.size _Z23__device_stub__train_WfPfS_S_, .Lfunc_end6-_Z23__device_stub__train_WfPfS_S_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__train_WNPfS_S_S_i # -- Begin function _Z23__device_stub__train_WNPfS_S_S_i
.p2align 4, 0x90
.type _Z23__device_stub__train_WNPfS_S_S_i,@function
_Z23__device_stub__train_WNPfS_S_S_i: # @_Z23__device_stub__train_WNPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8train_WNPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end7:
.size _Z23__device_stub__train_WNPfS_S_S_i, .Lfunc_end7-_Z23__device_stub__train_WNPfS_S_S_i
.cfi_endproc
# -- End function
.globl _Z22__device_stub__train_BPfS_ # -- Begin function _Z22__device_stub__train_BPfS_
.p2align 4, 0x90
.type _Z22__device_stub__train_BPfS_,@function
_Z22__device_stub__train_BPfS_: # @_Z22__device_stub__train_BPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7train_BPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end8:
.size _Z22__device_stub__train_BPfS_, .Lfunc_end8-_Z22__device_stub__train_BPfS_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__train_WhPfS_S_i # -- Begin function _Z23__device_stub__train_WhPfS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__train_WhPfS_S_i,@function
_Z23__device_stub__train_WhPfS_S_i: # @_Z23__device_stub__train_WhPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8train_WhPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end9:
.size _Z23__device_stub__train_WhPfS_S_i, .Lfunc_end9-_Z23__device_stub__train_WhPfS_S_i
.cfi_endproc
# -- End function
.globl _Z5trainv # -- Begin function _Z5trainv
.p2align 4, 0x90
.type _Z5trainv,@function
_Z5trainv: # @_Z5trainv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967328, %rbx # imm = 0x100000020
leaq 96(%rbx), %r14
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB10_2
# %bb.1:
movq N(%rip), %rax
movq Y(%rip), %rcx
movq V(%rip), %rdx
movq %rax, 48(%rsp)
movq %rcx, 40(%rsp)
movq %rdx, 32(%rsp)
leaq 48(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rax
movq %rax, 88(%rsp)
leaq 32(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 8(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7train_VPfS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB10_2:
callq hipDeviceSynchronize
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB10_4
# %bb.3:
movq N(%rip), %rax
movq W(%rip), %rcx
movq V(%rip), %rdx
movq %rax, 48(%rsp)
movq %rcx, 40(%rsp)
movq %rdx, 32(%rsp)
leaq 48(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rax
movq %rax, 88(%rsp)
leaq 32(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 8(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8train_WfPfS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB10_4:
callq hipDeviceSynchronize
movq V(%rip), %rax
movl $2, %r13d
movq U(%rip), %rcx
leaq 64(%rsp), %r15
leaq 80(%rsp), %r12
jmp .LBB10_5
.p2align 4, 0x90
.LBB10_15: # in Loop: Header=BB10_5 Depth=1
callq hipDeviceSynchronize
movq %rbp, %rax
movq 144(%rsp), %rcx # 8-byte Reload
subl $1, %r13d
jb .LBB10_16
.LBB10_5: # =>This Loop Header: Depth=1
# Child Loop BB10_8 Depth 2
movq %rcx, 152(%rsp) # 8-byte Spill
movq %rax, %rbp
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB10_7
# %bb.6: # in Loop: Header=BB10_5 Depth=1
movq N(%rip), %rax
movq W(%rip), %rcx
movq R(%rip), %rdx
leal 1(%r13), %esi
movq %rax, 48(%rsp)
movq %rcx, 40(%rsp)
movq %rbp, 32(%rsp)
movq %rdx, 8(%rsp)
movl %esi, 140(%rsp)
leaq 48(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rax
movq %rax, 88(%rsp)
leaq 32(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 140(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rdi
movq %r15, %rsi
leaq 56(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z8train_WNPfS_S_S_i, %edi
movq %r12, %r9
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB10_7: # in Loop: Header=BB10_5 Depth=1
movq %rbp, 144(%rsp) # 8-byte Spill
movq %r13, 160(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
movl $1000, %ebp # imm = 0x3E8
movl $1, %r13d
jmp .LBB10_8
.p2align 4, 0x90
.LBB10_10: # in Loop: Header=BB10_8 Depth=2
callq hipDeviceSynchronize
addl %r13d, %r13d
leal 1(%rbp), %eax
shrl %eax
cmpl $2, %ebp
movl %eax, %ebp
jbe .LBB10_11
.LBB10_8: # Parent Loop BB10_5 Depth=1
# => This Inner Loop Header: Depth=2
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB10_10
# %bb.9: # in Loop: Header=BB10_8 Depth=2
movq R(%rip), %rax
movq %rax, 48(%rsp)
movl %ebp, 8(%rsp)
movl %r13d, 56(%rsp)
leaq 48(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rdi
movq %r15, %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z10predict_RiPfii, %edi
movq %r12, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB10_10
.p2align 4, 0x90
.LBB10_11: # in Loop: Header=BB10_5 Depth=1
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 152(%rsp), %rbp # 8-byte Reload
jne .LBB10_13
# %bb.12: # in Loop: Header=BB10_5 Depth=1
movq R(%rip), %rax
movq %rax, 48(%rsp)
movq %rbp, 40(%rsp)
leaq 48(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rdi
movq %r15, %rsi
leaq 32(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z7train_BPfS_, %edi
movq %r12, %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB10_13: # in Loop: Header=BB10_5 Depth=1
callq hipDeviceSynchronize
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 160(%rsp), %r13 # 8-byte Reload
jne .LBB10_15
# %bb.14: # in Loop: Header=BB10_5 Depth=1
movq N(%rip), %rax
movq W(%rip), %rcx
movq %rax, 48(%rsp)
movq %rcx, 40(%rsp)
movq %rbp, 32(%rsp)
movl %r13d, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rax
movq %rax, 88(%rsp)
leaq 32(%rsp), %rax
movq %rax, 96(%rsp)
leaq 128(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rdi
movq %r15, %rsi
leaq 8(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z8train_WhPfS_S_i, %edi
movq %r12, %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB10_15
.LBB10_16:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end10:
.size _Z5trainv, .Lfunc_end10-_Z5trainv
.cfi_endproc
# -- End function
.globl _Z24__device_stub__normalizePfS_S_ # -- Begin function _Z24__device_stub__normalizePfS_S_
.p2align 4, 0x90
.type _Z24__device_stub__normalizePfS_S_,@function
_Z24__device_stub__normalizePfS_S_: # @_Z24__device_stub__normalizePfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9normalizePfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end11:
.size _Z24__device_stub__normalizePfS_S_, .Lfunc_end11-_Z24__device_stub__normalizePfS_S_
.cfi_endproc
# -- End function
.globl _Z10initializev # -- Begin function _Z10initializev
.p2align 4, 0x90
.type _Z10initializev,@function
_Z10initializev: # @_Z10initializev
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl $W, %edi
movl $16000000, %esi # imm = 0xF42400
callq hipMalloc
movl $R, %edi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
movl $N, %edi
movl $20000, %esi # imm = 0x4E20
callq hipMalloc
movl $Y, %edi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
movl $pY, %edi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
movl $U, %edi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
movl $V, %edi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
movabsq $4294967328, %rdx # imm = 0x100000020
leaq 96(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB12_2
# %bb.1:
movq W(%rip), %rax
movq N(%rip), %rcx
movq Y(%rip), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9normalizePfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB12_2:
callq hipDeviceSynchronize
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end12:
.size _Z10initializev, .Lfunc_end12-_Z10initializev
.cfi_endproc
# -- End function
.globl _Z14calculateErrorv # -- Begin function _Z14calculateErrorv
.p2align 4, 0x90
.type _Z14calculateErrorv,@function
_Z14calculateErrorv: # @_Z14calculateErrorv
.cfi_startproc
# %bb.0:
xorps %xmm0, %xmm0
movq $-4000, %rax # imm = 0xF060
.p2align 4, 0x90
.LBB13_1: # =>This Inner Loop Header: Depth=1
movss Dh+4000(%rax), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss Yh+4000(%rax), %xmm1
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
addq $4, %rax
jne .LBB13_1
# %bb.2:
movl count(%rip), %esi
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
jmp printf # TAILCALL
.Lfunc_end13:
.size _Z14calculateErrorv, .Lfunc_end13-_Z14calculateErrorv
.cfi_endproc
# -- End function
.globl _Z13freeResourcesv # -- Begin function _Z13freeResourcesv
.p2align 4, 0x90
.type _Z13freeResourcesv,@function
_Z13freeResourcesv: # @_Z13freeResourcesv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq Y(%rip), %rdi
callq hipFree
movq N(%rip), %rdi
callq hipFree
movq W(%rip), %rdi
callq hipFree
movq pY(%rip), %rdi
callq hipFree
movq U(%rip), %rdi
callq hipFree
movq V(%rip), %rdi
callq hipFree
movq R(%rip), %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp hipFree # TAILCALL
.Lfunc_end14:
.size _Z13freeResourcesv, .Lfunc_end14-_Z13freeResourcesv
.cfi_endproc
# -- End function
.globl _Z7predictv # -- Begin function _Z7predictv
.p2align 4, 0x90
.type _Z7predictv,@function
_Z7predictv: # @_Z7predictv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967328, %rbx # imm = 0x100000020
leaq 96(%rbx), %r14
movl $1, %r15d
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB15_2
# %bb.1:
leaq 40(%rsp), %rax
movq N(%rip), %rcx
movq %rcx, 40(%rsp)
movq %rax, (%rsp)
leaq 64(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movq %rsp, %r9
movl $_Z9predict_NPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB15_2:
callq hipDeviceSynchronize
leaq 96(%rsp), %r12
leaq 64(%rsp), %r13
jmp .LBB15_3
.p2align 4, 0x90
.LBB15_9: # in Loop: Header=BB15_3 Depth=1
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 112(%rsp), %r15 # 8-byte Reload
je .LBB15_10
.LBB15_11: # in Loop: Header=BB15_3 Depth=1
callq hipDeviceSynchronize
incl %r15d
cmpl $5, %r15d
je .LBB15_12
.LBB15_3: # =>This Loop Header: Depth=1
# Child Loop BB15_6 Depth 2
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB15_5
# %bb.4: # in Loop: Header=BB15_3 Depth=1
movq N(%rip), %rax
movq W(%rip), %rcx
movq R(%rip), %rdx
leal -1(%r15), %esi
movq %rax, 32(%rsp)
movq %rcx, 24(%rsp)
movq %rdx, (%rsp)
movl %esi, 108(%rsp)
leaq 32(%rsp), %rax
movq %rax, 64(%rsp)
leaq 24(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 108(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 56(%rsp), %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z10predict_WNPfS_S_i, %edi
movq %r13, %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB15_5: # in Loop: Header=BB15_3 Depth=1
movq %r15, 112(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
movl $1000, %r15d # imm = 0x3E8
movl $1, %ebp
jmp .LBB15_6
.p2align 4, 0x90
.LBB15_8: # in Loop: Header=BB15_6 Depth=2
callq hipDeviceSynchronize
addl %ebp, %ebp
leal 1(%r15), %eax
shrl %eax
cmpl $2, %r15d
movl %eax, %r15d
jbe .LBB15_9
.LBB15_6: # Parent Loop BB15_3 Depth=1
# => This Inner Loop Header: Depth=2
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB15_8
# %bb.7: # in Loop: Header=BB15_6 Depth=2
movq R(%rip), %rax
movq %rax, 32(%rsp)
movl %r15d, 56(%rsp)
movl %ebp, 96(%rsp)
leaq 32(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
movq %r12, 80(%rsp)
leaq 8(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 24(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z10predict_RiPfii, %edi
movq %r13, %r9
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB15_8
.p2align 4, 0x90
.LBB15_10: # in Loop: Header=BB15_3 Depth=1
movq N(%rip), %rax
movq R(%rip), %rcx
movq %rax, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r15d, 96(%rsp)
leaq 32(%rsp), %rax
movq %rax, 64(%rsp)
leaq 24(%rsp), %rax
movq %rax, 72(%rsp)
movq %r12, 80(%rsp)
leaq 8(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %rsp, %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z10predict_NkPfS_i, %edi
movq %r13, %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB15_11
.LBB15_12:
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB15_14
# %bb.13:
movq N(%rip), %rax
movq pY(%rip), %rcx
movq %rax, 32(%rsp)
movq %rcx, 24(%rsp)
leaq 32(%rsp), %rax
movq %rax, 64(%rsp)
leaq 24(%rsp), %rax
movq %rax, 72(%rsp)
leaq 8(%rsp), %rdi
leaq 40(%rsp), %rsi
movq %rsp, %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10predict_YpPfS_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB15_14:
callq hipDeviceSynchronize
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end15:
.size _Z7predictv, .Lfunc_end15-_Z7predictv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI16_0:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
callq _Z10initializev
movl $0, count(%rip)
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB16_1: # =>This Loop Header: Depth=1
# Child Loop BB16_6 Depth 2
callq clock
movq %rax, %r14
callq _Z7predictv
callq _Z5trainv
callq clock
subq %r14, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI16_0(%rip), %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
movq Y(%rip), %rsi
movl $Yh, %edi
movl $4000, %edx # imm = 0xFA0
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB16_4
# %bb.2: # in Loop: Header=BB16_1 Depth=1
xorl %ebp, %ebp
movl $.L.str.1, %edi
movl $.L.str.2, %esi
movl $318, %edx # imm = 0x13E
jmp .LBB16_3
.p2align 4, 0x90
.LBB16_4: # in Loop: Header=BB16_1 Depth=1
movq pY(%rip), %rsi
movl $Dh, %edi
movl $4000, %edx # imm = 0xFA0
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB16_5
# %bb.12: # in Loop: Header=BB16_1 Depth=1
xorl %ebp, %ebp
movl $.L.str.1, %edi
movl $.L.str.2, %esi
movl $319, %edx # imm = 0x13F
.LBB16_3: # in Loop: Header=BB16_1 Depth=1
xorl %eax, %eax
callq printf
movl $1, %ebx
testb %bpl, %bpl
je .LBB16_11
.LBB16_9: # in Loop: Header=BB16_1 Depth=1
movl count(%rip), %eax
leal 1(%rax), %ecx
movl %ecx, count(%rip)
cmpl $3, %eax
jl .LBB16_1
jmp .LBB16_10
.LBB16_5: # %.preheader.preheader
# in Loop: Header=BB16_1 Depth=1
xorps %xmm0, %xmm0
movq $-4000, %rax # imm = 0xF060
.p2align 4, 0x90
.LBB16_6: # %.preheader
# Parent Loop BB16_1 Depth=1
# => This Inner Loop Header: Depth=2
movss Dh+4000(%rax), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss Yh+4000(%rax), %xmm1
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
addq $4, %rax
jne .LBB16_6
# %bb.7: # %_Z14calculateErrorv.exit
# in Loop: Header=BB16_1 Depth=1
movl count(%rip), %esi
cvtss2sd %xmm0, %xmm0
movb $1, %bpl
movl $.L.str, %edi
movb $1, %al
callq printf
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
testb %bpl, %bpl
jne .LBB16_9
jmp .LBB16_11
.LBB16_10:
movq Y(%rip), %rdi
callq hipFree
movq N(%rip), %rdi
callq hipFree
movq W(%rip), %rdi
callq hipFree
movq pY(%rip), %rdi
callq hipFree
movq U(%rip), %rdi
callq hipFree
movq V(%rip), %rdi
callq hipFree
movq R(%rip), %rdi
callq hipFree
xorl %ebx, %ebx
.LBB16_11: # %.loopexit
movl %ebx, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end16:
.size main, .Lfunc_end16-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB17_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB17_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9predict_NPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10predict_WNPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10predict_RiPfii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10predict_NkPfS_i, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10predict_YpPfS_, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7train_VPfS_S_, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8train_WfPfS_S_, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8train_WNPfS_S_S_i, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7train_BPfS_, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8train_WhPfS_S_i, %esi
movl $.L__unnamed_10, %edx
movl $.L__unnamed_10, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9normalizePfS_S_, %esi
movl $.L__unnamed_11, %edx
movl $.L__unnamed_11, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end17:
.size __hip_module_ctor, .Lfunc_end17-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB18_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB18_2:
retq
.Lfunc_end18:
.size __hip_module_dtor, .Lfunc_end18-__hip_module_dtor
.cfi_endproc
# -- End function
.type W,@object # @W
.bss
.globl W
.p2align 3, 0x0
W:
.quad 0
.size W, 8
.type R,@object # @R
.globl R
.p2align 3, 0x0
R:
.quad 0
.size R, 8
.type N,@object # @N
.globl N
.p2align 3, 0x0
N:
.quad 0
.size N, 8
.type Y,@object # @Y
.globl Y
.p2align 3, 0x0
Y:
.quad 0
.size Y, 8
.type pY,@object # @pY
.globl pY
.p2align 3, 0x0
pY:
.quad 0
.size pY, 8
.type U,@object # @U
.globl U
.p2align 3, 0x0
U:
.quad 0
.size U, 8
.type V,@object # @V
.globl V
.p2align 3, 0x0
V:
.quad 0
.size V, 8
.type Yh,@object # @Yh
.globl Yh
.p2align 4, 0x0
Yh:
.zero 4000
.size Yh, 4000
.type Dh,@object # @Dh
.globl Dh
.p2align 4, 0x0
Dh:
.zero 4000
.size Dh, 4000
.type count,@object # @count
.globl count
.p2align 2, 0x0
count:
.long 0 # 0x0
.size count, 4
.type _Z9predict_NPf,@object # @_Z9predict_NPf
.section .rodata,"a",@progbits
.globl _Z9predict_NPf
.p2align 3, 0x0
_Z9predict_NPf:
.quad _Z24__device_stub__predict_NPf
.size _Z9predict_NPf, 8
.type _Z10predict_WNPfS_S_i,@object # @_Z10predict_WNPfS_S_i
.globl _Z10predict_WNPfS_S_i
.p2align 3, 0x0
_Z10predict_WNPfS_S_i:
.quad _Z25__device_stub__predict_WNPfS_S_i
.size _Z10predict_WNPfS_S_i, 8
.type _Z10predict_RiPfii,@object # @_Z10predict_RiPfii
.globl _Z10predict_RiPfii
.p2align 3, 0x0
_Z10predict_RiPfii:
.quad _Z25__device_stub__predict_RiPfii
.size _Z10predict_RiPfii, 8
.type _Z10predict_NkPfS_i,@object # @_Z10predict_NkPfS_i
.globl _Z10predict_NkPfS_i
.p2align 3, 0x0
_Z10predict_NkPfS_i:
.quad _Z25__device_stub__predict_NkPfS_i
.size _Z10predict_NkPfS_i, 8
.type _Z10predict_YpPfS_,@object # @_Z10predict_YpPfS_
.globl _Z10predict_YpPfS_
.p2align 3, 0x0
_Z10predict_YpPfS_:
.quad _Z25__device_stub__predict_YpPfS_
.size _Z10predict_YpPfS_, 8
.type _Z7train_VPfS_S_,@object # @_Z7train_VPfS_S_
.globl _Z7train_VPfS_S_
.p2align 3, 0x0
_Z7train_VPfS_S_:
.quad _Z22__device_stub__train_VPfS_S_
.size _Z7train_VPfS_S_, 8
.type _Z8train_WfPfS_S_,@object # @_Z8train_WfPfS_S_
.globl _Z8train_WfPfS_S_
.p2align 3, 0x0
_Z8train_WfPfS_S_:
.quad _Z23__device_stub__train_WfPfS_S_
.size _Z8train_WfPfS_S_, 8
.type _Z8train_WNPfS_S_S_i,@object # @_Z8train_WNPfS_S_S_i
.globl _Z8train_WNPfS_S_S_i
.p2align 3, 0x0
_Z8train_WNPfS_S_S_i:
.quad _Z23__device_stub__train_WNPfS_S_S_i
.size _Z8train_WNPfS_S_S_i, 8
.type _Z7train_BPfS_,@object # @_Z7train_BPfS_
.globl _Z7train_BPfS_
.p2align 3, 0x0
_Z7train_BPfS_:
.quad _Z22__device_stub__train_BPfS_
.size _Z7train_BPfS_, 8
.type _Z8train_WhPfS_S_i,@object # @_Z8train_WhPfS_S_i
.globl _Z8train_WhPfS_S_i
.p2align 3, 0x0
_Z8train_WhPfS_S_i:
.quad _Z23__device_stub__train_WhPfS_S_i
.size _Z8train_WhPfS_S_i, 8
.type _Z9normalizePfS_S_,@object # @_Z9normalizePfS_S_
.globl _Z9normalizePfS_S_
.p2align 3, 0x0
_Z9normalizePfS_S_:
.quad _Z24__device_stub__normalizePfS_S_
.size _Z9normalizePfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ITERATION : %d\tLOSS : %f\t"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error at %s:%d\n"
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/ShamsArfeen/Deep-Learning-with-CUDA/main/deep.hip"
.size .L.str.2, 107
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "TIME: %f\n"
.size .L.str.3, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9predict_NPf"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10predict_WNPfS_S_i"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10predict_RiPfii"
.size .L__unnamed_3, 19
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z10predict_NkPfS_i"
.size .L__unnamed_4, 20
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z10predict_YpPfS_"
.size .L__unnamed_5, 19
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z7train_VPfS_S_"
.size .L__unnamed_6, 17
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "_Z8train_WfPfS_S_"
.size .L__unnamed_7, 18
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "_Z8train_WNPfS_S_S_i"
.size .L__unnamed_8, 21
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "_Z7train_BPfS_"
.size .L__unnamed_9, 15
.type .L__unnamed_10,@object # @9
.L__unnamed_10:
.asciz "_Z8train_WhPfS_S_i"
.size .L__unnamed_10, 19
.type .L__unnamed_11,@object # @10
.L__unnamed_11:
.asciz "_Z9normalizePfS_S_"
.size .L__unnamed_11, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__predict_NPf
.addrsig_sym _Z25__device_stub__predict_WNPfS_S_i
.addrsig_sym _Z25__device_stub__predict_RiPfii
.addrsig_sym _Z25__device_stub__predict_NkPfS_i
.addrsig_sym _Z25__device_stub__predict_YpPfS_
.addrsig_sym _Z22__device_stub__train_VPfS_S_
.addrsig_sym _Z23__device_stub__train_WfPfS_S_
.addrsig_sym _Z23__device_stub__train_WNPfS_S_S_i
.addrsig_sym _Z22__device_stub__train_BPfS_
.addrsig_sym _Z23__device_stub__train_WhPfS_S_i
.addrsig_sym _Z24__device_stub__normalizePfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym W
.addrsig_sym R
.addrsig_sym N
.addrsig_sym Y
.addrsig_sym pY
.addrsig_sym U
.addrsig_sym V
.addrsig_sym Yh
.addrsig_sym Dh
.addrsig_sym _Z9predict_NPf
.addrsig_sym _Z10predict_WNPfS_S_i
.addrsig_sym _Z10predict_RiPfii
.addrsig_sym _Z10predict_NkPfS_i
.addrsig_sym _Z10predict_YpPfS_
.addrsig_sym _Z7train_VPfS_S_
.addrsig_sym _Z8train_WfPfS_S_
.addrsig_sym _Z8train_WNPfS_S_S_i
.addrsig_sym _Z7train_BPfS_
.addrsig_sym _Z8train_WhPfS_S_i
.addrsig_sym _Z9normalizePfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cufft.h>
// Declared extern "C" to disable C++ name mangling
extern "C" void launchCUFFT(float *d_data, int n, void *stream)
{
cufftHandle plan;
cufftPlan1d(&plan, n, CUFFT_C2C, 1);
cufftSetStream(plan, (cudaStream_t)stream);
cufftExecC2C(plan, (cufftComplex*)d_data, (cufftComplex*)d_data,CUFFT_FORWARD);
cufftDestroy(plan);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cufft.h>
// Declared extern "C" to disable C++ name mangling
extern "C" void launchCUFFT(float *d_data, int n, void *stream)
{
cufftHandle plan;
cufftPlan1d(&plan, n, CUFFT_C2C, 1);
cufftSetStream(plan, (cudaStream_t)stream);
cufftExecC2C(plan, (cufftComplex*)d_data, (cufftComplex*)d_data,CUFFT_FORWARD);
cufftDestroy(plan);
} | .file "tmpxft_000e27f5_00000000-6_cufft.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl launchCUFFT
.type launchCUFFT, @function
launchCUFFT:
.LFB2050:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rdx, %rbp
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
movl $1, %ecx
movl $41, %edx
call cufftPlan1d@PLT
movq %rbp, %rsi
movl 4(%rsp), %edi
call cufftSetStream@PLT
movl $-1, %ecx
movq %rbx, %rdx
movq %rbx, %rsi
movl 4(%rsp), %edi
call cufftExecC2C@PLT
movl 4(%rsp), %edi
call cufftDestroy@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2050:
.size launchCUFFT, .-launchCUFFT
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cufft.h>
// Declared extern "C" to disable C++ name mangling
extern "C" void launchCUFFT(float *d_data, int n, void *stream)
{
cufftHandle plan;
cufftPlan1d(&plan, n, CUFFT_C2C, 1);
cufftSetStream(plan, (cudaStream_t)stream);
cufftExecC2C(plan, (cufftComplex*)d_data, (cufftComplex*)d_data,CUFFT_FORWARD);
cufftDestroy(plan);
} | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
// Declared extern "C" to disable C++ name mangling
extern "C" void launchCUFFT(float *d_data, int n, void *stream)
{
hipfftHandle plan;
hipfftPlan1d(&plan, n, HIPFFT_C2C, 1);
hipfftSetStream(plan, (hipStream_t)stream);
hipfftExecC2C(plan, (hipfftComplex*)d_data, (hipfftComplex*)d_data,HIPFFT_FORWARD);
hipfftDestroy(plan);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
// Declared extern "C" to disable C++ name mangling
extern "C" void launchCUFFT(float *d_data, int n, void *stream)
{
hipfftHandle plan;
hipfftPlan1d(&plan, n, HIPFFT_C2C, 1);
hipfftSetStream(plan, (hipStream_t)stream);
hipfftExecC2C(plan, (hipfftComplex*)d_data, (hipfftComplex*)d_data,HIPFFT_FORWARD);
hipfftDestroy(plan);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
// Declared extern "C" to disable C++ name mangling
extern "C" void launchCUFFT(float *d_data, int n, void *stream)
{
hipfftHandle plan;
hipfftPlan1d(&plan, n, HIPFFT_C2C, 1);
hipfftSetStream(plan, (hipStream_t)stream);
hipfftExecC2C(plan, (hipfftComplex*)d_data, (hipfftComplex*)d_data,HIPFFT_FORWARD);
hipfftDestroy(plan);
} | .text
.file "cufft.hip"
.globl launchCUFFT # -- Begin function launchCUFFT
.p2align 4, 0x90
.type launchCUFFT,@function
launchCUFFT: # @launchCUFFT
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdx, %rbx
movq %rdi, %r14
movq %rsp, %rdi
movl $41, %edx
movl $1, %ecx
callq hipfftPlan1d
movq (%rsp), %rdi
movq %rbx, %rsi
callq hipfftSetStream
movq (%rsp), %rdi
movq %r14, %rsi
movq %r14, %rdx
movl $-1, %ecx
callq hipfftExecC2C
movq (%rsp), %rdi
callq hipfftDestroy
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size launchCUFFT, .Lfunc_end0-launchCUFFT
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e27f5_00000000-6_cufft.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl launchCUFFT
.type launchCUFFT, @function
launchCUFFT:
.LFB2050:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rdx, %rbp
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
movl $1, %ecx
movl $41, %edx
call cufftPlan1d@PLT
movq %rbp, %rsi
movl 4(%rsp), %edi
call cufftSetStream@PLT
movl $-1, %ecx
movq %rbx, %rdx
movq %rbx, %rsi
movl 4(%rsp), %edi
call cufftExecC2C@PLT
movl 4(%rsp), %edi
call cufftDestroy@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2050:
.size launchCUFFT, .-launchCUFFT
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cufft.hip"
.globl launchCUFFT # -- Begin function launchCUFFT
.p2align 4, 0x90
.type launchCUFFT,@function
launchCUFFT: # @launchCUFFT
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdx, %rbx
movq %rdi, %r14
movq %rsp, %rdi
movl $41, %edx
movl $1, %ecx
callq hipfftPlan1d
movq (%rsp), %rdi
movq %rbx, %rsi
callq hipfftSetStream
movq (%rsp), %rdi
movq %r14, %rsi
movq %r14, %rdx
movl $-1, %ecx
callq hipfftExecC2C
movq (%rsp), %rdi
callq hipfftDestroy
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size launchCUFFT, .Lfunc_end0-launchCUFFT
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
//#include <cuda.h>
int main(void) {
cudaDeviceProp prop;//cudaDevieProp is a structure, prop is a structure variable.
int count;
cudaGetDeviceCount (&count);
for (int i=0; i< count; i++){
cudaGetDeviceProperties (&prop, i);
printf("\n****************************Device %d*************************************\n",i);
printf("----------General Information----------\n");
printf("Name: %s\n", prop.name);
printf("Compute capability: %d.%d\n", prop.major, prop.minor);
// printf("Clock rate: %d\n", prop.clockRate);
printf("Clock rate: %d MHz\n", (prop.clockRate/1000));
printf("GPU type: ");
if (prop.integrated)
printf ("Integrated GPU\n");
else
printf ("Discreted GPU\n");
printf("Device copy overlap: ");
if (prop.deviceOverlap)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Kernel execution timeout: ");
if (prop.kernelExecTimeoutEnabled)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Mapping Host Memory into CUDA Device Address Space: ");
if (prop.canMapHostMemory)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Executing Multiple Kernels Support: ");
if (prop.concurrentKernels)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Device Computing Mode: ");
if (prop.computeMode == 0) printf("Default\n");
if (prop.computeMode == 1) printf("Exclusive\n");
if (prop.computeMode == 2) printf("Prohibited\n");
printf( "\n----------Memory Information for device----------\n");
// printf( "Total Global Memory: %ld\n", prop.totalGlobalMem);
printf( "Total Global Memory: %ld MB\n", (prop.totalGlobalMem/1024/1024));
// printf( "Total Constant Memory: %ld\n", prop.totalConstMem );
printf( "Total Constant Memory: %ld kB\n", (prop.totalConstMem/1024));
// printf( "Total Constant Memory: %ld MB\n", (prop.totalConstMem/1024/1024));
// printf( "Max Memory Pitch Allowed for Memory Copies: %ld\n", prop.memPitch );
printf( "Max Memory Pitch Allowed for Memory Copies: %ld MB\n", (prop.memPitch/1024/1024));
printf( "Texture Alignment: %ld B\n", prop.textureAlignment );
printf( "Max Size Supported for 1D Textures: %ld\n", prop.maxTexture1D);
printf( "Max Dimensions Supported for 2D Texture: (%d, %d)\n", prop.maxTexture2D[0], prop.maxTexture2D[1]);
printf( "Max Dimensions Supported for 3D Texture: (%d, %d, %d)\n",
prop.maxTexture3D[0],
prop.maxTexture3D[1],
prop.maxTexture3D[2]);
/* printf( "Max Dimensions Supported for 2D Texture Array: (%d, %d, %d)\n",
prop.maxTexture2DArray[0],
prop.maxTexture2DArray[1],
prop.maxTexture2DArray[2]);
*/
printf( "\n----------Thread Information for device----------\n");
printf( "Streaming Multiprocessor count: %d\n", prop.multiProcessorCount);
// printf( "Shared Memory per Block: %ld\n", prop.sharedMemPerBlock);
printf( "Shared Memory per Block: %ld KB\n", (prop.sharedMemPerBlock/1024));
printf( "Registers per Block: %ld\n", prop.regsPerBlock);
printf( "Threads in warp: %ld\n", prop.warpSize);
printf( "Max threads per block: %d\n",
prop.maxThreadsPerBlock);
printf( "Max thread dimensions: (%d, %d, %d)\n",
prop.maxThreadsDim[0], prop.maxThreadsDim[1],
prop.maxThreadsDim[2]);
printf( "Max grid dimensions: (%d, %d, %d)\n",
prop.maxGridSize[0], prop.maxGridSize[1],
prop.maxGridSize[2]);
printf("*****************************************************************\n");
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
//#include <cuda.h>
int main(void) {
cudaDeviceProp prop;//cudaDevieProp is a structure, prop is a structure variable.
int count;
cudaGetDeviceCount (&count);
for (int i=0; i< count; i++){
cudaGetDeviceProperties (&prop, i);
printf("\n****************************Device %d*************************************\n",i);
printf("----------General Information----------\n");
printf("Name: %s\n", prop.name);
printf("Compute capability: %d.%d\n", prop.major, prop.minor);
// printf("Clock rate: %d\n", prop.clockRate);
printf("Clock rate: %d MHz\n", (prop.clockRate/1000));
printf("GPU type: ");
if (prop.integrated)
printf ("Integrated GPU\n");
else
printf ("Discreted GPU\n");
printf("Device copy overlap: ");
if (prop.deviceOverlap)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Kernel execution timeout: ");
if (prop.kernelExecTimeoutEnabled)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Mapping Host Memory into CUDA Device Address Space: ");
if (prop.canMapHostMemory)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Executing Multiple Kernels Support: ");
if (prop.concurrentKernels)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Device Computing Mode: ");
if (prop.computeMode == 0) printf("Default\n");
if (prop.computeMode == 1) printf("Exclusive\n");
if (prop.computeMode == 2) printf("Prohibited\n");
printf( "\n----------Memory Information for device----------\n");
// printf( "Total Global Memory: %ld\n", prop.totalGlobalMem);
printf( "Total Global Memory: %ld MB\n", (prop.totalGlobalMem/1024/1024));
// printf( "Total Constant Memory: %ld\n", prop.totalConstMem );
printf( "Total Constant Memory: %ld kB\n", (prop.totalConstMem/1024));
// printf( "Total Constant Memory: %ld MB\n", (prop.totalConstMem/1024/1024));
// printf( "Max Memory Pitch Allowed for Memory Copies: %ld\n", prop.memPitch );
printf( "Max Memory Pitch Allowed for Memory Copies: %ld MB\n", (prop.memPitch/1024/1024));
printf( "Texture Alignment: %ld B\n", prop.textureAlignment );
printf( "Max Size Supported for 1D Textures: %ld\n", prop.maxTexture1D);
printf( "Max Dimensions Supported for 2D Texture: (%d, %d)\n", prop.maxTexture2D[0], prop.maxTexture2D[1]);
printf( "Max Dimensions Supported for 3D Texture: (%d, %d, %d)\n",
prop.maxTexture3D[0],
prop.maxTexture3D[1],
prop.maxTexture3D[2]);
/* printf( "Max Dimensions Supported for 2D Texture Array: (%d, %d, %d)\n",
prop.maxTexture2DArray[0],
prop.maxTexture2DArray[1],
prop.maxTexture2DArray[2]);
*/
printf( "\n----------Thread Information for device----------\n");
printf( "Streaming Multiprocessor count: %d\n", prop.multiProcessorCount);
// printf( "Shared Memory per Block: %ld\n", prop.sharedMemPerBlock);
printf( "Shared Memory per Block: %ld KB\n", (prop.sharedMemPerBlock/1024));
printf( "Registers per Block: %ld\n", prop.regsPerBlock);
printf( "Threads in warp: %ld\n", prop.warpSize);
printf( "Max threads per block: %d\n",
prop.maxThreadsPerBlock);
printf( "Max thread dimensions: (%d, %d, %d)\n",
prop.maxThreadsDim[0], prop.maxThreadsDim[1],
prop.maxThreadsDim[2]);
printf( "Max grid dimensions: (%d, %d, %d)\n",
prop.maxGridSize[0], prop.maxGridSize[1],
prop.maxGridSize[2]);
printf("*****************************************************************\n");
}
return 0;
} | .file "tmpxft_0018eaaa_00000000-6_page32_gpuinfo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\n****************************Device %d*************************************\n"
.align 8
.LC1:
.string "----------General Information----------\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Name: %s\n"
.LC3:
.string "Compute capability: %d.%d\n"
.LC4:
.string "Clock rate: %d MHz\n"
.LC5:
.string "GPU type: "
.LC6:
.string "Integrated GPU\n"
.LC7:
.string "Discreted GPU\n"
.LC8:
.string "Device copy overlap: "
.LC9:
.string "Enabled\n"
.LC10:
.string "Disabled\n"
.LC11:
.string "Kernel execution timeout: "
.section .rodata.str1.8
.align 8
.LC12:
.string "Mapping Host Memory into CUDA Device Address Space: "
.align 8
.LC13:
.string "Executing Multiple Kernels Support: "
.section .rodata.str1.1
.LC14:
.string "Device Computing Mode: "
.LC15:
.string "Default\n"
.LC16:
.string "Exclusive\n"
.LC17:
.string "Prohibited\n"
.section .rodata.str1.8
.align 8
.LC18:
.string "\n----------Memory Information for device----------\n"
.section .rodata.str1.1
.LC19:
.string "Total Global Memory: %ld MB\n"
.section .rodata.str1.8
.align 8
.LC20:
.string "Total Constant Memory: %ld kB\n"
.align 8
.LC21:
.string "Max Memory Pitch Allowed for Memory Copies: %ld MB\n"
.section .rodata.str1.1
.LC22:
.string "Texture Alignment: %ld B\n"
.section .rodata.str1.8
.align 8
.LC23:
.string "Max Size Supported for 1D Textures: %ld\n"
.align 8
.LC24:
.string "Max Dimensions Supported for 2D Texture: (%d, %d)\n"
.align 8
.LC25:
.string "Max Dimensions Supported for 3D Texture: (%d, %d, %d)\n"
.align 8
.LC26:
.string "\n----------Thread Information for device----------\n"
.align 8
.LC27:
.string "Streaming Multiprocessor count: %d\n"
.align 8
.LC28:
.string "Shared Memory per Block: %ld KB\n"
.section .rodata.str1.1
.LC29:
.string "Registers per Block: %ld\n"
.LC30:
.string "Threads in warp: %ld\n"
.LC31:
.string "Max threads per block: %d\n"
.section .rodata.str1.8
.align 8
.LC32:
.string "Max thread dimensions: (%d, %d, %d)\n"
.align 8
.LC33:
.string "Max grid dimensions: (%d, %d, %d)\n"
.align 8
.LC34:
.string "*****************************************************************\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebx
leaq .LC0(%rip), %r14
leaq .LC1(%rip), %r13
leaq .LC2(%rip), %r12
leaq .LC3(%rip), %rbp
jmp .L18
.L5:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L6
.L7:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L8
.L9:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L10
.L11:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L12
.L13:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L14:
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 420(%rsp)
je .L22
.L15:
cmpl $1, 420(%rsp)
je .L23
.L16:
cmpl $2, 420(%rsp)
je .L24
.L17:
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
shrq $20, %rdx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
shrq $10, %rdx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
shrq $20, %rdx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 384(%rsp), %rdx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 424(%rsp), %edx
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 440(%rsp), %ecx
movl 436(%rsp), %edx
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 480(%rsp), %r8d
movl 476(%rsp), %ecx
movl 472(%rsp), %edx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
shrq $10, %rdx
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC29(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC30(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC31(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC32(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC33(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC34(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L4
.L18:
leaq 16(%rsp), %r15
movl %ebx, %esi
movq %r15, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %eax
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
sarl $31, %eax
subl %eax, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 412(%rsp)
je .L5
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L6:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 400(%rsp)
je .L7
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L8:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 408(%rsp)
je .L9
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L10:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 416(%rsp)
je .L11
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L12:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 592(%rsp)
je .L13
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.L22:
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L15
.L23:
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L24:
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
//#include <cuda.h>
int main(void) {
cudaDeviceProp prop;//cudaDevieProp is a structure, prop is a structure variable.
int count;
cudaGetDeviceCount (&count);
for (int i=0; i< count; i++){
cudaGetDeviceProperties (&prop, i);
printf("\n****************************Device %d*************************************\n",i);
printf("----------General Information----------\n");
printf("Name: %s\n", prop.name);
printf("Compute capability: %d.%d\n", prop.major, prop.minor);
// printf("Clock rate: %d\n", prop.clockRate);
printf("Clock rate: %d MHz\n", (prop.clockRate/1000));
printf("GPU type: ");
if (prop.integrated)
printf ("Integrated GPU\n");
else
printf ("Discreted GPU\n");
printf("Device copy overlap: ");
if (prop.deviceOverlap)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Kernel execution timeout: ");
if (prop.kernelExecTimeoutEnabled)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Mapping Host Memory into CUDA Device Address Space: ");
if (prop.canMapHostMemory)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Executing Multiple Kernels Support: ");
if (prop.concurrentKernels)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Device Computing Mode: ");
if (prop.computeMode == 0) printf("Default\n");
if (prop.computeMode == 1) printf("Exclusive\n");
if (prop.computeMode == 2) printf("Prohibited\n");
printf( "\n----------Memory Information for device----------\n");
// printf( "Total Global Memory: %ld\n", prop.totalGlobalMem);
printf( "Total Global Memory: %ld MB\n", (prop.totalGlobalMem/1024/1024));
// printf( "Total Constant Memory: %ld\n", prop.totalConstMem );
printf( "Total Constant Memory: %ld kB\n", (prop.totalConstMem/1024));
// printf( "Total Constant Memory: %ld MB\n", (prop.totalConstMem/1024/1024));
// printf( "Max Memory Pitch Allowed for Memory Copies: %ld\n", prop.memPitch );
printf( "Max Memory Pitch Allowed for Memory Copies: %ld MB\n", (prop.memPitch/1024/1024));
printf( "Texture Alignment: %ld B\n", prop.textureAlignment );
printf( "Max Size Supported for 1D Textures: %ld\n", prop.maxTexture1D);
printf( "Max Dimensions Supported for 2D Texture: (%d, %d)\n", prop.maxTexture2D[0], prop.maxTexture2D[1]);
printf( "Max Dimensions Supported for 3D Texture: (%d, %d, %d)\n",
prop.maxTexture3D[0],
prop.maxTexture3D[1],
prop.maxTexture3D[2]);
/* printf( "Max Dimensions Supported for 2D Texture Array: (%d, %d, %d)\n",
prop.maxTexture2DArray[0],
prop.maxTexture2DArray[1],
prop.maxTexture2DArray[2]);
*/
printf( "\n----------Thread Information for device----------\n");
printf( "Streaming Multiprocessor count: %d\n", prop.multiProcessorCount);
// printf( "Shared Memory per Block: %ld\n", prop.sharedMemPerBlock);
printf( "Shared Memory per Block: %ld KB\n", (prop.sharedMemPerBlock/1024));
printf( "Registers per Block: %ld\n", prop.regsPerBlock);
printf( "Threads in warp: %ld\n", prop.warpSize);
printf( "Max threads per block: %d\n",
prop.maxThreadsPerBlock);
printf( "Max thread dimensions: (%d, %d, %d)\n",
prop.maxThreadsDim[0], prop.maxThreadsDim[1],
prop.maxThreadsDim[2]);
printf( "Max grid dimensions: (%d, %d, %d)\n",
prop.maxGridSize[0], prop.maxGridSize[1],
prop.maxGridSize[2]);
printf("*****************************************************************\n");
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
//#include <cuda.h>
int main(void) {
hipDeviceProp_t prop;//cudaDevieProp is a structure, prop is a structure variable.
int count;
hipGetDeviceCount (&count);
for (int i=0; i< count; i++){
hipGetDeviceProperties (&prop, i);
printf("\n****************************Device %d*************************************\n",i);
printf("----------General Information----------\n");
printf("Name: %s\n", prop.name);
printf("Compute capability: %d.%d\n", prop.major, prop.minor);
// printf("Clock rate: %d\n", prop.clockRate);
printf("Clock rate: %d MHz\n", (prop.clockRate/1000));
printf("GPU type: ");
if (prop.integrated)
printf ("Integrated GPU\n");
else
printf ("Discreted GPU\n");
printf("Device copy overlap: ");
if (prop.deviceOverlap)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Kernel execution timeout: ");
if (prop.kernelExecTimeoutEnabled)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Mapping Host Memory into CUDA Device Address Space: ");
if (prop.canMapHostMemory)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Executing Multiple Kernels Support: ");
if (prop.concurrentKernels)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Device Computing Mode: ");
if (prop.computeMode == 0) printf("Default\n");
if (prop.computeMode == 1) printf("Exclusive\n");
if (prop.computeMode == 2) printf("Prohibited\n");
printf( "\n----------Memory Information for device----------\n");
// printf( "Total Global Memory: %ld\n", prop.totalGlobalMem);
printf( "Total Global Memory: %ld MB\n", (prop.totalGlobalMem/1024/1024));
// printf( "Total Constant Memory: %ld\n", prop.totalConstMem );
printf( "Total Constant Memory: %ld kB\n", (prop.totalConstMem/1024));
// printf( "Total Constant Memory: %ld MB\n", (prop.totalConstMem/1024/1024));
// printf( "Max Memory Pitch Allowed for Memory Copies: %ld\n", prop.memPitch );
printf( "Max Memory Pitch Allowed for Memory Copies: %ld MB\n", (prop.memPitch/1024/1024));
printf( "Texture Alignment: %ld B\n", prop.textureAlignment );
printf( "Max Size Supported for 1D Textures: %ld\n", prop.maxTexture1D);
printf( "Max Dimensions Supported for 2D Texture: (%d, %d)\n", prop.maxTexture2D[0], prop.maxTexture2D[1]);
printf( "Max Dimensions Supported for 3D Texture: (%d, %d, %d)\n",
prop.maxTexture3D[0],
prop.maxTexture3D[1],
prop.maxTexture3D[2]);
/* printf( "Max Dimensions Supported for 2D Texture Array: (%d, %d, %d)\n",
prop.maxTexture2DArray[0],
prop.maxTexture2DArray[1],
prop.maxTexture2DArray[2]);
*/
printf( "\n----------Thread Information for device----------\n");
printf( "Streaming Multiprocessor count: %d\n", prop.multiProcessorCount);
// printf( "Shared Memory per Block: %ld\n", prop.sharedMemPerBlock);
printf( "Shared Memory per Block: %ld KB\n", (prop.sharedMemPerBlock/1024));
printf( "Registers per Block: %ld\n", prop.regsPerBlock);
printf( "Threads in warp: %ld\n", prop.warpSize);
printf( "Max threads per block: %d\n",
prop.maxThreadsPerBlock);
printf( "Max thread dimensions: (%d, %d, %d)\n",
prop.maxThreadsDim[0], prop.maxThreadsDim[1],
prop.maxThreadsDim[2]);
printf( "Max grid dimensions: (%d, %d, %d)\n",
prop.maxGridSize[0], prop.maxGridSize[1],
prop.maxGridSize[2]);
printf("*****************************************************************\n");
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
//#include <cuda.h>
int main(void) {
hipDeviceProp_t prop;//cudaDevieProp is a structure, prop is a structure variable.
int count;
hipGetDeviceCount (&count);
for (int i=0; i< count; i++){
hipGetDeviceProperties (&prop, i);
printf("\n****************************Device %d*************************************\n",i);
printf("----------General Information----------\n");
printf("Name: %s\n", prop.name);
printf("Compute capability: %d.%d\n", prop.major, prop.minor);
// printf("Clock rate: %d\n", prop.clockRate);
printf("Clock rate: %d MHz\n", (prop.clockRate/1000));
printf("GPU type: ");
if (prop.integrated)
printf ("Integrated GPU\n");
else
printf ("Discreted GPU\n");
printf("Device copy overlap: ");
if (prop.deviceOverlap)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Kernel execution timeout: ");
if (prop.kernelExecTimeoutEnabled)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Mapping Host Memory into CUDA Device Address Space: ");
if (prop.canMapHostMemory)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Executing Multiple Kernels Support: ");
if (prop.concurrentKernels)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Device Computing Mode: ");
if (prop.computeMode == 0) printf("Default\n");
if (prop.computeMode == 1) printf("Exclusive\n");
if (prop.computeMode == 2) printf("Prohibited\n");
printf( "\n----------Memory Information for device----------\n");
// printf( "Total Global Memory: %ld\n", prop.totalGlobalMem);
printf( "Total Global Memory: %ld MB\n", (prop.totalGlobalMem/1024/1024));
// printf( "Total Constant Memory: %ld\n", prop.totalConstMem );
printf( "Total Constant Memory: %ld kB\n", (prop.totalConstMem/1024));
// printf( "Total Constant Memory: %ld MB\n", (prop.totalConstMem/1024/1024));
// printf( "Max Memory Pitch Allowed for Memory Copies: %ld\n", prop.memPitch );
printf( "Max Memory Pitch Allowed for Memory Copies: %ld MB\n", (prop.memPitch/1024/1024));
printf( "Texture Alignment: %ld B\n", prop.textureAlignment );
printf( "Max Size Supported for 1D Textures: %ld\n", prop.maxTexture1D);
printf( "Max Dimensions Supported for 2D Texture: (%d, %d)\n", prop.maxTexture2D[0], prop.maxTexture2D[1]);
printf( "Max Dimensions Supported for 3D Texture: (%d, %d, %d)\n",
prop.maxTexture3D[0],
prop.maxTexture3D[1],
prop.maxTexture3D[2]);
/* printf( "Max Dimensions Supported for 2D Texture Array: (%d, %d, %d)\n",
prop.maxTexture2DArray[0],
prop.maxTexture2DArray[1],
prop.maxTexture2DArray[2]);
*/
printf( "\n----------Thread Information for device----------\n");
printf( "Streaming Multiprocessor count: %d\n", prop.multiProcessorCount);
// printf( "Shared Memory per Block: %ld\n", prop.sharedMemPerBlock);
printf( "Shared Memory per Block: %ld KB\n", (prop.sharedMemPerBlock/1024));
printf( "Registers per Block: %ld\n", prop.regsPerBlock);
printf( "Threads in warp: %ld\n", prop.warpSize);
printf( "Max threads per block: %d\n",
prop.maxThreadsPerBlock);
printf( "Max thread dimensions: (%d, %d, %d)\n",
prop.maxThreadsDim[0], prop.maxThreadsDim[1],
prop.maxThreadsDim[2]);
printf( "Max grid dimensions: (%d, %d, %d)\n",
prop.maxGridSize[0], prop.maxGridSize[1],
prop.maxGridSize[2]);
printf("*****************************************************************\n");
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
//#include <cuda.h>
int main(void) {
hipDeviceProp_t prop;//cudaDevieProp is a structure, prop is a structure variable.
int count;
hipGetDeviceCount (&count);
for (int i=0; i< count; i++){
hipGetDeviceProperties (&prop, i);
printf("\n****************************Device %d*************************************\n",i);
printf("----------General Information----------\n");
printf("Name: %s\n", prop.name);
printf("Compute capability: %d.%d\n", prop.major, prop.minor);
// printf("Clock rate: %d\n", prop.clockRate);
printf("Clock rate: %d MHz\n", (prop.clockRate/1000));
printf("GPU type: ");
if (prop.integrated)
printf ("Integrated GPU\n");
else
printf ("Discreted GPU\n");
printf("Device copy overlap: ");
if (prop.deviceOverlap)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Kernel execution timeout: ");
if (prop.kernelExecTimeoutEnabled)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Mapping Host Memory into CUDA Device Address Space: ");
if (prop.canMapHostMemory)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Executing Multiple Kernels Support: ");
if (prop.concurrentKernels)
printf ("Enabled\n");
else
printf ("Disabled\n");
printf( "Device Computing Mode: ");
if (prop.computeMode == 0) printf("Default\n");
if (prop.computeMode == 1) printf("Exclusive\n");
if (prop.computeMode == 2) printf("Prohibited\n");
printf( "\n----------Memory Information for device----------\n");
// printf( "Total Global Memory: %ld\n", prop.totalGlobalMem);
printf( "Total Global Memory: %ld MB\n", (prop.totalGlobalMem/1024/1024));
// printf( "Total Constant Memory: %ld\n", prop.totalConstMem );
printf( "Total Constant Memory: %ld kB\n", (prop.totalConstMem/1024));
// printf( "Total Constant Memory: %ld MB\n", (prop.totalConstMem/1024/1024));
// printf( "Max Memory Pitch Allowed for Memory Copies: %ld\n", prop.memPitch );
printf( "Max Memory Pitch Allowed for Memory Copies: %ld MB\n", (prop.memPitch/1024/1024));
printf( "Texture Alignment: %ld B\n", prop.textureAlignment );
printf( "Max Size Supported for 1D Textures: %ld\n", prop.maxTexture1D);
printf( "Max Dimensions Supported for 2D Texture: (%d, %d)\n", prop.maxTexture2D[0], prop.maxTexture2D[1]);
printf( "Max Dimensions Supported for 3D Texture: (%d, %d, %d)\n",
prop.maxTexture3D[0],
prop.maxTexture3D[1],
prop.maxTexture3D[2]);
/* printf( "Max Dimensions Supported for 2D Texture Array: (%d, %d, %d)\n",
prop.maxTexture2DArray[0],
prop.maxTexture2DArray[1],
prop.maxTexture2DArray[2]);
*/
printf( "\n----------Thread Information for device----------\n");
printf( "Streaming Multiprocessor count: %d\n", prop.multiProcessorCount);
// printf( "Shared Memory per Block: %ld\n", prop.sharedMemPerBlock);
printf( "Shared Memory per Block: %ld KB\n", (prop.sharedMemPerBlock/1024));
printf( "Registers per Block: %ld\n", prop.regsPerBlock);
printf( "Threads in warp: %ld\n", prop.warpSize);
printf( "Max threads per block: %d\n",
prop.maxThreadsPerBlock);
printf( "Max thread dimensions: (%d, %d, %d)\n",
prop.maxThreadsDim[0], prop.maxThreadsDim[1],
prop.maxThreadsDim[2]);
printf( "Max grid dimensions: (%d, %d, %d)\n",
prop.maxGridSize[0], prop.maxGridSize[1],
prop.maxGridSize[2]);
printf("*****************************************************************\n");
}
return 0;
} | .text
.file "page32_gpuinfo.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jle .LBB0_9
# %bb.1: # %.lr.ph
leaq 8(%rsp), %rbx
movl $.Lstr.1, %r14d
movl $.Lstr.9, %r15d
xorl %ebp, %ebp
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_8: # in Loop: Header=BB0_2 Depth=1
movl $.Lstr.14, %edi
callq puts@PLT
movq 296(%rsp), %rsi
shrq $20, %rsi
movl $.L.str.19, %edi
xorl %eax, %eax
callq printf
movq 360(%rsp), %rsi
shrq $10, %rsi
movl $.L.str.20, %edi
xorl %eax, %eax
callq printf
movq 320(%rsp), %rsi
shrq $20, %rsi
movl $.L.str.21, %edi
xorl %eax, %eax
callq printf
movq 376(%rsp), %rsi
movl $.L.str.22, %edi
xorl %eax, %eax
callq printf
movl 416(%rsp), %esi
movl $.L.str.23, %edi
xorl %eax, %eax
callq printf
movl 428(%rsp), %esi
movl 432(%rsp), %edx
movl $.L.str.24, %edi
xorl %eax, %eax
callq printf
movl 464(%rsp), %esi
movl 468(%rsp), %edx
movl 472(%rsp), %ecx
movl $.L.str.25, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.15, %edi
callq puts@PLT
movl 396(%rsp), %esi
movl $.L.str.27, %edi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
shrq $10, %rsi
movl $.L.str.28, %edi
xorl %eax, %eax
callq printf
movl 312(%rsp), %esi
movl $.L.str.29, %edi
xorl %eax, %eax
callq printf
movl 316(%rsp), %esi
movl $.L.str.30, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.31, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl 336(%rsp), %edx
movl 340(%rsp), %ecx
movl $.L.str.32, %edi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl 348(%rsp), %edx
movl 352(%rsp), %ecx
movl $.L.str.33, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.16, %edi
callq puts@PLT
incl %ebp
cmpl 4(%rsp), %ebp
jge .LBB0_9
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 368(%rsp), %esi
movl 372(%rsp), %edx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movslq 356(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rax
shrq $63, %rax
sarq $38, %rsi
addl %eax, %esi
movl $.L.str.4, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
cmpl $0, 404(%rsp)
movl $.Lstr.2, %edi
cmoveq %r14, %rdi
callq puts@PLT
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
cmpl $0, 392(%rsp)
movl $.Lstr.10, %edi
cmoveq %r15, %rdi
callq puts@PLT
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
cmpl $0, 400(%rsp)
movl $.Lstr.10, %edi
cmoveq %r15, %rdi
callq puts@PLT
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
cmpl $0, 408(%rsp)
movl $.Lstr.10, %edi
cmoveq %r15, %rdi
callq puts@PLT
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
cmpl $0, 584(%rsp)
movl $.Lstr.10, %edi
cmoveq %r15, %rdi
callq puts@PLT
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
cmpl $0, 412(%rsp)
je .LBB0_3
# %bb.4: # in Loop: Header=BB0_2 Depth=1
cmpl $1, 412(%rsp)
je .LBB0_5
.LBB0_6: # in Loop: Header=BB0_2 Depth=1
cmpl $2, 412(%rsp)
jne .LBB0_8
jmp .LBB0_7
.p2align 4, 0x90
.LBB0_3: # in Loop: Header=BB0_2 Depth=1
movl $.Lstr.11, %edi
callq puts@PLT
cmpl $1, 412(%rsp)
jne .LBB0_6
.LBB0_5: # in Loop: Header=BB0_2 Depth=1
movl $.Lstr.12, %edi
callq puts@PLT
cmpl $2, 412(%rsp)
jne .LBB0_8
.LBB0_7: # in Loop: Header=BB0_2 Depth=1
movl $.Lstr.13, %edi
callq puts@PLT
jmp .LBB0_8
.LBB0_9: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n****************************Device %d*************************************\n"
.size .L.str, 77
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Name: %s\n"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Compute capability: %d.%d\n"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Clock rate: %d MHz\n"
.size .L.str.4, 20
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "GPU type: "
.size .L.str.5, 11
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Device copy overlap: "
.size .L.str.8, 22
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Kernel execution timeout: "
.size .L.str.11, 27
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Mapping Host Memory into CUDA Device Address Space: "
.size .L.str.12, 53
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Executing Multiple Kernels Support: "
.size .L.str.13, 37
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Device Computing Mode: "
.size .L.str.14, 24
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Total Global Memory: %ld MB\n"
.size .L.str.19, 29
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "Total Constant Memory: %ld kB\n"
.size .L.str.20, 31
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "Max Memory Pitch Allowed for Memory Copies: %ld MB\n"
.size .L.str.21, 52
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "Texture Alignment: %ld B\n"
.size .L.str.22, 26
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "Max Size Supported for 1D Textures: %ld\n"
.size .L.str.23, 41
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "Max Dimensions Supported for 2D Texture: (%d, %d)\n"
.size .L.str.24, 51
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz "Max Dimensions Supported for 3D Texture: (%d, %d, %d)\n"
.size .L.str.25, 55
.type .L.str.27,@object # @.str.27
.L.str.27:
.asciz "Streaming Multiprocessor count: %d\n"
.size .L.str.27, 36
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz "Shared Memory per Block: %ld KB\n"
.size .L.str.28, 33
.type .L.str.29,@object # @.str.29
.L.str.29:
.asciz "Registers per Block: %ld\n"
.size .L.str.29, 26
.type .L.str.30,@object # @.str.30
.L.str.30:
.asciz "Threads in warp: %ld\n"
.size .L.str.30, 22
.type .L.str.31,@object # @.str.31
.L.str.31:
.asciz "Max threads per block: %d\n"
.size .L.str.31, 27
.type .L.str.32,@object # @.str.32
.L.str.32:
.asciz "Max thread dimensions: (%d, %d, %d)\n"
.size .L.str.32, 37
.type .L.str.33,@object # @.str.33
.L.str.33:
.asciz "Max grid dimensions: (%d, %d, %d)\n"
.size .L.str.33, 35
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "----------General Information----------"
.size .Lstr, 40
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Discreted GPU"
.size .Lstr.1, 14
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Integrated GPU"
.size .Lstr.2, 15
.type .Lstr.9,@object # @str.9
.Lstr.9:
.asciz "Disabled"
.size .Lstr.9, 9
.type .Lstr.10,@object # @str.10
.Lstr.10:
.asciz "Enabled"
.size .Lstr.10, 8
.type .Lstr.11,@object # @str.11
.Lstr.11:
.asciz "Default"
.size .Lstr.11, 8
.type .Lstr.12,@object # @str.12
.Lstr.12:
.asciz "Exclusive"
.size .Lstr.12, 10
.type .Lstr.13,@object # @str.13
.Lstr.13:
.asciz "Prohibited"
.size .Lstr.13, 11
.type .Lstr.14,@object # @str.14
.Lstr.14:
.asciz "\n----------Memory Information for device----------"
.size .Lstr.14, 51
.type .Lstr.15,@object # @str.15
.Lstr.15:
.asciz "\n----------Thread Information for device----------"
.size .Lstr.15, 51
.type .Lstr.16,@object # @str.16
.Lstr.16:
.asciz "*****************************************************************"
.size .Lstr.16, 66
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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