system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018eaaa_00000000-6_page32_gpuinfo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\n****************************Device %d*************************************\n"
.align 8
.LC1:
.string "----------General Information----------\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Name: %s\n"
.LC3:
.string "Compute capability: %d.%d\n"
.LC4:
.string "Clock rate: %d MHz\n"
.LC5:
.string "GPU type: "
.LC6:
.string "Integrated GPU\n"
.LC7:
.string "Discreted GPU\n"
.LC8:
.string "Device copy overlap: "
.LC9:
.string "Enabled\n"
.LC10:
.string "Disabled\n"
.LC11:
.string "Kernel execution timeout: "
.section .rodata.str1.8
.align 8
.LC12:
.string "Mapping Host Memory into CUDA Device Address Space: "
.align 8
.LC13:
.string "Executing Multiple Kernels Support: "
.section .rodata.str1.1
.LC14:
.string "Device Computing Mode: "
.LC15:
.string "Default\n"
.LC16:
.string "Exclusive\n"
.LC17:
.string "Prohibited\n"
.section .rodata.str1.8
.align 8
.LC18:
.string "\n----------Memory Information for device----------\n"
.section .rodata.str1.1
.LC19:
.string "Total Global Memory: %ld MB\n"
.section .rodata.str1.8
.align 8
.LC20:
.string "Total Constant Memory: %ld kB\n"
.align 8
.LC21:
.string "Max Memory Pitch Allowed for Memory Copies: %ld MB\n"
.section .rodata.str1.1
.LC22:
.string "Texture Alignment: %ld B\n"
.section .rodata.str1.8
.align 8
.LC23:
.string "Max Size Supported for 1D Textures: %ld\n"
.align 8
.LC24:
.string "Max Dimensions Supported for 2D Texture: (%d, %d)\n"
.align 8
.LC25:
.string "Max Dimensions Supported for 3D Texture: (%d, %d, %d)\n"
.align 8
.LC26:
.string "\n----------Thread Information for device----------\n"
.align 8
.LC27:
.string "Streaming Multiprocessor count: %d\n"
.align 8
.LC28:
.string "Shared Memory per Block: %ld KB\n"
.section .rodata.str1.1
.LC29:
.string "Registers per Block: %ld\n"
.LC30:
.string "Threads in warp: %ld\n"
.LC31:
.string "Max threads per block: %d\n"
.section .rodata.str1.8
.align 8
.LC32:
.string "Max thread dimensions: (%d, %d, %d)\n"
.align 8
.LC33:
.string "Max grid dimensions: (%d, %d, %d)\n"
.align 8
.LC34:
.string "*****************************************************************\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebx
leaq .LC0(%rip), %r14
leaq .LC1(%rip), %r13
leaq .LC2(%rip), %r12
leaq .LC3(%rip), %rbp
jmp .L18
.L5:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L6
.L7:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L8
.L9:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L10
.L11:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L12
.L13:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L14:
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 420(%rsp)
je .L22
.L15:
cmpl $1, 420(%rsp)
je .L23
.L16:
cmpl $2, 420(%rsp)
je .L24
.L17:
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
shrq $20, %rdx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
shrq $10, %rdx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
shrq $20, %rdx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 384(%rsp), %rdx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 424(%rsp), %edx
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 440(%rsp), %ecx
movl 436(%rsp), %edx
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 480(%rsp), %r8d
movl 476(%rsp), %ecx
movl 472(%rsp), %edx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
shrq $10, %rdx
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC29(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC30(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC31(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC32(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC33(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC34(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L4
.L18:
leaq 16(%rsp), %r15
movl %ebx, %esi
movq %r15, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %eax
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
sarl $31, %eax
subl %eax, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 412(%rsp)
je .L5
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L6:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 400(%rsp)
je .L7
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L8:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 408(%rsp)
je .L9
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L10:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 416(%rsp)
je .L11
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L12:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 592(%rsp)
je .L13
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.L22:
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L15
.L23:
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L24:
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "page32_gpuinfo.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jle .LBB0_9
# %bb.1: # %.lr.ph
leaq 8(%rsp), %rbx
movl $.Lstr.1, %r14d
movl $.Lstr.9, %r15d
xorl %ebp, %ebp
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_8: # in Loop: Header=BB0_2 Depth=1
movl $.Lstr.14, %edi
callq puts@PLT
movq 296(%rsp), %rsi
shrq $20, %rsi
movl $.L.str.19, %edi
xorl %eax, %eax
callq printf
movq 360(%rsp), %rsi
shrq $10, %rsi
movl $.L.str.20, %edi
xorl %eax, %eax
callq printf
movq 320(%rsp), %rsi
shrq $20, %rsi
movl $.L.str.21, %edi
xorl %eax, %eax
callq printf
movq 376(%rsp), %rsi
movl $.L.str.22, %edi
xorl %eax, %eax
callq printf
movl 416(%rsp), %esi
movl $.L.str.23, %edi
xorl %eax, %eax
callq printf
movl 428(%rsp), %esi
movl 432(%rsp), %edx
movl $.L.str.24, %edi
xorl %eax, %eax
callq printf
movl 464(%rsp), %esi
movl 468(%rsp), %edx
movl 472(%rsp), %ecx
movl $.L.str.25, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.15, %edi
callq puts@PLT
movl 396(%rsp), %esi
movl $.L.str.27, %edi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
shrq $10, %rsi
movl $.L.str.28, %edi
xorl %eax, %eax
callq printf
movl 312(%rsp), %esi
movl $.L.str.29, %edi
xorl %eax, %eax
callq printf
movl 316(%rsp), %esi
movl $.L.str.30, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.31, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl 336(%rsp), %edx
movl 340(%rsp), %ecx
movl $.L.str.32, %edi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl 348(%rsp), %edx
movl 352(%rsp), %ecx
movl $.L.str.33, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.16, %edi
callq puts@PLT
incl %ebp
cmpl 4(%rsp), %ebp
jge .LBB0_9
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 368(%rsp), %esi
movl 372(%rsp), %edx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movslq 356(%rsp), %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rax
shrq $63, %rax
sarq $38, %rsi
addl %eax, %esi
movl $.L.str.4, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
cmpl $0, 404(%rsp)
movl $.Lstr.2, %edi
cmoveq %r14, %rdi
callq puts@PLT
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
cmpl $0, 392(%rsp)
movl $.Lstr.10, %edi
cmoveq %r15, %rdi
callq puts@PLT
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
cmpl $0, 400(%rsp)
movl $.Lstr.10, %edi
cmoveq %r15, %rdi
callq puts@PLT
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
cmpl $0, 408(%rsp)
movl $.Lstr.10, %edi
cmoveq %r15, %rdi
callq puts@PLT
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
cmpl $0, 584(%rsp)
movl $.Lstr.10, %edi
cmoveq %r15, %rdi
callq puts@PLT
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
cmpl $0, 412(%rsp)
je .LBB0_3
# %bb.4: # in Loop: Header=BB0_2 Depth=1
cmpl $1, 412(%rsp)
je .LBB0_5
.LBB0_6: # in Loop: Header=BB0_2 Depth=1
cmpl $2, 412(%rsp)
jne .LBB0_8
jmp .LBB0_7
.p2align 4, 0x90
.LBB0_3: # in Loop: Header=BB0_2 Depth=1
movl $.Lstr.11, %edi
callq puts@PLT
cmpl $1, 412(%rsp)
jne .LBB0_6
.LBB0_5: # in Loop: Header=BB0_2 Depth=1
movl $.Lstr.12, %edi
callq puts@PLT
cmpl $2, 412(%rsp)
jne .LBB0_8
.LBB0_7: # in Loop: Header=BB0_2 Depth=1
movl $.Lstr.13, %edi
callq puts@PLT
jmp .LBB0_8
.LBB0_9: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n****************************Device %d*************************************\n"
.size .L.str, 77
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Name: %s\n"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Compute capability: %d.%d\n"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Clock rate: %d MHz\n"
.size .L.str.4, 20
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "GPU type: "
.size .L.str.5, 11
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Device copy overlap: "
.size .L.str.8, 22
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Kernel execution timeout: "
.size .L.str.11, 27
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Mapping Host Memory into CUDA Device Address Space: "
.size .L.str.12, 53
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Executing Multiple Kernels Support: "
.size .L.str.13, 37
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Device Computing Mode: "
.size .L.str.14, 24
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Total Global Memory: %ld MB\n"
.size .L.str.19, 29
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "Total Constant Memory: %ld kB\n"
.size .L.str.20, 31
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "Max Memory Pitch Allowed for Memory Copies: %ld MB\n"
.size .L.str.21, 52
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "Texture Alignment: %ld B\n"
.size .L.str.22, 26
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "Max Size Supported for 1D Textures: %ld\n"
.size .L.str.23, 41
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "Max Dimensions Supported for 2D Texture: (%d, %d)\n"
.size .L.str.24, 51
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz "Max Dimensions Supported for 3D Texture: (%d, %d, %d)\n"
.size .L.str.25, 55
.type .L.str.27,@object # @.str.27
.L.str.27:
.asciz "Streaming Multiprocessor count: %d\n"
.size .L.str.27, 36
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz "Shared Memory per Block: %ld KB\n"
.size .L.str.28, 33
.type .L.str.29,@object # @.str.29
.L.str.29:
.asciz "Registers per Block: %ld\n"
.size .L.str.29, 26
.type .L.str.30,@object # @.str.30
.L.str.30:
.asciz "Threads in warp: %ld\n"
.size .L.str.30, 22
.type .L.str.31,@object # @.str.31
.L.str.31:
.asciz "Max threads per block: %d\n"
.size .L.str.31, 27
.type .L.str.32,@object # @.str.32
.L.str.32:
.asciz "Max thread dimensions: (%d, %d, %d)\n"
.size .L.str.32, 37
.type .L.str.33,@object # @.str.33
.L.str.33:
.asciz "Max grid dimensions: (%d, %d, %d)\n"
.size .L.str.33, 35
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "----------General Information----------"
.size .Lstr, 40
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Discreted GPU"
.size .Lstr.1, 14
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Integrated GPU"
.size .Lstr.2, 15
.type .Lstr.9,@object # @str.9
.Lstr.9:
.asciz "Disabled"
.size .Lstr.9, 9
.type .Lstr.10,@object # @str.10
.Lstr.10:
.asciz "Enabled"
.size .Lstr.10, 8
.type .Lstr.11,@object # @str.11
.Lstr.11:
.asciz "Default"
.size .Lstr.11, 8
.type .Lstr.12,@object # @str.12
.Lstr.12:
.asciz "Exclusive"
.size .Lstr.12, 10
.type .Lstr.13,@object # @str.13
.Lstr.13:
.asciz "Prohibited"
.size .Lstr.13, 11
.type .Lstr.14,@object # @str.14
.Lstr.14:
.asciz "\n----------Memory Information for device----------"
.size .Lstr.14, 51
.type .Lstr.15,@object # @str.15
.Lstr.15:
.asciz "\n----------Thread Information for device----------"
.size .Lstr.15, 51
.type .Lstr.16,@object # @str.16
.Lstr.16:
.asciz "*****************************************************************"
.size .Lstr.16, 66
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernelMultMat(int *a, int *b, int *c,int m){
int i,add;
int col=blockDim.x*blockIdx.x + threadIdx.x;
int row=blockDim.y*blockIdx.y + threadIdx.y;
if(col<m && row<m) {
add=0;
for(i=0; i< m ;i++){
add += a[i+m*row]*b[col+m*i];
}
c[row*m+col] = add;
}
} | code for sm_80
Function : _Z13kernelMultMatPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xbf0 ; /* 0x00000af000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xaf0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*01b0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fce00078e0219 */
/*01c0*/ @!P0 BRA 0x960 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6a0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0230*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0250*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0270*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0280*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*0290*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02a0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02b0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02c0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02d0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02e0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02f0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0300*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0310*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0320*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0330*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0340*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0350*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0360*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0370*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0380*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0390*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*03a0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03c0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03d0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03e0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*03f0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0400*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*0410*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0420*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0430*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0440*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0450*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0470*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0480*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0490*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*04a0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04b0*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*04c0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04d0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04e0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04f0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*0500*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0510*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0520*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0530*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0540*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0550*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0560*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0570*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0580*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05a0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05d0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05e0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05f0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*0600*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*0610*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0620*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0630*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0640*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0650*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0660*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0670*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0680*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0690*/ @P1 BRA 0x210 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x940 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06c0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06d0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06f0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0700*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0710*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0720*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0730*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0740*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0750*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0770*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0780*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0790*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07d0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07f0*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0800*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0810*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0830*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0840*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0850*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*08c0*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08d0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08e0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08f0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*0900*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*0910*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*0920*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0930*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0940*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xaf0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0970*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0980*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0990*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09b0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09c0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09e0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*09f0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a10*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a30*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a40*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a60*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a70*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a80*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a90*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0aa0*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0ab0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ac0*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0ad0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ae0*/ @P0 BRA 0x960 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0af0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b00*/ @!P0 BRA 0xbf0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b10*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b40*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b50*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b60*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b70*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bd0*/ IMAD R28, R11, R4, R28 ; /* 0x000000040b1c7224 */
/* 0x004fcc00078e021c */
/*0be0*/ @P0 BRA 0xb60 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernelMultMat(int *a, int *b, int *c,int m){
int i,add;
int col=blockDim.x*blockIdx.x + threadIdx.x;
int row=blockDim.y*blockIdx.y + threadIdx.y;
if(col<m && row<m) {
add=0;
for(i=0; i< m ;i++){
add += a[i+m*row]*b[col+m*i];
}
c[row*m+col] = add;
}
} | .file "tmpxft_00026fb9_00000000-6_kernelMultMat.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13kernelMultMatPiS_S_iPiS_S_i
.type _Z38__device_stub__Z13kernelMultMatPiS_S_iPiS_S_i, @function
_Z38__device_stub__Z13kernelMultMatPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13kernelMultMatPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z13kernelMultMatPiS_S_iPiS_S_i, .-_Z38__device_stub__Z13kernelMultMatPiS_S_iPiS_S_i
.globl _Z13kernelMultMatPiS_S_i
.type _Z13kernelMultMatPiS_S_i, @function
_Z13kernelMultMatPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13kernelMultMatPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13kernelMultMatPiS_S_i, .-_Z13kernelMultMatPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13kernelMultMatPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernelMultMatPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernelMultMat(int *a, int *b, int *c,int m){
int i,add;
int col=blockDim.x*blockIdx.x + threadIdx.x;
int row=blockDim.y*blockIdx.y + threadIdx.y;
if(col<m && row<m) {
add=0;
for(i=0; i< m ;i++){
add += a[i+m*row]*b[col+m*i];
}
c[row*m+col] = add;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernelMultMat(int *a, int *b, int *c,int m){
int i,add;
int col=blockDim.x*blockIdx.x + threadIdx.x;
int row=blockDim.y*blockIdx.y + threadIdx.y;
if(col<m && row<m) {
add=0;
for(i=0; i< m ;i++){
add += a[i+m*row]*b[col+m*i];
}
c[row*m+col] = add;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernelMultMat(int *a, int *b, int *c,int m){
int i,add;
int col=blockDim.x*blockIdx.x + threadIdx.x;
int row=blockDim.y*blockIdx.y + threadIdx.y;
if(col<m && row<m) {
add=0;
for(i=0; i< m ;i++){
add += a[i+m*row]*b[col+m*i];
}
c[row*m+col] = add;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13kernelMultMatPiS_S_i
.globl _Z13kernelMultMatPiS_S_i
.p2align 8
.type _Z13kernelMultMatPiS_S_i,@function
_Z13kernelMultMatPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_lg_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13kernelMultMatPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13kernelMultMatPiS_S_i, .Lfunc_end0-_Z13kernelMultMatPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13kernelMultMatPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13kernelMultMatPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernelMultMat(int *a, int *b, int *c,int m){
int i,add;
int col=blockDim.x*blockIdx.x + threadIdx.x;
int row=blockDim.y*blockIdx.y + threadIdx.y;
if(col<m && row<m) {
add=0;
for(i=0; i< m ;i++){
add += a[i+m*row]*b[col+m*i];
}
c[row*m+col] = add;
}
} | .text
.file "kernelMultMat.hip"
.globl _Z28__device_stub__kernelMultMatPiS_S_i # -- Begin function _Z28__device_stub__kernelMultMatPiS_S_i
.p2align 4, 0x90
.type _Z28__device_stub__kernelMultMatPiS_S_i,@function
_Z28__device_stub__kernelMultMatPiS_S_i: # @_Z28__device_stub__kernelMultMatPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13kernelMultMatPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__kernelMultMatPiS_S_i, .Lfunc_end0-_Z28__device_stub__kernelMultMatPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernelMultMatPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13kernelMultMatPiS_S_i,@object # @_Z13kernelMultMatPiS_S_i
.section .rodata,"a",@progbits
.globl _Z13kernelMultMatPiS_S_i
.p2align 3, 0x0
_Z13kernelMultMatPiS_S_i:
.quad _Z28__device_stub__kernelMultMatPiS_S_i
.size _Z13kernelMultMatPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13kernelMultMatPiS_S_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__kernelMultMatPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13kernelMultMatPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13kernelMultMatPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xbf0 ; /* 0x00000af000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xaf0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*01b0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fce00078e0219 */
/*01c0*/ @!P0 BRA 0x960 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6a0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0230*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0250*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0270*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0280*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*0290*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02a0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02b0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02c0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02d0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02e0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02f0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0300*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0310*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0320*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0330*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0340*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0350*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0360*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0370*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0380*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0390*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*03a0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03c0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03d0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03e0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*03f0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0400*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*0410*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0420*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0430*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0440*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0450*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0470*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0480*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0490*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*04a0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04b0*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*04c0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04d0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04e0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04f0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*0500*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0510*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0520*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0530*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0540*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0550*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0560*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0570*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0580*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05a0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05d0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05e0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05f0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*0600*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*0610*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0620*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0630*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0640*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0650*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0660*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0670*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0680*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0690*/ @P1 BRA 0x210 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x940 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06c0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06d0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06f0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0700*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0710*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0720*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0730*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0740*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0750*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0770*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0780*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0790*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07d0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07f0*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0800*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0810*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0830*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0840*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0850*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*08c0*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08d0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08e0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08f0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*0900*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*0910*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*0920*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0930*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0940*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xaf0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0970*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0980*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0990*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09b0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09c0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09e0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*09f0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a10*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a30*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a40*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a60*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a70*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a80*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a90*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0aa0*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0ab0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ac0*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0ad0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ae0*/ @P0 BRA 0x960 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0af0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b00*/ @!P0 BRA 0xbf0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b10*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b40*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b50*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b60*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b70*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bd0*/ IMAD R28, R11, R4, R28 ; /* 0x000000040b1c7224 */
/* 0x004fcc00078e021c */
/*0be0*/ @P0 BRA 0xb60 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13kernelMultMatPiS_S_i
.globl _Z13kernelMultMatPiS_S_i
.p2align 8
.type _Z13kernelMultMatPiS_S_i,@function
_Z13kernelMultMatPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_lg_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13kernelMultMatPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13kernelMultMatPiS_S_i, .Lfunc_end0-_Z13kernelMultMatPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13kernelMultMatPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13kernelMultMatPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00026fb9_00000000-6_kernelMultMat.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13kernelMultMatPiS_S_iPiS_S_i
.type _Z38__device_stub__Z13kernelMultMatPiS_S_iPiS_S_i, @function
_Z38__device_stub__Z13kernelMultMatPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13kernelMultMatPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z13kernelMultMatPiS_S_iPiS_S_i, .-_Z38__device_stub__Z13kernelMultMatPiS_S_iPiS_S_i
.globl _Z13kernelMultMatPiS_S_i
.type _Z13kernelMultMatPiS_S_i, @function
_Z13kernelMultMatPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13kernelMultMatPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13kernelMultMatPiS_S_i, .-_Z13kernelMultMatPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13kernelMultMatPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernelMultMatPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernelMultMat.hip"
.globl _Z28__device_stub__kernelMultMatPiS_S_i # -- Begin function _Z28__device_stub__kernelMultMatPiS_S_i
.p2align 4, 0x90
.type _Z28__device_stub__kernelMultMatPiS_S_i,@function
_Z28__device_stub__kernelMultMatPiS_S_i: # @_Z28__device_stub__kernelMultMatPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13kernelMultMatPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__kernelMultMatPiS_S_i, .Lfunc_end0-_Z28__device_stub__kernelMultMatPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernelMultMatPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13kernelMultMatPiS_S_i,@object # @_Z13kernelMultMatPiS_S_i
.section .rodata,"a",@progbits
.globl _Z13kernelMultMatPiS_S_i
.p2align 3, 0x0
_Z13kernelMultMatPiS_S_i:
.quad _Z28__device_stub__kernelMultMatPiS_S_i
.size _Z13kernelMultMatPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13kernelMultMatPiS_S_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__kernelMultMatPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13kernelMultMatPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "computing_gpu.cuh"
cufftComplex *h0;
cufftComplex *h_k;
cufftComplex *h_k_normalx;
cufftComplex *h_k_normaly;
cufftComplex *h0_minus;
curandGenerator_t gen;
float *randData;
float *term;
__constant__ cufftComplex _wind;
__constant__ float _Anorm;
__constant__ float _g;
__constant__ float _lx;
__constant__ float _lz;
extern "C" void cuda_init_h() {
cudaMalloc((void**)&h0, MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION * sizeof (cufftComplex));
cudaMalloc((void**)&h_k, MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION * sizeof (cufftComplex));
cudaMalloc((void**)&h_k_normalx, MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION * sizeof (cufftComplex));
cudaMalloc((void**)&h_k_normaly, MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION * sizeof (cufftComplex));
cudaMalloc((void**)&h0_minus, MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION * sizeof (cufftComplex));
float g = 9.81f;
cudaMemcpyToSymbol(_g, &g, sizeof (float));
cudaMalloc((void**)&randData, 2 * MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION * sizeof(float));
cudaMalloc((void**)&term, MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION * sizeof(float));
curandCreateGenerator(&gen,CURAND_RNG_PSEUDO_DEFAULT);
curandSetPseudoRandomGeneratorSeed(gen, 1234ULL);
}
__device__ cufftComplex get_h0(cufftComplex a, int i, int j, float *randData) {
cufftComplex res;
float norm1 = randData[2 * (i * MAX_WAVE_RESOLUTION + j)];
float norm2 = randData[2 * (i * MAX_WAVE_RESOLUTION + j) + 1];
float term;
float t = sqrt(_wind.x * _wind.x + _wind.y * _wind.y);
if (((a.x == 0) && (a.y == 0)) || (t == 0)) {
term = 0;
} else {
float l = t * t / _g;
float kl = sqrt(a.x * a.x + a.y * a.y);
float n1 = t * kl;
term = a.x * _wind.x / n1 + a.y * _wind.y / n1;
if (term < 0) {
term = 0;
} else {
float t1 = exp(-1 / (kl * kl * l * l));
term = _Anorm * t1 * term * term/ (kl * kl * kl * kl);
}
}
term = sqrt(term * 0.5);
res.x = norm1 * term;
res.y = norm2 * term;
return res;
}
__global__ void generationH0(cufftComplex *h0, cufftComplex *h0_minus, float *randData) {
int bx = threadIdx.x;
int by = blockIdx.x;
int num = bx + by * BLOCK_SIZE;
cufftComplex a;
cufftComplex am;
if (num < MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION) {
int i = num / MAX_WAVE_RESOLUTION;
int j = num - i * MAX_WAVE_RESOLUTION;
cufftComplex k;
cufftComplex km;
k.x = 2 * PI * (i - MAX_WAVE_RESOLUTION / 2) / _lx;
k.y = 2 * PI * (j - MAX_WAVE_RESOLUTION / 2) / _lz;
km.x = -k.x;
km.y = -k.y;
a = get_h0(k, i, j, randData);
am = get_h0(km, i, j, randData);
}
__syncthreads();
if (num < MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION) {
h0[num] = a;
h0_minus[num] = am;
}
}
//ïóñòü áóäóò ïåðåäàâàòüñÿ âñå ïàðàìåòðû
extern "C" void generation_h0(float lx, float lz, float windx, float windy, float anorm) {
cufftComplex wind;
wind.x = windx;
wind.y = windy;
cudaMemcpyToSymbol(_lx, &lx, sizeof (float));
cudaMemcpyToSymbol(_lz, &lz, sizeof (float));
cudaMemcpyToSymbol(_wind, &wind, sizeof (cufftComplex));
cudaMemcpyToSymbol(_Anorm, &anorm, sizeof (float));
curandGenerateNormal(gen, randData, 2 * MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION, 0.f, 1.f);
dim3 threads = dim3(BLOCK_SIZE);
dim3 blocks = dim3((int) ((MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION - 0.5) / threads.x) + 1);
generationH0 <<<blocks, threads>>> (h0, h0_minus, randData);
cudaDeviceSynchronize();
}
__device__ cufftComplex get_h(int i, int j, float t, cufftComplex *h0, cufftComplex *h0_minus) {
cufftComplex h_0 = h0[MAX_WAVE_RESOLUTION * i + j];
cufftComplex h_1 = h0_minus[MAX_WAVE_RESOLUTION * i + j];
cufftComplex a;
a.x = 2 * PI * (i - MAX_WAVE_RESOLUTION / 2) / _lx;
a.y = 2 * PI * (j - MAX_WAVE_RESOLUTION / 2) / _lz;
cufftComplex p;
cufftComplex hi;
cufftComplex pi;
float x = sqrt(_g * sqrt(a.x * a.x + a.y * a.y)) * t;
p.x = cos(x);
p.y = sin(x);
hi.x = h_1.x;
hi.y = -h_1.y;
pi.x = p.x;
pi.y = -p.y;
cufftComplex res;
res.x = h_0.x * p.x - h_0.y * p.y + hi.x * pi.x - hi.y * pi.y;
res.y = h_0.x * p.y + h_0.y * p.x + hi.x * pi.y + hi.y * pi.x;
return res;
}
__device__ int fftshift(int idx) {
if (idx >= MAX_WAVE_RESOLUTION / 2)
return idx - MAX_WAVE_RESOLUTION / 2;
else
return idx + MAX_WAVE_RESOLUTION / 2;
}
__global__ void generationHeight(float *t, cufftComplex * h_k, cufftComplex * h_k_normalx, cufftComplex * h_k_normaly, cufftComplex *h0, cufftComplex *h0_minus) {
int bx = threadIdx.x;
int by = blockIdx.x;
int num = bx + by * BLOCK_SIZE;
cufftComplex res;
int shifti;
int shiftj;
int i;
int j;
cufftComplex k;
if (num < MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION) {
i = num / MAX_WAVE_RESOLUTION;
j = num - i * MAX_WAVE_RESOLUTION;
shifti = fftshift(i);
shiftj = fftshift(j);
k.x = 2 * PI * (shifti - MAX_WAVE_RESOLUTION / 2) / _lx;
k.y = 2 * PI * (shiftj - MAX_WAVE_RESOLUTION / 2) / _lz;
cufftComplex term = get_h(i , j, *t, h0, h0_minus);
res = term;
}
__syncthreads();
if (num < MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION) {
h_k[shifti * MAX_WAVE_RESOLUTION + shiftj] = res;
h_k_normalx[shifti * MAX_WAVE_RESOLUTION + shiftj].x = -k.x * res.y;
h_k_normalx[shifti * MAX_WAVE_RESOLUTION + shiftj].y = k.x * res.x;
h_k_normaly[shifti * MAX_WAVE_RESOLUTION + shiftj].x = -k.y * res.y;
h_k_normaly[shifti * MAX_WAVE_RESOLUTION + shiftj].y = k.y * res.x;
}
}
extern "C" void generation_h(float t) {
dim3 threads = dim3(BLOCK_SIZE);
dim3 blocks = dim3((int) ((MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION - 0.5) / threads.x) + 1);
float* _t = NULL;
cudaMalloc ((void**)&_t, sizeof (float));
cudaMemcpy (_t, &t, sizeof (float), cudaMemcpyHostToDevice);
generationHeight <<<blocks, threads>>> (_t, h_k, h_k_normalx, h_k_normaly, h0, h0_minus);
cudaDeviceSynchronize();
}
__global__ void calc_density_mip0(cufftComplex * h, float * res) {
int bx = threadIdx.x;
int by = blockIdx.x;
int num = bx + by * BLOCK_SIZE;
int i = num / MAX_WAVE_RESOLUTION;
int j = num - i * MAX_WAVE_RESOLUTION;
float ans = 0;
if ((i < MAX_WAVE_RESOLUTION - 1) && (j < MAX_WAVE_RESOLUTION - 1)) {
float max_ = h[MAX_WAVE_RESOLUTION * i + j].x;
max_ = max(max_, h[MAX_WAVE_RESOLUTION * i + j + 1].x);
max_ = max(max_, h[MAX_WAVE_RESOLUTION * (i + 1) + j + 1].x);
max_ = max(max_, h[MAX_WAVE_RESOLUTION * (i + 1) + j].x);
float min_ = h[MAX_WAVE_RESOLUTION * i + j].x;
min_ = min(min_, h[MAX_WAVE_RESOLUTION * i + j + 1].x);
min_ = min(min_, h[MAX_WAVE_RESOLUTION * (i + 1) + j + 1].x);
min_ = min(min_, h[MAX_WAVE_RESOLUTION * (i + 1) + j].x);
ans = abs(max_ - min_);
}
__syncthreads();
if (num < MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION) {
res[i * MAX_WAVE_RESOLUTION + j] = h[MAX_WAVE_RESOLUTION * i + j].x;
}
}
extern "C" void density_mip0(float * calc, cufftComplex * res) {
dim3 threads = dim3(BLOCK_SIZE);
dim3 blocks = dim3((int) ((MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION - 0.5) / threads.x) + 1);
calc_density_mip0 <<<blocks, threads>>> (res, calc);
cudaDeviceSynchronize();
}
__global__ void calc_density_mip_next(float * den, float * term, int * size) {
int bx = threadIdx.x;
int by = blockIdx.x;
int num = bx + by * BLOCK_SIZE;
int i = num / (*size);
int j = num - i * (*size);
float ans = 0;
if (num < (*size) * (*size)) {
float max_ = den[4 * (*size) * i + 2 * j];
max_ = max(max_, den[4 * (*size) * i + 2 * (*size) + 2 * j]);
max_ = max(max_, den[4 * (*size) * i + 2 * j + 1]);
max_ = max(max_, den[4 * (*size) * i + 2 * (*size) + 2 * j + 1]);
ans = max_;
}
__syncthreads();
if (num < (*size) * (*size)) {
term[i * (*size) + j] = ans;
}
}
extern "C" void density_mip_next(float * calc, int size) {
dim3 threads = dim3(BLOCK_SIZE);
dim3 blocks = dim3((int) ((size * size - 0.5) / threads.x) + 1);
float * md;
int * size_;
cudaMalloc ((void**)&size_, sizeof (float));
cudaMemcpy (size_, &size, sizeof (float), cudaMemcpyHostToDevice);
calc_density_mip_next <<<blocks, threads>>> (calc, term, size_);
cudaError_t l;
l = cudaDeviceSynchronize();
l = cudaMemcpy (calc, term, size * size * sizeof (float), cudaMemcpyDeviceToDevice);
} | .file "tmpxft_00039936_00000000-6_computing_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl cuda_init_h
.type cuda_init_h, @function
cuda_init_h:
.LFB2050:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $524288, %esi
leaq h0(%rip), %rdi
call cudaMalloc@PLT
movl $524288, %esi
leaq h_k(%rip), %rdi
call cudaMalloc@PLT
movl $524288, %esi
leaq h_k_normalx(%rip), %rdi
call cudaMalloc@PLT
movl $524288, %esi
leaq h_k_normaly(%rip), %rdi
call cudaMalloc@PLT
movl $524288, %esi
leaq h0_minus(%rip), %rdi
call cudaMalloc@PLT
movl $0x411cf5c3, 4(%rsp)
leaq 4(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL2_g(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $524288, %esi
leaq randData(%rip), %rdi
call cudaMalloc@PLT
movl $262144, %esi
leaq term(%rip), %rdi
call cudaMalloc@PLT
movl $100, %esi
leaq gen(%rip), %rdi
call curandCreateGenerator@PLT
movl $1234, %esi
movq gen(%rip), %rdi
call curandSetPseudoRandomGeneratorSeed@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2050:
.size cuda_init_h, .-cuda_init_h
.globl _Z6get_h06float2iiPf
.type _Z6get_h06float2iiPf, @function
_Z6get_h06float2iiPf:
.LFB2051:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2051:
.size _Z6get_h06float2iiPf, .-_Z6get_h06float2iiPf
.globl _Z5get_hiifP6float2S0_
.type _Z5get_hiifP6float2S0_, @function
_Z5get_hiifP6float2S0_:
.LFB2053:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2053:
.size _Z5get_hiifP6float2S0_, .-_Z5get_hiifP6float2S0_
.globl _Z8fftshifti
.type _Z8fftshifti, @function
_Z8fftshifti:
.LFB2054:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2054:
.size _Z8fftshifti, .-_Z8fftshifti
.globl _Z43__device_stub__Z12generationH0P6float2S0_PfP6float2S0_Pf
.type _Z43__device_stub__Z12generationH0P6float2S0_PfP6float2S0_Pf, @function
_Z43__device_stub__Z12generationH0P6float2S0_PfP6float2S0_Pf:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12generationH0P6float2S0_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z43__device_stub__Z12generationH0P6float2S0_PfP6float2S0_Pf, .-_Z43__device_stub__Z12generationH0P6float2S0_PfP6float2S0_Pf
.globl _Z12generationH0P6float2S0_Pf
.type _Z12generationH0P6float2S0_Pf, @function
_Z12generationH0P6float2S0_Pf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z12generationH0P6float2S0_PfP6float2S0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12generationH0P6float2S0_Pf, .-_Z12generationH0P6float2S0_Pf
.globl generation_h0
.type generation_h0, @function
generation_h0:
.LFB2052:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm4, 4(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movss %xmm2, 24(%rsp)
movss %xmm3, 28(%rsp)
leaq 12(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL3_lx(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 8(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL3_lz(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 24(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq _ZL5_wind(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 4(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL6_Anorm(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movss .LC1(%rip), %xmm1
pxor %xmm0, %xmm0
movl $131072, %edx
movq randData(%rip), %rsi
movq gen(%rip), %rdi
call curandGenerateNormal@PLT
movl $1, 36(%rsp)
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $64, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L22:
call cudaDeviceSynchronize@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq randData(%rip), %rdx
movq h0_minus(%rip), %rsi
movq h0(%rip), %rdi
call _Z43__device_stub__Z12generationH0P6float2S0_PfP6float2S0_Pf
jmp .L22
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size generation_h0, .-generation_h0
.globl _Z56__device_stub__Z16generationHeightPfP6float2S1_S1_S1_S1_PfP6float2S1_S1_S1_S1_
.type _Z56__device_stub__Z16generationHeightPfP6float2S1_S1_S1_S1_PfP6float2S1_S1_S1_S1_, @function
_Z56__device_stub__Z16generationHeightPfP6float2S1_S1_S1_S1_PfP6float2S1_S1_S1_S1_:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16generationHeightPfP6float2S1_S1_S1_S1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z56__device_stub__Z16generationHeightPfP6float2S1_S1_S1_S1_PfP6float2S1_S1_S1_S1_, .-_Z56__device_stub__Z16generationHeightPfP6float2S1_S1_S1_S1_PfP6float2S1_S1_S1_S1_
.globl _Z16generationHeightPfP6float2S1_S1_S1_S1_
.type _Z16generationHeightPfP6float2S1_S1_S1_S1_, @function
_Z16generationHeightPfP6float2S1_S1_S1_S1_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__Z16generationHeightPfP6float2S1_S1_S1_S1_PfP6float2S1_S1_S1_S1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z16generationHeightPfP6float2S1_S1_S1_S1_, .-_Z16generationHeightPfP6float2S1_S1_S1_S1_
.globl generation_h
.type generation_h, @function
generation_h:
.LFB2055:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 32(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L36:
call cudaDeviceSynchronize@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movq h0_minus(%rip), %r9
movq h0(%rip), %r8
movq h_k_normaly(%rip), %rcx
movq h_k_normalx(%rip), %rdx
movq h_k(%rip), %rsi
movq 24(%rsp), %rdi
call _Z56__device_stub__Z16generationHeightPfP6float2S1_S1_S1_S1_PfP6float2S1_S1_S1_S1_
jmp .L36
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size generation_h, .-generation_h
.globl _Z45__device_stub__Z17calc_density_mip0P6float2PfP6float2Pf
.type _Z45__device_stub__Z17calc_density_mip0P6float2PfP6float2Pf, @function
_Z45__device_stub__Z17calc_density_mip0P6float2PfP6float2Pf:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17calc_density_mip0P6float2Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z45__device_stub__Z17calc_density_mip0P6float2PfP6float2Pf, .-_Z45__device_stub__Z17calc_density_mip0P6float2PfP6float2Pf
.globl _Z17calc_density_mip0P6float2Pf
.type _Z17calc_density_mip0P6float2Pf, @function
_Z17calc_density_mip0P6float2Pf:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z17calc_density_mip0P6float2PfP6float2Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z17calc_density_mip0P6float2Pf, .-_Z17calc_density_mip0P6float2Pf
.globl density_mip0
.type density_mip0, @function
density_mip0:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %rbx
movl $1, 12(%rsp)
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $64, 8(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L50:
call cudaDeviceSynchronize@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movq %rbp, %rsi
movq %rbx, %rdi
call _Z45__device_stub__Z17calc_density_mip0P6float2PfP6float2Pf
jmp .L50
.cfi_endproc
.LFE2056:
.size density_mip0, .-density_mip0
.globl _Z45__device_stub__Z21calc_density_mip_nextPfS_PiPfS_Pi
.type _Z45__device_stub__Z21calc_density_mip_nextPfS_PiPfS_Pi, @function
_Z45__device_stub__Z21calc_density_mip_nextPfS_PiPfS_Pi:
.LFB2088:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L57
.L53:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L58
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21calc_density_mip_nextPfS_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L53
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z45__device_stub__Z21calc_density_mip_nextPfS_PiPfS_Pi, .-_Z45__device_stub__Z21calc_density_mip_nextPfS_PiPfS_Pi
.globl _Z21calc_density_mip_nextPfS_Pi
.type _Z21calc_density_mip_nextPfS_Pi, @function
_Z21calc_density_mip_nextPfS_Pi:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z21calc_density_mip_nextPfS_PiPfS_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z21calc_density_mip_nextPfS_Pi, .-_Z21calc_density_mip_nextPfS_Pi
.globl density_mip_next
.type density_mip_next, @function
density_mip_next:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movl %esi, %eax
movl %esi, 12(%rsp)
movq %fs:40, %rdx
movq %rdx, 56(%rsp)
xorl %edx, %edx
movl $1, 36(%rsp)
movl $1, 40(%rsp)
imull %esi, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
subsd .LC3(%rip), %xmm0
mulsd .LC4(%rip), %xmm0
cvttsd2sil %xmm0, %eax
addl $1, %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 32(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L62:
call cudaDeviceSynchronize@PLT
movl 12(%rsp), %edx
imull %edx, %edx
movslq %edx, %rdx
salq $2, %rdx
movl $3, %ecx
movq term(%rip), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L66
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
movq 24(%rsp), %rdx
movq term(%rip), %rsi
movq %rbx, %rdi
call _Z45__device_stub__Z21calc_density_mip_nextPfS_PiPfS_Pi
jmp .L62
.L66:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size density_mip_next, .-density_mip_next
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z21calc_density_mip_nextPfS_Pi"
.align 8
.LC6:
.string "_Z17calc_density_mip0P6float2Pf"
.align 8
.LC7:
.string "_Z16generationHeightPfP6float2S1_S1_S1_S1_"
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string "_Z12generationH0P6float2S0_Pf"
.LC9:
.string "_wind"
.LC10:
.string "_Anorm"
.LC11:
.string "_g"
.LC12:
.string "_lx"
.LC13:
.string "_lz"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z21calc_density_mip_nextPfS_Pi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z17calc_density_mip0P6float2Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z16generationHeightPfP6float2S1_S1_S1_S1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z12generationH0P6float2S0_Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5_wind(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6_Anorm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2_g(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3_lx(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3_lz(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3_lz
.comm _ZL3_lz,4,4
.local _ZL3_lx
.comm _ZL3_lx,4,4
.local _ZL2_g
.comm _ZL2_g,4,4
.local _ZL6_Anorm
.comm _ZL6_Anorm,4,4
.local _ZL5_wind
.comm _ZL5_wind,8,8
.globl term
.bss
.align 8
.type term, @object
.size term, 8
term:
.zero 8
.globl randData
.align 8
.type randData, @object
.size randData, 8
randData:
.zero 8
.globl gen
.align 8
.type gen, @object
.size gen, 8
gen:
.zero 8
.globl h0_minus
.align 8
.type h0_minus, @object
.size h0_minus, 8
h0_minus:
.zero 8
.globl h_k_normaly
.align 8
.type h_k_normaly, @object
.size h_k_normaly, 8
h_k_normaly:
.zero 8
.globl h_k_normalx
.align 8
.type h_k_normalx, @object
.size h_k_normalx, 8
h_k_normalx:
.zero 8
.globl h_k
.align 8
.type h_k, @object
.size h_k, 8
h_k:
.zero 8
.globl h0
.align 8
.type h0, @object
.size h0, 8
h0:
.zero 8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1071644672
.align 8
.LC4:
.long 0
.long 1066401792
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "computing_gpu.cuh"
cufftComplex *h0;
cufftComplex *h_k;
cufftComplex *h_k_normalx;
cufftComplex *h_k_normaly;
cufftComplex *h0_minus;
curandGenerator_t gen;
float *randData;
float *term;
__constant__ cufftComplex _wind;
__constant__ float _Anorm;
__constant__ float _g;
__constant__ float _lx;
__constant__ float _lz;
extern "C" void cuda_init_h() {
cudaMalloc((void**)&h0, MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION * sizeof (cufftComplex));
cudaMalloc((void**)&h_k, MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION * sizeof (cufftComplex));
cudaMalloc((void**)&h_k_normalx, MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION * sizeof (cufftComplex));
cudaMalloc((void**)&h_k_normaly, MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION * sizeof (cufftComplex));
cudaMalloc((void**)&h0_minus, MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION * sizeof (cufftComplex));
float g = 9.81f;
cudaMemcpyToSymbol(_g, &g, sizeof (float));
cudaMalloc((void**)&randData, 2 * MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION * sizeof(float));
cudaMalloc((void**)&term, MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION * sizeof(float));
curandCreateGenerator(&gen,CURAND_RNG_PSEUDO_DEFAULT);
curandSetPseudoRandomGeneratorSeed(gen, 1234ULL);
}
__device__ cufftComplex get_h0(cufftComplex a, int i, int j, float *randData) {
cufftComplex res;
float norm1 = randData[2 * (i * MAX_WAVE_RESOLUTION + j)];
float norm2 = randData[2 * (i * MAX_WAVE_RESOLUTION + j) + 1];
float term;
float t = sqrt(_wind.x * _wind.x + _wind.y * _wind.y);
if (((a.x == 0) && (a.y == 0)) || (t == 0)) {
term = 0;
} else {
float l = t * t / _g;
float kl = sqrt(a.x * a.x + a.y * a.y);
float n1 = t * kl;
term = a.x * _wind.x / n1 + a.y * _wind.y / n1;
if (term < 0) {
term = 0;
} else {
float t1 = exp(-1 / (kl * kl * l * l));
term = _Anorm * t1 * term * term/ (kl * kl * kl * kl);
}
}
term = sqrt(term * 0.5);
res.x = norm1 * term;
res.y = norm2 * term;
return res;
}
__global__ void generationH0(cufftComplex *h0, cufftComplex *h0_minus, float *randData) {
int bx = threadIdx.x;
int by = blockIdx.x;
int num = bx + by * BLOCK_SIZE;
cufftComplex a;
cufftComplex am;
if (num < MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION) {
int i = num / MAX_WAVE_RESOLUTION;
int j = num - i * MAX_WAVE_RESOLUTION;
cufftComplex k;
cufftComplex km;
k.x = 2 * PI * (i - MAX_WAVE_RESOLUTION / 2) / _lx;
k.y = 2 * PI * (j - MAX_WAVE_RESOLUTION / 2) / _lz;
km.x = -k.x;
km.y = -k.y;
a = get_h0(k, i, j, randData);
am = get_h0(km, i, j, randData);
}
__syncthreads();
if (num < MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION) {
h0[num] = a;
h0_minus[num] = am;
}
}
//ïóñòü áóäóò ïåðåäàâàòüñÿ âñå ïàðàìåòðû
extern "C" void generation_h0(float lx, float lz, float windx, float windy, float anorm) {
cufftComplex wind;
wind.x = windx;
wind.y = windy;
cudaMemcpyToSymbol(_lx, &lx, sizeof (float));
cudaMemcpyToSymbol(_lz, &lz, sizeof (float));
cudaMemcpyToSymbol(_wind, &wind, sizeof (cufftComplex));
cudaMemcpyToSymbol(_Anorm, &anorm, sizeof (float));
curandGenerateNormal(gen, randData, 2 * MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION, 0.f, 1.f);
dim3 threads = dim3(BLOCK_SIZE);
dim3 blocks = dim3((int) ((MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION - 0.5) / threads.x) + 1);
generationH0 <<<blocks, threads>>> (h0, h0_minus, randData);
cudaDeviceSynchronize();
}
__device__ cufftComplex get_h(int i, int j, float t, cufftComplex *h0, cufftComplex *h0_minus) {
cufftComplex h_0 = h0[MAX_WAVE_RESOLUTION * i + j];
cufftComplex h_1 = h0_minus[MAX_WAVE_RESOLUTION * i + j];
cufftComplex a;
a.x = 2 * PI * (i - MAX_WAVE_RESOLUTION / 2) / _lx;
a.y = 2 * PI * (j - MAX_WAVE_RESOLUTION / 2) / _lz;
cufftComplex p;
cufftComplex hi;
cufftComplex pi;
float x = sqrt(_g * sqrt(a.x * a.x + a.y * a.y)) * t;
p.x = cos(x);
p.y = sin(x);
hi.x = h_1.x;
hi.y = -h_1.y;
pi.x = p.x;
pi.y = -p.y;
cufftComplex res;
res.x = h_0.x * p.x - h_0.y * p.y + hi.x * pi.x - hi.y * pi.y;
res.y = h_0.x * p.y + h_0.y * p.x + hi.x * pi.y + hi.y * pi.x;
return res;
}
__device__ int fftshift(int idx) {
if (idx >= MAX_WAVE_RESOLUTION / 2)
return idx - MAX_WAVE_RESOLUTION / 2;
else
return idx + MAX_WAVE_RESOLUTION / 2;
}
__global__ void generationHeight(float *t, cufftComplex * h_k, cufftComplex * h_k_normalx, cufftComplex * h_k_normaly, cufftComplex *h0, cufftComplex *h0_minus) {
int bx = threadIdx.x;
int by = blockIdx.x;
int num = bx + by * BLOCK_SIZE;
cufftComplex res;
int shifti;
int shiftj;
int i;
int j;
cufftComplex k;
if (num < MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION) {
i = num / MAX_WAVE_RESOLUTION;
j = num - i * MAX_WAVE_RESOLUTION;
shifti = fftshift(i);
shiftj = fftshift(j);
k.x = 2 * PI * (shifti - MAX_WAVE_RESOLUTION / 2) / _lx;
k.y = 2 * PI * (shiftj - MAX_WAVE_RESOLUTION / 2) / _lz;
cufftComplex term = get_h(i , j, *t, h0, h0_minus);
res = term;
}
__syncthreads();
if (num < MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION) {
h_k[shifti * MAX_WAVE_RESOLUTION + shiftj] = res;
h_k_normalx[shifti * MAX_WAVE_RESOLUTION + shiftj].x = -k.x * res.y;
h_k_normalx[shifti * MAX_WAVE_RESOLUTION + shiftj].y = k.x * res.x;
h_k_normaly[shifti * MAX_WAVE_RESOLUTION + shiftj].x = -k.y * res.y;
h_k_normaly[shifti * MAX_WAVE_RESOLUTION + shiftj].y = k.y * res.x;
}
}
extern "C" void generation_h(float t) {
dim3 threads = dim3(BLOCK_SIZE);
dim3 blocks = dim3((int) ((MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION - 0.5) / threads.x) + 1);
float* _t = NULL;
cudaMalloc ((void**)&_t, sizeof (float));
cudaMemcpy (_t, &t, sizeof (float), cudaMemcpyHostToDevice);
generationHeight <<<blocks, threads>>> (_t, h_k, h_k_normalx, h_k_normaly, h0, h0_minus);
cudaDeviceSynchronize();
}
__global__ void calc_density_mip0(cufftComplex * h, float * res) {
int bx = threadIdx.x;
int by = blockIdx.x;
int num = bx + by * BLOCK_SIZE;
int i = num / MAX_WAVE_RESOLUTION;
int j = num - i * MAX_WAVE_RESOLUTION;
float ans = 0;
if ((i < MAX_WAVE_RESOLUTION - 1) && (j < MAX_WAVE_RESOLUTION - 1)) {
float max_ = h[MAX_WAVE_RESOLUTION * i + j].x;
max_ = max(max_, h[MAX_WAVE_RESOLUTION * i + j + 1].x);
max_ = max(max_, h[MAX_WAVE_RESOLUTION * (i + 1) + j + 1].x);
max_ = max(max_, h[MAX_WAVE_RESOLUTION * (i + 1) + j].x);
float min_ = h[MAX_WAVE_RESOLUTION * i + j].x;
min_ = min(min_, h[MAX_WAVE_RESOLUTION * i + j + 1].x);
min_ = min(min_, h[MAX_WAVE_RESOLUTION * (i + 1) + j + 1].x);
min_ = min(min_, h[MAX_WAVE_RESOLUTION * (i + 1) + j].x);
ans = abs(max_ - min_);
}
__syncthreads();
if (num < MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION) {
res[i * MAX_WAVE_RESOLUTION + j] = h[MAX_WAVE_RESOLUTION * i + j].x;
}
}
extern "C" void density_mip0(float * calc, cufftComplex * res) {
dim3 threads = dim3(BLOCK_SIZE);
dim3 blocks = dim3((int) ((MAX_WAVE_RESOLUTION * MAX_WAVE_RESOLUTION - 0.5) / threads.x) + 1);
calc_density_mip0 <<<blocks, threads>>> (res, calc);
cudaDeviceSynchronize();
}
__global__ void calc_density_mip_next(float * den, float * term, int * size) {
int bx = threadIdx.x;
int by = blockIdx.x;
int num = bx + by * BLOCK_SIZE;
int i = num / (*size);
int j = num - i * (*size);
float ans = 0;
if (num < (*size) * (*size)) {
float max_ = den[4 * (*size) * i + 2 * j];
max_ = max(max_, den[4 * (*size) * i + 2 * (*size) + 2 * j]);
max_ = max(max_, den[4 * (*size) * i + 2 * j + 1]);
max_ = max(max_, den[4 * (*size) * i + 2 * (*size) + 2 * j + 1]);
ans = max_;
}
__syncthreads();
if (num < (*size) * (*size)) {
term[i * (*size) + j] = ans;
}
}
extern "C" void density_mip_next(float * calc, int size) {
dim3 threads = dim3(BLOCK_SIZE);
dim3 blocks = dim3((int) ((size * size - 0.5) / threads.x) + 1);
float * md;
int * size_;
cudaMalloc ((void**)&size_, sizeof (float));
cudaMemcpy (size_, &size, sizeof (float), cudaMemcpyHostToDevice);
calc_density_mip_next <<<blocks, threads>>> (calc, term, size_);
cudaError_t l;
l = cudaDeviceSynchronize();
l = cudaMemcpy (calc, term, size * size * sizeof (float), cudaMemcpyDeviceToDevice);
} | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <hipfft/hipfft.h>
#include <hiprand/hiprand.h>
#define MAX_WAVE_RESOLUTION 256
#define BLOCK_SIZE 64
#define PI 3.141592653589793238f
extern "C" hipfftComplex *h0;
extern "C" hipfftComplex *h_k;
extern "C" hipfftComplex *h_k_normalx;
extern "C" hipfftComplex *h_k_normaly;
extern "C" hipfftComplex *h0_minus;
extern "C" hipGraphicsResource * resource1;
extern "C" void cuda_init_h();
extern "C" void generation_h0(float lx, float lz, float windx, float windy, float anorm);
extern "C" void generation_h(float t);
extern "C" void density_mip0(float * calc, hipfftComplex * h_field);
extern "C" void density_mip_next(float * calc, int size); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <hipfft/hipfft.h>
#include <hiprand/hiprand.h>
#define MAX_WAVE_RESOLUTION 256
#define BLOCK_SIZE 64
#define PI 3.141592653589793238f
extern "C" hipfftComplex *h0;
extern "C" hipfftComplex *h_k;
extern "C" hipfftComplex *h_k_normalx;
extern "C" hipfftComplex *h_k_normaly;
extern "C" hipfftComplex *h0_minus;
extern "C" hipGraphicsResource * resource1;
extern "C" void cuda_init_h();
extern "C" void generation_h0(float lx, float lz, float windx, float windy, float anorm);
extern "C" void generation_h(float t);
extern "C" void density_mip0(float * calc, hipfftComplex * h_field);
extern "C" void density_mip_next(float * calc, int size); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <hipfft/hipfft.h>
#include <hiprand/hiprand.h>
#define MAX_WAVE_RESOLUTION 256
#define BLOCK_SIZE 64
#define PI 3.141592653589793238f
extern "C" hipfftComplex *h0;
extern "C" hipfftComplex *h_k;
extern "C" hipfftComplex *h_k_normalx;
extern "C" hipfftComplex *h_k_normaly;
extern "C" hipfftComplex *h0_minus;
extern "C" hipGraphicsResource * resource1;
extern "C" void cuda_init_h();
extern "C" void generation_h0(float lx, float lz, float windx, float windy, float anorm);
extern "C" void generation_h(float t);
extern "C" void density_mip0(float * calc, hipfftComplex * h_field);
extern "C" void density_mip_next(float * calc, int size); | .text
.file "computing_gpu.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00039936_00000000-6_computing_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl cuda_init_h
.type cuda_init_h, @function
cuda_init_h:
.LFB2050:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $524288, %esi
leaq h0(%rip), %rdi
call cudaMalloc@PLT
movl $524288, %esi
leaq h_k(%rip), %rdi
call cudaMalloc@PLT
movl $524288, %esi
leaq h_k_normalx(%rip), %rdi
call cudaMalloc@PLT
movl $524288, %esi
leaq h_k_normaly(%rip), %rdi
call cudaMalloc@PLT
movl $524288, %esi
leaq h0_minus(%rip), %rdi
call cudaMalloc@PLT
movl $0x411cf5c3, 4(%rsp)
leaq 4(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL2_g(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $524288, %esi
leaq randData(%rip), %rdi
call cudaMalloc@PLT
movl $262144, %esi
leaq term(%rip), %rdi
call cudaMalloc@PLT
movl $100, %esi
leaq gen(%rip), %rdi
call curandCreateGenerator@PLT
movl $1234, %esi
movq gen(%rip), %rdi
call curandSetPseudoRandomGeneratorSeed@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2050:
.size cuda_init_h, .-cuda_init_h
.globl _Z6get_h06float2iiPf
.type _Z6get_h06float2iiPf, @function
_Z6get_h06float2iiPf:
.LFB2051:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2051:
.size _Z6get_h06float2iiPf, .-_Z6get_h06float2iiPf
.globl _Z5get_hiifP6float2S0_
.type _Z5get_hiifP6float2S0_, @function
_Z5get_hiifP6float2S0_:
.LFB2053:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2053:
.size _Z5get_hiifP6float2S0_, .-_Z5get_hiifP6float2S0_
.globl _Z8fftshifti
.type _Z8fftshifti, @function
_Z8fftshifti:
.LFB2054:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2054:
.size _Z8fftshifti, .-_Z8fftshifti
.globl _Z43__device_stub__Z12generationH0P6float2S0_PfP6float2S0_Pf
.type _Z43__device_stub__Z12generationH0P6float2S0_PfP6float2S0_Pf, @function
_Z43__device_stub__Z12generationH0P6float2S0_PfP6float2S0_Pf:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12generationH0P6float2S0_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z43__device_stub__Z12generationH0P6float2S0_PfP6float2S0_Pf, .-_Z43__device_stub__Z12generationH0P6float2S0_PfP6float2S0_Pf
.globl _Z12generationH0P6float2S0_Pf
.type _Z12generationH0P6float2S0_Pf, @function
_Z12generationH0P6float2S0_Pf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z12generationH0P6float2S0_PfP6float2S0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12generationH0P6float2S0_Pf, .-_Z12generationH0P6float2S0_Pf
.globl generation_h0
.type generation_h0, @function
generation_h0:
.LFB2052:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm4, 4(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movss %xmm2, 24(%rsp)
movss %xmm3, 28(%rsp)
leaq 12(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL3_lx(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 8(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL3_lz(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 24(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $8, %edx
leaq _ZL5_wind(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 4(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL6_Anorm(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movss .LC1(%rip), %xmm1
pxor %xmm0, %xmm0
movl $131072, %edx
movq randData(%rip), %rsi
movq gen(%rip), %rdi
call curandGenerateNormal@PLT
movl $1, 36(%rsp)
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $64, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L22:
call cudaDeviceSynchronize@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq randData(%rip), %rdx
movq h0_minus(%rip), %rsi
movq h0(%rip), %rdi
call _Z43__device_stub__Z12generationH0P6float2S0_PfP6float2S0_Pf
jmp .L22
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size generation_h0, .-generation_h0
.globl _Z56__device_stub__Z16generationHeightPfP6float2S1_S1_S1_S1_PfP6float2S1_S1_S1_S1_
.type _Z56__device_stub__Z16generationHeightPfP6float2S1_S1_S1_S1_PfP6float2S1_S1_S1_S1_, @function
_Z56__device_stub__Z16generationHeightPfP6float2S1_S1_S1_S1_PfP6float2S1_S1_S1_S1_:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16generationHeightPfP6float2S1_S1_S1_S1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z56__device_stub__Z16generationHeightPfP6float2S1_S1_S1_S1_PfP6float2S1_S1_S1_S1_, .-_Z56__device_stub__Z16generationHeightPfP6float2S1_S1_S1_S1_PfP6float2S1_S1_S1_S1_
.globl _Z16generationHeightPfP6float2S1_S1_S1_S1_
.type _Z16generationHeightPfP6float2S1_S1_S1_S1_, @function
_Z16generationHeightPfP6float2S1_S1_S1_S1_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__Z16generationHeightPfP6float2S1_S1_S1_S1_PfP6float2S1_S1_S1_S1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z16generationHeightPfP6float2S1_S1_S1_S1_, .-_Z16generationHeightPfP6float2S1_S1_S1_S1_
.globl generation_h
.type generation_h, @function
generation_h:
.LFB2055:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 32(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L36:
call cudaDeviceSynchronize@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movq h0_minus(%rip), %r9
movq h0(%rip), %r8
movq h_k_normaly(%rip), %rcx
movq h_k_normalx(%rip), %rdx
movq h_k(%rip), %rsi
movq 24(%rsp), %rdi
call _Z56__device_stub__Z16generationHeightPfP6float2S1_S1_S1_S1_PfP6float2S1_S1_S1_S1_
jmp .L36
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size generation_h, .-generation_h
.globl _Z45__device_stub__Z17calc_density_mip0P6float2PfP6float2Pf
.type _Z45__device_stub__Z17calc_density_mip0P6float2PfP6float2Pf, @function
_Z45__device_stub__Z17calc_density_mip0P6float2PfP6float2Pf:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17calc_density_mip0P6float2Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z45__device_stub__Z17calc_density_mip0P6float2PfP6float2Pf, .-_Z45__device_stub__Z17calc_density_mip0P6float2PfP6float2Pf
.globl _Z17calc_density_mip0P6float2Pf
.type _Z17calc_density_mip0P6float2Pf, @function
_Z17calc_density_mip0P6float2Pf:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z17calc_density_mip0P6float2PfP6float2Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z17calc_density_mip0P6float2Pf, .-_Z17calc_density_mip0P6float2Pf
.globl density_mip0
.type density_mip0, @function
density_mip0:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %rbx
movl $1, 12(%rsp)
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $64, 8(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L50:
call cudaDeviceSynchronize@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movq %rbp, %rsi
movq %rbx, %rdi
call _Z45__device_stub__Z17calc_density_mip0P6float2PfP6float2Pf
jmp .L50
.cfi_endproc
.LFE2056:
.size density_mip0, .-density_mip0
.globl _Z45__device_stub__Z21calc_density_mip_nextPfS_PiPfS_Pi
.type _Z45__device_stub__Z21calc_density_mip_nextPfS_PiPfS_Pi, @function
_Z45__device_stub__Z21calc_density_mip_nextPfS_PiPfS_Pi:
.LFB2088:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L57
.L53:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L58
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21calc_density_mip_nextPfS_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L53
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z45__device_stub__Z21calc_density_mip_nextPfS_PiPfS_Pi, .-_Z45__device_stub__Z21calc_density_mip_nextPfS_PiPfS_Pi
.globl _Z21calc_density_mip_nextPfS_Pi
.type _Z21calc_density_mip_nextPfS_Pi, @function
_Z21calc_density_mip_nextPfS_Pi:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z21calc_density_mip_nextPfS_PiPfS_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z21calc_density_mip_nextPfS_Pi, .-_Z21calc_density_mip_nextPfS_Pi
.globl density_mip_next
.type density_mip_next, @function
density_mip_next:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movl %esi, %eax
movl %esi, 12(%rsp)
movq %fs:40, %rdx
movq %rdx, 56(%rsp)
xorl %edx, %edx
movl $1, 36(%rsp)
movl $1, 40(%rsp)
imull %esi, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
subsd .LC3(%rip), %xmm0
mulsd .LC4(%rip), %xmm0
cvttsd2sil %xmm0, %eax
addl $1, %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 32(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L62:
call cudaDeviceSynchronize@PLT
movl 12(%rsp), %edx
imull %edx, %edx
movslq %edx, %rdx
salq $2, %rdx
movl $3, %ecx
movq term(%rip), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L66
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
movq 24(%rsp), %rdx
movq term(%rip), %rsi
movq %rbx, %rdi
call _Z45__device_stub__Z21calc_density_mip_nextPfS_PiPfS_Pi
jmp .L62
.L66:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size density_mip_next, .-density_mip_next
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z21calc_density_mip_nextPfS_Pi"
.align 8
.LC6:
.string "_Z17calc_density_mip0P6float2Pf"
.align 8
.LC7:
.string "_Z16generationHeightPfP6float2S1_S1_S1_S1_"
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string "_Z12generationH0P6float2S0_Pf"
.LC9:
.string "_wind"
.LC10:
.string "_Anorm"
.LC11:
.string "_g"
.LC12:
.string "_lx"
.LC13:
.string "_lz"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z21calc_density_mip_nextPfS_Pi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z17calc_density_mip0P6float2Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z16generationHeightPfP6float2S1_S1_S1_S1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z12generationH0P6float2S0_Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5_wind(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6_Anorm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2_g(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3_lx(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3_lz(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL3_lz
.comm _ZL3_lz,4,4
.local _ZL3_lx
.comm _ZL3_lx,4,4
.local _ZL2_g
.comm _ZL2_g,4,4
.local _ZL6_Anorm
.comm _ZL6_Anorm,4,4
.local _ZL5_wind
.comm _ZL5_wind,8,8
.globl term
.bss
.align 8
.type term, @object
.size term, 8
term:
.zero 8
.globl randData
.align 8
.type randData, @object
.size randData, 8
randData:
.zero 8
.globl gen
.align 8
.type gen, @object
.size gen, 8
gen:
.zero 8
.globl h0_minus
.align 8
.type h0_minus, @object
.size h0_minus, 8
h0_minus:
.zero 8
.globl h_k_normaly
.align 8
.type h_k_normaly, @object
.size h_k_normaly, 8
h_k_normaly:
.zero 8
.globl h_k_normalx
.align 8
.type h_k_normalx, @object
.size h_k_normalx, 8
h_k_normalx:
.zero 8
.globl h_k
.align 8
.type h_k, @object
.size h_k, 8
h_k:
.zero 8
.globl h0
.align 8
.type h0, @object
.size h0, 8
h0:
.zero 8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1071644672
.align 8
.LC4:
.long 0
.long 1066401792
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "computing_gpu.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Match3(float *d_pts1, float *d_pts2, float *d_score, int *d_index)
{
__shared__ float buffer1[M2W*(NDIM + 1)]; //%%%%
__shared__ float buffer2[M2H*NDIM];
__shared__ float scores[M2W*M2H];
int tx = threadIdx.x;
int ty = threadIdx.y;
int idx = tx + M2W*ty;
int bp1 = M2W*blockIdx.x;
if (ty<M2W)
for (int d=tx;d<NDIM;d+=M2W)
for (int j=ty;j<M2W;j+=M2H)
buffer1[j*(NDIM + 1) + d] = d_pts1[(bp1 + j)*NDIM + d]; //%%%%
__syncthreads();
float max_score = 0.0f;
int index = -1;
for (int bp2=0;bp2<NPTS;bp2+=M2H) {
for (int d=tx;d<NDIM;d+=M2W)
buffer2[ty*NDIM + d] = d_pts2[(bp2 + ty)*NDIM + d];
__syncthreads();
float score = 0.0f;
for (int d=0;d<NDIM;d++)
score += buffer1[tx*(NDIM + 1) + d]*buffer2[ty*NDIM + d]; //%%%%
scores[idx] = score;
__syncthreads();
if (ty==0) {
for (int i=0;i<M2H;i++) {
if (scores[i*M2W + tx]>max_score) {
max_score = scores[i*M2W + tx];
index = bp2 + i;
}
}
}
__syncthreads();
}
if (ty==0) {
d_score[bp1 + tx] = max_score;
d_index[bp1 + tx] = index;
}
} | code for sm_80
Function : _Z6Match3PfS_S_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x400 ; /* 0x000003c000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ ISETP.GT.AND P1, PT, R4, 0x7f, PT ; /* 0x0000007f0400780c */
/* 0x001fc80003f24270 */
/*0060*/ ISETP.GT.OR P0, PT, R3, 0xf, P1 ; /* 0x0000000f0300780c */
/* 0x002fda0000f04670 */
/*0070*/ @P0 BRA 0x3f0 ; /* 0x0000037000000947 */
/* 0x000fea0003800000 */
/*0080*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0090*/ IMNMX R2, RZ, R3, !PT ; /* 0x00000003ff027217 */
/* 0x000fe20007800200 */
/*00a0*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0004 */
/*00b0*/ IADD3 R5, R3.reuse, 0x10, RZ ; /* 0x0000001003057810 */
/* 0x040fe40007ffe0ff */
/*00c0*/ IADD3 R2, -R3.reuse, 0xf, R2 ; /* 0x0000000f03027810 */
/* 0x040fe40007ffe102 */
/*00d0*/ IADD3 R8, R3.reuse, 0x20, RZ ; /* 0x0000002003087810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LEA.HI R11, R2, 0x1, RZ, 0x1c ; /* 0x00000001020b7811 */
/* 0x000fe400078fe0ff */
/*00f0*/ IADD3 R17, R3, 0x30, RZ ; /* 0x0000003003117810 */
/* 0x000fc40007ffe0ff */
/*0100*/ LOP3.LUT R11, R11, 0x3, RZ, 0xc0, !PT ; /* 0x000000030b0b7812 */
/* 0x000fe200078ec0ff */
/*0110*/ IMAD R9, R0, 0x10, R3 ; /* 0x0000001000097824 */
/* 0x001fc600078e0203 */
/*0120*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f05270 */
/*0130*/ BSSY B1, 0x290 ; /* 0x0000015000017945 */
/* 0x000fe20003800000 */
/*0140*/ ISETP.GE.U32.AND P2, PT, R2, 0x30, PT ; /* 0x000000300200780c */
/* 0x000fe20003f46070 */
/*0150*/ IMAD.MOV.U32 R13, RZ, RZ, R3 ; /* 0x000000ffff0d7224 */
/* 0x000fd400078e0003 */
/*0160*/ @!P0 BRA 0x280 ; /* 0x0000011000008947 */
/* 0x001fea0003800000 */
/*0170*/ IMAD R6, R9, 0x80, R10 ; /* 0x0000008009067824 */
/* 0x000fe400078e020a */
/*0180*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fca00078e0207 */
/*01a0*/ LDG.E R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IMAD R13, R3, 0x81, R10 ; /* 0x00000081030d7824 */
/* 0x000fe200078e020a */
/*01c0*/ ISETP.NE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fc60003f05270 */
/*01d0*/ IMAD.SHL.U32 R15, R13, 0x4, RZ ; /* 0x000000040d0f7824 */
/* 0x000fe400078e00ff */
/*01e0*/ IMAD.MOV.U32 R13, RZ, RZ, R5 ; /* 0x000000ffff0d7224 */
/* 0x000fc600078e0005 */
/*01f0*/ STS [R15], R12 ; /* 0x0000000c0f007388 */
/* 0x0041ea0000000800 */
/*0200*/ @!P0 BRA 0x280 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0210*/ ISETP.NE.AND P0, PT, R11, 0x2, PT ; /* 0x000000020b00780c */
/* 0x000fe20003f05270 */
/*0220*/ LDG.E R12, [R6.64+0x2000] ; /* 0x00200004060c7981 */
/* 0x001e98000c1e1900 */
/*0230*/ @P0 LDG.E R14, [R6.64+0x4000] ; /* 0x00400004060e0981 */
/* 0x000ee2000c1e1900 */
/*0240*/ IMAD.MOV.U32 R13, RZ, RZ, R8 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0008 */
/*0250*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R17 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0011 */
/*0260*/ STS [R15+0x2040], R12 ; /* 0x0020400c0f007388 */
/* 0x0041e80000000800 */
/*0270*/ @P0 STS [R15+0x4080], R14 ; /* 0x0040800e0f000388 */
/* 0x0081e40000000800 */
/*0280*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0290*/ BSSY B1, 0x3c0 ; /* 0x0000012000017945 */
/* 0x000fe20003800000 */
/*02a0*/ @!P2 BRA 0x3b0 ; /* 0x000001000000a947 */
/* 0x000fea0003800000 */
/*02b0*/ IMAD R7, R0, 0x10, R13 ; /* 0x0000001000077824 */
/* 0x000fe400078e020d */
/*02c0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fc400078e00ff */
/*02d0*/ IMAD R7, R7, 0x80, R10 ; /* 0x0000008007077824 */
/* 0x000fc800078e020a */
/*02e0*/ IMAD.WIDE R6, R7, R6, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fca00078e0206 */
/*02f0*/ LDG.E R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x001ea8000c1e1900 */
/*0300*/ LDG.E R14, [R6.64+0x2000] ; /* 0x00200004060e7981 */
/* 0x000ee8000c1e1900 */
/*0310*/ LDG.E R16, [R6.64+0x4000] ; /* 0x0040000406107981 */
/* 0x000f28000c1e1900 */
/*0320*/ LDG.E R18, [R6.64+0x6000] ; /* 0x0060000406127981 */
/* 0x000f62000c1e1900 */
/*0330*/ IMAD R15, R13.reuse, 0x81, R10 ; /* 0x000000810d0f7824 */
/* 0x040fe200078e020a */
/*0340*/ ISETP.GE.AND P0, PT, R13, -0x30, PT ; /* 0xffffffd00d00780c */
/* 0x000fc40003f06270 */
/*0350*/ IADD3 R13, R13, 0x40, RZ ; /* 0x000000400d0d7810 */
/* 0x000fe40007ffe0ff */
/*0360*/ STS [R15.X4], R12 ; /* 0x0000000c0f007388 */
/* 0x0041e80000004800 */
/*0370*/ STS [R15.X4+0x2040], R14 ; /* 0x0020400e0f007388 */
/* 0x0081e80000004800 */
/*0380*/ STS [R15.X4+0x4080], R16 ; /* 0x004080100f007388 */
/* 0x0101e80000004800 */
/*0390*/ STS [R15.X4+0x60c0], R18 ; /* 0x0060c0120f007388 */
/* 0x0201e20000004800 */
/*03a0*/ @!P0 BRA 0x2b0 ; /* 0xffffff0000008947 */
/* 0x000fea000383ffff */
/*03b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*03c0*/ ISETP.GE.AND P0, PT, R10.reuse, 0x70, PT ; /* 0x000000700a00780c */
/* 0x040fe40003f06270 */
/*03d0*/ IADD3 R10, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fd60007ffe0ff */
/*03e0*/ @!P0 BRA 0x120 ; /* 0xfffffd3000008947 */
/* 0x000fea000383ffff */
/*03f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0400*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0410*/ IMNMX R5, R4.reuse, 0x70, !PT ; /* 0x0000007004057817 */
/* 0x040fe20007800200 */
/*0420*/ IMAD R23, R3.reuse, 0x10, R4.reuse ; /* 0x0000001003177824 */
/* 0x140fe200078e0204 */
/*0430*/ LEA R18, R3.reuse, 0x2040, 0x9 ; /* 0x0000204003127811 */
/* 0x041fe200078e48ff */
/*0440*/ IMAD R2, R3, 0x80, R4 ; /* 0x0000008003027824 */
/* 0x000fe200078e0204 */
/*0450*/ IADD3 R22, -R4.reuse, 0xf, R5 ; /* 0x0000000f04167810 */
/* 0x040fe20007ffe105 */
/*0460*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0470*/ IADD3 R0, R4, 0x10, RZ ; /* 0x0000001004007810 */
/* 0x000fe20007ffe0ff */
/*0480*/ IMAD.MOV.U32 R16, RZ, RZ, -0x1 ; /* 0xffffffffff107424 */
/* 0x000fe200078e00ff */
/*0490*/ LEA.HI R19, R22, 0x1, RZ, 0x1c ; /* 0x0000000116137811 */
/* 0x000fe200078fe0ff */
/*04a0*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fe200078e00ff */
/*04b0*/ IADD3 R5, R4, 0x20, RZ ; /* 0x0000002004057810 */
/* 0x000fc40007ffe0ff */
/*04c0*/ IADD3 R6, R4, 0x30, RZ ; /* 0x0000003004067810 */
/* 0x000fe40007ffe0ff */
/*04d0*/ IADD3 R18, R18, 0x80, RZ ; /* 0x0000008012127810 */
/* 0x000fe40007ffe0ff */
/*04e0*/ LOP3.LUT R19, R19, 0x3, RZ, 0xc0, !PT ; /* 0x0000000313137812 */
/* 0x000fe400078ec0ff */
/*04f0*/ BSSY B0, 0xbf0 ; /* 0x000006f000007945 */
/* 0x000fe20003800000 */
/*0500*/ @P1 BRA 0xbe0 ; /* 0x000006d000001947 */
/* 0x000fea0003800000 */
/*0510*/ ISETP.NE.AND P0, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fe20003f05270 */
/*0520*/ BSSY B1, 0x670 ; /* 0x0000014000017945 */
/* 0x000fe20003800000 */
/*0530*/ ISETP.GE.U32.AND P2, PT, R22, 0x30, PT ; /* 0x000000301600780c */
/* 0x000fe20003f46070 */
/*0540*/ IMAD.IADD R10, R3, 0x1, R17 ; /* 0x00000001030a7824 */
/* 0x000fe400078e0211 */
/*0550*/ IMAD.MOV.U32 R13, RZ, RZ, R4 ; /* 0x000000ffff0d7224 */
/* 0x000fd000078e0004 */
/*0560*/ @!P0 BRA 0x660 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0570*/ IMAD R8, R10, 0x80, R4 ; /* 0x000000800a087824 */
/* 0x000fe400078e0204 */
/*0580*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*0590*/ IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e0209 */
/*05a0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ ISETP.NE.AND P0, PT, R19, 0x1, PT ; /* 0x000000011300780c */
/* 0x000fe20003f05270 */
/*05c0*/ IMAD.MOV.U32 R13, RZ, RZ, R0 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0000 */
/*05d0*/ STS [R2.X4+0x2040], R11 ; /* 0x0020400b02007388 */
/* 0x0041f40000004800 */
/*05e0*/ @!P0 BRA 0x660 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.NE.AND P0, PT, R19, 0x2, PT ; /* 0x000000021300780c */
/* 0x000fe20003f05270 */
/*0600*/ LDG.E R11, [R8.64+0x40] ; /* 0x00004004080b7981 */
/* 0x001e98000c1e1900 */
/*0610*/ @P0 LDG.E R15, [R8.64+0x80] ; /* 0x00008004080f0981 */
/* 0x000ee2000c1e1900 */
/*0620*/ IMAD.MOV.U32 R13, RZ, RZ, R5 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0005 */
/*0630*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R6 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0006 */
/*0640*/ STS [R2.X4+0x2080], R11 ; /* 0x0020800b02007388 */
/* 0x0041e80000004800 */
/*0650*/ @P0 STS [R2.X4+0x20c0], R15 ; /* 0x0020c00f02000388 */
/* 0x0081e40000004800 */
/*0660*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0670*/ @!P2 BRA 0xbe0 ; /* 0x000005600000a947 */
/* 0x000fea0003800000 */
/*0680*/ IADD3 R11, R13, -0x40, RZ ; /* 0xffffffc00d0b7810 */
/* 0x001fe20007ffe0ff */
/*0690*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*06a0*/ BSSY B1, 0x9a0 ; /* 0x000002f000017945 */
/* 0x000fe20003800000 */
/*06b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0f070 */
/*06c0*/ IADD3 R8, -R11, 0x40, RZ ; /* 0x000000400b087810 */
/* 0x000fc80007ffe1ff */
/*06d0*/ ISETP.GT.AND P2, PT, R8, 0xc0, PT ; /* 0x000000c00800780c */
/* 0x000fe20003f44270 */
/*06e0*/ IMAD R8, R10, 0x80, R13 ; /* 0x000000800a087824 */
/* 0x000fe400078e020d */
/*06f0*/ IMAD R10, R13, 0x4, R18 ; /* 0x000000040d0a7824 */
/* 0x000fe400078e0212 */
/*0700*/ IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fd000078e0209 */
/*0710*/ @!P2 BRA 0x990 ; /* 0x000002700000a947 */
/* 0x000fea0003800000 */
/*0720*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0730*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R15, [R8.64+0x40] ; /* 0x00004004080f7981 */
/* 0x000ee8000c1e1900 */
/*0750*/ LDG.E R21, [R8.64+0x80] ; /* 0x0000800408157981 */
/* 0x000f28000c1e1900 */
/*0760*/ LDG.E R25, [R8.64+0xc0] ; /* 0x0000c00408197981 */
/* 0x000f68000c1e1900 */
/*0770*/ LDG.E R27, [R8.64+0x100] ; /* 0x00010004081b7981 */
/* 0x000f68000c1e1900 */
/*0780*/ LDG.E R29, [R8.64+0x140] ; /* 0x00014004081d7981 */
/* 0x000f68000c1e1900 */
/*0790*/ LDG.E R12, [R8.64+0x180] ; /* 0x00018004080c7981 */
/* 0x000f68000c1e1900 */
/*07a0*/ LDG.E R14, [R8.64+0x1c0] ; /* 0x0001c004080e7981 */
/* 0x000168000c1e1900 */
/*07b0*/ LDG.E R20, [R8.64+0x200] ; /* 0x0002000408147981 */
/* 0x000168000c1e1900 */
/*07c0*/ LDG.E R24, [R8.64+0x240] ; /* 0x0002400408187981 */
/* 0x000168000c1e1900 */
/*07d0*/ LDG.E R26, [R8.64+0x280] ; /* 0x00028004081a7981 */
/* 0x000168000c1e1900 */
/*07e0*/ STS [R10+-0x80], R13 ; /* 0xffff800d0a007388 */
/* 0x0043e80000000800 */
/*07f0*/ STS [R10+-0x40], R15 ; /* 0xffffc00f0a007388 */
/* 0x0085e80000000800 */
/*0800*/ STS [R10], R21 ; /* 0x000000150a007388 */
/* 0x0107e80000000800 */
/*0810*/ STS [R10+0x40], R25 ; /* 0x000040190a007388 */
/* 0x0209e80000000800 */
/*0820*/ STS [R10+0x80], R27 ; /* 0x0000801b0a007388 */
/* 0x0007e80000000800 */
/*0830*/ LDG.E R13, [R8.64+0x2c0] ; /* 0x0002c004080d7981 */
/* 0x002168000c1e1900 */
/*0840*/ LDG.E R15, [R8.64+0x300] ; /* 0x00030004080f7981 */
/* 0x0040a8000c1e1900 */
/*0850*/ LDG.E R21, [R8.64+0x340] ; /* 0x0003400408157981 */
/* 0x0080e8000c1e1900 */
/*0860*/ LDG.E R25, [R8.64+0x380] ; /* 0x0003800408197981 */
/* 0x010128000c1e1900 */
/*0870*/ LDG.E R27, [R8.64+0x3c0] ; /* 0x0003c004081b7981 */
/* 0x000122000c1e1900 */
/*0880*/ IADD3 R11, R11, 0x100, RZ ; /* 0x000001000b0b7810 */
/* 0x000fc60007ffe0ff */
/*0890*/ STS [R10+0xc0], R29 ; /* 0x0000c01d0a007388 */
/* 0x000fe20000000800 */
/*08a0*/ ISETP.GE.AND P2, PT, R11, -0x80, PT ; /* 0xffffff800b00780c */
/* 0x000fc60003f46270 */
/*08b0*/ STS [R10+0x100], R12 ; /* 0x0001000c0a007388 */
/* 0x000fe20000000800 */
/*08c0*/ IADD3 R8, P3, R8, 0x400, RZ ; /* 0x0000040008087810 */
/* 0x001fc60007f7e0ff */
/*08d0*/ STS [R10+0x140], R14 ; /* 0x0001400e0a007388 */
/* 0x000fe40000000800 */
/*08e0*/ IMAD.X R9, RZ, RZ, R9, P3 ; /* 0x000000ffff097224 */
/* 0x000fe400018e0609 */
/*08f0*/ STS [R10+0x180], R20 ; /* 0x000180140a007388 */
/* 0x000fe80000000800 */
/*0900*/ STS [R10+0x1c0], R24 ; /* 0x0001c0180a007388 */
/* 0x000fe80000000800 */
/*0910*/ STS [R10+0x200], R26 ; /* 0x0002001a0a007388 */
/* 0x000fe80000000800 */
/*0920*/ STS [R10+0x240], R13 ; /* 0x0002400d0a007388 */
/* 0x020fe80000000800 */
/*0930*/ STS [R10+0x280], R15 ; /* 0x0002800f0a007388 */
/* 0x004fe80000000800 */
/*0940*/ STS [R10+0x2c0], R21 ; /* 0x0002c0150a007388 */
/* 0x008fe80000000800 */
/*0950*/ STS [R10+0x300], R25 ; /* 0x000300190a007388 */
/* 0x010fe80000000800 */
/*0960*/ STS [R10+0x340], R27 ; /* 0x0003401b0a007388 */
/* 0x0001e40000000800 */
/*0970*/ IADD3 R10, R10, 0x400, RZ ; /* 0x000004000a0a7810 */
/* 0x001fe20007ffe0ff */
/*0980*/ @!P2 BRA 0x730 ; /* 0xfffffda00000a947 */
/* 0x000fea000383ffff */
/*0990*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09a0*/ IADD3 R12, -R11, 0x40, RZ ; /* 0x000000400b0c7810 */
/* 0x000fe20007ffe1ff */
/*09b0*/ BSSY B1, 0xb40 ; /* 0x0000018000017945 */
/* 0x000fe60003800000 */
/*09c0*/ ISETP.GT.AND P2, PT, R12, 0x40, PT ; /* 0x000000400c00780c */
/* 0x000fda0003f44270 */
/*09d0*/ @!P2 BRA 0xb30 ; /* 0x000001500000a947 */
/* 0x000fea0003800000 */
/*09e0*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x0000a8000c1e1900 */
/*09f0*/ LDG.E R15, [R8.64+0x40] ; /* 0x00004004080f7981 */
/* 0x0000e8000c1e1900 */
/*0a00*/ LDG.E R21, [R8.64+0x80] ; /* 0x0000800408157981 */
/* 0x000128000c1e1900 */
/*0a10*/ LDG.E R25, [R8.64+0xc0] ; /* 0x0000c00408197981 */
/* 0x000168000c1e1900 */
/*0a20*/ LDG.E R27, [R8.64+0x100] ; /* 0x00010004081b7981 */
/* 0x000168000c1e1900 */
/*0a30*/ LDG.E R29, [R8.64+0x140] ; /* 0x00014004081d7981 */
/* 0x000168000c1e1900 */
/*0a40*/ LDG.E R12, [R8.64+0x180] ; /* 0x00018004080c7981 */
/* 0x000168000c1e1900 */
/*0a50*/ LDG.E R14, [R8.64+0x1c0] ; /* 0x0001c004080e7981 */
/* 0x000162000c1e1900 */
/*0a60*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0a70*/ IADD3 R11, R11, 0x80, RZ ; /* 0x000000800b0b7810 */
/* 0x000fe40007ffe0ff */
/*0a80*/ IADD3 R8, P2, R8, 0x200, RZ ; /* 0x0000020008087810 */
/* 0x001fca0007f5e0ff */
/*0a90*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0609 */
/*0aa0*/ STS [R10+-0x80], R13 ; /* 0xffff800d0a007388 */
/* 0x004fe80000000800 */
/*0ab0*/ STS [R10+-0x40], R15 ; /* 0xffffc00f0a007388 */
/* 0x008fe80000000800 */
/*0ac0*/ STS [R10], R21 ; /* 0x000000150a007388 */
/* 0x010fe80000000800 */
/*0ad0*/ STS [R10+0x40], R25 ; /* 0x000040190a007388 */
/* 0x020fe80000000800 */
/*0ae0*/ STS [R10+0x80], R27 ; /* 0x0000801b0a007388 */
/* 0x000fe80000000800 */
/*0af0*/ STS [R10+0xc0], R29 ; /* 0x0000c01d0a007388 */
/* 0x000fe80000000800 */
/*0b00*/ STS [R10+0x100], R12 ; /* 0x0001000c0a007388 */
/* 0x000fe80000000800 */
/*0b10*/ STS [R10+0x140], R14 ; /* 0x0001400e0a007388 */
/* 0x0001e40000000800 */
/*0b20*/ IADD3 R10, R10, 0x200, RZ ; /* 0x000002000a0a7810 */
/* 0x001fc40007ffe0ff */
/*0b30*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0b40*/ ISETP.LT.OR P0, PT, R11, 0x40, P0 ; /* 0x000000400b00780c */
/* 0x000fda0000701670 */
/*0b50*/ @!P0 BRA 0xbe0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0b60*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x000ea8000c1e1900 */
/*0b70*/ LDG.E R13, [R8.64+0x40] ; /* 0x00004004080d7981 */
/* 0x000ee8000c1e1900 */
/*0b80*/ LDG.E R15, [R8.64+0x80] ; /* 0x00008004080f7981 */
/* 0x000f28000c1e1900 */
/*0b90*/ LDG.E R21, [R8.64+0xc0] ; /* 0x0000c00408157981 */
/* 0x000f68000c1e1900 */
/*0ba0*/ STS [R10+-0x80], R11 ; /* 0xffff800b0a007388 */
/* 0x0041e80000000800 */
/*0bb0*/ STS [R10+-0x40], R13 ; /* 0xffffc00d0a007388 */
/* 0x0081e80000000800 */
/*0bc0*/ STS [R10], R15 ; /* 0x0000000f0a007388 */
/* 0x0101e80000000800 */
/*0bd0*/ STS [R10+0x40], R21 ; /* 0x000040150a007388 */
/* 0x0201e40000000800 */
/*0be0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0bf0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0c00*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x001fc400078e00ff */
/*0c10*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fc800078e00ff */
/*0c20*/ IMAD R21, R4, 0x81, R20.reuse ; /* 0x0000008104157824 */
/* 0x100fe400078e0214 */
/*0c30*/ IMAD R24, R3, 0x80, R20 ; /* 0x0000008003187824 */
/* 0x000fe200078e0214 */
/*0c40*/ IADD3 R20, R20, 0x10, RZ ; /* 0x0000001014147810 */
/* 0x000fe40007ffe0ff */
/*0c50*/ LDS R8, [R21.X4] ; /* 0x0000000015087984 */
/* 0x000fe40000004800 */
/*0c60*/ ISETP.NE.AND P0, PT, R20, 0x80, PT ; /* 0x000000801400780c */
/* 0x000fe40003f05270 */
/*0c70*/ LDS.128 R12, [R24.X4+0x2040] ; /* 0x00204000180c7984 */
/* 0x000e280000004c00 */
/*0c80*/ LDS R9, [R21.X4+0x4] ; /* 0x0000040015097984 */
/* 0x000e680000004800 */
/*0c90*/ LDS R10, [R21.X4+0x8] ; /* 0x00000800150a7984 */
/* 0x000ea80000004800 */
/*0ca0*/ LDS R26, [R21.X4+0x14] ; /* 0x00001400151a7984 */
/* 0x000fe80000004800 */
/*0cb0*/ LDS R25, [R21.X4+0x18] ; /* 0x0000180015197984 */
/* 0x000fe80000004800 */
/*0cc0*/ LDS R27, [R21.X4+0x3c] ; /* 0x00003c00151b7984 */
/* 0x000fe20000004800 */
/*0cd0*/ FFMA R8, R12, R8, R11 ; /* 0x000000080c087223 */
/* 0x001fc6000000000b */
/*0ce0*/ LDS R12, [R21.X4+0xc] ; /* 0x00000c00150c7984 */
/* 0x000e220000004800 */
/*0cf0*/ FFMA R9, R9, R13, R8 ; /* 0x0000000d09097223 */
/* 0x002fc60000000008 */
/*0d00*/ LDS R13, [R21.X4+0x10] ; /* 0x00001000150d7984 */
/* 0x000fe20000004800 */
/*0d10*/ FFMA R14, R10, R14, R9 ; /* 0x0000000e0a0e7223 */
/* 0x004fc60000000009 */
/*0d20*/ LDS.128 R8, [R24.X4+0x2050] ; /* 0x0020500018087984 */
/* 0x000e620000004c00 */
/*0d30*/ FFMA R12, R12, R15, R14 ; /* 0x0000000f0c0c7223 */
/* 0x001fc8000000000e */
/*0d40*/ FFMA R8, R8, R13, R12 ; /* 0x0000000d08087223 */
/* 0x002fe4000000000c */
/*0d50*/ LDS.128 R12, [R24.X4+0x2060] ; /* 0x00206000180c7984 */
/* 0x000fe40000004c00 */
/*0d60*/ FFMA R8, R26, R9, R8 ; /* 0x000000091a087223 */
/* 0x000fe40000000008 */
/*0d70*/ LDS R26, [R21.X4+0x1c] ; /* 0x00001c00151a7984 */
/* 0x000e240000004800 */
/*0d80*/ FFMA R8, R25, R10, R8 ; /* 0x0000000a19087223 */
/* 0x000fe40000000008 */
/*0d90*/ LDS R9, [R21.X4+0x20] ; /* 0x0000200015097984 */
/* 0x000e680000004800 */
/*0da0*/ LDS R10, [R21.X4+0x24] ; /* 0x00002400150a7984 */
/* 0x000ea80000004800 */
/*0db0*/ LDS R25, [R21.X4+0x28] ; /* 0x0000280015197984 */
/* 0x000ee20000004800 */
/*0dc0*/ FFMA R8, R26, R11, R8 ; /* 0x0000000b1a087223 */
/* 0x001fc80000000008 */
/*0dd0*/ FFMA R8, R12, R9, R8 ; /* 0x000000090c087223 */
/* 0x002fe40000000008 */
/*0de0*/ LDS R12, [R21.X4+0x2c] ; /* 0x00002c00150c7984 */
/* 0x000e240000004800 */
/*0df0*/ FFMA R26, R10, R13, R8 ; /* 0x0000000d0a1a7223 */
/* 0x004fe40000000008 */
/*0e00*/ LDS R13, [R21.X4+0x30] ; /* 0x00003000150d7984 */
/* 0x000fe40000004800 */
/*0e10*/ FFMA R14, R25, R14, R26 ; /* 0x0000000e190e7223 */
/* 0x008fe4000000001a */
/*0e20*/ LDS.128 R8, [R24.X4+0x2070] ; /* 0x0020700018087984 */
/* 0x000e680000004c00 */
/*0e30*/ LDS R25, [R21.X4+0x34] ; /* 0x0000340015197984 */
/* 0x000ea80000004800 */
/*0e40*/ LDS R26, [R21.X4+0x38] ; /* 0x00003800151a7984 */
/* 0x000ee20000004800 */
/*0e50*/ FFMA R12, R12, R15, R14 ; /* 0x0000000f0c0c7223 */
/* 0x001fc8000000000e */
/*0e60*/ FFMA R8, R8, R13, R12 ; /* 0x0000000d08087223 */
/* 0x002fc8000000000c */
/*0e70*/ FFMA R9, R25, R9, R8 ; /* 0x0000000919097223 */
/* 0x004fc80000000008 */
/*0e80*/ FFMA R10, R26, R10, R9 ; /* 0x0000000a1a0a7223 */
/* 0x008fc80000000009 */
/*0e90*/ FFMA R11, R27, R11, R10 ; /* 0x0000000b1b0b7223 */
/* 0x000fe2000000000a */
/*0ea0*/ @P0 BRA 0xc20 ; /* 0xfffffd7000000947 */
/* 0x000fea000383ffff */
/*0eb0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f05270 */
/*0ec0*/ STS [R23.X4+0x4040], R11 ; /* 0x0040400b17007388 */
/* 0x0001e20000004800 */
/*0ed0*/ BSSY B0, 0x1310 ; /* 0x0000043000007945 */
/* 0x000fe60003800000 */
/*0ee0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0ef0*/ @P0 BRA 0x1300 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0f00*/ LDS R10, [R4.X4+0x4040] ; /* 0x00404000040a7984 */
/* 0x001e280000004800 */
/*0f10*/ LDS R9, [R4.X4+0x4080] ; /* 0x0040800004097984 */
/* 0x000e680000004800 */
/*0f20*/ LDS R11, [R4.X4+0x40c0] ; /* 0x0040c000040b7984 */
/* 0x000ea80000004800 */
/*0f30*/ LDS R12, [R4.X4+0x4100] ; /* 0x00410000040c7984 */
/* 0x000ee80000004800 */
/*0f40*/ LDS R13, [R4.X4+0x4140] ; /* 0x00414000040d7984 */
/* 0x000f280000004800 */
/*0f50*/ LDS R8, [R4.X4+0x4180] ; /* 0x0041800004087984 */
/* 0x000f680000004800 */
/*0f60*/ LDS R14, [R4.X4+0x4300] ; /* 0x00430000040e7984 */
/* 0x000fe80000004800 */
/*0f70*/ LDS R20, [R4.X4+0x4340] ; /* 0x0043400004147984 */
/* 0x000fe80000004800 */
/*0f80*/ LDS R24, [R4.X4+0x43c0] ; /* 0x0043c00004187984 */
/* 0x000fe20000004800 */
/*0f90*/ FSETP.GT.AND P2, PT, R10, R7, PT ; /* 0x000000070a00720b */
/* 0x001fc80003f44000 */
/*0fa0*/ FSEL R10, R10, R7, P2 ; /* 0x000000070a0a7208 */
/* 0x000fe40001000000 */
/*0fb0*/ LDS R7, [R4.X4+0x41c0] ; /* 0x0041c00004077984 */
/* 0x000e220000004800 */
/*0fc0*/ SEL R16, R17, R16, P2 ; /* 0x0000001011107207 */
/* 0x000fe40001000000 */
/*0fd0*/ FSETP.GT.AND P3, PT, R9, R10, PT ; /* 0x0000000a0900720b */
/* 0x002fc80003f64000 */
/*0fe0*/ FSEL R10, R9, R10, P3 ; /* 0x0000000a090a7208 */
/* 0x000fe40001800000 */
/*0ff0*/ LDS R9, [R4.X4+0x4200] ; /* 0x0042000004097984 */
/* 0x000e640000004800 */
/*1000*/ FSETP.GT.AND P4, PT, R11, R10, PT ; /* 0x0000000a0b00720b */
/* 0x004fc80003f84000 */
/*1010*/ FSEL R11, R11, R10, P4 ; /* 0x0000000a0b0b7208 */
/* 0x000fe40002000000 */
/*1020*/ LDS R10, [R4.X4+0x4240] ; /* 0x00424000040a7984 */
/* 0x000ea20000004800 */
/*1030*/ @P3 IADD3 R16, R17, 0x1, RZ ; /* 0x0000000111103810 */
/* 0x000fe40007ffe0ff */
/*1040*/ FSETP.GT.AND P5, PT, R12, R11, PT ; /* 0x0000000b0c00720b */
/* 0x008fc80003fa4000 */
/*1050*/ FSEL R12, R12, R11, P5 ; /* 0x0000000b0c0c7208 */
/* 0x000fe40002800000 */
/*1060*/ LDS R11, [R4.X4+0x4280] ; /* 0x00428000040b7984 */
/* 0x000ee20000004800 */
/*1070*/ @P4 IADD3 R16, R17, 0x2, RZ ; /* 0x0000000211104810 */
/* 0x000fe40007ffe0ff */
/*1080*/ FSETP.GT.AND P6, PT, R13, R12, PT ; /* 0x0000000c0d00720b */
/* 0x010fc80003fc4000 */
/*1090*/ FSEL R13, R13, R12, P6 ; /* 0x0000000c0d0d7208 */
/* 0x000fe40003000000 */
/*10a0*/ LDS R12, [R4.X4+0x42c0] ; /* 0x0042c000040c7984 */
/* 0x000f220000004800 */
/*10b0*/ @P5 IADD3 R16, R17, 0x3, RZ ; /* 0x0000000311105810 */
/* 0x000fe40007ffe0ff */
/*10c0*/ FSETP.GT.AND P2, PT, R8, R13, PT ; /* 0x0000000d0800720b */
/* 0x020fc80003f44000 */
/*10d0*/ FSEL R8, R8, R13, P2 ; /* 0x0000000d08087208 */
/* 0x000fe40001000000 */
/*10e0*/ @P6 IADD3 R16, R17, 0x4, RZ ; /* 0x0000000411106810 */
/* 0x000fe40007ffe0ff */
/*10f0*/ FSETP.GT.AND P3, PT, R7, R8, PT ; /* 0x000000080700720b */
/* 0x001fc80003f64000 */
/*1100*/ FSEL R8, R7, R8, P3 ; /* 0x0000000807087208 */
/* 0x000fe40001800000 */
/*1110*/ @P2 IADD3 R16, R17, 0x5, RZ ; /* 0x0000000511102810 */
/* 0x000fe40007ffe0ff */
/*1120*/ FSETP.GT.AND P4, PT, R9, R8, PT ; /* 0x000000080900720b */
/* 0x002fc80003f84000 */
/*1130*/ FSEL R9, R9, R8, P4 ; /* 0x0000000809097208 */
/* 0x000fe40002000000 */
/*1140*/ LDS R8, [R4.X4+0x4380] ; /* 0x0043800004087984 */
/* 0x000e220000004800 */
/*1150*/ @P3 IADD3 R16, R17, 0x6, RZ ; /* 0x0000000611103810 */
/* 0x000fe40007ffe0ff */
/*1160*/ FSETP.GT.AND P5, PT, R10, R9, PT ; /* 0x000000090a00720b */
/* 0x004fc80003fa4000 */
/*1170*/ FSEL R10, R10, R9, P5 ; /* 0x000000090a0a7208 */
/* 0x000fe40002800000 */
/*1180*/ @P4 IADD3 R16, R17, 0x7, RZ ; /* 0x0000000711104810 */
/* 0x000fe40007ffe0ff */
/*1190*/ FSETP.GT.AND P6, PT, R11, R10, PT ; /* 0x0000000a0b00720b */
/* 0x008fc80003fc4000 */
/*11a0*/ FSEL R11, R11, R10, P6 ; /* 0x0000000a0b0b7208 */
/* 0x000fe40003000000 */
/*11b0*/ LDS R10, [R4.X4+0x4400] ; /* 0x00440000040a7984 */
/* 0x000e620000004800 */
/*11c0*/ @P5 IADD3 R16, R17, 0x8, RZ ; /* 0x0000000811105810 */
/* 0x000fe40007ffe0ff */
/*11d0*/ FSETP.GT.AND P2, PT, R12, R11, PT ; /* 0x0000000b0c00720b */
/* 0x010fc80003f44000 */
/*11e0*/ FSEL R11, R12, R11, P2 ; /* 0x0000000b0c0b7208 */
/* 0x000fe40001000000 */
/*11f0*/ @P6 IADD3 R16, R17, 0x9, RZ ; /* 0x0000000911106810 */
/* 0x000fe40007ffe0ff */
/*1200*/ FSETP.GT.AND P3, PT, R14, R11, PT ; /* 0x0000000b0e00720b */
/* 0x000fc80003f64000 */
/*1210*/ FSEL R11, R14, R11, P3 ; /* 0x0000000b0e0b7208 */
/* 0x000fe40001800000 */
/*1220*/ @P2 IADD3 R16, R17, 0xa, RZ ; /* 0x0000000a11102810 */
/* 0x000fe40007ffe0ff */
/*1230*/ FSETP.GT.AND P4, PT, R20, R11, PT ; /* 0x0000000b1400720b */
/* 0x000fc80003f84000 */
/*1240*/ FSEL R11, R20, R11, P4 ; /* 0x0000000b140b7208 */
/* 0x000fe40002000000 */
/*1250*/ @P3 IADD3 R16, R17, 0xb, RZ ; /* 0x0000000b11103810 */
/* 0x000fe40007ffe0ff */
/*1260*/ FSETP.GT.AND P5, PT, R8, R11, PT ; /* 0x0000000b0800720b */
/* 0x001fc80003fa4000 */
/*1270*/ FSEL R7, R8, R11, P5 ; /* 0x0000000b08077208 */
/* 0x000fe40002800000 */
/*1280*/ @P4 IADD3 R16, R17, 0xc, RZ ; /* 0x0000000c11104810 */
/* 0x000fe40007ffe0ff */
/*1290*/ FSETP.GT.AND P2, PT, R24, R7, PT ; /* 0x000000071800720b */
/* 0x000fc80003f44000 */
/*12a0*/ FSEL R7, R24, R7, P2 ; /* 0x0000000718077208 */
/* 0x000fe40001000000 */
/*12b0*/ @P5 IADD3 R16, R17, 0xd, RZ ; /* 0x0000000d11105810 */
/* 0x000fe40007ffe0ff */
/*12c0*/ FSETP.GT.AND P3, PT, R10, R7, PT ; /* 0x000000070a00720b */
/* 0x002fca0003f64000 */
/*12d0*/ @P2 IADD3 R16, R17, 0xe, RZ ; /* 0x0000000e11102810 */
/* 0x000fd00007ffe0ff */
/*12e0*/ @P3 IMAD.MOV.U32 R7, RZ, RZ, R10 ; /* 0x000000ffff073224 */
/* 0x000fe200078e000a */
/*12f0*/ @P3 IADD3 R16, R17, 0xf, RZ ; /* 0x0000000f11103810 */
/* 0x000fe40007ffe0ff */
/*1300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*1310*/ IADD3 R17, R17, 0x10, RZ ; /* 0x0000001011117810 */
/* 0x000fe20007ffe0ff */
/*1320*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*1330*/ ISETP.GE.U32.AND P2, PT, R17, 0x4000, PT ; /* 0x000040001100780c */
/* 0x000fda0003f46070 */
/*1340*/ @P2 CALL.REL.NOINC 0x1360 ; /* 0x0000001000002944 */
/* 0x000fe20003c00000 */
/*1350*/ BRA 0x4f0 ; /* 0xfffff19000007947 */
/* 0x000fea000383ffff */
/*1360*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*1370*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*1380*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*1390*/ IMAD R4, R3, 0x10, R4 ; /* 0x0000001003047824 */
/* 0x001fc800078e0204 */
/*13a0*/ IMAD.WIDE R2, R4, R5, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fc800078e0205 */
/*13b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fe200078e0205 */
/*13c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*13d0*/ STG.E [R4.64], R16 ; /* 0x0000001004007986 */
/* 0x000fe2000c101904 */
/*13e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*13f0*/ BRA 0x13f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Match3(float *d_pts1, float *d_pts2, float *d_score, int *d_index)
{
__shared__ float buffer1[M2W*(NDIM + 1)]; //%%%%
__shared__ float buffer2[M2H*NDIM];
__shared__ float scores[M2W*M2H];
int tx = threadIdx.x;
int ty = threadIdx.y;
int idx = tx + M2W*ty;
int bp1 = M2W*blockIdx.x;
if (ty<M2W)
for (int d=tx;d<NDIM;d+=M2W)
for (int j=ty;j<M2W;j+=M2H)
buffer1[j*(NDIM + 1) + d] = d_pts1[(bp1 + j)*NDIM + d]; //%%%%
__syncthreads();
float max_score = 0.0f;
int index = -1;
for (int bp2=0;bp2<NPTS;bp2+=M2H) {
for (int d=tx;d<NDIM;d+=M2W)
buffer2[ty*NDIM + d] = d_pts2[(bp2 + ty)*NDIM + d];
__syncthreads();
float score = 0.0f;
for (int d=0;d<NDIM;d++)
score += buffer1[tx*(NDIM + 1) + d]*buffer2[ty*NDIM + d]; //%%%%
scores[idx] = score;
__syncthreads();
if (ty==0) {
for (int i=0;i<M2H;i++) {
if (scores[i*M2W + tx]>max_score) {
max_score = scores[i*M2W + tx];
index = bp2 + i;
}
}
}
__syncthreads();
}
if (ty==0) {
d_score[bp1 + tx] = max_score;
d_index[bp1 + tx] = index;
}
} | .file "tmpxft_0004160b_00000000-6_Match3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z6Match3PfS_S_PiPfS_S_Pi
.type _Z31__device_stub__Z6Match3PfS_S_PiPfS_S_Pi, @function
_Z31__device_stub__Z6Match3PfS_S_PiPfS_S_Pi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6Match3PfS_S_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z6Match3PfS_S_PiPfS_S_Pi, .-_Z31__device_stub__Z6Match3PfS_S_PiPfS_S_Pi
.globl _Z6Match3PfS_S_Pi
.type _Z6Match3PfS_S_Pi, @function
_Z6Match3PfS_S_Pi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6Match3PfS_S_PiPfS_S_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6Match3PfS_S_Pi, .-_Z6Match3PfS_S_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6Match3PfS_S_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6Match3PfS_S_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Match3(float *d_pts1, float *d_pts2, float *d_score, int *d_index)
{
__shared__ float buffer1[M2W*(NDIM + 1)]; //%%%%
__shared__ float buffer2[M2H*NDIM];
__shared__ float scores[M2W*M2H];
int tx = threadIdx.x;
int ty = threadIdx.y;
int idx = tx + M2W*ty;
int bp1 = M2W*blockIdx.x;
if (ty<M2W)
for (int d=tx;d<NDIM;d+=M2W)
for (int j=ty;j<M2W;j+=M2H)
buffer1[j*(NDIM + 1) + d] = d_pts1[(bp1 + j)*NDIM + d]; //%%%%
__syncthreads();
float max_score = 0.0f;
int index = -1;
for (int bp2=0;bp2<NPTS;bp2+=M2H) {
for (int d=tx;d<NDIM;d+=M2W)
buffer2[ty*NDIM + d] = d_pts2[(bp2 + ty)*NDIM + d];
__syncthreads();
float score = 0.0f;
for (int d=0;d<NDIM;d++)
score += buffer1[tx*(NDIM + 1) + d]*buffer2[ty*NDIM + d]; //%%%%
scores[idx] = score;
__syncthreads();
if (ty==0) {
for (int i=0;i<M2H;i++) {
if (scores[i*M2W + tx]>max_score) {
max_score = scores[i*M2W + tx];
index = bp2 + i;
}
}
}
__syncthreads();
}
if (ty==0) {
d_score[bp1 + tx] = max_score;
d_index[bp1 + tx] = index;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Match3(float *d_pts1, float *d_pts2, float *d_score, int *d_index)
{
__shared__ float buffer1[M2W*(NDIM + 1)]; //%%%%
__shared__ float buffer2[M2H*NDIM];
__shared__ float scores[M2W*M2H];
int tx = threadIdx.x;
int ty = threadIdx.y;
int idx = tx + M2W*ty;
int bp1 = M2W*blockIdx.x;
if (ty<M2W)
for (int d=tx;d<NDIM;d+=M2W)
for (int j=ty;j<M2W;j+=M2H)
buffer1[j*(NDIM + 1) + d] = d_pts1[(bp1 + j)*NDIM + d]; //%%%%
__syncthreads();
float max_score = 0.0f;
int index = -1;
for (int bp2=0;bp2<NPTS;bp2+=M2H) {
for (int d=tx;d<NDIM;d+=M2W)
buffer2[ty*NDIM + d] = d_pts2[(bp2 + ty)*NDIM + d];
__syncthreads();
float score = 0.0f;
for (int d=0;d<NDIM;d++)
score += buffer1[tx*(NDIM + 1) + d]*buffer2[ty*NDIM + d]; //%%%%
scores[idx] = score;
__syncthreads();
if (ty==0) {
for (int i=0;i<M2H;i++) {
if (scores[i*M2W + tx]>max_score) {
max_score = scores[i*M2W + tx];
index = bp2 + i;
}
}
}
__syncthreads();
}
if (ty==0) {
d_score[bp1 + tx] = max_score;
d_index[bp1 + tx] = index;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Match3(float *d_pts1, float *d_pts2, float *d_score, int *d_index)
{
__shared__ float buffer1[M2W*(NDIM + 1)]; //%%%%
__shared__ float buffer2[M2H*NDIM];
__shared__ float scores[M2W*M2H];
int tx = threadIdx.x;
int ty = threadIdx.y;
int idx = tx + M2W*ty;
int bp1 = M2W*blockIdx.x;
if (ty<M2W)
for (int d=tx;d<NDIM;d+=M2W)
for (int j=ty;j<M2W;j+=M2H)
buffer1[j*(NDIM + 1) + d] = d_pts1[(bp1 + j)*NDIM + d]; //%%%%
__syncthreads();
float max_score = 0.0f;
int index = -1;
for (int bp2=0;bp2<NPTS;bp2+=M2H) {
for (int d=tx;d<NDIM;d+=M2W)
buffer2[ty*NDIM + d] = d_pts2[(bp2 + ty)*NDIM + d];
__syncthreads();
float score = 0.0f;
for (int d=0;d<NDIM;d++)
score += buffer1[tx*(NDIM + 1) + d]*buffer2[ty*NDIM + d]; //%%%%
scores[idx] = score;
__syncthreads();
if (ty==0) {
for (int i=0;i<M2H;i++) {
if (scores[i*M2W + tx]>max_score) {
max_score = scores[i*M2W + tx];
index = bp2 + i;
}
}
}
__syncthreads();
}
if (ty==0) {
d_score[bp1 + tx] = max_score;
d_index[bp1 + tx] = index;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6Match3PfS_S_Pi
.globl _Z6Match3PfS_S_Pi
.p2align 8
.type _Z6Match3PfS_S_Pi,@function
_Z6Match3PfS_S_Pi:
v_bfe_u32 v5, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_lshl_b32 s5, s15, 4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, 16, v5
v_cmp_gt_u32_e64 s2, 0x80, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x0
v_mul_u32_u24_e32 v1, 0x81, v5
v_add_lshl_u32 v0, v5, s5, 7
v_mov_b32_e32 v2, v4
s_mov_b32 s6, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_lshl_u32 v1, v1, v4, 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, v0, v2
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_cmp_lt_u32_e32 vcc_lo, 0x6f, v2
global_load_b32 v3, v[6:7], off
v_add_nc_u32_e32 v6, 16, v2
s_or_b32 s6, vcc_lo, s6
v_mov_b32_e32 v2, v6
s_waitcnt vmcnt(0)
ds_store_b32 v1, v3
v_add_nc_u32_e32 v1, 64, v1
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[6:7], s[0:1], 0x8
v_lshl_add_u32 v0, v5, 4, v4
v_dual_mov_b32 v7, -1 :: v_dual_lshlrev_b32 v2, 7, v5
v_mul_u32_u24_e32 v1, 0x81, v4
v_dual_mov_b32 v6, 0 :: v_dual_lshlrev_b32 v3, 2, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshl_add_u32 v10, v0, 2, 0x4040
v_add_lshl_u32 v0, v4, v2, 2
v_lshl_add_u32 v8, v5, 9, 0x2040
v_cmp_gt_u32_e32 vcc_lo, 0x80, v4
v_cmp_eq_u32_e64 s2, 0, v5
v_add_nc_u32_e32 v9, -16, v4
v_lshlrev_b32_e32 v12, 2, v1
v_add_nc_u32_e32 v11, v8, v3
v_add_nc_u32_e32 v13, 0x4040, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_co_u32 v0, s3, s6, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s7, 0, s3
s_mov_b32 s6, 0
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz .LBB0_6
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v14, v11 :: v_dual_mov_b32 v3, v1
v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v15, v9
s_mov_b32 s8, 0
.LBB0_5:
global_load_b32 v16, v[2:3], off
v_add_nc_u32_e32 v15, 16, v15
v_add_co_u32 v2, s3, v2, 64
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s3, 0, v3, s3
v_cmp_lt_u32_e64 s4, 0x6f, v15
s_delay_alu instid0(VALU_DEP_1)
s_or_b32 s8, s4, s8
s_waitcnt vmcnt(0)
ds_store_b32 v14, v16
v_add_nc_u32_e32 v14, 64, v14
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s7
v_mov_b32_e32 v2, 0
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_7:
v_add_nc_u32_e32 v3, s3, v12
v_add_nc_u32_e32 v14, s3, v8
s_add_i32 s3, s3, 4
ds_load_b32 v3, v3
ds_load_b32 v14, v14
s_cmpk_eq_i32 s3, 0x200
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v3, v14
s_cbranch_scc0 .LBB0_7
ds_store_b32 v10, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v2, v13
s_mov_b32 s7, 0
.LBB0_10:
ds_load_b32 v3, v2
s_add_i32 s8, s6, s7
v_add_nc_u32_e32 v2, 64, v2
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s7, 16
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e64 s3, v3, v6
v_cndmask_b32_e64 v6, v6, v3, s3
v_cndmask_b32_e64 v7, v7, s8, s3
s_cbranch_scc1 .LBB0_10
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s4
v_add_co_u32 v0, s3, v0, 0x2000
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s3, 0, v1, s3
s_add_i32 s3, s6, 16
s_cmpk_gt_u32 s6, 0x3fef
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_13
s_mov_b32 s6, s3
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execnz .LBB0_4
s_branch .LBB0_6
.LBB0_13:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v5
s_cbranch_execz .LBB0_15
s_load_b128 s[0:3], s[0:1], 0x10
v_add_nc_u32_e32 v0, s5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[2:3], v6, off
global_store_b32 v[0:1], v7, off
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6Match3PfS_S_Pi
.amdhsa_group_segment_fixed_size 17472
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6Match3PfS_S_Pi, .Lfunc_end0-_Z6Match3PfS_S_Pi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 17472
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6Match3PfS_S_Pi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6Match3PfS_S_Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Match3(float *d_pts1, float *d_pts2, float *d_score, int *d_index)
{
__shared__ float buffer1[M2W*(NDIM + 1)]; //%%%%
__shared__ float buffer2[M2H*NDIM];
__shared__ float scores[M2W*M2H];
int tx = threadIdx.x;
int ty = threadIdx.y;
int idx = tx + M2W*ty;
int bp1 = M2W*blockIdx.x;
if (ty<M2W)
for (int d=tx;d<NDIM;d+=M2W)
for (int j=ty;j<M2W;j+=M2H)
buffer1[j*(NDIM + 1) + d] = d_pts1[(bp1 + j)*NDIM + d]; //%%%%
__syncthreads();
float max_score = 0.0f;
int index = -1;
for (int bp2=0;bp2<NPTS;bp2+=M2H) {
for (int d=tx;d<NDIM;d+=M2W)
buffer2[ty*NDIM + d] = d_pts2[(bp2 + ty)*NDIM + d];
__syncthreads();
float score = 0.0f;
for (int d=0;d<NDIM;d++)
score += buffer1[tx*(NDIM + 1) + d]*buffer2[ty*NDIM + d]; //%%%%
scores[idx] = score;
__syncthreads();
if (ty==0) {
for (int i=0;i<M2H;i++) {
if (scores[i*M2W + tx]>max_score) {
max_score = scores[i*M2W + tx];
index = bp2 + i;
}
}
}
__syncthreads();
}
if (ty==0) {
d_score[bp1 + tx] = max_score;
d_index[bp1 + tx] = index;
}
} | .text
.file "Match3.hip"
.globl _Z21__device_stub__Match3PfS_S_Pi # -- Begin function _Z21__device_stub__Match3PfS_S_Pi
.p2align 4, 0x90
.type _Z21__device_stub__Match3PfS_S_Pi,@function
_Z21__device_stub__Match3PfS_S_Pi: # @_Z21__device_stub__Match3PfS_S_Pi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6Match3PfS_S_Pi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__Match3PfS_S_Pi, .Lfunc_end0-_Z21__device_stub__Match3PfS_S_Pi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6Match3PfS_S_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6Match3PfS_S_Pi,@object # @_Z6Match3PfS_S_Pi
.section .rodata,"a",@progbits
.globl _Z6Match3PfS_S_Pi
.p2align 3, 0x0
_Z6Match3PfS_S_Pi:
.quad _Z21__device_stub__Match3PfS_S_Pi
.size _Z6Match3PfS_S_Pi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6Match3PfS_S_Pi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__Match3PfS_S_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6Match3PfS_S_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004160b_00000000-6_Match3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z6Match3PfS_S_PiPfS_S_Pi
.type _Z31__device_stub__Z6Match3PfS_S_PiPfS_S_Pi, @function
_Z31__device_stub__Z6Match3PfS_S_PiPfS_S_Pi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6Match3PfS_S_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z6Match3PfS_S_PiPfS_S_Pi, .-_Z31__device_stub__Z6Match3PfS_S_PiPfS_S_Pi
.globl _Z6Match3PfS_S_Pi
.type _Z6Match3PfS_S_Pi, @function
_Z6Match3PfS_S_Pi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6Match3PfS_S_PiPfS_S_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6Match3PfS_S_Pi, .-_Z6Match3PfS_S_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6Match3PfS_S_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6Match3PfS_S_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Match3.hip"
.globl _Z21__device_stub__Match3PfS_S_Pi # -- Begin function _Z21__device_stub__Match3PfS_S_Pi
.p2align 4, 0x90
.type _Z21__device_stub__Match3PfS_S_Pi,@function
_Z21__device_stub__Match3PfS_S_Pi: # @_Z21__device_stub__Match3PfS_S_Pi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6Match3PfS_S_Pi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__Match3PfS_S_Pi, .Lfunc_end0-_Z21__device_stub__Match3PfS_S_Pi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6Match3PfS_S_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6Match3PfS_S_Pi,@object # @_Z6Match3PfS_S_Pi
.section .rodata,"a",@progbits
.globl _Z6Match3PfS_S_Pi
.p2align 3, 0x0
_Z6Match3PfS_S_Pi:
.quad _Z21__device_stub__Match3PfS_S_Pi
.size _Z6Match3PfS_S_Pi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6Match3PfS_S_Pi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__Match3PfS_S_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6Match3PfS_S_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cmath>
#include <cufft.h>
void cufft_core_execute(float* Signal_h, int Size, float2* SignalFFT_h) {
float *Signal_d;
float2 *SignalFFT_d;
cudaMalloc((void**)&Signal_d, Size*sizeof(float));
cudaMalloc((void**)&SignalFFT_d, (Size/2+1)*sizeof(float2));
cudaMemcpy(Signal_d, Signal_h, Size*sizeof(float), cudaMemcpyHostToDevice);
cufftHandle Plan;
cufftPlan1d(&Plan, Size, CUFFT_R2C, 1);
cufftExecR2C(Plan, (cufftReal*)Signal_d, (cufftComplex*)SignalFFT_d);
cudaMemcpy(SignalFFT_h, SignalFFT_d, (Size/2+1)*sizeof(float2), cudaMemcpyDeviceToHost);
cudaFree(Signal_d);
cudaFree(SignalFFT_d);
cufftDestroy(Plan);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cmath>
#include <cufft.h>
void cufft_core_execute(float* Signal_h, int Size, float2* SignalFFT_h) {
float *Signal_d;
float2 *SignalFFT_d;
cudaMalloc((void**)&Signal_d, Size*sizeof(float));
cudaMalloc((void**)&SignalFFT_d, (Size/2+1)*sizeof(float2));
cudaMemcpy(Signal_d, Signal_h, Size*sizeof(float), cudaMemcpyHostToDevice);
cufftHandle Plan;
cufftPlan1d(&Plan, Size, CUFFT_R2C, 1);
cufftExecR2C(Plan, (cufftReal*)Signal_d, (cufftComplex*)SignalFFT_d);
cudaMemcpy(SignalFFT_h, SignalFFT_d, (Size/2+1)*sizeof(float2), cudaMemcpyDeviceToHost);
cudaFree(Signal_d);
cudaFree(SignalFFT_d);
cufftDestroy(Plan);
} | .file "tmpxft_00102b10_00000000-6_cufft_core.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18cufft_core_executePfiP6float2
.type _Z18cufft_core_executePfiP6float2, @function
_Z18cufft_core_executePfiP6float2:
.LFB2050:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r14
movl %esi, %ebp
movq %rdx, %r13
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movslq %esi, %r12
salq $2, %r12
leaq 8(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %ebp, %ebx
shrl $31, %ebx
addl %ebp, %ebx
sarl %ebx
addl $1, %ebx
movslq %ebx, %rbx
salq $3, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rdi
movl $1, %ecx
movl $42, %edx
movl %ebp, %esi
call cufftPlan1d@PLT
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl 4(%rsp), %edi
call cufftExecR2C@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl 4(%rsp), %edi
call cufftDestroy@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2050:
.size _Z18cufft_core_executePfiP6float2, .-_Z18cufft_core_executePfiP6float2
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cmath>
#include <cufft.h>
void cufft_core_execute(float* Signal_h, int Size, float2* SignalFFT_h) {
float *Signal_d;
float2 *SignalFFT_d;
cudaMalloc((void**)&Signal_d, Size*sizeof(float));
cudaMalloc((void**)&SignalFFT_d, (Size/2+1)*sizeof(float2));
cudaMemcpy(Signal_d, Signal_h, Size*sizeof(float), cudaMemcpyHostToDevice);
cufftHandle Plan;
cufftPlan1d(&Plan, Size, CUFFT_R2C, 1);
cufftExecR2C(Plan, (cufftReal*)Signal_d, (cufftComplex*)SignalFFT_d);
cudaMemcpy(SignalFFT_h, SignalFFT_d, (Size/2+1)*sizeof(float2), cudaMemcpyDeviceToHost);
cudaFree(Signal_d);
cudaFree(SignalFFT_d);
cufftDestroy(Plan);
} | #include <hip/hip_runtime.h>
#include <cmath>
#include <hipfft/hipfft.h>
void cufft_core_execute(float* Signal_h, int Size, float2* SignalFFT_h) {
float *Signal_d;
float2 *SignalFFT_d;
hipMalloc((void**)&Signal_d, Size*sizeof(float));
hipMalloc((void**)&SignalFFT_d, (Size/2+1)*sizeof(float2));
hipMemcpy(Signal_d, Signal_h, Size*sizeof(float), hipMemcpyHostToDevice);
hipfftHandle Plan;
hipfftPlan1d(&Plan, Size, HIPFFT_R2C, 1);
hipfftExecR2C(Plan, (hipfftReal*)Signal_d, (hipfftComplex*)SignalFFT_d);
hipMemcpy(SignalFFT_h, SignalFFT_d, (Size/2+1)*sizeof(float2), hipMemcpyDeviceToHost);
hipFree(Signal_d);
hipFree(SignalFFT_d);
hipfftDestroy(Plan);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cmath>
#include <hipfft/hipfft.h>
void cufft_core_execute(float* Signal_h, int Size, float2* SignalFFT_h) {
float *Signal_d;
float2 *SignalFFT_d;
hipMalloc((void**)&Signal_d, Size*sizeof(float));
hipMalloc((void**)&SignalFFT_d, (Size/2+1)*sizeof(float2));
hipMemcpy(Signal_d, Signal_h, Size*sizeof(float), hipMemcpyHostToDevice);
hipfftHandle Plan;
hipfftPlan1d(&Plan, Size, HIPFFT_R2C, 1);
hipfftExecR2C(Plan, (hipfftReal*)Signal_d, (hipfftComplex*)SignalFFT_d);
hipMemcpy(SignalFFT_h, SignalFFT_d, (Size/2+1)*sizeof(float2), hipMemcpyDeviceToHost);
hipFree(Signal_d);
hipFree(SignalFFT_d);
hipfftDestroy(Plan);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cmath>
#include <hipfft/hipfft.h>
void cufft_core_execute(float* Signal_h, int Size, float2* SignalFFT_h) {
float *Signal_d;
float2 *SignalFFT_d;
hipMalloc((void**)&Signal_d, Size*sizeof(float));
hipMalloc((void**)&SignalFFT_d, (Size/2+1)*sizeof(float2));
hipMemcpy(Signal_d, Signal_h, Size*sizeof(float), hipMemcpyHostToDevice);
hipfftHandle Plan;
hipfftPlan1d(&Plan, Size, HIPFFT_R2C, 1);
hipfftExecR2C(Plan, (hipfftReal*)Signal_d, (hipfftComplex*)SignalFFT_d);
hipMemcpy(SignalFFT_h, SignalFFT_d, (Size/2+1)*sizeof(float2), hipMemcpyDeviceToHost);
hipFree(Signal_d);
hipFree(SignalFFT_d);
hipfftDestroy(Plan);
} | .text
.file "cufft_core.hip"
.globl _Z18cufft_core_executePfiP15HIP_vector_typeIfLj2EE # -- Begin function _Z18cufft_core_executePfiP15HIP_vector_typeIfLj2EE
.p2align 4, 0x90
.type _Z18cufft_core_executePfiP15HIP_vector_typeIfLj2EE,@function
_Z18cufft_core_executePfiP15HIP_vector_typeIfLj2EE: # @_Z18cufft_core_executePfiP15HIP_vector_typeIfLj2EE
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rdi, %r12
movslq %esi, %r15
leaq (,%r15,4), %r13
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movl %r15d, %eax
shrl $31, %eax
addl %r15d, %eax
sarl %eax
cltq
leaq 8(,%rax,8), %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
movl %r15d, %esi
movl $42, %edx
movl $1, %ecx
callq hipfftPlan1d
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
callq hipfftExecR2C
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipfftDestroy
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z18cufft_core_executePfiP15HIP_vector_typeIfLj2EE, .Lfunc_end0-_Z18cufft_core_executePfiP15HIP_vector_typeIfLj2EE
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00102b10_00000000-6_cufft_core.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18cufft_core_executePfiP6float2
.type _Z18cufft_core_executePfiP6float2, @function
_Z18cufft_core_executePfiP6float2:
.LFB2050:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r14
movl %esi, %ebp
movq %rdx, %r13
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movslq %esi, %r12
salq $2, %r12
leaq 8(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %ebp, %ebx
shrl $31, %ebx
addl %ebp, %ebx
sarl %ebx
addl $1, %ebx
movslq %ebx, %rbx
salq $3, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rdi
movl $1, %ecx
movl $42, %edx
movl %ebp, %esi
call cufftPlan1d@PLT
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl 4(%rsp), %edi
call cufftExecR2C@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl 4(%rsp), %edi
call cufftDestroy@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2050:
.size _Z18cufft_core_executePfiP6float2, .-_Z18cufft_core_executePfiP6float2
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cufft_core.hip"
.globl _Z18cufft_core_executePfiP15HIP_vector_typeIfLj2EE # -- Begin function _Z18cufft_core_executePfiP15HIP_vector_typeIfLj2EE
.p2align 4, 0x90
.type _Z18cufft_core_executePfiP15HIP_vector_typeIfLj2EE,@function
_Z18cufft_core_executePfiP15HIP_vector_typeIfLj2EE: # @_Z18cufft_core_executePfiP15HIP_vector_typeIfLj2EE
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rdi, %r12
movslq %esi, %r15
leaq (,%r15,4), %r13
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movl %r15d, %eax
shrl $31, %eax
addl %r15d, %eax
sarl %eax
cltq
leaq 8(,%rax,8), %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
movl %r15d, %esi
movl $42, %edx
movl $1, %ecx
callq hipfftPlan1d
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
callq hipfftExecR2C
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipfftDestroy
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z18cufft_core_executePfiP15HIP_vector_typeIfLj2EE, .Lfunc_end0-_Z18cufft_core_executePfiP15HIP_vector_typeIfLj2EE
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <math.h>
int banyakdata = 1;
int dimensigrid = 1;
int dimensiblok = 1;
__global__ void kernelenk(int *res) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int temp = 0;
for (int i = 0; i < 1000; i++)
{
for (int j = 0; j < 1000; j++)
{
int kali = 1+j+i;
temp += kali;
}
}
res[idx] = temp;
}
void fserial(int *res) {
for (int kk = 0; kk < banyakdata; ++kk)
{
int temp = 0;
for (int i = 0; i < 1000; i++)
{
for (int j = 0; j < 1000; j++)
{
int kali = 1+j+i;
temp += kali;
}
}
res[kk] = temp;
}
}
int serial(){
int *res;
res = (int*) malloc(sizeof(int) * banyakdata);
clock_t begin = clock();
fserial(res);
clock_t end = clock();
double time_spent = (double)(end - begin);
printf("Durasi enkripsi = %f milliseconds\n", time_spent / 1000);
for (int i = 0; i < 5; i++)
{
printf("Res %d : %d\n",i,res[i]);
}
printf("Res %d : %d\n",banyakdata-1,res[banyakdata-1]);
free(res);
}
int paralel(){
int *res, *devres;
res = (int*) malloc(sizeof(int) * banyakdata);
cudaMalloc((void**)&devres,sizeof(int) * banyakdata);
kernelenk<<<dimensigrid,dimensiblok>>>(devres);
cudaDeviceSynchronize();
cudaMemcpy(res, devres, sizeof(int) * banyakdata, cudaMemcpyDeviceToHost);
for (int i = 0; i < 5; i++)
{
printf("Res %d : %d\n",i,res[i]);
}
printf("Res %d : %d\n",banyakdata-1,res[banyakdata-1]);
cudaFree(devres);
free(res);
return 0;
}
int main(){
// serial();
paralel();
} | code for sm_80
Function : _Z9kernelenkPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R7, 0x3b9aca00 ; /* 0x3b9aca0000077802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0070*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <math.h>
int banyakdata = 1;
int dimensigrid = 1;
int dimensiblok = 1;
__global__ void kernelenk(int *res) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int temp = 0;
for (int i = 0; i < 1000; i++)
{
for (int j = 0; j < 1000; j++)
{
int kali = 1+j+i;
temp += kali;
}
}
res[idx] = temp;
}
void fserial(int *res) {
for (int kk = 0; kk < banyakdata; ++kk)
{
int temp = 0;
for (int i = 0; i < 1000; i++)
{
for (int j = 0; j < 1000; j++)
{
int kali = 1+j+i;
temp += kali;
}
}
res[kk] = temp;
}
}
int serial(){
int *res;
res = (int*) malloc(sizeof(int) * banyakdata);
clock_t begin = clock();
fserial(res);
clock_t end = clock();
double time_spent = (double)(end - begin);
printf("Durasi enkripsi = %f milliseconds\n", time_spent / 1000);
for (int i = 0; i < 5; i++)
{
printf("Res %d : %d\n",i,res[i]);
}
printf("Res %d : %d\n",banyakdata-1,res[banyakdata-1]);
free(res);
}
int paralel(){
int *res, *devres;
res = (int*) malloc(sizeof(int) * banyakdata);
cudaMalloc((void**)&devres,sizeof(int) * banyakdata);
kernelenk<<<dimensigrid,dimensiblok>>>(devres);
cudaDeviceSynchronize();
cudaMemcpy(res, devres, sizeof(int) * banyakdata, cudaMemcpyDeviceToHost);
for (int i = 0; i < 5; i++)
{
printf("Res %d : %d\n",i,res[i]);
}
printf("Res %d : %d\n",banyakdata-1,res[banyakdata-1]);
cudaFree(devres);
free(res);
return 0;
}
int main(){
// serial();
paralel();
} | .file "tmpxft_000f9632_00000000-6_teskernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7fserialPi
.type _Z7fserialPi, @function
_Z7fserialPi:
.LFB2057:
.cfi_startproc
endbr64
movq %rdi, %r8
movl $0, %edi
movl $0, %r9d
cmpl $0, banyakdata(%rip)
jle .L12
.L4:
movl $1998, %esi
movl $1, %ecx
movl %r9d, %edx
.L8:
movl $1000, %eax
.L6:
subl $1, %eax
jne .L6
addl %ecx, %edx
leal 498501(%rsi,%rdx), %eax
movl %eax, %edx
addl $1, %ecx
addl $999, %esi
cmpl $1001, %ecx
jne .L8
movl %eax, (%r8,%rdi,4)
addq $1, %rdi
cmpl %edi, banyakdata(%rip)
jg .L4
ret
.L12:
ret
.cfi_endproc
.LFE2057:
.size _Z7fserialPi, .-_Z7fserialPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Durasi enkripsi = %f milliseconds\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Res %d : %d\n"
.text
.globl _Z6serialv
.type _Z6serialv, @function
_Z6serialv:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movslq banyakdata(%rip), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbp
call clock@PLT
movq %rax, %rbx
movq %rbp, %rdi
call _Z7fserialPi
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC2(%rip), %r12
.L14:
movl 0(%rbp,%rbx,4), %ecx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L14
movl banyakdata(%rip), %edx
movslq %edx, %rax
movl -4(%rbp,%rax,4), %ecx
subl $1, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
.cfi_endproc
.LFE2058:
.size _Z6serialv, .-_Z6serialv
.globl _Z28__device_stub__Z9kernelenkPiPi
.type _Z28__device_stub__Z9kernelenkPiPi, @function
_Z28__device_stub__Z9kernelenkPiPi:
.LFB2085:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9kernelenkPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z28__device_stub__Z9kernelenkPiPi, .-_Z28__device_stub__Z9kernelenkPiPi
.globl _Z9kernelenkPi
.type _Z9kernelenkPi, @function
_Z9kernelenkPi:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9kernelenkPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z9kernelenkPi, .-_Z9kernelenkPi
.globl _Z7paralelv
.type _Z7paralelv, @function
_Z7paralelv:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movslq banyakdata(%rip), %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl dimensiblok(%rip), %eax
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl dimensigrid(%rip), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L26:
call cudaDeviceSynchronize@PLT
movslq banyakdata(%rip), %rdx
salq $2, %rdx
movl $2, %ecx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC2(%rip), %r12
.L27:
movl 0(%rbp,%rbx,4), %ecx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L27
movl banyakdata(%rip), %edx
movslq %edx, %rax
movl -4(%rbp,%rax,4), %ecx
subl $1, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z28__device_stub__Z9kernelenkPiPi
jmp .L26
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z7paralelv, .-_Z7paralelv
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z7paralelv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9kernelenkPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9kernelenkPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dimensiblok
.data
.align 4
.type dimensiblok, @object
.size dimensiblok, 4
dimensiblok:
.long 1
.globl dimensigrid
.align 4
.type dimensigrid, @object
.size dimensigrid, 4
dimensigrid:
.long 1
.globl banyakdata
.align 4
.type banyakdata, @object
.size banyakdata, 4
banyakdata:
.long 1
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <math.h>
int banyakdata = 1;
int dimensigrid = 1;
int dimensiblok = 1;
__global__ void kernelenk(int *res) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int temp = 0;
for (int i = 0; i < 1000; i++)
{
for (int j = 0; j < 1000; j++)
{
int kali = 1+j+i;
temp += kali;
}
}
res[idx] = temp;
}
void fserial(int *res) {
for (int kk = 0; kk < banyakdata; ++kk)
{
int temp = 0;
for (int i = 0; i < 1000; i++)
{
for (int j = 0; j < 1000; j++)
{
int kali = 1+j+i;
temp += kali;
}
}
res[kk] = temp;
}
}
int serial(){
int *res;
res = (int*) malloc(sizeof(int) * banyakdata);
clock_t begin = clock();
fserial(res);
clock_t end = clock();
double time_spent = (double)(end - begin);
printf("Durasi enkripsi = %f milliseconds\n", time_spent / 1000);
for (int i = 0; i < 5; i++)
{
printf("Res %d : %d\n",i,res[i]);
}
printf("Res %d : %d\n",banyakdata-1,res[banyakdata-1]);
free(res);
}
int paralel(){
int *res, *devres;
res = (int*) malloc(sizeof(int) * banyakdata);
cudaMalloc((void**)&devres,sizeof(int) * banyakdata);
kernelenk<<<dimensigrid,dimensiblok>>>(devres);
cudaDeviceSynchronize();
cudaMemcpy(res, devres, sizeof(int) * banyakdata, cudaMemcpyDeviceToHost);
for (int i = 0; i < 5; i++)
{
printf("Res %d : %d\n",i,res[i]);
}
printf("Res %d : %d\n",banyakdata-1,res[banyakdata-1]);
cudaFree(devres);
free(res);
return 0;
}
int main(){
// serial();
paralel();
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <math.h>
int banyakdata = 1;
int dimensigrid = 1;
int dimensiblok = 1;
__global__ void kernelenk(int *res) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int temp = 0;
for (int i = 0; i < 1000; i++)
{
for (int j = 0; j < 1000; j++)
{
int kali = 1+j+i;
temp += kali;
}
}
res[idx] = temp;
}
void fserial(int *res) {
for (int kk = 0; kk < banyakdata; ++kk)
{
int temp = 0;
for (int i = 0; i < 1000; i++)
{
for (int j = 0; j < 1000; j++)
{
int kali = 1+j+i;
temp += kali;
}
}
res[kk] = temp;
}
}
int serial(){
int *res;
res = (int*) malloc(sizeof(int) * banyakdata);
clock_t begin = clock();
fserial(res);
clock_t end = clock();
double time_spent = (double)(end - begin);
printf("Durasi enkripsi = %f milliseconds\n", time_spent / 1000);
for (int i = 0; i < 5; i++)
{
printf("Res %d : %d\n",i,res[i]);
}
printf("Res %d : %d\n",banyakdata-1,res[banyakdata-1]);
free(res);
}
int paralel(){
int *res, *devres;
res = (int*) malloc(sizeof(int) * banyakdata);
hipMalloc((void**)&devres,sizeof(int) * banyakdata);
kernelenk<<<dimensigrid,dimensiblok>>>(devres);
hipDeviceSynchronize();
hipMemcpy(res, devres, sizeof(int) * banyakdata, hipMemcpyDeviceToHost);
for (int i = 0; i < 5; i++)
{
printf("Res %d : %d\n",i,res[i]);
}
printf("Res %d : %d\n",banyakdata-1,res[banyakdata-1]);
hipFree(devres);
free(res);
return 0;
}
int main(){
// serial();
paralel();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <math.h>
int banyakdata = 1;
int dimensigrid = 1;
int dimensiblok = 1;
__global__ void kernelenk(int *res) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int temp = 0;
for (int i = 0; i < 1000; i++)
{
for (int j = 0; j < 1000; j++)
{
int kali = 1+j+i;
temp += kali;
}
}
res[idx] = temp;
}
void fserial(int *res) {
for (int kk = 0; kk < banyakdata; ++kk)
{
int temp = 0;
for (int i = 0; i < 1000; i++)
{
for (int j = 0; j < 1000; j++)
{
int kali = 1+j+i;
temp += kali;
}
}
res[kk] = temp;
}
}
int serial(){
int *res;
res = (int*) malloc(sizeof(int) * banyakdata);
clock_t begin = clock();
fserial(res);
clock_t end = clock();
double time_spent = (double)(end - begin);
printf("Durasi enkripsi = %f milliseconds\n", time_spent / 1000);
for (int i = 0; i < 5; i++)
{
printf("Res %d : %d\n",i,res[i]);
}
printf("Res %d : %d\n",banyakdata-1,res[banyakdata-1]);
free(res);
}
int paralel(){
int *res, *devres;
res = (int*) malloc(sizeof(int) * banyakdata);
hipMalloc((void**)&devres,sizeof(int) * banyakdata);
kernelenk<<<dimensigrid,dimensiblok>>>(devres);
hipDeviceSynchronize();
hipMemcpy(res, devres, sizeof(int) * banyakdata, hipMemcpyDeviceToHost);
for (int i = 0; i < 5; i++)
{
printf("Res %d : %d\n",i,res[i]);
}
printf("Res %d : %d\n",banyakdata-1,res[banyakdata-1]);
hipFree(devres);
free(res);
return 0;
}
int main(){
// serial();
paralel();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9kernelenkPi
.globl _Z9kernelenkPi
.p2align 8
.type _Z9kernelenkPi,@function
_Z9kernelenkPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0x3b9aca00
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9kernelenkPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9kernelenkPi, .Lfunc_end0-_Z9kernelenkPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9kernelenkPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9kernelenkPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <math.h>
int banyakdata = 1;
int dimensigrid = 1;
int dimensiblok = 1;
__global__ void kernelenk(int *res) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int temp = 0;
for (int i = 0; i < 1000; i++)
{
for (int j = 0; j < 1000; j++)
{
int kali = 1+j+i;
temp += kali;
}
}
res[idx] = temp;
}
void fserial(int *res) {
for (int kk = 0; kk < banyakdata; ++kk)
{
int temp = 0;
for (int i = 0; i < 1000; i++)
{
for (int j = 0; j < 1000; j++)
{
int kali = 1+j+i;
temp += kali;
}
}
res[kk] = temp;
}
}
int serial(){
int *res;
res = (int*) malloc(sizeof(int) * banyakdata);
clock_t begin = clock();
fserial(res);
clock_t end = clock();
double time_spent = (double)(end - begin);
printf("Durasi enkripsi = %f milliseconds\n", time_spent / 1000);
for (int i = 0; i < 5; i++)
{
printf("Res %d : %d\n",i,res[i]);
}
printf("Res %d : %d\n",banyakdata-1,res[banyakdata-1]);
free(res);
}
int paralel(){
int *res, *devres;
res = (int*) malloc(sizeof(int) * banyakdata);
hipMalloc((void**)&devres,sizeof(int) * banyakdata);
kernelenk<<<dimensigrid,dimensiblok>>>(devres);
hipDeviceSynchronize();
hipMemcpy(res, devres, sizeof(int) * banyakdata, hipMemcpyDeviceToHost);
for (int i = 0; i < 5; i++)
{
printf("Res %d : %d\n",i,res[i]);
}
printf("Res %d : %d\n",banyakdata-1,res[banyakdata-1]);
hipFree(devres);
free(res);
return 0;
}
int main(){
// serial();
paralel();
} | .text
.file "teskernel.hip"
.globl _Z24__device_stub__kernelenkPi # -- Begin function _Z24__device_stub__kernelenkPi
.p2align 4, 0x90
.type _Z24__device_stub__kernelenkPi,@function
_Z24__device_stub__kernelenkPi: # @_Z24__device_stub__kernelenkPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z9kernelenkPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z24__device_stub__kernelenkPi, .Lfunc_end0-_Z24__device_stub__kernelenkPi
.cfi_endproc
# -- End function
.globl _Z7fserialPi # -- Begin function _Z7fserialPi
.p2align 4, 0x90
.type _Z7fserialPi,@function
_Z7fserialPi: # @_Z7fserialPi
.cfi_startproc
# %bb.0:
cmpl $0, banyakdata(%rip)
jle .LBB1_3
# %bb.1: # %.preheader15.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_2: # %.preheader15
# =>This Inner Loop Header: Depth=1
movl $1000000000, (%rdi,%rax,4) # imm = 0x3B9ACA00
incq %rax
movslq banyakdata(%rip), %rcx
cmpq %rcx, %rax
jl .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z7fserialPi, .Lfunc_end1-_Z7fserialPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6serialv
.LCPI2_0:
.quad 0x408f400000000000 # double 1000
.text
.globl _Z6serialv
.p2align 4, 0x90
.type _Z6serialv,@function
_Z6serialv: # @_Z6serialv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movslq banyakdata(%rip), %rdi
shlq $2, %rdi
callq malloc
movq %rax, %rbx
callq clock
movq %rax, %r14
movl banyakdata(%rip), %eax
testl %eax, %eax
jle .LBB2_3
# %bb.1: # %.preheader15.i.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # %.preheader15.i
# =>This Inner Loop Header: Depth=1
movl $1000000000, (%rbx,%rcx,4) # imm = 0x3B9ACA00
incq %rcx
cmpq %rcx, %rax
jne .LBB2_2
.LBB2_3: # %_Z7fserialPi.exit
callq clock
subq %r14, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_4: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %edx
movl $.L.str.1, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $5, %r14
jne .LBB2_4
# %bb.5:
movslq banyakdata(%rip), %rsi
movl -4(%rbx,%rsi,4), %edx
decq %rsi
movl $.L.str.1, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
.Lfunc_end2:
.size _Z6serialv, .Lfunc_end2-_Z6serialv
.cfi_endproc
# -- End function
.globl _Z7paralelv # -- Begin function _Z7paralelv
.p2align 4, 0x90
.type _Z7paralelv,@function
_Z7paralelv: # @_Z7paralelv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movslq banyakdata(%rip), %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl dimensigrid(%rip), %edi
movl dimensiblok(%rip), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9kernelenkPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movslq banyakdata(%rip), %rdx
shlq $2, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %edx
movl $.L.str.1, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $5, %r14
jne .LBB3_3
# %bb.4:
movslq banyakdata(%rip), %rsi
movl -4(%rbx,%rsi,4), %edx
decq %rsi
movl $.L.str.1, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z7paralelv, .Lfunc_end3-_Z7paralelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z7paralelv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9kernelenkPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type banyakdata,@object # @banyakdata
.data
.globl banyakdata
.p2align 2, 0x0
banyakdata:
.long 1 # 0x1
.size banyakdata, 4
.type dimensigrid,@object # @dimensigrid
.globl dimensigrid
.p2align 2, 0x0
dimensigrid:
.long 1 # 0x1
.size dimensigrid, 4
.type dimensiblok,@object # @dimensiblok
.globl dimensiblok
.p2align 2, 0x0
dimensiblok:
.long 1 # 0x1
.size dimensiblok, 4
.type _Z9kernelenkPi,@object # @_Z9kernelenkPi
.section .rodata,"a",@progbits
.globl _Z9kernelenkPi
.p2align 3, 0x0
_Z9kernelenkPi:
.quad _Z24__device_stub__kernelenkPi
.size _Z9kernelenkPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Durasi enkripsi = %f milliseconds\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Res %d : %d\n"
.size .L.str.1, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9kernelenkPi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__kernelenkPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9kernelenkPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9kernelenkPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R7, 0x3b9aca00 ; /* 0x3b9aca0000077802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0070*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9kernelenkPi
.globl _Z9kernelenkPi
.p2align 8
.type _Z9kernelenkPi,@function
_Z9kernelenkPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0x3b9aca00
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9kernelenkPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9kernelenkPi, .Lfunc_end0-_Z9kernelenkPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9kernelenkPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9kernelenkPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f9632_00000000-6_teskernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7fserialPi
.type _Z7fserialPi, @function
_Z7fserialPi:
.LFB2057:
.cfi_startproc
endbr64
movq %rdi, %r8
movl $0, %edi
movl $0, %r9d
cmpl $0, banyakdata(%rip)
jle .L12
.L4:
movl $1998, %esi
movl $1, %ecx
movl %r9d, %edx
.L8:
movl $1000, %eax
.L6:
subl $1, %eax
jne .L6
addl %ecx, %edx
leal 498501(%rsi,%rdx), %eax
movl %eax, %edx
addl $1, %ecx
addl $999, %esi
cmpl $1001, %ecx
jne .L8
movl %eax, (%r8,%rdi,4)
addq $1, %rdi
cmpl %edi, banyakdata(%rip)
jg .L4
ret
.L12:
ret
.cfi_endproc
.LFE2057:
.size _Z7fserialPi, .-_Z7fserialPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Durasi enkripsi = %f milliseconds\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Res %d : %d\n"
.text
.globl _Z6serialv
.type _Z6serialv, @function
_Z6serialv:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movslq banyakdata(%rip), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbp
call clock@PLT
movq %rax, %rbx
movq %rbp, %rdi
call _Z7fserialPi
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC2(%rip), %r12
.L14:
movl 0(%rbp,%rbx,4), %ecx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L14
movl banyakdata(%rip), %edx
movslq %edx, %rax
movl -4(%rbp,%rax,4), %ecx
subl $1, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
.cfi_endproc
.LFE2058:
.size _Z6serialv, .-_Z6serialv
.globl _Z28__device_stub__Z9kernelenkPiPi
.type _Z28__device_stub__Z9kernelenkPiPi, @function
_Z28__device_stub__Z9kernelenkPiPi:
.LFB2085:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9kernelenkPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z28__device_stub__Z9kernelenkPiPi, .-_Z28__device_stub__Z9kernelenkPiPi
.globl _Z9kernelenkPi
.type _Z9kernelenkPi, @function
_Z9kernelenkPi:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9kernelenkPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z9kernelenkPi, .-_Z9kernelenkPi
.globl _Z7paralelv
.type _Z7paralelv, @function
_Z7paralelv:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movslq banyakdata(%rip), %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl dimensiblok(%rip), %eax
movl %eax, 28(%rsp)
movl $1, 32(%rsp)
movl dimensigrid(%rip), %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L26:
call cudaDeviceSynchronize@PLT
movslq banyakdata(%rip), %rdx
salq $2, %rdx
movl $2, %ecx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC2(%rip), %r12
.L27:
movl 0(%rbp,%rbx,4), %ecx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L27
movl banyakdata(%rip), %edx
movslq %edx, %rax
movl -4(%rbp,%rax,4), %ecx
subl $1, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z28__device_stub__Z9kernelenkPiPi
jmp .L26
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z7paralelv, .-_Z7paralelv
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z7paralelv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9kernelenkPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9kernelenkPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dimensiblok
.data
.align 4
.type dimensiblok, @object
.size dimensiblok, 4
dimensiblok:
.long 1
.globl dimensigrid
.align 4
.type dimensigrid, @object
.size dimensigrid, 4
dimensigrid:
.long 1
.globl banyakdata
.align 4
.type banyakdata, @object
.size banyakdata, 4
banyakdata:
.long 1
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "teskernel.hip"
.globl _Z24__device_stub__kernelenkPi # -- Begin function _Z24__device_stub__kernelenkPi
.p2align 4, 0x90
.type _Z24__device_stub__kernelenkPi,@function
_Z24__device_stub__kernelenkPi: # @_Z24__device_stub__kernelenkPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z9kernelenkPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z24__device_stub__kernelenkPi, .Lfunc_end0-_Z24__device_stub__kernelenkPi
.cfi_endproc
# -- End function
.globl _Z7fserialPi # -- Begin function _Z7fserialPi
.p2align 4, 0x90
.type _Z7fserialPi,@function
_Z7fserialPi: # @_Z7fserialPi
.cfi_startproc
# %bb.0:
cmpl $0, banyakdata(%rip)
jle .LBB1_3
# %bb.1: # %.preheader15.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_2: # %.preheader15
# =>This Inner Loop Header: Depth=1
movl $1000000000, (%rdi,%rax,4) # imm = 0x3B9ACA00
incq %rax
movslq banyakdata(%rip), %rcx
cmpq %rcx, %rax
jl .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z7fserialPi, .Lfunc_end1-_Z7fserialPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6serialv
.LCPI2_0:
.quad 0x408f400000000000 # double 1000
.text
.globl _Z6serialv
.p2align 4, 0x90
.type _Z6serialv,@function
_Z6serialv: # @_Z6serialv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movslq banyakdata(%rip), %rdi
shlq $2, %rdi
callq malloc
movq %rax, %rbx
callq clock
movq %rax, %r14
movl banyakdata(%rip), %eax
testl %eax, %eax
jle .LBB2_3
# %bb.1: # %.preheader15.i.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # %.preheader15.i
# =>This Inner Loop Header: Depth=1
movl $1000000000, (%rbx,%rcx,4) # imm = 0x3B9ACA00
incq %rcx
cmpq %rcx, %rax
jne .LBB2_2
.LBB2_3: # %_Z7fserialPi.exit
callq clock
subq %r14, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_4: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %edx
movl $.L.str.1, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $5, %r14
jne .LBB2_4
# %bb.5:
movslq banyakdata(%rip), %rsi
movl -4(%rbx,%rsi,4), %edx
decq %rsi
movl $.L.str.1, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
.Lfunc_end2:
.size _Z6serialv, .Lfunc_end2-_Z6serialv
.cfi_endproc
# -- End function
.globl _Z7paralelv # -- Begin function _Z7paralelv
.p2align 4, 0x90
.type _Z7paralelv,@function
_Z7paralelv: # @_Z7paralelv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movslq banyakdata(%rip), %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl dimensigrid(%rip), %edi
movl dimensiblok(%rip), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9kernelenkPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movslq banyakdata(%rip), %rdx
shlq $2, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %edx
movl $.L.str.1, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $5, %r14
jne .LBB3_3
# %bb.4:
movslq banyakdata(%rip), %rsi
movl -4(%rbx,%rsi,4), %edx
decq %rsi
movl $.L.str.1, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z7paralelv, .Lfunc_end3-_Z7paralelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z7paralelv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9kernelenkPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type banyakdata,@object # @banyakdata
.data
.globl banyakdata
.p2align 2, 0x0
banyakdata:
.long 1 # 0x1
.size banyakdata, 4
.type dimensigrid,@object # @dimensigrid
.globl dimensigrid
.p2align 2, 0x0
dimensigrid:
.long 1 # 0x1
.size dimensigrid, 4
.type dimensiblok,@object # @dimensiblok
.globl dimensiblok
.p2align 2, 0x0
dimensiblok:
.long 1 # 0x1
.size dimensiblok, 4
.type _Z9kernelenkPi,@object # @_Z9kernelenkPi
.section .rodata,"a",@progbits
.globl _Z9kernelenkPi
.p2align 3, 0x0
_Z9kernelenkPi:
.quad _Z24__device_stub__kernelenkPi
.size _Z9kernelenkPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Durasi enkripsi = %f milliseconds\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Res %d : %d\n"
.size .L.str.1, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9kernelenkPi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__kernelenkPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9kernelenkPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __device__ int read_cell(int * source_domain, int x, int y, int dx, int dy, unsigned int domain_x, unsigned int domain_y){
x = (unsigned int)(x + dx + domain_x) % domain_x;
y = (unsigned int)(y + dy + domain_y) % domain_y;
return source_domain[y * domain_x + x];
}
__device__ void write_cell(int * source_domain, int x, int y, int dx, int dy, unsigned int domain_x, unsigned int domain_y, int val){
x = (unsigned int)(x + dx + domain_x) % domain_x;
y = (unsigned int)(y + dy + domain_y) % domain_y;
source_domain[y * domain_x + x] = val;
}
// 1 cell per thread, 1 cell per word kernel
__global__ void life_kernel(int * source_domain, int * dest_domain, int domain_x, int domain_y) {
extern __shared__ int cells[];
int tx = blockIdx.x * (blockDim.x-2) + threadIdx.x-1;
int ty = blockIdx.y * (blockDim.y-2) + threadIdx.y-1;
int myself = read_cell(source_domain,tx,ty,0,0,domain_x,domain_y);
cells[threadIdx.y*blockDim.x+threadIdx.x] = myself;
__syncthreads();
// Read the 8 neighbors and count number of blue and red
int num_red = 0;
int num_blue = 0;
int neighbors[8];
neighbors[0] = read_cell(source_domain, tx,ty, -1,-1, domain_x, domain_y);
neighbors[1] = read_cell(source_domain, tx,ty, -1, 1, domain_x, domain_y);
neighbors[2] = read_cell(source_domain, tx,ty, 1,-1, domain_x, domain_y);
neighbors[3] = read_cell(source_domain, tx,ty, 1, 1, domain_x, domain_y);
neighbors[4] = read_cell(source_domain, tx,ty, 0,-1, domain_x, domain_y);
neighbors[5] = read_cell(source_domain, tx,ty, 0, 1, domain_x, domain_y);
neighbors[6] = read_cell(source_domain, tx,ty, 1, 0, domain_x, domain_y);
neighbors[7] = read_cell(source_domain, tx,ty, -1, 0, domain_x, domain_y);
for(int i = 0; i < 8; i++){
if(neighbors[i] == 1){
num_red ++;
}
else if(neighbors[i] == 2){
num_blue ++;
}
}
int tot = num_red + num_blue;
int newVal = myself;
if(myself == 0 && tot == 3){ // If it born
newVal = num_blue > num_red ? 2 : 1;
}
if(myself != 0 && (tot > 3 || tot < 2)){ // If it dies
newVal = 0;
}
else if(myself != 0 && (tot <= 3 || tot >= 2)){ // He continues to live
newVal = myself;
}
write_cell(source_domain, tx, ty, 0, 0, domain_x, domain_y, newVal);
} | code for sm_80
Function : _Z11life_kernelPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.U32.RP R6, c[0x0][0x174] ; /* 0x00005d0000067b06 */
/* 0x000e220000209000 */
/*0020*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e620000002500 */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e620000002100 */
/*0040*/ LOP3.LUT R14, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff0e7a12 */
/* 0x000fc600078e33ff */
/*0050*/ S2R R10, SR_TID.Y ; /* 0x00000000000a7919 */
/* 0x000ea40000002200 */
/*0060*/ I2F.U32.RP R0, c[0x0][0x170] ; /* 0x00005c0000007b06 */
/* 0x000ee20000209000 */
/*0070*/ S2UR UR5, SR_CTAID.Y ; /* 0x00000000000579c3 */
/* 0x000eae0000002600 */
/*0080*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e300000001000 */
/*0090*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x008ee20000001000 */
/*00a0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fe20007ffe0ff */
/*00b0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x2 ; /* 0x00000002ff067424 */
/* 0x000fcc00078e00ff */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000122000021f000 */
/*00d0*/ IADD3 R9, -R6, c[0x0][0x4], RZ ; /* 0x0000010006097a10 */
/* 0x000fe40007ffe1ff */
/*00e0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x008fe40007ffe0ff */
/*00f0*/ IADD3 R0, -R6, c[0x0][0x0], RZ ; /* 0x0000000006007a10 */
/* 0x000fc60007ffe1ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000762000021f000 */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD R0, R0, UR4, R7 ; /* 0x0000000400007c24 */
/* 0x002fe4000f8e0207 */
/*0130*/ IMAD.MOV R13, RZ, RZ, -R5 ; /* 0x000000ffff0d7224 */
/* 0x010fc600078e0a05 */
/*0140*/ IADD3 R11, R0, c[0x0][0x170], RZ ; /* 0x00005c00000b7a10 */
/* 0x000fe20007ffe0ff */
/*0150*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x008fe400078e00ff */
/*0160*/ IMAD R13, R13, c[0x0][0x174], RZ ; /* 0x00005d000d0d7a24 */
/* 0x000fe400078e02ff */
/*0170*/ IMAD.MOV R8, RZ, RZ, -R3 ; /* 0x000000ffff087224 */
/* 0x020fe400078e0a03 */
/*0180*/ IMAD.HI.U32 R13, R5, R13, R4 ; /* 0x0000000d050d7227 */
/* 0x000fc800078e0004 */
/*0190*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0008 */
/*01a0*/ IMAD R8, R9, UR5, R10 ; /* 0x0000000509087c24 */
/* 0x004fe2000f8e020a */
/*01b0*/ LOP3.LUT R9, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff097a12 */
/* 0x000fe200078e33ff */
/*01c0*/ IMAD R5, R6, c[0x0][0x170], RZ ; /* 0x00005c0006057a24 */
/* 0x000fe200078e02ff */
/*01d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*01e0*/ IADD3 R8, R8, c[0x0][0x174], RZ ; /* 0x00005d0008087a10 */
/* 0x000fe20007ffe0ff */
/*01f0*/ IMAD.HI.U32 R12, R3, R5, R2 ; /* 0x00000005030c7227 */
/* 0x000fe200078e0002 */
/*0200*/ IADD3 R3, R11, -0x1, RZ ; /* 0xffffffff0b037810 */
/* 0x000fe40007ffe0ff */
/*0210*/ IADD3 R2, R8, -0x1, RZ ; /* 0xffffffff08027810 */
/* 0x000fc60007ffe0ff */
/*0220*/ IMAD.HI.U32 R0, R12, R3, RZ ; /* 0x000000030c007227 */
/* 0x000fc800078e00ff */
/*0230*/ IMAD.HI.U32 R4, R13, R2, RZ ; /* 0x000000020d047227 */
/* 0x000fc800078e00ff */
/*0240*/ IMAD.MOV R5, RZ, RZ, -R4 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0a04 */
/*0250*/ IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0a00 */
/*0260*/ IMAD R5, R5, c[0x0][0x174], R2 ; /* 0x00005d0005057a24 */
/* 0x000fe400078e0202 */
/*0270*/ IMAD R6, R0, c[0x0][0x170], R3 ; /* 0x00005c0000067a24 */
/* 0x000fe400078e0203 */
/*0280*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0290*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe40003f26070 */
/*02a0*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fd60003f06070 */
/*02b0*/ @P1 IADD3 R5, R5, -c[0x0][0x174], RZ ; /* 0x80005d0005051a10 */
/* 0x000fe40007ffe0ff */
/*02c0*/ @P0 IADD3 R6, R6, -c[0x0][0x170], RZ ; /* 0x80005c0006060a10 */
/* 0x000fe40007ffe0ff */
/*02d0*/ ISETP.GE.U32.AND P3, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe40003f66070 */
/*02e0*/ ISETP.GE.U32.AND P2, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fe40003f46070 */
/*02f0*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fe40003f25070 */
/*0300*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fce0003f05070 */
/*0310*/ @P3 IADD3 R5, R5, -c[0x0][0x174], RZ ; /* 0x80005d0005053a10 */
/* 0x000fe40007ffe0ff */
/*0320*/ @P2 IADD3 R6, R6, -c[0x0][0x170], RZ ; /* 0x80005c0006062a10 */
/* 0x000fe40007ffe0ff */
/*0330*/ SEL R5, R14, R5, !P1 ; /* 0x000000050e057207 */
/* 0x000fe40004800000 */
/*0340*/ SEL R6, R9, R6, !P0 ; /* 0x0000000609067207 */
/* 0x000fca0004000000 */
/*0350*/ IMAD R3, R5, c[0x0][0x170], R6 ; /* 0x00005c0005037a24 */
/* 0x000fc800078e0206 */
/*0360*/ IMAD.WIDE.U32 R2, R3, R4, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0004 */
/*0370*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IADD3 R15, R11, -0x2, RZ ; /* 0xfffffffe0b0f7810 */
/* 0x000fe20007ffe0ff */
/*0390*/ IMAD R23, R10, c[0x0][0x0], R7 ; /* 0x000000000a177a24 */
/* 0x000fe200078e0207 */
/*03a0*/ IADD3 R18, R8, -0x2, RZ ; /* 0xfffffffe08127810 */
/* 0x000fc60007ffe0ff */
/*03b0*/ IMAD.HI.U32 R16, R12, R15, RZ ; /* 0x0000000f0c107227 */
/* 0x000fc800078e00ff */
/*03c0*/ IMAD.HI.U32 R17, R13, R18, RZ ; /* 0x000000120d117227 */
/* 0x000fc800078e00ff */
/*03d0*/ IMAD.MOV R16, RZ, RZ, -R16 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0a10 */
/*03e0*/ IMAD.HI.U32 R13, R13, R8, RZ ; /* 0x000000080d0d7227 */
/* 0x000fc800078e00ff */
/*03f0*/ IMAD.MOV R17, RZ, RZ, -R17 ; /* 0x000000ffff117224 */
/* 0x000fe400078e0a11 */
/*0400*/ IMAD R16, R16, c[0x0][0x170], R15 ; /* 0x00005c0010107a24 */
/* 0x000fe400078e020f */
/*0410*/ IMAD.MOV R19, RZ, RZ, -R13 ; /* 0x000000ffff137224 */
/* 0x000fe400078e0a0d */
/*0420*/ IMAD R13, R17, c[0x0][0x174], R18 ; /* 0x00005d00110d7a24 */
/* 0x000fe200078e0212 */
/*0430*/ ISETP.GE.U32.AND P2, PT, R16, c[0x0][0x170], PT ; /* 0x00005c0010007a0c */
/* 0x000fe20003f46070 */
/*0440*/ IMAD R15, R19, c[0x0][0x174], R8 ; /* 0x00005d00130f7a24 */
/* 0x000fe400078e0208 */
/*0450*/ IMAD.HI.U32 R12, R12, R11, RZ ; /* 0x0000000b0c0c7227 */
/* 0x000fe200078e00ff */
/*0460*/ ISETP.GE.U32.AND P3, PT, R13, c[0x0][0x174], PT ; /* 0x00005d000d007a0c */
/* 0x000fc40003f66070 */
/*0470*/ ISETP.GE.U32.AND P4, PT, R15, c[0x0][0x174], PT ; /* 0x00005d000f007a0c */
/* 0x000fe20003f86070 */
/*0480*/ IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0c7224 */
/* 0x000fc800078e0a0c */
/*0490*/ IMAD R12, R12, c[0x0][0x170], R11 ; /* 0x00005c000c0c7a24 */
/* 0x000fe400078e020b */
/*04a0*/ @P2 IADD3 R16, R16, -c[0x0][0x170], RZ ; /* 0x80005c0010102a10 */
/* 0x000fc60007ffe0ff */
/*04b0*/ ISETP.GE.U32.AND P2, PT, R12, c[0x0][0x170], PT ; /* 0x00005c000c007a0c */
/* 0x000fe40003f46070 */
/*04c0*/ @P3 IADD3 R13, R13, -c[0x0][0x174], RZ ; /* 0x80005d000d0d3a10 */
/* 0x000fe40007ffe0ff */
/*04d0*/ @P4 IADD3 R15, R15, -c[0x0][0x174], RZ ; /* 0x80005d000f0f4a10 */
/* 0x000fe40007ffe0ff */
/*04e0*/ ISETP.GE.U32.AND P5, PT, R13, c[0x0][0x174], PT ; /* 0x00005d000d007a0c */
/* 0x000fe40003fa6070 */
/*04f0*/ ISETP.GE.U32.AND P4, PT, R16, c[0x0][0x170], PT ; /* 0x00005c0010007a0c */
/* 0x000fe40003f86070 */
/*0500*/ ISETP.GE.U32.AND P3, PT, R15, c[0x0][0x174], PT ; /* 0x00005d000f007a0c */
/* 0x000fc60003f66070 */
/*0510*/ @P2 IADD3 R12, R12, -c[0x0][0x170], RZ ; /* 0x80005c000c0c2a10 */
/* 0x000fc80007ffe0ff */
/*0520*/ ISETP.GE.U32.AND P2, PT, R12, c[0x0][0x170], PT ; /* 0x00005c000c007a0c */
/* 0x000fe40003f46070 */
/*0530*/ @P5 IADD3 R13, R13, -c[0x0][0x174], RZ ; /* 0x80005d000d0d5a10 */
/* 0x000fe40007ffe0ff */
/*0540*/ @P4 IADD3 R16, R16, -c[0x0][0x170], RZ ; /* 0x80005c0010104a10 */
/* 0x000fe40007ffe0ff */
/*0550*/ @P3 IADD3 R15, R15, -c[0x0][0x174], RZ ; /* 0x80005d000f0f3a10 */
/* 0x000fe40007ffe0ff */
/*0560*/ SEL R11, R14, R13, !P1 ; /* 0x0000000d0e0b7207 */
/* 0x000fe40004800000 */
/*0570*/ SEL R8, R9, R16, !P0 ; /* 0x0000001009087207 */
/* 0x000fc40004000000 */
/*0580*/ SEL R13, R14, R15, !P1 ; /* 0x0000000f0e0d7207 */
/* 0x000fe40004800000 */
/*0590*/ @P2 IADD3 R12, R12, -c[0x0][0x170], RZ ; /* 0x80005c000c0c2a10 */
/* 0x000fe20007ffe0ff */
/*05a0*/ IMAD R15, R11, c[0x0][0x170], R8.reuse ; /* 0x00005c000b0f7a24 */
/* 0x100fe400078e0208 */
/*05b0*/ IMAD R17, R13, c[0x0][0x170], R8 ; /* 0x00005c000d117a24 */
/* 0x000fe400078e0208 */
/*05c0*/ IMAD.WIDE.U32 R14, R15, R4, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x000fe200078e0004 */
/*05d0*/ SEL R24, R9, R12, !P0 ; /* 0x0000000c09187207 */
/* 0x000fc60004000000 */
/*05e0*/ IMAD.WIDE.U32 R16, R17, R4, c[0x0][0x160] ; /* 0x0000580011107625 */
/* 0x000fc800078e0004 */
/*05f0*/ IMAD R19, R11, c[0x0][0x170], R24.reuse ; /* 0x00005c000b137a24 */
/* 0x100fe400078e0218 */
/*0600*/ IMAD R21, R13, c[0x0][0x170], R24 ; /* 0x00005c000d157a24 */
/* 0x000fe400078e0218 */
/*0610*/ IMAD.WIDE.U32 R18, R19, R4, c[0x0][0x160] ; /* 0x0000580013127625 */
/* 0x000fc800078e0004 */
/*0620*/ IMAD.WIDE.U32 R20, R21, R4, c[0x0][0x160] ; /* 0x0000580015147625 */
/* 0x000fe200078e0004 */
/*0630*/ STS [R23.X4], R0 ; /* 0x0000000017007388 */
/* 0x0041e80000004800 */
/*0640*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0650*/ IMAD R23, R11, c[0x0][0x170], R6 ; /* 0x00005c000b177a24 */
/* 0x001fca00078e0206 */
/*0660*/ LDG.E R7, [R14.64] ; /* 0x000000040e077981 */
/* 0x0000a8000c1e1900 */
/*0670*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x0002e8000c1e1900 */
/*0680*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000f22000c1e1900 */
/*0690*/ IMAD.WIDE.U32 R22, R23, R4, c[0x0][0x160] ; /* 0x0000580017167625 */
/* 0x000fc600078e0004 */
/*06a0*/ LDG.E R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x000f62000c1e1900 */
/*06b0*/ IMAD R15, R13, c[0x0][0x170], R6 ; /* 0x00005c000d0f7a24 */
/* 0x001fc600078e0206 */
/*06c0*/ LDG.E R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x000f62000c1e1900 */
/*06d0*/ IMAD.WIDE.U32 R14, R15, R4, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x000fc800078e0004 */
/*06e0*/ IMAD R17, R5.reuse, c[0x0][0x170], R24 ; /* 0x00005c0005117a24 */
/* 0x042fe200078e0218 */
/*06f0*/ LDG.E R11, [R14.64] ; /* 0x000000040e0b7981 */
/* 0x000f62000c1e1900 */
/*0700*/ IMAD R5, R5, c[0x0][0x170], R8 ; /* 0x00005c0005057a24 */
/* 0x000fe400078e0208 */
/*0710*/ IMAD.WIDE.U32 R16, R17, R4, c[0x0][0x160] ; /* 0x0000580011107625 */
/* 0x000fc800078e0004 */
/*0720*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe400078e0004 */
/*0730*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f68000c1e1900 */
/*0740*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000162000c1e1900 */
/*0750*/ IMAD.MOV.U32 R13, RZ, RZ, 0x2 ; /* 0x00000002ff0d7424 */
/* 0x000fe200078e00ff */
/*0760*/ ISETP.NE.AND P1, PT, R7, 0x2, PT ; /* 0x000000020700780c */
/* 0x004fe40003f25270 */
/*0770*/ ISETP.NE.AND P2, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x008fc40003f45270 */
/*0780*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe40003f05270 */
/*0790*/ SEL R8, RZ, 0x1, P1 ; /* 0x00000001ff087807 */
/* 0x000fe40000800000 */
/*07a0*/ ISETP.NE.AND P5, PT, R10.reuse, 0x2, PT ; /* 0x000000020a00780c */
/* 0x050fe40003fa5270 */
/*07b0*/ ISETP.NE.AND P4, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fc60003f85270 */
/*07c0*/ @P1 IMAD.MOV R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d1424 */
/* 0x000fe200078e02ff */
/*07d0*/ ISETP.NE.AND P1, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe20003f25270 */
/*07e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x2 ; /* 0x00000002ff077424 */
/* 0x000fe200078e00ff */
/*07f0*/ ISETP.NE.AND P3, PT, R12.reuse, 0x2, PT ; /* 0x000000020c00780c */
/* 0x060fe20003f65270 */
/*0800*/ @P2 IMAD.MOV R13, RZ, RZ, R8 ; /* 0x000000ffff0d2224 */
/* 0x000fe200078e0208 */
/*0810*/ ISETP.NE.AND P2, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fe40003f45270 */
/*0820*/ SEL R5, RZ, 0x1, P1 ; /* 0x00000001ff057807 */
/* 0x001fe40000800000 */
/*0830*/ SEL R8, RZ, 0x1, P4 ; /* 0x00000001ff087807 */
/* 0x000fe40002000000 */
/*0840*/ @!P0 SEL R5, R7, 0x1, !P1 ; /* 0x0000000107058807 */
/* 0x000fc40004800000 */
/*0850*/ IADD3 R9, R13, 0x1, RZ ; /* 0x000000010d097810 */
/* 0x000fe20007ffe0ff */
/*0860*/ @P5 IMAD.MOV R9, RZ, RZ, R13 ; /* 0x000000ffff095224 */
/* 0x000fe200078e020d */
/*0870*/ ISETP.NE.AND P0, PT, R6.reuse, 0x1, PT ; /* 0x000000010600780c */
/* 0x040fe20003f05270 */
/*0880*/ IMAD.IADD R5, R5, 0x1, R8 ; /* 0x0000000105057824 */
/* 0x000fe200078e0208 */
/*0890*/ ISETP.NE.AND P1, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x000fe40003f25270 */
/*08a0*/ IADD3 R8, R9, 0x1, RZ ; /* 0x0000000109087810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ @P3 IMAD.MOV R8, RZ, RZ, R9 ; /* 0x000000ffff083224 */
/* 0x000fe200078e0209 */
/*08c0*/ IADD3 R6, R5, 0x1, RZ ; /* 0x0000000105067810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ @P2 IMAD.MOV R6, RZ, RZ, R5 ; /* 0x000000ffff062224 */
/* 0x000fe200078e0205 */
/*08e0*/ ISETP.NE.AND P2, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fc40003f45270 */
/*08f0*/ ISETP.NE.AND P3, PT, R11, 0x2, PT ; /* 0x000000020b00780c */
/* 0x000fe40003f65270 */
/*0900*/ IADD3 R5, R6, 0x1, RZ ; /* 0x0000000106057810 */
/* 0x000fe20007ffe0ff */
/*0910*/ @P0 IMAD.MOV R5, RZ, RZ, R6 ; /* 0x000000ffff050224 */
/* 0x000fe200078e0206 */
/*0920*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fe20007ffe0ff */
/*0930*/ @P1 IMAD.MOV R9, RZ, RZ, R8 ; /* 0x000000ffff091224 */
/* 0x000fe200078e0208 */
/*0940*/ ISETP.NE.AND P0, PT, R16.reuse, 0x1, PT ; /* 0x000000011000780c */
/* 0x040fe40003f05270 */
/*0950*/ ISETP.NE.AND P1, PT, R16, 0x2, PT ; /* 0x000000021000780c */
/* 0x000fe40003f25270 */
/*0960*/ IADD3 R6, R5, 0x1, RZ ; /* 0x0000000105067810 */
/* 0x000fe20007ffe0ff */
/*0970*/ @P2 IMAD.MOV R6, RZ, RZ, R5 ; /* 0x000000ffff062224 */
/* 0x000fe200078e0205 */
/*0980*/ IADD3 R8, R9, 0x1, RZ ; /* 0x0000000109087810 */
/* 0x000fe20007ffe0ff */
/*0990*/ @P3 IMAD.MOV R8, RZ, RZ, R9 ; /* 0x000000ffff083224 */
/* 0x000fe200078e0209 */
/*09a0*/ ISETP.NE.AND P2, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc40003f45270 */
/*09b0*/ ISETP.NE.AND P3, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fe40003f65270 */
/*09c0*/ IADD3 R4, R6, 0x1, RZ ; /* 0x0000000106047810 */
/* 0x000fe20007ffe0ff */
/*09d0*/ @P0 IMAD.MOV R4, RZ, RZ, R6 ; /* 0x000000ffff040224 */
/* 0x000fe200078e0206 */
/*09e0*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fe20007ffe0ff */
/*09f0*/ @P1 IMAD.MOV R9, RZ, RZ, R8 ; /* 0x000000ffff091224 */
/* 0x000fc600078e0208 */
/*0a00*/ IADD3 R5, R4, 0x1, RZ ; /* 0x0000000104057810 */
/* 0x000fe40007ffe0ff */
/*0a10*/ IADD3 R6, R9, 0x1, RZ ; /* 0x0000000109067810 */
/* 0x000fe20007ffe0ff */
/*0a20*/ @P2 IMAD.MOV R5, RZ, RZ, R4 ; /* 0x000000ffff052224 */
/* 0x000fe400078e0204 */
/*0a30*/ @P3 IMAD.MOV R6, RZ, RZ, R9 ; /* 0x000000ffff063224 */
/* 0x000fc800078e0209 */
/*0a40*/ IMAD.IADD R4, R5, 0x1, R6 ; /* 0x0000000105047824 */
/* 0x000fe200078e0206 */
/*0a50*/ ISETP.GT.AND P2, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x000fc80003f44270 */
/*0a60*/ ISETP.NE.AND P1, PT, R4.reuse, 0x3, PT ; /* 0x000000030400780c */
/* 0x040fe40003f25270 */
/*0a70*/ LOP3.LUT R4, R4, 0xfffffffe, RZ, 0xc0, !PT ; /* 0xfffffffe04047812 */
/* 0x000fe400078ec0ff */
/*0a80*/ ISETP.EQ.AND P1, PT, R0, RZ, !P1 ; /* 0x000000ff0000720c */
/* 0x000fe40004f22270 */
/*0a90*/ ISETP.NE.AND P0, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fc80003f05270 */
/*0aa0*/ ISETP.NE.AND P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fce0000705270 */
/*0ab0*/ @P1 SEL R0, R7, 0x1, P2 ; /* 0x0000000107001807 */
/* 0x000fc80001000000 */
/*0ac0*/ SEL R5, R0, RZ, !P0 ; /* 0x000000ff00057207 */
/* 0x000fca0004000000 */
/*0ad0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0ae0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0af0*/ BRA 0xaf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __device__ int read_cell(int * source_domain, int x, int y, int dx, int dy, unsigned int domain_x, unsigned int domain_y){
x = (unsigned int)(x + dx + domain_x) % domain_x;
y = (unsigned int)(y + dy + domain_y) % domain_y;
return source_domain[y * domain_x + x];
}
__device__ void write_cell(int * source_domain, int x, int y, int dx, int dy, unsigned int domain_x, unsigned int domain_y, int val){
x = (unsigned int)(x + dx + domain_x) % domain_x;
y = (unsigned int)(y + dy + domain_y) % domain_y;
source_domain[y * domain_x + x] = val;
}
// 1 cell per thread, 1 cell per word kernel
__global__ void life_kernel(int * source_domain, int * dest_domain, int domain_x, int domain_y) {
extern __shared__ int cells[];
int tx = blockIdx.x * (blockDim.x-2) + threadIdx.x-1;
int ty = blockIdx.y * (blockDim.y-2) + threadIdx.y-1;
int myself = read_cell(source_domain,tx,ty,0,0,domain_x,domain_y);
cells[threadIdx.y*blockDim.x+threadIdx.x] = myself;
__syncthreads();
// Read the 8 neighbors and count number of blue and red
int num_red = 0;
int num_blue = 0;
int neighbors[8];
neighbors[0] = read_cell(source_domain, tx,ty, -1,-1, domain_x, domain_y);
neighbors[1] = read_cell(source_domain, tx,ty, -1, 1, domain_x, domain_y);
neighbors[2] = read_cell(source_domain, tx,ty, 1,-1, domain_x, domain_y);
neighbors[3] = read_cell(source_domain, tx,ty, 1, 1, domain_x, domain_y);
neighbors[4] = read_cell(source_domain, tx,ty, 0,-1, domain_x, domain_y);
neighbors[5] = read_cell(source_domain, tx,ty, 0, 1, domain_x, domain_y);
neighbors[6] = read_cell(source_domain, tx,ty, 1, 0, domain_x, domain_y);
neighbors[7] = read_cell(source_domain, tx,ty, -1, 0, domain_x, domain_y);
for(int i = 0; i < 8; i++){
if(neighbors[i] == 1){
num_red ++;
}
else if(neighbors[i] == 2){
num_blue ++;
}
}
int tot = num_red + num_blue;
int newVal = myself;
if(myself == 0 && tot == 3){ // If it born
newVal = num_blue > num_red ? 2 : 1;
}
if(myself != 0 && (tot > 3 || tot < 2)){ // If it dies
newVal = 0;
}
else if(myself != 0 && (tot <= 3 || tot >= 2)){ // He continues to live
newVal = myself;
}
write_cell(source_domain, tx, ty, 0, 0, domain_x, domain_y, newVal);
} | .file "tmpxft_00073ffb_00000000-6_life_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9read_cellPiiiiijj
.type _Z9read_cellPiiiiijj, @function
_Z9read_cellPiiiiijj:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z9read_cellPiiiiijj, .-_Z9read_cellPiiiiijj
.globl _Z10write_cellPiiiiijji
.type _Z10write_cellPiiiiijji, @function
_Z10write_cellPiiiiijji:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z10write_cellPiiiiijji, .-_Z10write_cellPiiiiijji
.globl _Z35__device_stub__Z11life_kernelPiS_iiPiS_ii
.type _Z35__device_stub__Z11life_kernelPiS_iiPiS_ii, @function
_Z35__device_stub__Z11life_kernelPiS_iiPiS_ii:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11life_kernelPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z35__device_stub__Z11life_kernelPiS_iiPiS_ii, .-_Z35__device_stub__Z11life_kernelPiS_iiPiS_ii
.globl _Z11life_kernelPiS_ii
.type _Z11life_kernelPiS_ii, @function
_Z11life_kernelPiS_ii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11life_kernelPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z11life_kernelPiS_ii, .-_Z11life_kernelPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11life_kernelPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11life_kernelPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __device__ int read_cell(int * source_domain, int x, int y, int dx, int dy, unsigned int domain_x, unsigned int domain_y){
x = (unsigned int)(x + dx + domain_x) % domain_x;
y = (unsigned int)(y + dy + domain_y) % domain_y;
return source_domain[y * domain_x + x];
}
__device__ void write_cell(int * source_domain, int x, int y, int dx, int dy, unsigned int domain_x, unsigned int domain_y, int val){
x = (unsigned int)(x + dx + domain_x) % domain_x;
y = (unsigned int)(y + dy + domain_y) % domain_y;
source_domain[y * domain_x + x] = val;
}
// 1 cell per thread, 1 cell per word kernel
__global__ void life_kernel(int * source_domain, int * dest_domain, int domain_x, int domain_y) {
extern __shared__ int cells[];
int tx = blockIdx.x * (blockDim.x-2) + threadIdx.x-1;
int ty = blockIdx.y * (blockDim.y-2) + threadIdx.y-1;
int myself = read_cell(source_domain,tx,ty,0,0,domain_x,domain_y);
cells[threadIdx.y*blockDim.x+threadIdx.x] = myself;
__syncthreads();
// Read the 8 neighbors and count number of blue and red
int num_red = 0;
int num_blue = 0;
int neighbors[8];
neighbors[0] = read_cell(source_domain, tx,ty, -1,-1, domain_x, domain_y);
neighbors[1] = read_cell(source_domain, tx,ty, -1, 1, domain_x, domain_y);
neighbors[2] = read_cell(source_domain, tx,ty, 1,-1, domain_x, domain_y);
neighbors[3] = read_cell(source_domain, tx,ty, 1, 1, domain_x, domain_y);
neighbors[4] = read_cell(source_domain, tx,ty, 0,-1, domain_x, domain_y);
neighbors[5] = read_cell(source_domain, tx,ty, 0, 1, domain_x, domain_y);
neighbors[6] = read_cell(source_domain, tx,ty, 1, 0, domain_x, domain_y);
neighbors[7] = read_cell(source_domain, tx,ty, -1, 0, domain_x, domain_y);
for(int i = 0; i < 8; i++){
if(neighbors[i] == 1){
num_red ++;
}
else if(neighbors[i] == 2){
num_blue ++;
}
}
int tot = num_red + num_blue;
int newVal = myself;
if(myself == 0 && tot == 3){ // If it born
newVal = num_blue > num_red ? 2 : 1;
}
if(myself != 0 && (tot > 3 || tot < 2)){ // If it dies
newVal = 0;
}
else if(myself != 0 && (tot <= 3 || tot >= 2)){ // He continues to live
newVal = myself;
}
write_cell(source_domain, tx, ty, 0, 0, domain_x, domain_y, newVal);
} | #include <hip/hip_runtime.h>
__device__ int read_cell(int * source_domain, int x, int y, int dx, int dy, unsigned int domain_x, unsigned int domain_y){
x = (unsigned int)(x + dx + domain_x) % domain_x;
y = (unsigned int)(y + dy + domain_y) % domain_y;
return source_domain[y * domain_x + x];
}
__device__ void write_cell(int * source_domain, int x, int y, int dx, int dy, unsigned int domain_x, unsigned int domain_y, int val){
x = (unsigned int)(x + dx + domain_x) % domain_x;
y = (unsigned int)(y + dy + domain_y) % domain_y;
source_domain[y * domain_x + x] = val;
}
// 1 cell per thread, 1 cell per word kernel
__global__ void life_kernel(int * source_domain, int * dest_domain, int domain_x, int domain_y) {
extern __shared__ int cells[];
int tx = blockIdx.x * (blockDim.x-2) + threadIdx.x-1;
int ty = blockIdx.y * (blockDim.y-2) + threadIdx.y-1;
int myself = read_cell(source_domain,tx,ty,0,0,domain_x,domain_y);
cells[threadIdx.y*blockDim.x+threadIdx.x] = myself;
__syncthreads();
// Read the 8 neighbors and count number of blue and red
int num_red = 0;
int num_blue = 0;
int neighbors[8];
neighbors[0] = read_cell(source_domain, tx,ty, -1,-1, domain_x, domain_y);
neighbors[1] = read_cell(source_domain, tx,ty, -1, 1, domain_x, domain_y);
neighbors[2] = read_cell(source_domain, tx,ty, 1,-1, domain_x, domain_y);
neighbors[3] = read_cell(source_domain, tx,ty, 1, 1, domain_x, domain_y);
neighbors[4] = read_cell(source_domain, tx,ty, 0,-1, domain_x, domain_y);
neighbors[5] = read_cell(source_domain, tx,ty, 0, 1, domain_x, domain_y);
neighbors[6] = read_cell(source_domain, tx,ty, 1, 0, domain_x, domain_y);
neighbors[7] = read_cell(source_domain, tx,ty, -1, 0, domain_x, domain_y);
for(int i = 0; i < 8; i++){
if(neighbors[i] == 1){
num_red ++;
}
else if(neighbors[i] == 2){
num_blue ++;
}
}
int tot = num_red + num_blue;
int newVal = myself;
if(myself == 0 && tot == 3){ // If it born
newVal = num_blue > num_red ? 2 : 1;
}
if(myself != 0 && (tot > 3 || tot < 2)){ // If it dies
newVal = 0;
}
else if(myself != 0 && (tot <= 3 || tot >= 2)){ // He continues to live
newVal = myself;
}
write_cell(source_domain, tx, ty, 0, 0, domain_x, domain_y, newVal);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__device__ int read_cell(int * source_domain, int x, int y, int dx, int dy, unsigned int domain_x, unsigned int domain_y){
x = (unsigned int)(x + dx + domain_x) % domain_x;
y = (unsigned int)(y + dy + domain_y) % domain_y;
return source_domain[y * domain_x + x];
}
__device__ void write_cell(int * source_domain, int x, int y, int dx, int dy, unsigned int domain_x, unsigned int domain_y, int val){
x = (unsigned int)(x + dx + domain_x) % domain_x;
y = (unsigned int)(y + dy + domain_y) % domain_y;
source_domain[y * domain_x + x] = val;
}
// 1 cell per thread, 1 cell per word kernel
__global__ void life_kernel(int * source_domain, int * dest_domain, int domain_x, int domain_y) {
extern __shared__ int cells[];
int tx = blockIdx.x * (blockDim.x-2) + threadIdx.x-1;
int ty = blockIdx.y * (blockDim.y-2) + threadIdx.y-1;
int myself = read_cell(source_domain,tx,ty,0,0,domain_x,domain_y);
cells[threadIdx.y*blockDim.x+threadIdx.x] = myself;
__syncthreads();
// Read the 8 neighbors and count number of blue and red
int num_red = 0;
int num_blue = 0;
int neighbors[8];
neighbors[0] = read_cell(source_domain, tx,ty, -1,-1, domain_x, domain_y);
neighbors[1] = read_cell(source_domain, tx,ty, -1, 1, domain_x, domain_y);
neighbors[2] = read_cell(source_domain, tx,ty, 1,-1, domain_x, domain_y);
neighbors[3] = read_cell(source_domain, tx,ty, 1, 1, domain_x, domain_y);
neighbors[4] = read_cell(source_domain, tx,ty, 0,-1, domain_x, domain_y);
neighbors[5] = read_cell(source_domain, tx,ty, 0, 1, domain_x, domain_y);
neighbors[6] = read_cell(source_domain, tx,ty, 1, 0, domain_x, domain_y);
neighbors[7] = read_cell(source_domain, tx,ty, -1, 0, domain_x, domain_y);
for(int i = 0; i < 8; i++){
if(neighbors[i] == 1){
num_red ++;
}
else if(neighbors[i] == 2){
num_blue ++;
}
}
int tot = num_red + num_blue;
int newVal = myself;
if(myself == 0 && tot == 3){ // If it born
newVal = num_blue > num_red ? 2 : 1;
}
if(myself != 0 && (tot > 3 || tot < 2)){ // If it dies
newVal = 0;
}
else if(myself != 0 && (tot <= 3 || tot >= 2)){ // He continues to live
newVal = myself;
}
write_cell(source_domain, tx, ty, 0, 0, domain_x, domain_y, newVal);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11life_kernelPiS_ii
.globl _Z11life_kernelPiS_ii
.p2align 8
.type _Z11life_kernelPiS_ii,@function
_Z11life_kernelPiS_ii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x24
v_bfe_u32 v4, v0, 10, 10
v_and_b32_e32 v7, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s3
v_cvt_f32_u32_e32 v2, s2
s_sub_i32 s5, 0, s3
s_sub_i32 s6, 0, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v1, 0x4f7ffffe, v1 :: v_dual_mul_f32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v1, v1
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, s5, v1
s_lshr_b32 s5, s4, 16
v_mul_lo_u32 v5, s6, v2
s_add_i32 s5, s5, -2
s_and_b32 s4, s4, 0xffff
s_mul_i32 s5, s5, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v6, s3, s5, v4
v_mul_hi_u32 v3, v1, v3
s_add_i32 s5, s4, -2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mul_hi_u32 v5, v2, v5
s_mul_i32 s5, s5, s14
v_add_nc_u32_e32 v0, -1, v6
v_add_nc_u32_e32 v11, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v0, v11
v_mul_lo_u32 v1, v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v1
v_subrev_nc_u32_e32 v1, s3, v0
v_cmp_le_u32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
v_add3_u32 v12, s2, s5, v7
v_add_nc_u32_e32 v5, v2, v5
v_mad_u32_u24 v4, v4, s4, v7
v_add_nc_u32_e32 v3, -1, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v21, v4, 2, 0
v_mul_hi_u32 v2, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s2
v_sub_nc_u32_e32 v2, v3, v2
v_subrev_nc_u32_e32 v3, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v1, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
v_cndmask_b32_e32 v1, v2, v1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s2, v1
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s2, v1
v_mul_lo_u32 v19, v0, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v15, v1, v2, vcc_lo
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, v19, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_add_nc_u32_e32 v0, -2, v6
v_add_co_u32 v8, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v3, vcc_lo
v_mul_hi_u32 v2, v0, v11
v_add_nc_u32_e32 v3, -2, v12
global_load_b32 v10, v[8:9], off
v_mul_hi_u32 v13, v3, v5
v_mul_hi_u32 v5, v12, v5
v_mul_lo_u32 v2, v2, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v13, v13, s2
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v5, s2
v_subrev_nc_u32_e32 v5, s3, v0
v_cmp_le_u32_e32 vcc_lo, s3, v0
v_sub_nc_u32_e32 v3, v3, v13
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_nc_u32_e32 v2, v12, v2
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
v_mul_hi_u32 v11, v6, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v12, s3, v0
v_mul_lo_u32 v11, v11, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v6, v6, v11
v_subrev_nc_u32_e32 v11, s2, v3
v_subrev_nc_u32_e32 v5, s3, v6
v_cmp_le_u32_e32 vcc_lo, s3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v6, v5, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s2, v3
v_subrev_nc_u32_e32 v6, s3, v5
v_cndmask_b32_e32 v3, v3, v11, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v0
v_subrev_nc_u32_e32 v11, s2, v2
v_cndmask_b32_e32 v0, v0, v12, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v5
v_subrev_nc_u32_e32 v12, s2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_lo_u32 v13, v0, s2
v_cndmask_b32_e32 v0, v5, v6, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s2, v3
v_mul_lo_u32 v16, v0, s2
v_cndmask_b32_e32 v20, v3, v12, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v5, v2, v11 :: v_dual_add_nc_u32 v0, v13, v20
v_subrev_nc_u32_e32 v6, s2, v5
v_cmp_le_u32_e32 vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_dual_cndmask_b32 v17, v5, v6 :: v_dual_add_nc_u32 v0, v16, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v0, v17, v13
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_add_nc_u32_e32 v0, v17, v16
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_lshlrev_b64 v[11:12], 2, v[0:1]
v_add_nc_u32_e32 v0, v13, v15
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[13:14], 2, v[0:1]
v_add_nc_u32_e32 v0, v16, v15
v_add_co_u32 v11, vcc_lo, s0, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s1, v12, vcc_lo
v_lshlrev_b64 v[15:16], 2, v[0:1]
v_add_nc_u32_e32 v0, v17, v19
v_add_co_u32 v13, vcc_lo, s0, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s1, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[17:18], 2, v[0:1]
v_add_nc_u32_e32 v0, v20, v19
v_add_co_u32 v15, vcc_lo, s0, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s1, v16, vcc_lo
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v17, vcc_lo, s0, v17
v_add_co_ci_u32_e32 v18, vcc_lo, s1, v18, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v19, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v20, vcc_lo, s1, v1, vcc_lo
s_mov_b64 s[0:1], 0
s_waitcnt vmcnt(0)
ds_store_b32 v21, v10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_clause 0x7
global_load_b32 v0, v[2:3], off
global_load_b32 v1, v[4:5], off
global_load_b32 v2, v[6:7], off
global_load_b32 v3, v[11:12], off
global_load_b32 v4, v[13:14], off
global_load_b32 v5, v[15:16], off
global_load_b32 v6, v[17:18], off
global_load_b32 v7, v[19:20], off
v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v12, 0
s_branch .LBB0_3
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
s_add_u32 s0, s0, 1
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s0, 8
s_cbranch_scc1 .LBB0_10
.LBB0_3:
s_mov_b32 m0, s0
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
v_movrels_b32_e32 v13, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 1, v13
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_7
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 2, v13
v_add_nc_u32_e32 v12, 1, v12
s_or_b32 exec_lo, exec_lo, s3
.LBB0_7:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_2
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 1, v13
s_cbranch_execz .LBB0_1
v_add_nc_u32_e32 v11, 1, v11
s_branch .LBB0_1
.LBB0_10:
v_add_nc_u32_e32 v0, v11, v12
v_cmp_gt_i32_e64 s1, v12, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, -2, v0
v_cmp_eq_u32_e32 vcc_lo, 3, v0
v_cmp_eq_u32_e64 s0, 2, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v1, 1, 2, s1
v_cndmask_b32_e64 v0, 0, v10, s0
v_cmp_eq_u32_e64 s0, 0, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
s_and_b32 vcc_lo, s0, vcc_lo
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v0, v0, v1, s0
global_store_b32 v[8:9], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11life_kernelPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11life_kernelPiS_ii, .Lfunc_end0-_Z11life_kernelPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11life_kernelPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11life_kernelPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__device__ int read_cell(int * source_domain, int x, int y, int dx, int dy, unsigned int domain_x, unsigned int domain_y){
x = (unsigned int)(x + dx + domain_x) % domain_x;
y = (unsigned int)(y + dy + domain_y) % domain_y;
return source_domain[y * domain_x + x];
}
__device__ void write_cell(int * source_domain, int x, int y, int dx, int dy, unsigned int domain_x, unsigned int domain_y, int val){
x = (unsigned int)(x + dx + domain_x) % domain_x;
y = (unsigned int)(y + dy + domain_y) % domain_y;
source_domain[y * domain_x + x] = val;
}
// 1 cell per thread, 1 cell per word kernel
__global__ void life_kernel(int * source_domain, int * dest_domain, int domain_x, int domain_y) {
extern __shared__ int cells[];
int tx = blockIdx.x * (blockDim.x-2) + threadIdx.x-1;
int ty = blockIdx.y * (blockDim.y-2) + threadIdx.y-1;
int myself = read_cell(source_domain,tx,ty,0,0,domain_x,domain_y);
cells[threadIdx.y*blockDim.x+threadIdx.x] = myself;
__syncthreads();
// Read the 8 neighbors and count number of blue and red
int num_red = 0;
int num_blue = 0;
int neighbors[8];
neighbors[0] = read_cell(source_domain, tx,ty, -1,-1, domain_x, domain_y);
neighbors[1] = read_cell(source_domain, tx,ty, -1, 1, domain_x, domain_y);
neighbors[2] = read_cell(source_domain, tx,ty, 1,-1, domain_x, domain_y);
neighbors[3] = read_cell(source_domain, tx,ty, 1, 1, domain_x, domain_y);
neighbors[4] = read_cell(source_domain, tx,ty, 0,-1, domain_x, domain_y);
neighbors[5] = read_cell(source_domain, tx,ty, 0, 1, domain_x, domain_y);
neighbors[6] = read_cell(source_domain, tx,ty, 1, 0, domain_x, domain_y);
neighbors[7] = read_cell(source_domain, tx,ty, -1, 0, domain_x, domain_y);
for(int i = 0; i < 8; i++){
if(neighbors[i] == 1){
num_red ++;
}
else if(neighbors[i] == 2){
num_blue ++;
}
}
int tot = num_red + num_blue;
int newVal = myself;
if(myself == 0 && tot == 3){ // If it born
newVal = num_blue > num_red ? 2 : 1;
}
if(myself != 0 && (tot > 3 || tot < 2)){ // If it dies
newVal = 0;
}
else if(myself != 0 && (tot <= 3 || tot >= 2)){ // He continues to live
newVal = myself;
}
write_cell(source_domain, tx, ty, 0, 0, domain_x, domain_y, newVal);
} | .text
.file "life_kernel.hip"
.globl _Z26__device_stub__life_kernelPiS_ii # -- Begin function _Z26__device_stub__life_kernelPiS_ii
.p2align 4, 0x90
.type _Z26__device_stub__life_kernelPiS_ii,@function
_Z26__device_stub__life_kernelPiS_ii: # @_Z26__device_stub__life_kernelPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11life_kernelPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__life_kernelPiS_ii, .Lfunc_end0-_Z26__device_stub__life_kernelPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11life_kernelPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11life_kernelPiS_ii,@object # @_Z11life_kernelPiS_ii
.section .rodata,"a",@progbits
.globl _Z11life_kernelPiS_ii
.p2align 3, 0x0
_Z11life_kernelPiS_ii:
.quad _Z26__device_stub__life_kernelPiS_ii
.size _Z11life_kernelPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11life_kernelPiS_ii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__life_kernelPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11life_kernelPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11life_kernelPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.U32.RP R6, c[0x0][0x174] ; /* 0x00005d0000067b06 */
/* 0x000e220000209000 */
/*0020*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e620000002500 */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e620000002100 */
/*0040*/ LOP3.LUT R14, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff0e7a12 */
/* 0x000fc600078e33ff */
/*0050*/ S2R R10, SR_TID.Y ; /* 0x00000000000a7919 */
/* 0x000ea40000002200 */
/*0060*/ I2F.U32.RP R0, c[0x0][0x170] ; /* 0x00005c0000007b06 */
/* 0x000ee20000209000 */
/*0070*/ S2UR UR5, SR_CTAID.Y ; /* 0x00000000000579c3 */
/* 0x000eae0000002600 */
/*0080*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e300000001000 */
/*0090*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x008ee20000001000 */
/*00a0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fe20007ffe0ff */
/*00b0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x2 ; /* 0x00000002ff067424 */
/* 0x000fcc00078e00ff */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000122000021f000 */
/*00d0*/ IADD3 R9, -R6, c[0x0][0x4], RZ ; /* 0x0000010006097a10 */
/* 0x000fe40007ffe1ff */
/*00e0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x008fe40007ffe0ff */
/*00f0*/ IADD3 R0, -R6, c[0x0][0x0], RZ ; /* 0x0000000006007a10 */
/* 0x000fc60007ffe1ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000762000021f000 */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD R0, R0, UR4, R7 ; /* 0x0000000400007c24 */
/* 0x002fe4000f8e0207 */
/*0130*/ IMAD.MOV R13, RZ, RZ, -R5 ; /* 0x000000ffff0d7224 */
/* 0x010fc600078e0a05 */
/*0140*/ IADD3 R11, R0, c[0x0][0x170], RZ ; /* 0x00005c00000b7a10 */
/* 0x000fe20007ffe0ff */
/*0150*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x008fe400078e00ff */
/*0160*/ IMAD R13, R13, c[0x0][0x174], RZ ; /* 0x00005d000d0d7a24 */
/* 0x000fe400078e02ff */
/*0170*/ IMAD.MOV R8, RZ, RZ, -R3 ; /* 0x000000ffff087224 */
/* 0x020fe400078e0a03 */
/*0180*/ IMAD.HI.U32 R13, R5, R13, R4 ; /* 0x0000000d050d7227 */
/* 0x000fc800078e0004 */
/*0190*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0008 */
/*01a0*/ IMAD R8, R9, UR5, R10 ; /* 0x0000000509087c24 */
/* 0x004fe2000f8e020a */
/*01b0*/ LOP3.LUT R9, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff097a12 */
/* 0x000fe200078e33ff */
/*01c0*/ IMAD R5, R6, c[0x0][0x170], RZ ; /* 0x00005c0006057a24 */
/* 0x000fe200078e02ff */
/*01d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*01e0*/ IADD3 R8, R8, c[0x0][0x174], RZ ; /* 0x00005d0008087a10 */
/* 0x000fe20007ffe0ff */
/*01f0*/ IMAD.HI.U32 R12, R3, R5, R2 ; /* 0x00000005030c7227 */
/* 0x000fe200078e0002 */
/*0200*/ IADD3 R3, R11, -0x1, RZ ; /* 0xffffffff0b037810 */
/* 0x000fe40007ffe0ff */
/*0210*/ IADD3 R2, R8, -0x1, RZ ; /* 0xffffffff08027810 */
/* 0x000fc60007ffe0ff */
/*0220*/ IMAD.HI.U32 R0, R12, R3, RZ ; /* 0x000000030c007227 */
/* 0x000fc800078e00ff */
/*0230*/ IMAD.HI.U32 R4, R13, R2, RZ ; /* 0x000000020d047227 */
/* 0x000fc800078e00ff */
/*0240*/ IMAD.MOV R5, RZ, RZ, -R4 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0a04 */
/*0250*/ IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0a00 */
/*0260*/ IMAD R5, R5, c[0x0][0x174], R2 ; /* 0x00005d0005057a24 */
/* 0x000fe400078e0202 */
/*0270*/ IMAD R6, R0, c[0x0][0x170], R3 ; /* 0x00005c0000067a24 */
/* 0x000fe400078e0203 */
/*0280*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0290*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe40003f26070 */
/*02a0*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fd60003f06070 */
/*02b0*/ @P1 IADD3 R5, R5, -c[0x0][0x174], RZ ; /* 0x80005d0005051a10 */
/* 0x000fe40007ffe0ff */
/*02c0*/ @P0 IADD3 R6, R6, -c[0x0][0x170], RZ ; /* 0x80005c0006060a10 */
/* 0x000fe40007ffe0ff */
/*02d0*/ ISETP.GE.U32.AND P3, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe40003f66070 */
/*02e0*/ ISETP.GE.U32.AND P2, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fe40003f46070 */
/*02f0*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fe40003f25070 */
/*0300*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fce0003f05070 */
/*0310*/ @P3 IADD3 R5, R5, -c[0x0][0x174], RZ ; /* 0x80005d0005053a10 */
/* 0x000fe40007ffe0ff */
/*0320*/ @P2 IADD3 R6, R6, -c[0x0][0x170], RZ ; /* 0x80005c0006062a10 */
/* 0x000fe40007ffe0ff */
/*0330*/ SEL R5, R14, R5, !P1 ; /* 0x000000050e057207 */
/* 0x000fe40004800000 */
/*0340*/ SEL R6, R9, R6, !P0 ; /* 0x0000000609067207 */
/* 0x000fca0004000000 */
/*0350*/ IMAD R3, R5, c[0x0][0x170], R6 ; /* 0x00005c0005037a24 */
/* 0x000fc800078e0206 */
/*0360*/ IMAD.WIDE.U32 R2, R3, R4, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0004 */
/*0370*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IADD3 R15, R11, -0x2, RZ ; /* 0xfffffffe0b0f7810 */
/* 0x000fe20007ffe0ff */
/*0390*/ IMAD R23, R10, c[0x0][0x0], R7 ; /* 0x000000000a177a24 */
/* 0x000fe200078e0207 */
/*03a0*/ IADD3 R18, R8, -0x2, RZ ; /* 0xfffffffe08127810 */
/* 0x000fc60007ffe0ff */
/*03b0*/ IMAD.HI.U32 R16, R12, R15, RZ ; /* 0x0000000f0c107227 */
/* 0x000fc800078e00ff */
/*03c0*/ IMAD.HI.U32 R17, R13, R18, RZ ; /* 0x000000120d117227 */
/* 0x000fc800078e00ff */
/*03d0*/ IMAD.MOV R16, RZ, RZ, -R16 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0a10 */
/*03e0*/ IMAD.HI.U32 R13, R13, R8, RZ ; /* 0x000000080d0d7227 */
/* 0x000fc800078e00ff */
/*03f0*/ IMAD.MOV R17, RZ, RZ, -R17 ; /* 0x000000ffff117224 */
/* 0x000fe400078e0a11 */
/*0400*/ IMAD R16, R16, c[0x0][0x170], R15 ; /* 0x00005c0010107a24 */
/* 0x000fe400078e020f */
/*0410*/ IMAD.MOV R19, RZ, RZ, -R13 ; /* 0x000000ffff137224 */
/* 0x000fe400078e0a0d */
/*0420*/ IMAD R13, R17, c[0x0][0x174], R18 ; /* 0x00005d00110d7a24 */
/* 0x000fe200078e0212 */
/*0430*/ ISETP.GE.U32.AND P2, PT, R16, c[0x0][0x170], PT ; /* 0x00005c0010007a0c */
/* 0x000fe20003f46070 */
/*0440*/ IMAD R15, R19, c[0x0][0x174], R8 ; /* 0x00005d00130f7a24 */
/* 0x000fe400078e0208 */
/*0450*/ IMAD.HI.U32 R12, R12, R11, RZ ; /* 0x0000000b0c0c7227 */
/* 0x000fe200078e00ff */
/*0460*/ ISETP.GE.U32.AND P3, PT, R13, c[0x0][0x174], PT ; /* 0x00005d000d007a0c */
/* 0x000fc40003f66070 */
/*0470*/ ISETP.GE.U32.AND P4, PT, R15, c[0x0][0x174], PT ; /* 0x00005d000f007a0c */
/* 0x000fe20003f86070 */
/*0480*/ IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0c7224 */
/* 0x000fc800078e0a0c */
/*0490*/ IMAD R12, R12, c[0x0][0x170], R11 ; /* 0x00005c000c0c7a24 */
/* 0x000fe400078e020b */
/*04a0*/ @P2 IADD3 R16, R16, -c[0x0][0x170], RZ ; /* 0x80005c0010102a10 */
/* 0x000fc60007ffe0ff */
/*04b0*/ ISETP.GE.U32.AND P2, PT, R12, c[0x0][0x170], PT ; /* 0x00005c000c007a0c */
/* 0x000fe40003f46070 */
/*04c0*/ @P3 IADD3 R13, R13, -c[0x0][0x174], RZ ; /* 0x80005d000d0d3a10 */
/* 0x000fe40007ffe0ff */
/*04d0*/ @P4 IADD3 R15, R15, -c[0x0][0x174], RZ ; /* 0x80005d000f0f4a10 */
/* 0x000fe40007ffe0ff */
/*04e0*/ ISETP.GE.U32.AND P5, PT, R13, c[0x0][0x174], PT ; /* 0x00005d000d007a0c */
/* 0x000fe40003fa6070 */
/*04f0*/ ISETP.GE.U32.AND P4, PT, R16, c[0x0][0x170], PT ; /* 0x00005c0010007a0c */
/* 0x000fe40003f86070 */
/*0500*/ ISETP.GE.U32.AND P3, PT, R15, c[0x0][0x174], PT ; /* 0x00005d000f007a0c */
/* 0x000fc60003f66070 */
/*0510*/ @P2 IADD3 R12, R12, -c[0x0][0x170], RZ ; /* 0x80005c000c0c2a10 */
/* 0x000fc80007ffe0ff */
/*0520*/ ISETP.GE.U32.AND P2, PT, R12, c[0x0][0x170], PT ; /* 0x00005c000c007a0c */
/* 0x000fe40003f46070 */
/*0530*/ @P5 IADD3 R13, R13, -c[0x0][0x174], RZ ; /* 0x80005d000d0d5a10 */
/* 0x000fe40007ffe0ff */
/*0540*/ @P4 IADD3 R16, R16, -c[0x0][0x170], RZ ; /* 0x80005c0010104a10 */
/* 0x000fe40007ffe0ff */
/*0550*/ @P3 IADD3 R15, R15, -c[0x0][0x174], RZ ; /* 0x80005d000f0f3a10 */
/* 0x000fe40007ffe0ff */
/*0560*/ SEL R11, R14, R13, !P1 ; /* 0x0000000d0e0b7207 */
/* 0x000fe40004800000 */
/*0570*/ SEL R8, R9, R16, !P0 ; /* 0x0000001009087207 */
/* 0x000fc40004000000 */
/*0580*/ SEL R13, R14, R15, !P1 ; /* 0x0000000f0e0d7207 */
/* 0x000fe40004800000 */
/*0590*/ @P2 IADD3 R12, R12, -c[0x0][0x170], RZ ; /* 0x80005c000c0c2a10 */
/* 0x000fe20007ffe0ff */
/*05a0*/ IMAD R15, R11, c[0x0][0x170], R8.reuse ; /* 0x00005c000b0f7a24 */
/* 0x100fe400078e0208 */
/*05b0*/ IMAD R17, R13, c[0x0][0x170], R8 ; /* 0x00005c000d117a24 */
/* 0x000fe400078e0208 */
/*05c0*/ IMAD.WIDE.U32 R14, R15, R4, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x000fe200078e0004 */
/*05d0*/ SEL R24, R9, R12, !P0 ; /* 0x0000000c09187207 */
/* 0x000fc60004000000 */
/*05e0*/ IMAD.WIDE.U32 R16, R17, R4, c[0x0][0x160] ; /* 0x0000580011107625 */
/* 0x000fc800078e0004 */
/*05f0*/ IMAD R19, R11, c[0x0][0x170], R24.reuse ; /* 0x00005c000b137a24 */
/* 0x100fe400078e0218 */
/*0600*/ IMAD R21, R13, c[0x0][0x170], R24 ; /* 0x00005c000d157a24 */
/* 0x000fe400078e0218 */
/*0610*/ IMAD.WIDE.U32 R18, R19, R4, c[0x0][0x160] ; /* 0x0000580013127625 */
/* 0x000fc800078e0004 */
/*0620*/ IMAD.WIDE.U32 R20, R21, R4, c[0x0][0x160] ; /* 0x0000580015147625 */
/* 0x000fe200078e0004 */
/*0630*/ STS [R23.X4], R0 ; /* 0x0000000017007388 */
/* 0x0041e80000004800 */
/*0640*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0650*/ IMAD R23, R11, c[0x0][0x170], R6 ; /* 0x00005c000b177a24 */
/* 0x001fca00078e0206 */
/*0660*/ LDG.E R7, [R14.64] ; /* 0x000000040e077981 */
/* 0x0000a8000c1e1900 */
/*0670*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x0002e8000c1e1900 */
/*0680*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000f22000c1e1900 */
/*0690*/ IMAD.WIDE.U32 R22, R23, R4, c[0x0][0x160] ; /* 0x0000580017167625 */
/* 0x000fc600078e0004 */
/*06a0*/ LDG.E R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x000f62000c1e1900 */
/*06b0*/ IMAD R15, R13, c[0x0][0x170], R6 ; /* 0x00005c000d0f7a24 */
/* 0x001fc600078e0206 */
/*06c0*/ LDG.E R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x000f62000c1e1900 */
/*06d0*/ IMAD.WIDE.U32 R14, R15, R4, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x000fc800078e0004 */
/*06e0*/ IMAD R17, R5.reuse, c[0x0][0x170], R24 ; /* 0x00005c0005117a24 */
/* 0x042fe200078e0218 */
/*06f0*/ LDG.E R11, [R14.64] ; /* 0x000000040e0b7981 */
/* 0x000f62000c1e1900 */
/*0700*/ IMAD R5, R5, c[0x0][0x170], R8 ; /* 0x00005c0005057a24 */
/* 0x000fe400078e0208 */
/*0710*/ IMAD.WIDE.U32 R16, R17, R4, c[0x0][0x160] ; /* 0x0000580011107625 */
/* 0x000fc800078e0004 */
/*0720*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe400078e0004 */
/*0730*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f68000c1e1900 */
/*0740*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000162000c1e1900 */
/*0750*/ IMAD.MOV.U32 R13, RZ, RZ, 0x2 ; /* 0x00000002ff0d7424 */
/* 0x000fe200078e00ff */
/*0760*/ ISETP.NE.AND P1, PT, R7, 0x2, PT ; /* 0x000000020700780c */
/* 0x004fe40003f25270 */
/*0770*/ ISETP.NE.AND P2, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x008fc40003f45270 */
/*0780*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe40003f05270 */
/*0790*/ SEL R8, RZ, 0x1, P1 ; /* 0x00000001ff087807 */
/* 0x000fe40000800000 */
/*07a0*/ ISETP.NE.AND P5, PT, R10.reuse, 0x2, PT ; /* 0x000000020a00780c */
/* 0x050fe40003fa5270 */
/*07b0*/ ISETP.NE.AND P4, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fc60003f85270 */
/*07c0*/ @P1 IMAD.MOV R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d1424 */
/* 0x000fe200078e02ff */
/*07d0*/ ISETP.NE.AND P1, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe20003f25270 */
/*07e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x2 ; /* 0x00000002ff077424 */
/* 0x000fe200078e00ff */
/*07f0*/ ISETP.NE.AND P3, PT, R12.reuse, 0x2, PT ; /* 0x000000020c00780c */
/* 0x060fe20003f65270 */
/*0800*/ @P2 IMAD.MOV R13, RZ, RZ, R8 ; /* 0x000000ffff0d2224 */
/* 0x000fe200078e0208 */
/*0810*/ ISETP.NE.AND P2, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fe40003f45270 */
/*0820*/ SEL R5, RZ, 0x1, P1 ; /* 0x00000001ff057807 */
/* 0x001fe40000800000 */
/*0830*/ SEL R8, RZ, 0x1, P4 ; /* 0x00000001ff087807 */
/* 0x000fe40002000000 */
/*0840*/ @!P0 SEL R5, R7, 0x1, !P1 ; /* 0x0000000107058807 */
/* 0x000fc40004800000 */
/*0850*/ IADD3 R9, R13, 0x1, RZ ; /* 0x000000010d097810 */
/* 0x000fe20007ffe0ff */
/*0860*/ @P5 IMAD.MOV R9, RZ, RZ, R13 ; /* 0x000000ffff095224 */
/* 0x000fe200078e020d */
/*0870*/ ISETP.NE.AND P0, PT, R6.reuse, 0x1, PT ; /* 0x000000010600780c */
/* 0x040fe20003f05270 */
/*0880*/ IMAD.IADD R5, R5, 0x1, R8 ; /* 0x0000000105057824 */
/* 0x000fe200078e0208 */
/*0890*/ ISETP.NE.AND P1, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x000fe40003f25270 */
/*08a0*/ IADD3 R8, R9, 0x1, RZ ; /* 0x0000000109087810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ @P3 IMAD.MOV R8, RZ, RZ, R9 ; /* 0x000000ffff083224 */
/* 0x000fe200078e0209 */
/*08c0*/ IADD3 R6, R5, 0x1, RZ ; /* 0x0000000105067810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ @P2 IMAD.MOV R6, RZ, RZ, R5 ; /* 0x000000ffff062224 */
/* 0x000fe200078e0205 */
/*08e0*/ ISETP.NE.AND P2, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fc40003f45270 */
/*08f0*/ ISETP.NE.AND P3, PT, R11, 0x2, PT ; /* 0x000000020b00780c */
/* 0x000fe40003f65270 */
/*0900*/ IADD3 R5, R6, 0x1, RZ ; /* 0x0000000106057810 */
/* 0x000fe20007ffe0ff */
/*0910*/ @P0 IMAD.MOV R5, RZ, RZ, R6 ; /* 0x000000ffff050224 */
/* 0x000fe200078e0206 */
/*0920*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fe20007ffe0ff */
/*0930*/ @P1 IMAD.MOV R9, RZ, RZ, R8 ; /* 0x000000ffff091224 */
/* 0x000fe200078e0208 */
/*0940*/ ISETP.NE.AND P0, PT, R16.reuse, 0x1, PT ; /* 0x000000011000780c */
/* 0x040fe40003f05270 */
/*0950*/ ISETP.NE.AND P1, PT, R16, 0x2, PT ; /* 0x000000021000780c */
/* 0x000fe40003f25270 */
/*0960*/ IADD3 R6, R5, 0x1, RZ ; /* 0x0000000105067810 */
/* 0x000fe20007ffe0ff */
/*0970*/ @P2 IMAD.MOV R6, RZ, RZ, R5 ; /* 0x000000ffff062224 */
/* 0x000fe200078e0205 */
/*0980*/ IADD3 R8, R9, 0x1, RZ ; /* 0x0000000109087810 */
/* 0x000fe20007ffe0ff */
/*0990*/ @P3 IMAD.MOV R8, RZ, RZ, R9 ; /* 0x000000ffff083224 */
/* 0x000fe200078e0209 */
/*09a0*/ ISETP.NE.AND P2, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc40003f45270 */
/*09b0*/ ISETP.NE.AND P3, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fe40003f65270 */
/*09c0*/ IADD3 R4, R6, 0x1, RZ ; /* 0x0000000106047810 */
/* 0x000fe20007ffe0ff */
/*09d0*/ @P0 IMAD.MOV R4, RZ, RZ, R6 ; /* 0x000000ffff040224 */
/* 0x000fe200078e0206 */
/*09e0*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fe20007ffe0ff */
/*09f0*/ @P1 IMAD.MOV R9, RZ, RZ, R8 ; /* 0x000000ffff091224 */
/* 0x000fc600078e0208 */
/*0a00*/ IADD3 R5, R4, 0x1, RZ ; /* 0x0000000104057810 */
/* 0x000fe40007ffe0ff */
/*0a10*/ IADD3 R6, R9, 0x1, RZ ; /* 0x0000000109067810 */
/* 0x000fe20007ffe0ff */
/*0a20*/ @P2 IMAD.MOV R5, RZ, RZ, R4 ; /* 0x000000ffff052224 */
/* 0x000fe400078e0204 */
/*0a30*/ @P3 IMAD.MOV R6, RZ, RZ, R9 ; /* 0x000000ffff063224 */
/* 0x000fc800078e0209 */
/*0a40*/ IMAD.IADD R4, R5, 0x1, R6 ; /* 0x0000000105047824 */
/* 0x000fe200078e0206 */
/*0a50*/ ISETP.GT.AND P2, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x000fc80003f44270 */
/*0a60*/ ISETP.NE.AND P1, PT, R4.reuse, 0x3, PT ; /* 0x000000030400780c */
/* 0x040fe40003f25270 */
/*0a70*/ LOP3.LUT R4, R4, 0xfffffffe, RZ, 0xc0, !PT ; /* 0xfffffffe04047812 */
/* 0x000fe400078ec0ff */
/*0a80*/ ISETP.EQ.AND P1, PT, R0, RZ, !P1 ; /* 0x000000ff0000720c */
/* 0x000fe40004f22270 */
/*0a90*/ ISETP.NE.AND P0, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fc80003f05270 */
/*0aa0*/ ISETP.NE.AND P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fce0000705270 */
/*0ab0*/ @P1 SEL R0, R7, 0x1, P2 ; /* 0x0000000107001807 */
/* 0x000fc80001000000 */
/*0ac0*/ SEL R5, R0, RZ, !P0 ; /* 0x000000ff00057207 */
/* 0x000fca0004000000 */
/*0ad0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0ae0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0af0*/ BRA 0xaf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11life_kernelPiS_ii
.globl _Z11life_kernelPiS_ii
.p2align 8
.type _Z11life_kernelPiS_ii,@function
_Z11life_kernelPiS_ii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x24
v_bfe_u32 v4, v0, 10, 10
v_and_b32_e32 v7, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s3
v_cvt_f32_u32_e32 v2, s2
s_sub_i32 s5, 0, s3
s_sub_i32 s6, 0, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v1, 0x4f7ffffe, v1 :: v_dual_mul_f32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v1, v1
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, s5, v1
s_lshr_b32 s5, s4, 16
v_mul_lo_u32 v5, s6, v2
s_add_i32 s5, s5, -2
s_and_b32 s4, s4, 0xffff
s_mul_i32 s5, s5, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v6, s3, s5, v4
v_mul_hi_u32 v3, v1, v3
s_add_i32 s5, s4, -2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mul_hi_u32 v5, v2, v5
s_mul_i32 s5, s5, s14
v_add_nc_u32_e32 v0, -1, v6
v_add_nc_u32_e32 v11, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v0, v11
v_mul_lo_u32 v1, v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v1
v_subrev_nc_u32_e32 v1, s3, v0
v_cmp_le_u32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
v_add3_u32 v12, s2, s5, v7
v_add_nc_u32_e32 v5, v2, v5
v_mad_u32_u24 v4, v4, s4, v7
v_add_nc_u32_e32 v3, -1, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v21, v4, 2, 0
v_mul_hi_u32 v2, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s2
v_sub_nc_u32_e32 v2, v3, v2
v_subrev_nc_u32_e32 v3, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v1, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
v_cndmask_b32_e32 v1, v2, v1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s2, v1
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s2, v1
v_mul_lo_u32 v19, v0, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v15, v1, v2, vcc_lo
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, v19, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_add_nc_u32_e32 v0, -2, v6
v_add_co_u32 v8, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v3, vcc_lo
v_mul_hi_u32 v2, v0, v11
v_add_nc_u32_e32 v3, -2, v12
global_load_b32 v10, v[8:9], off
v_mul_hi_u32 v13, v3, v5
v_mul_hi_u32 v5, v12, v5
v_mul_lo_u32 v2, v2, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v13, v13, s2
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v5, s2
v_subrev_nc_u32_e32 v5, s3, v0
v_cmp_le_u32_e32 vcc_lo, s3, v0
v_sub_nc_u32_e32 v3, v3, v13
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_nc_u32_e32 v2, v12, v2
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
v_mul_hi_u32 v11, v6, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v12, s3, v0
v_mul_lo_u32 v11, v11, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v6, v6, v11
v_subrev_nc_u32_e32 v11, s2, v3
v_subrev_nc_u32_e32 v5, s3, v6
v_cmp_le_u32_e32 vcc_lo, s3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v6, v5, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s2, v3
v_subrev_nc_u32_e32 v6, s3, v5
v_cndmask_b32_e32 v3, v3, v11, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v0
v_subrev_nc_u32_e32 v11, s2, v2
v_cndmask_b32_e32 v0, v0, v12, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v5
v_subrev_nc_u32_e32 v12, s2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_lo_u32 v13, v0, s2
v_cndmask_b32_e32 v0, v5, v6, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s2, v3
v_mul_lo_u32 v16, v0, s2
v_cndmask_b32_e32 v20, v3, v12, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v5, v2, v11 :: v_dual_add_nc_u32 v0, v13, v20
v_subrev_nc_u32_e32 v6, s2, v5
v_cmp_le_u32_e32 vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_dual_cndmask_b32 v17, v5, v6 :: v_dual_add_nc_u32 v0, v16, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v0, v17, v13
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_add_nc_u32_e32 v0, v17, v16
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_lshlrev_b64 v[11:12], 2, v[0:1]
v_add_nc_u32_e32 v0, v13, v15
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[13:14], 2, v[0:1]
v_add_nc_u32_e32 v0, v16, v15
v_add_co_u32 v11, vcc_lo, s0, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s1, v12, vcc_lo
v_lshlrev_b64 v[15:16], 2, v[0:1]
v_add_nc_u32_e32 v0, v17, v19
v_add_co_u32 v13, vcc_lo, s0, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s1, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[17:18], 2, v[0:1]
v_add_nc_u32_e32 v0, v20, v19
v_add_co_u32 v15, vcc_lo, s0, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s1, v16, vcc_lo
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v17, vcc_lo, s0, v17
v_add_co_ci_u32_e32 v18, vcc_lo, s1, v18, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v19, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v20, vcc_lo, s1, v1, vcc_lo
s_mov_b64 s[0:1], 0
s_waitcnt vmcnt(0)
ds_store_b32 v21, v10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_clause 0x7
global_load_b32 v0, v[2:3], off
global_load_b32 v1, v[4:5], off
global_load_b32 v2, v[6:7], off
global_load_b32 v3, v[11:12], off
global_load_b32 v4, v[13:14], off
global_load_b32 v5, v[15:16], off
global_load_b32 v6, v[17:18], off
global_load_b32 v7, v[19:20], off
v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v12, 0
s_branch .LBB0_3
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
s_add_u32 s0, s0, 1
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s0, 8
s_cbranch_scc1 .LBB0_10
.LBB0_3:
s_mov_b32 m0, s0
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
v_movrels_b32_e32 v13, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 1, v13
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_7
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 2, v13
v_add_nc_u32_e32 v12, 1, v12
s_or_b32 exec_lo, exec_lo, s3
.LBB0_7:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_2
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 1, v13
s_cbranch_execz .LBB0_1
v_add_nc_u32_e32 v11, 1, v11
s_branch .LBB0_1
.LBB0_10:
v_add_nc_u32_e32 v0, v11, v12
v_cmp_gt_i32_e64 s1, v12, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, -2, v0
v_cmp_eq_u32_e32 vcc_lo, 3, v0
v_cmp_eq_u32_e64 s0, 2, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v1, 1, 2, s1
v_cndmask_b32_e64 v0, 0, v10, s0
v_cmp_eq_u32_e64 s0, 0, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
s_and_b32 vcc_lo, s0, vcc_lo
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v0, v0, v1, s0
global_store_b32 v[8:9], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11life_kernelPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11life_kernelPiS_ii, .Lfunc_end0-_Z11life_kernelPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11life_kernelPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11life_kernelPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00073ffb_00000000-6_life_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9read_cellPiiiiijj
.type _Z9read_cellPiiiiijj, @function
_Z9read_cellPiiiiijj:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z9read_cellPiiiiijj, .-_Z9read_cellPiiiiijj
.globl _Z10write_cellPiiiiijji
.type _Z10write_cellPiiiiijji, @function
_Z10write_cellPiiiiijji:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z10write_cellPiiiiijji, .-_Z10write_cellPiiiiijji
.globl _Z35__device_stub__Z11life_kernelPiS_iiPiS_ii
.type _Z35__device_stub__Z11life_kernelPiS_iiPiS_ii, @function
_Z35__device_stub__Z11life_kernelPiS_iiPiS_ii:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11life_kernelPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z35__device_stub__Z11life_kernelPiS_iiPiS_ii, .-_Z35__device_stub__Z11life_kernelPiS_iiPiS_ii
.globl _Z11life_kernelPiS_ii
.type _Z11life_kernelPiS_ii, @function
_Z11life_kernelPiS_ii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11life_kernelPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z11life_kernelPiS_ii, .-_Z11life_kernelPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11life_kernelPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11life_kernelPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "life_kernel.hip"
.globl _Z26__device_stub__life_kernelPiS_ii # -- Begin function _Z26__device_stub__life_kernelPiS_ii
.p2align 4, 0x90
.type _Z26__device_stub__life_kernelPiS_ii,@function
_Z26__device_stub__life_kernelPiS_ii: # @_Z26__device_stub__life_kernelPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11life_kernelPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__life_kernelPiS_ii, .Lfunc_end0-_Z26__device_stub__life_kernelPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11life_kernelPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11life_kernelPiS_ii,@object # @_Z11life_kernelPiS_ii
.section .rodata,"a",@progbits
.globl _Z11life_kernelPiS_ii
.p2align 3, 0x0
_Z11life_kernelPiS_ii:
.quad _Z26__device_stub__life_kernelPiS_ii
.size _Z11life_kernelPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11life_kernelPiS_ii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__life_kernelPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11life_kernelPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void laplacianFilter(unsigned char *srcImage, unsigned char *dstImage, unsigned int width, unsigned int height)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
float ker[3][3] = {{0, -1, 0}, {-1, 4, -1}, {0, -1, 0}};
//float kernel[3][3] = {-1, -1, -1, -1, 8, -1, -1, -1, -1};
// only threads inside image will write results
if((x>=FILTER_WIDTH/2) && (x<(width-FILTER_WIDTH/2)) && (y>=FILTER_HEIGHT/2) && (y<(height-FILTER_HEIGHT/2)))
{
// Sum of pixel values
float sum = 0;
// Loop inside the filter to average pixel values
for(int ky=-FILTER_HEIGHT/2; ky<=FILTER_HEIGHT/2; ky++) {
for(int kx=-FILTER_WIDTH/2; kx<=FILTER_WIDTH/2; kx++) {
float fl = srcImage[((y+ky)*width + (x+kx))];
sum += fl*ker[ky+FILTER_HEIGHT/2][kx+FILTER_WIDTH/2];
}
}
dstImage[(y*width+x)] = sum;
}
} | code for sm_80
Function : _Z15laplacianFilterPhS_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*0030*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UIADD3 UR4, -UR5, UR6, URZ ; /* 0x0000000605047290 */
/* 0x000fc6000fffe13f */
/*0060*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0070*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fe2000bf06070 */
/*00a0*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fe2000fffe13f */
/*00b0*/ IMAD R3, R0, c[0x0][0x4], R5 ; /* 0x0000010000037a24 */
/* 0x002fe400078e0205 */
/*00c0*/ ISETP.LT.OR P0, PT, R2, 0x1, P0 ; /* 0x000000010200780c */
/* 0x000fc80000701670 */
/*00d0*/ ISETP.LT.OR P0, PT, R3, 0x1, P0 ; /* 0x000000010300780c */
/* 0x000fc80000701670 */
/*00e0*/ ISETP.GE.U32.OR P0, PT, R3, UR4, P0 ; /* 0x0000000403007c0c */
/* 0x000fda0008706470 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ IMAD R0, R3.reuse, c[0x0][0x170], R2 ; /* 0x00005c0003007a24 */
/* 0x040fe200078e0202 */
/*0110*/ IADD3 R3, R3, -0x1, RZ ; /* 0xffffffff03037810 */
/* 0x000fe20007ffe0ff */
/*0120*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0130*/ IADD3 R12, P0, R0.reuse, c[0x0][0x160], RZ ; /* 0x00005800000c7a10 */
/* 0x040fe20007f1e0ff */
/*0140*/ IMAD R3, R3, c[0x0][0x170], R2 ; /* 0x00005c0003037a24 */
/* 0x000fe200078e0202 */
/*0150*/ IADD3 R10, R0, -0x1, RZ ; /* 0xffffffff000a7810 */
/* 0x000fc60007ffe0ff */
/*0160*/ IMAD.X R13, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff0d7624 */
/* 0x000fe200000e06ff */
/*0170*/ IADD3 R6, P1, R3.reuse, c[0x0][0x160], RZ ; /* 0x0000580003067a10 */
/* 0x040fe40007f3e0ff */
/*0180*/ IADD3 R4, R3.reuse, -0x1, RZ ; /* 0xffffffff03047810 */
/* 0x040fe40007ffe0ff */
/*0190*/ IADD3 R10, P0, R10, c[0x0][0x160], RZ ; /* 0x000058000a0a7a10 */
/* 0x000fe20007f1e0ff */
/*01a0*/ IMAD.X R7, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff077624 */
/* 0x000fe200008e06ff */
/*01b0*/ IADD3 R4, P1, R4, c[0x0][0x160], RZ ; /* 0x0000580004047a10 */
/* 0x000fe20007f3e0ff */
/*01c0*/ LDG.E.U8 R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x0000a2000c1e1100 */
/*01d0*/ IADD3 R8, R3, 0x1, RZ ; /* 0x0000000103087810 */
/* 0x000fe20007ffe0ff */
/*01e0*/ IMAD.X R11, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff0b7624 */
/* 0x000fc400000e06ff */
/*01f0*/ IMAD.X R5, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff057624 */
/* 0x000fe200008e06ff */
/*0200*/ IADD3 R8, P0, R8, c[0x0][0x160], RZ ; /* 0x0000580008087a10 */
/* 0x000fe20007f1e0ff */
/*0210*/ LDG.E.U8 R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x0002e8000c1e1100 */
/*0220*/ LDG.E.U8 R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000962000c1e1100 */
/*0230*/ IADD3.X R9, RZ, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900ff097a10 */
/* 0x000fe400007fe4ff */
/*0240*/ IADD3 R14, R0.reuse, 0x1, RZ ; /* 0x00000001000e7810 */
/* 0x040fe20007ffe0ff */
/*0250*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1100 */
/*0260*/ IADD3 R17, R0, c[0x0][0x170], RZ ; /* 0x00005c0000117a10 */
/* 0x000fc40007ffe0ff */
/*0270*/ IADD3 R12, P0, R14, c[0x0][0x160], RZ ; /* 0x000058000e0c7a10 */
/* 0x001fe20007f1e0ff */
/*0280*/ LDG.E.U8 R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1100 */
/*0290*/ IADD3 R6, R17, -0x1, RZ ; /* 0xffffffff11067810 */
/* 0x002fc60007ffe0ff */
/*02a0*/ IMAD.X R13, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff0d7624 */
/* 0x000fe200000e06ff */
/*02b0*/ IADD3 R4, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x010fe40007f1e0ff */
/*02c0*/ IADD3 R14, P1, R17.reuse, c[0x0][0x160], RZ ; /* 0x00005800110e7a10 */
/* 0x040fe40007f3e0ff */
/*02d0*/ IADD3 R6, R17, 0x1, RZ ; /* 0x0000000111067810 */
/* 0x000fe20007ffe0ff */
/*02e0*/ IMAD.X R5, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff057624 */
/* 0x000fe200000e06ff */
/*02f0*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f22000c1e1100 */
/*0300*/ IMAD.X R15, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff0f7624 */
/* 0x000fe200008e06ff */
/*0310*/ IADD3 R6, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006067a10 */
/* 0x000fe40007f1e0ff */
/*0320*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000f24000c1e1100 */
/*0330*/ IADD3.X R7, RZ, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900ff077a10 */
/* 0x000fc400007fe4ff */
/*0340*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f28000c1e1100 */
/*0350*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f22000c1e1100 */
/*0360*/ I2F.U16 R3, R3 ; /* 0x0000000300037306 */
/* 0x008ff00000101000 */
/*0370*/ I2F.U16 R16, R16 ; /* 0x0000001000107306 */
/* 0x020e300000101000 */
/*0380*/ I2F.U16 R9, R9 ; /* 0x0000000900097306 */
/* 0x004e700000101000 */
/*0390*/ I2F.U16 R11, R10 ; /* 0x0000000a000b7306 */
/* 0x000ea20000101000 */
/*03a0*/ FFMA R8, RZ, R16, RZ ; /* 0x00000010ff087223 */
/* 0x001fce00000000ff */
/*03b0*/ I2F.U16 R17, R2 ; /* 0x0000000200117306 */
/* 0x000e220000101000 */
/*03c0*/ FADD R8, R8, -R3 ; /* 0x8000000308087221 */
/* 0x000fce0000000000 */
/*03d0*/ I2F.U16 R13, R12 ; /* 0x0000000c000d7306 */
/* 0x010ee20000101000 */
/*03e0*/ FFMA R8, RZ, R9, R8 ; /* 0x00000009ff087223 */
/* 0x002fce0000000008 */
/*03f0*/ I2F.U16 R5, R4 ; /* 0x0000000400057306 */
/* 0x000e620000101000 */
/*0400*/ FADD R8, R8, -R11 ; /* 0x8000000b08087221 */
/* 0x004fce0000000000 */
/*0410*/ I2F.U16 R14, R14 ; /* 0x0000000e000e7306 */
/* 0x000ea20000101000 */
/*0420*/ FFMA R8, R17, 4, R8 ; /* 0x4080000011087823 */
/* 0x001fce0000000008 */
/*0430*/ I2F.U16 R6, R6 ; /* 0x0000000600067306 */
/* 0x000e220000101000 */
/*0440*/ FADD R8, R8, -R13 ; /* 0x8000000d08087221 */
/* 0x008fc80000000000 */
/*0450*/ FFMA R5, RZ, R5, R8 ; /* 0x00000005ff057223 */
/* 0x002fc80000000008 */
/*0460*/ FADD R5, R5, -R14 ; /* 0x8000000e05057221 */
/* 0x004fc80000000000 */
/*0470*/ FFMA R5, RZ, R6, R5 ; /* 0x00000006ff057223 */
/* 0x001fcc0000000005 */
/*0480*/ F2I.U32.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e22000020f000 */
/*0490*/ IADD3 R2, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x000fca0007f1e0ff */
/*04a0*/ IMAD.X R3, RZ, RZ, c[0x0][0x16c], P0 ; /* 0x00005b00ff037624 */
/* 0x000fca00000e06ff */
/*04b0*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101104 */
/*04c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04d0*/ BRA 0x4d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void laplacianFilter(unsigned char *srcImage, unsigned char *dstImage, unsigned int width, unsigned int height)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
float ker[3][3] = {{0, -1, 0}, {-1, 4, -1}, {0, -1, 0}};
//float kernel[3][3] = {-1, -1, -1, -1, 8, -1, -1, -1, -1};
// only threads inside image will write results
if((x>=FILTER_WIDTH/2) && (x<(width-FILTER_WIDTH/2)) && (y>=FILTER_HEIGHT/2) && (y<(height-FILTER_HEIGHT/2)))
{
// Sum of pixel values
float sum = 0;
// Loop inside the filter to average pixel values
for(int ky=-FILTER_HEIGHT/2; ky<=FILTER_HEIGHT/2; ky++) {
for(int kx=-FILTER_WIDTH/2; kx<=FILTER_WIDTH/2; kx++) {
float fl = srcImage[((y+ky)*width + (x+kx))];
sum += fl*ker[ky+FILTER_HEIGHT/2][kx+FILTER_WIDTH/2];
}
}
dstImage[(y*width+x)] = sum;
}
} | .file "tmpxft_000286fc_00000000-6_laplacianFilter.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15laplacianFilterPhS_jjPhS_jj
.type _Z39__device_stub__Z15laplacianFilterPhS_jjPhS_jj, @function
_Z39__device_stub__Z15laplacianFilterPhS_jjPhS_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15laplacianFilterPhS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z15laplacianFilterPhS_jjPhS_jj, .-_Z39__device_stub__Z15laplacianFilterPhS_jjPhS_jj
.globl _Z15laplacianFilterPhS_jj
.type _Z15laplacianFilterPhS_jj, @function
_Z15laplacianFilterPhS_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15laplacianFilterPhS_jjPhS_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15laplacianFilterPhS_jj, .-_Z15laplacianFilterPhS_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15laplacianFilterPhS_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15laplacianFilterPhS_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void laplacianFilter(unsigned char *srcImage, unsigned char *dstImage, unsigned int width, unsigned int height)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
float ker[3][3] = {{0, -1, 0}, {-1, 4, -1}, {0, -1, 0}};
//float kernel[3][3] = {-1, -1, -1, -1, 8, -1, -1, -1, -1};
// only threads inside image will write results
if((x>=FILTER_WIDTH/2) && (x<(width-FILTER_WIDTH/2)) && (y>=FILTER_HEIGHT/2) && (y<(height-FILTER_HEIGHT/2)))
{
// Sum of pixel values
float sum = 0;
// Loop inside the filter to average pixel values
for(int ky=-FILTER_HEIGHT/2; ky<=FILTER_HEIGHT/2; ky++) {
for(int kx=-FILTER_WIDTH/2; kx<=FILTER_WIDTH/2; kx++) {
float fl = srcImage[((y+ky)*width + (x+kx))];
sum += fl*ker[ky+FILTER_HEIGHT/2][kx+FILTER_WIDTH/2];
}
}
dstImage[(y*width+x)] = sum;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void laplacianFilter(unsigned char *srcImage, unsigned char *dstImage, unsigned int width, unsigned int height)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
float ker[3][3] = {{0, -1, 0}, {-1, 4, -1}, {0, -1, 0}};
//float kernel[3][3] = {-1, -1, -1, -1, 8, -1, -1, -1, -1};
// only threads inside image will write results
if((x>=FILTER_WIDTH/2) && (x<(width-FILTER_WIDTH/2)) && (y>=FILTER_HEIGHT/2) && (y<(height-FILTER_HEIGHT/2)))
{
// Sum of pixel values
float sum = 0;
// Loop inside the filter to average pixel values
for(int ky=-FILTER_HEIGHT/2; ky<=FILTER_HEIGHT/2; ky++) {
for(int kx=-FILTER_WIDTH/2; kx<=FILTER_WIDTH/2; kx++) {
float fl = srcImage[((y+ky)*width + (x+kx))];
sum += fl*ker[ky+FILTER_HEIGHT/2][kx+FILTER_WIDTH/2];
}
}
dstImage[(y*width+x)] = sum;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void laplacianFilter(unsigned char *srcImage, unsigned char *dstImage, unsigned int width, unsigned int height)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
float ker[3][3] = {{0, -1, 0}, {-1, 4, -1}, {0, -1, 0}};
//float kernel[3][3] = {-1, -1, -1, -1, 8, -1, -1, -1, -1};
// only threads inside image will write results
if((x>=FILTER_WIDTH/2) && (x<(width-FILTER_WIDTH/2)) && (y>=FILTER_HEIGHT/2) && (y<(height-FILTER_HEIGHT/2)))
{
// Sum of pixel values
float sum = 0;
// Loop inside the filter to average pixel values
for(int ky=-FILTER_HEIGHT/2; ky<=FILTER_HEIGHT/2; ky++) {
for(int kx=-FILTER_WIDTH/2; kx<=FILTER_WIDTH/2; kx++) {
float fl = srcImage[((y+ky)*width + (x+kx))];
sum += fl*ker[ky+FILTER_HEIGHT/2][kx+FILTER_WIDTH/2];
}
}
dstImage[(y*width+x)] = sum;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15laplacianFilterPhS_jj
.globl _Z15laplacianFilterPhS_jj
.p2align 8
.type _Z15laplacianFilterPhS_jj,@function
_Z15laplacianFilterPhS_jj:
s_load_b64 s[4:5], s[0:1], 0x4
s_load_b32 s6, s[2:3], 0x24
s_mov_b32 s8, 0
v_bfe_u32 v4, v0, 10, 10
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_dual_mov_b32 v6, s8 :: v_dual_and_b32 v1, 0x3ff, v0
v_bfe_u32 v3, v0, 20, 10
v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, s11
v_dual_mov_b32 v11, -1.0 :: v_dual_mov_b32 v10, 4.0
v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v7, s9
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s4, 16
v_mul_u32_u24_e32 v5, s5, v4
s_mul_i32 s0, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, s0, v1
s_add_u32 s0, s2, 24
s_addc_u32 s1, s3, 0
s_and_b32 s6, s6, 0xffff
s_mul_i32 s14, s14, s6
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v2, v5, v3
v_mul_lo_u32 v2, v0, 36
v_add_nc_u32_e32 v0, s14, v1
ds_store_b128 v2, v[6:9]
ds_store_b128 v2, v[6:9] offset:16
ds_store_b64 v2, v[10:11] offset:16
ds_store_b32 v2, v12 offset:32
ds_store_2addr_b32 v2, v11, v11 offset0:1 offset1:3
ds_store_b32 v2, v11 offset:28
v_cmpx_lt_i32_e32 0, v0
s_cbranch_execz .LBB0_7
s_load_b32 s0, s[0:1], 0xc
s_load_b64 s[6:7], s[2:3], 0x10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s0, 16
s_add_i32 s1, s7, -1
s_mul_i32 s15, s15, s0
s_add_i32 s0, s6, -1
v_add_nc_u32_e32 v2, s15, v4
v_cmp_gt_u32_e32 vcc_lo, s0, v0
s_mov_b32 s7, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e64 s0, s1, v2
v_cmp_lt_i32_e64 s1, 0, v2
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_7
v_mul_lo_u32 v6, v1, s5
s_load_b64 s[0:1], s[2:3], 0x0
v_add3_u32 v7, v4, s15, -1
v_mul_lo_u32 v8, v5, 36
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[4:5], null, s6, v7, v[1:2]
v_mul_lo_u32 v6, v6, s4
v_mul_u32_u24_e32 v5, 36, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v3, v4, s14, -1
v_mul_lo_u32 v1, v6, 36
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v4, v1, v8, v5
v_mov_b32_e32 v1, 0
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v5, v3
s_mov_b32 s4, 0
.LBB0_4:
s_waitcnt lgkmcnt(0)
global_load_u8 v6, v5, s[0:1]
v_add_nc_u32_e32 v7, s4, v4
v_add_nc_u32_e32 v5, 1, v5
s_add_i32 s4, s4, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s4, 12
ds_load_b32 v7, v7
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v6, v6
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v1, v7, v6
s_cbranch_scc0 .LBB0_4
v_add_nc_u32_e32 v4, 12, v4
v_add_nc_u32_e32 v3, s6, v3
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, 2
s_cbranch_scc0 .LBB0_3
s_load_b64 s[0:1], s[2:3], 0x8
v_mad_u64_u32 v[3:4], null, v2, s6, v[0:1]
v_cvt_i32_f32_e32 v0, v1
s_waitcnt lgkmcnt(0)
global_store_b8 v3, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15laplacianFilterPhS_jj
.amdhsa_group_segment_fixed_size 36864
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 1
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15laplacianFilterPhS_jj, .Lfunc_end0-_Z15laplacianFilterPhS_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 36864
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15laplacianFilterPhS_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15laplacianFilterPhS_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void laplacianFilter(unsigned char *srcImage, unsigned char *dstImage, unsigned int width, unsigned int height)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
float ker[3][3] = {{0, -1, 0}, {-1, 4, -1}, {0, -1, 0}};
//float kernel[3][3] = {-1, -1, -1, -1, 8, -1, -1, -1, -1};
// only threads inside image will write results
if((x>=FILTER_WIDTH/2) && (x<(width-FILTER_WIDTH/2)) && (y>=FILTER_HEIGHT/2) && (y<(height-FILTER_HEIGHT/2)))
{
// Sum of pixel values
float sum = 0;
// Loop inside the filter to average pixel values
for(int ky=-FILTER_HEIGHT/2; ky<=FILTER_HEIGHT/2; ky++) {
for(int kx=-FILTER_WIDTH/2; kx<=FILTER_WIDTH/2; kx++) {
float fl = srcImage[((y+ky)*width + (x+kx))];
sum += fl*ker[ky+FILTER_HEIGHT/2][kx+FILTER_WIDTH/2];
}
}
dstImage[(y*width+x)] = sum;
}
} | .text
.file "laplacianFilter.hip"
.globl _Z30__device_stub__laplacianFilterPhS_jj # -- Begin function _Z30__device_stub__laplacianFilterPhS_jj
.p2align 4, 0x90
.type _Z30__device_stub__laplacianFilterPhS_jj,@function
_Z30__device_stub__laplacianFilterPhS_jj: # @_Z30__device_stub__laplacianFilterPhS_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15laplacianFilterPhS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__laplacianFilterPhS_jj, .Lfunc_end0-_Z30__device_stub__laplacianFilterPhS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15laplacianFilterPhS_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15laplacianFilterPhS_jj,@object # @_Z15laplacianFilterPhS_jj
.section .rodata,"a",@progbits
.globl _Z15laplacianFilterPhS_jj
.p2align 3, 0x0
_Z15laplacianFilterPhS_jj:
.quad _Z30__device_stub__laplacianFilterPhS_jj
.size _Z15laplacianFilterPhS_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15laplacianFilterPhS_jj"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__laplacianFilterPhS_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15laplacianFilterPhS_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15laplacianFilterPhS_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*0030*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UIADD3 UR4, -UR5, UR6, URZ ; /* 0x0000000605047290 */
/* 0x000fc6000fffe13f */
/*0060*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0070*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fe2000bf06070 */
/*00a0*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fe2000fffe13f */
/*00b0*/ IMAD R3, R0, c[0x0][0x4], R5 ; /* 0x0000010000037a24 */
/* 0x002fe400078e0205 */
/*00c0*/ ISETP.LT.OR P0, PT, R2, 0x1, P0 ; /* 0x000000010200780c */
/* 0x000fc80000701670 */
/*00d0*/ ISETP.LT.OR P0, PT, R3, 0x1, P0 ; /* 0x000000010300780c */
/* 0x000fc80000701670 */
/*00e0*/ ISETP.GE.U32.OR P0, PT, R3, UR4, P0 ; /* 0x0000000403007c0c */
/* 0x000fda0008706470 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ IMAD R0, R3.reuse, c[0x0][0x170], R2 ; /* 0x00005c0003007a24 */
/* 0x040fe200078e0202 */
/*0110*/ IADD3 R3, R3, -0x1, RZ ; /* 0xffffffff03037810 */
/* 0x000fe20007ffe0ff */
/*0120*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0130*/ IADD3 R12, P0, R0.reuse, c[0x0][0x160], RZ ; /* 0x00005800000c7a10 */
/* 0x040fe20007f1e0ff */
/*0140*/ IMAD R3, R3, c[0x0][0x170], R2 ; /* 0x00005c0003037a24 */
/* 0x000fe200078e0202 */
/*0150*/ IADD3 R10, R0, -0x1, RZ ; /* 0xffffffff000a7810 */
/* 0x000fc60007ffe0ff */
/*0160*/ IMAD.X R13, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff0d7624 */
/* 0x000fe200000e06ff */
/*0170*/ IADD3 R6, P1, R3.reuse, c[0x0][0x160], RZ ; /* 0x0000580003067a10 */
/* 0x040fe40007f3e0ff */
/*0180*/ IADD3 R4, R3.reuse, -0x1, RZ ; /* 0xffffffff03047810 */
/* 0x040fe40007ffe0ff */
/*0190*/ IADD3 R10, P0, R10, c[0x0][0x160], RZ ; /* 0x000058000a0a7a10 */
/* 0x000fe20007f1e0ff */
/*01a0*/ IMAD.X R7, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff077624 */
/* 0x000fe200008e06ff */
/*01b0*/ IADD3 R4, P1, R4, c[0x0][0x160], RZ ; /* 0x0000580004047a10 */
/* 0x000fe20007f3e0ff */
/*01c0*/ LDG.E.U8 R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x0000a2000c1e1100 */
/*01d0*/ IADD3 R8, R3, 0x1, RZ ; /* 0x0000000103087810 */
/* 0x000fe20007ffe0ff */
/*01e0*/ IMAD.X R11, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff0b7624 */
/* 0x000fc400000e06ff */
/*01f0*/ IMAD.X R5, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff057624 */
/* 0x000fe200008e06ff */
/*0200*/ IADD3 R8, P0, R8, c[0x0][0x160], RZ ; /* 0x0000580008087a10 */
/* 0x000fe20007f1e0ff */
/*0210*/ LDG.E.U8 R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x0002e8000c1e1100 */
/*0220*/ LDG.E.U8 R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000962000c1e1100 */
/*0230*/ IADD3.X R9, RZ, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900ff097a10 */
/* 0x000fe400007fe4ff */
/*0240*/ IADD3 R14, R0.reuse, 0x1, RZ ; /* 0x00000001000e7810 */
/* 0x040fe20007ffe0ff */
/*0250*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1100 */
/*0260*/ IADD3 R17, R0, c[0x0][0x170], RZ ; /* 0x00005c0000117a10 */
/* 0x000fc40007ffe0ff */
/*0270*/ IADD3 R12, P0, R14, c[0x0][0x160], RZ ; /* 0x000058000e0c7a10 */
/* 0x001fe20007f1e0ff */
/*0280*/ LDG.E.U8 R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1100 */
/*0290*/ IADD3 R6, R17, -0x1, RZ ; /* 0xffffffff11067810 */
/* 0x002fc60007ffe0ff */
/*02a0*/ IMAD.X R13, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff0d7624 */
/* 0x000fe200000e06ff */
/*02b0*/ IADD3 R4, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x010fe40007f1e0ff */
/*02c0*/ IADD3 R14, P1, R17.reuse, c[0x0][0x160], RZ ; /* 0x00005800110e7a10 */
/* 0x040fe40007f3e0ff */
/*02d0*/ IADD3 R6, R17, 0x1, RZ ; /* 0x0000000111067810 */
/* 0x000fe20007ffe0ff */
/*02e0*/ IMAD.X R5, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff057624 */
/* 0x000fe200000e06ff */
/*02f0*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f22000c1e1100 */
/*0300*/ IMAD.X R15, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff0f7624 */
/* 0x000fe200008e06ff */
/*0310*/ IADD3 R6, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006067a10 */
/* 0x000fe40007f1e0ff */
/*0320*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000f24000c1e1100 */
/*0330*/ IADD3.X R7, RZ, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900ff077a10 */
/* 0x000fc400007fe4ff */
/*0340*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f28000c1e1100 */
/*0350*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f22000c1e1100 */
/*0360*/ I2F.U16 R3, R3 ; /* 0x0000000300037306 */
/* 0x008ff00000101000 */
/*0370*/ I2F.U16 R16, R16 ; /* 0x0000001000107306 */
/* 0x020e300000101000 */
/*0380*/ I2F.U16 R9, R9 ; /* 0x0000000900097306 */
/* 0x004e700000101000 */
/*0390*/ I2F.U16 R11, R10 ; /* 0x0000000a000b7306 */
/* 0x000ea20000101000 */
/*03a0*/ FFMA R8, RZ, R16, RZ ; /* 0x00000010ff087223 */
/* 0x001fce00000000ff */
/*03b0*/ I2F.U16 R17, R2 ; /* 0x0000000200117306 */
/* 0x000e220000101000 */
/*03c0*/ FADD R8, R8, -R3 ; /* 0x8000000308087221 */
/* 0x000fce0000000000 */
/*03d0*/ I2F.U16 R13, R12 ; /* 0x0000000c000d7306 */
/* 0x010ee20000101000 */
/*03e0*/ FFMA R8, RZ, R9, R8 ; /* 0x00000009ff087223 */
/* 0x002fce0000000008 */
/*03f0*/ I2F.U16 R5, R4 ; /* 0x0000000400057306 */
/* 0x000e620000101000 */
/*0400*/ FADD R8, R8, -R11 ; /* 0x8000000b08087221 */
/* 0x004fce0000000000 */
/*0410*/ I2F.U16 R14, R14 ; /* 0x0000000e000e7306 */
/* 0x000ea20000101000 */
/*0420*/ FFMA R8, R17, 4, R8 ; /* 0x4080000011087823 */
/* 0x001fce0000000008 */
/*0430*/ I2F.U16 R6, R6 ; /* 0x0000000600067306 */
/* 0x000e220000101000 */
/*0440*/ FADD R8, R8, -R13 ; /* 0x8000000d08087221 */
/* 0x008fc80000000000 */
/*0450*/ FFMA R5, RZ, R5, R8 ; /* 0x00000005ff057223 */
/* 0x002fc80000000008 */
/*0460*/ FADD R5, R5, -R14 ; /* 0x8000000e05057221 */
/* 0x004fc80000000000 */
/*0470*/ FFMA R5, RZ, R6, R5 ; /* 0x00000006ff057223 */
/* 0x001fcc0000000005 */
/*0480*/ F2I.U32.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e22000020f000 */
/*0490*/ IADD3 R2, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x000fca0007f1e0ff */
/*04a0*/ IMAD.X R3, RZ, RZ, c[0x0][0x16c], P0 ; /* 0x00005b00ff037624 */
/* 0x000fca00000e06ff */
/*04b0*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101104 */
/*04c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04d0*/ BRA 0x4d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15laplacianFilterPhS_jj
.globl _Z15laplacianFilterPhS_jj
.p2align 8
.type _Z15laplacianFilterPhS_jj,@function
_Z15laplacianFilterPhS_jj:
s_load_b64 s[4:5], s[0:1], 0x4
s_load_b32 s6, s[2:3], 0x24
s_mov_b32 s8, 0
v_bfe_u32 v4, v0, 10, 10
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_dual_mov_b32 v6, s8 :: v_dual_and_b32 v1, 0x3ff, v0
v_bfe_u32 v3, v0, 20, 10
v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, s11
v_dual_mov_b32 v11, -1.0 :: v_dual_mov_b32 v10, 4.0
v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v7, s9
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s4, 16
v_mul_u32_u24_e32 v5, s5, v4
s_mul_i32 s0, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, s0, v1
s_add_u32 s0, s2, 24
s_addc_u32 s1, s3, 0
s_and_b32 s6, s6, 0xffff
s_mul_i32 s14, s14, s6
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v2, v5, v3
v_mul_lo_u32 v2, v0, 36
v_add_nc_u32_e32 v0, s14, v1
ds_store_b128 v2, v[6:9]
ds_store_b128 v2, v[6:9] offset:16
ds_store_b64 v2, v[10:11] offset:16
ds_store_b32 v2, v12 offset:32
ds_store_2addr_b32 v2, v11, v11 offset0:1 offset1:3
ds_store_b32 v2, v11 offset:28
v_cmpx_lt_i32_e32 0, v0
s_cbranch_execz .LBB0_7
s_load_b32 s0, s[0:1], 0xc
s_load_b64 s[6:7], s[2:3], 0x10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s0, 16
s_add_i32 s1, s7, -1
s_mul_i32 s15, s15, s0
s_add_i32 s0, s6, -1
v_add_nc_u32_e32 v2, s15, v4
v_cmp_gt_u32_e32 vcc_lo, s0, v0
s_mov_b32 s7, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e64 s0, s1, v2
v_cmp_lt_i32_e64 s1, 0, v2
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_7
v_mul_lo_u32 v6, v1, s5
s_load_b64 s[0:1], s[2:3], 0x0
v_add3_u32 v7, v4, s15, -1
v_mul_lo_u32 v8, v5, 36
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[4:5], null, s6, v7, v[1:2]
v_mul_lo_u32 v6, v6, s4
v_mul_u32_u24_e32 v5, 36, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v3, v4, s14, -1
v_mul_lo_u32 v1, v6, 36
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v4, v1, v8, v5
v_mov_b32_e32 v1, 0
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v5, v3
s_mov_b32 s4, 0
.LBB0_4:
s_waitcnt lgkmcnt(0)
global_load_u8 v6, v5, s[0:1]
v_add_nc_u32_e32 v7, s4, v4
v_add_nc_u32_e32 v5, 1, v5
s_add_i32 s4, s4, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s4, 12
ds_load_b32 v7, v7
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v6, v6
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v1, v7, v6
s_cbranch_scc0 .LBB0_4
v_add_nc_u32_e32 v4, 12, v4
v_add_nc_u32_e32 v3, s6, v3
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, 2
s_cbranch_scc0 .LBB0_3
s_load_b64 s[0:1], s[2:3], 0x8
v_mad_u64_u32 v[3:4], null, v2, s6, v[0:1]
v_cvt_i32_f32_e32 v0, v1
s_waitcnt lgkmcnt(0)
global_store_b8 v3, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15laplacianFilterPhS_jj
.amdhsa_group_segment_fixed_size 36864
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 1
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15laplacianFilterPhS_jj, .Lfunc_end0-_Z15laplacianFilterPhS_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 36864
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15laplacianFilterPhS_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15laplacianFilterPhS_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000286fc_00000000-6_laplacianFilter.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15laplacianFilterPhS_jjPhS_jj
.type _Z39__device_stub__Z15laplacianFilterPhS_jjPhS_jj, @function
_Z39__device_stub__Z15laplacianFilterPhS_jjPhS_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15laplacianFilterPhS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z15laplacianFilterPhS_jjPhS_jj, .-_Z39__device_stub__Z15laplacianFilterPhS_jjPhS_jj
.globl _Z15laplacianFilterPhS_jj
.type _Z15laplacianFilterPhS_jj, @function
_Z15laplacianFilterPhS_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15laplacianFilterPhS_jjPhS_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15laplacianFilterPhS_jj, .-_Z15laplacianFilterPhS_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15laplacianFilterPhS_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15laplacianFilterPhS_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "laplacianFilter.hip"
.globl _Z30__device_stub__laplacianFilterPhS_jj # -- Begin function _Z30__device_stub__laplacianFilterPhS_jj
.p2align 4, 0x90
.type _Z30__device_stub__laplacianFilterPhS_jj,@function
_Z30__device_stub__laplacianFilterPhS_jj: # @_Z30__device_stub__laplacianFilterPhS_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15laplacianFilterPhS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__laplacianFilterPhS_jj, .Lfunc_end0-_Z30__device_stub__laplacianFilterPhS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15laplacianFilterPhS_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15laplacianFilterPhS_jj,@object # @_Z15laplacianFilterPhS_jj
.section .rodata,"a",@progbits
.globl _Z15laplacianFilterPhS_jj
.p2align 3, 0x0
_Z15laplacianFilterPhS_jj:
.quad _Z30__device_stub__laplacianFilterPhS_jj
.size _Z15laplacianFilterPhS_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15laplacianFilterPhS_jj"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__laplacianFilterPhS_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15laplacianFilterPhS_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#define ARRAY_SIZE 16
__global__ void print_index_and_data(int * data) {
int tid = threadIdx.x;
int block_offeset = blockIdx.x * blockDim.x;
int row_offset = blockDim.x * gridDim.x * blockIdx.y;
int gid = tid + block_offeset + row_offset;
// printf("threadIdx.x: %d, offeset: %d, gid: %d, blockIdx.x: %d, blockDim.x: %d, gridDim.x: %d, data: %d\n", tid, gid, offeset, blockIdx.x, blockDim.x, gridDim.x, data[gid]);
//printf("threadIdx.x: %d, gid: %d, blockIdx.x: %d, blockIdx.y: %d, blockDim.x: %d, blockDim.y: %d, gridDim.x: %d, data: %d\n", tid, gid, blockIdx.x, blockIdx.y, blockDim.x, blockDim.y, gridDim.x, data[gid]);
printf("%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t%d\n", tid, gid, blockIdx.x, blockIdx.y, blockDim.x, blockDim.y, gridDim.x, data[gid]);
}
int main() {
// int nx = 16;
// int ny = 16;
int array_size_bytes = sizeof(int) * ARRAY_SIZE;
// int h_data[ARRAY_SIZE] = {23, 9, 7, 14, 27, 4, 3, 11, 10, 13, 61, 42, 50, 67, 83, 22};
int h_data[ARRAY_SIZE];
for(int i=0; i<ARRAY_SIZE; i++) {
h_data[i] =i;
printf("%d ", h_data[i]);
}
printf("\n\n");
dim3 block(4);
dim3 grid(2, 2);
int * d_data;
cudaMalloc((void**)&d_data, array_size_bytes);
cudaMemcpy(d_data, h_data, array_size_bytes, cudaMemcpyHostToDevice);
printf("threadIdx.x\tgid\tblockIdx.x\tblockIdx.y\tblockDim.x\tblockDim.y\tgridDim.x\tdata\n");
print_index_and_data<<<grid, block>>>(d_data);
// print_index_and_data<<<4, 4>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z20print_index_and_dataPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R14, SR_CTAID.X ; /* 0x00000000000e7919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x20, RZ ; /* 0xffffffe001017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R15, SR_CTAID.Y ; /* 0x00000000000f7919 */
/* 0x000e280000002600 */
/*0060*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R13, R15, c[0x0][0xc], R14 ; /* 0x000003000f0d7a24 */
/* 0x001fc800078e020e */
/*0080*/ IMAD R13, R13, c[0x0][0x0], R12 ; /* 0x000000000d0d7a24 */
/* 0x002fc800078e020c */
/*0090*/ IMAD.WIDE R2, R13, R2, c[0x0][0x160] ; /* 0x000058000d027625 */
/* 0x000fca00078e0202 */
/*00a0*/ LDG.E R19, [R2.64] ; /* 0x0000000402137981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff107624 */
/* 0x000fe200078e00ff */
/*00c0*/ MOV R18, c[0x0][0xc] ; /* 0x0000030000127a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff117624 */
/* 0x000fe200078e00ff */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*00f0*/ STL.128 [R1], R12 ; /* 0x0000000c01007387 */
/* 0x0001e20000100c00 */
/*0100*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0120*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000620000000a00 */
/*0130*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0140*/ IADD3.X R7, RZ, c[0x0][0x24], RZ, P0, !PT ; /* 0x00000900ff077a10 */
/* 0x000fe200007fe4ff */
/*0150*/ STL.128 [R1+0x10], R16 ; /* 0x0000101001007387 */
/* 0x0041ea0000100c00 */
/*0160*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x002fc60000000000 */
/*0170*/ MOV R11, 0x1e0 ; /* 0x000001e0000b7802 */
/* 0x000fe40000000f00 */
/*0180*/ MOV R20, 0x160 ; /* 0x0000016000147802 */
/* 0x000fc40000000f00 */
/*0190*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe40000000f00 */
/*01b0*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*01c0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*01d0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#define ARRAY_SIZE 16
__global__ void print_index_and_data(int * data) {
int tid = threadIdx.x;
int block_offeset = blockIdx.x * blockDim.x;
int row_offset = blockDim.x * gridDim.x * blockIdx.y;
int gid = tid + block_offeset + row_offset;
// printf("threadIdx.x: %d, offeset: %d, gid: %d, blockIdx.x: %d, blockDim.x: %d, gridDim.x: %d, data: %d\n", tid, gid, offeset, blockIdx.x, blockDim.x, gridDim.x, data[gid]);
//printf("threadIdx.x: %d, gid: %d, blockIdx.x: %d, blockIdx.y: %d, blockDim.x: %d, blockDim.y: %d, gridDim.x: %d, data: %d\n", tid, gid, blockIdx.x, blockIdx.y, blockDim.x, blockDim.y, gridDim.x, data[gid]);
printf("%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t%d\n", tid, gid, blockIdx.x, blockIdx.y, blockDim.x, blockDim.y, gridDim.x, data[gid]);
}
int main() {
// int nx = 16;
// int ny = 16;
int array_size_bytes = sizeof(int) * ARRAY_SIZE;
// int h_data[ARRAY_SIZE] = {23, 9, 7, 14, 27, 4, 3, 11, 10, 13, 61, 42, 50, 67, 83, 22};
int h_data[ARRAY_SIZE];
for(int i=0; i<ARRAY_SIZE; i++) {
h_data[i] =i;
printf("%d ", h_data[i]);
}
printf("\n\n");
dim3 block(4);
dim3 grid(2, 2);
int * d_data;
cudaMalloc((void**)&d_data, array_size_bytes);
cudaMemcpy(d_data, h_data, array_size_bytes, cudaMemcpyHostToDevice);
printf("threadIdx.x\tgid\tblockIdx.x\tblockIdx.y\tblockDim.x\tblockDim.y\tgridDim.x\tdata\n");
print_index_and_data<<<grid, block>>>(d_data);
// print_index_and_data<<<4, 4>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | .file "tmpxft_001854f8_00000000-6_unique_2d_grid.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z20print_index_and_dataPiPi
.type _Z40__device_stub__Z20print_index_and_dataPiPi, @function
_Z40__device_stub__Z20print_index_and_dataPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20print_index_and_dataPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z40__device_stub__Z20print_index_and_dataPiPi, .-_Z40__device_stub__Z20print_index_and_dataPiPi
.globl _Z20print_index_and_dataPi
.type _Z20print_index_and_dataPi, @function
_Z20print_index_and_dataPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z20print_index_and_dataPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z20print_index_and_dataPi, .-_Z20print_index_and_dataPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "threadIdx.x\tgid\tblockIdx.x\tblockIdx.y\tblockDim.x\tblockDim.y\tgridDim.x\tdata\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $120, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L12:
movl %ebx, %edx
movl %ebx, 32(%rsp,%rbx,4)
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $16, %rbx
jne .L12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $2, 20(%rsp)
movl $2, 24(%rsp)
movl $1, 28(%rsp)
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq (%rsp), %rdi
call _Z40__device_stub__Z20print_index_and_dataPiPi
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z20print_index_and_dataPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z20print_index_and_dataPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#define ARRAY_SIZE 16
__global__ void print_index_and_data(int * data) {
int tid = threadIdx.x;
int block_offeset = blockIdx.x * blockDim.x;
int row_offset = blockDim.x * gridDim.x * blockIdx.y;
int gid = tid + block_offeset + row_offset;
// printf("threadIdx.x: %d, offeset: %d, gid: %d, blockIdx.x: %d, blockDim.x: %d, gridDim.x: %d, data: %d\n", tid, gid, offeset, blockIdx.x, blockDim.x, gridDim.x, data[gid]);
//printf("threadIdx.x: %d, gid: %d, blockIdx.x: %d, blockIdx.y: %d, blockDim.x: %d, blockDim.y: %d, gridDim.x: %d, data: %d\n", tid, gid, blockIdx.x, blockIdx.y, blockDim.x, blockDim.y, gridDim.x, data[gid]);
printf("%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t%d\n", tid, gid, blockIdx.x, blockIdx.y, blockDim.x, blockDim.y, gridDim.x, data[gid]);
}
int main() {
// int nx = 16;
// int ny = 16;
int array_size_bytes = sizeof(int) * ARRAY_SIZE;
// int h_data[ARRAY_SIZE] = {23, 9, 7, 14, 27, 4, 3, 11, 10, 13, 61, 42, 50, 67, 83, 22};
int h_data[ARRAY_SIZE];
for(int i=0; i<ARRAY_SIZE; i++) {
h_data[i] =i;
printf("%d ", h_data[i]);
}
printf("\n\n");
dim3 block(4);
dim3 grid(2, 2);
int * d_data;
cudaMalloc((void**)&d_data, array_size_bytes);
cudaMemcpy(d_data, h_data, array_size_bytes, cudaMemcpyHostToDevice);
printf("threadIdx.x\tgid\tblockIdx.x\tblockIdx.y\tblockDim.x\tblockDim.y\tgridDim.x\tdata\n");
print_index_and_data<<<grid, block>>>(d_data);
// print_index_and_data<<<4, 4>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#define ARRAY_SIZE 16
__global__ void print_index_and_data(int * data) {
int tid = threadIdx.x;
int block_offeset = blockIdx.x * blockDim.x;
int row_offset = blockDim.x * gridDim.x * blockIdx.y;
int gid = tid + block_offeset + row_offset;
// printf("threadIdx.x: %d, offeset: %d, gid: %d, blockIdx.x: %d, blockDim.x: %d, gridDim.x: %d, data: %d\n", tid, gid, offeset, blockIdx.x, blockDim.x, gridDim.x, data[gid]);
//printf("threadIdx.x: %d, gid: %d, blockIdx.x: %d, blockIdx.y: %d, blockDim.x: %d, blockDim.y: %d, gridDim.x: %d, data: %d\n", tid, gid, blockIdx.x, blockIdx.y, blockDim.x, blockDim.y, gridDim.x, data[gid]);
printf("%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t%d\n", tid, gid, blockIdx.x, blockIdx.y, blockDim.x, blockDim.y, gridDim.x, data[gid]);
}
int main() {
// int nx = 16;
// int ny = 16;
int array_size_bytes = sizeof(int) * ARRAY_SIZE;
// int h_data[ARRAY_SIZE] = {23, 9, 7, 14, 27, 4, 3, 11, 10, 13, 61, 42, 50, 67, 83, 22};
int h_data[ARRAY_SIZE];
for(int i=0; i<ARRAY_SIZE; i++) {
h_data[i] =i;
printf("%d ", h_data[i]);
}
printf("\n\n");
dim3 block(4);
dim3 grid(2, 2);
int * d_data;
hipMalloc((void**)&d_data, array_size_bytes);
hipMemcpy(d_data, h_data, array_size_bytes, hipMemcpyHostToDevice);
printf("threadIdx.x\tgid\tblockIdx.x\tblockIdx.y\tblockDim.x\tblockDim.y\tgridDim.x\tdata\n");
print_index_and_data<<<grid, block>>>(d_data);
// print_index_and_data<<<4, 4>>>(d_data);
hipDeviceSynchronize();
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#define ARRAY_SIZE 16
__global__ void print_index_and_data(int * data) {
int tid = threadIdx.x;
int block_offeset = blockIdx.x * blockDim.x;
int row_offset = blockDim.x * gridDim.x * blockIdx.y;
int gid = tid + block_offeset + row_offset;
// printf("threadIdx.x: %d, offeset: %d, gid: %d, blockIdx.x: %d, blockDim.x: %d, gridDim.x: %d, data: %d\n", tid, gid, offeset, blockIdx.x, blockDim.x, gridDim.x, data[gid]);
//printf("threadIdx.x: %d, gid: %d, blockIdx.x: %d, blockIdx.y: %d, blockDim.x: %d, blockDim.y: %d, gridDim.x: %d, data: %d\n", tid, gid, blockIdx.x, blockIdx.y, blockDim.x, blockDim.y, gridDim.x, data[gid]);
printf("%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t%d\n", tid, gid, blockIdx.x, blockIdx.y, blockDim.x, blockDim.y, gridDim.x, data[gid]);
}
int main() {
// int nx = 16;
// int ny = 16;
int array_size_bytes = sizeof(int) * ARRAY_SIZE;
// int h_data[ARRAY_SIZE] = {23, 9, 7, 14, 27, 4, 3, 11, 10, 13, 61, 42, 50, 67, 83, 22};
int h_data[ARRAY_SIZE];
for(int i=0; i<ARRAY_SIZE; i++) {
h_data[i] =i;
printf("%d ", h_data[i]);
}
printf("\n\n");
dim3 block(4);
dim3 grid(2, 2);
int * d_data;
hipMalloc((void**)&d_data, array_size_bytes);
hipMemcpy(d_data, h_data, array_size_bytes, hipMemcpyHostToDevice);
printf("threadIdx.x\tgid\tblockIdx.x\tblockIdx.y\tblockDim.x\tblockDim.y\tgridDim.x\tdata\n");
print_index_and_data<<<grid, block>>>(d_data);
// print_index_and_data<<<4, 4>>>(d_data);
hipDeviceSynchronize();
hipDeviceReset();
return 0;
} | .text
.file "unique_2d_grid.hip"
.globl _Z35__device_stub__print_index_and_dataPi # -- Begin function _Z35__device_stub__print_index_and_dataPi
.p2align 4, 0x90
.type _Z35__device_stub__print_index_and_dataPi,@function
_Z35__device_stub__print_index_and_dataPi: # @_Z35__device_stub__print_index_and_dataPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z20print_index_and_dataPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z35__device_stub__print_index_and_dataPi, .Lfunc_end0-_Z35__device_stub__print_index_and_dataPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ebx, 80(%rsp,%rbx,4)
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB1_1
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
movabsq $8589934594, %rdi # imm = 0x200000002
movabsq $4294967300, %rdx # imm = 0x100000004
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z20print_index_and_dataPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20print_index_and_dataPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20print_index_and_dataPi,@object # @_Z20print_index_and_dataPi
.section .rodata,"a",@progbits
.globl _Z20print_index_and_dataPi
.p2align 3, 0x0
_Z20print_index_and_dataPi:
.quad _Z35__device_stub__print_index_and_dataPi
.size _Z20print_index_and_dataPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20print_index_and_dataPi"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n"
.size .Lstr, 2
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "threadIdx.x\tgid\tblockIdx.x\tblockIdx.y\tblockDim.x\tblockDim.y\tgridDim.x\tdata"
.size .Lstr.1, 75
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__print_index_and_dataPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20print_index_and_dataPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001854f8_00000000-6_unique_2d_grid.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z20print_index_and_dataPiPi
.type _Z40__device_stub__Z20print_index_and_dataPiPi, @function
_Z40__device_stub__Z20print_index_and_dataPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20print_index_and_dataPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z40__device_stub__Z20print_index_and_dataPiPi, .-_Z40__device_stub__Z20print_index_and_dataPiPi
.globl _Z20print_index_and_dataPi
.type _Z20print_index_and_dataPi, @function
_Z20print_index_and_dataPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z20print_index_and_dataPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z20print_index_and_dataPi, .-_Z20print_index_and_dataPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "threadIdx.x\tgid\tblockIdx.x\tblockIdx.y\tblockDim.x\tblockDim.y\tgridDim.x\tdata\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $120, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L12:
movl %ebx, %edx
movl %ebx, 32(%rsp,%rbx,4)
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $16, %rbx
jne .L12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $2, 20(%rsp)
movl $2, 24(%rsp)
movl $1, 28(%rsp)
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq (%rsp), %rdi
call _Z40__device_stub__Z20print_index_and_dataPiPi
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z20print_index_and_dataPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z20print_index_and_dataPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "unique_2d_grid.hip"
.globl _Z35__device_stub__print_index_and_dataPi # -- Begin function _Z35__device_stub__print_index_and_dataPi
.p2align 4, 0x90
.type _Z35__device_stub__print_index_and_dataPi,@function
_Z35__device_stub__print_index_and_dataPi: # @_Z35__device_stub__print_index_and_dataPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z20print_index_and_dataPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z35__device_stub__print_index_and_dataPi, .Lfunc_end0-_Z35__device_stub__print_index_and_dataPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ebx, 80(%rsp,%rbx,4)
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB1_1
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
movabsq $8589934594, %rdi # imm = 0x200000002
movabsq $4294967300, %rdx # imm = 0x100000004
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z20print_index_and_dataPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20print_index_and_dataPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20print_index_and_dataPi,@object # @_Z20print_index_and_dataPi
.section .rodata,"a",@progbits
.globl _Z20print_index_and_dataPi
.p2align 3, 0x0
_Z20print_index_and_dataPi:
.quad _Z35__device_stub__print_index_and_dataPi
.size _Z20print_index_and_dataPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20print_index_and_dataPi"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n"
.size .Lstr, 2
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "threadIdx.x\tgid\tblockIdx.x\tblockIdx.y\tblockDim.x\tblockDim.y\tgridDim.x\tdata"
.size .Lstr.1, 75
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__print_index_and_dataPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20print_index_and_dataPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cmath>
__global__ void mylog10(double* value)
{
value[threadIdx.x] = std::log10(value[threadIdx.x]);
} | code for sm_80
Function : _Z7mylog10Pd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0050*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1b00 */
/*0060*/ BSSY B0, 0x430 ; /* 0x000003c000007945 */
/* 0x000fe20003800000 */
/*0070*/ ISETP.GT.AND P0, PT, R5, 0xfffff, PT ; /* 0x000fffff0500780c */
/* 0x004fe20003f04270 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*0090*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fd400078e0005 */
/*00a0*/ @!P0 DMUL R6, R6, 1.80143985094819840000e+16 ; /* 0x4350000006068828 */
/* 0x000e140000000000 */
/*00b0*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff058224 */
/* 0x001fe400078e0007 */
/*00c0*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff048224 */
/* 0x000fc600078e0006 */
/*00d0*/ IADD3 R0, R5, -0x1, RZ ; /* 0xffffffff05007810 */
/* 0x000fc80007ffe0ff */
/*00e0*/ ISETP.GE.U32.AND P1, PT, R0, 0x7fefffff, PT ; /* 0x7fefffff0000780c */
/* 0x000fe20003f26070 */
/*00f0*/ IMAD.MOV.U32 R0, RZ, RZ, -0x3ff ; /* 0xfffffc01ff007424 */
/* 0x000fe200078e00ff */
/*0100*/ @!P0 MOV R0, 0xfffffbcb ; /* 0xfffffbcb00008802 */
/* 0x000fd60000000f00 */
/*0110*/ @P1 MOV R8, 0x0 ; /* 0x0000000000081802 */
/* 0x000fe20000000f00 */
/*0120*/ @P1 IMAD.MOV.U32 R9, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff091424 */
/* 0x000fe200078e00ff */
/*0130*/ @P1 FSETP.NEU.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700120b */
/* 0x000fca0003f4d000 */
/*0140*/ @P1 DFMA R8, R6, R8, +INF ; /* 0x7ff000000608142b */
/* 0x000e140000000008 */
/*0150*/ @P1 FSEL R14, R8, RZ, P2 ; /* 0x000000ff080e1208 */
/* 0x001fe40001000000 */
/*0160*/ @P1 FSEL R15, R9, -QNAN , P2 ; /* 0xfff00000090f1808 */
/* 0x000fe20001000000 */
/*0170*/ @P1 BRA 0x420 ; /* 0x000002a000001947 */
/* 0x000fea0003800000 */
/*0180*/ LOP3.LUT R6, R5.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff05067812 */
/* 0x040fe200078ec0ff */
/*0190*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*01a0*/ MOV R16, 0x3ae80f1e ; /* 0x3ae80f1e00107802 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x3eb1380b ; /* 0x3eb1380bff117424 */
/* 0x000fe200078e00ff */
/*01c0*/ LOP3.LUT R7, R6, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000006077812 */
/* 0x000fe200078efcff */
/*01d0*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0004 */
/*01e0*/ LEA.HI R5, R5, R0, RZ, 0xc ; /* 0x0000000005057211 */
/* 0x000fe400078f60ff */
/*01f0*/ ISETP.GE.AND P0, PT, R7, 0x3ff6a09f, PT ; /* 0x3ff6a09f0700780c */
/* 0x000fda0003f06270 */
/*0200*/ @P0 IADD3 R9, R7, -0x100000, RZ ; /* 0xfff0000007090810 */
/* 0x000fe40007ffe0ff */
/*0210*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fc60007ffe0ff */
/*0220*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff070224 */
/* 0x000fe200078e0009 */
/*0230*/ LOP3.LUT R4, R5, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000005047812 */
/* 0x000fe200078e3cff */
/*0240*/ IMAD.MOV.U32 R5, RZ, RZ, 0x43300000 ; /* 0x43300000ff057424 */
/* 0x000fc800078e00ff */
/*0250*/ DADD R14, R6, 1 ; /* 0x3ff00000060e7429 */
/* 0x000e080000000000 */
/*0260*/ DADD R6, R6, -1 ; /* 0xbff0000006067429 */
/* 0x000fe40000000000 */
/*0270*/ MUFU.RCP64H R9, R15 ; /* 0x0000000f00097308 */
/* 0x001e240000001800 */
/*0280*/ DADD R4, R4, c[0x2][0x38] ; /* 0x00800e0004047629 */
/* 0x000fc80000000000 */
/*0290*/ DFMA R10, -R14, R8, 1 ; /* 0x3ff000000e0a742b */
/* 0x001e0c0000000108 */
/*02a0*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*02b0*/ DFMA R8, R8, R10, R8 ; /* 0x0000000a0808722b */
/* 0x001e0c0000000008 */
/*02c0*/ DMUL R10, R8, R6 ; /* 0x00000006080a7228 */
/* 0x001e0c0000000000 */
/*02d0*/ DFMA R10, R8, R6, R10 ; /* 0x00000006080a722b */
/* 0x001e0c000000000a */
/*02e0*/ DMUL R12, R10, R10 ; /* 0x0000000a0a0c7228 */
/* 0x001e080000000000 */
/*02f0*/ DADD R14, R6, -R10 ; /* 0x00000000060e7229 */
/* 0x000e48000000080a */
/*0300*/ DFMA R16, R12, R16, c[0x2][0x0] ; /* 0x008000000c10762b */
/* 0x001e080000000010 */
/*0310*/ DADD R18, R14, R14 ; /* 0x000000000e127229 */
/* 0x002fc8000000000e */
/*0320*/ DFMA R16, R12, R16, c[0x2][0x8] ; /* 0x008002000c10762b */
/* 0x001e080000000010 */
/*0330*/ DFMA R14, R4, c[0x2][0x40], R10 ; /* 0x00801000040e7a2b */
/* 0x000fc8000000000a */
/*0340*/ DFMA R16, R12, R16, c[0x2][0x10] ; /* 0x008004000c10762b */
/* 0x001e080000000010 */
/*0350*/ DFMA R18, R6, -R10, R18 ; /* 0x8000000a0612722b */
/* 0x000fc80000000012 */
/*0360*/ DFMA R16, R12, R16, c[0x2][0x18] ; /* 0x008006000c10762b */
/* 0x001e080000000010 */
/*0370*/ DFMA R6, -R4, c[0x2][0x40], R14 ; /* 0x0080100004067a2b */
/* 0x000fc8000000010e */
/*0380*/ DFMA R16, R12, R16, c[0x2][0x20] ; /* 0x008008000c10762b */
/* 0x001e080000000010 */
/*0390*/ DMUL R18, R8, R18 ; /* 0x0000001208127228 */
/* 0x000fc80000000000 */
/*03a0*/ DFMA R16, R12, R16, c[0x2][0x28] ; /* 0x00800a000c10762b */
/* 0x001e080000000010 */
/*03b0*/ DADD R6, -R10, R6 ; /* 0x000000000a067229 */
/* 0x000fc80000000106 */
/*03c0*/ DFMA R16, R12, R16, c[0x2][0x30] ; /* 0x00800c000c10762b */
/* 0x001e0c0000000010 */
/*03d0*/ DMUL R16, R12, R16 ; /* 0x000000100c107228 */
/* 0x001e0c0000000000 */
/*03e0*/ DFMA R16, R10, R16, R18 ; /* 0x000000100a10722b */
/* 0x001e0c0000000012 */
/*03f0*/ DADD R6, R16, -R6 ; /* 0x0000000010067229 */
/* 0x001e0c0000000806 */
/*0400*/ DFMA R6, R4, c[0x2][0x48], R6 ; /* 0x0080120004067a2b */
/* 0x001e0c0000000006 */
/*0410*/ DADD R14, R14, R6 ; /* 0x000000000e0e7229 */
/* 0x00104c0000000006 */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ DMUL R4, R14, c[0x2][0x50] ; /* 0x008014000e047a28 */
/* 0x002e4c0000000000 */
/*0440*/ DFMA R4, R14, c[0x2][0x58], R4 ; /* 0x008016000e047a2b */
/* 0x002e4e0000000004 */
/*0450*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x002fe2000c101b04 */
/*0460*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0470*/ BRA 0x470; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cmath>
__global__ void mylog10(double* value)
{
value[threadIdx.x] = std::log10(value[threadIdx.x]);
} | .file "tmpxft_0002a769_00000000-6_log10.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z7mylog10PdPd
.type _Z26__device_stub__Z7mylog10PdPd, @function
_Z26__device_stub__Z7mylog10PdPd:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7mylog10Pd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z7mylog10PdPd, .-_Z26__device_stub__Z7mylog10PdPd
.globl _Z7mylog10Pd
.type _Z7mylog10Pd, @function
_Z7mylog10Pd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7mylog10PdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7mylog10Pd, .-_Z7mylog10Pd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7mylog10Pd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mylog10Pd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cmath>
__global__ void mylog10(double* value)
{
value[threadIdx.x] = std::log10(value[threadIdx.x]);
} | #include <hip/hip_runtime.h>
#include <cmath>
__global__ void mylog10(double* value)
{
value[threadIdx.x] = std::log10(value[threadIdx.x]);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cmath>
__global__ void mylog10(double* value)
{
value[threadIdx.x] = std::log10(value[threadIdx.x]);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mylog10Pd
.globl _Z7mylog10Pd
.p2align 8
.type _Z7mylog10Pd,@function
_Z7mylog10Pd:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v20, 3, v0
s_mov_b32 s3, 0x3fe55555
s_mov_b32 s2, 0x55555555
s_mov_b32 s5, 0x3fc38538
s_mov_b32 s4, 0x6b47b09a
s_mov_b32 s7, 0x3fc3ab76
s_mov_b32 s6, 0xbf559e2b
s_waitcnt lgkmcnt(0)
global_load_b64 v[0:1], v20, s[0:1]
s_waitcnt vmcnt(0)
v_frexp_mant_f64_e32 v[2:3], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[2:3]
s_mov_b32 s2, 0x55555780
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
v_ldexp_f64 v[2:3], v[2:3], v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[2:3], 1.0
v_add_f64 v[10:11], v[2:3], -1.0
v_rcp_f64_e32 v[6:7], v[4:5]
v_add_f64 v[12:13], v[4:5], -1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], -v[12:13]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[8:9], v[6:7], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[8:9], v[6:7], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[8:9], v[10:11], v[6:7]
v_mul_f64 v[14:15], v[4:5], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[8:9], v[4:5], -v[14:15]
v_fma_f64 v[2:3], v[8:9], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[14:15], v[2:3]
v_add_f64 v[12:13], v[10:11], -v[4:5]
v_add_f64 v[14:15], v[4:5], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[10:11], -v[12:13]
v_add_f64 v[2:3], v[14:15], -v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[10:11], -v[4:5]
v_add_f64 v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[12:13], v[2:3]
v_mul_f64 v[2:3], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[8:9], v[2:3]
v_mul_f64 v[6:7], v[4:5], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[6:7], s[6:7], s[4:5]
s_mov_b32 s5, 0x3fc7474d
s_mov_b32 s4, 0xd7f4df2e
v_mul_f64 v[12:13], v[4:5], v[6:7]
v_fma_f64 v[10:11], v[6:7], v[10:11], s[4:5]
s_mov_b32 s5, 0x3fcc71c0
s_mov_b32 s4, 0x16291751
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[10:11], v[6:7], v[10:11], s[4:5]
s_mov_b32 s5, 0x3fd24924
s_mov_b32 s4, 0x9b27acf1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[10:11], v[6:7], v[10:11], s[4:5]
s_mov_b32 s5, 0x3fd99999
s_mov_b32 s4, 0x998ef7b6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[10:11], v[6:7], v[10:11], s[4:5]
s_mov_b32 s5, 0x3fd34413
s_mov_b32 s4, 0x509f79ff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_fma_f64 v[6:7], v[6:7], v[10:11], s[2:3]
v_ldexp_f64 v[10:11], v[4:5], 1
v_add_f64 v[4:5], v[4:5], -v[8:9]
s_mov_b32 s3, 0x3fdbcb7b
s_mov_b32 s2, 0x1526e50e
v_mul_f64 v[6:7], v[12:13], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[2:3], -v[4:5]
v_add_f64 v[8:9], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f64 v[2:3], v[2:3], 1
v_add_f64 v[4:5], v[8:9], -v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[6:7], -v[4:5]
v_frexp_exp_i32_f64_e32 v6, v[0:1]
v_add_f64 v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x204
v_cvt_f64_i32_e32 v[6:7], v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[8:9], v[2:3]
v_mul_f64 v[12:13], v[6:7], s[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[8:9], v[4:5], -v[8:9]
v_mul_f64 v[10:11], v[4:5], s[2:3]
v_fma_f64 v[14:15], v[6:7], s[4:5], -v[12:13]
s_mov_b32 s5, 0x3c695355
s_mov_b32 s4, 0xbaaafad3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[2:3], v[2:3], -v[8:9]
v_fma_f64 v[8:9], v[4:5], s[2:3], -v[10:11]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[2:3], v[2:3], s[2:3], v[8:9]
s_mov_b32 s3, 0xbc49dc1d
s_mov_b32 s2, 0xa994fd21
s_delay_alu instid0(VALU_DEP_4) | instid1(SALU_CYCLE_1)
v_fma_f64 v[6:7], v[6:7], s[2:3], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[2:3], v[4:5], s[4:5], v[2:3]
v_add_f64 v[4:5], v[12:13], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[10:11], v[2:3]
v_add_f64 v[12:13], v[4:5], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[4:5], v[8:9]
v_add_f64 v[10:11], v[8:9], -v[10:11]
v_add_f64 v[6:7], v[6:7], -v[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[16:17], v[14:15], -v[4:5]
v_add_f64 v[2:3], v[2:3], -v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[18:19], v[14:15], -v[16:17]
v_add_f64 v[8:9], v[8:9], -v[16:17]
v_add_f64 v[10:11], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], -v[18:19]
v_add_f64 v[4:5], v[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[10:11], -v[6:7]
v_add_f64 v[4:5], v[10:11], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[10:11], -v[8:9]
v_add_f64 v[2:3], v[2:3], -v[8:9]
v_add_f64 v[12:13], v[14:15], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], -v[10:11]
v_add_f64 v[8:9], v[12:13], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[2:3], v[6:7]
v_add_f64 v[4:5], v[4:5], -v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[4:5]
v_add_f64 v[2:3], v[12:13], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v3, v3, v1 :: v_dual_cndmask_b32 v2, v2, v0
v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
v_cndmask_b32_e32 v3, 0x7ff80000, v3, vcc_lo
v_cmp_nge_f64_e32 vcc_lo, 0, v[0:1]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
v_cmp_neq_f64_e32 vcc_lo, 0, v[0:1]
v_cndmask_b32_e32 v3, 0xfff00000, v3, vcc_lo
global_store_b64 v20, v[2:3], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mylog10Pd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7mylog10Pd, .Lfunc_end0-_Z7mylog10Pd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mylog10Pd
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z7mylog10Pd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cmath>
__global__ void mylog10(double* value)
{
value[threadIdx.x] = std::log10(value[threadIdx.x]);
} | .text
.file "log10.hip"
.globl _Z22__device_stub__mylog10Pd # -- Begin function _Z22__device_stub__mylog10Pd
.p2align 4, 0x90
.type _Z22__device_stub__mylog10Pd,@function
_Z22__device_stub__mylog10Pd: # @_Z22__device_stub__mylog10Pd
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7mylog10Pd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z22__device_stub__mylog10Pd, .Lfunc_end0-_Z22__device_stub__mylog10Pd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mylog10Pd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7mylog10Pd,@object # @_Z7mylog10Pd
.section .rodata,"a",@progbits
.globl _Z7mylog10Pd
.p2align 3, 0x0
_Z7mylog10Pd:
.quad _Z22__device_stub__mylog10Pd
.size _Z7mylog10Pd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7mylog10Pd"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__mylog10Pd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7mylog10Pd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7mylog10Pd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0050*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1b00 */
/*0060*/ BSSY B0, 0x430 ; /* 0x000003c000007945 */
/* 0x000fe20003800000 */
/*0070*/ ISETP.GT.AND P0, PT, R5, 0xfffff, PT ; /* 0x000fffff0500780c */
/* 0x004fe20003f04270 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*0090*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fd400078e0005 */
/*00a0*/ @!P0 DMUL R6, R6, 1.80143985094819840000e+16 ; /* 0x4350000006068828 */
/* 0x000e140000000000 */
/*00b0*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff058224 */
/* 0x001fe400078e0007 */
/*00c0*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff048224 */
/* 0x000fc600078e0006 */
/*00d0*/ IADD3 R0, R5, -0x1, RZ ; /* 0xffffffff05007810 */
/* 0x000fc80007ffe0ff */
/*00e0*/ ISETP.GE.U32.AND P1, PT, R0, 0x7fefffff, PT ; /* 0x7fefffff0000780c */
/* 0x000fe20003f26070 */
/*00f0*/ IMAD.MOV.U32 R0, RZ, RZ, -0x3ff ; /* 0xfffffc01ff007424 */
/* 0x000fe200078e00ff */
/*0100*/ @!P0 MOV R0, 0xfffffbcb ; /* 0xfffffbcb00008802 */
/* 0x000fd60000000f00 */
/*0110*/ @P1 MOV R8, 0x0 ; /* 0x0000000000081802 */
/* 0x000fe20000000f00 */
/*0120*/ @P1 IMAD.MOV.U32 R9, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff091424 */
/* 0x000fe200078e00ff */
/*0130*/ @P1 FSETP.NEU.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700120b */
/* 0x000fca0003f4d000 */
/*0140*/ @P1 DFMA R8, R6, R8, +INF ; /* 0x7ff000000608142b */
/* 0x000e140000000008 */
/*0150*/ @P1 FSEL R14, R8, RZ, P2 ; /* 0x000000ff080e1208 */
/* 0x001fe40001000000 */
/*0160*/ @P1 FSEL R15, R9, -QNAN , P2 ; /* 0xfff00000090f1808 */
/* 0x000fe20001000000 */
/*0170*/ @P1 BRA 0x420 ; /* 0x000002a000001947 */
/* 0x000fea0003800000 */
/*0180*/ LOP3.LUT R6, R5.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff05067812 */
/* 0x040fe200078ec0ff */
/*0190*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*01a0*/ MOV R16, 0x3ae80f1e ; /* 0x3ae80f1e00107802 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x3eb1380b ; /* 0x3eb1380bff117424 */
/* 0x000fe200078e00ff */
/*01c0*/ LOP3.LUT R7, R6, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000006077812 */
/* 0x000fe200078efcff */
/*01d0*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0004 */
/*01e0*/ LEA.HI R5, R5, R0, RZ, 0xc ; /* 0x0000000005057211 */
/* 0x000fe400078f60ff */
/*01f0*/ ISETP.GE.AND P0, PT, R7, 0x3ff6a09f, PT ; /* 0x3ff6a09f0700780c */
/* 0x000fda0003f06270 */
/*0200*/ @P0 IADD3 R9, R7, -0x100000, RZ ; /* 0xfff0000007090810 */
/* 0x000fe40007ffe0ff */
/*0210*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fc60007ffe0ff */
/*0220*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff070224 */
/* 0x000fe200078e0009 */
/*0230*/ LOP3.LUT R4, R5, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000005047812 */
/* 0x000fe200078e3cff */
/*0240*/ IMAD.MOV.U32 R5, RZ, RZ, 0x43300000 ; /* 0x43300000ff057424 */
/* 0x000fc800078e00ff */
/*0250*/ DADD R14, R6, 1 ; /* 0x3ff00000060e7429 */
/* 0x000e080000000000 */
/*0260*/ DADD R6, R6, -1 ; /* 0xbff0000006067429 */
/* 0x000fe40000000000 */
/*0270*/ MUFU.RCP64H R9, R15 ; /* 0x0000000f00097308 */
/* 0x001e240000001800 */
/*0280*/ DADD R4, R4, c[0x2][0x38] ; /* 0x00800e0004047629 */
/* 0x000fc80000000000 */
/*0290*/ DFMA R10, -R14, R8, 1 ; /* 0x3ff000000e0a742b */
/* 0x001e0c0000000108 */
/*02a0*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*02b0*/ DFMA R8, R8, R10, R8 ; /* 0x0000000a0808722b */
/* 0x001e0c0000000008 */
/*02c0*/ DMUL R10, R8, R6 ; /* 0x00000006080a7228 */
/* 0x001e0c0000000000 */
/*02d0*/ DFMA R10, R8, R6, R10 ; /* 0x00000006080a722b */
/* 0x001e0c000000000a */
/*02e0*/ DMUL R12, R10, R10 ; /* 0x0000000a0a0c7228 */
/* 0x001e080000000000 */
/*02f0*/ DADD R14, R6, -R10 ; /* 0x00000000060e7229 */
/* 0x000e48000000080a */
/*0300*/ DFMA R16, R12, R16, c[0x2][0x0] ; /* 0x008000000c10762b */
/* 0x001e080000000010 */
/*0310*/ DADD R18, R14, R14 ; /* 0x000000000e127229 */
/* 0x002fc8000000000e */
/*0320*/ DFMA R16, R12, R16, c[0x2][0x8] ; /* 0x008002000c10762b */
/* 0x001e080000000010 */
/*0330*/ DFMA R14, R4, c[0x2][0x40], R10 ; /* 0x00801000040e7a2b */
/* 0x000fc8000000000a */
/*0340*/ DFMA R16, R12, R16, c[0x2][0x10] ; /* 0x008004000c10762b */
/* 0x001e080000000010 */
/*0350*/ DFMA R18, R6, -R10, R18 ; /* 0x8000000a0612722b */
/* 0x000fc80000000012 */
/*0360*/ DFMA R16, R12, R16, c[0x2][0x18] ; /* 0x008006000c10762b */
/* 0x001e080000000010 */
/*0370*/ DFMA R6, -R4, c[0x2][0x40], R14 ; /* 0x0080100004067a2b */
/* 0x000fc8000000010e */
/*0380*/ DFMA R16, R12, R16, c[0x2][0x20] ; /* 0x008008000c10762b */
/* 0x001e080000000010 */
/*0390*/ DMUL R18, R8, R18 ; /* 0x0000001208127228 */
/* 0x000fc80000000000 */
/*03a0*/ DFMA R16, R12, R16, c[0x2][0x28] ; /* 0x00800a000c10762b */
/* 0x001e080000000010 */
/*03b0*/ DADD R6, -R10, R6 ; /* 0x000000000a067229 */
/* 0x000fc80000000106 */
/*03c0*/ DFMA R16, R12, R16, c[0x2][0x30] ; /* 0x00800c000c10762b */
/* 0x001e0c0000000010 */
/*03d0*/ DMUL R16, R12, R16 ; /* 0x000000100c107228 */
/* 0x001e0c0000000000 */
/*03e0*/ DFMA R16, R10, R16, R18 ; /* 0x000000100a10722b */
/* 0x001e0c0000000012 */
/*03f0*/ DADD R6, R16, -R6 ; /* 0x0000000010067229 */
/* 0x001e0c0000000806 */
/*0400*/ DFMA R6, R4, c[0x2][0x48], R6 ; /* 0x0080120004067a2b */
/* 0x001e0c0000000006 */
/*0410*/ DADD R14, R14, R6 ; /* 0x000000000e0e7229 */
/* 0x00104c0000000006 */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ DMUL R4, R14, c[0x2][0x50] ; /* 0x008014000e047a28 */
/* 0x002e4c0000000000 */
/*0440*/ DFMA R4, R14, c[0x2][0x58], R4 ; /* 0x008016000e047a2b */
/* 0x002e4e0000000004 */
/*0450*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x002fe2000c101b04 */
/*0460*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0470*/ BRA 0x470; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mylog10Pd
.globl _Z7mylog10Pd
.p2align 8
.type _Z7mylog10Pd,@function
_Z7mylog10Pd:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v20, 3, v0
s_mov_b32 s3, 0x3fe55555
s_mov_b32 s2, 0x55555555
s_mov_b32 s5, 0x3fc38538
s_mov_b32 s4, 0x6b47b09a
s_mov_b32 s7, 0x3fc3ab76
s_mov_b32 s6, 0xbf559e2b
s_waitcnt lgkmcnt(0)
global_load_b64 v[0:1], v20, s[0:1]
s_waitcnt vmcnt(0)
v_frexp_mant_f64_e32 v[2:3], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[2:3]
s_mov_b32 s2, 0x55555780
v_cndmask_b32_e64 v4, 0, 1, vcc_lo
v_ldexp_f64 v[2:3], v[2:3], v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[2:3], 1.0
v_add_f64 v[10:11], v[2:3], -1.0
v_rcp_f64_e32 v[6:7], v[4:5]
v_add_f64 v[12:13], v[4:5], -1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], -v[12:13]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[8:9], v[6:7], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[8:9], v[6:7], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[8:9], v[10:11], v[6:7]
v_mul_f64 v[14:15], v[4:5], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[8:9], v[4:5], -v[14:15]
v_fma_f64 v[2:3], v[8:9], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[14:15], v[2:3]
v_add_f64 v[12:13], v[10:11], -v[4:5]
v_add_f64 v[14:15], v[4:5], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[10:11], -v[12:13]
v_add_f64 v[2:3], v[14:15], -v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[10:11], -v[4:5]
v_add_f64 v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[12:13], v[2:3]
v_mul_f64 v[2:3], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[8:9], v[2:3]
v_mul_f64 v[6:7], v[4:5], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[6:7], s[6:7], s[4:5]
s_mov_b32 s5, 0x3fc7474d
s_mov_b32 s4, 0xd7f4df2e
v_mul_f64 v[12:13], v[4:5], v[6:7]
v_fma_f64 v[10:11], v[6:7], v[10:11], s[4:5]
s_mov_b32 s5, 0x3fcc71c0
s_mov_b32 s4, 0x16291751
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[10:11], v[6:7], v[10:11], s[4:5]
s_mov_b32 s5, 0x3fd24924
s_mov_b32 s4, 0x9b27acf1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[10:11], v[6:7], v[10:11], s[4:5]
s_mov_b32 s5, 0x3fd99999
s_mov_b32 s4, 0x998ef7b6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[10:11], v[6:7], v[10:11], s[4:5]
s_mov_b32 s5, 0x3fd34413
s_mov_b32 s4, 0x509f79ff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_fma_f64 v[6:7], v[6:7], v[10:11], s[2:3]
v_ldexp_f64 v[10:11], v[4:5], 1
v_add_f64 v[4:5], v[4:5], -v[8:9]
s_mov_b32 s3, 0x3fdbcb7b
s_mov_b32 s2, 0x1526e50e
v_mul_f64 v[6:7], v[12:13], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[2:3], -v[4:5]
v_add_f64 v[8:9], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f64 v[2:3], v[2:3], 1
v_add_f64 v[4:5], v[8:9], -v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[6:7], -v[4:5]
v_frexp_exp_i32_f64_e32 v6, v[0:1]
v_add_f64 v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x204
v_cvt_f64_i32_e32 v[6:7], v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[8:9], v[2:3]
v_mul_f64 v[12:13], v[6:7], s[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[8:9], v[4:5], -v[8:9]
v_mul_f64 v[10:11], v[4:5], s[2:3]
v_fma_f64 v[14:15], v[6:7], s[4:5], -v[12:13]
s_mov_b32 s5, 0x3c695355
s_mov_b32 s4, 0xbaaafad3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[2:3], v[2:3], -v[8:9]
v_fma_f64 v[8:9], v[4:5], s[2:3], -v[10:11]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[2:3], v[2:3], s[2:3], v[8:9]
s_mov_b32 s3, 0xbc49dc1d
s_mov_b32 s2, 0xa994fd21
s_delay_alu instid0(VALU_DEP_4) | instid1(SALU_CYCLE_1)
v_fma_f64 v[6:7], v[6:7], s[2:3], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[2:3], v[4:5], s[4:5], v[2:3]
v_add_f64 v[4:5], v[12:13], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[10:11], v[2:3]
v_add_f64 v[12:13], v[4:5], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[4:5], v[8:9]
v_add_f64 v[10:11], v[8:9], -v[10:11]
v_add_f64 v[6:7], v[6:7], -v[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[16:17], v[14:15], -v[4:5]
v_add_f64 v[2:3], v[2:3], -v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[18:19], v[14:15], -v[16:17]
v_add_f64 v[8:9], v[8:9], -v[16:17]
v_add_f64 v[10:11], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], -v[18:19]
v_add_f64 v[4:5], v[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[10:11], -v[6:7]
v_add_f64 v[4:5], v[10:11], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[10:11], -v[8:9]
v_add_f64 v[2:3], v[2:3], -v[8:9]
v_add_f64 v[12:13], v[14:15], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], -v[10:11]
v_add_f64 v[8:9], v[12:13], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[2:3], v[6:7]
v_add_f64 v[4:5], v[4:5], -v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[4:5]
v_add_f64 v[2:3], v[12:13], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v3, v3, v1 :: v_dual_cndmask_b32 v2, v2, v0
v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
v_cndmask_b32_e32 v3, 0x7ff80000, v3, vcc_lo
v_cmp_nge_f64_e32 vcc_lo, 0, v[0:1]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
v_cmp_neq_f64_e32 vcc_lo, 0, v[0:1]
v_cndmask_b32_e32 v3, 0xfff00000, v3, vcc_lo
global_store_b64 v20, v[2:3], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mylog10Pd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7mylog10Pd, .Lfunc_end0-_Z7mylog10Pd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mylog10Pd
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z7mylog10Pd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002a769_00000000-6_log10.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z7mylog10PdPd
.type _Z26__device_stub__Z7mylog10PdPd, @function
_Z26__device_stub__Z7mylog10PdPd:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7mylog10Pd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z7mylog10PdPd, .-_Z26__device_stub__Z7mylog10PdPd
.globl _Z7mylog10Pd
.type _Z7mylog10Pd, @function
_Z7mylog10Pd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7mylog10PdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7mylog10Pd, .-_Z7mylog10Pd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7mylog10Pd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mylog10Pd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "log10.hip"
.globl _Z22__device_stub__mylog10Pd # -- Begin function _Z22__device_stub__mylog10Pd
.p2align 4, 0x90
.type _Z22__device_stub__mylog10Pd,@function
_Z22__device_stub__mylog10Pd: # @_Z22__device_stub__mylog10Pd
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7mylog10Pd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z22__device_stub__mylog10Pd, .Lfunc_end0-_Z22__device_stub__mylog10Pd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mylog10Pd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7mylog10Pd,@object # @_Z7mylog10Pd
.section .rodata,"a",@progbits
.globl _Z7mylog10Pd
.p2align 3, 0x0
_Z7mylog10Pd:
.quad _Z22__device_stub__mylog10Pd
.size _Z7mylog10Pd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7mylog10Pd"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__mylog10Pd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7mylog10Pd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <time.h>
#include <cuda_runtime.h>
#include <cassert>
#include <cstdlib>
#include <functional>
#include <iostream>
#include <algorithm>
#include <vector>
using std::cout;
using std::generate;
using std::vector;
#define SIZE 10000
#define N 10
#define CUDA_CALL(x) do { if((x)!=cudaSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define CHECK(x) do { if((x)!=cudaSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
__global__ void computeMovingAverage(const float *dev_a, float *dev_b, int size, int n) {
int idx = blockDim.x * blockIdx.x + threadIdx.x;
if(idx < (size - n + 2)){
for(int i = 0; i< n; i++){
dev_b[idx] += dev_a[idx + i]/n;
}
}
__syncthreads();
}
void computeMovingAverageOnCPU(vector<float> &host_a, float &cpuRef, int size, int n) {
vector<float> temp_vec(size);
for(int i = 0; i < (size - n + 2); i++)
for(int j = 0; j < n; j++)
temp_vec[i] += host_a[i+j]/n;
for(int i = 0; i < (size - n + 2); i++)
cpuRef += (float)(temp_vec[i]/(size - n + 1));
}
int main(void){
// set up device
int dev = 0;
cudaDeviceProp deviceProp;
CHECK(cudaGetDeviceProperties(&deviceProp, dev));
printf("Using Device %d: %s\n", dev, deviceProp.name);
CHECK(cudaSetDevice(dev));
int n = N;
int size = SIZE;
printf("Array Size: %d Sample Size: %d\n", size, N);
size_t nBytes = size * sizeof(float);
float cpuRef = 0.0f;
float gpuRef = 0.0f;
// initialize random number
srand ((int)time(0));
// initialize vector and generate random indices between 0 and 5.
vector<float> host_a(size);
vector<float> host_b(size-n);
generate(host_a.begin(), host_a.end(), []() { return rand() % 5; });
float *dev_a, *dev_b;
cudaMalloc(&dev_a, nBytes);
cudaMalloc(&dev_b, nBytes);
cudaMemcpy(dev_a, host_a.data(), nBytes, cudaMemcpyHostToDevice);
// declare block and grid dimension.
dim3 block (1000);
dim3 grid (10);
// Timer starts
float GPUtime, CPUtime;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
computeMovingAverage <<< grid, block >>> (dev_a, dev_b, size, n);
cudaMemcpy(host_b.data(), dev_b, nBytes, cudaMemcpyDeviceToHost);
for(int x = 0; x< (size-n+2); x++){
gpuRef += (float)(host_b[x]/(size - n + 1));
}
// timer stops
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&GPUtime, start, stop);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
computeMovingAverageOnCPU(host_a, cpuRef, size, n);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&CPUtime, start, stop);
printf("Kernel: computeMovingAverage <<<gridDim: %d, blockDim: %d>>>\n", grid.x, block.x);
printf("Compute time on GPU: %3.6f ms \n", GPUtime);
printf("Compute time on CPU: %3.6f ms \n", CPUtime);
printf("Moving Average computed on CPU: %3.6f\n", cpuRef);
printf("Moving Average computed on GPU: %3.6f\n", gpuRef);
cudaFree(dev_a);
cudaFree(dev_b);
return (0);
} | code for sm_80
Function : _Z20computeMovingAveragePKfPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff087624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x890 ; /* 0x0000084000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0060*/ UIADD3 UR4, UR4, 0x2, -UR5 ; /* 0x0000000204047890 */
/* 0x000fe2000fffe805 */
/*0070*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R4, R11, c[0x0][0x0], R10 ; /* 0x000000000b047a24 */
/* 0x001fca00078e020a */
/*0090*/ ISETP.GE.OR P0, PT, R4, UR4, !P0 ; /* 0x0000000404007c0c */
/* 0x000fda000c706670 */
/*00a0*/ @P0 BRA 0x880 ; /* 0x000007d000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R2, R8.reuse, -0x1, RZ ; /* 0xffffffff08027810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ I2F R0, c[0x0][0x174] ; /* 0x00005d0000007b06 */
/* 0x000e220000201400 */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*00e0*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe200078ec0ff */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0110*/ IMAD.WIDE R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fd800078e0203 */
/*0120*/ @!P0 BRA 0x650 ; /* 0x0000052000008947 */
/* 0x000fea0003800000 */
/*0130*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x001fe40000000a00 */
/*0140*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000162000c1e1900 */
/*0150*/ LEA R6, P0, R4, c[0x0][0x160], 0x2 ; /* 0x0000580004067a11 */
/* 0x000fe200078010ff */
/*0160*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0170*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe40000011404 */
/*0180*/ IADD3 R12, -R8, c[0x0][0x174], RZ ; /* 0x00005d00080c7a10 */
/* 0x000fe40007ffe1ff */
/*0190*/ LEA.HI.X R7, R4, c[0x0][0x164], R5, 0x2, P0 ; /* 0x0000590004077a11 */
/* 0x000fc600000f1405 */
/*01a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*01b0*/ LDG.E R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ MUFU.RCP R5, R0 ; /* 0x0000000000057308 */
/* 0x000e620000001000 */
/*01d0*/ BSSY B1, 0x290 ; /* 0x000000b000017945 */
/* 0x000fe20003800000 */
/*01e0*/ FFMA R4, -R0, R5, 1 ; /* 0x3f80000000047423 */
/* 0x002fc80000000105 */
/*01f0*/ FFMA R4, R5, R4, R5 ; /* 0x0000000405047223 */
/* 0x000fe40000000005 */
/*0200*/ FCHK P0, R15, R0 ; /* 0x000000000f007302 */
/* 0x004e640000000000 */
/*0210*/ FFMA R5, R15, R4, RZ ; /* 0x000000040f057223 */
/* 0x000fc800000000ff */
/*0220*/ FFMA R14, -R0, R5, R15 ; /* 0x00000005000e7223 */
/* 0x000fc8000000010f */
/*0230*/ FFMA R4, R4, R14, R5 ; /* 0x0000000e04047223 */
/* 0x000fe20000000005 */
/*0240*/ @!P0 BRA 0x280 ; /* 0x0000003000008947 */
/* 0x003fea0003800000 */
/*0250*/ MOV R4, 0x270 ; /* 0x0000027000047802 */
/* 0x000fe40000000f00 */
/*0260*/ CALL.REL.NOINC 0x8b0 ; /* 0x0000064000007944 */
/* 0x021fea0003c00000 */
/*0270*/ IMAD.MOV.U32 R4, RZ, RZ, R19 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0013 */
/*0280*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0290*/ FADD R13, R4, R13 ; /* 0x0000000d040d7221 */
/* 0x020fe20000000000 */
/*02a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*02b0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*02c0*/ LDG.E R15, [R6.64+0x4] ; /* 0x00000404060f7981 */
/* 0x000ea2000c1e1900 */
/*02d0*/ MUFU.RCP R5, R0 ; /* 0x0000000000057308 */
/* 0x000ee20000001000 */
/*02e0*/ BSSY B1, 0x3a0 ; /* 0x000000b000017945 */
/* 0x000fe20003800000 */
/*02f0*/ FFMA R4, -R0, R5, 1 ; /* 0x3f80000000047423 */
/* 0x008fc80000000105 */
/*0300*/ FFMA R14, R5, R4, R5 ; /* 0x00000004050e7223 */
/* 0x000fe40000000005 */
/*0310*/ FCHK P0, R15, R0 ; /* 0x000000000f007302 */
/* 0x004ea40000000000 */
/*0320*/ FFMA R5, R14, R15, RZ ; /* 0x0000000f0e057223 */
/* 0x000fc800000000ff */
/*0330*/ FFMA R4, -R0, R5, R15 ; /* 0x0000000500047223 */
/* 0x000fc8000000010f */
/*0340*/ FFMA R4, R14, R4, R5 ; /* 0x000000040e047223 */
/* 0x000fe20000000005 */
/*0350*/ @!P0 BRA 0x390 ; /* 0x0000003000008947 */
/* 0x004fea0003800000 */
/*0360*/ MOV R4, 0x380 ; /* 0x0000038000047802 */
/* 0x002fe40000000f00 */
/*0370*/ CALL.REL.NOINC 0x8b0 ; /* 0x0000053000007944 */
/* 0x001fea0003c00000 */
/*0380*/ IMAD.MOV.U32 R4, RZ, RZ, R19 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0013 */
/*0390*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x002fea0003800000 */
/*03a0*/ FADD R13, R13, R4 ; /* 0x000000040d0d7221 */
/* 0x000fe20000000000 */
/*03b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*03c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*03d0*/ LDG.E R15, [R6.64+0x8] ; /* 0x00000804060f7981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ MUFU.RCP R5, R0 ; /* 0x0000000000057308 */
/* 0x000ee20000001000 */
/*03f0*/ BSSY B1, 0x4b0 ; /* 0x000000b000017945 */
/* 0x000fe20003800000 */
/*0400*/ FFMA R4, -R0, R5, 1 ; /* 0x3f80000000047423 */
/* 0x008fc80000000105 */
/*0410*/ FFMA R14, R5, R4, R5 ; /* 0x00000004050e7223 */
/* 0x000fe40000000005 */
/*0420*/ FCHK P0, R15, R0 ; /* 0x000000000f007302 */
/* 0x004ea40000000000 */
/*0430*/ FFMA R5, R14, R15, RZ ; /* 0x0000000f0e057223 */
/* 0x000fc800000000ff */
/*0440*/ FFMA R4, -R0, R5, R15 ; /* 0x0000000500047223 */
/* 0x000fc8000000010f */
/*0450*/ FFMA R4, R14, R4, R5 ; /* 0x000000040e047223 */
/* 0x000fe20000000005 */
/*0460*/ @!P0 BRA 0x4a0 ; /* 0x0000003000008947 */
/* 0x004fea0003800000 */
/*0470*/ MOV R4, 0x490 ; /* 0x0000049000047802 */
/* 0x002fe40000000f00 */
/*0480*/ CALL.REL.NOINC 0x8b0 ; /* 0x0000042000007944 */
/* 0x001fea0003c00000 */
/*0490*/ IMAD.MOV.U32 R4, RZ, RZ, R19 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0013 */
/*04a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x002fea0003800000 */
/*04b0*/ FADD R13, R13, R4 ; /* 0x000000040d0d7221 */
/* 0x000fe20000000000 */
/*04c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*04d0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*04e0*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c04060f7981 */
/* 0x000ea2000c1e1900 */
/*04f0*/ MUFU.RCP R5, R0 ; /* 0x0000000000057308 */
/* 0x000ee20000001000 */
/*0500*/ BSSY B1, 0x5c0 ; /* 0x000000b000017945 */
/* 0x000fe20003800000 */
/*0510*/ FFMA R4, -R0, R5, 1 ; /* 0x3f80000000047423 */
/* 0x008fc80000000105 */
/*0520*/ FFMA R14, R5, R4, R5 ; /* 0x00000004050e7223 */
/* 0x000fe40000000005 */
/*0530*/ FCHK P0, R15, R0 ; /* 0x000000000f007302 */
/* 0x004ea40000000000 */
/*0540*/ FFMA R5, R14, R15, RZ ; /* 0x0000000f0e057223 */
/* 0x000fc800000000ff */
/*0550*/ FFMA R4, -R0, R5, R15 ; /* 0x0000000500047223 */
/* 0x000fc8000000010f */
/*0560*/ FFMA R4, R14, R4, R5 ; /* 0x000000040e047223 */
/* 0x000fe20000000005 */
/*0570*/ @!P0 BRA 0x5b0 ; /* 0x0000003000008947 */
/* 0x004fea0003800000 */
/*0580*/ MOV R4, 0x5a0 ; /* 0x000005a000047802 */
/* 0x002fe40000000f00 */
/*0590*/ CALL.REL.NOINC 0x8b0 ; /* 0x0000031000007944 */
/* 0x001fea0003c00000 */
/*05a0*/ IMAD.MOV.U32 R4, RZ, RZ, R19 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0013 */
/*05b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x002fea0003800000 */
/*05c0*/ IADD3 R12, R12, -0x4, RZ ; /* 0xfffffffc0c0c7810 */
/* 0x000fe20007ffe0ff */
/*05d0*/ FADD R13, R13, R4 ; /* 0x000000040d0d7221 */
/* 0x000fe20000000000 */
/*05e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*05f0*/ IADD3 R6, P1, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007f3e0ff */
/*0600*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f05270 */
/*0610*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e2000c101904 */
/*0620*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007ffe0ff */
/*0630*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fd400008e0607 */
/*0640*/ @P0 BRA 0x1a0 ; /* 0xfffffb5000000947 */
/* 0x002fea000383ffff */
/*0650*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x001fda0003f05270 */
/*0660*/ @!P0 BRA 0x880 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0670*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0680*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000162000c1e1900 */
/*0690*/ IMAD.IADD R10, R10, 0x1, R9 ; /* 0x000000010a0a7824 */
/* 0x000fe400078e0209 */
/*06a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*06b0*/ IMAD R4, R11, c[0x0][0x0], R10 ; /* 0x000000000b047a24 */
/* 0x000fc800078e020a */
/*06c0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*06d0*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*06e0*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x001fc600078e0005 */
/*06f0*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fe20000000f00 */
/*0700*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0710*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0720*/ LDG.E R15, [R4.64] ; /* 0x00000004040f7981 */
/* 0x000ea2000c1e1900 */
/*0730*/ MUFU.RCP R11, R0 ; /* 0x00000000000b7308 */
/* 0x000e220000001000 */
/*0740*/ BSSY B1, 0x800 ; /* 0x000000b000017945 */
/* 0x000fe20003800000 */
/*0750*/ FFMA R10, -R0, R11, 1 ; /* 0x3f800000000a7423 */
/* 0x001fc8000000010b */
/*0760*/ FFMA R12, R11, R10, R11 ; /* 0x0000000a0b0c7223 */
/* 0x000fe4000000000b */
/*0770*/ FCHK P0, R15, R0 ; /* 0x000000000f007302 */
/* 0x004e240000000000 */
/*0780*/ FFMA R11, R12, R15, RZ ; /* 0x0000000f0c0b7223 */
/* 0x000fc800000000ff */
/*0790*/ FFMA R10, -R0, R11, R15 ; /* 0x0000000b000a7223 */
/* 0x000fc8000000010f */
/*07a0*/ FFMA R10, R12, R10, R11 ; /* 0x0000000a0c0a7223 */
/* 0x000fe2000000000b */
/*07b0*/ @!P0 BRA 0x7f0 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*07c0*/ MOV R4, 0x7e0 ; /* 0x000007e000047802 */
/* 0x000fe40000000f00 */
/*07d0*/ CALL.REL.NOINC 0x8b0 ; /* 0x000000d000007944 */
/* 0x020fea0003c00000 */
/*07e0*/ IMAD.MOV.U32 R10, RZ, RZ, R19 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e0013 */
/*07f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0800*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe20007ffe0ff */
/*0810*/ FADD R7, R10, R7 ; /* 0x000000070a077221 */
/* 0x020fe20000000000 */
/*0820*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0830*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f3e0ff */
/*0840*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0850*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*0860*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fd400008e0609 */
/*0870*/ @P0 BRA 0x6f0 ; /* 0xfffffe7000000947 */
/* 0x001fea000383ffff */
/*0880*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0890*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08b0*/ SHF.R.U32.HI R5, RZ, 0x17, R0.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011600 */
/*08c0*/ BSSY B2, 0xf00 ; /* 0x0000063000027945 */
/* 0x000fe20003800000 */
/*08d0*/ SHF.R.U32.HI R16, RZ, 0x17, R15 ; /* 0x00000017ff107819 */
/* 0x000fe2000001160f */
/*08e0*/ IMAD.MOV.U32 R18, RZ, RZ, R0 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0000 */
/*08f0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fc400078ec0ff */
/*0900*/ LOP3.LUT R16, R16, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff10107812 */
/* 0x000fe400078ec0ff */
/*0910*/ IADD3 R19, R5, -0x1, RZ ; /* 0xffffffff05137810 */
/* 0x000fe40007ffe0ff */
/*0920*/ IADD3 R17, R16, -0x1, RZ ; /* 0xffffffff10117810 */
/* 0x000fe40007ffe0ff */
/*0930*/ ISETP.GT.U32.AND P0, PT, R19, 0xfd, PT ; /* 0x000000fd1300780c */
/* 0x000fc80003f04070 */
/*0940*/ ISETP.GT.U32.OR P0, PT, R17, 0xfd, P0 ; /* 0x000000fd1100780c */
/* 0x000fda0000704470 */
/*0950*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e8224 */
/* 0x000fe200078e00ff */
/*0960*/ @!P0 BRA 0xae0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0970*/ FSETP.GTU.FTZ.AND P0, PT, |R15|, +INF , PT ; /* 0x7f8000000f00780b */
/* 0x000fe40003f1c200 */
/*0980*/ FSETP.GTU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fc80003f3c200 */
/*0990*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*09a0*/ @P0 BRA 0xee0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*09b0*/ LOP3.LUT P0, RZ, R18, 0x7fffffff, R15, 0xc8, !PT ; /* 0x7fffffff12ff7812 */
/* 0x000fda000780c80f */
/*09c0*/ @!P0 BRA 0xec0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*09d0*/ FSETP.NEU.FTZ.AND P2, PT, |R15|.reuse, +INF , PT ; /* 0x7f8000000f00780b */
/* 0x040fe40003f5d200 */
/*09e0*/ FSETP.NEU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fe40003f3d200 */
/*09f0*/ FSETP.NEU.FTZ.AND P0, PT, |R15|, +INF , PT ; /* 0x7f8000000f00780b */
/* 0x000fd60003f1d200 */
/*0a00*/ @!P1 BRA !P2, 0xec0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0a10*/ LOP3.LUT P2, RZ, R15, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0fff7812 */
/* 0x000fc8000784c0ff */
/*0a20*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0a30*/ @P1 BRA 0xea0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0a40*/ LOP3.LUT P1, RZ, R18, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff12ff7812 */
/* 0x000fc8000782c0ff */
/*0a50*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0a60*/ @P0 BRA 0xe70 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0a70*/ ISETP.GE.AND P0, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe40003f06270 */
/*0a80*/ ISETP.GE.AND P1, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fd60003f26270 */
/*0a90*/ @P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e0224 */
/* 0x000fe400078e00ff */
/*0aa0*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, -0x40 ; /* 0xffffffc0ff0e8424 */
/* 0x000fe400078e00ff */
/*0ab0*/ @!P0 FFMA R15, R15, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000f0f8823 */
/* 0x000fe400000000ff */
/*0ac0*/ @!P1 FFMA R18, R0, 1.84467440737095516160e+19, RZ ; /* 0x5f80000000129823 */
/* 0x000fe200000000ff */
/*0ad0*/ @!P1 IADD3 R14, R14, 0x40, RZ ; /* 0x000000400e0e9810 */
/* 0x000fe40007ffe0ff */
/*0ae0*/ LEA R17, R5, 0xc0800000, 0x17 ; /* 0xc080000005117811 */
/* 0x000fe200078eb8ff */
/*0af0*/ BSSY B3, 0xe60 ; /* 0x0000036000037945 */
/* 0x000fe20003800000 */
/*0b00*/ IADD3 R16, R16, -0x7f, RZ ; /* 0xffffff8110107810 */
/* 0x000fe40007ffe0ff */
/*0b10*/ IADD3 R21, -R17, R18, RZ ; /* 0x0000001211157210 */
/* 0x000fc60007ffe1ff */
/*0b20*/ IMAD R20, R16.reuse, -0x800000, R15 ; /* 0xff80000010147824 */
/* 0x040fe200078e020f */
/*0b30*/ MUFU.RCP R18, R21 ; /* 0x0000001500127308 */
/* 0x0000620000001000 */
/*0b40*/ FADD.FTZ R17, -R21, -RZ ; /* 0x800000ff15117221 */
/* 0x000fe20000010100 */
/*0b50*/ IADD3 R21, R16, 0x7f, -R5 ; /* 0x0000007f10157810 */
/* 0x001fca0007ffe805 */
/*0b60*/ IMAD.IADD R16, R21, 0x1, R14 ; /* 0x0000000115107824 */
/* 0x000fe400078e020e */
/*0b70*/ FFMA R19, R18, R17, 1 ; /* 0x3f80000012137423 */
/* 0x002fc80000000011 */
/*0b80*/ FFMA R15, R18, R19, R18 ; /* 0x00000013120f7223 */
/* 0x000fc80000000012 */
/*0b90*/ FFMA R18, R20, R15, RZ ; /* 0x0000000f14127223 */
/* 0x000fc800000000ff */
/*0ba0*/ FFMA R19, R17, R18, R20 ; /* 0x0000001211137223 */
/* 0x000fc80000000014 */
/*0bb0*/ FFMA R18, R15, R19, R18 ; /* 0x000000130f127223 */
/* 0x000fc80000000012 */
/*0bc0*/ FFMA R17, R17, R18, R20 ; /* 0x0000001211117223 */
/* 0x000fc80000000014 */
/*0bd0*/ FFMA R19, R15, R17, R18 ; /* 0x000000110f137223 */
/* 0x000fca0000000012 */
/*0be0*/ SHF.R.U32.HI R5, RZ, 0x17, R19 ; /* 0x00000017ff057819 */
/* 0x000fc80000011613 */
/*0bf0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0c00*/ IMAD.IADD R14, R5, 0x1, R16 ; /* 0x00000001050e7824 */
/* 0x000fca00078e0210 */
/*0c10*/ IADD3 R5, R14, -0x1, RZ ; /* 0xffffffff0e057810 */
/* 0x000fc80007ffe0ff */
/*0c20*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0c30*/ @!P0 BRA 0xe40 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0c40*/ ISETP.GT.AND P0, PT, R14, 0xfe, PT ; /* 0x000000fe0e00780c */
/* 0x000fda0003f04270 */
/*0c50*/ @P0 BRA 0xe10 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0c60*/ ISETP.GE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fda0003f06270 */
/*0c70*/ @P0 BRA 0xe50 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0c80*/ ISETP.GE.AND P0, PT, R14, -0x18, PT ; /* 0xffffffe80e00780c */
/* 0x000fe40003f06270 */
/*0c90*/ LOP3.LUT R19, R19, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000013137812 */
/* 0x000fd600078ec0ff */
/*0ca0*/ @!P0 BRA 0xe50 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0cb0*/ FFMA.RZ R5, R15, R17.reuse, R18.reuse ; /* 0x000000110f057223 */
/* 0x180fe2000000c012 */
/*0cc0*/ ISETP.NE.AND P2, PT, R14.reuse, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x040fe40003f45270 */
/*0cd0*/ ISETP.NE.AND P1, PT, R14.reuse, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x040fe40003f25270 */
/*0ce0*/ LOP3.LUT R16, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05107812 */
/* 0x000fe200078ec0ff */
/*0cf0*/ FFMA.RP R5, R15.reuse, R17.reuse, R18.reuse ; /* 0x000000110f057223 */
/* 0x1c0fe40000008012 */
/*0d00*/ FFMA.RM R18, R15, R17, R18 ; /* 0x000000110f127223 */
/* 0x000fe20000004012 */
/*0d10*/ IADD3 R15, R14, 0x20, RZ ; /* 0x000000200e0f7810 */
/* 0x000fe20007ffe0ff */
/*0d20*/ IMAD.MOV R14, RZ, RZ, -R14 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0a0e */
/*0d30*/ LOP3.LUT R16, R16, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000010107812 */
/* 0x000fc400078efcff */
/*0d40*/ FSETP.NEU.FTZ.AND P0, PT, R5, R18, PT ; /* 0x000000120500720b */
/* 0x000fe40003f1d000 */
/*0d50*/ SHF.L.U32 R15, R16, R15, RZ ; /* 0x0000000f100f7219 */
/* 0x000fe400000006ff */
/*0d60*/ SEL R5, R14, RZ, P2 ; /* 0x000000ff0e057207 */
/* 0x000fe40001000000 */
/*0d70*/ ISETP.NE.AND P1, PT, R15, RZ, P1 ; /* 0x000000ff0f00720c */
/* 0x000fe40000f25270 */
/*0d80*/ SHF.R.U32.HI R5, RZ, R5, R16 ; /* 0x00000005ff057219 */
/* 0x000fe40000011610 */
/*0d90*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0da0*/ SHF.R.U32.HI R15, RZ, 0x1, R5 ; /* 0x00000001ff0f7819 */
/* 0x000fe40000011605 */
/*0db0*/ SEL R14, RZ, 0x1, !P0 ; /* 0x00000001ff0e7807 */
/* 0x000fc80004000000 */
/*0dc0*/ LOP3.LUT R14, R14, 0x1, R15, 0xf8, !PT ; /* 0x000000010e0e7812 */
/* 0x000fc800078ef80f */
/*0dd0*/ LOP3.LUT R14, R14, R5, RZ, 0xc0, !PT ; /* 0x000000050e0e7212 */
/* 0x000fca00078ec0ff */
/*0de0*/ IMAD.IADD R14, R15, 0x1, R14 ; /* 0x000000010f0e7824 */
/* 0x000fca00078e020e */
/*0df0*/ LOP3.LUT R19, R14, R19, RZ, 0xfc, !PT ; /* 0x000000130e137212 */
/* 0x000fe200078efcff */
/*0e00*/ BRA 0xe50 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0e10*/ LOP3.LUT R19, R19, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000013137812 */
/* 0x000fc800078ec0ff */
/*0e20*/ LOP3.LUT R19, R19, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000013137812 */
/* 0x000fe200078efcff */
/*0e30*/ BRA 0xe50 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0e40*/ IMAD R19, R16, 0x800000, R19 ; /* 0x0080000010137824 */
/* 0x000fe400078e0213 */
/*0e50*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0e60*/ BRA 0xef0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0e70*/ LOP3.LUT R15, R18, 0x80000000, R15, 0x48, !PT ; /* 0x80000000120f7812 */
/* 0x000fc800078e480f */
/*0e80*/ LOP3.LUT R19, R15, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f8000000f137812 */
/* 0x000fe200078efcff */
/*0e90*/ BRA 0xef0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0ea0*/ LOP3.LUT R19, R18, 0x80000000, R15, 0x48, !PT ; /* 0x8000000012137812 */
/* 0x000fe200078e480f */
/*0eb0*/ BRA 0xef0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0ec0*/ MUFU.RSQ R19, -QNAN ; /* 0xffc0000000137908 */
/* 0x000e220000001400 */
/*0ed0*/ BRA 0xef0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0ee0*/ FADD.FTZ R19, R15, R0 ; /* 0x000000000f137221 */
/* 0x000fe40000010000 */
/*0ef0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0f00*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0f10*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff0e004007950 */
/* 0x000fea0003c3ffff */
/*0f20*/ BRA 0xf20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <time.h>
#include <cuda_runtime.h>
#include <cassert>
#include <cstdlib>
#include <functional>
#include <iostream>
#include <algorithm>
#include <vector>
using std::cout;
using std::generate;
using std::vector;
#define SIZE 10000
#define N 10
#define CUDA_CALL(x) do { if((x)!=cudaSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define CHECK(x) do { if((x)!=cudaSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
__global__ void computeMovingAverage(const float *dev_a, float *dev_b, int size, int n) {
int idx = blockDim.x * blockIdx.x + threadIdx.x;
if(idx < (size - n + 2)){
for(int i = 0; i< n; i++){
dev_b[idx] += dev_a[idx + i]/n;
}
}
__syncthreads();
}
void computeMovingAverageOnCPU(vector<float> &host_a, float &cpuRef, int size, int n) {
vector<float> temp_vec(size);
for(int i = 0; i < (size - n + 2); i++)
for(int j = 0; j < n; j++)
temp_vec[i] += host_a[i+j]/n;
for(int i = 0; i < (size - n + 2); i++)
cpuRef += (float)(temp_vec[i]/(size - n + 1));
}
int main(void){
// set up device
int dev = 0;
cudaDeviceProp deviceProp;
CHECK(cudaGetDeviceProperties(&deviceProp, dev));
printf("Using Device %d: %s\n", dev, deviceProp.name);
CHECK(cudaSetDevice(dev));
int n = N;
int size = SIZE;
printf("Array Size: %d Sample Size: %d\n", size, N);
size_t nBytes = size * sizeof(float);
float cpuRef = 0.0f;
float gpuRef = 0.0f;
// initialize random number
srand ((int)time(0));
// initialize vector and generate random indices between 0 and 5.
vector<float> host_a(size);
vector<float> host_b(size-n);
generate(host_a.begin(), host_a.end(), []() { return rand() % 5; });
float *dev_a, *dev_b;
cudaMalloc(&dev_a, nBytes);
cudaMalloc(&dev_b, nBytes);
cudaMemcpy(dev_a, host_a.data(), nBytes, cudaMemcpyHostToDevice);
// declare block and grid dimension.
dim3 block (1000);
dim3 grid (10);
// Timer starts
float GPUtime, CPUtime;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
computeMovingAverage <<< grid, block >>> (dev_a, dev_b, size, n);
cudaMemcpy(host_b.data(), dev_b, nBytes, cudaMemcpyDeviceToHost);
for(int x = 0; x< (size-n+2); x++){
gpuRef += (float)(host_b[x]/(size - n + 1));
}
// timer stops
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&GPUtime, start, stop);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
computeMovingAverageOnCPU(host_a, cpuRef, size, n);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&CPUtime, start, stop);
printf("Kernel: computeMovingAverage <<<gridDim: %d, blockDim: %d>>>\n", grid.x, block.x);
printf("Compute time on GPU: %3.6f ms \n", GPUtime);
printf("Compute time on CPU: %3.6f ms \n", CPUtime);
printf("Moving Average computed on CPU: %3.6f\n", cpuRef);
printf("Moving Average computed on GPU: %3.6f\n", gpuRef);
cudaFree(dev_a);
cudaFree(dev_b);
return (0);
} | .file "tmpxft_000d2eae_00000000-6_moving_Average.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4927:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4927:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cannot create std::vector larger than max_size()"
.text
.globl _Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii
.type _Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii, @function
_Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii:
.LFB4920:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movslq %edx, %r15
movq %r15, %rax
shrq $61, %rax
jne .L22
movq %rdi, %rbp
movq %rsi, %r12
movl %edx, %r14d
movl %ecx, %ebx
testq %r15, %r15
je .L5
leaq 0(,%r15,4), %r13
movq %r13, %rdi
call _Znwm@PLT
movq %rax, %r8
movl $0x00000000, (%rax)
cmpq $1, %r15
je .L6
leaq (%rax,%r13), %rdx
leaq 4(%rax), %rax
cmpq %rax, %rdx
je .L6
.L7:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L7
.L6:
subl %ebx, %r14d
movl %r14d, %r11d
addl $1, %r11d
js .L16
.L15:
movq %r8, %rsi
leal 1(%r14), %r10d
movslq %ebx, %r9
salq $2, %r9
subq %r8, %r9
movq %r8, %rdx
movl $0, %edi
jmp .L8
.L22:
leaq .LC0(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L11:
movq 0(%rbp), %rcx
leaq (%rcx,%rdi,4), %rax
addq %r9, %rcx
addq %rdx, %rcx
pxor %xmm1, %xmm1
cvtsi2ssl %ebx, %xmm1
.L9:
movss (%rax), %xmm0
divss %xmm1, %xmm0
addss (%rdx), %xmm0
movss %xmm0, (%rdx)
addq $4, %rax
cmpq %rcx, %rax
jne .L9
.L12:
leaq 1(%rdi), %rax
addq $4, %rdx
cmpq %r10, %rdi
je .L10
movq %rax, %rdi
.L8:
testl %ebx, %ebx
jg .L11
jmp .L12
.L10:
movss (%r12), %xmm1
leaq 4(%rsi,%r10,4), %rax
pxor %xmm2, %xmm2
cvtsi2ssl %r11d, %xmm2
.L13:
movss (%rsi), %xmm0
divss %xmm2, %xmm0
addss %xmm0, %xmm1
addq $4, %rsi
cmpq %rax, %rsi
jne .L13
movss %xmm1, (%r12)
testq %r8, %r8
je .L3
.L16:
movq %r13, %rsi
movq %r8, %rdi
call _ZdlPvm@PLT
.L3:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
subl %ecx, %r14d
movq %r15, %r13
movl $0, %r8d
movl %r14d, %r11d
addl $1, %r11d
jns .L15
jmp .L3
.cfi_endproc
.LFE4920:
.size _Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii, .-_Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii
.globl _Z45__device_stub__Z20computeMovingAveragePKfPfiiPKfPfii
.type _Z45__device_stub__Z20computeMovingAveragePKfPfiiPKfPfii, @function
_Z45__device_stub__Z20computeMovingAveragePKfPfiiPKfPfii:
.LFB4949:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20computeMovingAveragePKfPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4949:
.size _Z45__device_stub__Z20computeMovingAveragePKfPfiiPKfPfii, .-_Z45__device_stub__Z20computeMovingAveragePKfPfiiPKfPfii
.globl _Z20computeMovingAveragePKfPfii
.type _Z20computeMovingAveragePKfPfii, @function
_Z20computeMovingAveragePKfPfii:
.LFB4950:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z20computeMovingAveragePKfPfiiPKfPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4950:
.size _Z20computeMovingAveragePKfPfii, .-_Z20computeMovingAveragePKfPfii
.section .rodata.str1.8
.align 8
.LC2:
.string "_Z20computeMovingAveragePKfPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4952:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z20computeMovingAveragePKfPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4952:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEED2Ev
.type _ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB5269:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L36
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L36:
ret
.cfi_endproc
.LFE5269:
.size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
.weak _ZNSt6vectorIfSaIfEED1Ev
.set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
.section .rodata.str1.8
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/wolfatthegate/CS79995-Assignment2/master/moving_Average.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Error at %s:%d\n"
.LC5:
.string "Using Device %d: %s\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Array Size: %d Sample Size: %d\n"
.align 8
.LC8:
.string "Kernel: computeMovingAverage <<<gridDim: %d, blockDim: %d>>>\n"
.align 8
.LC9:
.string "Compute time on GPU: %3.6f ms \n"
.align 8
.LC10:
.string "Compute time on CPU: %3.6f ms \n"
.align 8
.LC11:
.string "Moving Average computed on CPU: %3.6f\n"
.align 8
.LC12:
.string "Moving Average computed on GPU: %3.6f\n"
.text
.globl main
.type main, @function
main:
.LFB4921:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4921
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1208, %rsp
.cfi_def_cfa_offset 1248
movq %fs:40, %rax
movq %rax, 1192(%rsp)
xorl %eax, %eax
leaq 160(%rsp), %rdi
movl $0, %esi
.LEHB0:
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L59
leaq 160(%rsp), %rcx
movl $0, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L60
movl $10, %ecx
movl $10000, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0x00000000, 28(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $40000, %edi
call _Znwm@PLT
.LEHE0:
movq %rax, %r12
movq %rax, 96(%rsp)
leaq 40000(%rax), %rdx
movq %rdx, 112(%rsp)
movl $0x00000000, (%rax)
leaq 4(%rax), %rax
.L43:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L43
movq %rdx, 104(%rsp)
movq $0, 136(%rsp)
movq $0, 144(%rsp)
movl $39960, %edi
.LEHB1:
call _Znwm@PLT
.LEHE1:
jmp .L61
.L59:
movl $55, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB2:
call __printf_chk@PLT
movl $1, %eax
jmp .L39
.L60:
movl $57, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.LEHE2:
movl $1, %eax
jmp .L39
.L61:
movq %rax, %rbx
movq %rax, 128(%rsp)
leaq 39960(%rax), %rdx
movq %rdx, 144(%rsp)
movl $0x00000000, (%rax)
leaq 4(%rax), %rax
.L44:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L44
movq %rdx, 136(%rsp)
movq %r12, %rbp
leaq 40000(%r12), %r13
.L45:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp)
addq $4, %rbp
cmpq %r13, %rbp
jne .L45
leaq 40(%rsp), %rdi
movl $40000, %esi
.LEHB3:
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40000, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl $10, 84(%rsp)
movl $1000, 72(%rsp)
movl 80(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 72(%rsp), %rdx
movq 84(%rsp), %rdi
movl 92(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L46
movl $10, %ecx
movl $10000, %edx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z45__device_stub__Z20computeMovingAveragePKfPfiiPKfPfii
.L46:
movl $2, %ecx
movl $40000, %edx
movq 48(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 39968(%rbx), %rdx
movl $0x00000000, 12(%rsp)
movss .LC7(%rip), %xmm1
.L47:
movss (%rax), %xmm0
divss %xmm1, %xmm0
addss 12(%rsp), %xmm0
movss %xmm0, 12(%rsp)
addq $4, %rax
cmpq %rax, %rdx
jne .L47
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 32(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
leaq 28(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $10, %ecx
movl $10000, %edx
call _Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 36(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $1000, %ecx
movl $10, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 32(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
.LEHE3:
leaq 128(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movl $0, %eax
.L39:
movq 1192(%rsp), %rdx
subq %fs:40, %rdx
jne .L62
addq $1208, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 128(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L49:
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 1192(%rsp), %rax
subq %fs:40, %rax
je .L50
call __stack_chk_fail@PLT
.L52:
endbr64
movq %rax, %rbx
jmp .L49
.L50:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L62:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4921:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4921:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4921-.LLSDACSB4921
.LLSDACSB4921:
.uleb128 .LEHB0-.LFB4921
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4921
.uleb128 .LEHE1-.LEHB1
.uleb128 .L52-.LFB4921
.uleb128 0
.uleb128 .LEHB2-.LFB4921
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4921
.uleb128 .LEHE3-.LEHB3
.uleb128 .L53-.LFB4921
.uleb128 0
.uleb128 .LEHB4-.LFB4921
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4921:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1176247296
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <time.h>
#include <cuda_runtime.h>
#include <cassert>
#include <cstdlib>
#include <functional>
#include <iostream>
#include <algorithm>
#include <vector>
using std::cout;
using std::generate;
using std::vector;
#define SIZE 10000
#define N 10
#define CUDA_CALL(x) do { if((x)!=cudaSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define CHECK(x) do { if((x)!=cudaSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
__global__ void computeMovingAverage(const float *dev_a, float *dev_b, int size, int n) {
int idx = blockDim.x * blockIdx.x + threadIdx.x;
if(idx < (size - n + 2)){
for(int i = 0; i< n; i++){
dev_b[idx] += dev_a[idx + i]/n;
}
}
__syncthreads();
}
void computeMovingAverageOnCPU(vector<float> &host_a, float &cpuRef, int size, int n) {
vector<float> temp_vec(size);
for(int i = 0; i < (size - n + 2); i++)
for(int j = 0; j < n; j++)
temp_vec[i] += host_a[i+j]/n;
for(int i = 0; i < (size - n + 2); i++)
cpuRef += (float)(temp_vec[i]/(size - n + 1));
}
int main(void){
// set up device
int dev = 0;
cudaDeviceProp deviceProp;
CHECK(cudaGetDeviceProperties(&deviceProp, dev));
printf("Using Device %d: %s\n", dev, deviceProp.name);
CHECK(cudaSetDevice(dev));
int n = N;
int size = SIZE;
printf("Array Size: %d Sample Size: %d\n", size, N);
size_t nBytes = size * sizeof(float);
float cpuRef = 0.0f;
float gpuRef = 0.0f;
// initialize random number
srand ((int)time(0));
// initialize vector and generate random indices between 0 and 5.
vector<float> host_a(size);
vector<float> host_b(size-n);
generate(host_a.begin(), host_a.end(), []() { return rand() % 5; });
float *dev_a, *dev_b;
cudaMalloc(&dev_a, nBytes);
cudaMalloc(&dev_b, nBytes);
cudaMemcpy(dev_a, host_a.data(), nBytes, cudaMemcpyHostToDevice);
// declare block and grid dimension.
dim3 block (1000);
dim3 grid (10);
// Timer starts
float GPUtime, CPUtime;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
computeMovingAverage <<< grid, block >>> (dev_a, dev_b, size, n);
cudaMemcpy(host_b.data(), dev_b, nBytes, cudaMemcpyDeviceToHost);
for(int x = 0; x< (size-n+2); x++){
gpuRef += (float)(host_b[x]/(size - n + 1));
}
// timer stops
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&GPUtime, start, stop);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
computeMovingAverageOnCPU(host_a, cpuRef, size, n);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&CPUtime, start, stop);
printf("Kernel: computeMovingAverage <<<gridDim: %d, blockDim: %d>>>\n", grid.x, block.x);
printf("Compute time on GPU: %3.6f ms \n", GPUtime);
printf("Compute time on CPU: %3.6f ms \n", CPUtime);
printf("Moving Average computed on CPU: %3.6f\n", cpuRef);
printf("Moving Average computed on GPU: %3.6f\n", gpuRef);
cudaFree(dev_a);
cudaFree(dev_b);
return (0);
} | #include <stdio.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <cassert>
#include <cstdlib>
#include <functional>
#include <iostream>
#include <algorithm>
#include <vector>
using std::cout;
using std::generate;
using std::vector;
#define SIZE 10000
#define N 10
#define CUDA_CALL(x) do { if((x)!=hipSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define CHECK(x) do { if((x)!=hipSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
__global__ void computeMovingAverage(const float *dev_a, float *dev_b, int size, int n) {
int idx = blockDim.x * blockIdx.x + threadIdx.x;
if(idx < (size - n + 2)){
for(int i = 0; i< n; i++){
dev_b[idx] += dev_a[idx + i]/n;
}
}
__syncthreads();
}
void computeMovingAverageOnCPU(vector<float> &host_a, float &cpuRef, int size, int n) {
vector<float> temp_vec(size);
for(int i = 0; i < (size - n + 2); i++)
for(int j = 0; j < n; j++)
temp_vec[i] += host_a[i+j]/n;
for(int i = 0; i < (size - n + 2); i++)
cpuRef += (float)(temp_vec[i]/(size - n + 1));
}
int main(void){
// set up device
int dev = 0;
hipDeviceProp_t deviceProp;
CHECK(hipGetDeviceProperties(&deviceProp, dev));
printf("Using Device %d: %s\n", dev, deviceProp.name);
CHECK(hipSetDevice(dev));
int n = N;
int size = SIZE;
printf("Array Size: %d Sample Size: %d\n", size, N);
size_t nBytes = size * sizeof(float);
float cpuRef = 0.0f;
float gpuRef = 0.0f;
// initialize random number
srand ((int)time(0));
// initialize vector and generate random indices between 0 and 5.
vector<float> host_a(size);
vector<float> host_b(size-n);
generate(host_a.begin(), host_a.end(), []() { return rand() % 5; });
float *dev_a, *dev_b;
hipMalloc(&dev_a, nBytes);
hipMalloc(&dev_b, nBytes);
hipMemcpy(dev_a, host_a.data(), nBytes, hipMemcpyHostToDevice);
// declare block and grid dimension.
dim3 block (1000);
dim3 grid (10);
// Timer starts
float GPUtime, CPUtime;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
computeMovingAverage <<< grid, block >>> (dev_a, dev_b, size, n);
hipMemcpy(host_b.data(), dev_b, nBytes, hipMemcpyDeviceToHost);
for(int x = 0; x< (size-n+2); x++){
gpuRef += (float)(host_b[x]/(size - n + 1));
}
// timer stops
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&GPUtime, start, stop);
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
computeMovingAverageOnCPU(host_a, cpuRef, size, n);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&CPUtime, start, stop);
printf("Kernel: computeMovingAverage <<<gridDim: %d, blockDim: %d>>>\n", grid.x, block.x);
printf("Compute time on GPU: %3.6f ms \n", GPUtime);
printf("Compute time on CPU: %3.6f ms \n", CPUtime);
printf("Moving Average computed on CPU: %3.6f\n", cpuRef);
printf("Moving Average computed on GPU: %3.6f\n", gpuRef);
hipFree(dev_a);
hipFree(dev_b);
return (0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <cassert>
#include <cstdlib>
#include <functional>
#include <iostream>
#include <algorithm>
#include <vector>
using std::cout;
using std::generate;
using std::vector;
#define SIZE 10000
#define N 10
#define CUDA_CALL(x) do { if((x)!=hipSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define CHECK(x) do { if((x)!=hipSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
__global__ void computeMovingAverage(const float *dev_a, float *dev_b, int size, int n) {
int idx = blockDim.x * blockIdx.x + threadIdx.x;
if(idx < (size - n + 2)){
for(int i = 0; i< n; i++){
dev_b[idx] += dev_a[idx + i]/n;
}
}
__syncthreads();
}
void computeMovingAverageOnCPU(vector<float> &host_a, float &cpuRef, int size, int n) {
vector<float> temp_vec(size);
for(int i = 0; i < (size - n + 2); i++)
for(int j = 0; j < n; j++)
temp_vec[i] += host_a[i+j]/n;
for(int i = 0; i < (size - n + 2); i++)
cpuRef += (float)(temp_vec[i]/(size - n + 1));
}
int main(void){
// set up device
int dev = 0;
hipDeviceProp_t deviceProp;
CHECK(hipGetDeviceProperties(&deviceProp, dev));
printf("Using Device %d: %s\n", dev, deviceProp.name);
CHECK(hipSetDevice(dev));
int n = N;
int size = SIZE;
printf("Array Size: %d Sample Size: %d\n", size, N);
size_t nBytes = size * sizeof(float);
float cpuRef = 0.0f;
float gpuRef = 0.0f;
// initialize random number
srand ((int)time(0));
// initialize vector and generate random indices between 0 and 5.
vector<float> host_a(size);
vector<float> host_b(size-n);
generate(host_a.begin(), host_a.end(), []() { return rand() % 5; });
float *dev_a, *dev_b;
hipMalloc(&dev_a, nBytes);
hipMalloc(&dev_b, nBytes);
hipMemcpy(dev_a, host_a.data(), nBytes, hipMemcpyHostToDevice);
// declare block and grid dimension.
dim3 block (1000);
dim3 grid (10);
// Timer starts
float GPUtime, CPUtime;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
computeMovingAverage <<< grid, block >>> (dev_a, dev_b, size, n);
hipMemcpy(host_b.data(), dev_b, nBytes, hipMemcpyDeviceToHost);
for(int x = 0; x< (size-n+2); x++){
gpuRef += (float)(host_b[x]/(size - n + 1));
}
// timer stops
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&GPUtime, start, stop);
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
computeMovingAverageOnCPU(host_a, cpuRef, size, n);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&CPUtime, start, stop);
printf("Kernel: computeMovingAverage <<<gridDim: %d, blockDim: %d>>>\n", grid.x, block.x);
printf("Compute time on GPU: %3.6f ms \n", GPUtime);
printf("Compute time on CPU: %3.6f ms \n", CPUtime);
printf("Moving Average computed on CPU: %3.6f\n", cpuRef);
printf("Moving Average computed on GPU: %3.6f\n", gpuRef);
hipFree(dev_a);
hipFree(dev_b);
return (0);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20computeMovingAveragePKfPfii
.globl _Z20computeMovingAveragePKfPfii
.p2align 8
.type _Z20computeMovingAveragePKfPfii,@function
_Z20computeMovingAveragePKfPfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_sub_i32 s2, s4, s5
s_add_i32 s2, s2, 2
s_cmp_gt_i32 s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_cselect_b32 s2, -1, 0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v5, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s5, 0
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_nc_u32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
global_load_b32 v2, v[6:7], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v6, null, v5, v5, v2
v_div_scale_f32 v9, vcc_lo, v2, v5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v6, v7, 1.0
v_fmac_f32_e32 v7, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v9, v7
v_fma_f32 v10, -v6, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v10, v7
v_fma_f32 v6, -v6, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v6, v6, v7, v8
v_div_fixup_f32 v2, v6, v5, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v0, v2
global_store_b32 v[3:4], v0, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20computeMovingAveragePKfPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20computeMovingAveragePKfPfii, .Lfunc_end0-_Z20computeMovingAveragePKfPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20computeMovingAveragePKfPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20computeMovingAveragePKfPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <cassert>
#include <cstdlib>
#include <functional>
#include <iostream>
#include <algorithm>
#include <vector>
using std::cout;
using std::generate;
using std::vector;
#define SIZE 10000
#define N 10
#define CUDA_CALL(x) do { if((x)!=hipSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define CHECK(x) do { if((x)!=hipSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
__global__ void computeMovingAverage(const float *dev_a, float *dev_b, int size, int n) {
int idx = blockDim.x * blockIdx.x + threadIdx.x;
if(idx < (size - n + 2)){
for(int i = 0; i< n; i++){
dev_b[idx] += dev_a[idx + i]/n;
}
}
__syncthreads();
}
void computeMovingAverageOnCPU(vector<float> &host_a, float &cpuRef, int size, int n) {
vector<float> temp_vec(size);
for(int i = 0; i < (size - n + 2); i++)
for(int j = 0; j < n; j++)
temp_vec[i] += host_a[i+j]/n;
for(int i = 0; i < (size - n + 2); i++)
cpuRef += (float)(temp_vec[i]/(size - n + 1));
}
int main(void){
// set up device
int dev = 0;
hipDeviceProp_t deviceProp;
CHECK(hipGetDeviceProperties(&deviceProp, dev));
printf("Using Device %d: %s\n", dev, deviceProp.name);
CHECK(hipSetDevice(dev));
int n = N;
int size = SIZE;
printf("Array Size: %d Sample Size: %d\n", size, N);
size_t nBytes = size * sizeof(float);
float cpuRef = 0.0f;
float gpuRef = 0.0f;
// initialize random number
srand ((int)time(0));
// initialize vector and generate random indices between 0 and 5.
vector<float> host_a(size);
vector<float> host_b(size-n);
generate(host_a.begin(), host_a.end(), []() { return rand() % 5; });
float *dev_a, *dev_b;
hipMalloc(&dev_a, nBytes);
hipMalloc(&dev_b, nBytes);
hipMemcpy(dev_a, host_a.data(), nBytes, hipMemcpyHostToDevice);
// declare block and grid dimension.
dim3 block (1000);
dim3 grid (10);
// Timer starts
float GPUtime, CPUtime;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
computeMovingAverage <<< grid, block >>> (dev_a, dev_b, size, n);
hipMemcpy(host_b.data(), dev_b, nBytes, hipMemcpyDeviceToHost);
for(int x = 0; x< (size-n+2); x++){
gpuRef += (float)(host_b[x]/(size - n + 1));
}
// timer stops
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&GPUtime, start, stop);
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
computeMovingAverageOnCPU(host_a, cpuRef, size, n);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&CPUtime, start, stop);
printf("Kernel: computeMovingAverage <<<gridDim: %d, blockDim: %d>>>\n", grid.x, block.x);
printf("Compute time on GPU: %3.6f ms \n", GPUtime);
printf("Compute time on CPU: %3.6f ms \n", CPUtime);
printf("Moving Average computed on CPU: %3.6f\n", cpuRef);
printf("Moving Average computed on GPU: %3.6f\n", gpuRef);
hipFree(dev_a);
hipFree(dev_b);
return (0);
} | .text
.file "moving_Average.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z35__device_stub__computeMovingAveragePKfPfii # -- Begin function _Z35__device_stub__computeMovingAveragePKfPfii
.p2align 4, 0x90
.type _Z35__device_stub__computeMovingAveragePKfPfii,@function
_Z35__device_stub__computeMovingAveragePKfPfii: # @_Z35__device_stub__computeMovingAveragePKfPfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20computeMovingAveragePKfPfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__computeMovingAveragePKfPfii, .Lfunc_end0-_Z35__device_stub__computeMovingAveragePKfPfii
.cfi_endproc
# -- End function
.globl _Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii # -- Begin function _Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii
.p2align 4, 0x90
.type _Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii,@function
_Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii: # @_Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testl %edx, %edx
js .LBB1_19
# %bb.1: # %_ZNSt6vectorIfSaIfEE17_S_check_init_lenEmRKS0_.exit.i
movl %ecx, %ebp
movl %edx, %r15d
movq %rsi, %rbx
movq %rdi, %r12
movslq %edx, %r13
je .LBB1_2
# %bb.3: # %_ZNSt16allocator_traitsISaIfEE8allocateERS0_m.exit.i.i.i.i
leaq (,%r13,4), %rdi
callq _Znwm
movq %rax, %r14
testl %r15d, %r15d
jne .LBB1_5
jmp .LBB1_7
.LBB1_2:
xorl %r14d, %r14d
testl %r15d, %r15d
je .LBB1_7
.LBB1_5:
movl $0, (%r14)
cmpl $1, %r15d
je .LBB1_7
# %bb.6: # %_ZSt6fill_nIPfmfET_S1_T0_RKT1_.exit.loopexit.i.i.i.i.i
leaq 4(%r14), %rdi
leaq -4(,%r13,4), %rdx
xorl %esi, %esi
callq memset@PLT
.LBB1_7: # %_ZNSt6vectorIfSaIfEEC2EmRKS0_.exit
subl %ebp, %r15d
leal 2(%r15), %eax
cmpl $-1, %r15d
jl .LBB1_13
# %bb.8: # %.preheader30.lr.ph
cvtsi2ss %ebp, %xmm0
movq (%r12), %rcx
cmpl $2, %eax
movl $1, %edx
cmovgel %eax, %edx
movl %ebp, %esi
xorl %edi, %edi
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_12: # %._crit_edge
# in Loop: Header=BB1_9 Depth=1
incq %rdi
addq $4, %rcx
cmpq %rdx, %rdi
je .LBB1_13
.LBB1_9: # %.preheader30
# =>This Loop Header: Depth=1
# Child Loop BB1_11 Depth 2
testl %ebp, %ebp
jle .LBB1_12
# %bb.10: # %.lr.ph
# in Loop: Header=BB1_9 Depth=1
movss (%r14,%rdi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_11: # Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rcx,%r8,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
divss %xmm0, %xmm2
addss %xmm2, %xmm1
movss %xmm1, (%r14,%rdi,4)
incq %r8
cmpq %r8, %rsi
jne .LBB1_11
jmp .LBB1_12
.LBB1_13: # %.preheader
cmpl $-1, %r15d
jl .LBB1_17
# %bb.14: # %.lr.ph37
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
incl %r15d
xorps %xmm1, %xmm1
cvtsi2ss %r15d, %xmm1
cmpl $2, %eax
movl $1, %ecx
cmovgel %eax, %ecx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_15: # =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
divss %xmm1, %xmm2
addss %xmm2, %xmm0
incq %rax
cmpq %rax, %rcx
jne .LBB1_15
# %bb.16: # %._crit_edge38
movss %xmm0, (%rbx)
.LBB1_17:
testq %r14, %r14
je .LBB1_18
# %bb.20:
movq %r14, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.LBB1_18: # %_ZNSt6vectorIfSaIfEED2Ev.exit
.cfi_def_cfa_offset 64
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_19: # %.noexc
.cfi_def_cfa_offset 64
movl $.L.str.9, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end1:
.size _Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii, .Lfunc_end1-_Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x461c1c00 # float 9991
.LCPI2_1:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1640, %rsp # imm = 0x668
.cfi_def_cfa_offset 1680
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
leaq 168(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
je .LBB2_3
# %bb.1:
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $55, %edx
jmp .LBB2_2
.LBB2_3:
.cfi_escape 0x2e, 0x00
leaq 168(%rsp), %rdx
movl $.L.str.2, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
.cfi_escape 0x2e, 0x00
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
je .LBB2_5
# %bb.4:
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $57, %edx
.LBB2_2:
xorl %eax, %eax
callq printf
movl $1, %eax
.LBB2_40:
addq $1640, %rsp # imm = 0x668
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_5: # %_ZNSt6vectorIfSaIfEEC2EmRKS0_.exit
.cfi_def_cfa_offset 1680
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
movl $10000, %esi # imm = 0x2710
movl $10, %edx
xorl %eax, %eax
callq printf
.cfi_escape 0x2e, 0x00
xorl %edi, %edi
callq time
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq srand
.cfi_escape 0x2e, 0x00
movl $40000, %edi # imm = 0x9C40
callq _Znwm
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $40000, %edx # imm = 0x9C40
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $39960, %edi # imm = 0x9C18
callq _Znwm
.Ltmp1:
# %bb.6: # %_ZNSt6vectorIfSaIfEEC2EmRKS0_.exit48
movq %rax, %r14
.cfi_escape 0x2e, 0x00
xorl %r15d, %r15d
movl $39960, %edx # imm = 0x9C18
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB2_7: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r15)
addq $4, %r15
cmpq $40000, %r15 # imm = 0x9C40
jne .LBB2_7
# %bb.8: # %_ZSt8generateIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEEZ4mainEUlvE_EvT_S8_T0_.exit
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
.Ltmp4:
# %bb.9: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit
.Ltmp5:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
.Ltmp6:
# %bb.10: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit49
movq 32(%rsp), %rdi
.Ltmp7:
.cfi_escape 0x2e, 0x00
movl $40000, %edx # imm = 0x9C40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp8:
# %bb.11:
.Ltmp10:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq hipEventCreate
.Ltmp11:
# %bb.12:
.Ltmp12:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
callq hipEventCreate
.Ltmp13:
# %bb.13:
movq 16(%rsp), %rdi
.Ltmp14:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp15:
# %bb.14:
.Ltmp16:
.cfi_escape 0x2e, 0x00
movabsq $4294967306, %rdi # imm = 0x10000000A
movabsq $4294968296, %rdx # imm = 0x1000003E8
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp17:
# %bb.15:
testl %eax, %eax
jne .LBB2_18
# %bb.16:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl $10000, 60(%rsp) # imm = 0x2710
movl $10, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 60(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rax
movq %rax, 152(%rsp)
.Ltmp18:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp19:
# %bb.17: # %.noexc
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
.Ltmp20:
.cfi_escape 0x2e, 0x10
leaq 128(%rsp), %r9
movl $_Z20computeMovingAveragePKfPfii, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp21:
.LBB2_18:
movq 24(%rsp), %rsi
.Ltmp22:
.cfi_escape 0x2e, 0x00
movl $40000, %edx # imm = 0x9C40
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp23:
# %bb.19: # %.preheader.preheader
xorps %xmm1, %xmm1
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_20: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_0(%rip), %xmm0
addss %xmm0, %xmm1
incq %rax
cmpq $9992, %rax # imm = 0x2708
jne .LBB2_20
# %bb.21:
movss %xmm1, 44(%rsp) # 4-byte Spill
movq 8(%rsp), %rdi
.Ltmp24:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp25:
# %bb.22:
movq 8(%rsp), %rdi
.Ltmp26:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp27:
# %bb.23:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
.Ltmp28:
.cfi_escape 0x2e, 0x00
leaq 52(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp29:
# %bb.24:
.Ltmp30:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq hipEventCreate
.Ltmp31:
# %bb.25:
.Ltmp32:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
callq hipEventCreate
.Ltmp33:
# %bb.26:
movq 16(%rsp), %rdi
.Ltmp34:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp35:
# %bb.27:
.Ltmp36:
.cfi_escape 0x2e, 0x00
movl $40000, %edi # imm = 0x9C40
callq _Znwm
.Ltmp37:
# %bb.28: # %.noexc52
movq %rax, %r15
.cfi_escape 0x2e, 0x00
xorl %r12d, %r12d
movl $40000, %edx # imm = 0x9C40
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movss .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rbx, %rax
.p2align 4, 0x90
.LBB2_29: # %.preheader30.i
# =>This Loop Header: Depth=1
# Child Loop BB2_30 Depth 2
movss (%r15,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_30: # Parent Loop BB2_29 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rax,%rcx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
divss %xmm0, %xmm2
addss %xmm2, %xmm1
incq %rcx
cmpq $10, %rcx
jne .LBB2_30
# %bb.31: # %._crit_edge.i
# in Loop: Header=BB2_29 Depth=1
movss %xmm1, (%r15,%r12,4)
incq %r12
addq $4, %rax
cmpq $9992, %r12 # imm = 0x2708
jne .LBB2_29
# %bb.32: # %.preheader.i.preheader
xorps %xmm2, %xmm2
xorl %eax, %eax
movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB2_33: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movss (%r15,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss %xmm1, %xmm0
addss %xmm0, %xmm2
incq %rax
cmpq $9992, %rax # imm = 0x2708
jne .LBB2_33
# %bb.34: # %_Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii.exit
movss %xmm2, 40(%rsp) # 4-byte Spill
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
movq 8(%rsp), %rdi
.Ltmp38:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp39:
# %bb.35:
movq 8(%rsp), %rdi
.Ltmp40:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp41:
# %bb.36:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
.Ltmp42:
.cfi_escape 0x2e, 0x00
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp43:
# %bb.37:
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %edi
movl $10, %esi
movl $1000, %edx # imm = 0x3E8
xorl %eax, %eax
callq printf
movss 52(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %edi
movb $1, %al
callq printf
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %edi
movb $1, %al
callq printf
movss 40(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str.7, %edi
movb $1, %al
callq printf
movss 44(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str.8, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
.Ltmp44:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp45:
# %bb.38:
movq 24(%rsp), %rdi
.Ltmp46:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp47:
# %bb.39: # %_ZNSt6vectorIfSaIfEED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
jmp .LBB2_40
.LBB2_41:
.Ltmp2:
movq %rax, %r15
jmp .LBB2_45
.LBB2_43:
.Ltmp9:
jmp .LBB2_44
.LBB2_42:
.Ltmp48:
.LBB2_44: # %_ZNSt6vectorIfSaIfEED2Ev.exit56
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB2_45: # %_ZNSt6vectorIfSaIfEED2Ev.exit58
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp8-.Ltmp3 # Call between .Ltmp3 and .Ltmp8
.uleb128 .Ltmp9-.Lfunc_begin0 # jumps to .Ltmp9
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp37-.Ltmp10 # Call between .Ltmp10 and .Ltmp37
.uleb128 .Ltmp48-.Lfunc_begin0 # jumps to .Ltmp48
.byte 0 # On action: cleanup
.uleb128 .Ltmp37-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp38-.Ltmp37 # Call between .Ltmp37 and .Ltmp38
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp38-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp47-.Ltmp38 # Call between .Ltmp38 and .Ltmp47
.uleb128 .Ltmp48-.Lfunc_begin0 # jumps to .Ltmp48
.byte 0 # On action: cleanup
.uleb128 .Ltmp47-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Lfunc_end2-.Ltmp47 # Call between .Ltmp47 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20computeMovingAveragePKfPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20computeMovingAveragePKfPfii,@object # @_Z20computeMovingAveragePKfPfii
.section .rodata,"a",@progbits
.globl _Z20computeMovingAveragePKfPfii
.p2align 3, 0x0
_Z20computeMovingAveragePKfPfii:
.quad _Z35__device_stub__computeMovingAveragePKfPfii
.size _Z20computeMovingAveragePKfPfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error at %s:%d\n"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/wolfatthegate/CS79995-Assignment2/master/moving_Average.hip"
.size .L.str.1, 117
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Using Device %d: %s\n"
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Array Size: %d Sample Size: %d\n"
.size .L.str.3, 33
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Kernel: computeMovingAverage <<<gridDim: %d, blockDim: %d>>>\n"
.size .L.str.4, 62
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Compute time on GPU: %3.6f ms \n"
.size .L.str.5, 32
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Compute time on CPU: %3.6f ms \n"
.size .L.str.6, 32
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Moving Average computed on CPU: %3.6f\n"
.size .L.str.7, 39
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Moving Average computed on GPU: %3.6f\n"
.size .L.str.8, 39
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "cannot create std::vector larger than max_size()"
.size .L.str.9, 49
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20computeMovingAveragePKfPfii"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__computeMovingAveragePKfPfii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z20computeMovingAveragePKfPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20computeMovingAveragePKfPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff087624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x890 ; /* 0x0000084000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0060*/ UIADD3 UR4, UR4, 0x2, -UR5 ; /* 0x0000000204047890 */
/* 0x000fe2000fffe805 */
/*0070*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R4, R11, c[0x0][0x0], R10 ; /* 0x000000000b047a24 */
/* 0x001fca00078e020a */
/*0090*/ ISETP.GE.OR P0, PT, R4, UR4, !P0 ; /* 0x0000000404007c0c */
/* 0x000fda000c706670 */
/*00a0*/ @P0 BRA 0x880 ; /* 0x000007d000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R2, R8.reuse, -0x1, RZ ; /* 0xffffffff08027810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ I2F R0, c[0x0][0x174] ; /* 0x00005d0000007b06 */
/* 0x000e220000201400 */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*00e0*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe200078ec0ff */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0110*/ IMAD.WIDE R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fd800078e0203 */
/*0120*/ @!P0 BRA 0x650 ; /* 0x0000052000008947 */
/* 0x000fea0003800000 */
/*0130*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x001fe40000000a00 */
/*0140*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000162000c1e1900 */
/*0150*/ LEA R6, P0, R4, c[0x0][0x160], 0x2 ; /* 0x0000580004067a11 */
/* 0x000fe200078010ff */
/*0160*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0170*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe40000011404 */
/*0180*/ IADD3 R12, -R8, c[0x0][0x174], RZ ; /* 0x00005d00080c7a10 */
/* 0x000fe40007ffe1ff */
/*0190*/ LEA.HI.X R7, R4, c[0x0][0x164], R5, 0x2, P0 ; /* 0x0000590004077a11 */
/* 0x000fc600000f1405 */
/*01a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*01b0*/ LDG.E R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ MUFU.RCP R5, R0 ; /* 0x0000000000057308 */
/* 0x000e620000001000 */
/*01d0*/ BSSY B1, 0x290 ; /* 0x000000b000017945 */
/* 0x000fe20003800000 */
/*01e0*/ FFMA R4, -R0, R5, 1 ; /* 0x3f80000000047423 */
/* 0x002fc80000000105 */
/*01f0*/ FFMA R4, R5, R4, R5 ; /* 0x0000000405047223 */
/* 0x000fe40000000005 */
/*0200*/ FCHK P0, R15, R0 ; /* 0x000000000f007302 */
/* 0x004e640000000000 */
/*0210*/ FFMA R5, R15, R4, RZ ; /* 0x000000040f057223 */
/* 0x000fc800000000ff */
/*0220*/ FFMA R14, -R0, R5, R15 ; /* 0x00000005000e7223 */
/* 0x000fc8000000010f */
/*0230*/ FFMA R4, R4, R14, R5 ; /* 0x0000000e04047223 */
/* 0x000fe20000000005 */
/*0240*/ @!P0 BRA 0x280 ; /* 0x0000003000008947 */
/* 0x003fea0003800000 */
/*0250*/ MOV R4, 0x270 ; /* 0x0000027000047802 */
/* 0x000fe40000000f00 */
/*0260*/ CALL.REL.NOINC 0x8b0 ; /* 0x0000064000007944 */
/* 0x021fea0003c00000 */
/*0270*/ IMAD.MOV.U32 R4, RZ, RZ, R19 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0013 */
/*0280*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0290*/ FADD R13, R4, R13 ; /* 0x0000000d040d7221 */
/* 0x020fe20000000000 */
/*02a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*02b0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*02c0*/ LDG.E R15, [R6.64+0x4] ; /* 0x00000404060f7981 */
/* 0x000ea2000c1e1900 */
/*02d0*/ MUFU.RCP R5, R0 ; /* 0x0000000000057308 */
/* 0x000ee20000001000 */
/*02e0*/ BSSY B1, 0x3a0 ; /* 0x000000b000017945 */
/* 0x000fe20003800000 */
/*02f0*/ FFMA R4, -R0, R5, 1 ; /* 0x3f80000000047423 */
/* 0x008fc80000000105 */
/*0300*/ FFMA R14, R5, R4, R5 ; /* 0x00000004050e7223 */
/* 0x000fe40000000005 */
/*0310*/ FCHK P0, R15, R0 ; /* 0x000000000f007302 */
/* 0x004ea40000000000 */
/*0320*/ FFMA R5, R14, R15, RZ ; /* 0x0000000f0e057223 */
/* 0x000fc800000000ff */
/*0330*/ FFMA R4, -R0, R5, R15 ; /* 0x0000000500047223 */
/* 0x000fc8000000010f */
/*0340*/ FFMA R4, R14, R4, R5 ; /* 0x000000040e047223 */
/* 0x000fe20000000005 */
/*0350*/ @!P0 BRA 0x390 ; /* 0x0000003000008947 */
/* 0x004fea0003800000 */
/*0360*/ MOV R4, 0x380 ; /* 0x0000038000047802 */
/* 0x002fe40000000f00 */
/*0370*/ CALL.REL.NOINC 0x8b0 ; /* 0x0000053000007944 */
/* 0x001fea0003c00000 */
/*0380*/ IMAD.MOV.U32 R4, RZ, RZ, R19 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0013 */
/*0390*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x002fea0003800000 */
/*03a0*/ FADD R13, R13, R4 ; /* 0x000000040d0d7221 */
/* 0x000fe20000000000 */
/*03b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*03c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*03d0*/ LDG.E R15, [R6.64+0x8] ; /* 0x00000804060f7981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ MUFU.RCP R5, R0 ; /* 0x0000000000057308 */
/* 0x000ee20000001000 */
/*03f0*/ BSSY B1, 0x4b0 ; /* 0x000000b000017945 */
/* 0x000fe20003800000 */
/*0400*/ FFMA R4, -R0, R5, 1 ; /* 0x3f80000000047423 */
/* 0x008fc80000000105 */
/*0410*/ FFMA R14, R5, R4, R5 ; /* 0x00000004050e7223 */
/* 0x000fe40000000005 */
/*0420*/ FCHK P0, R15, R0 ; /* 0x000000000f007302 */
/* 0x004ea40000000000 */
/*0430*/ FFMA R5, R14, R15, RZ ; /* 0x0000000f0e057223 */
/* 0x000fc800000000ff */
/*0440*/ FFMA R4, -R0, R5, R15 ; /* 0x0000000500047223 */
/* 0x000fc8000000010f */
/*0450*/ FFMA R4, R14, R4, R5 ; /* 0x000000040e047223 */
/* 0x000fe20000000005 */
/*0460*/ @!P0 BRA 0x4a0 ; /* 0x0000003000008947 */
/* 0x004fea0003800000 */
/*0470*/ MOV R4, 0x490 ; /* 0x0000049000047802 */
/* 0x002fe40000000f00 */
/*0480*/ CALL.REL.NOINC 0x8b0 ; /* 0x0000042000007944 */
/* 0x001fea0003c00000 */
/*0490*/ IMAD.MOV.U32 R4, RZ, RZ, R19 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0013 */
/*04a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x002fea0003800000 */
/*04b0*/ FADD R13, R13, R4 ; /* 0x000000040d0d7221 */
/* 0x000fe20000000000 */
/*04c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*04d0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*04e0*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c04060f7981 */
/* 0x000ea2000c1e1900 */
/*04f0*/ MUFU.RCP R5, R0 ; /* 0x0000000000057308 */
/* 0x000ee20000001000 */
/*0500*/ BSSY B1, 0x5c0 ; /* 0x000000b000017945 */
/* 0x000fe20003800000 */
/*0510*/ FFMA R4, -R0, R5, 1 ; /* 0x3f80000000047423 */
/* 0x008fc80000000105 */
/*0520*/ FFMA R14, R5, R4, R5 ; /* 0x00000004050e7223 */
/* 0x000fe40000000005 */
/*0530*/ FCHK P0, R15, R0 ; /* 0x000000000f007302 */
/* 0x004ea40000000000 */
/*0540*/ FFMA R5, R14, R15, RZ ; /* 0x0000000f0e057223 */
/* 0x000fc800000000ff */
/*0550*/ FFMA R4, -R0, R5, R15 ; /* 0x0000000500047223 */
/* 0x000fc8000000010f */
/*0560*/ FFMA R4, R14, R4, R5 ; /* 0x000000040e047223 */
/* 0x000fe20000000005 */
/*0570*/ @!P0 BRA 0x5b0 ; /* 0x0000003000008947 */
/* 0x004fea0003800000 */
/*0580*/ MOV R4, 0x5a0 ; /* 0x000005a000047802 */
/* 0x002fe40000000f00 */
/*0590*/ CALL.REL.NOINC 0x8b0 ; /* 0x0000031000007944 */
/* 0x001fea0003c00000 */
/*05a0*/ IMAD.MOV.U32 R4, RZ, RZ, R19 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0013 */
/*05b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x002fea0003800000 */
/*05c0*/ IADD3 R12, R12, -0x4, RZ ; /* 0xfffffffc0c0c7810 */
/* 0x000fe20007ffe0ff */
/*05d0*/ FADD R13, R13, R4 ; /* 0x000000040d0d7221 */
/* 0x000fe20000000000 */
/*05e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*05f0*/ IADD3 R6, P1, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007f3e0ff */
/*0600*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f05270 */
/*0610*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e2000c101904 */
/*0620*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007ffe0ff */
/*0630*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fd400008e0607 */
/*0640*/ @P0 BRA 0x1a0 ; /* 0xfffffb5000000947 */
/* 0x002fea000383ffff */
/*0650*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x001fda0003f05270 */
/*0660*/ @!P0 BRA 0x880 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0670*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0680*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000162000c1e1900 */
/*0690*/ IMAD.IADD R10, R10, 0x1, R9 ; /* 0x000000010a0a7824 */
/* 0x000fe400078e0209 */
/*06a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*06b0*/ IMAD R4, R11, c[0x0][0x0], R10 ; /* 0x000000000b047a24 */
/* 0x000fc800078e020a */
/*06c0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*06d0*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*06e0*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x001fc600078e0005 */
/*06f0*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fe20000000f00 */
/*0700*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0710*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0720*/ LDG.E R15, [R4.64] ; /* 0x00000004040f7981 */
/* 0x000ea2000c1e1900 */
/*0730*/ MUFU.RCP R11, R0 ; /* 0x00000000000b7308 */
/* 0x000e220000001000 */
/*0740*/ BSSY B1, 0x800 ; /* 0x000000b000017945 */
/* 0x000fe20003800000 */
/*0750*/ FFMA R10, -R0, R11, 1 ; /* 0x3f800000000a7423 */
/* 0x001fc8000000010b */
/*0760*/ FFMA R12, R11, R10, R11 ; /* 0x0000000a0b0c7223 */
/* 0x000fe4000000000b */
/*0770*/ FCHK P0, R15, R0 ; /* 0x000000000f007302 */
/* 0x004e240000000000 */
/*0780*/ FFMA R11, R12, R15, RZ ; /* 0x0000000f0c0b7223 */
/* 0x000fc800000000ff */
/*0790*/ FFMA R10, -R0, R11, R15 ; /* 0x0000000b000a7223 */
/* 0x000fc8000000010f */
/*07a0*/ FFMA R10, R12, R10, R11 ; /* 0x0000000a0c0a7223 */
/* 0x000fe2000000000b */
/*07b0*/ @!P0 BRA 0x7f0 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*07c0*/ MOV R4, 0x7e0 ; /* 0x000007e000047802 */
/* 0x000fe40000000f00 */
/*07d0*/ CALL.REL.NOINC 0x8b0 ; /* 0x000000d000007944 */
/* 0x020fea0003c00000 */
/*07e0*/ IMAD.MOV.U32 R10, RZ, RZ, R19 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e0013 */
/*07f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0800*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe20007ffe0ff */
/*0810*/ FADD R7, R10, R7 ; /* 0x000000070a077221 */
/* 0x020fe20000000000 */
/*0820*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0830*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f3e0ff */
/*0840*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0850*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*0860*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fd400008e0609 */
/*0870*/ @P0 BRA 0x6f0 ; /* 0xfffffe7000000947 */
/* 0x001fea000383ffff */
/*0880*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0890*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08b0*/ SHF.R.U32.HI R5, RZ, 0x17, R0.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011600 */
/*08c0*/ BSSY B2, 0xf00 ; /* 0x0000063000027945 */
/* 0x000fe20003800000 */
/*08d0*/ SHF.R.U32.HI R16, RZ, 0x17, R15 ; /* 0x00000017ff107819 */
/* 0x000fe2000001160f */
/*08e0*/ IMAD.MOV.U32 R18, RZ, RZ, R0 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0000 */
/*08f0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fc400078ec0ff */
/*0900*/ LOP3.LUT R16, R16, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff10107812 */
/* 0x000fe400078ec0ff */
/*0910*/ IADD3 R19, R5, -0x1, RZ ; /* 0xffffffff05137810 */
/* 0x000fe40007ffe0ff */
/*0920*/ IADD3 R17, R16, -0x1, RZ ; /* 0xffffffff10117810 */
/* 0x000fe40007ffe0ff */
/*0930*/ ISETP.GT.U32.AND P0, PT, R19, 0xfd, PT ; /* 0x000000fd1300780c */
/* 0x000fc80003f04070 */
/*0940*/ ISETP.GT.U32.OR P0, PT, R17, 0xfd, P0 ; /* 0x000000fd1100780c */
/* 0x000fda0000704470 */
/*0950*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e8224 */
/* 0x000fe200078e00ff */
/*0960*/ @!P0 BRA 0xae0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0970*/ FSETP.GTU.FTZ.AND P0, PT, |R15|, +INF , PT ; /* 0x7f8000000f00780b */
/* 0x000fe40003f1c200 */
/*0980*/ FSETP.GTU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fc80003f3c200 */
/*0990*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*09a0*/ @P0 BRA 0xee0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*09b0*/ LOP3.LUT P0, RZ, R18, 0x7fffffff, R15, 0xc8, !PT ; /* 0x7fffffff12ff7812 */
/* 0x000fda000780c80f */
/*09c0*/ @!P0 BRA 0xec0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*09d0*/ FSETP.NEU.FTZ.AND P2, PT, |R15|.reuse, +INF , PT ; /* 0x7f8000000f00780b */
/* 0x040fe40003f5d200 */
/*09e0*/ FSETP.NEU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fe40003f3d200 */
/*09f0*/ FSETP.NEU.FTZ.AND P0, PT, |R15|, +INF , PT ; /* 0x7f8000000f00780b */
/* 0x000fd60003f1d200 */
/*0a00*/ @!P1 BRA !P2, 0xec0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0a10*/ LOP3.LUT P2, RZ, R15, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0fff7812 */
/* 0x000fc8000784c0ff */
/*0a20*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0a30*/ @P1 BRA 0xea0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0a40*/ LOP3.LUT P1, RZ, R18, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff12ff7812 */
/* 0x000fc8000782c0ff */
/*0a50*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0a60*/ @P0 BRA 0xe70 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0a70*/ ISETP.GE.AND P0, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe40003f06270 */
/*0a80*/ ISETP.GE.AND P1, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fd60003f26270 */
/*0a90*/ @P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e0224 */
/* 0x000fe400078e00ff */
/*0aa0*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, -0x40 ; /* 0xffffffc0ff0e8424 */
/* 0x000fe400078e00ff */
/*0ab0*/ @!P0 FFMA R15, R15, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000f0f8823 */
/* 0x000fe400000000ff */
/*0ac0*/ @!P1 FFMA R18, R0, 1.84467440737095516160e+19, RZ ; /* 0x5f80000000129823 */
/* 0x000fe200000000ff */
/*0ad0*/ @!P1 IADD3 R14, R14, 0x40, RZ ; /* 0x000000400e0e9810 */
/* 0x000fe40007ffe0ff */
/*0ae0*/ LEA R17, R5, 0xc0800000, 0x17 ; /* 0xc080000005117811 */
/* 0x000fe200078eb8ff */
/*0af0*/ BSSY B3, 0xe60 ; /* 0x0000036000037945 */
/* 0x000fe20003800000 */
/*0b00*/ IADD3 R16, R16, -0x7f, RZ ; /* 0xffffff8110107810 */
/* 0x000fe40007ffe0ff */
/*0b10*/ IADD3 R21, -R17, R18, RZ ; /* 0x0000001211157210 */
/* 0x000fc60007ffe1ff */
/*0b20*/ IMAD R20, R16.reuse, -0x800000, R15 ; /* 0xff80000010147824 */
/* 0x040fe200078e020f */
/*0b30*/ MUFU.RCP R18, R21 ; /* 0x0000001500127308 */
/* 0x0000620000001000 */
/*0b40*/ FADD.FTZ R17, -R21, -RZ ; /* 0x800000ff15117221 */
/* 0x000fe20000010100 */
/*0b50*/ IADD3 R21, R16, 0x7f, -R5 ; /* 0x0000007f10157810 */
/* 0x001fca0007ffe805 */
/*0b60*/ IMAD.IADD R16, R21, 0x1, R14 ; /* 0x0000000115107824 */
/* 0x000fe400078e020e */
/*0b70*/ FFMA R19, R18, R17, 1 ; /* 0x3f80000012137423 */
/* 0x002fc80000000011 */
/*0b80*/ FFMA R15, R18, R19, R18 ; /* 0x00000013120f7223 */
/* 0x000fc80000000012 */
/*0b90*/ FFMA R18, R20, R15, RZ ; /* 0x0000000f14127223 */
/* 0x000fc800000000ff */
/*0ba0*/ FFMA R19, R17, R18, R20 ; /* 0x0000001211137223 */
/* 0x000fc80000000014 */
/*0bb0*/ FFMA R18, R15, R19, R18 ; /* 0x000000130f127223 */
/* 0x000fc80000000012 */
/*0bc0*/ FFMA R17, R17, R18, R20 ; /* 0x0000001211117223 */
/* 0x000fc80000000014 */
/*0bd0*/ FFMA R19, R15, R17, R18 ; /* 0x000000110f137223 */
/* 0x000fca0000000012 */
/*0be0*/ SHF.R.U32.HI R5, RZ, 0x17, R19 ; /* 0x00000017ff057819 */
/* 0x000fc80000011613 */
/*0bf0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0c00*/ IMAD.IADD R14, R5, 0x1, R16 ; /* 0x00000001050e7824 */
/* 0x000fca00078e0210 */
/*0c10*/ IADD3 R5, R14, -0x1, RZ ; /* 0xffffffff0e057810 */
/* 0x000fc80007ffe0ff */
/*0c20*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0c30*/ @!P0 BRA 0xe40 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0c40*/ ISETP.GT.AND P0, PT, R14, 0xfe, PT ; /* 0x000000fe0e00780c */
/* 0x000fda0003f04270 */
/*0c50*/ @P0 BRA 0xe10 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0c60*/ ISETP.GE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fda0003f06270 */
/*0c70*/ @P0 BRA 0xe50 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0c80*/ ISETP.GE.AND P0, PT, R14, -0x18, PT ; /* 0xffffffe80e00780c */
/* 0x000fe40003f06270 */
/*0c90*/ LOP3.LUT R19, R19, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000013137812 */
/* 0x000fd600078ec0ff */
/*0ca0*/ @!P0 BRA 0xe50 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0cb0*/ FFMA.RZ R5, R15, R17.reuse, R18.reuse ; /* 0x000000110f057223 */
/* 0x180fe2000000c012 */
/*0cc0*/ ISETP.NE.AND P2, PT, R14.reuse, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x040fe40003f45270 */
/*0cd0*/ ISETP.NE.AND P1, PT, R14.reuse, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x040fe40003f25270 */
/*0ce0*/ LOP3.LUT R16, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05107812 */
/* 0x000fe200078ec0ff */
/*0cf0*/ FFMA.RP R5, R15.reuse, R17.reuse, R18.reuse ; /* 0x000000110f057223 */
/* 0x1c0fe40000008012 */
/*0d00*/ FFMA.RM R18, R15, R17, R18 ; /* 0x000000110f127223 */
/* 0x000fe20000004012 */
/*0d10*/ IADD3 R15, R14, 0x20, RZ ; /* 0x000000200e0f7810 */
/* 0x000fe20007ffe0ff */
/*0d20*/ IMAD.MOV R14, RZ, RZ, -R14 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0a0e */
/*0d30*/ LOP3.LUT R16, R16, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000010107812 */
/* 0x000fc400078efcff */
/*0d40*/ FSETP.NEU.FTZ.AND P0, PT, R5, R18, PT ; /* 0x000000120500720b */
/* 0x000fe40003f1d000 */
/*0d50*/ SHF.L.U32 R15, R16, R15, RZ ; /* 0x0000000f100f7219 */
/* 0x000fe400000006ff */
/*0d60*/ SEL R5, R14, RZ, P2 ; /* 0x000000ff0e057207 */
/* 0x000fe40001000000 */
/*0d70*/ ISETP.NE.AND P1, PT, R15, RZ, P1 ; /* 0x000000ff0f00720c */
/* 0x000fe40000f25270 */
/*0d80*/ SHF.R.U32.HI R5, RZ, R5, R16 ; /* 0x00000005ff057219 */
/* 0x000fe40000011610 */
/*0d90*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0da0*/ SHF.R.U32.HI R15, RZ, 0x1, R5 ; /* 0x00000001ff0f7819 */
/* 0x000fe40000011605 */
/*0db0*/ SEL R14, RZ, 0x1, !P0 ; /* 0x00000001ff0e7807 */
/* 0x000fc80004000000 */
/*0dc0*/ LOP3.LUT R14, R14, 0x1, R15, 0xf8, !PT ; /* 0x000000010e0e7812 */
/* 0x000fc800078ef80f */
/*0dd0*/ LOP3.LUT R14, R14, R5, RZ, 0xc0, !PT ; /* 0x000000050e0e7212 */
/* 0x000fca00078ec0ff */
/*0de0*/ IMAD.IADD R14, R15, 0x1, R14 ; /* 0x000000010f0e7824 */
/* 0x000fca00078e020e */
/*0df0*/ LOP3.LUT R19, R14, R19, RZ, 0xfc, !PT ; /* 0x000000130e137212 */
/* 0x000fe200078efcff */
/*0e00*/ BRA 0xe50 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0e10*/ LOP3.LUT R19, R19, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000013137812 */
/* 0x000fc800078ec0ff */
/*0e20*/ LOP3.LUT R19, R19, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000013137812 */
/* 0x000fe200078efcff */
/*0e30*/ BRA 0xe50 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0e40*/ IMAD R19, R16, 0x800000, R19 ; /* 0x0080000010137824 */
/* 0x000fe400078e0213 */
/*0e50*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0e60*/ BRA 0xef0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0e70*/ LOP3.LUT R15, R18, 0x80000000, R15, 0x48, !PT ; /* 0x80000000120f7812 */
/* 0x000fc800078e480f */
/*0e80*/ LOP3.LUT R19, R15, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f8000000f137812 */
/* 0x000fe200078efcff */
/*0e90*/ BRA 0xef0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0ea0*/ LOP3.LUT R19, R18, 0x80000000, R15, 0x48, !PT ; /* 0x8000000012137812 */
/* 0x000fe200078e480f */
/*0eb0*/ BRA 0xef0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0ec0*/ MUFU.RSQ R19, -QNAN ; /* 0xffc0000000137908 */
/* 0x000e220000001400 */
/*0ed0*/ BRA 0xef0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0ee0*/ FADD.FTZ R19, R15, R0 ; /* 0x000000000f137221 */
/* 0x000fe40000010000 */
/*0ef0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0f00*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0f10*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff0e004007950 */
/* 0x000fea0003c3ffff */
/*0f20*/ BRA 0xf20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20computeMovingAveragePKfPfii
.globl _Z20computeMovingAveragePKfPfii
.p2align 8
.type _Z20computeMovingAveragePKfPfii,@function
_Z20computeMovingAveragePKfPfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_sub_i32 s2, s4, s5
s_add_i32 s2, s2, 2
s_cmp_gt_i32 s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_cselect_b32 s2, -1, 0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v5, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s5, 0
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_nc_u32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
global_load_b32 v2, v[6:7], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v6, null, v5, v5, v2
v_div_scale_f32 v9, vcc_lo, v2, v5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v6, v7, 1.0
v_fmac_f32_e32 v7, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v9, v7
v_fma_f32 v10, -v6, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v10, v7
v_fma_f32 v6, -v6, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v6, v6, v7, v8
v_div_fixup_f32 v2, v6, v5, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v0, v2
global_store_b32 v[3:4], v0, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20computeMovingAveragePKfPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20computeMovingAveragePKfPfii, .Lfunc_end0-_Z20computeMovingAveragePKfPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20computeMovingAveragePKfPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20computeMovingAveragePKfPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d2eae_00000000-6_moving_Average.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4927:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4927:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cannot create std::vector larger than max_size()"
.text
.globl _Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii
.type _Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii, @function
_Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii:
.LFB4920:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movslq %edx, %r15
movq %r15, %rax
shrq $61, %rax
jne .L22
movq %rdi, %rbp
movq %rsi, %r12
movl %edx, %r14d
movl %ecx, %ebx
testq %r15, %r15
je .L5
leaq 0(,%r15,4), %r13
movq %r13, %rdi
call _Znwm@PLT
movq %rax, %r8
movl $0x00000000, (%rax)
cmpq $1, %r15
je .L6
leaq (%rax,%r13), %rdx
leaq 4(%rax), %rax
cmpq %rax, %rdx
je .L6
.L7:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L7
.L6:
subl %ebx, %r14d
movl %r14d, %r11d
addl $1, %r11d
js .L16
.L15:
movq %r8, %rsi
leal 1(%r14), %r10d
movslq %ebx, %r9
salq $2, %r9
subq %r8, %r9
movq %r8, %rdx
movl $0, %edi
jmp .L8
.L22:
leaq .LC0(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L11:
movq 0(%rbp), %rcx
leaq (%rcx,%rdi,4), %rax
addq %r9, %rcx
addq %rdx, %rcx
pxor %xmm1, %xmm1
cvtsi2ssl %ebx, %xmm1
.L9:
movss (%rax), %xmm0
divss %xmm1, %xmm0
addss (%rdx), %xmm0
movss %xmm0, (%rdx)
addq $4, %rax
cmpq %rcx, %rax
jne .L9
.L12:
leaq 1(%rdi), %rax
addq $4, %rdx
cmpq %r10, %rdi
je .L10
movq %rax, %rdi
.L8:
testl %ebx, %ebx
jg .L11
jmp .L12
.L10:
movss (%r12), %xmm1
leaq 4(%rsi,%r10,4), %rax
pxor %xmm2, %xmm2
cvtsi2ssl %r11d, %xmm2
.L13:
movss (%rsi), %xmm0
divss %xmm2, %xmm0
addss %xmm0, %xmm1
addq $4, %rsi
cmpq %rax, %rsi
jne .L13
movss %xmm1, (%r12)
testq %r8, %r8
je .L3
.L16:
movq %r13, %rsi
movq %r8, %rdi
call _ZdlPvm@PLT
.L3:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
subl %ecx, %r14d
movq %r15, %r13
movl $0, %r8d
movl %r14d, %r11d
addl $1, %r11d
jns .L15
jmp .L3
.cfi_endproc
.LFE4920:
.size _Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii, .-_Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii
.globl _Z45__device_stub__Z20computeMovingAveragePKfPfiiPKfPfii
.type _Z45__device_stub__Z20computeMovingAveragePKfPfiiPKfPfii, @function
_Z45__device_stub__Z20computeMovingAveragePKfPfiiPKfPfii:
.LFB4949:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20computeMovingAveragePKfPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4949:
.size _Z45__device_stub__Z20computeMovingAveragePKfPfiiPKfPfii, .-_Z45__device_stub__Z20computeMovingAveragePKfPfiiPKfPfii
.globl _Z20computeMovingAveragePKfPfii
.type _Z20computeMovingAveragePKfPfii, @function
_Z20computeMovingAveragePKfPfii:
.LFB4950:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z20computeMovingAveragePKfPfiiPKfPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4950:
.size _Z20computeMovingAveragePKfPfii, .-_Z20computeMovingAveragePKfPfii
.section .rodata.str1.8
.align 8
.LC2:
.string "_Z20computeMovingAveragePKfPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4952:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z20computeMovingAveragePKfPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4952:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEED2Ev
.type _ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB5269:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L36
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L36:
ret
.cfi_endproc
.LFE5269:
.size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
.weak _ZNSt6vectorIfSaIfEED1Ev
.set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
.section .rodata.str1.8
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/wolfatthegate/CS79995-Assignment2/master/moving_Average.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Error at %s:%d\n"
.LC5:
.string "Using Device %d: %s\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Array Size: %d Sample Size: %d\n"
.align 8
.LC8:
.string "Kernel: computeMovingAverage <<<gridDim: %d, blockDim: %d>>>\n"
.align 8
.LC9:
.string "Compute time on GPU: %3.6f ms \n"
.align 8
.LC10:
.string "Compute time on CPU: %3.6f ms \n"
.align 8
.LC11:
.string "Moving Average computed on CPU: %3.6f\n"
.align 8
.LC12:
.string "Moving Average computed on GPU: %3.6f\n"
.text
.globl main
.type main, @function
main:
.LFB4921:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4921
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1208, %rsp
.cfi_def_cfa_offset 1248
movq %fs:40, %rax
movq %rax, 1192(%rsp)
xorl %eax, %eax
leaq 160(%rsp), %rdi
movl $0, %esi
.LEHB0:
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L59
leaq 160(%rsp), %rcx
movl $0, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L60
movl $10, %ecx
movl $10000, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0x00000000, 28(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $40000, %edi
call _Znwm@PLT
.LEHE0:
movq %rax, %r12
movq %rax, 96(%rsp)
leaq 40000(%rax), %rdx
movq %rdx, 112(%rsp)
movl $0x00000000, (%rax)
leaq 4(%rax), %rax
.L43:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L43
movq %rdx, 104(%rsp)
movq $0, 136(%rsp)
movq $0, 144(%rsp)
movl $39960, %edi
.LEHB1:
call _Znwm@PLT
.LEHE1:
jmp .L61
.L59:
movl $55, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB2:
call __printf_chk@PLT
movl $1, %eax
jmp .L39
.L60:
movl $57, %ecx
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.LEHE2:
movl $1, %eax
jmp .L39
.L61:
movq %rax, %rbx
movq %rax, 128(%rsp)
leaq 39960(%rax), %rdx
movq %rdx, 144(%rsp)
movl $0x00000000, (%rax)
leaq 4(%rax), %rax
.L44:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L44
movq %rdx, 136(%rsp)
movq %r12, %rbp
leaq 40000(%r12), %r13
.L45:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp)
addq $4, %rbp
cmpq %r13, %rbp
jne .L45
leaq 40(%rsp), %rdi
movl $40000, %esi
.LEHB3:
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40000, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl $10, 84(%rsp)
movl $1000, 72(%rsp)
movl 80(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 72(%rsp), %rdx
movq 84(%rsp), %rdi
movl 92(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L46
movl $10, %ecx
movl $10000, %edx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z45__device_stub__Z20computeMovingAveragePKfPfiiPKfPfii
.L46:
movl $2, %ecx
movl $40000, %edx
movq 48(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 39968(%rbx), %rdx
movl $0x00000000, 12(%rsp)
movss .LC7(%rip), %xmm1
.L47:
movss (%rax), %xmm0
divss %xmm1, %xmm0
addss 12(%rsp), %xmm0
movss %xmm0, 12(%rsp)
addq $4, %rax
cmpq %rax, %rdx
jne .L47
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 32(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
leaq 28(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $10, %ecx
movl $10000, %edx
call _Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 36(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $1000, %ecx
movl $10, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 32(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
.LEHE3:
leaq 128(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movl $0, %eax
.L39:
movq 1192(%rsp), %rdx
subq %fs:40, %rdx
jne .L62
addq $1208, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 128(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L49:
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 1192(%rsp), %rax
subq %fs:40, %rax
je .L50
call __stack_chk_fail@PLT
.L52:
endbr64
movq %rax, %rbx
jmp .L49
.L50:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L62:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4921:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4921:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4921-.LLSDACSB4921
.LLSDACSB4921:
.uleb128 .LEHB0-.LFB4921
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4921
.uleb128 .LEHE1-.LEHB1
.uleb128 .L52-.LFB4921
.uleb128 0
.uleb128 .LEHB2-.LFB4921
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4921
.uleb128 .LEHE3-.LEHB3
.uleb128 .L53-.LFB4921
.uleb128 0
.uleb128 .LEHB4-.LFB4921
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4921:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1176247296
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "moving_Average.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z35__device_stub__computeMovingAveragePKfPfii # -- Begin function _Z35__device_stub__computeMovingAveragePKfPfii
.p2align 4, 0x90
.type _Z35__device_stub__computeMovingAveragePKfPfii,@function
_Z35__device_stub__computeMovingAveragePKfPfii: # @_Z35__device_stub__computeMovingAveragePKfPfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20computeMovingAveragePKfPfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__computeMovingAveragePKfPfii, .Lfunc_end0-_Z35__device_stub__computeMovingAveragePKfPfii
.cfi_endproc
# -- End function
.globl _Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii # -- Begin function _Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii
.p2align 4, 0x90
.type _Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii,@function
_Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii: # @_Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testl %edx, %edx
js .LBB1_19
# %bb.1: # %_ZNSt6vectorIfSaIfEE17_S_check_init_lenEmRKS0_.exit.i
movl %ecx, %ebp
movl %edx, %r15d
movq %rsi, %rbx
movq %rdi, %r12
movslq %edx, %r13
je .LBB1_2
# %bb.3: # %_ZNSt16allocator_traitsISaIfEE8allocateERS0_m.exit.i.i.i.i
leaq (,%r13,4), %rdi
callq _Znwm
movq %rax, %r14
testl %r15d, %r15d
jne .LBB1_5
jmp .LBB1_7
.LBB1_2:
xorl %r14d, %r14d
testl %r15d, %r15d
je .LBB1_7
.LBB1_5:
movl $0, (%r14)
cmpl $1, %r15d
je .LBB1_7
# %bb.6: # %_ZSt6fill_nIPfmfET_S1_T0_RKT1_.exit.loopexit.i.i.i.i.i
leaq 4(%r14), %rdi
leaq -4(,%r13,4), %rdx
xorl %esi, %esi
callq memset@PLT
.LBB1_7: # %_ZNSt6vectorIfSaIfEEC2EmRKS0_.exit
subl %ebp, %r15d
leal 2(%r15), %eax
cmpl $-1, %r15d
jl .LBB1_13
# %bb.8: # %.preheader30.lr.ph
cvtsi2ss %ebp, %xmm0
movq (%r12), %rcx
cmpl $2, %eax
movl $1, %edx
cmovgel %eax, %edx
movl %ebp, %esi
xorl %edi, %edi
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_12: # %._crit_edge
# in Loop: Header=BB1_9 Depth=1
incq %rdi
addq $4, %rcx
cmpq %rdx, %rdi
je .LBB1_13
.LBB1_9: # %.preheader30
# =>This Loop Header: Depth=1
# Child Loop BB1_11 Depth 2
testl %ebp, %ebp
jle .LBB1_12
# %bb.10: # %.lr.ph
# in Loop: Header=BB1_9 Depth=1
movss (%r14,%rdi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_11: # Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rcx,%r8,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
divss %xmm0, %xmm2
addss %xmm2, %xmm1
movss %xmm1, (%r14,%rdi,4)
incq %r8
cmpq %r8, %rsi
jne .LBB1_11
jmp .LBB1_12
.LBB1_13: # %.preheader
cmpl $-1, %r15d
jl .LBB1_17
# %bb.14: # %.lr.ph37
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
incl %r15d
xorps %xmm1, %xmm1
cvtsi2ss %r15d, %xmm1
cmpl $2, %eax
movl $1, %ecx
cmovgel %eax, %ecx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_15: # =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
divss %xmm1, %xmm2
addss %xmm2, %xmm0
incq %rax
cmpq %rax, %rcx
jne .LBB1_15
# %bb.16: # %._crit_edge38
movss %xmm0, (%rbx)
.LBB1_17:
testq %r14, %r14
je .LBB1_18
# %bb.20:
movq %r14, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.LBB1_18: # %_ZNSt6vectorIfSaIfEED2Ev.exit
.cfi_def_cfa_offset 64
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_19: # %.noexc
.cfi_def_cfa_offset 64
movl $.L.str.9, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end1:
.size _Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii, .Lfunc_end1-_Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x461c1c00 # float 9991
.LCPI2_1:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1640, %rsp # imm = 0x668
.cfi_def_cfa_offset 1680
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
leaq 168(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
je .LBB2_3
# %bb.1:
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $55, %edx
jmp .LBB2_2
.LBB2_3:
.cfi_escape 0x2e, 0x00
leaq 168(%rsp), %rdx
movl $.L.str.2, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
.cfi_escape 0x2e, 0x00
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
je .LBB2_5
# %bb.4:
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $57, %edx
.LBB2_2:
xorl %eax, %eax
callq printf
movl $1, %eax
.LBB2_40:
addq $1640, %rsp # imm = 0x668
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_5: # %_ZNSt6vectorIfSaIfEEC2EmRKS0_.exit
.cfi_def_cfa_offset 1680
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
movl $10000, %esi # imm = 0x2710
movl $10, %edx
xorl %eax, %eax
callq printf
.cfi_escape 0x2e, 0x00
xorl %edi, %edi
callq time
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq srand
.cfi_escape 0x2e, 0x00
movl $40000, %edi # imm = 0x9C40
callq _Znwm
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $40000, %edx # imm = 0x9C40
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $39960, %edi # imm = 0x9C18
callq _Znwm
.Ltmp1:
# %bb.6: # %_ZNSt6vectorIfSaIfEEC2EmRKS0_.exit48
movq %rax, %r14
.cfi_escape 0x2e, 0x00
xorl %r15d, %r15d
movl $39960, %edx # imm = 0x9C18
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB2_7: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r15)
addq $4, %r15
cmpq $40000, %r15 # imm = 0x9C40
jne .LBB2_7
# %bb.8: # %_ZSt8generateIN9__gnu_cxx17__normal_iteratorIPfSt6vectorIfSaIfEEEEZ4mainEUlvE_EvT_S8_T0_.exit
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
.Ltmp4:
# %bb.9: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit
.Ltmp5:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
.Ltmp6:
# %bb.10: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit49
movq 32(%rsp), %rdi
.Ltmp7:
.cfi_escape 0x2e, 0x00
movl $40000, %edx # imm = 0x9C40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp8:
# %bb.11:
.Ltmp10:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq hipEventCreate
.Ltmp11:
# %bb.12:
.Ltmp12:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
callq hipEventCreate
.Ltmp13:
# %bb.13:
movq 16(%rsp), %rdi
.Ltmp14:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp15:
# %bb.14:
.Ltmp16:
.cfi_escape 0x2e, 0x00
movabsq $4294967306, %rdi # imm = 0x10000000A
movabsq $4294968296, %rdx # imm = 0x1000003E8
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp17:
# %bb.15:
testl %eax, %eax
jne .LBB2_18
# %bb.16:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl $10000, 60(%rsp) # imm = 0x2710
movl $10, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 60(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rax
movq %rax, 152(%rsp)
.Ltmp18:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp19:
# %bb.17: # %.noexc
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
.Ltmp20:
.cfi_escape 0x2e, 0x10
leaq 128(%rsp), %r9
movl $_Z20computeMovingAveragePKfPfii, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp21:
.LBB2_18:
movq 24(%rsp), %rsi
.Ltmp22:
.cfi_escape 0x2e, 0x00
movl $40000, %edx # imm = 0x9C40
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp23:
# %bb.19: # %.preheader.preheader
xorps %xmm1, %xmm1
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_20: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_0(%rip), %xmm0
addss %xmm0, %xmm1
incq %rax
cmpq $9992, %rax # imm = 0x2708
jne .LBB2_20
# %bb.21:
movss %xmm1, 44(%rsp) # 4-byte Spill
movq 8(%rsp), %rdi
.Ltmp24:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp25:
# %bb.22:
movq 8(%rsp), %rdi
.Ltmp26:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp27:
# %bb.23:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
.Ltmp28:
.cfi_escape 0x2e, 0x00
leaq 52(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp29:
# %bb.24:
.Ltmp30:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq hipEventCreate
.Ltmp31:
# %bb.25:
.Ltmp32:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
callq hipEventCreate
.Ltmp33:
# %bb.26:
movq 16(%rsp), %rdi
.Ltmp34:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp35:
# %bb.27:
.Ltmp36:
.cfi_escape 0x2e, 0x00
movl $40000, %edi # imm = 0x9C40
callq _Znwm
.Ltmp37:
# %bb.28: # %.noexc52
movq %rax, %r15
.cfi_escape 0x2e, 0x00
xorl %r12d, %r12d
movl $40000, %edx # imm = 0x9C40
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movss .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rbx, %rax
.p2align 4, 0x90
.LBB2_29: # %.preheader30.i
# =>This Loop Header: Depth=1
# Child Loop BB2_30 Depth 2
movss (%r15,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_30: # Parent Loop BB2_29 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rax,%rcx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
divss %xmm0, %xmm2
addss %xmm2, %xmm1
incq %rcx
cmpq $10, %rcx
jne .LBB2_30
# %bb.31: # %._crit_edge.i
# in Loop: Header=BB2_29 Depth=1
movss %xmm1, (%r15,%r12,4)
incq %r12
addq $4, %rax
cmpq $9992, %r12 # imm = 0x2708
jne .LBB2_29
# %bb.32: # %.preheader.i.preheader
xorps %xmm2, %xmm2
xorl %eax, %eax
movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB2_33: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movss (%r15,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss %xmm1, %xmm0
addss %xmm0, %xmm2
incq %rax
cmpq $9992, %rax # imm = 0x2708
jne .LBB2_33
# %bb.34: # %_Z25computeMovingAverageOnCPURSt6vectorIfSaIfEERfii.exit
movss %xmm2, 40(%rsp) # 4-byte Spill
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
movq 8(%rsp), %rdi
.Ltmp38:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp39:
# %bb.35:
movq 8(%rsp), %rdi
.Ltmp40:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp41:
# %bb.36:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
.Ltmp42:
.cfi_escape 0x2e, 0x00
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp43:
# %bb.37:
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %edi
movl $10, %esi
movl $1000, %edx # imm = 0x3E8
xorl %eax, %eax
callq printf
movss 52(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %edi
movb $1, %al
callq printf
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %edi
movb $1, %al
callq printf
movss 40(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str.7, %edi
movb $1, %al
callq printf
movss 44(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str.8, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
.Ltmp44:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp45:
# %bb.38:
movq 24(%rsp), %rdi
.Ltmp46:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp47:
# %bb.39: # %_ZNSt6vectorIfSaIfEED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
jmp .LBB2_40
.LBB2_41:
.Ltmp2:
movq %rax, %r15
jmp .LBB2_45
.LBB2_43:
.Ltmp9:
jmp .LBB2_44
.LBB2_42:
.Ltmp48:
.LBB2_44: # %_ZNSt6vectorIfSaIfEED2Ev.exit56
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB2_45: # %_ZNSt6vectorIfSaIfEED2Ev.exit58
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp8-.Ltmp3 # Call between .Ltmp3 and .Ltmp8
.uleb128 .Ltmp9-.Lfunc_begin0 # jumps to .Ltmp9
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp37-.Ltmp10 # Call between .Ltmp10 and .Ltmp37
.uleb128 .Ltmp48-.Lfunc_begin0 # jumps to .Ltmp48
.byte 0 # On action: cleanup
.uleb128 .Ltmp37-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp38-.Ltmp37 # Call between .Ltmp37 and .Ltmp38
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp38-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp47-.Ltmp38 # Call between .Ltmp38 and .Ltmp47
.uleb128 .Ltmp48-.Lfunc_begin0 # jumps to .Ltmp48
.byte 0 # On action: cleanup
.uleb128 .Ltmp47-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Lfunc_end2-.Ltmp47 # Call between .Ltmp47 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20computeMovingAveragePKfPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20computeMovingAveragePKfPfii,@object # @_Z20computeMovingAveragePKfPfii
.section .rodata,"a",@progbits
.globl _Z20computeMovingAveragePKfPfii
.p2align 3, 0x0
_Z20computeMovingAveragePKfPfii:
.quad _Z35__device_stub__computeMovingAveragePKfPfii
.size _Z20computeMovingAveragePKfPfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error at %s:%d\n"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/wolfatthegate/CS79995-Assignment2/master/moving_Average.hip"
.size .L.str.1, 117
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Using Device %d: %s\n"
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Array Size: %d Sample Size: %d\n"
.size .L.str.3, 33
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Kernel: computeMovingAverage <<<gridDim: %d, blockDim: %d>>>\n"
.size .L.str.4, 62
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Compute time on GPU: %3.6f ms \n"
.size .L.str.5, 32
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Compute time on CPU: %3.6f ms \n"
.size .L.str.6, 32
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Moving Average computed on CPU: %3.6f\n"
.size .L.str.7, 39
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Moving Average computed on GPU: %3.6f\n"
.size .L.str.8, 39
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "cannot create std::vector larger than max_size()"
.size .L.str.9, 49
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20computeMovingAveragePKfPfii"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__computeMovingAveragePKfPfii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z20computeMovingAveragePKfPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Single Author info:
yjkamdar Yash J Kamdar
Group info:
vphadke Vandan V Phadke
angodse Anupam N Godse
*/
#include <stdlib.h>
#include <stdio.h>
#include <cuda_runtime.h>
#include <time.h>
#define __DEBUG
#define VSQR 0.1
#define TSCALE 1.0
#define CUDA_CALL( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__,__LINE__)
/**************************************
* void __cudaSafeCall(cudaError err, const char *file, const int line)
* void __cudaCheckError(const char *file, const int line)
*
* These routines were taken from the GPU Computing SDK
* (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
**************************************/
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
cudaError_t err = cudaGetLastError();
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment if not needed.
/*err = cudaThreadSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}*/
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
int tpdt(double *t, double dt, double tf)
{
if((*t) + dt > tf) return 0;
(*t) = (*t) + dt;
return 1;
}
/*9-point evolution of the grid using the GPU*/
__global__ void evolve9ptgpu(double *un, double *uc, double *uo, double *pebbles, int n, double h, double dt, double t){
/*Calculate the index of the current grid point calculation*/
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int totalLength = n*n;
/*Boudary conditions for the grid*/
if (idx >= 0 && idx < totalLength) {
if((idx % n == 0) || ((idx + 1) % n == 0) || idx < n || idx > n*(n-1) - 1)
{
un[idx] = 0;
}
/*Calculate grid point value using the 9-point scale*/
else
{
un[idx] = 2*uc[idx] - uo[idx] + VSQR *(dt * dt) *((uc[idx-1] + uc[idx+1] +
uc[idx + n] + uc[idx - n] + 0.25 * (uc[idx -n - 1] + uc[idx - n + 1] +
uc[idx -1 + n] + uc[idx + 1 + n]) - 5 * uc[idx])/(h * h)
+ (-1 * __expf(-TSCALE * t) * pebbles[idx]));
}
}
}
__global__ void evolvegpu(double *un, double *uc, double *uo, double *pebbles, int n, double h, double dt, double t){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int totalLength = n*n;
if (idx >= 0 && idx < totalLength) {
if((idx % n == 0) || ((idx + 1) % n == 0) || idx < n || idx > n*(n-1) - 1)
{
un[idx] = 0;
}
else
{
un[idx] = 2*uc[idx] - uo[idx] + VSQR *(dt * dt) *((uc[idx-1] + uc[idx+1] +
uc[idx + n] + uc[idx - n] - 4 * uc[idx])/(h * h) + (__expf(-TSCALE * t) * pebbles[idx]));
}
}
}
void run_gpu(double *u, double *u0, double *u1, double *pebbles, int n, double h, double end_time, int nthreads)
{
cudaEvent_t kstart, kstop;
float ktime;
/* HW2: Define your local variables here */
int nBlocks = n / nthreads;
double t, dt;
double *uc, *uo;
double *un_d, *uc_d, *uo_d, *pebbles_d;
uc = (double*)malloc(sizeof(double) * n * n);
uo = (double*)malloc(sizeof(double) * n * n);
t = 0.;
dt = h / 2.;
memcpy(uo, u0, sizeof(double) * n * n);
memcpy(uc, u1, sizeof(double) * n * n);
/* Set up device timers */
CUDA_CALL(cudaSetDevice(0));
CUDA_CALL(cudaEventCreate(&kstart));
CUDA_CALL(cudaEventCreate(&kstop));
/* HW2: Add CUDA kernel call preperation code here */
cudaMalloc((void **) &un_d, sizeof(double) * n * n);
cudaMalloc((void **) &uc_d, sizeof(double) * n * n);
cudaMalloc((void **) &uo_d, sizeof(double) * n * n);
cudaMalloc((void **) &pebbles_d, sizeof(double) * n * n);
cudaMemcpy(pebbles_d, pebbles, sizeof(double) * n * n, cudaMemcpyHostToDevice);
/* Start GPU computation timer */
CUDA_CALL(cudaEventRecord(kstart, 0));
/* HW2: Add main lake simulation loop here */
while(1)
{
cudaMemcpy(uo_d, uo, sizeof(double) * n * n, cudaMemcpyHostToDevice);
cudaMemcpy(uc_d, uc, sizeof(double) * n * n, cudaMemcpyHostToDevice);
evolve9ptgpu<<<nBlocks*nBlocks, nthreads*nthreads>>>(un_d, uc_d, uo_d, pebbles_d, n, h, dt, t);
//evolvegpu<<<nBlocks*nBlocks, nthreads*nthreads>>>(un_d, uc_d, uo_d, pebbles_d, n, h, dt, t);
cudaMemcpy(uo, uc_d, sizeof(double) * n * n, cudaMemcpyDeviceToHost);
cudaMemcpy(uc, un_d, sizeof(double) * n * n, cudaMemcpyDeviceToHost);
if(!tpdt(&t,dt,end_time)) break;
}
memcpy(u, uc, sizeof(double) * n * n);
/* Stop GPU computation timer */
CUDA_CALL(cudaEventRecord(kstop, 0));
CUDA_CALL(cudaEventSynchronize(kstop));
CUDA_CALL(cudaEventElapsedTime(&ktime, kstart, kstop));
printf("GPU computation: %f msec\n", ktime);
/* HW2: Add post CUDA kernel call processing and cleanup here */
free(uc);
free(uo);
cudaFree(un_d);
cudaFree(uc_d);
cudaFree(uo_d);
/* timer cleanup */
CUDA_CALL(cudaEventDestroy(kstart));
CUDA_CALL(cudaEventDestroy(kstop));
} | .file "tmpxft_000c62bc_00000000-6_lakegpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4tpdtPddd
.type _Z4tpdtPddd, @function
_Z4tpdtPddd:
.LFB2059:
.cfi_startproc
endbr64
addsd (%rdi), %xmm0
movl $0, %eax
comisd %xmm1, %xmm0
ja .L3
movsd %xmm0, (%rdi)
movl $1, %eax
.L3:
ret
.cfi_endproc
.LFE2059:
.size _Z4tpdtPddd, .-_Z4tpdtPddd
.globl _Z42__device_stub__Z12evolve9ptgpuPdS_S_S_idddPdS_S_S_iddd
.type _Z42__device_stub__Z12evolve9ptgpuPdS_S_S_idddPdS_S_S_iddd, @function
_Z42__device_stub__Z12evolve9ptgpuPdS_S_S_idddPdS_S_S_iddd:
.LFB2085:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movl %r8d, 28(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movsd %xmm2, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z12evolve9ptgpuPdS_S_S_iddd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z42__device_stub__Z12evolve9ptgpuPdS_S_S_idddPdS_S_S_iddd, .-_Z42__device_stub__Z12evolve9ptgpuPdS_S_S_idddPdS_S_S_iddd
.globl _Z12evolve9ptgpuPdS_S_S_iddd
.type _Z12evolve9ptgpuPdS_S_S_iddd, @function
_Z12evolve9ptgpuPdS_S_S_iddd:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z12evolve9ptgpuPdS_S_S_idddPdS_S_S_iddd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z12evolve9ptgpuPdS_S_S_iddd, .-_Z12evolve9ptgpuPdS_S_S_iddd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/anupamgodse/Parallel-Systems-Fall-2018/master/HW2/p3/lakegpu.cu"
.align 8
.LC3:
.string "cudaSafeCall() failed at %s:%i : %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "GPU computation: %f msec\n"
.text
.globl _Z7run_gpuPdS_S_S_iddi
.type _Z7run_gpuPdS_S_S_iddi, @function
_Z7run_gpuPdS_S_S_iddi:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 8(%rsp)
movq %rdx, 48(%rsp)
movq %rcx, 56(%rsp)
movl %r8d, %r15d
movsd %xmm0, 32(%rsp)
movsd %xmm1, 24(%rsp)
movl %r9d, %r13d
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl %r8d, %eax
cltd
idivl %r9d
movl %eax, %r14d
movslq %r8d, %rbx
imulq %rbx, %rbx
salq $3, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movsd 32(%rsp), %xmm6
mulsd .LC1(%rip), %xmm6
movsd %xmm6, 16(%rsp)
movq %rbx, %rcx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %rax, %rdi
call __memcpy_chk@PLT
movq %rbx, %rcx
movq %rbx, %rdx
movq 48(%rsp), %rsi
movq %rbp, %rdi
call __memcpy_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L30
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L31
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L32
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 56(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L33
imull %r13d, %r13d
imull %r14d, %r14d
movq $0x000000000, 8(%rsp)
.L20:
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl %r13d, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl %r14d, 112(%rsp)
movl $1, 116(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L19:
movl $2, %ecx
movq %rbx, %rdx
movq 88(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movsd 8(%rsp), %xmm3
addsd 16(%rsp), %xmm3
movsd %xmm3, 8(%rsp)
comisd 24(%rsp), %xmm3
jbe .L20
movq %rbx, %rdx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call memcpy@PLT
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L35
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
testl %eax, %eax
jne .L36
leaq 124(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L37
pxor %xmm0, %xmm0
cvtss2sd 124(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaEventDestroy@PLT
testl %eax, %eax
jne .L38
movq 72(%rsp), %rdi
call cudaEventDestroy@PLT
testl %eax, %eax
jne .L39
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $153, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $154, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $155, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $166, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L34:
movsd 8(%rsp), %xmm2
movsd 16(%rsp), %xmm1
movsd 32(%rsp), %xmm0
movl %r15d, %r8d
movq 104(%rsp), %rcx
movq 96(%rsp), %rdx
movq 88(%rsp), %rsi
movq 80(%rsp), %rdi
call _Z42__device_stub__Z12evolve9ptgpuPdS_S_S_idddPdS_S_S_iddd
jmp .L19
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $186, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $187, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $188, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $199, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L39:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $200, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z7run_gpuPdS_S_S_iddi, .-_Z7run_gpuPdS_S_S_iddi
.globl _Z38__device_stub__Z9evolvegpuPdS_S_S_idddPdS_S_S_iddd
.type _Z38__device_stub__Z9evolvegpuPdS_S_S_idddPdS_S_S_iddd, @function
_Z38__device_stub__Z9evolvegpuPdS_S_S_idddPdS_S_S_iddd:
.LFB2087:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movl %r8d, 28(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movsd %xmm2, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z9evolvegpuPdS_S_S_iddd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z38__device_stub__Z9evolvegpuPdS_S_S_idddPdS_S_S_iddd, .-_Z38__device_stub__Z9evolvegpuPdS_S_S_idddPdS_S_S_iddd
.globl _Z9evolvegpuPdS_S_S_iddd
.type _Z9evolvegpuPdS_S_S_iddd, @function
_Z9evolvegpuPdS_S_S_iddd:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z9evolvegpuPdS_S_S_idddPdS_S_S_iddd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z9evolvegpuPdS_S_S_iddd, .-_Z9evolvegpuPdS_S_S_iddd
.section .rodata.str1.1
.LC5:
.string "_Z9evolvegpuPdS_S_S_iddd"
.LC6:
.string "_Z12evolve9ptgpuPdS_S_S_iddd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9evolvegpuPdS_S_S_iddd(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z12evolve9ptgpuPdS_S_S_iddd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1071644672
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Single Author info:
yjkamdar Yash J Kamdar
Group info:
vphadke Vandan V Phadke
angodse Anupam N Godse
*/
#include <stdlib.h>
#include <stdio.h>
#include <cuda_runtime.h>
#include <time.h>
#define __DEBUG
#define VSQR 0.1
#define TSCALE 1.0
#define CUDA_CALL( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__,__LINE__)
/**************************************
* void __cudaSafeCall(cudaError err, const char *file, const int line)
* void __cudaCheckError(const char *file, const int line)
*
* These routines were taken from the GPU Computing SDK
* (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
**************************************/
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
cudaError_t err = cudaGetLastError();
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment if not needed.
/*err = cudaThreadSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}*/
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
int tpdt(double *t, double dt, double tf)
{
if((*t) + dt > tf) return 0;
(*t) = (*t) + dt;
return 1;
}
/*9-point evolution of the grid using the GPU*/
__global__ void evolve9ptgpu(double *un, double *uc, double *uo, double *pebbles, int n, double h, double dt, double t){
/*Calculate the index of the current grid point calculation*/
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int totalLength = n*n;
/*Boudary conditions for the grid*/
if (idx >= 0 && idx < totalLength) {
if((idx % n == 0) || ((idx + 1) % n == 0) || idx < n || idx > n*(n-1) - 1)
{
un[idx] = 0;
}
/*Calculate grid point value using the 9-point scale*/
else
{
un[idx] = 2*uc[idx] - uo[idx] + VSQR *(dt * dt) *((uc[idx-1] + uc[idx+1] +
uc[idx + n] + uc[idx - n] + 0.25 * (uc[idx -n - 1] + uc[idx - n + 1] +
uc[idx -1 + n] + uc[idx + 1 + n]) - 5 * uc[idx])/(h * h)
+ (-1 * __expf(-TSCALE * t) * pebbles[idx]));
}
}
}
__global__ void evolvegpu(double *un, double *uc, double *uo, double *pebbles, int n, double h, double dt, double t){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int totalLength = n*n;
if (idx >= 0 && idx < totalLength) {
if((idx % n == 0) || ((idx + 1) % n == 0) || idx < n || idx > n*(n-1) - 1)
{
un[idx] = 0;
}
else
{
un[idx] = 2*uc[idx] - uo[idx] + VSQR *(dt * dt) *((uc[idx-1] + uc[idx+1] +
uc[idx + n] + uc[idx - n] - 4 * uc[idx])/(h * h) + (__expf(-TSCALE * t) * pebbles[idx]));
}
}
}
void run_gpu(double *u, double *u0, double *u1, double *pebbles, int n, double h, double end_time, int nthreads)
{
cudaEvent_t kstart, kstop;
float ktime;
/* HW2: Define your local variables here */
int nBlocks = n / nthreads;
double t, dt;
double *uc, *uo;
double *un_d, *uc_d, *uo_d, *pebbles_d;
uc = (double*)malloc(sizeof(double) * n * n);
uo = (double*)malloc(sizeof(double) * n * n);
t = 0.;
dt = h / 2.;
memcpy(uo, u0, sizeof(double) * n * n);
memcpy(uc, u1, sizeof(double) * n * n);
/* Set up device timers */
CUDA_CALL(cudaSetDevice(0));
CUDA_CALL(cudaEventCreate(&kstart));
CUDA_CALL(cudaEventCreate(&kstop));
/* HW2: Add CUDA kernel call preperation code here */
cudaMalloc((void **) &un_d, sizeof(double) * n * n);
cudaMalloc((void **) &uc_d, sizeof(double) * n * n);
cudaMalloc((void **) &uo_d, sizeof(double) * n * n);
cudaMalloc((void **) &pebbles_d, sizeof(double) * n * n);
cudaMemcpy(pebbles_d, pebbles, sizeof(double) * n * n, cudaMemcpyHostToDevice);
/* Start GPU computation timer */
CUDA_CALL(cudaEventRecord(kstart, 0));
/* HW2: Add main lake simulation loop here */
while(1)
{
cudaMemcpy(uo_d, uo, sizeof(double) * n * n, cudaMemcpyHostToDevice);
cudaMemcpy(uc_d, uc, sizeof(double) * n * n, cudaMemcpyHostToDevice);
evolve9ptgpu<<<nBlocks*nBlocks, nthreads*nthreads>>>(un_d, uc_d, uo_d, pebbles_d, n, h, dt, t);
//evolvegpu<<<nBlocks*nBlocks, nthreads*nthreads>>>(un_d, uc_d, uo_d, pebbles_d, n, h, dt, t);
cudaMemcpy(uo, uc_d, sizeof(double) * n * n, cudaMemcpyDeviceToHost);
cudaMemcpy(uc, un_d, sizeof(double) * n * n, cudaMemcpyDeviceToHost);
if(!tpdt(&t,dt,end_time)) break;
}
memcpy(u, uc, sizeof(double) * n * n);
/* Stop GPU computation timer */
CUDA_CALL(cudaEventRecord(kstop, 0));
CUDA_CALL(cudaEventSynchronize(kstop));
CUDA_CALL(cudaEventElapsedTime(&ktime, kstart, kstop));
printf("GPU computation: %f msec\n", ktime);
/* HW2: Add post CUDA kernel call processing and cleanup here */
free(uc);
free(uo);
cudaFree(un_d);
cudaFree(uc_d);
cudaFree(uo_d);
/* timer cleanup */
CUDA_CALL(cudaEventDestroy(kstart));
CUDA_CALL(cudaEventDestroy(kstop));
} | /*
Single Author info:
yjkamdar Yash J Kamdar
Group info:
vphadke Vandan V Phadke
angodse Anupam N Godse
*/
#include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define __DEBUG
#define VSQR 0.1
#define TSCALE 1.0
#define CUDA_CALL( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__,__LINE__)
/**************************************
* void __cudaSafeCall(cudaError err, const char *file, const int line)
* void __cudaCheckError(const char *file, const int line)
*
* These routines were taken from the GPU Computing SDK
* (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
**************************************/
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s.\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment if not needed.
/*err = cudaThreadSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}*/
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
int tpdt(double *t, double dt, double tf)
{
if((*t) + dt > tf) return 0;
(*t) = (*t) + dt;
return 1;
}
/*9-point evolution of the grid using the GPU*/
__global__ void evolve9ptgpu(double *un, double *uc, double *uo, double *pebbles, int n, double h, double dt, double t){
/*Calculate the index of the current grid point calculation*/
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int totalLength = n*n;
/*Boudary conditions for the grid*/
if (idx >= 0 && idx < totalLength) {
if((idx % n == 0) || ((idx + 1) % n == 0) || idx < n || idx > n*(n-1) - 1)
{
un[idx] = 0;
}
/*Calculate grid point value using the 9-point scale*/
else
{
un[idx] = 2*uc[idx] - uo[idx] + VSQR *(dt * dt) *((uc[idx-1] + uc[idx+1] +
uc[idx + n] + uc[idx - n] + 0.25 * (uc[idx -n - 1] + uc[idx - n + 1] +
uc[idx -1 + n] + uc[idx + 1 + n]) - 5 * uc[idx])/(h * h)
+ (-1 * __expf(-TSCALE * t) * pebbles[idx]));
}
}
}
__global__ void evolvegpu(double *un, double *uc, double *uo, double *pebbles, int n, double h, double dt, double t){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int totalLength = n*n;
if (idx >= 0 && idx < totalLength) {
if((idx % n == 0) || ((idx + 1) % n == 0) || idx < n || idx > n*(n-1) - 1)
{
un[idx] = 0;
}
else
{
un[idx] = 2*uc[idx] - uo[idx] + VSQR *(dt * dt) *((uc[idx-1] + uc[idx+1] +
uc[idx + n] + uc[idx - n] - 4 * uc[idx])/(h * h) + (__expf(-TSCALE * t) * pebbles[idx]));
}
}
}
void run_gpu(double *u, double *u0, double *u1, double *pebbles, int n, double h, double end_time, int nthreads)
{
hipEvent_t kstart, kstop;
float ktime;
/* HW2: Define your local variables here */
int nBlocks = n / nthreads;
double t, dt;
double *uc, *uo;
double *un_d, *uc_d, *uo_d, *pebbles_d;
uc = (double*)malloc(sizeof(double) * n * n);
uo = (double*)malloc(sizeof(double) * n * n);
t = 0.;
dt = h / 2.;
memcpy(uo, u0, sizeof(double) * n * n);
memcpy(uc, u1, sizeof(double) * n * n);
/* Set up device timers */
CUDA_CALL(hipSetDevice(0));
CUDA_CALL(hipEventCreate(&kstart));
CUDA_CALL(hipEventCreate(&kstop));
/* HW2: Add CUDA kernel call preperation code here */
hipMalloc((void **) &un_d, sizeof(double) * n * n);
hipMalloc((void **) &uc_d, sizeof(double) * n * n);
hipMalloc((void **) &uo_d, sizeof(double) * n * n);
hipMalloc((void **) &pebbles_d, sizeof(double) * n * n);
hipMemcpy(pebbles_d, pebbles, sizeof(double) * n * n, hipMemcpyHostToDevice);
/* Start GPU computation timer */
CUDA_CALL(hipEventRecord(kstart, 0));
/* HW2: Add main lake simulation loop here */
while(1)
{
hipMemcpy(uo_d, uo, sizeof(double) * n * n, hipMemcpyHostToDevice);
hipMemcpy(uc_d, uc, sizeof(double) * n * n, hipMemcpyHostToDevice);
evolve9ptgpu<<<nBlocks*nBlocks, nthreads*nthreads>>>(un_d, uc_d, uo_d, pebbles_d, n, h, dt, t);
//evolvegpu<<<nBlocks*nBlocks, nthreads*nthreads>>>(un_d, uc_d, uo_d, pebbles_d, n, h, dt, t);
hipMemcpy(uo, uc_d, sizeof(double) * n * n, hipMemcpyDeviceToHost);
hipMemcpy(uc, un_d, sizeof(double) * n * n, hipMemcpyDeviceToHost);
if(!tpdt(&t,dt,end_time)) break;
}
memcpy(u, uc, sizeof(double) * n * n);
/* Stop GPU computation timer */
CUDA_CALL(hipEventRecord(kstop, 0));
CUDA_CALL(hipEventSynchronize(kstop));
CUDA_CALL(hipEventElapsedTime(&ktime, kstart, kstop));
printf("GPU computation: %f msec\n", ktime);
/* HW2: Add post CUDA kernel call processing and cleanup here */
free(uc);
free(uo);
hipFree(un_d);
hipFree(uc_d);
hipFree(uo_d);
/* timer cleanup */
CUDA_CALL(hipEventDestroy(kstart));
CUDA_CALL(hipEventDestroy(kstop));
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Single Author info:
yjkamdar Yash J Kamdar
Group info:
vphadke Vandan V Phadke
angodse Anupam N Godse
*/
#include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define __DEBUG
#define VSQR 0.1
#define TSCALE 1.0
#define CUDA_CALL( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__,__LINE__)
/**************************************
* void __cudaSafeCall(cudaError err, const char *file, const int line)
* void __cudaCheckError(const char *file, const int line)
*
* These routines were taken from the GPU Computing SDK
* (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
**************************************/
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s.\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment if not needed.
/*err = cudaThreadSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}*/
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
int tpdt(double *t, double dt, double tf)
{
if((*t) + dt > tf) return 0;
(*t) = (*t) + dt;
return 1;
}
/*9-point evolution of the grid using the GPU*/
__global__ void evolve9ptgpu(double *un, double *uc, double *uo, double *pebbles, int n, double h, double dt, double t){
/*Calculate the index of the current grid point calculation*/
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int totalLength = n*n;
/*Boudary conditions for the grid*/
if (idx >= 0 && idx < totalLength) {
if((idx % n == 0) || ((idx + 1) % n == 0) || idx < n || idx > n*(n-1) - 1)
{
un[idx] = 0;
}
/*Calculate grid point value using the 9-point scale*/
else
{
un[idx] = 2*uc[idx] - uo[idx] + VSQR *(dt * dt) *((uc[idx-1] + uc[idx+1] +
uc[idx + n] + uc[idx - n] + 0.25 * (uc[idx -n - 1] + uc[idx - n + 1] +
uc[idx -1 + n] + uc[idx + 1 + n]) - 5 * uc[idx])/(h * h)
+ (-1 * __expf(-TSCALE * t) * pebbles[idx]));
}
}
}
__global__ void evolvegpu(double *un, double *uc, double *uo, double *pebbles, int n, double h, double dt, double t){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int totalLength = n*n;
if (idx >= 0 && idx < totalLength) {
if((idx % n == 0) || ((idx + 1) % n == 0) || idx < n || idx > n*(n-1) - 1)
{
un[idx] = 0;
}
else
{
un[idx] = 2*uc[idx] - uo[idx] + VSQR *(dt * dt) *((uc[idx-1] + uc[idx+1] +
uc[idx + n] + uc[idx - n] - 4 * uc[idx])/(h * h) + (__expf(-TSCALE * t) * pebbles[idx]));
}
}
}
void run_gpu(double *u, double *u0, double *u1, double *pebbles, int n, double h, double end_time, int nthreads)
{
hipEvent_t kstart, kstop;
float ktime;
/* HW2: Define your local variables here */
int nBlocks = n / nthreads;
double t, dt;
double *uc, *uo;
double *un_d, *uc_d, *uo_d, *pebbles_d;
uc = (double*)malloc(sizeof(double) * n * n);
uo = (double*)malloc(sizeof(double) * n * n);
t = 0.;
dt = h / 2.;
memcpy(uo, u0, sizeof(double) * n * n);
memcpy(uc, u1, sizeof(double) * n * n);
/* Set up device timers */
CUDA_CALL(hipSetDevice(0));
CUDA_CALL(hipEventCreate(&kstart));
CUDA_CALL(hipEventCreate(&kstop));
/* HW2: Add CUDA kernel call preperation code here */
hipMalloc((void **) &un_d, sizeof(double) * n * n);
hipMalloc((void **) &uc_d, sizeof(double) * n * n);
hipMalloc((void **) &uo_d, sizeof(double) * n * n);
hipMalloc((void **) &pebbles_d, sizeof(double) * n * n);
hipMemcpy(pebbles_d, pebbles, sizeof(double) * n * n, hipMemcpyHostToDevice);
/* Start GPU computation timer */
CUDA_CALL(hipEventRecord(kstart, 0));
/* HW2: Add main lake simulation loop here */
while(1)
{
hipMemcpy(uo_d, uo, sizeof(double) * n * n, hipMemcpyHostToDevice);
hipMemcpy(uc_d, uc, sizeof(double) * n * n, hipMemcpyHostToDevice);
evolve9ptgpu<<<nBlocks*nBlocks, nthreads*nthreads>>>(un_d, uc_d, uo_d, pebbles_d, n, h, dt, t);
//evolvegpu<<<nBlocks*nBlocks, nthreads*nthreads>>>(un_d, uc_d, uo_d, pebbles_d, n, h, dt, t);
hipMemcpy(uo, uc_d, sizeof(double) * n * n, hipMemcpyDeviceToHost);
hipMemcpy(uc, un_d, sizeof(double) * n * n, hipMemcpyDeviceToHost);
if(!tpdt(&t,dt,end_time)) break;
}
memcpy(u, uc, sizeof(double) * n * n);
/* Stop GPU computation timer */
CUDA_CALL(hipEventRecord(kstop, 0));
CUDA_CALL(hipEventSynchronize(kstop));
CUDA_CALL(hipEventElapsedTime(&ktime, kstart, kstop));
printf("GPU computation: %f msec\n", ktime);
/* HW2: Add post CUDA kernel call processing and cleanup here */
free(uc);
free(uo);
hipFree(un_d);
hipFree(uc_d);
hipFree(uo_d);
/* timer cleanup */
CUDA_CALL(hipEventDestroy(kstart));
CUDA_CALL(hipEventDestroy(kstop));
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12evolve9ptgpuPdS_S_S_iddd
.globl _Z12evolve9ptgpuPdS_S_S_iddd
.p2align 8
.type _Z12evolve9ptgpuPdS_S_S_iddd,@function
_Z12evolve9ptgpuPdS_S_S_iddd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4c
s_load_b32 s10, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s10, s10
v_cmp_lt_i32_e32 vcc_lo, -1, v1
v_cmp_gt_i32_e64 s2, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_10
s_ashr_i32 s2, s10, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s3, s10, s2
s_mov_b32 s8, exec_lo
s_xor_b32 s3, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s2, 0, s3
v_xor_b32_e32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s2, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v2, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s3
v_sub_nc_u32_e32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v3
v_sub_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e64 s2, 0, v2
v_cmpx_ne_u32_e32 0, v2
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v3, 1, v1
s_mov_b32 s4, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v3
v_add_nc_u32_e32 v4, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v4, v2
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s3
v_sub_nc_u32_e32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s3, v0
v_cmp_le_u32_e32 vcc_lo, s3, v0
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v4, s3, v0
v_cmp_le_u32_e32 vcc_lo, s3, v0
v_cmp_gt_i32_e64 s3, s10, v1
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v2
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_or_b32 s3, s3, vcc_lo
s_xor_b32 s5, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s9, s5
s_cbranch_execz .LBB0_6
s_add_i32 s5, s10, -1
s_mov_b32 s11, exec_lo
s_mul_i32 s5, s5, s10
s_delay_alu instid0(SALU_CYCLE_1)
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[16:17], s[0:1], 0x18
v_add_nc_u32_e32 v8, -1, v1
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v15, s10, v1
v_subrev_nc_u32_e32 v5, s10, v1
v_add_nc_u32_e32 v19, s10, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v9, 31, v8
v_dual_mov_b32 v4, v2 :: v_dual_add_nc_u32 v17, s10, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v16, 31, v15
v_lshlrev_b64 v[9:10], 3, v[8:9]
s_delay_alu instid0(VALU_DEP_4)
v_lshlrev_b64 v[11:12], 3, v[3:4]
v_ashrrev_i32_e32 v18, 31, v17
v_lshlrev_b64 v[4:5], 3, v[5:6]
v_lshlrev_b64 v[15:16], 3, v[15:16]
v_ashrrev_i32_e32 v20, 31, v19
v_lshlrev_b64 v[21:22], 3, v[1:2]
v_lshlrev_b64 v[17:18], 3, v[17:18]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v12, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v5, vcc_lo
s_clause 0x3
global_load_b64 v[13:14], v[6:7], off
global_load_b64 v[9:10], v[9:10], off
global_load_b128 v[4:7], v[11:12], off
global_load_b64 v[11:12], v[11:12], off offset:-8
v_add_co_u32 v15, vcc_lo, s4, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v16, vcc_lo
v_add_co_u32 v17, vcc_lo, s4, v17
v_add_co_ci_u32_e32 v18, vcc_lo, s5, v18, vcc_lo
s_clause 0x1
global_load_b64 v[15:16], v[15:16], off
global_load_b64 v[17:18], v[17:18], off
v_lshlrev_b64 v[19:20], 3, v[19:20]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v19, vcc_lo, s4, v19
v_add_co_ci_u32_e32 v20, vcc_lo, s5, v20, vcc_lo
v_add_co_u32 v23, vcc_lo, s4, v21
v_add_co_ci_u32_e32 v24, vcc_lo, s5, v22, vcc_lo
s_clause 0x1
global_load_b64 v[19:20], v[19:20], off
global_load_b64 v[23:24], v[23:24], off
s_clause 0x1
s_load_b128 s[12:15], s[0:1], 0x28
s_load_b64 s[4:5], s[0:1], 0x38
s_waitcnt lgkmcnt(0)
v_cvt_f32_f64_e32 v0, s[4:5]
s_mov_b32 s5, 0x3fb99999
s_mov_b32 s4, 0x9999999a
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, 0xbfb8aa3b, v0
v_exp_f32_e32 v0, v0
s_waitcnt vmcnt(6)
v_add_f64 v[8:9], v[13:14], v[9:10]
s_waitcnt vmcnt(4)
v_add_f64 v[6:7], v[11:12], v[6:7]
v_add_co_u32 v11, vcc_lo, s6, v21
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v22, vcc_lo
v_add_co_u32 v13, vcc_lo, s16, v21
v_add_co_ci_u32_e32 v14, vcc_lo, s17, v22, vcc_lo
global_load_b64 v[11:12], v[11:12], off
global_load_b64 v[13:14], v[13:14], off
s_waitcnt vmcnt(5)
v_add_f64 v[8:9], v[8:9], v[15:16]
s_waitcnt vmcnt(4)
v_add_f64 v[6:7], v[6:7], v[17:18]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[3:4], v[8:9], v[4:5]
s_waitcnt vmcnt(3)
v_add_f64 v[5:6], v[6:7], v[19:20]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[3:4], v[5:6], 0x3fd00000, v[3:4]
v_mul_f64 v[5:6], s[12:13], s[12:13]
s_waitcnt vmcnt(2)
v_fma_f64 v[3:4], v[23:24], 0xc0140000, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[7:8], null, v[5:6], v[5:6], v[3:4]
v_div_scale_f64 v[17:18], vcc_lo, v[3:4], v[5:6], v[3:4]
v_rcp_f64_e32 v[9:10], v[7:8]
s_waitcnt_depctr 0xfff
v_fma_f64 v[15:16], -v[7:8], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[15:16], v[9:10]
v_fma_f64 v[15:16], -v[7:8], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[15:16], v[9:10]
v_mul_f64 v[15:16], v[17:18], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[7:8], v[15:16], v[17:18]
v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[15:16]
v_mul_f64 v[9:10], s[14:15], s[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_div_fixup_f64 v[3:4], v[7:8], v[5:6], v[3:4]
v_cvt_f64_f32_e32 v[5:6], v0
s_waitcnt vmcnt(1)
v_fma_f64 v[7:8], v[23:24], 2.0, -v[11:12]
v_mul_f64 v[9:10], v[9:10], s[4:5]
s_xor_b32 s4, exec_lo, -1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], -v[13:14], v[5:6], v[3:4]
v_fma_f64 v[4:5], v[9:10], v[3:4], v[7:8]
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s3, s3, exec_lo
s_and_b32 s4, s4, exec_lo
s_or_b32 s3, s3, s4
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s2, exec_lo
s_and_b32 s3, s3, exec_lo
s_or_b32 s2, s2, s3
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s3, s2
v_mov_b32_e32 v4, 0
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v2, 0
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[4:5], off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12evolve9ptgpuPdS_S_S_iddd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 25
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12evolve9ptgpuPdS_S_S_iddd, .Lfunc_end0-_Z12evolve9ptgpuPdS_S_S_iddd
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9evolvegpuPdS_S_S_iddd
.globl _Z9evolvegpuPdS_S_S_iddd
.p2align 8
.type _Z9evolvegpuPdS_S_S_iddd,@function
_Z9evolvegpuPdS_S_S_iddd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4c
s_load_b32 s10, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s10, s10
v_cmp_lt_i32_e32 vcc_lo, -1, v1
v_cmp_gt_i32_e64 s2, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_10
s_ashr_i32 s2, s10, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s3, s10, s2
s_mov_b32 s8, exec_lo
s_xor_b32 s3, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s2, 0, s3
v_xor_b32_e32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s2, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v2, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s3
v_sub_nc_u32_e32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v3
v_sub_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e64 s2, 0, v2
v_cmpx_ne_u32_e32 0, v2
s_cbranch_execz .LBB1_7
v_add_nc_u32_e32 v3, 1, v1
s_mov_b32 s4, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v3
v_add_nc_u32_e32 v4, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v4, v2
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s3
v_sub_nc_u32_e32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s3, v0
v_cmp_le_u32_e32 vcc_lo, s3, v0
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v4, s3, v0
v_cmp_le_u32_e32 vcc_lo, s3, v0
v_cmp_gt_i32_e64 s3, s10, v1
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v2
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_or_b32 s3, s3, vcc_lo
s_xor_b32 s5, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s9, s5
s_cbranch_execz .LBB1_6
s_add_i32 s5, s10, -1
s_mov_b32 s11, exec_lo
s_mul_i32 s5, s5, s10
s_delay_alu instid0(SALU_CYCLE_1)
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB1_5
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[16:17], s[0:1], 0x18
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v11, s10, v1
v_subrev_nc_u32_e32 v13, s10, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mov_b32_e32 v4, v2
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[11:12], 3, v[11:12]
v_lshlrev_b64 v[13:14], 3, v[13:14]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v11
s_clause 0x1
global_load_b64 v[9:10], v[7:8], off offset:-8
global_load_b64 v[3:4], v[3:4], off
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
v_add_co_u32 v13, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
s_clause 0x2
global_load_b64 v[11:12], v[11:12], off
global_load_b64 v[13:14], v[13:14], off
global_load_b64 v[7:8], v[7:8], off
s_clause 0x1
s_load_b128 s[12:15], s[0:1], 0x28
s_load_b64 s[4:5], s[0:1], 0x38
v_add_co_u32 v15, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v16, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s16, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s17, v6, vcc_lo
global_load_b64 v[15:16], v[15:16], off
global_load_b64 v[5:6], v[5:6], off
s_waitcnt lgkmcnt(0)
v_cvt_f32_f64_e32 v0, s[4:5]
s_mov_b32 s5, 0x3fb99999
s_mov_b32 s4, 0x9999999a
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, 0xbfb8aa3b, v0
v_exp_f32_e32 v0, v0
s_waitcnt vmcnt(5)
v_add_f64 v[3:4], v[9:10], v[3:4]
v_mul_f64 v[9:10], s[12:13], s[12:13]
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[3:4], v[11:12]
s_waitcnt vmcnt(3)
v_add_f64 v[3:4], v[3:4], v[13:14]
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[3:4], v[7:8], -4.0, v[3:4]
s_waitcnt vmcnt(1)
v_fma_f64 v[7:8], v[7:8], 2.0, -v[15:16]
v_div_scale_f64 v[11:12], null, v[9:10], v[9:10], v[3:4]
v_div_scale_f64 v[19:20], vcc_lo, v[3:4], v[9:10], v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[13:14], v[11:12]
s_waitcnt_depctr 0xfff
v_fma_f64 v[17:18], -v[11:12], v[13:14], 1.0
v_fma_f64 v[13:14], v[13:14], v[17:18], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], -v[11:12], v[13:14], 1.0
v_fma_f64 v[13:14], v[13:14], v[17:18], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[17:18], v[19:20], v[13:14]
v_fma_f64 v[11:12], -v[11:12], v[17:18], v[19:20]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[11:12], v[11:12], v[13:14], v[17:18]
v_mul_f64 v[13:14], s[14:15], s[14:15]
v_div_fixup_f64 v[3:4], v[11:12], v[9:10], v[3:4]
v_cvt_f64_f32_e32 v[9:10], v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_f64 v[11:12], v[13:14], s[4:5]
s_xor_b32 s4, exec_lo, -1
s_waitcnt vmcnt(0)
v_fma_f64 v[3:4], v[5:6], v[9:10], v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[4:5], v[11:12], v[3:4], v[7:8]
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s3, s3, exec_lo
s_and_b32 s4, s4, exec_lo
s_or_b32 s3, s3, s4
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s2, exec_lo
s_and_b32 s3, s3, exec_lo
s_or_b32 s2, s2, s3
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s3, s2
v_mov_b32_e32 v4, 0
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v2, 0
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[4:5], off
.LBB1_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9evolvegpuPdS_S_S_iddd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9evolvegpuPdS_S_S_iddd, .Lfunc_end1-_Z9evolvegpuPdS_S_S_iddd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 8
.value_kind: by_value
- .offset: 56
.size: 8
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12evolve9ptgpuPdS_S_S_iddd
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z12evolve9ptgpuPdS_S_S_iddd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 25
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 8
.value_kind: by_value
- .offset: 56
.size: 8
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9evolvegpuPdS_S_S_iddd
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z9evolvegpuPdS_S_S_iddd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Single Author info:
yjkamdar Yash J Kamdar
Group info:
vphadke Vandan V Phadke
angodse Anupam N Godse
*/
#include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define __DEBUG
#define VSQR 0.1
#define TSCALE 1.0
#define CUDA_CALL( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__,__LINE__)
/**************************************
* void __cudaSafeCall(cudaError err, const char *file, const int line)
* void __cudaCheckError(const char *file, const int line)
*
* These routines were taken from the GPU Computing SDK
* (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
**************************************/
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s.\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment if not needed.
/*err = cudaThreadSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}*/
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
int tpdt(double *t, double dt, double tf)
{
if((*t) + dt > tf) return 0;
(*t) = (*t) + dt;
return 1;
}
/*9-point evolution of the grid using the GPU*/
__global__ void evolve9ptgpu(double *un, double *uc, double *uo, double *pebbles, int n, double h, double dt, double t){
/*Calculate the index of the current grid point calculation*/
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int totalLength = n*n;
/*Boudary conditions for the grid*/
if (idx >= 0 && idx < totalLength) {
if((idx % n == 0) || ((idx + 1) % n == 0) || idx < n || idx > n*(n-1) - 1)
{
un[idx] = 0;
}
/*Calculate grid point value using the 9-point scale*/
else
{
un[idx] = 2*uc[idx] - uo[idx] + VSQR *(dt * dt) *((uc[idx-1] + uc[idx+1] +
uc[idx + n] + uc[idx - n] + 0.25 * (uc[idx -n - 1] + uc[idx - n + 1] +
uc[idx -1 + n] + uc[idx + 1 + n]) - 5 * uc[idx])/(h * h)
+ (-1 * __expf(-TSCALE * t) * pebbles[idx]));
}
}
}
__global__ void evolvegpu(double *un, double *uc, double *uo, double *pebbles, int n, double h, double dt, double t){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int totalLength = n*n;
if (idx >= 0 && idx < totalLength) {
if((idx % n == 0) || ((idx + 1) % n == 0) || idx < n || idx > n*(n-1) - 1)
{
un[idx] = 0;
}
else
{
un[idx] = 2*uc[idx] - uo[idx] + VSQR *(dt * dt) *((uc[idx-1] + uc[idx+1] +
uc[idx + n] + uc[idx - n] - 4 * uc[idx])/(h * h) + (__expf(-TSCALE * t) * pebbles[idx]));
}
}
}
void run_gpu(double *u, double *u0, double *u1, double *pebbles, int n, double h, double end_time, int nthreads)
{
hipEvent_t kstart, kstop;
float ktime;
/* HW2: Define your local variables here */
int nBlocks = n / nthreads;
double t, dt;
double *uc, *uo;
double *un_d, *uc_d, *uo_d, *pebbles_d;
uc = (double*)malloc(sizeof(double) * n * n);
uo = (double*)malloc(sizeof(double) * n * n);
t = 0.;
dt = h / 2.;
memcpy(uo, u0, sizeof(double) * n * n);
memcpy(uc, u1, sizeof(double) * n * n);
/* Set up device timers */
CUDA_CALL(hipSetDevice(0));
CUDA_CALL(hipEventCreate(&kstart));
CUDA_CALL(hipEventCreate(&kstop));
/* HW2: Add CUDA kernel call preperation code here */
hipMalloc((void **) &un_d, sizeof(double) * n * n);
hipMalloc((void **) &uc_d, sizeof(double) * n * n);
hipMalloc((void **) &uo_d, sizeof(double) * n * n);
hipMalloc((void **) &pebbles_d, sizeof(double) * n * n);
hipMemcpy(pebbles_d, pebbles, sizeof(double) * n * n, hipMemcpyHostToDevice);
/* Start GPU computation timer */
CUDA_CALL(hipEventRecord(kstart, 0));
/* HW2: Add main lake simulation loop here */
while(1)
{
hipMemcpy(uo_d, uo, sizeof(double) * n * n, hipMemcpyHostToDevice);
hipMemcpy(uc_d, uc, sizeof(double) * n * n, hipMemcpyHostToDevice);
evolve9ptgpu<<<nBlocks*nBlocks, nthreads*nthreads>>>(un_d, uc_d, uo_d, pebbles_d, n, h, dt, t);
//evolvegpu<<<nBlocks*nBlocks, nthreads*nthreads>>>(un_d, uc_d, uo_d, pebbles_d, n, h, dt, t);
hipMemcpy(uo, uc_d, sizeof(double) * n * n, hipMemcpyDeviceToHost);
hipMemcpy(uc, un_d, sizeof(double) * n * n, hipMemcpyDeviceToHost);
if(!tpdt(&t,dt,end_time)) break;
}
memcpy(u, uc, sizeof(double) * n * n);
/* Stop GPU computation timer */
CUDA_CALL(hipEventRecord(kstop, 0));
CUDA_CALL(hipEventSynchronize(kstop));
CUDA_CALL(hipEventElapsedTime(&ktime, kstart, kstop));
printf("GPU computation: %f msec\n", ktime);
/* HW2: Add post CUDA kernel call processing and cleanup here */
free(uc);
free(uo);
hipFree(un_d);
hipFree(uc_d);
hipFree(uo_d);
/* timer cleanup */
CUDA_CALL(hipEventDestroy(kstart));
CUDA_CALL(hipEventDestroy(kstop));
} | .text
.file "lakegpu.hip"
.globl _Z4tpdtPddd # -- Begin function _Z4tpdtPddd
.p2align 4, 0x90
.type _Z4tpdtPddd,@function
_Z4tpdtPddd: # @_Z4tpdtPddd
.cfi_startproc
# %bb.0:
addsd (%rdi), %xmm0
xorl %eax, %eax
ucomisd %xmm1, %xmm0
ja .LBB0_2
# %bb.1:
movsd %xmm0, (%rdi)
movl $1, %eax
.LBB0_2:
retq
.Lfunc_end0:
.size _Z4tpdtPddd, .Lfunc_end0-_Z4tpdtPddd
.cfi_endproc
# -- End function
.globl _Z27__device_stub__evolve9ptgpuPdS_S_S_iddd # -- Begin function _Z27__device_stub__evolve9ptgpuPdS_S_S_iddd
.p2align 4, 0x90
.type _Z27__device_stub__evolve9ptgpuPdS_S_S_iddd,@function
_Z27__device_stub__evolve9ptgpuPdS_S_S_iddd: # @_Z27__device_stub__evolve9ptgpuPdS_S_S_iddd
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r8d, 4(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movsd %xmm2, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12evolve9ptgpuPdS_S_S_iddd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end1:
.size _Z27__device_stub__evolve9ptgpuPdS_S_S_iddd, .Lfunc_end1-_Z27__device_stub__evolve9ptgpuPdS_S_S_iddd
.cfi_endproc
# -- End function
.globl _Z24__device_stub__evolvegpuPdS_S_S_iddd # -- Begin function _Z24__device_stub__evolvegpuPdS_S_S_iddd
.p2align 4, 0x90
.type _Z24__device_stub__evolvegpuPdS_S_S_iddd,@function
_Z24__device_stub__evolvegpuPdS_S_S_iddd: # @_Z24__device_stub__evolvegpuPdS_S_S_iddd
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r8d, 4(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movsd %xmm2, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9evolvegpuPdS_S_S_iddd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end2:
.size _Z24__device_stub__evolvegpuPdS_S_S_iddd, .Lfunc_end2-_Z24__device_stub__evolvegpuPdS_S_S_iddd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7run_gpuPdS_S_S_iddi
.LCPI3_0:
.quad 0x3fe0000000000000 # double 0.5
.text
.globl _Z7run_gpuPdS_S_S_iddi
.p2align 4, 0x90
.type _Z7run_gpuPdS_S_S_iddi,@function
_Z7run_gpuPdS_S_S_iddi: # @_Z7run_gpuPdS_S_S_iddi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %r15d
movsd %xmm1, 112(%rsp) # 8-byte Spill
movsd %xmm0, 80(%rsp) # 8-byte Spill
movl %r8d, %ebp
movq %rcx, 104(%rsp) # 8-byte Spill
movq %rdx, 64(%rsp) # 8-byte Spill
movq %rsi, 8(%rsp) # 8-byte Spill
movq %rdi, 96(%rsp) # 8-byte Spill
movl %r8d, %eax
cltd
idivl %r9d
movl %eax, %r12d
movslq %r8d, %r13
imulq %r13, %r13
shlq $3, %r13
movq %r13, %rdi
callq malloc
movq %rax, %rbx
movq %r13, %rdi
callq malloc
movq %rax, %r14
movq %rax, %rdi
movq 8(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
callq memcpy@PLT
movq %rbx, %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
callq memcpy@PLT
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB3_1
# %bb.3: # %_Z14__cudaSafeCall10hipError_tPKci.exit
leaq 48(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB3_4
# %bb.5: # %_Z14__cudaSafeCall10hipError_tPKci.exit56
leaq 24(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB3_6
# %bb.7: # %_Z14__cudaSafeCall10hipError_tPKci.exit58
leaq 40(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 88(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 88(%rsp), %rdi
movq 104(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB3_23
# %bb.8: # %_Z14__cudaSafeCall10hipError_tPKci.exit60.preheader
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
mulsd 80(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 8(%rsp) # 8-byte Spill
imull %r12d, %r12d
imull %r15d, %r15d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
orq %rax, %r15
xorpd %xmm0, %xmm0
movapd %xmm0, 64(%rsp) # 16-byte Spill
jmp .LBB3_9
.p2align 4, 0x90
.LBB3_11: # %_Z4tpdtPddd.exit
# in Loop: Header=BB3_9 Depth=1
movq 16(%rsp), %rsi
movq %r14, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rsi
movq %rbx, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movapd 64(%rsp), %xmm3 # 16-byte Reload
addsd %xmm3, %xmm0
movsd 112(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
ucomisd %xmm1, %xmm0
cmpltsd %xmm0, %xmm1
movapd %xmm1, %xmm2
andnpd %xmm0, %xmm2
andpd %xmm3, %xmm1
orpd %xmm2, %xmm1
movapd %xmm1, 64(%rsp) # 16-byte Spill
ja .LBB3_12
.LBB3_9: # %_Z14__cudaSafeCall10hipError_tPKci.exit60
# =>This Inner Loop Header: Depth=1
movq 32(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10: # in Loop: Header=BB3_9 Depth=1
movq 40(%rsp), %rax
movq 16(%rsp), %rcx
movq 32(%rsp), %rdx
movq 88(%rsp), %rsi
movq %rax, 216(%rsp)
movq %rcx, 208(%rsp)
movq %rdx, 200(%rsp)
movq %rsi, 192(%rsp)
movl %ebp, 60(%rsp)
movsd 80(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 184(%rsp)
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 176(%rsp)
movapd 64(%rsp), %xmm0 # 16-byte Reload
movsd %xmm0, 168(%rsp)
leaq 216(%rsp), %rax
movq %rax, 224(%rsp)
leaq 208(%rsp), %rax
movq %rax, 232(%rsp)
leaq 200(%rsp), %rax
movq %rax, 240(%rsp)
leaq 192(%rsp), %rax
movq %rax, 248(%rsp)
leaq 60(%rsp), %rax
movq %rax, 256(%rsp)
leaq 184(%rsp), %rax
movq %rax, 264(%rsp)
leaq 176(%rsp), %rax
movq %rax, 272(%rsp)
leaq 168(%rsp), %rax
movq %rax, 280(%rsp)
leaq 152(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 152(%rsp), %rsi
movl 160(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
movl $_Z12evolve9ptgpuPdS_S_S_iddd, %edi
leaq 224(%rsp), %r9
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_11
.LBB3_12:
movq 96(%rsp), %rdi # 8-byte Reload
movq %rbx, %rsi
movq %r13, %rdx
callq memcpy@PLT
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB3_13
# %bb.14: # %_Z14__cudaSafeCall10hipError_tPKci.exit62
movq 24(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB3_15
# %bb.16: # %_Z14__cudaSafeCall10hipError_tPKci.exit64
movq 48(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 224(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB3_17
# %bb.18: # %_Z14__cudaSafeCall10hipError_tPKci.exit66
movss 224(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB3_19
# %bb.20: # %_Z14__cudaSafeCall10hipError_tPKci.exit68
movq 24(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB3_21
# %bb.22: # %_Z14__cudaSafeCall10hipError_tPKci.exit70
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 352
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $153, %ecx
jmp .LBB3_2
.LBB3_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $154, %ecx
jmp .LBB3_2
.LBB3_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $155, %ecx
jmp .LBB3_2
.LBB3_23:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $166, %ecx
jmp .LBB3_2
.LBB3_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $186, %ecx
jmp .LBB3_2
.LBB3_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $187, %ecx
jmp .LBB3_2
.LBB3_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $188, %ecx
jmp .LBB3_2
.LBB3_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $199, %ecx
jmp .LBB3_2
.LBB3_21:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $200, %ecx
.LBB3_2:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end3:
.size _Z7run_gpuPdS_S_S_iddi, .Lfunc_end3-_Z7run_gpuPdS_S_S_iddi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12evolve9ptgpuPdS_S_S_iddd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9evolvegpuPdS_S_S_iddd, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12evolve9ptgpuPdS_S_S_iddd,@object # @_Z12evolve9ptgpuPdS_S_S_iddd
.section .rodata,"a",@progbits
.globl _Z12evolve9ptgpuPdS_S_S_iddd
.p2align 3, 0x0
_Z12evolve9ptgpuPdS_S_S_iddd:
.quad _Z27__device_stub__evolve9ptgpuPdS_S_S_iddd
.size _Z12evolve9ptgpuPdS_S_S_iddd, 8
.type _Z9evolvegpuPdS_S_S_iddd,@object # @_Z9evolvegpuPdS_S_S_iddd
.globl _Z9evolvegpuPdS_S_S_iddd
.p2align 3, 0x0
_Z9evolvegpuPdS_S_S_iddd:
.quad _Z24__device_stub__evolvegpuPdS_S_S_iddd
.size _Z9evolvegpuPdS_S_S_iddd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/anupamgodse/Parallel-Systems-Fall-2018/master/HW2/p3/lakegpu.hip"
.size .L.str, 122
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU computation: %f msec\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cudaSafeCall() failed at %s:%i : %s\n"
.size .L.str.2, 37
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12evolve9ptgpuPdS_S_S_iddd"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9evolvegpuPdS_S_S_iddd"
.size .L__unnamed_2, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__evolve9ptgpuPdS_S_S_iddd
.addrsig_sym _Z24__device_stub__evolvegpuPdS_S_S_iddd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12evolve9ptgpuPdS_S_S_iddd
.addrsig_sym _Z9evolvegpuPdS_S_S_iddd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c62bc_00000000-6_lakegpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4tpdtPddd
.type _Z4tpdtPddd, @function
_Z4tpdtPddd:
.LFB2059:
.cfi_startproc
endbr64
addsd (%rdi), %xmm0
movl $0, %eax
comisd %xmm1, %xmm0
ja .L3
movsd %xmm0, (%rdi)
movl $1, %eax
.L3:
ret
.cfi_endproc
.LFE2059:
.size _Z4tpdtPddd, .-_Z4tpdtPddd
.globl _Z42__device_stub__Z12evolve9ptgpuPdS_S_S_idddPdS_S_S_iddd
.type _Z42__device_stub__Z12evolve9ptgpuPdS_S_S_idddPdS_S_S_iddd, @function
_Z42__device_stub__Z12evolve9ptgpuPdS_S_S_idddPdS_S_S_iddd:
.LFB2085:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movl %r8d, 28(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movsd %xmm2, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z12evolve9ptgpuPdS_S_S_iddd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z42__device_stub__Z12evolve9ptgpuPdS_S_S_idddPdS_S_S_iddd, .-_Z42__device_stub__Z12evolve9ptgpuPdS_S_S_idddPdS_S_S_iddd
.globl _Z12evolve9ptgpuPdS_S_S_iddd
.type _Z12evolve9ptgpuPdS_S_S_iddd, @function
_Z12evolve9ptgpuPdS_S_S_iddd:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z12evolve9ptgpuPdS_S_S_idddPdS_S_S_iddd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z12evolve9ptgpuPdS_S_S_iddd, .-_Z12evolve9ptgpuPdS_S_S_iddd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/anupamgodse/Parallel-Systems-Fall-2018/master/HW2/p3/lakegpu.cu"
.align 8
.LC3:
.string "cudaSafeCall() failed at %s:%i : %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "GPU computation: %f msec\n"
.text
.globl _Z7run_gpuPdS_S_S_iddi
.type _Z7run_gpuPdS_S_S_iddi, @function
_Z7run_gpuPdS_S_S_iddi:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 8(%rsp)
movq %rdx, 48(%rsp)
movq %rcx, 56(%rsp)
movl %r8d, %r15d
movsd %xmm0, 32(%rsp)
movsd %xmm1, 24(%rsp)
movl %r9d, %r13d
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl %r8d, %eax
cltd
idivl %r9d
movl %eax, %r14d
movslq %r8d, %rbx
imulq %rbx, %rbx
salq $3, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movsd 32(%rsp), %xmm6
mulsd .LC1(%rip), %xmm6
movsd %xmm6, 16(%rsp)
movq %rbx, %rcx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %rax, %rdi
call __memcpy_chk@PLT
movq %rbx, %rcx
movq %rbx, %rdx
movq 48(%rsp), %rsi
movq %rbp, %rdi
call __memcpy_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L30
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L31
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L32
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 56(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L33
imull %r13d, %r13d
imull %r14d, %r14d
movq $0x000000000, 8(%rsp)
.L20:
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl %r13d, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl %r14d, 112(%rsp)
movl $1, 116(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L19:
movl $2, %ecx
movq %rbx, %rdx
movq 88(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movsd 8(%rsp), %xmm3
addsd 16(%rsp), %xmm3
movsd %xmm3, 8(%rsp)
comisd 24(%rsp), %xmm3
jbe .L20
movq %rbx, %rdx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call memcpy@PLT
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L35
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
testl %eax, %eax
jne .L36
leaq 124(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L37
pxor %xmm0, %xmm0
cvtss2sd 124(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaEventDestroy@PLT
testl %eax, %eax
jne .L38
movq 72(%rsp), %rdi
call cudaEventDestroy@PLT
testl %eax, %eax
jne .L39
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $153, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $154, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $155, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $166, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L34:
movsd 8(%rsp), %xmm2
movsd 16(%rsp), %xmm1
movsd 32(%rsp), %xmm0
movl %r15d, %r8d
movq 104(%rsp), %rcx
movq 96(%rsp), %rdx
movq 88(%rsp), %rsi
movq 80(%rsp), %rdi
call _Z42__device_stub__Z12evolve9ptgpuPdS_S_S_idddPdS_S_S_iddd
jmp .L19
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $186, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $187, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $188, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $199, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L39:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $200, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z7run_gpuPdS_S_S_iddi, .-_Z7run_gpuPdS_S_S_iddi
.globl _Z38__device_stub__Z9evolvegpuPdS_S_S_idddPdS_S_S_iddd
.type _Z38__device_stub__Z9evolvegpuPdS_S_S_idddPdS_S_S_iddd, @function
_Z38__device_stub__Z9evolvegpuPdS_S_S_idddPdS_S_S_iddd:
.LFB2087:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movl %r8d, 28(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movsd %xmm2, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z9evolvegpuPdS_S_S_iddd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z38__device_stub__Z9evolvegpuPdS_S_S_idddPdS_S_S_iddd, .-_Z38__device_stub__Z9evolvegpuPdS_S_S_idddPdS_S_S_iddd
.globl _Z9evolvegpuPdS_S_S_iddd
.type _Z9evolvegpuPdS_S_S_iddd, @function
_Z9evolvegpuPdS_S_S_iddd:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z9evolvegpuPdS_S_S_idddPdS_S_S_iddd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z9evolvegpuPdS_S_S_iddd, .-_Z9evolvegpuPdS_S_S_iddd
.section .rodata.str1.1
.LC5:
.string "_Z9evolvegpuPdS_S_S_iddd"
.LC6:
.string "_Z12evolve9ptgpuPdS_S_S_iddd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9evolvegpuPdS_S_S_iddd(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z12evolve9ptgpuPdS_S_S_iddd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1071644672
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lakegpu.hip"
.globl _Z4tpdtPddd # -- Begin function _Z4tpdtPddd
.p2align 4, 0x90
.type _Z4tpdtPddd,@function
_Z4tpdtPddd: # @_Z4tpdtPddd
.cfi_startproc
# %bb.0:
addsd (%rdi), %xmm0
xorl %eax, %eax
ucomisd %xmm1, %xmm0
ja .LBB0_2
# %bb.1:
movsd %xmm0, (%rdi)
movl $1, %eax
.LBB0_2:
retq
.Lfunc_end0:
.size _Z4tpdtPddd, .Lfunc_end0-_Z4tpdtPddd
.cfi_endproc
# -- End function
.globl _Z27__device_stub__evolve9ptgpuPdS_S_S_iddd # -- Begin function _Z27__device_stub__evolve9ptgpuPdS_S_S_iddd
.p2align 4, 0x90
.type _Z27__device_stub__evolve9ptgpuPdS_S_S_iddd,@function
_Z27__device_stub__evolve9ptgpuPdS_S_S_iddd: # @_Z27__device_stub__evolve9ptgpuPdS_S_S_iddd
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r8d, 4(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movsd %xmm2, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12evolve9ptgpuPdS_S_S_iddd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end1:
.size _Z27__device_stub__evolve9ptgpuPdS_S_S_iddd, .Lfunc_end1-_Z27__device_stub__evolve9ptgpuPdS_S_S_iddd
.cfi_endproc
# -- End function
.globl _Z24__device_stub__evolvegpuPdS_S_S_iddd # -- Begin function _Z24__device_stub__evolvegpuPdS_S_S_iddd
.p2align 4, 0x90
.type _Z24__device_stub__evolvegpuPdS_S_S_iddd,@function
_Z24__device_stub__evolvegpuPdS_S_S_iddd: # @_Z24__device_stub__evolvegpuPdS_S_S_iddd
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r8d, 4(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movsd %xmm2, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9evolvegpuPdS_S_S_iddd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end2:
.size _Z24__device_stub__evolvegpuPdS_S_S_iddd, .Lfunc_end2-_Z24__device_stub__evolvegpuPdS_S_S_iddd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7run_gpuPdS_S_S_iddi
.LCPI3_0:
.quad 0x3fe0000000000000 # double 0.5
.text
.globl _Z7run_gpuPdS_S_S_iddi
.p2align 4, 0x90
.type _Z7run_gpuPdS_S_S_iddi,@function
_Z7run_gpuPdS_S_S_iddi: # @_Z7run_gpuPdS_S_S_iddi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %r15d
movsd %xmm1, 112(%rsp) # 8-byte Spill
movsd %xmm0, 80(%rsp) # 8-byte Spill
movl %r8d, %ebp
movq %rcx, 104(%rsp) # 8-byte Spill
movq %rdx, 64(%rsp) # 8-byte Spill
movq %rsi, 8(%rsp) # 8-byte Spill
movq %rdi, 96(%rsp) # 8-byte Spill
movl %r8d, %eax
cltd
idivl %r9d
movl %eax, %r12d
movslq %r8d, %r13
imulq %r13, %r13
shlq $3, %r13
movq %r13, %rdi
callq malloc
movq %rax, %rbx
movq %r13, %rdi
callq malloc
movq %rax, %r14
movq %rax, %rdi
movq 8(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
callq memcpy@PLT
movq %rbx, %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
callq memcpy@PLT
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB3_1
# %bb.3: # %_Z14__cudaSafeCall10hipError_tPKci.exit
leaq 48(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB3_4
# %bb.5: # %_Z14__cudaSafeCall10hipError_tPKci.exit56
leaq 24(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB3_6
# %bb.7: # %_Z14__cudaSafeCall10hipError_tPKci.exit58
leaq 40(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 88(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 88(%rsp), %rdi
movq 104(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB3_23
# %bb.8: # %_Z14__cudaSafeCall10hipError_tPKci.exit60.preheader
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
mulsd 80(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 8(%rsp) # 8-byte Spill
imull %r12d, %r12d
imull %r15d, %r15d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
orq %rax, %r15
xorpd %xmm0, %xmm0
movapd %xmm0, 64(%rsp) # 16-byte Spill
jmp .LBB3_9
.p2align 4, 0x90
.LBB3_11: # %_Z4tpdtPddd.exit
# in Loop: Header=BB3_9 Depth=1
movq 16(%rsp), %rsi
movq %r14, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rsi
movq %rbx, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movapd 64(%rsp), %xmm3 # 16-byte Reload
addsd %xmm3, %xmm0
movsd 112(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
ucomisd %xmm1, %xmm0
cmpltsd %xmm0, %xmm1
movapd %xmm1, %xmm2
andnpd %xmm0, %xmm2
andpd %xmm3, %xmm1
orpd %xmm2, %xmm1
movapd %xmm1, 64(%rsp) # 16-byte Spill
ja .LBB3_12
.LBB3_9: # %_Z14__cudaSafeCall10hipError_tPKci.exit60
# =>This Inner Loop Header: Depth=1
movq 32(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10: # in Loop: Header=BB3_9 Depth=1
movq 40(%rsp), %rax
movq 16(%rsp), %rcx
movq 32(%rsp), %rdx
movq 88(%rsp), %rsi
movq %rax, 216(%rsp)
movq %rcx, 208(%rsp)
movq %rdx, 200(%rsp)
movq %rsi, 192(%rsp)
movl %ebp, 60(%rsp)
movsd 80(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 184(%rsp)
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 176(%rsp)
movapd 64(%rsp), %xmm0 # 16-byte Reload
movsd %xmm0, 168(%rsp)
leaq 216(%rsp), %rax
movq %rax, 224(%rsp)
leaq 208(%rsp), %rax
movq %rax, 232(%rsp)
leaq 200(%rsp), %rax
movq %rax, 240(%rsp)
leaq 192(%rsp), %rax
movq %rax, 248(%rsp)
leaq 60(%rsp), %rax
movq %rax, 256(%rsp)
leaq 184(%rsp), %rax
movq %rax, 264(%rsp)
leaq 176(%rsp), %rax
movq %rax, 272(%rsp)
leaq 168(%rsp), %rax
movq %rax, 280(%rsp)
leaq 152(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 152(%rsp), %rsi
movl 160(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
movl $_Z12evolve9ptgpuPdS_S_S_iddd, %edi
leaq 224(%rsp), %r9
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_11
.LBB3_12:
movq 96(%rsp), %rdi # 8-byte Reload
movq %rbx, %rsi
movq %r13, %rdx
callq memcpy@PLT
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB3_13
# %bb.14: # %_Z14__cudaSafeCall10hipError_tPKci.exit62
movq 24(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB3_15
# %bb.16: # %_Z14__cudaSafeCall10hipError_tPKci.exit64
movq 48(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 224(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB3_17
# %bb.18: # %_Z14__cudaSafeCall10hipError_tPKci.exit66
movss 224(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB3_19
# %bb.20: # %_Z14__cudaSafeCall10hipError_tPKci.exit68
movq 24(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB3_21
# %bb.22: # %_Z14__cudaSafeCall10hipError_tPKci.exit70
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 352
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $153, %ecx
jmp .LBB3_2
.LBB3_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $154, %ecx
jmp .LBB3_2
.LBB3_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $155, %ecx
jmp .LBB3_2
.LBB3_23:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $166, %ecx
jmp .LBB3_2
.LBB3_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $186, %ecx
jmp .LBB3_2
.LBB3_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $187, %ecx
jmp .LBB3_2
.LBB3_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $188, %ecx
jmp .LBB3_2
.LBB3_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $199, %ecx
jmp .LBB3_2
.LBB3_21:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $200, %ecx
.LBB3_2:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end3:
.size _Z7run_gpuPdS_S_S_iddi, .Lfunc_end3-_Z7run_gpuPdS_S_S_iddi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12evolve9ptgpuPdS_S_S_iddd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9evolvegpuPdS_S_S_iddd, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12evolve9ptgpuPdS_S_S_iddd,@object # @_Z12evolve9ptgpuPdS_S_S_iddd
.section .rodata,"a",@progbits
.globl _Z12evolve9ptgpuPdS_S_S_iddd
.p2align 3, 0x0
_Z12evolve9ptgpuPdS_S_S_iddd:
.quad _Z27__device_stub__evolve9ptgpuPdS_S_S_iddd
.size _Z12evolve9ptgpuPdS_S_S_iddd, 8
.type _Z9evolvegpuPdS_S_S_iddd,@object # @_Z9evolvegpuPdS_S_S_iddd
.globl _Z9evolvegpuPdS_S_S_iddd
.p2align 3, 0x0
_Z9evolvegpuPdS_S_S_iddd:
.quad _Z24__device_stub__evolvegpuPdS_S_S_iddd
.size _Z9evolvegpuPdS_S_S_iddd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/anupamgodse/Parallel-Systems-Fall-2018/master/HW2/p3/lakegpu.hip"
.size .L.str, 122
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU computation: %f msec\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cudaSafeCall() failed at %s:%i : %s\n"
.size .L.str.2, 37
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12evolve9ptgpuPdS_S_S_iddd"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9evolvegpuPdS_S_S_iddd"
.size .L__unnamed_2, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__evolve9ptgpuPdS_S_S_iddd
.addrsig_sym _Z24__device_stub__evolvegpuPdS_S_S_iddd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12evolve9ptgpuPdS_S_S_iddd
.addrsig_sym _Z9evolvegpuPdS_S_S_iddd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
void print_array(float *A, int N)
{
for(int i=0;i<N;i++)
printf("%.2f ",A[i]);
printf("\n");
}
__global__ void
process_kernel1(float *input1, float *input2, float *output, int datasize)
{
int numElements = datasize / sizeof(float);
//Write code for i
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int i = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
if (i < numElements)
{
output[i] = sinf(input1[i]) + cosf(input2[i]);
}
}
__global__ void
process_kernel2(float *input, float *output, int datasize)
{
int numElements = datasize / sizeof(float);
//Write code for i
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int i = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
if (i < numElements)
{
output[i] = logf(input[i]);
}
}
__global__ void
process_kernel3(float *input, float *output, int datasize)
{
int numElements = datasize / sizeof(float);
//Write code for i
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int i = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
if (i < numElements)
{
output[i] = sqrtf(input[i]);
}
}
int main(void)
{
cudaError_t err = cudaSuccess;
int numElements = 16384;
size_t size = numElements * sizeof(float);
float *h_input1 = (float *)malloc(size);
float *h_input2 = (float *)malloc(size);
float *h_output1 = (float *)malloc(size);
float *h_output2 = (float *)malloc(size);
float *h_output3 = (float *)malloc(size);
if (h_input1 == NULL || h_input2 == NULL || h_output1 == NULL || h_output2 == NULL || h_output3 == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
for (int i = 0; i < numElements; ++i)
{
scanf("%f",&h_input1[i]);
}
for (int i = 0; i < numElements; ++i)
{
scanf("%f",&h_input2[i]);
}
float *d_input1 = NULL;
err = cudaMalloc((void **)&d_input1, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector d_input1 (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
float *d_input2 = NULL;
err = cudaMalloc((void **)&d_input2, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector d_input2 (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
float *d_output1 = NULL;
err = cudaMalloc((void **)&d_output1, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector h_output1 (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
float *d_output2 = NULL;
err = cudaMalloc((void **)&d_output2, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector h_output2 (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
float *d_output3 = NULL;
err = cudaMalloc((void **)&d_output3, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector h_output3 (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// printf("Copy input data from the host memory to the CUDA device\n");
err = cudaMemcpy(d_input1, h_input1, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector h_input1 from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_input2, h_input2, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector h_input2 from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
//Complete Code for launching process_kernel1
dim3 X1(4, 2, 2);
dim3 Y1(32, 32, 1);
process_kernel1<<<X1, Y1>>>(d_input1, d_input2, d_output1, size);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch process_kernel1 kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
//Complete Code for launching process_kernel2
dim3 X2(2, 8, 1);
dim3 Y2(8, 8, 16);
process_kernel2<<<X2, Y2>>>(d_output1, d_output2, size);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch process_kernel2 kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
//Complete Code for launching process_kernel3
dim3 X3(16, 1, 1);
dim3 Y3(128, 8, 1);
process_kernel3<<<X3, Y3>>>(d_output2, d_output3, size);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch process_kernel3 kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// printf("Copy output data from the CUDA device to the host memory\n");
err = cudaMemcpy(h_output1, d_output1, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector d_output1 from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(h_output2, d_output2, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector d_output2 from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(h_output3, d_output3, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector d_output3 from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Verify that the result vectors are as expected
for (int i = 0; i < numElements; ++i)
{
if (fabs(sinf(h_input1[i]) + cosf(h_input2[i]) - h_output1[i]) > 1e-5)
{
fprintf(stderr, "Result verification for h_output1 failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
for (int i = 0; i < numElements; ++i)
{
if (fabs(logf(h_output1[i]) - h_output2[i]) > 1e-5)
{
fprintf(stderr, "Result verification for h_output2 failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
for (int i = 0; i < numElements; ++i)
{
if (fabs(sqrtf(h_output2[i]) - h_output3[i]) > 1e-5)
{
fprintf(stderr, "Result verification for h_output3 failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
print_array(h_output3,numElements);
err = cudaFree(d_input1);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector d_input1 (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_input2);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector d_input2 (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_output1);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector d_output1 (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_output2);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector d_output2 (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_output3);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector d_output3 (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
free(h_input1);
free(h_input2);
free(h_output1);
free(h_output2);
free(h_output3);
err = cudaDeviceReset();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
return 0;
} | .file "tmpxft_000732d7_00000000-6_multi_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%.2f "
.LC1:
.string "\n"
.text
.globl _Z11print_arrayPfi
.type _Z11print_arrayPfi, @function
_Z11print_arrayPfi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %esi, %esi
jle .L4
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC0(%rip), %rbp
.L5:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L5
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11print_arrayPfi, .-_Z11print_arrayPfi
.globl _Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i
.type _Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15process_kernel1PfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i, .-_Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i
.globl _Z15process_kernel1PfS_S_i
.type _Z15process_kernel1PfS_S_i, @function
_Z15process_kernel1PfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15process_kernel1PfS_S_i, .-_Z15process_kernel1PfS_S_i
.globl _Z38__device_stub__Z15process_kernel2PfS_iPfS_i
.type _Z38__device_stub__Z15process_kernel2PfS_iPfS_i, @function
_Z38__device_stub__Z15process_kernel2PfS_iPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15process_kernel2PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z38__device_stub__Z15process_kernel2PfS_iPfS_i, .-_Z38__device_stub__Z15process_kernel2PfS_iPfS_i
.globl _Z15process_kernel2PfS_i
.type _Z15process_kernel2PfS_i, @function
_Z15process_kernel2PfS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15process_kernel2PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z15process_kernel2PfS_i, .-_Z15process_kernel2PfS_i
.globl _Z38__device_stub__Z15process_kernel3PfS_iPfS_i
.type _Z38__device_stub__Z15process_kernel3PfS_iPfS_i, @function
_Z38__device_stub__Z15process_kernel3PfS_iPfS_i:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15process_kernel3PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z38__device_stub__Z15process_kernel3PfS_iPfS_i, .-_Z38__device_stub__Z15process_kernel3PfS_iPfS_i
.globl _Z15process_kernel3PfS_i
.type _Z15process_kernel3PfS_i, @function
_Z15process_kernel3PfS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15process_kernel3PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z15process_kernel3PfS_i, .-_Z15process_kernel3PfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Failed to allocate host vectors!\n"
.section .rodata.str1.1
.LC3:
.string "%f"
.section .rodata.str1.8
.align 8
.LC4:
.string "Failed to allocate device vector d_input1 (error code %s)!\n"
.align 8
.LC5:
.string "Failed to allocate device vector d_input2 (error code %s)!\n"
.align 8
.LC6:
.string "Failed to allocate device vector h_output1 (error code %s)!\n"
.align 8
.LC7:
.string "Failed to allocate device vector h_output2 (error code %s)!\n"
.align 8
.LC8:
.string "Failed to allocate device vector h_output3 (error code %s)!\n"
.align 8
.LC9:
.string "Failed to copy vector h_input1 from host to device (error code %s)!\n"
.align 8
.LC10:
.string "Failed to copy vector h_input2 from host to device (error code %s)!\n"
.align 8
.LC11:
.string "Failed to launch process_kernel1 kernel (error code %s)!\n"
.align 8
.LC12:
.string "Failed to launch process_kernel2 kernel (error code %s)!\n"
.align 8
.LC13:
.string "Failed to launch process_kernel3 kernel (error code %s)!\n"
.align 8
.LC14:
.string "Failed to copy vector d_output1 from device to host (error code %s)!\n"
.align 8
.LC15:
.string "Failed to copy vector d_output2 from device to host (error code %s)!\n"
.align 8
.LC16:
.string "Failed to copy vector d_output3 from device to host (error code %s)!\n"
.align 8
.LC19:
.string "Result verification for h_output1 failed at element %d!\n"
.align 8
.LC20:
.string "Result verification for h_output2 failed at element %d!\n"
.align 8
.LC22:
.string "Result verification for h_output3 failed at element %d!\n"
.align 8
.LC23:
.string "Failed to free device vector d_input1 (error code %s)!\n"
.align 8
.LC24:
.string "Failed to free device vector d_input2 (error code %s)!\n"
.align 8
.LC25:
.string "Failed to free device vector d_output1 (error code %s)!\n"
.align 8
.LC26:
.string "Failed to free device vector d_output2 (error code %s)!\n"
.align 8
.LC27:
.string "Failed to free device vector d_output3 (error code %s)!\n"
.align 8
.LC28:
.string "Failed to deinitialize the device! error=%s\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $65536, %edi
call malloc@PLT
movq %rax, %r13
movl $65536, %edi
call malloc@PLT
movq %rax, %r14
movl $65536, %edi
call malloc@PLT
movq %rax, %rbp
movl $65536, %edi
call malloc@PLT
movq %rax, %r12
movl $65536, %edi
call malloc@PLT
movq %rax, 8(%rsp)
testq %r13, %r13
je .L33
movq %rax, %rcx
testq %r14, %r14
je .L33
testq %rbp, %rbp
sete %al
testq %r12, %r12
sete %dl
orb %dl, %al
jne .L33
testq %rcx, %rcx
je .L33
movq %r13, %rbx
leaq 65536(%r13), %r15
.L36:
movq %rbx, %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L36
movq %r14, %rbx
leaq 65536(%r14), %r15
.L37:
movq %rbx, %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L37
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L87
movq $0, 32(%rsp)
leaq 32(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L88
movq $0, 40(%rsp)
leaq 40(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L89
movq $0, 48(%rsp)
leaq 48(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L90
movq $0, 56(%rsp)
leaq 56(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L91
movl $1, %ecx
movl $65536, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L92
movl $1, %ecx
movl $65536, %edx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L93
movl $4, 64(%rsp)
movl $2, 68(%rsp)
movl $32, 76(%rsp)
movl $32, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $2, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L94
.L45:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L95
movl $2, 88(%rsp)
movl $8, 92(%rsp)
movl $8, 100(%rsp)
movl $8, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $16, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L96
.L47:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L97
movl $16, 112(%rsp)
movl $1, 116(%rsp)
movl $128, 124(%rsp)
movl $8, 128(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L98
.L49:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L99
movl $2, %ecx
movl $65536, %edx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L100
movl $2, %ecx
movl $65536, %edx
movq 48(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L101
movl $2, %ecx
movl $65536, %edx
movq 56(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L102
movl $0, %ebx
.L53:
movss 0(%r13,%rbx,4), %xmm0
call sinf@PLT
movss %xmm0, 4(%rsp)
movss (%r14,%rbx,4), %xmm0
call cosf@PLT
addss 4(%rsp), %xmm0
subss 0(%rbp,%rbx,4), %xmm0
andps .LC17(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
comisd .LC18(%rip), %xmm0
ja .L103
addq $1, %rbx
cmpq $16384, %rbx
jne .L53
movl $0, %ebx
.L58:
movss 0(%rbp,%rbx,4), %xmm0
call logf@PLT
subss (%r12,%rbx,4), %xmm0
andps .LC17(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
comisd .LC18(%rip), %xmm0
ja .L104
addq $1, %rbx
cmpq $16384, %rbx
jne .L58
movl $0, %ebx
movl $0x00000000, %r15d
.L64:
movss (%r12,%rbx,4), %xmm0
movd %r15d, %xmm2
ucomiss %xmm0, %xmm2
ja .L84
sqrtss %xmm0, %xmm0
.L61:
movq 8(%rsp), %rax
subss (%rax,%rbx,4), %xmm0
andps .LC17(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
comisd .LC18(%rip), %xmm0
ja .L105
addq $1, %rbx
cmpq $16384, %rbx
jne .L64
movl $16384, %esi
movq 8(%rsp), %rdi
call _Z11print_arrayPfi
movq 24(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L106
movq 32(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L107
movq 40(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L108
movq 48(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L109
movq 56(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L110
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L111
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L112
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L87:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L88:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L89:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L90:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L91:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L92:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L93:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L94:
movl $65536, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i
jmp .L45
.L95:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L96:
movl $65536, %edx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z38__device_stub__Z15process_kernel2PfS_iPfS_i
jmp .L47
.L97:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L98:
movl $65536, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z38__device_stub__Z15process_kernel3PfS_iPfS_i
jmp .L49
.L99:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L100:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L101:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L102:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L103:
movl %ebx, %ecx
leaq .LC19(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L104:
movl %ebx, %ecx
leaq .LC20(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L84:
call sqrtf@PLT
jmp .L61
.L105:
movl %ebx, %ecx
leaq .LC22(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L106:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC23(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L107:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L108:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L109:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC26(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L110:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC27(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L111:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC28(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L112:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC29:
.string "_Z15process_kernel3PfS_i"
.LC30:
.string "_Z15process_kernel2PfS_i"
.LC31:
.string "_Z15process_kernel1PfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC29(%rip), %rdx
movq %rdx, %rcx
leaq _Z15process_kernel3PfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC30(%rip), %rdx
movq %rdx, %rcx
leaq _Z15process_kernel2PfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC31(%rip), %rdx
movq %rdx, %rcx
leaq _Z15process_kernel1PfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC17:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC18:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
void print_array(float *A, int N)
{
for(int i=0;i<N;i++)
printf("%.2f ",A[i]);
printf("\n");
}
__global__ void
process_kernel1(float *input1, float *input2, float *output, int datasize)
{
int numElements = datasize / sizeof(float);
//Write code for i
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int i = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
if (i < numElements)
{
output[i] = sinf(input1[i]) + cosf(input2[i]);
}
}
__global__ void
process_kernel2(float *input, float *output, int datasize)
{
int numElements = datasize / sizeof(float);
//Write code for i
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int i = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
if (i < numElements)
{
output[i] = logf(input[i]);
}
}
__global__ void
process_kernel3(float *input, float *output, int datasize)
{
int numElements = datasize / sizeof(float);
//Write code for i
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int i = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
if (i < numElements)
{
output[i] = sqrtf(input[i]);
}
}
int main(void)
{
cudaError_t err = cudaSuccess;
int numElements = 16384;
size_t size = numElements * sizeof(float);
float *h_input1 = (float *)malloc(size);
float *h_input2 = (float *)malloc(size);
float *h_output1 = (float *)malloc(size);
float *h_output2 = (float *)malloc(size);
float *h_output3 = (float *)malloc(size);
if (h_input1 == NULL || h_input2 == NULL || h_output1 == NULL || h_output2 == NULL || h_output3 == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
for (int i = 0; i < numElements; ++i)
{
scanf("%f",&h_input1[i]);
}
for (int i = 0; i < numElements; ++i)
{
scanf("%f",&h_input2[i]);
}
float *d_input1 = NULL;
err = cudaMalloc((void **)&d_input1, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector d_input1 (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
float *d_input2 = NULL;
err = cudaMalloc((void **)&d_input2, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector d_input2 (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
float *d_output1 = NULL;
err = cudaMalloc((void **)&d_output1, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector h_output1 (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
float *d_output2 = NULL;
err = cudaMalloc((void **)&d_output2, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector h_output2 (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
float *d_output3 = NULL;
err = cudaMalloc((void **)&d_output3, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector h_output3 (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// printf("Copy input data from the host memory to the CUDA device\n");
err = cudaMemcpy(d_input1, h_input1, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector h_input1 from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_input2, h_input2, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector h_input2 from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
//Complete Code for launching process_kernel1
dim3 X1(4, 2, 2);
dim3 Y1(32, 32, 1);
process_kernel1<<<X1, Y1>>>(d_input1, d_input2, d_output1, size);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch process_kernel1 kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
//Complete Code for launching process_kernel2
dim3 X2(2, 8, 1);
dim3 Y2(8, 8, 16);
process_kernel2<<<X2, Y2>>>(d_output1, d_output2, size);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch process_kernel2 kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
//Complete Code for launching process_kernel3
dim3 X3(16, 1, 1);
dim3 Y3(128, 8, 1);
process_kernel3<<<X3, Y3>>>(d_output2, d_output3, size);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch process_kernel3 kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// printf("Copy output data from the CUDA device to the host memory\n");
err = cudaMemcpy(h_output1, d_output1, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector d_output1 from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(h_output2, d_output2, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector d_output2 from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(h_output3, d_output3, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector d_output3 from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
// Verify that the result vectors are as expected
for (int i = 0; i < numElements; ++i)
{
if (fabs(sinf(h_input1[i]) + cosf(h_input2[i]) - h_output1[i]) > 1e-5)
{
fprintf(stderr, "Result verification for h_output1 failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
for (int i = 0; i < numElements; ++i)
{
if (fabs(logf(h_output1[i]) - h_output2[i]) > 1e-5)
{
fprintf(stderr, "Result verification for h_output2 failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
for (int i = 0; i < numElements; ++i)
{
if (fabs(sqrtf(h_output2[i]) - h_output3[i]) > 1e-5)
{
fprintf(stderr, "Result verification for h_output3 failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
print_array(h_output3,numElements);
err = cudaFree(d_input1);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector d_input1 (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_input2);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector d_input2 (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_output1);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector d_output1 (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_output2);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector d_output2 (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaFree(d_output3);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to free device vector d_output3 (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
free(h_input1);
free(h_input2);
free(h_output1);
free(h_output2);
free(h_output3);
err = cudaDeviceReset();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
void print_array(float *A, int N)
{
for(int i=0;i<N;i++)
printf("%.2f ",A[i]);
printf("\n");
}
__global__ void
process_kernel1(float *input1, float *input2, float *output, int datasize)
{
int numElements = datasize / sizeof(float);
//Write code for i
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int i = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
if (i < numElements)
{
output[i] = sinf(input1[i]) + cosf(input2[i]);
}
}
__global__ void
process_kernel2(float *input, float *output, int datasize)
{
int numElements = datasize / sizeof(float);
//Write code for i
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int i = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
if (i < numElements)
{
output[i] = logf(input[i]);
}
}
__global__ void
process_kernel3(float *input, float *output, int datasize)
{
int numElements = datasize / sizeof(float);
//Write code for i
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int i = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
if (i < numElements)
{
output[i] = sqrtf(input[i]);
}
}
int main(void)
{
hipError_t err = hipSuccess;
int numElements = 16384;
size_t size = numElements * sizeof(float);
float *h_input1 = (float *)malloc(size);
float *h_input2 = (float *)malloc(size);
float *h_output1 = (float *)malloc(size);
float *h_output2 = (float *)malloc(size);
float *h_output3 = (float *)malloc(size);
if (h_input1 == NULL || h_input2 == NULL || h_output1 == NULL || h_output2 == NULL || h_output3 == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
for (int i = 0; i < numElements; ++i)
{
scanf("%f",&h_input1[i]);
}
for (int i = 0; i < numElements; ++i)
{
scanf("%f",&h_input2[i]);
}
float *d_input1 = NULL;
err = hipMalloc((void **)&d_input1, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector d_input1 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
float *d_input2 = NULL;
err = hipMalloc((void **)&d_input2, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector d_input2 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
float *d_output1 = NULL;
err = hipMalloc((void **)&d_output1, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector h_output1 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
float *d_output2 = NULL;
err = hipMalloc((void **)&d_output2, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector h_output2 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
float *d_output3 = NULL;
err = hipMalloc((void **)&d_output3, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector h_output3 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// printf("Copy input data from the host memory to the CUDA device\n");
err = hipMemcpy(d_input1, h_input1, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector h_input1 from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_input2, h_input2, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector h_input2 from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
//Complete Code for launching process_kernel1
dim3 X1(4, 2, 2);
dim3 Y1(32, 32, 1);
process_kernel1<<<X1, Y1>>>(d_input1, d_input2, d_output1, size);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch process_kernel1 kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
//Complete Code for launching process_kernel2
dim3 X2(2, 8, 1);
dim3 Y2(8, 8, 16);
process_kernel2<<<X2, Y2>>>(d_output1, d_output2, size);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch process_kernel2 kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
//Complete Code for launching process_kernel3
dim3 X3(16, 1, 1);
dim3 Y3(128, 8, 1);
process_kernel3<<<X3, Y3>>>(d_output2, d_output3, size);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch process_kernel3 kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// printf("Copy output data from the CUDA device to the host memory\n");
err = hipMemcpy(h_output1, d_output1, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector d_output1 from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(h_output2, d_output2, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector d_output2 from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(h_output3, d_output3, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector d_output3 from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Verify that the result vectors are as expected
for (int i = 0; i < numElements; ++i)
{
if (fabs(sinf(h_input1[i]) + cosf(h_input2[i]) - h_output1[i]) > 1e-5)
{
fprintf(stderr, "Result verification for h_output1 failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
for (int i = 0; i < numElements; ++i)
{
if (fabs(logf(h_output1[i]) - h_output2[i]) > 1e-5)
{
fprintf(stderr, "Result verification for h_output2 failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
for (int i = 0; i < numElements; ++i)
{
if (fabs(sqrtf(h_output2[i]) - h_output3[i]) > 1e-5)
{
fprintf(stderr, "Result verification for h_output3 failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
print_array(h_output3,numElements);
err = hipFree(d_input1);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector d_input1 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_input2);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector d_input2 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_output1);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector d_output1 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_output2);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector d_output2 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_output3);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector d_output3 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
free(h_input1);
free(h_input2);
free(h_output1);
free(h_output2);
free(h_output3);
err = hipDeviceReset();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
void print_array(float *A, int N)
{
for(int i=0;i<N;i++)
printf("%.2f ",A[i]);
printf("\n");
}
__global__ void
process_kernel1(float *input1, float *input2, float *output, int datasize)
{
int numElements = datasize / sizeof(float);
//Write code for i
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int i = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
if (i < numElements)
{
output[i] = sinf(input1[i]) + cosf(input2[i]);
}
}
__global__ void
process_kernel2(float *input, float *output, int datasize)
{
int numElements = datasize / sizeof(float);
//Write code for i
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int i = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
if (i < numElements)
{
output[i] = logf(input[i]);
}
}
__global__ void
process_kernel3(float *input, float *output, int datasize)
{
int numElements = datasize / sizeof(float);
//Write code for i
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int i = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
if (i < numElements)
{
output[i] = sqrtf(input[i]);
}
}
int main(void)
{
hipError_t err = hipSuccess;
int numElements = 16384;
size_t size = numElements * sizeof(float);
float *h_input1 = (float *)malloc(size);
float *h_input2 = (float *)malloc(size);
float *h_output1 = (float *)malloc(size);
float *h_output2 = (float *)malloc(size);
float *h_output3 = (float *)malloc(size);
if (h_input1 == NULL || h_input2 == NULL || h_output1 == NULL || h_output2 == NULL || h_output3 == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
for (int i = 0; i < numElements; ++i)
{
scanf("%f",&h_input1[i]);
}
for (int i = 0; i < numElements; ++i)
{
scanf("%f",&h_input2[i]);
}
float *d_input1 = NULL;
err = hipMalloc((void **)&d_input1, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector d_input1 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
float *d_input2 = NULL;
err = hipMalloc((void **)&d_input2, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector d_input2 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
float *d_output1 = NULL;
err = hipMalloc((void **)&d_output1, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector h_output1 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
float *d_output2 = NULL;
err = hipMalloc((void **)&d_output2, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector h_output2 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
float *d_output3 = NULL;
err = hipMalloc((void **)&d_output3, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector h_output3 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// printf("Copy input data from the host memory to the CUDA device\n");
err = hipMemcpy(d_input1, h_input1, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector h_input1 from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_input2, h_input2, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector h_input2 from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
//Complete Code for launching process_kernel1
dim3 X1(4, 2, 2);
dim3 Y1(32, 32, 1);
process_kernel1<<<X1, Y1>>>(d_input1, d_input2, d_output1, size);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch process_kernel1 kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
//Complete Code for launching process_kernel2
dim3 X2(2, 8, 1);
dim3 Y2(8, 8, 16);
process_kernel2<<<X2, Y2>>>(d_output1, d_output2, size);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch process_kernel2 kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
//Complete Code for launching process_kernel3
dim3 X3(16, 1, 1);
dim3 Y3(128, 8, 1);
process_kernel3<<<X3, Y3>>>(d_output2, d_output3, size);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch process_kernel3 kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// printf("Copy output data from the CUDA device to the host memory\n");
err = hipMemcpy(h_output1, d_output1, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector d_output1 from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(h_output2, d_output2, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector d_output2 from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(h_output3, d_output3, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector d_output3 from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Verify that the result vectors are as expected
for (int i = 0; i < numElements; ++i)
{
if (fabs(sinf(h_input1[i]) + cosf(h_input2[i]) - h_output1[i]) > 1e-5)
{
fprintf(stderr, "Result verification for h_output1 failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
for (int i = 0; i < numElements; ++i)
{
if (fabs(logf(h_output1[i]) - h_output2[i]) > 1e-5)
{
fprintf(stderr, "Result verification for h_output2 failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
for (int i = 0; i < numElements; ++i)
{
if (fabs(sqrtf(h_output2[i]) - h_output3[i]) > 1e-5)
{
fprintf(stderr, "Result verification for h_output3 failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
print_array(h_output3,numElements);
err = hipFree(d_input1);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector d_input1 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_input2);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector d_input2 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_output1);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector d_output1 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_output2);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector d_output2 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_output3);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector d_output3 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
free(h_input1);
free(h_input2);
free(h_output1);
free(h_output2);
free(h_output3);
err = hipDeviceReset();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15process_kernel1PfS_S_i
.globl _Z15process_kernel1PfS_S_i
.p2align 8
.type _Z15process_kernel1PfS_S_i,@function
_Z15process_kernel1PfS_S_i:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b64 s[4:5], s[0:1], 0x2c
v_bfe_u32 v1, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s2, s3, s2
s_and_b32 s3, s5, 0xffff
s_add_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
s_lshr_b32 s3, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
v_and_b32_e32 v2, 0x3ff, v0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v3, s3, v[2:3]
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s2, 2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_10
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s3, exec_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v3, 0x7fffffff, v2
v_cmpx_ngt_f32_e64 0x48000000, |v2|
s_xor_b32 s4, exec_lo, s3
s_cbranch_execz .LBB0_3
s_mov_b32 s2, 0x7fffff
v_mov_b32_e32 v6, 0
v_and_or_b32 v14, v3, s2, 0x800000
v_lshrrev_b32_e32 v11, 23, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, v14, 0xfe5163ab, 0
v_add_nc_u32_e32 v12, 0xffffff88, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v12
v_mad_u64_u32 v[7:8], null, v14, 0x3c439041, v[5:6]
v_cndmask_b32_e64 v13, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v5, v8
v_add_nc_u32_e32 v13, v13, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, v14, 0xdb629599, v[5:6]
v_cmp_lt_u32_e64 s2, 31, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v15, 0, 0xffffffe0, s2
v_dual_mov_b32 v5, v9 :: v_dual_cndmask_b32 v4, v8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v15, v15, v13
v_mad_u64_u32 v[9:10], null, v14, 0xf534ddc0, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v15
v_mov_b32_e32 v5, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v7, v9, v7, vcc_lo
v_mad_u64_u32 v[10:11], null, v14, 0xfc2757d1, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v4, v7, v4, s2
v_mov_b32_e32 v5, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[11:12], null, v14, 0x4e441529, v[5:6]
v_mov_b32_e32 v5, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[12:13], null, v14, 0xa2f9836e, v[5:6]
v_cndmask_b32_e64 v5, 0, 0xffffffe0, s3
v_dual_cndmask_b32 v6, v11, v9 :: v_dual_add_nc_u32 v5, v5, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v12, v12, v10 :: v_dual_cndmask_b32 v11, v13, v11
v_cndmask_b32_e32 v10, v10, v8, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v9, v12, v6, s2
v_cndmask_b32_e64 v11, v11, v12, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v6, v6, v10, s2
v_sub_nc_u32_e32 v12, 32, v5
v_cndmask_b32_e64 v10, v10, v7, s2
v_cndmask_b32_e64 v11, v11, v9, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v9, v9, v6, s3
v_cndmask_b32_e64 v6, v6, v10, s3
v_cndmask_b32_e64 v4, v10, v4, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v13, v11, v9, v12
v_alignbit_b32 v8, v9, v6, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v5, v13, v11, vcc_lo
v_alignbit_b32 v11, v6, v4, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v7, v8, v9, vcc_lo
v_bfe_u32 v8, v5, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v6, v11, v6, vcc_lo
v_alignbit_b32 v9, v5, v7, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v10, 0, v8
v_alignbit_b32 v7, v7, v6, 30
v_alignbit_b32 v4, v6, v4, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v9, v9, v10
v_xor_b32_e32 v6, v7, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v4, v4, v10
v_clz_i32_u32_e32 v11, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v11, 32, v11
v_sub_nc_u32_e32 v7, 31, v11
v_lshlrev_b32_e32 v13, 23, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_alignbit_b32 v9, v9, v6, v7
v_alignbit_b32 v4, v6, v4, v7
v_lshrrev_b32_e32 v7, 29, v5
v_alignbit_b32 v6, v9, v4, 9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v7, 31, v7
v_lshrrev_b32_e32 v9, 9, v9
v_clz_i32_u32_e32 v10, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v12, 0.5, v7
v_min_u32_e32 v10, 32, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v12, v12, v13
v_sub_nc_u32_e32 v14, 31, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v4, v6, v4, v14
v_or_b32_e32 v6, v9, v12
v_add_lshl_u32 v9, v10, v11, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v4, 9, v4
v_mul_f32_e32 v10, 0x3fc90fda, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v4, v9
v_fma_f32 v9, v6, 0x3fc90fda, -v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 0x33000000, v4
v_fmamk_f32 v6, v6, 0x33a22168, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v4, v4, v7
v_fmac_f32_e32 v6, 0x3fc90fda, v4
v_lshrrev_b32_e32 v5, 30, v5
s_delay_alu instid0(VALU_DEP_1)
v_dual_add_f32 v4, v10, v6 :: v_dual_add_nc_u32 v5, v8, v5
.LBB0_3:
s_and_not1_saveexec_b32 s2, s4
v_mul_f32_e64 v4, 0x3f22f983, |v2|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v5, v4
v_fma_f32 v4, v5, 0xbfc90fda, |v2|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v4, v5, 0xb3a22168, v4
v_fmamk_f32 v4, v5, 0xa7c234c4, v4
v_cvt_i32_f32_e32 v5, v5
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[2:3], s[0:1], 0x8
v_lshlrev_b64 v[6:7], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_mov_b32 s3, exec_lo
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_cmpx_ngt_f32_e64 0x48000000, |v6|
s_xor_b32 s4, exec_lo, s3
s_cbranch_execz .LBB0_7
v_dual_mov_b32 v9, 0 :: v_dual_and_b32 v14, 0x7fffffff, v6
s_mov_b32 s2, 0x7fffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_and_or_b32 v17, v14, s2, 0x800000
v_lshrrev_b32_e32 v14, 23, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[7:8], null, v17, 0xfe5163ab, 0
v_add_nc_u32_e32 v15, 0xffffff88, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v15
v_mad_u64_u32 v[10:11], null, v17, 0x3c439041, v[8:9]
v_cndmask_b32_e64 v16, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v8, v11
v_add_nc_u32_e32 v16, v16, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[11:12], null, v17, 0xdb629599, v[8:9]
v_cmp_lt_u32_e64 s2, 31, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v18, 0, 0xffffffe0, s2
v_dual_mov_b32 v8, v12 :: v_dual_cndmask_b32 v7, v11, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v18, v18, v16
v_mad_u64_u32 v[12:13], null, v17, 0xf534ddc0, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v18
v_mov_b32_e32 v8, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v10, v12, v10, vcc_lo
v_mad_u64_u32 v[13:14], null, v17, 0xfc2757d1, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v7, v10, v7, s2
v_mov_b32_e32 v8, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[14:15], null, v17, 0x4e441529, v[8:9]
v_mov_b32_e32 v8, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[15:16], null, v17, 0xa2f9836e, v[8:9]
v_cndmask_b32_e64 v8, 0, 0xffffffe0, s3
v_dual_cndmask_b32 v9, v14, v12 :: v_dual_add_nc_u32 v8, v8, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v15, v15, v13 :: v_dual_cndmask_b32 v14, v16, v14
v_cndmask_b32_e32 v13, v13, v11, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v15, v9, s2
v_cndmask_b32_e64 v14, v14, v15, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v9, v9, v13, s2
v_sub_nc_u32_e32 v15, 32, v8
v_cndmask_b32_e64 v13, v13, v10, s2
v_cndmask_b32_e64 v14, v14, v12, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v12, v12, v9, s3
v_cndmask_b32_e64 v9, v9, v13, s3
v_cndmask_b32_e64 v7, v13, v7, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v16, v14, v12, v15
v_alignbit_b32 v11, v12, v9, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v8, v16, v14, vcc_lo
v_alignbit_b32 v14, v9, v7, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v10, v11, v12, vcc_lo
v_bfe_u32 v11, v8, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v9, v14, v9, vcc_lo
v_alignbit_b32 v12, v8, v10, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v13, 0, v11
v_alignbit_b32 v10, v10, v9, 30
v_alignbit_b32 v7, v9, v7, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v12, v12, v13
v_xor_b32_e32 v9, v10, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v7, v7, v13
v_clz_i32_u32_e32 v14, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v14, 32, v14
v_sub_nc_u32_e32 v10, 31, v14
v_lshlrev_b32_e32 v16, 23, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_alignbit_b32 v12, v12, v9, v10
v_alignbit_b32 v7, v9, v7, v10
v_lshrrev_b32_e32 v10, 29, v8
v_alignbit_b32 v9, v12, v7, 9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v10, 31, v10
v_lshrrev_b32_e32 v12, 9, v12
v_clz_i32_u32_e32 v13, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v15, 0.5, v10
v_min_u32_e32 v13, 32, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v15, v15, v16
v_sub_nc_u32_e32 v17, 31, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v7, v9, v7, v17
v_or_b32_e32 v9, v12, v15
v_add_lshl_u32 v12, v13, v14, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v7, 9, v7
v_mul_f32_e32 v13, 0x3fc90fda, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v7, v7, v12
v_fma_f32 v12, v9, 0x3fc90fda, -v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, 0x33000000, v7
v_fmamk_f32 v9, v9, 0x33a22168, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v7, v7, v10
v_fmac_f32_e32 v9, 0x3fc90fda, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v13, v9
v_lshrrev_b32_e32 v8, 30, v8
v_add_nc_u32_e32 v8, v11, v8
.LBB0_7:
s_and_not1_saveexec_b32 s2, s4
v_mul_f32_e64 v7, 0x3f22f983, |v6|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v8, v7
v_fma_f32 v7, v8, 0xbfc90fda, |v6|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v7, v8, 0xb3a22168, v7
v_fmamk_f32 v7, v8, 0xa7c234c4, v7
v_cvt_i32_f32_e32 v8, v8
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_dual_mul_f32 v9, v4, v4 :: v_dual_mul_f32 v10, v7, v7
s_mov_b32 s2, 0xb94c1982
s_mov_b32 s3, 0x37d75334
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_fmaak_f32 v11, s2, v9, 0x3c0881c4 :: v_dual_fmaak_f32 v14, s2, v10, 0x3c0881c4
v_dual_fmaak_f32 v12, s3, v9, 0xbab64f3b :: v_dual_fmaak_f32 v15, s3, v10, 0xbab64f3b
v_and_b32_e32 v13, 1, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_fmaak_f32 v11, v9, v11, 0xbe2aaa9d :: v_dual_fmaak_f32 v14, v10, v14, 0xbe2aaa9d
v_dual_fmaak_f32 v12, v9, v12, 0x3d2aabf7 :: v_dual_lshlrev_b32 v5, 30, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_fmaak_f32 v15, v10, v15, 0x3d2aabf7 :: v_dual_and_b32 v16, 1, v8
v_dual_mul_f32 v11, v9, v11 :: v_dual_mul_f32 v14, v10, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmaak_f32 v12, v9, v12, 0xbf000004
v_cmp_eq_u32_e32 vcc_lo, 0, v13
v_dual_fmac_f32 v4, v4, v11 :: v_dual_and_b32 v5, 0x80000000, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_fmac_f32 v7, v7, v14 :: v_dual_lshlrev_b32 v8, 30, v8
v_fma_f32 v9, v9, v12, 1.0
v_fmaak_f32 v15, v10, v15, 0xbf000004
v_xor_b32_e32 v3, v3, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_and_b32_e32 v8, 0x80000000, v8
v_cndmask_b32_e32 v4, v9, v4, vcc_lo
v_fma_f32 v10, v10, v15, 1.0
v_cmp_eq_u32_e32 vcc_lo, 0, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor3_b32 v3, v3, v5, v4
v_cndmask_b32_e64 v7, -v7, v10, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x1f8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v4, v8, v7
v_cndmask_b32_e32 v2, 0x7fc00000, v3, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v6, 0x1f8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v3, 0x7fc00000, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15process_kernel1PfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15process_kernel1PfS_S_i, .Lfunc_end0-_Z15process_kernel1PfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15process_kernel2PfS_i
.globl _Z15process_kernel2PfS_i
.p2align 8
.type _Z15process_kernel2PfS_i,@function
_Z15process_kernel2PfS_i:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b64 s[4:5], s[0:1], 0x24
v_bfe_u32 v1, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s2, s3, s2
s_and_b32 s3, s5, 0xffff
s_add_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
s_load_b32 s2, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_lshr_b32 s3, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
v_and_b32_e32 v2, 0x3ff, v0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v3, s3, v[2:3]
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s2, 2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v2
v_cndmask_b32_e64 v3, 1.0, 0x4f800000, vcc_lo
v_mul_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_log_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x3f317217, v2
v_fma_f32 v4, v2, 0x3f317217, -v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v4, v2, 0x3377d1cf, v4
v_add_f32_e32 v3, v3, v4
v_cndmask_b32_e64 v4, 0, 0x41b17218, vcc_lo
v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_sub_f32_e32 v2, v2, v4
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15process_kernel2PfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15process_kernel2PfS_i, .Lfunc_end1-_Z15process_kernel2PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15process_kernel3PfS_i
.globl _Z15process_kernel3PfS_i
.p2align 8
.type _Z15process_kernel3PfS_i,@function
_Z15process_kernel3PfS_i:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b64 s[4:5], s[0:1], 0x24
v_bfe_u32 v1, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s2, s3, s2
s_and_b32 s3, s5, 0xffff
s_add_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
s_load_b32 s2, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_lshr_b32 s3, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
v_and_b32_e32 v2, 0x3ff, v0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v3, s3, v[2:3]
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s2, 2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
v_fma_f32 v6, -v4, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v5, v3, v2
v_cmp_ge_f32_e64 s0, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v3, v4, s0
v_cmp_lt_f32_e64 s0, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v5, s0
v_mul_f32_e32 v4, 0x37800000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15process_kernel3PfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z15process_kernel3PfS_i, .Lfunc_end2-_Z15process_kernel3PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15process_kernel1PfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15process_kernel1PfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15process_kernel2PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15process_kernel2PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15process_kernel3PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15process_kernel3PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
void print_array(float *A, int N)
{
for(int i=0;i<N;i++)
printf("%.2f ",A[i]);
printf("\n");
}
__global__ void
process_kernel1(float *input1, float *input2, float *output, int datasize)
{
int numElements = datasize / sizeof(float);
//Write code for i
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int i = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
if (i < numElements)
{
output[i] = sinf(input1[i]) + cosf(input2[i]);
}
}
__global__ void
process_kernel2(float *input, float *output, int datasize)
{
int numElements = datasize / sizeof(float);
//Write code for i
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int i = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
if (i < numElements)
{
output[i] = logf(input[i]);
}
}
__global__ void
process_kernel3(float *input, float *output, int datasize)
{
int numElements = datasize / sizeof(float);
//Write code for i
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x + blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x * blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int i = blockNum * (blockDim.x * blockDim.y * blockDim.z) + threadNum;
if (i < numElements)
{
output[i] = sqrtf(input[i]);
}
}
int main(void)
{
hipError_t err = hipSuccess;
int numElements = 16384;
size_t size = numElements * sizeof(float);
float *h_input1 = (float *)malloc(size);
float *h_input2 = (float *)malloc(size);
float *h_output1 = (float *)malloc(size);
float *h_output2 = (float *)malloc(size);
float *h_output3 = (float *)malloc(size);
if (h_input1 == NULL || h_input2 == NULL || h_output1 == NULL || h_output2 == NULL || h_output3 == NULL)
{
fprintf(stderr, "Failed to allocate host vectors!\n");
exit(EXIT_FAILURE);
}
for (int i = 0; i < numElements; ++i)
{
scanf("%f",&h_input1[i]);
}
for (int i = 0; i < numElements; ++i)
{
scanf("%f",&h_input2[i]);
}
float *d_input1 = NULL;
err = hipMalloc((void **)&d_input1, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector d_input1 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
float *d_input2 = NULL;
err = hipMalloc((void **)&d_input2, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector d_input2 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
float *d_output1 = NULL;
err = hipMalloc((void **)&d_output1, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector h_output1 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
float *d_output2 = NULL;
err = hipMalloc((void **)&d_output2, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector h_output2 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
float *d_output3 = NULL;
err = hipMalloc((void **)&d_output3, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector h_output3 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// printf("Copy input data from the host memory to the CUDA device\n");
err = hipMemcpy(d_input1, h_input1, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector h_input1 from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_input2, h_input2, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector h_input2 from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
//Complete Code for launching process_kernel1
dim3 X1(4, 2, 2);
dim3 Y1(32, 32, 1);
process_kernel1<<<X1, Y1>>>(d_input1, d_input2, d_output1, size);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch process_kernel1 kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
//Complete Code for launching process_kernel2
dim3 X2(2, 8, 1);
dim3 Y2(8, 8, 16);
process_kernel2<<<X2, Y2>>>(d_output1, d_output2, size);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch process_kernel2 kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
//Complete Code for launching process_kernel3
dim3 X3(16, 1, 1);
dim3 Y3(128, 8, 1);
process_kernel3<<<X3, Y3>>>(d_output2, d_output3, size);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch process_kernel3 kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// printf("Copy output data from the CUDA device to the host memory\n");
err = hipMemcpy(h_output1, d_output1, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector d_output1 from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(h_output2, d_output2, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector d_output2 from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(h_output3, d_output3, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector d_output3 from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
// Verify that the result vectors are as expected
for (int i = 0; i < numElements; ++i)
{
if (fabs(sinf(h_input1[i]) + cosf(h_input2[i]) - h_output1[i]) > 1e-5)
{
fprintf(stderr, "Result verification for h_output1 failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
for (int i = 0; i < numElements; ++i)
{
if (fabs(logf(h_output1[i]) - h_output2[i]) > 1e-5)
{
fprintf(stderr, "Result verification for h_output2 failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
for (int i = 0; i < numElements; ++i)
{
if (fabs(sqrtf(h_output2[i]) - h_output3[i]) > 1e-5)
{
fprintf(stderr, "Result verification for h_output3 failed at element %d!\n", i);
exit(EXIT_FAILURE);
}
}
print_array(h_output3,numElements);
err = hipFree(d_input1);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector d_input1 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_input2);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector d_input2 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_output1);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector d_output1 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_output2);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector d_output2 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipFree(d_output3);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to free device vector d_output3 (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
free(h_input1);
free(h_input2);
free(h_output1);
free(h_output2);
free(h_output3);
err = hipDeviceReset();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to deinitialize the device! error=%s\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
return 0;
} | .text
.file "multi_kernel.hip"
.globl _Z11print_arrayPfi # -- Begin function _Z11print_arrayPfi
.p2align 4, 0x90
.type _Z11print_arrayPfi,@function
_Z11print_arrayPfi: # @_Z11print_arrayPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end0:
.size _Z11print_arrayPfi, .Lfunc_end0-_Z11print_arrayPfi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__process_kernel1PfS_S_i # -- Begin function _Z30__device_stub__process_kernel1PfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__process_kernel1PfS_S_i,@function
_Z30__device_stub__process_kernel1PfS_S_i: # @_Z30__device_stub__process_kernel1PfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15process_kernel1PfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z30__device_stub__process_kernel1PfS_S_i, .Lfunc_end1-_Z30__device_stub__process_kernel1PfS_S_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__process_kernel2PfS_i # -- Begin function _Z30__device_stub__process_kernel2PfS_i
.p2align 4, 0x90
.type _Z30__device_stub__process_kernel2PfS_i,@function
_Z30__device_stub__process_kernel2PfS_i: # @_Z30__device_stub__process_kernel2PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15process_kernel2PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z30__device_stub__process_kernel2PfS_i, .Lfunc_end2-_Z30__device_stub__process_kernel2PfS_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__process_kernel3PfS_i # -- Begin function _Z30__device_stub__process_kernel3PfS_i
.p2align 4, 0x90
.type _Z30__device_stub__process_kernel3PfS_i,@function
_Z30__device_stub__process_kernel3PfS_i: # @_Z30__device_stub__process_kernel3PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15process_kernel3PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z30__device_stub__process_kernel3PfS_i, .Lfunc_end3-_Z30__device_stub__process_kernel3PfS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI4_1:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $65536, %edi # imm = 0x10000
callq malloc
movq %rax, %rbx
movl $65536, %edi # imm = 0x10000
callq malloc
movq %rax, %r14
movl $65536, %edi # imm = 0x10000
callq malloc
movq %rax, %r15
movl $65536, %edi # imm = 0x10000
callq malloc
movq %rax, %r12
movl $65536, %edi # imm = 0x10000
callq malloc
testq %rbx, %rbx
je .LBB4_72
# %bb.1:
testq %r14, %r14
je .LBB4_72
# %bb.2:
testq %r15, %r15
je .LBB4_72
# %bb.3:
testq %r12, %r12
je .LBB4_72
# %bb.4:
movq %rax, %r13
testq %rax, %rax
je .LBB4_72
# %bb.5: # %.preheader211.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_6: # %.preheader211
# =>This Inner Loop Header: Depth=1
leaq (%rbx,%rbp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
addq $4, %rbp
cmpq $65536, %rbp # imm = 0x10000
jne .LBB4_6
# %bb.7: # %.preheader210.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_8: # %.preheader210
# =>This Inner Loop Header: Depth=1
leaq (%r14,%rbp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
addq $4, %rbp
cmpq $65536, %rbp # imm = 0x10000
jne .LBB4_8
# %bb.9:
movq $0, 112(%rsp)
leaq 112(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
testl %eax, %eax
jne .LBB4_10
# %bb.12:
movq $0, 104(%rsp)
leaq 104(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
testl %eax, %eax
jne .LBB4_13
# %bb.14:
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
testl %eax, %eax
jne .LBB4_15
# %bb.16:
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
testl %eax, %eax
jne .LBB4_17
# %bb.18:
movq $0, 96(%rsp)
leaq 96(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
testl %eax, %eax
jne .LBB4_19
# %bb.20:
movq 112(%rsp), %rdi
movl $65536, %edx # imm = 0x10000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_21
# %bb.22:
movq 104(%rsp), %rdi
movl $65536, %edx # imm = 0x10000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_23
# %bb.24:
movabsq $8589934596, %rdi # imm = 0x200000004
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $2, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_26
# %bb.25:
movq 112(%rsp), %rax
movq 104(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 40(%rsp)
movl $65536, 124(%rsp) # imm = 0x10000
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 124(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z15process_kernel1PfS_S_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_26:
callq hipGetLastError
testl %eax, %eax
jne .LBB4_27
# %bb.28:
movabsq $34359738370, %rbp # imm = 0x800000002
leaq 6(%rbp), %rdx
movq %rbp, %rdi
movl $1, %esi
movl $16, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_30
# %bb.29:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $65536, 24(%rsp) # imm = 0x10000
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z15process_kernel2PfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_30:
callq hipGetLastError
testl %eax, %eax
jne .LBB4_31
# %bb.32:
addq $126, %rbp
movabsq $4294967312, %rdi # imm = 0x100000010
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_34
# %bb.33:
movq 8(%rsp), %rax
movq 96(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $65536, 24(%rsp) # imm = 0x10000
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z15process_kernel3PfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_34:
callq hipGetLastError
testl %eax, %eax
jne .LBB4_35
# %bb.36:
movq 16(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_37
# %bb.38:
movq 8(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_39
# %bb.40:
movq 96(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_73
# %bb.41: # %.preheader209.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_42: # %.preheader209
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq sinf
movss %xmm0, 120(%rsp) # 4-byte Spill
movss (%r14,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq cosf
addss 120(%rsp), %xmm0 # 4-byte Folded Reload
subss (%r15,%rbp,4), %xmm0
andps .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd .LCPI4_1(%rip), %xmm0
ja .LBB4_43
# %bb.45: # in Loop: Header=BB4_42 Depth=1
incq %rbp
cmpq $16384, %rbp # imm = 0x4000
jne .LBB4_42
# %bb.46: # %.preheader208.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_47: # %.preheader208
# =>This Inner Loop Header: Depth=1
movss (%r15,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq logf
subss (%r12,%rbp,4), %xmm0
andps .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd .LCPI4_1(%rip), %xmm0
ja .LBB4_48
# %bb.49: # in Loop: Header=BB4_47 Depth=1
incq %rbp
cmpq $16384, %rbp # imm = 0x4000
jne .LBB4_47
# %bb.50: # %.preheader.preheader
xorl %ebp, %ebp
xorps %xmm1, %xmm1
.p2align 4, 0x90
.LBB4_51: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%r12,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jb .LBB4_56
# %bb.52: # in Loop: Header=BB4_51 Depth=1
sqrtss %xmm0, %xmm0
jmp .LBB4_57
.p2align 4, 0x90
.LBB4_56: # %call.sqrt
# in Loop: Header=BB4_51 Depth=1
callq sqrtf
xorps %xmm1, %xmm1
.LBB4_57: # %.preheader.split
# in Loop: Header=BB4_51 Depth=1
subss (%r13,%rbp,4), %xmm0
andps .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd .LCPI4_1(%rip), %xmm0
ja .LBB4_58
# %bb.59: # in Loop: Header=BB4_51 Depth=1
incq %rbp
cmpq $16384, %rbp # imm = 0x4000
jne .LBB4_51
# %bb.60: # %.lr.ph.i.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_53: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%r13,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbp
cmpq $16384, %rbp # imm = 0x4000
jne .LBB4_53
# %bb.54: # %_Z11print_arrayPfi.exit
movl $10, %edi
callq putchar@PLT
movq 112(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_55
# %bb.61:
movq 104(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_62
# %bb.63:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_64
# %bb.65:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_66
# %bb.67:
movq 96(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_68
# %bb.69:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq %r13, %rdi
callq free
callq hipDeviceReset
testl %eax, %eax
jne .LBB4_70
# %bb.71:
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_43:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rdi
movl $.L.str.17, %esi
jmp .LBB4_44
.LBB4_48:
movq stderr(%rip), %rdi
movl $.L.str.18, %esi
jmp .LBB4_44
.LBB4_58:
movq stderr(%rip), %rdi
movl $.L.str.19, %esi
.LBB4_44:
movl %ebp, %edx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB4_72:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $33, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB4_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
jmp .LBB4_11
.LBB4_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
jmp .LBB4_11
.LBB4_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
jmp .LBB4_11
.LBB4_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
jmp .LBB4_11
.LBB4_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
jmp .LBB4_11
.LBB4_21:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %esi
jmp .LBB4_11
.LBB4_23:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
jmp .LBB4_11
.LBB4_27:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %esi
jmp .LBB4_11
.LBB4_31:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
jmp .LBB4_11
.LBB4_35:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.13, %esi
jmp .LBB4_11
.LBB4_37:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.14, %esi
jmp .LBB4_11
.LBB4_39:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
jmp .LBB4_11
.LBB4_73:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
jmp .LBB4_11
.LBB4_55:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.20, %esi
jmp .LBB4_11
.LBB4_62:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.21, %esi
jmp .LBB4_11
.LBB4_64:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.22, %esi
jmp .LBB4_11
.LBB4_66:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.23, %esi
jmp .LBB4_11
.LBB4_68:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.24, %esi
jmp .LBB4_11
.LBB4_70:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.25, %esi
.LBB4_11:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15process_kernel1PfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15process_kernel2PfS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15process_kernel3PfS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.2f "
.size .L.str, 6
.type _Z15process_kernel1PfS_S_i,@object # @_Z15process_kernel1PfS_S_i
.section .rodata,"a",@progbits
.globl _Z15process_kernel1PfS_S_i
.p2align 3, 0x0
_Z15process_kernel1PfS_S_i:
.quad _Z30__device_stub__process_kernel1PfS_S_i
.size _Z15process_kernel1PfS_S_i, 8
.type _Z15process_kernel2PfS_i,@object # @_Z15process_kernel2PfS_i
.globl _Z15process_kernel2PfS_i
.p2align 3, 0x0
_Z15process_kernel2PfS_i:
.quad _Z30__device_stub__process_kernel2PfS_i
.size _Z15process_kernel2PfS_i, 8
.type _Z15process_kernel3PfS_i,@object # @_Z15process_kernel3PfS_i
.globl _Z15process_kernel3PfS_i
.p2align 3, 0x0
_Z15process_kernel3PfS_i:
.quad _Z30__device_stub__process_kernel3PfS_i
.size _Z15process_kernel3PfS_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Failed to allocate host vectors!\n"
.size .L.str.2, 34
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to allocate device vector d_input1 (error code %s)!\n"
.size .L.str.4, 60
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to allocate device vector d_input2 (error code %s)!\n"
.size .L.str.5, 60
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Failed to allocate device vector h_output1 (error code %s)!\n"
.size .L.str.6, 61
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to allocate device vector h_output2 (error code %s)!\n"
.size .L.str.7, 61
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to allocate device vector h_output3 (error code %s)!\n"
.size .L.str.8, 61
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Failed to copy vector h_input1 from host to device (error code %s)!\n"
.size .L.str.9, 69
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Failed to copy vector h_input2 from host to device (error code %s)!\n"
.size .L.str.10, 69
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Failed to launch process_kernel1 kernel (error code %s)!\n"
.size .L.str.11, 58
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Failed to launch process_kernel2 kernel (error code %s)!\n"
.size .L.str.12, 58
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Failed to launch process_kernel3 kernel (error code %s)!\n"
.size .L.str.13, 58
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Failed to copy vector d_output1 from device to host (error code %s)!\n"
.size .L.str.14, 70
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Failed to copy vector d_output2 from device to host (error code %s)!\n"
.size .L.str.15, 70
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Failed to copy vector d_output3 from device to host (error code %s)!\n"
.size .L.str.16, 70
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Result verification for h_output1 failed at element %d!\n"
.size .L.str.17, 57
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Result verification for h_output2 failed at element %d!\n"
.size .L.str.18, 57
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Result verification for h_output3 failed at element %d!\n"
.size .L.str.19, 57
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "Failed to free device vector d_input1 (error code %s)!\n"
.size .L.str.20, 56
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "Failed to free device vector d_input2 (error code %s)!\n"
.size .L.str.21, 56
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "Failed to free device vector d_output1 (error code %s)!\n"
.size .L.str.22, 57
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "Failed to free device vector d_output2 (error code %s)!\n"
.size .L.str.23, 57
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "Failed to free device vector d_output3 (error code %s)!\n"
.size .L.str.24, 57
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz "Failed to deinitialize the device! error=%s\n"
.size .L.str.25, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15process_kernel1PfS_S_i"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15process_kernel2PfS_i"
.size .L__unnamed_2, 25
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z15process_kernel3PfS_i"
.size .L__unnamed_3, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__process_kernel1PfS_S_i
.addrsig_sym _Z30__device_stub__process_kernel2PfS_i
.addrsig_sym _Z30__device_stub__process_kernel3PfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15process_kernel1PfS_S_i
.addrsig_sym _Z15process_kernel2PfS_i
.addrsig_sym _Z15process_kernel3PfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000732d7_00000000-6_multi_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%.2f "
.LC1:
.string "\n"
.text
.globl _Z11print_arrayPfi
.type _Z11print_arrayPfi, @function
_Z11print_arrayPfi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %esi, %esi
jle .L4
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC0(%rip), %rbp
.L5:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L5
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11print_arrayPfi, .-_Z11print_arrayPfi
.globl _Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i
.type _Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15process_kernel1PfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i, .-_Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i
.globl _Z15process_kernel1PfS_S_i
.type _Z15process_kernel1PfS_S_i, @function
_Z15process_kernel1PfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15process_kernel1PfS_S_i, .-_Z15process_kernel1PfS_S_i
.globl _Z38__device_stub__Z15process_kernel2PfS_iPfS_i
.type _Z38__device_stub__Z15process_kernel2PfS_iPfS_i, @function
_Z38__device_stub__Z15process_kernel2PfS_iPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15process_kernel2PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z38__device_stub__Z15process_kernel2PfS_iPfS_i, .-_Z38__device_stub__Z15process_kernel2PfS_iPfS_i
.globl _Z15process_kernel2PfS_i
.type _Z15process_kernel2PfS_i, @function
_Z15process_kernel2PfS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15process_kernel2PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z15process_kernel2PfS_i, .-_Z15process_kernel2PfS_i
.globl _Z38__device_stub__Z15process_kernel3PfS_iPfS_i
.type _Z38__device_stub__Z15process_kernel3PfS_iPfS_i, @function
_Z38__device_stub__Z15process_kernel3PfS_iPfS_i:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15process_kernel3PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z38__device_stub__Z15process_kernel3PfS_iPfS_i, .-_Z38__device_stub__Z15process_kernel3PfS_iPfS_i
.globl _Z15process_kernel3PfS_i
.type _Z15process_kernel3PfS_i, @function
_Z15process_kernel3PfS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15process_kernel3PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z15process_kernel3PfS_i, .-_Z15process_kernel3PfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Failed to allocate host vectors!\n"
.section .rodata.str1.1
.LC3:
.string "%f"
.section .rodata.str1.8
.align 8
.LC4:
.string "Failed to allocate device vector d_input1 (error code %s)!\n"
.align 8
.LC5:
.string "Failed to allocate device vector d_input2 (error code %s)!\n"
.align 8
.LC6:
.string "Failed to allocate device vector h_output1 (error code %s)!\n"
.align 8
.LC7:
.string "Failed to allocate device vector h_output2 (error code %s)!\n"
.align 8
.LC8:
.string "Failed to allocate device vector h_output3 (error code %s)!\n"
.align 8
.LC9:
.string "Failed to copy vector h_input1 from host to device (error code %s)!\n"
.align 8
.LC10:
.string "Failed to copy vector h_input2 from host to device (error code %s)!\n"
.align 8
.LC11:
.string "Failed to launch process_kernel1 kernel (error code %s)!\n"
.align 8
.LC12:
.string "Failed to launch process_kernel2 kernel (error code %s)!\n"
.align 8
.LC13:
.string "Failed to launch process_kernel3 kernel (error code %s)!\n"
.align 8
.LC14:
.string "Failed to copy vector d_output1 from device to host (error code %s)!\n"
.align 8
.LC15:
.string "Failed to copy vector d_output2 from device to host (error code %s)!\n"
.align 8
.LC16:
.string "Failed to copy vector d_output3 from device to host (error code %s)!\n"
.align 8
.LC19:
.string "Result verification for h_output1 failed at element %d!\n"
.align 8
.LC20:
.string "Result verification for h_output2 failed at element %d!\n"
.align 8
.LC22:
.string "Result verification for h_output3 failed at element %d!\n"
.align 8
.LC23:
.string "Failed to free device vector d_input1 (error code %s)!\n"
.align 8
.LC24:
.string "Failed to free device vector d_input2 (error code %s)!\n"
.align 8
.LC25:
.string "Failed to free device vector d_output1 (error code %s)!\n"
.align 8
.LC26:
.string "Failed to free device vector d_output2 (error code %s)!\n"
.align 8
.LC27:
.string "Failed to free device vector d_output3 (error code %s)!\n"
.align 8
.LC28:
.string "Failed to deinitialize the device! error=%s\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $65536, %edi
call malloc@PLT
movq %rax, %r13
movl $65536, %edi
call malloc@PLT
movq %rax, %r14
movl $65536, %edi
call malloc@PLT
movq %rax, %rbp
movl $65536, %edi
call malloc@PLT
movq %rax, %r12
movl $65536, %edi
call malloc@PLT
movq %rax, 8(%rsp)
testq %r13, %r13
je .L33
movq %rax, %rcx
testq %r14, %r14
je .L33
testq %rbp, %rbp
sete %al
testq %r12, %r12
sete %dl
orb %dl, %al
jne .L33
testq %rcx, %rcx
je .L33
movq %r13, %rbx
leaq 65536(%r13), %r15
.L36:
movq %rbx, %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L36
movq %r14, %rbx
leaq 65536(%r14), %r15
.L37:
movq %rbx, %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L37
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L87
movq $0, 32(%rsp)
leaq 32(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L88
movq $0, 40(%rsp)
leaq 40(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L89
movq $0, 48(%rsp)
leaq 48(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L90
movq $0, 56(%rsp)
leaq 56(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L91
movl $1, %ecx
movl $65536, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L92
movl $1, %ecx
movl $65536, %edx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L93
movl $4, 64(%rsp)
movl $2, 68(%rsp)
movl $32, 76(%rsp)
movl $32, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $2, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L94
.L45:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L95
movl $2, 88(%rsp)
movl $8, 92(%rsp)
movl $8, 100(%rsp)
movl $8, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $16, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L96
.L47:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L97
movl $16, 112(%rsp)
movl $1, 116(%rsp)
movl $128, 124(%rsp)
movl $8, 128(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L98
.L49:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L99
movl $2, %ecx
movl $65536, %edx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L100
movl $2, %ecx
movl $65536, %edx
movq 48(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L101
movl $2, %ecx
movl $65536, %edx
movq 56(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L102
movl $0, %ebx
.L53:
movss 0(%r13,%rbx,4), %xmm0
call sinf@PLT
movss %xmm0, 4(%rsp)
movss (%r14,%rbx,4), %xmm0
call cosf@PLT
addss 4(%rsp), %xmm0
subss 0(%rbp,%rbx,4), %xmm0
andps .LC17(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
comisd .LC18(%rip), %xmm0
ja .L103
addq $1, %rbx
cmpq $16384, %rbx
jne .L53
movl $0, %ebx
.L58:
movss 0(%rbp,%rbx,4), %xmm0
call logf@PLT
subss (%r12,%rbx,4), %xmm0
andps .LC17(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
comisd .LC18(%rip), %xmm0
ja .L104
addq $1, %rbx
cmpq $16384, %rbx
jne .L58
movl $0, %ebx
movl $0x00000000, %r15d
.L64:
movss (%r12,%rbx,4), %xmm0
movd %r15d, %xmm2
ucomiss %xmm0, %xmm2
ja .L84
sqrtss %xmm0, %xmm0
.L61:
movq 8(%rsp), %rax
subss (%rax,%rbx,4), %xmm0
andps .LC17(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
comisd .LC18(%rip), %xmm0
ja .L105
addq $1, %rbx
cmpq $16384, %rbx
jne .L64
movl $16384, %esi
movq 8(%rsp), %rdi
call _Z11print_arrayPfi
movq 24(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L106
movq 32(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L107
movq 40(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L108
movq 48(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L109
movq 56(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L110
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L111
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L112
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L87:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L88:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L89:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L90:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L91:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L92:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L93:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L94:
movl $65536, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i
jmp .L45
.L95:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L96:
movl $65536, %edx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z38__device_stub__Z15process_kernel2PfS_iPfS_i
jmp .L47
.L97:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L98:
movl $65536, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z38__device_stub__Z15process_kernel3PfS_iPfS_i
jmp .L49
.L99:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L100:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L101:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L102:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L103:
movl %ebx, %ecx
leaq .LC19(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L104:
movl %ebx, %ecx
leaq .LC20(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L84:
call sqrtf@PLT
jmp .L61
.L105:
movl %ebx, %ecx
leaq .LC22(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L106:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC23(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L107:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L108:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L109:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC26(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L110:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC27(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L111:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC28(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L112:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC29:
.string "_Z15process_kernel3PfS_i"
.LC30:
.string "_Z15process_kernel2PfS_i"
.LC31:
.string "_Z15process_kernel1PfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC29(%rip), %rdx
movq %rdx, %rcx
leaq _Z15process_kernel3PfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC30(%rip), %rdx
movq %rdx, %rcx
leaq _Z15process_kernel2PfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC31(%rip), %rdx
movq %rdx, %rcx
leaq _Z15process_kernel1PfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC17:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC18:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "multi_kernel.hip"
.globl _Z11print_arrayPfi # -- Begin function _Z11print_arrayPfi
.p2align 4, 0x90
.type _Z11print_arrayPfi,@function
_Z11print_arrayPfi: # @_Z11print_arrayPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end0:
.size _Z11print_arrayPfi, .Lfunc_end0-_Z11print_arrayPfi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__process_kernel1PfS_S_i # -- Begin function _Z30__device_stub__process_kernel1PfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__process_kernel1PfS_S_i,@function
_Z30__device_stub__process_kernel1PfS_S_i: # @_Z30__device_stub__process_kernel1PfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15process_kernel1PfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z30__device_stub__process_kernel1PfS_S_i, .Lfunc_end1-_Z30__device_stub__process_kernel1PfS_S_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__process_kernel2PfS_i # -- Begin function _Z30__device_stub__process_kernel2PfS_i
.p2align 4, 0x90
.type _Z30__device_stub__process_kernel2PfS_i,@function
_Z30__device_stub__process_kernel2PfS_i: # @_Z30__device_stub__process_kernel2PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15process_kernel2PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z30__device_stub__process_kernel2PfS_i, .Lfunc_end2-_Z30__device_stub__process_kernel2PfS_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__process_kernel3PfS_i # -- Begin function _Z30__device_stub__process_kernel3PfS_i
.p2align 4, 0x90
.type _Z30__device_stub__process_kernel3PfS_i,@function
_Z30__device_stub__process_kernel3PfS_i: # @_Z30__device_stub__process_kernel3PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15process_kernel3PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z30__device_stub__process_kernel3PfS_i, .Lfunc_end3-_Z30__device_stub__process_kernel3PfS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI4_1:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $65536, %edi # imm = 0x10000
callq malloc
movq %rax, %rbx
movl $65536, %edi # imm = 0x10000
callq malloc
movq %rax, %r14
movl $65536, %edi # imm = 0x10000
callq malloc
movq %rax, %r15
movl $65536, %edi # imm = 0x10000
callq malloc
movq %rax, %r12
movl $65536, %edi # imm = 0x10000
callq malloc
testq %rbx, %rbx
je .LBB4_72
# %bb.1:
testq %r14, %r14
je .LBB4_72
# %bb.2:
testq %r15, %r15
je .LBB4_72
# %bb.3:
testq %r12, %r12
je .LBB4_72
# %bb.4:
movq %rax, %r13
testq %rax, %rax
je .LBB4_72
# %bb.5: # %.preheader211.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_6: # %.preheader211
# =>This Inner Loop Header: Depth=1
leaq (%rbx,%rbp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
addq $4, %rbp
cmpq $65536, %rbp # imm = 0x10000
jne .LBB4_6
# %bb.7: # %.preheader210.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_8: # %.preheader210
# =>This Inner Loop Header: Depth=1
leaq (%r14,%rbp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
addq $4, %rbp
cmpq $65536, %rbp # imm = 0x10000
jne .LBB4_8
# %bb.9:
movq $0, 112(%rsp)
leaq 112(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
testl %eax, %eax
jne .LBB4_10
# %bb.12:
movq $0, 104(%rsp)
leaq 104(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
testl %eax, %eax
jne .LBB4_13
# %bb.14:
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
testl %eax, %eax
jne .LBB4_15
# %bb.16:
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
testl %eax, %eax
jne .LBB4_17
# %bb.18:
movq $0, 96(%rsp)
leaq 96(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
testl %eax, %eax
jne .LBB4_19
# %bb.20:
movq 112(%rsp), %rdi
movl $65536, %edx # imm = 0x10000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_21
# %bb.22:
movq 104(%rsp), %rdi
movl $65536, %edx # imm = 0x10000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_23
# %bb.24:
movabsq $8589934596, %rdi # imm = 0x200000004
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $2, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_26
# %bb.25:
movq 112(%rsp), %rax
movq 104(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 40(%rsp)
movl $65536, 124(%rsp) # imm = 0x10000
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 124(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z15process_kernel1PfS_S_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_26:
callq hipGetLastError
testl %eax, %eax
jne .LBB4_27
# %bb.28:
movabsq $34359738370, %rbp # imm = 0x800000002
leaq 6(%rbp), %rdx
movq %rbp, %rdi
movl $1, %esi
movl $16, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_30
# %bb.29:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $65536, 24(%rsp) # imm = 0x10000
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z15process_kernel2PfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_30:
callq hipGetLastError
testl %eax, %eax
jne .LBB4_31
# %bb.32:
addq $126, %rbp
movabsq $4294967312, %rdi # imm = 0x100000010
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_34
# %bb.33:
movq 8(%rsp), %rax
movq 96(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $65536, 24(%rsp) # imm = 0x10000
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z15process_kernel3PfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_34:
callq hipGetLastError
testl %eax, %eax
jne .LBB4_35
# %bb.36:
movq 16(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_37
# %bb.38:
movq 8(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_39
# %bb.40:
movq 96(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_73
# %bb.41: # %.preheader209.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_42: # %.preheader209
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq sinf
movss %xmm0, 120(%rsp) # 4-byte Spill
movss (%r14,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq cosf
addss 120(%rsp), %xmm0 # 4-byte Folded Reload
subss (%r15,%rbp,4), %xmm0
andps .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd .LCPI4_1(%rip), %xmm0
ja .LBB4_43
# %bb.45: # in Loop: Header=BB4_42 Depth=1
incq %rbp
cmpq $16384, %rbp # imm = 0x4000
jne .LBB4_42
# %bb.46: # %.preheader208.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_47: # %.preheader208
# =>This Inner Loop Header: Depth=1
movss (%r15,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq logf
subss (%r12,%rbp,4), %xmm0
andps .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd .LCPI4_1(%rip), %xmm0
ja .LBB4_48
# %bb.49: # in Loop: Header=BB4_47 Depth=1
incq %rbp
cmpq $16384, %rbp # imm = 0x4000
jne .LBB4_47
# %bb.50: # %.preheader.preheader
xorl %ebp, %ebp
xorps %xmm1, %xmm1
.p2align 4, 0x90
.LBB4_51: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%r12,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jb .LBB4_56
# %bb.52: # in Loop: Header=BB4_51 Depth=1
sqrtss %xmm0, %xmm0
jmp .LBB4_57
.p2align 4, 0x90
.LBB4_56: # %call.sqrt
# in Loop: Header=BB4_51 Depth=1
callq sqrtf
xorps %xmm1, %xmm1
.LBB4_57: # %.preheader.split
# in Loop: Header=BB4_51 Depth=1
subss (%r13,%rbp,4), %xmm0
andps .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd .LCPI4_1(%rip), %xmm0
ja .LBB4_58
# %bb.59: # in Loop: Header=BB4_51 Depth=1
incq %rbp
cmpq $16384, %rbp # imm = 0x4000
jne .LBB4_51
# %bb.60: # %.lr.ph.i.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_53: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%r13,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbp
cmpq $16384, %rbp # imm = 0x4000
jne .LBB4_53
# %bb.54: # %_Z11print_arrayPfi.exit
movl $10, %edi
callq putchar@PLT
movq 112(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_55
# %bb.61:
movq 104(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_62
# %bb.63:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_64
# %bb.65:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_66
# %bb.67:
movq 96(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_68
# %bb.69:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq %r13, %rdi
callq free
callq hipDeviceReset
testl %eax, %eax
jne .LBB4_70
# %bb.71:
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_43:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rdi
movl $.L.str.17, %esi
jmp .LBB4_44
.LBB4_48:
movq stderr(%rip), %rdi
movl $.L.str.18, %esi
jmp .LBB4_44
.LBB4_58:
movq stderr(%rip), %rdi
movl $.L.str.19, %esi
.LBB4_44:
movl %ebp, %edx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB4_72:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $33, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB4_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
jmp .LBB4_11
.LBB4_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
jmp .LBB4_11
.LBB4_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
jmp .LBB4_11
.LBB4_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
jmp .LBB4_11
.LBB4_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
jmp .LBB4_11
.LBB4_21:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %esi
jmp .LBB4_11
.LBB4_23:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
jmp .LBB4_11
.LBB4_27:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %esi
jmp .LBB4_11
.LBB4_31:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
jmp .LBB4_11
.LBB4_35:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.13, %esi
jmp .LBB4_11
.LBB4_37:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.14, %esi
jmp .LBB4_11
.LBB4_39:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
jmp .LBB4_11
.LBB4_73:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
jmp .LBB4_11
.LBB4_55:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.20, %esi
jmp .LBB4_11
.LBB4_62:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.21, %esi
jmp .LBB4_11
.LBB4_64:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.22, %esi
jmp .LBB4_11
.LBB4_66:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.23, %esi
jmp .LBB4_11
.LBB4_68:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.24, %esi
jmp .LBB4_11
.LBB4_70:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.25, %esi
.LBB4_11:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15process_kernel1PfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15process_kernel2PfS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15process_kernel3PfS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.2f "
.size .L.str, 6
.type _Z15process_kernel1PfS_S_i,@object # @_Z15process_kernel1PfS_S_i
.section .rodata,"a",@progbits
.globl _Z15process_kernel1PfS_S_i
.p2align 3, 0x0
_Z15process_kernel1PfS_S_i:
.quad _Z30__device_stub__process_kernel1PfS_S_i
.size _Z15process_kernel1PfS_S_i, 8
.type _Z15process_kernel2PfS_i,@object # @_Z15process_kernel2PfS_i
.globl _Z15process_kernel2PfS_i
.p2align 3, 0x0
_Z15process_kernel2PfS_i:
.quad _Z30__device_stub__process_kernel2PfS_i
.size _Z15process_kernel2PfS_i, 8
.type _Z15process_kernel3PfS_i,@object # @_Z15process_kernel3PfS_i
.globl _Z15process_kernel3PfS_i
.p2align 3, 0x0
_Z15process_kernel3PfS_i:
.quad _Z30__device_stub__process_kernel3PfS_i
.size _Z15process_kernel3PfS_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Failed to allocate host vectors!\n"
.size .L.str.2, 34
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to allocate device vector d_input1 (error code %s)!\n"
.size .L.str.4, 60
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to allocate device vector d_input2 (error code %s)!\n"
.size .L.str.5, 60
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Failed to allocate device vector h_output1 (error code %s)!\n"
.size .L.str.6, 61
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to allocate device vector h_output2 (error code %s)!\n"
.size .L.str.7, 61
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to allocate device vector h_output3 (error code %s)!\n"
.size .L.str.8, 61
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Failed to copy vector h_input1 from host to device (error code %s)!\n"
.size .L.str.9, 69
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Failed to copy vector h_input2 from host to device (error code %s)!\n"
.size .L.str.10, 69
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Failed to launch process_kernel1 kernel (error code %s)!\n"
.size .L.str.11, 58
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Failed to launch process_kernel2 kernel (error code %s)!\n"
.size .L.str.12, 58
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Failed to launch process_kernel3 kernel (error code %s)!\n"
.size .L.str.13, 58
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Failed to copy vector d_output1 from device to host (error code %s)!\n"
.size .L.str.14, 70
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Failed to copy vector d_output2 from device to host (error code %s)!\n"
.size .L.str.15, 70
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Failed to copy vector d_output3 from device to host (error code %s)!\n"
.size .L.str.16, 70
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Result verification for h_output1 failed at element %d!\n"
.size .L.str.17, 57
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Result verification for h_output2 failed at element %d!\n"
.size .L.str.18, 57
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Result verification for h_output3 failed at element %d!\n"
.size .L.str.19, 57
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "Failed to free device vector d_input1 (error code %s)!\n"
.size .L.str.20, 56
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "Failed to free device vector d_input2 (error code %s)!\n"
.size .L.str.21, 56
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "Failed to free device vector d_output1 (error code %s)!\n"
.size .L.str.22, 57
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "Failed to free device vector d_output2 (error code %s)!\n"
.size .L.str.23, 57
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "Failed to free device vector d_output3 (error code %s)!\n"
.size .L.str.24, 57
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz "Failed to deinitialize the device! error=%s\n"
.size .L.str.25, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15process_kernel1PfS_S_i"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15process_kernel2PfS_i"
.size .L__unnamed_2, 25
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z15process_kernel3PfS_i"
.size .L__unnamed_3, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__process_kernel1PfS_S_i
.addrsig_sym _Z30__device_stub__process_kernel2PfS_i
.addrsig_sym _Z30__device_stub__process_kernel3PfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15process_kernel1PfS_S_i
.addrsig_sym _Z15process_kernel2PfS_i
.addrsig_sym _Z15process_kernel3PfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void matSum(float* S, float* A, float* B, int N) {
int i = blockIdx.y*blockDim.y + threadIdx.y;
int j = blockIdx.x*blockDim.x + threadIdx.x;
int tid = i*N + j;
if (tid < N*N) {
S[tid] = A[tid] + B[tid];
}
} | code for sm_80
Function : _Z6matSumPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0050*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fc400078e0203 */
/*0080*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R0, c[0x0][0x178], R3 ; /* 0x00005e0000007a24 */
/* 0x000fca00078e0203 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00e0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0207 */
/*00f0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x0c0fe400078e0207 */
/*0100*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0207 */
/*0130*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0140*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void matSum(float* S, float* A, float* B, int N) {
int i = blockIdx.y*blockDim.y + threadIdx.y;
int j = blockIdx.x*blockDim.x + threadIdx.x;
int tid = i*N + j;
if (tid < N*N) {
S[tid] = A[tid] + B[tid];
}
} | .file "tmpxft_000e9958_00000000-6_matSum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6matSumPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6matSumPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6matSumPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matSumPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6matSumPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6matSumPfS_S_iPfS_S_i
.globl _Z6matSumPfS_S_i
.type _Z6matSumPfS_S_i, @function
_Z6matSumPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6matSumPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6matSumPfS_S_i, .-_Z6matSumPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6matSumPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matSumPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void matSum(float* S, float* A, float* B, int N) {
int i = blockIdx.y*blockDim.y + threadIdx.y;
int j = blockIdx.x*blockDim.x + threadIdx.x;
int tid = i*N + j;
if (tid < N*N) {
S[tid] = A[tid] + B[tid];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matSum(float* S, float* A, float* B, int N) {
int i = blockIdx.y*blockDim.y + threadIdx.y;
int j = blockIdx.x*blockDim.x + threadIdx.x;
int tid = i*N + j;
if (tid < N*N) {
S[tid] = A[tid] + B[tid];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matSum(float* S, float* A, float* B, int N) {
int i = blockIdx.y*blockDim.y + threadIdx.y;
int j = blockIdx.x*blockDim.x + threadIdx.x;
int tid = i*N + j;
if (tid < N*N) {
S[tid] = A[tid] + B[tid];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matSumPfS_S_i
.globl _Z6matSumPfS_S_i
.p2align 8
.type _Z6matSumPfS_S_i,@function
_Z6matSumPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_mul_i32 s14, s14, s2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s3
s_mul_i32 s3, s3, s3
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matSumPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matSumPfS_S_i, .Lfunc_end0-_Z6matSumPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matSumPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matSumPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matSum(float* S, float* A, float* B, int N) {
int i = blockIdx.y*blockDim.y + threadIdx.y;
int j = blockIdx.x*blockDim.x + threadIdx.x;
int tid = i*N + j;
if (tid < N*N) {
S[tid] = A[tid] + B[tid];
}
} | .text
.file "matSum.hip"
.globl _Z21__device_stub__matSumPfS_S_i # -- Begin function _Z21__device_stub__matSumPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__matSumPfS_S_i,@function
_Z21__device_stub__matSumPfS_S_i: # @_Z21__device_stub__matSumPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matSumPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__matSumPfS_S_i, .Lfunc_end0-_Z21__device_stub__matSumPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matSumPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matSumPfS_S_i,@object # @_Z6matSumPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6matSumPfS_S_i
.p2align 3, 0x0
_Z6matSumPfS_S_i:
.quad _Z21__device_stub__matSumPfS_S_i
.size _Z6matSumPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6matSumPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matSumPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matSumPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6matSumPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0050*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fc400078e0203 */
/*0080*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R0, c[0x0][0x178], R3 ; /* 0x00005e0000007a24 */
/* 0x000fca00078e0203 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00e0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0207 */
/*00f0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x0c0fe400078e0207 */
/*0100*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0207 */
/*0130*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0140*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matSumPfS_S_i
.globl _Z6matSumPfS_S_i
.p2align 8
.type _Z6matSumPfS_S_i,@function
_Z6matSumPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_mul_i32 s14, s14, s2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s3
s_mul_i32 s3, s3, s3
v_add3_u32 v0, s14, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matSumPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matSumPfS_S_i, .Lfunc_end0-_Z6matSumPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matSumPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matSumPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e9958_00000000-6_matSum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6matSumPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6matSumPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6matSumPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matSumPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6matSumPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6matSumPfS_S_iPfS_S_i
.globl _Z6matSumPfS_S_i
.type _Z6matSumPfS_S_i, @function
_Z6matSumPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6matSumPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6matSumPfS_S_i, .-_Z6matSumPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6matSumPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matSumPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matSum.hip"
.globl _Z21__device_stub__matSumPfS_S_i # -- Begin function _Z21__device_stub__matSumPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__matSumPfS_S_i,@function
_Z21__device_stub__matSumPfS_S_i: # @_Z21__device_stub__matSumPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matSumPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__matSumPfS_S_i, .Lfunc_end0-_Z21__device_stub__matSumPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matSumPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matSumPfS_S_i,@object # @_Z6matSumPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6matSumPfS_S_i
.p2align 3, 0x0
_Z6matSumPfS_S_i:
.quad _Z21__device_stub__matSumPfS_S_i
.size _Z6matSumPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6matSumPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matSumPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matSumPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C" __constant__ int my_constant = 314;
extern "C" __global__ void sum(const float* x, const float* y, float* out, int count) {
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < count; i += blockDim.x * gridDim.x) {
out[i] = x[i] + y[i];
}
} | code for sm_80
Function : sum
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0100*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101904 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C" __constant__ int my_constant = 314;
extern "C" __global__ void sum(const float* x, const float* y, float* out, int count) {
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < count; i += blockDim.x * gridDim.x) {
out[i] = x[i] + y[i];
}
} | .file "tmpxft_00186acd_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi
.type _Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi, @function
_Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq sum(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi, .-_Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi
.globl sum
.type sum, @function
sum:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size sum, .-sum
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "sum"
.LC1:
.string "my_constant"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq sum(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq my_constant(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C" __constant__ int my_constant = 314;
extern "C" __global__ void sum(const float* x, const float* y, float* out, int count) {
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < count; i += blockDim.x * gridDim.x) {
out[i] = x[i] + y[i];
}
} | #include <hip/hip_runtime.h>
extern "C" __constant__ int my_constant = 314;
extern "C" __global__ void sum(const float* x, const float* y, float* out, int count) {
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < count; i += blockDim.x * gridDim.x) {
out[i] = x[i] + y[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C" __constant__ int my_constant = 314;
extern "C" __global__ void sum(const float* x, const float* y, float* out, int count) {
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < count; i += blockDim.x * gridDim.x) {
out[i] = x[i] + y[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected sum
.globl sum
.p2align 8
.type sum,@function
sum:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s10, s9
s_mov_b32 s9, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, s0, s2, v2
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s1, v1
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_store_b32 v[2:3], v0, off
s_or_b32 s9, vcc_lo, s9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel sum
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size sum, .Lfunc_end0-sum
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected my_constant
.type my_constant,@object
.data
.globl my_constant
.p2align 2, 0x0
my_constant:
.long 314
.size my_constant, 4
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: sum
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: sum.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C" __constant__ int my_constant = 314;
extern "C" __global__ void sum(const float* x, const float* y, float* out, int count) {
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < count; i += blockDim.x * gridDim.x) {
out[i] = x[i] + y[i];
}
} | .text
.file "add.hip"
.globl __device_stub__sum # -- Begin function __device_stub__sum
.p2align 4, 0x90
.type __device_stub__sum,@function
__device_stub__sum: # @__device_stub__sum
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $sum, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__sum, .Lfunc_end0-__device_stub__sum
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $sum, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $my_constant, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type my_constant,@object # @my_constant
.local my_constant
.comm my_constant,4,4
.type sum,@object # @sum
.section .rodata,"a",@progbits
.globl sum
.p2align 3, 0x0
sum:
.quad __device_stub__sum
.size sum, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "sum"
.size .L__unnamed_1, 4
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "my_constant"
.size .L__unnamed_2, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__sum
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym my_constant
.addrsig_sym sum
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : sum
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0100*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101904 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected sum
.globl sum
.p2align 8
.type sum,@function
sum:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s10, s9
s_mov_b32 s9, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, s0, s2, v2
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s1, v1
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_store_b32 v[2:3], v0, off
s_or_b32 s9, vcc_lo, s9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel sum
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size sum, .Lfunc_end0-sum
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected my_constant
.type my_constant,@object
.data
.globl my_constant
.p2align 2, 0x0
my_constant:
.long 314
.size my_constant, 4
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: sum
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: sum.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00186acd_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi
.type _Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi, @function
_Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq sum(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi, .-_Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi
.globl sum
.type sum, @function
sum:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z3sumPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size sum, .-sum
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "sum"
.LC1:
.string "my_constant"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq sum(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq my_constant(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl __device_stub__sum # -- Begin function __device_stub__sum
.p2align 4, 0x90
.type __device_stub__sum,@function
__device_stub__sum: # @__device_stub__sum
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $sum, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__sum, .Lfunc_end0-__device_stub__sum
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $sum, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $my_constant, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type my_constant,@object # @my_constant
.local my_constant
.comm my_constant,4,4
.type sum,@object # @sum
.section .rodata,"a",@progbits
.globl sum
.p2align 3, 0x0
sum:
.quad __device_stub__sum
.size sum, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "sum"
.size .L__unnamed_1, 4
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "my_constant"
.size .L__unnamed_2, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__sum
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym my_constant
.addrsig_sym sum
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
/**
* This file contains all the functors used for triSolver
x_prime means that list is [i-1]
a => a[i]
a_prime => a[i-1]
**/
/**
* returns c/(b-a*c_prime)
**/
struct Hydrogen{
__host__ __device__
double operator()(double a, double b, double c , double c_prime){
double x = a*c_prime;
double y = b - x;
return c/y;
}
};
struct Helium{
__host__ __device__
double operator()(double a, double b, double d, double c_prime, double d_prime){
double x = a * d_prime;
double y = a * c_prime;
double A = d - x;
double B = b - y;
return A/B;
}
};
struct Silicon{
//d_prime => d[i+1]
__host__ __device__
double operator()(double c, double d, double d_prime){
double x = c * d_prime;
return d - x;
}
}; | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
/**
* This file contains all the functors used for triSolver
x_prime means that list is [i-1]
a => a[i]
a_prime => a[i-1]
**/
/**
* returns c/(b-a*c_prime)
**/
struct Hydrogen{
__host__ __device__
double operator()(double a, double b, double c , double c_prime){
double x = a*c_prime;
double y = b - x;
return c/y;
}
};
struct Helium{
__host__ __device__
double operator()(double a, double b, double d, double c_prime, double d_prime){
double x = a * d_prime;
double y = a * c_prime;
double A = d - x;
double B = b - y;
return A/B;
}
};
struct Silicon{
//d_prime => d[i+1]
__host__ __device__
double operator()(double c, double d, double d_prime){
double x = c * d_prime;
return d - x;
}
}; | .file "tmpxft_0006d130_00000000-6_cu_functors.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
/**
* This file contains all the functors used for triSolver
x_prime means that list is [i-1]
a => a[i]
a_prime => a[i-1]
**/
/**
* returns c/(b-a*c_prime)
**/
struct Hydrogen{
__host__ __device__
double operator()(double a, double b, double c , double c_prime){
double x = a*c_prime;
double y = b - x;
return c/y;
}
};
struct Helium{
__host__ __device__
double operator()(double a, double b, double d, double c_prime, double d_prime){
double x = a * d_prime;
double y = a * c_prime;
double A = d - x;
double B = b - y;
return A/B;
}
};
struct Silicon{
//d_prime => d[i+1]
__host__ __device__
double operator()(double c, double d, double d_prime){
double x = c * d_prime;
return d - x;
}
}; | #include <hip/hip_runtime.h>
/**
* This file contains all the functors used for triSolver
x_prime means that list is [i-1]
a => a[i]
a_prime => a[i-1]
**/
/**
* returns c/(b-a*c_prime)
**/
struct Hydrogen{
__host__ __device__
double operator()(double a, double b, double c , double c_prime){
double x = a*c_prime;
double y = b - x;
return c/y;
}
};
struct Helium{
__host__ __device__
double operator()(double a, double b, double d, double c_prime, double d_prime){
double x = a * d_prime;
double y = a * c_prime;
double A = d - x;
double B = b - y;
return A/B;
}
};
struct Silicon{
//d_prime => d[i+1]
__host__ __device__
double operator()(double c, double d, double d_prime){
double x = c * d_prime;
return d - x;
}
}; |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/**
* This file contains all the functors used for triSolver
x_prime means that list is [i-1]
a => a[i]
a_prime => a[i-1]
**/
/**
* returns c/(b-a*c_prime)
**/
struct Hydrogen{
__host__ __device__
double operator()(double a, double b, double c , double c_prime){
double x = a*c_prime;
double y = b - x;
return c/y;
}
};
struct Helium{
__host__ __device__
double operator()(double a, double b, double d, double c_prime, double d_prime){
double x = a * d_prime;
double y = a * c_prime;
double A = d - x;
double B = b - y;
return A/B;
}
};
struct Silicon{
//d_prime => d[i+1]
__host__ __device__
double operator()(double c, double d, double d_prime){
double x = c * d_prime;
return d - x;
}
}; | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/**
* This file contains all the functors used for triSolver
x_prime means that list is [i-1]
a => a[i]
a_prime => a[i-1]
**/
/**
* returns c/(b-a*c_prime)
**/
struct Hydrogen{
__host__ __device__
double operator()(double a, double b, double c , double c_prime){
double x = a*c_prime;
double y = b - x;
return c/y;
}
};
struct Helium{
__host__ __device__
double operator()(double a, double b, double d, double c_prime, double d_prime){
double x = a * d_prime;
double y = a * c_prime;
double A = d - x;
double B = b - y;
return A/B;
}
};
struct Silicon{
//d_prime => d[i+1]
__host__ __device__
double operator()(double c, double d, double d_prime){
double x = c * d_prime;
return d - x;
}
}; | .text
.file "cu_functors.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006d130_00000000-6_cu_functors.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cu_functors.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <iostream>
#include <math.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
// CUDA kernel to add elements of two arrays
__global__
void add(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
int main(void)
{
int N = 1<<20;
float *x, *y;
printf("Allocate Unified Memory -- accessible from CPU or GPU\n");
gpuErrchk(cudaMallocManaged(&x, N*sizeof(float)));
gpuErrchk(cudaMallocManaged(&y, N*sizeof(float)));
printf("Initialize x and y arrays on the host\n");
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
printf("Launch kernel on 1M elements on the GPU\n");
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, x, y);
printf("Wait for GPU to finish before accessing on host\n");
gpuErrchk(cudaDeviceSynchronize());
printf("Check for errors (all values should be 3.0f)\n");
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
printf("Free memory\n");
gpuErrchk(cudaFree(x));
gpuErrchk(cudaFree(y));
return 0;
} | code for sm_80
Function : _Z3addiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x320 ; /* 0x0000029000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x160], R0 ; /* 0x0000580007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R4, RZ, RZ, -R2 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a02 */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x310 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R6, 0x4 ; /* 0x0000000400067802 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0004 */
/*0250*/ IMAD.WIDE R4, R3, R6, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0206 */
/*0270*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x0000a2000c1e1900 */
/*0290*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02c0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fca0000000000 */
/*02e0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*02f0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*0300*/ @P0 BRA 0x270 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0330*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x002fd400000001ff */
/*0340*/ IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0206 */
/*0350*/ IMAD.WIDE R6, R3, R6, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fe200078e0206 */
/*0360*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1900 */
/*0370*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0206 */
/*0390*/ FADD R17, R2, R9 ; /* 0x0000000902117221 */
/* 0x004fe40000000000 */
/*03a0*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x000fc600078e0204 */
/*03b0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e8000c101904 */
/*03c0*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc800078e020a */
/*03f0*/ FADD R19, R2, R13 ; /* 0x0000000d02137221 */
/* 0x004fe40000000000 */
/*0400*/ IMAD.WIDE R12, R0, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0208 */
/*0410*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0003e8000c101904 */
/*0420*/ LDG.E R2, [R14.64] ; /* 0x000000040e027981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R5, [R12.64] ; /* 0x000000040c057981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R6, R0, 0x4, R14 ; /* 0x0000000400067825 */
/* 0x001fc800078e020e */
/*0450*/ FADD R21, R2, R5 ; /* 0x0000000502157221 */
/* 0x004fe40000000000 */
/*0460*/ IMAD.WIDE R4, R0, 0x4, R12 ; /* 0x0000000400047825 */
/* 0x000fc600078e020c */
/*0470*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04b0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fe20003f06270 */
/*04d0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*04e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0003ee000c101904 */
/*04f0*/ @!P0 BRA 0x330 ; /* 0xfffffe3000008947 */
/* 0x000fea000383ffff */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <iostream>
#include <math.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
// CUDA kernel to add elements of two arrays
__global__
void add(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
int main(void)
{
int N = 1<<20;
float *x, *y;
printf("Allocate Unified Memory -- accessible from CPU or GPU\n");
gpuErrchk(cudaMallocManaged(&x, N*sizeof(float)));
gpuErrchk(cudaMallocManaged(&y, N*sizeof(float)));
printf("Initialize x and y arrays on the host\n");
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
printf("Launch kernel on 1M elements on the GPU\n");
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, x, y);
printf("Wait for GPU to finish before accessing on host\n");
gpuErrchk(cudaDeviceSynchronize());
printf("Check for errors (all values should be 3.0f)\n");
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
printf("Free memory\n");
gpuErrchk(cudaFree(x));
gpuErrchk(cudaFree(y));
return 0;
} | .file "tmpxft_0001ac97_00000000-6_add_grid.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB3669:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z25__device_stub__Z3addiPfS_iPfS_
.type _Z25__device_stub__Z3addiPfS_iPfS_, @function
_Z25__device_stub__Z3addiPfS_iPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z25__device_stub__Z3addiPfS_iPfS_, .-_Z25__device_stub__Z3addiPfS_iPfS_
.globl _Z3addiPfS_
.type _Z3addiPfS_, @function
_Z3addiPfS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3addiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z3addiPfS_, .-_Z3addiPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Allocate Unified Memory -- accessible from CPU or GPU\n"
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/tonivega/GVirtuS/master/plugins/cudart/demo/add_grid.cu"
.align 8
.LC4:
.string "Initialize x and y arrays on the host\n"
.align 8
.LC7:
.string "Launch kernel on 1M elements on the GPU\n"
.align 8
.LC8:
.string "Wait for GPU to finish before accessing on host\n"
.align 8
.LC9:
.string "Check for errors (all values should be 3.0f)\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC12:
.string "Max error: "
.LC13:
.string "Free memory\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
movl $1, %ecx
movl $32, %edx
leaq .LC3(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 24(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
movl $1, %ecx
movl $33, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
movss .LC5(%rip), %xmm1
movss .LC6(%rip), %xmm0
.L20:
movq 16(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 24(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L20
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $4096, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L21:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $47, %edx
leaq .LC3(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rbx
leaq 4194304(%rbx), %rbp
movl $0x00000000, 12(%rsp)
.L22:
movss (%rbx), %xmm0
subss .LC10(%rip), %xmm0
andps .LC11(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L22
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $56, %edx
leaq .LC3(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $57, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl $1048576, %edi
call _Z25__device_stub__Z3addiPfS_iPfS_
jmp .L21
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z3addiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1065353216
.align 4
.LC6:
.long 1073741824
.align 4
.LC10:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC11:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <iostream>
#include <math.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
// CUDA kernel to add elements of two arrays
__global__
void add(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
int main(void)
{
int N = 1<<20;
float *x, *y;
printf("Allocate Unified Memory -- accessible from CPU or GPU\n");
gpuErrchk(cudaMallocManaged(&x, N*sizeof(float)));
gpuErrchk(cudaMallocManaged(&y, N*sizeof(float)));
printf("Initialize x and y arrays on the host\n");
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
printf("Launch kernel on 1M elements on the GPU\n");
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, x, y);
printf("Wait for GPU to finish before accessing on host\n");
gpuErrchk(cudaDeviceSynchronize());
printf("Check for errors (all values should be 3.0f)\n");
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
printf("Free memory\n");
gpuErrchk(cudaFree(x));
gpuErrchk(cudaFree(y));
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <math.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
// CUDA kernel to add elements of two arrays
__global__
void add(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
int main(void)
{
int N = 1<<20;
float *x, *y;
printf("Allocate Unified Memory -- accessible from CPU or GPU\n");
gpuErrchk(hipMallocManaged(&x, N*sizeof(float)));
gpuErrchk(hipMallocManaged(&y, N*sizeof(float)));
printf("Initialize x and y arrays on the host\n");
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
printf("Launch kernel on 1M elements on the GPU\n");
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, x, y);
printf("Wait for GPU to finish before accessing on host\n");
gpuErrchk(hipDeviceSynchronize());
printf("Check for errors (all values should be 3.0f)\n");
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
printf("Free memory\n");
gpuErrchk(hipFree(x));
gpuErrchk(hipFree(y));
return 0;
} |
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