system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <math.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
// CUDA kernel to add elements of two arrays
__global__
void add(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
int main(void)
{
int N = 1<<20;
float *x, *y;
printf("Allocate Unified Memory -- accessible from CPU or GPU\n");
gpuErrchk(hipMallocManaged(&x, N*sizeof(float)));
gpuErrchk(hipMallocManaged(&y, N*sizeof(float)));
printf("Initialize x and y arrays on the host\n");
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
printf("Launch kernel on 1M elements on the GPU\n");
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, x, y);
printf("Wait for GPU to finish before accessing on host\n");
gpuErrchk(hipDeviceSynchronize());
printf("Check for errors (all values should be 3.0f)\n");
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
printf("Free memory\n");
gpuErrchk(hipFree(x));
gpuErrchk(hipFree(y));
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPfS_
.globl _Z3addiPfS_
.p2align 8
.type _Z3addiPfS_,@function
_Z3addiPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s8
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s2, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e64 s0, s10, v1
global_store_b32 v[6:7], v0, off
s_or_b32 s1, s0, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPfS_, .Lfunc_end0-_Z3addiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <math.h>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
// CUDA kernel to add elements of two arrays
__global__
void add(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
int main(void)
{
int N = 1<<20;
float *x, *y;
printf("Allocate Unified Memory -- accessible from CPU or GPU\n");
gpuErrchk(hipMallocManaged(&x, N*sizeof(float)));
gpuErrchk(hipMallocManaged(&y, N*sizeof(float)));
printf("Initialize x and y arrays on the host\n");
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
printf("Launch kernel on 1M elements on the GPU\n");
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, x, y);
printf("Wait for GPU to finish before accessing on host\n");
gpuErrchk(hipDeviceSynchronize());
printf("Check for errors (all values should be 3.0f)\n");
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
printf("Free memory\n");
gpuErrchk(hipFree(x));
gpuErrchk(hipFree(y));
return 0;
} | .text
.file "add_grid.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiPfS_ # -- Begin function _Z18__device_stub__addiPfS_
.p2align 4, 0x90
.type _Z18__device_stub__addiPfS_,@function
_Z18__device_stub__addiPfS_: # @_Z18__device_stub__addiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPfS_, .Lfunc_end0-_Z18__device_stub__addiPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl $.Lstr, %edi
callq puts@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit28
movl $.Lstr.1, %edi
callq puts@PLT
movq 16(%rsp), %rax
xorl %ecx, %ecx
movq 8(%rsp), %rdx
.p2align 4, 0x90
.LBB1_6: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB1_6
# %bb.7:
movl $.Lstr.2, %edi
callq puts@PLT
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $1048576, 28(%rsp) # imm = 0x100000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_9:
movl $.Lstr.3, %edi
callq puts@PLT
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_10
# %bb.20: # %_Z9gpuAssert10hipError_tPKcib.exit30
movl $.Lstr.4, %edi
callq puts@PLT
xorps %xmm2, %xmm2
xorl %eax, %eax
movq 8(%rsp), %rcx
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_21: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_21
# %bb.11:
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $11, %edx
movaps %xmm5, 128(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 128(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_22
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_14
# %bb.13:
movzbl 67(%rbx), %ecx
jmp .LBB1_15
.LBB1_14:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.Lstr.5, %edi
callq puts@PLT
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit32
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_18
# %bb.19: # %_Z9gpuAssert10hipError_tPKcib.exit34
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $34, %r8d
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $35, %r8d
jmp .LBB1_2
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $49, %r8d
jmp .LBB1_2
.LBB1_22:
callq _ZSt16__throw_bad_castv
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $58, %r8d
jmp .LBB1_2
.LBB1_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $59, %r8d
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiPfS_,@object # @_Z3addiPfS_
.section .rodata,"a",@progbits
.globl _Z3addiPfS_
.p2align 3, 0x0
_Z3addiPfS_:
.quad _Z18__device_stub__addiPfS_
.size _Z3addiPfS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/tonivega/GVirtuS/master/plugins/cudart/demo/add_grid.hip"
.size .L.str.1, 114
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Max error: "
.size .L.str.6, 12
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.8, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiPfS_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Allocate Unified Memory -- accessible from CPU or GPU"
.size .Lstr, 54
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Initialize x and y arrays on the host"
.size .Lstr.1, 38
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Launch kernel on 1M elements on the GPU"
.size .Lstr.2, 40
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Wait for GPU to finish before accessing on host"
.size .Lstr.3, 48
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Check for errors (all values should be 3.0f)"
.size .Lstr.4, 45
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Free memory"
.size .Lstr.5, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x320 ; /* 0x0000029000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x160], R0 ; /* 0x0000580007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R4, RZ, RZ, -R2 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a02 */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x310 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R6, 0x4 ; /* 0x0000000400067802 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0004 */
/*0250*/ IMAD.WIDE R4, R3, R6, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0206 */
/*0270*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x0000a2000c1e1900 */
/*0290*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02c0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fca0000000000 */
/*02e0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*02f0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*0300*/ @P0 BRA 0x270 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0330*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x002fd400000001ff */
/*0340*/ IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0206 */
/*0350*/ IMAD.WIDE R6, R3, R6, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fe200078e0206 */
/*0360*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1900 */
/*0370*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0206 */
/*0390*/ FADD R17, R2, R9 ; /* 0x0000000902117221 */
/* 0x004fe40000000000 */
/*03a0*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x000fc600078e0204 */
/*03b0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e8000c101904 */
/*03c0*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc800078e020a */
/*03f0*/ FADD R19, R2, R13 ; /* 0x0000000d02137221 */
/* 0x004fe40000000000 */
/*0400*/ IMAD.WIDE R12, R0, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0208 */
/*0410*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0003e8000c101904 */
/*0420*/ LDG.E R2, [R14.64] ; /* 0x000000040e027981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R5, [R12.64] ; /* 0x000000040c057981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R6, R0, 0x4, R14 ; /* 0x0000000400067825 */
/* 0x001fc800078e020e */
/*0450*/ FADD R21, R2, R5 ; /* 0x0000000502157221 */
/* 0x004fe40000000000 */
/*0460*/ IMAD.WIDE R4, R0, 0x4, R12 ; /* 0x0000000400047825 */
/* 0x000fc600078e020c */
/*0470*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04b0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fe20003f06270 */
/*04d0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*04e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0003ee000c101904 */
/*04f0*/ @!P0 BRA 0x330 ; /* 0xfffffe3000008947 */
/* 0x000fea000383ffff */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPfS_
.globl _Z3addiPfS_
.p2align 8
.type _Z3addiPfS_,@function
_Z3addiPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s8
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s2, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e64 s0, s10, v1
global_store_b32 v[6:7], v0, off
s_or_b32 s1, s0, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPfS_, .Lfunc_end0-_Z3addiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001ac97_00000000-6_add_grid.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB3669:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z25__device_stub__Z3addiPfS_iPfS_
.type _Z25__device_stub__Z3addiPfS_iPfS_, @function
_Z25__device_stub__Z3addiPfS_iPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z25__device_stub__Z3addiPfS_iPfS_, .-_Z25__device_stub__Z3addiPfS_iPfS_
.globl _Z3addiPfS_
.type _Z3addiPfS_, @function
_Z3addiPfS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3addiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z3addiPfS_, .-_Z3addiPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Allocate Unified Memory -- accessible from CPU or GPU\n"
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/tonivega/GVirtuS/master/plugins/cudart/demo/add_grid.cu"
.align 8
.LC4:
.string "Initialize x and y arrays on the host\n"
.align 8
.LC7:
.string "Launch kernel on 1M elements on the GPU\n"
.align 8
.LC8:
.string "Wait for GPU to finish before accessing on host\n"
.align 8
.LC9:
.string "Check for errors (all values should be 3.0f)\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC12:
.string "Max error: "
.LC13:
.string "Free memory\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
movl $1, %ecx
movl $32, %edx
leaq .LC3(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 24(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
movl $1, %ecx
movl $33, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
movss .LC5(%rip), %xmm1
movss .LC6(%rip), %xmm0
.L20:
movq 16(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 24(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L20
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $4096, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L21:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $47, %edx
leaq .LC3(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rbx
leaq 4194304(%rbx), %rbp
movl $0x00000000, 12(%rsp)
.L22:
movss (%rbx), %xmm0
subss .LC10(%rip), %xmm0
andps .LC11(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L22
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $56, %edx
leaq .LC3(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $57, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl $1048576, %edi
call _Z25__device_stub__Z3addiPfS_iPfS_
jmp .L21
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z3addiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1065353216
.align 4
.LC6:
.long 1073741824
.align 4
.LC10:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC11:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add_grid.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiPfS_ # -- Begin function _Z18__device_stub__addiPfS_
.p2align 4, 0x90
.type _Z18__device_stub__addiPfS_,@function
_Z18__device_stub__addiPfS_: # @_Z18__device_stub__addiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPfS_, .Lfunc_end0-_Z18__device_stub__addiPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl $.Lstr, %edi
callq puts@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit28
movl $.Lstr.1, %edi
callq puts@PLT
movq 16(%rsp), %rax
xorl %ecx, %ecx
movq 8(%rsp), %rdx
.p2align 4, 0x90
.LBB1_6: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB1_6
# %bb.7:
movl $.Lstr.2, %edi
callq puts@PLT
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $1048576, 28(%rsp) # imm = 0x100000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_9:
movl $.Lstr.3, %edi
callq puts@PLT
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_10
# %bb.20: # %_Z9gpuAssert10hipError_tPKcib.exit30
movl $.Lstr.4, %edi
callq puts@PLT
xorps %xmm2, %xmm2
xorl %eax, %eax
movq 8(%rsp), %rcx
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_21: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_21
# %bb.11:
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $11, %edx
movaps %xmm5, 128(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 128(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_22
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_14
# %bb.13:
movzbl 67(%rbx), %ecx
jmp .LBB1_15
.LBB1_14:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.Lstr.5, %edi
callq puts@PLT
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit32
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_18
# %bb.19: # %_Z9gpuAssert10hipError_tPKcib.exit34
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $34, %r8d
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $35, %r8d
jmp .LBB1_2
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $49, %r8d
jmp .LBB1_2
.LBB1_22:
callq _ZSt16__throw_bad_castv
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $58, %r8d
jmp .LBB1_2
.LBB1_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $59, %r8d
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiPfS_,@object # @_Z3addiPfS_
.section .rodata,"a",@progbits
.globl _Z3addiPfS_
.p2align 3, 0x0
_Z3addiPfS_:
.quad _Z18__device_stub__addiPfS_
.size _Z3addiPfS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/tonivega/GVirtuS/master/plugins/cudart/demo/add_grid.hip"
.size .L.str.1, 114
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Max error: "
.size .L.str.6, 12
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.8, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiPfS_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Allocate Unified Memory -- accessible from CPU or GPU"
.size .Lstr, 54
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Initialize x and y arrays on the host"
.size .Lstr.1, 38
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Launch kernel on 1M elements on the GPU"
.size .Lstr.2, 40
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Wait for GPU to finish before accessing on host"
.size .Lstr.3, 48
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Check for errors (all values should be 3.0f)"
.size .Lstr.4, 45
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Free memory"
.size .Lstr.5, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void threshold(float *vec, int *bin, const int k_bin, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
// xIndex is a value from 1 to k from the vector ind
if ( (xIndex < n) & (bin[xIndex]>k_bin) )
vec[xIndex]=0.0f;
} | code for sm_80
Function : _Z9thresholdPfPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0005 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0080*/ ISETP.GT.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x004fc80003f04270 */
/*0090*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x174], !P0 ; /* 0x00005d0000007a0c */
/* 0x000fda0004706470 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fc800078010ff */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x164], RZ, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f14ff */
/*00d0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void threshold(float *vec, int *bin, const int k_bin, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
// xIndex is a value from 1 to k from the vector ind
if ( (xIndex < n) & (bin[xIndex]>k_bin) )
vec[xIndex]=0.0f;
} | .file "tmpxft_000515a3_00000000-6_threshold.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9thresholdPfPiiiPfPiii
.type _Z32__device_stub__Z9thresholdPfPiiiPfPiii, @function
_Z32__device_stub__Z9thresholdPfPiiiPfPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9thresholdPfPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z9thresholdPfPiiiPfPiii, .-_Z32__device_stub__Z9thresholdPfPiiiPfPiii
.globl _Z9thresholdPfPiii
.type _Z9thresholdPfPiii, @function
_Z9thresholdPfPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9thresholdPfPiiiPfPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9thresholdPfPiii, .-_Z9thresholdPfPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9thresholdPfPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9thresholdPfPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void threshold(float *vec, int *bin, const int k_bin, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
// xIndex is a value from 1 to k from the vector ind
if ( (xIndex < n) & (bin[xIndex]>k_bin) )
vec[xIndex]=0.0f;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void threshold(float *vec, int *bin, const int k_bin, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
// xIndex is a value from 1 to k from the vector ind
if ( (xIndex < n) & (bin[xIndex]>k_bin) )
vec[xIndex]=0.0f;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void threshold(float *vec, int *bin, const int k_bin, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
// xIndex is a value from 1 to k from the vector ind
if ( (xIndex < n) & (bin[xIndex]>k_bin) )
vec[xIndex]=0.0f;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9thresholdPfPiii
.globl _Z9thresholdPfPiii
.p2align 8
.type _Z9thresholdPfPiii,@function
_Z9thresholdPfPiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_cmp_gt_u32_e32 vcc_lo, s7, v1
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e64 s2, s6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v4, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9thresholdPfPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9thresholdPfPiii, .Lfunc_end0-_Z9thresholdPfPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9thresholdPfPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9thresholdPfPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void threshold(float *vec, int *bin, const int k_bin, const int n)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
// xIndex is a value from 1 to k from the vector ind
if ( (xIndex < n) & (bin[xIndex]>k_bin) )
vec[xIndex]=0.0f;
} | .text
.file "threshold.hip"
.globl _Z24__device_stub__thresholdPfPiii # -- Begin function _Z24__device_stub__thresholdPfPiii
.p2align 4, 0x90
.type _Z24__device_stub__thresholdPfPiii,@function
_Z24__device_stub__thresholdPfPiii: # @_Z24__device_stub__thresholdPfPiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9thresholdPfPiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__thresholdPfPiii, .Lfunc_end0-_Z24__device_stub__thresholdPfPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9thresholdPfPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9thresholdPfPiii,@object # @_Z9thresholdPfPiii
.section .rodata,"a",@progbits
.globl _Z9thresholdPfPiii
.p2align 3, 0x0
_Z9thresholdPfPiii:
.quad _Z24__device_stub__thresholdPfPiii
.size _Z9thresholdPfPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9thresholdPfPiii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__thresholdPfPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9thresholdPfPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9thresholdPfPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0005 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0080*/ ISETP.GT.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x004fc80003f04270 */
/*0090*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x174], !P0 ; /* 0x00005d0000007a0c */
/* 0x000fda0004706470 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fc800078010ff */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x164], RZ, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f14ff */
/*00d0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9thresholdPfPiii
.globl _Z9thresholdPfPiii
.p2align 8
.type _Z9thresholdPfPiii,@function
_Z9thresholdPfPiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_cmp_gt_u32_e32 vcc_lo, s7, v1
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e64 s2, s6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v4, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9thresholdPfPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9thresholdPfPiii, .Lfunc_end0-_Z9thresholdPfPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9thresholdPfPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9thresholdPfPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000515a3_00000000-6_threshold.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9thresholdPfPiiiPfPiii
.type _Z32__device_stub__Z9thresholdPfPiiiPfPiii, @function
_Z32__device_stub__Z9thresholdPfPiiiPfPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9thresholdPfPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z9thresholdPfPiiiPfPiii, .-_Z32__device_stub__Z9thresholdPfPiiiPfPiii
.globl _Z9thresholdPfPiii
.type _Z9thresholdPfPiii, @function
_Z9thresholdPfPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9thresholdPfPiiiPfPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9thresholdPfPiii, .-_Z9thresholdPfPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9thresholdPfPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9thresholdPfPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "threshold.hip"
.globl _Z24__device_stub__thresholdPfPiii # -- Begin function _Z24__device_stub__thresholdPfPiii
.p2align 4, 0x90
.type _Z24__device_stub__thresholdPfPiii,@function
_Z24__device_stub__thresholdPfPiii: # @_Z24__device_stub__thresholdPfPiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9thresholdPfPiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__thresholdPfPiii, .Lfunc_end0-_Z24__device_stub__thresholdPfPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9thresholdPfPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9thresholdPfPiii,@object # @_Z9thresholdPfPiii
.section .rodata,"a",@progbits
.globl _Z9thresholdPfPiii
.p2align 3, 0x0
_Z9thresholdPfPiii:
.quad _Z24__device_stub__thresholdPfPiii
.size _Z9thresholdPfPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9thresholdPfPiii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__thresholdPfPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9thresholdPfPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#define BLOCKSIZE 26
__global__ void dkernel() {
__shared__ char str[BLOCKSIZE+1];
str[threadIdx.x] = 'A' + (threadIdx.x + blockIdx.x) % BLOCKSIZE;
if (threadIdx.x == 0) {
str[BLOCKSIZE] = '\0';
}
//__syncthreads();
if (threadIdx.x == 0) {
printf("%d: %s\n", blockIdx.x, str);
}
}
int main() {
dkernel<<<10, BLOCKSIZE>>>();
cudaDeviceSynchronize();
} | code for sm_80
Function : _Z7dkernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0040*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f3e0ff */
/*0050*/ IMAD.IADD R0, R8, 0x1, R5 ; /* 0x0000000108007824 */
/* 0x001fe200078e0205 */
/*0060*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc60003f05270 */
/*0070*/ IMAD.WIDE.U32 R2, R0, 0x4ec4ec4f, RZ ; /* 0x4ec4ec4f00027825 */
/* 0x000fca00078e00ff */
/*0080*/ SHF.R.U32.HI R3, RZ, 0x3, R3 ; /* 0x00000003ff037819 */
/* 0x000fca0000011603 */
/*0090*/ IMAD R0, R3, -0x1a, R0 ; /* 0xffffffe603007824 */
/* 0x000fca00078e0200 */
/*00a0*/ IADD3 R0, R0, 0x41, RZ ; /* 0x0000004100007810 */
/* 0x000fca0007ffe0ff */
/*00b0*/ STS.U8 [R5], R0 ; /* 0x0000000005007388 */
/* 0x0001e20000000000 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x18] ; /* 0x00000600ff0a7624 */
/* 0x000fe200078e00ff */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe20000000f00 */
/*00f0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x1c] ; /* 0x00000700ff0b7624 */
/* 0x000fe200078e00ff */
/*0100*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0001e20000100800 */
/*0110*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe200008e06ff */
/*0120*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0000620000000a00 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0140*/ STL.64 [R1+0x8], R10 ; /* 0x0000080a01007387 */
/* 0x0001e20000100a00 */
/*0150*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fc600078e00ff */
/*0160*/ STS.U8 [0x1a], RZ ; /* 0x00001affff007388 */
/* 0x000fe80000000000 */
/*0170*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x001fe40000000000 */
/*0180*/ MOV R11, 0x1f0 ; /* 0x000001f0000b7802 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R20, 0x170 ; /* 0x0000017000147802 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*01c0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*01d0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*01e0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#define BLOCKSIZE 26
__global__ void dkernel() {
__shared__ char str[BLOCKSIZE+1];
str[threadIdx.x] = 'A' + (threadIdx.x + blockIdx.x) % BLOCKSIZE;
if (threadIdx.x == 0) {
str[BLOCKSIZE] = '\0';
}
//__syncthreads();
if (threadIdx.x == 0) {
printf("%d: %s\n", blockIdx.x, str);
}
}
int main() {
dkernel<<<10, BLOCKSIZE>>>();
cudaDeviceSynchronize();
} | .file "tmpxft_00056adf_00000000-6_shared.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z7dkernelvv
.type _Z25__device_stub__Z7dkernelvv, @function
_Z25__device_stub__Z7dkernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z7dkernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z7dkernelvv, .-_Z25__device_stub__Z7dkernelvv
.globl _Z7dkernelv
.type _Z7dkernelv, @function
_Z7dkernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z7dkernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7dkernelv, .-_Z7dkernelv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $26, 20(%rsp)
movl $1, 24(%rsp)
movl $10, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z25__device_stub__Z7dkernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7dkernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7dkernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#define BLOCKSIZE 26
__global__ void dkernel() {
__shared__ char str[BLOCKSIZE+1];
str[threadIdx.x] = 'A' + (threadIdx.x + blockIdx.x) % BLOCKSIZE;
if (threadIdx.x == 0) {
str[BLOCKSIZE] = '\0';
}
//__syncthreads();
if (threadIdx.x == 0) {
printf("%d: %s\n", blockIdx.x, str);
}
}
int main() {
dkernel<<<10, BLOCKSIZE>>>();
cudaDeviceSynchronize();
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#define BLOCKSIZE 26
__global__ void dkernel() {
__shared__ char str[BLOCKSIZE+1];
str[threadIdx.x] = 'A' + (threadIdx.x + blockIdx.x) % BLOCKSIZE;
if (threadIdx.x == 0) {
str[BLOCKSIZE] = '\0';
}
//__syncthreads();
if (threadIdx.x == 0) {
printf("%d: %s\n", blockIdx.x, str);
}
}
int main() {
dkernel<<<10, BLOCKSIZE>>>();
hipDeviceSynchronize();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define BLOCKSIZE 26
__global__ void dkernel() {
__shared__ char str[BLOCKSIZE+1];
str[threadIdx.x] = 'A' + (threadIdx.x + blockIdx.x) % BLOCKSIZE;
if (threadIdx.x == 0) {
str[BLOCKSIZE] = '\0';
}
//__syncthreads();
if (threadIdx.x == 0) {
printf("%d: %s\n", blockIdx.x, str);
}
}
int main() {
dkernel<<<10, BLOCKSIZE>>>();
hipDeviceSynchronize();
} | .text
.file "shared.hip"
.globl _Z22__device_stub__dkernelv # -- Begin function _Z22__device_stub__dkernelv
.p2align 4, 0x90
.type _Z22__device_stub__dkernelv,@function
_Z22__device_stub__dkernelv: # @_Z22__device_stub__dkernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7dkernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z22__device_stub__dkernelv, .Lfunc_end0-_Z22__device_stub__dkernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967306, %rdi # imm = 0x10000000A
leaq 16(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7dkernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7dkernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7dkernelv,@object # @_Z7dkernelv
.section .rodata,"a",@progbits
.globl _Z7dkernelv
.p2align 3, 0x0
_Z7dkernelv:
.quad _Z22__device_stub__dkernelv
.size _Z7dkernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7dkernelv"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__dkernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7dkernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00056adf_00000000-6_shared.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z7dkernelvv
.type _Z25__device_stub__Z7dkernelvv, @function
_Z25__device_stub__Z7dkernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z7dkernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z7dkernelvv, .-_Z25__device_stub__Z7dkernelvv
.globl _Z7dkernelv
.type _Z7dkernelv, @function
_Z7dkernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z7dkernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7dkernelv, .-_Z7dkernelv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $26, 20(%rsp)
movl $1, 24(%rsp)
movl $10, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z25__device_stub__Z7dkernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7dkernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7dkernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "shared.hip"
.globl _Z22__device_stub__dkernelv # -- Begin function _Z22__device_stub__dkernelv
.p2align 4, 0x90
.type _Z22__device_stub__dkernelv,@function
_Z22__device_stub__dkernelv: # @_Z22__device_stub__dkernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7dkernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z22__device_stub__dkernelv, .Lfunc_end0-_Z22__device_stub__dkernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967306, %rdi # imm = 0x10000000A
leaq 16(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7dkernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7dkernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7dkernelv,@object # @_Z7dkernelv
.section .rodata,"a",@progbits
.globl _Z7dkernelv
.p2align 3, 0x0
_Z7dkernelv:
.quad _Z22__device_stub__dkernelv
.size _Z7dkernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7dkernelv"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__dkernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7dkernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void naive_matrix_transpose(float *input, int axis_0, int axis_1, float *output)
{
__shared__ float tile[TILE_DIM][TILE_DIM + 1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
for (int i = 0; i < TILE_DIM && y + i < axis_1 && x < axis_0; i += BLOCK_HEIGHT) {
tile[threadIdx.y + i][threadIdx.x] = input[(y + i) * axis_0 + x];
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x;
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int i = 0; i < TILE_DIM && y + i < axis_1 && x < axis_0; i += BLOCK_HEIGHT) {
output[(y + i) * axis_0 + x] = tile[(threadIdx.x)][threadIdx.y + i];
}
} | code for sm_80
Function : _Z22naive_matrix_transposePfiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x280 ; /* 0x0000024000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R8, SR_TID.Y ; /* 0x0000000000087919 */
/* 0x000e280000002200 */
/*0050*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e680000002500 */
/*0060*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0070*/ LEA R5, R6, R8, 0x5 ; /* 0x0000000806057211 */
/* 0x001fc800078e28ff */
/*0080*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x16c], PT ; /* 0x00005b0005007a0c */
/* 0x000fe20003f06270 */
/*0090*/ IMAD R0, R4, 0x20, R9 ; /* 0x0000002004007824 */
/* 0x002fca00078e0209 */
/*00a0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*00b0*/ @P0 BRA 0x270 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R2, R5, c[0x0][0x168], R0 ; /* 0x00005a0005027a24 */
/* 0x000fd200078e0200 */
/*00e0*/ IMAD.WIDE R2, R2, R13, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e020d */
/*00f0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IMAD R11, R8, 0x21, R9 ; /* 0x00000021080b7824 */
/* 0x000fe200078e0209 */
/*0110*/ IADD3 R7, R5, 0x8, RZ ; /* 0x0000000805077810 */
/* 0x000fc80007ffe0ff */
/*0120*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x16c], PT ; /* 0x00005b0007007a0c */
/* 0x000fe20003f06270 */
/*0130*/ STS [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x0041d80000004800 */
/*0140*/ @P0 BRA 0x270 ; /* 0x0000012000000947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD R2, R7, c[0x0][0x168], R0 ; /* 0x00005a0007027a24 */
/* 0x001fc800078e0200 */
/*0160*/ IMAD.WIDE R2, R2, R13, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e020d */
/*0170*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IADD3 R7, R5, 0x10, RZ ; /* 0x0000001005077810 */
/* 0x000fc80007ffe0ff */
/*0190*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x16c], PT ; /* 0x00005b0007007a0c */
/* 0x000fe20003f06270 */
/*01a0*/ STS [R11.X4+0x420], R2 ; /* 0x000420020b007388 */
/* 0x0041d80000004800 */
/*01b0*/ @P0 BRA 0x270 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*01c0*/ IMAD R2, R7, c[0x0][0x168], R0 ; /* 0x00005a0007027a24 */
/* 0x001fc800078e0200 */
/*01d0*/ IMAD.WIDE R2, R2, R13, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e020d */
/*01e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*01f0*/ IADD3 R5, R5, 0x18, RZ ; /* 0x0000001805057810 */
/* 0x000fc80007ffe0ff */
/*0200*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x16c], PT ; /* 0x00005b0005007a0c */
/* 0x000fe20003f06270 */
/*0210*/ STS [R11.X4+0x840], R2 ; /* 0x000840020b007388 */
/* 0x0041d80000004800 */
/*0220*/ @P0 BRA 0x270 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0230*/ IMAD R2, R5, c[0x0][0x168], R0 ; /* 0x00005a0005027a24 */
/* 0x001fc800078e0200 */
/*0240*/ IMAD.WIDE R2, R2, R13, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e020d */
/*0250*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0260*/ STS [R11.X4+0xc60], R2 ; /* 0x000c60020b007388 */
/* 0x0041e40000004800 */
/*0270*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0290*/ IMAD R0, R4, 0x20, R8 ; /* 0x0000002004007824 */
/* 0x000fe200078e0208 */
/*02a0*/ LEA R5, R6, R9, 0x5 ; /* 0x0000000906057211 */
/* 0x000fc800078e28ff */
/*02b0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fc80003f06270 */
/*02c0*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x168], P0 ; /* 0x00005a0005007a0c */
/* 0x000fda0000706670 */
/*02d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02e0*/ IMAD R8, R9, 0x21, R8 ; /* 0x0000002109087824 */
/* 0x000fe200078e0208 */
/*02f0*/ IADD3 R4, R0.reuse, 0x8, RZ ; /* 0x0000000800047810 */
/* 0x040fe20007ffe0ff */
/*0300*/ IMAD R2, R0, c[0x0][0x168], R5 ; /* 0x00005a0000027a24 */
/* 0x001fe200078e0205 */
/*0310*/ MOV R9, 0x4 ; /* 0x0000000400097802 */
/* 0x000fe40000000f00 */
/*0320*/ LDS R7, [R8.X4] ; /* 0x0000000008077984 */
/* 0x000e220000004800 */
/*0330*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x16c], PT ; /* 0x00005b0004007a0c */
/* 0x000fe40003f06270 */
/*0340*/ IMAD.WIDE R2, R2, R9, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0209 */
/*0350*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0011ec000c101904 */
/*0360*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0370*/ LDS R7, [R8.X4+0x20] ; /* 0x0000200008077984 */
/* 0x001e220000004800 */
/*0380*/ IADD3 R6, R0, 0x10, RZ ; /* 0x0000001000067810 */
/* 0x000fe20007ffe0ff */
/*0390*/ IMAD R2, R4, c[0x0][0x168], R5 ; /* 0x00005a0004027a24 */
/* 0x000fc600078e0205 */
/*03a0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x16c], PT ; /* 0x00005b0006007a0c */
/* 0x000fe20003f06270 */
/*03b0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0209 */
/*03c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0011ee000c101904 */
/*03d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03e0*/ LDS R7, [R8.X4+0x40] ; /* 0x0000400008077984 */
/* 0x001e220000004800 */
/*03f0*/ IADD3 R0, R0, 0x18, RZ ; /* 0x0000001800007810 */
/* 0x000fe20007ffe0ff */
/*0400*/ IMAD R2, R6, c[0x0][0x168], R5 ; /* 0x00005a0006027a24 */
/* 0x000fc600078e0205 */
/*0410*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fe20003f06270 */
/*0420*/ IMAD.WIDE R2, R2, R9, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0209 */
/*0430*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0011ee000c101904 */
/*0440*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0450*/ LDS R7, [R8.X4+0x60] ; /* 0x0000600008077984 */
/* 0x001e220000004800 */
/*0460*/ IMAD R2, R0, c[0x0][0x168], R5 ; /* 0x00005a0000027a24 */
/* 0x000fc800078e0205 */
/*0470*/ IMAD.WIDE R2, R2, R9, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0209 */
/*0480*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101904 */
/*0490*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04a0*/ BRA 0x4a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void naive_matrix_transpose(float *input, int axis_0, int axis_1, float *output)
{
__shared__ float tile[TILE_DIM][TILE_DIM + 1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
for (int i = 0; i < TILE_DIM && y + i < axis_1 && x < axis_0; i += BLOCK_HEIGHT) {
tile[threadIdx.y + i][threadIdx.x] = input[(y + i) * axis_0 + x];
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x;
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int i = 0; i < TILE_DIM && y + i < axis_1 && x < axis_0; i += BLOCK_HEIGHT) {
output[(y + i) * axis_0 + x] = tile[(threadIdx.x)][threadIdx.y + i];
}
} | .file "tmpxft_0010b6a2_00000000-6_naive_matrix_transpose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z22naive_matrix_transposePfiiS_PfiiS_
.type _Z46__device_stub__Z22naive_matrix_transposePfiiS_PfiiS_, @function
_Z46__device_stub__Z22naive_matrix_transposePfiiS_PfiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22naive_matrix_transposePfiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z22naive_matrix_transposePfiiS_PfiiS_, .-_Z46__device_stub__Z22naive_matrix_transposePfiiS_PfiiS_
.globl _Z22naive_matrix_transposePfiiS_
.type _Z22naive_matrix_transposePfiiS_, @function
_Z22naive_matrix_transposePfiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z22naive_matrix_transposePfiiS_PfiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22naive_matrix_transposePfiiS_, .-_Z22naive_matrix_transposePfiiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22naive_matrix_transposePfiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22naive_matrix_transposePfiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void naive_matrix_transpose(float *input, int axis_0, int axis_1, float *output)
{
__shared__ float tile[TILE_DIM][TILE_DIM + 1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
for (int i = 0; i < TILE_DIM && y + i < axis_1 && x < axis_0; i += BLOCK_HEIGHT) {
tile[threadIdx.y + i][threadIdx.x] = input[(y + i) * axis_0 + x];
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x;
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int i = 0; i < TILE_DIM && y + i < axis_1 && x < axis_0; i += BLOCK_HEIGHT) {
output[(y + i) * axis_0 + x] = tile[(threadIdx.x)][threadIdx.y + i];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void naive_matrix_transpose(float *input, int axis_0, int axis_1, float *output)
{
__shared__ float tile[TILE_DIM][TILE_DIM + 1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
for (int i = 0; i < TILE_DIM && y + i < axis_1 && x < axis_0; i += BLOCK_HEIGHT) {
tile[threadIdx.y + i][threadIdx.x] = input[(y + i) * axis_0 + x];
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x;
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int i = 0; i < TILE_DIM && y + i < axis_1 && x < axis_0; i += BLOCK_HEIGHT) {
output[(y + i) * axis_0 + x] = tile[(threadIdx.x)][threadIdx.y + i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void naive_matrix_transpose(float *input, int axis_0, int axis_1, float *output)
{
__shared__ float tile[TILE_DIM][TILE_DIM + 1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
for (int i = 0; i < TILE_DIM && y + i < axis_1 && x < axis_0; i += BLOCK_HEIGHT) {
tile[threadIdx.y + i][threadIdx.x] = input[(y + i) * axis_0 + x];
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x;
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int i = 0; i < TILE_DIM && y + i < axis_1 && x < axis_0; i += BLOCK_HEIGHT) {
output[(y + i) * axis_0 + x] = tile[(threadIdx.x)][threadIdx.y + i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22naive_matrix_transposePfiiS_
.globl _Z22naive_matrix_transposePfiiS_
.p2align 8
.type _Z22naive_matrix_transposePfiiS_,@function
_Z22naive_matrix_transposePfiiS_:
s_load_b64 s[2:3], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
s_lshl_b32 s7, s14, 5
v_bfe_u32 v3, v0, 10, 10
s_lshl_b32 s6, s15, 5
s_mov_b32 s8, exec_lo
v_add_nc_u32_e32 v1, s7, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_5
s_load_b64 s[4:5], s[0:1], 0x0
v_add_nc_u32_e32 v4, s6, v3
v_lshlrev_b32_e32 v1, 2, v2
s_lshl_b32 s9, s2, 3
s_mov_b32 s10, -8
s_mov_b32 s11, 0
v_mul_lo_u32 v0, s2, v4
v_mad_u32_u24 v5, v3, 0x84, v1
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v0, v2, v0, s7
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s13, exec_lo, s12
s_or_b32 s11, s13, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_5
.LBB0_3:
v_add3_u32 v1, v4, s10, 8
s_or_b32 s12, s12, exec_lo
s_mov_b32 s13, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s10, s10, 8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_gt_u32 s10, 23
s_cselect_b32 s14, -1, 0
v_lshlrev_b64 v[6:7], 2, v[0:1]
s_and_not1_b32 s12, s12, exec_lo
s_and_b32 s14, s14, exec_lo
v_add_nc_u32_e32 v0, s9, v0
s_or_b32 s12, s12, s14
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v1, v[6:7], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v1
v_add_nc_u32_e32 v5, 0x420, v5
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v0, s6, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_10
s_load_b64 s[0:1], s[0:1], 0x10
v_add_nc_u32_e32 v4, s7, v3
v_lshlrev_b32_e32 v1, 2, v3
s_mov_b32 s4, -8
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, s2, v4
v_mad_u32_u24 v3, v2, 0x84, v1
s_lshl_b32 s2, s2, 3
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v0, v2, v0, s6
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s7, exec_lo, s6
s_or_b32 s5, s7, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_10
.LBB0_8:
v_add3_u32 v1, v4, s4, 8
s_or_b32 s6, s6, exec_lo
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_7
ds_load_b32 v5, v3
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s4, s4, 8
v_add_nc_u32_e32 v3, 32, v3
s_cmp_gt_u32 s4, 23
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_cselect_b32 s8, -1, 0
v_add_nc_u32_e32 v0, s2, v0
s_and_not1_b32 s6, s6, exec_lo
s_and_b32 s8, s8, exec_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_or_b32 s6, s6, s8
global_store_b32 v[1:2], v5, off
s_branch .LBB0_7
.LBB0_10:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22naive_matrix_transposePfiiS_
.amdhsa_group_segment_fixed_size 4224
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22naive_matrix_transposePfiiS_, .Lfunc_end0-_Z22naive_matrix_transposePfiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 4224
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22naive_matrix_transposePfiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22naive_matrix_transposePfiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void naive_matrix_transpose(float *input, int axis_0, int axis_1, float *output)
{
__shared__ float tile[TILE_DIM][TILE_DIM + 1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
for (int i = 0; i < TILE_DIM && y + i < axis_1 && x < axis_0; i += BLOCK_HEIGHT) {
tile[threadIdx.y + i][threadIdx.x] = input[(y + i) * axis_0 + x];
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x;
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int i = 0; i < TILE_DIM && y + i < axis_1 && x < axis_0; i += BLOCK_HEIGHT) {
output[(y + i) * axis_0 + x] = tile[(threadIdx.x)][threadIdx.y + i];
}
} | .text
.file "naive_matrix_transpose.hip"
.globl _Z37__device_stub__naive_matrix_transposePfiiS_ # -- Begin function _Z37__device_stub__naive_matrix_transposePfiiS_
.p2align 4, 0x90
.type _Z37__device_stub__naive_matrix_transposePfiiS_,@function
_Z37__device_stub__naive_matrix_transposePfiiS_: # @_Z37__device_stub__naive_matrix_transposePfiiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22naive_matrix_transposePfiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z37__device_stub__naive_matrix_transposePfiiS_, .Lfunc_end0-_Z37__device_stub__naive_matrix_transposePfiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22naive_matrix_transposePfiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22naive_matrix_transposePfiiS_,@object # @_Z22naive_matrix_transposePfiiS_
.section .rodata,"a",@progbits
.globl _Z22naive_matrix_transposePfiiS_
.p2align 3, 0x0
_Z22naive_matrix_transposePfiiS_:
.quad _Z37__device_stub__naive_matrix_transposePfiiS_
.size _Z22naive_matrix_transposePfiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22naive_matrix_transposePfiiS_"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__naive_matrix_transposePfiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22naive_matrix_transposePfiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z22naive_matrix_transposePfiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x280 ; /* 0x0000024000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R8, SR_TID.Y ; /* 0x0000000000087919 */
/* 0x000e280000002200 */
/*0050*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e680000002500 */
/*0060*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0070*/ LEA R5, R6, R8, 0x5 ; /* 0x0000000806057211 */
/* 0x001fc800078e28ff */
/*0080*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x16c], PT ; /* 0x00005b0005007a0c */
/* 0x000fe20003f06270 */
/*0090*/ IMAD R0, R4, 0x20, R9 ; /* 0x0000002004007824 */
/* 0x002fca00078e0209 */
/*00a0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*00b0*/ @P0 BRA 0x270 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R2, R5, c[0x0][0x168], R0 ; /* 0x00005a0005027a24 */
/* 0x000fd200078e0200 */
/*00e0*/ IMAD.WIDE R2, R2, R13, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e020d */
/*00f0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IMAD R11, R8, 0x21, R9 ; /* 0x00000021080b7824 */
/* 0x000fe200078e0209 */
/*0110*/ IADD3 R7, R5, 0x8, RZ ; /* 0x0000000805077810 */
/* 0x000fc80007ffe0ff */
/*0120*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x16c], PT ; /* 0x00005b0007007a0c */
/* 0x000fe20003f06270 */
/*0130*/ STS [R11.X4], R2 ; /* 0x000000020b007388 */
/* 0x0041d80000004800 */
/*0140*/ @P0 BRA 0x270 ; /* 0x0000012000000947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD R2, R7, c[0x0][0x168], R0 ; /* 0x00005a0007027a24 */
/* 0x001fc800078e0200 */
/*0160*/ IMAD.WIDE R2, R2, R13, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e020d */
/*0170*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IADD3 R7, R5, 0x10, RZ ; /* 0x0000001005077810 */
/* 0x000fc80007ffe0ff */
/*0190*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x16c], PT ; /* 0x00005b0007007a0c */
/* 0x000fe20003f06270 */
/*01a0*/ STS [R11.X4+0x420], R2 ; /* 0x000420020b007388 */
/* 0x0041d80000004800 */
/*01b0*/ @P0 BRA 0x270 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*01c0*/ IMAD R2, R7, c[0x0][0x168], R0 ; /* 0x00005a0007027a24 */
/* 0x001fc800078e0200 */
/*01d0*/ IMAD.WIDE R2, R2, R13, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e020d */
/*01e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*01f0*/ IADD3 R5, R5, 0x18, RZ ; /* 0x0000001805057810 */
/* 0x000fc80007ffe0ff */
/*0200*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x16c], PT ; /* 0x00005b0005007a0c */
/* 0x000fe20003f06270 */
/*0210*/ STS [R11.X4+0x840], R2 ; /* 0x000840020b007388 */
/* 0x0041d80000004800 */
/*0220*/ @P0 BRA 0x270 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0230*/ IMAD R2, R5, c[0x0][0x168], R0 ; /* 0x00005a0005027a24 */
/* 0x001fc800078e0200 */
/*0240*/ IMAD.WIDE R2, R2, R13, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e020d */
/*0250*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0260*/ STS [R11.X4+0xc60], R2 ; /* 0x000c60020b007388 */
/* 0x0041e40000004800 */
/*0270*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0290*/ IMAD R0, R4, 0x20, R8 ; /* 0x0000002004007824 */
/* 0x000fe200078e0208 */
/*02a0*/ LEA R5, R6, R9, 0x5 ; /* 0x0000000906057211 */
/* 0x000fc800078e28ff */
/*02b0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fc80003f06270 */
/*02c0*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x168], P0 ; /* 0x00005a0005007a0c */
/* 0x000fda0000706670 */
/*02d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02e0*/ IMAD R8, R9, 0x21, R8 ; /* 0x0000002109087824 */
/* 0x000fe200078e0208 */
/*02f0*/ IADD3 R4, R0.reuse, 0x8, RZ ; /* 0x0000000800047810 */
/* 0x040fe20007ffe0ff */
/*0300*/ IMAD R2, R0, c[0x0][0x168], R5 ; /* 0x00005a0000027a24 */
/* 0x001fe200078e0205 */
/*0310*/ MOV R9, 0x4 ; /* 0x0000000400097802 */
/* 0x000fe40000000f00 */
/*0320*/ LDS R7, [R8.X4] ; /* 0x0000000008077984 */
/* 0x000e220000004800 */
/*0330*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x16c], PT ; /* 0x00005b0004007a0c */
/* 0x000fe40003f06270 */
/*0340*/ IMAD.WIDE R2, R2, R9, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0209 */
/*0350*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0011ec000c101904 */
/*0360*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0370*/ LDS R7, [R8.X4+0x20] ; /* 0x0000200008077984 */
/* 0x001e220000004800 */
/*0380*/ IADD3 R6, R0, 0x10, RZ ; /* 0x0000001000067810 */
/* 0x000fe20007ffe0ff */
/*0390*/ IMAD R2, R4, c[0x0][0x168], R5 ; /* 0x00005a0004027a24 */
/* 0x000fc600078e0205 */
/*03a0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x16c], PT ; /* 0x00005b0006007a0c */
/* 0x000fe20003f06270 */
/*03b0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0209 */
/*03c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0011ee000c101904 */
/*03d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03e0*/ LDS R7, [R8.X4+0x40] ; /* 0x0000400008077984 */
/* 0x001e220000004800 */
/*03f0*/ IADD3 R0, R0, 0x18, RZ ; /* 0x0000001800007810 */
/* 0x000fe20007ffe0ff */
/*0400*/ IMAD R2, R6, c[0x0][0x168], R5 ; /* 0x00005a0006027a24 */
/* 0x000fc600078e0205 */
/*0410*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fe20003f06270 */
/*0420*/ IMAD.WIDE R2, R2, R9, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0209 */
/*0430*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0011ee000c101904 */
/*0440*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0450*/ LDS R7, [R8.X4+0x60] ; /* 0x0000600008077984 */
/* 0x001e220000004800 */
/*0460*/ IMAD R2, R0, c[0x0][0x168], R5 ; /* 0x00005a0000027a24 */
/* 0x000fc800078e0205 */
/*0470*/ IMAD.WIDE R2, R2, R9, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0209 */
/*0480*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101904 */
/*0490*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04a0*/ BRA 0x4a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22naive_matrix_transposePfiiS_
.globl _Z22naive_matrix_transposePfiiS_
.p2align 8
.type _Z22naive_matrix_transposePfiiS_,@function
_Z22naive_matrix_transposePfiiS_:
s_load_b64 s[2:3], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
s_lshl_b32 s7, s14, 5
v_bfe_u32 v3, v0, 10, 10
s_lshl_b32 s6, s15, 5
s_mov_b32 s8, exec_lo
v_add_nc_u32_e32 v1, s7, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_5
s_load_b64 s[4:5], s[0:1], 0x0
v_add_nc_u32_e32 v4, s6, v3
v_lshlrev_b32_e32 v1, 2, v2
s_lshl_b32 s9, s2, 3
s_mov_b32 s10, -8
s_mov_b32 s11, 0
v_mul_lo_u32 v0, s2, v4
v_mad_u32_u24 v5, v3, 0x84, v1
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v0, v2, v0, s7
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s13, exec_lo, s12
s_or_b32 s11, s13, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_5
.LBB0_3:
v_add3_u32 v1, v4, s10, 8
s_or_b32 s12, s12, exec_lo
s_mov_b32 s13, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s10, s10, 8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_gt_u32 s10, 23
s_cselect_b32 s14, -1, 0
v_lshlrev_b64 v[6:7], 2, v[0:1]
s_and_not1_b32 s12, s12, exec_lo
s_and_b32 s14, s14, exec_lo
v_add_nc_u32_e32 v0, s9, v0
s_or_b32 s12, s12, s14
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v1, v[6:7], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v1
v_add_nc_u32_e32 v5, 0x420, v5
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v0, s6, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_10
s_load_b64 s[0:1], s[0:1], 0x10
v_add_nc_u32_e32 v4, s7, v3
v_lshlrev_b32_e32 v1, 2, v3
s_mov_b32 s4, -8
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, s2, v4
v_mad_u32_u24 v3, v2, 0x84, v1
s_lshl_b32 s2, s2, 3
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v0, v2, v0, s6
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s7, exec_lo, s6
s_or_b32 s5, s7, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_10
.LBB0_8:
v_add3_u32 v1, v4, s4, 8
s_or_b32 s6, s6, exec_lo
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_7
ds_load_b32 v5, v3
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s4, s4, 8
v_add_nc_u32_e32 v3, 32, v3
s_cmp_gt_u32 s4, 23
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_cselect_b32 s8, -1, 0
v_add_nc_u32_e32 v0, s2, v0
s_and_not1_b32 s6, s6, exec_lo
s_and_b32 s8, s8, exec_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_or_b32 s6, s6, s8
global_store_b32 v[1:2], v5, off
s_branch .LBB0_7
.LBB0_10:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22naive_matrix_transposePfiiS_
.amdhsa_group_segment_fixed_size 4224
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22naive_matrix_transposePfiiS_, .Lfunc_end0-_Z22naive_matrix_transposePfiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 4224
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22naive_matrix_transposePfiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22naive_matrix_transposePfiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010b6a2_00000000-6_naive_matrix_transpose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z22naive_matrix_transposePfiiS_PfiiS_
.type _Z46__device_stub__Z22naive_matrix_transposePfiiS_PfiiS_, @function
_Z46__device_stub__Z22naive_matrix_transposePfiiS_PfiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22naive_matrix_transposePfiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z22naive_matrix_transposePfiiS_PfiiS_, .-_Z46__device_stub__Z22naive_matrix_transposePfiiS_PfiiS_
.globl _Z22naive_matrix_transposePfiiS_
.type _Z22naive_matrix_transposePfiiS_, @function
_Z22naive_matrix_transposePfiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z22naive_matrix_transposePfiiS_PfiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22naive_matrix_transposePfiiS_, .-_Z22naive_matrix_transposePfiiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22naive_matrix_transposePfiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22naive_matrix_transposePfiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "naive_matrix_transpose.hip"
.globl _Z37__device_stub__naive_matrix_transposePfiiS_ # -- Begin function _Z37__device_stub__naive_matrix_transposePfiiS_
.p2align 4, 0x90
.type _Z37__device_stub__naive_matrix_transposePfiiS_,@function
_Z37__device_stub__naive_matrix_transposePfiiS_: # @_Z37__device_stub__naive_matrix_transposePfiiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22naive_matrix_transposePfiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z37__device_stub__naive_matrix_transposePfiiS_, .Lfunc_end0-_Z37__device_stub__naive_matrix_transposePfiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22naive_matrix_transposePfiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22naive_matrix_transposePfiiS_,@object # @_Z22naive_matrix_transposePfiiS_
.section .rodata,"a",@progbits
.globl _Z22naive_matrix_transposePfiiS_
.p2align 3, 0x0
_Z22naive_matrix_transposePfiiS_:
.quad _Z37__device_stub__naive_matrix_transposePfiiS_
.size _Z22naive_matrix_transposePfiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22naive_matrix_transposePfiiS_"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__naive_matrix_transposePfiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22naive_matrix_transposePfiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
{
__global__ void Dstanh_32(const int lengthX, const float sf, const float *gradc, const float *fc, float *gradn)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthX)
{
gradn[i] += sf*gradc[i]*(1.0-(fc[i]/sf)*(fc[i]/sf));
}
}
} | code for sm_80
Function : Dstanh_32
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R6, R0, R5, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ MUFU.RCP R3, c[0x0][0x164] ; /* 0x0000590000037b08 */
/* 0x000e220000001000 */
/*00d0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff087624 */
/* 0x000fe200078e00ff */
/*00e0*/ BSSY B0, 0x1b0 ; /* 0x000000c000007945 */
/* 0x000fe60003800000 */
/*00f0*/ FFMA R8, R3, -R8, 1 ; /* 0x3f80000003087423 */
/* 0x001fc80000000808 */
/*0100*/ FFMA R9, R3, R8, R3 ; /* 0x0000000803097223 */
/* 0x000fe20000000003 */
/*0110*/ FCHK P0, R6, c[0x0][0x164] ; /* 0x0000590006007b02 */
/* 0x004e260000000000 */
/*0120*/ FFMA R8, R6, R9, RZ ; /* 0x0000000906087223 */
/* 0x000fe400000000ff */
/*0130*/ FMUL R2, R4, c[0x0][0x164] ; /* 0x0000590004027a20 */
/* 0x008fe40000400000 */
/*0140*/ FFMA R10, R8, -c[0x0][0x164], R6 ; /* 0x80005900080a7a23 */
/* 0x000fc80000000006 */
/*0150*/ F2F.F64.F32 R2, R2 ; /* 0x0000000200027310 */
/* 0x000e620000201800 */
/*0160*/ FFMA R8, R9, R10, R8 ; /* 0x0000000a09087223 */
/* 0x000fe20000000008 */
/*0170*/ @!P0 BRA 0x1a0 ; /* 0x0000002000008947 */
/* 0x001fec0003800000 */
/*0180*/ MOV R4, 0x1a0 ; /* 0x000001a000047802 */
/* 0x000fe40000000f00 */
/*0190*/ CALL.REL.NOINC 0x260 ; /* 0x000000c000007944 */
/* 0x002fea0003c00000 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*01c0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fca00078e0207 */
/*01d0*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ FMUL R0, R8, R8 ; /* 0x0000000808007220 */
/* 0x000fc80000400000 */
/*01f0*/ F2F.F64.F32 R4, R0 ; /* 0x0000000000047310 */
/* 0x000e240000201800 */
/*0200*/ DADD R4, -R4, 1 ; /* 0x3ff0000004047429 */
/* 0x001e0c0000000100 */
/*0210*/ F2F.F64.F32 R8, R9 ; /* 0x0000000900087310 */
/* 0x004e240000201800 */
/*0220*/ DFMA R2, R2, R4, R8 ; /* 0x000000040202722b */
/* 0x003e140000000008 */
/*0230*/ F2F.F32.F64 R3, R2 ; /* 0x0000000200037310 */
/* 0x001e240000301000 */
/*0240*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x001fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff0d7624 */
/* 0x000fe200078e00ff */
/*0270*/ SHF.R.U32.HI R5, RZ, 0x17, R6.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011606 */
/*0280*/ BSSY B1, 0x8d0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0290*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0006 */
/*02a0*/ SHF.R.U32.HI R7, RZ, 0x17, R13 ; /* 0x00000017ff077819 */
/* 0x000fe2000001160d */
/*02b0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff097624 */
/* 0x000fe200078e00ff */
/*02c0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fc400078ec0ff */
/*02d0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fe400078ec0ff */
/*02e0*/ IADD3 R11, R5, -0x1, RZ ; /* 0xffffffff050b7810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ IADD3 R12, R7, -0x1, RZ ; /* 0xffffffff070c7810 */
/* 0x000fc80007ffe0ff */
/*0300*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0310*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*0320*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*0330*/ @!P0 BRA 0x4b0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0340*/ FSETP.GTU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f3c200 */
/*0350*/ FSETP.GTU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fc80003f1c200 */
/*0360*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0370*/ @P0 BRA 0x8b0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0380*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*0390*/ @!P0 BRA 0x890 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*03a0*/ FSETP.NEU.FTZ.AND P2, PT, |R6|.reuse, +INF , PT ; /* 0x7f8000000600780b */
/* 0x040fe40003f5d200 */
/*03b0*/ FSETP.NEU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f3d200 */
/*03c0*/ FSETP.NEU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fd60003f1d200 */
/*03d0*/ @!P1 BRA !P2, 0x890 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*03e0*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*03f0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0400*/ @P1 BRA 0x870 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0410*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*0420*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0430*/ @P0 BRA 0x840 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0440*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0450*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0460*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0470*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*0480*/ @!P0 FFMA R8, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006088823 */
/* 0x000fe400000000ff */
/*0490*/ @!P1 FFMA R9, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d099823 */
/* 0x000fe200000000ff */
/*04a0*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*04b0*/ LEA R6, R7, 0xc0800000, 0x17 ; /* 0xc080000007067811 */
/* 0x000fe200078eb8ff */
/*04c0*/ BSSY B2, 0x830 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*04d0*/ IMAD.IADD R9, R9, 0x1, -R6 ; /* 0x0000000109097824 */
/* 0x000fe200078e0a06 */
/*04e0*/ IADD3 R6, R5, -0x7f, RZ ; /* 0xffffff8105067810 */
/* 0x000fc60007ffe0ff */
/*04f0*/ MUFU.RCP R11, R9 ; /* 0x00000009000b7308 */
/* 0x000e220000001000 */
/*0500*/ FADD.FTZ R13, -R9, -RZ ; /* 0x800000ff090d7221 */
/* 0x000fe20000010100 */
/*0510*/ IADD3 R7, R6.reuse, 0x7f, -R7 ; /* 0x0000007f06077810 */
/* 0x040fe20007ffe807 */
/*0520*/ IMAD R8, R6, -0x800000, R8 ; /* 0xff80000006087824 */
/* 0x000fc800078e0208 */
/*0530*/ IMAD.IADD R7, R7, 0x1, R10 ; /* 0x0000000107077824 */
/* 0x000fe400078e020a */
/*0540*/ FFMA R12, R11, R13, 1 ; /* 0x3f8000000b0c7423 */
/* 0x001fc8000000000d */
/*0550*/ FFMA R11, R11, R12, R11 ; /* 0x0000000c0b0b7223 */
/* 0x000fc8000000000b */
/*0560*/ FFMA R5, R8, R11, RZ ; /* 0x0000000b08057223 */
/* 0x000fc800000000ff */
/*0570*/ FFMA R12, R13, R5, R8 ; /* 0x000000050d0c7223 */
/* 0x000fc80000000008 */
/*0580*/ FFMA R12, R11, R12, R5 ; /* 0x0000000c0b0c7223 */
/* 0x000fc80000000005 */
/*0590*/ FFMA R13, R13, R12, R8 ; /* 0x0000000c0d0d7223 */
/* 0x000fc80000000008 */
/*05a0*/ FFMA R5, R11, R13, R12 ; /* 0x0000000d0b057223 */
/* 0x000fca000000000c */
/*05b0*/ SHF.R.U32.HI R6, RZ, 0x17, R5 ; /* 0x00000017ff067819 */
/* 0x000fc80000011605 */
/*05c0*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fca00078ec0ff */
/*05d0*/ IMAD.IADD R10, R6, 0x1, R7 ; /* 0x00000001060a7824 */
/* 0x000fca00078e0207 */
/*05e0*/ IADD3 R6, R10, -0x1, RZ ; /* 0xffffffff0a067810 */
/* 0x000fc80007ffe0ff */
/*05f0*/ ISETP.GE.U32.AND P0, PT, R6, 0xfe, PT ; /* 0x000000fe0600780c */
/* 0x000fda0003f06070 */
/*0600*/ @!P0 BRA 0x810 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0610*/ ISETP.GT.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f04270 */
/*0620*/ @P0 BRA 0x7e0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0630*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f06270 */
/*0640*/ @P0 BRA 0x820 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0650*/ ISETP.GE.AND P0, PT, R10, -0x18, PT ; /* 0xffffffe80a00780c */
/* 0x000fe40003f06270 */
/*0660*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*0670*/ @!P0 BRA 0x820 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0680*/ FFMA.RZ R6, R11.reuse, R13.reuse, R12.reuse ; /* 0x0000000d0b067223 */
/* 0x1c0fe2000000c00c */
/*0690*/ IADD3 R9, R10.reuse, 0x20, RZ ; /* 0x000000200a097810 */
/* 0x040fe20007ffe0ff */
/*06a0*/ FFMA.RM R7, R11.reuse, R13.reuse, R12.reuse ; /* 0x0000000d0b077223 */
/* 0x1c0fe2000000400c */
/*06b0*/ ISETP.NE.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f45270 */
/*06c0*/ LOP3.LUT R8, R6, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff06087812 */
/* 0x000fe200078ec0ff */
/*06d0*/ FFMA.RP R6, R11, R13, R12 ; /* 0x0000000d0b067223 */
/* 0x000fe2000000800c */
/*06e0*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25270 */
/*06f0*/ IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0a0a */
/*0700*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe400078efcff */
/*0710*/ FSETP.NEU.FTZ.AND P0, PT, R6, R7, PT ; /* 0x000000070600720b */
/* 0x000fc40003f1d000 */
/*0720*/ SHF.L.U32 R9, R8, R9, RZ ; /* 0x0000000908097219 */
/* 0x000fe400000006ff */
/*0730*/ SEL R7, R10, RZ, P2 ; /* 0x000000ff0a077207 */
/* 0x000fe40001000000 */
/*0740*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*0750*/ SHF.R.U32.HI R7, RZ, R7, R8 ; /* 0x00000007ff077219 */
/* 0x000fe40000011608 */
/*0760*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0770*/ SHF.R.U32.HI R9, RZ, 0x1, R7 ; /* 0x00000001ff097819 */
/* 0x000fc40000011607 */
/*0780*/ SEL R6, RZ, 0x1, !P0 ; /* 0x00000001ff067807 */
/* 0x000fc80004000000 */
/*0790*/ LOP3.LUT R6, R6, 0x1, R9, 0xf8, !PT ; /* 0x0000000106067812 */
/* 0x000fc800078ef809 */
/*07a0*/ LOP3.LUT R6, R6, R7, RZ, 0xc0, !PT ; /* 0x0000000706067212 */
/* 0x000fca00078ec0ff */
/*07b0*/ IMAD.IADD R6, R9, 0x1, R6 ; /* 0x0000000109067824 */
/* 0x000fca00078e0206 */
/*07c0*/ LOP3.LUT R5, R6, R5, RZ, 0xfc, !PT ; /* 0x0000000506057212 */
/* 0x000fe200078efcff */
/*07d0*/ BRA 0x820 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*07e0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*07f0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0800*/ BRA 0x820 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0810*/ IMAD R5, R7, 0x800000, R5 ; /* 0x0080000007057824 */
/* 0x000fe400078e0205 */
/*0820*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0830*/ BRA 0x8c0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0840*/ LOP3.LUT R5, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009057812 */
/* 0x000fc800078e4808 */
/*0850*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0860*/ BRA 0x8c0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0870*/ LOP3.LUT R5, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009057812 */
/* 0x000fe200078e4808 */
/*0880*/ BRA 0x8c0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0890*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*08a0*/ BRA 0x8c0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*08b0*/ FADD.FTZ R5, R6, c[0x0][0x164] ; /* 0x0000590006057621 */
/* 0x000fe40000010000 */
/*08c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08d0*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0005 */
/*08e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*08f0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff70004007950 */
/* 0x000fea0003c3ffff */
/*0900*/ BRA 0x900; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
{
__global__ void Dstanh_32(const int lengthX, const float sf, const float *gradc, const float *fc, float *gradn)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthX)
{
gradn[i] += sf*gradc[i]*(1.0-(fc[i]/sf)*(fc[i]/sf));
}
}
} | .file "tmpxft_000bbb20_00000000-6_Dstanh_32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z9Dstanh_32ifPKfS0_PfifPKfS0_Pf
.type _Z36__device_stub__Z9Dstanh_32ifPKfS0_PfifPKfS0_Pf, @function
_Z36__device_stub__Z9Dstanh_32ifPKfS0_PfifPKfS0_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq Dstanh_32(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z9Dstanh_32ifPKfS0_PfifPKfS0_Pf, .-_Z36__device_stub__Z9Dstanh_32ifPKfS0_PfifPKfS0_Pf
.globl Dstanh_32
.type Dstanh_32, @function
Dstanh_32:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z9Dstanh_32ifPKfS0_PfifPKfS0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size Dstanh_32, .-Dstanh_32
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Dstanh_32"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq Dstanh_32(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
{
__global__ void Dstanh_32(const int lengthX, const float sf, const float *gradc, const float *fc, float *gradn)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthX)
{
gradn[i] += sf*gradc[i]*(1.0-(fc[i]/sf)*(fc[i]/sf));
}
}
} | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void Dstanh_32(const int lengthX, const float sf, const float *gradc, const float *fc, float *gradn)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthX)
{
gradn[i] += sf*gradc[i]*(1.0-(fc[i]/sf)*(fc[i]/sf));
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void Dstanh_32(const int lengthX, const float sf, const float *gradc, const float *fc, float *gradn)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthX)
{
gradn[i] += sf*gradc[i]*(1.0-(fc[i]/sf)*(fc[i]/sf));
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected Dstanh_32
.globl Dstanh_32
.p2align 8
.type Dstanh_32,@function
Dstanh_32:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b32 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v6, v[0:1], off
s_waitcnt vmcnt(2)
v_div_scale_f32 v2, null, s0, s0, v4
v_div_scale_f32 v8, vcc_lo, v4, s0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v2, v3, 1.0
v_fmac_f32_e32 v3, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v8, v3
v_fma_f32 v9, -v2, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v9, v3
v_fma_f32 v2, -v2, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f32 v2, v2, v3, v7
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[6:7], v6
v_div_fixup_f32 v2, v2, s0, v4
v_mul_f32_e32 v4, s0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v2, v2, v2
v_cvt_f64_f32_e32 v[4:5], v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[2:3], v2
v_add_f64 v[2:3], -v[2:3], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[2:3], v[4:5], v[6:7]
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel Dstanh_32
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size Dstanh_32, .Lfunc_end0-Dstanh_32
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: Dstanh_32
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: Dstanh_32.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void Dstanh_32(const int lengthX, const float sf, const float *gradc, const float *fc, float *gradn)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<lengthX)
{
gradn[i] += sf*gradc[i]*(1.0-(fc[i]/sf)*(fc[i]/sf));
}
}
} | .text
.file "Dstanh_32.hip"
.globl __device_stub__Dstanh_32 # -- Begin function __device_stub__Dstanh_32
.p2align 4, 0x90
.type __device_stub__Dstanh_32,@function
__device_stub__Dstanh_32: # @__device_stub__Dstanh_32
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movss %xmm0, (%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $Dstanh_32, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__Dstanh_32, .Lfunc_end0-__device_stub__Dstanh_32
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $Dstanh_32, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type Dstanh_32,@object # @Dstanh_32
.section .rodata,"a",@progbits
.globl Dstanh_32
.p2align 3, 0x0
Dstanh_32:
.quad __device_stub__Dstanh_32
.size Dstanh_32, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "Dstanh_32"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__Dstanh_32
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym Dstanh_32
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : Dstanh_32
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R6, R0, R5, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ MUFU.RCP R3, c[0x0][0x164] ; /* 0x0000590000037b08 */
/* 0x000e220000001000 */
/*00d0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff087624 */
/* 0x000fe200078e00ff */
/*00e0*/ BSSY B0, 0x1b0 ; /* 0x000000c000007945 */
/* 0x000fe60003800000 */
/*00f0*/ FFMA R8, R3, -R8, 1 ; /* 0x3f80000003087423 */
/* 0x001fc80000000808 */
/*0100*/ FFMA R9, R3, R8, R3 ; /* 0x0000000803097223 */
/* 0x000fe20000000003 */
/*0110*/ FCHK P0, R6, c[0x0][0x164] ; /* 0x0000590006007b02 */
/* 0x004e260000000000 */
/*0120*/ FFMA R8, R6, R9, RZ ; /* 0x0000000906087223 */
/* 0x000fe400000000ff */
/*0130*/ FMUL R2, R4, c[0x0][0x164] ; /* 0x0000590004027a20 */
/* 0x008fe40000400000 */
/*0140*/ FFMA R10, R8, -c[0x0][0x164], R6 ; /* 0x80005900080a7a23 */
/* 0x000fc80000000006 */
/*0150*/ F2F.F64.F32 R2, R2 ; /* 0x0000000200027310 */
/* 0x000e620000201800 */
/*0160*/ FFMA R8, R9, R10, R8 ; /* 0x0000000a09087223 */
/* 0x000fe20000000008 */
/*0170*/ @!P0 BRA 0x1a0 ; /* 0x0000002000008947 */
/* 0x001fec0003800000 */
/*0180*/ MOV R4, 0x1a0 ; /* 0x000001a000047802 */
/* 0x000fe40000000f00 */
/*0190*/ CALL.REL.NOINC 0x260 ; /* 0x000000c000007944 */
/* 0x002fea0003c00000 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*01c0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fca00078e0207 */
/*01d0*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ FMUL R0, R8, R8 ; /* 0x0000000808007220 */
/* 0x000fc80000400000 */
/*01f0*/ F2F.F64.F32 R4, R0 ; /* 0x0000000000047310 */
/* 0x000e240000201800 */
/*0200*/ DADD R4, -R4, 1 ; /* 0x3ff0000004047429 */
/* 0x001e0c0000000100 */
/*0210*/ F2F.F64.F32 R8, R9 ; /* 0x0000000900087310 */
/* 0x004e240000201800 */
/*0220*/ DFMA R2, R2, R4, R8 ; /* 0x000000040202722b */
/* 0x003e140000000008 */
/*0230*/ F2F.F32.F64 R3, R2 ; /* 0x0000000200037310 */
/* 0x001e240000301000 */
/*0240*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x001fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff0d7624 */
/* 0x000fe200078e00ff */
/*0270*/ SHF.R.U32.HI R5, RZ, 0x17, R6.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011606 */
/*0280*/ BSSY B1, 0x8d0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0290*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0006 */
/*02a0*/ SHF.R.U32.HI R7, RZ, 0x17, R13 ; /* 0x00000017ff077819 */
/* 0x000fe2000001160d */
/*02b0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff097624 */
/* 0x000fe200078e00ff */
/*02c0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fc400078ec0ff */
/*02d0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fe400078ec0ff */
/*02e0*/ IADD3 R11, R5, -0x1, RZ ; /* 0xffffffff050b7810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ IADD3 R12, R7, -0x1, RZ ; /* 0xffffffff070c7810 */
/* 0x000fc80007ffe0ff */
/*0300*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0310*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*0320*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*0330*/ @!P0 BRA 0x4b0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0340*/ FSETP.GTU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f3c200 */
/*0350*/ FSETP.GTU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fc80003f1c200 */
/*0360*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0370*/ @P0 BRA 0x8b0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0380*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*0390*/ @!P0 BRA 0x890 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*03a0*/ FSETP.NEU.FTZ.AND P2, PT, |R6|.reuse, +INF , PT ; /* 0x7f8000000600780b */
/* 0x040fe40003f5d200 */
/*03b0*/ FSETP.NEU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f3d200 */
/*03c0*/ FSETP.NEU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fd60003f1d200 */
/*03d0*/ @!P1 BRA !P2, 0x890 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*03e0*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*03f0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0400*/ @P1 BRA 0x870 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0410*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*0420*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0430*/ @P0 BRA 0x840 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0440*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0450*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0460*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0470*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*0480*/ @!P0 FFMA R8, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006088823 */
/* 0x000fe400000000ff */
/*0490*/ @!P1 FFMA R9, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d099823 */
/* 0x000fe200000000ff */
/*04a0*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*04b0*/ LEA R6, R7, 0xc0800000, 0x17 ; /* 0xc080000007067811 */
/* 0x000fe200078eb8ff */
/*04c0*/ BSSY B2, 0x830 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*04d0*/ IMAD.IADD R9, R9, 0x1, -R6 ; /* 0x0000000109097824 */
/* 0x000fe200078e0a06 */
/*04e0*/ IADD3 R6, R5, -0x7f, RZ ; /* 0xffffff8105067810 */
/* 0x000fc60007ffe0ff */
/*04f0*/ MUFU.RCP R11, R9 ; /* 0x00000009000b7308 */
/* 0x000e220000001000 */
/*0500*/ FADD.FTZ R13, -R9, -RZ ; /* 0x800000ff090d7221 */
/* 0x000fe20000010100 */
/*0510*/ IADD3 R7, R6.reuse, 0x7f, -R7 ; /* 0x0000007f06077810 */
/* 0x040fe20007ffe807 */
/*0520*/ IMAD R8, R6, -0x800000, R8 ; /* 0xff80000006087824 */
/* 0x000fc800078e0208 */
/*0530*/ IMAD.IADD R7, R7, 0x1, R10 ; /* 0x0000000107077824 */
/* 0x000fe400078e020a */
/*0540*/ FFMA R12, R11, R13, 1 ; /* 0x3f8000000b0c7423 */
/* 0x001fc8000000000d */
/*0550*/ FFMA R11, R11, R12, R11 ; /* 0x0000000c0b0b7223 */
/* 0x000fc8000000000b */
/*0560*/ FFMA R5, R8, R11, RZ ; /* 0x0000000b08057223 */
/* 0x000fc800000000ff */
/*0570*/ FFMA R12, R13, R5, R8 ; /* 0x000000050d0c7223 */
/* 0x000fc80000000008 */
/*0580*/ FFMA R12, R11, R12, R5 ; /* 0x0000000c0b0c7223 */
/* 0x000fc80000000005 */
/*0590*/ FFMA R13, R13, R12, R8 ; /* 0x0000000c0d0d7223 */
/* 0x000fc80000000008 */
/*05a0*/ FFMA R5, R11, R13, R12 ; /* 0x0000000d0b057223 */
/* 0x000fca000000000c */
/*05b0*/ SHF.R.U32.HI R6, RZ, 0x17, R5 ; /* 0x00000017ff067819 */
/* 0x000fc80000011605 */
/*05c0*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fca00078ec0ff */
/*05d0*/ IMAD.IADD R10, R6, 0x1, R7 ; /* 0x00000001060a7824 */
/* 0x000fca00078e0207 */
/*05e0*/ IADD3 R6, R10, -0x1, RZ ; /* 0xffffffff0a067810 */
/* 0x000fc80007ffe0ff */
/*05f0*/ ISETP.GE.U32.AND P0, PT, R6, 0xfe, PT ; /* 0x000000fe0600780c */
/* 0x000fda0003f06070 */
/*0600*/ @!P0 BRA 0x810 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0610*/ ISETP.GT.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f04270 */
/*0620*/ @P0 BRA 0x7e0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0630*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f06270 */
/*0640*/ @P0 BRA 0x820 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0650*/ ISETP.GE.AND P0, PT, R10, -0x18, PT ; /* 0xffffffe80a00780c */
/* 0x000fe40003f06270 */
/*0660*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*0670*/ @!P0 BRA 0x820 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0680*/ FFMA.RZ R6, R11.reuse, R13.reuse, R12.reuse ; /* 0x0000000d0b067223 */
/* 0x1c0fe2000000c00c */
/*0690*/ IADD3 R9, R10.reuse, 0x20, RZ ; /* 0x000000200a097810 */
/* 0x040fe20007ffe0ff */
/*06a0*/ FFMA.RM R7, R11.reuse, R13.reuse, R12.reuse ; /* 0x0000000d0b077223 */
/* 0x1c0fe2000000400c */
/*06b0*/ ISETP.NE.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f45270 */
/*06c0*/ LOP3.LUT R8, R6, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff06087812 */
/* 0x000fe200078ec0ff */
/*06d0*/ FFMA.RP R6, R11, R13, R12 ; /* 0x0000000d0b067223 */
/* 0x000fe2000000800c */
/*06e0*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25270 */
/*06f0*/ IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0a0a */
/*0700*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe400078efcff */
/*0710*/ FSETP.NEU.FTZ.AND P0, PT, R6, R7, PT ; /* 0x000000070600720b */
/* 0x000fc40003f1d000 */
/*0720*/ SHF.L.U32 R9, R8, R9, RZ ; /* 0x0000000908097219 */
/* 0x000fe400000006ff */
/*0730*/ SEL R7, R10, RZ, P2 ; /* 0x000000ff0a077207 */
/* 0x000fe40001000000 */
/*0740*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*0750*/ SHF.R.U32.HI R7, RZ, R7, R8 ; /* 0x00000007ff077219 */
/* 0x000fe40000011608 */
/*0760*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0770*/ SHF.R.U32.HI R9, RZ, 0x1, R7 ; /* 0x00000001ff097819 */
/* 0x000fc40000011607 */
/*0780*/ SEL R6, RZ, 0x1, !P0 ; /* 0x00000001ff067807 */
/* 0x000fc80004000000 */
/*0790*/ LOP3.LUT R6, R6, 0x1, R9, 0xf8, !PT ; /* 0x0000000106067812 */
/* 0x000fc800078ef809 */
/*07a0*/ LOP3.LUT R6, R6, R7, RZ, 0xc0, !PT ; /* 0x0000000706067212 */
/* 0x000fca00078ec0ff */
/*07b0*/ IMAD.IADD R6, R9, 0x1, R6 ; /* 0x0000000109067824 */
/* 0x000fca00078e0206 */
/*07c0*/ LOP3.LUT R5, R6, R5, RZ, 0xfc, !PT ; /* 0x0000000506057212 */
/* 0x000fe200078efcff */
/*07d0*/ BRA 0x820 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*07e0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*07f0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0800*/ BRA 0x820 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0810*/ IMAD R5, R7, 0x800000, R5 ; /* 0x0080000007057824 */
/* 0x000fe400078e0205 */
/*0820*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0830*/ BRA 0x8c0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0840*/ LOP3.LUT R5, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009057812 */
/* 0x000fc800078e4808 */
/*0850*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0860*/ BRA 0x8c0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0870*/ LOP3.LUT R5, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009057812 */
/* 0x000fe200078e4808 */
/*0880*/ BRA 0x8c0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0890*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*08a0*/ BRA 0x8c0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*08b0*/ FADD.FTZ R5, R6, c[0x0][0x164] ; /* 0x0000590006057621 */
/* 0x000fe40000010000 */
/*08c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08d0*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0005 */
/*08e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*08f0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff70004007950 */
/* 0x000fea0003c3ffff */
/*0900*/ BRA 0x900; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected Dstanh_32
.globl Dstanh_32
.p2align 8
.type Dstanh_32,@function
Dstanh_32:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b32 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v6, v[0:1], off
s_waitcnt vmcnt(2)
v_div_scale_f32 v2, null, s0, s0, v4
v_div_scale_f32 v8, vcc_lo, v4, s0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v2, v3, 1.0
v_fmac_f32_e32 v3, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v8, v3
v_fma_f32 v9, -v2, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v9, v3
v_fma_f32 v2, -v2, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f32 v2, v2, v3, v7
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[6:7], v6
v_div_fixup_f32 v2, v2, s0, v4
v_mul_f32_e32 v4, s0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v2, v2, v2
v_cvt_f64_f32_e32 v[4:5], v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[2:3], v2
v_add_f64 v[2:3], -v[2:3], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[2:3], v[4:5], v[6:7]
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel Dstanh_32
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size Dstanh_32, .Lfunc_end0-Dstanh_32
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: Dstanh_32
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: Dstanh_32.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bbb20_00000000-6_Dstanh_32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z9Dstanh_32ifPKfS0_PfifPKfS0_Pf
.type _Z36__device_stub__Z9Dstanh_32ifPKfS0_PfifPKfS0_Pf, @function
_Z36__device_stub__Z9Dstanh_32ifPKfS0_PfifPKfS0_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq Dstanh_32(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z9Dstanh_32ifPKfS0_PfifPKfS0_Pf, .-_Z36__device_stub__Z9Dstanh_32ifPKfS0_PfifPKfS0_Pf
.globl Dstanh_32
.type Dstanh_32, @function
Dstanh_32:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z9Dstanh_32ifPKfS0_PfifPKfS0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size Dstanh_32, .-Dstanh_32
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Dstanh_32"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq Dstanh_32(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Dstanh_32.hip"
.globl __device_stub__Dstanh_32 # -- Begin function __device_stub__Dstanh_32
.p2align 4, 0x90
.type __device_stub__Dstanh_32,@function
__device_stub__Dstanh_32: # @__device_stub__Dstanh_32
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movss %xmm0, (%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $Dstanh_32, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__Dstanh_32, .Lfunc_end0-__device_stub__Dstanh_32
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $Dstanh_32, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type Dstanh_32,@object # @Dstanh_32
.section .rodata,"a",@progbits
.globl Dstanh_32
.p2align 3, 0x0
Dstanh_32:
.quad __device_stub__Dstanh_32
.size Dstanh_32, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "Dstanh_32"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__Dstanh_32
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym Dstanh_32
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void add( int* a,int* b, int*c )
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
c[tid] = a[tid] + b[tid];
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void add( int* a,int* b, int*c )
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
c[tid] = a[tid] + b[tid];
} | .file "tmpxft_001afb11_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void add( int* a,int* b, int*c )
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
c[tid] = a[tid] + b[tid];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add( int* a,int* b, int*c )
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
c[tid] = a[tid] + b[tid];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add( int* a,int* b, int*c )
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
c[tid] = a[tid] + b[tid];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add( int* a,int* b, int*c )
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
c[tid] = a[tid] + b[tid];
} | .text
.file "add.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001afb11_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
extern int cuda_add(int argc, char*argv[]);
int cuda_matrix_mul(int argc, char* argv[]);
int cuda_matrix_mul_s(int argc, char* argv[]);
int page_locked_mem(int argc, char *argv[]);
int cuda_gl(int argc, char *argv[]);
int cuda_texture(int argc, char* argv[]);
int main(int argc, char* argv[])
{
cuda_texture(argc, argv);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
extern int cuda_add(int argc, char*argv[]);
int cuda_matrix_mul(int argc, char* argv[]);
int cuda_matrix_mul_s(int argc, char* argv[]);
int page_locked_mem(int argc, char *argv[]);
int cuda_gl(int argc, char *argv[]);
int cuda_texture(int argc, char* argv[]);
int main(int argc, char* argv[])
{
cuda_texture(argc, argv);
} | .file "tmpxft_00127e4f_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z12cuda_textureiPPc@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
extern int cuda_add(int argc, char*argv[]);
int cuda_matrix_mul(int argc, char* argv[]);
int cuda_matrix_mul_s(int argc, char* argv[]);
int page_locked_mem(int argc, char *argv[]);
int cuda_gl(int argc, char *argv[]);
int cuda_texture(int argc, char* argv[]);
int main(int argc, char* argv[])
{
cuda_texture(argc, argv);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
extern int cuda_add(int argc, char*argv[]);
int cuda_matrix_mul(int argc, char* argv[]);
int cuda_matrix_mul_s(int argc, char* argv[]);
int page_locked_mem(int argc, char *argv[]);
int cuda_gl(int argc, char *argv[]);
int cuda_texture(int argc, char* argv[]);
int main(int argc, char* argv[])
{
cuda_texture(argc, argv);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
extern int cuda_add(int argc, char*argv[]);
int cuda_matrix_mul(int argc, char* argv[]);
int cuda_matrix_mul_s(int argc, char* argv[]);
int page_locked_mem(int argc, char *argv[]);
int cuda_gl(int argc, char *argv[]);
int cuda_texture(int argc, char* argv[]);
int main(int argc, char* argv[])
{
cuda_texture(argc, argv);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
extern int cuda_add(int argc, char*argv[]);
int cuda_matrix_mul(int argc, char* argv[]);
int cuda_matrix_mul_s(int argc, char* argv[]);
int page_locked_mem(int argc, char *argv[]);
int cuda_gl(int argc, char *argv[]);
int cuda_texture(int argc, char* argv[]);
int main(int argc, char* argv[])
{
cuda_texture(argc, argv);
} | .text
.file "main.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z12cuda_textureiPPc
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00127e4f_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z12cuda_textureiPPc@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z12cuda_textureiPPc
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Copyright (c) 2020 Saurabh Yadav
//
// This software is released under the MIT License.
// https://opensource.org/licenses/MIT
#include <stdio.h>
#include <unistd.h>
#include <stdlib.h>
#include <math.h>
#include <cuda_runtime.h>
#define TOTAL_ROWS 1000U
#define TOTAL_COLS 2000U
__global__
void init_matrix(float *matrix, int width, int height, float val) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = idx; i < width * height; i += gridDim.x * blockDim.x) {
matrix[i]=val;
}
}
__global__
void add_matrices(float * mat_A_arr, float * mat_B_arr, float * mat_C_arr,
int num_cols, int num_rows) {
int row = threadIdx.y + blockIdx.y * blockDim.y;
int col = threadIdx.x + blockIdx.x * blockDim.x;
if(row < num_rows && col < num_cols) {
mat_C_arr[row*num_cols + col] = mat_A_arr[row*num_cols + col] +
mat_B_arr[row*num_cols + col];
}
}
int main() {
cudaError_t err = cudaSuccess;
float *mat_A, *mat_B, *mat_C;
size_t memsize = TOTAL_COLS * TOTAL_ROWS * sizeof(float);
/* Allocate memories for the matrices*/
err = cudaMallocManaged(&mat_A, memsize);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix A (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMallocManaged(&mat_B, memsize);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix B (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMallocManaged(&mat_C, memsize);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix C (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Initialize matrices A and B */
int blocksize_for_init = 256;
int blocks_for_init = (TOTAL_ROWS*TOTAL_COLS + blocksize_for_init - 1)
/ (blocksize_for_init);
init_matrix<<<blocks_for_init, blocksize_for_init>>>(mat_A, TOTAL_COLS, TOTAL_ROWS, 1);
init_matrix<<<blocks_for_init, blocksize_for_init>>>(mat_B, TOTAL_COLS, TOTAL_ROWS, 2);
err = cudaGetLastError();
if( err != cudaSuccess) {
fprintf(stderr, "Failed to initialize matrix (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Do the matrix addition */
size_t blocksizeX = 16;
size_t blocksizeY = 16;
dim3 DimGrid( (TOTAL_COLS-1)/blocksizeX + 1, (TOTAL_ROWS-1)/blocksizeY + 1);
dim3 DimBlock( blocksizeX, blocksizeY);
add_matrices<<<DimGrid, DimBlock>>>(mat_A, mat_B, mat_C, TOTAL_COLS, TOTAL_ROWS);
err = cudaGetLastError();
if( err != cudaSuccess) {
fprintf(stderr, "Failed to perform matrix addition (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cudaDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < (TOTAL_ROWS*TOTAL_COLS); i++)
maxError = fmax(maxError, fabs(mat_C[i]-3.0f));
printf("Max error: %f\n", maxError);
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z12add_matricesPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R3, c[0x0][0x4], R0 ; /* 0x0000010003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, c[0x0][0x178], R3 ; /* 0x00005e0000007a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0120*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11init_matrixPfiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fe20000000f00 */
/*00a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ MOV R9, c[0x0][0xc] ; /* 0x0000030000097a02 */
/* 0x000fce0000000f00 */
/*00c0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*00d0*/ IMAD R0, R9, c[0x0][0x0], R0 ; /* 0x0000000009007a24 */
/* 0x000fe200078e0200 */
/*00e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101906 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0100*/ @!P0 BRA 0xc0 ; /* 0xffffffb000008947 */
/* 0x001fea000383ffff */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Copyright (c) 2020 Saurabh Yadav
//
// This software is released under the MIT License.
// https://opensource.org/licenses/MIT
#include <stdio.h>
#include <unistd.h>
#include <stdlib.h>
#include <math.h>
#include <cuda_runtime.h>
#define TOTAL_ROWS 1000U
#define TOTAL_COLS 2000U
__global__
void init_matrix(float *matrix, int width, int height, float val) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = idx; i < width * height; i += gridDim.x * blockDim.x) {
matrix[i]=val;
}
}
__global__
void add_matrices(float * mat_A_arr, float * mat_B_arr, float * mat_C_arr,
int num_cols, int num_rows) {
int row = threadIdx.y + blockIdx.y * blockDim.y;
int col = threadIdx.x + blockIdx.x * blockDim.x;
if(row < num_rows && col < num_cols) {
mat_C_arr[row*num_cols + col] = mat_A_arr[row*num_cols + col] +
mat_B_arr[row*num_cols + col];
}
}
int main() {
cudaError_t err = cudaSuccess;
float *mat_A, *mat_B, *mat_C;
size_t memsize = TOTAL_COLS * TOTAL_ROWS * sizeof(float);
/* Allocate memories for the matrices*/
err = cudaMallocManaged(&mat_A, memsize);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix A (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMallocManaged(&mat_B, memsize);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix B (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMallocManaged(&mat_C, memsize);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix C (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Initialize matrices A and B */
int blocksize_for_init = 256;
int blocks_for_init = (TOTAL_ROWS*TOTAL_COLS + blocksize_for_init - 1)
/ (blocksize_for_init);
init_matrix<<<blocks_for_init, blocksize_for_init>>>(mat_A, TOTAL_COLS, TOTAL_ROWS, 1);
init_matrix<<<blocks_for_init, blocksize_for_init>>>(mat_B, TOTAL_COLS, TOTAL_ROWS, 2);
err = cudaGetLastError();
if( err != cudaSuccess) {
fprintf(stderr, "Failed to initialize matrix (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Do the matrix addition */
size_t blocksizeX = 16;
size_t blocksizeY = 16;
dim3 DimGrid( (TOTAL_COLS-1)/blocksizeX + 1, (TOTAL_ROWS-1)/blocksizeY + 1);
dim3 DimBlock( blocksizeX, blocksizeY);
add_matrices<<<DimGrid, DimBlock>>>(mat_A, mat_B, mat_C, TOTAL_COLS, TOTAL_ROWS);
err = cudaGetLastError();
if( err != cudaSuccess) {
fprintf(stderr, "Failed to perform matrix addition (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cudaDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < (TOTAL_ROWS*TOTAL_COLS); i++)
maxError = fmax(maxError, fabs(mat_C[i]-3.0f));
printf("Max error: %f\n", maxError);
return EXIT_SUCCESS;
} | .file "tmpxft_00024373_00000000-6_matrix_addition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z11init_matrixPfiifPfiif
.type _Z34__device_stub__Z11init_matrixPfiifPfiif, @function
_Z34__device_stub__Z11init_matrixPfiifPfiif:
.LFB2095:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11init_matrixPfiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z34__device_stub__Z11init_matrixPfiifPfiif, .-_Z34__device_stub__Z11init_matrixPfiifPfiif
.globl _Z11init_matrixPfiif
.type _Z11init_matrixPfiif, @function
_Z11init_matrixPfiif:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11init_matrixPfiifPfiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z11init_matrixPfiif, .-_Z11init_matrixPfiif
.globl _Z38__device_stub__Z12add_matricesPfS_S_iiPfS_S_ii
.type _Z38__device_stub__Z12add_matricesPfS_S_iiPfS_S_ii, @function
_Z38__device_stub__Z12add_matricesPfS_S_iiPfS_S_ii:
.LFB2097:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12add_matricesPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2097:
.size _Z38__device_stub__Z12add_matricesPfS_S_iiPfS_S_ii, .-_Z38__device_stub__Z12add_matricesPfS_S_iiPfS_S_ii
.globl _Z12add_matricesPfS_S_ii
.type _Z12add_matricesPfS_S_ii, @function
_Z12add_matricesPfS_S_ii:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12add_matricesPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _Z12add_matricesPfS_S_ii, .-_Z12add_matricesPfS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Failed to allocate memory for matrix A (error code %s)!\n"
.align 8
.LC2:
.string "Failed to allocate memory for matrix B (error code %s)!\n"
.align 8
.LC3:
.string "Failed to allocate memory for matrix C (error code %s)!\n"
.align 8
.LC6:
.string "Failed to initialize matrix (error code %s)!\n"
.align 8
.LC7:
.string "Failed to perform matrix addition (error code %s)!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC10:
.string "Max error: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $8000000, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L32
leaq 16(%rsp), %rdi
movl $1, %edx
movl $8000000, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L33
leaq 24(%rsp), %rdi
movl $1, %edx
movl $8000000, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L34
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $7813, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L23:
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $7813, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L24:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L37
movl $125, 32(%rsp)
movl $63, 36(%rsp)
movl $1, 40(%rsp)
movl $16, 44(%rsp)
movl $16, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L26:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L39
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rbx
leaq 8000000(%rbx), %rbp
pxor %xmm1, %xmm1
.L28:
movss (%rbx), %xmm2
subss .LC8(%rip), %xmm2
andps .LC9(%rip), %xmm2
movaps %xmm2, %xmm0
call fmaxf@PLT
movaps %xmm0, %xmm1
addq $4, %rbx
cmpq %rbp, %rbx
jne .L28
cvtss2sd %xmm0, %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
movss .LC4(%rip), %xmm0
movl $1000, %edx
movl $2000, %esi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z11init_matrixPfiifPfiif
jmp .L23
.L36:
movss .LC5(%rip), %xmm0
movl $1000, %edx
movl $2000, %esi
movq 16(%rsp), %rdi
call _Z34__device_stub__Z11init_matrixPfiifPfiif
jmp .L24
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl $1000, %r8d
movl $2000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z12add_matricesPfS_S_iiPfS_S_ii
jmp .L26
.L39:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z12add_matricesPfS_S_ii"
.LC12:
.string "_Z11init_matrixPfiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2100:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z12add_matricesPfS_S_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z11init_matrixPfiif(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2100:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1065353216
.align 4
.LC5:
.long 1073741824
.align 4
.LC8:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC9:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Copyright (c) 2020 Saurabh Yadav
//
// This software is released under the MIT License.
// https://opensource.org/licenses/MIT
#include <stdio.h>
#include <unistd.h>
#include <stdlib.h>
#include <math.h>
#include <cuda_runtime.h>
#define TOTAL_ROWS 1000U
#define TOTAL_COLS 2000U
__global__
void init_matrix(float *matrix, int width, int height, float val) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = idx; i < width * height; i += gridDim.x * blockDim.x) {
matrix[i]=val;
}
}
__global__
void add_matrices(float * mat_A_arr, float * mat_B_arr, float * mat_C_arr,
int num_cols, int num_rows) {
int row = threadIdx.y + blockIdx.y * blockDim.y;
int col = threadIdx.x + blockIdx.x * blockDim.x;
if(row < num_rows && col < num_cols) {
mat_C_arr[row*num_cols + col] = mat_A_arr[row*num_cols + col] +
mat_B_arr[row*num_cols + col];
}
}
int main() {
cudaError_t err = cudaSuccess;
float *mat_A, *mat_B, *mat_C;
size_t memsize = TOTAL_COLS * TOTAL_ROWS * sizeof(float);
/* Allocate memories for the matrices*/
err = cudaMallocManaged(&mat_A, memsize);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix A (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMallocManaged(&mat_B, memsize);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix B (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMallocManaged(&mat_C, memsize);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix C (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Initialize matrices A and B */
int blocksize_for_init = 256;
int blocks_for_init = (TOTAL_ROWS*TOTAL_COLS + blocksize_for_init - 1)
/ (blocksize_for_init);
init_matrix<<<blocks_for_init, blocksize_for_init>>>(mat_A, TOTAL_COLS, TOTAL_ROWS, 1);
init_matrix<<<blocks_for_init, blocksize_for_init>>>(mat_B, TOTAL_COLS, TOTAL_ROWS, 2);
err = cudaGetLastError();
if( err != cudaSuccess) {
fprintf(stderr, "Failed to initialize matrix (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Do the matrix addition */
size_t blocksizeX = 16;
size_t blocksizeY = 16;
dim3 DimGrid( (TOTAL_COLS-1)/blocksizeX + 1, (TOTAL_ROWS-1)/blocksizeY + 1);
dim3 DimBlock( blocksizeX, blocksizeY);
add_matrices<<<DimGrid, DimBlock>>>(mat_A, mat_B, mat_C, TOTAL_COLS, TOTAL_ROWS);
err = cudaGetLastError();
if( err != cudaSuccess) {
fprintf(stderr, "Failed to perform matrix addition (error code %s)!\n",
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cudaDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < (TOTAL_ROWS*TOTAL_COLS); i++)
maxError = fmax(maxError, fabs(mat_C[i]-3.0f));
printf("Max error: %f\n", maxError);
return EXIT_SUCCESS;
} | // Copyright (c) 2020 Saurabh Yadav
//
// This software is released under the MIT License.
// https://opensource.org/licenses/MIT
#include <stdio.h>
#include <unistd.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define TOTAL_ROWS 1000U
#define TOTAL_COLS 2000U
__global__
void init_matrix(float *matrix, int width, int height, float val) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = idx; i < width * height; i += gridDim.x * blockDim.x) {
matrix[i]=val;
}
}
__global__
void add_matrices(float * mat_A_arr, float * mat_B_arr, float * mat_C_arr,
int num_cols, int num_rows) {
int row = threadIdx.y + blockIdx.y * blockDim.y;
int col = threadIdx.x + blockIdx.x * blockDim.x;
if(row < num_rows && col < num_cols) {
mat_C_arr[row*num_cols + col] = mat_A_arr[row*num_cols + col] +
mat_B_arr[row*num_cols + col];
}
}
int main() {
hipError_t err = hipSuccess;
float *mat_A, *mat_B, *mat_C;
size_t memsize = TOTAL_COLS * TOTAL_ROWS * sizeof(float);
/* Allocate memories for the matrices*/
err = hipMallocManaged(&mat_A, memsize);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix A (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMallocManaged(&mat_B, memsize);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix B (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMallocManaged(&mat_C, memsize);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix C (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Initialize matrices A and B */
int blocksize_for_init = 256;
int blocks_for_init = (TOTAL_ROWS*TOTAL_COLS + blocksize_for_init - 1)
/ (blocksize_for_init);
init_matrix<<<blocks_for_init, blocksize_for_init>>>(mat_A, TOTAL_COLS, TOTAL_ROWS, 1);
init_matrix<<<blocks_for_init, blocksize_for_init>>>(mat_B, TOTAL_COLS, TOTAL_ROWS, 2);
err = hipGetLastError();
if( err != hipSuccess) {
fprintf(stderr, "Failed to initialize matrix (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Do the matrix addition */
size_t blocksizeX = 16;
size_t blocksizeY = 16;
dim3 DimGrid( (TOTAL_COLS-1)/blocksizeX + 1, (TOTAL_ROWS-1)/blocksizeY + 1);
dim3 DimBlock( blocksizeX, blocksizeY);
add_matrices<<<DimGrid, DimBlock>>>(mat_A, mat_B, mat_C, TOTAL_COLS, TOTAL_ROWS);
err = hipGetLastError();
if( err != hipSuccess) {
fprintf(stderr, "Failed to perform matrix addition (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < (TOTAL_ROWS*TOTAL_COLS); i++)
maxError = fmax(maxError, fabs(mat_C[i]-3.0f));
printf("Max error: %f\n", maxError);
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Copyright (c) 2020 Saurabh Yadav
//
// This software is released under the MIT License.
// https://opensource.org/licenses/MIT
#include <stdio.h>
#include <unistd.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define TOTAL_ROWS 1000U
#define TOTAL_COLS 2000U
__global__
void init_matrix(float *matrix, int width, int height, float val) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = idx; i < width * height; i += gridDim.x * blockDim.x) {
matrix[i]=val;
}
}
__global__
void add_matrices(float * mat_A_arr, float * mat_B_arr, float * mat_C_arr,
int num_cols, int num_rows) {
int row = threadIdx.y + blockIdx.y * blockDim.y;
int col = threadIdx.x + blockIdx.x * blockDim.x;
if(row < num_rows && col < num_cols) {
mat_C_arr[row*num_cols + col] = mat_A_arr[row*num_cols + col] +
mat_B_arr[row*num_cols + col];
}
}
int main() {
hipError_t err = hipSuccess;
float *mat_A, *mat_B, *mat_C;
size_t memsize = TOTAL_COLS * TOTAL_ROWS * sizeof(float);
/* Allocate memories for the matrices*/
err = hipMallocManaged(&mat_A, memsize);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix A (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMallocManaged(&mat_B, memsize);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix B (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMallocManaged(&mat_C, memsize);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix C (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Initialize matrices A and B */
int blocksize_for_init = 256;
int blocks_for_init = (TOTAL_ROWS*TOTAL_COLS + blocksize_for_init - 1)
/ (blocksize_for_init);
init_matrix<<<blocks_for_init, blocksize_for_init>>>(mat_A, TOTAL_COLS, TOTAL_ROWS, 1);
init_matrix<<<blocks_for_init, blocksize_for_init>>>(mat_B, TOTAL_COLS, TOTAL_ROWS, 2);
err = hipGetLastError();
if( err != hipSuccess) {
fprintf(stderr, "Failed to initialize matrix (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Do the matrix addition */
size_t blocksizeX = 16;
size_t blocksizeY = 16;
dim3 DimGrid( (TOTAL_COLS-1)/blocksizeX + 1, (TOTAL_ROWS-1)/blocksizeY + 1);
dim3 DimBlock( blocksizeX, blocksizeY);
add_matrices<<<DimGrid, DimBlock>>>(mat_A, mat_B, mat_C, TOTAL_COLS, TOTAL_ROWS);
err = hipGetLastError();
if( err != hipSuccess) {
fprintf(stderr, "Failed to perform matrix addition (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < (TOTAL_ROWS*TOTAL_COLS); i++)
maxError = fmax(maxError, fabs(mat_C[i]-3.0f));
printf("Max error: %f\n", maxError);
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11init_matrixPfiif
.globl _Z11init_matrixPfiif
.p2align 8
.type _Z11init_matrixPfiif,@function
_Z11init_matrixPfiif:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x8
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_mul_i32 s4, s7, s6
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b32 s6, s[0:1], 0x10
s_load_b32 s7, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s6
s_mul_i32 s1, s7, s5
s_mov_b32 s5, 0
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, s2, v2
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s5, vcc_lo, s5
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11init_matrixPfiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11init_matrixPfiif, .Lfunc_end0-_Z11init_matrixPfiif
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12add_matricesPfS_S_ii
.globl _Z12add_matricesPfS_S_ii
.p2align 8
.type _Z12add_matricesPfS_S_ii,@function
_Z12add_matricesPfS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_2
s_load_b128 s[8:11], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12add_matricesPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12add_matricesPfS_S_ii, .Lfunc_end1-_Z12add_matricesPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11init_matrixPfiif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11init_matrixPfiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12add_matricesPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12add_matricesPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Copyright (c) 2020 Saurabh Yadav
//
// This software is released under the MIT License.
// https://opensource.org/licenses/MIT
#include <stdio.h>
#include <unistd.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define TOTAL_ROWS 1000U
#define TOTAL_COLS 2000U
__global__
void init_matrix(float *matrix, int width, int height, float val) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for (int i = idx; i < width * height; i += gridDim.x * blockDim.x) {
matrix[i]=val;
}
}
__global__
void add_matrices(float * mat_A_arr, float * mat_B_arr, float * mat_C_arr,
int num_cols, int num_rows) {
int row = threadIdx.y + blockIdx.y * blockDim.y;
int col = threadIdx.x + blockIdx.x * blockDim.x;
if(row < num_rows && col < num_cols) {
mat_C_arr[row*num_cols + col] = mat_A_arr[row*num_cols + col] +
mat_B_arr[row*num_cols + col];
}
}
int main() {
hipError_t err = hipSuccess;
float *mat_A, *mat_B, *mat_C;
size_t memsize = TOTAL_COLS * TOTAL_ROWS * sizeof(float);
/* Allocate memories for the matrices*/
err = hipMallocManaged(&mat_A, memsize);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix A (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMallocManaged(&mat_B, memsize);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix B (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMallocManaged(&mat_C, memsize);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate memory for matrix C (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Initialize matrices A and B */
int blocksize_for_init = 256;
int blocks_for_init = (TOTAL_ROWS*TOTAL_COLS + blocksize_for_init - 1)
/ (blocksize_for_init);
init_matrix<<<blocks_for_init, blocksize_for_init>>>(mat_A, TOTAL_COLS, TOTAL_ROWS, 1);
init_matrix<<<blocks_for_init, blocksize_for_init>>>(mat_B, TOTAL_COLS, TOTAL_ROWS, 2);
err = hipGetLastError();
if( err != hipSuccess) {
fprintf(stderr, "Failed to initialize matrix (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Do the matrix addition */
size_t blocksizeX = 16;
size_t blocksizeY = 16;
dim3 DimGrid( (TOTAL_COLS-1)/blocksizeX + 1, (TOTAL_ROWS-1)/blocksizeY + 1);
dim3 DimBlock( blocksizeX, blocksizeY);
add_matrices<<<DimGrid, DimBlock>>>(mat_A, mat_B, mat_C, TOTAL_COLS, TOTAL_ROWS);
err = hipGetLastError();
if( err != hipSuccess) {
fprintf(stderr, "Failed to perform matrix addition (error code %s)!\n",
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < (TOTAL_ROWS*TOTAL_COLS); i++)
maxError = fmax(maxError, fabs(mat_C[i]-3.0f));
printf("Max error: %f\n", maxError);
return EXIT_SUCCESS;
} | .text
.file "matrix_addition.hip"
.globl _Z26__device_stub__init_matrixPfiif # -- Begin function _Z26__device_stub__init_matrixPfiif
.p2align 4, 0x90
.type _Z26__device_stub__init_matrixPfiif,@function
_Z26__device_stub__init_matrixPfiif: # @_Z26__device_stub__init_matrixPfiif
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11init_matrixPfiif, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__init_matrixPfiif, .Lfunc_end0-_Z26__device_stub__init_matrixPfiif
.cfi_endproc
# -- End function
.globl _Z27__device_stub__add_matricesPfS_S_ii # -- Begin function _Z27__device_stub__add_matricesPfS_S_ii
.p2align 4, 0x90
.type _Z27__device_stub__add_matricesPfS_S_ii,@function
_Z27__device_stub__add_matricesPfS_S_ii: # @_Z27__device_stub__add_matricesPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12add_matricesPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__add_matricesPfS_S_ii, .Lfunc_end1-_Z27__device_stub__add_matricesPfS_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $168, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 160(%rsp), %rdi
movl $8000000, %esi # imm = 0x7A1200
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB2_1
# %bb.3:
leaq 152(%rsp), %rdi
movl $8000000, %esi # imm = 0x7A1200
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB2_4
# %bb.5:
leaq 144(%rsp), %rdi
movl $8000000, %esi # imm = 0x7A1200
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB2_6
# %bb.7:
movabsq $4294967552, %rbx # imm = 0x100000100
leaq 7557(%rbx), %r14
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_9
# %bb.8:
movq 160(%rsp), %rax
movq %rax, 80(%rsp)
movl $2000, 24(%rsp) # imm = 0x7D0
movl $1000, 16(%rsp) # imm = 0x3E8
movl $1065353216, 12(%rsp) # imm = 0x3F800000
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11init_matrixPfiif, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_9:
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10:
movq 152(%rsp), %rax
movq %rax, 80(%rsp)
movl $2000, 24(%rsp) # imm = 0x7D0
movl $1000, 16(%rsp) # imm = 0x3E8
movl $1073741824, 12(%rsp) # imm = 0x40000000
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11init_matrixPfiif, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_12
# %bb.13:
movabsq $270582939773, %rdi # imm = 0x3F0000007D
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_15
# %bb.14:
movq 160(%rsp), %rax
movq 152(%rsp), %rcx
movq 144(%rsp), %rdx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
movl $2000, 12(%rsp) # imm = 0x7D0
movl $1000, 92(%rsp) # imm = 0x3E8
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 92(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12add_matricesPfS_S_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_15:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_16
# %bb.17:
callq hipDeviceSynchronize
xorps %xmm3, %xmm3
xorl %eax, %eax
movq 144(%rsp), %rcx
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI2_1(%rip), %xmm2 # xmm2 = [NaN,NaN,NaN,NaN]
movaps %xmm3, %xmm1
.p2align 4, 0x90
.LBB2_18: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rax,4), %xmm4 # xmm4 = mem[0],zero,zero,zero
addss %xmm0, %xmm4
andps %xmm2, %xmm4
cmpunordss %xmm1, %xmm1
movaps %xmm1, %xmm5
andps %xmm4, %xmm5
maxss %xmm3, %xmm4
andnps %xmm4, %xmm1
orps %xmm5, %xmm1
incq %rax
movaps %xmm1, %xmm3
cmpq $2000000, %rax # imm = 0x1E8480
jne .LBB2_18
# %bb.19:
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
jmp .LBB2_2
.LBB2_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
jmp .LBB2_2
.LBB2_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
jmp .LBB2_2
.LBB2_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
jmp .LBB2_2
.LBB2_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
.LBB2_2:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11init_matrixPfiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12add_matricesPfS_S_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11init_matrixPfiif,@object # @_Z11init_matrixPfiif
.section .rodata,"a",@progbits
.globl _Z11init_matrixPfiif
.p2align 3, 0x0
_Z11init_matrixPfiif:
.quad _Z26__device_stub__init_matrixPfiif
.size _Z11init_matrixPfiif, 8
.type _Z12add_matricesPfS_S_ii,@object # @_Z12add_matricesPfS_S_ii
.globl _Z12add_matricesPfS_S_ii
.p2align 3, 0x0
_Z12add_matricesPfS_S_ii:
.quad _Z27__device_stub__add_matricesPfS_S_ii
.size _Z12add_matricesPfS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to allocate memory for matrix A (error code %s)!\n"
.size .L.str, 57
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed to allocate memory for matrix B (error code %s)!\n"
.size .L.str.1, 57
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate memory for matrix C (error code %s)!\n"
.size .L.str.2, 57
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to initialize matrix (error code %s)!\n"
.size .L.str.3, 46
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to perform matrix addition (error code %s)!\n"
.size .L.str.4, 52
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Max error: %f\n"
.size .L.str.5, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11init_matrixPfiif"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12add_matricesPfS_S_ii"
.size .L__unnamed_2, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__init_matrixPfiif
.addrsig_sym _Z27__device_stub__add_matricesPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11init_matrixPfiif
.addrsig_sym _Z12add_matricesPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12add_matricesPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R3, c[0x0][0x4], R0 ; /* 0x0000010003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, c[0x0][0x178], R3 ; /* 0x00005e0000007a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0120*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11init_matrixPfiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fe20000000f00 */
/*00a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ MOV R9, c[0x0][0xc] ; /* 0x0000030000097a02 */
/* 0x000fce0000000f00 */
/*00c0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*00d0*/ IMAD R0, R9, c[0x0][0x0], R0 ; /* 0x0000000009007a24 */
/* 0x000fe200078e0200 */
/*00e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101906 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0100*/ @!P0 BRA 0xc0 ; /* 0xffffffb000008947 */
/* 0x001fea000383ffff */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11init_matrixPfiif
.globl _Z11init_matrixPfiif
.p2align 8
.type _Z11init_matrixPfiif,@function
_Z11init_matrixPfiif:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x8
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_mul_i32 s4, s7, s6
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b32 s6, s[0:1], 0x10
s_load_b32 s7, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s6
s_mul_i32 s1, s7, s5
s_mov_b32 s5, 0
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, s2, v2
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s5, vcc_lo, s5
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11init_matrixPfiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11init_matrixPfiif, .Lfunc_end0-_Z11init_matrixPfiif
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12add_matricesPfS_S_ii
.globl _Z12add_matricesPfS_S_ii
.p2align 8
.type _Z12add_matricesPfS_S_ii,@function
_Z12add_matricesPfS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_2
s_load_b128 s[8:11], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12add_matricesPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12add_matricesPfS_S_ii, .Lfunc_end1-_Z12add_matricesPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11init_matrixPfiif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11init_matrixPfiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12add_matricesPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12add_matricesPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00024373_00000000-6_matrix_addition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z11init_matrixPfiifPfiif
.type _Z34__device_stub__Z11init_matrixPfiifPfiif, @function
_Z34__device_stub__Z11init_matrixPfiifPfiif:
.LFB2095:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11init_matrixPfiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z34__device_stub__Z11init_matrixPfiifPfiif, .-_Z34__device_stub__Z11init_matrixPfiifPfiif
.globl _Z11init_matrixPfiif
.type _Z11init_matrixPfiif, @function
_Z11init_matrixPfiif:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11init_matrixPfiifPfiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z11init_matrixPfiif, .-_Z11init_matrixPfiif
.globl _Z38__device_stub__Z12add_matricesPfS_S_iiPfS_S_ii
.type _Z38__device_stub__Z12add_matricesPfS_S_iiPfS_S_ii, @function
_Z38__device_stub__Z12add_matricesPfS_S_iiPfS_S_ii:
.LFB2097:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12add_matricesPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2097:
.size _Z38__device_stub__Z12add_matricesPfS_S_iiPfS_S_ii, .-_Z38__device_stub__Z12add_matricesPfS_S_iiPfS_S_ii
.globl _Z12add_matricesPfS_S_ii
.type _Z12add_matricesPfS_S_ii, @function
_Z12add_matricesPfS_S_ii:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12add_matricesPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _Z12add_matricesPfS_S_ii, .-_Z12add_matricesPfS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Failed to allocate memory for matrix A (error code %s)!\n"
.align 8
.LC2:
.string "Failed to allocate memory for matrix B (error code %s)!\n"
.align 8
.LC3:
.string "Failed to allocate memory for matrix C (error code %s)!\n"
.align 8
.LC6:
.string "Failed to initialize matrix (error code %s)!\n"
.align 8
.LC7:
.string "Failed to perform matrix addition (error code %s)!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC10:
.string "Max error: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $8000000, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L32
leaq 16(%rsp), %rdi
movl $1, %edx
movl $8000000, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L33
leaq 24(%rsp), %rdi
movl $1, %edx
movl $8000000, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L34
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $7813, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L23:
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $7813, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L24:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L37
movl $125, 32(%rsp)
movl $63, 36(%rsp)
movl $1, 40(%rsp)
movl $16, 44(%rsp)
movl $16, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L26:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L39
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rbx
leaq 8000000(%rbx), %rbp
pxor %xmm1, %xmm1
.L28:
movss (%rbx), %xmm2
subss .LC8(%rip), %xmm2
andps .LC9(%rip), %xmm2
movaps %xmm2, %xmm0
call fmaxf@PLT
movaps %xmm0, %xmm1
addq $4, %rbx
cmpq %rbp, %rbx
jne .L28
cvtss2sd %xmm0, %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
movss .LC4(%rip), %xmm0
movl $1000, %edx
movl $2000, %esi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z11init_matrixPfiifPfiif
jmp .L23
.L36:
movss .LC5(%rip), %xmm0
movl $1000, %edx
movl $2000, %esi
movq 16(%rsp), %rdi
call _Z34__device_stub__Z11init_matrixPfiifPfiif
jmp .L24
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl $1000, %r8d
movl $2000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z12add_matricesPfS_S_iiPfS_S_ii
jmp .L26
.L39:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z12add_matricesPfS_S_ii"
.LC12:
.string "_Z11init_matrixPfiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2100:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z12add_matricesPfS_S_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z11init_matrixPfiif(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2100:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1065353216
.align 4
.LC5:
.long 1073741824
.align 4
.LC8:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC9:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_addition.hip"
.globl _Z26__device_stub__init_matrixPfiif # -- Begin function _Z26__device_stub__init_matrixPfiif
.p2align 4, 0x90
.type _Z26__device_stub__init_matrixPfiif,@function
_Z26__device_stub__init_matrixPfiif: # @_Z26__device_stub__init_matrixPfiif
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11init_matrixPfiif, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__init_matrixPfiif, .Lfunc_end0-_Z26__device_stub__init_matrixPfiif
.cfi_endproc
# -- End function
.globl _Z27__device_stub__add_matricesPfS_S_ii # -- Begin function _Z27__device_stub__add_matricesPfS_S_ii
.p2align 4, 0x90
.type _Z27__device_stub__add_matricesPfS_S_ii,@function
_Z27__device_stub__add_matricesPfS_S_ii: # @_Z27__device_stub__add_matricesPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12add_matricesPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__add_matricesPfS_S_ii, .Lfunc_end1-_Z27__device_stub__add_matricesPfS_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $168, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 160(%rsp), %rdi
movl $8000000, %esi # imm = 0x7A1200
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB2_1
# %bb.3:
leaq 152(%rsp), %rdi
movl $8000000, %esi # imm = 0x7A1200
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB2_4
# %bb.5:
leaq 144(%rsp), %rdi
movl $8000000, %esi # imm = 0x7A1200
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB2_6
# %bb.7:
movabsq $4294967552, %rbx # imm = 0x100000100
leaq 7557(%rbx), %r14
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_9
# %bb.8:
movq 160(%rsp), %rax
movq %rax, 80(%rsp)
movl $2000, 24(%rsp) # imm = 0x7D0
movl $1000, 16(%rsp) # imm = 0x3E8
movl $1065353216, 12(%rsp) # imm = 0x3F800000
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11init_matrixPfiif, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_9:
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10:
movq 152(%rsp), %rax
movq %rax, 80(%rsp)
movl $2000, 24(%rsp) # imm = 0x7D0
movl $1000, 16(%rsp) # imm = 0x3E8
movl $1073741824, 12(%rsp) # imm = 0x40000000
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11init_matrixPfiif, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_12
# %bb.13:
movabsq $270582939773, %rdi # imm = 0x3F0000007D
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_15
# %bb.14:
movq 160(%rsp), %rax
movq 152(%rsp), %rcx
movq 144(%rsp), %rdx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
movl $2000, 12(%rsp) # imm = 0x7D0
movl $1000, 92(%rsp) # imm = 0x3E8
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 92(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12add_matricesPfS_S_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_15:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_16
# %bb.17:
callq hipDeviceSynchronize
xorps %xmm3, %xmm3
xorl %eax, %eax
movq 144(%rsp), %rcx
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI2_1(%rip), %xmm2 # xmm2 = [NaN,NaN,NaN,NaN]
movaps %xmm3, %xmm1
.p2align 4, 0x90
.LBB2_18: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rax,4), %xmm4 # xmm4 = mem[0],zero,zero,zero
addss %xmm0, %xmm4
andps %xmm2, %xmm4
cmpunordss %xmm1, %xmm1
movaps %xmm1, %xmm5
andps %xmm4, %xmm5
maxss %xmm3, %xmm4
andnps %xmm4, %xmm1
orps %xmm5, %xmm1
incq %rax
movaps %xmm1, %xmm3
cmpq $2000000, %rax # imm = 0x1E8480
jne .LBB2_18
# %bb.19:
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
jmp .LBB2_2
.LBB2_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
jmp .LBB2_2
.LBB2_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
jmp .LBB2_2
.LBB2_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
jmp .LBB2_2
.LBB2_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
.LBB2_2:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11init_matrixPfiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12add_matricesPfS_S_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11init_matrixPfiif,@object # @_Z11init_matrixPfiif
.section .rodata,"a",@progbits
.globl _Z11init_matrixPfiif
.p2align 3, 0x0
_Z11init_matrixPfiif:
.quad _Z26__device_stub__init_matrixPfiif
.size _Z11init_matrixPfiif, 8
.type _Z12add_matricesPfS_S_ii,@object # @_Z12add_matricesPfS_S_ii
.globl _Z12add_matricesPfS_S_ii
.p2align 3, 0x0
_Z12add_matricesPfS_S_ii:
.quad _Z27__device_stub__add_matricesPfS_S_ii
.size _Z12add_matricesPfS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to allocate memory for matrix A (error code %s)!\n"
.size .L.str, 57
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Failed to allocate memory for matrix B (error code %s)!\n"
.size .L.str.1, 57
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate memory for matrix C (error code %s)!\n"
.size .L.str.2, 57
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to initialize matrix (error code %s)!\n"
.size .L.str.3, 46
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to perform matrix addition (error code %s)!\n"
.size .L.str.4, 52
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Max error: %f\n"
.size .L.str.5, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11init_matrixPfiif"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12add_matricesPfS_S_ii"
.size .L__unnamed_2, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__init_matrixPfiif
.addrsig_sym _Z27__device_stub__add_matricesPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11init_matrixPfiif
.addrsig_sym _Z12add_matricesPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void derive(double *data, double *out, int stride, int gsize, double dx){
int gid = getGid3d3d();
if (gid < gsize){
if (gid + stride < gsize){
out[gid] = (data[gid+stride] - data[gid])/dx;
}
else{
out[gid] = data[gid]/dx;
}
}
} | code for sm_80
Function : _Z6derivePdS_iid
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e280000002700 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R7, SR_TID.Z ; /* 0x0000000000077919 */
/* 0x000ea80000002300 */
/*0050*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000ee80000002200 */
/*0060*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000f220000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x10], R3 ; /* 0x0000040000007a24 */
/* 0x001fc800078e0203 */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R0, c[0x0][0x8], R7 ; /* 0x0000020000007a24 */
/* 0x004fc800078e0207 */
/*00a0*/ IMAD R0, R0, c[0x0][0x4], R9 ; /* 0x0000010000007a24 */
/* 0x008fc800078e0209 */
/*00b0*/ IMAD R0, R0, c[0x0][0x0], R11 ; /* 0x0000000000007a24 */
/* 0x010fca00078e020b */
/*00c0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06270 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R6, R0, c[0x0][0x170], RZ ; /* 0x00005c0000067a10 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe200078e00ff */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0110*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x174], PT ; /* 0x00005d0006007a0c */
/* 0x000fe20003f06270 */
/*0120*/ IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0207 */
/*0130*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fd000078e0207 */
/*0140*/ @!P0 BRA 0x300 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0150*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*0160*/ MUFU.RCP64H R7, c[0x0][0x17c] ; /* 0x00005f0000077b08 */
/* 0x000e220000001800 */
/*0170*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0a7624 */
/* 0x000fe200078e00ff */
/*0180*/ BSSY B0, 0x2e0 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0190*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff0b7624 */
/* 0x000fe400078e00ff */
/*01a0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fcc00078e00ff */
/*01b0*/ DFMA R8, R6, -R10, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c000000080a */
/*01c0*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*01d0*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*01e0*/ DFMA R6, R8, -R10, 1 ; /* 0x3ff000000806742b */
/* 0x001e0c000000080a */
/*01f0*/ DFMA R6, R8, R6, R8 ; /* 0x000000060806722b */
/* 0x001e8c0000000008 */
/*0200*/ DMUL R8, R4, R6 ; /* 0x0000000604087228 */
/* 0x004e220000000000 */
/*0210*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x000fca0003f2e200 */
/*0220*/ DFMA R10, R8, -c[0x0][0x178], R4 ; /* 0x80005e00080a7a2b */
/* 0x001e0c0000000004 */
/*0230*/ DFMA R6, R6, R10, R8 ; /* 0x0000000a0606722b */
/* 0x001e140000000008 */
/*0240*/ FFMA R0, RZ, c[0x0][0x17c], R7 ; /* 0x00005f00ff007a23 */
/* 0x001fca0000000007 */
/*0250*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0260*/ @P0 BRA P1, 0x2d0 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0270*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0280*/ MOV R0, 0x2d0 ; /* 0x000002d000007802 */
/* 0x000fe20000000f00 */
/*0290*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0005 */
/*02a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff067624 */
/* 0x000fe400078e00ff */
/*02b0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff077624 */
/* 0x000fe400078e00ff */
/*02c0*/ CALL.REL.NOINC 0x4e0 ; /* 0x0000021000007944 */
/* 0x000fea0003c00000 */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02e0*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe2000c101b04 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0310*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000eaa000c1e1b00 */
/*0320*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*0330*/ MUFU.RCP64H R9, c[0x0][0x17c] ; /* 0x00005f0000097b08 */
/* 0x000e220000001800 */
/*0340*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0a7624 */
/* 0x000fe200078e00ff */
/*0350*/ BSSY B0, 0x4c0 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*0360*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff0b7624 */
/* 0x000fc400078e00ff */
/*0370*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fcc00078e00ff */
/*0380*/ DFMA R12, R8, -R10, 1 ; /* 0x3ff00000080c742b */
/* 0x001e0c000000080a */
/*0390*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*03a0*/ DFMA R12, R8, R12, R8 ; /* 0x0000000c080c722b */
/* 0x001e0c0000000008 */
/*03b0*/ DFMA R10, R12, -R10, 1 ; /* 0x3ff000000c0a742b */
/* 0x001e0c000000080a */
/*03c0*/ DFMA R10, R12, R10, R12 ; /* 0x0000000a0c0a722b */
/* 0x001fc8000000000c */
/*03d0*/ DADD R8, -R4, R6 ; /* 0x0000000004087229 */
/* 0x004e0c0000000106 */
/*03e0*/ DMUL R4, R8, R10 ; /* 0x0000000a08047228 */
/* 0x001e080000000000 */
/*03f0*/ FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT ; /* 0x036000000900780b */
/* 0x000fe40003f2e200 */
/*0400*/ DFMA R6, R4, -c[0x0][0x178], R8 ; /* 0x80005e0004067a2b */
/* 0x001e0c0000000008 */
/*0410*/ DFMA R4, R6, R10, R4 ; /* 0x0000000a0604722b */
/* 0x001e140000000004 */
/*0420*/ FFMA R0, RZ, c[0x0][0x17c], R5 ; /* 0x00005f00ff007a23 */
/* 0x001fca0000000005 */
/*0430*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0440*/ @P0 BRA P1, 0x4b0 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0450*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff067624 */
/* 0x000fe200078e00ff */
/*0460*/ MOV R0, 0x490 ; /* 0x0000049000007802 */
/* 0x000fe20000000f00 */
/*0470*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff077624 */
/* 0x000fe400078e00ff */
/*0480*/ CALL.REL.NOINC 0x4e0 ; /* 0x0000005000007944 */
/* 0x000fea0003c00000 */
/*0490*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0006 */
/*04a0*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0007 */
/*04b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04c0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b04 */
/*04d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04e0*/ FSETP.GEU.AND P0, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f0e200 */
/*04f0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0d7424 */
/* 0x000fe200078e00ff */
/*0500*/ LOP3.LUT R4, R7, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff07047812 */
/* 0x000fe200078ec0ff */
/*0510*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*0520*/ FSETP.GEU.AND P2, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f4e200 */
/*0530*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0008 */
/*0540*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0550*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0006 */
/*0560*/ LOP3.LUT R12, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090c7812 */
/* 0x000fe200078ec0ff */
/*0570*/ BSSY B1, 0xa80 ; /* 0x0000050000017945 */
/* 0x000fe20003800000 */
/*0580*/ LOP3.LUT R15, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070f7812 */
/* 0x000fc600078ec0ff */
/*0590*/ @!P0 DMUL R4, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006048828 */
/* 0x000e220000000000 */
/*05a0*/ ISETP.GE.U32.AND P1, PT, R12, R15, PT ; /* 0x0000000f0c00720c */
/* 0x000fc60003f26070 */
/*05b0*/ @!P2 LOP3.LUT R11, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070ba812 */
/* 0x000fe200078ec0ff */
/*05c0*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*05d0*/ MUFU.RCP64H R17, R5 ; /* 0x0000000500117308 */
/* 0x001e240000001800 */
/*05e0*/ @!P2 ISETP.GE.U32.AND P3, PT, R12, R11, PT ; /* 0x0000000b0c00a20c */
/* 0x000fe40003f66070 */
/*05f0*/ SEL R11, R13.reuse, 0x63400000, !P1 ; /* 0x634000000d0b7807 */
/* 0x040fe40004800000 */
/*0600*/ @!P2 SEL R21, R13, 0x63400000, !P3 ; /* 0x634000000d15a807 */
/* 0x000fe40005800000 */
/*0610*/ LOP3.LUT R11, R11, 0x800fffff, R9, 0xf8, !PT ; /* 0x800fffff0b0b7812 */
/* 0x000fc400078ef809 */
/*0620*/ @!P2 LOP3.LUT R21, R21, 0x80000000, R9, 0xf8, !PT ; /* 0x800000001515a812 */
/* 0x000fc800078ef809 */
/*0630*/ @!P2 LOP3.LUT R21, R21, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001515a812 */
/* 0x000fe200078efcff */
/*0640*/ DFMA R18, R16, -R4, 1 ; /* 0x3ff000001012742b */
/* 0x001e0a0000000804 */
/*0650*/ @!P2 DFMA R10, R10, 2, -R20 ; /* 0x400000000a0aa82b */
/* 0x000fc80000000814 */
/*0660*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0670*/ DFMA R18, R16, R18, R16 ; /* 0x000000121012722b */
/* 0x0010640000000010 */
/*0680*/ IMAD.MOV.U32 R16, RZ, RZ, R12 ; /* 0x000000ffff107224 */
/* 0x001fe200078e000c */
/*0690*/ @!P2 LOP3.LUT R16, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b10a812 */
/* 0x000fe200078ec0ff */
/*06a0*/ IMAD.MOV.U32 R17, RZ, RZ, R15 ; /* 0x000000ffff117224 */
/* 0x000fe200078e000f */
/*06b0*/ @!P0 LOP3.LUT R17, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005118812 */
/* 0x000fe200078ec0ff */
/*06c0*/ DFMA R20, R18, -R4, 1 ; /* 0x3ff000001214742b */
/* 0x002e060000000804 */
/*06d0*/ IADD3 R22, R17, -0x1, RZ ; /* 0xffffffff11167810 */
/* 0x000fc60007ffe0ff */
/*06e0*/ DFMA R18, R18, R20, R18 ; /* 0x000000141212722b */
/* 0x0010640000000012 */
/*06f0*/ IADD3 R20, R16, -0x1, RZ ; /* 0xffffffff10147810 */
/* 0x001fc80007ffe0ff */
/*0700*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fe20003f04070 */
/*0710*/ DMUL R14, R18, R10 ; /* 0x0000000a120e7228 */
/* 0x002e060000000000 */
/*0720*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fc60000704470 */
/*0730*/ DFMA R20, R14, -R4, R10 ; /* 0x800000040e14722b */
/* 0x001e0c000000000a */
/*0740*/ DFMA R14, R18, R20, R14 ; /* 0x00000014120e722b */
/* 0x001048000000000e */
/*0750*/ @P0 BRA 0x920 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0760*/ LOP3.LUT R9, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007097812 */
/* 0x003fc800078ec0ff */
/*0770*/ ISETP.GE.U32.AND P0, PT, R12.reuse, R9, PT ; /* 0x000000090c00720c */
/* 0x040fe20003f06070 */
/*0780*/ IMAD.IADD R8, R12, 0x1, -R9 ; /* 0x000000010c087824 */
/* 0x000fc600078e0a09 */
/*0790*/ SEL R13, R13, 0x63400000, !P0 ; /* 0x634000000d0d7807 */
/* 0x000fe40004000000 */
/*07a0*/ IMNMX R8, R8, -0x46a00000, !PT ; /* 0xb960000008087817 */
/* 0x000fc80007800200 */
/*07b0*/ IMNMX R8, R8, 0x46a00000, PT ; /* 0x46a0000008087817 */
/* 0x000fca0003800200 */
/*07c0*/ IMAD.IADD R16, R8, 0x1, -R13 ; /* 0x0000000108107824 */
/* 0x000fe400078e0a0d */
/*07d0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*07e0*/ IADD3 R9, R16, 0x7fe00000, RZ ; /* 0x7fe0000010097810 */
/* 0x000fcc0007ffe0ff */
/*07f0*/ DMUL R12, R14, R8 ; /* 0x000000080e0c7228 */
/* 0x000e140000000000 */
/*0800*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x001fda0003f0c200 */
/*0810*/ @P0 BRA 0xa70 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0820*/ DFMA R4, R14, -R4, R10 ; /* 0x800000040e04722b */
/* 0x000e22000000000a */
/*0830*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd200078e00ff */
/*0840*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*0850*/ LOP3.LUT R7, R5, 0x80000000, R7, 0x48, !PT ; /* 0x8000000005077812 */
/* 0x000fc800078e4807 */
/*0860*/ LOP3.LUT R9, R7, R9, RZ, 0xfc, !PT ; /* 0x0000000907097212 */
/* 0x000fce00078efcff */
/*0870*/ @!P0 BRA 0xa70 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0880*/ IMAD.MOV R5, RZ, RZ, -R16 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a10 */
/*0890*/ DMUL.RP R8, R14, R8 ; /* 0x000000080e087228 */
/* 0x000e220000008000 */
/*08a0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*08b0*/ DFMA R4, R12, -R4, R14 ; /* 0x800000040c04722b */
/* 0x000e46000000000e */
/*08c0*/ LOP3.LUT R7, R9, R7, RZ, 0x3c, !PT ; /* 0x0000000709077212 */
/* 0x001fc600078e3cff */
/*08d0*/ IADD3 R4, -R16, -0x43300000, RZ ; /* 0xbcd0000010047810 */
/* 0x002fc80007ffe1ff */
/*08e0*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*08f0*/ FSEL R12, R8, R12, !P0 ; /* 0x0000000c080c7208 */
/* 0x000fe40004000000 */
/*0900*/ FSEL R13, R7, R13, !P0 ; /* 0x0000000d070d7208 */
/* 0x000fe20004000000 */
/*0910*/ BRA 0xa70 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0920*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x003e1c0003f08000 */
/*0930*/ @P0 BRA 0xa50 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0940*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e1c0003f08000 */
/*0950*/ @P0 BRA 0xa20 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0960*/ ISETP.NE.AND P0, PT, R16, R17, PT ; /* 0x000000111000720c */
/* 0x000fe20003f05270 */
/*0970*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0980*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0990*/ @!P0 BRA 0xa70 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*09a0*/ ISETP.NE.AND P0, PT, R16, 0x7ff00000, PT ; /* 0x7ff000001000780c */
/* 0x000fe40003f05270 */
/*09b0*/ LOP3.LUT R13, R9, 0x80000000, R7, 0x48, !PT ; /* 0x80000000090d7812 */
/* 0x000fe400078e4807 */
/*09c0*/ ISETP.EQ.OR P0, PT, R17, RZ, !P0 ; /* 0x000000ff1100720c */
/* 0x000fda0004702670 */
/*09d0*/ @P0 LOP3.LUT R4, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d040812 */
/* 0x000fe200078efcff */
/*09e0*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*09f0*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*0a00*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R4 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0004 */
/*0a10*/ BRA 0xa70 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0a20*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*0a30*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0006 */
/*0a40*/ BRA 0xa70 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0a50*/ LOP3.LUT R13, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090d7812 */
/* 0x000fe200078efcff */
/*0a60*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0008 */
/*0a70*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a80*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0a90*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc400078e00ff */
/*0aa0*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000c */
/*0ab0*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000d */
/*0ac0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff53004007950 */
/* 0x000fec0003c3ffff */
/*0ad0*/ BRA 0xad0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void derive(double *data, double *out, int stride, int gsize, double dx){
int gid = getGid3d3d();
if (gid < gsize){
if (gid + stride < gsize){
out[gid] = (data[gid+stride] - data[gid])/dx;
}
else{
out[gid] = data[gid]/dx;
}
}
} | .file "tmpxft_000b854d_00000000-6_derive.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10getGid3d3dv
.type _Z10getGid3d3dv, @function
_Z10getGid3d3dv:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10getGid3d3dv, .-_Z10getGid3d3dv
.globl _Z30__device_stub__Z6derivePdS_iidPdS_iid
.type _Z30__device_stub__Z6derivePdS_iidPdS_iid, @function
_Z30__device_stub__Z6derivePdS_iidPdS_iid:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6derivePdS_iid(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z30__device_stub__Z6derivePdS_iidPdS_iid, .-_Z30__device_stub__Z6derivePdS_iidPdS_iid
.globl _Z6derivePdS_iid
.type _Z6derivePdS_iid, @function
_Z6derivePdS_iid:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6derivePdS_iidPdS_iid
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z6derivePdS_iid, .-_Z6derivePdS_iid
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6derivePdS_iid"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6derivePdS_iid(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void derive(double *data, double *out, int stride, int gsize, double dx){
int gid = getGid3d3d();
if (gid < gsize){
if (gid + stride < gsize){
out[gid] = (data[gid+stride] - data[gid])/dx;
}
else{
out[gid] = data[gid]/dx;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void derive(double *data, double *out, int stride, int gsize, double dx){
int gid = getGid3d3d();
if (gid < gsize){
if (gid + stride < gsize){
out[gid] = (data[gid+stride] - data[gid])/dx;
}
else{
out[gid] = data[gid]/dx;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void derive(double *data, double *out, int stride, int gsize, double dx){
int gid = getGid3d3d();
if (gid < gsize){
if (gid + stride < gsize){
out[gid] = (data[gid+stride] - data[gid])/dx;
}
else{
out[gid] = data[gid]/dx;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6derivePdS_iid
.globl _Z6derivePdS_iid
.p2align 8
.type _Z6derivePdS_iid,@function
_Z6derivePdS_iid:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b64 s[6:7], s[0:1], 0x2c
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s13
s_cmp_lt_u32 s13, s2
s_cselect_b32 s2, 12, 18
v_mov_b32_e32 v1, s2
s_and_b32 s2, s7, 0xffff
global_load_u16 v5, v1, s[4:5]
v_bfe_u32 v1, v0, 20, 10
s_load_b32 s4, s[0:1], 0x14
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s3, s2, v[1:2]
v_bfe_u32 v1, v0, 10, 10
s_lshr_b32 s2, s6, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, v2, s2, v[1:2]
v_and_b32_e32 v2, 0x3ff, v0
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, v5, v[2:3]
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b32 s5, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s4, v4
s_and_saveexec_b32 s4, vcc_lo
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_3
v_lshlrev_b64 v[2:3], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b64 v[2:3], v[2:3], off
.LBB0_3:
s_and_not1_saveexec_b32 s4, s4
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[4:5]
v_lshlrev_b64 v[4:5], 3, v[0:1]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_clause 0x1
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], -v[4:5]
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt vmcnt(0) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[4:5], null, s[2:3], s[2:3], v[2:3]
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_div_scale_f64 v[8:9], vcc_lo, v[2:3], s[2:3], v[2:3]
v_mul_f64 v[10:11], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_div_fixup_f64 v[2:3], v[4:5], s[2:3], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6derivePdS_iid
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6derivePdS_iid, .Lfunc_end0-_Z6derivePdS_iid
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6derivePdS_iid
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6derivePdS_iid.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void derive(double *data, double *out, int stride, int gsize, double dx){
int gid = getGid3d3d();
if (gid < gsize){
if (gid + stride < gsize){
out[gid] = (data[gid+stride] - data[gid])/dx;
}
else{
out[gid] = data[gid]/dx;
}
}
} | .text
.file "derive.hip"
.globl _Z21__device_stub__derivePdS_iid # -- Begin function _Z21__device_stub__derivePdS_iid
.p2align 4, 0x90
.type _Z21__device_stub__derivePdS_iid,@function
_Z21__device_stub__derivePdS_iid: # @_Z21__device_stub__derivePdS_iid
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movsd %xmm0, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6derivePdS_iid, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__derivePdS_iid, .Lfunc_end0-_Z21__device_stub__derivePdS_iid
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6derivePdS_iid, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6derivePdS_iid,@object # @_Z6derivePdS_iid
.section .rodata,"a",@progbits
.globl _Z6derivePdS_iid
.p2align 3, 0x0
_Z6derivePdS_iid:
.quad _Z21__device_stub__derivePdS_iid
.size _Z6derivePdS_iid, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6derivePdS_iid"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__derivePdS_iid
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6derivePdS_iid
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6derivePdS_iid
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e280000002700 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R7, SR_TID.Z ; /* 0x0000000000077919 */
/* 0x000ea80000002300 */
/*0050*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000ee80000002200 */
/*0060*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000f220000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x10], R3 ; /* 0x0000040000007a24 */
/* 0x001fc800078e0203 */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*0090*/ IMAD R0, R0, c[0x0][0x8], R7 ; /* 0x0000020000007a24 */
/* 0x004fc800078e0207 */
/*00a0*/ IMAD R0, R0, c[0x0][0x4], R9 ; /* 0x0000010000007a24 */
/* 0x008fc800078e0209 */
/*00b0*/ IMAD R0, R0, c[0x0][0x0], R11 ; /* 0x0000000000007a24 */
/* 0x010fca00078e020b */
/*00c0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06270 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R6, R0, c[0x0][0x170], RZ ; /* 0x00005c0000067a10 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe200078e00ff */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0110*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x174], PT ; /* 0x00005d0006007a0c */
/* 0x000fe20003f06270 */
/*0120*/ IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0207 */
/*0130*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fd000078e0207 */
/*0140*/ @!P0 BRA 0x300 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0150*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*0160*/ MUFU.RCP64H R7, c[0x0][0x17c] ; /* 0x00005f0000077b08 */
/* 0x000e220000001800 */
/*0170*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0a7624 */
/* 0x000fe200078e00ff */
/*0180*/ BSSY B0, 0x2e0 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0190*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff0b7624 */
/* 0x000fe400078e00ff */
/*01a0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fcc00078e00ff */
/*01b0*/ DFMA R8, R6, -R10, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c000000080a */
/*01c0*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*01d0*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*01e0*/ DFMA R6, R8, -R10, 1 ; /* 0x3ff000000806742b */
/* 0x001e0c000000080a */
/*01f0*/ DFMA R6, R8, R6, R8 ; /* 0x000000060806722b */
/* 0x001e8c0000000008 */
/*0200*/ DMUL R8, R4, R6 ; /* 0x0000000604087228 */
/* 0x004e220000000000 */
/*0210*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x000fca0003f2e200 */
/*0220*/ DFMA R10, R8, -c[0x0][0x178], R4 ; /* 0x80005e00080a7a2b */
/* 0x001e0c0000000004 */
/*0230*/ DFMA R6, R6, R10, R8 ; /* 0x0000000a0606722b */
/* 0x001e140000000008 */
/*0240*/ FFMA R0, RZ, c[0x0][0x17c], R7 ; /* 0x00005f00ff007a23 */
/* 0x001fca0000000007 */
/*0250*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0260*/ @P0 BRA P1, 0x2d0 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0270*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0280*/ MOV R0, 0x2d0 ; /* 0x000002d000007802 */
/* 0x000fe20000000f00 */
/*0290*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0005 */
/*02a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff067624 */
/* 0x000fe400078e00ff */
/*02b0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff077624 */
/* 0x000fe400078e00ff */
/*02c0*/ CALL.REL.NOINC 0x4e0 ; /* 0x0000021000007944 */
/* 0x000fea0003c00000 */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02e0*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe2000c101b04 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0310*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000eaa000c1e1b00 */
/*0320*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*0330*/ MUFU.RCP64H R9, c[0x0][0x17c] ; /* 0x00005f0000097b08 */
/* 0x000e220000001800 */
/*0340*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0a7624 */
/* 0x000fe200078e00ff */
/*0350*/ BSSY B0, 0x4c0 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*0360*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff0b7624 */
/* 0x000fc400078e00ff */
/*0370*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fcc00078e00ff */
/*0380*/ DFMA R12, R8, -R10, 1 ; /* 0x3ff00000080c742b */
/* 0x001e0c000000080a */
/*0390*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*03a0*/ DFMA R12, R8, R12, R8 ; /* 0x0000000c080c722b */
/* 0x001e0c0000000008 */
/*03b0*/ DFMA R10, R12, -R10, 1 ; /* 0x3ff000000c0a742b */
/* 0x001e0c000000080a */
/*03c0*/ DFMA R10, R12, R10, R12 ; /* 0x0000000a0c0a722b */
/* 0x001fc8000000000c */
/*03d0*/ DADD R8, -R4, R6 ; /* 0x0000000004087229 */
/* 0x004e0c0000000106 */
/*03e0*/ DMUL R4, R8, R10 ; /* 0x0000000a08047228 */
/* 0x001e080000000000 */
/*03f0*/ FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT ; /* 0x036000000900780b */
/* 0x000fe40003f2e200 */
/*0400*/ DFMA R6, R4, -c[0x0][0x178], R8 ; /* 0x80005e0004067a2b */
/* 0x001e0c0000000008 */
/*0410*/ DFMA R4, R6, R10, R4 ; /* 0x0000000a0604722b */
/* 0x001e140000000004 */
/*0420*/ FFMA R0, RZ, c[0x0][0x17c], R5 ; /* 0x00005f00ff007a23 */
/* 0x001fca0000000005 */
/*0430*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0440*/ @P0 BRA P1, 0x4b0 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0450*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff067624 */
/* 0x000fe200078e00ff */
/*0460*/ MOV R0, 0x490 ; /* 0x0000049000007802 */
/* 0x000fe20000000f00 */
/*0470*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff077624 */
/* 0x000fe400078e00ff */
/*0480*/ CALL.REL.NOINC 0x4e0 ; /* 0x0000005000007944 */
/* 0x000fea0003c00000 */
/*0490*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0006 */
/*04a0*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0007 */
/*04b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04c0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b04 */
/*04d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04e0*/ FSETP.GEU.AND P0, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f0e200 */
/*04f0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0d7424 */
/* 0x000fe200078e00ff */
/*0500*/ LOP3.LUT R4, R7, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff07047812 */
/* 0x000fe200078ec0ff */
/*0510*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*0520*/ FSETP.GEU.AND P2, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f4e200 */
/*0530*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0008 */
/*0540*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0550*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0006 */
/*0560*/ LOP3.LUT R12, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090c7812 */
/* 0x000fe200078ec0ff */
/*0570*/ BSSY B1, 0xa80 ; /* 0x0000050000017945 */
/* 0x000fe20003800000 */
/*0580*/ LOP3.LUT R15, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070f7812 */
/* 0x000fc600078ec0ff */
/*0590*/ @!P0 DMUL R4, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006048828 */
/* 0x000e220000000000 */
/*05a0*/ ISETP.GE.U32.AND P1, PT, R12, R15, PT ; /* 0x0000000f0c00720c */
/* 0x000fc60003f26070 */
/*05b0*/ @!P2 LOP3.LUT R11, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070ba812 */
/* 0x000fe200078ec0ff */
/*05c0*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*05d0*/ MUFU.RCP64H R17, R5 ; /* 0x0000000500117308 */
/* 0x001e240000001800 */
/*05e0*/ @!P2 ISETP.GE.U32.AND P3, PT, R12, R11, PT ; /* 0x0000000b0c00a20c */
/* 0x000fe40003f66070 */
/*05f0*/ SEL R11, R13.reuse, 0x63400000, !P1 ; /* 0x634000000d0b7807 */
/* 0x040fe40004800000 */
/*0600*/ @!P2 SEL R21, R13, 0x63400000, !P3 ; /* 0x634000000d15a807 */
/* 0x000fe40005800000 */
/*0610*/ LOP3.LUT R11, R11, 0x800fffff, R9, 0xf8, !PT ; /* 0x800fffff0b0b7812 */
/* 0x000fc400078ef809 */
/*0620*/ @!P2 LOP3.LUT R21, R21, 0x80000000, R9, 0xf8, !PT ; /* 0x800000001515a812 */
/* 0x000fc800078ef809 */
/*0630*/ @!P2 LOP3.LUT R21, R21, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001515a812 */
/* 0x000fe200078efcff */
/*0640*/ DFMA R18, R16, -R4, 1 ; /* 0x3ff000001012742b */
/* 0x001e0a0000000804 */
/*0650*/ @!P2 DFMA R10, R10, 2, -R20 ; /* 0x400000000a0aa82b */
/* 0x000fc80000000814 */
/*0660*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0670*/ DFMA R18, R16, R18, R16 ; /* 0x000000121012722b */
/* 0x0010640000000010 */
/*0680*/ IMAD.MOV.U32 R16, RZ, RZ, R12 ; /* 0x000000ffff107224 */
/* 0x001fe200078e000c */
/*0690*/ @!P2 LOP3.LUT R16, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b10a812 */
/* 0x000fe200078ec0ff */
/*06a0*/ IMAD.MOV.U32 R17, RZ, RZ, R15 ; /* 0x000000ffff117224 */
/* 0x000fe200078e000f */
/*06b0*/ @!P0 LOP3.LUT R17, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005118812 */
/* 0x000fe200078ec0ff */
/*06c0*/ DFMA R20, R18, -R4, 1 ; /* 0x3ff000001214742b */
/* 0x002e060000000804 */
/*06d0*/ IADD3 R22, R17, -0x1, RZ ; /* 0xffffffff11167810 */
/* 0x000fc60007ffe0ff */
/*06e0*/ DFMA R18, R18, R20, R18 ; /* 0x000000141212722b */
/* 0x0010640000000012 */
/*06f0*/ IADD3 R20, R16, -0x1, RZ ; /* 0xffffffff10147810 */
/* 0x001fc80007ffe0ff */
/*0700*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fe20003f04070 */
/*0710*/ DMUL R14, R18, R10 ; /* 0x0000000a120e7228 */
/* 0x002e060000000000 */
/*0720*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fc60000704470 */
/*0730*/ DFMA R20, R14, -R4, R10 ; /* 0x800000040e14722b */
/* 0x001e0c000000000a */
/*0740*/ DFMA R14, R18, R20, R14 ; /* 0x00000014120e722b */
/* 0x001048000000000e */
/*0750*/ @P0 BRA 0x920 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0760*/ LOP3.LUT R9, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007097812 */
/* 0x003fc800078ec0ff */
/*0770*/ ISETP.GE.U32.AND P0, PT, R12.reuse, R9, PT ; /* 0x000000090c00720c */
/* 0x040fe20003f06070 */
/*0780*/ IMAD.IADD R8, R12, 0x1, -R9 ; /* 0x000000010c087824 */
/* 0x000fc600078e0a09 */
/*0790*/ SEL R13, R13, 0x63400000, !P0 ; /* 0x634000000d0d7807 */
/* 0x000fe40004000000 */
/*07a0*/ IMNMX R8, R8, -0x46a00000, !PT ; /* 0xb960000008087817 */
/* 0x000fc80007800200 */
/*07b0*/ IMNMX R8, R8, 0x46a00000, PT ; /* 0x46a0000008087817 */
/* 0x000fca0003800200 */
/*07c0*/ IMAD.IADD R16, R8, 0x1, -R13 ; /* 0x0000000108107824 */
/* 0x000fe400078e0a0d */
/*07d0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*07e0*/ IADD3 R9, R16, 0x7fe00000, RZ ; /* 0x7fe0000010097810 */
/* 0x000fcc0007ffe0ff */
/*07f0*/ DMUL R12, R14, R8 ; /* 0x000000080e0c7228 */
/* 0x000e140000000000 */
/*0800*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x001fda0003f0c200 */
/*0810*/ @P0 BRA 0xa70 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0820*/ DFMA R4, R14, -R4, R10 ; /* 0x800000040e04722b */
/* 0x000e22000000000a */
/*0830*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd200078e00ff */
/*0840*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*0850*/ LOP3.LUT R7, R5, 0x80000000, R7, 0x48, !PT ; /* 0x8000000005077812 */
/* 0x000fc800078e4807 */
/*0860*/ LOP3.LUT R9, R7, R9, RZ, 0xfc, !PT ; /* 0x0000000907097212 */
/* 0x000fce00078efcff */
/*0870*/ @!P0 BRA 0xa70 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0880*/ IMAD.MOV R5, RZ, RZ, -R16 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a10 */
/*0890*/ DMUL.RP R8, R14, R8 ; /* 0x000000080e087228 */
/* 0x000e220000008000 */
/*08a0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*08b0*/ DFMA R4, R12, -R4, R14 ; /* 0x800000040c04722b */
/* 0x000e46000000000e */
/*08c0*/ LOP3.LUT R7, R9, R7, RZ, 0x3c, !PT ; /* 0x0000000709077212 */
/* 0x001fc600078e3cff */
/*08d0*/ IADD3 R4, -R16, -0x43300000, RZ ; /* 0xbcd0000010047810 */
/* 0x002fc80007ffe1ff */
/*08e0*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*08f0*/ FSEL R12, R8, R12, !P0 ; /* 0x0000000c080c7208 */
/* 0x000fe40004000000 */
/*0900*/ FSEL R13, R7, R13, !P0 ; /* 0x0000000d070d7208 */
/* 0x000fe20004000000 */
/*0910*/ BRA 0xa70 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0920*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x003e1c0003f08000 */
/*0930*/ @P0 BRA 0xa50 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0940*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e1c0003f08000 */
/*0950*/ @P0 BRA 0xa20 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0960*/ ISETP.NE.AND P0, PT, R16, R17, PT ; /* 0x000000111000720c */
/* 0x000fe20003f05270 */
/*0970*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0980*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0990*/ @!P0 BRA 0xa70 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*09a0*/ ISETP.NE.AND P0, PT, R16, 0x7ff00000, PT ; /* 0x7ff000001000780c */
/* 0x000fe40003f05270 */
/*09b0*/ LOP3.LUT R13, R9, 0x80000000, R7, 0x48, !PT ; /* 0x80000000090d7812 */
/* 0x000fe400078e4807 */
/*09c0*/ ISETP.EQ.OR P0, PT, R17, RZ, !P0 ; /* 0x000000ff1100720c */
/* 0x000fda0004702670 */
/*09d0*/ @P0 LOP3.LUT R4, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d040812 */
/* 0x000fe200078efcff */
/*09e0*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*09f0*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*0a00*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R4 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0004 */
/*0a10*/ BRA 0xa70 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0a20*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*0a30*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0006 */
/*0a40*/ BRA 0xa70 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0a50*/ LOP3.LUT R13, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090d7812 */
/* 0x000fe200078efcff */
/*0a60*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0008 */
/*0a70*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a80*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0a90*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc400078e00ff */
/*0aa0*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000c */
/*0ab0*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000d */
/*0ac0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff53004007950 */
/* 0x000fec0003c3ffff */
/*0ad0*/ BRA 0xad0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6derivePdS_iid
.globl _Z6derivePdS_iid
.p2align 8
.type _Z6derivePdS_iid,@function
_Z6derivePdS_iid:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b64 s[6:7], s[0:1], 0x2c
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s13
s_cmp_lt_u32 s13, s2
s_cselect_b32 s2, 12, 18
v_mov_b32_e32 v1, s2
s_and_b32 s2, s7, 0xffff
global_load_u16 v5, v1, s[4:5]
v_bfe_u32 v1, v0, 20, 10
s_load_b32 s4, s[0:1], 0x14
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s3, s2, v[1:2]
v_bfe_u32 v1, v0, 10, 10
s_lshr_b32 s2, s6, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, v2, s2, v[1:2]
v_and_b32_e32 v2, 0x3ff, v0
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, v5, v[2:3]
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b32 s5, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s4, v4
s_and_saveexec_b32 s4, vcc_lo
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_3
v_lshlrev_b64 v[2:3], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b64 v[2:3], v[2:3], off
.LBB0_3:
s_and_not1_saveexec_b32 s4, s4
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[4:5]
v_lshlrev_b64 v[4:5], 3, v[0:1]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_clause 0x1
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], -v[4:5]
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt vmcnt(0) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[4:5], null, s[2:3], s[2:3], v[2:3]
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_div_scale_f64 v[8:9], vcc_lo, v[2:3], s[2:3], v[2:3]
v_mul_f64 v[10:11], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_div_fixup_f64 v[2:3], v[4:5], s[2:3], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6derivePdS_iid
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6derivePdS_iid, .Lfunc_end0-_Z6derivePdS_iid
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6derivePdS_iid
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6derivePdS_iid.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b854d_00000000-6_derive.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10getGid3d3dv
.type _Z10getGid3d3dv, @function
_Z10getGid3d3dv:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10getGid3d3dv, .-_Z10getGid3d3dv
.globl _Z30__device_stub__Z6derivePdS_iidPdS_iid
.type _Z30__device_stub__Z6derivePdS_iidPdS_iid, @function
_Z30__device_stub__Z6derivePdS_iidPdS_iid:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6derivePdS_iid(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z30__device_stub__Z6derivePdS_iidPdS_iid, .-_Z30__device_stub__Z6derivePdS_iidPdS_iid
.globl _Z6derivePdS_iid
.type _Z6derivePdS_iid, @function
_Z6derivePdS_iid:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6derivePdS_iidPdS_iid
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z6derivePdS_iid, .-_Z6derivePdS_iid
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6derivePdS_iid"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6derivePdS_iid(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "derive.hip"
.globl _Z21__device_stub__derivePdS_iid # -- Begin function _Z21__device_stub__derivePdS_iid
.p2align 4, 0x90
.type _Z21__device_stub__derivePdS_iid,@function
_Z21__device_stub__derivePdS_iid: # @_Z21__device_stub__derivePdS_iid
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movsd %xmm0, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6derivePdS_iid, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__derivePdS_iid, .Lfunc_end0-_Z21__device_stub__derivePdS_iid
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6derivePdS_iid, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6derivePdS_iid,@object # @_Z6derivePdS_iid
.section .rodata,"a",@progbits
.globl _Z6derivePdS_iid
.p2align 3, 0x0
_Z6derivePdS_iid:
.quad _Z21__device_stub__derivePdS_iid
.size _Z6derivePdS_iid, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6derivePdS_iid"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__derivePdS_iid
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6derivePdS_iid
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<chrono>
#include<stdio.h>
#include<iostream>
#include<math.h>
#include<string>
#include<sstream>
#include<fstream>
#include<vector>
#include<malloc.h>
#define LENGTH_DICTIONARY 57664
#define LENGTH_DOCS 10000
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
using namespace std;
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void cosine_similarity(int *sparsemat, double *cosinematrix, int dicsize,int docsize)
{
double mul = 0.0, d_a = 0.0, d_b = 0.0 ;
int doc1index = blockIdx.x;
int doc2index = threadIdx.x;
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(doc1index == doc2index)
cosinematrix[index] = -1;
else {
int *A = &sparsemat[doc1index*dicsize];
int *B = &sparsemat[doc2index*dicsize] ;
for(unsigned int i = 0; i < dicsize; ++i)
{
mul += A[i] * B[i] ;
d_a += A[i] * A[i] ;
d_b += B[i] * B[i] ;
}
cosinematrix[index] = mul / (sqrt(d_a) * sqrt(d_b)) ;
}
}
void getTokens(string line,vector<string>&tokens)
{
istringstream tokenStream(line);
string token;
while (getline(tokenStream, token,' '))
{
tokens.push_back(token);
}
}
void printVector(vector<string> v)
{
cout<<"size: "<<v.size()<<endl;
for(int i=0;i<v.size();i++)
{
cout<<v[i]<<" ";
}
cout<<endl;
}
void feedTheMatrix(vector<string> tokens, int * mat)
{
for(int i=0;i<LENGTH_DICTIONARY;i++)
{
mat[i] = 0;
//cout<<i<<" "<<LENGTH_DICTIONARY<<endl;
}
for(int i=1;i<tokens.size();i++)
{
mat[stoi(tokens[i])] +=1;
}
}
void printTheMatrix(int *mat,int row,int col)
{
for(int i=0;i<row;i++) {
for(int j=0;j<col;j++)
cout<<mat[(i*LENGTH_DICTIONARY)+j]<<" ";
cout<<endl;
}
}
void printTheCosineMatrix(double *mat,int row,int col)
{
for(int i=0;i<row;i++) {
for(int j=0;j<col;j++)
cout<<mat[(i*LENGTH_DOCS)+j]<<" ";
cout<<endl;
}
}
int findIndexofHighestSimilarity(double *cosinematrix)
{
int index = 0;
double maxvalue = -1;
for(int i=0;i<LENGTH_DOCS;i++)
{
if(cosinematrix[i] > maxvalue)
{
maxvalue = cosinematrix[i];
index = i;
}
}
return index;
}
int main()
{
int *sparsemat;
int *d_sparsemat;
sparsemat = (int *)malloc(LENGTH_DOCS*LENGTH_DICTIONARY*sizeof(int));
gpuErrchk( cudaMalloc((void **)&d_sparsemat,LENGTH_DOCS*LENGTH_DICTIONARY*sizeof(int)));
//get the contents of file
ifstream inFile;
inFile.open("./sample10000.txt");
if (!inFile) {
cerr << "Unable to open file sample100.txt";
// exit(1); // call system to stop
return -1;
}
string line;
int linenum = 0;
while (getline(inFile,line)) {
//cout<<line<<endl;
vector<string> tokens;
getTokens(line,tokens);
//cout<<linenum<<" "<<LENGTH_DOCS<<endl;
//printVector(tokens);
feedTheMatrix(tokens,&(sparsemat[linenum*LENGTH_DICTIONARY]));
linenum++;
}
inFile.close();
//printTheMatrix(sparsemat,LENGTH_DOCS,LENGTH_DICTIONARY);
//create a docs*docs matrix
double *cosinematrix;
double *d_cosinematrix;
cosinematrix = (double *)malloc(LENGTH_DOCS*LENGTH_DOCS*sizeof(double));
gpuErrchk(cudaMalloc((void **)&d_cosinematrix,LENGTH_DOCS*LENGTH_DOCS*sizeof(double)));
gpuErrchk(cudaMemcpy(d_sparsemat,sparsemat,LENGTH_DOCS*LENGTH_DICTIONARY*sizeof(int),cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(d_cosinematrix,cosinematrix,LENGTH_DOCS*LENGTH_DOCS*sizeof(double),cudaMemcpyHostToDevice));
chrono::time_point<chrono::system_clock> start = chrono::system_clock::now();
cosine_similarity<<<LENGTH_DOCS,LENGTH_DOCS>>>(d_sparsemat,d_cosinematrix,LENGTH_DICTIONARY,LENGTH_DOCS);
/*
for(int i=0;i<LENGTH_DOCS;i++)
{
for(int j =0;j<LENGTH_DOCS;j++)
{
if(i==j)
{
//obviously same docs have highest similarity so equating them to -1
cosinematrix[i][j] = -1;
}
else
{
cosinematrix[i][j] = cosine_similarity(sparsemat[i],sparsemat[j],LENGTH_DICTIONARY);
}
}
}
*/
gpuErrchk( cudaDeviceSynchronize());
gpuErrchk( cudaMemcpy(cosinematrix,d_cosinematrix,LENGTH_DOCS*LENGTH_DOCS*sizeof(double),cudaMemcpyDeviceToHost));
chrono::time_point<chrono::system_clock> end = chrono::system_clock::now();
chrono::duration<double> elapsed_sec = end - start;
double count_sec = elapsed_sec.count();
cout<<"Time(cosine_similarity_calculations/sec): "<<(LENGTH_DOCS*LENGTH_DOCS)/count_sec<<endl;
//printTheCosineMatrix(cosinematrix,LENGTH_DOCS,LENGTH_DOCS);
//sort the matrix
for(int i=0;i<LENGTH_DOCS;i++)
{
int similardoc = findIndexofHighestSimilarity(&cosinematrix[i*LENGTH_DOCS]);
cout<<"doc "<<i<<" is similart to doc "<<similardoc<<endl;
}
free(sparsemat);
free(cosinematrix);
cudaFree(d_sparsemat);
cudaFree(d_cosinematrix);
} | #include <hip/hip_runtime.h>
#include<chrono>
#include<stdio.h>
#include<iostream>
#include<math.h>
#include<string>
#include<sstream>
#include<fstream>
#include<vector>
#include<malloc.h>
#define LENGTH_DICTIONARY 57664
#define LENGTH_DOCS 10000
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
using namespace std;
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void cosine_similarity(int *sparsemat, double *cosinematrix, int dicsize,int docsize)
{
double mul = 0.0, d_a = 0.0, d_b = 0.0 ;
int doc1index = blockIdx.x;
int doc2index = threadIdx.x;
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(doc1index == doc2index)
cosinematrix[index] = -1;
else {
int *A = &sparsemat[doc1index*dicsize];
int *B = &sparsemat[doc2index*dicsize] ;
for(unsigned int i = 0; i < dicsize; ++i)
{
mul += A[i] * B[i] ;
d_a += A[i] * A[i] ;
d_b += B[i] * B[i] ;
}
cosinematrix[index] = mul / (sqrt(d_a) * sqrt(d_b)) ;
}
}
void getTokens(string line,vector<string>&tokens)
{
istringstream tokenStream(line);
string token;
while (getline(tokenStream, token,' '))
{
tokens.push_back(token);
}
}
void printVector(vector<string> v)
{
cout<<"size: "<<v.size()<<endl;
for(int i=0;i<v.size();i++)
{
cout<<v[i]<<" ";
}
cout<<endl;
}
void feedTheMatrix(vector<string> tokens, int * mat)
{
for(int i=0;i<LENGTH_DICTIONARY;i++)
{
mat[i] = 0;
//cout<<i<<" "<<LENGTH_DICTIONARY<<endl;
}
for(int i=1;i<tokens.size();i++)
{
mat[stoi(tokens[i])] +=1;
}
}
void printTheMatrix(int *mat,int row,int col)
{
for(int i=0;i<row;i++) {
for(int j=0;j<col;j++)
cout<<mat[(i*LENGTH_DICTIONARY)+j]<<" ";
cout<<endl;
}
}
void printTheCosineMatrix(double *mat,int row,int col)
{
for(int i=0;i<row;i++) {
for(int j=0;j<col;j++)
cout<<mat[(i*LENGTH_DOCS)+j]<<" ";
cout<<endl;
}
}
int findIndexofHighestSimilarity(double *cosinematrix)
{
int index = 0;
double maxvalue = -1;
for(int i=0;i<LENGTH_DOCS;i++)
{
if(cosinematrix[i] > maxvalue)
{
maxvalue = cosinematrix[i];
index = i;
}
}
return index;
}
int main()
{
int *sparsemat;
int *d_sparsemat;
sparsemat = (int *)malloc(LENGTH_DOCS*LENGTH_DICTIONARY*sizeof(int));
gpuErrchk( hipMalloc((void **)&d_sparsemat,LENGTH_DOCS*LENGTH_DICTIONARY*sizeof(int)));
//get the contents of file
ifstream inFile;
inFile.open("./sample10000.txt");
if (!inFile) {
cerr << "Unable to open file sample100.txt";
// exit(1); // call system to stop
return -1;
}
string line;
int linenum = 0;
while (getline(inFile,line)) {
//cout<<line<<endl;
vector<string> tokens;
getTokens(line,tokens);
//cout<<linenum<<" "<<LENGTH_DOCS<<endl;
//printVector(tokens);
feedTheMatrix(tokens,&(sparsemat[linenum*LENGTH_DICTIONARY]));
linenum++;
}
inFile.close();
//printTheMatrix(sparsemat,LENGTH_DOCS,LENGTH_DICTIONARY);
//create a docs*docs matrix
double *cosinematrix;
double *d_cosinematrix;
cosinematrix = (double *)malloc(LENGTH_DOCS*LENGTH_DOCS*sizeof(double));
gpuErrchk(hipMalloc((void **)&d_cosinematrix,LENGTH_DOCS*LENGTH_DOCS*sizeof(double)));
gpuErrchk(hipMemcpy(d_sparsemat,sparsemat,LENGTH_DOCS*LENGTH_DICTIONARY*sizeof(int),hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(d_cosinematrix,cosinematrix,LENGTH_DOCS*LENGTH_DOCS*sizeof(double),hipMemcpyHostToDevice));
chrono::time_point<chrono::system_clock> start = chrono::system_clock::now();
cosine_similarity<<<LENGTH_DOCS,LENGTH_DOCS>>>(d_sparsemat,d_cosinematrix,LENGTH_DICTIONARY,LENGTH_DOCS);
/*
for(int i=0;i<LENGTH_DOCS;i++)
{
for(int j =0;j<LENGTH_DOCS;j++)
{
if(i==j)
{
//obviously same docs have highest similarity so equating them to -1
cosinematrix[i][j] = -1;
}
else
{
cosinematrix[i][j] = cosine_similarity(sparsemat[i],sparsemat[j],LENGTH_DICTIONARY);
}
}
}
*/
gpuErrchk( hipDeviceSynchronize());
gpuErrchk( hipMemcpy(cosinematrix,d_cosinematrix,LENGTH_DOCS*LENGTH_DOCS*sizeof(double),hipMemcpyDeviceToHost));
chrono::time_point<chrono::system_clock> end = chrono::system_clock::now();
chrono::duration<double> elapsed_sec = end - start;
double count_sec = elapsed_sec.count();
cout<<"Time(cosine_similarity_calculations/sec): "<<(LENGTH_DOCS*LENGTH_DOCS)/count_sec<<endl;
//printTheCosineMatrix(cosinematrix,LENGTH_DOCS,LENGTH_DOCS);
//sort the matrix
for(int i=0;i<LENGTH_DOCS;i++)
{
int similardoc = findIndexofHighestSimilarity(&cosinematrix[i*LENGTH_DOCS]);
cout<<"doc "<<i<<" is similart to doc "<<similardoc<<endl;
}
free(sparsemat);
free(cosinematrix);
hipFree(d_sparsemat);
hipFree(d_cosinematrix);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<chrono>
#include<stdio.h>
#include<iostream>
#include<math.h>
#include<string>
#include<sstream>
#include<fstream>
#include<vector>
#include<malloc.h>
#define LENGTH_DICTIONARY 57664
#define LENGTH_DOCS 10000
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
using namespace std;
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void cosine_similarity(int *sparsemat, double *cosinematrix, int dicsize,int docsize)
{
double mul = 0.0, d_a = 0.0, d_b = 0.0 ;
int doc1index = blockIdx.x;
int doc2index = threadIdx.x;
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(doc1index == doc2index)
cosinematrix[index] = -1;
else {
int *A = &sparsemat[doc1index*dicsize];
int *B = &sparsemat[doc2index*dicsize] ;
for(unsigned int i = 0; i < dicsize; ++i)
{
mul += A[i] * B[i] ;
d_a += A[i] * A[i] ;
d_b += B[i] * B[i] ;
}
cosinematrix[index] = mul / (sqrt(d_a) * sqrt(d_b)) ;
}
}
void getTokens(string line,vector<string>&tokens)
{
istringstream tokenStream(line);
string token;
while (getline(tokenStream, token,' '))
{
tokens.push_back(token);
}
}
void printVector(vector<string> v)
{
cout<<"size: "<<v.size()<<endl;
for(int i=0;i<v.size();i++)
{
cout<<v[i]<<" ";
}
cout<<endl;
}
void feedTheMatrix(vector<string> tokens, int * mat)
{
for(int i=0;i<LENGTH_DICTIONARY;i++)
{
mat[i] = 0;
//cout<<i<<" "<<LENGTH_DICTIONARY<<endl;
}
for(int i=1;i<tokens.size();i++)
{
mat[stoi(tokens[i])] +=1;
}
}
void printTheMatrix(int *mat,int row,int col)
{
for(int i=0;i<row;i++) {
for(int j=0;j<col;j++)
cout<<mat[(i*LENGTH_DICTIONARY)+j]<<" ";
cout<<endl;
}
}
void printTheCosineMatrix(double *mat,int row,int col)
{
for(int i=0;i<row;i++) {
for(int j=0;j<col;j++)
cout<<mat[(i*LENGTH_DOCS)+j]<<" ";
cout<<endl;
}
}
int findIndexofHighestSimilarity(double *cosinematrix)
{
int index = 0;
double maxvalue = -1;
for(int i=0;i<LENGTH_DOCS;i++)
{
if(cosinematrix[i] > maxvalue)
{
maxvalue = cosinematrix[i];
index = i;
}
}
return index;
}
int main()
{
int *sparsemat;
int *d_sparsemat;
sparsemat = (int *)malloc(LENGTH_DOCS*LENGTH_DICTIONARY*sizeof(int));
gpuErrchk( hipMalloc((void **)&d_sparsemat,LENGTH_DOCS*LENGTH_DICTIONARY*sizeof(int)));
//get the contents of file
ifstream inFile;
inFile.open("./sample10000.txt");
if (!inFile) {
cerr << "Unable to open file sample100.txt";
// exit(1); // call system to stop
return -1;
}
string line;
int linenum = 0;
while (getline(inFile,line)) {
//cout<<line<<endl;
vector<string> tokens;
getTokens(line,tokens);
//cout<<linenum<<" "<<LENGTH_DOCS<<endl;
//printVector(tokens);
feedTheMatrix(tokens,&(sparsemat[linenum*LENGTH_DICTIONARY]));
linenum++;
}
inFile.close();
//printTheMatrix(sparsemat,LENGTH_DOCS,LENGTH_DICTIONARY);
//create a docs*docs matrix
double *cosinematrix;
double *d_cosinematrix;
cosinematrix = (double *)malloc(LENGTH_DOCS*LENGTH_DOCS*sizeof(double));
gpuErrchk(hipMalloc((void **)&d_cosinematrix,LENGTH_DOCS*LENGTH_DOCS*sizeof(double)));
gpuErrchk(hipMemcpy(d_sparsemat,sparsemat,LENGTH_DOCS*LENGTH_DICTIONARY*sizeof(int),hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(d_cosinematrix,cosinematrix,LENGTH_DOCS*LENGTH_DOCS*sizeof(double),hipMemcpyHostToDevice));
chrono::time_point<chrono::system_clock> start = chrono::system_clock::now();
cosine_similarity<<<LENGTH_DOCS,LENGTH_DOCS>>>(d_sparsemat,d_cosinematrix,LENGTH_DICTIONARY,LENGTH_DOCS);
/*
for(int i=0;i<LENGTH_DOCS;i++)
{
for(int j =0;j<LENGTH_DOCS;j++)
{
if(i==j)
{
//obviously same docs have highest similarity so equating them to -1
cosinematrix[i][j] = -1;
}
else
{
cosinematrix[i][j] = cosine_similarity(sparsemat[i],sparsemat[j],LENGTH_DICTIONARY);
}
}
}
*/
gpuErrchk( hipDeviceSynchronize());
gpuErrchk( hipMemcpy(cosinematrix,d_cosinematrix,LENGTH_DOCS*LENGTH_DOCS*sizeof(double),hipMemcpyDeviceToHost));
chrono::time_point<chrono::system_clock> end = chrono::system_clock::now();
chrono::duration<double> elapsed_sec = end - start;
double count_sec = elapsed_sec.count();
cout<<"Time(cosine_similarity_calculations/sec): "<<(LENGTH_DOCS*LENGTH_DOCS)/count_sec<<endl;
//printTheCosineMatrix(cosinematrix,LENGTH_DOCS,LENGTH_DOCS);
//sort the matrix
for(int i=0;i<LENGTH_DOCS;i++)
{
int similardoc = findIndexofHighestSimilarity(&cosinematrix[i*LENGTH_DOCS]);
cout<<"doc "<<i<<" is similart to doc "<<similardoc<<endl;
}
free(sparsemat);
free(cosinematrix);
hipFree(d_sparsemat);
hipFree(d_cosinematrix);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17cosine_similarityPiPdii
.globl _Z17cosine_similarityPiPdii
.p2align 8
.type _Z17cosine_similarityPiPdii,@function
_Z17cosine_similarityPiPdii:
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0xbff00000
s_mov_b32 s4, exec_lo
v_cmpx_ne_u32_e64 s15, v0
s_cbranch_execz .LBB0_5
s_load_b32 s5, s[0:1], 0x10
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s5, 0
s_cbranch_scc1 .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
v_mul_lo_u32 v3, v0, s5
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_mul_i32 s6, s15, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s7, s6, 31
s_lshl_b64 s[6:7], s[6:7], 2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 2, v[3:4]
v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v6, vcc_lo
v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
s_add_u32 s2, s2, s6
s_addc_u32 s3, s3, s7
.p2align 6
.LBB0_3:
global_load_b32 v9, v[7:8], off
s_load_b32 s6, s[2:3], 0x0
v_add_co_u32 v7, vcc_lo, v7, 4
s_add_i32 s5, s5, -1
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s5, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_lo_u32 v11, v9, s6
v_mul_lo_u32 v13, v9, v9
s_mul_i32 s6, s6, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[9:10], s6
v_cvt_f64_i32_e32 v[11:12], v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[13:14], v13
v_add_f64 v[3:4], v[3:4], v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[1:2], v[1:2], v[11:12]
v_add_f64 v[5:6], v[5:6], v[13:14]
s_cbranch_scc0 .LBB0_3
.LBB0_4:
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[3:4]
v_cmp_gt_f64_e64 s2, 0x10000000, v[5:6]
v_cndmask_b32_e64 v7, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v8, 0, 1, s2
s_and_b32 s3, vcc_lo, exec_lo
v_lshlrev_b32_e32 v7, 8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[3:4], v[3:4], v7
v_cmp_class_f64_e64 vcc_lo, v[3:4], 0x260
v_lshlrev_b32_e32 v8, 8, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ldexp_f64 v[5:6], v[5:6], v8
v_rsq_f64_e32 v[7:8], v[3:4]
v_rsq_f64_e32 v[9:10], v[5:6]
s_waitcnt_depctr 0xfff
v_mul_f64 v[11:12], v[3:4], v[7:8]
v_mul_f64 v[7:8], v[7:8], 0.5
v_mul_f64 v[13:14], v[5:6], v[9:10]
v_mul_f64 v[9:10], v[9:10], 0.5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[15:16], -v[7:8], v[11:12], 0.5
v_fma_f64 v[17:18], -v[9:10], v[13:14], 0.5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[11:12], v[11:12], v[15:16], v[11:12]
v_fma_f64 v[7:8], v[7:8], v[15:16], v[7:8]
v_fma_f64 v[13:14], v[13:14], v[17:18], v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[15:16], -v[11:12], v[11:12], v[3:4]
v_fma_f64 v[9:10], v[9:10], v[17:18], v[9:10]
v_fma_f64 v[17:18], -v[13:14], v[13:14], v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[11:12], v[15:16], v[7:8], v[11:12]
v_fma_f64 v[13:14], v[17:18], v[9:10], v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[15:16], -v[11:12], v[11:12], v[3:4]
v_fma_f64 v[17:18], -v[13:14], v[13:14], v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[7:8], v[15:16], v[7:8], v[11:12]
v_cndmask_b32_e64 v11, 0, 0xffffff80, s2
s_cselect_b32 s2, 0xffffff80, 0
v_fma_f64 v[9:10], v[17:18], v[9:10], v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ldexp_f64 v[7:8], v[7:8], s2
v_cmp_class_f64_e64 s2, v[5:6], 0x260
v_ldexp_f64 v[9:10], v[9:10], v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v4, v8, v4
v_cndmask_b32_e64 v6, v10, v6, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v5, v9, v5, s2
v_mul_f64 v[3:4], v[5:6], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[5:6], null, v[3:4], v[3:4], v[1:2]
v_rcp_f64_e32 v[7:8], v[5:6]
s_waitcnt_depctr 0xfff
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
v_div_scale_f64 v[9:10], vcc_lo, v[1:2], v[3:4], v[1:2]
v_mul_f64 v[11:12], v[9:10], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], -v[5:6], v[11:12], v[9:10]
v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[11:12]
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f64 v[1:2], v[5:6], v[3:4], v[1:2]
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, 0xffff, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b64 v[3:4], v[1:2], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17cosine_similarityPiPdii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17cosine_similarityPiPdii, .Lfunc_end0-_Z17cosine_similarityPiPdii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17cosine_similarityPiPdii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17cosine_similarityPiPdii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
int is_power_of_two(int x)
{
// https://stackoverflow.com/questions/600293/how-to-check-if-a-number-is-a-power-of-2/600306#600306
return (x != 0) && ((x & (x - 1)) == 0);
}
__global__ void sum_arr(float *arr, int n, double *res) {
for(int i=0; i<n; i++)
*res += arr[i];
}
int main(int argc, char const *argv[])
{
const int N = argc-1;
if(N == 0 || !is_power_of_two(N)) {
printf("Please call the program with the 2^N array elements "
"to be summed as arguments.\n");
return 1;
}
float *arr;
double *sum;
cudaMallocManaged(&arr, sizeof *arr * N);
cudaMallocManaged(&sum, sizeof *sum);
*sum = 0;
// initialize array on host with program arguments
for(int i=0; i<N; i++) {
arr[i] = atof(argv[i+1]);
}
sum_arr<<<1, 1>>>(arr, N, sum);
cudaDeviceSynchronize();
cudaFree(arr);
printf("Result is: %f\n", *sum);
return 0;
} | code for sm_80
Function : _Z7sum_arrPfiPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0090*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fd400078e00ff */
/*00b0*/ @!P0 BRA 0xa20 ; /* 0x0000096000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R6, -R0, c[0x0][0x168], RZ ; /* 0x00005a0000067a10 */
/* 0x000fe20007ffe1ff */
/*00d0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000802087981 */
/* 0x000162000c1e1b00 */
/*00e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe200078e00ff */
/*0100*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fd800078e00ff */
/*0120*/ @!P0 BRA 0x8a0 ; /* 0x0000077000008947 */
/* 0x001fea0003800000 */
/*0130*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0140*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0150*/ @!P1 BRA 0x5f0 ; /* 0x0000049000009947 */
/* 0x000fea0003800000 */
/*0160*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0170*/ LDG.E R7, [R4.64] ; /* 0x0000000804077981 */
/* 0x000ea4000c1e1900 */
/*0180*/ F2F.F64.F32 R10, R7 ; /* 0x00000007000a7310 */
/* 0x004e240000201800 */
/*0190*/ DADD R10, R10, R8 ; /* 0x000000000a0a7229 */
/* 0x021e0e0000000008 */
/*01a0*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b08 */
/*01b0*/ LDG.E R16, [R4.64+0x4] ; /* 0x0000040804107981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ F2F.F64.F32 R8, R16 ; /* 0x0000001000087310 */
/* 0x006e640000201800 */
/*01d0*/ DADD R8, R10, R8 ; /* 0x000000000a087229 */
/* 0x002e4e0000000008 */
/*01e0*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b08 */
/*01f0*/ LDG.E R17, [R4.64+0x8] ; /* 0x0000080804117981 */
/* 0x000ea4000c1e1900 */
/*0200*/ F2F.F64.F32 R12, R17 ; /* 0x00000011000c7310 */
/* 0x004ea40000201800 */
/*0210*/ DADD R12, R8, R12 ; /* 0x00000000080c7229 */
/* 0x004e8e000000000c */
/*0220*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0045e8000c101b08 */
/*0230*/ LDG.E R7, [R4.64+0xc] ; /* 0x00000c0804077981 */
/* 0x000ee4000c1e1900 */
/*0240*/ F2F.F64.F32 R14, R7 ; /* 0x00000007000e7310 */
/* 0x008ee40000201800 */
/*0250*/ DADD R14, R12, R14 ; /* 0x000000000c0e7229 */
/* 0x008ece000000000e */
/*0260*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b08 */
/*0270*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100804107981 */
/* 0x000e24000c1e1900 */
/*0280*/ F2F.F64.F32 R10, R16 ; /* 0x00000010000a7310 */
/* 0x001e240000201800 */
/*0290*/ DADD R10, R14, R10 ; /* 0x000000000e0a7229 */
/* 0x001e0e000000000a */
/*02a0*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b08 */
/*02b0*/ LDG.E R17, [R4.64+0x14] ; /* 0x0000140804117981 */
/* 0x000e64000c1e1900 */
/*02c0*/ F2F.F64.F32 R8, R17 ; /* 0x0000001100087310 */
/* 0x002e640000201800 */
/*02d0*/ DADD R8, R10, R8 ; /* 0x000000000a087229 */
/* 0x002e4e0000000008 */
/*02e0*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b08 */
/*02f0*/ LDG.E R7, [R4.64+0x18] ; /* 0x0000180804077981 */
/* 0x000ea4000c1e1900 */
/*0300*/ F2F.F64.F32 R12, R7 ; /* 0x00000007000c7310 */
/* 0x004ea40000201800 */
/*0310*/ DADD R12, R8, R12 ; /* 0x00000000080c7229 */
/* 0x004e8e000000000c */
/*0320*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0045e8000c101b08 */
/*0330*/ LDG.E R16, [R4.64+0x1c] ; /* 0x00001c0804107981 */
/* 0x000ee4000c1e1900 */
/*0340*/ F2F.F64.F32 R14, R16 ; /* 0x00000010000e7310 */
/* 0x008ee40000201800 */
/*0350*/ DADD R14, R12, R14 ; /* 0x000000000c0e7229 */
/* 0x008ece000000000e */
/*0360*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b08 */
/*0370*/ LDG.E R17, [R4.64+0x20] ; /* 0x0000200804117981 */
/* 0x000e24000c1e1900 */
/*0380*/ F2F.F64.F32 R10, R17 ; /* 0x00000011000a7310 */
/* 0x001e240000201800 */
/*0390*/ DADD R10, R14, R10 ; /* 0x000000000e0a7229 */
/* 0x001e0e000000000a */
/*03a0*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b08 */
/*03b0*/ LDG.E R7, [R4.64+0x24] ; /* 0x0000240804077981 */
/* 0x000e64000c1e1900 */
/*03c0*/ F2F.F64.F32 R8, R7 ; /* 0x0000000700087310 */
/* 0x002e640000201800 */
/*03d0*/ DADD R8, R10, R8 ; /* 0x000000000a087229 */
/* 0x002e4e0000000008 */
/*03e0*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b08 */
/*03f0*/ LDG.E R16, [R4.64+0x28] ; /* 0x0000280804107981 */
/* 0x000ea4000c1e1900 */
/*0400*/ F2F.F64.F32 R12, R16 ; /* 0x00000010000c7310 */
/* 0x004ea40000201800 */
/*0410*/ DADD R12, R8, R12 ; /* 0x00000000080c7229 */
/* 0x004e8e000000000c */
/*0420*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0045e8000c101b08 */
/*0430*/ LDG.E R17, [R4.64+0x2c] ; /* 0x00002c0804117981 */
/* 0x000ee4000c1e1900 */
/*0440*/ F2F.F64.F32 R14, R17 ; /* 0x00000011000e7310 */
/* 0x008ee40000201800 */
/*0450*/ DADD R14, R12, R14 ; /* 0x000000000c0e7229 */
/* 0x008ece000000000e */
/*0460*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b08 */
/*0470*/ LDG.E R7, [R4.64+0x30] ; /* 0x0000300804077981 */
/* 0x000e24000c1e1900 */
/*0480*/ F2F.F64.F32 R10, R7 ; /* 0x00000007000a7310 */
/* 0x001e240000201800 */
/*0490*/ DADD R10, R14, R10 ; /* 0x000000000e0a7229 */
/* 0x001e0e000000000a */
/*04a0*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b08 */
/*04b0*/ LDG.E R16, [R4.64+0x34] ; /* 0x0000340804107981 */
/* 0x000e64000c1e1900 */
/*04c0*/ F2F.F64.F32 R8, R16 ; /* 0x0000001000087310 */
/* 0x002ea40000201800 */
/*04d0*/ DADD R12, R10, R8 ; /* 0x000000000a0c7229 */
/* 0x004e4e0000000008 */
/*04e0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0023e8000c101b08 */
/*04f0*/ LDG.E R17, [R4.64+0x38] ; /* 0x0000380804117981 */
/* 0x000ea4000c1e1900 */
/*0500*/ F2F.F64.F32 R8, R17 ; /* 0x0000001100087310 */
/* 0x004ee40000201800 */
/*0510*/ DADD R14, R12, R8 ; /* 0x000000000c0e7229 */
/* 0x008e8e0000000008 */
/*0520*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0043e8000c101b08 */
/*0530*/ LDG.E R7, [R4.64+0x3c] ; /* 0x00003c0804077981 */
/* 0x0004e2000c1e1900 */
/*0540*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe20007ffe0ff */
/*0550*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0560*/ IADD3 R10, P2, R4, 0x40, RZ ; /* 0x00000040040a7810 */
/* 0x001fe40007f5e0ff */
/*0570*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc60003f24270 */
/*0580*/ IMAD.X R11, RZ, RZ, R5, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fe400010e0605 */
/*0590*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x004fe400078e000a */
/*05a0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*05b0*/ F2F.F64.F32 R8, R7 ; /* 0x0000000700087310 */
/* 0x008e240000201800 */
/*05c0*/ DADD R8, R14, R8 ; /* 0x000000000e087229 */
/* 0x001e0e0000000008 */
/*05d0*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0013e2000c101b08 */
/*05e0*/ @P1 BRA 0x170 ; /* 0xfffffb8000001947 */
/* 0x000fea000383ffff */
/*05f0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0600*/ @!P1 BRA 0x880 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*0610*/ LDG.E R7, [R4.64] ; /* 0x0000000804077981 */
/* 0x000ea4000c1e1900 */
/*0620*/ F2F.F64.F32 R10, R7 ; /* 0x00000007000a7310 */
/* 0x004e240000201800 */
/*0630*/ DADD R10, R8, R10 ; /* 0x00000000080a7229 */
/* 0x021e0e000000000a */
/*0640*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b08 */
/*0650*/ LDG.E R16, [R4.64+0x4] ; /* 0x0000040804107981 */
/* 0x000ea4000c1e1900 */
/*0660*/ F2F.F64.F32 R8, R16 ; /* 0x0000001000087310 */
/* 0x006e640000201800 */
/*0670*/ DADD R8, R10, R8 ; /* 0x000000000a087229 */
/* 0x002e4e0000000008 */
/*0680*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b08 */
/*0690*/ LDG.E R17, [R4.64+0x8] ; /* 0x0000080804117981 */
/* 0x000ea4000c1e1900 */
/*06a0*/ F2F.F64.F32 R12, R17 ; /* 0x00000011000c7310 */
/* 0x004ea40000201800 */
/*06b0*/ DADD R12, R8, R12 ; /* 0x00000000080c7229 */
/* 0x004e8e000000000c */
/*06c0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0045e8000c101b08 */
/*06d0*/ LDG.E R7, [R4.64+0xc] ; /* 0x00000c0804077981 */
/* 0x000ee4000c1e1900 */
/*06e0*/ F2F.F64.F32 R14, R7 ; /* 0x00000007000e7310 */
/* 0x008ee40000201800 */
/*06f0*/ DADD R14, R12, R14 ; /* 0x000000000c0e7229 */
/* 0x008ece000000000e */
/*0700*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b08 */
/*0710*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100804107981 */
/* 0x000e24000c1e1900 */
/*0720*/ F2F.F64.F32 R10, R16 ; /* 0x00000010000a7310 */
/* 0x001e240000201800 */
/*0730*/ DADD R10, R14, R10 ; /* 0x000000000e0a7229 */
/* 0x001e0e000000000a */
/*0740*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b08 */
/*0750*/ LDG.E R17, [R4.64+0x14] ; /* 0x0000140804117981 */
/* 0x000e64000c1e1900 */
/*0760*/ F2F.F64.F32 R8, R17 ; /* 0x0000001100087310 */
/* 0x002ea40000201800 */
/*0770*/ DADD R12, R10, R8 ; /* 0x000000000a0c7229 */
/* 0x004e4e0000000008 */
/*0780*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0023e8000c101b08 */
/*0790*/ LDG.E R7, [R4.64+0x18] ; /* 0x0000180804077981 */
/* 0x000ea4000c1e1900 */
/*07a0*/ F2F.F64.F32 R8, R7 ; /* 0x0000000700087310 */
/* 0x004ee40000201800 */
/*07b0*/ DADD R14, R12, R8 ; /* 0x000000000c0e7229 */
/* 0x008e8e0000000008 */
/*07c0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0043e8000c101b08 */
/*07d0*/ LDG.E R16, [R4.64+0x1c] ; /* 0x00001c0804107981 */
/* 0x0004e2000c1e1900 */
/*07e0*/ IADD3 R10, P1, R4, 0x20, RZ ; /* 0x00000020040a7810 */
/* 0x001fe20007f3e0ff */
/*07f0*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0800*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0810*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0820*/ IMAD.X R11, RZ, RZ, R5, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fc400008e0605 */
/*0830*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x004fe400078e000a */
/*0840*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*0850*/ F2F.F64.F32 R8, R16 ; /* 0x0000001000087310 */
/* 0x008e240000201800 */
/*0860*/ DADD R8, R14, R8 ; /* 0x000000000e087229 */
/* 0x001e0e0000000008 */
/*0870*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0013e8000c101b08 */
/*0880*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0890*/ @!P0 BRA 0xa20 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*08a0*/ LDG.E R7, [R4.64] ; /* 0x0000000804077981 */
/* 0x000ea4000c1e1900 */
/*08b0*/ F2F.F64.F32 R10, R7 ; /* 0x00000007000a7310 */
/* 0x004e240000201800 */
/*08c0*/ DADD R10, R10, R8 ; /* 0x000000000a0a7229 */
/* 0x021e0e0000000008 */
/*08d0*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b08 */
/*08e0*/ LDG.E R16, [R4.64+0x4] ; /* 0x0000040804107981 */
/* 0x000ea4000c1e1900 */
/*08f0*/ F2F.F64.F32 R8, R16 ; /* 0x0000001000087310 */
/* 0x006e640000201800 */
/*0900*/ DADD R12, R10, R8 ; /* 0x000000000a0c7229 */
/* 0x002e4e0000000008 */
/*0910*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0023e8000c101b08 */
/*0920*/ LDG.E R17, [R4.64+0x8] ; /* 0x0000080804117981 */
/* 0x000ea4000c1e1900 */
/*0930*/ F2F.F64.F32 R8, R17 ; /* 0x0000001100087310 */
/* 0x004ea40000201800 */
/*0940*/ DADD R14, R12, R8 ; /* 0x000000000c0e7229 */
/* 0x004e8e0000000008 */
/*0950*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0043e8000c101b08 */
/*0960*/ LDG.E R7, [R4.64+0xc] ; /* 0x00000c0804077981 */
/* 0x0004e2000c1e1900 */
/*0970*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*0980*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0990*/ IADD3 R10, P1, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x001fe40007f3e0ff */
/*09a0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc60003f05270 */
/*09b0*/ IMAD.X R11, RZ, RZ, R5, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe400008e0605 */
/*09c0*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x004fe400078e000a */
/*09d0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*09e0*/ F2F.F64.F32 R8, R7 ; /* 0x0000000700087310 */
/* 0x008e240000201800 */
/*09f0*/ DADD R8, R14, R8 ; /* 0x000000000e087229 */
/* 0x001e0e0000000008 */
/*0a00*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0013e4000c101b08 */
/*0a10*/ @P0 BRA 0x8a0 ; /* 0xfffffe8000000947 */
/* 0x002fea000383ffff */
/*0a20*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0a30*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0a40*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000802047981 */
/* 0x000162000c1e1b00 */
/*0a50*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0a60*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0a70*/ UIMAD.WIDE UR4, UR4, UR5, UR6 ; /* 0x00000005040472a5 */
/* 0x000fcc000f8e0206 */
/*0a80*/ IMAD.U32 R8, RZ, RZ, UR4 ; /* 0x00000004ff087e24 */
/* 0x022fe4000f8e00ff */
/*0a90*/ IMAD.U32 R9, RZ, RZ, UR5 ; /* 0x00000005ff097e24 */
/* 0x000fca000f8e00ff */
/*0aa0*/ LDG.E R6, [R8.64] ; /* 0x0000000808067981 */
/* 0x000ea2000c1e1900 */
/*0ab0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0ac0*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc6000ff1e03f */
/*0ad0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0ae0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0af0*/ F2F.F64.F32 R6, R6 ; /* 0x0000000600067310 */
/* 0x004e640000201800 */
/*0b00*/ DADD R4, R6, R4 ; /* 0x0000000006047229 */
/* 0x002e4e0000000004 */
/*0b10*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0023e4000c101b08 */
/*0b20*/ @P0 BRA 0xa80 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0b30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b40*/ BRA 0xb40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
int is_power_of_two(int x)
{
// https://stackoverflow.com/questions/600293/how-to-check-if-a-number-is-a-power-of-2/600306#600306
return (x != 0) && ((x & (x - 1)) == 0);
}
__global__ void sum_arr(float *arr, int n, double *res) {
for(int i=0; i<n; i++)
*res += arr[i];
}
int main(int argc, char const *argv[])
{
const int N = argc-1;
if(N == 0 || !is_power_of_two(N)) {
printf("Please call the program with the 2^N array elements "
"to be summed as arguments.\n");
return 1;
}
float *arr;
double *sum;
cudaMallocManaged(&arr, sizeof *arr * N);
cudaMallocManaged(&sum, sizeof *sum);
*sum = 0;
// initialize array on host with program arguments
for(int i=0; i<N; i++) {
arr[i] = atof(argv[i+1]);
}
sum_arr<<<1, 1>>>(arr, N, sum);
cudaDeviceSynchronize();
cudaFree(arr);
printf("Result is: %f\n", *sum);
return 0;
} | .file "tmpxft_000139e4_00000000-6_2-b.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15is_power_of_twoi
.type _Z15is_power_of_twoi, @function
_Z15is_power_of_twoi:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
testl %edi, %edi
je .L4
leal -1(%rdi), %eax
testl %edi, %eax
sete %al
.L4:
movzbl %al, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z15is_power_of_twoi, .-_Z15is_power_of_twoi
.globl _Z29__device_stub__Z7sum_arrPfiPdPfiPd
.type _Z29__device_stub__Z7sum_arrPfiPdPfiPd, @function
_Z29__device_stub__Z7sum_arrPfiPdPfiPd:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7sum_arrPfiPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z7sum_arrPfiPdPfiPd, .-_Z29__device_stub__Z7sum_arrPfiPdPfiPd
.globl _Z7sum_arrPfiPd
.type _Z7sum_arrPfiPd, @function
_Z7sum_arrPfiPd:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7sum_arrPfiPdPfiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7sum_arrPfiPd, .-_Z7sum_arrPfiPd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Please call the program with the 2^N array elements to be summed as arguments.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Result is: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %edi, %r12d
subl $1, %r12d
je .L15
movl %edi, %ebx
movq %rsi, %rbp
movl %r12d, %edi
call _Z15is_power_of_twoi
testl %eax, %eax
jne .L16
.L15:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L14:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L24
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movslq %r12d, %rsi
salq $2, %rsi
movq %rsp, %rdi
movl $1, %edx
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $8, %esi
call cudaMallocManaged@PLT
movq 8(%rsp), %rax
movq $0x000000000, (%rax)
testl %r12d, %r12d
jle .L18
leal -1(%rbx), %r13d
salq $2, %r13
movl $0, %ebx
.L19:
movq 8(%rbp,%rbx,2), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
movq (%rsp), %rax
movss %xmm0, (%rax,%rbx)
addq $4, %rbx
cmpq %r13, %rbx
jne .L19
.L18:
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L20:
call cudaDeviceSynchronize@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rax
movsd (%rax), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L14
.L25:
movq 8(%rsp), %rdx
movl %r12d, %esi
movq (%rsp), %rdi
call _Z29__device_stub__Z7sum_arrPfiPdPfiPd
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z7sum_arrPfiPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z7sum_arrPfiPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
int is_power_of_two(int x)
{
// https://stackoverflow.com/questions/600293/how-to-check-if-a-number-is-a-power-of-2/600306#600306
return (x != 0) && ((x & (x - 1)) == 0);
}
__global__ void sum_arr(float *arr, int n, double *res) {
for(int i=0; i<n; i++)
*res += arr[i];
}
int main(int argc, char const *argv[])
{
const int N = argc-1;
if(N == 0 || !is_power_of_two(N)) {
printf("Please call the program with the 2^N array elements "
"to be summed as arguments.\n");
return 1;
}
float *arr;
double *sum;
cudaMallocManaged(&arr, sizeof *arr * N);
cudaMallocManaged(&sum, sizeof *sum);
*sum = 0;
// initialize array on host with program arguments
for(int i=0; i<N; i++) {
arr[i] = atof(argv[i+1]);
}
sum_arr<<<1, 1>>>(arr, N, sum);
cudaDeviceSynchronize();
cudaFree(arr);
printf("Result is: %f\n", *sum);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int is_power_of_two(int x)
{
// https://stackoverflow.com/questions/600293/how-to-check-if-a-number-is-a-power-of-2/600306#600306
return (x != 0) && ((x & (x - 1)) == 0);
}
__global__ void sum_arr(float *arr, int n, double *res) {
for(int i=0; i<n; i++)
*res += arr[i];
}
int main(int argc, char const *argv[])
{
const int N = argc-1;
if(N == 0 || !is_power_of_two(N)) {
printf("Please call the program with the 2^N array elements "
"to be summed as arguments.\n");
return 1;
}
float *arr;
double *sum;
hipMallocManaged(&arr, sizeof *arr * N);
hipMallocManaged(&sum, sizeof *sum);
*sum = 0;
// initialize array on host with program arguments
for(int i=0; i<N; i++) {
arr[i] = atof(argv[i+1]);
}
sum_arr<<<1, 1>>>(arr, N, sum);
hipDeviceSynchronize();
hipFree(arr);
printf("Result is: %f\n", *sum);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int is_power_of_two(int x)
{
// https://stackoverflow.com/questions/600293/how-to-check-if-a-number-is-a-power-of-2/600306#600306
return (x != 0) && ((x & (x - 1)) == 0);
}
__global__ void sum_arr(float *arr, int n, double *res) {
for(int i=0; i<n; i++)
*res += arr[i];
}
int main(int argc, char const *argv[])
{
const int N = argc-1;
if(N == 0 || !is_power_of_two(N)) {
printf("Please call the program with the 2^N array elements "
"to be summed as arguments.\n");
return 1;
}
float *arr;
double *sum;
hipMallocManaged(&arr, sizeof *arr * N);
hipMallocManaged(&sum, sizeof *sum);
*sum = 0;
// initialize array on host with program arguments
for(int i=0; i<N; i++) {
arr[i] = atof(argv[i+1]);
}
sum_arr<<<1, 1>>>(arr, N, sum);
hipDeviceSynchronize();
hipFree(arr);
printf("Result is: %f\n", *sum);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7sum_arrPfiPd
.globl _Z7sum_arrPfiPd
.p2align 8
.type _Z7sum_arrPfiPd,@function
_Z7sum_arrPfiPd:
s_load_b32 s4, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b64 s[6:7], s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
.LBB0_2:
s_load_b32 s5, s[0:1], 0x0
s_add_i32 s4, s4, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s4, 0
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[2:3], s5
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], v[2:3]
s_cbranch_scc0 .LBB0_2
v_mov_b32_e32 v2, 0
global_store_b64 v2, v[0:1], s[2:3]
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7sum_arrPfiPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7sum_arrPfiPd, .Lfunc_end0-_Z7sum_arrPfiPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7sum_arrPfiPd
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z7sum_arrPfiPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int is_power_of_two(int x)
{
// https://stackoverflow.com/questions/600293/how-to-check-if-a-number-is-a-power-of-2/600306#600306
return (x != 0) && ((x & (x - 1)) == 0);
}
__global__ void sum_arr(float *arr, int n, double *res) {
for(int i=0; i<n; i++)
*res += arr[i];
}
int main(int argc, char const *argv[])
{
const int N = argc-1;
if(N == 0 || !is_power_of_two(N)) {
printf("Please call the program with the 2^N array elements "
"to be summed as arguments.\n");
return 1;
}
float *arr;
double *sum;
hipMallocManaged(&arr, sizeof *arr * N);
hipMallocManaged(&sum, sizeof *sum);
*sum = 0;
// initialize array on host with program arguments
for(int i=0; i<N; i++) {
arr[i] = atof(argv[i+1]);
}
sum_arr<<<1, 1>>>(arr, N, sum);
hipDeviceSynchronize();
hipFree(arr);
printf("Result is: %f\n", *sum);
return 0;
} | .text
.file "2-b.hip"
.globl _Z15is_power_of_twoi # -- Begin function _Z15is_power_of_twoi
.p2align 4, 0x90
.type _Z15is_power_of_twoi,@function
_Z15is_power_of_twoi: # @_Z15is_power_of_twoi
.cfi_startproc
# %bb.0:
# kill: def $edi killed $edi def $rdi
testl %edi, %edi
je .LBB0_1
# %bb.2:
leal -1(%rdi), %ecx
xorl %eax, %eax
testl %ecx, %edi
sete %al
retq
.LBB0_1:
xorl %eax, %eax
retq
.Lfunc_end0:
.size _Z15is_power_of_twoi, .Lfunc_end0-_Z15is_power_of_twoi
.cfi_endproc
# -- End function
.globl _Z22__device_stub__sum_arrPfiPd # -- Begin function _Z22__device_stub__sum_arrPfiPd
.p2align 4, 0x90
.type _Z22__device_stub__sum_arrPfiPd,@function
_Z22__device_stub__sum_arrPfiPd: # @_Z22__device_stub__sum_arrPfiPd
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7sum_arrPfiPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__sum_arrPfiPd, .Lfunc_end1-_Z22__device_stub__sum_arrPfiPd
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %r14d
leal -1(%r14), %ebp
leal -2(%r14), %eax
movl %ebp, %ecx
xorl %eax, %ecx
cmpl %eax, %ecx
jbe .LBB2_1
# %bb.2:
movq %rsi, %rbx
movslq %ebp, %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $8, %esi
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %rax
movq $0, (%rax)
cmpl $2, %r14d
jl .LBB2_5
# %bb.3: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq 1(%r15), %r12
movq 8(%rbx,%r15,8), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movq 16(%rsp), %rax
movss %xmm0, (%rax,%r15,4)
movq %r12, %r15
cmpq %r12, %r14
jne .LBB2_4
.LBB2_5: # %._crit_edge
xorl %ebx, %ebx
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movl %ebp, 28(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7sum_arrPfiPd, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rax
movsd (%rax), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movb $1, %al
callq printf
jmp .LBB2_8
.LBB2_1:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %ebx
.LBB2_8:
movl %ebx, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7sum_arrPfiPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7sum_arrPfiPd,@object # @_Z7sum_arrPfiPd
.section .rodata,"a",@progbits
.globl _Z7sum_arrPfiPd
.p2align 3, 0x0
_Z7sum_arrPfiPd:
.quad _Z22__device_stub__sum_arrPfiPd
.size _Z7sum_arrPfiPd, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Result is: %f\n"
.size .L.str.1, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7sum_arrPfiPd"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Please call the program with the 2^N array elements to be summed as arguments."
.size .Lstr, 79
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__sum_arrPfiPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7sum_arrPfiPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7sum_arrPfiPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0090*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fd400078e00ff */
/*00b0*/ @!P0 BRA 0xa20 ; /* 0x0000096000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R6, -R0, c[0x0][0x168], RZ ; /* 0x00005a0000067a10 */
/* 0x000fe20007ffe1ff */
/*00d0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000802087981 */
/* 0x000162000c1e1b00 */
/*00e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe200078e00ff */
/*0100*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fd800078e00ff */
/*0120*/ @!P0 BRA 0x8a0 ; /* 0x0000077000008947 */
/* 0x001fea0003800000 */
/*0130*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0140*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0150*/ @!P1 BRA 0x5f0 ; /* 0x0000049000009947 */
/* 0x000fea0003800000 */
/*0160*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0170*/ LDG.E R7, [R4.64] ; /* 0x0000000804077981 */
/* 0x000ea4000c1e1900 */
/*0180*/ F2F.F64.F32 R10, R7 ; /* 0x00000007000a7310 */
/* 0x004e240000201800 */
/*0190*/ DADD R10, R10, R8 ; /* 0x000000000a0a7229 */
/* 0x021e0e0000000008 */
/*01a0*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b08 */
/*01b0*/ LDG.E R16, [R4.64+0x4] ; /* 0x0000040804107981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ F2F.F64.F32 R8, R16 ; /* 0x0000001000087310 */
/* 0x006e640000201800 */
/*01d0*/ DADD R8, R10, R8 ; /* 0x000000000a087229 */
/* 0x002e4e0000000008 */
/*01e0*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b08 */
/*01f0*/ LDG.E R17, [R4.64+0x8] ; /* 0x0000080804117981 */
/* 0x000ea4000c1e1900 */
/*0200*/ F2F.F64.F32 R12, R17 ; /* 0x00000011000c7310 */
/* 0x004ea40000201800 */
/*0210*/ DADD R12, R8, R12 ; /* 0x00000000080c7229 */
/* 0x004e8e000000000c */
/*0220*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0045e8000c101b08 */
/*0230*/ LDG.E R7, [R4.64+0xc] ; /* 0x00000c0804077981 */
/* 0x000ee4000c1e1900 */
/*0240*/ F2F.F64.F32 R14, R7 ; /* 0x00000007000e7310 */
/* 0x008ee40000201800 */
/*0250*/ DADD R14, R12, R14 ; /* 0x000000000c0e7229 */
/* 0x008ece000000000e */
/*0260*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b08 */
/*0270*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100804107981 */
/* 0x000e24000c1e1900 */
/*0280*/ F2F.F64.F32 R10, R16 ; /* 0x00000010000a7310 */
/* 0x001e240000201800 */
/*0290*/ DADD R10, R14, R10 ; /* 0x000000000e0a7229 */
/* 0x001e0e000000000a */
/*02a0*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b08 */
/*02b0*/ LDG.E R17, [R4.64+0x14] ; /* 0x0000140804117981 */
/* 0x000e64000c1e1900 */
/*02c0*/ F2F.F64.F32 R8, R17 ; /* 0x0000001100087310 */
/* 0x002e640000201800 */
/*02d0*/ DADD R8, R10, R8 ; /* 0x000000000a087229 */
/* 0x002e4e0000000008 */
/*02e0*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b08 */
/*02f0*/ LDG.E R7, [R4.64+0x18] ; /* 0x0000180804077981 */
/* 0x000ea4000c1e1900 */
/*0300*/ F2F.F64.F32 R12, R7 ; /* 0x00000007000c7310 */
/* 0x004ea40000201800 */
/*0310*/ DADD R12, R8, R12 ; /* 0x00000000080c7229 */
/* 0x004e8e000000000c */
/*0320*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0045e8000c101b08 */
/*0330*/ LDG.E R16, [R4.64+0x1c] ; /* 0x00001c0804107981 */
/* 0x000ee4000c1e1900 */
/*0340*/ F2F.F64.F32 R14, R16 ; /* 0x00000010000e7310 */
/* 0x008ee40000201800 */
/*0350*/ DADD R14, R12, R14 ; /* 0x000000000c0e7229 */
/* 0x008ece000000000e */
/*0360*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b08 */
/*0370*/ LDG.E R17, [R4.64+0x20] ; /* 0x0000200804117981 */
/* 0x000e24000c1e1900 */
/*0380*/ F2F.F64.F32 R10, R17 ; /* 0x00000011000a7310 */
/* 0x001e240000201800 */
/*0390*/ DADD R10, R14, R10 ; /* 0x000000000e0a7229 */
/* 0x001e0e000000000a */
/*03a0*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b08 */
/*03b0*/ LDG.E R7, [R4.64+0x24] ; /* 0x0000240804077981 */
/* 0x000e64000c1e1900 */
/*03c0*/ F2F.F64.F32 R8, R7 ; /* 0x0000000700087310 */
/* 0x002e640000201800 */
/*03d0*/ DADD R8, R10, R8 ; /* 0x000000000a087229 */
/* 0x002e4e0000000008 */
/*03e0*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b08 */
/*03f0*/ LDG.E R16, [R4.64+0x28] ; /* 0x0000280804107981 */
/* 0x000ea4000c1e1900 */
/*0400*/ F2F.F64.F32 R12, R16 ; /* 0x00000010000c7310 */
/* 0x004ea40000201800 */
/*0410*/ DADD R12, R8, R12 ; /* 0x00000000080c7229 */
/* 0x004e8e000000000c */
/*0420*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0045e8000c101b08 */
/*0430*/ LDG.E R17, [R4.64+0x2c] ; /* 0x00002c0804117981 */
/* 0x000ee4000c1e1900 */
/*0440*/ F2F.F64.F32 R14, R17 ; /* 0x00000011000e7310 */
/* 0x008ee40000201800 */
/*0450*/ DADD R14, R12, R14 ; /* 0x000000000c0e7229 */
/* 0x008ece000000000e */
/*0460*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b08 */
/*0470*/ LDG.E R7, [R4.64+0x30] ; /* 0x0000300804077981 */
/* 0x000e24000c1e1900 */
/*0480*/ F2F.F64.F32 R10, R7 ; /* 0x00000007000a7310 */
/* 0x001e240000201800 */
/*0490*/ DADD R10, R14, R10 ; /* 0x000000000e0a7229 */
/* 0x001e0e000000000a */
/*04a0*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b08 */
/*04b0*/ LDG.E R16, [R4.64+0x34] ; /* 0x0000340804107981 */
/* 0x000e64000c1e1900 */
/*04c0*/ F2F.F64.F32 R8, R16 ; /* 0x0000001000087310 */
/* 0x002ea40000201800 */
/*04d0*/ DADD R12, R10, R8 ; /* 0x000000000a0c7229 */
/* 0x004e4e0000000008 */
/*04e0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0023e8000c101b08 */
/*04f0*/ LDG.E R17, [R4.64+0x38] ; /* 0x0000380804117981 */
/* 0x000ea4000c1e1900 */
/*0500*/ F2F.F64.F32 R8, R17 ; /* 0x0000001100087310 */
/* 0x004ee40000201800 */
/*0510*/ DADD R14, R12, R8 ; /* 0x000000000c0e7229 */
/* 0x008e8e0000000008 */
/*0520*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0043e8000c101b08 */
/*0530*/ LDG.E R7, [R4.64+0x3c] ; /* 0x00003c0804077981 */
/* 0x0004e2000c1e1900 */
/*0540*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe20007ffe0ff */
/*0550*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0560*/ IADD3 R10, P2, R4, 0x40, RZ ; /* 0x00000040040a7810 */
/* 0x001fe40007f5e0ff */
/*0570*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc60003f24270 */
/*0580*/ IMAD.X R11, RZ, RZ, R5, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fe400010e0605 */
/*0590*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x004fe400078e000a */
/*05a0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*05b0*/ F2F.F64.F32 R8, R7 ; /* 0x0000000700087310 */
/* 0x008e240000201800 */
/*05c0*/ DADD R8, R14, R8 ; /* 0x000000000e087229 */
/* 0x001e0e0000000008 */
/*05d0*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0013e2000c101b08 */
/*05e0*/ @P1 BRA 0x170 ; /* 0xfffffb8000001947 */
/* 0x000fea000383ffff */
/*05f0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0600*/ @!P1 BRA 0x880 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*0610*/ LDG.E R7, [R4.64] ; /* 0x0000000804077981 */
/* 0x000ea4000c1e1900 */
/*0620*/ F2F.F64.F32 R10, R7 ; /* 0x00000007000a7310 */
/* 0x004e240000201800 */
/*0630*/ DADD R10, R8, R10 ; /* 0x00000000080a7229 */
/* 0x021e0e000000000a */
/*0640*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b08 */
/*0650*/ LDG.E R16, [R4.64+0x4] ; /* 0x0000040804107981 */
/* 0x000ea4000c1e1900 */
/*0660*/ F2F.F64.F32 R8, R16 ; /* 0x0000001000087310 */
/* 0x006e640000201800 */
/*0670*/ DADD R8, R10, R8 ; /* 0x000000000a087229 */
/* 0x002e4e0000000008 */
/*0680*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e8000c101b08 */
/*0690*/ LDG.E R17, [R4.64+0x8] ; /* 0x0000080804117981 */
/* 0x000ea4000c1e1900 */
/*06a0*/ F2F.F64.F32 R12, R17 ; /* 0x00000011000c7310 */
/* 0x004ea40000201800 */
/*06b0*/ DADD R12, R8, R12 ; /* 0x00000000080c7229 */
/* 0x004e8e000000000c */
/*06c0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0045e8000c101b08 */
/*06d0*/ LDG.E R7, [R4.64+0xc] ; /* 0x00000c0804077981 */
/* 0x000ee4000c1e1900 */
/*06e0*/ F2F.F64.F32 R14, R7 ; /* 0x00000007000e7310 */
/* 0x008ee40000201800 */
/*06f0*/ DADD R14, R12, R14 ; /* 0x000000000c0e7229 */
/* 0x008ece000000000e */
/*0700*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0087e8000c101b08 */
/*0710*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100804107981 */
/* 0x000e24000c1e1900 */
/*0720*/ F2F.F64.F32 R10, R16 ; /* 0x00000010000a7310 */
/* 0x001e240000201800 */
/*0730*/ DADD R10, R14, R10 ; /* 0x000000000e0a7229 */
/* 0x001e0e000000000a */
/*0740*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b08 */
/*0750*/ LDG.E R17, [R4.64+0x14] ; /* 0x0000140804117981 */
/* 0x000e64000c1e1900 */
/*0760*/ F2F.F64.F32 R8, R17 ; /* 0x0000001100087310 */
/* 0x002ea40000201800 */
/*0770*/ DADD R12, R10, R8 ; /* 0x000000000a0c7229 */
/* 0x004e4e0000000008 */
/*0780*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0023e8000c101b08 */
/*0790*/ LDG.E R7, [R4.64+0x18] ; /* 0x0000180804077981 */
/* 0x000ea4000c1e1900 */
/*07a0*/ F2F.F64.F32 R8, R7 ; /* 0x0000000700087310 */
/* 0x004ee40000201800 */
/*07b0*/ DADD R14, R12, R8 ; /* 0x000000000c0e7229 */
/* 0x008e8e0000000008 */
/*07c0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0043e8000c101b08 */
/*07d0*/ LDG.E R16, [R4.64+0x1c] ; /* 0x00001c0804107981 */
/* 0x0004e2000c1e1900 */
/*07e0*/ IADD3 R10, P1, R4, 0x20, RZ ; /* 0x00000020040a7810 */
/* 0x001fe20007f3e0ff */
/*07f0*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0800*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0810*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0820*/ IMAD.X R11, RZ, RZ, R5, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fc400008e0605 */
/*0830*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x004fe400078e000a */
/*0840*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*0850*/ F2F.F64.F32 R8, R16 ; /* 0x0000001000087310 */
/* 0x008e240000201800 */
/*0860*/ DADD R8, R14, R8 ; /* 0x000000000e087229 */
/* 0x001e0e0000000008 */
/*0870*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0013e8000c101b08 */
/*0880*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0890*/ @!P0 BRA 0xa20 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*08a0*/ LDG.E R7, [R4.64] ; /* 0x0000000804077981 */
/* 0x000ea4000c1e1900 */
/*08b0*/ F2F.F64.F32 R10, R7 ; /* 0x00000007000a7310 */
/* 0x004e240000201800 */
/*08c0*/ DADD R10, R10, R8 ; /* 0x000000000a0a7229 */
/* 0x021e0e0000000008 */
/*08d0*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b08 */
/*08e0*/ LDG.E R16, [R4.64+0x4] ; /* 0x0000040804107981 */
/* 0x000ea4000c1e1900 */
/*08f0*/ F2F.F64.F32 R8, R16 ; /* 0x0000001000087310 */
/* 0x006e640000201800 */
/*0900*/ DADD R12, R10, R8 ; /* 0x000000000a0c7229 */
/* 0x002e4e0000000008 */
/*0910*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0023e8000c101b08 */
/*0920*/ LDG.E R17, [R4.64+0x8] ; /* 0x0000080804117981 */
/* 0x000ea4000c1e1900 */
/*0930*/ F2F.F64.F32 R8, R17 ; /* 0x0000001100087310 */
/* 0x004ea40000201800 */
/*0940*/ DADD R14, R12, R8 ; /* 0x000000000c0e7229 */
/* 0x004e8e0000000008 */
/*0950*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0043e8000c101b08 */
/*0960*/ LDG.E R7, [R4.64+0xc] ; /* 0x00000c0804077981 */
/* 0x0004e2000c1e1900 */
/*0970*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*0980*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0990*/ IADD3 R10, P1, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x001fe40007f3e0ff */
/*09a0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc60003f05270 */
/*09b0*/ IMAD.X R11, RZ, RZ, R5, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe400008e0605 */
/*09c0*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x004fe400078e000a */
/*09d0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*09e0*/ F2F.F64.F32 R8, R7 ; /* 0x0000000700087310 */
/* 0x008e240000201800 */
/*09f0*/ DADD R8, R14, R8 ; /* 0x000000000e087229 */
/* 0x001e0e0000000008 */
/*0a00*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0013e4000c101b08 */
/*0a10*/ @P0 BRA 0x8a0 ; /* 0xfffffe8000000947 */
/* 0x002fea000383ffff */
/*0a20*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0a30*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0a40*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000802047981 */
/* 0x000162000c1e1b00 */
/*0a50*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0a60*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0a70*/ UIMAD.WIDE UR4, UR4, UR5, UR6 ; /* 0x00000005040472a5 */
/* 0x000fcc000f8e0206 */
/*0a80*/ IMAD.U32 R8, RZ, RZ, UR4 ; /* 0x00000004ff087e24 */
/* 0x022fe4000f8e00ff */
/*0a90*/ IMAD.U32 R9, RZ, RZ, UR5 ; /* 0x00000005ff097e24 */
/* 0x000fca000f8e00ff */
/*0aa0*/ LDG.E R6, [R8.64] ; /* 0x0000000808067981 */
/* 0x000ea2000c1e1900 */
/*0ab0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0ac0*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc6000ff1e03f */
/*0ad0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0ae0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0af0*/ F2F.F64.F32 R6, R6 ; /* 0x0000000600067310 */
/* 0x004e640000201800 */
/*0b00*/ DADD R4, R6, R4 ; /* 0x0000000006047229 */
/* 0x002e4e0000000004 */
/*0b10*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0023e4000c101b08 */
/*0b20*/ @P0 BRA 0xa80 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0b30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b40*/ BRA 0xb40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7sum_arrPfiPd
.globl _Z7sum_arrPfiPd
.p2align 8
.type _Z7sum_arrPfiPd,@function
_Z7sum_arrPfiPd:
s_load_b32 s4, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b64 s[6:7], s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
.LBB0_2:
s_load_b32 s5, s[0:1], 0x0
s_add_i32 s4, s4, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s4, 0
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[2:3], s5
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], v[2:3]
s_cbranch_scc0 .LBB0_2
v_mov_b32_e32 v2, 0
global_store_b64 v2, v[0:1], s[2:3]
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7sum_arrPfiPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7sum_arrPfiPd, .Lfunc_end0-_Z7sum_arrPfiPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7sum_arrPfiPd
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z7sum_arrPfiPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000139e4_00000000-6_2-b.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15is_power_of_twoi
.type _Z15is_power_of_twoi, @function
_Z15is_power_of_twoi:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
testl %edi, %edi
je .L4
leal -1(%rdi), %eax
testl %edi, %eax
sete %al
.L4:
movzbl %al, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z15is_power_of_twoi, .-_Z15is_power_of_twoi
.globl _Z29__device_stub__Z7sum_arrPfiPdPfiPd
.type _Z29__device_stub__Z7sum_arrPfiPdPfiPd, @function
_Z29__device_stub__Z7sum_arrPfiPdPfiPd:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7sum_arrPfiPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z7sum_arrPfiPdPfiPd, .-_Z29__device_stub__Z7sum_arrPfiPdPfiPd
.globl _Z7sum_arrPfiPd
.type _Z7sum_arrPfiPd, @function
_Z7sum_arrPfiPd:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7sum_arrPfiPdPfiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7sum_arrPfiPd, .-_Z7sum_arrPfiPd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Please call the program with the 2^N array elements to be summed as arguments.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Result is: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %edi, %r12d
subl $1, %r12d
je .L15
movl %edi, %ebx
movq %rsi, %rbp
movl %r12d, %edi
call _Z15is_power_of_twoi
testl %eax, %eax
jne .L16
.L15:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L14:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L24
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movslq %r12d, %rsi
salq $2, %rsi
movq %rsp, %rdi
movl $1, %edx
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $8, %esi
call cudaMallocManaged@PLT
movq 8(%rsp), %rax
movq $0x000000000, (%rax)
testl %r12d, %r12d
jle .L18
leal -1(%rbx), %r13d
salq $2, %r13
movl $0, %ebx
.L19:
movq 8(%rbp,%rbx,2), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
movq (%rsp), %rax
movss %xmm0, (%rax,%rbx)
addq $4, %rbx
cmpq %r13, %rbx
jne .L19
.L18:
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L20:
call cudaDeviceSynchronize@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rax
movsd (%rax), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L14
.L25:
movq 8(%rsp), %rdx
movl %r12d, %esi
movq (%rsp), %rdi
call _Z29__device_stub__Z7sum_arrPfiPdPfiPd
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z7sum_arrPfiPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z7sum_arrPfiPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "2-b.hip"
.globl _Z15is_power_of_twoi # -- Begin function _Z15is_power_of_twoi
.p2align 4, 0x90
.type _Z15is_power_of_twoi,@function
_Z15is_power_of_twoi: # @_Z15is_power_of_twoi
.cfi_startproc
# %bb.0:
# kill: def $edi killed $edi def $rdi
testl %edi, %edi
je .LBB0_1
# %bb.2:
leal -1(%rdi), %ecx
xorl %eax, %eax
testl %ecx, %edi
sete %al
retq
.LBB0_1:
xorl %eax, %eax
retq
.Lfunc_end0:
.size _Z15is_power_of_twoi, .Lfunc_end0-_Z15is_power_of_twoi
.cfi_endproc
# -- End function
.globl _Z22__device_stub__sum_arrPfiPd # -- Begin function _Z22__device_stub__sum_arrPfiPd
.p2align 4, 0x90
.type _Z22__device_stub__sum_arrPfiPd,@function
_Z22__device_stub__sum_arrPfiPd: # @_Z22__device_stub__sum_arrPfiPd
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7sum_arrPfiPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z22__device_stub__sum_arrPfiPd, .Lfunc_end1-_Z22__device_stub__sum_arrPfiPd
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %r14d
leal -1(%r14), %ebp
leal -2(%r14), %eax
movl %ebp, %ecx
xorl %eax, %ecx
cmpl %eax, %ecx
jbe .LBB2_1
# %bb.2:
movq %rsi, %rbx
movslq %ebp, %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $8, %esi
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %rax
movq $0, (%rax)
cmpl $2, %r14d
jl .LBB2_5
# %bb.3: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq 1(%r15), %r12
movq 8(%rbx,%r15,8), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movq 16(%rsp), %rax
movss %xmm0, (%rax,%r15,4)
movq %r12, %r15
cmpq %r12, %r14
jne .LBB2_4
.LBB2_5: # %._crit_edge
xorl %ebx, %ebx
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movl %ebp, 28(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7sum_arrPfiPd, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rax
movsd (%rax), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movb $1, %al
callq printf
jmp .LBB2_8
.LBB2_1:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %ebx
.LBB2_8:
movl %ebx, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7sum_arrPfiPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7sum_arrPfiPd,@object # @_Z7sum_arrPfiPd
.section .rodata,"a",@progbits
.globl _Z7sum_arrPfiPd
.p2align 3, 0x0
_Z7sum_arrPfiPd:
.quad _Z22__device_stub__sum_arrPfiPd
.size _Z7sum_arrPfiPd, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Result is: %f\n"
.size .L.str.1, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7sum_arrPfiPd"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Please call the program with the 2^N array elements to be summed as arguments."
.size .Lstr, 79
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__sum_arrPfiPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7sum_arrPfiPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
#include <assert.h>
__global__ void partial_sum(long num, double *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x, y = threadIdx.y + blockIdx.y * blockDim.y, index = x + y*blockDim.x*gridDim.x;
double sum = 0.0;
double cur = index*num + 1;
for (long i = 0; i < num; ++i) {
sum += 1.0/cur;
cur += 1.0;
}
out[index] = sum;
}
__global__ void add_harmonics(double start, double *partials, long num) {
partials[num] = start;
for (long i = 0; i < num; ++i) {
partials[num] += partials[i];
}
}
int main(int argc, char **argv) {
if (argc < 2) {
printf("usage:\n%s <N_ITERATIONS>\n", *argv);
return -1;
}
dim3 block(32, 8);
long threads_per_block = block.x * block.y, block_w = 6, block_h = 2, blocks = block_w * block_h, threads = threads_per_block*blocks;
long terms = (long)strtod(argv[1], 0), iterations_per_thread = terms/threads, iterations_left = terms%threads;
long bytes = (threads+1) * sizeof(double); // last elem is sum of all
dim3 grid(block_w, block_h);
double *partials, harmonics = 0.0;
for (long i = terms-iterations_left; i <= terms; ++i) {
harmonics += 1.0/i;
}
cudaMalloc(&partials, bytes);
partial_sum <<<grid, block>>> (iterations_per_thread, partials);
cudaDeviceSynchronize();
add_harmonics <<<1, 1>>> (harmonics, partials, threads); // we want to compute the sum of partial sums on the device
cudaMemcpy(&harmonics, partials+threads, sizeof(double), cudaMemcpyDeviceToHost);
cudaFree(partials);
double gamma = harmonics - log(terms);
printf("%.17f\n", gamma);
return 0;
} | code for sm_80
Function : _Z13add_harmonicsdPdl
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe200078e00ff */
/*0050*/ ISETP.GE.U32.AND P0, PT, R0.reuse, 0x1, PT ; /* 0x000000010000780c */
/* 0x040fe20003f06070 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0070*/ LEA R2, P1, R0.reuse, c[0x0][0x168], 0x3 ; /* 0x00005a0000027a11 */
/* 0x040fe400078218ff */
/*0080*/ ISETP.GE.AND.EX P0, PT, R7, RZ, PT, P0 ; /* 0x000000ff0700720c */
/* 0x000fe40003f06300 */
/*0090*/ LEA.HI.X R3, R0, c[0x0][0x16c], R7, 0x3, P1 ; /* 0x00005b0000037a11 */
/* 0x000fca00008f1c07 */
/*00a0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0001ec000c101b08 */
/*00b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R4, P0, R0.reuse, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x041fe20007f1e0ff */
/*00d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00e0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*00f0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*0100*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f26070 */
/*0110*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff067624 */
/* 0x000fe200078e00ff */
/*0120*/ IADD3.X R4, R7, -0x1, RZ, P0, !PT ; /* 0xffffffff07047810 */
/* 0x000fe200007fe4ff */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff077624 */
/* 0x000fe200078e00ff */
/*0140*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc40003f05070 */
/*0150*/ ISETP.GE.U32.AND.EX P1, PT, R4, RZ, PT, P1 ; /* 0x000000ff0400720c */
/* 0x000fe40003f26110 */
/*0160*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fd60003f05300 */
/*0170*/ @!P1 BRA 0x330 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0180*/ IADD3 R14, P1, R0, -c[0x0][0x170], RZ ; /* 0x80005c00000e7a10 */
/* 0x000fe20007f3e0ff */
/*0190*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*01a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*01c0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*01d0*/ IMAD.X R15, RZ, RZ, ~c[0x0][0x174], P1 ; /* 0x80005d00ff0f7624 */
/* 0x000fc600008e06ff */
/*01e0*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000804087981 */
/* 0x000ea4000c1e1b00 */
/*01f0*/ DADD R8, R8, R6 ; /* 0x0000000008087229 */
/* 0x004e0e0000000006 */
/*0200*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0011e8000c101b08 */
/*0210*/ LDG.E.64 R6, [R4.64+0x8] ; /* 0x0000080804067981 */
/* 0x002ea4000c1e1b00 */
/*0220*/ DADD R10, R8, R6 ; /* 0x00000000080a7229 */
/* 0x004e4e0000000006 */
/*0230*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0023e8000c101b08 */
/*0240*/ LDG.E.64 R6, [R4.64+0x10] ; /* 0x0000100804067981 */
/* 0x000ea2000c1e1b00 */
/*0250*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc8000ff1e03f */
/*0260*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0270*/ DADD R12, R10, R6 ; /* 0x000000000a0c7229 */
/* 0x004e8e0000000006 */
/*0280*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0043e8000c101b08 */
/*0290*/ LDG.E.64 R6, [R4.64+0x18] ; /* 0x0000180804067981 */
/* 0x0004e2000c1e1b00 */
/*02a0*/ IADD3 R8, P2, R14, UR4, RZ ; /* 0x000000040e087c10 */
/* 0x001fc8000ff5e0ff */
/*02b0*/ ISETP.NE.U32.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25070 */
/*02c0*/ IADD3.X R8, R15, UR5, RZ, P2, !PT ; /* 0x000000050f087c10 */
/* 0x000fe400097fe4ff */
/*02d0*/ IADD3 R4, P2, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x004fe40007f5e0ff */
/*02e0*/ ISETP.NE.AND.EX P1, PT, R8, RZ, PT, P1 ; /* 0x000000ff0800720c */
/* 0x000fc60003f25310 */
/*02f0*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0300*/ DADD R6, R12, R6 ; /* 0x000000000c067229 */
/* 0x008e0e0000000006 */
/*0310*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0013e4000c101b08 */
/*0320*/ @P1 BRA 0x1e0 ; /* 0xfffffeb000001947 */
/* 0x000fea000383ffff */
/*0330*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0340*/ IADD3 R0, P0, RZ, -R0, RZ ; /* 0x80000000ff007210 */
/* 0x000fe20007f1e0ff */
/*0350*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000a00 */
/*0360*/ ULEA UR6, UP0, UR4, UR6, 0x3 ; /* 0x0000000604067291 */
/* 0x000fe4000f80183f */
/*0370*/ IMAD.X R8, RZ, RZ, -0x1, P0 ; /* 0xffffffffff087424 */
/* 0x000fe400000e06ff */
/*0380*/ ULEA.HI.X UR4, UR4, UR7, UR5, 0x3, UP0 ; /* 0x0000000704047291 */
/* 0x000fc800080f1c05 */
/*0390*/ IMAD.U32 R4, RZ, RZ, UR6 ; /* 0x00000006ff047e24 */
/* 0x000fe4000f8e00ff */
/*03a0*/ IMAD.U32 R5, RZ, RZ, UR4 ; /* 0x00000004ff057e24 */
/* 0x000fcc000f8e00ff */
/*03b0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000ea2000c1e1b00 */
/*03c0*/ IADD3 R0, P0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007f1e0ff */
/*03d0*/ UIADD3 UR6, UP0, UR6, 0x8, URZ ; /* 0x0000000806067890 */
/* 0x000fc8000ff1e03f */
/*03e0*/ IMAD.X R8, RZ, RZ, R8, P0 ; /* 0x000000ffff087224 */
/* 0x000fe200000e0608 */
/*03f0*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05070 */
/*0400*/ UIADD3.X UR4, URZ, UR4, URZ, UP0, !UPT ; /* 0x000000043f047290 */
/* 0x000fc600087fe43f */
/*0410*/ ISETP.NE.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fe20003f05300 */
/*0420*/ DADD R6, R4, R6 ; /* 0x0000000004067229 */
/* 0x007e0e0000000006 */
/*0430*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0011ea000c101b08 */
/*0440*/ @P0 BRA 0x390 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0450*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0460*/ BRA 0x460; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11partial_sumlPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff067624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff087624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0060*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe40003f06070 */
/*0080*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e640000002500 */
/*0090*/ ISETP.GE.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fc40003f06300 */
/*00a0*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*00b0*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fc800078e0203 */
/*00c0*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*00d0*/ IMAD R5, R0, c[0x0][0x0], R7 ; /* 0x0000000000057a24 */
/* 0x004fca00078e0207 */
/*00e0*/ SHF.R.S32.HI R4, RZ, 0x1f, R5 ; /* 0x0000001fff047819 */
/* 0x000fe20000011405 */
/*00f0*/ @!P0 BRA 0x8e0 ; /* 0x000007e000008947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD R0, R4, c[0x0][0x160], RZ ; /* 0x0000580004007a24 */
/* 0x000fe200078e02ff */
/*0110*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*0120*/ IMAD.WIDE.U32 R2, R5, R6, c[0x2][0x0] ; /* 0x0080000005027625 */
/* 0x000fc800078e0006 */
/*0130*/ IMAD R17, R5, c[0x0][0x164], R0 ; /* 0x0000590005117a24 */
/* 0x000fe200078e0200 */
/*0140*/ IADD3 R0, P1, R6, -0x1, RZ ; /* 0xffffffff06007810 */
/* 0x000fe20007f3e0ff */
/*0150*/ IMAD.MOV.U32 R16, RZ, RZ, R2 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0002 */
/*0160*/ IMAD.IADD R17, R3, 0x1, R17 ; /* 0x0000000103117824 */
/* 0x000fe200078e0211 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*0180*/ IADD3.X R0, R8, -0x1, RZ, P1, !PT ; /* 0xffffffff08007810 */
/* 0x000fe40000ffe4ff */
/*0190*/ LOP3.LUT R3, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306037812 */
/* 0x000fe200078ec0ff */
/*01a0*/ I2F.F64.S64 R16, R16 ; /* 0x0000001000107312 */
/* 0x000e220000301c00 */
/*01b0*/ ISETP.GE.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0003f06100 */
/*01c0*/ @!P0 BRA 0x710 ; /* 0x0000054000008947 */
/* 0x000fea0003800000 */
/*01d0*/ IADD3 R2, P0, R3, -c[0x0][0x160], RZ ; /* 0x8000580003027a10 */
/* 0x000fe20007f1e0ff */
/*01e0*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fc8000001ff00 */
/*01f0*/ IMAD.X R0, RZ, RZ, ~c[0x0][0x164], P0 ; /* 0x80005900ff007624 */
/* 0x000fe400000e06ff */
/*0200*/ MUFU.RCP64H R7, R17 ; /* 0x0000001100077308 */
/* 0x009e220000001800 */
/*0210*/ IADD3 R6, R17, 0x300402, RZ ; /* 0x0030040211067810 */
/* 0x000fe20007ffe0ff */
/*0220*/ BSSY B0, 0x350 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0230*/ IADD3 R2, P0, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fe40007f1e0ff */
/*0240*/ FSETP.GEU.AND P1, PT, |R6|, 5.8789094863358348022e-39, PT ; /* 0x004004020600780b */
/* 0x000fc60003f2e200 */
/*0250*/ IMAD.X R0, RZ, RZ, R0, P0 ; /* 0x000000ffff007224 */
/* 0x000fe200000e0600 */
/*0260*/ ISETP.NE.U32.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc80003f05070 */
/*0270*/ ISETP.NE.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fe20003f05300 */
/*0280*/ DFMA R8, R6, -R16, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c0000000810 */
/*0290*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*02a0*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*02b0*/ DFMA R10, R8, -R16, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c0000000810 */
/*02c0*/ DFMA R14, R8, R10, R8 ; /* 0x0000000a080e722b */
/* 0x0010620000000008 */
/*02d0*/ @P1 BRA 0x340 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*02e0*/ LOP3.LUT R12, R17, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff110c7812 */
/* 0x000fe200078ec0ff */
/*02f0*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x001fe200078e0010 */
/*0300*/ MOV R6, 0x340 ; /* 0x0000034000067802 */
/* 0x000fe20000000f00 */
/*0310*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0011 */
/*0320*/ IADD3 R12, R12, -0x100000, RZ ; /* 0xfff000000c0c7810 */
/* 0x000fe40007ffe0ff */
/*0330*/ CALL.REL.NOINC 0x920 ; /* 0x000005e000007944 */
/* 0x002fea0003c00000 */
/*0340*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0350*/ DADD R16, R16, 1 ; /* 0x3ff0000010107429 */
/* 0x000ea20000000000 */
/*0360*/ BSSY B0, 0x480 ; /* 0x0000011000007945 */
/* 0x000fe60003800000 */
/*0370*/ DADD R18, R14, R18 ; /* 0x000000000e127229 */
/* 0x002fe40000000012 */
/*0380*/ MUFU.RCP64H R7, R17 ; /* 0x0000001100077308 */
/* 0x004e680000001800 */
/*0390*/ IADD3 R6, R17, 0x300402, RZ ; /* 0x0030040211067810 */
/* 0x000fc80007ffe0ff */
/*03a0*/ FSETP.GEU.AND P1, PT, |R6|, 5.8789094863358348022e-39, PT ; /* 0x004004020600780b */
/* 0x000fe40003f2e200 */
/*03b0*/ DFMA R8, -R16, R6, 1 ; /* 0x3ff000001008742b */
/* 0x003e0c0000000106 */
/*03c0*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*03d0*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*03e0*/ DFMA R10, -R16, R8, 1 ; /* 0x3ff00000100a742b */
/* 0x001e0c0000000108 */
/*03f0*/ DFMA R14, R8, R10, R8 ; /* 0x0000000a080e722b */
/* 0x0010620000000008 */
/*0400*/ @P1 BRA 0x470 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0410*/ LOP3.LUT R12, R17, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff110c7812 */
/* 0x000fe200078ec0ff */
/*0420*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x001fe200078e0010 */
/*0430*/ MOV R6, 0x470 ; /* 0x0000047000067802 */
/* 0x000fe20000000f00 */
/*0440*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0011 */
/*0450*/ IADD3 R12, R12, -0x100000, RZ ; /* 0xfff000000c0c7810 */
/* 0x000fe40007ffe0ff */
/*0460*/ CALL.REL.NOINC 0x920 ; /* 0x000004b000007944 */
/* 0x002fea0003c00000 */
/*0470*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0480*/ DADD R16, R16, 1 ; /* 0x3ff0000010107429 */
/* 0x000ea20000000000 */
/*0490*/ BSSY B0, 0x5b0 ; /* 0x0000011000007945 */
/* 0x000fe60003800000 */
/*04a0*/ DADD R18, R18, R14 ; /* 0x0000000012127229 */
/* 0x002fe4000000000e */
/*04b0*/ MUFU.RCP64H R7, R17 ; /* 0x0000001100077308 */
/* 0x004e680000001800 */
/*04c0*/ IADD3 R6, R17, 0x300402, RZ ; /* 0x0030040211067810 */
/* 0x000fc80007ffe0ff */
/*04d0*/ FSETP.GEU.AND P1, PT, |R6|, 5.8789094863358348022e-39, PT ; /* 0x004004020600780b */
/* 0x000fe40003f2e200 */
/*04e0*/ DFMA R8, -R16, R6, 1 ; /* 0x3ff000001008742b */
/* 0x003e0c0000000106 */
/*04f0*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0500*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*0510*/ DFMA R10, -R16, R8, 1 ; /* 0x3ff00000100a742b */
/* 0x001e0c0000000108 */
/*0520*/ DFMA R14, R8, R10, R8 ; /* 0x0000000a080e722b */
/* 0x0010620000000008 */
/*0530*/ @P1 BRA 0x5a0 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0540*/ LOP3.LUT R12, R17, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff110c7812 */
/* 0x000fe200078ec0ff */
/*0550*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x001fe200078e0010 */
/*0560*/ MOV R6, 0x5a0 ; /* 0x000005a000067802 */
/* 0x000fe20000000f00 */
/*0570*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0011 */
/*0580*/ IADD3 R12, R12, -0x100000, RZ ; /* 0xfff000000c0c7810 */
/* 0x000fe40007ffe0ff */
/*0590*/ CALL.REL.NOINC 0x920 ; /* 0x0000038000007944 */
/* 0x002fea0003c00000 */
/*05a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05b0*/ DADD R16, R16, 1 ; /* 0x3ff0000010107429 */
/* 0x000ea20000000000 */
/*05c0*/ BSSY B0, 0x6e0 ; /* 0x0000011000007945 */
/* 0x000fe60003800000 */
/*05d0*/ DADD R18, R18, R14 ; /* 0x0000000012127229 */
/* 0x002fe4000000000e */
/*05e0*/ MUFU.RCP64H R7, R17 ; /* 0x0000001100077308 */
/* 0x004e680000001800 */
/*05f0*/ IADD3 R6, R17, 0x300402, RZ ; /* 0x0030040211067810 */
/* 0x000fc80007ffe0ff */
/*0600*/ FSETP.GEU.AND P1, PT, |R6|, 5.8789094863358348022e-39, PT ; /* 0x004004020600780b */
/* 0x000fe40003f2e200 */
/*0610*/ DFMA R8, -R16, R6, 1 ; /* 0x3ff000001008742b */
/* 0x003e0c0000000106 */
/*0620*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0630*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*0640*/ DFMA R10, -R16, R8, 1 ; /* 0x3ff00000100a742b */
/* 0x001e0c0000000108 */
/*0650*/ DFMA R14, R8, R10, R8 ; /* 0x0000000a080e722b */
/* 0x0010620000000008 */
/*0660*/ @P1 BRA 0x6d0 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0670*/ LOP3.LUT R12, R17, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff110c7812 */
/* 0x000fe200078ec0ff */
/*0680*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x001fe200078e0010 */
/*0690*/ MOV R6, 0x6d0 ; /* 0x000006d000067802 */
/* 0x000fe20000000f00 */
/*06a0*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0011 */
/*06b0*/ IADD3 R12, R12, -0x100000, RZ ; /* 0xfff000000c0c7810 */
/* 0x000fe40007ffe0ff */
/*06c0*/ CALL.REL.NOINC 0x920 ; /* 0x0000025000007944 */
/* 0x002fea0003c00000 */
/*06d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06e0*/ DADD R18, R18, R14 ; /* 0x0000000012127229 */
/* 0x002288000000000e */
/*06f0*/ DADD R16, R16, 1 ; /* 0x3ff0000010107429 */
/* 0x000ee20000000000 */
/*0700*/ @P0 BRA 0x200 ; /* 0xfffffaf000000947 */
/* 0x006ff0000383ffff */
/*0710*/ ISETP.NE.U32.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc80003f05070 */
/*0720*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05300 */
/*0730*/ @!P0 BRA 0x8e0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0740*/ IADD3 R3, P0, RZ, -R3, RZ ; /* 0x80000003ff037210 */
/* 0x000fca0007f1e0ff */
/*0750*/ IMAD.X R0, RZ, RZ, -0x1, P0 ; /* 0xffffffffff007424 */
/* 0x000fe400000e06ff */
/*0760*/ MUFU.RCP64H R7, R17 ; /* 0x0000001100077308 */
/* 0x009e220000001800 */
/*0770*/ IADD3 R6, R17, 0x300402, RZ ; /* 0x0030040211067810 */
/* 0x000fe20007ffe0ff */
/*0780*/ BSSY B0, 0x8b0 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0790*/ IADD3 R3, P0, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe40007f1e0ff */
/*07a0*/ FSETP.GEU.AND P1, PT, |R6|, 5.8789094863358348022e-39, PT ; /* 0x004004020600780b */
/* 0x000fc60003f2e200 */
/*07b0*/ IMAD.X R0, RZ, RZ, R0, P0 ; /* 0x000000ffff007224 */
/* 0x000fe200000e0600 */
/*07c0*/ ISETP.NE.U32.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc80003f05070 */
/*07d0*/ ISETP.NE.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fe20003f05300 */
/*07e0*/ DFMA R8, R6, -R16, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c0000000810 */
/*07f0*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0800*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*0810*/ DFMA R10, R8, -R16, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c0000000810 */
/*0820*/ DFMA R14, R8, R10, R8 ; /* 0x0000000a080e722b */
/* 0x0010620000000008 */
/*0830*/ @P1 BRA 0x8a0 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0840*/ LOP3.LUT R12, R17, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff110c7812 */
/* 0x000fe200078ec0ff */
/*0850*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x001fe200078e0010 */
/*0860*/ MOV R6, 0x8a0 ; /* 0x000008a000067802 */
/* 0x000fe20000000f00 */
/*0870*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0011 */
/*0880*/ IADD3 R12, R12, -0x100000, RZ ; /* 0xfff000000c0c7810 */
/* 0x000fe40007ffe0ff */
/*0890*/ CALL.REL.NOINC 0x920 ; /* 0x0000008000007944 */
/* 0x002fea0003c00000 */
/*08a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08b0*/ DADD R18, R14, R18 ; /* 0x000000000e127229 */
/* 0x0022880000000012 */
/*08c0*/ DADD R16, R16, 1 ; /* 0x3ff0000010107429 */
/* 0x000ee20000000000 */
/*08d0*/ @P0 BRA 0x760 ; /* 0xfffffe8000000947 */
/* 0x006ff0000383ffff */
/*08e0*/ LEA R2, P0, R5, c[0x0][0x168], 0x3 ; /* 0x00005a0005027a11 */
/* 0x000fc800078018ff */
/*08f0*/ LEA.HI.X R3, R5, c[0x0][0x16c], R4, 0x3, P0 ; /* 0x00005b0005037a11 */
/* 0x000fca00000f1c04 */
/*0900*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x000fe2000c101b04 */
/*0910*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0920*/ DSETP.GTU.AND P1, PT, |R8|, +INF , PT ; /* 0x7ff000000800742a */
/* 0x000e220003f2c200 */
/*0930*/ BSSY B1, 0xb70 ; /* 0x0000023000017945 */
/* 0x000fda0003800000 */
/*0940*/ @P1 BRA 0xb40 ; /* 0x000001f000001947 */
/* 0x001fea0003800000 */
/*0950*/ LOP3.LUT R7, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09077812 */
/* 0x000fc800078ec0ff */
/*0960*/ IADD3 R10, R7, -0x1, RZ ; /* 0xffffffff070a7810 */
/* 0x000fc80007ffe0ff */
/*0970*/ ISETP.GE.U32.AND P1, PT, R10, 0x7fefffff, PT ; /* 0x7fefffff0a00780c */
/* 0x000fda0003f26070 */
/*0980*/ @P1 LOP3.LUT R15, R9, 0x7ff00000, RZ, 0x3c, !PT ; /* 0x7ff00000090f1812 */
/* 0x000fe200078e3cff */
/*0990*/ @P1 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e1224 */
/* 0x000fe200078e00ff */
/*09a0*/ @P1 BRA 0xb60 ; /* 0x000001b000001947 */
/* 0x000fea0003800000 */
/*09b0*/ ISETP.GE.U32.AND P1, PT, R7, 0x1000001, PT ; /* 0x010000010700780c */
/* 0x000fda0003f26070 */
/*09c0*/ @!P1 BRA 0xaa0 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*09d0*/ IADD3 R11, R9, -0x3fe00000, RZ ; /* 0xc0200000090b7810 */
/* 0x000fe20007ffe0ff */
/*09e0*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e0008 */
/*09f0*/ MUFU.RCP64H R13, R11 ; /* 0x0000000b000d7308 */
/* 0x000e260000001800 */
/*0a00*/ DFMA R14, -R10, R12, 1 ; /* 0x3ff000000a0e742b */
/* 0x001e0c000000010c */
/*0a10*/ DFMA R14, R14, R14, R14 ; /* 0x0000000e0e0e722b */
/* 0x001e0c000000000e */
/*0a20*/ DFMA R14, R12, R14, R12 ; /* 0x0000000e0c0e722b */
/* 0x001e0c000000000c */
/*0a30*/ DFMA R12, -R10, R14, 1 ; /* 0x3ff000000a0c742b */
/* 0x001e0c000000010e */
/*0a40*/ DFMA R14, R14, R12, R14 ; /* 0x0000000c0e0e722b */
/* 0x001e0c000000000e */
/*0a50*/ DMUL R14, R14, 2.2250738585072013831e-308 ; /* 0x001000000e0e7828 */
/* 0x001e0c0000000000 */
/*0a60*/ DFMA R8, -R8, R14, 1 ; /* 0x3ff000000808742b */
/* 0x001e0c000000010e */
/*0a70*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0a80*/ DFMA R14, R14, R8, R14 ; /* 0x000000080e0e722b */
/* 0x001062000000000e */
/*0a90*/ BRA 0xb60 ; /* 0x000000c000007947 */
/* 0x000fea0003800000 */
/*0aa0*/ DMUL R10, R8, 8.11296384146066816958e+31 ; /* 0x46900000080a7828 */
/* 0x0000640000000000 */
/*0ab0*/ IMAD.MOV.U32 R8, RZ, RZ, R12 ; /* 0x000000ffff087224 */
/* 0x001fc800078e000c */
/*0ac0*/ MUFU.RCP64H R9, R11 ; /* 0x0000000b00097308 */
/* 0x002e240000001800 */
/*0ad0*/ DFMA R12, -R10, R8, 1 ; /* 0x3ff000000a0c742b */
/* 0x001e0c0000000108 */
/*0ae0*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*0af0*/ DFMA R12, R8, R12, R8 ; /* 0x0000000c080c722b */
/* 0x001e0c0000000008 */
/*0b00*/ DFMA R8, -R10, R12, 1 ; /* 0x3ff000000a08742b */
/* 0x001e0c000000010c */
/*0b10*/ DFMA R8, R12, R8, R12 ; /* 0x000000080c08722b */
/* 0x001e0c000000000c */
/*0b20*/ DMUL R14, R8, 8.11296384146066816958e+31 ; /* 0x46900000080e7828 */
/* 0x0010620000000000 */
/*0b30*/ BRA 0xb60 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0b40*/ LOP3.LUT R15, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090f7812 */
/* 0x000fe200078efcff */
/*0b50*/ IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0008 */
/*0b60*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0b70*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*0b80*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff47006007950 */
/* 0x000fea0003c3ffff */
/*0b90*/ BRA 0xb90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
#include <assert.h>
__global__ void partial_sum(long num, double *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x, y = threadIdx.y + blockIdx.y * blockDim.y, index = x + y*blockDim.x*gridDim.x;
double sum = 0.0;
double cur = index*num + 1;
for (long i = 0; i < num; ++i) {
sum += 1.0/cur;
cur += 1.0;
}
out[index] = sum;
}
__global__ void add_harmonics(double start, double *partials, long num) {
partials[num] = start;
for (long i = 0; i < num; ++i) {
partials[num] += partials[i];
}
}
int main(int argc, char **argv) {
if (argc < 2) {
printf("usage:\n%s <N_ITERATIONS>\n", *argv);
return -1;
}
dim3 block(32, 8);
long threads_per_block = block.x * block.y, block_w = 6, block_h = 2, blocks = block_w * block_h, threads = threads_per_block*blocks;
long terms = (long)strtod(argv[1], 0), iterations_per_thread = terms/threads, iterations_left = terms%threads;
long bytes = (threads+1) * sizeof(double); // last elem is sum of all
dim3 grid(block_w, block_h);
double *partials, harmonics = 0.0;
for (long i = terms-iterations_left; i <= terms; ++i) {
harmonics += 1.0/i;
}
cudaMalloc(&partials, bytes);
partial_sum <<<grid, block>>> (iterations_per_thread, partials);
cudaDeviceSynchronize();
add_harmonics <<<1, 1>>> (harmonics, partials, threads); // we want to compute the sum of partial sums on the device
cudaMemcpy(&harmonics, partials+threads, sizeof(double), cudaMemcpyDeviceToHost);
cudaFree(partials);
double gamma = harmonics - log(terms);
printf("%.17f\n", gamma);
return 0;
} | .file "tmpxft_000682db_00000000-6_eulerm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11partial_sumlPdlPd
.type _Z32__device_stub__Z11partial_sumlPdlPd, @function
_Z32__device_stub__Z11partial_sumlPdlPd:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11partial_sumlPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z11partial_sumlPdlPd, .-_Z32__device_stub__Z11partial_sumlPdlPd
.globl _Z11partial_sumlPd
.type _Z11partial_sumlPd, @function
_Z11partial_sumlPd:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11partial_sumlPdlPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11partial_sumlPd, .-_Z11partial_sumlPd
.globl _Z35__device_stub__Z13add_harmonicsdPdldPdl
.type _Z35__device_stub__Z13add_harmonicsdPdldPdl, @function
_Z35__device_stub__Z13add_harmonicsdPdldPdl:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movsd %xmm0, 24(%rsp)
movq %rdi, 16(%rsp)
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13add_harmonicsdPdl(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z13add_harmonicsdPdldPdl, .-_Z35__device_stub__Z13add_harmonicsdPdldPdl
.globl _Z13add_harmonicsdPdl
.type _Z13add_harmonicsdPdl, @function
_Z13add_harmonicsdPdl:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13add_harmonicsdPdldPdl
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13add_harmonicsdPdl, .-_Z13add_harmonicsdPdl
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "usage:\n%s <N_ITERATIONS>\n"
.LC3:
.string "%.17f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L31
movl $1, 32(%rsp)
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
cvttsd2siq %xmm0, %rbx
movl $6, 36(%rsp)
movl $2, 40(%rsp)
movl $1, 44(%rsp)
movabsq $3074457345618258603, %rdx
movq %rbx, %rax
imulq %rdx
sarq $9, %rdx
movq %rbx, %rax
sarq $63, %rax
subq %rax, %rdx
leaq (%rdx,%rdx,2), %rax
salq $10, %rax
leaq 1(%rbx), %rdx
pxor %xmm0, %xmm0
movsd .LC2(%rip), %xmm3
cmpq %rax, %rbx
jl .L32
.L24:
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
movapd %xmm3, %xmm1
divsd %xmm2, %xmm1
addsd %xmm1, %xmm0
addq $1, %rax
cmpq %rax, %rdx
jne .L24
movsd %xmm0, 16(%rsp)
.L23:
leaq 8(%rsp), %rdi
movl $24584, %esi
call cudaMalloc@PLT
movl $32, 24(%rsp)
movl $8, 28(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L25:
call cudaDeviceSynchronize@PLT
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L26:
movq 8(%rsp), %rax
leaq 24576(%rax), %rsi
leaq 16(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rbp
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
call log@PLT
movapd %xmm0, %xmm1
movq %rbp, %xmm0
subsd %xmm1, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
.L19:
movq 72(%rsp), %rdx
subq %fs:40, %rdx
jne .L35
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq (%rsi), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %eax
jmp .L19
.L32:
movsd %xmm0, 16(%rsp)
jmp .L23
.L33:
movl $3072, %ecx
movq %rbx, %rax
cqto
idivq %rcx
movq %rax, %rdi
movq 8(%rsp), %rsi
call _Z32__device_stub__Z11partial_sumlPdlPd
jmp .L25
.L34:
movl $3072, %esi
movq 8(%rsp), %rdi
movsd 16(%rsp), %xmm0
call _Z35__device_stub__Z13add_harmonicsdPdldPdl
jmp .L26
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z13add_harmonicsdPdl"
.LC5:
.string "_Z11partial_sumlPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13add_harmonicsdPdl(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z11partial_sumlPd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
#include <assert.h>
__global__ void partial_sum(long num, double *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x, y = threadIdx.y + blockIdx.y * blockDim.y, index = x + y*blockDim.x*gridDim.x;
double sum = 0.0;
double cur = index*num + 1;
for (long i = 0; i < num; ++i) {
sum += 1.0/cur;
cur += 1.0;
}
out[index] = sum;
}
__global__ void add_harmonics(double start, double *partials, long num) {
partials[num] = start;
for (long i = 0; i < num; ++i) {
partials[num] += partials[i];
}
}
int main(int argc, char **argv) {
if (argc < 2) {
printf("usage:\n%s <N_ITERATIONS>\n", *argv);
return -1;
}
dim3 block(32, 8);
long threads_per_block = block.x * block.y, block_w = 6, block_h = 2, blocks = block_w * block_h, threads = threads_per_block*blocks;
long terms = (long)strtod(argv[1], 0), iterations_per_thread = terms/threads, iterations_left = terms%threads;
long bytes = (threads+1) * sizeof(double); // last elem is sum of all
dim3 grid(block_w, block_h);
double *partials, harmonics = 0.0;
for (long i = terms-iterations_left; i <= terms; ++i) {
harmonics += 1.0/i;
}
cudaMalloc(&partials, bytes);
partial_sum <<<grid, block>>> (iterations_per_thread, partials);
cudaDeviceSynchronize();
add_harmonics <<<1, 1>>> (harmonics, partials, threads); // we want to compute the sum of partial sums on the device
cudaMemcpy(&harmonics, partials+threads, sizeof(double), cudaMemcpyDeviceToHost);
cudaFree(partials);
double gamma = harmonics - log(terms);
printf("%.17f\n", gamma);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <assert.h>
__global__ void partial_sum(long num, double *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x, y = threadIdx.y + blockIdx.y * blockDim.y, index = x + y*blockDim.x*gridDim.x;
double sum = 0.0;
double cur = index*num + 1;
for (long i = 0; i < num; ++i) {
sum += 1.0/cur;
cur += 1.0;
}
out[index] = sum;
}
__global__ void add_harmonics(double start, double *partials, long num) {
partials[num] = start;
for (long i = 0; i < num; ++i) {
partials[num] += partials[i];
}
}
int main(int argc, char **argv) {
if (argc < 2) {
printf("usage:\n%s <N_ITERATIONS>\n", *argv);
return -1;
}
dim3 block(32, 8);
long threads_per_block = block.x * block.y, block_w = 6, block_h = 2, blocks = block_w * block_h, threads = threads_per_block*blocks;
long terms = (long)strtod(argv[1], 0), iterations_per_thread = terms/threads, iterations_left = terms%threads;
long bytes = (threads+1) * sizeof(double); // last elem is sum of all
dim3 grid(block_w, block_h);
double *partials, harmonics = 0.0;
for (long i = terms-iterations_left; i <= terms; ++i) {
harmonics += 1.0/i;
}
hipMalloc(&partials, bytes);
partial_sum <<<grid, block>>> (iterations_per_thread, partials);
hipDeviceSynchronize();
add_harmonics <<<1, 1>>> (harmonics, partials, threads); // we want to compute the sum of partial sums on the device
hipMemcpy(&harmonics, partials+threads, sizeof(double), hipMemcpyDeviceToHost);
hipFree(partials);
double gamma = harmonics - log(terms);
printf("%.17f\n", gamma);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <assert.h>
__global__ void partial_sum(long num, double *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x, y = threadIdx.y + blockIdx.y * blockDim.y, index = x + y*blockDim.x*gridDim.x;
double sum = 0.0;
double cur = index*num + 1;
for (long i = 0; i < num; ++i) {
sum += 1.0/cur;
cur += 1.0;
}
out[index] = sum;
}
__global__ void add_harmonics(double start, double *partials, long num) {
partials[num] = start;
for (long i = 0; i < num; ++i) {
partials[num] += partials[i];
}
}
int main(int argc, char **argv) {
if (argc < 2) {
printf("usage:\n%s <N_ITERATIONS>\n", *argv);
return -1;
}
dim3 block(32, 8);
long threads_per_block = block.x * block.y, block_w = 6, block_h = 2, blocks = block_w * block_h, threads = threads_per_block*blocks;
long terms = (long)strtod(argv[1], 0), iterations_per_thread = terms/threads, iterations_left = terms%threads;
long bytes = (threads+1) * sizeof(double); // last elem is sum of all
dim3 grid(block_w, block_h);
double *partials, harmonics = 0.0;
for (long i = terms-iterations_left; i <= terms; ++i) {
harmonics += 1.0/i;
}
hipMalloc(&partials, bytes);
partial_sum <<<grid, block>>> (iterations_per_thread, partials);
hipDeviceSynchronize();
add_harmonics <<<1, 1>>> (harmonics, partials, threads); // we want to compute the sum of partial sums on the device
hipMemcpy(&harmonics, partials+threads, sizeof(double), hipMemcpyDeviceToHost);
hipFree(partials);
double gamma = harmonics - log(terms);
printf("%.17f\n", gamma);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11partial_sumlPd
.globl _Z11partial_sumlPd
.p2align 8
.type _Z11partial_sumlPd,@function
_Z11partial_sumlPd:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s5, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s6, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s5, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
v_cmp_lt_i64_e64 s4, s[2:3], 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_and_b32 vcc_lo, exec_lo, s4
v_ashrrev_i32_e32 v1, 31, v0
s_cbranch_vccnz .LBB0_3
v_mad_u64_u32 v[2:3], null, v0, s2, 1
v_mul_lo_u32 v4, v0, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v1, s2
v_add3_u32 v3, v5, v3, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_u32_e32 v[5:6], v2
v_cvt_f64_i32_e32 v[3:4], v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[3:4], v[3:4], 32
v_add_f64 v[4:5], v[3:4], v[5:6]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], 1.0
v_div_scale_f64 v[12:13], vcc_lo, 1.0, v[4:5], 1.0
s_add_u32 s2, s2, -1
s_addc_u32 s3, s3, -1
s_cmp_eq_u64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[12:13], v[8:9]
v_fma_f64 v[6:7], -v[6:7], v[10:11], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[10:11]
v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
v_add_f64 v[4:5], v[4:5], 1.0
s_delay_alu instid0(VALU_DEP_2)
v_add_f64 v[2:3], v[2:3], v[6:7]
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11partial_sumlPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11partial_sumlPd, .Lfunc_end0-_Z11partial_sumlPd
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13add_harmonicsdPdl
.globl _Z13add_harmonicsdPdl
.p2align 8
.type _Z13add_harmonicsdPdl,@function
_Z13add_harmonicsdPdl:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_cmp_lt_i64_e64 s8, s[4:5], 1
v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
s_lshl_b64 s[6:7], s[4:5], 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
s_add_u32 s0, s2, s6
s_addc_u32 s1, s3, s7
s_and_b32 vcc_lo, exec_lo, s8
global_store_b64 v2, v[0:1], s[0:1]
s_cbranch_vccnz .LBB1_3
global_load_b64 v[0:1], v2, s[0:1]
.LBB1_2:
global_load_b64 v[3:4], v2, s[2:3]
s_add_u32 s4, s4, -1
s_addc_u32 s5, s5, -1
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_cmp_eq_u64 s[4:5], 0
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[3:4], v[0:1]
global_store_b64 v2, v[0:1], s[0:1]
s_cbranch_scc0 .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13add_harmonicsdPdl
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 9
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13add_harmonicsdPdl, .Lfunc_end1-_Z13add_harmonicsdPdl
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11partial_sumlPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11partial_sumlPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13add_harmonicsdPdl
.private_segment_fixed_size: 0
.sgpr_count: 11
.sgpr_spill_count: 0
.symbol: _Z13add_harmonicsdPdl.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <assert.h>
__global__ void partial_sum(long num, double *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x, y = threadIdx.y + blockIdx.y * blockDim.y, index = x + y*blockDim.x*gridDim.x;
double sum = 0.0;
double cur = index*num + 1;
for (long i = 0; i < num; ++i) {
sum += 1.0/cur;
cur += 1.0;
}
out[index] = sum;
}
__global__ void add_harmonics(double start, double *partials, long num) {
partials[num] = start;
for (long i = 0; i < num; ++i) {
partials[num] += partials[i];
}
}
int main(int argc, char **argv) {
if (argc < 2) {
printf("usage:\n%s <N_ITERATIONS>\n", *argv);
return -1;
}
dim3 block(32, 8);
long threads_per_block = block.x * block.y, block_w = 6, block_h = 2, blocks = block_w * block_h, threads = threads_per_block*blocks;
long terms = (long)strtod(argv[1], 0), iterations_per_thread = terms/threads, iterations_left = terms%threads;
long bytes = (threads+1) * sizeof(double); // last elem is sum of all
dim3 grid(block_w, block_h);
double *partials, harmonics = 0.0;
for (long i = terms-iterations_left; i <= terms; ++i) {
harmonics += 1.0/i;
}
hipMalloc(&partials, bytes);
partial_sum <<<grid, block>>> (iterations_per_thread, partials);
hipDeviceSynchronize();
add_harmonics <<<1, 1>>> (harmonics, partials, threads); // we want to compute the sum of partial sums on the device
hipMemcpy(&harmonics, partials+threads, sizeof(double), hipMemcpyDeviceToHost);
hipFree(partials);
double gamma = harmonics - log(terms);
printf("%.17f\n", gamma);
return 0;
} | .text
.file "eulerm.hip"
.globl _Z26__device_stub__partial_sumlPd # -- Begin function _Z26__device_stub__partial_sumlPd
.p2align 4, 0x90
.type _Z26__device_stub__partial_sumlPd,@function
_Z26__device_stub__partial_sumlPd: # @_Z26__device_stub__partial_sumlPd
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11partial_sumlPd, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__partial_sumlPd, .Lfunc_end0-_Z26__device_stub__partial_sumlPd
.cfi_endproc
# -- End function
.globl _Z28__device_stub__add_harmonicsdPdl # -- Begin function _Z28__device_stub__add_harmonicsdPdl
.p2align 4, 0x90
.type _Z28__device_stub__add_harmonicsdPdl,@function
_Z28__device_stub__add_harmonicsdPdl: # @_Z28__device_stub__add_harmonicsdPdl
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movsd %xmm0, 72(%rsp)
movq %rdi, 64(%rsp)
movq %rsi, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13add_harmonicsdPdl, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z28__device_stub__add_harmonicsdPdl, .Lfunc_end1-_Z28__device_stub__add_harmonicsdPdl
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
cmpl $1, %edi
jg .LBB2_2
# %bb.1:
movq (%rsi), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $-1, %r14d
jmp .LBB2_9
.LBB2_2:
movq 8(%rsi), %rdi
xorl %esi, %esi
callq strtod
cvttsd2si %xmm0, %rbx
movabsq $3074457345618258603, %rcx # imm = 0x2AAAAAAAAAAAAAAB
movq %rbx, %rax
imulq %rcx
movq %rdx, %r14
movq %rdx, %rax
shrq $63, %rax
sarq $9, %r14
addq %rax, %r14
movq %r14, %rax
shlq $10, %rax
leaq (%rax,%rax,2), %rax
movq %rbx, %rcx
subq %rax, %rcx
movq $0, (%rsp)
js .LBB2_3
# %bb.10: # %.lr.ph.preheader
movq %rbx, %rax
subq %rcx, %rax
xorpd %xmm0, %xmm0
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB2_11: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm2, %xmm2
cvtsi2sd %rax, %xmm2
movapd %xmm1, %xmm3
divsd %xmm2, %xmm3
addsd %xmm3, %xmm0
leaq 1(%rax), %rcx
cmpq %rbx, %rax
movq %rcx, %rax
jl .LBB2_11
jmp .LBB2_4
.LBB2_3:
xorpd %xmm0, %xmm0
.LBB2_4: # %._crit_edge
movsd %xmm0, (%rsp)
leaq 8(%rsp), %rdi
movl $24584, %esi # imm = 0x6008
callq hipMalloc
movabsq $8589934598, %rdi # imm = 0x200000006
movabsq $34359738400, %rdx # imm = 0x800000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 8(%rsp), %rax
movq %r14, 72(%rsp)
movq %rax, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11partial_sumlPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
callq hipDeviceSynchronize
xorl %r14d, %r14d
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movsd (%rsp), %xmm0 # xmm0 = mem[0],zero
movq 8(%rsp), %rax
movsd %xmm0, 72(%rsp)
movq %rax, 64(%rsp)
movq $3072, 56(%rsp) # imm = 0xC00
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13add_harmonicsdPdl, %edi
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
movl $24576, %esi # imm = 0x6000
addq 8(%rsp), %rsi
movq %rsp, %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movsd (%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 104(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sd %rbx, %xmm0
callq log
movsd 104(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
subsd %xmm0, %xmm1
movl $.L.str.1, %edi
movapd %xmm1, %xmm0
movb $1, %al
callq printf
.LBB2_9:
movl %r14d, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11partial_sumlPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13add_harmonicsdPdl, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11partial_sumlPd,@object # @_Z11partial_sumlPd
.section .rodata,"a",@progbits
.globl _Z11partial_sumlPd
.p2align 3, 0x0
_Z11partial_sumlPd:
.quad _Z26__device_stub__partial_sumlPd
.size _Z11partial_sumlPd, 8
.type _Z13add_harmonicsdPdl,@object # @_Z13add_harmonicsdPdl
.globl _Z13add_harmonicsdPdl
.p2align 3, 0x0
_Z13add_harmonicsdPdl:
.quad _Z28__device_stub__add_harmonicsdPdl
.size _Z13add_harmonicsdPdl, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "usage:\n%s <N_ITERATIONS>\n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%.17f\n"
.size .L.str.1, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11partial_sumlPd"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13add_harmonicsdPdl"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__partial_sumlPd
.addrsig_sym _Z28__device_stub__add_harmonicsdPdl
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11partial_sumlPd
.addrsig_sym _Z13add_harmonicsdPdl
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13add_harmonicsdPdl
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe200078e00ff */
/*0050*/ ISETP.GE.U32.AND P0, PT, R0.reuse, 0x1, PT ; /* 0x000000010000780c */
/* 0x040fe20003f06070 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0070*/ LEA R2, P1, R0.reuse, c[0x0][0x168], 0x3 ; /* 0x00005a0000027a11 */
/* 0x040fe400078218ff */
/*0080*/ ISETP.GE.AND.EX P0, PT, R7, RZ, PT, P0 ; /* 0x000000ff0700720c */
/* 0x000fe40003f06300 */
/*0090*/ LEA.HI.X R3, R0, c[0x0][0x16c], R7, 0x3, P1 ; /* 0x00005b0000037a11 */
/* 0x000fca00008f1c07 */
/*00a0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0001ec000c101b08 */
/*00b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R4, P0, R0.reuse, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x041fe20007f1e0ff */
/*00d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00e0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*00f0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*0100*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f26070 */
/*0110*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff067624 */
/* 0x000fe200078e00ff */
/*0120*/ IADD3.X R4, R7, -0x1, RZ, P0, !PT ; /* 0xffffffff07047810 */
/* 0x000fe200007fe4ff */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff077624 */
/* 0x000fe200078e00ff */
/*0140*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc40003f05070 */
/*0150*/ ISETP.GE.U32.AND.EX P1, PT, R4, RZ, PT, P1 ; /* 0x000000ff0400720c */
/* 0x000fe40003f26110 */
/*0160*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fd60003f05300 */
/*0170*/ @!P1 BRA 0x330 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0180*/ IADD3 R14, P1, R0, -c[0x0][0x170], RZ ; /* 0x80005c00000e7a10 */
/* 0x000fe20007f3e0ff */
/*0190*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*01a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*01c0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*01d0*/ IMAD.X R15, RZ, RZ, ~c[0x0][0x174], P1 ; /* 0x80005d00ff0f7624 */
/* 0x000fc600008e06ff */
/*01e0*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000804087981 */
/* 0x000ea4000c1e1b00 */
/*01f0*/ DADD R8, R8, R6 ; /* 0x0000000008087229 */
/* 0x004e0e0000000006 */
/*0200*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0011e8000c101b08 */
/*0210*/ LDG.E.64 R6, [R4.64+0x8] ; /* 0x0000080804067981 */
/* 0x002ea4000c1e1b00 */
/*0220*/ DADD R10, R8, R6 ; /* 0x00000000080a7229 */
/* 0x004e4e0000000006 */
/*0230*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0023e8000c101b08 */
/*0240*/ LDG.E.64 R6, [R4.64+0x10] ; /* 0x0000100804067981 */
/* 0x000ea2000c1e1b00 */
/*0250*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc8000ff1e03f */
/*0260*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0270*/ DADD R12, R10, R6 ; /* 0x000000000a0c7229 */
/* 0x004e8e0000000006 */
/*0280*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0043e8000c101b08 */
/*0290*/ LDG.E.64 R6, [R4.64+0x18] ; /* 0x0000180804067981 */
/* 0x0004e2000c1e1b00 */
/*02a0*/ IADD3 R8, P2, R14, UR4, RZ ; /* 0x000000040e087c10 */
/* 0x001fc8000ff5e0ff */
/*02b0*/ ISETP.NE.U32.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25070 */
/*02c0*/ IADD3.X R8, R15, UR5, RZ, P2, !PT ; /* 0x000000050f087c10 */
/* 0x000fe400097fe4ff */
/*02d0*/ IADD3 R4, P2, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x004fe40007f5e0ff */
/*02e0*/ ISETP.NE.AND.EX P1, PT, R8, RZ, PT, P1 ; /* 0x000000ff0800720c */
/* 0x000fc60003f25310 */
/*02f0*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0300*/ DADD R6, R12, R6 ; /* 0x000000000c067229 */
/* 0x008e0e0000000006 */
/*0310*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0013e4000c101b08 */
/*0320*/ @P1 BRA 0x1e0 ; /* 0xfffffeb000001947 */
/* 0x000fea000383ffff */
/*0330*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0340*/ IADD3 R0, P0, RZ, -R0, RZ ; /* 0x80000000ff007210 */
/* 0x000fe20007f1e0ff */
/*0350*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000a00 */
/*0360*/ ULEA UR6, UP0, UR4, UR6, 0x3 ; /* 0x0000000604067291 */
/* 0x000fe4000f80183f */
/*0370*/ IMAD.X R8, RZ, RZ, -0x1, P0 ; /* 0xffffffffff087424 */
/* 0x000fe400000e06ff */
/*0380*/ ULEA.HI.X UR4, UR4, UR7, UR5, 0x3, UP0 ; /* 0x0000000704047291 */
/* 0x000fc800080f1c05 */
/*0390*/ IMAD.U32 R4, RZ, RZ, UR6 ; /* 0x00000006ff047e24 */
/* 0x000fe4000f8e00ff */
/*03a0*/ IMAD.U32 R5, RZ, RZ, UR4 ; /* 0x00000004ff057e24 */
/* 0x000fcc000f8e00ff */
/*03b0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000ea2000c1e1b00 */
/*03c0*/ IADD3 R0, P0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007f1e0ff */
/*03d0*/ UIADD3 UR6, UP0, UR6, 0x8, URZ ; /* 0x0000000806067890 */
/* 0x000fc8000ff1e03f */
/*03e0*/ IMAD.X R8, RZ, RZ, R8, P0 ; /* 0x000000ffff087224 */
/* 0x000fe200000e0608 */
/*03f0*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05070 */
/*0400*/ UIADD3.X UR4, URZ, UR4, URZ, UP0, !UPT ; /* 0x000000043f047290 */
/* 0x000fc600087fe43f */
/*0410*/ ISETP.NE.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fe20003f05300 */
/*0420*/ DADD R6, R4, R6 ; /* 0x0000000004067229 */
/* 0x007e0e0000000006 */
/*0430*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0011ea000c101b08 */
/*0440*/ @P0 BRA 0x390 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0450*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0460*/ BRA 0x460; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11partial_sumlPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff067624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff087624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0060*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe40003f06070 */
/*0080*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e640000002500 */
/*0090*/ ISETP.GE.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fc40003f06300 */
/*00a0*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*00b0*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fc800078e0203 */
/*00c0*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*00d0*/ IMAD R5, R0, c[0x0][0x0], R7 ; /* 0x0000000000057a24 */
/* 0x004fca00078e0207 */
/*00e0*/ SHF.R.S32.HI R4, RZ, 0x1f, R5 ; /* 0x0000001fff047819 */
/* 0x000fe20000011405 */
/*00f0*/ @!P0 BRA 0x8e0 ; /* 0x000007e000008947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD R0, R4, c[0x0][0x160], RZ ; /* 0x0000580004007a24 */
/* 0x000fe200078e02ff */
/*0110*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*0120*/ IMAD.WIDE.U32 R2, R5, R6, c[0x2][0x0] ; /* 0x0080000005027625 */
/* 0x000fc800078e0006 */
/*0130*/ IMAD R17, R5, c[0x0][0x164], R0 ; /* 0x0000590005117a24 */
/* 0x000fe200078e0200 */
/*0140*/ IADD3 R0, P1, R6, -0x1, RZ ; /* 0xffffffff06007810 */
/* 0x000fe20007f3e0ff */
/*0150*/ IMAD.MOV.U32 R16, RZ, RZ, R2 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0002 */
/*0160*/ IMAD.IADD R17, R3, 0x1, R17 ; /* 0x0000000103117824 */
/* 0x000fe200078e0211 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*0180*/ IADD3.X R0, R8, -0x1, RZ, P1, !PT ; /* 0xffffffff08007810 */
/* 0x000fe40000ffe4ff */
/*0190*/ LOP3.LUT R3, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306037812 */
/* 0x000fe200078ec0ff */
/*01a0*/ I2F.F64.S64 R16, R16 ; /* 0x0000001000107312 */
/* 0x000e220000301c00 */
/*01b0*/ ISETP.GE.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0003f06100 */
/*01c0*/ @!P0 BRA 0x710 ; /* 0x0000054000008947 */
/* 0x000fea0003800000 */
/*01d0*/ IADD3 R2, P0, R3, -c[0x0][0x160], RZ ; /* 0x8000580003027a10 */
/* 0x000fe20007f1e0ff */
/*01e0*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fc8000001ff00 */
/*01f0*/ IMAD.X R0, RZ, RZ, ~c[0x0][0x164], P0 ; /* 0x80005900ff007624 */
/* 0x000fe400000e06ff */
/*0200*/ MUFU.RCP64H R7, R17 ; /* 0x0000001100077308 */
/* 0x009e220000001800 */
/*0210*/ IADD3 R6, R17, 0x300402, RZ ; /* 0x0030040211067810 */
/* 0x000fe20007ffe0ff */
/*0220*/ BSSY B0, 0x350 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0230*/ IADD3 R2, P0, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fe40007f1e0ff */
/*0240*/ FSETP.GEU.AND P1, PT, |R6|, 5.8789094863358348022e-39, PT ; /* 0x004004020600780b */
/* 0x000fc60003f2e200 */
/*0250*/ IMAD.X R0, RZ, RZ, R0, P0 ; /* 0x000000ffff007224 */
/* 0x000fe200000e0600 */
/*0260*/ ISETP.NE.U32.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc80003f05070 */
/*0270*/ ISETP.NE.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fe20003f05300 */
/*0280*/ DFMA R8, R6, -R16, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c0000000810 */
/*0290*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*02a0*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*02b0*/ DFMA R10, R8, -R16, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c0000000810 */
/*02c0*/ DFMA R14, R8, R10, R8 ; /* 0x0000000a080e722b */
/* 0x0010620000000008 */
/*02d0*/ @P1 BRA 0x340 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*02e0*/ LOP3.LUT R12, R17, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff110c7812 */
/* 0x000fe200078ec0ff */
/*02f0*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x001fe200078e0010 */
/*0300*/ MOV R6, 0x340 ; /* 0x0000034000067802 */
/* 0x000fe20000000f00 */
/*0310*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0011 */
/*0320*/ IADD3 R12, R12, -0x100000, RZ ; /* 0xfff000000c0c7810 */
/* 0x000fe40007ffe0ff */
/*0330*/ CALL.REL.NOINC 0x920 ; /* 0x000005e000007944 */
/* 0x002fea0003c00000 */
/*0340*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0350*/ DADD R16, R16, 1 ; /* 0x3ff0000010107429 */
/* 0x000ea20000000000 */
/*0360*/ BSSY B0, 0x480 ; /* 0x0000011000007945 */
/* 0x000fe60003800000 */
/*0370*/ DADD R18, R14, R18 ; /* 0x000000000e127229 */
/* 0x002fe40000000012 */
/*0380*/ MUFU.RCP64H R7, R17 ; /* 0x0000001100077308 */
/* 0x004e680000001800 */
/*0390*/ IADD3 R6, R17, 0x300402, RZ ; /* 0x0030040211067810 */
/* 0x000fc80007ffe0ff */
/*03a0*/ FSETP.GEU.AND P1, PT, |R6|, 5.8789094863358348022e-39, PT ; /* 0x004004020600780b */
/* 0x000fe40003f2e200 */
/*03b0*/ DFMA R8, -R16, R6, 1 ; /* 0x3ff000001008742b */
/* 0x003e0c0000000106 */
/*03c0*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*03d0*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*03e0*/ DFMA R10, -R16, R8, 1 ; /* 0x3ff00000100a742b */
/* 0x001e0c0000000108 */
/*03f0*/ DFMA R14, R8, R10, R8 ; /* 0x0000000a080e722b */
/* 0x0010620000000008 */
/*0400*/ @P1 BRA 0x470 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0410*/ LOP3.LUT R12, R17, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff110c7812 */
/* 0x000fe200078ec0ff */
/*0420*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x001fe200078e0010 */
/*0430*/ MOV R6, 0x470 ; /* 0x0000047000067802 */
/* 0x000fe20000000f00 */
/*0440*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0011 */
/*0450*/ IADD3 R12, R12, -0x100000, RZ ; /* 0xfff000000c0c7810 */
/* 0x000fe40007ffe0ff */
/*0460*/ CALL.REL.NOINC 0x920 ; /* 0x000004b000007944 */
/* 0x002fea0003c00000 */
/*0470*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0480*/ DADD R16, R16, 1 ; /* 0x3ff0000010107429 */
/* 0x000ea20000000000 */
/*0490*/ BSSY B0, 0x5b0 ; /* 0x0000011000007945 */
/* 0x000fe60003800000 */
/*04a0*/ DADD R18, R18, R14 ; /* 0x0000000012127229 */
/* 0x002fe4000000000e */
/*04b0*/ MUFU.RCP64H R7, R17 ; /* 0x0000001100077308 */
/* 0x004e680000001800 */
/*04c0*/ IADD3 R6, R17, 0x300402, RZ ; /* 0x0030040211067810 */
/* 0x000fc80007ffe0ff */
/*04d0*/ FSETP.GEU.AND P1, PT, |R6|, 5.8789094863358348022e-39, PT ; /* 0x004004020600780b */
/* 0x000fe40003f2e200 */
/*04e0*/ DFMA R8, -R16, R6, 1 ; /* 0x3ff000001008742b */
/* 0x003e0c0000000106 */
/*04f0*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0500*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*0510*/ DFMA R10, -R16, R8, 1 ; /* 0x3ff00000100a742b */
/* 0x001e0c0000000108 */
/*0520*/ DFMA R14, R8, R10, R8 ; /* 0x0000000a080e722b */
/* 0x0010620000000008 */
/*0530*/ @P1 BRA 0x5a0 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0540*/ LOP3.LUT R12, R17, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff110c7812 */
/* 0x000fe200078ec0ff */
/*0550*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x001fe200078e0010 */
/*0560*/ MOV R6, 0x5a0 ; /* 0x000005a000067802 */
/* 0x000fe20000000f00 */
/*0570*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0011 */
/*0580*/ IADD3 R12, R12, -0x100000, RZ ; /* 0xfff000000c0c7810 */
/* 0x000fe40007ffe0ff */
/*0590*/ CALL.REL.NOINC 0x920 ; /* 0x0000038000007944 */
/* 0x002fea0003c00000 */
/*05a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05b0*/ DADD R16, R16, 1 ; /* 0x3ff0000010107429 */
/* 0x000ea20000000000 */
/*05c0*/ BSSY B0, 0x6e0 ; /* 0x0000011000007945 */
/* 0x000fe60003800000 */
/*05d0*/ DADD R18, R18, R14 ; /* 0x0000000012127229 */
/* 0x002fe4000000000e */
/*05e0*/ MUFU.RCP64H R7, R17 ; /* 0x0000001100077308 */
/* 0x004e680000001800 */
/*05f0*/ IADD3 R6, R17, 0x300402, RZ ; /* 0x0030040211067810 */
/* 0x000fc80007ffe0ff */
/*0600*/ FSETP.GEU.AND P1, PT, |R6|, 5.8789094863358348022e-39, PT ; /* 0x004004020600780b */
/* 0x000fe40003f2e200 */
/*0610*/ DFMA R8, -R16, R6, 1 ; /* 0x3ff000001008742b */
/* 0x003e0c0000000106 */
/*0620*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0630*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*0640*/ DFMA R10, -R16, R8, 1 ; /* 0x3ff00000100a742b */
/* 0x001e0c0000000108 */
/*0650*/ DFMA R14, R8, R10, R8 ; /* 0x0000000a080e722b */
/* 0x0010620000000008 */
/*0660*/ @P1 BRA 0x6d0 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0670*/ LOP3.LUT R12, R17, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff110c7812 */
/* 0x000fe200078ec0ff */
/*0680*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x001fe200078e0010 */
/*0690*/ MOV R6, 0x6d0 ; /* 0x000006d000067802 */
/* 0x000fe20000000f00 */
/*06a0*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0011 */
/*06b0*/ IADD3 R12, R12, -0x100000, RZ ; /* 0xfff000000c0c7810 */
/* 0x000fe40007ffe0ff */
/*06c0*/ CALL.REL.NOINC 0x920 ; /* 0x0000025000007944 */
/* 0x002fea0003c00000 */
/*06d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06e0*/ DADD R18, R18, R14 ; /* 0x0000000012127229 */
/* 0x002288000000000e */
/*06f0*/ DADD R16, R16, 1 ; /* 0x3ff0000010107429 */
/* 0x000ee20000000000 */
/*0700*/ @P0 BRA 0x200 ; /* 0xfffffaf000000947 */
/* 0x006ff0000383ffff */
/*0710*/ ISETP.NE.U32.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc80003f05070 */
/*0720*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05300 */
/*0730*/ @!P0 BRA 0x8e0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0740*/ IADD3 R3, P0, RZ, -R3, RZ ; /* 0x80000003ff037210 */
/* 0x000fca0007f1e0ff */
/*0750*/ IMAD.X R0, RZ, RZ, -0x1, P0 ; /* 0xffffffffff007424 */
/* 0x000fe400000e06ff */
/*0760*/ MUFU.RCP64H R7, R17 ; /* 0x0000001100077308 */
/* 0x009e220000001800 */
/*0770*/ IADD3 R6, R17, 0x300402, RZ ; /* 0x0030040211067810 */
/* 0x000fe20007ffe0ff */
/*0780*/ BSSY B0, 0x8b0 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0790*/ IADD3 R3, P0, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe40007f1e0ff */
/*07a0*/ FSETP.GEU.AND P1, PT, |R6|, 5.8789094863358348022e-39, PT ; /* 0x004004020600780b */
/* 0x000fc60003f2e200 */
/*07b0*/ IMAD.X R0, RZ, RZ, R0, P0 ; /* 0x000000ffff007224 */
/* 0x000fe200000e0600 */
/*07c0*/ ISETP.NE.U32.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc80003f05070 */
/*07d0*/ ISETP.NE.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fe20003f05300 */
/*07e0*/ DFMA R8, R6, -R16, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c0000000810 */
/*07f0*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0800*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*0810*/ DFMA R10, R8, -R16, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c0000000810 */
/*0820*/ DFMA R14, R8, R10, R8 ; /* 0x0000000a080e722b */
/* 0x0010620000000008 */
/*0830*/ @P1 BRA 0x8a0 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0840*/ LOP3.LUT R12, R17, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff110c7812 */
/* 0x000fe200078ec0ff */
/*0850*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x001fe200078e0010 */
/*0860*/ MOV R6, 0x8a0 ; /* 0x000008a000067802 */
/* 0x000fe20000000f00 */
/*0870*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0011 */
/*0880*/ IADD3 R12, R12, -0x100000, RZ ; /* 0xfff000000c0c7810 */
/* 0x000fe40007ffe0ff */
/*0890*/ CALL.REL.NOINC 0x920 ; /* 0x0000008000007944 */
/* 0x002fea0003c00000 */
/*08a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08b0*/ DADD R18, R14, R18 ; /* 0x000000000e127229 */
/* 0x0022880000000012 */
/*08c0*/ DADD R16, R16, 1 ; /* 0x3ff0000010107429 */
/* 0x000ee20000000000 */
/*08d0*/ @P0 BRA 0x760 ; /* 0xfffffe8000000947 */
/* 0x006ff0000383ffff */
/*08e0*/ LEA R2, P0, R5, c[0x0][0x168], 0x3 ; /* 0x00005a0005027a11 */
/* 0x000fc800078018ff */
/*08f0*/ LEA.HI.X R3, R5, c[0x0][0x16c], R4, 0x3, P0 ; /* 0x00005b0005037a11 */
/* 0x000fca00000f1c04 */
/*0900*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x000fe2000c101b04 */
/*0910*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0920*/ DSETP.GTU.AND P1, PT, |R8|, +INF , PT ; /* 0x7ff000000800742a */
/* 0x000e220003f2c200 */
/*0930*/ BSSY B1, 0xb70 ; /* 0x0000023000017945 */
/* 0x000fda0003800000 */
/*0940*/ @P1 BRA 0xb40 ; /* 0x000001f000001947 */
/* 0x001fea0003800000 */
/*0950*/ LOP3.LUT R7, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09077812 */
/* 0x000fc800078ec0ff */
/*0960*/ IADD3 R10, R7, -0x1, RZ ; /* 0xffffffff070a7810 */
/* 0x000fc80007ffe0ff */
/*0970*/ ISETP.GE.U32.AND P1, PT, R10, 0x7fefffff, PT ; /* 0x7fefffff0a00780c */
/* 0x000fda0003f26070 */
/*0980*/ @P1 LOP3.LUT R15, R9, 0x7ff00000, RZ, 0x3c, !PT ; /* 0x7ff00000090f1812 */
/* 0x000fe200078e3cff */
/*0990*/ @P1 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e1224 */
/* 0x000fe200078e00ff */
/*09a0*/ @P1 BRA 0xb60 ; /* 0x000001b000001947 */
/* 0x000fea0003800000 */
/*09b0*/ ISETP.GE.U32.AND P1, PT, R7, 0x1000001, PT ; /* 0x010000010700780c */
/* 0x000fda0003f26070 */
/*09c0*/ @!P1 BRA 0xaa0 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*09d0*/ IADD3 R11, R9, -0x3fe00000, RZ ; /* 0xc0200000090b7810 */
/* 0x000fe20007ffe0ff */
/*09e0*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e0008 */
/*09f0*/ MUFU.RCP64H R13, R11 ; /* 0x0000000b000d7308 */
/* 0x000e260000001800 */
/*0a00*/ DFMA R14, -R10, R12, 1 ; /* 0x3ff000000a0e742b */
/* 0x001e0c000000010c */
/*0a10*/ DFMA R14, R14, R14, R14 ; /* 0x0000000e0e0e722b */
/* 0x001e0c000000000e */
/*0a20*/ DFMA R14, R12, R14, R12 ; /* 0x0000000e0c0e722b */
/* 0x001e0c000000000c */
/*0a30*/ DFMA R12, -R10, R14, 1 ; /* 0x3ff000000a0c742b */
/* 0x001e0c000000010e */
/*0a40*/ DFMA R14, R14, R12, R14 ; /* 0x0000000c0e0e722b */
/* 0x001e0c000000000e */
/*0a50*/ DMUL R14, R14, 2.2250738585072013831e-308 ; /* 0x001000000e0e7828 */
/* 0x001e0c0000000000 */
/*0a60*/ DFMA R8, -R8, R14, 1 ; /* 0x3ff000000808742b */
/* 0x001e0c000000010e */
/*0a70*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0a80*/ DFMA R14, R14, R8, R14 ; /* 0x000000080e0e722b */
/* 0x001062000000000e */
/*0a90*/ BRA 0xb60 ; /* 0x000000c000007947 */
/* 0x000fea0003800000 */
/*0aa0*/ DMUL R10, R8, 8.11296384146066816958e+31 ; /* 0x46900000080a7828 */
/* 0x0000640000000000 */
/*0ab0*/ IMAD.MOV.U32 R8, RZ, RZ, R12 ; /* 0x000000ffff087224 */
/* 0x001fc800078e000c */
/*0ac0*/ MUFU.RCP64H R9, R11 ; /* 0x0000000b00097308 */
/* 0x002e240000001800 */
/*0ad0*/ DFMA R12, -R10, R8, 1 ; /* 0x3ff000000a0c742b */
/* 0x001e0c0000000108 */
/*0ae0*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*0af0*/ DFMA R12, R8, R12, R8 ; /* 0x0000000c080c722b */
/* 0x001e0c0000000008 */
/*0b00*/ DFMA R8, -R10, R12, 1 ; /* 0x3ff000000a08742b */
/* 0x001e0c000000010c */
/*0b10*/ DFMA R8, R12, R8, R12 ; /* 0x000000080c08722b */
/* 0x001e0c000000000c */
/*0b20*/ DMUL R14, R8, 8.11296384146066816958e+31 ; /* 0x46900000080e7828 */
/* 0x0010620000000000 */
/*0b30*/ BRA 0xb60 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0b40*/ LOP3.LUT R15, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090f7812 */
/* 0x000fe200078efcff */
/*0b50*/ IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0008 */
/*0b60*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0b70*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*0b80*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff47006007950 */
/* 0x000fea0003c3ffff */
/*0b90*/ BRA 0xb90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11partial_sumlPd
.globl _Z11partial_sumlPd
.p2align 8
.type _Z11partial_sumlPd,@function
_Z11partial_sumlPd:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s5, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s6, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s5, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
v_cmp_lt_i64_e64 s4, s[2:3], 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_and_b32 vcc_lo, exec_lo, s4
v_ashrrev_i32_e32 v1, 31, v0
s_cbranch_vccnz .LBB0_3
v_mad_u64_u32 v[2:3], null, v0, s2, 1
v_mul_lo_u32 v4, v0, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v1, s2
v_add3_u32 v3, v5, v3, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_u32_e32 v[5:6], v2
v_cvt_f64_i32_e32 v[3:4], v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[3:4], v[3:4], 32
v_add_f64 v[4:5], v[3:4], v[5:6]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], 1.0
v_div_scale_f64 v[12:13], vcc_lo, 1.0, v[4:5], 1.0
s_add_u32 s2, s2, -1
s_addc_u32 s3, s3, -1
s_cmp_eq_u64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[12:13], v[8:9]
v_fma_f64 v[6:7], -v[6:7], v[10:11], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[10:11]
v_div_fixup_f64 v[6:7], v[6:7], v[4:5], 1.0
v_add_f64 v[4:5], v[4:5], 1.0
s_delay_alu instid0(VALU_DEP_2)
v_add_f64 v[2:3], v[2:3], v[6:7]
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11partial_sumlPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11partial_sumlPd, .Lfunc_end0-_Z11partial_sumlPd
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13add_harmonicsdPdl
.globl _Z13add_harmonicsdPdl
.p2align 8
.type _Z13add_harmonicsdPdl,@function
_Z13add_harmonicsdPdl:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_cmp_lt_i64_e64 s8, s[4:5], 1
v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
s_lshl_b64 s[6:7], s[4:5], 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
s_add_u32 s0, s2, s6
s_addc_u32 s1, s3, s7
s_and_b32 vcc_lo, exec_lo, s8
global_store_b64 v2, v[0:1], s[0:1]
s_cbranch_vccnz .LBB1_3
global_load_b64 v[0:1], v2, s[0:1]
.LBB1_2:
global_load_b64 v[3:4], v2, s[2:3]
s_add_u32 s4, s4, -1
s_addc_u32 s5, s5, -1
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_cmp_eq_u64 s[4:5], 0
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[3:4], v[0:1]
global_store_b64 v2, v[0:1], s[0:1]
s_cbranch_scc0 .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13add_harmonicsdPdl
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 9
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13add_harmonicsdPdl, .Lfunc_end1-_Z13add_harmonicsdPdl
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11partial_sumlPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11partial_sumlPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13add_harmonicsdPdl
.private_segment_fixed_size: 0
.sgpr_count: 11
.sgpr_spill_count: 0
.symbol: _Z13add_harmonicsdPdl.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000682db_00000000-6_eulerm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11partial_sumlPdlPd
.type _Z32__device_stub__Z11partial_sumlPdlPd, @function
_Z32__device_stub__Z11partial_sumlPdlPd:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11partial_sumlPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z11partial_sumlPdlPd, .-_Z32__device_stub__Z11partial_sumlPdlPd
.globl _Z11partial_sumlPd
.type _Z11partial_sumlPd, @function
_Z11partial_sumlPd:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11partial_sumlPdlPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11partial_sumlPd, .-_Z11partial_sumlPd
.globl _Z35__device_stub__Z13add_harmonicsdPdldPdl
.type _Z35__device_stub__Z13add_harmonicsdPdldPdl, @function
_Z35__device_stub__Z13add_harmonicsdPdldPdl:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movsd %xmm0, 24(%rsp)
movq %rdi, 16(%rsp)
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13add_harmonicsdPdl(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z13add_harmonicsdPdldPdl, .-_Z35__device_stub__Z13add_harmonicsdPdldPdl
.globl _Z13add_harmonicsdPdl
.type _Z13add_harmonicsdPdl, @function
_Z13add_harmonicsdPdl:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13add_harmonicsdPdldPdl
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13add_harmonicsdPdl, .-_Z13add_harmonicsdPdl
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "usage:\n%s <N_ITERATIONS>\n"
.LC3:
.string "%.17f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L31
movl $1, 32(%rsp)
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
cvttsd2siq %xmm0, %rbx
movl $6, 36(%rsp)
movl $2, 40(%rsp)
movl $1, 44(%rsp)
movabsq $3074457345618258603, %rdx
movq %rbx, %rax
imulq %rdx
sarq $9, %rdx
movq %rbx, %rax
sarq $63, %rax
subq %rax, %rdx
leaq (%rdx,%rdx,2), %rax
salq $10, %rax
leaq 1(%rbx), %rdx
pxor %xmm0, %xmm0
movsd .LC2(%rip), %xmm3
cmpq %rax, %rbx
jl .L32
.L24:
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
movapd %xmm3, %xmm1
divsd %xmm2, %xmm1
addsd %xmm1, %xmm0
addq $1, %rax
cmpq %rax, %rdx
jne .L24
movsd %xmm0, 16(%rsp)
.L23:
leaq 8(%rsp), %rdi
movl $24584, %esi
call cudaMalloc@PLT
movl $32, 24(%rsp)
movl $8, 28(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L25:
call cudaDeviceSynchronize@PLT
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L26:
movq 8(%rsp), %rax
leaq 24576(%rax), %rsi
leaq 16(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rbp
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
call log@PLT
movapd %xmm0, %xmm1
movq %rbp, %xmm0
subsd %xmm1, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
.L19:
movq 72(%rsp), %rdx
subq %fs:40, %rdx
jne .L35
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq (%rsi), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %eax
jmp .L19
.L32:
movsd %xmm0, 16(%rsp)
jmp .L23
.L33:
movl $3072, %ecx
movq %rbx, %rax
cqto
idivq %rcx
movq %rax, %rdi
movq 8(%rsp), %rsi
call _Z32__device_stub__Z11partial_sumlPdlPd
jmp .L25
.L34:
movl $3072, %esi
movq 8(%rsp), %rdi
movsd 16(%rsp), %xmm0
call _Z35__device_stub__Z13add_harmonicsdPdldPdl
jmp .L26
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z13add_harmonicsdPdl"
.LC5:
.string "_Z11partial_sumlPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13add_harmonicsdPdl(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z11partial_sumlPd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "eulerm.hip"
.globl _Z26__device_stub__partial_sumlPd # -- Begin function _Z26__device_stub__partial_sumlPd
.p2align 4, 0x90
.type _Z26__device_stub__partial_sumlPd,@function
_Z26__device_stub__partial_sumlPd: # @_Z26__device_stub__partial_sumlPd
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11partial_sumlPd, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__partial_sumlPd, .Lfunc_end0-_Z26__device_stub__partial_sumlPd
.cfi_endproc
# -- End function
.globl _Z28__device_stub__add_harmonicsdPdl # -- Begin function _Z28__device_stub__add_harmonicsdPdl
.p2align 4, 0x90
.type _Z28__device_stub__add_harmonicsdPdl,@function
_Z28__device_stub__add_harmonicsdPdl: # @_Z28__device_stub__add_harmonicsdPdl
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movsd %xmm0, 72(%rsp)
movq %rdi, 64(%rsp)
movq %rsi, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13add_harmonicsdPdl, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z28__device_stub__add_harmonicsdPdl, .Lfunc_end1-_Z28__device_stub__add_harmonicsdPdl
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
cmpl $1, %edi
jg .LBB2_2
# %bb.1:
movq (%rsi), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $-1, %r14d
jmp .LBB2_9
.LBB2_2:
movq 8(%rsi), %rdi
xorl %esi, %esi
callq strtod
cvttsd2si %xmm0, %rbx
movabsq $3074457345618258603, %rcx # imm = 0x2AAAAAAAAAAAAAAB
movq %rbx, %rax
imulq %rcx
movq %rdx, %r14
movq %rdx, %rax
shrq $63, %rax
sarq $9, %r14
addq %rax, %r14
movq %r14, %rax
shlq $10, %rax
leaq (%rax,%rax,2), %rax
movq %rbx, %rcx
subq %rax, %rcx
movq $0, (%rsp)
js .LBB2_3
# %bb.10: # %.lr.ph.preheader
movq %rbx, %rax
subq %rcx, %rax
xorpd %xmm0, %xmm0
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB2_11: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm2, %xmm2
cvtsi2sd %rax, %xmm2
movapd %xmm1, %xmm3
divsd %xmm2, %xmm3
addsd %xmm3, %xmm0
leaq 1(%rax), %rcx
cmpq %rbx, %rax
movq %rcx, %rax
jl .LBB2_11
jmp .LBB2_4
.LBB2_3:
xorpd %xmm0, %xmm0
.LBB2_4: # %._crit_edge
movsd %xmm0, (%rsp)
leaq 8(%rsp), %rdi
movl $24584, %esi # imm = 0x6008
callq hipMalloc
movabsq $8589934598, %rdi # imm = 0x200000006
movabsq $34359738400, %rdx # imm = 0x800000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 8(%rsp), %rax
movq %r14, 72(%rsp)
movq %rax, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11partial_sumlPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
callq hipDeviceSynchronize
xorl %r14d, %r14d
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movsd (%rsp), %xmm0 # xmm0 = mem[0],zero
movq 8(%rsp), %rax
movsd %xmm0, 72(%rsp)
movq %rax, 64(%rsp)
movq $3072, 56(%rsp) # imm = 0xC00
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13add_harmonicsdPdl, %edi
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
movl $24576, %esi # imm = 0x6000
addq 8(%rsp), %rsi
movq %rsp, %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movsd (%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 104(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sd %rbx, %xmm0
callq log
movsd 104(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
subsd %xmm0, %xmm1
movl $.L.str.1, %edi
movapd %xmm1, %xmm0
movb $1, %al
callq printf
.LBB2_9:
movl %r14d, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11partial_sumlPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13add_harmonicsdPdl, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11partial_sumlPd,@object # @_Z11partial_sumlPd
.section .rodata,"a",@progbits
.globl _Z11partial_sumlPd
.p2align 3, 0x0
_Z11partial_sumlPd:
.quad _Z26__device_stub__partial_sumlPd
.size _Z11partial_sumlPd, 8
.type _Z13add_harmonicsdPdl,@object # @_Z13add_harmonicsdPdl
.globl _Z13add_harmonicsdPdl
.p2align 3, 0x0
_Z13add_harmonicsdPdl:
.quad _Z28__device_stub__add_harmonicsdPdl
.size _Z13add_harmonicsdPdl, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "usage:\n%s <N_ITERATIONS>\n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%.17f\n"
.size .L.str.1, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11partial_sumlPd"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13add_harmonicsdPdl"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__partial_sumlPd
.addrsig_sym _Z28__device_stub__add_harmonicsdPdl
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11partial_sumlPd
.addrsig_sym _Z13add_harmonicsdPdl
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
int main(void)
{
const int SIZE = 5;
const int a[SIZE] = { 1,2,3,4,5 };
int b[SIZE] = { 0,0,0,0,0 };
//½ÃÀÛ Àü °ª È®ÀÎ
printf("a = {%d,%d,%d,%d,%d}\n", a[0], a[1], a[2], a[3], a[4]);
int* dev_a = 0;
int* dev_b = 0;
//GPU ¸Þ¸ð¸® °ø°£ ÇÒ´ç
cudaMalloc((void**)&dev_a, SIZE * sizeof(int));
cudaMalloc((void**)&dev_b, SIZE * sizeof(int));
//RAM -> VRAM ¸Þ¸ð¸® º¹»ç
//a -> dev_a
cudaMemcpy(dev_a, a, SIZE * sizeof(int), cudaMemcpyHostToDevice);
//dev_a -> dev_b
cudaMemcpy(dev_b, dev_a, SIZE * sizeof(int), cudaMemcpyDeviceToDevice);
//dev_b -> b
cudaMemcpy(b, dev_b, SIZE * sizeof(int), cudaMemcpyDeviceToHost);
//VRAM ÇÒ´ç °ø°£ ÇØÁ¦
cudaFree(dev_a);
cudaFree(dev_b);
printf("b = {%d,%d,%d,%d,%d}\n", b[0], b[1], b[2], b[3], b[4]);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
int main(void)
{
const int SIZE = 5;
const int a[SIZE] = { 1,2,3,4,5 };
int b[SIZE] = { 0,0,0,0,0 };
//½ÃÀÛ Àü °ª È®ÀÎ
printf("a = {%d,%d,%d,%d,%d}\n", a[0], a[1], a[2], a[3], a[4]);
int* dev_a = 0;
int* dev_b = 0;
//GPU ¸Þ¸ð¸® °ø°£ ÇÒ´ç
cudaMalloc((void**)&dev_a, SIZE * sizeof(int));
cudaMalloc((void**)&dev_b, SIZE * sizeof(int));
//RAM -> VRAM ¸Þ¸ð¸® º¹»ç
//a -> dev_a
cudaMemcpy(dev_a, a, SIZE * sizeof(int), cudaMemcpyHostToDevice);
//dev_a -> dev_b
cudaMemcpy(dev_b, dev_a, SIZE * sizeof(int), cudaMemcpyDeviceToDevice);
//dev_b -> b
cudaMemcpy(b, dev_b, SIZE * sizeof(int), cudaMemcpyDeviceToHost);
//VRAM ÇÒ´ç °ø°£ ÇØÁ¦
cudaFree(dev_a);
cudaFree(dev_b);
printf("b = {%d,%d,%d,%d,%d}\n", b[0], b[1], b[2], b[3], b[4]);
return 0;
} | .file "tmpxft_001797c3_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "a = {%d,%d,%d,%d,%d}\n"
.LC1:
.string "b = {%d,%d,%d,%d,%d}\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $96, %rsp
.cfi_def_cfa_offset 104
movq %fs:40, %rax
movq %rax, 80(%rsp)
xorl %eax, %eax
movl $1, 24(%rsp)
movl $2, 28(%rsp)
movl $3, 32(%rsp)
movl $4, 36(%rsp)
movl $5, 40(%rsp)
movl $0, 56(%rsp)
movl $0, 60(%rsp)
movl $0, 64(%rsp)
movl $0, 68(%rsp)
movl $0, 72(%rsp)
pushq $5
.cfi_def_cfa_offset 112
movl $4, %r9d
movl $3, %r8d
movl $2, %ecx
movl $1, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movq $0, 16(%rsp)
movq $0, 24(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 96
movq %rsp, %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $3, %ecx
movl $20, %edx
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $20, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
subq $8, %rsp
.cfi_def_cfa_offset 104
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 112
movl 76(%rsp), %r9d
movl 72(%rsp), %r8d
movl 68(%rsp), %ecx
movl 64(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
int main(void)
{
const int SIZE = 5;
const int a[SIZE] = { 1,2,3,4,5 };
int b[SIZE] = { 0,0,0,0,0 };
//½ÃÀÛ Àü °ª È®ÀÎ
printf("a = {%d,%d,%d,%d,%d}\n", a[0], a[1], a[2], a[3], a[4]);
int* dev_a = 0;
int* dev_b = 0;
//GPU ¸Þ¸ð¸® °ø°£ ÇÒ´ç
cudaMalloc((void**)&dev_a, SIZE * sizeof(int));
cudaMalloc((void**)&dev_b, SIZE * sizeof(int));
//RAM -> VRAM ¸Þ¸ð¸® º¹»ç
//a -> dev_a
cudaMemcpy(dev_a, a, SIZE * sizeof(int), cudaMemcpyHostToDevice);
//dev_a -> dev_b
cudaMemcpy(dev_b, dev_a, SIZE * sizeof(int), cudaMemcpyDeviceToDevice);
//dev_b -> b
cudaMemcpy(b, dev_b, SIZE * sizeof(int), cudaMemcpyDeviceToHost);
//VRAM ÇÒ´ç °ø°£ ÇØÁ¦
cudaFree(dev_a);
cudaFree(dev_b);
printf("b = {%d,%d,%d,%d,%d}\n", b[0], b[1], b[2], b[3], b[4]);
return 0;
} | #include <hip/hip_runtime.h>
#include <cstdio>
int main(void)
{
const int SIZE = 5;
const int a[SIZE] = { 1,2,3,4,5 };
int b[SIZE] = { 0,0,0,0,0 };
//½ÃÀÛ Àü °ª È®ÀÎ
printf("a = {%d,%d,%d,%d,%d}\n", a[0], a[1], a[2], a[3], a[4]);
int* dev_a = 0;
int* dev_b = 0;
//GPU ¸Þ¸ð¸® °ø°£ ÇÒ´ç
hipMalloc((void**)&dev_a, SIZE * sizeof(int));
hipMalloc((void**)&dev_b, SIZE * sizeof(int));
//RAM -> VRAM ¸Þ¸ð¸® º¹»ç
//a -> dev_a
hipMemcpy(dev_a, a, SIZE * sizeof(int), hipMemcpyHostToDevice);
//dev_a -> dev_b
hipMemcpy(dev_b, dev_a, SIZE * sizeof(int), hipMemcpyDeviceToDevice);
//dev_b -> b
hipMemcpy(b, dev_b, SIZE * sizeof(int), hipMemcpyDeviceToHost);
//VRAM ÇÒ´ç °ø°£ ÇØÁ¦
hipFree(dev_a);
hipFree(dev_b);
printf("b = {%d,%d,%d,%d,%d}\n", b[0], b[1], b[2], b[3], b[4]);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
int main(void)
{
const int SIZE = 5;
const int a[SIZE] = { 1,2,3,4,5 };
int b[SIZE] = { 0,0,0,0,0 };
//½ÃÀÛ Àü °ª È®ÀÎ
printf("a = {%d,%d,%d,%d,%d}\n", a[0], a[1], a[2], a[3], a[4]);
int* dev_a = 0;
int* dev_b = 0;
//GPU ¸Þ¸ð¸® °ø°£ ÇÒ´ç
hipMalloc((void**)&dev_a, SIZE * sizeof(int));
hipMalloc((void**)&dev_b, SIZE * sizeof(int));
//RAM -> VRAM ¸Þ¸ð¸® º¹»ç
//a -> dev_a
hipMemcpy(dev_a, a, SIZE * sizeof(int), hipMemcpyHostToDevice);
//dev_a -> dev_b
hipMemcpy(dev_b, dev_a, SIZE * sizeof(int), hipMemcpyDeviceToDevice);
//dev_b -> b
hipMemcpy(b, dev_b, SIZE * sizeof(int), hipMemcpyDeviceToHost);
//VRAM ÇÒ´ç °ø°£ ÇØÁ¦
hipFree(dev_a);
hipFree(dev_b);
printf("b = {%d,%d,%d,%d,%d}\n", b[0], b[1], b[2], b[3], b[4]);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
int main(void)
{
const int SIZE = 5;
const int a[SIZE] = { 1,2,3,4,5 };
int b[SIZE] = { 0,0,0,0,0 };
//½ÃÀÛ Àü °ª È®ÀÎ
printf("a = {%d,%d,%d,%d,%d}\n", a[0], a[1], a[2], a[3], a[4]);
int* dev_a = 0;
int* dev_b = 0;
//GPU ¸Þ¸ð¸® °ø°£ ÇÒ´ç
hipMalloc((void**)&dev_a, SIZE * sizeof(int));
hipMalloc((void**)&dev_b, SIZE * sizeof(int));
//RAM -> VRAM ¸Þ¸ð¸® º¹»ç
//a -> dev_a
hipMemcpy(dev_a, a, SIZE * sizeof(int), hipMemcpyHostToDevice);
//dev_a -> dev_b
hipMemcpy(dev_b, dev_a, SIZE * sizeof(int), hipMemcpyDeviceToDevice);
//dev_b -> b
hipMemcpy(b, dev_b, SIZE * sizeof(int), hipMemcpyDeviceToHost);
//VRAM ÇÒ´ç °ø°£ ÇØÁ¦
hipFree(dev_a);
hipFree(dev_b);
printf("b = {%d,%d,%d,%d,%d}\n", b[0], b[1], b[2], b[3], b[4]);
return 0;
} | .text
.file "kernel.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movaps .LCPI0_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
movaps %xmm0, 48(%rsp)
movl $5, 64(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 16(%rsp)
movl $0, 32(%rsp)
movl $.L.str, %edi
movl $1, %esi
movl $2, %edx
movl $3, %ecx
movl $4, %r8d
movl $5, %r9d
xorl %eax, %eax
callq printf
movq $0, 8(%rsp)
movq $0, (%rsp)
leaq 8(%rsp), %rdi
movl $20, %esi
callq hipMalloc
movq %rsp, %rdi
movl $20, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 48(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movl $20, %edx
movl $3, %ecx
callq hipMemcpy
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $20, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl 16(%rsp), %esi
movl 20(%rsp), %edx
movl 24(%rsp), %ecx
movl 28(%rsp), %r8d
movl 32(%rsp), %r9d
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "a = {%d,%d,%d,%d,%d}\n"
.size .L.str, 22
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "b = {%d,%d,%d,%d,%d}\n"
.size .L.str.1, 22
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001797c3_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "a = {%d,%d,%d,%d,%d}\n"
.LC1:
.string "b = {%d,%d,%d,%d,%d}\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $96, %rsp
.cfi_def_cfa_offset 104
movq %fs:40, %rax
movq %rax, 80(%rsp)
xorl %eax, %eax
movl $1, 24(%rsp)
movl $2, 28(%rsp)
movl $3, 32(%rsp)
movl $4, 36(%rsp)
movl $5, 40(%rsp)
movl $0, 56(%rsp)
movl $0, 60(%rsp)
movl $0, 64(%rsp)
movl $0, 68(%rsp)
movl $0, 72(%rsp)
pushq $5
.cfi_def_cfa_offset 112
movl $4, %r9d
movl $3, %r8d
movl $2, %ecx
movl $1, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movq $0, 16(%rsp)
movq $0, 24(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 96
movq %rsp, %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $3, %ecx
movl $20, %edx
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $20, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
subq $8, %rsp
.cfi_def_cfa_offset 104
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 112
movl 76(%rsp), %r9d
movl 72(%rsp), %r8d
movl 68(%rsp), %ecx
movl 64(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movaps .LCPI0_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
movaps %xmm0, 48(%rsp)
movl $5, 64(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 16(%rsp)
movl $0, 32(%rsp)
movl $.L.str, %edi
movl $1, %esi
movl $2, %edx
movl $3, %ecx
movl $4, %r8d
movl $5, %r9d
xorl %eax, %eax
callq printf
movq $0, 8(%rsp)
movq $0, (%rsp)
leaq 8(%rsp), %rdi
movl $20, %esi
callq hipMalloc
movq %rsp, %rdi
movl $20, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 48(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movl $20, %edx
movl $3, %ecx
callq hipMemcpy
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $20, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl 16(%rsp), %esi
movl 20(%rsp), %edx
movl 24(%rsp), %ecx
movl 28(%rsp), %r8d
movl 32(%rsp), %r9d
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "a = {%d,%d,%d,%d,%d}\n"
.size .L.str, 22
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "b = {%d,%d,%d,%d,%d}\n"
.size .L.str.1, 22
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define Q(x) (x) * (x)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
#define N 1024
#define TB 32
int main(){
clock_t tStart = clock();
int *a , *b , *c;
size_t size = N * N * sizeof(int) ;
a = (int *)malloc( size );
b = (int *)malloc( size );
c = (int *)malloc( size );
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
a[i * N + j] = i + j;
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
b[i * N + j] = 1;
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
c[i * N + j] = a[i * N + j] * b[i * N + j];
printf("Time taken: %.2fms\n", 1000.0 * (double)(clock() - tStart)/CLOCKS_PER_SEC);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define Q(x) (x) * (x)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
#define N 1024
#define TB 32
int main(){
clock_t tStart = clock();
int *a , *b , *c;
size_t size = N * N * sizeof(int) ;
a = (int *)malloc( size );
b = (int *)malloc( size );
c = (int *)malloc( size );
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
a[i * N + j] = i + j;
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
b[i * N + j] = 1;
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
c[i * N + j] = a[i * N + j] * b[i * N + j];
printf("Time taken: %.2fms\n", 1000.0 * (double)(clock() - tStart)/CLOCKS_PER_SEC);
return 0;
} | .file "tmpxft_0001ecd0_00000000-6_times_C.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10862:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10862:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Time taken: %.2fms\n"
.text
.globl main
.type main, @function
main:
.LFB10859:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
call clock@PLT
movq %rax, %r12
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %rsi
movq %rbp, %r8
movl $1024, %ecx
movl $0, %edi
.L4:
movl %edi, %eax
movq %r8, %rdx
.L5:
movl %eax, (%rdx)
addl $1, %eax
addq $4, %rdx
cmpl %ecx, %eax
jne .L5
addl $1, %edi
addq $4096, %r8
addl $1, %ecx
cmpl $1024, %edi
jne .L4
leaq 4096(%rbx), %rdx
leaq 4198400(%rbx), %rcx
.L8:
leaq -4096(%rdx), %rax
.L7:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L7
addq $4096, %rdx
cmpq %rcx, %rdx
jne .L8
movl $4096, %ecx
.L9:
leaq -4096(%rcx), %rax
.L10:
movl 0(%rbp,%rax), %edx
imull (%rbx,%rax), %edx
movl %edx, (%rsi,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L10
addq $4096, %rcx
cmpq $4198400, %rcx
jne .L9
call clock@PLT
subq %r12, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC0(%rip), %xmm0
divsd .LC1(%rip), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10859:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10885:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10885:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1083129856
.align 8
.LC1:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define Q(x) (x) * (x)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
#define N 1024
#define TB 32
int main(){
clock_t tStart = clock();
int *a , *b , *c;
size_t size = N * N * sizeof(int) ;
a = (int *)malloc( size );
b = (int *)malloc( size );
c = (int *)malloc( size );
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
a[i * N + j] = i + j;
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
b[i * N + j] = 1;
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
c[i * N + j] = a[i * N + j] * b[i * N + j];
printf("Time taken: %.2fms\n", 1000.0 * (double)(clock() - tStart)/CLOCKS_PER_SEC);
return 0;
} | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define Q(x) (x) * (x)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
#define N 1024
#define TB 32
int main(){
clock_t tStart = clock();
int *a , *b , *c;
size_t size = N * N * sizeof(int) ;
a = (int *)malloc( size );
b = (int *)malloc( size );
c = (int *)malloc( size );
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
a[i * N + j] = i + j;
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
b[i * N + j] = 1;
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
c[i * N + j] = a[i * N + j] * b[i * N + j];
printf("Time taken: %.2fms\n", 1000.0 * (double)(clock() - tStart)/CLOCKS_PER_SEC);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define Q(x) (x) * (x)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
#define N 1024
#define TB 32
int main(){
clock_t tStart = clock();
int *a , *b , *c;
size_t size = N * N * sizeof(int) ;
a = (int *)malloc( size );
b = (int *)malloc( size );
c = (int *)malloc( size );
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
a[i * N + j] = i + j;
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
b[i * N + j] = 1;
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
c[i * N + j] = a[i * N + j] * b[i * N + j];
printf("Time taken: %.2fms\n", 1000.0 * (double)(clock() - tStart)/CLOCKS_PER_SEC);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define Q(x) (x) * (x)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
#define N 1024
#define TB 32
int main(){
clock_t tStart = clock();
int *a , *b , *c;
size_t size = N * N * sizeof(int) ;
a = (int *)malloc( size );
b = (int *)malloc( size );
c = (int *)malloc( size );
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
a[i * N + j] = i + j;
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
b[i * N + j] = 1;
for(int i = 0; i < N; i++)
for(int j = 0; j < N; j++)
c[i * N + j] = a[i * N + j] * b[i * N + j];
printf("Time taken: %.2fms\n", 1000.0 * (double)(clock() - tStart)/CLOCKS_PER_SEC);
return 0;
} | .text
.file "times_C.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x408f400000000000 # double 1000
.LCPI0_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.preheader39.preheader
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
callq clock
movq %rax, %rbx
callq clock
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
divsd .LCPI0_1(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time taken: %.2fms\n"
.size .L.str, 20
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001ecd0_00000000-6_times_C.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10862:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10862:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Time taken: %.2fms\n"
.text
.globl main
.type main, @function
main:
.LFB10859:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
call clock@PLT
movq %rax, %r12
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %rsi
movq %rbp, %r8
movl $1024, %ecx
movl $0, %edi
.L4:
movl %edi, %eax
movq %r8, %rdx
.L5:
movl %eax, (%rdx)
addl $1, %eax
addq $4, %rdx
cmpl %ecx, %eax
jne .L5
addl $1, %edi
addq $4096, %r8
addl $1, %ecx
cmpl $1024, %edi
jne .L4
leaq 4096(%rbx), %rdx
leaq 4198400(%rbx), %rcx
.L8:
leaq -4096(%rdx), %rax
.L7:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L7
addq $4096, %rdx
cmpq %rcx, %rdx
jne .L8
movl $4096, %ecx
.L9:
leaq -4096(%rcx), %rax
.L10:
movl 0(%rbp,%rax), %edx
imull (%rbx,%rax), %edx
movl %edx, (%rsi,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L10
addq $4096, %rcx
cmpq $4198400, %rcx
jne .L9
call clock@PLT
subq %r12, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC0(%rip), %xmm0
divsd .LC1(%rip), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10859:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10885:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10885:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1083129856
.align 8
.LC1:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "times_C.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x408f400000000000 # double 1000
.LCPI0_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.preheader39.preheader
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
callq clock
movq %rax, %rbx
callq clock
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
divsd .LCPI0_1(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time taken: %.2fms\n"
.size .L.str, 20
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define VECT_SIZE 10000000
#define THRESHOLD 1.e-7
__global__ void VectorAdd(float *w, float *u, float *v, int n) {
for (int i = 0; i < n; i++) {
w[i] = u[i] + v[i];
}
}
void fill(float *v) {
for (int i = 0; i < VECT_SIZE; i++) {
v[i] = (float)i;
}
}
int main() {
// Host pointers
float *u, *v, *w;
// Device pointers
float *u_device, *v_device, *w_device;
// Alloco mem host
u = (float *) malloc(sizeof(float)*VECT_SIZE);
v = (float *) malloc(sizeof(float)*VECT_SIZE);
w = (float *) malloc(sizeof(float)*VECT_SIZE);
fill(u);
fill(v);
// Alloco mem device
cudaMalloc((void **) &u_device, sizeof(float)*VECT_SIZE);
cudaMalloc((void **) &v_device, sizeof(float)*VECT_SIZE);
cudaMalloc((void **) &w_device, sizeof(float)*VECT_SIZE);
// H --> D
cudaMemcpy(u_device, u, sizeof(float)*VECT_SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(v_device, v, sizeof(float)*VECT_SIZE, cudaMemcpyHostToDevice);
// Kernel call
VectorAdd<<<1,1>>>(w_device, u_device, v_device, VECT_SIZE);
// D --> H
cudaMemcpy(w, w_device, sizeof(float)*VECT_SIZE, cudaMemcpyDeviceToHost);
// check ?
for (int i = 0; i < VECT_SIZE; i++) {
if (!((w[i]-u[i]-v[i]) < THRESHOLD)) {
fprintf(stderr,"Got mistake!\n");
}
}
cudaFree(u_device);
cudaFree(v_device);
cudaFree(w_device);
free(u);
free(v);
free(w);
} | code for sm_80
Function : _Z9VectorAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0xb80 ; /* 0x00000ae000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R8, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000087a10 */
/* 0x000fe20007ffe1ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fe200078e00ff */
/*0120*/ MOV R6, c[0x0][0x168] ; /* 0x00005a0000067a02 */
/* 0x000fd20000000f00 */
/*0130*/ @!P0 BRA 0x990 ; /* 0x0000085000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0160*/ @!P1 BRA 0x670 ; /* 0x0000050000009947 */
/* 0x000fea0003800000 */
/*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0180*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*01a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*01b0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c10190c */
/*01c0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*01f0*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c10190c */
/*0200*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea4000c1e1900 */
/*0220*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0230*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0005e8000c10190c */
/*0240*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x000ee8000c1e1900 */
/*0250*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x000ee4000c1e1900 */
/*0260*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x008fca0000000000 */
/*0270*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0007e8000c10190c */
/*0280*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100c02097981 */
/* 0x001f28000c1e1900 */
/*0290*/ LDG.E R10, [R6.64+0x10] ; /* 0x0000100c060a7981 */
/* 0x000f24000c1e1900 */
/*02a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*02b0*/ STG.E [R4.64+0x10], R9 ; /* 0x0000100904007986 */
/* 0x0001e8000c10190c */
/*02c0*/ LDG.E R10, [R2.64+0x14] ; /* 0x0000140c020a7981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R11, [R6.64+0x14] ; /* 0x0000140c060b7981 */
/* 0x002f24000c1e1900 */
/*02e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*02f0*/ STG.E [R4.64+0x14], R11 ; /* 0x0000140b04007986 */
/* 0x0003e8000c10190c */
/*0300*/ LDG.E R10, [R2.64+0x18] ; /* 0x0000180c020a7981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R13, [R6.64+0x18] ; /* 0x0000180c060d7981 */
/* 0x004f24000c1e1900 */
/*0320*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0330*/ STG.E [R4.64+0x18], R13 ; /* 0x0000180d04007986 */
/* 0x0005e8000c10190c */
/*0340*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c0c020a7981 */
/* 0x000f28000c1e1900 */
/*0350*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c0c060f7981 */
/* 0x008f24000c1e1900 */
/*0360*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x010fca0000000000 */
/*0370*/ STG.E [R4.64+0x1c], R15 ; /* 0x00001c0f04007986 */
/* 0x0007e8000c10190c */
/*0380*/ LDG.E R9, [R2.64+0x20] ; /* 0x0000200c02097981 */
/* 0x001f28000c1e1900 */
/*0390*/ LDG.E R10, [R6.64+0x20] ; /* 0x0000200c060a7981 */
/* 0x000f24000c1e1900 */
/*03a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*03b0*/ STG.E [R4.64+0x20], R9 ; /* 0x0000200904007986 */
/* 0x0001e8000c10190c */
/*03c0*/ LDG.E R10, [R2.64+0x24] ; /* 0x0000240c020a7981 */
/* 0x000f28000c1e1900 */
/*03d0*/ LDG.E R11, [R6.64+0x24] ; /* 0x0000240c060b7981 */
/* 0x002f24000c1e1900 */
/*03e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*03f0*/ STG.E [R4.64+0x24], R11 ; /* 0x0000240b04007986 */
/* 0x0003e8000c10190c */
/*0400*/ LDG.E R10, [R2.64+0x28] ; /* 0x0000280c020a7981 */
/* 0x000f28000c1e1900 */
/*0410*/ LDG.E R13, [R6.64+0x28] ; /* 0x0000280c060d7981 */
/* 0x004f24000c1e1900 */
/*0420*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0430*/ STG.E [R4.64+0x28], R13 ; /* 0x0000280d04007986 */
/* 0x0005e8000c10190c */
/*0440*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c0c020a7981 */
/* 0x000f28000c1e1900 */
/*0450*/ LDG.E R15, [R6.64+0x2c] ; /* 0x00002c0c060f7981 */
/* 0x008f24000c1e1900 */
/*0460*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x010fca0000000000 */
/*0470*/ STG.E [R4.64+0x2c], R15 ; /* 0x00002c0f04007986 */
/* 0x0007e8000c10190c */
/*0480*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300c02097981 */
/* 0x001f28000c1e1900 */
/*0490*/ LDG.E R10, [R6.64+0x30] ; /* 0x0000300c060a7981 */
/* 0x000f24000c1e1900 */
/*04a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*04b0*/ STG.E [R4.64+0x30], R9 ; /* 0x0000300904007986 */
/* 0x000fe8000c10190c */
/*04c0*/ LDG.E R10, [R2.64+0x34] ; /* 0x0000340c020a7981 */
/* 0x000f28000c1e1900 */
/*04d0*/ LDG.E R11, [R6.64+0x34] ; /* 0x0000340c060b7981 */
/* 0x002f24000c1e1900 */
/*04e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*04f0*/ STG.E [R4.64+0x34], R11 ; /* 0x0000340b04007986 */
/* 0x0001e8000c10190c */
/*0500*/ LDG.E R10, [R2.64+0x38] ; /* 0x0000380c020a7981 */
/* 0x000f28000c1e1900 */
/*0510*/ LDG.E R13, [R6.64+0x38] ; /* 0x0000380c060d7981 */
/* 0x004f22000c1e1900 */
/*0520*/ IADD3 R12, P1, R2, 0x40, RZ ; /* 0x00000040020c7810 */
/* 0x000fe40007f3e0ff */
/*0530*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*0540*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0550*/ STG.E [R4.64+0x38], R13 ; /* 0x0000380d04007986 */
/* 0x000fe8000c10190c */
/*0560*/ LDG.E R10, [R2.64+0x3c] ; /* 0x00003c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0570*/ LDG.E R15, [R6.64+0x3c] ; /* 0x00003c0c060f7981 */
/* 0x0086a2000c1e1900 */
/*0580*/ IADD3.X R11, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0b7210 */
/* 0x001fe20000ffe4ff */
/*0590*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*05a0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fc40003f24270 */
/*05b0*/ IADD3 R9, P3, R4, 0x40, RZ ; /* 0x0000004004097810 */
/* 0x000fe20007f7e0ff */
/*05c0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000c */
/*05d0*/ IADD3 R14, P2, R6, 0x40, RZ ; /* 0x00000040060e7810 */
/* 0x000fe40007f5e0ff */
/*05e0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fc60000000f00 */
/*05f0*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x008fe400010e0607 */
/*0600*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000e */
/*0610*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0620*/ IADD3.X R10, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc80001ffe4ff */
/*0630*/ STG.E [R4.64+0x3c], R15 ; /* 0x00003c0f04007986 */
/* 0x0001e4000c10190c */
/*0640*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0650*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*0660*/ @P1 BRA 0x180 ; /* 0xfffffb1000001947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x970 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0690*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*06a0*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*06b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*06c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c10190c */
/*06d0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*06e0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*06f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0700*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c10190c */
/*0710*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0720*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea4000c1e1900 */
/*0730*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0740*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0005e8000c10190c */
/*0750*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x000ee8000c1e1900 */
/*0760*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x000ee4000c1e1900 */
/*0770*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x008fca0000000000 */
/*0780*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0007e8000c10190c */
/*0790*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100c02097981 */
/* 0x001f28000c1e1900 */
/*07a0*/ LDG.E R10, [R6.64+0x10] ; /* 0x0000100c060a7981 */
/* 0x000f24000c1e1900 */
/*07b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*07c0*/ STG.E [R4.64+0x10], R9 ; /* 0x0000100904007986 */
/* 0x000fe8000c10190c */
/*07d0*/ LDG.E R10, [R2.64+0x14] ; /* 0x0000140c020a7981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R11, [R6.64+0x14] ; /* 0x0000140c060b7981 */
/* 0x002f24000c1e1900 */
/*07f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*0800*/ STG.E [R4.64+0x14], R11 ; /* 0x0000140b04007986 */
/* 0x0001e8000c10190c */
/*0810*/ LDG.E R10, [R2.64+0x18] ; /* 0x0000180c020a7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R13, [R6.64+0x18] ; /* 0x0000180c060d7981 */
/* 0x004f24000c1e1900 */
/*0830*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0840*/ STG.E [R4.64+0x18], R13 ; /* 0x0000180d04007986 */
/* 0x000fe8000c10190c */
/*0850*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0860*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c0c060f7981 */
/* 0x0086a2000c1e1900 */
/*0870*/ IADD3 R11, P2, R2, 0x20, RZ ; /* 0x00000020020b7810 */
/* 0x001fe20007f5e0ff */
/*0880*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0890*/ IADD3 R9, P3, R4, 0x20, RZ ; /* 0x0000002004097810 */
/* 0x000fc40007f7e0ff */
/*08a0*/ IADD3 R14, P1, R6, 0x20, RZ ; /* 0x00000020060e7810 */
/* 0x000fe20007f3e0ff */
/*08b0*/ IMAD.X R12, RZ, RZ, R3, P2 ; /* 0x000000ffff0c7224 */
/* 0x000fe200010e0603 */
/*08c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*08d0*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000b */
/*08e0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*08f0*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x008fe200078e000e */
/*0900*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe40000ffe4ff */
/*0910*/ MOV R3, R12 ; /* 0x0000000c00037202 */
/* 0x000fe20000000f00 */
/*0920*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0930*/ IADD3.X R10, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc80001ffe4ff */
/*0940*/ STG.E [R4.64+0x1c], R15 ; /* 0x00001c0f04007986 */
/* 0x0001e4000c10190c */
/*0950*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0960*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000a */
/*0970*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb80 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0990*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*09b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*09c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c10190c */
/*09d0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*09f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0a00*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0001e8000c10190c */
/*0a10*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0a20*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea2000c1e1900 */
/*0a30*/ IADD3 R12, P0, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fe40007f1e0ff */
/*0a40*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0a60*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x000fe8000c10190c */
/*0a70*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0a80*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x0006a2000c1e1900 */
/*0a90*/ IADD3.X R11, RZ, R3, RZ, P0, !PT ; /* 0x00000003ff0b7210 */
/* 0x001fe200007fe4ff */
/*0aa0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0ab0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc40003f05270 */
/*0ac0*/ IADD3 R9, P2, R4, 0x10, RZ ; /* 0x0000001004097810 */
/* 0x000fe20007f5e0ff */
/*0ad0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000c */
/*0ae0*/ IADD3 R14, P1, R6, 0x10, RZ ; /* 0x00000010060e7810 */
/* 0x000fe40007f3e0ff */
/*0af0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fc60000000f00 */
/*0b00*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x008fe400008e0607 */
/*0b10*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000e */
/*0b20*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0b30*/ IADD3.X R10, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc800017fe4ff */
/*0b40*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0001e4000c10190c */
/*0b50*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0b60*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*0b70*/ @P0 BRA 0x990 ; /* 0xfffffe1000000947 */
/* 0x000fea000383ffff */
/*0b80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0b90*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0ba0*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0bb0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0bc0*/ ULDC.64 UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe40000000a00 */
/*0bd0*/ ULDC.64 UR10, c[0x0][0x168] ; /* 0x00005a00000a7ab9 */
/* 0x000fe40000000a00 */
/*0be0*/ UIMAD.WIDE UR6, UR4, UR5, UR6 ; /* 0x00000005040672a5 */
/* 0x000fe4000f8e0206 */
/*0bf0*/ UIMAD.WIDE UR8, UR4, UR5, UR8 ; /* 0x00000005040872a5 */
/* 0x000fc4000f8e0208 */
/*0c00*/ UIMAD.WIDE UR4, UR4, UR5, UR10 ; /* 0x00000005040472a5 */
/* 0x000fca000f8e020a */
/*0c10*/ MOV R2, UR8 ; /* 0x0000000800027c02 */
/* 0x000fe20008000f00 */
/*0c20*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x000fe2000f8e00ff */
/*0c30*/ MOV R4, UR4 ; /* 0x0000000400047c02 */
/* 0x000fe20008000f00 */
/*0c40*/ IMAD.U32 R3, RZ, RZ, UR9 ; /* 0x00000009ff037e24 */
/* 0x000fc8000f8e00ff */
/*0c50*/ LDG.E R5, [R4.64] ; /* 0x0000000c04057981 */
/* 0x000ea8000c1e1900 */
/*0c60*/ LDG.E R2, [R2.64] ; /* 0x0000000c02027981 */
/* 0x000ea2000c1e1900 */
/*0c70*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0c80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0c90*/ UIADD3 UR8, UP1, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe2000ff3e03f */
/*0ca0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x001fe20008000f00 */
/*0cb0*/ UIADD3 UR6, UP0, UR6, 0x4, URZ ; /* 0x0000000406067890 */
/* 0x000fe2000ff1e03f */
/*0cc0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe20008000f00 */
/*0cd0*/ UIADD3 UR4, UP2, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000ff5e03f */
/*0ce0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0cf0*/ UIADD3.X UR9, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f097290 */
/* 0x000fe40008ffe43f */
/*0d00*/ UIADD3.X UR5, URZ, UR5, URZ, UP2, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200097fe43f */
/*0d10*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0d20*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e2000c10190c */
/*0d30*/ @P0 BRA 0xc10 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*0d40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d50*/ BRA 0xd50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define VECT_SIZE 10000000
#define THRESHOLD 1.e-7
__global__ void VectorAdd(float *w, float *u, float *v, int n) {
for (int i = 0; i < n; i++) {
w[i] = u[i] + v[i];
}
}
void fill(float *v) {
for (int i = 0; i < VECT_SIZE; i++) {
v[i] = (float)i;
}
}
int main() {
// Host pointers
float *u, *v, *w;
// Device pointers
float *u_device, *v_device, *w_device;
// Alloco mem host
u = (float *) malloc(sizeof(float)*VECT_SIZE);
v = (float *) malloc(sizeof(float)*VECT_SIZE);
w = (float *) malloc(sizeof(float)*VECT_SIZE);
fill(u);
fill(v);
// Alloco mem device
cudaMalloc((void **) &u_device, sizeof(float)*VECT_SIZE);
cudaMalloc((void **) &v_device, sizeof(float)*VECT_SIZE);
cudaMalloc((void **) &w_device, sizeof(float)*VECT_SIZE);
// H --> D
cudaMemcpy(u_device, u, sizeof(float)*VECT_SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(v_device, v, sizeof(float)*VECT_SIZE, cudaMemcpyHostToDevice);
// Kernel call
VectorAdd<<<1,1>>>(w_device, u_device, v_device, VECT_SIZE);
// D --> H
cudaMemcpy(w, w_device, sizeof(float)*VECT_SIZE, cudaMemcpyDeviceToHost);
// check ?
for (int i = 0; i < VECT_SIZE; i++) {
if (!((w[i]-u[i]-v[i]) < THRESHOLD)) {
fprintf(stderr,"Got mistake!\n");
}
}
cudaFree(u_device);
cudaFree(v_device);
cudaFree(w_device);
free(u);
free(v);
free(w);
} | .file "tmpxft_000888f3_00000000-6_single_thread_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4fillPf
.type _Z4fillPf, @function
_Z4fillPf:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
.L4:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdi,%rax,4)
addq $1, %rax
cmpq $10000000, %rax
jne .L4
ret
.cfi_endproc
.LFE2057:
.size _Z4fillPf, .-_Z4fillPf
.globl _Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i
.type _Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9VectorAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i
.globl _Z9VectorAddPfS_S_i
.type _Z9VectorAddPfS_S_i, @function
_Z9VectorAddPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9VectorAddPfS_S_i, .-_Z9VectorAddPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Got mistake!\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $40000000, %edi
call malloc@PLT
movq %rax, %r12
movl $40000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $40000000, %edi
call malloc@PLT
movq %rax, %r13
movq %r12, %rdi
call _Z4fillPf
movq %rbp, %rdi
call _Z4fillPf
leaq 8(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40000000, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40000000, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L15:
movl $2, %ecx
movl $40000000, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC1(%rip), %r14
jmp .L17
.L21:
movl $10000000, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i
jmp .L15
.L16:
addq $4, %rbx
cmpq $40000000, %rbx
je .L22
.L17:
movss 0(%r13,%rbx), %xmm0
subss (%r12,%rbx), %xmm0
subss 0(%rbp,%rbx), %xmm0
cvtss2sd %xmm0, %xmm0
movsd .LC0(%rip), %xmm1
comisd %xmm0, %xmm1
ja .L16
movq %r14, %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L16
.L22:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z9VectorAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9VectorAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1698910392
.long 1048238066
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define VECT_SIZE 10000000
#define THRESHOLD 1.e-7
__global__ void VectorAdd(float *w, float *u, float *v, int n) {
for (int i = 0; i < n; i++) {
w[i] = u[i] + v[i];
}
}
void fill(float *v) {
for (int i = 0; i < VECT_SIZE; i++) {
v[i] = (float)i;
}
}
int main() {
// Host pointers
float *u, *v, *w;
// Device pointers
float *u_device, *v_device, *w_device;
// Alloco mem host
u = (float *) malloc(sizeof(float)*VECT_SIZE);
v = (float *) malloc(sizeof(float)*VECT_SIZE);
w = (float *) malloc(sizeof(float)*VECT_SIZE);
fill(u);
fill(v);
// Alloco mem device
cudaMalloc((void **) &u_device, sizeof(float)*VECT_SIZE);
cudaMalloc((void **) &v_device, sizeof(float)*VECT_SIZE);
cudaMalloc((void **) &w_device, sizeof(float)*VECT_SIZE);
// H --> D
cudaMemcpy(u_device, u, sizeof(float)*VECT_SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(v_device, v, sizeof(float)*VECT_SIZE, cudaMemcpyHostToDevice);
// Kernel call
VectorAdd<<<1,1>>>(w_device, u_device, v_device, VECT_SIZE);
// D --> H
cudaMemcpy(w, w_device, sizeof(float)*VECT_SIZE, cudaMemcpyDeviceToHost);
// check ?
for (int i = 0; i < VECT_SIZE; i++) {
if (!((w[i]-u[i]-v[i]) < THRESHOLD)) {
fprintf(stderr,"Got mistake!\n");
}
}
cudaFree(u_device);
cudaFree(v_device);
cudaFree(w_device);
free(u);
free(v);
free(w);
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define VECT_SIZE 10000000
#define THRESHOLD 1.e-7
__global__ void VectorAdd(float *w, float *u, float *v, int n) {
for (int i = 0; i < n; i++) {
w[i] = u[i] + v[i];
}
}
void fill(float *v) {
for (int i = 0; i < VECT_SIZE; i++) {
v[i] = (float)i;
}
}
int main() {
// Host pointers
float *u, *v, *w;
// Device pointers
float *u_device, *v_device, *w_device;
// Alloco mem host
u = (float *) malloc(sizeof(float)*VECT_SIZE);
v = (float *) malloc(sizeof(float)*VECT_SIZE);
w = (float *) malloc(sizeof(float)*VECT_SIZE);
fill(u);
fill(v);
// Alloco mem device
hipMalloc((void **) &u_device, sizeof(float)*VECT_SIZE);
hipMalloc((void **) &v_device, sizeof(float)*VECT_SIZE);
hipMalloc((void **) &w_device, sizeof(float)*VECT_SIZE);
// H --> D
hipMemcpy(u_device, u, sizeof(float)*VECT_SIZE, hipMemcpyHostToDevice);
hipMemcpy(v_device, v, sizeof(float)*VECT_SIZE, hipMemcpyHostToDevice);
// Kernel call
VectorAdd<<<1,1>>>(w_device, u_device, v_device, VECT_SIZE);
// D --> H
hipMemcpy(w, w_device, sizeof(float)*VECT_SIZE, hipMemcpyDeviceToHost);
// check ?
for (int i = 0; i < VECT_SIZE; i++) {
if (!((w[i]-u[i]-v[i]) < THRESHOLD)) {
fprintf(stderr,"Got mistake!\n");
}
}
hipFree(u_device);
hipFree(v_device);
hipFree(w_device);
free(u);
free(v);
free(w);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define VECT_SIZE 10000000
#define THRESHOLD 1.e-7
__global__ void VectorAdd(float *w, float *u, float *v, int n) {
for (int i = 0; i < n; i++) {
w[i] = u[i] + v[i];
}
}
void fill(float *v) {
for (int i = 0; i < VECT_SIZE; i++) {
v[i] = (float)i;
}
}
int main() {
// Host pointers
float *u, *v, *w;
// Device pointers
float *u_device, *v_device, *w_device;
// Alloco mem host
u = (float *) malloc(sizeof(float)*VECT_SIZE);
v = (float *) malloc(sizeof(float)*VECT_SIZE);
w = (float *) malloc(sizeof(float)*VECT_SIZE);
fill(u);
fill(v);
// Alloco mem device
hipMalloc((void **) &u_device, sizeof(float)*VECT_SIZE);
hipMalloc((void **) &v_device, sizeof(float)*VECT_SIZE);
hipMalloc((void **) &w_device, sizeof(float)*VECT_SIZE);
// H --> D
hipMemcpy(u_device, u, sizeof(float)*VECT_SIZE, hipMemcpyHostToDevice);
hipMemcpy(v_device, v, sizeof(float)*VECT_SIZE, hipMemcpyHostToDevice);
// Kernel call
VectorAdd<<<1,1>>>(w_device, u_device, v_device, VECT_SIZE);
// D --> H
hipMemcpy(w, w_device, sizeof(float)*VECT_SIZE, hipMemcpyDeviceToHost);
// check ?
for (int i = 0; i < VECT_SIZE; i++) {
if (!((w[i]-u[i]-v[i]) < THRESHOLD)) {
fprintf(stderr,"Got mistake!\n");
}
}
hipFree(u_device);
hipFree(v_device);
hipFree(w_device);
free(u);
free(v);
free(w);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9VectorAddPfS_S_i
.globl _Z9VectorAddPfS_S_i
.p2align 8
.type _Z9VectorAddPfS_S_i,@function
_Z9VectorAddPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_add_i32 s2, s2, -1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[4:5]
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s2, 0
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9VectorAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9VectorAddPfS_S_i, .Lfunc_end0-_Z9VectorAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9VectorAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9VectorAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define VECT_SIZE 10000000
#define THRESHOLD 1.e-7
__global__ void VectorAdd(float *w, float *u, float *v, int n) {
for (int i = 0; i < n; i++) {
w[i] = u[i] + v[i];
}
}
void fill(float *v) {
for (int i = 0; i < VECT_SIZE; i++) {
v[i] = (float)i;
}
}
int main() {
// Host pointers
float *u, *v, *w;
// Device pointers
float *u_device, *v_device, *w_device;
// Alloco mem host
u = (float *) malloc(sizeof(float)*VECT_SIZE);
v = (float *) malloc(sizeof(float)*VECT_SIZE);
w = (float *) malloc(sizeof(float)*VECT_SIZE);
fill(u);
fill(v);
// Alloco mem device
hipMalloc((void **) &u_device, sizeof(float)*VECT_SIZE);
hipMalloc((void **) &v_device, sizeof(float)*VECT_SIZE);
hipMalloc((void **) &w_device, sizeof(float)*VECT_SIZE);
// H --> D
hipMemcpy(u_device, u, sizeof(float)*VECT_SIZE, hipMemcpyHostToDevice);
hipMemcpy(v_device, v, sizeof(float)*VECT_SIZE, hipMemcpyHostToDevice);
// Kernel call
VectorAdd<<<1,1>>>(w_device, u_device, v_device, VECT_SIZE);
// D --> H
hipMemcpy(w, w_device, sizeof(float)*VECT_SIZE, hipMemcpyDeviceToHost);
// check ?
for (int i = 0; i < VECT_SIZE; i++) {
if (!((w[i]-u[i]-v[i]) < THRESHOLD)) {
fprintf(stderr,"Got mistake!\n");
}
}
hipFree(u_device);
hipFree(v_device);
hipFree(w_device);
free(u);
free(v);
free(w);
} | .text
.file "single_thread_hello.hip"
.globl _Z24__device_stub__VectorAddPfS_S_i # -- Begin function _Z24__device_stub__VectorAddPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__VectorAddPfS_S_i,@function
_Z24__device_stub__VectorAddPfS_S_i: # @_Z24__device_stub__VectorAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9VectorAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__VectorAddPfS_S_i, .Lfunc_end0-_Z24__device_stub__VectorAddPfS_S_i
.cfi_endproc
# -- End function
.globl _Z4fillPf # -- Begin function _Z4fillPf
.p2align 4, 0x90
.type _Z4fillPf,@function
_Z4fillPf: # @_Z4fillPf
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rdi,%rax,4)
incq %rax
cmpq $10000000, %rax # imm = 0x989680
jne .LBB1_1
# %bb.2:
retq
.Lfunc_end1:
.size _Z4fillPf, .Lfunc_end1-_Z4fillPf
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3e7ad7f29abcaf48 # double 9.9999999999999995E-8
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %rbx
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %r14
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $10000000, %rax # imm = 0x989680
jne .LBB2_1
# %bb.2: # %_Z4fillPf.exit.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # %_Z4fillPf.exit
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $10000000, %rax # imm = 0x989680
jne .LBB2_3
# %bb.4: # %_Z4fillPf.exit21
leaq 24(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
leaq 16(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
movq 24(%rsp), %rdi
movl $40000000, %edx # imm = 0x2625A00
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $40000000, %edx # imm = 0x2625A00
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $10000000, 36(%rsp) # imm = 0x989680
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9VectorAddPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rsi
movl $40000000, %edx # imm = 0x2625A00
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
jmp .LBB2_7
.p2align 4, 0x90
.LBB2_9: # in Loop: Header=BB2_7 Depth=1
incq %r12
cmpq $10000000, %r12 # imm = 0x989680
je .LBB2_10
.LBB2_7: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rbx,%r12,4), %xmm0
subss (%r14,%r12,4), %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd %xmm0, %xmm1
ja .LBB2_9
# %bb.8: # in Loop: Header=BB2_7 Depth=1
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $13, %esi
movl $1, %edx
callq fwrite@PLT
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
jmp .LBB2_9
.LBB2_10:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9VectorAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9VectorAddPfS_S_i,@object # @_Z9VectorAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z9VectorAddPfS_S_i
.p2align 3, 0x0
_Z9VectorAddPfS_S_i:
.quad _Z24__device_stub__VectorAddPfS_S_i
.size _Z9VectorAddPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Got mistake!\n"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9VectorAddPfS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__VectorAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9VectorAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9VectorAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0xb80 ; /* 0x00000ae000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R8, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000087a10 */
/* 0x000fe20007ffe1ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fe200078e00ff */
/*0120*/ MOV R6, c[0x0][0x168] ; /* 0x00005a0000067a02 */
/* 0x000fd20000000f00 */
/*0130*/ @!P0 BRA 0x990 ; /* 0x0000085000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0160*/ @!P1 BRA 0x670 ; /* 0x0000050000009947 */
/* 0x000fea0003800000 */
/*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0180*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*01a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*01b0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c10190c */
/*01c0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*01f0*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c10190c */
/*0200*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea4000c1e1900 */
/*0220*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0230*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0005e8000c10190c */
/*0240*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x000ee8000c1e1900 */
/*0250*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x000ee4000c1e1900 */
/*0260*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x008fca0000000000 */
/*0270*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0007e8000c10190c */
/*0280*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100c02097981 */
/* 0x001f28000c1e1900 */
/*0290*/ LDG.E R10, [R6.64+0x10] ; /* 0x0000100c060a7981 */
/* 0x000f24000c1e1900 */
/*02a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*02b0*/ STG.E [R4.64+0x10], R9 ; /* 0x0000100904007986 */
/* 0x0001e8000c10190c */
/*02c0*/ LDG.E R10, [R2.64+0x14] ; /* 0x0000140c020a7981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R11, [R6.64+0x14] ; /* 0x0000140c060b7981 */
/* 0x002f24000c1e1900 */
/*02e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*02f0*/ STG.E [R4.64+0x14], R11 ; /* 0x0000140b04007986 */
/* 0x0003e8000c10190c */
/*0300*/ LDG.E R10, [R2.64+0x18] ; /* 0x0000180c020a7981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R13, [R6.64+0x18] ; /* 0x0000180c060d7981 */
/* 0x004f24000c1e1900 */
/*0320*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0330*/ STG.E [R4.64+0x18], R13 ; /* 0x0000180d04007986 */
/* 0x0005e8000c10190c */
/*0340*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c0c020a7981 */
/* 0x000f28000c1e1900 */
/*0350*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c0c060f7981 */
/* 0x008f24000c1e1900 */
/*0360*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x010fca0000000000 */
/*0370*/ STG.E [R4.64+0x1c], R15 ; /* 0x00001c0f04007986 */
/* 0x0007e8000c10190c */
/*0380*/ LDG.E R9, [R2.64+0x20] ; /* 0x0000200c02097981 */
/* 0x001f28000c1e1900 */
/*0390*/ LDG.E R10, [R6.64+0x20] ; /* 0x0000200c060a7981 */
/* 0x000f24000c1e1900 */
/*03a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*03b0*/ STG.E [R4.64+0x20], R9 ; /* 0x0000200904007986 */
/* 0x0001e8000c10190c */
/*03c0*/ LDG.E R10, [R2.64+0x24] ; /* 0x0000240c020a7981 */
/* 0x000f28000c1e1900 */
/*03d0*/ LDG.E R11, [R6.64+0x24] ; /* 0x0000240c060b7981 */
/* 0x002f24000c1e1900 */
/*03e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*03f0*/ STG.E [R4.64+0x24], R11 ; /* 0x0000240b04007986 */
/* 0x0003e8000c10190c */
/*0400*/ LDG.E R10, [R2.64+0x28] ; /* 0x0000280c020a7981 */
/* 0x000f28000c1e1900 */
/*0410*/ LDG.E R13, [R6.64+0x28] ; /* 0x0000280c060d7981 */
/* 0x004f24000c1e1900 */
/*0420*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0430*/ STG.E [R4.64+0x28], R13 ; /* 0x0000280d04007986 */
/* 0x0005e8000c10190c */
/*0440*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c0c020a7981 */
/* 0x000f28000c1e1900 */
/*0450*/ LDG.E R15, [R6.64+0x2c] ; /* 0x00002c0c060f7981 */
/* 0x008f24000c1e1900 */
/*0460*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x010fca0000000000 */
/*0470*/ STG.E [R4.64+0x2c], R15 ; /* 0x00002c0f04007986 */
/* 0x0007e8000c10190c */
/*0480*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300c02097981 */
/* 0x001f28000c1e1900 */
/*0490*/ LDG.E R10, [R6.64+0x30] ; /* 0x0000300c060a7981 */
/* 0x000f24000c1e1900 */
/*04a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*04b0*/ STG.E [R4.64+0x30], R9 ; /* 0x0000300904007986 */
/* 0x000fe8000c10190c */
/*04c0*/ LDG.E R10, [R2.64+0x34] ; /* 0x0000340c020a7981 */
/* 0x000f28000c1e1900 */
/*04d0*/ LDG.E R11, [R6.64+0x34] ; /* 0x0000340c060b7981 */
/* 0x002f24000c1e1900 */
/*04e0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*04f0*/ STG.E [R4.64+0x34], R11 ; /* 0x0000340b04007986 */
/* 0x0001e8000c10190c */
/*0500*/ LDG.E R10, [R2.64+0x38] ; /* 0x0000380c020a7981 */
/* 0x000f28000c1e1900 */
/*0510*/ LDG.E R13, [R6.64+0x38] ; /* 0x0000380c060d7981 */
/* 0x004f22000c1e1900 */
/*0520*/ IADD3 R12, P1, R2, 0x40, RZ ; /* 0x00000040020c7810 */
/* 0x000fe40007f3e0ff */
/*0530*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*0540*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0550*/ STG.E [R4.64+0x38], R13 ; /* 0x0000380d04007986 */
/* 0x000fe8000c10190c */
/*0560*/ LDG.E R10, [R2.64+0x3c] ; /* 0x00003c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0570*/ LDG.E R15, [R6.64+0x3c] ; /* 0x00003c0c060f7981 */
/* 0x0086a2000c1e1900 */
/*0580*/ IADD3.X R11, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0b7210 */
/* 0x001fe20000ffe4ff */
/*0590*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*05a0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fc40003f24270 */
/*05b0*/ IADD3 R9, P3, R4, 0x40, RZ ; /* 0x0000004004097810 */
/* 0x000fe20007f7e0ff */
/*05c0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000c */
/*05d0*/ IADD3 R14, P2, R6, 0x40, RZ ; /* 0x00000040060e7810 */
/* 0x000fe40007f5e0ff */
/*05e0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fc60000000f00 */
/*05f0*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x008fe400010e0607 */
/*0600*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000e */
/*0610*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0620*/ IADD3.X R10, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc80001ffe4ff */
/*0630*/ STG.E [R4.64+0x3c], R15 ; /* 0x00003c0f04007986 */
/* 0x0001e4000c10190c */
/*0640*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0650*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*0660*/ @P1 BRA 0x180 ; /* 0xfffffb1000001947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x970 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0690*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*06a0*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*06b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*06c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c10190c */
/*06d0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*06e0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*06f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0700*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c10190c */
/*0710*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0720*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea4000c1e1900 */
/*0730*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0740*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0005e8000c10190c */
/*0750*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x000ee8000c1e1900 */
/*0760*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x000ee4000c1e1900 */
/*0770*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x008fca0000000000 */
/*0780*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0007e8000c10190c */
/*0790*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100c02097981 */
/* 0x001f28000c1e1900 */
/*07a0*/ LDG.E R10, [R6.64+0x10] ; /* 0x0000100c060a7981 */
/* 0x000f24000c1e1900 */
/*07b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fca0000000000 */
/*07c0*/ STG.E [R4.64+0x10], R9 ; /* 0x0000100904007986 */
/* 0x000fe8000c10190c */
/*07d0*/ LDG.E R10, [R2.64+0x14] ; /* 0x0000140c020a7981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R11, [R6.64+0x14] ; /* 0x0000140c060b7981 */
/* 0x002f24000c1e1900 */
/*07f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x010fca0000000000 */
/*0800*/ STG.E [R4.64+0x14], R11 ; /* 0x0000140b04007986 */
/* 0x0001e8000c10190c */
/*0810*/ LDG.E R10, [R2.64+0x18] ; /* 0x0000180c020a7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R13, [R6.64+0x18] ; /* 0x0000180c060d7981 */
/* 0x004f24000c1e1900 */
/*0830*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x010fca0000000000 */
/*0840*/ STG.E [R4.64+0x18], R13 ; /* 0x0000180d04007986 */
/* 0x000fe8000c10190c */
/*0850*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0860*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c0c060f7981 */
/* 0x0086a2000c1e1900 */
/*0870*/ IADD3 R11, P2, R2, 0x20, RZ ; /* 0x00000020020b7810 */
/* 0x001fe20007f5e0ff */
/*0880*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0890*/ IADD3 R9, P3, R4, 0x20, RZ ; /* 0x0000002004097810 */
/* 0x000fc40007f7e0ff */
/*08a0*/ IADD3 R14, P1, R6, 0x20, RZ ; /* 0x00000020060e7810 */
/* 0x000fe20007f3e0ff */
/*08b0*/ IMAD.X R12, RZ, RZ, R3, P2 ; /* 0x000000ffff0c7224 */
/* 0x000fe200010e0603 */
/*08c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*08d0*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000b */
/*08e0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*08f0*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x008fe200078e000e */
/*0900*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe40000ffe4ff */
/*0910*/ MOV R3, R12 ; /* 0x0000000c00037202 */
/* 0x000fe20000000f00 */
/*0920*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0930*/ IADD3.X R10, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc80001ffe4ff */
/*0940*/ STG.E [R4.64+0x1c], R15 ; /* 0x00001c0f04007986 */
/* 0x0001e4000c10190c */
/*0950*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0960*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000a */
/*0970*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb80 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0990*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*09b0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x004fca0000000000 */
/*09c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c10190c */
/*09d0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*09f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0a00*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0001e8000c10190c */
/*0a10*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0a20*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea2000c1e1900 */
/*0a30*/ IADD3 R12, P0, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fe40007f1e0ff */
/*0a40*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*0a60*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x000fe8000c10190c */
/*0a70*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0a80*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x0006a2000c1e1900 */
/*0a90*/ IADD3.X R11, RZ, R3, RZ, P0, !PT ; /* 0x00000003ff0b7210 */
/* 0x001fe200007fe4ff */
/*0aa0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0ab0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc40003f05270 */
/*0ac0*/ IADD3 R9, P2, R4, 0x10, RZ ; /* 0x0000001004097810 */
/* 0x000fe20007f5e0ff */
/*0ad0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000c */
/*0ae0*/ IADD3 R14, P1, R6, 0x10, RZ ; /* 0x00000010060e7810 */
/* 0x000fe40007f3e0ff */
/*0af0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fc60000000f00 */
/*0b00*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x008fe400008e0607 */
/*0b10*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000e */
/*0b20*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fe20000000000 */
/*0b30*/ IADD3.X R10, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc800017fe4ff */
/*0b40*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0001e4000c10190c */
/*0b50*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x001fe20000000f00 */
/*0b60*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*0b70*/ @P0 BRA 0x990 ; /* 0xfffffe1000000947 */
/* 0x000fea000383ffff */
/*0b80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0b90*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0ba0*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0bb0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0bc0*/ ULDC.64 UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe40000000a00 */
/*0bd0*/ ULDC.64 UR10, c[0x0][0x168] ; /* 0x00005a00000a7ab9 */
/* 0x000fe40000000a00 */
/*0be0*/ UIMAD.WIDE UR6, UR4, UR5, UR6 ; /* 0x00000005040672a5 */
/* 0x000fe4000f8e0206 */
/*0bf0*/ UIMAD.WIDE UR8, UR4, UR5, UR8 ; /* 0x00000005040872a5 */
/* 0x000fc4000f8e0208 */
/*0c00*/ UIMAD.WIDE UR4, UR4, UR5, UR10 ; /* 0x00000005040472a5 */
/* 0x000fca000f8e020a */
/*0c10*/ MOV R2, UR8 ; /* 0x0000000800027c02 */
/* 0x000fe20008000f00 */
/*0c20*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x000fe2000f8e00ff */
/*0c30*/ MOV R4, UR4 ; /* 0x0000000400047c02 */
/* 0x000fe20008000f00 */
/*0c40*/ IMAD.U32 R3, RZ, RZ, UR9 ; /* 0x00000009ff037e24 */
/* 0x000fc8000f8e00ff */
/*0c50*/ LDG.E R5, [R4.64] ; /* 0x0000000c04057981 */
/* 0x000ea8000c1e1900 */
/*0c60*/ LDG.E R2, [R2.64] ; /* 0x0000000c02027981 */
/* 0x000ea2000c1e1900 */
/*0c70*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0c80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0c90*/ UIADD3 UR8, UP1, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe2000ff3e03f */
/*0ca0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x001fe20008000f00 */
/*0cb0*/ UIADD3 UR6, UP0, UR6, 0x4, URZ ; /* 0x0000000406067890 */
/* 0x000fe2000ff1e03f */
/*0cc0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe20008000f00 */
/*0cd0*/ UIADD3 UR4, UP2, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000ff5e03f */
/*0ce0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0cf0*/ UIADD3.X UR9, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f097290 */
/* 0x000fe40008ffe43f */
/*0d00*/ UIADD3.X UR5, URZ, UR5, URZ, UP2, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200097fe43f */
/*0d10*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0d20*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e2000c10190c */
/*0d30*/ @P0 BRA 0xc10 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*0d40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d50*/ BRA 0xd50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9VectorAddPfS_S_i
.globl _Z9VectorAddPfS_S_i
.p2align 8
.type _Z9VectorAddPfS_S_i,@function
_Z9VectorAddPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_add_i32 s2, s2, -1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[4:5]
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s2, 0
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9VectorAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9VectorAddPfS_S_i, .Lfunc_end0-_Z9VectorAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9VectorAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9VectorAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000888f3_00000000-6_single_thread_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4fillPf
.type _Z4fillPf, @function
_Z4fillPf:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
.L4:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdi,%rax,4)
addq $1, %rax
cmpq $10000000, %rax
jne .L4
ret
.cfi_endproc
.LFE2057:
.size _Z4fillPf, .-_Z4fillPf
.globl _Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i
.type _Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9VectorAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i
.globl _Z9VectorAddPfS_S_i
.type _Z9VectorAddPfS_S_i, @function
_Z9VectorAddPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9VectorAddPfS_S_i, .-_Z9VectorAddPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Got mistake!\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $40000000, %edi
call malloc@PLT
movq %rax, %r12
movl $40000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $40000000, %edi
call malloc@PLT
movq %rax, %r13
movq %r12, %rdi
call _Z4fillPf
movq %rbp, %rdi
call _Z4fillPf
leaq 8(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40000000, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40000000, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L15:
movl $2, %ecx
movl $40000000, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC1(%rip), %r14
jmp .L17
.L21:
movl $10000000, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i
jmp .L15
.L16:
addq $4, %rbx
cmpq $40000000, %rbx
je .L22
.L17:
movss 0(%r13,%rbx), %xmm0
subss (%r12,%rbx), %xmm0
subss 0(%rbp,%rbx), %xmm0
cvtss2sd %xmm0, %xmm0
movsd .LC0(%rip), %xmm1
comisd %xmm0, %xmm1
ja .L16
movq %r14, %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L16
.L22:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z9VectorAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9VectorAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1698910392
.long 1048238066
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "single_thread_hello.hip"
.globl _Z24__device_stub__VectorAddPfS_S_i # -- Begin function _Z24__device_stub__VectorAddPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__VectorAddPfS_S_i,@function
_Z24__device_stub__VectorAddPfS_S_i: # @_Z24__device_stub__VectorAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9VectorAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__VectorAddPfS_S_i, .Lfunc_end0-_Z24__device_stub__VectorAddPfS_S_i
.cfi_endproc
# -- End function
.globl _Z4fillPf # -- Begin function _Z4fillPf
.p2align 4, 0x90
.type _Z4fillPf,@function
_Z4fillPf: # @_Z4fillPf
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rdi,%rax,4)
incq %rax
cmpq $10000000, %rax # imm = 0x989680
jne .LBB1_1
# %bb.2:
retq
.Lfunc_end1:
.size _Z4fillPf, .Lfunc_end1-_Z4fillPf
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3e7ad7f29abcaf48 # double 9.9999999999999995E-8
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %rbx
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %r14
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $10000000, %rax # imm = 0x989680
jne .LBB2_1
# %bb.2: # %_Z4fillPf.exit.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # %_Z4fillPf.exit
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $10000000, %rax # imm = 0x989680
jne .LBB2_3
# %bb.4: # %_Z4fillPf.exit21
leaq 24(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
leaq 16(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
movq 24(%rsp), %rdi
movl $40000000, %edx # imm = 0x2625A00
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $40000000, %edx # imm = 0x2625A00
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $10000000, 36(%rsp) # imm = 0x989680
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9VectorAddPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rsi
movl $40000000, %edx # imm = 0x2625A00
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
jmp .LBB2_7
.p2align 4, 0x90
.LBB2_9: # in Loop: Header=BB2_7 Depth=1
incq %r12
cmpq $10000000, %r12 # imm = 0x989680
je .LBB2_10
.LBB2_7: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rbx,%r12,4), %xmm0
subss (%r14,%r12,4), %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd %xmm0, %xmm1
ja .LBB2_9
# %bb.8: # in Loop: Header=BB2_7 Depth=1
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $13, %esi
movl $1, %edx
callq fwrite@PLT
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
jmp .LBB2_9
.LBB2_10:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9VectorAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9VectorAddPfS_S_i,@object # @_Z9VectorAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z9VectorAddPfS_S_i
.p2align 3, 0x0
_Z9VectorAddPfS_S_i:
.quad _Z24__device_stub__VectorAddPfS_S_i
.size _Z9VectorAddPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Got mistake!\n"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9VectorAddPfS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__VectorAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9VectorAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// Created by depaulsmiller on 9/9/20.
//
#include <chrono>
#include <algorithm>
#include <vector>
#include <iostream>
#include <functional>
#include <unordered_map>
#include <set>
#include <atomic>
#include <thread>
int main() {
int size = 136 * 512;
std::vector<std::pair<unsigned, unsigned>> vec;
vec.reserve(size);
for (int i = 0; i < size; i++) {
vec.push_back({rand(), 1});
}
std::vector<std::pair<unsigned, unsigned>> vec2;
vec2.reserve(size);
float *prob = new float[10000];
std::atomic_bool go{false};
std::atomic_int done{0};
std::vector<std::thread> threads;
int num_threads = 12;
threads.reserve(num_threads);
std::atomic_int caught;
for (int i = 0; i < num_threads; i++) {
threads.push_back(std::thread([&go, &done, &prob, &caught](std::pair<unsigned, unsigned> *data, int startidx, int endidx) {
while (!go);
int tmp = 0;
for (int i = startidx; i < endidx; i++) {
if (prob[data[i].first % 10000] < 0.01)
data[i].second = 1;
}
//caught.fetch_add(tmp);
std::atomic_thread_fence(std::memory_order_seq_cst);
done++;
//std::cerr << tmp << std::endl;
}, vec.data(), i * size / num_threads, i * size / num_threads + size / num_threads));
}
auto start = std::chrono::high_resolution_clock::now();
go = true;
while (done != num_threads);
auto end = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> dur = end - start;
for(auto& t : threads){
t.join();
}
std::cerr << dur.count() * 1e3 << " ms" << std::endl;
std::cerr << vec.size() / dur.count() / 1e6 << "Mops" << std::endl;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// Created by depaulsmiller on 9/9/20.
//
#include <chrono>
#include <algorithm>
#include <vector>
#include <iostream>
#include <functional>
#include <unordered_map>
#include <set>
#include <atomic>
#include <thread>
int main() {
int size = 136 * 512;
std::vector<std::pair<unsigned, unsigned>> vec;
vec.reserve(size);
for (int i = 0; i < size; i++) {
vec.push_back({rand(), 1});
}
std::vector<std::pair<unsigned, unsigned>> vec2;
vec2.reserve(size);
float *prob = new float[10000];
std::atomic_bool go{false};
std::atomic_int done{0};
std::vector<std::thread> threads;
int num_threads = 12;
threads.reserve(num_threads);
std::atomic_int caught;
for (int i = 0; i < num_threads; i++) {
threads.push_back(std::thread([&go, &done, &prob, &caught](std::pair<unsigned, unsigned> *data, int startidx, int endidx) {
while (!go);
int tmp = 0;
for (int i = startidx; i < endidx; i++) {
if (prob[data[i].first % 10000] < 0.01)
data[i].second = 1;
}
//caught.fetch_add(tmp);
std::atomic_thread_fence(std::memory_order_seq_cst);
done++;
//std::cerr << tmp << std::endl;
}, vec.data(), i * size / num_threads, i * size / num_threads + size / num_threads));
}
auto start = std::chrono::high_resolution_clock::now();
go = true;
while (done != num_threads);
auto end = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> dur = end - start;
for(auto& t : threads){
t.join();
}
std::cerr << dur.count() * 1e3 << " ms" << std::endl;
std::cerr << vec.size() / dur.count() / 1e6 << "Mops" << std::endl;
} | .file "tmpxft_001258a6_00000000-6_model_service_rate.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._ZNSt6thread24_M_thread_deps_never_runEv,"axG",@progbits,_ZNSt6thread24_M_thread_deps_never_runEv,comdat
.weak _ZNSt6thread24_M_thread_deps_never_runEv
.type _ZNSt6thread24_M_thread_deps_never_runEv, @function
_ZNSt6thread24_M_thread_deps_never_runEv:
.LFB5708:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE5708:
.size _ZNSt6thread24_M_thread_deps_never_runEv, .-_ZNSt6thread24_M_thread_deps_never_runEv
.text
.align 2
.type _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEED2Ev, @function
_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEED2Ev:
.LFB6815:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 16+_ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE(%rip), %rax
movq %rax, (%rdi)
call _ZNSt6thread6_StateD2Ev@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6815:
.size _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEED2Ev, .-_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEED2Ev
.set _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEED1Ev,_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEED2Ev
.align 2
.type _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEED0Ev, @function
_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEED0Ev:
.LFB6817:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE(%rip), %rax
movq %rax, (%rdi)
call _ZNSt6thread6_StateD2Ev@PLT
movl $56, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6817:
.size _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEED0Ev, .-_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEED0Ev
.align 2
.type _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEE6_M_runEv, @function
_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEE6_M_runEv:
.LFB6818:
.cfi_startproc
endbr64
movq %rdi, %rsi
movl 8(%rdi), %edx
movl 12(%rdi), %edi
movq 16(%rsi), %r8
.L7:
movq 24(%rsi), %rax
movzbl (%rax), %eax
testb %al, %al
je .L7
cmpl %edi, %edx
jle .L8
movslq %edi, %rax
leaq (%r8,%rax,8), %rcx
subl %edi, %edx
addq %rax, %rdx
leaq (%r8,%rdx,8), %r9
movl $3518437209, %r8d
movsd .LC0(%rip), %xmm1
jmp .L11
.L9:
addq $8, %rcx
cmpq %r9, %rcx
je .L8
.L11:
movq 40(%rsi), %rdi
movl (%rcx), %edx
movl %edx, %eax
imulq %r8, %rax
shrq $45, %rax
imull $10000, %eax, %eax
subl %eax, %edx
movq (%rdi), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rdx,4), %xmm0
comisd %xmm0, %xmm1
jbe .L9
movl $1, 4(%rcx)
jmp .L9
.L8:
lock orq $0, (%rsp)
movq 32(%rsi), %rax
lock addl $1, (%rax)
ret
.cfi_endproc
.LFE6818:
.size _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEE6_M_runEv, .-_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEE6_M_runEv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5779:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5779:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB5802:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5802:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorISt4pairIjjESaIS1_EED2Ev,"axG",@progbits,_ZNSt6vectorISt4pairIjjESaIS1_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorISt4pairIjjESaIS1_EED2Ev
.type _ZNSt6vectorISt4pairIjjESaIS1_EED2Ev, @function
_ZNSt6vectorISt4pairIjjESaIS1_EED2Ev:
.LFB6205:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L22
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L22:
ret
.cfi_endproc
.LFE6205:
.size _ZNSt6vectorISt4pairIjjESaIS1_EED2Ev, .-_ZNSt6vectorISt4pairIjjESaIS1_EED2Ev
.weak _ZNSt6vectorISt4pairIjjESaIS1_EED1Ev
.set _ZNSt6vectorISt4pairIjjESaIS1_EED1Ev,_ZNSt6vectorISt4pairIjjESaIS1_EED2Ev
.section .rodata._ZNSt6vectorISt4pairIjjESaIS1_EE7reserveEm.str1.1,"aMS",@progbits,1
.LC1:
.string "vector::reserve"
.section .text._ZNSt6vectorISt4pairIjjESaIS1_EE7reserveEm,"axG",@progbits,_ZNSt6vectorISt4pairIjjESaIS1_EE7reserveEm,comdat
.align 2
.weak _ZNSt6vectorISt4pairIjjESaIS1_EE7reserveEm
.type _ZNSt6vectorISt4pairIjjESaIS1_EE7reserveEm, @function
_ZNSt6vectorISt4pairIjjESaIS1_EE7reserveEm:
.LFB6207:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %rax
shrq $60, %rax
jne .L33
movq %rdi, %rbx
movq (%rdi), %rdx
movq 16(%rdi), %rax
subq %rdx, %rax
sarq $3, %rax
cmpq %rsi, %rax
jnb .L25
movq 8(%rdi), %r13
subq %rdx, %r13
leaq 0(,%rsi,8), %rbp
movq %rbp, %rdi
call _Znwm@PLT
movq %rax, %r12
movq 8(%rbx), %rsi
movq (%rbx), %rdi
cmpq %rdi, %rsi
je .L28
movq %rax, %rdx
movq %rdi, %rax
.L29:
movq (%rax), %rcx
movq %rcx, (%rdx)
addq $8, %rax
addq $8, %rdx
cmpq %rax, %rsi
jne .L29
.L28:
testq %rdi, %rdi
je .L30
movq 16(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L30:
movq %r12, (%rbx)
addq %r12, %r13
movq %r13, 8(%rbx)
addq %rbp, %r12
movq %r12, 16(%rbx)
.L25:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
leaq .LC1(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.cfi_endproc
.LFE6207:
.size _ZNSt6vectorISt4pairIjjESaIS1_EE7reserveEm, .-_ZNSt6vectorISt4pairIjjESaIS1_EE7reserveEm
.section .text._ZNSt6vectorISt6threadSaIS0_EED2Ev,"axG",@progbits,_ZNSt6vectorISt6threadSaIS0_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorISt6threadSaIS0_EED2Ev
.type _ZNSt6vectorISt6threadSaIS0_EED2Ev, @function
_ZNSt6vectorISt6threadSaIS0_EED2Ev:
.LFB6226:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 8(%rdi), %rdx
movq (%rdi), %rcx
cmpq %rcx, %rdx
je .L35
movq %rcx, %rax
.L37:
cmpq $0, (%rax)
jne .L41
addq $8, %rax
cmpq %rax, %rdx
jne .L37
.L35:
testq %rcx, %rcx
je .L34
movq 16(%rdi), %rsi
subq %rcx, %rsi
movq %rcx, %rdi
call _ZdlPvm@PLT
.L34:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
call _ZSt9terminatev@PLT
.cfi_endproc
.LFE6226:
.size _ZNSt6vectorISt6threadSaIS0_EED2Ev, .-_ZNSt6vectorISt6threadSaIS0_EED2Ev
.weak _ZNSt6vectorISt6threadSaIS0_EED1Ev
.set _ZNSt6vectorISt6threadSaIS0_EED1Ev,_ZNSt6vectorISt6threadSaIS0_EED2Ev
.section .rodata._ZNSt6vectorISt4pairIjjESaIS1_EE17_M_realloc_insertIJS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_.str1.1,"aMS",@progbits,1
.LC2:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorISt4pairIjjESaIS1_EE17_M_realloc_insertIJS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_,"axG",@progbits,_ZNSt6vectorISt4pairIjjESaIS1_EE17_M_realloc_insertIJS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorISt4pairIjjESaIS1_EE17_M_realloc_insertIJS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_
.type _ZNSt6vectorISt4pairIjjESaIS1_EE17_M_realloc_insertIJS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_, @function
_ZNSt6vectorISt4pairIjjESaIS1_EE17_M_realloc_insertIJS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_:
.LFB6587:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r12
movq %rbp, %rax
subq %r12, %rax
sarq $3, %rax
movabsq $1152921504606846975, %rdx
cmpq %rdx, %rax
je .L60
movq %rdi, %r14
movq %rsi, %r13
movq %rsi, %rbx
cmpq %r12, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L45
movabsq $1152921504606846975, %rdx
cmpq %rdx, %rax
cmovbe %rax, %rdx
movq %rdx, 16(%rsp)
movq %rsi, %rdi
subq %r12, %rdi
movq %rdi, 24(%rsp)
movl $0, %r15d
testq %rax, %rax
je .L46
jmp .L52
.L60:
leaq .LC2(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L55:
movq %r15, %rsi
jmp .L47
.L45:
movq %rsi, %rax
subq %r12, %rax
movq %rax, 24(%rsp)
movabsq $1152921504606846975, %rax
movq %rax, 16(%rsp)
.L52:
movq 16(%rsp), %rax
leaq 0(,%rax,8), %rdi
call _Znwm@PLT
movq %rax, %r15
.L46:
movq 8(%rsp), %rax
movq (%rax), %rax
movq 24(%rsp), %rdi
movq %rax, (%r15,%rdi)
cmpq %r12, %r13
je .L55
movq %r13, %rsi
subq %r12, %rsi
addq %r15, %rsi
movq %r15, %rax
movq %r12, %rdx
.L48:
movq (%rdx), %rcx
movq %rcx, (%rax)
addq $8, %rdx
addq $8, %rax
cmpq %rax, %rsi
jne .L48
.L47:
leaq 8(%rsi), %rax
movq %rax, 8(%rsp)
cmpq %rbp, %r13
je .L49
movq %rbp, %rcx
subq %r13, %rcx
.L50:
movq (%rbx), %rdx
movq %rdx, (%rax)
addq $8, %rbx
addq $8, %rax
cmpq %rbp, %rbx
jne .L50
addq %rcx, 8(%rsp)
.L49:
testq %r12, %r12
je .L51
movq 16(%r14), %rsi
subq %r12, %rsi
movq %r12, %rdi
call _ZdlPvm@PLT
.L51:
movq %r15, (%r14)
movq 8(%rsp), %rax
movq %rax, 8(%r14)
movq 16(%rsp), %rax
leaq (%r15,%rax,8), %rax
movq %rax, 16(%r14)
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6587:
.size _ZNSt6vectorISt4pairIjjESaIS1_EE17_M_realloc_insertIJS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_, .-_ZNSt6vectorISt4pairIjjESaIS1_EE17_M_realloc_insertIJS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_
.section .text._ZNSt6vectorISt6threadSaIS0_EE17_M_realloc_insertIJS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_,"axG",@progbits,_ZNSt6vectorISt6threadSaIS0_EE17_M_realloc_insertIJS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorISt6threadSaIS0_EE17_M_realloc_insertIJS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_
.type _ZNSt6vectorISt6threadSaIS0_EE17_M_realloc_insertIJS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_, @function
_ZNSt6vectorISt6threadSaIS0_EE17_M_realloc_insertIJS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_:
.LFB6622:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r12
movq %rbp, %rax
subq %r12, %rax
sarq $3, %rax
movabsq $1152921504606846975, %rdx
cmpq %rdx, %rax
je .L79
movq %rdi, %r14
movq %rsi, %r13
movq %rsi, %rbx
cmpq %r12, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L64
movabsq $1152921504606846975, %rdx
cmpq %rdx, %rax
cmovbe %rax, %rdx
movq %rdx, 16(%rsp)
subq %r12, %rsi
movq %rsi, 24(%rsp)
movl $0, %r15d
testq %rax, %rax
je .L65
jmp .L71
.L79:
leaq .LC2(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L74:
movq %r15, %rax
jmp .L66
.L64:
movq %rsi, %rax
subq %r12, %rax
movq %rax, 24(%rsp)
movabsq $1152921504606846975, %rax
movq %rax, 16(%rsp)
.L71:
movq 16(%rsp), %rax
leaq 0(,%rax,8), %rdi
call _Znwm@PLT
movq %rax, %r15
.L65:
movq 8(%rsp), %rdi
movq (%rdi), %rax
movq 24(%rsp), %rsi
movq %rax, (%r15,%rsi)
movq $0, (%rdi)
cmpq %r12, %r13
je .L74
movq %r13, %rsi
subq %r12, %rsi
movq %r12, %rax
movq %r15, %rdx
.L67:
movq (%rax), %rcx
movq %rcx, (%rdx)
addq $8, %rax
addq $8, %rdx
cmpq %rbx, %rax
jne .L67
leaq (%r15,%rsi), %rax
.L66:
addq $8, %rax
movq %rax, 8(%rsp)
cmpq %rbp, %r13
je .L68
movq %rbp, %rcx
subq %r13, %rcx
.L69:
movq (%rbx), %rdx
movq %rdx, (%rax)
addq $8, %rbx
addq $8, %rax
cmpq %rbp, %rbx
jne .L69
addq %rcx, 8(%rsp)
.L68:
testq %r12, %r12
je .L70
movq 16(%r14), %rsi
subq %r12, %rsi
movq %r12, %rdi
call _ZdlPvm@PLT
.L70:
movq %r15, (%r14)
movq 8(%rsp), %rax
movq %rax, 8(%r14)
movq 16(%rsp), %rax
leaq (%r15,%rax,8), %rax
movq %rax, 16(%r14)
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6622:
.size _ZNSt6vectorISt6threadSaIS0_EE17_M_realloc_insertIJS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_, .-_ZNSt6vectorISt6threadSaIS0_EE17_M_realloc_insertIJS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string " ms"
.LC7:
.string "Mops"
.text
.globl main
.type main, @function
main:
.LFB5740:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA5740
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
leaq 64(%rsp), %rdi
movl $69632, %esi
.LEHB0:
call _ZNSt6vectorISt4pairIjjESaIS1_EE7reserveEm
movl $69632, %ebx
leaq 128(%rsp), %rbp
jmp .L83
.L81:
leaq 64(%rsp), %rdi
movq %rbp, %rdx
call _ZNSt6vectorISt4pairIjjESaIS1_EE17_M_realloc_insertIJS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_
.LEHE0:
.L82:
subl $1, %ebx
je .L115
.L83:
call rand@PLT
movl %eax, 128(%rsp)
movl $1, 132(%rsp)
movq 72(%rsp), %rsi
cmpq 80(%rsp), %rsi
je .L81
movq 128(%rsp), %rax
movq %rax, (%rsi)
addq $8, %rsi
movq %rsi, 72(%rsp)
jmp .L82
.L115:
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
leaq 96(%rsp), %rdi
movl $69632, %esi
.LEHB1:
call _ZNSt6vectorISt4pairIjjESaIS1_EE7reserveEm
movl $40000, %edi
call _Znam@PLT
.LEHE1:
movq %rax, 40(%rsp)
movb $0, 31(%rsp)
movl $0, 32(%rsp)
movq $0, 128(%rsp)
movq $0, 136(%rsp)
movq $0, 144(%rsp)
movl $96, %edi
.LEHB2:
call _Znwm@PLT
.LEHE2:
movq %rax, 128(%rsp)
movq %rax, 136(%rsp)
addq $96, %rax
movq %rax, 144(%rsp)
leaq 31(%rsp), %r14
leaq 32(%rsp), %r15
jmp .L91
.L118:
leaq 16+_ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE(%rip), %rcx
movq %rcx, (%rax)
movl %r13d, 8(%rax)
movl %ebp, 12(%rax)
movq %r12, 16(%rax)
movq %r14, 24(%rax)
movq %r15, 32(%rax)
leaq 40(%rsp), %rdx
movq %rdx, 40(%rax)
leaq 36(%rsp), %rdx
movq %rdx, 48(%rax)
movq %rax, 56(%rsp)
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdi
leaq _ZNSt6thread24_M_thread_deps_never_runEv(%rip), %rdx
.LEHB3:
call _ZNSt6thread15_M_start_threadESt10unique_ptrINS_6_StateESt14default_deleteIS1_EEPFvvE@PLT
.LEHE3:
movq 56(%rsp), %rdi
testq %rdi, %rdi
je .L84
movq (%rdi), %rax
call *8(%rax)
.L84:
movq 136(%rsp), %rsi
cmpq 144(%rsp), %rsi
je .L116
movq $0, (%rsi)
movq 48(%rsp), %rax
movq %rax, (%rsi)
addq $8, %rsi
movq %rsi, 136(%rsp)
.L90:
addl $69632, %ebx
cmpl $835584, %ebx
je .L117
.L91:
movslq %ebx, %rbp
imulq $715827883, %rbp, %rbp
sarq $33, %rbp
movl %ebx, %eax
sarl $31, %eax
subl %eax, %ebp
leal 5802(%rbp), %r13d
movq 64(%rsp), %r12
movq $0, 48(%rsp)
movl $56, %edi
.LEHB4:
call _Znwm@PLT
.LEHE4:
jmp .L118
.L107:
endbr64
movq %rax, %rbx
movq 56(%rsp), %rdi
testq %rdi, %rdi
je .L89
movq (%rdi), %rax
call *8(%rax)
.L89:
leaq 128(%rsp), %rdi
call _ZNSt6vectorISt6threadSaIS0_EED1Ev
.L99:
leaq 96(%rsp), %rdi
call _ZNSt6vectorISt4pairIjjESaIS1_EED1Ev
.L100:
leaq 64(%rsp), %rdi
call _ZNSt6vectorISt4pairIjjESaIS1_EED1Ev
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L101
call __stack_chk_fail@PLT
.L116:
leaq 48(%rsp), %rdx
leaq 128(%rsp), %rdi
.LEHB5:
call _ZNSt6vectorISt6threadSaIS0_EE17_M_realloc_insertIJS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_
.LEHE5:
cmpq $0, 48(%rsp)
je .L90
call _ZSt9terminatev@PLT
.L117:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl $1, %eax
xchgb 31(%rsp), %al
.L92:
movl 32(%rsp), %eax
cmpl $12, %eax
jne .L92
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC3(%rip), %xmm0
movsd %xmm0, 8(%rsp)
movq 128(%rsp), %rbx
movq 136(%rsp), %rbp
cmpq %rbx, %rbp
jne .L94
.L93:
movsd 8(%rsp), %xmm0
mulsd .LC4(%rip), %xmm0
leaq _ZSt4cerr(%rip), %rdi
.LEHB6:
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L119
.L120:
addq $8, %rbx
cmpq %rbx, %rbp
je .L93
.L94:
movq %rbx, %rdi
call _ZNSt6thread4joinEv@PLT
jmp .L120
.L119:
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 72(%rsp), %rax
subq 64(%rsp), %rax
sarq $3, %rax
js .L95
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L96:
divsd 8(%rsp), %xmm0
divsd .LC6(%rip), %xmm0
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L121
.L95:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L96
.L121:
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE6:
leaq 128(%rsp), %rdi
call _ZNSt6vectorISt6threadSaIS0_EED1Ev
leaq 96(%rsp), %rdi
call _ZNSt6vectorISt4pairIjjESaIS1_EED1Ev
leaq 64(%rsp), %rdi
call _ZNSt6vectorISt4pairIjjESaIS1_EED1Ev
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L122
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L106:
.cfi_restore_state
endbr64
movq %rax, %rbx
cmpq $0, 48(%rsp)
je .L89
call _ZSt9terminatev@PLT
.L105:
endbr64
movq %rax, %rbx
jmp .L89
.L104:
endbr64
movq %rax, %rbx
jmp .L99
.L103:
endbr64
movq %rax, %rbx
jmp .L100
.L101:
movq %rbx, %rdi
.LEHB7:
call _Unwind_Resume@PLT
.LEHE7:
.L122:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5740:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA5740:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE5740-.LLSDACSB5740
.LLSDACSB5740:
.uleb128 .LEHB0-.LFB5740
.uleb128 .LEHE0-.LEHB0
.uleb128 .L103-.LFB5740
.uleb128 0
.uleb128 .LEHB1-.LFB5740
.uleb128 .LEHE1-.LEHB1
.uleb128 .L104-.LFB5740
.uleb128 0
.uleb128 .LEHB2-.LFB5740
.uleb128 .LEHE2-.LEHB2
.uleb128 .L105-.LFB5740
.uleb128 0
.uleb128 .LEHB3-.LFB5740
.uleb128 .LEHE3-.LEHB3
.uleb128 .L107-.LFB5740
.uleb128 0
.uleb128 .LEHB4-.LFB5740
.uleb128 .LEHE4-.LEHB4
.uleb128 .L105-.LFB5740
.uleb128 0
.uleb128 .LEHB5-.LFB5740
.uleb128 .LEHE5-.LEHB5
.uleb128 .L106-.LFB5740
.uleb128 0
.uleb128 .LEHB6-.LFB5740
.uleb128 .LEHE6-.LEHB6
.uleb128 .L105-.LFB5740
.uleb128 0
.uleb128 .LEHB7-.LFB5740
.uleb128 .LEHE7-.LEHB7
.uleb128 0
.uleb128 0
.LLSDACSE5740:
.text
.size main, .-main
.section .data.rel.ro,"aw"
.align 8
.type _ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE, @object
.size _ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE, 24
_ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE
.quad _ZTINSt6thread6_StateE
.section .rodata
.align 32
.type _ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE, @object
.size _ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE, 85
_ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE:
.string "*NSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE"
.section .data.rel.ro.local,"aw"
.align 8
.type _ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE, @object
.size _ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE, 40
_ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE:
.quad 0
.quad _ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE
.quad _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEED1Ev
.quad _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEED0Ev
.quad _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEE6_M_runEv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 1202590843
.long 1065646817
.align 8
.LC3:
.long 0
.long 1104006501
.align 8
.LC4:
.long 0
.long 1083129856
.align 8
.LC6:
.long 0
.long 1093567616
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// Created by depaulsmiller on 9/9/20.
//
#include <chrono>
#include <algorithm>
#include <vector>
#include <iostream>
#include <functional>
#include <unordered_map>
#include <set>
#include <atomic>
#include <thread>
int main() {
int size = 136 * 512;
std::vector<std::pair<unsigned, unsigned>> vec;
vec.reserve(size);
for (int i = 0; i < size; i++) {
vec.push_back({rand(), 1});
}
std::vector<std::pair<unsigned, unsigned>> vec2;
vec2.reserve(size);
float *prob = new float[10000];
std::atomic_bool go{false};
std::atomic_int done{0};
std::vector<std::thread> threads;
int num_threads = 12;
threads.reserve(num_threads);
std::atomic_int caught;
for (int i = 0; i < num_threads; i++) {
threads.push_back(std::thread([&go, &done, &prob, &caught](std::pair<unsigned, unsigned> *data, int startidx, int endidx) {
while (!go);
int tmp = 0;
for (int i = startidx; i < endidx; i++) {
if (prob[data[i].first % 10000] < 0.01)
data[i].second = 1;
}
//caught.fetch_add(tmp);
std::atomic_thread_fence(std::memory_order_seq_cst);
done++;
//std::cerr << tmp << std::endl;
}, vec.data(), i * size / num_threads, i * size / num_threads + size / num_threads));
}
auto start = std::chrono::high_resolution_clock::now();
go = true;
while (done != num_threads);
auto end = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> dur = end - start;
for(auto& t : threads){
t.join();
}
std::cerr << dur.count() * 1e3 << " ms" << std::endl;
std::cerr << vec.size() / dur.count() / 1e6 << "Mops" << std::endl;
} | //
// Created by depaulsmiller on 9/9/20.
//
#include <hip/hip_runtime.h>
#include <chrono>
#include <algorithm>
#include <vector>
#include <iostream>
#include <functional>
#include <unordered_map>
#include <set>
#include <atomic>
#include <thread>
int main() {
int size = 136 * 512;
std::vector<std::pair<unsigned, unsigned>> vec;
vec.reserve(size);
for (int i = 0; i < size; i++) {
vec.push_back({rand(), 1});
}
std::vector<std::pair<unsigned, unsigned>> vec2;
vec2.reserve(size);
float *prob = new float[10000];
std::atomic_bool go{false};
std::atomic_int done{0};
std::vector<std::thread> threads;
int num_threads = 12;
threads.reserve(num_threads);
std::atomic_int caught;
for (int i = 0; i < num_threads; i++) {
threads.push_back(std::thread([&go, &done, &prob, &caught](std::pair<unsigned, unsigned> *data, int startidx, int endidx) {
while (!go);
int tmp = 0;
for (int i = startidx; i < endidx; i++) {
if (prob[data[i].first % 10000] < 0.01)
data[i].second = 1;
}
//caught.fetch_add(tmp);
std::atomic_thread_fence(std::memory_order_seq_cst);
done++;
//std::cerr << tmp << std::endl;
}, vec.data(), i * size / num_threads, i * size / num_threads + size / num_threads));
}
auto start = std::chrono::high_resolution_clock::now();
go = true;
while (done != num_threads);
auto end = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> dur = end - start;
for(auto& t : threads){
t.join();
}
std::cerr << dur.count() * 1e3 << " ms" << std::endl;
std::cerr << vec.size() / dur.count() / 1e6 << "Mops" << std::endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// Created by depaulsmiller on 9/9/20.
//
#include <hip/hip_runtime.h>
#include <chrono>
#include <algorithm>
#include <vector>
#include <iostream>
#include <functional>
#include <unordered_map>
#include <set>
#include <atomic>
#include <thread>
int main() {
int size = 136 * 512;
std::vector<std::pair<unsigned, unsigned>> vec;
vec.reserve(size);
for (int i = 0; i < size; i++) {
vec.push_back({rand(), 1});
}
std::vector<std::pair<unsigned, unsigned>> vec2;
vec2.reserve(size);
float *prob = new float[10000];
std::atomic_bool go{false};
std::atomic_int done{0};
std::vector<std::thread> threads;
int num_threads = 12;
threads.reserve(num_threads);
std::atomic_int caught;
for (int i = 0; i < num_threads; i++) {
threads.push_back(std::thread([&go, &done, &prob, &caught](std::pair<unsigned, unsigned> *data, int startidx, int endidx) {
while (!go);
int tmp = 0;
for (int i = startidx; i < endidx; i++) {
if (prob[data[i].first % 10000] < 0.01)
data[i].second = 1;
}
//caught.fetch_add(tmp);
std::atomic_thread_fence(std::memory_order_seq_cst);
done++;
//std::cerr << tmp << std::endl;
}, vec.data(), i * size / num_threads, i * size / num_threads + size / num_threads));
}
auto start = std::chrono::high_resolution_clock::now();
go = true;
while (done != num_threads);
auto end = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> dur = end - start;
for(auto& t : threads){
t.join();
}
std::cerr << dur.count() * 1e3 << " ms" << std::endl;
std::cerr << vec.size() / dur.count() / 1e6 << "Mops" << std::endl;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// Created by depaulsmiller on 9/9/20.
//
#include <hip/hip_runtime.h>
#include <chrono>
#include <algorithm>
#include <vector>
#include <iostream>
#include <functional>
#include <unordered_map>
#include <set>
#include <atomic>
#include <thread>
int main() {
int size = 136 * 512;
std::vector<std::pair<unsigned, unsigned>> vec;
vec.reserve(size);
for (int i = 0; i < size; i++) {
vec.push_back({rand(), 1});
}
std::vector<std::pair<unsigned, unsigned>> vec2;
vec2.reserve(size);
float *prob = new float[10000];
std::atomic_bool go{false};
std::atomic_int done{0};
std::vector<std::thread> threads;
int num_threads = 12;
threads.reserve(num_threads);
std::atomic_int caught;
for (int i = 0; i < num_threads; i++) {
threads.push_back(std::thread([&go, &done, &prob, &caught](std::pair<unsigned, unsigned> *data, int startidx, int endidx) {
while (!go);
int tmp = 0;
for (int i = startidx; i < endidx; i++) {
if (prob[data[i].first % 10000] < 0.01)
data[i].second = 1;
}
//caught.fetch_add(tmp);
std::atomic_thread_fence(std::memory_order_seq_cst);
done++;
//std::cerr << tmp << std::endl;
}, vec.data(), i * size / num_threads, i * size / num_threads + size / num_threads));
}
auto start = std::chrono::high_resolution_clock::now();
go = true;
while (done != num_threads);
auto end = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> dur = end - start;
for(auto& t : threads){
t.join();
}
std::cerr << dur.count() * 1e3 << " ms" << std::endl;
std::cerr << vec.size() / dur.count() / 1e6 << "Mops" << std::endl;
} | .text
.file "model_service_rate.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.LCPI0_1:
.quad 0x408f400000000000 # double 1000
.LCPI0_4:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_2:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI0_3:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt16allocator_traitsISaISt4pairIjjEEE8allocateERS2_m.exit.i.i
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.Ltmp0:
movl $557056, %edi # imm = 0x88000
callq _Znwm
.Ltmp1:
# %bb.1: # %_ZNSt12_Vector_baseISt4pairIjjESaIS1_EE13_M_deallocateEPS1_m.exit.i
movabsq $4294967296, %r13 # imm = 0x100000000
movq %rax, %rbx
addq $557056, %rbx # imm = 0x88000
xorl %r12d, %r12d
movq %rax, %rcx
movq %rax, 8(%rsp) # 8-byte Spill
movq %rax, %r15
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_3: # in Loop: Header=BB0_2 Depth=1
movl %eax, %eax
orq %r13, %rax
movq %rax, (%r15)
.LBB0_17: # %_ZNSt6vectorISt4pairIjjESaIS1_EE9push_backEOS1_.exit
# in Loop: Header=BB0_2 Depth=1
addq $8, %r15
incl %r12d
cmpl $69632, %r12d # imm = 0x11000
je .LBB0_18
.LBB0_2: # =>This Loop Header: Depth=1
# Child Loop BB0_13 Depth 2
callq rand
cmpq %rbx, %r15
jne .LBB0_3
# %bb.4: # in Loop: Header=BB0_2 Depth=1
movq %r15, %rbp
subq 8(%rsp), %rbp # 8-byte Folded Reload
movabsq $9223372036854775800, %rcx # imm = 0x7FFFFFFFFFFFFFF8
cmpq %rcx, %rbp
je .LBB0_5
# %bb.7: # %_ZNKSt6vectorISt4pairIjjESaIS1_EE12_M_check_lenEmPKc.exit.i
# in Loop: Header=BB0_2 Depth=1
sarq $3, %rbp
cmpq $1, %rbp
movq %rbp, %rcx
adcq $0, %rcx
leaq (%rcx,%rbp), %rbx
movabsq $1152921504606846975, %rdx # imm = 0xFFFFFFFFFFFFFFF
cmpq %rdx, %rbx
cmovaeq %rdx, %rbx
addq %rbp, %rcx
cmovbq %rdx, %rbx
testq %rbx, %rbx
je .LBB0_8
# %bb.9: # in Loop: Header=BB0_2 Depth=1
movl %eax, %r13d
leaq (,%rbx,8), %rdi
.Ltmp3:
callq _Znwm
.Ltmp4:
# %bb.10: # in Loop: Header=BB0_2 Depth=1
movq %rax, %r14
movl %r13d, %eax
movabsq $4294967296, %r13 # imm = 0x100000000
jmp .LBB0_11
.LBB0_8: # in Loop: Header=BB0_2 Depth=1
xorl %r14d, %r14d
.LBB0_11: # %_ZNSt12_Vector_baseISt4pairIjjESaIS1_EE11_M_allocateEm.exit.i
# in Loop: Header=BB0_2 Depth=1
movl %eax, %eax
orq %r13, %rax
movq %rax, (%r14,%rbp,8)
movq %r14, %rbp
cmpq %r15, 8(%rsp) # 8-byte Folded Reload
je .LBB0_14
# %bb.12: # %.lr.ph.i.i.i.i88.preheader
# in Loop: Header=BB0_2 Depth=1
movq %r14, %rbp
movq 8(%rsp), %rax # 8-byte Reload
.p2align 4, 0x90
.LBB0_13: # %.lr.ph.i.i.i.i88
# Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rax), %rcx
movq %rcx, (%rbp)
addq $8, %rax
addq $8, %rbp
cmpq %r15, %rax
jne .LBB0_13
.LBB0_14: # %_ZNSt6vectorISt4pairIjjESaIS1_EE11_S_relocateEPS1_S4_S4_RS2_.exit.i92
# in Loop: Header=BB0_2 Depth=1
movq 8(%rsp), %rdi # 8-byte Reload
testq %rdi, %rdi
je .LBB0_16
# %bb.15: # in Loop: Header=BB0_2 Depth=1
callq _ZdlPv
.LBB0_16: # %_ZNSt6vectorISt4pairIjjESaIS1_EE17_M_realloc_insertIJS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_.exit
# in Loop: Header=BB0_2 Depth=1
leaq (%r14,%rbx,8), %rbx
movq %r14, 8(%rsp) # 8-byte Spill
movq %rbp, %r15
jmp .LBB0_17
.LBB0_18: # %_ZNSt16allocator_traitsISaISt4pairIjjEEE8allocateERS2_m.exit.i.i41
.Ltmp6:
movl $557056, %edi # imm = 0x88000
callq _Znwm
.Ltmp7:
# %bb.19: # %_ZNSt6vectorISt4pairIjjESaIS1_EE7reserveEm.exit51
.Ltmp9:
movq %rax, 72(%rsp) # 8-byte Spill
movl $40000, %edi # imm = 0x9C40
callq _Znam
.Ltmp10:
# %bb.20:
movq %rax, 96(%rsp)
movb $0, 7(%rsp)
movl $0, 28(%rsp)
xorpd %xmm0, %xmm0
movapd %xmm0, 32(%rsp)
movq $0, 48(%rsp)
xorl %r14d, %r14d
testb %r14b, %r14b
jne .LBB0_28
# %bb.21: # %_ZNSt16allocator_traitsISaISt6threadEE8allocateERS1_m.exit.i.i
movq 40(%rsp), %rbx
.Ltmp12:
movl $96, %edi
callq _Znwm
.Ltmp13:
# %bb.22: # %.noexc59
movq %rax, %r12
testq %rbx, %rbx
je .LBB0_25
# %bb.23: # %.lr.ph.i.i.i.i54.preheader
movq %rbx, %rdx
andq $-8, %rdx
xorl %r13d, %r13d
xorl %edi, %edi
xorl %esi, %esi
callq memset@PLT
movq %r12, %rax
.p2align 4, 0x90
.LBB0_24: # %.lr.ph.i.i.i.i54
# =>This Inner Loop Header: Depth=1
movq $0, (%rax)
movq (%r13), %rcx
movq %rcx, (%rax)
addq $8, %r13
addq $8, %rax
cmpq %rbx, %r13
jne .LBB0_24
.LBB0_25: # %_ZNSt6vectorISt6threadSaIS0_EE11_S_relocateEPS0_S3_S3_RS1_.exit.i
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_27
# %bb.26:
callq _ZdlPv
.LBB0_27: # %_ZNSt12_Vector_baseISt6threadSaIS0_EE13_M_deallocateEPS0_m.exit.i
movq %r12, 32(%rsp)
addq %r12, %rbx
movq %rbx, 40(%rsp)
addq $96, %r12
movq %r12, 48(%rsp)
.LBB0_28: # %_ZNSt6vectorISt6threadSaIS0_EE7reserveEm.exit
movl $0, 84(%rsp)
leaq 96(%rsp), %rbx
leaq 84(%rsp), %r13
leaq 16(%rsp), %rbp
leaq 64(%rsp), %r12
.p2align 4, 0x90
.LBB0_29: # =>This Inner Loop Header: Depth=1
movq $0, 16(%rsp)
.Ltmp15:
movl $56, %edi
callq _Znwm
.Ltmp16:
# %bb.30: # %.noexc62
# in Loop: Header=BB0_29 Depth=1
movl %r14d, %ecx
movl $2863311531, %edx # imm = 0xAAAAAAAB
imulq %rdx, %rcx
shrq $35, %rcx
leal 5802(%rcx), %edx
movq $_ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE+16, (%rax)
movl %edx, 8(%rax)
movl %ecx, 12(%rax)
movq 8(%rsp), %rcx # 8-byte Reload
movq %rcx, 16(%rax)
leaq 7(%rsp), %rcx
movq %rcx, 24(%rax)
leaq 28(%rsp), %rcx
movq %rcx, 32(%rax)
movq %rbx, 40(%rax)
movq %r13, 48(%rax)
movq %rax, 64(%rsp)
.Ltmp18:
movl $_ZNSt6thread24_M_thread_deps_never_runEv, %edx
movq %rbp, %rdi
movq %r12, %rsi
callq _ZNSt6thread15_M_start_threadESt10unique_ptrINS_6_StateESt14default_deleteIS1_EEPFvvE
.Ltmp19:
# %bb.31: # in Loop: Header=BB0_29 Depth=1
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_33
# %bb.32: # %_ZNKSt14default_deleteINSt6thread6_StateEEclEPS1_.exit.i.i
# in Loop: Header=BB0_29 Depth=1
movq (%rdi), %rax
callq *8(%rax)
.LBB0_33: # %_ZNSt6threadC2IZ4mainEUlPSt4pairIjjEiiE_JS3_iiEvEEOT_DpOT0_.exit
# in Loop: Header=BB0_29 Depth=1
movq 40(%rsp), %rsi
cmpq 48(%rsp), %rsi
je .LBB0_43
# %bb.34: # in Loop: Header=BB0_29 Depth=1
movq $0, (%rsi)
movq 16(%rsp), %rax
movq %rax, (%rsi)
movq $0, 16(%rsp)
addq $8, %rsi
movq %rsi, 40(%rsp)
jmp .LBB0_44
.p2align 4, 0x90
.LBB0_43: # in Loop: Header=BB0_29 Depth=1
.Ltmp21:
leaq 32(%rsp), %rdi
movq %rbp, %rdx
callq _ZNSt6vectorISt6threadSaIS0_EE17_M_realloc_insertIJS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_
.Ltmp22:
.LBB0_44: # %_ZNSt6vectorISt6threadSaIS0_EE9push_backEOS0_.exit
# in Loop: Header=BB0_29 Depth=1
cmpq $0, 16(%rsp)
jne .LBB0_79
# %bb.45: # %_ZNSt6threadD2Ev.exit
# in Loop: Header=BB0_29 Depth=1
addl $69632, %r14d # imm = 0x11000
cmpl $835584, %r14d # imm = 0xCC000
jne .LBB0_29
# %bb.46:
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
movb $1, %al
xchgb %al, 7(%rsp)
.p2align 4, 0x90
.LBB0_47: # =>This Inner Loop Header: Depth=1
movl 28(%rsp), %eax
cmpl $12, %eax
jne .LBB0_47
# %bb.48:
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r12
movq 32(%rsp), %r13
movq 40(%rsp), %r14
cmpq %r14, %r13
je .LBB0_50
.p2align 4, 0x90
.LBB0_57: # %.lr.ph
# =>This Inner Loop Header: Depth=1
.Ltmp24:
movq %r13, %rdi
callq _ZNSt6thread4joinEv
.Ltmp25:
# %bb.58: # in Loop: Header=BB0_57 Depth=1
addq $8, %r13
cmpq %r14, %r13
jne .LBB0_57
.LBB0_50: # %._crit_edge
subq %rbx, %r12
cvtsi2sd %r12, %xmm1
divsd .LCPI0_0(%rip), %xmm1
movsd .LCPI0_1(%rip), %xmm0 # xmm0 = mem[0],zero
movsd %xmm1, 88(%rsp) # 8-byte Spill
mulsd %xmm1, %xmm0
.Ltmp27:
movl $_ZSt4cerr, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp28:
# %bb.51: # %_ZNSolsEd.exit
.Ltmp29:
movq %rax, %rbx
movl $.L.str, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp30:
# %bb.52: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .LBB0_67
# %bb.53: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB0_60
# %bb.54:
movzbl 67(%r12), %eax
jmp .LBB0_62
.LBB0_60:
.Ltmp31:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp32:
# %bb.61: # %.noexc98
movq (%r12), %rax
.Ltmp33:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp34:
.LBB0_62: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp35:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp36:
# %bb.63: # %.noexc100
.Ltmp37:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp38:
# %bb.64: # %_ZNSolsEPFRSoS_E.exit
subq 8(%rsp), %r15 # 8-byte Folded Reload
sarq $3, %r15
movq %r15, %xmm1
punpckldq .LCPI0_2(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI0_3(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
divsd 88(%rsp), %xmm0 # 8-byte Folded Reload
divsd .LCPI0_4(%rip), %xmm0
.Ltmp39:
movl $_ZSt4cerr, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp40:
# %bb.65: # %_ZNSolsEd.exit73
.Ltmp41:
movq %rax, %r15
movl $.L.str.1, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp42:
# %bb.66: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit75
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_67
# %bb.69: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i103
cmpb $0, 56(%r12)
je .LBB0_71
# %bb.70:
movzbl 67(%r12), %eax
jmp .LBB0_73
.LBB0_71:
.Ltmp43:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp44:
# %bb.72: # %.noexc108
movq (%r12), %rax
.Ltmp45:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp46:
.LBB0_73: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i105
.Ltmp47:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp48:
# %bb.74: # %.noexc110
.Ltmp49:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp50:
# %bb.75: # %_ZNSolsEPFRSoS_E.exit77
movq 32(%rsp), %rdi
movq 40(%rsp), %rax
cmpq %rax, %rdi
movq 8(%rsp), %rbx # 8-byte Reload
je .LBB0_80
# %bb.76:
movq %rdi, %rcx
.p2align 4, 0x90
.LBB0_78: # %_ZSt8_DestroyISt6threadEvPT_.exit.i.i.i.i
# =>This Inner Loop Header: Depth=1
cmpq $0, (%rcx)
jne .LBB0_79
# %bb.77: # in Loop: Header=BB0_78 Depth=1
addq $8, %rcx
cmpq %rax, %rcx
jne .LBB0_78
.LBB0_80: # %_ZSt8_DestroyIPSt6threadS0_EvT_S2_RSaIT0_E.exit.i
testq %rdi, %rdi
je .LBB0_82
# %bb.81:
callq _ZdlPv
.LBB0_82: # %_ZNSt6vectorISt6threadSaIS0_EED2Ev.exit
movq 72(%rsp), %rdi # 8-byte Reload
callq _ZdlPv
testq %rbx, %rbx
je .LBB0_84
# %bb.83:
movq %rbx, %rdi
callq _ZdlPv
.LBB0_84: # %_ZNSt6vectorISt4pairIjjESaIS1_EED2Ev.exit81
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 160
.Ltmp54:
movl $.L.str.3, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp55:
# %bb.6: # %.noexc94
.LBB0_67: # %.invoke
.Ltmp51:
callq _ZSt16__throw_bad_castv
.Ltmp52:
# %bb.68: # %.cont
.LBB0_39:
.Ltmp14:
jmp .LBB0_86
.LBB0_38:
.Ltmp11:
movq %rax, %r15
jmp .LBB0_88
.LBB0_37:
.Ltmp8:
movq %rax, %r15
xorl %eax, %eax
movq %rax, 72(%rsp) # 8-byte Spill
jmp .LBB0_88
.LBB0_93:
.Ltmp2:
movq %rax, %r15
xorl %eax, %eax
movq %rax, 8(%rsp) # 8-byte Spill
jmp .LBB0_90
.LBB0_35: # %.loopexit
.Ltmp5:
movq %rax, %r15
jmp .LBB0_90
.LBB0_85:
.Ltmp53:
jmp .LBB0_86
.LBB0_55:
.Ltmp23:
cmpq $0, 16(%rsp)
je .LBB0_86
.LBB0_79:
callq _ZSt9terminatev
.LBB0_36: # %.loopexit.split-lp
.Ltmp56:
movq %rax, %r15
jmp .LBB0_90
.LBB0_59:
.Ltmp26:
jmp .LBB0_86
.LBB0_56:
.Ltmp17:
.LBB0_86:
movq %rax, %r15
jmp .LBB0_87
.LBB0_40:
.Ltmp20:
movq %rax, %r15
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_42
# %bb.41: # %_ZNKSt14default_deleteINSt6thread6_StateEEclEPS1_.exit.i9.i
movq (%rdi), %rax
callq *8(%rax)
.LBB0_42: # %_ZNSt10unique_ptrINSt6thread6_StateESt14default_deleteIS1_EED2Ev.exit10.i
movq $0, 64(%rsp)
.LBB0_87:
leaq 32(%rsp), %rdi
callq _ZNSt6vectorISt6threadSaIS0_EED2Ev
.LBB0_88:
movq 72(%rsp), %rdi # 8-byte Reload
testq %rdi, %rdi
je .LBB0_90
# %bb.89:
callq _ZdlPv
.LBB0_90: # %_ZNSt6vectorISt4pairIjjESaIS1_EED2Ev.exit83
movq 8(%rsp), %rdi # 8-byte Reload
testq %rdi, %rdi
je .LBB0_92
# %bb.91:
callq _ZdlPv
.LBB0_92: # %_ZNSt6vectorISt4pairIjjESaIS1_EED2Ev.exit85
movq %r15, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp15-.Ltmp13 # Call between .Ltmp13 and .Ltmp15
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin0 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp19-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp21-.Ltmp19 # Call between .Ltmp19 and .Ltmp21
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp22-.Ltmp21 # Call between .Ltmp21 and .Ltmp22
.uleb128 .Ltmp23-.Lfunc_begin0 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp25-.Ltmp24 # Call between .Ltmp24 and .Ltmp25
.uleb128 .Ltmp26-.Lfunc_begin0 # jumps to .Ltmp26
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp50-.Ltmp27 # Call between .Ltmp27 and .Ltmp50
.uleb128 .Ltmp53-.Lfunc_begin0 # jumps to .Ltmp53
.byte 0 # On action: cleanup
.uleb128 .Ltmp54-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp55-.Ltmp54 # Call between .Ltmp54 and .Ltmp55
.uleb128 .Ltmp56-.Lfunc_begin0 # jumps to .Ltmp56
.byte 0 # On action: cleanup
.uleb128 .Ltmp51-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp52-.Ltmp51 # Call between .Ltmp51 and .Ltmp52
.uleb128 .Ltmp53-.Lfunc_begin0 # jumps to .Ltmp53
.byte 0 # On action: cleanup
.uleb128 .Ltmp52-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Lfunc_end0-.Ltmp52 # Call between .Ltmp52 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._ZNSt6vectorISt6threadSaIS0_EED2Ev,"axG",@progbits,_ZNSt6vectorISt6threadSaIS0_EED2Ev,comdat
.weak _ZNSt6vectorISt6threadSaIS0_EED2Ev # -- Begin function _ZNSt6vectorISt6threadSaIS0_EED2Ev
.p2align 4, 0x90
.type _ZNSt6vectorISt6threadSaIS0_EED2Ev,@function
_ZNSt6vectorISt6threadSaIS0_EED2Ev: # @_ZNSt6vectorISt6threadSaIS0_EED2Ev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rdi, %rax
movq (%rdi), %rdi
movq 8(%rax), %rax
cmpq %rax, %rdi
je .LBB1_5
# %bb.1:
movq %rdi, %rcx
.p2align 4, 0x90
.LBB1_3: # %_ZSt8_DestroyISt6threadEvPT_.exit.i.i.i
# =>This Inner Loop Header: Depth=1
cmpq $0, (%rcx)
jne .LBB1_4
# %bb.2: # in Loop: Header=BB1_3 Depth=1
addq $8, %rcx
cmpq %rax, %rcx
jne .LBB1_3
.LBB1_5: # %_ZSt8_DestroyIPSt6threadS0_EvT_S2_RSaIT0_E.exit
testq %rdi, %rdi
je .LBB1_6
# %bb.7:
popq %rax
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.LBB1_6: # %_ZNSt12_Vector_baseISt6threadSaIS0_EED2Ev.exit
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 16
callq _ZSt9terminatev
.Lfunc_end1:
.size _ZNSt6vectorISt6threadSaIS0_EED2Ev, .Lfunc_end1-_ZNSt6vectorISt6threadSaIS0_EED2Ev
.cfi_endproc
# -- End function
.section .text._ZNSt6vectorISt6threadSaIS0_EE17_M_realloc_insertIJS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_,"axG",@progbits,_ZNSt6vectorISt6threadSaIS0_EE17_M_realloc_insertIJS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_,comdat
.weak _ZNSt6vectorISt6threadSaIS0_EE17_M_realloc_insertIJS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_ # -- Begin function _ZNSt6vectorISt6threadSaIS0_EE17_M_realloc_insertIJS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_
.p2align 4, 0x90
.type _ZNSt6vectorISt6threadSaIS0_EE17_M_realloc_insertIJS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_,@function
_ZNSt6vectorISt6threadSaIS0_EE17_M_realloc_insertIJS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_: # @_ZNSt6vectorISt6threadSaIS0_EE17_M_realloc_insertIJS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq (%rdi), %r14
movq 8(%rdi), %r13
movq %r13, %rax
subq %r14, %rax
movabsq $9223372036854775800, %rcx # imm = 0x7FFFFFFFFFFFFFF8
cmpq %rcx, %rax
je .LBB2_12
# %bb.1: # %_ZNKSt6vectorISt6threadSaIS0_EE12_M_check_lenEmPKc.exit
movq %rsi, %r15
movq %rdi, (%rsp) # 8-byte Spill
sarq $3, %rax
cmpq $1, %rax
movq %rax, %rcx
adcq $0, %rcx
leaq (%rcx,%rax), %rbp
movabsq $1152921504606846975, %rsi # imm = 0xFFFFFFFFFFFFFFF
cmpq %rsi, %rbp
cmovaeq %rsi, %rbp
addq %rax, %rcx
cmovbq %rsi, %rbp
movq %r15, %r12
subq %r14, %r12
sarq $3, %r12
testq %rbp, %rbp
je .LBB2_2
# %bb.3:
leaq (,%rbp,8), %rdi
movq %rdx, %rbx
callq _Znwm
movq %rbx, %rdx
movq %rax, %rbx
jmp .LBB2_4
.LBB2_2:
xorl %ebx, %ebx
.LBB2_4: # %_ZNSt12_Vector_baseISt6threadSaIS0_EE11_M_allocateEm.exit
movq $0, (%rbx,%r12,8)
movq (%rdx), %rax
movq %rax, (%rbx,%r12,8)
movq $0, (%rdx)
movq %rbx, %r12
cmpq %r15, %r14
je .LBB2_7
# %bb.5: # %.lr.ph.i.i.i.preheader
movq %rbx, %r12
movq %r14, %rax
.p2align 4, 0x90
.LBB2_6: # %.lr.ph.i.i.i
# =>This Inner Loop Header: Depth=1
movq $0, (%r12)
movq (%rax), %rcx
movq %rcx, (%r12)
movq $0, (%rax)
addq $8, %rax
addq $8, %r12
cmpq %r15, %rax
jne .LBB2_6
.LBB2_7: # %_ZNSt6vectorISt6threadSaIS0_EE11_S_relocateEPS0_S3_S3_RS1_.exit
addq $8, %r12
cmpq %r15, %r13
je .LBB2_9
.p2align 4, 0x90
.LBB2_8: # %.lr.ph.i.i.i17
# =>This Inner Loop Header: Depth=1
movq $0, (%r12)
movq (%r15), %rax
movq %rax, (%r12)
movq $0, (%r15)
addq $8, %r15
addq $8, %r12
cmpq %r13, %r15
jne .LBB2_8
.LBB2_9: # %_ZNSt6vectorISt6threadSaIS0_EE11_S_relocateEPS0_S3_S3_RS1_.exit22
testq %r14, %r14
je .LBB2_11
# %bb.10:
movq %r14, %rdi
callq _ZdlPv
.LBB2_11: # %_ZNSt12_Vector_baseISt6threadSaIS0_EE13_M_deallocateEPS0_m.exit
movq (%rsp), %rcx # 8-byte Reload
movq %rbx, (%rcx)
movq %r12, 8(%rcx)
leaq (%rbx,%rbp,8), %rax
movq %rax, 16(%rcx)
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_12:
.cfi_def_cfa_offset 64
movl $.L.str.3, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end2:
.size _ZNSt6vectorISt6threadSaIS0_EE17_M_realloc_insertIJS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_, .Lfunc_end2-_ZNSt6vectorISt6threadSaIS0_EE17_M_realloc_insertIJS0_EEEvN9__gnu_cxx17__normal_iteratorIPS0_S2_EEDpOT_
.cfi_endproc
# -- End function
.section .text._ZNSt6thread24_M_thread_deps_never_runEv,"axG",@progbits,_ZNSt6thread24_M_thread_deps_never_runEv,comdat
.weak _ZNSt6thread24_M_thread_deps_never_runEv # -- Begin function _ZNSt6thread24_M_thread_deps_never_runEv
.p2align 4, 0x90
.type _ZNSt6thread24_M_thread_deps_never_runEv,@function
_ZNSt6thread24_M_thread_deps_never_runEv: # @_ZNSt6thread24_M_thread_deps_never_runEv
.cfi_startproc
# %bb.0:
retq
.Lfunc_end3:
.size _ZNSt6thread24_M_thread_deps_never_runEv, .Lfunc_end3-_ZNSt6thread24_M_thread_deps_never_runEv
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEED0Ev
.type _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEED0Ev,@function
_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEED0Ev: # @_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEED0Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq _ZNSt6thread6_StateD2Ev
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.Lfunc_end4:
.size _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEED0Ev, .Lfunc_end4-_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEED0Ev
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEE6_M_runEv
.LCPI5_0:
.quad 0x3f847ae147ae147b # double 0.01
.text
.p2align 4, 0x90
.type _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEE6_M_runEv,@function
_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEE6_M_runEv: # @_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEE6_M_runEv
.cfi_startproc
# %bb.0:
movq 16(%rdi), %rax
movslq 12(%rdi), %rcx
movslq 8(%rdi), %rdx
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
movq 24(%rdi), %rsi
movzbl (%rsi), %esi
testb $1, %sil
je .LBB5_1
# %bb.2: # %.preheader.i.i.i.i.i
cmpl %edx, %ecx
jge .LBB5_7
# %bb.3: # %.lr.ph.i.i.i.i.i
movq 40(%rdi), %rsi
movq (%rsi), %rsi
movl $3518437209, %r8d # imm = 0xD1B71759
movsd .LCPI5_0(%rip), %xmm0 # xmm0 = mem[0],zero
jmp .LBB5_4
.p2align 4, 0x90
.LBB5_6: # in Loop: Header=BB5_4 Depth=1
incq %rcx
cmpq %rcx, %rdx
je .LBB5_7
.LBB5_4: # =>This Inner Loop Header: Depth=1
movl (%rax,%rcx,8), %r9d
movq %r9, %r10
imulq %r8, %r10
shrq $45, %r10
imull $10000, %r10d, %r10d # imm = 0x2710
subl %r10d, %r9d
movss (%rsi,%r9,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jbe .LBB5_6
# %bb.5: # in Loop: Header=BB5_4 Depth=1
movl $1, 4(%rax,%rcx,8)
jmp .LBB5_6
.LBB5_7: # %_ZNSt6thread8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S4_iiEEEclEv.exit
mfence
movq 32(%rdi), %rax
lock incl (%rax)
retq
.Lfunc_end5:
.size _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEE6_M_runEv, .Lfunc_end5-_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEE6_M_runEv
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " ms"
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Mops"
.size .L.str.1, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "vector::_M_realloc_insert"
.size .L.str.3, 26
.type _ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE,@object # @_ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE:
.quad 0
.quad _ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE
.quad _ZNSt6thread6_StateD2Ev
.quad _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEED0Ev
.quad _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEE6_M_runEv
.size _ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE, 40
.type _ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE,@object # @_ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE
_ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE:
.asciz "NSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE"
.size _ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE, 84
.type _ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE,@object # @_ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE
.p2align 3, 0x0
_ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE
.quad _ZTINSt6thread6_StateE
.size _ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE, 24
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _ZNSt6thread24_M_thread_deps_never_runEv
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZTVN10__cxxabiv120__si_class_type_infoE
.addrsig_sym _ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE
.addrsig_sym _ZTINSt6thread6_StateE
.addrsig_sym _ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJZ4mainEUlPSt4pairIjjEiiE_S5_iiEEEEEE
.addrsig_sym __hip_cuid_ |
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