system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuArraysCopyToBatch_kernel(const float2 *imageIn, const int inNX, const int inNY, float2 *imageOut, const int outNX, const int outNY, const int nImagesX, const int nImagesY, const int strideX, const int strideY)
{
int idxImage = blockIdx.z;
int outx = threadIdx.x + blockDim.x*blockIdx.x;
int outy = threadIdx.y + blockDim.y*blockIdx.y;
if(idxImage >=nImagesX*nImagesY|| outx >= outNX || outy >= outNY) return;
int idxOut = idxImage*outNX*outNY + outx*outNY + outy;
int idxImageX = idxImage/nImagesY;
int idxImageY = idxImage%nImagesY;
int idxIn = (idxImageX*strideX+outx)*inNY + idxImageY*strideY+outy;
imageOut[idxOut] = imageIn[idxIn];
} | .text
.file "cuArraysCopyToBatch_kernel.hip"
.globl _Z41__device_stub__cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii # -- Begin function _Z41__device_stub__cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.p2align 4, 0x90
.type _Z41__device_stub__cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii,@function
_Z41__device_stub__cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii: # @_Z41__device_stub__cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z41__device_stub__cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii, .Lfunc_end0-_Z41__device_stub__cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii,@object # @_Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.section .rodata,"a",@progbits
.globl _Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.p2align 3, 0x0
_Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii:
.quad _Z41__device_stub__cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.size _Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii"
.size .L__unnamed_1, 69
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0050*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e680000002700 */
/*0060*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000ea80000002600 */
/*0070*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000ea20000002200 */
/*0080*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fe200078e0202 */
/*0090*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x002fc8000bf06270 */
/*00a0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe20000706670 */
/*00b0*/ IMAD R2, R4, c[0x0][0x4], R5 ; /* 0x0000010004027a24 */
/* 0x004fca00078e0205 */
/*00c0*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x17c], P0 ; /* 0x00005f0002007a0c */
/* 0x000fda0000706670 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IABS R7, c[0x0][0x184] ; /* 0x0000610000077a13 */
/* 0x000fe20000000000 */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0100*/ I2F.RP R6, R7 ; /* 0x0000000700067306 */
/* 0x000e300000209400 */
/*0110*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0120*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0130*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0140*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0150*/ IMAD.MOV R8, RZ, RZ, -R5 ; /* 0x000000ffff087224 */
/* 0x002fc800078e0a05 */
/*0160*/ IMAD R9, R8, R7, RZ ; /* 0x0000000708097224 */
/* 0x000fe200078e02ff */
/*0170*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fc80000000000 */
/*0180*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fe200078e0004 */
/*0190*/ LOP3.LUT R4, R0, c[0x0][0x184], RZ, 0x3c, !PT ; /* 0x0000610000047a12 */
/* 0x000fc800078e3cff */
/*01a0*/ ISETP.GE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f26270 */
/*01b0*/ IMAD.HI.U32 R5, R5, R8, RZ ; /* 0x0000000805057227 */
/* 0x000fc800078e00ff */
/*01c0*/ IMAD.MOV R6, RZ, RZ, -R5 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a05 */
/*01d0*/ IMAD R6, R7, R6, R8 ; /* 0x0000000607067224 */
/* 0x000fca00078e0208 */
/*01e0*/ ISETP.GT.U32.AND P2, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fda0003f44070 */
/*01f0*/ @!P2 IADD3 R6, R6, -R7.reuse, RZ ; /* 0x800000070606a210 */
/* 0x080fe40007ffe0ff */
/*0200*/ @!P2 IADD3 R5, R5, 0x1, RZ ; /* 0x000000010505a810 */
/* 0x000fe40007ffe0ff */
/*0210*/ ISETP.GE.U32.AND P0, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x000fe40003f06070 */
/*0220*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x184], PT ; /* 0x00006100ff007a0c */
/* 0x000fe40003f45270 */
/*0230*/ MOV R6, 0x8 ; /* 0x0000000800067802 */
/* 0x000fd20000000f00 */
/*0240*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fca0007ffe0ff */
/*0250*/ @!P1 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff059224 */
/* 0x000fe200078e0a05 */
/*0260*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0x184], RZ, 0x33, !PT ; /* 0x00006100ff05aa12 */
/* 0x000fc800078e33ff */
/*0270*/ IADD3 R7, -R5.reuse, RZ, RZ ; /* 0x000000ff05077210 */
/* 0x040fe20007ffe1ff */
/*0280*/ IMAD R5, R5, c[0x0][0x188], R3 ; /* 0x0000620005057a24 */
/* 0x000fc800078e0203 */
/*0290*/ IMAD R7, R7, c[0x0][0x184], R0 ; /* 0x0000610007077a24 */
/* 0x000fc800078e0200 */
/*02a0*/ IMAD R4, R7, c[0x0][0x18c], R2 ; /* 0x0000630007047a24 */
/* 0x000fc800078e0202 */
/*02b0*/ IMAD R4, R5, c[0x0][0x16c], R4 ; /* 0x00005b0005047a24 */
/* 0x000fc800078e0204 */
/*02c0*/ IMAD.WIDE R4, R4, R6, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0206 */
/*02d0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*02e0*/ IMAD R3, R0, c[0x0][0x178], R3 ; /* 0x00005e0000037a24 */
/* 0x000fc800078e0203 */
/*02f0*/ IMAD R3, R3, c[0x0][0x17c], R2 ; /* 0x00005f0003037a24 */
/* 0x000fc800078e0202 */
/*0300*/ IMAD.WIDE R2, R3, R6, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0206 */
/*0310*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x004fe2000c101b04 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ BRA 0x330; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.globl _Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.p2align 8
.type _Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii,@function
_Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b128 s[4:7], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s13, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_mul_i32 s2, s7, s6
s_cmp_lt_i32 s15, s2
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s3, s3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_ashr_i32 s6, s7, 31
s_ashr_i32 s9, s15, 31
s_add_i32 s2, s7, s6
s_add_i32 s10, s15, s9
s_xor_b32 s8, s2, s6
s_xor_b32 s10, s10, s9
v_cvt_f32_u32_e32 v2, s8
s_sub_i32 s3, 0, s8
s_xor_b32 s6, s9, s6
s_load_b32 s13, s[0:1], 0xc
v_mad_u64_u32 v[4:5], null, s15, s4, v[0:1]
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v2, v2
v_readfirstlane_b32 s2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s3, s2
s_mul_hi_u32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s11, s2, s3
s_load_b64 s[2:3], s[0:1], 0x28
s_mul_hi_u32 s11, s10, s11
s_mul_i32 s12, s11, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s9, s10, s12
s_add_i32 s10, s11, 1
s_sub_i32 s12, s9, s8
s_cmp_ge_u32 s9, s8
s_cselect_b32 s10, s10, s11
s_cselect_b32 s9, s12, s9
s_add_i32 s11, s10, 1
s_cmp_ge_u32 s9, s8
s_cselect_b32 s8, s11, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s8, s8, s6
s_sub_i32 s6, s8, s6
s_load_b64 s[8:9], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s6, s2, v[0:1]
s_mul_i32 s6, s6, s7
s_load_b64 s[0:1], s[0:1], 0x0
s_sub_i32 s2, s15, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s2, s2, s3
v_mul_lo_u32 v2, v2, s13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, s2, v1, v2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, v4, s5, v[1:2]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[5:6]
v_add_co_u32 v0, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii, .Lfunc_end0-_Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012fd7d_00000000-6_cuArraysCopyToBatch_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z64__device_stub__Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiiiPK6float2iiPS_iiiiii
.type _Z64__device_stub__Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiiiPK6float2iiPS_iiiiii, @function
_Z64__device_stub__Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiiiPK6float2iiPS_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 216
pushq 40(%rsp)
.cfi_def_cfa_offset 224
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z64__device_stub__Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiiiPK6float2iiPS_iiiiii, .-_Z64__device_stub__Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiiiPK6float2iiPS_iiiiii
.globl _Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiii
.type _Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiii, @function
_Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z64__device_stub__Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiiiPK6float2iiPS_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiii, .-_Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuArraysCopyToBatch_kernel.hip"
.globl _Z41__device_stub__cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii # -- Begin function _Z41__device_stub__cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.p2align 4, 0x90
.type _Z41__device_stub__cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii,@function
_Z41__device_stub__cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii: # @_Z41__device_stub__cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z41__device_stub__cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii, .Lfunc_end0-_Z41__device_stub__cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii,@object # @_Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.section .rodata,"a",@progbits
.globl _Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.p2align 3, 0x0
_Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii:
.quad _Z41__device_stub__cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.size _Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii"
.size .L__unnamed_1, 69
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<cuda.h>
__global__ void prime_generator(int *input,int *prime_list,int *total_input,int *seed)
{
printf("-------XXXXXX>>> %d\n",seed[0]);
int i= blockIdx.x * blockDim.x + threadIdx.x;
int primeno= prime_list[i];
int total=seed[0]*seed[0];
for(int k=seed[0];k<total;k++)
{
if(k%primeno==0)
{
input[k]=1;
}
}
}
int main()
{
int total_input=100000000;
int *input;
int n= 10 ;// seed prime list.
int calculate_upto=pow(n,2);
int *primelist;
input=(int *)malloc(total_input*sizeof(int));
primelist=(int *)malloc(total_input*sizeof(int));
memset(input,-1,total_input*sizeof(int));
for(int j=0;j<calculate_upto;j++)
{
input[j]=0;
}
for (int p=2; p*p<=n; p++)
{
if (input[p] == 0)
{
for (int i=p*2; i<=n; i += p)
input[i] = 1;
}
}
int i=0;
for (int p=2; p<=n; p++){
if (input[p]==0)
{
primelist[i]=p;
i++;
}
}
int *d_input;
int *d_prime_list;
int *h_pl;
int *d_total_input;
int *d_seed;
h_pl=(int *)malloc(total_input*sizeof(int));
cudaMalloc(&d_input,total_input*sizeof(int));
cudaMalloc(&d_prime_list,total_input*sizeof(int));
cudaMalloc(&d_total_input,sizeof(int));
cudaMalloc(&d_seed,sizeof(int));
cudaMemcpy(d_total_input,&total_input,sizeof(int),cudaMemcpyHostToDevice);
//cudaMemcpy(d_input,input,total_input*sizeof(int),cudaMemcpyHostToDevice);
while(n<=total_input){
printf("inside loop\n");
if(cudaMemcpy(d_input,input,total_input*sizeof(int),cudaMemcpyHostToDevice)!=cudaSuccess)
{
printf("not able to copy memory\n");
}
if(cudaMemcpy(d_prime_list,primelist,total_input*sizeof(int),cudaMemcpyHostToDevice) != cudaSuccess)
{
printf("not able to copy memory 2\n");
}
if(cudaMemcpy(d_seed,&n,sizeof(int),cudaMemcpyHostToDevice) != cudaSuccess)
{
printf(" not able to copy memory\n");
}
prime_generator<<<5,500>>>(d_input,d_prime_list,d_total_input,d_seed);
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess)
printf("Error: %s\n", cudaGetErrorString(err));
/*
if(cudaMemcpy(h_pl,d_prime_list,total_input*sizeof(int),cudaMemcpyDeviceToHost)!=cudaSuccess)
{
printf("not able to copy memory!!\n");
}
*/
if(cudaMemcpy(input,d_input,total_input*sizeof(int),cudaMemcpyDeviceToHost)!=cudaSuccess)
{
printf(" hello not able to copy memory::\n");
}
printf("------------>> %d\n",i);
for(int p=n;p<total_input;p++)
{
// printf("%d ----> %d\n",p,input[p]);
if(input[p]==0){
primelist[i]=p;
i++;
}
}
for(int p=0;p<i;p++)
{
printf("%d\n",primelist[p]);
}
n=n*n;
printf("################ %d\n",n);
if(pow(n,2)>=total_input){
for(int m=n;m<total_input;m++) input[m]=0;
}
else
{
for(int m=n;m<pow(n,2);m++) input[m]=0;
}
}
/*for(int p=0;p<i;p++)
{
printf("%d\n",primelist[p]);
}*/
return 0;
} | code for sm_80
Function : _Z15prime_generatorPiS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff107624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff117624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fc80007ffe0ff */
/*0050*/ LDG.E R0, [R16.64] ; /* 0x0000002410007981 */
/* 0x000ea2000c1e1900 */
/*0060*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0080*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fc600078e00ff */
/*00a0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e220000000a00 */
/*00b0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00c0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0043ec0000100800 */
/*00d0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x001fe20000000000 */
/*00e0*/ MOV R11, 0x150 ; /* 0x00000150000b7802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R20, 0xd0 ; /* 0x000000d000147802 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*0120*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0130*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0140*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0150*/ LDG.E R3, [R16.64] ; /* 0x0000002410037981 */
/* 0x000ea8000c1e1900 */
/*0160*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0170*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0180*/ IMAD R0, R3, R3, RZ ; /* 0x0000000303007224 */
/* 0x004fca00078e02ff */
/*0190*/ ISETP.GT.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f04270 */
/*01a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01b0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x003fe400078e00ff */
/*01c0*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x000fc800078e0205 */
/*01d0*/ IMAD.WIDE R4, R4, R8, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0208 */
/*01e0*/ LDG.E R2, [R4.64] ; /* 0x0000002404027981 */
/* 0x000162000c1e1900 */
/*01f0*/ IMAD.IADD R10, R0, 0x1, -R3 ; /* 0x00000001000a7824 */
/* 0x000fca00078e0a03 */
/*0200*/ IADD3 R6, R10.reuse, -0x1, RZ ; /* 0xffffffff0a067810 */
/* 0x040fe40007ffe0ff */
/*0210*/ LOP3.LUT P1, R10, R10, 0x3, RZ, 0xc0, !PT ; /* 0x000000030a0a7812 */
/* 0x000fe4000782c0ff */
/*0220*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fd60003f06070 */
/*0230*/ @!P1 BRA 0x4b0 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*0240*/ IABS R4, R2.reuse ; /* 0x0000000200047213 */
/* 0x0a1fe20000000000 */
/*0250*/ BSSY B0, 0x4b0 ; /* 0x0000025000007945 */
/* 0x000fe20003800000 */
/*0260*/ IABS R12, R2 ; /* 0x00000002000c7213 */
/* 0x000fe20000000000 */
/*0270*/ IMAD.WIDE R8, R3, R8, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fe200078e0208 */
/*0280*/ I2F.RP R5, R4 ; /* 0x0000000400057306 */
/* 0x000e220000209400 */
/*0290*/ IABS R14, R2 ; /* 0x00000002000e7213 */
/* 0x000fe40000000000 */
/*02a0*/ IMAD.MOV R13, RZ, RZ, -R12 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0a0c */
/*02b0*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f25270 */
/*02c0*/ IMAD.MOV.U32 R12, RZ, RZ, R14 ; /* 0x000000ffff0c7224 */
/* 0x000fc400078e000e */
/*02d0*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*02e0*/ IADD3 R6, R5, 0xffffffe, RZ ; /* 0x0ffffffe05067810 */
/* 0x001fcc0007ffe0ff */
/*02f0*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0300*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0310*/ IMAD.MOV R11, RZ, RZ, -R7 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a07 */
/*0320*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0330*/ IMAD.HI.U32 R5, R7, R11, R6 ; /* 0x0000000b07057227 */
/* 0x000fc800078e0006 */
/*0340*/ IMAD.MOV.U32 R11, RZ, RZ, R13 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e000d */
/*0350*/ IABS R7, R3 ; /* 0x0000000300077213 */
/* 0x001fe40000000000 */
/*0360*/ ISETP.GE.AND P3, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f66270 */
/*0370*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0380*/ IMAD.HI.U32 R6, R5, R7, RZ ; /* 0x0000000705067227 */
/* 0x000fe200078e00ff */
/*0390*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fc60007ffe0ff */
/*03a0*/ IMAD R7, R6, R11, R7 ; /* 0x0000000b06077224 */
/* 0x000fca00078e0207 */
/*03b0*/ ISETP.GT.U32.AND P2, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fda0003f44070 */
/*03c0*/ @!P2 IMAD.IADD R7, R7, 0x1, -R12 ; /* 0x000000010707a824 */
/* 0x000fca00078e0a0c */
/*03d0*/ ISETP.GT.U32.AND P2, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fda0003f44070 */
/*03e0*/ @!P2 IMAD.IADD R7, R7, 0x1, -R12 ; /* 0x000000010707a824 */
/* 0x000fc800078e0a0c */
/*03f0*/ @!P3 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff07b224 */
/* 0x000fe200078e0a07 */
/*0400*/ @!P1 LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff079212 */
/* 0x000fe400078e33ff */
/*0410*/ ISETP.NE.AND P3, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f65270 */
/*0420*/ ISETP.NE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f45270 */
/*0430*/ @!P2 MOV R13, 0x1 ; /* 0x00000001000da802 */
/* 0x000fe20000000f00 */
/*0440*/ @!P2 IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff06a224 */
/* 0x000fe400078e0008 */
/*0450*/ @!P2 IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff07a224 */
/* 0x000fca00078e0009 */
/*0460*/ @!P2 STG.E [R6.64], R13 ; /* 0x0000000d0600a986 */
/* 0x0001e2000c101924 */
/*0470*/ IADD3 R8, P2, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fca0007f5e0ff */
/*0480*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0609 */
/*0490*/ @P3 BRA 0x350 ; /* 0xfffffeb000003947 */
/* 0x000fea000383ffff */
/*04a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x001fea0003800000 */
/*04c0*/ IABS R4, R2 ; /* 0x0000000200047213 */
/* 0x020fe20000000000 */
/*04d0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fc600078e00ff */
/*04e0*/ I2F.RP R5, R4 ; /* 0x0000000400057306 */
/* 0x000e220000209400 */
/*04f0*/ IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fce00078e0206 */
/*0500*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*0510*/ IADD3 R8, R5, 0xffffffe, RZ ; /* 0x0ffffffe05087810 */
/* 0x001fcc0007ffe0ff */
/*0520*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*0530*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe400078e00ff */
/*0540*/ IMAD.MOV R11, RZ, RZ, -R9 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a09 */
/*0550*/ IMAD R11, R11, R4, RZ ; /* 0x000000040b0b7224 */
/* 0x000fc800078e02ff */
/*0560*/ IMAD.HI.U32 R5, R9, R11, R8 ; /* 0x0000000b09057227 */
/* 0x000fc800078e0008 */
/*0570*/ IABS R10, R2.reuse ; /* 0x00000002000a7213 */
/* 0x080fe40000000000 */
/*0580*/ IABS R8, R3 ; /* 0x0000000300087213 */
/* 0x001fe40000000000 */
/*0590*/ I2F.RP R13, R10 ; /* 0x0000000a000d7306 */
/* 0x000e220000209400 */
/*05a0*/ IABS R11, R2 ; /* 0x00000002000b7213 */
/* 0x000fe40000000000 */
/*05b0*/ IMAD.HI.U32 R5, R5, R8, RZ ; /* 0x0000000805057227 */
/* 0x000fe200078e00ff */
/*05c0*/ IADD3 R18, R3.reuse, 0x2, RZ ; /* 0x0000000203127810 */
/* 0x040fe40007ffe0ff */
/*05d0*/ IADD3 R19, R3, 0x3, RZ ; /* 0x0000000303137810 */
/* 0x000fe20007ffe0ff */
/*05e0*/ IMAD.MOV R12, RZ, RZ, -R11 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0a0b */
/*05f0*/ IABS R15, R18 ; /* 0x00000012000f7213 */
/* 0x000fc40000000000 */
/*0600*/ IABS R16, R19 ; /* 0x0000001300107213 */
/* 0x000fe20000000000 */
/*0610*/ IMAD R11, R5, R12, R8 ; /* 0x0000000c050b7224 */
/* 0x000fe400078e0208 */
/*0620*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*0630*/ MUFU.RCP R13, R13 ; /* 0x0000000d000d7308 */
/* 0x001e240000001000 */
/*0640*/ ISETP.GT.U32.AND P0, PT, R4, R11, PT ; /* 0x0000000b0400720c */
/* 0x000fda0003f04070 */
/*0650*/ @!P0 IMAD.IADD R11, R11, 0x1, -R10.reuse ; /* 0x000000010b0b8824 */
/* 0x100fe200078e0a0a */
/*0660*/ IADD3 R9, R13, 0xffffffe, RZ ; /* 0x0ffffffe0d097810 */
/* 0x001fe40007ffe0ff */
/*0670*/ IADD3 R13, R3, 0x1, RZ ; /* 0x00000001030d7810 */
/* 0x000fe40007ffe0ff */
/*0680*/ ISETP.GT.U32.AND P6, PT, R4, R11, PT ; /* 0x0000000b0400720c */
/* 0x000fe20003fc4070 */
/*0690*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000a */
/*06a0*/ F2I.FTZ.U32.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e22000021f000 */
/*06b0*/ IABS R14, R13 ; /* 0x0000000d000e7213 */
/* 0x000fd40000000000 */
/*06c0*/ @!P6 IMAD.IADD R11, R11, 0x1, -R10 ; /* 0x000000010b0be824 */
/* 0x000fe200078e0a0a */
/*06d0*/ ISETP.GE.AND P6, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fe20003fc6270 */
/*06e0*/ IMAD.MOV R5, RZ, RZ, -R9 ; /* 0x000000ffff057224 */
/* 0x001fc800078e0a09 */
/*06f0*/ IMAD R5, R5, R10, RZ ; /* 0x0000000a05057224 */
/* 0x000fc800078e02ff */
/*0700*/ IMAD.HI.U32 R5, R9, R5, R8 ; /* 0x0000000509057227 */
/* 0x000fc800078e0008 */
/*0710*/ IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000e */
/*0720*/ MOV R14, R15 ; /* 0x0000000f000e7202 */
/* 0x000fe20000000f00 */
/*0730*/ IMAD.HI.U32 R17, R5, R16, RZ ; /* 0x0000001005117227 */
/* 0x000fc800078e00ff */
/*0740*/ IMAD.HI.U32 R15, R5, R14, RZ ; /* 0x0000000e050f7227 */
/* 0x000fc800078e00ff */
/*0750*/ IMAD.HI.U32 R9, R5, R8, RZ ; /* 0x0000000805097227 */
/* 0x000fc800078e00ff */
/*0760*/ IMAD R15, R15, R12.reuse, R14 ; /* 0x0000000c0f0f7224 */
/* 0x080fe400078e020e */
/*0770*/ IMAD R17, R17, R12.reuse, R16 ; /* 0x0000000c11117224 */
/* 0x080fe400078e0210 */
/*0780*/ IMAD R9, R9, R12, R8 ; /* 0x0000000c09097224 */
/* 0x000fe200078e0208 */
/*0790*/ ISETP.GT.U32.AND P1, PT, R4.reuse, R15, PT ; /* 0x0000000f0400720c */
/* 0x040fe40003f24070 */
/*07a0*/ ISETP.GT.U32.AND P2, PT, R4.reuse, R17, PT ; /* 0x000000110400720c */
/* 0x040fe40003f44070 */
/*07b0*/ ISETP.GT.U32.AND P0, PT, R4, R9, PT ; /* 0x000000090400720c */
/* 0x000fe40003f04070 */
/*07c0*/ LOP3.LUT R8, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff087212 */
/* 0x000fce00078e33ff */
/*07d0*/ @!P1 IMAD.IADD R15, R15, 0x1, -R10.reuse ; /* 0x000000010f0f9824 */
/* 0x100fe200078e0a0a */
/*07e0*/ ISETP.GE.AND P1, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe20003f26270 */
/*07f0*/ @!P2 IMAD.IADD R17, R17, 0x1, -R10.reuse ; /* 0x000000011111a824 */
/* 0x100fe200078e0a0a */
/*0800*/ ISETP.GE.AND P2, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f46270 */
/*0810*/ @!P0 IMAD.IADD R9, R9, 0x1, -R10 ; /* 0x0000000109098824 */
/* 0x000fe200078e0a0a */
/*0820*/ ISETP.GT.U32.AND P4, PT, R4.reuse, R15, PT ; /* 0x0000000f0400720c */
/* 0x040fe40003f84070 */
/*0830*/ ISETP.GT.U32.AND P3, PT, R4.reuse, R17, PT ; /* 0x000000110400720c */
/* 0x040fe40003f64070 */
/*0840*/ ISETP.GT.U32.AND P5, PT, R4, R9, PT ; /* 0x000000090400720c */
/* 0x000fe40003fa4070 */
/*0850*/ ISETP.GE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc40003f06270 */
/*0860*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fca0007ffe0ff */
/*0870*/ @!P4 IMAD.IADD R15, R15, 0x1, -R10.reuse ; /* 0x000000010f0fc824 */
/* 0x100fe400078e0a0a */
/*0880*/ @!P3 IMAD.IADD R17, R17, 0x1, -R10.reuse ; /* 0x000000011111b824 */
/* 0x100fe200078e0a0a */
/*0890*/ ISETP.NE.AND P3, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f65270 */
/*08a0*/ @!P5 IMAD.IADD R9, R9, 0x1, -R10 ; /* 0x000000010909d824 */
/* 0x000fe400078e0a0a */
/*08b0*/ @!P1 IMAD.MOV R15, RZ, RZ, -R15 ; /* 0x000000ffff0f9224 */
/* 0x000fe400078e0a0f */
/*08c0*/ @!P6 IMAD.MOV R17, RZ, RZ, -R17 ; /* 0x000000ffff11e224 */
/* 0x000fe200078e0a11 */
/*08d0*/ @!P2 IADD3 R9, -R9, RZ, RZ ; /* 0x000000ff0909a210 */
/* 0x000fe20007ffe1ff */
/*08e0*/ @!P0 IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0b8224 */
/* 0x000fe200078e0a0b */
/*08f0*/ SEL R15, R8, R15, !P3 ; /* 0x0000000f080f7207 */
/* 0x000fc40005800000 */
/*0900*/ SEL R17, R8.reuse, R17, !P3 ; /* 0x0000001108117207 */
/* 0x040fe40005800000 */
/*0910*/ SEL R11, R8.reuse, R11, !P3 ; /* 0x0000000b080b7207 */
/* 0x040fe40005800000 */
/*0920*/ SEL R9, R8, R9, !P3 ; /* 0x0000000908097207 */
/* 0x000fe20005800000 */
/*0930*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0006 */
/*0940*/ ISETP.NE.AND P2, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f45270 */
/*0950*/ ISETP.NE.AND P3, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe40003f65270 */
/*0960*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fc40003f05270 */
/*0970*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f25270 */
/*0980*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fcc00078e0007 */
/*0990*/ @!P2 IMAD.MOV.U32 R15, RZ, RZ, 0x1 ; /* 0x00000001ff0fa424 */
/* 0x000fe400078e00ff */
/*09a0*/ @!P3 IMAD.MOV.U32 R17, RZ, RZ, 0x1 ; /* 0x00000001ff11b424 */
/* 0x000fe400078e00ff */
/*09b0*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b8424 */
/* 0x000fe200078e00ff */
/*09c0*/ @!P2 STG.E [R8.64+0x8], R15 ; /* 0x0000080f0800a986 */
/* 0x0001e2000c101924 */
/*09d0*/ @!P1 IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d9424 */
/* 0x000fc600078e00ff */
/*09e0*/ @!P3 STG.E [R8.64+0xc], R17 ; /* 0x00000c110800b986 */
/* 0x0001e8000c101924 */
/*09f0*/ @!P0 STG.E [R8.64], R11 ; /* 0x0000000b08008986 */
/* 0x0001e2000c101924 */
/*0a00*/ ISETP.GE.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x000fc60003f06270 */
/*0a10*/ @!P1 STG.E [R8.64+0x4], R13 ; /* 0x0000040d08009986 */
/* 0x0001e2000c101924 */
/*0a20*/ IADD3 R6, P1, R8, 0x10, RZ ; /* 0x0000001008067810 */
/* 0x000fca0007f3e0ff */
/*0a30*/ IMAD.X R7, RZ, RZ, R9, P1 ; /* 0x000000ffff077224 */
/* 0x000fc800008e0609 */
/*0a40*/ @!P0 BRA 0x570 ; /* 0xfffffb2000008947 */
/* 0x000fea000383ffff */
/*0a50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a60*/ BRA 0xa60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<cuda.h>
__global__ void prime_generator(int *input,int *prime_list,int *total_input,int *seed)
{
printf("-------XXXXXX>>> %d\n",seed[0]);
int i= blockIdx.x * blockDim.x + threadIdx.x;
int primeno= prime_list[i];
int total=seed[0]*seed[0];
for(int k=seed[0];k<total;k++)
{
if(k%primeno==0)
{
input[k]=1;
}
}
}
int main()
{
int total_input=100000000;
int *input;
int n= 10 ;// seed prime list.
int calculate_upto=pow(n,2);
int *primelist;
input=(int *)malloc(total_input*sizeof(int));
primelist=(int *)malloc(total_input*sizeof(int));
memset(input,-1,total_input*sizeof(int));
for(int j=0;j<calculate_upto;j++)
{
input[j]=0;
}
for (int p=2; p*p<=n; p++)
{
if (input[p] == 0)
{
for (int i=p*2; i<=n; i += p)
input[i] = 1;
}
}
int i=0;
for (int p=2; p<=n; p++){
if (input[p]==0)
{
primelist[i]=p;
i++;
}
}
int *d_input;
int *d_prime_list;
int *h_pl;
int *d_total_input;
int *d_seed;
h_pl=(int *)malloc(total_input*sizeof(int));
cudaMalloc(&d_input,total_input*sizeof(int));
cudaMalloc(&d_prime_list,total_input*sizeof(int));
cudaMalloc(&d_total_input,sizeof(int));
cudaMalloc(&d_seed,sizeof(int));
cudaMemcpy(d_total_input,&total_input,sizeof(int),cudaMemcpyHostToDevice);
//cudaMemcpy(d_input,input,total_input*sizeof(int),cudaMemcpyHostToDevice);
while(n<=total_input){
printf("inside loop\n");
if(cudaMemcpy(d_input,input,total_input*sizeof(int),cudaMemcpyHostToDevice)!=cudaSuccess)
{
printf("not able to copy memory\n");
}
if(cudaMemcpy(d_prime_list,primelist,total_input*sizeof(int),cudaMemcpyHostToDevice) != cudaSuccess)
{
printf("not able to copy memory 2\n");
}
if(cudaMemcpy(d_seed,&n,sizeof(int),cudaMemcpyHostToDevice) != cudaSuccess)
{
printf(" not able to copy memory\n");
}
prime_generator<<<5,500>>>(d_input,d_prime_list,d_total_input,d_seed);
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess)
printf("Error: %s\n", cudaGetErrorString(err));
/*
if(cudaMemcpy(h_pl,d_prime_list,total_input*sizeof(int),cudaMemcpyDeviceToHost)!=cudaSuccess)
{
printf("not able to copy memory!!\n");
}
*/
if(cudaMemcpy(input,d_input,total_input*sizeof(int),cudaMemcpyDeviceToHost)!=cudaSuccess)
{
printf(" hello not able to copy memory::\n");
}
printf("------------>> %d\n",i);
for(int p=n;p<total_input;p++)
{
// printf("%d ----> %d\n",p,input[p]);
if(input[p]==0){
primelist[i]=p;
i++;
}
}
for(int p=0;p<i;p++)
{
printf("%d\n",primelist[p]);
}
n=n*n;
printf("################ %d\n",n);
if(pow(n,2)>=total_input){
for(int m=n;m<total_input;m++) input[m]=0;
}
else
{
for(int m=n;m<pow(n,2);m++) input[m]=0;
}
}
/*for(int p=0;p<i;p++)
{
printf("%d\n",primelist[p]);
}*/
return 0;
} | .file "tmpxft_00180de2_00000000-6_prime.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z15prime_generatorPiS_S_S_PiS_S_S_
.type _Z41__device_stub__Z15prime_generatorPiS_S_S_PiS_S_S_, @function
_Z41__device_stub__Z15prime_generatorPiS_S_S_PiS_S_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15prime_generatorPiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z41__device_stub__Z15prime_generatorPiS_S_S_PiS_S_S_, .-_Z41__device_stub__Z15prime_generatorPiS_S_S_PiS_S_S_
.globl _Z15prime_generatorPiS_S_S_
.type _Z15prime_generatorPiS_S_S_, @function
_Z15prime_generatorPiS_S_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15prime_generatorPiS_S_S_PiS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z15prime_generatorPiS_S_S_, .-_Z15prime_generatorPiS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "inside loop\n"
.LC1:
.string "not able to copy memory\n"
.LC2:
.string "not able to copy memory 2\n"
.LC3:
.string " not able to copy memory\n"
.LC4:
.string "Error: %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string " hello not able to copy memory::\n"
.section .rodata.str1.1
.LC6:
.string "------------>> %d\n"
.LC7:
.string "%d\n"
.LC8:
.string "################ %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $100000000, 8(%rsp)
movl $10, 12(%rsp)
movl $400000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $400000000, %edi
call malloc@PLT
movq %rax, %r15
movl $400000000, %edx
movl $-1, %esi
movq %rbp, %rdi
call memset@PLT
leaq 400(%rbp), %rdx
.L12:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
movl $4, %esi
movl $2, %ecx
jmp .L16
.L13:
leal 1(%rdx), %eax
addq $1, %rcx
addl $2, %esi
imull %eax, %eax
cmpl $10, %eax
jg .L14
.L16:
movl %ecx, %edx
cmpl $0, 0(%rbp,%rcx,4)
jne .L13
cmpl $10, %esi
jg .L14
movslq %esi, %rax
.L15:
movl $1, 0(%rbp,%rax,4)
addq %rcx, %rax
cmpl $10, %eax
jle .L15
jmp .L13
.L14:
movl $2, %eax
movl $0, %r12d
jmp .L18
.L17:
addq $1, %rax
cmpq $11, %rax
je .L47
.L18:
cmpl $0, 0(%rbp,%rax,4)
jne .L17
movslq %r12d, %rdx
movl %eax, (%r15,%rdx,4)
addl $1, %r12d
jmp .L17
.L47:
leaq 16(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
movslq 8(%rsp), %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl 8(%rsp), %eax
cmpl %eax, 12(%rsp)
jle .L37
jmp .L19
.L48:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L20
.L49:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L50:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L51:
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z41__device_stub__Z15prime_generatorPiS_S_S_PiS_S_S_
jmp .L23
.L52:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.L53:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L25
.L27:
addq $1, %rax
cmpl %eax, %edx
jle .L26
.L28:
cmpl $0, 0(%rbp,%rax,4)
jne .L27
movslq %r12d, %rcx
movl %eax, (%r15,%rcx,4)
addl $1, %r12d
jmp .L27
.L26:
testl %r12d, %r12d
jle .L29
movq %r15, %rbx
movslq %r12d, %rax
leaq (%r15,%rax,4), %r14
leaq .LC7(%rip), %r13
.L30:
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r14, %rbx
jne .L30
.L29:
movl 12(%rsp), %edx
imull %edx, %edx
movl %edx, 12(%rsp)
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %ecx
pxor %xmm0, %xmm0
cvtsi2sdl %ecx, %xmm0
mulsd %xmm0, %xmm0
movl 8(%rsp), %edx
pxor %xmm1, %xmm1
cvtsi2sdl %edx, %xmm1
movslq %ecx, %rax
comisd %xmm1, %xmm0
jb .L32
cmpl %edx, %ecx
jge .L33
movslq %ecx, %rsi
leaq 0(%rbp,%rsi,4), %rax
subl %ecx, %edx
addq %rsi, %rdx
leaq 0(%rbp,%rdx,4), %rdx
.L34:
movl $0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L34
.L37:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq 8(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L48
.L20:
movslq 8(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L49
.L21:
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L50
.L22:
movl $500, 60(%rsp)
movl $1, 64(%rsp)
movl $5, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L23:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L52
.L24:
movslq 8(%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L53
.L25:
movl %r12d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %eax
movl 8(%rsp), %edx
cmpl %edx, %eax
jge .L26
cltq
jmp .L28
.L36:
movl $0, 0(%rbp,%rax,4)
addq $1, %rax
.L32:
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
comisd %xmm1, %xmm0
ja .L36
.L33:
cmpl %edx, %ecx
jle .L37
.L19:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L54
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z15prime_generatorPiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z15prime_generatorPiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<cuda.h>
__global__ void prime_generator(int *input,int *prime_list,int *total_input,int *seed)
{
printf("-------XXXXXX>>> %d\n",seed[0]);
int i= blockIdx.x * blockDim.x + threadIdx.x;
int primeno= prime_list[i];
int total=seed[0]*seed[0];
for(int k=seed[0];k<total;k++)
{
if(k%primeno==0)
{
input[k]=1;
}
}
}
int main()
{
int total_input=100000000;
int *input;
int n= 10 ;// seed prime list.
int calculate_upto=pow(n,2);
int *primelist;
input=(int *)malloc(total_input*sizeof(int));
primelist=(int *)malloc(total_input*sizeof(int));
memset(input,-1,total_input*sizeof(int));
for(int j=0;j<calculate_upto;j++)
{
input[j]=0;
}
for (int p=2; p*p<=n; p++)
{
if (input[p] == 0)
{
for (int i=p*2; i<=n; i += p)
input[i] = 1;
}
}
int i=0;
for (int p=2; p<=n; p++){
if (input[p]==0)
{
primelist[i]=p;
i++;
}
}
int *d_input;
int *d_prime_list;
int *h_pl;
int *d_total_input;
int *d_seed;
h_pl=(int *)malloc(total_input*sizeof(int));
cudaMalloc(&d_input,total_input*sizeof(int));
cudaMalloc(&d_prime_list,total_input*sizeof(int));
cudaMalloc(&d_total_input,sizeof(int));
cudaMalloc(&d_seed,sizeof(int));
cudaMemcpy(d_total_input,&total_input,sizeof(int),cudaMemcpyHostToDevice);
//cudaMemcpy(d_input,input,total_input*sizeof(int),cudaMemcpyHostToDevice);
while(n<=total_input){
printf("inside loop\n");
if(cudaMemcpy(d_input,input,total_input*sizeof(int),cudaMemcpyHostToDevice)!=cudaSuccess)
{
printf("not able to copy memory\n");
}
if(cudaMemcpy(d_prime_list,primelist,total_input*sizeof(int),cudaMemcpyHostToDevice) != cudaSuccess)
{
printf("not able to copy memory 2\n");
}
if(cudaMemcpy(d_seed,&n,sizeof(int),cudaMemcpyHostToDevice) != cudaSuccess)
{
printf(" not able to copy memory\n");
}
prime_generator<<<5,500>>>(d_input,d_prime_list,d_total_input,d_seed);
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess)
printf("Error: %s\n", cudaGetErrorString(err));
/*
if(cudaMemcpy(h_pl,d_prime_list,total_input*sizeof(int),cudaMemcpyDeviceToHost)!=cudaSuccess)
{
printf("not able to copy memory!!\n");
}
*/
if(cudaMemcpy(input,d_input,total_input*sizeof(int),cudaMemcpyDeviceToHost)!=cudaSuccess)
{
printf(" hello not able to copy memory::\n");
}
printf("------------>> %d\n",i);
for(int p=n;p<total_input;p++)
{
// printf("%d ----> %d\n",p,input[p]);
if(input[p]==0){
primelist[i]=p;
i++;
}
}
for(int p=0;p<i;p++)
{
printf("%d\n",primelist[p]);
}
n=n*n;
printf("################ %d\n",n);
if(pow(n,2)>=total_input){
for(int m=n;m<total_input;m++) input[m]=0;
}
else
{
for(int m=n;m<pow(n,2);m++) input[m]=0;
}
}
/*for(int p=0;p<i;p++)
{
printf("%d\n",primelist[p]);
}*/
return 0;
} | #include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<hip/hip_runtime.h>
__global__ void prime_generator(int *input,int *prime_list,int *total_input,int *seed)
{
printf("-------XXXXXX>>> %d\n",seed[0]);
int i= blockIdx.x * blockDim.x + threadIdx.x;
int primeno= prime_list[i];
int total=seed[0]*seed[0];
for(int k=seed[0];k<total;k++)
{
if(k%primeno==0)
{
input[k]=1;
}
}
}
int main()
{
int total_input=100000000;
int *input;
int n= 10 ;// seed prime list.
int calculate_upto=pow(n,2);
int *primelist;
input=(int *)malloc(total_input*sizeof(int));
primelist=(int *)malloc(total_input*sizeof(int));
memset(input,-1,total_input*sizeof(int));
for(int j=0;j<calculate_upto;j++)
{
input[j]=0;
}
for (int p=2; p*p<=n; p++)
{
if (input[p] == 0)
{
for (int i=p*2; i<=n; i += p)
input[i] = 1;
}
}
int i=0;
for (int p=2; p<=n; p++){
if (input[p]==0)
{
primelist[i]=p;
i++;
}
}
int *d_input;
int *d_prime_list;
int *h_pl;
int *d_total_input;
int *d_seed;
h_pl=(int *)malloc(total_input*sizeof(int));
hipMalloc(&d_input,total_input*sizeof(int));
hipMalloc(&d_prime_list,total_input*sizeof(int));
hipMalloc(&d_total_input,sizeof(int));
hipMalloc(&d_seed,sizeof(int));
hipMemcpy(d_total_input,&total_input,sizeof(int),hipMemcpyHostToDevice);
//cudaMemcpy(d_input,input,total_input*sizeof(int),cudaMemcpyHostToDevice);
while(n<=total_input){
printf("inside loop\n");
if(hipMemcpy(d_input,input,total_input*sizeof(int),hipMemcpyHostToDevice)!=hipSuccess)
{
printf("not able to copy memory\n");
}
if(hipMemcpy(d_prime_list,primelist,total_input*sizeof(int),hipMemcpyHostToDevice) != hipSuccess)
{
printf("not able to copy memory 2\n");
}
if(hipMemcpy(d_seed,&n,sizeof(int),hipMemcpyHostToDevice) != hipSuccess)
{
printf(" not able to copy memory\n");
}
prime_generator<<<5,500>>>(d_input,d_prime_list,d_total_input,d_seed);
hipError_t err = hipGetLastError();
if (err != hipSuccess)
printf("Error: %s\n", hipGetErrorString(err));
/*
if(cudaMemcpy(h_pl,d_prime_list,total_input*sizeof(int),cudaMemcpyDeviceToHost)!=cudaSuccess)
{
printf("not able to copy memory!!\n");
}
*/
if(hipMemcpy(input,d_input,total_input*sizeof(int),hipMemcpyDeviceToHost)!=hipSuccess)
{
printf(" hello not able to copy memory::\n");
}
printf("------------>> %d\n",i);
for(int p=n;p<total_input;p++)
{
// printf("%d ----> %d\n",p,input[p]);
if(input[p]==0){
primelist[i]=p;
i++;
}
}
for(int p=0;p<i;p++)
{
printf("%d\n",primelist[p]);
}
n=n*n;
printf("################ %d\n",n);
if(pow(n,2)>=total_input){
for(int m=n;m<total_input;m++) input[m]=0;
}
else
{
for(int m=n;m<pow(n,2);m++) input[m]=0;
}
}
/*for(int p=0;p<i;p++)
{
printf("%d\n",primelist[p]);
}*/
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<hip/hip_runtime.h>
__global__ void prime_generator(int *input,int *prime_list,int *total_input,int *seed)
{
printf("-------XXXXXX>>> %d\n",seed[0]);
int i= blockIdx.x * blockDim.x + threadIdx.x;
int primeno= prime_list[i];
int total=seed[0]*seed[0];
for(int k=seed[0];k<total;k++)
{
if(k%primeno==0)
{
input[k]=1;
}
}
}
int main()
{
int total_input=100000000;
int *input;
int n= 10 ;// seed prime list.
int calculate_upto=pow(n,2);
int *primelist;
input=(int *)malloc(total_input*sizeof(int));
primelist=(int *)malloc(total_input*sizeof(int));
memset(input,-1,total_input*sizeof(int));
for(int j=0;j<calculate_upto;j++)
{
input[j]=0;
}
for (int p=2; p*p<=n; p++)
{
if (input[p] == 0)
{
for (int i=p*2; i<=n; i += p)
input[i] = 1;
}
}
int i=0;
for (int p=2; p<=n; p++){
if (input[p]==0)
{
primelist[i]=p;
i++;
}
}
int *d_input;
int *d_prime_list;
int *h_pl;
int *d_total_input;
int *d_seed;
h_pl=(int *)malloc(total_input*sizeof(int));
hipMalloc(&d_input,total_input*sizeof(int));
hipMalloc(&d_prime_list,total_input*sizeof(int));
hipMalloc(&d_total_input,sizeof(int));
hipMalloc(&d_seed,sizeof(int));
hipMemcpy(d_total_input,&total_input,sizeof(int),hipMemcpyHostToDevice);
//cudaMemcpy(d_input,input,total_input*sizeof(int),cudaMemcpyHostToDevice);
while(n<=total_input){
printf("inside loop\n");
if(hipMemcpy(d_input,input,total_input*sizeof(int),hipMemcpyHostToDevice)!=hipSuccess)
{
printf("not able to copy memory\n");
}
if(hipMemcpy(d_prime_list,primelist,total_input*sizeof(int),hipMemcpyHostToDevice) != hipSuccess)
{
printf("not able to copy memory 2\n");
}
if(hipMemcpy(d_seed,&n,sizeof(int),hipMemcpyHostToDevice) != hipSuccess)
{
printf(" not able to copy memory\n");
}
prime_generator<<<5,500>>>(d_input,d_prime_list,d_total_input,d_seed);
hipError_t err = hipGetLastError();
if (err != hipSuccess)
printf("Error: %s\n", hipGetErrorString(err));
/*
if(cudaMemcpy(h_pl,d_prime_list,total_input*sizeof(int),cudaMemcpyDeviceToHost)!=cudaSuccess)
{
printf("not able to copy memory!!\n");
}
*/
if(hipMemcpy(input,d_input,total_input*sizeof(int),hipMemcpyDeviceToHost)!=hipSuccess)
{
printf(" hello not able to copy memory::\n");
}
printf("------------>> %d\n",i);
for(int p=n;p<total_input;p++)
{
// printf("%d ----> %d\n",p,input[p]);
if(input[p]==0){
primelist[i]=p;
i++;
}
}
for(int p=0;p<i;p++)
{
printf("%d\n",primelist[p]);
}
n=n*n;
printf("################ %d\n",n);
if(pow(n,2)>=total_input){
for(int m=n;m<total_input;m++) input[m]=0;
}
else
{
for(int m=n;m<pow(n,2);m++) input[m]=0;
}
}
/*for(int p=0;p<i;p++)
{
printf("%d\n",primelist[p]);
}*/
return 0;
} | .text
.file "prime.hip"
.globl _Z30__device_stub__prime_generatorPiS_S_S_ # -- Begin function _Z30__device_stub__prime_generatorPiS_S_S_
.p2align 4, 0x90
.type _Z30__device_stub__prime_generatorPiS_S_S_,@function
_Z30__device_stub__prime_generatorPiS_S_S_: # @_Z30__device_stub__prime_generatorPiS_S_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15prime_generatorPiS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__prime_generatorPiS_S_S_, .Lfunc_end0-_Z30__device_stub__prime_generatorPiS_S_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.preheader83.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $100000000, 8(%rsp) # imm = 0x5F5E100
movl $10, 12(%rsp)
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %rbx
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %r14
movl $400000000, %edx # imm = 0x17D78400
movq %rbx, %rdi
movl $255, %esi
callq memset@PLT
movl $400, %edx # imm = 0x190
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 16(%rbx), %rax
movl $4, %ecx
movl $2, %edx
movl $8, %esi
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_4: # %.loopexit82
# in Loop: Header=BB1_1 Depth=1
incq %rdx
addq $2, %rcx
addq $8, %rax
addq $4, %rsi
cmpq $4, %rdx
je .LBB1_5
.LBB1_1: # %.preheader83
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
cmpl $0, (%rbx,%rdx,4)
jne .LBB1_4
# %bb.2: # %.lr.ph.preheader
# in Loop: Header=BB1_1 Depth=1
movq %rax, %rdi
movq %rcx, %r8
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, (%rdi)
addq %rdx, %r8
addq %rsi, %rdi
cmpq $11, %r8
jb .LBB1_3
jmp .LBB1_4
.LBB1_5: # %.preheader81.preheader
xorl %r15d, %r15d
movl $2, %eax
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_6 Depth=1
incq %rax
cmpq $11, %rax
je .LBB1_9
.LBB1_6: # %.preheader81
# =>This Inner Loop Header: Depth=1
cmpl $0, (%rbx,%rax,4)
jne .LBB1_8
# %bb.7: # in Loop: Header=BB1_6 Depth=1
movslq %r15d, %r15
movl %eax, (%r14,%r15,4)
incl %r15d
jmp .LBB1_8
.LBB1_9:
leaq 16(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
movslq 8(%rsp), %rsi
shlq $2, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 32(%rsp), %rdi
leaq 8(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %eax
cmpl 8(%rsp), %eax
jle .LBB1_10
.LBB1_38: # %._crit_edge105
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_10: # %.lr.ph104
.cfi_def_cfa_offset 224
movabsq $4294967301, %rax # imm = 0x100000005
leaq 495(%rax), %rbp
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_37: # %.loopexit
# in Loop: Header=BB1_11 Depth=1
movl 12(%rsp), %eax
cmpl 8(%rsp), %eax
jg .LBB1_38
.LBB1_11: # =>This Loop Header: Depth=1
# Child Loop BB1_25 Depth 2
# Child Loop BB1_30 Depth 2
# Child Loop BB1_36 Depth 2
movl $.Lstr, %edi
callq puts@PLT
movq 16(%rsp), %rdi
movslq 8(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_13
# %bb.12: # in Loop: Header=BB1_11 Depth=1
movl $.Lstr.1, %edi
callq puts@PLT
.LBB1_13: # in Loop: Header=BB1_11 Depth=1
movq 40(%rsp), %rdi
movslq 8(%rsp), %rdx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_15
# %bb.14: # in Loop: Header=BB1_11 Depth=1
movl $.Lstr.2, %edi
callq puts@PLT
.LBB1_15: # in Loop: Header=BB1_11 Depth=1
movq 24(%rsp), %rdi
movl $4, %edx
leaq 12(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_17
# %bb.16: # in Loop: Header=BB1_11 Depth=1
movl $.Lstr.3, %edi
callq puts@PLT
.LBB1_17: # in Loop: Header=BB1_11 Depth=1
movabsq $4294967301, %rdi # imm = 0x100000005
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_19
# %bb.18: # in Loop: Header=BB1_11 Depth=1
movq 16(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rsi, 96(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z15prime_generatorPiS_S_S_, %edi
leaq 128(%rsp), %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_19: # in Loop: Header=BB1_11 Depth=1
callq hipGetLastError
testl %eax, %eax
je .LBB1_21
# %bb.20: # in Loop: Header=BB1_11 Depth=1
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_21: # in Loop: Header=BB1_11 Depth=1
movq 16(%rsp), %rsi
movslq 8(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_23
# %bb.22: # in Loop: Header=BB1_11 Depth=1
movl $.Lstr.4, %edi
callq puts@PLT
.LBB1_23: # in Loop: Header=BB1_11 Depth=1
movl $.L.str.6, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movslq 12(%rsp), %rsi
movslq 8(%rsp), %rax
cmpl %eax, %esi
jge .LBB1_28
# %bb.24: # %.lr.ph92.preheader
# in Loop: Header=BB1_11 Depth=1
movl %esi, %ecx
leaq (%rbx,%rsi,4), %rdx
subq %rsi, %rax
xorl %esi, %esi
jmp .LBB1_25
.p2align 4, 0x90
.LBB1_27: # in Loop: Header=BB1_25 Depth=2
incq %rsi
cmpq %rsi, %rax
je .LBB1_28
.LBB1_25: # %.lr.ph92
# Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
cmpl $0, (%rdx,%rsi,4)
jne .LBB1_27
# %bb.26: # in Loop: Header=BB1_25 Depth=2
movslq %r15d, %r15
leal (%rcx,%rsi), %edi
movl %edi, (%r14,%r15,4)
incl %r15d
jmp .LBB1_27
.p2align 4, 0x90
.LBB1_28: # %.preheader
# in Loop: Header=BB1_11 Depth=1
testl %r15d, %r15d
jle .LBB1_31
# %bb.29: # %.lr.ph94.preheader
# in Loop: Header=BB1_11 Depth=1
movl %r15d, %r13d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_30: # %.lr.ph94
# Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %r13
jne .LBB1_30
.LBB1_31: # %._crit_edge
# in Loop: Header=BB1_11 Depth=1
movl 12(%rsp), %esi
imull %esi, %esi
movl %esi, 12(%rsp)
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movslq 12(%rsp), %rax
cvtsi2sd %eax, %xmm0
mulsd %xmm0, %xmm0
movl 8(%rsp), %ecx
cvtsi2sd %ecx, %xmm1
ucomisd %xmm1, %xmm0
jae .LBB1_32
# %bb.34: # in Loop: Header=BB1_11 Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
movapd %xmm1, %xmm0
mulsd %xmm1, %xmm0
ucomisd %xmm1, %xmm0
jbe .LBB1_37
# %bb.35: # %.lr.ph100.preheader
# in Loop: Header=BB1_11 Depth=1
leaq (%rbx,%rax,4), %rcx
incl %eax
.p2align 4, 0x90
.LBB1_36: # %.lr.ph100
# Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movl $0, (%rcx)
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
addq $4, %rcx
incl %eax
ucomisd %xmm1, %xmm0
ja .LBB1_36
jmp .LBB1_37
.p2align 4, 0x90
.LBB1_32: # in Loop: Header=BB1_11 Depth=1
cmpl %ecx, %eax
jge .LBB1_37
# %bb.33: # %.lr.ph97.preheader
# in Loop: Header=BB1_11 Depth=1
leaq (%rbx,%rax,4), %rdi
notl %eax
addl %eax, %ecx
leaq 4(,%rcx,4), %rdx
xorl %esi, %esi
callq memset@PLT
jmp .LBB1_37
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15prime_generatorPiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15prime_generatorPiS_S_S_,@object # @_Z15prime_generatorPiS_S_S_
.section .rodata,"a",@progbits
.globl _Z15prime_generatorPiS_S_S_
.p2align 3, 0x0
_Z15prime_generatorPiS_S_S_:
.quad _Z30__device_stub__prime_generatorPiS_S_S_
.size _Z15prime_generatorPiS_S_S_, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "Error: %s\n"
.size .L.str.4, 11
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "------------>> %d\n"
.size .L.str.6, 19
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d\n"
.size .L.str.7, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "################ %d\n"
.size .L.str.8, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15prime_generatorPiS_S_S_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "inside loop"
.size .Lstr, 12
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "not able to copy memory"
.size .Lstr.1, 24
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "not able to copy memory 2"
.size .Lstr.2, 26
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz " not able to copy memory"
.size .Lstr.3, 25
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz " hello not able to copy memory::"
.size .Lstr.4, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__prime_generatorPiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15prime_generatorPiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00180de2_00000000-6_prime.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z15prime_generatorPiS_S_S_PiS_S_S_
.type _Z41__device_stub__Z15prime_generatorPiS_S_S_PiS_S_S_, @function
_Z41__device_stub__Z15prime_generatorPiS_S_S_PiS_S_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15prime_generatorPiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z41__device_stub__Z15prime_generatorPiS_S_S_PiS_S_S_, .-_Z41__device_stub__Z15prime_generatorPiS_S_S_PiS_S_S_
.globl _Z15prime_generatorPiS_S_S_
.type _Z15prime_generatorPiS_S_S_, @function
_Z15prime_generatorPiS_S_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15prime_generatorPiS_S_S_PiS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z15prime_generatorPiS_S_S_, .-_Z15prime_generatorPiS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "inside loop\n"
.LC1:
.string "not able to copy memory\n"
.LC2:
.string "not able to copy memory 2\n"
.LC3:
.string " not able to copy memory\n"
.LC4:
.string "Error: %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string " hello not able to copy memory::\n"
.section .rodata.str1.1
.LC6:
.string "------------>> %d\n"
.LC7:
.string "%d\n"
.LC8:
.string "################ %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $100000000, 8(%rsp)
movl $10, 12(%rsp)
movl $400000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $400000000, %edi
call malloc@PLT
movq %rax, %r15
movl $400000000, %edx
movl $-1, %esi
movq %rbp, %rdi
call memset@PLT
leaq 400(%rbp), %rdx
.L12:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
movl $4, %esi
movl $2, %ecx
jmp .L16
.L13:
leal 1(%rdx), %eax
addq $1, %rcx
addl $2, %esi
imull %eax, %eax
cmpl $10, %eax
jg .L14
.L16:
movl %ecx, %edx
cmpl $0, 0(%rbp,%rcx,4)
jne .L13
cmpl $10, %esi
jg .L14
movslq %esi, %rax
.L15:
movl $1, 0(%rbp,%rax,4)
addq %rcx, %rax
cmpl $10, %eax
jle .L15
jmp .L13
.L14:
movl $2, %eax
movl $0, %r12d
jmp .L18
.L17:
addq $1, %rax
cmpq $11, %rax
je .L47
.L18:
cmpl $0, 0(%rbp,%rax,4)
jne .L17
movslq %r12d, %rdx
movl %eax, (%r15,%rdx,4)
addl $1, %r12d
jmp .L17
.L47:
leaq 16(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
movslq 8(%rsp), %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl 8(%rsp), %eax
cmpl %eax, 12(%rsp)
jle .L37
jmp .L19
.L48:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L20
.L49:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L50:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L51:
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z41__device_stub__Z15prime_generatorPiS_S_S_PiS_S_S_
jmp .L23
.L52:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.L53:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L25
.L27:
addq $1, %rax
cmpl %eax, %edx
jle .L26
.L28:
cmpl $0, 0(%rbp,%rax,4)
jne .L27
movslq %r12d, %rcx
movl %eax, (%r15,%rcx,4)
addl $1, %r12d
jmp .L27
.L26:
testl %r12d, %r12d
jle .L29
movq %r15, %rbx
movslq %r12d, %rax
leaq (%r15,%rax,4), %r14
leaq .LC7(%rip), %r13
.L30:
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r14, %rbx
jne .L30
.L29:
movl 12(%rsp), %edx
imull %edx, %edx
movl %edx, 12(%rsp)
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %ecx
pxor %xmm0, %xmm0
cvtsi2sdl %ecx, %xmm0
mulsd %xmm0, %xmm0
movl 8(%rsp), %edx
pxor %xmm1, %xmm1
cvtsi2sdl %edx, %xmm1
movslq %ecx, %rax
comisd %xmm1, %xmm0
jb .L32
cmpl %edx, %ecx
jge .L33
movslq %ecx, %rsi
leaq 0(%rbp,%rsi,4), %rax
subl %ecx, %edx
addq %rsi, %rdx
leaq 0(%rbp,%rdx,4), %rdx
.L34:
movl $0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L34
.L37:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq 8(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L48
.L20:
movslq 8(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L49
.L21:
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L50
.L22:
movl $500, 60(%rsp)
movl $1, 64(%rsp)
movl $5, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L23:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L52
.L24:
movslq 8(%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L53
.L25:
movl %r12d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %eax
movl 8(%rsp), %edx
cmpl %edx, %eax
jge .L26
cltq
jmp .L28
.L36:
movl $0, 0(%rbp,%rax,4)
addq $1, %rax
.L32:
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
comisd %xmm1, %xmm0
ja .L36
.L33:
cmpl %edx, %ecx
jle .L37
.L19:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L54
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z15prime_generatorPiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z15prime_generatorPiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "prime.hip"
.globl _Z30__device_stub__prime_generatorPiS_S_S_ # -- Begin function _Z30__device_stub__prime_generatorPiS_S_S_
.p2align 4, 0x90
.type _Z30__device_stub__prime_generatorPiS_S_S_,@function
_Z30__device_stub__prime_generatorPiS_S_S_: # @_Z30__device_stub__prime_generatorPiS_S_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15prime_generatorPiS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__prime_generatorPiS_S_S_, .Lfunc_end0-_Z30__device_stub__prime_generatorPiS_S_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.preheader83.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $100000000, 8(%rsp) # imm = 0x5F5E100
movl $10, 12(%rsp)
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %rbx
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %r14
movl $400000000, %edx # imm = 0x17D78400
movq %rbx, %rdi
movl $255, %esi
callq memset@PLT
movl $400, %edx # imm = 0x190
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 16(%rbx), %rax
movl $4, %ecx
movl $2, %edx
movl $8, %esi
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_4: # %.loopexit82
# in Loop: Header=BB1_1 Depth=1
incq %rdx
addq $2, %rcx
addq $8, %rax
addq $4, %rsi
cmpq $4, %rdx
je .LBB1_5
.LBB1_1: # %.preheader83
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
cmpl $0, (%rbx,%rdx,4)
jne .LBB1_4
# %bb.2: # %.lr.ph.preheader
# in Loop: Header=BB1_1 Depth=1
movq %rax, %rdi
movq %rcx, %r8
.p2align 4, 0x90
.LBB1_3: # %.lr.ph
# Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, (%rdi)
addq %rdx, %r8
addq %rsi, %rdi
cmpq $11, %r8
jb .LBB1_3
jmp .LBB1_4
.LBB1_5: # %.preheader81.preheader
xorl %r15d, %r15d
movl $2, %eax
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_6 Depth=1
incq %rax
cmpq $11, %rax
je .LBB1_9
.LBB1_6: # %.preheader81
# =>This Inner Loop Header: Depth=1
cmpl $0, (%rbx,%rax,4)
jne .LBB1_8
# %bb.7: # in Loop: Header=BB1_6 Depth=1
movslq %r15d, %r15
movl %eax, (%r14,%r15,4)
incl %r15d
jmp .LBB1_8
.LBB1_9:
leaq 16(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
movslq 8(%rsp), %rsi
shlq $2, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 32(%rsp), %rdi
leaq 8(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %eax
cmpl 8(%rsp), %eax
jle .LBB1_10
.LBB1_38: # %._crit_edge105
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_10: # %.lr.ph104
.cfi_def_cfa_offset 224
movabsq $4294967301, %rax # imm = 0x100000005
leaq 495(%rax), %rbp
jmp .LBB1_11
.p2align 4, 0x90
.LBB1_37: # %.loopexit
# in Loop: Header=BB1_11 Depth=1
movl 12(%rsp), %eax
cmpl 8(%rsp), %eax
jg .LBB1_38
.LBB1_11: # =>This Loop Header: Depth=1
# Child Loop BB1_25 Depth 2
# Child Loop BB1_30 Depth 2
# Child Loop BB1_36 Depth 2
movl $.Lstr, %edi
callq puts@PLT
movq 16(%rsp), %rdi
movslq 8(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_13
# %bb.12: # in Loop: Header=BB1_11 Depth=1
movl $.Lstr.1, %edi
callq puts@PLT
.LBB1_13: # in Loop: Header=BB1_11 Depth=1
movq 40(%rsp), %rdi
movslq 8(%rsp), %rdx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_15
# %bb.14: # in Loop: Header=BB1_11 Depth=1
movl $.Lstr.2, %edi
callq puts@PLT
.LBB1_15: # in Loop: Header=BB1_11 Depth=1
movq 24(%rsp), %rdi
movl $4, %edx
leaq 12(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_17
# %bb.16: # in Loop: Header=BB1_11 Depth=1
movl $.Lstr.3, %edi
callq puts@PLT
.LBB1_17: # in Loop: Header=BB1_11 Depth=1
movabsq $4294967301, %rdi # imm = 0x100000005
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_19
# %bb.18: # in Loop: Header=BB1_11 Depth=1
movq 16(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rsi, 96(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z15prime_generatorPiS_S_S_, %edi
leaq 128(%rsp), %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_19: # in Loop: Header=BB1_11 Depth=1
callq hipGetLastError
testl %eax, %eax
je .LBB1_21
# %bb.20: # in Loop: Header=BB1_11 Depth=1
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_21: # in Loop: Header=BB1_11 Depth=1
movq 16(%rsp), %rsi
movslq 8(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_23
# %bb.22: # in Loop: Header=BB1_11 Depth=1
movl $.Lstr.4, %edi
callq puts@PLT
.LBB1_23: # in Loop: Header=BB1_11 Depth=1
movl $.L.str.6, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movslq 12(%rsp), %rsi
movslq 8(%rsp), %rax
cmpl %eax, %esi
jge .LBB1_28
# %bb.24: # %.lr.ph92.preheader
# in Loop: Header=BB1_11 Depth=1
movl %esi, %ecx
leaq (%rbx,%rsi,4), %rdx
subq %rsi, %rax
xorl %esi, %esi
jmp .LBB1_25
.p2align 4, 0x90
.LBB1_27: # in Loop: Header=BB1_25 Depth=2
incq %rsi
cmpq %rsi, %rax
je .LBB1_28
.LBB1_25: # %.lr.ph92
# Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
cmpl $0, (%rdx,%rsi,4)
jne .LBB1_27
# %bb.26: # in Loop: Header=BB1_25 Depth=2
movslq %r15d, %r15
leal (%rcx,%rsi), %edi
movl %edi, (%r14,%r15,4)
incl %r15d
jmp .LBB1_27
.p2align 4, 0x90
.LBB1_28: # %.preheader
# in Loop: Header=BB1_11 Depth=1
testl %r15d, %r15d
jle .LBB1_31
# %bb.29: # %.lr.ph94.preheader
# in Loop: Header=BB1_11 Depth=1
movl %r15d, %r13d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_30: # %.lr.ph94
# Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %r13
jne .LBB1_30
.LBB1_31: # %._crit_edge
# in Loop: Header=BB1_11 Depth=1
movl 12(%rsp), %esi
imull %esi, %esi
movl %esi, 12(%rsp)
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movslq 12(%rsp), %rax
cvtsi2sd %eax, %xmm0
mulsd %xmm0, %xmm0
movl 8(%rsp), %ecx
cvtsi2sd %ecx, %xmm1
ucomisd %xmm1, %xmm0
jae .LBB1_32
# %bb.34: # in Loop: Header=BB1_11 Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
movapd %xmm1, %xmm0
mulsd %xmm1, %xmm0
ucomisd %xmm1, %xmm0
jbe .LBB1_37
# %bb.35: # %.lr.ph100.preheader
# in Loop: Header=BB1_11 Depth=1
leaq (%rbx,%rax,4), %rcx
incl %eax
.p2align 4, 0x90
.LBB1_36: # %.lr.ph100
# Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movl $0, (%rcx)
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
addq $4, %rcx
incl %eax
ucomisd %xmm1, %xmm0
ja .LBB1_36
jmp .LBB1_37
.p2align 4, 0x90
.LBB1_32: # in Loop: Header=BB1_11 Depth=1
cmpl %ecx, %eax
jge .LBB1_37
# %bb.33: # %.lr.ph97.preheader
# in Loop: Header=BB1_11 Depth=1
leaq (%rbx,%rax,4), %rdi
notl %eax
addl %eax, %ecx
leaq 4(,%rcx,4), %rdx
xorl %esi, %esi
callq memset@PLT
jmp .LBB1_37
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15prime_generatorPiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15prime_generatorPiS_S_S_,@object # @_Z15prime_generatorPiS_S_S_
.section .rodata,"a",@progbits
.globl _Z15prime_generatorPiS_S_S_
.p2align 3, 0x0
_Z15prime_generatorPiS_S_S_:
.quad _Z30__device_stub__prime_generatorPiS_S_S_
.size _Z15prime_generatorPiS_S_S_, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "Error: %s\n"
.size .L.str.4, 11
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "------------>> %d\n"
.size .L.str.6, 19
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d\n"
.size .L.str.7, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "################ %d\n"
.size .L.str.8, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15prime_generatorPiS_S_S_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "inside loop"
.size .Lstr, 12
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "not able to copy memory"
.size .Lstr.1, 24
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "not able to copy memory 2"
.size .Lstr.2, 26
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz " not able to copy memory"
.size .Lstr.3, 25
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz " hello not able to copy memory::"
.size .Lstr.4, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__prime_generatorPiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15prime_generatorPiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void BFS_UNIFIED(int source, int* edges, int* dest, int* label, int* visited, int *c_frontier_tail, int *c_frontier, int *p_frontier_tail, int *p_frontier)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < *p_frontier_tail)
{
int c_vertex = p_frontier[i];
for (int i = edges[c_vertex]; i < edges[c_vertex+1]; ++i)
{
int was_visited = atomicExch(visited + dest[i], 1);
if (!was_visited)
{
int old_tail = atomicAdd(c_frontier_tail, 1);
c_frontier[old_tail] = dest[i];
label[dest[i]] = label[c_vertex] + 1;
}
}
}
} | code for sm_80
Function : _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R3, c[0x0][0x19c] ; /* 0x0000670000037a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x198] ; /* 0x00006600ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x004fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*00b0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x1a0] ; /* 0x0000680004047625 */
/* 0x000fcc00078e0209 */
/*00c0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ IMAD.WIDE R2, R5, R9, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x004fca00078e0209 */
/*00e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x000ea4000c1e1900 */
/*0100*/ ISETP.GE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x004fda0003f06270 */
/*0110*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0120*/ SHF.R.S32.HI R8, RZ, 0x1f, R5 ; /* 0x0000001fff087819 */
/* 0x000fe20000011405 */
/*0130*/ IMAD.WIDE R6, R0, R9, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0209 */
/*0140*/ LEA R4, P0, R5, c[0x0][0x178], 0x2 ; /* 0x00005e0005047a11 */
/* 0x000fc800078010ff */
/*0150*/ LEA.HI.X R5, R5, c[0x0][0x17c], R8, 0x2, P0 ; /* 0x00005f0005057a11 */
/* 0x000fe400000f1408 */
/*0160*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000ea2000c1e1900 */
/*0170*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*0180*/ HFMA2.MMA R9, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff097435 */
/* 0x000fe200000001ff */
/*0190*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe40003800000 */
/*01a0*/ IMAD.WIDE R10, R11, R8, c[0x0][0x180] ; /* 0x000060000b0a7625 */
/* 0x004fcc00078e0208 */
/*01b0*/ ATOMG.E.EXCH.STRONG.GPU PT, R10, [R10.64], R9 ; /* 0x000000090a0a79a8 */
/* 0x000ea2000c1ee1c4 */
/*01c0*/ BSSY B0, 0x350 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*01d0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x004fda0003f05270 */
/*01e0*/ @P0 BRA 0x340 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*01f0*/ S2R R9, SR_LANEID ; /* 0x0000000000097919 */
/* 0x000e220000000000 */
/*0200*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe200038e0100 */
/*0210*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff0a7624 */
/* 0x000fe200078e00ff */
/*0220*/ FLO.U32 R14, UR6 ; /* 0x00000006000e7d00 */
/* 0x000e2200080e0000 */
/*0230*/ MOV R11, c[0x0][0x18c] ; /* 0x00006300000b7a02 */
/* 0x000fce0000000f00 */
/*0240*/ POPC R19, UR6 ; /* 0x0000000600137d09 */
/* 0x000e620008000000 */
/*0250*/ ISETP.EQ.U32.AND P0, PT, R14, R9, PT ; /* 0x000000090e00720c */
/* 0x001fda0003f02070 */
/*0260*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R19, [R10.64], R19 ; /* 0x000000130a1309a8 */
/* 0x002ea800081ee1c4 */
/*0270*/ LDG.E R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x000ee8000c1e1900 */
/*0280*/ S2R R9, SR_LTMASK ; /* 0x0000000000097919 */
/* 0x000e240000003900 */
/*0290*/ LOP3.LUT R16, R9, UR6, RZ, 0xc0, !PT ; /* 0x0000000609107c12 */
/* 0x001fcc000f8ec0ff */
/*02a0*/ POPC R16, R16 ; /* 0x0000001000107309 */
/* 0x000e220000000000 */
/*02b0*/ SHFL.IDX PT, R13, R19, R14, 0x1f ; /* 0x00001f0e130d7589 */
/* 0x004e2400000e0000 */
/*02c0*/ IMAD.IADD R13, R13, 0x1, R16 ; /* 0x000000010d0d7824 */
/* 0x001fc800078e0210 */
/*02d0*/ IMAD.WIDE R12, R13, R8, c[0x0][0x190] ; /* 0x000064000d0c7625 */
/* 0x000fca00078e0208 */
/*02e0*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x0081e8000c101904 */
/*02f0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1900 */
/*0300*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x000ee2000c1e1900 */
/*0310*/ IADD3 R11, R9, 0x1, RZ ; /* 0x00000001090b7810 */
/* 0x004fe20007ffe0ff */
/*0320*/ IMAD.WIDE R8, R17, R8, c[0x0][0x178] ; /* 0x00005e0011087625 */
/* 0x008fca00078e0208 */
/*0330*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e4000c101904 */
/*0340*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0350*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x001ea2000c1e1900 */
/*0360*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*0370*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc80007f3e0ff */
/*0380*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe40000ffe4ff */
/*0390*/ ISETP.GE.AND P0, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x004fda0003f06270 */
/*03a0*/ @!P0 BRA 0x160 ; /* 0xfffffdb000008947 */
/* 0x000fea000383ffff */
/*03b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03c0*/ BRA 0x3c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void BFS_UNIFIED(int source, int* edges, int* dest, int* label, int* visited, int *c_frontier_tail, int *c_frontier, int *p_frontier_tail, int *p_frontier)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < *p_frontier_tail)
{
int c_vertex = p_frontier[i];
for (int i = edges[c_vertex]; i < edges[c_vertex+1]; ++i)
{
int was_visited = atomicExch(visited + dest[i], 1);
if (!was_visited)
{
int old_tail = atomicAdd(c_frontier_tail, 1);
c_frontier[old_tail] = dest[i];
label[dest[i]] = label[c_vertex] + 1;
}
}
}
} | .file "tmpxft_00130070_00000000-6_BFS_UNIFIED.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_
.type _Z46__device_stub__Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_, @function
_Z46__device_stub__Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 76(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 240(%rsp), %rax
movq %rax, 24(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq 256(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 248
pushq 88(%rsp)
.cfi_def_cfa_offset 256
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_, .-_Z46__device_stub__Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_
.globl _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.type _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_, @function
_Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z46__device_stub__Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_, .-_Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void BFS_UNIFIED(int source, int* edges, int* dest, int* label, int* visited, int *c_frontier_tail, int *c_frontier, int *p_frontier_tail, int *p_frontier)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < *p_frontier_tail)
{
int c_vertex = p_frontier[i];
for (int i = edges[c_vertex]; i < edges[c_vertex+1]; ++i)
{
int was_visited = atomicExch(visited + dest[i], 1);
if (!was_visited)
{
int old_tail = atomicAdd(c_frontier_tail, 1);
c_frontier[old_tail] = dest[i];
label[dest[i]] = label[c_vertex] + 1;
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void BFS_UNIFIED(int source, int* edges, int* dest, int* label, int* visited, int *c_frontier_tail, int *c_frontier, int *p_frontier_tail, int *p_frontier)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < *p_frontier_tail)
{
int c_vertex = p_frontier[i];
for (int i = edges[c_vertex]; i < edges[c_vertex+1]; ++i)
{
int was_visited = atomicExch(visited + dest[i], 1);
if (!was_visited)
{
int old_tail = atomicAdd(c_frontier_tail, 1);
c_frontier[old_tail] = dest[i];
label[dest[i]] = label[c_vertex] + 1;
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void BFS_UNIFIED(int source, int* edges, int* dest, int* label, int* visited, int *c_frontier_tail, int *c_frontier, int *p_frontier_tail, int *p_frontier)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < *p_frontier_tail)
{
int c_vertex = p_frontier[i];
for (int i = edges[c_vertex]; i < edges[c_vertex+1]; ++i)
{
int was_visited = atomicExch(visited + dest[i], 1);
if (!was_visited)
{
int old_tail = atomicAdd(c_frontier_tail, 1);
c_frontier[old_tail] = dest[i];
label[dest[i]] = label[c_vertex] + 1;
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.globl _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.p2align 8
.type _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_,@function
_Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x38
s_load_b32 s4, s[0:1], 0x54
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b64 s[2:3], s[0:1], 0x40
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_load_b64 s[2:3], s[0:1], 0x8
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v5, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v2, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x30
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v7, 1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[8:9], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v8
v_mov_b32_e32 v8, 0
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v9, vcc_lo
s_branch .LBB0_5
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
global_load_b32 v11, v[5:6], off
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s4, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, s4, v9
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s2, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[9:10], v11, off
global_load_b32 v9, v[5:6], off
global_load_b32 v11, v[3:4], off
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v10, 31, v9
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v11, 1, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s6, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_store_b32 v[9:10], v11, off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
global_load_b32 v9, v[0:1], off offset:4
v_add_nc_u32_e32 v2, 1, v2
v_add_co_u32 v5, s0, v5, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, v2, v9
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_8
.LBB0_5:
global_load_b32 v9, v[5:6], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s8, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
global_atomic_swap_b32 v9, v[9:10], v7, off glc
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 0, v9
s_cbranch_execz .LBB0_4
s_mov_b32 s5, exec_lo
s_mov_b32 s4, exec_lo
v_mbcnt_lo_u32_b32 v9, s5, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v9
s_cbranch_execz .LBB0_3
s_bcnt1_i32_b32 s5, s5
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v10, s5
global_atomic_add_u32 v10, v8, v10, s[10:11] glc
s_branch .LBB0_3
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_, .Lfunc_end0-_Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void BFS_UNIFIED(int source, int* edges, int* dest, int* label, int* visited, int *c_frontier_tail, int *c_frontier, int *p_frontier_tail, int *p_frontier)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < *p_frontier_tail)
{
int c_vertex = p_frontier[i];
for (int i = edges[c_vertex]; i < edges[c_vertex+1]; ++i)
{
int was_visited = atomicExch(visited + dest[i], 1);
if (!was_visited)
{
int old_tail = atomicAdd(c_frontier_tail, 1);
c_frontier[old_tail] = dest[i];
label[dest[i]] = label[c_vertex] + 1;
}
}
}
} | .text
.file "BFS_UNIFIED.hip"
.globl _Z26__device_stub__BFS_UNIFIEDiPiS_S_S_S_S_S_S_ # -- Begin function _Z26__device_stub__BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.p2align 4, 0x90
.type _Z26__device_stub__BFS_UNIFIEDiPiS_S_S_S_S_S_S_,@function
_Z26__device_stub__BFS_UNIFIEDiPiS_S_S_S_S_S_S_: # @_Z26__device_stub__BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z26__device_stub__BFS_UNIFIEDiPiS_S_S_S_S_S_S_, .Lfunc_end0-_Z26__device_stub__BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_,@object # @_Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.p2align 3, 0x0
_Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_:
.quad _Z26__device_stub__BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.size _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R3, c[0x0][0x19c] ; /* 0x0000670000037a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x198] ; /* 0x00006600ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x004fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*00b0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x1a0] ; /* 0x0000680004047625 */
/* 0x000fcc00078e0209 */
/*00c0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ IMAD.WIDE R2, R5, R9, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x004fca00078e0209 */
/*00e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x000ea4000c1e1900 */
/*0100*/ ISETP.GE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x004fda0003f06270 */
/*0110*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0120*/ SHF.R.S32.HI R8, RZ, 0x1f, R5 ; /* 0x0000001fff087819 */
/* 0x000fe20000011405 */
/*0130*/ IMAD.WIDE R6, R0, R9, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0209 */
/*0140*/ LEA R4, P0, R5, c[0x0][0x178], 0x2 ; /* 0x00005e0005047a11 */
/* 0x000fc800078010ff */
/*0150*/ LEA.HI.X R5, R5, c[0x0][0x17c], R8, 0x2, P0 ; /* 0x00005f0005057a11 */
/* 0x000fe400000f1408 */
/*0160*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000ea2000c1e1900 */
/*0170*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*0180*/ HFMA2.MMA R9, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff097435 */
/* 0x000fe200000001ff */
/*0190*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe40003800000 */
/*01a0*/ IMAD.WIDE R10, R11, R8, c[0x0][0x180] ; /* 0x000060000b0a7625 */
/* 0x004fcc00078e0208 */
/*01b0*/ ATOMG.E.EXCH.STRONG.GPU PT, R10, [R10.64], R9 ; /* 0x000000090a0a79a8 */
/* 0x000ea2000c1ee1c4 */
/*01c0*/ BSSY B0, 0x350 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*01d0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x004fda0003f05270 */
/*01e0*/ @P0 BRA 0x340 ; /* 0x0000015000000947 */
/* 0x000fea0003800000 */
/*01f0*/ S2R R9, SR_LANEID ; /* 0x0000000000097919 */
/* 0x000e220000000000 */
/*0200*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe200038e0100 */
/*0210*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff0a7624 */
/* 0x000fe200078e00ff */
/*0220*/ FLO.U32 R14, UR6 ; /* 0x00000006000e7d00 */
/* 0x000e2200080e0000 */
/*0230*/ MOV R11, c[0x0][0x18c] ; /* 0x00006300000b7a02 */
/* 0x000fce0000000f00 */
/*0240*/ POPC R19, UR6 ; /* 0x0000000600137d09 */
/* 0x000e620008000000 */
/*0250*/ ISETP.EQ.U32.AND P0, PT, R14, R9, PT ; /* 0x000000090e00720c */
/* 0x001fda0003f02070 */
/*0260*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R19, [R10.64], R19 ; /* 0x000000130a1309a8 */
/* 0x002ea800081ee1c4 */
/*0270*/ LDG.E R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x000ee8000c1e1900 */
/*0280*/ S2R R9, SR_LTMASK ; /* 0x0000000000097919 */
/* 0x000e240000003900 */
/*0290*/ LOP3.LUT R16, R9, UR6, RZ, 0xc0, !PT ; /* 0x0000000609107c12 */
/* 0x001fcc000f8ec0ff */
/*02a0*/ POPC R16, R16 ; /* 0x0000001000107309 */
/* 0x000e220000000000 */
/*02b0*/ SHFL.IDX PT, R13, R19, R14, 0x1f ; /* 0x00001f0e130d7589 */
/* 0x004e2400000e0000 */
/*02c0*/ IMAD.IADD R13, R13, 0x1, R16 ; /* 0x000000010d0d7824 */
/* 0x001fc800078e0210 */
/*02d0*/ IMAD.WIDE R12, R13, R8, c[0x0][0x190] ; /* 0x000064000d0c7625 */
/* 0x000fca00078e0208 */
/*02e0*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x0081e8000c101904 */
/*02f0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1900 */
/*0300*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x000ee2000c1e1900 */
/*0310*/ IADD3 R11, R9, 0x1, RZ ; /* 0x00000001090b7810 */
/* 0x004fe20007ffe0ff */
/*0320*/ IMAD.WIDE R8, R17, R8, c[0x0][0x178] ; /* 0x00005e0011087625 */
/* 0x008fca00078e0208 */
/*0330*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e4000c101904 */
/*0340*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0350*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x001ea2000c1e1900 */
/*0360*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*0370*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc80007f3e0ff */
/*0380*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe40000ffe4ff */
/*0390*/ ISETP.GE.AND P0, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x004fda0003f06270 */
/*03a0*/ @!P0 BRA 0x160 ; /* 0xfffffdb000008947 */
/* 0x000fea000383ffff */
/*03b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03c0*/ BRA 0x3c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.globl _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.p2align 8
.type _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_,@function
_Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x38
s_load_b32 s4, s[0:1], 0x54
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b64 s[2:3], s[0:1], 0x40
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_load_b64 s[2:3], s[0:1], 0x8
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v5, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v2, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x30
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v7, 1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[8:9], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v8
v_mov_b32_e32 v8, 0
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v9, vcc_lo
s_branch .LBB0_5
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
global_load_b32 v11, v[5:6], off
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s4, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, s4, v9
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s2, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[9:10], v11, off
global_load_b32 v9, v[5:6], off
global_load_b32 v11, v[3:4], off
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v10, 31, v9
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v11, 1, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s6, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_store_b32 v[9:10], v11, off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
global_load_b32 v9, v[0:1], off offset:4
v_add_nc_u32_e32 v2, 1, v2
v_add_co_u32 v5, s0, v5, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, v2, v9
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_8
.LBB0_5:
global_load_b32 v9, v[5:6], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s8, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
global_atomic_swap_b32 v9, v[9:10], v7, off glc
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 0, v9
s_cbranch_execz .LBB0_4
s_mov_b32 s5, exec_lo
s_mov_b32 s4, exec_lo
v_mbcnt_lo_u32_b32 v9, s5, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v9
s_cbranch_execz .LBB0_3
s_bcnt1_i32_b32 s5, s5
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v10, s5
global_atomic_add_u32 v10, v8, v10, s[10:11] glc
s_branch .LBB0_3
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_, .Lfunc_end0-_Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00130070_00000000-6_BFS_UNIFIED.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_
.type _Z46__device_stub__Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_, @function
_Z46__device_stub__Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 76(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 240(%rsp), %rax
movq %rax, 24(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq 256(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 248
pushq 88(%rsp)
.cfi_def_cfa_offset 256
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_, .-_Z46__device_stub__Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_
.globl _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.type _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_, @function
_Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z46__device_stub__Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_iPiS_S_S_S_S_S_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_, .-_Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "BFS_UNIFIED.hip"
.globl _Z26__device_stub__BFS_UNIFIEDiPiS_S_S_S_S_S_S_ # -- Begin function _Z26__device_stub__BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.p2align 4, 0x90
.type _Z26__device_stub__BFS_UNIFIEDiPiS_S_S_S_S_S_S_,@function
_Z26__device_stub__BFS_UNIFIEDiPiS_S_S_S_S_S_S_: # @_Z26__device_stub__BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z26__device_stub__BFS_UNIFIEDiPiS_S_S_S_S_S_S_, .Lfunc_end0-_Z26__device_stub__BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_,@object # @_Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.p2align 3, 0x0
_Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_:
.quad _Z26__device_stub__BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.size _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11BFS_UNIFIEDiPiS_S_S_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void aproximarPi( float *x, float *y, int *z, int tam) {
int i = threadIdx.x + blockIdx.x*blockDim.x; // 0 - 2047
int j = threadIdx.y + blockIdx.y*blockDim.y; // 0 - 2047
int index = j + i*tam; // 0 - 4194303
if( (x[index] * x[index] + y[index] * y[index]) <= 1.0f){
atomicAdd(z, 1);
}
} | code for sm_80
Function : _Z11aproximarPiPfS_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fe200078e0205 */
/*0080*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fc600000001ff */
/*0090*/ IMAD R3, R0, c[0x0][0x178], R3 ; /* 0x00005e0000037a24 */
/* 0x000fce00078e0203 */
/*00a0*/ IMAD.WIDE R4, R3, R2, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0202 */
/*00b0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fe400078e0202 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee2000c1e1900 */
/*00e0*/ FMUL R7, R4, R4 ; /* 0x0000000404077220 */
/* 0x004fc80000400000 */
/*00f0*/ FFMA R7, R2, R2, R7 ; /* 0x0000000202077223 */
/* 0x008fca0000000007 */
/*0100*/ FSETP.GTU.AND P0, PT, R7, 1, PT ; /* 0x3f8000000700780b */
/* 0x000fda0003f0c000 */
/*0110*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0120*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0130*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe200038e0100 */
/*0140*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe20000000f00 */
/*0150*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0160*/ POPC R5, UR6 ; /* 0x0000000600057d09 */
/* 0x000e620008000000 */
/*0170*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fc80000000f00 */
/*0180*/ ISETP.EQ.U32.AND P0, PT, R0, UR7, PT ; /* 0x0000000700007c0c */
/* 0x001fda000bf02070 */
/*0190*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x002fe2000c10e184 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void aproximarPi( float *x, float *y, int *z, int tam) {
int i = threadIdx.x + blockIdx.x*blockDim.x; // 0 - 2047
int j = threadIdx.y + blockIdx.y*blockDim.y; // 0 - 2047
int index = j + i*tam; // 0 - 4194303
if( (x[index] * x[index] + y[index] * y[index]) <= 1.0f){
atomicAdd(z, 1);
}
} | .file "tmpxft_001361b6_00000000-6_aproximarPi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11aproximarPiPfS_PiiPfS_Pii
.type _Z36__device_stub__Z11aproximarPiPfS_PiiPfS_Pii, @function
_Z36__device_stub__Z11aproximarPiPfS_PiiPfS_Pii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11aproximarPiPfS_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z11aproximarPiPfS_PiiPfS_Pii, .-_Z36__device_stub__Z11aproximarPiPfS_PiiPfS_Pii
.globl _Z11aproximarPiPfS_Pii
.type _Z11aproximarPiPfS_Pii, @function
_Z11aproximarPiPfS_Pii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11aproximarPiPfS_PiiPfS_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11aproximarPiPfS_Pii, .-_Z11aproximarPiPfS_Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11aproximarPiPfS_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11aproximarPiPfS_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void aproximarPi( float *x, float *y, int *z, int tam) {
int i = threadIdx.x + blockIdx.x*blockDim.x; // 0 - 2047
int j = threadIdx.y + blockIdx.y*blockDim.y; // 0 - 2047
int index = j + i*tam; // 0 - 4194303
if( (x[index] * x[index] + y[index] * y[index]) <= 1.0f){
atomicAdd(z, 1);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void aproximarPi( float *x, float *y, int *z, int tam) {
int i = threadIdx.x + blockIdx.x*blockDim.x; // 0 - 2047
int j = threadIdx.y + blockIdx.y*blockDim.y; // 0 - 2047
int index = j + i*tam; // 0 - 4194303
if( (x[index] * x[index] + y[index] * y[index]) <= 1.0f){
atomicAdd(z, 1);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void aproximarPi( float *x, float *y, int *z, int tam) {
int i = threadIdx.x + blockIdx.x*blockDim.x; // 0 - 2047
int j = threadIdx.y + blockIdx.y*blockDim.y; // 0 - 2047
int index = j + i*tam; // 0 - 4194303
if( (x[index] * x[index] + y[index] * y[index]) <= 1.0f){
atomicAdd(z, 1);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11aproximarPiPfS_Pii
.globl _Z11aproximarPiPfS_Pii
.p2align 8
.type _Z11aproximarPiPfS_Pii,@function
_Z11aproximarPiPfS_Pii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s4, v[1:2]
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s3
v_add3_u32 v0, s15, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v1, v2, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v1, v0, v0
v_cmpx_ge_f32_e32 1.0, v1
s_cbranch_execz .LBB0_3
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x10
s_bcnt1_i32_b32 s2, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11aproximarPiPfS_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11aproximarPiPfS_Pii, .Lfunc_end0-_Z11aproximarPiPfS_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11aproximarPiPfS_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11aproximarPiPfS_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void aproximarPi( float *x, float *y, int *z, int tam) {
int i = threadIdx.x + blockIdx.x*blockDim.x; // 0 - 2047
int j = threadIdx.y + blockIdx.y*blockDim.y; // 0 - 2047
int index = j + i*tam; // 0 - 4194303
if( (x[index] * x[index] + y[index] * y[index]) <= 1.0f){
atomicAdd(z, 1);
}
} | .text
.file "aproximarPi.hip"
.globl _Z26__device_stub__aproximarPiPfS_Pii # -- Begin function _Z26__device_stub__aproximarPiPfS_Pii
.p2align 4, 0x90
.type _Z26__device_stub__aproximarPiPfS_Pii,@function
_Z26__device_stub__aproximarPiPfS_Pii: # @_Z26__device_stub__aproximarPiPfS_Pii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11aproximarPiPfS_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__aproximarPiPfS_Pii, .Lfunc_end0-_Z26__device_stub__aproximarPiPfS_Pii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11aproximarPiPfS_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11aproximarPiPfS_Pii,@object # @_Z11aproximarPiPfS_Pii
.section .rodata,"a",@progbits
.globl _Z11aproximarPiPfS_Pii
.p2align 3, 0x0
_Z11aproximarPiPfS_Pii:
.quad _Z26__device_stub__aproximarPiPfS_Pii
.size _Z11aproximarPiPfS_Pii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11aproximarPiPfS_Pii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__aproximarPiPfS_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11aproximarPiPfS_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11aproximarPiPfS_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fe200078e0205 */
/*0080*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fc600000001ff */
/*0090*/ IMAD R3, R0, c[0x0][0x178], R3 ; /* 0x00005e0000037a24 */
/* 0x000fce00078e0203 */
/*00a0*/ IMAD.WIDE R4, R3, R2, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0202 */
/*00b0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fe400078e0202 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee2000c1e1900 */
/*00e0*/ FMUL R7, R4, R4 ; /* 0x0000000404077220 */
/* 0x004fc80000400000 */
/*00f0*/ FFMA R7, R2, R2, R7 ; /* 0x0000000202077223 */
/* 0x008fca0000000007 */
/*0100*/ FSETP.GTU.AND P0, PT, R7, 1, PT ; /* 0x3f8000000700780b */
/* 0x000fda0003f0c000 */
/*0110*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0120*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0130*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe200038e0100 */
/*0140*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe20000000f00 */
/*0150*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0160*/ POPC R5, UR6 ; /* 0x0000000600057d09 */
/* 0x000e620008000000 */
/*0170*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fc80000000f00 */
/*0180*/ ISETP.EQ.U32.AND P0, PT, R0, UR7, PT ; /* 0x0000000700007c0c */
/* 0x001fda000bf02070 */
/*0190*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x002fe2000c10e184 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11aproximarPiPfS_Pii
.globl _Z11aproximarPiPfS_Pii
.p2align 8
.type _Z11aproximarPiPfS_Pii,@function
_Z11aproximarPiPfS_Pii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s4, v[1:2]
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s3
v_add3_u32 v0, s15, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v1, v2, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v1, v0, v0
v_cmpx_ge_f32_e32 1.0, v1
s_cbranch_execz .LBB0_3
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x10
s_bcnt1_i32_b32 s2, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11aproximarPiPfS_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11aproximarPiPfS_Pii, .Lfunc_end0-_Z11aproximarPiPfS_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11aproximarPiPfS_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11aproximarPiPfS_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001361b6_00000000-6_aproximarPi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11aproximarPiPfS_PiiPfS_Pii
.type _Z36__device_stub__Z11aproximarPiPfS_PiiPfS_Pii, @function
_Z36__device_stub__Z11aproximarPiPfS_PiiPfS_Pii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11aproximarPiPfS_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z11aproximarPiPfS_PiiPfS_Pii, .-_Z36__device_stub__Z11aproximarPiPfS_PiiPfS_Pii
.globl _Z11aproximarPiPfS_Pii
.type _Z11aproximarPiPfS_Pii, @function
_Z11aproximarPiPfS_Pii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11aproximarPiPfS_PiiPfS_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11aproximarPiPfS_Pii, .-_Z11aproximarPiPfS_Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11aproximarPiPfS_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11aproximarPiPfS_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "aproximarPi.hip"
.globl _Z26__device_stub__aproximarPiPfS_Pii # -- Begin function _Z26__device_stub__aproximarPiPfS_Pii
.p2align 4, 0x90
.type _Z26__device_stub__aproximarPiPfS_Pii,@function
_Z26__device_stub__aproximarPiPfS_Pii: # @_Z26__device_stub__aproximarPiPfS_Pii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11aproximarPiPfS_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__aproximarPiPfS_Pii, .Lfunc_end0-_Z26__device_stub__aproximarPiPfS_Pii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11aproximarPiPfS_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11aproximarPiPfS_Pii,@object # @_Z11aproximarPiPfS_Pii
.section .rodata,"a",@progbits
.globl _Z11aproximarPiPfS_Pii
.p2align 3, 0x0
_Z11aproximarPiPfS_Pii:
.quad _Z26__device_stub__aproximarPiPfS_Pii
.size _Z11aproximarPiPfS_Pii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11aproximarPiPfS_Pii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__aproximarPiPfS_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11aproximarPiPfS_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <bits/stdc++.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include <thrust/find.h>
#include <thrust/generate.h>
#include <thrust/transform.h>
#include <thrust/sequence.h>
#include <thrust/random.h>
#include <thrust/random/uniform_int_distribution.h>
#include <thrust/adjacent_difference.h>
#define REP(i,s,n) for(int (i)=s; (i)<(int)(n);(i)++)
#define RIT(it,c) for(__typeof(c.begin()) it = c.begin();it!=c.end();it++)
#define ALL(x) x.begin(), x.end()
#define SZ(x) (int)(x).size()
#define MSET(m,v) memset(m,v,sizeof(m))
using namespace std;
typedef vector<int> vi;
typedef vector<long> vl;
typedef vector<bool> vb;
typedef vector<double> vd;
typedef pair<int,int> ii;
typedef pair<long, long> ll;
typedef unordered_set<int> ui;
class SerialRunTime{
int N;
public:
SerialRunTime(int n):N(n){};
void seqRun(){
vector<int> Integers(N);
cout<<"\n==================================\n";
clock_t t_start = clock();
for(int i=0;i<N;++i) Integers[i] = i;
clock_t t_end = clock();
cout<<"Sequence Time Usage: "<<double(t_end-t_start)/CLOCKS_PER_SEC<<" s\nCheck Answer:"<<endl;
for(int i=0;i<10;++i) cout<<Integers[i]<<' ';
cout<<"\n==================================\n";
}
void genRun(){
int mod = 1E6;
vector<int> Integers(N);
cout<<"\n==================================\n";
clock_t t_start = clock();
generate(Integers.begin(), Integers.end(), [&mod](){return rand()%mod;});
clock_t t_end = clock();
cout<<"Random Number Generation Time Usage: "<<double(t_end-t_start)/CLOCKS_PER_SEC<<" s\nCheck Answer:"<<endl;
for(int i=0;i<10;++i) cout<<Integers[i]<<' ';
cout<<"\n==================================\n";
}
void unaryRun(){
int mod = 1E6;
vector<int> Integers(N),ans(N);
for(int i=0;i<N;++i) Integers[i] = i;
cout<<"\n==================================\n";
clock_t t_start = clock();
transform(Integers.begin(), Integers.end(), ans.begin(), [&mod](int x){return 2*x%mod;});
clock_t t_end = clock();
cout<<"Unary Operation transformation Time Usage: "<<double(t_end-t_start)/CLOCKS_PER_SEC<<" s\nCheck Answer:"<<endl;
for(int i=0;i<10;++i) cout<<ans[i]<<' ';
cout<<"\n==================================\n";
}
void binaryRun(){
vector<int> A(N),B(N),C(N);
for(int i=0;i<N;++i) A[i] = i,B[i] = 5;
cout<<"\n==================================\n";
clock_t t_start = clock();
transform(A.begin(), A.end(), B.begin(), C.begin(), modulus<int>());
clock_t t_end = clock();
cout<<"Binary Operation transformation Time Usage: "<<double(t_end-t_start)/CLOCKS_PER_SEC<<" s\nCheck Answer:"<<endl;
for(int i=0;i<10;++i) cout<<C[i]<<' ';
cout<<"\n==================================\n";
}
void diffRun(){
vector<int> A(N),B(N);
for(int i=0;i<N;++i) A[i] = i;
cout<<"\n==================================\n";
clock_t t_start = clock();
adjacent_difference(A.begin(), A.end(), B.begin());
clock_t t_end = clock();
cout<<"Adjacent difference Time Usage: "<<double(t_end-t_start)/CLOCKS_PER_SEC<<" s\nCheck Answer:"<<endl;
for(int i=0;i<10;++i) cout<<B[i]<<' ';
cout<<"\n==================================\n";
}
};
class SerialRunTimeTest{
SerialRunTime se;
public:
SerialRunTimeTest(int n):se(n){}
void run(){
se.seqRun();
se.genRun();
se.unaryRun();
se.binaryRun();
se.diffRun();
}
};
class ThrustRunTime{
int N;
public:
thrust::host_vector<int> A;
thrust::device_vector<int> dA;
struct getRand{
private:
thrust::uniform_int_distribution<int> g;
thrust::minstd_rand rng;
public:
getRand(int l, int u):g(l, u+1){}
__host__ __device__
int operator ()(){ return g(rng);}
};
struct Dop{
int M;
Dop(int m):M(m){}
__host__ __device__
int operator ()(int x){ return (2*x)%M;}
};
ThrustRunTime(int n):N(n){
A.resize(N);
dA.resize(N);
}
void seqRun(){
cout<<"\n==================================\n";
clock_t t_start = clock();
thrust::sequence(dA.begin(), dA.end());
clock_t t_end = clock();
cout<<"Sequence Time Usage: "<<double(t_end-t_start)/CLOCKS_PER_SEC<<" s\nCheck Answer:"<<endl;
thrust::copy(dA.begin(), dA.end(), A.begin());
for(int i=0;i<10;++i) cout<<A[i]<<' ';
cout<<"\n==================================\n";
}
void genRun(){
int mod = 1E6;
getRand g(0, mod);
thrust::device_vector<int> dB(N);
cout<<"\n==================================\n";
clock_t t_start = clock();
thrust::generate(dB.begin(), dB.end(), g);
clock_t t_end = clock();
cout<<"Random Number Generation Time Usage: "<<double(t_end-t_start)/CLOCKS_PER_SEC<<" s\nCheck Answer:"<<endl;
thrust::copy(dB.begin(), dB.end(), A.begin());
for(int i=0;i<N;i+=N/10) cout<<A[i]<<' ';
cout<<"\n==================================\n";
}
void unaryRun(){
int mod = 1E6;
Dop unary(mod);
thrust::device_vector<int> dB(N);
thrust::sequence(dB.begin(), dB.end());
cout<<"\n==================================\n";
clock_t t_start = clock();
thrust::transform(dB.begin(), dB.end(), dA.begin(), unary);
clock_t t_end = clock();
cout<<"Unary Operation transformation Time Usage: "<<double(t_end-t_start)/CLOCKS_PER_SEC<<" s\nCheck Answer:"<<endl;
thrust::copy(dA.begin(), dA.end(), A.begin());
for(int i=0;i<10;++i) cout<<A[i]<<' ';
cout<<"\n==================================\n";
}
void binaryRun(){
thrust::device_vector<int> dB(N),dC(N);
thrust::sequence(dB.begin(), dB.end());
thrust::fill(dC.begin(), dC.end(), 5);
cout<<"\n==================================\n";
clock_t t_start = clock();
thrust::transform(dB.begin(), dB.end(), dC.begin(), dA.begin(), thrust::modulus<int>());
clock_t t_end = clock();
cout<<"Binary Operation transformation Time Usage: "<<double(t_end-t_start)/CLOCKS_PER_SEC<<" s\nCheck Answer:"<<endl;
thrust::copy(dA.begin(), dA.end(), A.begin());
for(int i=0;i<10;++i) cout<<A[i]<<' ';
cout<<"\n==================================\n";
}
void diffRun(){
thrust::device_vector<int> dB(N);
thrust::sequence(dB.begin(), dB.end());
cout<<"\n==================================\n";
clock_t t_start = clock();
thrust::adjacent_difference(dB.begin(), dB.end(), dA.begin());
clock_t t_end = clock();
cout<<"Adjacent difference Time Usage: "<<double(t_end-t_start)/CLOCKS_PER_SEC<<" s\nCheck Answer:"<<endl;
thrust::copy(dA.begin(), dA.end(), A.begin());
for(int i=0;i<10;++i) cout<<A[i]<<' ';
cout<<"\n==================================\n";
}
};
class ThrustRunTimeTest{
ThrustRunTime se;
public:
ThrustRunTimeTest(int n):se(n){}
void run(){
se.seqRun();
se.genRun();
se.unaryRun();
se.binaryRun();
se.diffRun();
}
};
int main(int argc, char *argv[]){
std::ios_base::sync_with_stdio(false),cin.tie(0),cout.tie(0);
if(argc <= 1 || argv[1][0] == 'S') {
SerialRunTimeTest test(1<<28);
test.run();
}
else{
ThrustRunTimeTest test(1<<28);
test.run();
}
return 0;
} | #include <hip/hip_runtime.h>
#include <bits/stdc++.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include <thrust/find.h>
#include <thrust/generate.h>
#include <thrust/transform.h>
#include <thrust/sequence.h>
#include <thrust/random.h>
#include <thrust/random/uniform_int_distribution.h>
#include <thrust/adjacent_difference.h>
#define REP(i,s,n) for(int (i)=s; (i)<(int)(n);(i)++)
#define RIT(it,c) for(__typeof(c.begin()) it = c.begin();it!=c.end();it++)
#define ALL(x) x.begin(), x.end()
#define SZ(x) (int)(x).size()
#define MSET(m,v) memset(m,v,sizeof(m))
using namespace std;
typedef vector<int> vi;
typedef vector<long> vl;
typedef vector<bool> vb;
typedef vector<double> vd;
typedef pair<int,int> ii;
typedef pair<long, long> ll;
typedef unordered_set<int> ui;
class SerialRunTime{
int N;
public:
SerialRunTime(int n):N(n){};
void seqRun(){
vector<int> Integers(N);
cout<<"\n==================================\n";
clock_t t_start = clock();
for(int i=0;i<N;++i) Integers[i] = i;
clock_t t_end = clock();
cout<<"Sequence Time Usage: "<<double(t_end-t_start)/CLOCKS_PER_SEC<<" s\nCheck Answer:"<<endl;
for(int i=0;i<10;++i) cout<<Integers[i]<<' ';
cout<<"\n==================================\n";
}
void genRun(){
int mod = 1E6;
vector<int> Integers(N);
cout<<"\n==================================\n";
clock_t t_start = clock();
generate(Integers.begin(), Integers.end(), [&mod](){return rand()%mod;});
clock_t t_end = clock();
cout<<"Random Number Generation Time Usage: "<<double(t_end-t_start)/CLOCKS_PER_SEC<<" s\nCheck Answer:"<<endl;
for(int i=0;i<10;++i) cout<<Integers[i]<<' ';
cout<<"\n==================================\n";
}
void unaryRun(){
int mod = 1E6;
vector<int> Integers(N),ans(N);
for(int i=0;i<N;++i) Integers[i] = i;
cout<<"\n==================================\n";
clock_t t_start = clock();
transform(Integers.begin(), Integers.end(), ans.begin(), [&mod](int x){return 2*x%mod;});
clock_t t_end = clock();
cout<<"Unary Operation transformation Time Usage: "<<double(t_end-t_start)/CLOCKS_PER_SEC<<" s\nCheck Answer:"<<endl;
for(int i=0;i<10;++i) cout<<ans[i]<<' ';
cout<<"\n==================================\n";
}
void binaryRun(){
vector<int> A(N),B(N),C(N);
for(int i=0;i<N;++i) A[i] = i,B[i] = 5;
cout<<"\n==================================\n";
clock_t t_start = clock();
transform(A.begin(), A.end(), B.begin(), C.begin(), modulus<int>());
clock_t t_end = clock();
cout<<"Binary Operation transformation Time Usage: "<<double(t_end-t_start)/CLOCKS_PER_SEC<<" s\nCheck Answer:"<<endl;
for(int i=0;i<10;++i) cout<<C[i]<<' ';
cout<<"\n==================================\n";
}
void diffRun(){
vector<int> A(N),B(N);
for(int i=0;i<N;++i) A[i] = i;
cout<<"\n==================================\n";
clock_t t_start = clock();
adjacent_difference(A.begin(), A.end(), B.begin());
clock_t t_end = clock();
cout<<"Adjacent difference Time Usage: "<<double(t_end-t_start)/CLOCKS_PER_SEC<<" s\nCheck Answer:"<<endl;
for(int i=0;i<10;++i) cout<<B[i]<<' ';
cout<<"\n==================================\n";
}
};
class SerialRunTimeTest{
SerialRunTime se;
public:
SerialRunTimeTest(int n):se(n){}
void run(){
se.seqRun();
se.genRun();
se.unaryRun();
se.binaryRun();
se.diffRun();
}
};
class ThrustRunTime{
int N;
public:
thrust::host_vector<int> A;
thrust::device_vector<int> dA;
struct getRand{
private:
thrust::uniform_int_distribution<int> g;
thrust::minstd_rand rng;
public:
getRand(int l, int u):g(l, u+1){}
__host__ __device__
int operator ()(){ return g(rng);}
};
struct Dop{
int M;
Dop(int m):M(m){}
__host__ __device__
int operator ()(int x){ return (2*x)%M;}
};
ThrustRunTime(int n):N(n){
A.resize(N);
dA.resize(N);
}
void seqRun(){
cout<<"\n==================================\n";
clock_t t_start = clock();
thrust::sequence(dA.begin(), dA.end());
clock_t t_end = clock();
cout<<"Sequence Time Usage: "<<double(t_end-t_start)/CLOCKS_PER_SEC<<" s\nCheck Answer:"<<endl;
thrust::copy(dA.begin(), dA.end(), A.begin());
for(int i=0;i<10;++i) cout<<A[i]<<' ';
cout<<"\n==================================\n";
}
void genRun(){
int mod = 1E6;
getRand g(0, mod);
thrust::device_vector<int> dB(N);
cout<<"\n==================================\n";
clock_t t_start = clock();
thrust::generate(dB.begin(), dB.end(), g);
clock_t t_end = clock();
cout<<"Random Number Generation Time Usage: "<<double(t_end-t_start)/CLOCKS_PER_SEC<<" s\nCheck Answer:"<<endl;
thrust::copy(dB.begin(), dB.end(), A.begin());
for(int i=0;i<N;i+=N/10) cout<<A[i]<<' ';
cout<<"\n==================================\n";
}
void unaryRun(){
int mod = 1E6;
Dop unary(mod);
thrust::device_vector<int> dB(N);
thrust::sequence(dB.begin(), dB.end());
cout<<"\n==================================\n";
clock_t t_start = clock();
thrust::transform(dB.begin(), dB.end(), dA.begin(), unary);
clock_t t_end = clock();
cout<<"Unary Operation transformation Time Usage: "<<double(t_end-t_start)/CLOCKS_PER_SEC<<" s\nCheck Answer:"<<endl;
thrust::copy(dA.begin(), dA.end(), A.begin());
for(int i=0;i<10;++i) cout<<A[i]<<' ';
cout<<"\n==================================\n";
}
void binaryRun(){
thrust::device_vector<int> dB(N),dC(N);
thrust::sequence(dB.begin(), dB.end());
thrust::fill(dC.begin(), dC.end(), 5);
cout<<"\n==================================\n";
clock_t t_start = clock();
thrust::transform(dB.begin(), dB.end(), dC.begin(), dA.begin(), thrust::modulus<int>());
clock_t t_end = clock();
cout<<"Binary Operation transformation Time Usage: "<<double(t_end-t_start)/CLOCKS_PER_SEC<<" s\nCheck Answer:"<<endl;
thrust::copy(dA.begin(), dA.end(), A.begin());
for(int i=0;i<10;++i) cout<<A[i]<<' ';
cout<<"\n==================================\n";
}
void diffRun(){
thrust::device_vector<int> dB(N);
thrust::sequence(dB.begin(), dB.end());
cout<<"\n==================================\n";
clock_t t_start = clock();
thrust::adjacent_difference(dB.begin(), dB.end(), dA.begin());
clock_t t_end = clock();
cout<<"Adjacent difference Time Usage: "<<double(t_end-t_start)/CLOCKS_PER_SEC<<" s\nCheck Answer:"<<endl;
thrust::copy(dA.begin(), dA.end(), A.begin());
for(int i=0;i<10;++i) cout<<A[i]<<' ';
cout<<"\n==================================\n";
}
};
class ThrustRunTimeTest{
ThrustRunTime se;
public:
ThrustRunTimeTest(int n):se(n){}
void run(){
se.seqRun();
se.genRun();
se.unaryRun();
se.binaryRun();
se.diffRun();
}
};
int main(int argc, char *argv[]){
std::ios_base::sync_with_stdio(false),cin.tie(0),cout.tie(0);
if(argc <= 1 || argv[1][0] == 'S') {
SerialRunTimeTest test(1<<28);
test.run();
}
else{
ThrustRunTimeTest test(1<<28);
test.run();
}
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
using namespace std;
int print_cuda_version()
{
int count = 0;
if (cudaSuccess != cudaGetDeviceCount(&count)) {
return -1;
}
if (count == 0) {
return -1;
}
for (int device = 0; device < count; ++device) {
cudaDeviceProp prop;
if (cudaSuccess == cudaGetDeviceProperties(&prop, device)) {
std::cout << prop.major << "." << prop.minor << std::endl;
}
}
return 0;
}
int main(int argc, char ** argv)
{
return print_cuda_version();
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
using namespace std;
int print_cuda_version()
{
int count = 0;
if (cudaSuccess != cudaGetDeviceCount(&count)) {
return -1;
}
if (count == 0) {
return -1;
}
for (int device = 0; device < count; ++device) {
cudaDeviceProp prop;
if (cudaSuccess == cudaGetDeviceProperties(&prop, device)) {
std::cout << prop.major << "." << prop.minor << std::endl;
}
}
return 0;
}
int main(int argc, char ** argv)
{
return print_cuda_version();
} | .file "tmpxft_00180ffc_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "."
.text
.globl _Z18print_cuda_versionv
.type _Z18print_cuda_versionv, @function
_Z18print_cuda_versionv:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L12
movl 12(%rsp), %eax
testl %eax, %eax
je .L13
jle .L14
movl $0, %ebx
leaq 16(%rsp), %r12
leaq _ZSt4cout(%rip), %r14
leaq .LC0(%rip), %r13
jmp .L10
.L19:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L17
call _ZSt16__throw_bad_castv@PLT
.L17:
call __stack_chk_fail@PLT
.L8:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L9:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L5:
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L18
.L10:
movl %ebx, %esi
movq %r12, %rdi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L5
movl 376(%rsp), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 380(%rsp), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L19
cmpb $0, 56(%r15)
je .L8
movzbl 67(%r15), %esi
jmp .L9
.L18:
movl $0, %eax
.L3:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L20
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movl $-1, %eax
jmp .L3
.L13:
movl $-1, %eax
jmp .L3
.L14:
movl $0, %eax
jmp .L3
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z18print_cuda_versionv, .-_Z18print_cuda_versionv
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z18print_cuda_versionv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
using namespace std;
int print_cuda_version()
{
int count = 0;
if (cudaSuccess != cudaGetDeviceCount(&count)) {
return -1;
}
if (count == 0) {
return -1;
}
for (int device = 0; device < count; ++device) {
cudaDeviceProp prop;
if (cudaSuccess == cudaGetDeviceProperties(&prop, device)) {
std::cout << prop.major << "." << prop.minor << std::endl;
}
}
return 0;
}
int main(int argc, char ** argv)
{
return print_cuda_version();
} | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
int print_cuda_version()
{
int count = 0;
if (hipSuccess != hipGetDeviceCount(&count)) {
return -1;
}
if (count == 0) {
return -1;
}
for (int device = 0; device < count; ++device) {
hipDeviceProp_t prop;
if (hipSuccess == hipGetDeviceProperties(&prop, device)) {
std::cout << prop.major << "." << prop.minor << std::endl;
}
}
return 0;
}
int main(int argc, char ** argv)
{
return print_cuda_version();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
int print_cuda_version()
{
int count = 0;
if (hipSuccess != hipGetDeviceCount(&count)) {
return -1;
}
if (count == 0) {
return -1;
}
for (int device = 0; device < count; ++device) {
hipDeviceProp_t prop;
if (hipSuccess == hipGetDeviceProperties(&prop, device)) {
std::cout << prop.major << "." << prop.minor << std::endl;
}
}
return 0;
}
int main(int argc, char ** argv)
{
return print_cuda_version();
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
int print_cuda_version()
{
int count = 0;
if (hipSuccess != hipGetDeviceCount(&count)) {
return -1;
}
if (count == 0) {
return -1;
}
for (int device = 0; device < count; ++device) {
hipDeviceProp_t prop;
if (hipSuccess == hipGetDeviceProperties(&prop, device)) {
std::cout << prop.major << "." << prop.minor << std::endl;
}
}
return 0;
}
int main(int argc, char ** argv)
{
return print_cuda_version();
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18print_cuda_versionv # -- Begin function _Z18print_cuda_versionv
.p2align 4, 0x90
.type _Z18print_cuda_versionv,@function
_Z18print_cuda_versionv: # @_Z18print_cuda_versionv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl %eax, %ecx
movl $-1, %eax
testl %ecx, %ecx
jne .LBB0_12
# %bb.1:
cmpl $0, 4(%rsp)
je .LBB0_12
# %bb.2: # %.preheader
cmpl $0, 4(%rsp)
jle .LBB0_11
# %bb.3: # %.lr.ph
xorl %ebx, %ebx
leaq 8(%rsp), %r14
jmp .LBB0_4
.LBB0_8: # in Loop: Header=BB0_4 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB0_4 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB0_10: # in Loop: Header=BB0_4 Depth=1
incl %ebx
cmpl 4(%rsp), %ebx
jge .LBB0_11
.LBB0_4: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_10
# %bb.5: # in Loop: Header=BB0_4 Depth=1
movl 368(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 372(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_13
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB0_4 Depth=1
cmpb $0, 56(%r15)
je .LBB0_8
# %bb.7: # in Loop: Header=BB0_4 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_9
.LBB0_11:
xorl %eax, %eax
.LBB0_12: # %.loopexit
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_13:
.cfi_def_cfa_offset 1520
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size _Z18print_cuda_versionv, .Lfunc_end0-_Z18print_cuda_versionv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
jmp _Z18print_cuda_versionv # TAILCALL
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "."
.size .L.str, 2
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00180ffc_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "."
.text
.globl _Z18print_cuda_versionv
.type _Z18print_cuda_versionv, @function
_Z18print_cuda_versionv:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L12
movl 12(%rsp), %eax
testl %eax, %eax
je .L13
jle .L14
movl $0, %ebx
leaq 16(%rsp), %r12
leaq _ZSt4cout(%rip), %r14
leaq .LC0(%rip), %r13
jmp .L10
.L19:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L17
call _ZSt16__throw_bad_castv@PLT
.L17:
call __stack_chk_fail@PLT
.L8:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L9:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L5:
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L18
.L10:
movl %ebx, %esi
movq %r12, %rdi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L5
movl 376(%rsp), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 380(%rsp), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L19
cmpb $0, 56(%r15)
je .L8
movzbl 67(%r15), %esi
jmp .L9
.L18:
movl $0, %eax
.L3:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L20
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movl $-1, %eax
jmp .L3
.L13:
movl $-1, %eax
jmp .L3
.L14:
movl $0, %eax
jmp .L3
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z18print_cuda_versionv, .-_Z18print_cuda_versionv
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z18print_cuda_versionv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18print_cuda_versionv # -- Begin function _Z18print_cuda_versionv
.p2align 4, 0x90
.type _Z18print_cuda_versionv,@function
_Z18print_cuda_versionv: # @_Z18print_cuda_versionv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl %eax, %ecx
movl $-1, %eax
testl %ecx, %ecx
jne .LBB0_12
# %bb.1:
cmpl $0, 4(%rsp)
je .LBB0_12
# %bb.2: # %.preheader
cmpl $0, 4(%rsp)
jle .LBB0_11
# %bb.3: # %.lr.ph
xorl %ebx, %ebx
leaq 8(%rsp), %r14
jmp .LBB0_4
.LBB0_8: # in Loop: Header=BB0_4 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB0_4 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB0_10: # in Loop: Header=BB0_4 Depth=1
incl %ebx
cmpl 4(%rsp), %ebx
jge .LBB0_11
.LBB0_4: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_10
# %bb.5: # in Loop: Header=BB0_4 Depth=1
movl 368(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 372(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_13
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB0_4 Depth=1
cmpb $0, 56(%r15)
je .LBB0_8
# %bb.7: # in Loop: Header=BB0_4 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_9
.LBB0_11:
xorl %eax, %eax
.LBB0_12: # %.loopexit
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_13:
.cfi_def_cfa_offset 1520
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size _Z18print_cuda_versionv, .Lfunc_end0-_Z18print_cuda_versionv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
jmp _Z18print_cuda_versionv # TAILCALL
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "."
.size .L.str, 2
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void square_array(float *a, int array_size)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<array_size) a[idx] = a[idx] * a[idx];
} | code for sm_80
Function : _Z12square_arrayPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FMUL R5, R0, R0 ; /* 0x0000000000057220 */
/* 0x004fca0000400000 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void square_array(float *a, int array_size)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<array_size) a[idx] = a[idx] * a[idx];
} | .file "tmpxft_00067aa4_00000000-6_square_array.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z12square_arrayPfiPfi
.type _Z33__device_stub__Z12square_arrayPfiPfi, @function
_Z33__device_stub__Z12square_arrayPfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12square_arrayPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z12square_arrayPfiPfi, .-_Z33__device_stub__Z12square_arrayPfiPfi
.globl _Z12square_arrayPfi
.type _Z12square_arrayPfi, @function
_Z12square_arrayPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12square_arrayPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12square_arrayPfi, .-_Z12square_arrayPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12square_arrayPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12square_arrayPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void square_array(float *a, int array_size)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<array_size) a[idx] = a[idx] * a[idx];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void square_array(float *a, int array_size)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<array_size) a[idx] = a[idx] * a[idx];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void square_array(float *a, int array_size)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<array_size) a[idx] = a[idx] * a[idx];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12square_arrayPfi
.globl _Z12square_arrayPfi
.p2align 8
.type _Z12square_arrayPfi,@function
_Z12square_arrayPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12square_arrayPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12square_arrayPfi, .Lfunc_end0-_Z12square_arrayPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12square_arrayPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12square_arrayPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void square_array(float *a, int array_size)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<array_size) a[idx] = a[idx] * a[idx];
} | .text
.file "square_array.hip"
.globl _Z27__device_stub__square_arrayPfi # -- Begin function _Z27__device_stub__square_arrayPfi
.p2align 4, 0x90
.type _Z27__device_stub__square_arrayPfi,@function
_Z27__device_stub__square_arrayPfi: # @_Z27__device_stub__square_arrayPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12square_arrayPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__square_arrayPfi, .Lfunc_end0-_Z27__device_stub__square_arrayPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12square_arrayPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12square_arrayPfi,@object # @_Z12square_arrayPfi
.section .rodata,"a",@progbits
.globl _Z12square_arrayPfi
.p2align 3, 0x0
_Z12square_arrayPfi:
.quad _Z27__device_stub__square_arrayPfi
.size _Z12square_arrayPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12square_arrayPfi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__square_arrayPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12square_arrayPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12square_arrayPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FMUL R5, R0, R0 ; /* 0x0000000000057220 */
/* 0x004fca0000400000 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12square_arrayPfi
.globl _Z12square_arrayPfi
.p2align 8
.type _Z12square_arrayPfi,@function
_Z12square_arrayPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12square_arrayPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12square_arrayPfi, .Lfunc_end0-_Z12square_arrayPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12square_arrayPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12square_arrayPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00067aa4_00000000-6_square_array.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z12square_arrayPfiPfi
.type _Z33__device_stub__Z12square_arrayPfiPfi, @function
_Z33__device_stub__Z12square_arrayPfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12square_arrayPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z12square_arrayPfiPfi, .-_Z33__device_stub__Z12square_arrayPfiPfi
.globl _Z12square_arrayPfi
.type _Z12square_arrayPfi, @function
_Z12square_arrayPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12square_arrayPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12square_arrayPfi, .-_Z12square_arrayPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12square_arrayPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12square_arrayPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "square_array.hip"
.globl _Z27__device_stub__square_arrayPfi # -- Begin function _Z27__device_stub__square_arrayPfi
.p2align 4, 0x90
.type _Z27__device_stub__square_arrayPfi,@function
_Z27__device_stub__square_arrayPfi: # @_Z27__device_stub__square_arrayPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12square_arrayPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__square_arrayPfi, .Lfunc_end0-_Z27__device_stub__square_arrayPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12square_arrayPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12square_arrayPfi,@object # @_Z12square_arrayPfi
.section .rodata,"a",@progbits
.globl _Z12square_arrayPfi
.p2align 3, 0x0
_Z12square_arrayPfi:
.quad _Z27__device_stub__square_arrayPfi
.size _Z12square_arrayPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12square_arrayPfi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__square_arrayPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12square_arrayPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* CUDA exercise to convert a simple serial code for a brute force
largest prime number search into CUDA (32-bit, int version). This
initial code is serial, but it is written as CUDA code for your
convenience, so should be compiled with nvcc (see below). Your task
is to convert the serial computation to a kernel computation. In
the simplest case, use atomicMax to find the globally largest prime
number.
All prime numbers can be expressed as 6*k-1 or 6*k+1, k being an
integer. We provide the range of k to probe as macro parameters
KMIN and KMAX (see below).
You should get a speedup ~20x with atomicMax.
Hints:
* It's very convenient to use a two-dimensional grid of blocks,
defined as "dim3 Nblocks (NBLOCKS, 2, 1);". The second grid
dimension is used to derive the two values of j=(-1; 1) inside the
kernel: "int j = 2*blockIdx.y - 1;". This way, there will be only
one loop inside the kernel - for y.
* When you get a failure (not a prime) inside the y loop, you can exit
the thread with "return" (no need to use "break").
To compile:
nvcc -arch=sm_20 -O2 primes.cu -o primes
*/
#include <sys/time.h>
#include <ctype.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <unistd.h>
// Range of k-numbers for primes search:
#define KMIN 100000000
// Should be smaller than 357,913,941 (because we are using signed int)
#define KMAX 100100000
// Number of threads in one block (possible range is 32...1024):
#define BLOCK_SIZE 256
// Number of blocks to run:
#define NBLOCKS (KMAX-KMIN+BLOCK_SIZE)/BLOCK_SIZE
/* Subtract the `struct timeval' values X and Y,
storing the result in RESULT.
Return 1 if the difference is negative, otherwise 0. */
// It messes up with y!
int
timeval_subtract (double *result, struct timeval *x, struct timeval *y)
{
struct timeval result0;
/* Perform the carry for the later subtraction by updating y. */
if (x->tv_usec < y->tv_usec) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000 + 1;
y->tv_usec -= 1000000 * nsec;
y->tv_sec += nsec;
}
if (x->tv_usec - y->tv_usec > 1000000) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000;
y->tv_usec += 1000000 * nsec;
y->tv_sec -= nsec;
}
/* Compute the time remaining to wait.
tv_usec is certainly positive. */
result0.tv_sec = x->tv_sec - y->tv_sec;
result0.tv_usec = x->tv_usec - y->tv_usec;
*result = ((double)result0.tv_usec)/1e6 + (double)result0.tv_sec;
/* Return 1 if result is negative. */
return x->tv_sec < y->tv_sec;
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Kernel(s) should go here:
int main (int argc,char **argv)
{
struct timeval tdr0, tdr1, tdr;
double restime;
int devid, devcount, error, success;
int xmax, ymax, x, y;
if (BLOCK_SIZE>1024)
{
printf ("Bad BLOCK_SIZE: %d\n", BLOCK_SIZE);
exit (1);
}
/* find number of device in current "context" */
cudaGetDevice(&devid);
/* find how many devices are available */
if (cudaGetDeviceCount(&devcount) || devcount==0)
{
printf ("No CUDA devices!\n");
exit (1);
}
else
{
cudaDeviceProp deviceProp;
cudaGetDeviceProperties (&deviceProp, devid);
printf ("Device count, devid: %d %d\n", devcount, devid);
printf ("Device: %s\n", deviceProp.name);
printf("[deviceProp.major.deviceProp.minor] = [%d.%d]\n\n", deviceProp.major, deviceProp.minor);
}
//--------------------------------------------------------------------------------
if (error = cudaDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr0, NULL);
// This serial computation will have to be replaced by calls to kernel(s):
xmax = 0;
for (int k=KMIN; k<=KMAX; k++)
{
// testing "-1" and "+1" cases:
for (int j=-1; j<2; j=j+2)
{
// Prime candidate:
x = 6*k + j;
// We should be dividing by numbers up to sqrt(x):
ymax = (int)ceil(sqrt((double)x));
// Primality test:
for (y=3; y<=ymax; y=y+2)
{
// Tpo be a success, the modulus should not be equal to zero:
success = x % y;
if (!success)
break;
}
if (success && x > xmax)
{
xmax = x;
}
}
}
if (error = cudaDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr1, NULL);
tdr = tdr0;
timeval_subtract (&restime, &tdr1, &tdr);
printf ("%d\n", xmax);
printf ("Time: %e\n", restime);
//--------------------------------------------------------------------------------
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* CUDA exercise to convert a simple serial code for a brute force
largest prime number search into CUDA (32-bit, int version). This
initial code is serial, but it is written as CUDA code for your
convenience, so should be compiled with nvcc (see below). Your task
is to convert the serial computation to a kernel computation. In
the simplest case, use atomicMax to find the globally largest prime
number.
All prime numbers can be expressed as 6*k-1 or 6*k+1, k being an
integer. We provide the range of k to probe as macro parameters
KMIN and KMAX (see below).
You should get a speedup ~20x with atomicMax.
Hints:
* It's very convenient to use a two-dimensional grid of blocks,
defined as "dim3 Nblocks (NBLOCKS, 2, 1);". The second grid
dimension is used to derive the two values of j=(-1; 1) inside the
kernel: "int j = 2*blockIdx.y - 1;". This way, there will be only
one loop inside the kernel - for y.
* When you get a failure (not a prime) inside the y loop, you can exit
the thread with "return" (no need to use "break").
To compile:
nvcc -arch=sm_20 -O2 primes.cu -o primes
*/
#include <sys/time.h>
#include <ctype.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <unistd.h>
// Range of k-numbers for primes search:
#define KMIN 100000000
// Should be smaller than 357,913,941 (because we are using signed int)
#define KMAX 100100000
// Number of threads in one block (possible range is 32...1024):
#define BLOCK_SIZE 256
// Number of blocks to run:
#define NBLOCKS (KMAX-KMIN+BLOCK_SIZE)/BLOCK_SIZE
/* Subtract the `struct timeval' values X and Y,
storing the result in RESULT.
Return 1 if the difference is negative, otherwise 0. */
// It messes up with y!
int
timeval_subtract (double *result, struct timeval *x, struct timeval *y)
{
struct timeval result0;
/* Perform the carry for the later subtraction by updating y. */
if (x->tv_usec < y->tv_usec) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000 + 1;
y->tv_usec -= 1000000 * nsec;
y->tv_sec += nsec;
}
if (x->tv_usec - y->tv_usec > 1000000) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000;
y->tv_usec += 1000000 * nsec;
y->tv_sec -= nsec;
}
/* Compute the time remaining to wait.
tv_usec is certainly positive. */
result0.tv_sec = x->tv_sec - y->tv_sec;
result0.tv_usec = x->tv_usec - y->tv_usec;
*result = ((double)result0.tv_usec)/1e6 + (double)result0.tv_sec;
/* Return 1 if result is negative. */
return x->tv_sec < y->tv_sec;
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Kernel(s) should go here:
int main (int argc,char **argv)
{
struct timeval tdr0, tdr1, tdr;
double restime;
int devid, devcount, error, success;
int xmax, ymax, x, y;
if (BLOCK_SIZE>1024)
{
printf ("Bad BLOCK_SIZE: %d\n", BLOCK_SIZE);
exit (1);
}
/* find number of device in current "context" */
cudaGetDevice(&devid);
/* find how many devices are available */
if (cudaGetDeviceCount(&devcount) || devcount==0)
{
printf ("No CUDA devices!\n");
exit (1);
}
else
{
cudaDeviceProp deviceProp;
cudaGetDeviceProperties (&deviceProp, devid);
printf ("Device count, devid: %d %d\n", devcount, devid);
printf ("Device: %s\n", deviceProp.name);
printf("[deviceProp.major.deviceProp.minor] = [%d.%d]\n\n", deviceProp.major, deviceProp.minor);
}
//--------------------------------------------------------------------------------
if (error = cudaDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr0, NULL);
// This serial computation will have to be replaced by calls to kernel(s):
xmax = 0;
for (int k=KMIN; k<=KMAX; k++)
{
// testing "-1" and "+1" cases:
for (int j=-1; j<2; j=j+2)
{
// Prime candidate:
x = 6*k + j;
// We should be dividing by numbers up to sqrt(x):
ymax = (int)ceil(sqrt((double)x));
// Primality test:
for (y=3; y<=ymax; y=y+2)
{
// Tpo be a success, the modulus should not be equal to zero:
success = x % y;
if (!success)
break;
}
if (success && x > xmax)
{
xmax = x;
}
}
}
if (error = cudaDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr1, NULL);
tdr = tdr0;
timeval_subtract (&restime, &tdr1, &tdr);
printf ("%d\n", xmax);
printf ("Time: %e\n", restime);
//--------------------------------------------------------------------------------
return 0;
} | .file "tmpxft_00155f2b_00000000-6_primes.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16timeval_subtractPdP7timevalS1_
.type _Z16timeval_subtractPdP7timevalS1_, @function
_Z16timeval_subtractPdP7timevalS1_:
.LFB2070:
.cfi_startproc
endbr64
movq %rdx, %rcx
movq 8(%rsi), %rax
movq 8(%rdx), %r8
cmpq %r8, %rax
jge .L4
movq %r8, %r9
subq %rax, %r9
movabsq $4835703278458516699, %rdx
movq %r9, %rax
imulq %rdx
sarq $18, %rdx
sarq $63, %r9
subq %r9, %rdx
addl $1, %edx
imull $1000000, %edx, %eax
cltq
subq %rax, %r8
movq %r8, 8(%rcx)
movslq %edx, %rdx
addq %rdx, (%rcx)
.L4:
movq 8(%rsi), %rax
movq 8(%rcx), %r8
movq %rax, %rdx
subq %r8, %rdx
cmpq $1000000, %rdx
jle .L5
movq %r8, %r9
subq %rax, %r9
movabsq $4835703278458516699, %rdx
movq %r9, %rax
imulq %rdx
sarq $18, %rdx
sarq $63, %r9
subq %r9, %rdx
imull $1000000, %edx, %eax
cltq
addq %r8, %rax
movq %rax, 8(%rcx)
movslq %edx, %rdx
subq %rdx, (%rcx)
.L5:
movq 8(%rsi), %rax
subq 8(%rcx), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq (%rsi), %rax
subq (%rcx), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, (%rdi)
movq (%rcx), %rax
cmpq %rax, (%rsi)
setl %al
movzbl %al, %eax
ret
.cfi_endproc
.LFE2070:
.size _Z16timeval_subtractPdP7timevalS1_, .-_Z16timeval_subtractPdP7timevalS1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Device count, devid: %d %d\n"
.LC2:
.string "Device: %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "[deviceProp.major.deviceProp.minor] = [%d.%d]\n\n"
.section .rodata.str1.1
.LC4:
.string "No CUDA devices!\n"
.LC5:
.string "Error %d\n"
.LC10:
.string "%d\n"
.LC11:
.string "Time: %e\n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1112, %rsp
.cfi_def_cfa_offset 1168
movq %fs:40, %rax
movq %rax, 1096(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call cudaGetDevice@PLT
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L7
cmpl $0, 4(%rsp)
je .L7
leaq 64(%rsp), %rbx
movl (%rsp), %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movl (%rsp), %ecx
movl 4(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 428(%rsp), %ecx
movl 424(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L30
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $600000003, %r13d
jmp .L10
.L7:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
movl %eax, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %edi
call exit@PLT
.L28:
call sqrt@PLT
jmp .L13
.L15:
testl %ebp, %ebp
je .L16
cmpl %r14d, %ebx
cmovge %ebx, %r14d
.L16:
addl $2, %r12d
cmpl %r13d, %r12d
je .L31
.L20:
movl %r12d, %ebx
pxor %xmm0, %xmm0
cvtsi2sdl %r12d, %xmm0
movq %r15, %xmm3
ucomisd %xmm0, %xmm3
ja .L28
sqrtsd %xmm0, %xmm0
.L13:
movapd %xmm0, %xmm2
movsd .LC12(%rip), %xmm1
andpd %xmm0, %xmm1
movsd .LC7(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L14
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm2
movsd .LC9(%rip), %xmm5
andpd %xmm5, %xmm2
addsd %xmm2, %xmm1
movsd .LC12(%rip), %xmm2
andnpd %xmm0, %xmm2
orpd %xmm1, %xmm2
.L14:
cvttsd2sil %xmm2, %esi
cmpl $2, %esi
jle .L15
movslq %ebx, %rbp
imulq $1431655766, %rbp, %rbp
shrq $32, %rbp
movl %ebx, %eax
sarl $31, %eax
subl %eax, %ebp
leal 0(%rbp,%rbp,2), %eax
movl %ebx, %ebp
subl %eax, %ebp
je .L16
movl $3, %ecx
.L17:
addl $2, %ecx
cmpl %ecx, %esi
jl .L15
movl %ebx, %eax
cltd
idivl %ecx
movl %edx, %ebp
testl %edx, %edx
jne .L17
jmp .L16
.L31:
addl $6, %r13d
cmpl $600600009, %r13d
je .L21
.L10:
leal -4(%r13), %r12d
movl $0x000000000, %r15d
jmp .L20
.L21:
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L32
leaq 32(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call gettimeofday@PLT
movdqa 16(%rsp), %xmm6
movaps %xmm6, 48(%rsp)
leaq 48(%rsp), %rdx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call _Z16timeval_subtractPdP7timevalS1_
movl %r14d, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $1112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl %eax, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.align 8
.LC7:
.long 0
.long 1127219200
.align 8
.LC9:
.long 0
.long 1072693248
.align 8
.LC12:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* CUDA exercise to convert a simple serial code for a brute force
largest prime number search into CUDA (32-bit, int version). This
initial code is serial, but it is written as CUDA code for your
convenience, so should be compiled with nvcc (see below). Your task
is to convert the serial computation to a kernel computation. In
the simplest case, use atomicMax to find the globally largest prime
number.
All prime numbers can be expressed as 6*k-1 or 6*k+1, k being an
integer. We provide the range of k to probe as macro parameters
KMIN and KMAX (see below).
You should get a speedup ~20x with atomicMax.
Hints:
* It's very convenient to use a two-dimensional grid of blocks,
defined as "dim3 Nblocks (NBLOCKS, 2, 1);". The second grid
dimension is used to derive the two values of j=(-1; 1) inside the
kernel: "int j = 2*blockIdx.y - 1;". This way, there will be only
one loop inside the kernel - for y.
* When you get a failure (not a prime) inside the y loop, you can exit
the thread with "return" (no need to use "break").
To compile:
nvcc -arch=sm_20 -O2 primes.cu -o primes
*/
#include <sys/time.h>
#include <ctype.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <unistd.h>
// Range of k-numbers for primes search:
#define KMIN 100000000
// Should be smaller than 357,913,941 (because we are using signed int)
#define KMAX 100100000
// Number of threads in one block (possible range is 32...1024):
#define BLOCK_SIZE 256
// Number of blocks to run:
#define NBLOCKS (KMAX-KMIN+BLOCK_SIZE)/BLOCK_SIZE
/* Subtract the `struct timeval' values X and Y,
storing the result in RESULT.
Return 1 if the difference is negative, otherwise 0. */
// It messes up with y!
int
timeval_subtract (double *result, struct timeval *x, struct timeval *y)
{
struct timeval result0;
/* Perform the carry for the later subtraction by updating y. */
if (x->tv_usec < y->tv_usec) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000 + 1;
y->tv_usec -= 1000000 * nsec;
y->tv_sec += nsec;
}
if (x->tv_usec - y->tv_usec > 1000000) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000;
y->tv_usec += 1000000 * nsec;
y->tv_sec -= nsec;
}
/* Compute the time remaining to wait.
tv_usec is certainly positive. */
result0.tv_sec = x->tv_sec - y->tv_sec;
result0.tv_usec = x->tv_usec - y->tv_usec;
*result = ((double)result0.tv_usec)/1e6 + (double)result0.tv_sec;
/* Return 1 if result is negative. */
return x->tv_sec < y->tv_sec;
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Kernel(s) should go here:
int main (int argc,char **argv)
{
struct timeval tdr0, tdr1, tdr;
double restime;
int devid, devcount, error, success;
int xmax, ymax, x, y;
if (BLOCK_SIZE>1024)
{
printf ("Bad BLOCK_SIZE: %d\n", BLOCK_SIZE);
exit (1);
}
/* find number of device in current "context" */
cudaGetDevice(&devid);
/* find how many devices are available */
if (cudaGetDeviceCount(&devcount) || devcount==0)
{
printf ("No CUDA devices!\n");
exit (1);
}
else
{
cudaDeviceProp deviceProp;
cudaGetDeviceProperties (&deviceProp, devid);
printf ("Device count, devid: %d %d\n", devcount, devid);
printf ("Device: %s\n", deviceProp.name);
printf("[deviceProp.major.deviceProp.minor] = [%d.%d]\n\n", deviceProp.major, deviceProp.minor);
}
//--------------------------------------------------------------------------------
if (error = cudaDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr0, NULL);
// This serial computation will have to be replaced by calls to kernel(s):
xmax = 0;
for (int k=KMIN; k<=KMAX; k++)
{
// testing "-1" and "+1" cases:
for (int j=-1; j<2; j=j+2)
{
// Prime candidate:
x = 6*k + j;
// We should be dividing by numbers up to sqrt(x):
ymax = (int)ceil(sqrt((double)x));
// Primality test:
for (y=3; y<=ymax; y=y+2)
{
// Tpo be a success, the modulus should not be equal to zero:
success = x % y;
if (!success)
break;
}
if (success && x > xmax)
{
xmax = x;
}
}
}
if (error = cudaDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr1, NULL);
tdr = tdr0;
timeval_subtract (&restime, &tdr1, &tdr);
printf ("%d\n", xmax);
printf ("Time: %e\n", restime);
//--------------------------------------------------------------------------------
return 0;
} | /* CUDA exercise to convert a simple serial code for a brute force
largest prime number search into CUDA (32-bit, int version). This
initial code is serial, but it is written as CUDA code for your
convenience, so should be compiled with nvcc (see below). Your task
is to convert the serial computation to a kernel computation. In
the simplest case, use atomicMax to find the globally largest prime
number.
All prime numbers can be expressed as 6*k-1 or 6*k+1, k being an
integer. We provide the range of k to probe as macro parameters
KMIN and KMAX (see below).
You should get a speedup ~20x with atomicMax.
Hints:
* It's very convenient to use a two-dimensional grid of blocks,
defined as "dim3 Nblocks (NBLOCKS, 2, 1);". The second grid
dimension is used to derive the two values of j=(-1; 1) inside the
kernel: "int j = 2*blockIdx.y - 1;". This way, there will be only
one loop inside the kernel - for y.
* When you get a failure (not a prime) inside the y loop, you can exit
the thread with "return" (no need to use "break").
To compile:
nvcc -arch=sm_20 -O2 primes.cu -o primes
*/
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include <ctype.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <unistd.h>
// Range of k-numbers for primes search:
#define KMIN 100000000
// Should be smaller than 357,913,941 (because we are using signed int)
#define KMAX 100100000
// Number of threads in one block (possible range is 32...1024):
#define BLOCK_SIZE 256
// Number of blocks to run:
#define NBLOCKS (KMAX-KMIN+BLOCK_SIZE)/BLOCK_SIZE
/* Subtract the `struct timeval' values X and Y,
storing the result in RESULT.
Return 1 if the difference is negative, otherwise 0. */
// It messes up with y!
int
timeval_subtract (double *result, struct timeval *x, struct timeval *y)
{
struct timeval result0;
/* Perform the carry for the later subtraction by updating y. */
if (x->tv_usec < y->tv_usec) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000 + 1;
y->tv_usec -= 1000000 * nsec;
y->tv_sec += nsec;
}
if (x->tv_usec - y->tv_usec > 1000000) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000;
y->tv_usec += 1000000 * nsec;
y->tv_sec -= nsec;
}
/* Compute the time remaining to wait.
tv_usec is certainly positive. */
result0.tv_sec = x->tv_sec - y->tv_sec;
result0.tv_usec = x->tv_usec - y->tv_usec;
*result = ((double)result0.tv_usec)/1e6 + (double)result0.tv_sec;
/* Return 1 if result is negative. */
return x->tv_sec < y->tv_sec;
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Kernel(s) should go here:
int main (int argc,char **argv)
{
struct timeval tdr0, tdr1, tdr;
double restime;
int devid, devcount, error, success;
int xmax, ymax, x, y;
if (BLOCK_SIZE>1024)
{
printf ("Bad BLOCK_SIZE: %d\n", BLOCK_SIZE);
exit (1);
}
/* find number of device in current "context" */
hipGetDevice(&devid);
/* find how many devices are available */
if (hipGetDeviceCount(&devcount) || devcount==0)
{
printf ("No CUDA devices!\n");
exit (1);
}
else
{
hipDeviceProp_t deviceProp;
hipGetDeviceProperties (&deviceProp, devid);
printf ("Device count, devid: %d %d\n", devcount, devid);
printf ("Device: %s\n", deviceProp.name);
printf("[deviceProp.major.deviceProp.minor] = [%d.%d]\n\n", deviceProp.major, deviceProp.minor);
}
//--------------------------------------------------------------------------------
if (error = hipDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr0, NULL);
// This serial computation will have to be replaced by calls to kernel(s):
xmax = 0;
for (int k=KMIN; k<=KMAX; k++)
{
// testing "-1" and "+1" cases:
for (int j=-1; j<2; j=j+2)
{
// Prime candidate:
x = 6*k + j;
// We should be dividing by numbers up to sqrt(x):
ymax = (int)ceil(sqrt((double)x));
// Primality test:
for (y=3; y<=ymax; y=y+2)
{
// Tpo be a success, the modulus should not be equal to zero:
success = x % y;
if (!success)
break;
}
if (success && x > xmax)
{
xmax = x;
}
}
}
if (error = hipDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr1, NULL);
tdr = tdr0;
timeval_subtract (&restime, &tdr1, &tdr);
printf ("%d\n", xmax);
printf ("Time: %e\n", restime);
//--------------------------------------------------------------------------------
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* CUDA exercise to convert a simple serial code for a brute force
largest prime number search into CUDA (32-bit, int version). This
initial code is serial, but it is written as CUDA code for your
convenience, so should be compiled with nvcc (see below). Your task
is to convert the serial computation to a kernel computation. In
the simplest case, use atomicMax to find the globally largest prime
number.
All prime numbers can be expressed as 6*k-1 or 6*k+1, k being an
integer. We provide the range of k to probe as macro parameters
KMIN and KMAX (see below).
You should get a speedup ~20x with atomicMax.
Hints:
* It's very convenient to use a two-dimensional grid of blocks,
defined as "dim3 Nblocks (NBLOCKS, 2, 1);". The second grid
dimension is used to derive the two values of j=(-1; 1) inside the
kernel: "int j = 2*blockIdx.y - 1;". This way, there will be only
one loop inside the kernel - for y.
* When you get a failure (not a prime) inside the y loop, you can exit
the thread with "return" (no need to use "break").
To compile:
nvcc -arch=sm_20 -O2 primes.cu -o primes
*/
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include <ctype.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <unistd.h>
// Range of k-numbers for primes search:
#define KMIN 100000000
// Should be smaller than 357,913,941 (because we are using signed int)
#define KMAX 100100000
// Number of threads in one block (possible range is 32...1024):
#define BLOCK_SIZE 256
// Number of blocks to run:
#define NBLOCKS (KMAX-KMIN+BLOCK_SIZE)/BLOCK_SIZE
/* Subtract the `struct timeval' values X and Y,
storing the result in RESULT.
Return 1 if the difference is negative, otherwise 0. */
// It messes up with y!
int
timeval_subtract (double *result, struct timeval *x, struct timeval *y)
{
struct timeval result0;
/* Perform the carry for the later subtraction by updating y. */
if (x->tv_usec < y->tv_usec) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000 + 1;
y->tv_usec -= 1000000 * nsec;
y->tv_sec += nsec;
}
if (x->tv_usec - y->tv_usec > 1000000) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000;
y->tv_usec += 1000000 * nsec;
y->tv_sec -= nsec;
}
/* Compute the time remaining to wait.
tv_usec is certainly positive. */
result0.tv_sec = x->tv_sec - y->tv_sec;
result0.tv_usec = x->tv_usec - y->tv_usec;
*result = ((double)result0.tv_usec)/1e6 + (double)result0.tv_sec;
/* Return 1 if result is negative. */
return x->tv_sec < y->tv_sec;
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Kernel(s) should go here:
int main (int argc,char **argv)
{
struct timeval tdr0, tdr1, tdr;
double restime;
int devid, devcount, error, success;
int xmax, ymax, x, y;
if (BLOCK_SIZE>1024)
{
printf ("Bad BLOCK_SIZE: %d\n", BLOCK_SIZE);
exit (1);
}
/* find number of device in current "context" */
hipGetDevice(&devid);
/* find how many devices are available */
if (hipGetDeviceCount(&devcount) || devcount==0)
{
printf ("No CUDA devices!\n");
exit (1);
}
else
{
hipDeviceProp_t deviceProp;
hipGetDeviceProperties (&deviceProp, devid);
printf ("Device count, devid: %d %d\n", devcount, devid);
printf ("Device: %s\n", deviceProp.name);
printf("[deviceProp.major.deviceProp.minor] = [%d.%d]\n\n", deviceProp.major, deviceProp.minor);
}
//--------------------------------------------------------------------------------
if (error = hipDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr0, NULL);
// This serial computation will have to be replaced by calls to kernel(s):
xmax = 0;
for (int k=KMIN; k<=KMAX; k++)
{
// testing "-1" and "+1" cases:
for (int j=-1; j<2; j=j+2)
{
// Prime candidate:
x = 6*k + j;
// We should be dividing by numbers up to sqrt(x):
ymax = (int)ceil(sqrt((double)x));
// Primality test:
for (y=3; y<=ymax; y=y+2)
{
// Tpo be a success, the modulus should not be equal to zero:
success = x % y;
if (!success)
break;
}
if (success && x > xmax)
{
xmax = x;
}
}
}
if (error = hipDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr1, NULL);
tdr = tdr0;
timeval_subtract (&restime, &tdr1, &tdr);
printf ("%d\n", xmax);
printf ("Time: %e\n", restime);
//--------------------------------------------------------------------------------
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* CUDA exercise to convert a simple serial code for a brute force
largest prime number search into CUDA (32-bit, int version). This
initial code is serial, but it is written as CUDA code for your
convenience, so should be compiled with nvcc (see below). Your task
is to convert the serial computation to a kernel computation. In
the simplest case, use atomicMax to find the globally largest prime
number.
All prime numbers can be expressed as 6*k-1 or 6*k+1, k being an
integer. We provide the range of k to probe as macro parameters
KMIN and KMAX (see below).
You should get a speedup ~20x with atomicMax.
Hints:
* It's very convenient to use a two-dimensional grid of blocks,
defined as "dim3 Nblocks (NBLOCKS, 2, 1);". The second grid
dimension is used to derive the two values of j=(-1; 1) inside the
kernel: "int j = 2*blockIdx.y - 1;". This way, there will be only
one loop inside the kernel - for y.
* When you get a failure (not a prime) inside the y loop, you can exit
the thread with "return" (no need to use "break").
To compile:
nvcc -arch=sm_20 -O2 primes.cu -o primes
*/
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include <ctype.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <unistd.h>
// Range of k-numbers for primes search:
#define KMIN 100000000
// Should be smaller than 357,913,941 (because we are using signed int)
#define KMAX 100100000
// Number of threads in one block (possible range is 32...1024):
#define BLOCK_SIZE 256
// Number of blocks to run:
#define NBLOCKS (KMAX-KMIN+BLOCK_SIZE)/BLOCK_SIZE
/* Subtract the `struct timeval' values X and Y,
storing the result in RESULT.
Return 1 if the difference is negative, otherwise 0. */
// It messes up with y!
int
timeval_subtract (double *result, struct timeval *x, struct timeval *y)
{
struct timeval result0;
/* Perform the carry for the later subtraction by updating y. */
if (x->tv_usec < y->tv_usec) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000 + 1;
y->tv_usec -= 1000000 * nsec;
y->tv_sec += nsec;
}
if (x->tv_usec - y->tv_usec > 1000000) {
int nsec = (y->tv_usec - x->tv_usec) / 1000000;
y->tv_usec += 1000000 * nsec;
y->tv_sec -= nsec;
}
/* Compute the time remaining to wait.
tv_usec is certainly positive. */
result0.tv_sec = x->tv_sec - y->tv_sec;
result0.tv_usec = x->tv_usec - y->tv_usec;
*result = ((double)result0.tv_usec)/1e6 + (double)result0.tv_sec;
/* Return 1 if result is negative. */
return x->tv_sec < y->tv_sec;
}
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Kernel(s) should go here:
int main (int argc,char **argv)
{
struct timeval tdr0, tdr1, tdr;
double restime;
int devid, devcount, error, success;
int xmax, ymax, x, y;
if (BLOCK_SIZE>1024)
{
printf ("Bad BLOCK_SIZE: %d\n", BLOCK_SIZE);
exit (1);
}
/* find number of device in current "context" */
hipGetDevice(&devid);
/* find how many devices are available */
if (hipGetDeviceCount(&devcount) || devcount==0)
{
printf ("No CUDA devices!\n");
exit (1);
}
else
{
hipDeviceProp_t deviceProp;
hipGetDeviceProperties (&deviceProp, devid);
printf ("Device count, devid: %d %d\n", devcount, devid);
printf ("Device: %s\n", deviceProp.name);
printf("[deviceProp.major.deviceProp.minor] = [%d.%d]\n\n", deviceProp.major, deviceProp.minor);
}
//--------------------------------------------------------------------------------
if (error = hipDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr0, NULL);
// This serial computation will have to be replaced by calls to kernel(s):
xmax = 0;
for (int k=KMIN; k<=KMAX; k++)
{
// testing "-1" and "+1" cases:
for (int j=-1; j<2; j=j+2)
{
// Prime candidate:
x = 6*k + j;
// We should be dividing by numbers up to sqrt(x):
ymax = (int)ceil(sqrt((double)x));
// Primality test:
for (y=3; y<=ymax; y=y+2)
{
// Tpo be a success, the modulus should not be equal to zero:
success = x % y;
if (!success)
break;
}
if (success && x > xmax)
{
xmax = x;
}
}
}
if (error = hipDeviceSynchronize())
{
printf ("Error %d\n", error);
exit (error);
}
gettimeofday (&tdr1, NULL);
tdr = tdr0;
timeval_subtract (&restime, &tdr1, &tdr);
printf ("%d\n", xmax);
printf ("Time: %e\n", restime);
//--------------------------------------------------------------------------------
return 0;
} | .text
.file "primes.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z16timeval_subtractPdP7timevalS1_
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z16timeval_subtractPdP7timevalS1_
.p2align 4, 0x90
.type _Z16timeval_subtractPdP7timevalS1_,@function
_Z16timeval_subtractPdP7timevalS1_: # @_Z16timeval_subtractPdP7timevalS1_
.cfi_startproc
# %bb.0:
movq %rdx, %rcx
movq 8(%rdx), %r9
movq %r9, %rax
movabsq $4835703278458516699, %r8 # imm = 0x431BDE82D7B634DB
subq 8(%rsi), %rax
jle .LBB0_2
# %bb.1:
imulq %r8
movq %rdx, %rax
shrq $18, %rax
shrq $63, %rdx
addl %edx, %eax
incl %eax
imull $1000000, %eax, %edx # imm = 0xF4240
movslq %edx, %rdx
subq %rdx, %r9
movq %r9, 8(%rcx)
cltq
addq %rax, (%rcx)
.LBB0_2:
movq 8(%rsi), %rdx
movq 8(%rcx), %r9
movq %rdx, %rax
subq %r9, %rax
cmpq $1000001, %rax # imm = 0xF4241
jl .LBB0_4
# %bb.3:
movq %r9, %rax
subq %rdx, %rax
imulq %r8
movq %rdx, %rax
shrq $63, %rax
sarq $18, %rdx
addq %rax, %rdx
movabsq $4294967296000000, %rax # imm = 0xF424000000000
imulq %rdx, %rax
sarq $32, %rax
addq %r9, %rax
movq %rax, 8(%rcx)
movslq %edx, %rax
subq %rax, (%rcx)
.LBB0_4:
movq 8(%rsi), %rax
subq 8(%rcx), %rax
cvtsi2sd %rax, %xmm0
movq (%rsi), %rdx
divsd .LCPI0_0(%rip), %xmm0
xorl %eax, %eax
subq (%rcx), %rdx
cvtsi2sd %rdx, %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rdi)
setl %al
retq
.Lfunc_end0:
.size _Z16timeval_subtractPdP7timevalS1_, .Lfunc_end0-_Z16timeval_subtractPdP7timevalS1_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI1_1:
.quad 0x0000000000000000 # double 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1512, %rsp # imm = 0x5E8
.cfi_def_cfa_offset 1568
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDevice
leaq 8(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB1_21
# %bb.1:
cmpl $0, 8(%rsp)
je .LBB1_21
# %bb.2:
movl 12(%rsp), %esi
leaq 40(%rsp), %r14
movq %r14, %rdi
callq hipGetDevicePropertiesR0600
movl 8(%rsp), %esi
movl 12(%rsp), %edx
xorl %ebx, %ebx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
movl 400(%rsp), %esi
movl 404(%rsp), %edx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_22
# %bb.3:
leaq 40(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $100000000, %r14d # imm = 0x5F5E100
# implicit-def: $ebp
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_4 Depth=1
incl %r14d
cmpl $100100001, %r14d # imm = 0x5F767A1
je .LBB1_8
.LBB1_4: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
# Child Loop BB1_17 Depth 3
leal (%r14,%r14), %eax
leal (%rax,%rax,2), %r15d
movl $-1, %r12d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_19: # in Loop: Header=BB1_5 Depth=2
movl %edx, %ebp
.LBB1_20: # %._crit_edge
# in Loop: Header=BB1_5 Depth=2
cmpl %r13d, %ebx
cmovlel %r13d, %ebx
testl %ebp, %ebp
cmovel %r13d, %ebx
leal 2(%r12), %eax
testl %r12d, %r12d
movl %eax, %r12d
jns .LBB1_7
.LBB1_5: # Parent Loop BB1_4 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_17 Depth 3
movl %ebx, %r13d
leal (%r12,%r15), %ebx
xorps %xmm0, %xmm0
cvtsi2sd %ebx, %xmm0
ucomisd .LCPI1_1(%rip), %xmm0
jb .LBB1_14
# %bb.6: # in Loop: Header=BB1_5 Depth=2
sqrtsd %xmm0, %xmm0
jmp .LBB1_15
.p2align 4, 0x90
.LBB1_14: # %call.sqrt
# in Loop: Header=BB1_5 Depth=2
callq sqrt
.LBB1_15: # %.split
# in Loop: Header=BB1_5 Depth=2
callq ceil@PLT
cvttsd2si %xmm0, %ecx
cmpl $3, %ecx
jl .LBB1_20
# %bb.16: # %.lr.ph.preheader
# in Loop: Header=BB1_5 Depth=2
movl $3, %esi
.p2align 4, 0x90
.LBB1_17: # %.lr.ph
# Parent Loop BB1_4 Depth=1
# Parent Loop BB1_5 Depth=2
# => This Inner Loop Header: Depth=3
xorl %ebp, %ebp
movl %ebx, %eax
xorl %edx, %edx
divl %esi
testl %edx, %edx
je .LBB1_20
# %bb.18: # in Loop: Header=BB1_17 Depth=3
addl $2, %esi
cmpl %ecx, %esi
jle .LBB1_17
jmp .LBB1_19
.LBB1_8:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_22
# %bb.9:
leaq 24(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 40(%rsp), %rcx
movq 48(%rsp), %rdi
movq 32(%rsp), %rsi
movq %rdi, %rax
movabsq $4835703278458516699, %r8 # imm = 0x431BDE82D7B634DB
subq %rsi, %rax
jle .LBB1_11
# %bb.10:
imulq %r8
movq %rdx, %rax
shrq $18, %rax
shrq $63, %rdx
addl %edx, %eax
incl %eax
imull $1000000, %eax, %edx # imm = 0xF4240
movslq %edx, %rdx
subq %rdx, %rdi
cltq
addq %rax, %rcx
.LBB1_11:
movq %rsi, %rax
subq %rdi, %rax
cmpq $1000001, %rax # imm = 0xF4241
jl .LBB1_13
# %bb.12:
movq %rdi, %rax
subq %rsi, %rax
imulq %r8
movq %rdx, %rax
shrq $63, %rax
sarq $18, %rdx
addq %rax, %rdx
movabsq $4294967296000000, %rax # imm = 0xF424000000000
imulq %rdx, %rax
sarq $32, %rax
addq %rax, %rdi
movslq %edx, %rax
subq %rax, %rcx
.LBB1_13: # %_Z16timeval_subtractPdP7timevalS1_.exit
movq 24(%rsp), %rax
subq %rdi, %rsi
xorps %xmm0, %xmm0
cvtsi2sd %rsi, %xmm0
divsd .LCPI1_0(%rip), %xmm0
subq %rcx, %rax
cvtsi2sd %rax, %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
movl $.L.str.5, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl $.L.str.6, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
xorl %eax, %eax
addq $1512, %rsp # imm = 0x5E8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_22:
.cfi_def_cfa_offset 1568
movl $.L.str.4, %edi
movl %eax, %esi
movl %eax, %ebx
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq exit
.LBB1_21:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Device count, devid: %d %d\n"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device: %s\n"
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "[deviceProp.major.deviceProp.minor] = [%d.%d]\n\n"
.size .L.str.3, 48
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error %d\n"
.size .L.str.4, 10
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d\n"
.size .L.str.5, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Time: %e\n"
.size .L.str.6, 10
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "No CUDA devices!"
.size .Lstr, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00155f2b_00000000-6_primes.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16timeval_subtractPdP7timevalS1_
.type _Z16timeval_subtractPdP7timevalS1_, @function
_Z16timeval_subtractPdP7timevalS1_:
.LFB2070:
.cfi_startproc
endbr64
movq %rdx, %rcx
movq 8(%rsi), %rax
movq 8(%rdx), %r8
cmpq %r8, %rax
jge .L4
movq %r8, %r9
subq %rax, %r9
movabsq $4835703278458516699, %rdx
movq %r9, %rax
imulq %rdx
sarq $18, %rdx
sarq $63, %r9
subq %r9, %rdx
addl $1, %edx
imull $1000000, %edx, %eax
cltq
subq %rax, %r8
movq %r8, 8(%rcx)
movslq %edx, %rdx
addq %rdx, (%rcx)
.L4:
movq 8(%rsi), %rax
movq 8(%rcx), %r8
movq %rax, %rdx
subq %r8, %rdx
cmpq $1000000, %rdx
jle .L5
movq %r8, %r9
subq %rax, %r9
movabsq $4835703278458516699, %rdx
movq %r9, %rax
imulq %rdx
sarq $18, %rdx
sarq $63, %r9
subq %r9, %rdx
imull $1000000, %edx, %eax
cltq
addq %r8, %rax
movq %rax, 8(%rcx)
movslq %edx, %rdx
subq %rdx, (%rcx)
.L5:
movq 8(%rsi), %rax
subq 8(%rcx), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq (%rsi), %rax
subq (%rcx), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, (%rdi)
movq (%rcx), %rax
cmpq %rax, (%rsi)
setl %al
movzbl %al, %eax
ret
.cfi_endproc
.LFE2070:
.size _Z16timeval_subtractPdP7timevalS1_, .-_Z16timeval_subtractPdP7timevalS1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Device count, devid: %d %d\n"
.LC2:
.string "Device: %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "[deviceProp.major.deviceProp.minor] = [%d.%d]\n\n"
.section .rodata.str1.1
.LC4:
.string "No CUDA devices!\n"
.LC5:
.string "Error %d\n"
.LC10:
.string "%d\n"
.LC11:
.string "Time: %e\n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1112, %rsp
.cfi_def_cfa_offset 1168
movq %fs:40, %rax
movq %rax, 1096(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call cudaGetDevice@PLT
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L7
cmpl $0, 4(%rsp)
je .L7
leaq 64(%rsp), %rbx
movl (%rsp), %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movl (%rsp), %ecx
movl 4(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 428(%rsp), %ecx
movl 424(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L30
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $600000003, %r13d
jmp .L10
.L7:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
movl %eax, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %edi
call exit@PLT
.L28:
call sqrt@PLT
jmp .L13
.L15:
testl %ebp, %ebp
je .L16
cmpl %r14d, %ebx
cmovge %ebx, %r14d
.L16:
addl $2, %r12d
cmpl %r13d, %r12d
je .L31
.L20:
movl %r12d, %ebx
pxor %xmm0, %xmm0
cvtsi2sdl %r12d, %xmm0
movq %r15, %xmm3
ucomisd %xmm0, %xmm3
ja .L28
sqrtsd %xmm0, %xmm0
.L13:
movapd %xmm0, %xmm2
movsd .LC12(%rip), %xmm1
andpd %xmm0, %xmm1
movsd .LC7(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L14
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm2
movsd .LC9(%rip), %xmm5
andpd %xmm5, %xmm2
addsd %xmm2, %xmm1
movsd .LC12(%rip), %xmm2
andnpd %xmm0, %xmm2
orpd %xmm1, %xmm2
.L14:
cvttsd2sil %xmm2, %esi
cmpl $2, %esi
jle .L15
movslq %ebx, %rbp
imulq $1431655766, %rbp, %rbp
shrq $32, %rbp
movl %ebx, %eax
sarl $31, %eax
subl %eax, %ebp
leal 0(%rbp,%rbp,2), %eax
movl %ebx, %ebp
subl %eax, %ebp
je .L16
movl $3, %ecx
.L17:
addl $2, %ecx
cmpl %ecx, %esi
jl .L15
movl %ebx, %eax
cltd
idivl %ecx
movl %edx, %ebp
testl %edx, %edx
jne .L17
jmp .L16
.L31:
addl $6, %r13d
cmpl $600600009, %r13d
je .L21
.L10:
leal -4(%r13), %r12d
movl $0x000000000, %r15d
jmp .L20
.L21:
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L32
leaq 32(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call gettimeofday@PLT
movdqa 16(%rsp), %xmm6
movaps %xmm6, 48(%rsp)
leaq 48(%rsp), %rdx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call _Z16timeval_subtractPdP7timevalS1_
movl %r14d, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $1112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl %eax, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.align 8
.LC7:
.long 0
.long 1127219200
.align 8
.LC9:
.long 0
.long 1072693248
.align 8
.LC12:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "primes.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z16timeval_subtractPdP7timevalS1_
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z16timeval_subtractPdP7timevalS1_
.p2align 4, 0x90
.type _Z16timeval_subtractPdP7timevalS1_,@function
_Z16timeval_subtractPdP7timevalS1_: # @_Z16timeval_subtractPdP7timevalS1_
.cfi_startproc
# %bb.0:
movq %rdx, %rcx
movq 8(%rdx), %r9
movq %r9, %rax
movabsq $4835703278458516699, %r8 # imm = 0x431BDE82D7B634DB
subq 8(%rsi), %rax
jle .LBB0_2
# %bb.1:
imulq %r8
movq %rdx, %rax
shrq $18, %rax
shrq $63, %rdx
addl %edx, %eax
incl %eax
imull $1000000, %eax, %edx # imm = 0xF4240
movslq %edx, %rdx
subq %rdx, %r9
movq %r9, 8(%rcx)
cltq
addq %rax, (%rcx)
.LBB0_2:
movq 8(%rsi), %rdx
movq 8(%rcx), %r9
movq %rdx, %rax
subq %r9, %rax
cmpq $1000001, %rax # imm = 0xF4241
jl .LBB0_4
# %bb.3:
movq %r9, %rax
subq %rdx, %rax
imulq %r8
movq %rdx, %rax
shrq $63, %rax
sarq $18, %rdx
addq %rax, %rdx
movabsq $4294967296000000, %rax # imm = 0xF424000000000
imulq %rdx, %rax
sarq $32, %rax
addq %r9, %rax
movq %rax, 8(%rcx)
movslq %edx, %rax
subq %rax, (%rcx)
.LBB0_4:
movq 8(%rsi), %rax
subq 8(%rcx), %rax
cvtsi2sd %rax, %xmm0
movq (%rsi), %rdx
divsd .LCPI0_0(%rip), %xmm0
xorl %eax, %eax
subq (%rcx), %rdx
cvtsi2sd %rdx, %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rdi)
setl %al
retq
.Lfunc_end0:
.size _Z16timeval_subtractPdP7timevalS1_, .Lfunc_end0-_Z16timeval_subtractPdP7timevalS1_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI1_1:
.quad 0x0000000000000000 # double 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1512, %rsp # imm = 0x5E8
.cfi_def_cfa_offset 1568
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDevice
leaq 8(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB1_21
# %bb.1:
cmpl $0, 8(%rsp)
je .LBB1_21
# %bb.2:
movl 12(%rsp), %esi
leaq 40(%rsp), %r14
movq %r14, %rdi
callq hipGetDevicePropertiesR0600
movl 8(%rsp), %esi
movl 12(%rsp), %edx
xorl %ebx, %ebx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
movl 400(%rsp), %esi
movl 404(%rsp), %edx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_22
# %bb.3:
leaq 40(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $100000000, %r14d # imm = 0x5F5E100
# implicit-def: $ebp
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_4 Depth=1
incl %r14d
cmpl $100100001, %r14d # imm = 0x5F767A1
je .LBB1_8
.LBB1_4: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
# Child Loop BB1_17 Depth 3
leal (%r14,%r14), %eax
leal (%rax,%rax,2), %r15d
movl $-1, %r12d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_19: # in Loop: Header=BB1_5 Depth=2
movl %edx, %ebp
.LBB1_20: # %._crit_edge
# in Loop: Header=BB1_5 Depth=2
cmpl %r13d, %ebx
cmovlel %r13d, %ebx
testl %ebp, %ebp
cmovel %r13d, %ebx
leal 2(%r12), %eax
testl %r12d, %r12d
movl %eax, %r12d
jns .LBB1_7
.LBB1_5: # Parent Loop BB1_4 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_17 Depth 3
movl %ebx, %r13d
leal (%r12,%r15), %ebx
xorps %xmm0, %xmm0
cvtsi2sd %ebx, %xmm0
ucomisd .LCPI1_1(%rip), %xmm0
jb .LBB1_14
# %bb.6: # in Loop: Header=BB1_5 Depth=2
sqrtsd %xmm0, %xmm0
jmp .LBB1_15
.p2align 4, 0x90
.LBB1_14: # %call.sqrt
# in Loop: Header=BB1_5 Depth=2
callq sqrt
.LBB1_15: # %.split
# in Loop: Header=BB1_5 Depth=2
callq ceil@PLT
cvttsd2si %xmm0, %ecx
cmpl $3, %ecx
jl .LBB1_20
# %bb.16: # %.lr.ph.preheader
# in Loop: Header=BB1_5 Depth=2
movl $3, %esi
.p2align 4, 0x90
.LBB1_17: # %.lr.ph
# Parent Loop BB1_4 Depth=1
# Parent Loop BB1_5 Depth=2
# => This Inner Loop Header: Depth=3
xorl %ebp, %ebp
movl %ebx, %eax
xorl %edx, %edx
divl %esi
testl %edx, %edx
je .LBB1_20
# %bb.18: # in Loop: Header=BB1_17 Depth=3
addl $2, %esi
cmpl %ecx, %esi
jle .LBB1_17
jmp .LBB1_19
.LBB1_8:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_22
# %bb.9:
leaq 24(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 40(%rsp), %rcx
movq 48(%rsp), %rdi
movq 32(%rsp), %rsi
movq %rdi, %rax
movabsq $4835703278458516699, %r8 # imm = 0x431BDE82D7B634DB
subq %rsi, %rax
jle .LBB1_11
# %bb.10:
imulq %r8
movq %rdx, %rax
shrq $18, %rax
shrq $63, %rdx
addl %edx, %eax
incl %eax
imull $1000000, %eax, %edx # imm = 0xF4240
movslq %edx, %rdx
subq %rdx, %rdi
cltq
addq %rax, %rcx
.LBB1_11:
movq %rsi, %rax
subq %rdi, %rax
cmpq $1000001, %rax # imm = 0xF4241
jl .LBB1_13
# %bb.12:
movq %rdi, %rax
subq %rsi, %rax
imulq %r8
movq %rdx, %rax
shrq $63, %rax
sarq $18, %rdx
addq %rax, %rdx
movabsq $4294967296000000, %rax # imm = 0xF424000000000
imulq %rdx, %rax
sarq $32, %rax
addq %rax, %rdi
movslq %edx, %rax
subq %rax, %rcx
.LBB1_13: # %_Z16timeval_subtractPdP7timevalS1_.exit
movq 24(%rsp), %rax
subq %rdi, %rsi
xorps %xmm0, %xmm0
cvtsi2sd %rsi, %xmm0
divsd .LCPI1_0(%rip), %xmm0
subq %rcx, %rax
cvtsi2sd %rax, %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
movl $.L.str.5, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl $.L.str.6, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
xorl %eax, %eax
addq $1512, %rsp # imm = 0x5E8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_22:
.cfi_def_cfa_offset 1568
movl $.L.str.4, %edi
movl %eax, %esi
movl %eax, %ebx
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq exit
.LBB1_21:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Device count, devid: %d %d\n"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device: %s\n"
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "[deviceProp.major.deviceProp.minor] = [%d.%d]\n\n"
.size .L.str.3, 48
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error %d\n"
.size .L.str.4, 10
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d\n"
.size .L.str.5, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Time: %e\n"
.size .L.str.6, 10
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "No CUDA devices!"
.size .Lstr, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // ============================================ //
// Author: Federico Massa
//
// This is a CPU/GPU particle filter benchmark
// It doesn't actually do anything but replicate
// computations similar to a real particle filter,
// just to evaluate CPU/GPU performances.
// ============================================ //
#include <iostream>
#include <cstdlib>
#include <sstream>
#include <numeric>
#include <random>
#include <chrono>
int nParticles;
int sizeX, sizeY;
int laserPoints;
typedef std::chrono::high_resolution_clock Time;
typedef std::chrono::milliseconds ms;
typedef std::chrono::duration<float> fsec;
std::vector<int> closest_idx;
void generateLaserPoints(std::vector<float>& laserX, std::vector<float>& laserY)
{
for (int i = 0; i < laserX.size(); i++) {
laserX[i] = rand()/RAND_MAX;
}
for (int i = 0; i < laserY.size(); i++) {
laserY[i] = rand()/RAND_MAX;
}
}
void generateOdometry(float& vx, float& vy) {
vx = rand()/RAND_MAX;
vy = rand()/RAND_MAX;
}
__host__ __device__ void getPixel(const float& laserX, const float& laserY, int& laserPX, int& laserPY) {
laserPX = 0;
laserPY = 0;
}
__host__ __device__ float computeWeight(const int& laserPX, const int& laserPY, const int& sizeX, int* closest_idx) {
int idx = laserPX + sizeX*laserPY;
int w = closest_idx[idx];
int wx = w*0;
int wy = w*0;
return wx*wx + wy*wy;
}
__global__ void pf_iteration_dev(int* dev_closest_idx, float* dev_laserX, float* dev_laserY, float* dev_vx, float* dev_vy, float* dev_particles_x, float* dev_particles_y, float* dev_particles_theta, int* dev_laserPoints, float* dev_weights, int* dev_sizeX, int* dev_sizeY) {
int index = threadIdx.x + blockIdx.x*blockDim.x;
// Predict
dev_particles_x[index] += *dev_vx*cos(dev_particles_theta[index]) + *dev_vy*sin(dev_particles_theta[index]);
dev_particles_x[index] += *dev_vx*cos(dev_particles_theta[index]) + *dev_vy*sin(dev_particles_theta[index]);
dev_particles_theta[index] += 1*3.14159/180.0;
// Update
float weight = 0;
for (int i = 0; i < *dev_laserPoints; i++) {
float localLaserX = dev_laserX[i]*cos(dev_particles_theta[index]) + dev_laserY[i]*sin(dev_particles_theta[index]);
float localLaserY = -dev_laserX[i]*sin(dev_particles_theta[index]) + dev_laserY[i]*cos(dev_particles_theta[index]);
int localLaserPX, localLaserPY;
// Transform laser point to pixel coordinates
getPixel(localLaserX, localLaserY, localLaserPX, localLaserPY);
weight += computeWeight(localLaserPX, localLaserPY, *dev_sizeX, dev_closest_idx);
}
dev_weights[index] = weight;
}
void pf_iteration(std::vector<int>& closest_idx, const std::vector<float>& currentlaserX, const std::vector<float>& currentlaserY, const float& vx, const float& vy, std::vector<float>& init_particles_x, std::vector<float>& init_particles_y, std::vector<float>& init_particles_theta, std::vector<float>& weights) {
for (int index = 0; index < nParticles; index++) {
// Predict
init_particles_x[index] += vx*cos(init_particles_theta[index]) + vy*sin(init_particles_theta[index]);
init_particles_y[index] += -vx*sin(init_particles_theta[index]) + vy*cos(init_particles_theta[index]);
init_particles_theta[index] += 1*3.14159/180.0;
// Update
float weight = 0;
for (int i = 0; i < laserPoints; i++) {
float localLaserX = currentlaserX[i]*cos(init_particles_theta[index]) + currentlaserY[i]*sin(init_particles_theta[index]);
float localLaserY = -currentlaserX[i]*sin(init_particles_theta[index]) + currentlaserY[i]*cos(init_particles_theta[index]);
int localLaserPX, localLaserPY;
// Transform laser point to pixel coordinates
getPixel(localLaserX, localLaserY, localLaserPX, localLaserPY);
weight += computeWeight(localLaserPX, localLaserPY, sizeX, closest_idx.data());
}
weights[index] = weight;
}
}
void gpu_test() {
int* dev_closest_idx;
int* dev_laserPoints;
float *dev_laserX, *dev_laserY;
float *dev_vx, *dev_vy;
float* dev_particles_x;
float* dev_particles_y;
float* dev_particles_theta;
float* dev_weights;
int* dev_sizeX, *dev_sizeY;
// Allocate distance map and copy it from host
cudaMalloc((void**)&dev_closest_idx, sizeX*sizeY*sizeof(int));
cudaMemcpy(dev_closest_idx, closest_idx.data(), sizeX*sizeY*sizeof(float), cudaMemcpyHostToDevice);
cudaMalloc((void**)&dev_laserX, laserPoints*sizeof(float));
cudaMalloc((void**)&dev_laserY, laserPoints*sizeof(float));
cudaMalloc((void**)&dev_vx, sizeof(float));
cudaMalloc((void**)&dev_vy, sizeof(float));
cudaMalloc((void**)&dev_particles_x, nParticles*sizeof(float));
cudaMalloc((void**)&dev_particles_y, nParticles*sizeof(float));
cudaMalloc((void**)&dev_particles_theta, nParticles*sizeof(float));
cudaMalloc((void**)&dev_weights, nParticles*sizeof(float));
cudaMalloc((void**)&dev_laserPoints, sizeof(int));
cudaMalloc((void**)&dev_sizeX, sizeof(int));
cudaMalloc((void**)&dev_sizeY, sizeof(int));
cudaMemcpy(dev_sizeX, &sizeX, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_sizeY, &sizeY, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_laserPoints, &laserPoints, sizeof(int), cudaMemcpyHostToDevice);
std::vector<float> init_particles_x, init_particles_y, init_particles_theta;
init_particles_x.reserve(nParticles);
init_particles_y.reserve(nParticles);
init_particles_theta.reserve(nParticles);
// Initialize particles
for (int i = 0; i < nParticles; i++) {
init_particles_x[i] = init_particles_y[i] = init_particles_theta[i] = 0.0;
}
cudaMemcpy(dev_particles_x, init_particles_x.data(), nParticles*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dev_particles_y, init_particles_y.data(), nParticles*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dev_particles_theta, init_particles_theta.data(), nParticles*sizeof(float), cudaMemcpyHostToDevice);
// Current measurements
std::vector<float> currentLaserX(laserPoints);
std::vector<float> currentLaserY(laserPoints);
float vx, vy;
// Weights (output)
std::vector<float> weights(nParticles);
const int iterations = 100;
std::vector<float> alloc_time, compute_time, retrieve_time;
// Particle filter iteration
for (int i = 0; i < iterations; i++) {
auto t0 = Time::now();
generateLaserPoints(currentLaserX, currentLaserY);
generateOdometry(vx, vy);
// Transfer current measurements to device
cudaMemcpy(dev_laserX, currentLaserX.data(), laserPoints*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dev_laserY, currentLaserY.data(), laserPoints*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dev_vx, &vx, sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dev_vy, &vy, sizeof(float), cudaMemcpyHostToDevice);
// 1 particle for each core
const int THREADS = 128;
const int BLOCKS = std::ceil(float(nParticles)/float(THREADS));
auto t1 = Time::now();
// Launch an iteration
pf_iteration_dev<<<BLOCKS,THREADS>>>(dev_closest_idx, dev_laserX, dev_laserY, dev_vx, dev_vy, dev_particles_x, dev_particles_y, dev_particles_theta, dev_laserPoints, dev_weights, dev_sizeX, dev_sizeY);
cudaDeviceSynchronize();
auto t2 = Time::now();
// Retrieve results
cudaMemcpy(weights.data(), dev_weights, nParticles*sizeof(float), cudaMemcpyDeviceToHost);
auto t3 = Time::now();
fsec fs_alloc = t1 - t0;
fsec fs_compute = t2 - t1;
fsec fs_retrieve = t3 - t2;
float alloc = fs_alloc.count();
float compute = fs_compute.count();
float retrieve = fs_retrieve.count();
alloc_time.push_back(alloc);
compute_time.push_back(compute);
retrieve_time.push_back(retrieve);
}
float alloc_mean = std::accumulate(alloc_time.begin(), alloc_time.end(), 0.0)/float(iterations);
float compute_mean = std::accumulate(compute_time.begin(), compute_time.end(), 0.0)/float(iterations);
float retrieve_mean = std::accumulate(retrieve_time.begin(), retrieve_time.end(), 0.0)/float(iterations);
printf("GPU test finished, average time over %d iterations was %f: %f (alloc), %f (compute), %f (retrieve)\n", iterations, alloc_mean+compute_mean+retrieve_mean, alloc_mean, compute_mean, retrieve_mean);
// Release memory on device
cudaFree(dev_closest_idx);
cudaFree(dev_laserX);
cudaFree(dev_laserY);
cudaFree(dev_vx);
cudaFree(dev_vy);
}
void cpu_test() {
std::vector<float> init_particles_x, init_particles_y, init_particles_theta;
init_particles_x.reserve(nParticles);
init_particles_y.reserve(nParticles);
init_particles_theta.reserve(nParticles);
// Initialize particles
for (int i = 0; i < nParticles; i++) {
init_particles_x[i] = init_particles_y[i] = init_particles_theta[i] = 0.0;
}
// Current measurements
std::vector<float> currentLaserX(laserPoints);
std::vector<float> currentLaserY(laserPoints);
float vx, vy;
// Weights (output)
std::vector<float> weights(nParticles);
const int iterations = 100;
std::vector<float> tot_time;
// Particle filter iteration
for (int i = 0; i < iterations; i++) {
auto t0 = Time::now();
generateLaserPoints(currentLaserX, currentLaserY);
generateOdometry(vx, vy);
// Launch an iteration
pf_iteration(closest_idx, currentLaserX, currentLaserY, vx, vy, init_particles_x, init_particles_y, init_particles_theta, weights);
auto t3 = Time::now();
fsec fs_tot = t3 - t0;
float tot = fs_tot.count();
tot_time.push_back(tot);
}
float tot_mean = std::accumulate(tot_time.begin(), tot_time.end(), 0.0)/float(iterations);
printf("###########################################################\n");
printf("CPU test finished, average time over %d iterations was %f\n", iterations, tot_mean);
printf("###########################################################\n\n");
}
int main(int argc, char** argv) {
if (argc != 5) {
std::cout << "Please specify an integer number of particles, map sizeX, map sizeY, laserPoints" << std::endl;
exit(1);
}
std::stringstream ss;
ss << argv[1];
ss >> nParticles;
ss.clear();
ss << argv[2];
ss >> sizeX;
ss.clear();
ss << argv[3];
ss >> sizeY;
ss.clear();
ss << argv[4];
ss >> laserPoints;
ss.clear();
printf("==================================================================\n");
printf("Dummy particle filter generator with %d particles, a %dx%d map, %d laser scan points\n", nParticles, sizeX, sizeY, laserPoints);
printf("==================================================================\n\n");
// Allocate dummy map, vectorized, indicating the index of the closest black pixel in the map
// with respect to the current index
closest_idx.reserve(sizeX*sizeY);
for (int i = 0; i < closest_idx.size(); i++)
closest_idx[i] = rand();
cpu_test();
int count;
cudaGetDeviceCount(&count);
for (int i = 0; i < count; i++) {
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, i);
printf("###################################################\n");
printf("Starting GPU benchmark on device %d with name: %s\n", i, prop.name);
cudaSetDevice(i);
gpu_test();
printf("##################################################\n\n");
}
} | // ============================================ //
// Author: Federico Massa
//
// This is a CPU/GPU particle filter benchmark
// It doesn't actually do anything but replicate
// computations similar to a real particle filter,
// just to evaluate CPU/GPU performances.
// ============================================ //
#include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <sstream>
#include <numeric>
#include <random>
#include <chrono>
int nParticles;
int sizeX, sizeY;
int laserPoints;
typedef std::chrono::high_resolution_clock Time;
typedef std::chrono::milliseconds ms;
typedef std::chrono::duration<float> fsec;
std::vector<int> closest_idx;
void generateLaserPoints(std::vector<float>& laserX, std::vector<float>& laserY)
{
for (int i = 0; i < laserX.size(); i++) {
laserX[i] = rand()/RAND_MAX;
}
for (int i = 0; i < laserY.size(); i++) {
laserY[i] = rand()/RAND_MAX;
}
}
void generateOdometry(float& vx, float& vy) {
vx = rand()/RAND_MAX;
vy = rand()/RAND_MAX;
}
__host__ __device__ void getPixel(const float& laserX, const float& laserY, int& laserPX, int& laserPY) {
laserPX = 0;
laserPY = 0;
}
__host__ __device__ float computeWeight(const int& laserPX, const int& laserPY, const int& sizeX, int* closest_idx) {
int idx = laserPX + sizeX*laserPY;
int w = closest_idx[idx];
int wx = w*0;
int wy = w*0;
return wx*wx + wy*wy;
}
__global__ void pf_iteration_dev(int* dev_closest_idx, float* dev_laserX, float* dev_laserY, float* dev_vx, float* dev_vy, float* dev_particles_x, float* dev_particles_y, float* dev_particles_theta, int* dev_laserPoints, float* dev_weights, int* dev_sizeX, int* dev_sizeY) {
int index = threadIdx.x + blockIdx.x*blockDim.x;
// Predict
dev_particles_x[index] += *dev_vx*cos(dev_particles_theta[index]) + *dev_vy*sin(dev_particles_theta[index]);
dev_particles_x[index] += *dev_vx*cos(dev_particles_theta[index]) + *dev_vy*sin(dev_particles_theta[index]);
dev_particles_theta[index] += 1*3.14159/180.0;
// Update
float weight = 0;
for (int i = 0; i < *dev_laserPoints; i++) {
float localLaserX = dev_laserX[i]*cos(dev_particles_theta[index]) + dev_laserY[i]*sin(dev_particles_theta[index]);
float localLaserY = -dev_laserX[i]*sin(dev_particles_theta[index]) + dev_laserY[i]*cos(dev_particles_theta[index]);
int localLaserPX, localLaserPY;
// Transform laser point to pixel coordinates
getPixel(localLaserX, localLaserY, localLaserPX, localLaserPY);
weight += computeWeight(localLaserPX, localLaserPY, *dev_sizeX, dev_closest_idx);
}
dev_weights[index] = weight;
}
void pf_iteration(std::vector<int>& closest_idx, const std::vector<float>& currentlaserX, const std::vector<float>& currentlaserY, const float& vx, const float& vy, std::vector<float>& init_particles_x, std::vector<float>& init_particles_y, std::vector<float>& init_particles_theta, std::vector<float>& weights) {
for (int index = 0; index < nParticles; index++) {
// Predict
init_particles_x[index] += vx*cos(init_particles_theta[index]) + vy*sin(init_particles_theta[index]);
init_particles_y[index] += -vx*sin(init_particles_theta[index]) + vy*cos(init_particles_theta[index]);
init_particles_theta[index] += 1*3.14159/180.0;
// Update
float weight = 0;
for (int i = 0; i < laserPoints; i++) {
float localLaserX = currentlaserX[i]*cos(init_particles_theta[index]) + currentlaserY[i]*sin(init_particles_theta[index]);
float localLaserY = -currentlaserX[i]*sin(init_particles_theta[index]) + currentlaserY[i]*cos(init_particles_theta[index]);
int localLaserPX, localLaserPY;
// Transform laser point to pixel coordinates
getPixel(localLaserX, localLaserY, localLaserPX, localLaserPY);
weight += computeWeight(localLaserPX, localLaserPY, sizeX, closest_idx.data());
}
weights[index] = weight;
}
}
void gpu_test() {
int* dev_closest_idx;
int* dev_laserPoints;
float *dev_laserX, *dev_laserY;
float *dev_vx, *dev_vy;
float* dev_particles_x;
float* dev_particles_y;
float* dev_particles_theta;
float* dev_weights;
int* dev_sizeX, *dev_sizeY;
// Allocate distance map and copy it from host
hipMalloc((void**)&dev_closest_idx, sizeX*sizeY*sizeof(int));
hipMemcpy(dev_closest_idx, closest_idx.data(), sizeX*sizeY*sizeof(float), hipMemcpyHostToDevice);
hipMalloc((void**)&dev_laserX, laserPoints*sizeof(float));
hipMalloc((void**)&dev_laserY, laserPoints*sizeof(float));
hipMalloc((void**)&dev_vx, sizeof(float));
hipMalloc((void**)&dev_vy, sizeof(float));
hipMalloc((void**)&dev_particles_x, nParticles*sizeof(float));
hipMalloc((void**)&dev_particles_y, nParticles*sizeof(float));
hipMalloc((void**)&dev_particles_theta, nParticles*sizeof(float));
hipMalloc((void**)&dev_weights, nParticles*sizeof(float));
hipMalloc((void**)&dev_laserPoints, sizeof(int));
hipMalloc((void**)&dev_sizeX, sizeof(int));
hipMalloc((void**)&dev_sizeY, sizeof(int));
hipMemcpy(dev_sizeX, &sizeX, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_sizeY, &sizeY, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_laserPoints, &laserPoints, sizeof(int), hipMemcpyHostToDevice);
std::vector<float> init_particles_x, init_particles_y, init_particles_theta;
init_particles_x.reserve(nParticles);
init_particles_y.reserve(nParticles);
init_particles_theta.reserve(nParticles);
// Initialize particles
for (int i = 0; i < nParticles; i++) {
init_particles_x[i] = init_particles_y[i] = init_particles_theta[i] = 0.0;
}
hipMemcpy(dev_particles_x, init_particles_x.data(), nParticles*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_particles_y, init_particles_y.data(), nParticles*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_particles_theta, init_particles_theta.data(), nParticles*sizeof(float), hipMemcpyHostToDevice);
// Current measurements
std::vector<float> currentLaserX(laserPoints);
std::vector<float> currentLaserY(laserPoints);
float vx, vy;
// Weights (output)
std::vector<float> weights(nParticles);
const int iterations = 100;
std::vector<float> alloc_time, compute_time, retrieve_time;
// Particle filter iteration
for (int i = 0; i < iterations; i++) {
auto t0 = Time::now();
generateLaserPoints(currentLaserX, currentLaserY);
generateOdometry(vx, vy);
// Transfer current measurements to device
hipMemcpy(dev_laserX, currentLaserX.data(), laserPoints*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_laserY, currentLaserY.data(), laserPoints*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_vx, &vx, sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_vy, &vy, sizeof(float), hipMemcpyHostToDevice);
// 1 particle for each core
const int THREADS = 128;
const int BLOCKS = std::ceil(float(nParticles)/float(THREADS));
auto t1 = Time::now();
// Launch an iteration
pf_iteration_dev<<<BLOCKS,THREADS>>>(dev_closest_idx, dev_laserX, dev_laserY, dev_vx, dev_vy, dev_particles_x, dev_particles_y, dev_particles_theta, dev_laserPoints, dev_weights, dev_sizeX, dev_sizeY);
hipDeviceSynchronize();
auto t2 = Time::now();
// Retrieve results
hipMemcpy(weights.data(), dev_weights, nParticles*sizeof(float), hipMemcpyDeviceToHost);
auto t3 = Time::now();
fsec fs_alloc = t1 - t0;
fsec fs_compute = t2 - t1;
fsec fs_retrieve = t3 - t2;
float alloc = fs_alloc.count();
float compute = fs_compute.count();
float retrieve = fs_retrieve.count();
alloc_time.push_back(alloc);
compute_time.push_back(compute);
retrieve_time.push_back(retrieve);
}
float alloc_mean = std::accumulate(alloc_time.begin(), alloc_time.end(), 0.0)/float(iterations);
float compute_mean = std::accumulate(compute_time.begin(), compute_time.end(), 0.0)/float(iterations);
float retrieve_mean = std::accumulate(retrieve_time.begin(), retrieve_time.end(), 0.0)/float(iterations);
printf("GPU test finished, average time over %d iterations was %f: %f (alloc), %f (compute), %f (retrieve)\n", iterations, alloc_mean+compute_mean+retrieve_mean, alloc_mean, compute_mean, retrieve_mean);
// Release memory on device
hipFree(dev_closest_idx);
hipFree(dev_laserX);
hipFree(dev_laserY);
hipFree(dev_vx);
hipFree(dev_vy);
}
void cpu_test() {
std::vector<float> init_particles_x, init_particles_y, init_particles_theta;
init_particles_x.reserve(nParticles);
init_particles_y.reserve(nParticles);
init_particles_theta.reserve(nParticles);
// Initialize particles
for (int i = 0; i < nParticles; i++) {
init_particles_x[i] = init_particles_y[i] = init_particles_theta[i] = 0.0;
}
// Current measurements
std::vector<float> currentLaserX(laserPoints);
std::vector<float> currentLaserY(laserPoints);
float vx, vy;
// Weights (output)
std::vector<float> weights(nParticles);
const int iterations = 100;
std::vector<float> tot_time;
// Particle filter iteration
for (int i = 0; i < iterations; i++) {
auto t0 = Time::now();
generateLaserPoints(currentLaserX, currentLaserY);
generateOdometry(vx, vy);
// Launch an iteration
pf_iteration(closest_idx, currentLaserX, currentLaserY, vx, vy, init_particles_x, init_particles_y, init_particles_theta, weights);
auto t3 = Time::now();
fsec fs_tot = t3 - t0;
float tot = fs_tot.count();
tot_time.push_back(tot);
}
float tot_mean = std::accumulate(tot_time.begin(), tot_time.end(), 0.0)/float(iterations);
printf("###########################################################\n");
printf("CPU test finished, average time over %d iterations was %f\n", iterations, tot_mean);
printf("###########################################################\n\n");
}
int main(int argc, char** argv) {
if (argc != 5) {
std::cout << "Please specify an integer number of particles, map sizeX, map sizeY, laserPoints" << std::endl;
exit(1);
}
std::stringstream ss;
ss << argv[1];
ss >> nParticles;
ss.clear();
ss << argv[2];
ss >> sizeX;
ss.clear();
ss << argv[3];
ss >> sizeY;
ss.clear();
ss << argv[4];
ss >> laserPoints;
ss.clear();
printf("==================================================================\n");
printf("Dummy particle filter generator with %d particles, a %dx%d map, %d laser scan points\n", nParticles, sizeX, sizeY, laserPoints);
printf("==================================================================\n\n");
// Allocate dummy map, vectorized, indicating the index of the closest black pixel in the map
// with respect to the current index
closest_idx.reserve(sizeX*sizeY);
for (int i = 0; i < closest_idx.size(); i++)
closest_idx[i] = rand();
cpu_test();
int count;
hipGetDeviceCount(&count);
for (int i = 0; i < count; i++) {
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, i);
printf("###################################################\n");
printf("Starting GPU benchmark on device %d with name: %s\n", i, prop.name);
hipSetDevice(i);
gpu_test();
printf("##################################################\n\n");
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // ============================================ //
// Author: Federico Massa
//
// This is a CPU/GPU particle filter benchmark
// It doesn't actually do anything but replicate
// computations similar to a real particle filter,
// just to evaluate CPU/GPU performances.
// ============================================ //
#include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <sstream>
#include <numeric>
#include <random>
#include <chrono>
int nParticles;
int sizeX, sizeY;
int laserPoints;
typedef std::chrono::high_resolution_clock Time;
typedef std::chrono::milliseconds ms;
typedef std::chrono::duration<float> fsec;
std::vector<int> closest_idx;
void generateLaserPoints(std::vector<float>& laserX, std::vector<float>& laserY)
{
for (int i = 0; i < laserX.size(); i++) {
laserX[i] = rand()/RAND_MAX;
}
for (int i = 0; i < laserY.size(); i++) {
laserY[i] = rand()/RAND_MAX;
}
}
void generateOdometry(float& vx, float& vy) {
vx = rand()/RAND_MAX;
vy = rand()/RAND_MAX;
}
__host__ __device__ void getPixel(const float& laserX, const float& laserY, int& laserPX, int& laserPY) {
laserPX = 0;
laserPY = 0;
}
__host__ __device__ float computeWeight(const int& laserPX, const int& laserPY, const int& sizeX, int* closest_idx) {
int idx = laserPX + sizeX*laserPY;
int w = closest_idx[idx];
int wx = w*0;
int wy = w*0;
return wx*wx + wy*wy;
}
__global__ void pf_iteration_dev(int* dev_closest_idx, float* dev_laserX, float* dev_laserY, float* dev_vx, float* dev_vy, float* dev_particles_x, float* dev_particles_y, float* dev_particles_theta, int* dev_laserPoints, float* dev_weights, int* dev_sizeX, int* dev_sizeY) {
int index = threadIdx.x + blockIdx.x*blockDim.x;
// Predict
dev_particles_x[index] += *dev_vx*cos(dev_particles_theta[index]) + *dev_vy*sin(dev_particles_theta[index]);
dev_particles_x[index] += *dev_vx*cos(dev_particles_theta[index]) + *dev_vy*sin(dev_particles_theta[index]);
dev_particles_theta[index] += 1*3.14159/180.0;
// Update
float weight = 0;
for (int i = 0; i < *dev_laserPoints; i++) {
float localLaserX = dev_laserX[i]*cos(dev_particles_theta[index]) + dev_laserY[i]*sin(dev_particles_theta[index]);
float localLaserY = -dev_laserX[i]*sin(dev_particles_theta[index]) + dev_laserY[i]*cos(dev_particles_theta[index]);
int localLaserPX, localLaserPY;
// Transform laser point to pixel coordinates
getPixel(localLaserX, localLaserY, localLaserPX, localLaserPY);
weight += computeWeight(localLaserPX, localLaserPY, *dev_sizeX, dev_closest_idx);
}
dev_weights[index] = weight;
}
void pf_iteration(std::vector<int>& closest_idx, const std::vector<float>& currentlaserX, const std::vector<float>& currentlaserY, const float& vx, const float& vy, std::vector<float>& init_particles_x, std::vector<float>& init_particles_y, std::vector<float>& init_particles_theta, std::vector<float>& weights) {
for (int index = 0; index < nParticles; index++) {
// Predict
init_particles_x[index] += vx*cos(init_particles_theta[index]) + vy*sin(init_particles_theta[index]);
init_particles_y[index] += -vx*sin(init_particles_theta[index]) + vy*cos(init_particles_theta[index]);
init_particles_theta[index] += 1*3.14159/180.0;
// Update
float weight = 0;
for (int i = 0; i < laserPoints; i++) {
float localLaserX = currentlaserX[i]*cos(init_particles_theta[index]) + currentlaserY[i]*sin(init_particles_theta[index]);
float localLaserY = -currentlaserX[i]*sin(init_particles_theta[index]) + currentlaserY[i]*cos(init_particles_theta[index]);
int localLaserPX, localLaserPY;
// Transform laser point to pixel coordinates
getPixel(localLaserX, localLaserY, localLaserPX, localLaserPY);
weight += computeWeight(localLaserPX, localLaserPY, sizeX, closest_idx.data());
}
weights[index] = weight;
}
}
void gpu_test() {
int* dev_closest_idx;
int* dev_laserPoints;
float *dev_laserX, *dev_laserY;
float *dev_vx, *dev_vy;
float* dev_particles_x;
float* dev_particles_y;
float* dev_particles_theta;
float* dev_weights;
int* dev_sizeX, *dev_sizeY;
// Allocate distance map and copy it from host
hipMalloc((void**)&dev_closest_idx, sizeX*sizeY*sizeof(int));
hipMemcpy(dev_closest_idx, closest_idx.data(), sizeX*sizeY*sizeof(float), hipMemcpyHostToDevice);
hipMalloc((void**)&dev_laserX, laserPoints*sizeof(float));
hipMalloc((void**)&dev_laserY, laserPoints*sizeof(float));
hipMalloc((void**)&dev_vx, sizeof(float));
hipMalloc((void**)&dev_vy, sizeof(float));
hipMalloc((void**)&dev_particles_x, nParticles*sizeof(float));
hipMalloc((void**)&dev_particles_y, nParticles*sizeof(float));
hipMalloc((void**)&dev_particles_theta, nParticles*sizeof(float));
hipMalloc((void**)&dev_weights, nParticles*sizeof(float));
hipMalloc((void**)&dev_laserPoints, sizeof(int));
hipMalloc((void**)&dev_sizeX, sizeof(int));
hipMalloc((void**)&dev_sizeY, sizeof(int));
hipMemcpy(dev_sizeX, &sizeX, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_sizeY, &sizeY, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_laserPoints, &laserPoints, sizeof(int), hipMemcpyHostToDevice);
std::vector<float> init_particles_x, init_particles_y, init_particles_theta;
init_particles_x.reserve(nParticles);
init_particles_y.reserve(nParticles);
init_particles_theta.reserve(nParticles);
// Initialize particles
for (int i = 0; i < nParticles; i++) {
init_particles_x[i] = init_particles_y[i] = init_particles_theta[i] = 0.0;
}
hipMemcpy(dev_particles_x, init_particles_x.data(), nParticles*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_particles_y, init_particles_y.data(), nParticles*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_particles_theta, init_particles_theta.data(), nParticles*sizeof(float), hipMemcpyHostToDevice);
// Current measurements
std::vector<float> currentLaserX(laserPoints);
std::vector<float> currentLaserY(laserPoints);
float vx, vy;
// Weights (output)
std::vector<float> weights(nParticles);
const int iterations = 100;
std::vector<float> alloc_time, compute_time, retrieve_time;
// Particle filter iteration
for (int i = 0; i < iterations; i++) {
auto t0 = Time::now();
generateLaserPoints(currentLaserX, currentLaserY);
generateOdometry(vx, vy);
// Transfer current measurements to device
hipMemcpy(dev_laserX, currentLaserX.data(), laserPoints*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_laserY, currentLaserY.data(), laserPoints*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_vx, &vx, sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dev_vy, &vy, sizeof(float), hipMemcpyHostToDevice);
// 1 particle for each core
const int THREADS = 128;
const int BLOCKS = std::ceil(float(nParticles)/float(THREADS));
auto t1 = Time::now();
// Launch an iteration
pf_iteration_dev<<<BLOCKS,THREADS>>>(dev_closest_idx, dev_laserX, dev_laserY, dev_vx, dev_vy, dev_particles_x, dev_particles_y, dev_particles_theta, dev_laserPoints, dev_weights, dev_sizeX, dev_sizeY);
hipDeviceSynchronize();
auto t2 = Time::now();
// Retrieve results
hipMemcpy(weights.data(), dev_weights, nParticles*sizeof(float), hipMemcpyDeviceToHost);
auto t3 = Time::now();
fsec fs_alloc = t1 - t0;
fsec fs_compute = t2 - t1;
fsec fs_retrieve = t3 - t2;
float alloc = fs_alloc.count();
float compute = fs_compute.count();
float retrieve = fs_retrieve.count();
alloc_time.push_back(alloc);
compute_time.push_back(compute);
retrieve_time.push_back(retrieve);
}
float alloc_mean = std::accumulate(alloc_time.begin(), alloc_time.end(), 0.0)/float(iterations);
float compute_mean = std::accumulate(compute_time.begin(), compute_time.end(), 0.0)/float(iterations);
float retrieve_mean = std::accumulate(retrieve_time.begin(), retrieve_time.end(), 0.0)/float(iterations);
printf("GPU test finished, average time over %d iterations was %f: %f (alloc), %f (compute), %f (retrieve)\n", iterations, alloc_mean+compute_mean+retrieve_mean, alloc_mean, compute_mean, retrieve_mean);
// Release memory on device
hipFree(dev_closest_idx);
hipFree(dev_laserX);
hipFree(dev_laserY);
hipFree(dev_vx);
hipFree(dev_vy);
}
void cpu_test() {
std::vector<float> init_particles_x, init_particles_y, init_particles_theta;
init_particles_x.reserve(nParticles);
init_particles_y.reserve(nParticles);
init_particles_theta.reserve(nParticles);
// Initialize particles
for (int i = 0; i < nParticles; i++) {
init_particles_x[i] = init_particles_y[i] = init_particles_theta[i] = 0.0;
}
// Current measurements
std::vector<float> currentLaserX(laserPoints);
std::vector<float> currentLaserY(laserPoints);
float vx, vy;
// Weights (output)
std::vector<float> weights(nParticles);
const int iterations = 100;
std::vector<float> tot_time;
// Particle filter iteration
for (int i = 0; i < iterations; i++) {
auto t0 = Time::now();
generateLaserPoints(currentLaserX, currentLaserY);
generateOdometry(vx, vy);
// Launch an iteration
pf_iteration(closest_idx, currentLaserX, currentLaserY, vx, vy, init_particles_x, init_particles_y, init_particles_theta, weights);
auto t3 = Time::now();
fsec fs_tot = t3 - t0;
float tot = fs_tot.count();
tot_time.push_back(tot);
}
float tot_mean = std::accumulate(tot_time.begin(), tot_time.end(), 0.0)/float(iterations);
printf("###########################################################\n");
printf("CPU test finished, average time over %d iterations was %f\n", iterations, tot_mean);
printf("###########################################################\n\n");
}
int main(int argc, char** argv) {
if (argc != 5) {
std::cout << "Please specify an integer number of particles, map sizeX, map sizeY, laserPoints" << std::endl;
exit(1);
}
std::stringstream ss;
ss << argv[1];
ss >> nParticles;
ss.clear();
ss << argv[2];
ss >> sizeX;
ss.clear();
ss << argv[3];
ss >> sizeY;
ss.clear();
ss << argv[4];
ss >> laserPoints;
ss.clear();
printf("==================================================================\n");
printf("Dummy particle filter generator with %d particles, a %dx%d map, %d laser scan points\n", nParticles, sizeX, sizeY, laserPoints);
printf("==================================================================\n\n");
// Allocate dummy map, vectorized, indicating the index of the closest black pixel in the map
// with respect to the current index
closest_idx.reserve(sizeX*sizeY);
for (int i = 0; i < closest_idx.size(); i++)
closest_idx[i] = rand();
cpu_test();
int count;
hipGetDeviceCount(&count);
for (int i = 0; i < count; i++) {
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, i);
printf("###################################################\n");
printf("Starting GPU benchmark on device %d with name: %s\n", i, prop.name);
hipSetDevice(i);
gpu_test();
printf("##################################################\n\n");
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16pf_iteration_devPiPfS0_S0_S0_S0_S0_S0_S_S0_S_S_
.globl _Z16pf_iteration_devPiPfS0_S0_S0_S0_S0_S0_S_S0_S_S_
.p2align 8
.type _Z16pf_iteration_devPiPfS0_S0_S0_S0_S0_S0_S_S0_S_S_,@function
_Z16pf_iteration_devPiPfS0_S0_S0_S0_S0_S0_S_S0_S_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x6c
s_load_b64 s[2:3], s[0:1], 0x38
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v7, 0x7fffffff, v0
v_cmp_ngt_f32_e64 s8, 0x48000000, |v0|
s_and_saveexec_b32 s2, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s2
s_cbranch_execz .LBB0_2
s_mov_b32 s2, 0x7fffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_or_b32 v17, v7, s2, 0x800000
v_mad_u64_u32 v[5:6], null, v17, 0xfe5163ab, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v8, v6
v_lshrrev_b32_e32 v6, 23, v7
v_mad_u64_u32 v[10:11], null, v17, 0x3c439041, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, 0xffffff88, v6
v_cmp_lt_u32_e32 vcc_lo, 63, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v8, v11
v_cndmask_b32_e64 v15, 0, 0xffffffc0, vcc_lo
v_mad_u64_u32 v[11:12], null, v17, 0xdb629599, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v15, v6
v_mov_b32_e32 v8, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_lt_u32_e64 s2, 31, v6
v_cndmask_b32_e32 v5, v11, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[12:13], null, v17, 0xf534ddc0, v[8:9]
v_cndmask_b32_e64 v16, 0, 0xffffffe0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v6, v16, v6
v_mov_b32_e32 v8, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v6
v_mad_u64_u32 v[13:14], null, v17, 0xfc2757d1, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v8, v14
v_mad_u64_u32 v[14:15], null, v17, 0x4e441529, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v8, v15
v_mad_u64_u32 v[15:16], null, v17, 0xa2f9836e, v[8:9]
v_cndmask_b32_e64 v8, 0, 0xffffffe0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v9, v14, v12 :: v_dual_add_nc_u32 v6, v8, v6
v_dual_cndmask_b32 v15, v15, v13 :: v_dual_cndmask_b32 v14, v16, v14
v_dual_cndmask_b32 v13, v13, v11 :: v_dual_cndmask_b32 v8, v12, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v6
v_cndmask_b32_e64 v10, v15, v9, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v14, v15, s2
v_cndmask_b32_e64 v9, v9, v13, s2
v_sub_nc_u32_e32 v14, 32, v6
v_cndmask_b32_e64 v13, v13, v8, s2
v_cndmask_b32_e64 v5, v8, v5, s2
v_cndmask_b32_e64 v12, v12, v10, s3
v_cndmask_b32_e64 v10, v10, v9, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v9, v9, v13, s3
v_cndmask_b32_e64 v5, v13, v5, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v15, v12, v10, v14
v_alignbit_b32 v11, v10, v9, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v13, v9, v5, v14
v_cndmask_b32_e32 v6, v15, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v8, v11, v10 :: v_dual_cndmask_b32 v9, v13, v9
v_bfe_u32 v10, v6, 29, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v11, v6, v8, 30
v_alignbit_b32 v8, v8, v9, 30
v_alignbit_b32 v5, v9, v5, 30
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v12, 0, v10
v_xor_b32_e32 v11, v11, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v8, v8, v12
v_xor_b32_e32 v5, v5, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v13, v11
v_min_u32_e32 v13, 32, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v9, 31, v13
v_lshlrev_b32_e32 v15, 23, v13
v_alignbit_b32 v11, v11, v8, v9
v_alignbit_b32 v5, v8, v5, v9
v_lshrrev_b32_e32 v9, 29, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v8, v11, v5, 9
v_lshlrev_b32_e32 v9, 31, v9
v_lshrrev_b32_e32 v11, 9, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_clz_i32_u32_e32 v12, v8
v_or_b32_e32 v14, 0.5, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_u32_e32 v12, 32, v12
v_sub_nc_u32_e32 v14, v14, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v16, 31, v12
v_alignbit_b32 v5, v8, v5, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_or_b32_e32 v8, v11, v14
v_add_lshl_u32 v11, v12, v13, 23
v_lshrrev_b32_e32 v5, 9, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v12, 0x3fc90fda, v8
v_sub_nc_u32_e32 v5, v5, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v11, v8, 0x3fc90fda, -v12
v_add_nc_u32_e32 v5, 0x33000000, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmamk_f32 v8, v8, 0x33a22168, v11
v_or_b32_e32 v5, v5, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, 0x3fc90fda, v5
v_lshrrev_b32_e32 v5, 30, v6
v_dual_add_f32 v8, v12, v8 :: v_dual_add_nc_u32 v9, v10, v5
.LBB0_2:
s_and_not1_saveexec_b32 s2, s4
v_mul_f32_e64 v5, 0x3f22f983, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v5, v5
v_fma_f32 v6, v5, 0xbfc90fda, |v0|
v_cvt_i32_f32_e32 v9, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v6, v5, 0xb3a22168, v6
v_fmamk_f32 v8, v5, 0xa7c234c4, v6
s_or_b32 exec_lo, exec_lo, s2
s_load_b128 s[4:7], s[0:1], 0x18
s_and_saveexec_b32 s2, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s8, exec_lo, s2
s_cbranch_execz .LBB0_6
s_mov_b32 s2, 0x7fffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_or_b32 v19, v7, s2, 0x800000
v_mad_u64_u32 v[5:6], null, v19, 0xfe5163ab, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v10, v6
v_lshrrev_b32_e32 v6, 23, v7
v_mad_u64_u32 v[12:13], null, v19, 0x3c439041, v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, 0xffffff88, v6
v_cmp_lt_u32_e32 vcc_lo, 63, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v10, v13
v_cndmask_b32_e64 v17, 0, 0xffffffc0, vcc_lo
v_mad_u64_u32 v[13:14], null, v19, 0xdb629599, v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v17, v6
v_mov_b32_e32 v10, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_lt_u32_e64 s2, 31, v6
v_cndmask_b32_e32 v5, v13, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[14:15], null, v19, 0xf534ddc0, v[10:11]
v_cndmask_b32_e64 v18, 0, 0xffffffe0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v6, v18, v6
v_mov_b32_e32 v10, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v6
v_mad_u64_u32 v[15:16], null, v19, 0xfc2757d1, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v10, v16
v_mad_u64_u32 v[16:17], null, v19, 0x4e441529, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v10, v17
v_mad_u64_u32 v[17:18], null, v19, 0xa2f9836e, v[10:11]
v_cndmask_b32_e64 v10, 0, 0xffffffe0, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v11, v16, v14, vcc_lo
v_dual_cndmask_b32 v17, v17, v15 :: v_dual_add_nc_u32 v6, v10, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v16, v18, v16 :: v_dual_cndmask_b32 v15, v15, v13
v_cndmask_b32_e32 v10, v14, v12, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v17, v11, s2
v_cndmask_b32_e64 v14, v16, v17, s2
v_cndmask_b32_e64 v11, v11, v15, s2
v_sub_nc_u32_e32 v16, 32, v6
v_cndmask_b32_e64 v15, v15, v10, s2
v_cndmask_b32_e64 v5, v10, v5, s2
v_cndmask_b32_e64 v14, v14, v12, s3
v_cndmask_b32_e64 v12, v12, v11, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v11, v11, v15, s3
v_cndmask_b32_e64 v5, v15, v5, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v17, v14, v12, v16
v_alignbit_b32 v13, v12, v11, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v15, v11, v5, v16
v_cndmask_b32_e32 v6, v17, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v10, v13, v12 :: v_dual_cndmask_b32 v11, v15, v11
v_bfe_u32 v12, v6, 29, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v13, v6, v10, 30
v_alignbit_b32 v10, v10, v11, 30
v_alignbit_b32 v5, v11, v5, 30
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v14, 0, v12
v_xor_b32_e32 v13, v13, v14
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v10, v10, v14
v_xor_b32_e32 v5, v5, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v15, v13
v_min_u32_e32 v15, 32, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v11, 31, v15
v_lshlrev_b32_e32 v17, 23, v15
v_alignbit_b32 v13, v13, v10, v11
v_alignbit_b32 v5, v10, v5, v11
v_lshrrev_b32_e32 v11, 29, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v10, v13, v5, 9
v_lshlrev_b32_e32 v11, 31, v11
v_lshrrev_b32_e32 v13, 9, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_clz_i32_u32_e32 v14, v10
v_or_b32_e32 v16, 0.5, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_u32_e32 v14, 32, v14
v_sub_nc_u32_e32 v16, v16, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v18, 31, v14
v_alignbit_b32 v5, v10, v5, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_or_b32_e32 v10, v13, v16
v_add_lshl_u32 v13, v14, v15, 23
v_lshrrev_b32_e32 v5, 9, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v14, 0x3fc90fda, v10
v_sub_nc_u32_e32 v5, v5, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v13, v10, 0x3fc90fda, -v14
v_add_nc_u32_e32 v5, 0x33000000, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmamk_f32 v10, v10, 0x33a22168, v13
v_or_b32_e32 v5, v5, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, 0x3fc90fda, v5
v_lshrrev_b32_e32 v5, 30, v6
v_dual_add_f32 v10, v14, v10 :: v_dual_add_nc_u32 v11, v12, v5
.LBB0_6:
s_or_saveexec_b32 s8, s8
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_xor_b32 exec_lo, exec_lo, s8
v_mul_f32_e64 v5, 0x3f22f983, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v5, v5
v_fma_f32 v6, v5, 0xbfc90fda, |v0|
v_cvt_i32_f32_e32 v11, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v6, v5, 0xb3a22168, v6
v_fmamk_f32 v10, v5, 0xa7c234c4, v6
s_or_b32 exec_lo, exec_lo, s8
s_load_b64 s[8:9], s[0:1], 0x28
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_dual_mul_f32 v15, v10, v10 :: v_dual_and_b32 v16, 1, v11
v_dual_mul_f32 v13, v8, v8 :: v_dual_and_b32 v14, 1, v9
v_xor_b32_e32 v7, v7, v0
v_lshlrev_b32_e32 v11, 30, v11
v_and_b32_e32 v11, 0x80000000, v11
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
s_mov_b32 s8, 0xb94c1982
s_mov_b32 s9, 0x37d75334
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_fmaak_f32 v20, s9, v15, 0xbab64f3b :: v_dual_lshlrev_b32 v9, 30, v9
global_load_b32 v12, v[5:6], off
v_fmaak_f32 v19, s8, v15, 0x3c0881c4
v_fmaak_f32 v18, s9, v13, 0xbab64f3b
v_cmp_eq_u32_e32 vcc_lo, 0, v14
v_fmaak_f32 v20, v15, v20, 0x3d2aabf7
v_and_b32_e32 v9, 0x80000000, v9
v_fmaak_f32 v19, v15, v19, 0xbe2aaa9d
v_fmaak_f32 v18, v13, v18, 0x3d2aabf7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmaak_f32 v20, v15, v20, 0xbf000004
v_mul_f32_e32 v19, v15, v19
v_fmaak_f32 v17, s8, v13, 0x3c0881c4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fmaak_f32 v18, v13, v18, 0xbf000004
v_fma_f32 v15, v15, v20, 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v10, v10, v19 :: v_dual_fmaak_f32 v17, v13, v17, 0xbe2aaa9d
v_mul_f32_e32 v17, v13, v17
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v13, v13, v18, 1.0
v_fmac_f32_e32 v8, v8, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v8, -v8, v13, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v16
v_xor_b32_e32 v8, v9, v8
v_cndmask_b32_e32 v10, v15, v10, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor3_b32 v7, v7, v11, v10
v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v7, 0x7fc00000, v7, vcc_lo
v_mul_f32_e32 v7, s3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, s2, v0
s_waitcnt vmcnt(0)
v_dual_add_f32 v0, v12, v7 :: v_dual_mov_b32 v7, 0
global_store_b32 v[5:6], v0, off
global_load_b32 v8, v[3:4], off
global_load_b32 v7, v7, s[4:5]
s_waitcnt vmcnt(1)
v_and_b32_e32 v9, 0x7fffffff, v8
v_cmp_ngt_f32_e64 s4, 0x48000000, |v8|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s4
s_xor_b32 s5, exec_lo, s2
s_cbranch_execz .LBB0_10
s_mov_b32 s2, 0x7fffff
v_mov_b32_e32 v12, 0
v_and_or_b32 v20, v9, s2, 0x800000
v_lshrrev_b32_e32 v17, 23, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[10:11], null, v20, 0xfe5163ab, 0
v_add_nc_u32_e32 v18, 0xffffff88, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v18
v_mad_u64_u32 v[13:14], null, v20, 0x3c439041, v[11:12]
v_cndmask_b32_e64 v19, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v11, v14
v_add_nc_u32_e32 v19, v19, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[14:15], null, v20, 0xdb629599, v[11:12]
v_cmp_lt_u32_e64 s2, 31, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v21, 0, 0xffffffe0, s2
v_dual_mov_b32 v11, v15 :: v_dual_cndmask_b32 v10, v14, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v21, v21, v19
v_mad_u64_u32 v[15:16], null, v20, 0xf534ddc0, v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v21
v_mov_b32_e32 v11, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v13, v15, v13, vcc_lo
v_mad_u64_u32 v[16:17], null, v20, 0xfc2757d1, v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v10, v13, v10, s2
v_mov_b32_e32 v11, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[17:18], null, v20, 0x4e441529, v[11:12]
v_mov_b32_e32 v11, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[18:19], null, v20, 0xa2f9836e, v[11:12]
v_cndmask_b32_e64 v11, 0, 0xffffffe0, s3
v_dual_cndmask_b32 v12, v17, v15 :: v_dual_add_nc_u32 v11, v11, v21
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v18, v18, v16 :: v_dual_cndmask_b32 v17, v19, v17
v_cndmask_b32_e32 v16, v16, v14, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v15, v18, v12, s2
v_cndmask_b32_e64 v17, v17, v18, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v12, v16, s2
v_sub_nc_u32_e32 v18, 32, v11
v_cndmask_b32_e64 v16, v16, v13, s2
v_cndmask_b32_e64 v17, v17, v15, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v15, v15, v12, s3
v_cndmask_b32_e64 v12, v12, v16, s3
v_cndmask_b32_e64 v10, v16, v10, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v19, v17, v15, v18
v_alignbit_b32 v14, v15, v12, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v11, v19, v17, vcc_lo
v_alignbit_b32 v17, v12, v10, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v13, v14, v15, vcc_lo
v_bfe_u32 v14, v11, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v12, v17, v12, vcc_lo
v_alignbit_b32 v15, v11, v13, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v16, 0, v14
v_alignbit_b32 v13, v13, v12, 30
v_alignbit_b32 v10, v12, v10, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v15, v15, v16
v_xor_b32_e32 v12, v13, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v10, v10, v16
v_clz_i32_u32_e32 v17, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v17, 32, v17
v_sub_nc_u32_e32 v13, 31, v17
v_lshlrev_b32_e32 v19, 23, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_alignbit_b32 v15, v15, v12, v13
v_alignbit_b32 v10, v12, v10, v13
v_lshrrev_b32_e32 v13, 29, v11
v_alignbit_b32 v12, v15, v10, 9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v13, 31, v13
v_lshrrev_b32_e32 v15, 9, v15
v_clz_i32_u32_e32 v16, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v18, 0.5, v13
v_min_u32_e32 v16, 32, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v18, v18, v19
v_sub_nc_u32_e32 v20, 31, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v10, v12, v10, v20
v_or_b32_e32 v12, v15, v18
v_add_lshl_u32 v15, v16, v17, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v10, 9, v10
v_mul_f32_e32 v16, 0x3fc90fda, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v10, v10, v15
v_fma_f32 v15, v12, 0x3fc90fda, -v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, 0x33000000, v10
v_fmamk_f32 v12, v12, 0x33a22168, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v10, v10, v13
v_fmac_f32_e32 v12, 0x3fc90fda, v10
v_lshrrev_b32_e32 v11, 30, v11
s_delay_alu instid0(VALU_DEP_1)
v_dual_add_f32 v10, v16, v12 :: v_dual_add_nc_u32 v11, v14, v11
.LBB0_10:
s_and_not1_saveexec_b32 s2, s5
v_mul_f32_e64 v10, 0x3f22f983, |v8|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v11, v10
v_fma_f32 v10, v11, 0xbfc90fda, |v8|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v10, v11, 0xb3a22168, v10
v_fmamk_f32 v10, v11, 0xa7c234c4, v10
v_cvt_i32_f32_e32 v11, v11
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v12, 0
global_load_b32 v12, v12, s[6:7]
s_and_saveexec_b32 s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s2
s_cbranch_execz .LBB0_14
s_mov_b32 s2, 0x7fffff
v_mov_b32_e32 v15, 0
v_and_or_b32 v23, v9, s2, 0x800000
v_lshrrev_b32_e32 v20, 23, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[13:14], null, v23, 0xfe5163ab, 0
v_add_nc_u32_e32 v21, 0xffffff88, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v21
v_mad_u64_u32 v[16:17], null, v23, 0x3c439041, v[14:15]
v_cndmask_b32_e64 v22, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v14, v17
v_add_nc_u32_e32 v22, v22, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[17:18], null, v23, 0xdb629599, v[14:15]
v_cmp_lt_u32_e64 s2, 31, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v24, 0, 0xffffffe0, s2
v_dual_mov_b32 v14, v18 :: v_dual_cndmask_b32 v13, v17, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v24, v24, v22
v_mad_u64_u32 v[18:19], null, v23, 0xf534ddc0, v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v24
v_mov_b32_e32 v14, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v16, v18, v16, vcc_lo
v_mad_u64_u32 v[19:20], null, v23, 0xfc2757d1, v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v13, v16, v13, s2
v_mov_b32_e32 v14, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[20:21], null, v23, 0x4e441529, v[14:15]
v_mov_b32_e32 v14, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[21:22], null, v23, 0xa2f9836e, v[14:15]
v_cndmask_b32_e64 v14, 0, 0xffffffe0, s3
v_dual_cndmask_b32 v15, v20, v18 :: v_dual_add_nc_u32 v14, v14, v24
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v21, v21, v19 :: v_dual_cndmask_b32 v20, v22, v20
v_cndmask_b32_e32 v19, v19, v17, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v18, v21, v15, s2
v_cndmask_b32_e64 v20, v20, v21, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v15, v15, v19, s2
v_sub_nc_u32_e32 v21, 32, v14
v_cndmask_b32_e64 v19, v19, v16, s2
v_cndmask_b32_e64 v20, v20, v18, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v18, v18, v15, s3
v_cndmask_b32_e64 v15, v15, v19, s3
v_cndmask_b32_e64 v13, v19, v13, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v22, v20, v18, v21
v_alignbit_b32 v17, v18, v15, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v14, v22, v20, vcc_lo
v_alignbit_b32 v20, v15, v13, v21
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v16, v17, v18, vcc_lo
v_bfe_u32 v17, v14, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v15, v20, v15, vcc_lo
v_alignbit_b32 v18, v14, v16, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v19, 0, v17
v_alignbit_b32 v16, v16, v15, 30
v_alignbit_b32 v13, v15, v13, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v18, v18, v19
v_xor_b32_e32 v15, v16, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v13, v13, v19
v_clz_i32_u32_e32 v20, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v20, 32, v20
v_sub_nc_u32_e32 v16, 31, v20
v_lshlrev_b32_e32 v22, 23, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_alignbit_b32 v18, v18, v15, v16
v_alignbit_b32 v13, v15, v13, v16
v_lshrrev_b32_e32 v16, 29, v14
v_alignbit_b32 v15, v18, v13, 9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v16, 31, v16
v_lshrrev_b32_e32 v18, 9, v18
v_clz_i32_u32_e32 v19, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v21, 0.5, v16
v_min_u32_e32 v19, 32, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v21, v21, v22
v_sub_nc_u32_e32 v23, 31, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v13, v15, v13, v23
v_or_b32_e32 v15, v18, v21
v_add_lshl_u32 v18, v19, v20, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v13, 9, v13
v_mul_f32_e32 v19, 0x3fc90fda, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v13, v13, v18
v_fma_f32 v18, v15, 0x3fc90fda, -v19
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v13, 0x33000000, v13
v_fmamk_f32 v15, v15, 0x33a22168, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v13, v13, v16
v_fmac_f32_e32 v15, 0x3fc90fda, v13
v_lshrrev_b32_e32 v14, 30, v14
s_delay_alu instid0(VALU_DEP_1)
v_dual_add_f32 v13, v19, v15 :: v_dual_add_nc_u32 v14, v17, v14
.LBB0_14:
s_and_not1_saveexec_b32 s2, s4
v_mul_f32_e64 v13, 0x3f22f983, |v8|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v14, v13
v_fma_f32 v13, v14, 0xbfc90fda, |v8|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v13, v14, 0xb3a22168, v13
v_fmamk_f32 v13, v14, 0xa7c234c4, v13
v_cvt_i32_f32_e32 v14, v14
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mul_f32 v15, v10, v10 :: v_dual_mul_f32 v16, v13, v13
s_mov_b32 s3, 0xb94c1982
s_mov_b32 s2, 0x37d75334
v_lshlrev_b32_e32 v20, 30, v11
v_dual_fmaak_f32 v18, s3, v15, 0x3c0881c4 :: v_dual_fmaak_f32 v19, s3, v16, 0x3c0881c4
v_fmaak_f32 v21, s2, v16, 0xbab64f3b
v_and_b32_e32 v11, 1, v11
v_xor_b32_e32 v9, v9, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_dual_fmaak_f32 v18, v15, v18, 0xbe2aaa9d :: v_dual_fmaak_f32 v19, v16, v19, 0xbe2aaa9d
v_fmaak_f32 v17, s2, v15, 0xbab64f3b
v_fmaak_f32 v21, v16, v21, 0x3d2aabf7
v_cmp_eq_u32_e32 vcc_lo, 0, v11
v_dual_mul_f32 v18, v15, v18 :: v_dual_mul_f32 v19, v16, v19
v_and_b32_e32 v20, 0x80000000, v20
v_fmaak_f32 v17, v15, v17, 0x3d2aabf7
s_mov_b32 s3, 0x3f91df45
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v10, v10, v18 :: v_dual_fmac_f32 v13, v13, v19
s_mov_b32 s2, 0xa50de270
v_fmaak_f32 v17, v15, v17, 0xbf000004
s_load_b64 s[0:1], s[0:1], 0x48
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f32 v15, v15, v17, 1.0
v_and_b32_e32 v17, 1, v14
v_dual_fmaak_f32 v21, v16, v21, 0xbf000004 :: v_dual_lshlrev_b32 v14, 30, v14
v_cndmask_b32_e64 v10, -v10, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v17
v_fma_f32 v16, v16, v21, 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v10, v20, v10
v_cndmask_b32_e32 v11, v16, v13, vcc_lo
v_and_b32_e32 v13, 0x80000000, v14
v_cmp_class_f32_e64 vcc_lo, v8, 0x1f8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor3_b32 v9, v9, v13, v11
v_cndmask_b32_e32 v8, 0x7fc00000, v10, vcc_lo
v_cndmask_b32_e32 v9, 0x7fc00000, v9, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, v12, v9
v_fmac_f32_e32 v9, v7, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v0, v9
global_store_b32 v[5:6], v0, off
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[5:6], v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_f64 v[5:6], v[5:6], s[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v5, v[5:6]
global_store_b32 v[3:4], v5, off
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16pf_iteration_devPiPfS0_S0_S0_S0_S0_S0_S_S0_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 352
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 25
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16pf_iteration_devPiPfS0_S0_S0_S0_S0_S0_S_S0_S_S_, .Lfunc_end0-_Z16pf_iteration_devPiPfS0_S0_S0_S0_S0_S0_S_S0_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 88
.size: 8
.value_kind: global_buffer
- .offset: 96
.size: 4
.value_kind: hidden_block_count_x
- .offset: 100
.size: 4
.value_kind: hidden_block_count_y
- .offset: 104
.size: 4
.value_kind: hidden_block_count_z
- .offset: 108
.size: 2
.value_kind: hidden_group_size_x
- .offset: 110
.size: 2
.value_kind: hidden_group_size_y
- .offset: 112
.size: 2
.value_kind: hidden_group_size_z
- .offset: 114
.size: 2
.value_kind: hidden_remainder_x
- .offset: 116
.size: 2
.value_kind: hidden_remainder_y
- .offset: 118
.size: 2
.value_kind: hidden_remainder_z
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 152
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 160
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 352
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16pf_iteration_devPiPfS0_S0_S0_S0_S0_S0_S_S0_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16pf_iteration_devPiPfS0_S0_S0_S0_S0_S0_S_S0_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 25
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "device.cuh"
__global__
void fill_array(double *d_A){
for (int i=0; i<1000; i++){
d_A[i] = i;
}
}
__global__
void fill_c_array(thrust::complex<double> *d_A){
for (int i=0; i<1000; i++){
d_A[i] = i;
}
}
thrust::device_vector<thrust::complex<double>> d_vec_A;
void get_cuda_array_ptr(double **array_ptr){
double *d_A = NULL;
cudaMalloc ((void**)&d_A, sizeof(double) * 1000);
fill_array<<<1,1>>>(d_A);
*array_ptr = d_A;
}
void get_cuda_c_array_ptr(std::complex<double> **array_ptr){
thrust::complex<double> *d_A = NULL;
cudaMalloc ((void**)&d_A, sizeof(thrust::complex<double>) * 1000);
fill_c_array<<<1,1>>>(d_A);
*array_ptr = reinterpret_cast<std::complex<double>*>(d_A);
}
void get_cuda_thrust_vector_ptr(std::complex<double> **array_ptr){
d_vec_A.resize(1000);
fill_c_array<<<1,1>>>(thrust::raw_pointer_cast(&d_vec_A[0]));
*array_ptr = reinterpret_cast<std::complex<double>*>( thrust::raw_pointer_cast(&d_vec_A[0]) );
}
void use_cuda_array_and_check(double *array_ptr){
double *h_A = new double [1000];
cudaMemcpy(h_A, array_ptr, sizeof(double) * 1000, cudaMemcpyDeviceToHost);
for (int i=0; i<10; i++){
std::cout << h_A[i] << std::endl;
}
}
void use_cuda_c_array_and_check(std::complex<double> *array_ptr){
std::complex<double> *h_A = new std::complex<double> [1000];
cudaMemcpy(h_A, array_ptr, sizeof(std::complex<double>) * 1000, cudaMemcpyDeviceToHost);
for (int i=0; i<10; i++){
std::cout << h_A[i] << std::endl;
}
} | #ifndef DEVICE_CUH
#define DEVICE_CUH
#include <iostream>
#include <complex>
#include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/complex.h>
void get_cuda_array_ptr(double **array_ptr);
void get_cuda_c_array_ptr(std::complex<double> **array_ptr);
void get_cuda_thrust_vector_ptr(std::complex<double> **array_ptr);
void use_cuda_array_and_check(double *array_ptr);
void use_cuda_c_array_and_check(std::complex<double> *array_ptr);
#endif // DEVICE_CUH |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef DEVICE_CUH
#define DEVICE_CUH
#include <iostream>
#include <complex>
#include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/complex.h>
void get_cuda_array_ptr(double **array_ptr);
void get_cuda_c_array_ptr(std::complex<double> **array_ptr);
void get_cuda_thrust_vector_ptr(std::complex<double> **array_ptr);
void use_cuda_array_and_check(double *array_ptr);
void use_cuda_c_array_and_check(std::complex<double> *array_ptr);
#endif // DEVICE_CUH | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef DEVICE_CUH
#define DEVICE_CUH
#include <iostream>
#include <complex>
#include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/complex.h>
void get_cuda_array_ptr(double **array_ptr);
void get_cuda_c_array_ptr(std::complex<double> **array_ptr);
void get_cuda_thrust_vector_ptr(std::complex<double> **array_ptr);
void use_cuda_array_and_check(double *array_ptr);
void use_cuda_c_array_and_check(std::complex<double> *array_ptr);
#endif // DEVICE_CUH | .text
.file "device.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void set_d_check_nnz(int *d_check_nnz, int *d_nnz_num, int pad_M, int SIGMA, int sigma_block_row)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= pad_M) {
return;
}
int a = 1;
if (d_nnz_num[blockIdx.y * pad_M + i] > 0) {
atomicAdd(&(d_check_nnz[blockIdx.y * sigma_block_row + i / SIGMA]), a);
}
} | code for sm_80
Function : _Z15set_d_check_nnzPiS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0070*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD R2, R5, c[0x0][0x170], R0 ; /* 0x00005c0005027a24 */
/* 0x001fc800078e0200 */
/*00a0*/ IMAD.WIDE.U32 R2, R2, R6, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0006 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f06270 */
/*00d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00e0*/ IABS R7, c[0x0][0x174] ; /* 0x00005d0000077a13 */
/* 0x000fc80000000000 */
/*00f0*/ I2F.RP R4, R7 ; /* 0x0000000700047306 */
/* 0x000e300000209400 */
/*0100*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*0140*/ IADD3 R8, RZ, -R3, RZ ; /* 0x80000003ff087210 */
/* 0x002fca0007ffe0ff */
/*0150*/ IMAD R9, R8, R7, RZ ; /* 0x0000000708097224 */
/* 0x000fe200078e02ff */
/*0160*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fe40000000000 */
/*0170*/ LOP3.LUT R0, R0, c[0x0][0x174], RZ, 0x3c, !PT ; /* 0x00005d0000007a12 */
/* 0x000fe200078e3cff */
/*0180*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fc600078e0002 */
/*0190*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f26270 */
/*01a0*/ IMAD.HI.U32 R3, R3, R8, RZ ; /* 0x0000000803037227 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*01c0*/ IMAD R4, R7, R4, R8 ; /* 0x0000000407047224 */
/* 0x000fca00078e0208 */
/*01d0*/ ISETP.GT.U32.AND P2, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fda0003f44070 */
/*01e0*/ @!P2 IADD3 R4, R4, -R7.reuse, RZ ; /* 0x800000070404a210 */
/* 0x080fe40007ffe0ff */
/*01f0*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fe40003f06070 */
/*0210*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fd60003f45270 */
/*0220*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0230*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*0240*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff03aa12 */
/* 0x000fca00078e33ff */
/*0250*/ IMAD R3, R5, c[0x0][0x178], R3 ; /* 0x00005e0005037a24 */
/* 0x000fe200078e0203 */
/*0260*/ HFMA2.MMA R5, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff057435 */
/* 0x000fc600000001ff */
/*0270*/ IMAD.WIDE.U32 R2, R3, R6, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0006 */
/*0280*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e184 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void set_d_check_nnz(int *d_check_nnz, int *d_nnz_num, int pad_M, int SIGMA, int sigma_block_row)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= pad_M) {
return;
}
int a = 1;
if (d_nnz_num[blockIdx.y * pad_M + i] > 0) {
atomicAdd(&(d_check_nnz[blockIdx.y * sigma_block_row + i / SIGMA]), a);
}
} | .file "tmpxft_00196b65_00000000-6_set_d_check_nnz.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z15set_d_check_nnzPiS_iiiPiS_iii
.type _Z40__device_stub__Z15set_d_check_nnzPiS_iiiPiS_iii, @function
_Z40__device_stub__Z15set_d_check_nnzPiS_iiiPiS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15set_d_check_nnzPiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z15set_d_check_nnzPiS_iiiPiS_iii, .-_Z40__device_stub__Z15set_d_check_nnzPiS_iiiPiS_iii
.globl _Z15set_d_check_nnzPiS_iii
.type _Z15set_d_check_nnzPiS_iii, @function
_Z15set_d_check_nnzPiS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15set_d_check_nnzPiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15set_d_check_nnzPiS_iii, .-_Z15set_d_check_nnzPiS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15set_d_check_nnzPiS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15set_d_check_nnzPiS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void set_d_check_nnz(int *d_check_nnz, int *d_nnz_num, int pad_M, int SIGMA, int sigma_block_row)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= pad_M) {
return;
}
int a = 1;
if (d_nnz_num[blockIdx.y * pad_M + i] > 0) {
atomicAdd(&(d_check_nnz[blockIdx.y * sigma_block_row + i / SIGMA]), a);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void set_d_check_nnz(int *d_check_nnz, int *d_nnz_num, int pad_M, int SIGMA, int sigma_block_row)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= pad_M) {
return;
}
int a = 1;
if (d_nnz_num[blockIdx.y * pad_M + i] > 0) {
atomicAdd(&(d_check_nnz[blockIdx.y * sigma_block_row + i / SIGMA]), a);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void set_d_check_nnz(int *d_check_nnz, int *d_nnz_num, int pad_M, int SIGMA, int sigma_block_row)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= pad_M) {
return;
}
int a = 1;
if (d_nnz_num[blockIdx.y * pad_M + i] > 0) {
atomicAdd(&(d_check_nnz[blockIdx.y * sigma_block_row + i / SIGMA]), a);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15set_d_check_nnzPiS_iii
.globl _Z15set_d_check_nnzPiS_iii
.p2align 8
.type _Z15set_d_check_nnzPiS_iii,@function
_Z15set_d_check_nnzPiS_iii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s14, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_mov_b32_e32 v1, 0
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x14
v_ashrrev_i32_e32 v4, 31, v2
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v4
v_xor_b32_e32 v2, v2, v4
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s4
v_xor_b32_e32 v4, s4, v4
s_xor_b32 s2, s2, s4
v_cvt_f32_u32_e32 v0, s2
s_sub_i32 s5, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s5, v0
v_mul_hi_u32 v3, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v3
v_mul_hi_u32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s2
v_sub_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
v_dual_cndmask_b32 v2, v2, v5 :: v_dual_add_nc_u32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, 1, v0
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v4
v_sub_nc_u32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
v_mov_b32_e32 v3, v1
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_mov_b32_e32 v2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15set_d_check_nnzPiS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15set_d_check_nnzPiS_iii, .Lfunc_end0-_Z15set_d_check_nnzPiS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15set_d_check_nnzPiS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15set_d_check_nnzPiS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void set_d_check_nnz(int *d_check_nnz, int *d_nnz_num, int pad_M, int SIGMA, int sigma_block_row)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= pad_M) {
return;
}
int a = 1;
if (d_nnz_num[blockIdx.y * pad_M + i] > 0) {
atomicAdd(&(d_check_nnz[blockIdx.y * sigma_block_row + i / SIGMA]), a);
}
} | .text
.file "set_d_check_nnz.hip"
.globl _Z30__device_stub__set_d_check_nnzPiS_iii # -- Begin function _Z30__device_stub__set_d_check_nnzPiS_iii
.p2align 4, 0x90
.type _Z30__device_stub__set_d_check_nnzPiS_iii,@function
_Z30__device_stub__set_d_check_nnzPiS_iii: # @_Z30__device_stub__set_d_check_nnzPiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15set_d_check_nnzPiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__set_d_check_nnzPiS_iii, .Lfunc_end0-_Z30__device_stub__set_d_check_nnzPiS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15set_d_check_nnzPiS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15set_d_check_nnzPiS_iii,@object # @_Z15set_d_check_nnzPiS_iii
.section .rodata,"a",@progbits
.globl _Z15set_d_check_nnzPiS_iii
.p2align 3, 0x0
_Z15set_d_check_nnzPiS_iii:
.quad _Z30__device_stub__set_d_check_nnzPiS_iii
.size _Z15set_d_check_nnzPiS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15set_d_check_nnzPiS_iii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__set_d_check_nnzPiS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15set_d_check_nnzPiS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15set_d_check_nnzPiS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0070*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD R2, R5, c[0x0][0x170], R0 ; /* 0x00005c0005027a24 */
/* 0x001fc800078e0200 */
/*00a0*/ IMAD.WIDE.U32 R2, R2, R6, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0006 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f06270 */
/*00d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00e0*/ IABS R7, c[0x0][0x174] ; /* 0x00005d0000077a13 */
/* 0x000fc80000000000 */
/*00f0*/ I2F.RP R4, R7 ; /* 0x0000000700047306 */
/* 0x000e300000209400 */
/*0100*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*0140*/ IADD3 R8, RZ, -R3, RZ ; /* 0x80000003ff087210 */
/* 0x002fca0007ffe0ff */
/*0150*/ IMAD R9, R8, R7, RZ ; /* 0x0000000708097224 */
/* 0x000fe200078e02ff */
/*0160*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fe40000000000 */
/*0170*/ LOP3.LUT R0, R0, c[0x0][0x174], RZ, 0x3c, !PT ; /* 0x00005d0000007a12 */
/* 0x000fe200078e3cff */
/*0180*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fc600078e0002 */
/*0190*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f26270 */
/*01a0*/ IMAD.HI.U32 R3, R3, R8, RZ ; /* 0x0000000803037227 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*01c0*/ IMAD R4, R7, R4, R8 ; /* 0x0000000407047224 */
/* 0x000fca00078e0208 */
/*01d0*/ ISETP.GT.U32.AND P2, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fda0003f44070 */
/*01e0*/ @!P2 IADD3 R4, R4, -R7.reuse, RZ ; /* 0x800000070404a210 */
/* 0x080fe40007ffe0ff */
/*01f0*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fe40003f06070 */
/*0210*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fd60003f45270 */
/*0220*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0230*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*0240*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff03aa12 */
/* 0x000fca00078e33ff */
/*0250*/ IMAD R3, R5, c[0x0][0x178], R3 ; /* 0x00005e0005037a24 */
/* 0x000fe200078e0203 */
/*0260*/ HFMA2.MMA R5, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff057435 */
/* 0x000fc600000001ff */
/*0270*/ IMAD.WIDE.U32 R2, R3, R6, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0006 */
/*0280*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e184 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15set_d_check_nnzPiS_iii
.globl _Z15set_d_check_nnzPiS_iii
.p2align 8
.type _Z15set_d_check_nnzPiS_iii,@function
_Z15set_d_check_nnzPiS_iii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s14, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_mov_b32_e32 v1, 0
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x14
v_ashrrev_i32_e32 v4, 31, v2
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v4
v_xor_b32_e32 v2, v2, v4
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s4
v_xor_b32_e32 v4, s4, v4
s_xor_b32 s2, s2, s4
v_cvt_f32_u32_e32 v0, s2
s_sub_i32 s5, 0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s5, v0
v_mul_hi_u32 v3, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v3
v_mul_hi_u32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s2
v_sub_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
v_dual_cndmask_b32 v2, v2, v5 :: v_dual_add_nc_u32 v3, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, 1, v0
v_cndmask_b32_e32 v0, v0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v4
v_sub_nc_u32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
v_mov_b32_e32 v3, v1
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_mov_b32_e32 v2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15set_d_check_nnzPiS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15set_d_check_nnzPiS_iii, .Lfunc_end0-_Z15set_d_check_nnzPiS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15set_d_check_nnzPiS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15set_d_check_nnzPiS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00196b65_00000000-6_set_d_check_nnz.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z15set_d_check_nnzPiS_iiiPiS_iii
.type _Z40__device_stub__Z15set_d_check_nnzPiS_iiiPiS_iii, @function
_Z40__device_stub__Z15set_d_check_nnzPiS_iiiPiS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15set_d_check_nnzPiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z15set_d_check_nnzPiS_iiiPiS_iii, .-_Z40__device_stub__Z15set_d_check_nnzPiS_iiiPiS_iii
.globl _Z15set_d_check_nnzPiS_iii
.type _Z15set_d_check_nnzPiS_iii, @function
_Z15set_d_check_nnzPiS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15set_d_check_nnzPiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15set_d_check_nnzPiS_iii, .-_Z15set_d_check_nnzPiS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15set_d_check_nnzPiS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15set_d_check_nnzPiS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "set_d_check_nnz.hip"
.globl _Z30__device_stub__set_d_check_nnzPiS_iii # -- Begin function _Z30__device_stub__set_d_check_nnzPiS_iii
.p2align 4, 0x90
.type _Z30__device_stub__set_d_check_nnzPiS_iii,@function
_Z30__device_stub__set_d_check_nnzPiS_iii: # @_Z30__device_stub__set_d_check_nnzPiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15set_d_check_nnzPiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__set_d_check_nnzPiS_iii, .Lfunc_end0-_Z30__device_stub__set_d_check_nnzPiS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15set_d_check_nnzPiS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15set_d_check_nnzPiS_iii,@object # @_Z15set_d_check_nnzPiS_iii
.section .rodata,"a",@progbits
.globl _Z15set_d_check_nnzPiS_iii
.p2align 3, 0x0
_Z15set_d_check_nnzPiS_iii:
.quad _Z30__device_stub__set_d_check_nnzPiS_iii
.size _Z15set_d_check_nnzPiS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15set_d_check_nnzPiS_iii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__set_d_check_nnzPiS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15set_d_check_nnzPiS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cuda_accumulate_occ(float * device_mapOcc, int numObjs, int numClusters, int clusterStart, int sub_numClusters, float *device_reduceOcc) {
int objIndex = blockDim.x * blockIdx.x + threadIdx.x;
extern __shared__ float shared_objects[];
if(objIndex < numObjs) {
for(int i = 0;i < sub_numClusters; i++)
// for(int i = clusterStart + sub_numClusters - 1;i >= clusterStart; i--)
shared_objects[threadIdx.x * sub_numClusters + i] = device_mapOcc[objIndex * numClusters + i + clusterStart];
}
else {
for(int i = 0;i < sub_numClusters; i++)
//for(int i = clusterStart + sub_numClusters - 1;i >= clusterStart; i--)
shared_objects[threadIdx.x * sub_numClusters + i] = 0;
}
__syncthreads();
for(int i = (blockDim.x >> 1); i >= 1; i>>=1) {
if(threadIdx.x < i) {
for(int j = 0;j < sub_numClusters; j++) {
//for(int j = clusterStart + sub_numClusters - 1;j >= clusterStart; j--)
shared_objects[threadIdx.x * sub_numClusters + j] += shared_objects[(threadIdx.x + i) * sub_numClusters + j];
}
}
__syncthreads();
}
if(threadIdx.x == 0) {
for(int i = 0;i < sub_numClusters;i++) {
// for(int i = clusterStart + sub_numClusters - 1;i >= clusterStart; i--)
device_reduceOcc[blockIdx.x * numClusters + i + clusterStart] = shared_objects[i];
}
}
} | .file "tmpxft_00010661_00000000-6_cuda_accumulate_occ.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z19cuda_accumulate_occPfiiiiS_PfiiiiS_
.type _Z45__device_stub__Z19cuda_accumulate_occPfiiiiS_PfiiiiS_, @function
_Z45__device_stub__Z19cuda_accumulate_occPfiiiiS_PfiiiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19cuda_accumulate_occPfiiiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z19cuda_accumulate_occPfiiiiS_PfiiiiS_, .-_Z45__device_stub__Z19cuda_accumulate_occPfiiiiS_PfiiiiS_
.globl _Z19cuda_accumulate_occPfiiiiS_
.type _Z19cuda_accumulate_occPfiiiiS_, @function
_Z19cuda_accumulate_occPfiiiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z19cuda_accumulate_occPfiiiiS_PfiiiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19cuda_accumulate_occPfiiiiS_, .-_Z19cuda_accumulate_occPfiiiiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19cuda_accumulate_occPfiiiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19cuda_accumulate_occPfiiiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cuda_accumulate_occ(float * device_mapOcc, int numObjs, int numClusters, int clusterStart, int sub_numClusters, float *device_reduceOcc) {
int objIndex = blockDim.x * blockIdx.x + threadIdx.x;
extern __shared__ float shared_objects[];
if(objIndex < numObjs) {
for(int i = 0;i < sub_numClusters; i++)
// for(int i = clusterStart + sub_numClusters - 1;i >= clusterStart; i--)
shared_objects[threadIdx.x * sub_numClusters + i] = device_mapOcc[objIndex * numClusters + i + clusterStart];
}
else {
for(int i = 0;i < sub_numClusters; i++)
//for(int i = clusterStart + sub_numClusters - 1;i >= clusterStart; i--)
shared_objects[threadIdx.x * sub_numClusters + i] = 0;
}
__syncthreads();
for(int i = (blockDim.x >> 1); i >= 1; i>>=1) {
if(threadIdx.x < i) {
for(int j = 0;j < sub_numClusters; j++) {
//for(int j = clusterStart + sub_numClusters - 1;j >= clusterStart; j--)
shared_objects[threadIdx.x * sub_numClusters + j] += shared_objects[(threadIdx.x + i) * sub_numClusters + j];
}
}
__syncthreads();
}
if(threadIdx.x == 0) {
for(int i = 0;i < sub_numClusters;i++) {
// for(int i = clusterStart + sub_numClusters - 1;i >= clusterStart; i--)
device_reduceOcc[blockIdx.x * numClusters + i + clusterStart] = shared_objects[i];
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_accumulate_occ(float * device_mapOcc, int numObjs, int numClusters, int clusterStart, int sub_numClusters, float *device_reduceOcc) {
int objIndex = blockDim.x * blockIdx.x + threadIdx.x;
extern __shared__ float shared_objects[];
if(objIndex < numObjs) {
for(int i = 0;i < sub_numClusters; i++)
// for(int i = clusterStart + sub_numClusters - 1;i >= clusterStart; i--)
shared_objects[threadIdx.x * sub_numClusters + i] = device_mapOcc[objIndex * numClusters + i + clusterStart];
}
else {
for(int i = 0;i < sub_numClusters; i++)
//for(int i = clusterStart + sub_numClusters - 1;i >= clusterStart; i--)
shared_objects[threadIdx.x * sub_numClusters + i] = 0;
}
__syncthreads();
for(int i = (blockDim.x >> 1); i >= 1; i>>=1) {
if(threadIdx.x < i) {
for(int j = 0;j < sub_numClusters; j++) {
//for(int j = clusterStart + sub_numClusters - 1;j >= clusterStart; j--)
shared_objects[threadIdx.x * sub_numClusters + j] += shared_objects[(threadIdx.x + i) * sub_numClusters + j];
}
}
__syncthreads();
}
if(threadIdx.x == 0) {
for(int i = 0;i < sub_numClusters;i++) {
// for(int i = clusterStart + sub_numClusters - 1;i >= clusterStart; i--)
device_reduceOcc[blockIdx.x * numClusters + i + clusterStart] = shared_objects[i];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_accumulate_occ(float * device_mapOcc, int numObjs, int numClusters, int clusterStart, int sub_numClusters, float *device_reduceOcc) {
int objIndex = blockDim.x * blockIdx.x + threadIdx.x;
extern __shared__ float shared_objects[];
if(objIndex < numObjs) {
for(int i = 0;i < sub_numClusters; i++)
// for(int i = clusterStart + sub_numClusters - 1;i >= clusterStart; i--)
shared_objects[threadIdx.x * sub_numClusters + i] = device_mapOcc[objIndex * numClusters + i + clusterStart];
}
else {
for(int i = 0;i < sub_numClusters; i++)
//for(int i = clusterStart + sub_numClusters - 1;i >= clusterStart; i--)
shared_objects[threadIdx.x * sub_numClusters + i] = 0;
}
__syncthreads();
for(int i = (blockDim.x >> 1); i >= 1; i>>=1) {
if(threadIdx.x < i) {
for(int j = 0;j < sub_numClusters; j++) {
//for(int j = clusterStart + sub_numClusters - 1;j >= clusterStart; j--)
shared_objects[threadIdx.x * sub_numClusters + j] += shared_objects[(threadIdx.x + i) * sub_numClusters + j];
}
}
__syncthreads();
}
if(threadIdx.x == 0) {
for(int i = 0;i < sub_numClusters;i++) {
// for(int i = clusterStart + sub_numClusters - 1;i >= clusterStart; i--)
device_reduceOcc[blockIdx.x * numClusters + i + clusterStart] = shared_objects[i];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19cuda_accumulate_occPfiiiiS_
.globl _Z19cuda_accumulate_occPfiiiiS_
.p2align 8
.type _Z19cuda_accumulate_occPfiiiiS_,@function
_Z19cuda_accumulate_occPfiiiiS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s6, s[0:1], 0x14
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s2, 0xffff
s_cmp_gt_i32 s6, 0
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, 0, 1, s2
s_mov_b32 s2, exec_lo
v_cmpx_le_i32_e64 s3, v1
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_4
v_cmp_ne_u32_e32 vcc_lo, 1, v3
s_cbranch_vccnz .LBB0_4
v_mul_lo_u32 v1, v0, s6
v_mov_b32_e32 v5, 0
s_mov_b32 s3, s6
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v4, v1, 2, 0
.LBB0_3:
ds_store_b32 v4, v5
v_add_nc_u32_e32 v4, 4, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s3, 0
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_or_saveexec_b32 s8, s2
s_load_b64 s[2:3], s[0:1], 0xc
s_xor_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_8
v_cmp_ne_u32_e32 vcc_lo, 1, v3
s_cbranch_vccnz .LBB0_8
s_load_b64 s[4:5], s[0:1], 0x0
v_mul_lo_u32 v4, v0, s6
s_waitcnt lgkmcnt(0)
s_mov_b32 s10, s3
s_mov_b32 s9, s6
v_mad_u64_u32 v[2:3], null, v1, s2, s[10:11]
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v1, v4, 2, 0
.LBB0_7:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s9, s9, -1
s_cmp_eq_u32 s9, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_nc_u32_e32 v2, 1, v2
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_b32 v1, v3
v_add_nc_u32_e32 v1, 4, v1
s_cbranch_scc0 .LBB0_7
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s8
s_cmp_lt_u32 s7, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_14
v_mul_lo_u32 v1, v0, s6
s_cmp_lt_i32 s6, 1
s_mov_b32 s4, 0
s_cselect_b32 s8, -1, 0
s_lshl_b32 s5, s6, 2
s_xor_b32 s8, s8, -1
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v3, v1, 2, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_11
.p2align 6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s10
s_cmp_lt_u32 s7, 4
s_mov_b32 s7, s9
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_14
.LBB0_11:
s_lshr_b32 s9, s7, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s9, v0
s_and_b32 s11, vcc_lo, s8
s_and_saveexec_b32 s10, s11
s_cbranch_execz .LBB0_10
v_add_nc_u32_e32 v4, s9, v0
s_mov_b32 s11, s6
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s5, v4, s[4:5]
v_mov_b32_e32 v2, v3
.LBB0_13:
ds_load_b32 v4, v1
ds_load_b32 v5, v2
v_add_nc_u32_e32 v1, 4, v1
s_add_i32 s11, s11, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s11, 0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v4, v4, v5
ds_store_b32 v2, v4
v_add_nc_u32_e32 v2, 4, v2
s_cbranch_scc1 .LBB0_13
s_branch .LBB0_10
.LBB0_14:
s_set_inst_prefetch_distance 0x2
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_cmp_gt_i32 s6, 0
s_mov_b32 s5, 0
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s4, vcc_lo, s4
s_and_saveexec_b32 s7, s4
s_cbranch_execz .LBB0_17
s_load_b64 s[0:1], s[0:1], 0x18
v_mov_b32_e32 v0, 0
s_mul_i32 s15, s15, s2
s_mov_b32 s2, s5
s_add_i32 s4, s3, s15
.LBB0_16:
v_mov_b32_e32 v1, s2
s_lshl_b64 s[8:9], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s0, s8
s_addc_u32 s9, s1, s9
ds_load_b32 v1, v1
s_add_i32 s6, s6, -1
s_add_i32 s2, s2, 4
s_add_i32 s4, s4, 1
s_cmp_lg_u32 s6, 0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[8:9]
s_cbranch_scc1 .LBB0_16
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19cuda_accumulate_occPfiiiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19cuda_accumulate_occPfiiiiS_, .Lfunc_end0-_Z19cuda_accumulate_occPfiiiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19cuda_accumulate_occPfiiiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19cuda_accumulate_occPfiiiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_accumulate_occ(float * device_mapOcc, int numObjs, int numClusters, int clusterStart, int sub_numClusters, float *device_reduceOcc) {
int objIndex = blockDim.x * blockIdx.x + threadIdx.x;
extern __shared__ float shared_objects[];
if(objIndex < numObjs) {
for(int i = 0;i < sub_numClusters; i++)
// for(int i = clusterStart + sub_numClusters - 1;i >= clusterStart; i--)
shared_objects[threadIdx.x * sub_numClusters + i] = device_mapOcc[objIndex * numClusters + i + clusterStart];
}
else {
for(int i = 0;i < sub_numClusters; i++)
//for(int i = clusterStart + sub_numClusters - 1;i >= clusterStart; i--)
shared_objects[threadIdx.x * sub_numClusters + i] = 0;
}
__syncthreads();
for(int i = (blockDim.x >> 1); i >= 1; i>>=1) {
if(threadIdx.x < i) {
for(int j = 0;j < sub_numClusters; j++) {
//for(int j = clusterStart + sub_numClusters - 1;j >= clusterStart; j--)
shared_objects[threadIdx.x * sub_numClusters + j] += shared_objects[(threadIdx.x + i) * sub_numClusters + j];
}
}
__syncthreads();
}
if(threadIdx.x == 0) {
for(int i = 0;i < sub_numClusters;i++) {
// for(int i = clusterStart + sub_numClusters - 1;i >= clusterStart; i--)
device_reduceOcc[blockIdx.x * numClusters + i + clusterStart] = shared_objects[i];
}
}
} | .text
.file "cuda_accumulate_occ.hip"
.globl _Z34__device_stub__cuda_accumulate_occPfiiiiS_ # -- Begin function _Z34__device_stub__cuda_accumulate_occPfiiiiS_
.p2align 4, 0x90
.type _Z34__device_stub__cuda_accumulate_occPfiiiiS_,@function
_Z34__device_stub__cuda_accumulate_occPfiiiiS_: # @_Z34__device_stub__cuda_accumulate_occPfiiiiS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %r9, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19cuda_accumulate_occPfiiiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z34__device_stub__cuda_accumulate_occPfiiiiS_, .Lfunc_end0-_Z34__device_stub__cuda_accumulate_occPfiiiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19cuda_accumulate_occPfiiiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19cuda_accumulate_occPfiiiiS_,@object # @_Z19cuda_accumulate_occPfiiiiS_
.section .rodata,"a",@progbits
.globl _Z19cuda_accumulate_occPfiiiiS_
.p2align 3, 0x0
_Z19cuda_accumulate_occPfiiiiS_:
.quad _Z34__device_stub__cuda_accumulate_occPfiiiiS_
.size _Z19cuda_accumulate_occPfiiiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19cuda_accumulate_occPfiiiiS_"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__cuda_accumulate_occPfiiiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19cuda_accumulate_occPfiiiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00010661_00000000-6_cuda_accumulate_occ.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z19cuda_accumulate_occPfiiiiS_PfiiiiS_
.type _Z45__device_stub__Z19cuda_accumulate_occPfiiiiS_PfiiiiS_, @function
_Z45__device_stub__Z19cuda_accumulate_occPfiiiiS_PfiiiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19cuda_accumulate_occPfiiiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z19cuda_accumulate_occPfiiiiS_PfiiiiS_, .-_Z45__device_stub__Z19cuda_accumulate_occPfiiiiS_PfiiiiS_
.globl _Z19cuda_accumulate_occPfiiiiS_
.type _Z19cuda_accumulate_occPfiiiiS_, @function
_Z19cuda_accumulate_occPfiiiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z19cuda_accumulate_occPfiiiiS_PfiiiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19cuda_accumulate_occPfiiiiS_, .-_Z19cuda_accumulate_occPfiiiiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19cuda_accumulate_occPfiiiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19cuda_accumulate_occPfiiiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_accumulate_occ.hip"
.globl _Z34__device_stub__cuda_accumulate_occPfiiiiS_ # -- Begin function _Z34__device_stub__cuda_accumulate_occPfiiiiS_
.p2align 4, 0x90
.type _Z34__device_stub__cuda_accumulate_occPfiiiiS_,@function
_Z34__device_stub__cuda_accumulate_occPfiiiiS_: # @_Z34__device_stub__cuda_accumulate_occPfiiiiS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %r9, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19cuda_accumulate_occPfiiiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z34__device_stub__cuda_accumulate_occPfiiiiS_, .Lfunc_end0-_Z34__device_stub__cuda_accumulate_occPfiiiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19cuda_accumulate_occPfiiiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19cuda_accumulate_occPfiiiiS_,@object # @_Z19cuda_accumulate_occPfiiiiS_
.section .rodata,"a",@progbits
.globl _Z19cuda_accumulate_occPfiiiiS_
.p2align 3, 0x0
_Z19cuda_accumulate_occPfiiiiS_:
.quad _Z34__device_stub__cuda_accumulate_occPfiiiiS_
.size _Z19cuda_accumulate_occPfiiiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19cuda_accumulate_occPfiiiiS_"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__cuda_accumulate_occPfiiiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19cuda_accumulate_occPfiiiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void update_e( int Nx, int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz, float *CEx, float *CEy, float *CEz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int Nyz = Ny*Nz;
int i = idx/Nyz;
int j = ( idx - i*Nyz )/Nz;
int k = idx - i*Nyz - j*Nz;
if ( i > 0 && j > 0 && k > 0 && i < Nx ) {
if ( j<Ny-1 && k<Nz-1 ) Ex[idx] += CEx[idx]*( Hz[idx+Nz] - Hz[idx] - Hy[idx+1] + Hy[idx] );
if ( i<Nx-1 && k<Nz-1 ) Ey[idx] += CEy[idx]*( Hx[idx+1] - Hx[idx] - Hz[idx+Nyz] + Hz[idx] );
if ( i<Nx-1 && j<Ny-1 ) Ez[idx] += CEz[idx]*( Hy[idx+Nyz] - Hy[idx] - Hx[idx+Nz] + Hx[idx] );
}
}
__global__ void update_h( int Nx, int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int Nyz = Ny*Nz;
int i = idx/Nyz;
int j = ( idx - i*Nyz )/Nz;
int k = idx - i*Nyz - j*Nz;
if ( i > 0 && j > 0 && k > 0 && i < Nx ) {
Hx[idx] -= 0.5*( Ez[idx] - Ez[idx-Nz] - Ey[idx] + Ey[idx-1] );
Hy[idx] -= 0.5*( Ex[idx] - Ex[idx-1] - Ez[idx] + Ez[idx-Nyz] );
Hz[idx] -= 0.5*( Ey[idx] - Ey[idx-Nyz] - Ex[idx] + Ex[idx-Nz] );
}
} | code for sm_80
Function : _Z8update_hiiiPfS_S_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff067624 */
/* 0x000fe200078e00ff */
/*0020*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0030*/ IABS R11, c[0x0][0x168] ; /* 0x00005a00000b7a13 */
/* 0x000fe40000000000 */
/*0040*/ IMAD R6, R6, c[0x0][0x164], RZ ; /* 0x0000590006067a24 */
/* 0x000fe200078e02ff */
/*0050*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0060*/ IABS R5, R6 ; /* 0x0000000600057213 */
/* 0x000fc80000000000 */
/*0070*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e700000209400 */
/*0080*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x002e620000001000 */
/*0090*/ IMAD R9, R9, c[0x0][0x0], R4 ; /* 0x0000000009097a24 */
/* 0x001fca00078e0204 */
/*00a0*/ IABS R4, R9 ; /* 0x0000000900047213 */
/* 0x000fe40000000000 */
/*00b0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x002fc80007ffe0ff */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*00e0*/ IADD3 R8, RZ, -R3, RZ ; /* 0x80000003ff087210 */
/* 0x002fca0007ffe0ff */
/*00f0*/ IMAD R7, R8, R5, RZ ; /* 0x0000000508077224 */
/* 0x000fe200078e02ff */
/*0100*/ IABS R8, R6 ; /* 0x0000000600087213 */
/* 0x000fc60000000000 */
/*0110*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0120*/ MOV R7, R4 ; /* 0x0000000400077202 */
/* 0x000fe40000000f00 */
/*0130*/ I2F.RP R4, R11 ; /* 0x0000000b00047306 */
/* 0x000e220000209400 */
/*0140*/ IMAD.MOV R2, RZ, RZ, -R8 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0a08 */
/*0150*/ IMAD.HI.U32 R0, R3, R7, RZ ; /* 0x0000000703007227 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD R2, R0, R2, R7 ; /* 0x0000000200027224 */
/* 0x000fca00078e0207 */
/*0170*/ ISETP.GT.U32.AND P2, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fe20003f44070 */
/*0180*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e180000001000 */
/*0190*/ @!P2 IADD3 R2, R2, -R5.reuse, RZ ; /* 0x800000050202a210 */
/* 0x080fe40007ffe0ff */
/*01a0*/ @!P2 IADD3 R0, R0, 0x1, RZ ; /* 0x000000010000a810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe40003f06070 */
/*01c0*/ LOP3.LUT R2, R9, R6, RZ, 0x3c, !PT ; /* 0x0000000609027212 */
/* 0x000fe400078e3cff */
/*01d0*/ ISETP.NE.AND P2, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f45270 */
/*01e0*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc40003f26270 */
/*01f0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fc80007ffe0ff */
/*0200*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000062000021f000 */
/*0210*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fca0007ffe0ff */
/*0220*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0000 */
/*0230*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fc600078e00ff */
/*0240*/ @!P1 IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff07079210 */
/* 0x000fe40007ffe1ff */
/*0250*/ @!P2 LOP3.LUT R7, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff07a212 */
/* 0x000fe200078e33ff */
/*0260*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x002fc600078e0a03 */
/*0270*/ IADD3 R0, -R7, RZ, RZ ; /* 0x000000ff07007210 */
/* 0x000fe20007ffe1ff */
/*0280*/ IMAD R5, R4, R11, RZ ; /* 0x0000000b04057224 */
/* 0x000fc800078e02ff */
/*0290*/ IMAD R13, R6, R0, R9 ; /* 0x00000000060d7224 */
/* 0x000fe400078e0209 */
/*02a0*/ IMAD.HI.U32 R2, R3, R5, R2 ; /* 0x0000000503027227 */
/* 0x000fc600078e0002 */
/*02b0*/ IABS R0, R13 ; /* 0x0000000d00007213 */
/* 0x000fca0000000000 */
/*02c0*/ IMAD.HI.U32 R2, R2, R0, RZ ; /* 0x0000000002027227 */
/* 0x000fca00078e00ff */
/*02d0*/ IADD3 R3, -R2, RZ, RZ ; /* 0x000000ff02037210 */
/* 0x000fca0007ffe1ff */
/*02e0*/ IMAD R0, R11, R3, R0 ; /* 0x000000030b007224 */
/* 0x000fca00078e0200 */
/*02f0*/ ISETP.GT.U32.AND P2, PT, R11, R0, PT ; /* 0x000000000b00720c */
/* 0x000fda0003f44070 */
/*0300*/ @!P2 IADD3 R0, R0, -R11.reuse, RZ ; /* 0x8000000b0000a210 */
/* 0x080fe40007ffe0ff */
/*0310*/ @!P2 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202a810 */
/* 0x000fe40007ffe0ff */
/*0320*/ ISETP.GE.U32.AND P0, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x000fe40003f06070 */
/*0330*/ LOP3.LUT R0, R13, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a000d007a12 */
/* 0x000fe400078e3cff */
/*0340*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f45270 */
/*0350*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f26270 */
/*0360*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fcc0007ffe0ff */
/*0370*/ @!P1 IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff029224 */
/* 0x000fe200078e0a02 */
/*0380*/ @!P2 LOP3.LUT R2, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff02aa12 */
/* 0x000fc800078e33ff */
/*0390*/ ISETP.GE.AND P0, PT, R2.reuse, 0x1, PT ; /* 0x000000010200780c */
/* 0x040fe20003f06270 */
/*03a0*/ IMAD R2, R2, c[0x0][0x168], RZ ; /* 0x00005a0002027a24 */
/* 0x000fc600078e02ff */
/*03b0*/ ISETP.LT.OR P0, PT, R7, 0x1, !P0 ; /* 0x000000010700780c */
/* 0x000fc80004701670 */
/*03c0*/ ISETP.LE.OR P0, PT, R13, R2, P0 ; /* 0x000000020d00720c */
/* 0x000fc80000703670 */
/*03d0*/ ISETP.GE.OR P0, PT, R7, c[0x0][0x160], P0 ; /* 0x0000580007007a0c */
/* 0x000fda0000706670 */
/*03e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03f0*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*0400*/ IADD3 R7, R9, -c[0x0][0x168], RZ ; /* 0x80005a0009077a10 */
/* 0x000fe20007ffe0ff */
/*0410*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0420*/ IMAD.WIDE R10, R7, R0, c[0x0][0x180] ; /* 0x00006000070a7625 */
/* 0x000fc800078e0200 */
/*0430*/ IMAD.WIDE R4, R9.reuse, R0.reuse, c[0x0][0x180] ; /* 0x0000600009047625 */
/* 0x0c0fe400078e0200 */
/*0440*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea4000c1e1900 */
/*0450*/ IMAD.WIDE R2, R9.reuse, R0.reuse, c[0x0][0x178] ; /* 0x00005e0009027625 */
/* 0x0c0fe400078e0200 */
/*0460*/ LDG.E R15, [R4.64] ; /* 0x00000004040f7981 */
/* 0x000ea4000c1e1900 */
/*0470*/ IMAD.WIDE R12, R9, R0, c[0x0][0x188] ; /* 0x00006200090c7625 */
/* 0x000fe400078e0200 */
/*0480*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ee8000c1e1900 */
/*0490*/ LDG.E R19, [R2.64+-0x4] ; /* 0xfffffc0402137981 */
/* 0x000f28000c1e1900 */
/*04a0*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000f62000c1e1900 */
/*04b0*/ FADD R15, -R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fc80000000100 */
/*04c0*/ FADD R8, R15, -R8 ; /* 0x800000080f087221 */
/* 0x008fc80000000000 */
/*04d0*/ FADD R8, R8, R19 ; /* 0x0000001308087221 */
/* 0x010fe20000000000 */
/*04e0*/ F2F.F64.F32 R16, R16 ; /* 0x0000001000107310 */
/* 0x020ff00000201800 */
/*04f0*/ F2F.F64.F32 R14, R8 ; /* 0x00000008000e7310 */
/* 0x000e240000201800 */
/*0500*/ DFMA R18, R14, -0.5, R16 ; /* 0xbfe000000e12782b */
/* 0x001e0c0000000010 */
/*0510*/ F2F.F32.F64 R23, R18 ; /* 0x0000001200177310 */
/* 0x001e220000301000 */
/*0520*/ IMAD.WIDE R10, R9.reuse, R0, c[0x0][0x170] ; /* 0x00005c00090a7625 */
/* 0x040fe200078e0200 */
/*0530*/ IADD3 R17, R9, -R6, RZ ; /* 0x8000000609117210 */
/* 0x000fca0007ffe0ff */
/*0540*/ IMAD.WIDE R20, R17, R0.reuse, c[0x0][0x180] ; /* 0x0000600011147625 */
/* 0x080fe200078e0200 */
/*0550*/ STG.E [R12.64], R23 ; /* 0x000000170c007986 */
/* 0x0011e8000c101904 */
/*0560*/ LDG.E R6, [R10.64+-0x4] ; /* 0xfffffc040a067981 */
/* 0x000ea8000c1e1900 */
/*0570*/ LDG.E R25, [R10.64] ; /* 0x000000040a197981 */
/* 0x000ea2000c1e1900 */
/*0580*/ IMAD.WIDE R14, R9, R0, c[0x0][0x190] ; /* 0x00006400090e7625 */
/* 0x000fc600078e0200 */
/*0590*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ee8000c1e1900 */
/*05a0*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000f28000c1e1900 */
/*05b0*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000f62000c1e1900 */
/*05c0*/ IMAD.WIDE R16, R17, R0, c[0x0][0x178] ; /* 0x00005e0011107625 */
/* 0x000fc800078e0200 */
/*05d0*/ IMAD.WIDE R8, R9, R0, c[0x0][0x198] ; /* 0x0000660009087625 */
/* 0x000fc800078e0200 */
/*05e0*/ FADD R6, -R6, R25 ; /* 0x0000001906067221 */
/* 0x004fc80000000100 */
/*05f0*/ FADD R6, R6, -R5 ; /* 0x8000000506067221 */
/* 0x008fc80000000000 */
/*0600*/ FADD R6, R6, R21 ; /* 0x0000001506067221 */
/* 0x010fe20000000000 */
/*0610*/ F2F.F64.F32 R18, R22 ; /* 0x0000001600127310 */
/* 0x020ff00000201800 */
/*0620*/ F2F.F64.F32 R12, R6 ; /* 0x00000006000c7310 */
/* 0x001e240000201800 */
/*0630*/ DFMA R12, R12, -0.5, R18 ; /* 0xbfe000000c0c782b */
/* 0x001e0c0000000012 */
/*0640*/ F2F.F32.F64 R19, R12 ; /* 0x0000000c00137310 */
/* 0x001e220000301000 */
/*0650*/ IMAD.WIDE R4, R7, R0, c[0x0][0x170] ; /* 0x00005c0007047625 */
/* 0x000fe200078e0200 */
/*0660*/ STG.E [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x001fe8000c101904 */
/*0670*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0680*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea8000c1e1900 */
/*0690*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ee8000c1e1900 */
/*06a0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000f28000c1e1900 */
/*06b0*/ LDG.E R18, [R8.64] ; /* 0x0000000408127981 */
/* 0x000f62000c1e1900 */
/*06c0*/ FADD R0, -R16, R3 ; /* 0x0000000310007221 */
/* 0x004fc80000000100 */
/*06d0*/ FADD R0, R0, -R11 ; /* 0x8000000b00007221 */
/* 0x008fc80000000000 */
/*06e0*/ FADD R0, R0, R5 ; /* 0x0000000500007221 */
/* 0x010fe20000000000 */
/*06f0*/ F2F.F64.F32 R12, R18 ; /* 0x00000012000c7310 */
/* 0x020ff00000201800 */
/*0700*/ F2F.F64.F32 R6, R0 ; /* 0x0000000000067310 */
/* 0x000e240000201800 */
/*0710*/ DFMA R6, R6, -0.5, R12 ; /* 0xbfe000000606782b */
/* 0x001e14000000000c */
/*0720*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x001e240000301000 */
/*0730*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x001fe2000c101904 */
/*0740*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0750*/ BRA 0x750; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8update_eiiiPfS_S_S_S_S_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0030*/ IABS R12, c[0x0][0x168] ; /* 0x00005a00000c7a13 */
/* 0x000fe40000000000 */
/*0040*/ IMAD R0, R2, c[0x0][0x164], RZ ; /* 0x0000590002007a24 */
/* 0x000fe200078e02ff */
/*0050*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0060*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fc80000000000 */
/*0070*/ I2F.RP R3, R8 ; /* 0x0000000800037306 */
/* 0x000e700000209400 */
/*0080*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x002e620000001000 */
/*0090*/ IMAD R9, R9, c[0x0][0x0], R6 ; /* 0x0000000009097a24 */
/* 0x001fe200078e0206 */
/*00a0*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc80000000000 */
/*00b0*/ IABS R10, R9 ; /* 0x00000009000a7213 */
/* 0x000fe40000000000 */
/*00c0*/ IADD3 R4, R3, 0xffffffe, RZ ; /* 0x0ffffffe03047810 */
/* 0x002fe20007ffe0ff */
/*00d0*/ IMAD.MOV R3, RZ, RZ, -R6 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0a06 */
/*00e0*/ I2F.RP R6, R12 ; /* 0x0000000c00067306 */
/* 0x000e300000209400 */
/*00f0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x0002b0000021f000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e220000001000 */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x002fc400078e00ff */
/*0120*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x004fc800078e0a05 */
/*0130*/ IMAD R7, R7, R8, RZ ; /* 0x0000000807077224 */
/* 0x000fc800078e02ff */
/*0140*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fe200078e0004 */
/*0150*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fca0007ffe0ff */
/*0160*/ IMAD.HI.U32 R7, R5, R10, RZ ; /* 0x0000000a05077227 */
/* 0x000fe400078e00ff */
/*0170*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0180*/ IMAD R3, R7, R3, R10 ; /* 0x0000000307037224 */
/* 0x000fca00078e020a */
/*0190*/ ISETP.GT.U32.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fe20003f24070 */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*01b0*/ IMAD.MOV R11, RZ, RZ, -R5 ; /* 0x000000ffff0b7224 */
/* 0x002fd400078e0a05 */
/*01c0*/ @!P1 IMAD.IADD R3, R3, 0x1, -R8 ; /* 0x0000000103039824 */
/* 0x000fe200078e0a08 */
/*01d0*/ @!P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107079810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f25270 */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R3, R8, PT ; /* 0x000000080300720c */
/* 0x000fe40003f06070 */
/*0200*/ LOP3.LUT R3, R9, R0, RZ, 0x3c, !PT ; /* 0x0000000009037212 */
/* 0x000fc800078e3cff */
/*0210*/ ISETP.GE.AND P2, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fce0003f46270 */
/*0220*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fcc0007ffe0ff */
/*0230*/ @!P2 IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff0707a210 */
/* 0x000fe40007ffe1ff */
/*0240*/ @!P1 LOP3.LUT R7, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff079212 */
/* 0x000fca00078e33ff */
/*0250*/ IMAD.MOV R3, RZ, RZ, -R7 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a07 */
/*0260*/ IMAD R8, R0, R3, R9 ; /* 0x0000000300087224 */
/* 0x000fe400078e0209 */
/*0270*/ IMAD R3, R11, R12, RZ ; /* 0x0000000c0b037224 */
/* 0x000fc600078e02ff */
/*0280*/ IABS R6, R8 ; /* 0x0000000800067213 */
/* 0x000fe20000000000 */
/*0290*/ IMAD.HI.U32 R4, R5, R3, R4 ; /* 0x0000000305047227 */
/* 0x000fc800078e0004 */
/*02a0*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0006 */
/*02b0*/ IMAD.HI.U32 R6, R4, R3, RZ ; /* 0x0000000304067227 */
/* 0x000fca00078e00ff */
/*02c0*/ IADD3 R4, -R6, RZ, RZ ; /* 0x000000ff06047210 */
/* 0x000fca0007ffe1ff */
/*02d0*/ IMAD R3, R12, R4, R3 ; /* 0x000000040c037224 */
/* 0x000fca00078e0203 */
/*02e0*/ ISETP.GT.U32.AND P1, PT, R12, R3, PT ; /* 0x000000030c00720c */
/* 0x000fda0003f24070 */
/*02f0*/ @!P1 IMAD.IADD R3, R3, 0x1, -R12 ; /* 0x0000000103039824 */
/* 0x000fe200078e0a0c */
/*0300*/ @!P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106069810 */
/* 0x000fe40007ffe0ff */
/*0310*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f25270 */
/*0320*/ ISETP.GE.U32.AND P0, PT, R3, R12, PT ; /* 0x0000000c0300720c */
/* 0x000fe40003f06070 */
/*0330*/ LOP3.LUT R3, R8, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0008037a12 */
/* 0x000fc800078e3cff */
/*0340*/ ISETP.GE.AND P2, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fce0003f46270 */
/*0350*/ @P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106060810 */
/* 0x000fcc0007ffe0ff */
/*0360*/ @!P2 IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff06a224 */
/* 0x000fe200078e0a06 */
/*0370*/ @!P1 LOP3.LUT R6, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff069a12 */
/* 0x000fc800078e33ff */
/*0380*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f06270 */
/*0390*/ IMAD.MOV R3, RZ, RZ, -R6 ; /* 0x000000ffff037224 */
/* 0x000fc600078e0a06 */
/*03a0*/ ISETP.LT.OR P0, PT, R7, 0x1, !P0 ; /* 0x000000010700780c */
/* 0x000fe20004701670 */
/*03b0*/ IMAD R3, R3, c[0x0][0x168], R8 ; /* 0x00005a0003037a24 */
/* 0x000fca00078e0208 */
/*03c0*/ ISETP.LT.OR P0, PT, R3, 0x1, P0 ; /* 0x000000010300780c */
/* 0x000fc80000701670 */
/*03d0*/ ISETP.GE.OR P0, PT, R7, c[0x0][0x160], P0 ; /* 0x0000580007007a0c */
/* 0x000fda0000706670 */
/*03e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03f0*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe20000000000 */
/*0400*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0410*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0420*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*0430*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fe2000fffe13f */
/*0440*/ ISETP.GE.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x000fe20003f06270 */
/*0450*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0460*/ IMAD.WIDE R4, R9, R8, c[0x0][0x198] ; /* 0x0000660009047625 */
/* 0x000fc600078e0208 */
/*0470*/ ISETP.GE.OR P2, PT, R6, UR4, P0 ; /* 0x0000000406007c0c */
/* 0x000fe20008746670 */
/*0480*/ IMAD.WIDE R2, R9, R8, c[0x0][0x190] ; /* 0x0000640009027625 */
/* 0x000fd800078e0208 */
/*0490*/ @!P2 IADD3 R13, R9, c[0x0][0x168], RZ ; /* 0x00005a00090daa10 */
/* 0x000fe20007ffe0ff */
/*04a0*/ @!P2 LDG.E R16, [R4.64] ; /* 0x000000080410a981 */
/* 0x000ea8000c1e1900 */
/*04b0*/ @!P2 IMAD.WIDE R12, R13, R8.reuse, c[0x0][0x198] ; /* 0x000066000d0ca625 */
/* 0x080fe200078e0208 */
/*04c0*/ @!P2 LDG.E R17, [R2.64+0x4] ; /* 0x000004080211a981 */
/* 0x000ee6000c1e1900 */
/*04d0*/ @!P2 IMAD.WIDE R14, R9.reuse, R8.reuse, c[0x0][0x1a0] ; /* 0x00006800090ea625 */
/* 0x0c0fe200078e0208 */
/*04e0*/ @!P2 LDG.E R19, [R2.64] ; /* 0x000000080213a981 */
/* 0x000f28000c1e1900 */
/*04f0*/ @!P2 LDG.E R13, [R12.64] ; /* 0x000000080c0da981 */
/* 0x0000a2000c1e1900 */
/*0500*/ @!P2 IMAD.WIDE R10, R9, R8, c[0x0][0x170] ; /* 0x00005c00090aa625 */
/* 0x000fc600078e0208 */
/*0510*/ @!P2 LDG.E R15, [R14.64] ; /* 0x000000080e0fa981 */
/* 0x000f68000c1e1900 */
/*0520*/ @!P2 LDG.E R18, [R10.64] ; /* 0x000000080a12a981 */
/* 0x000f62000c1e1900 */
/*0530*/ UIADD3 UR5, -UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fcc000fffe13f */
/*0540*/ ISETP.GE.OR P0, PT, R7, UR5, P0 ; /* 0x0000000507007c0c */
/* 0x000fe40008706670 */
/*0550*/ SHF.R.S32.HI R20, RZ, 0x1f, R9 ; /* 0x0000001fff147819 */
/* 0x000fe40000011409 */
/*0560*/ SHF.L.U32 R12, R9, 0x2, RZ ; /* 0x00000002090c7819 */
/* 0x001fe400000006ff */
/*0570*/ ISETP.GE.AND P1, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fe2000bf26270 */
/*0580*/ BSSY B0, 0x750 ; /* 0x000001c000007945 */
/* 0x000fe20003800000 */
/*0590*/ IADD3 R6, P3, R12, c[0x0][0x188], RZ ; /* 0x000062000c067a10 */
/* 0x000fe40007f7e0ff */
/*05a0*/ ISETP.GE.OR P1, PT, R7, UR5, P1 ; /* 0x0000000507007c0c */
/* 0x000fe20008f26670 */
/*05b0*/ @!P2 FADD R16, -R16, R13 ; /* 0x0000000d1010a221 */
/* 0x004fc80000000100 */
/*05c0*/ @!P2 FADD R16, R16, -R17 ; /* 0x800000111010a221 */
/* 0x008fc80000000000 */
/*05d0*/ @!P2 FADD R16, R16, R19 ; /* 0x000000131010a221 */
/* 0x010fc80000000000 */
/*05e0*/ @!P2 FFMA R15, R16, R15, R18 ; /* 0x0000000f100fa223 */
/* 0x020fca0000000012 */
/*05f0*/ @!P2 STG.E [R10.64], R15 ; /* 0x0000000f0a00a986 */
/* 0x0001e2000c101908 */
/*0600*/ SHF.L.U64.HI R13, R9, 0x2, R20 ; /* 0x00000002090d7819 */
/* 0x000fc80000010214 */
/*0610*/ IADD3.X R7, R13, c[0x0][0x18c], RZ, P3, !PT ; /* 0x000063000d077a10 */
/* 0x000fe20001ffe4ff */
/*0620*/ @P0 BRA 0x740 ; /* 0x0000011000000947 */
/* 0x000fea0003800000 */
/*0630*/ IMAD.IADD R17, R9, 0x1, R0 ; /* 0x0000000109117824 */
/* 0x000fe200078e0200 */
/*0640*/ LDG.E R18, [R6.64] ; /* 0x0000000806127981 */
/* 0x000ea6000c1e1900 */
/*0650*/ IMAD.WIDE R16, R17, R8, c[0x0][0x198] ; /* 0x0000660011107625 */
/* 0x000fe200078e0208 */
/*0660*/ LDG.E R19, [R6.64+0x4] ; /* 0x0000040806137981 */
/* 0x000ea2000c1e1900 */
/*0670*/ IADD3 R14, P0, R12.reuse, c[0x0][0x1a8], RZ ; /* 0x00006a000c0e7a10 */
/* 0x040fe40007f1e0ff */
/*0680*/ IADD3 R10, P2, R12, c[0x0][0x178], RZ ; /* 0x00005e000c0a7a10 */
/* 0x001fe20007f5e0ff */
/*0690*/ LDG.E R5, [R4.64] ; /* 0x0000000804057981 */
/* 0x000ee2000c1e1900 */
/*06a0*/ IADD3.X R15, R13, c[0x0][0x1ac], RZ, P0, !PT ; /* 0x00006b000d0f7a10 */
/* 0x000fc600007fe4ff */
/*06b0*/ LDG.E R17, [R16.64] ; /* 0x0000000810117981 */
/* 0x000f22000c1e1900 */
/*06c0*/ IADD3.X R11, R13, c[0x0][0x17c], RZ, P2, !PT ; /* 0x00005f000d0b7a10 */
/* 0x000fc600017fe4ff */
/*06d0*/ LDG.E R15, [R14.64] ; /* 0x000000080e0f7981 */
/* 0x000f68000c1e1900 */
/*06e0*/ LDG.E R20, [R10.64] ; /* 0x000000080a147981 */
/* 0x000f62000c1e1900 */
/*06f0*/ FADD R18, -R18, R19 ; /* 0x0000001312127221 */
/* 0x004fc80000000100 */
/*0700*/ FADD R18, R18, -R17 ; /* 0x8000001112127221 */
/* 0x010fc80000000000 */
/*0710*/ FADD R18, R18, R5 ; /* 0x0000000512127221 */
/* 0x008fc80000000000 */
/*0720*/ FFMA R19, R18, R15, R20 ; /* 0x0000000f12137223 */
/* 0x020fca0000000014 */
/*0730*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0001e4000c101908 */
/*0740*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0750*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0760*/ IMAD.IADD R5, R9.reuse, 0x1, R0 ; /* 0x0000000109057824 */
/* 0x040fe200078e0200 */
/*0770*/ IADD3 R9, R9, c[0x0][0x168], RZ ; /* 0x00005a0009097a10 */
/* 0x000fe20007ffe0ff */
/*0780*/ LDG.E R2, [R2.64] ; /* 0x0000000802027981 */
/* 0x000ea4000c1e1900 */
/*0790*/ IMAD.WIDE R4, R5, R8.reuse, c[0x0][0x190] ; /* 0x0000640005047625 */
/* 0x080fe200078e0208 */
/*07a0*/ IADD3 R10, P0, R12.reuse, c[0x0][0x1b0], RZ ; /* 0x00006c000c0a7a10 */
/* 0x041fe20007f1e0ff */
/*07b0*/ LDG.E R7, [R6.64] ; /* 0x0000000806077981 */
/* 0x000ee4000c1e1900 */
/*07c0*/ IMAD.WIDE R8, R9, R8, c[0x0][0x188] ; /* 0x0000620009087625 */
/* 0x000fe400078e0208 */
/*07d0*/ LDG.E R5, [R4.64] ; /* 0x0000000804057981 */
/* 0x000ea2000c1e1900 */
/*07e0*/ IADD3 R12, P1, R12, c[0x0][0x180], RZ ; /* 0x000060000c0c7a10 */
/* 0x000fc60007f3e0ff */
/*07f0*/ LDG.E R9, [R8.64] ; /* 0x0000000808097981 */
/* 0x000f22000c1e1900 */
/*0800*/ IADD3.X R11, R13.reuse, c[0x0][0x1b4], RZ, P0, !PT ; /* 0x00006d000d0b7a10 */
/* 0x040fe400007fe4ff */
/*0810*/ IADD3.X R13, R13, c[0x0][0x184], RZ, P1, !PT ; /* 0x000061000d0d7a10 */
/* 0x000fc80000ffe4ff */
/*0820*/ LDG.E R11, [R10.64] ; /* 0x000000080a0b7981 */
/* 0x000f68000c1e1900 */
/*0830*/ LDG.E R0, [R12.64] ; /* 0x000000080c007981 */
/* 0x000f62000c1e1900 */
/*0840*/ FADD R2, -R2, R5 ; /* 0x0000000502027221 */
/* 0x004fc80000000100 */
/*0850*/ FADD R2, R2, -R9 ; /* 0x8000000902027221 */
/* 0x010fc80000000000 */
/*0860*/ FADD R2, R2, R7 ; /* 0x0000000702027221 */
/* 0x008fc80000000000 */
/*0870*/ FFMA R3, R2, R11, R0 ; /* 0x0000000b02037223 */
/* 0x020fca0000000000 */
/*0880*/ STG.E [R12.64], R3 ; /* 0x000000030c007986 */
/* 0x000fe2000c101908 */
/*0890*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08a0*/ BRA 0x8a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void update_e( int Nx, int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz, float *CEx, float *CEy, float *CEz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int Nyz = Ny*Nz;
int i = idx/Nyz;
int j = ( idx - i*Nyz )/Nz;
int k = idx - i*Nyz - j*Nz;
if ( i > 0 && j > 0 && k > 0 && i < Nx ) {
if ( j<Ny-1 && k<Nz-1 ) Ex[idx] += CEx[idx]*( Hz[idx+Nz] - Hz[idx] - Hy[idx+1] + Hy[idx] );
if ( i<Nx-1 && k<Nz-1 ) Ey[idx] += CEy[idx]*( Hx[idx+1] - Hx[idx] - Hz[idx+Nyz] + Hz[idx] );
if ( i<Nx-1 && j<Ny-1 ) Ez[idx] += CEz[idx]*( Hy[idx+Nyz] - Hy[idx] - Hx[idx+Nz] + Hx[idx] );
}
}
__global__ void update_h( int Nx, int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int Nyz = Ny*Nz;
int i = idx/Nyz;
int j = ( idx - i*Nyz )/Nz;
int k = idx - i*Nyz - j*Nz;
if ( i > 0 && j > 0 && k > 0 && i < Nx ) {
Hx[idx] -= 0.5*( Ez[idx] - Ez[idx-Nz] - Ey[idx] + Ey[idx-1] );
Hy[idx] -= 0.5*( Ex[idx] - Ex[idx-1] - Ez[idx] + Ez[idx-Nyz] );
Hz[idx] -= 0.5*( Ey[idx] - Ey[idx-Nyz] - Ex[idx] + Ex[idx-Nz] );
}
} | .file "tmpxft_0007d45b_00000000-6_dielectric.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_
.type _Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_, @function
_Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movl %edi, 92(%rsp)
movl %esi, 88(%rsp)
movl %edx, 84(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
movq 288(%rsp), %rax
movq %rax, 48(%rsp)
movq 296(%rsp), %rax
movq %rax, 40(%rsp)
movq 304(%rsp), %rax
movq %rax, 32(%rsp)
movq 312(%rsp), %rax
movq %rax, 24(%rsp)
movq 320(%rsp), %rax
movq %rax, 16(%rsp)
movq 328(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 92(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 84(%rsp), %rax
movq %rax, 176(%rsp)
leaq 72(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rax
movq %rax, 192(%rsp)
leaq 56(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rax
movq %rax, 208(%rsp)
leaq 40(%rsp), %rax
movq %rax, 216(%rsp)
leaq 32(%rsp), %rax
movq %rax, 224(%rsp)
leaq 24(%rsp), %rax
movq %rax, 232(%rsp)
leaq 16(%rsp), %rax
movq %rax, 240(%rsp)
leaq 8(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 104(%rsp)
.cfi_def_cfa_offset 304
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z8update_eiiiPfS_S_S_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_, .-_Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_
.globl _Z8update_eiiiPfS_S_S_S_S_S_S_S_
.type _Z8update_eiiiPfS_S_S_S_S_S_S_S_, @function
_Z8update_eiiiPfS_S_S_S_S_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 56(%rsp)
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8update_eiiiPfS_S_S_S_S_S_S_S_, .-_Z8update_eiiiPfS_S_S_S_S_S_S_S_
.globl _Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_
.type _Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_, @function
_Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movq %rcx, 40(%rsp)
movq %r8, 32(%rsp)
movq %r9, 24(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq 232(%rsp), %rax
movq %rax, 8(%rsp)
movq 240(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z8update_hiiiPfS_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_, .-_Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_
.globl _Z8update_hiiiPfS_S_S_S_S_
.type _Z8update_hiiiPfS_S_S_S_S_, @function
_Z8update_hiiiPfS_S_S_S_S_:
.LFB2054:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z8update_hiiiPfS_S_S_S_S_, .-_Z8update_hiiiPfS_S_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8update_hiiiPfS_S_S_S_S_"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z8update_eiiiPfS_S_S_S_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8update_hiiiPfS_S_S_S_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8update_eiiiPfS_S_S_S_S_S_S_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void update_e( int Nx, int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz, float *CEx, float *CEy, float *CEz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int Nyz = Ny*Nz;
int i = idx/Nyz;
int j = ( idx - i*Nyz )/Nz;
int k = idx - i*Nyz - j*Nz;
if ( i > 0 && j > 0 && k > 0 && i < Nx ) {
if ( j<Ny-1 && k<Nz-1 ) Ex[idx] += CEx[idx]*( Hz[idx+Nz] - Hz[idx] - Hy[idx+1] + Hy[idx] );
if ( i<Nx-1 && k<Nz-1 ) Ey[idx] += CEy[idx]*( Hx[idx+1] - Hx[idx] - Hz[idx+Nyz] + Hz[idx] );
if ( i<Nx-1 && j<Ny-1 ) Ez[idx] += CEz[idx]*( Hy[idx+Nyz] - Hy[idx] - Hx[idx+Nz] + Hx[idx] );
}
}
__global__ void update_h( int Nx, int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int Nyz = Ny*Nz;
int i = idx/Nyz;
int j = ( idx - i*Nyz )/Nz;
int k = idx - i*Nyz - j*Nz;
if ( i > 0 && j > 0 && k > 0 && i < Nx ) {
Hx[idx] -= 0.5*( Ez[idx] - Ez[idx-Nz] - Ey[idx] + Ey[idx-1] );
Hy[idx] -= 0.5*( Ex[idx] - Ex[idx-1] - Ez[idx] + Ez[idx-Nyz] );
Hz[idx] -= 0.5*( Ey[idx] - Ey[idx-Nyz] - Ex[idx] + Ex[idx-Nz] );
}
} | #include <hip/hip_runtime.h>
__global__ void update_e( int Nx, int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz, float *CEx, float *CEy, float *CEz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int Nyz = Ny*Nz;
int i = idx/Nyz;
int j = ( idx - i*Nyz )/Nz;
int k = idx - i*Nyz - j*Nz;
if ( i > 0 && j > 0 && k > 0 && i < Nx ) {
if ( j<Ny-1 && k<Nz-1 ) Ex[idx] += CEx[idx]*( Hz[idx+Nz] - Hz[idx] - Hy[idx+1] + Hy[idx] );
if ( i<Nx-1 && k<Nz-1 ) Ey[idx] += CEy[idx]*( Hx[idx+1] - Hx[idx] - Hz[idx+Nyz] + Hz[idx] );
if ( i<Nx-1 && j<Ny-1 ) Ez[idx] += CEz[idx]*( Hy[idx+Nyz] - Hy[idx] - Hx[idx+Nz] + Hx[idx] );
}
}
__global__ void update_h( int Nx, int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int Nyz = Ny*Nz;
int i = idx/Nyz;
int j = ( idx - i*Nyz )/Nz;
int k = idx - i*Nyz - j*Nz;
if ( i > 0 && j > 0 && k > 0 && i < Nx ) {
Hx[idx] -= 0.5*( Ez[idx] - Ez[idx-Nz] - Ey[idx] + Ey[idx-1] );
Hy[idx] -= 0.5*( Ex[idx] - Ex[idx-1] - Ez[idx] + Ez[idx-Nyz] );
Hz[idx] -= 0.5*( Ey[idx] - Ey[idx-Nyz] - Ex[idx] + Ex[idx-Nz] );
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void update_e( int Nx, int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz, float *CEx, float *CEy, float *CEz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int Nyz = Ny*Nz;
int i = idx/Nyz;
int j = ( idx - i*Nyz )/Nz;
int k = idx - i*Nyz - j*Nz;
if ( i > 0 && j > 0 && k > 0 && i < Nx ) {
if ( j<Ny-1 && k<Nz-1 ) Ex[idx] += CEx[idx]*( Hz[idx+Nz] - Hz[idx] - Hy[idx+1] + Hy[idx] );
if ( i<Nx-1 && k<Nz-1 ) Ey[idx] += CEy[idx]*( Hx[idx+1] - Hx[idx] - Hz[idx+Nyz] + Hz[idx] );
if ( i<Nx-1 && j<Ny-1 ) Ez[idx] += CEz[idx]*( Hy[idx+Nyz] - Hy[idx] - Hx[idx+Nz] + Hx[idx] );
}
}
__global__ void update_h( int Nx, int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int Nyz = Ny*Nz;
int i = idx/Nyz;
int j = ( idx - i*Nyz )/Nz;
int k = idx - i*Nyz - j*Nz;
if ( i > 0 && j > 0 && k > 0 && i < Nx ) {
Hx[idx] -= 0.5*( Ez[idx] - Ez[idx-Nz] - Ey[idx] + Ey[idx-1] );
Hy[idx] -= 0.5*( Ex[idx] - Ex[idx-1] - Ez[idx] + Ez[idx-Nyz] );
Hz[idx] -= 0.5*( Ey[idx] - Ey[idx-Nyz] - Ex[idx] + Ex[idx-Nz] );
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8update_eiiiPfS_S_S_S_S_S_S_S_
.globl _Z8update_eiiiPfS_S_S_S_S_S_S_S_
.p2align 8
.type _Z8update_eiiiPfS_S_S_S_S_S_S_S_,@function
_Z8update_eiiiPfS_S_S_S_S_S_S_S_:
s_clause 0x2
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x64
s_waitcnt lgkmcnt(0)
s_mul_i32 s12, s3, s9
s_and_b32 s2, s2, 0xffff
s_ashr_i32 s4, s12, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s12, s4
s_xor_b32 s5, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s5
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_sub_i32 s2, 0, s5
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s2, v3
s_ashr_i32 s2, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_add_i32 s6, s3, s2
v_ashrrev_i32_e32 v2, 31, v1
s_xor_b32 s6, s6, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v0, v3, v0
v_add_nc_u32_e32 v4, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s4, v2
v_add_nc_u32_e32 v0, v3, v0
s_sub_i32 s4, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v3, v0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s5, v3
v_cmp_le_u32_e32 vcc_lo, s5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
v_cvt_f32_u32_e32 v5, s6
v_cmp_le_u32_e32 vcc_lo, s5, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v4, 1, v0
v_rcp_iflag_f32_e32 v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v0, v0, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v3
v_mul_lo_u32 v3, v0, s12
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v4, s4, v2
v_sub_nc_u32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v3
v_mul_hi_u32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v3, v5
v_add_nc_u32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_xor_b32_e32 v4, v6, v5
v_xor_b32_e32 v5, s2, v5
v_cmp_gt_i32_e64 s2, s8, v0
v_mul_hi_u32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, v2, s6
v_sub_nc_u32_e32 v4, v4, v6
v_add_nc_u32_e32 v6, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v7, s6, v4
v_cmp_le_u32_e32 vcc_lo, s6, v4
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v7, vcc_lo
v_add_nc_u32_e32 v6, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s6, v4
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v5
v_sub_nc_u32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v2, s3
v_sub_nc_u32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min3_i32 v4, v0, v2, v3
v_cmp_lt_i32_e32 vcc_lo, 0, v4
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_7
s_load_b128 s[4:7], s[0:1], 0x30
s_add_i32 s2, s9, -1
s_add_i32 s9, s3, -1
v_cmp_gt_i32_e32 vcc_lo, s2, v2
v_cmp_gt_i32_e64 s2, s9, v3
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v3, s3, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, vcc_lo, s2
s_and_saveexec_b32 s9, s3
s_cbranch_execz .LBB0_3
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x10
s_load_b64 s[14:15], s[0:1], 0x40
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_lshlrev_b64 v[4:5], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s3, s6, v4
v_add_co_ci_u32_e64 v5, s3, s7, v5, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s3, s6, v6
v_add_co_ci_u32_e64 v9, s3, s7, v7, s3
v_add_co_u32 v10, s3, s4, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v11, s3, s5, v7, s3
s_clause 0x1
global_load_b32 v12, v[4:5], off
global_load_b32 v13, v[8:9], off
global_load_b64 v[4:5], v[10:11], off
v_add_co_u32 v8, s3, s14, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s3, s15, v7, s3
v_add_co_u32 v6, s3, s10, v6
v_add_co_ci_u32_e64 v7, s3, s11, v7, s3
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(3)
v_sub_f32_e32 v10, v12, v13
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, v10, v5
v_add_f32_e32 v4, v5, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v9, v8, v4
global_store_b32 v[6:7], v9, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s9
s_load_b64 s[10:11], s[0:1], 0x28
s_add_i32 s3, s8, -1
v_add_nc_u32_e32 v4, s12, v1
v_cmp_gt_i32_e64 s3, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_and_saveexec_b32 s8, s2
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b64 s[12:13], s[0:1], 0x48
s_load_b64 s[14:15], s[0:1], 0x18
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[8:9], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, s2, s10, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v11, s2, s11, v7, s2
v_add_co_u32 v12, s2, s6, v6
v_add_co_ci_u32_e64 v13, s2, s7, v7, s2
v_add_co_u32 v8, s2, s6, v8
global_load_b64 v[10:11], v[10:11], off
v_add_co_ci_u32_e64 v9, s2, s7, v9, s2
v_add_co_u32 v14, s2, s12, v6
s_clause 0x1
global_load_b32 v0, v[8:9], off
global_load_b32 v8, v[12:13], off
v_add_co_ci_u32_e64 v15, s2, s13, v7, s2
v_add_co_u32 v5, s2, s14, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s2, s15, v7, s2
global_load_b32 v7, v[14:15], off
global_load_b32 v9, v[5:6], off
s_waitcnt vmcnt(4)
v_sub_f32_e32 v10, v11, v10
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v0, v10, v0
s_waitcnt vmcnt(2)
v_add_f32_e32 v0, v0, v8
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v9, v7, v0
global_store_b32 v[5:6], v9, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s8
s_and_b32 s2, s3, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v5, 31, v4
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b64 s[0:1], s[0:1], 0x50
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_lshlrev_b64 v[5:6], 2, v[4:5]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_clause 0x1
global_load_b32 v9, v[5:6], off
global_load_b32 v8, v[7:8], off
v_add_co_u32 v4, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v0
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[6:7], off
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(4)
v_sub_f32_e32 v6, v9, v8
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v2, v6, v2
s_waitcnt vmcnt(2)
v_add_f32_e32 v2, v2, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v5, v4, v2
global_store_b32 v[0:1], v5, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8update_eiiiPfS_S_S_S_S_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 344
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8update_eiiiPfS_S_S_S_S_S_S_S_, .Lfunc_end0-_Z8update_eiiiPfS_S_S_S_S_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8update_hiiiPfS_S_S_S_S_
.globl _Z8update_hiiiPfS_S_S_S_S_
.p2align 8
.type _Z8update_hiiiPfS_S_S_S_S_,@function
_Z8update_hiiiPfS_S_S_S_S_:
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s13, s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x4c
s_waitcnt lgkmcnt(0)
s_mul_i32 s12, s13, s5
s_and_b32 s2, s2, 0xffff
s_ashr_i32 s3, s12, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s12, s3
s_xor_b32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s5
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_sub_i32 s2, 0, s5
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s2, v3
s_ashr_i32 s2, s13, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_add_i32 s6, s13, s2
v_ashrrev_i32_e32 v2, 31, v1
s_xor_b32 s6, s6, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v0, v3, v0
v_add_nc_u32_e32 v4, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s3, v2
v_add_nc_u32_e32 v0, v3, v0
s_sub_i32 s3, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v3, v0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s5, v3
v_cmp_le_u32_e32 vcc_lo, s5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
v_cvt_f32_u32_e32 v5, s6
v_cmp_le_u32_e32 vcc_lo, s5, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v4, 1, v0
v_rcp_iflag_f32_e32 v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v0, v0, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v3
v_mul_lo_u32 v3, v0, s12
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mul_lo_u32 v4, s3, v2
v_cmp_gt_i32_e64 s3, s4, v0
v_sub_nc_u32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v5, 31, v3
v_mul_hi_u32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v3, v5
v_add_nc_u32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v6, v5
v_xor_b32_e32 v5, s2, v5
v_mul_hi_u32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, v2, s6
v_sub_nc_u32_e32 v4, v4, v6
v_add_nc_u32_e32 v6, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v7, s6, v4
v_cmp_le_u32_e32 vcc_lo, s6, v4
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v7, vcc_lo
v_add_nc_u32_e32 v6, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s6, v4
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v5
v_sub_nc_u32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v2, s13
v_min_i32_e32 v2, v0, v2
v_cmp_lt_i32_e32 vcc_lo, 0, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, v3, v4
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_2
s_load_b256 s[4:11], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
v_subrev_nc_u32_e32 v3, s13, v1
s_load_b128 s[0:3], s[0:1], 0x30
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_add_co_u32 v4, vcc_lo, v5, -4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v17, vcc_lo, -1, v6, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v6, vcc_lo
v_add_co_u32 v9, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v6, vcc_lo
s_clause 0x1
global_load_b32 v0, v[7:8], off
global_load_b32 v15, v[9:10], off
v_add_co_u32 v9, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v17, vcc_lo
global_load_b32 v16, v[11:12], off
v_add_co_u32 v13, vcc_lo, s10, v5
v_add_co_ci_u32_e32 v14, vcc_lo, s11, v6, vcc_lo
global_load_b32 v9, v[9:10], off
global_load_b32 v10, v[13:14], off
s_waitcnt vmcnt(3)
v_sub_f32_e32 v0, v0, v15
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v0, v0, v16
s_waitcnt vmcnt(1)
v_add_f32_e32 v0, v0, v9
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[9:10], v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[15:16], v0
v_subrev_nc_u32_e32 v0, s12, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_fma_f64 v[9:10], v[15:16], -0.5, v[9:10]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v18, v[9:10]
v_add_co_u32 v9, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v15, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v17, vcc_lo
global_store_b32 v[13:14], v18, off
s_clause 0x1
global_load_b32 v4, v[9:10], off
global_load_b32 v15, v[15:16], off
v_add_co_u32 v13, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v14, vcc_lo, s9, v1, vcc_lo
global_load_b32 v16, v[7:8], off
v_add_co_u32 v7, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v6, vcc_lo
global_load_b32 v13, v[13:14], off
global_load_b32 v14, v[7:8], off
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(3)
v_sub_f32_e32 v4, v4, v15
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v4, v4, v16
s_waitcnt vmcnt(1)
v_add_f32_e32 v4, v4, v13
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[13:14], v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[15:16], v4
v_fma_f64 v[13:14], v[15:16], -0.5, v[13:14]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v4, v[13:14]
global_store_b32 v[7:8], v4, off
s_clause 0x1
global_load_b32 v4, v[11:12], off
global_load_b32 v7, v[0:1], off
v_add_co_u32 v0, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
s_clause 0x1
global_load_b32 v2, v[9:10], off
global_load_b32 v3, v[0:1], off
v_add_co_u32 v0, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v6, vcc_lo
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(3)
v_sub_f32_e32 v4, v4, v7
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v2, v4, v2
s_waitcnt vmcnt(1)
v_add_f32_e32 v2, v2, v3
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[4:5], v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[2:3], v2
v_fma_f64 v[2:3], v[2:3], -0.5, v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8update_hiiiPfS_S_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8update_hiiiPfS_S_S_S_S_, .Lfunc_end1-_Z8update_hiiiPfS_S_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .offset: 88
.size: 4
.value_kind: hidden_block_count_x
- .offset: 92
.size: 4
.value_kind: hidden_block_count_y
- .offset: 96
.size: 4
.value_kind: hidden_block_count_z
- .offset: 100
.size: 2
.value_kind: hidden_group_size_x
- .offset: 102
.size: 2
.value_kind: hidden_group_size_y
- .offset: 104
.size: 2
.value_kind: hidden_group_size_z
- .offset: 106
.size: 2
.value_kind: hidden_remainder_x
- .offset: 108
.size: 2
.value_kind: hidden_remainder_y
- .offset: 110
.size: 2
.value_kind: hidden_remainder_z
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 152
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 344
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8update_eiiiPfS_S_S_S_S_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8update_eiiiPfS_S_S_S_S_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8update_hiiiPfS_S_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8update_hiiiPfS_S_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void update_e( int Nx, int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz, float *CEx, float *CEy, float *CEz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int Nyz = Ny*Nz;
int i = idx/Nyz;
int j = ( idx - i*Nyz )/Nz;
int k = idx - i*Nyz - j*Nz;
if ( i > 0 && j > 0 && k > 0 && i < Nx ) {
if ( j<Ny-1 && k<Nz-1 ) Ex[idx] += CEx[idx]*( Hz[idx+Nz] - Hz[idx] - Hy[idx+1] + Hy[idx] );
if ( i<Nx-1 && k<Nz-1 ) Ey[idx] += CEy[idx]*( Hx[idx+1] - Hx[idx] - Hz[idx+Nyz] + Hz[idx] );
if ( i<Nx-1 && j<Ny-1 ) Ez[idx] += CEz[idx]*( Hy[idx+Nyz] - Hy[idx] - Hx[idx+Nz] + Hx[idx] );
}
}
__global__ void update_h( int Nx, int Ny, int Nz, float *Ex, float *Ey, float *Ez, float *Hx, float *Hy, float *Hz ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
int Nyz = Ny*Nz;
int i = idx/Nyz;
int j = ( idx - i*Nyz )/Nz;
int k = idx - i*Nyz - j*Nz;
if ( i > 0 && j > 0 && k > 0 && i < Nx ) {
Hx[idx] -= 0.5*( Ez[idx] - Ez[idx-Nz] - Ey[idx] + Ey[idx-1] );
Hy[idx] -= 0.5*( Ex[idx] - Ex[idx-1] - Ez[idx] + Ez[idx-Nyz] );
Hz[idx] -= 0.5*( Ey[idx] - Ey[idx-Nyz] - Ex[idx] + Ex[idx-Nz] );
}
} | .text
.file "dielectric.hip"
.globl _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_ # -- Begin function _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_,@function
_Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_: # @_Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8update_eiiiPfS_S_S_S_S_S_S_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_, .Lfunc_end0-_Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__update_hiiiPfS_S_S_S_S_ # -- Begin function _Z23__device_stub__update_hiiiPfS_S_S_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__update_hiiiPfS_S_S_S_S_,@function
_Z23__device_stub__update_hiiiPfS_S_S_S_S_: # @_Z23__device_stub__update_hiiiPfS_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8update_hiiiPfS_S_S_S_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z23__device_stub__update_hiiiPfS_S_S_S_S_, .Lfunc_end1-_Z23__device_stub__update_hiiiPfS_S_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8update_eiiiPfS_S_S_S_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8update_hiiiPfS_S_S_S_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8update_eiiiPfS_S_S_S_S_S_S_S_,@object # @_Z8update_eiiiPfS_S_S_S_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z8update_eiiiPfS_S_S_S_S_S_S_S_
.p2align 3, 0x0
_Z8update_eiiiPfS_S_S_S_S_S_S_S_:
.quad _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_
.size _Z8update_eiiiPfS_S_S_S_S_S_S_S_, 8
.type _Z8update_hiiiPfS_S_S_S_S_,@object # @_Z8update_hiiiPfS_S_S_S_S_
.globl _Z8update_hiiiPfS_S_S_S_S_
.p2align 3, 0x0
_Z8update_hiiiPfS_S_S_S_S_:
.quad _Z23__device_stub__update_hiiiPfS_S_S_S_S_
.size _Z8update_hiiiPfS_S_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8update_eiiiPfS_S_S_S_S_S_S_S_"
.size .L__unnamed_1, 33
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8update_hiiiPfS_S_S_S_S_"
.size .L__unnamed_2, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_
.addrsig_sym _Z23__device_stub__update_hiiiPfS_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8update_eiiiPfS_S_S_S_S_S_S_S_
.addrsig_sym _Z8update_hiiiPfS_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007d45b_00000000-6_dielectric.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_
.type _Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_, @function
_Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movl %edi, 92(%rsp)
movl %esi, 88(%rsp)
movl %edx, 84(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
movq 288(%rsp), %rax
movq %rax, 48(%rsp)
movq 296(%rsp), %rax
movq %rax, 40(%rsp)
movq 304(%rsp), %rax
movq %rax, 32(%rsp)
movq 312(%rsp), %rax
movq %rax, 24(%rsp)
movq 320(%rsp), %rax
movq %rax, 16(%rsp)
movq 328(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 92(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 84(%rsp), %rax
movq %rax, 176(%rsp)
leaq 72(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rax
movq %rax, 192(%rsp)
leaq 56(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rax
movq %rax, 208(%rsp)
leaq 40(%rsp), %rax
movq %rax, 216(%rsp)
leaq 32(%rsp), %rax
movq %rax, 224(%rsp)
leaq 24(%rsp), %rax
movq %rax, 232(%rsp)
leaq 16(%rsp), %rax
movq %rax, 240(%rsp)
leaq 8(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 104(%rsp)
.cfi_def_cfa_offset 304
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z8update_eiiiPfS_S_S_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_, .-_Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_
.globl _Z8update_eiiiPfS_S_S_S_S_S_S_S_
.type _Z8update_eiiiPfS_S_S_S_S_S_S_S_, @function
_Z8update_eiiiPfS_S_S_S_S_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 56(%rsp)
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z46__device_stub__Z8update_eiiiPfS_S_S_S_S_S_S_S_iiiPfS_S_S_S_S_S_S_S_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8update_eiiiPfS_S_S_S_S_S_S_S_, .-_Z8update_eiiiPfS_S_S_S_S_S_S_S_
.globl _Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_
.type _Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_, @function
_Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movq %rcx, 40(%rsp)
movq %r8, 32(%rsp)
movq %r9, 24(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq 232(%rsp), %rax
movq %rax, 8(%rsp)
movq 240(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z8update_hiiiPfS_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_, .-_Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_
.globl _Z8update_hiiiPfS_S_S_S_S_
.type _Z8update_hiiiPfS_S_S_S_S_, @function
_Z8update_hiiiPfS_S_S_S_S_:
.LFB2054:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z40__device_stub__Z8update_hiiiPfS_S_S_S_S_iiiPfS_S_S_S_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z8update_hiiiPfS_S_S_S_S_, .-_Z8update_hiiiPfS_S_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8update_hiiiPfS_S_S_S_S_"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z8update_eiiiPfS_S_S_S_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8update_hiiiPfS_S_S_S_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8update_eiiiPfS_S_S_S_S_S_S_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dielectric.hip"
.globl _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_ # -- Begin function _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_,@function
_Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_: # @_Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8update_eiiiPfS_S_S_S_S_S_S_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_, .Lfunc_end0-_Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_
.cfi_endproc
# -- End function
.globl _Z23__device_stub__update_hiiiPfS_S_S_S_S_ # -- Begin function _Z23__device_stub__update_hiiiPfS_S_S_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__update_hiiiPfS_S_S_S_S_,@function
_Z23__device_stub__update_hiiiPfS_S_S_S_S_: # @_Z23__device_stub__update_hiiiPfS_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8update_hiiiPfS_S_S_S_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z23__device_stub__update_hiiiPfS_S_S_S_S_, .Lfunc_end1-_Z23__device_stub__update_hiiiPfS_S_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8update_eiiiPfS_S_S_S_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8update_hiiiPfS_S_S_S_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8update_eiiiPfS_S_S_S_S_S_S_S_,@object # @_Z8update_eiiiPfS_S_S_S_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z8update_eiiiPfS_S_S_S_S_S_S_S_
.p2align 3, 0x0
_Z8update_eiiiPfS_S_S_S_S_S_S_S_:
.quad _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_
.size _Z8update_eiiiPfS_S_S_S_S_S_S_S_, 8
.type _Z8update_hiiiPfS_S_S_S_S_,@object # @_Z8update_hiiiPfS_S_S_S_S_
.globl _Z8update_hiiiPfS_S_S_S_S_
.p2align 3, 0x0
_Z8update_hiiiPfS_S_S_S_S_:
.quad _Z23__device_stub__update_hiiiPfS_S_S_S_S_
.size _Z8update_hiiiPfS_S_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8update_eiiiPfS_S_S_S_S_S_S_S_"
.size .L__unnamed_1, 33
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8update_hiiiPfS_S_S_S_S_"
.size .L__unnamed_2, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__update_eiiiPfS_S_S_S_S_S_S_S_
.addrsig_sym _Z23__device_stub__update_hiiiPfS_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8update_eiiiPfS_S_S_S_S_S_S_S_
.addrsig_sym _Z8update_hiiiPfS_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void SetMatrixVauleMinMaxY( float* matrix, int cols, int size, int id_min, int id_max, float value)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int id_row = id / cols;
if (id_row >= id_min && id_row <= id_max && id < size)
matrix[id] = value;
} | code for sm_80
Function : _Z21SetMatrixVauleMinMaxYPfiiiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R9, c[0x0][0x168] ; /* 0x00005a0000097a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e260000002600 */
/*0030*/ I2F.RP R4, R9 ; /* 0x0000000900047306 */
/* 0x000e620000209400 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea60000002100 */
/*0060*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e620000001000 */
/*0070*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0205 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fe200078e0207 */
/*0090*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x002fc80007ffe0ff */
/*00a0*/ IABS R4, R0 ; /* 0x0000000000047213 */
/* 0x000fe20000000000 */
/*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00d0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*00e0*/ IMAD R5, R6, R9, RZ ; /* 0x0000000906057224 */
/* 0x000fc800078e02ff */
/*00f0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*0100*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD.MOV R2, RZ, RZ, -R3 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a03 */
/*0120*/ IMAD R2, R9, R2, R4 ; /* 0x0000000209027224 */
/* 0x000fca00078e0204 */
/*0130*/ ISETP.GT.U32.AND P2, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fda0003f44070 */
/*0140*/ @!P2 IADD3 R2, R2, -R9.reuse, RZ ; /* 0x800000090202a210 */
/* 0x080fe40007ffe0ff */
/*0150*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0160*/ ISETP.GE.U32.AND P0, PT, R2, R9, PT ; /* 0x000000090200720c */
/* 0x000fe40003f06070 */
/*0170*/ LOP3.LUT R2, R0, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0000027a12 */
/* 0x000fe400078e3cff */
/*0180*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f45270 */
/*0190*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f26270 */
/*01a0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fcc0007ffe0ff */
/*01b0*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*01c0*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff03aa12 */
/* 0x000fc800078e33ff */
/*01d0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fc80003f06270 */
/*01e0*/ ISETP.GT.OR P0, PT, R3, c[0x0][0x174], !P0 ; /* 0x00005d0003007a0c */
/* 0x000fc80004704670 */
/*01f0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x16c], P0 ; /* 0x00005b0000007a0c */
/* 0x000fda0000706670 */
/*0200*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0220*/ MOV R5, c[0x0][0x178] ; /* 0x00005e0000057a02 */
/* 0x000fe20000000f00 */
/*0230*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0240*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0250*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void SetMatrixVauleMinMaxY( float* matrix, int cols, int size, int id_min, int id_max, float value)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int id_row = id / cols;
if (id_row >= id_min && id_row <= id_max && id < size)
matrix[id] = value;
} | .file "tmpxft_001782a9_00000000-6_SetMatrixVauleMinMaxY.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z21SetMatrixVauleMinMaxYPfiiiifPfiiiif
.type _Z46__device_stub__Z21SetMatrixVauleMinMaxYPfiiiifPfiiiif, @function
_Z46__device_stub__Z21SetMatrixVauleMinMaxYPfiiiifPfiiiif:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21SetMatrixVauleMinMaxYPfiiiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z21SetMatrixVauleMinMaxYPfiiiifPfiiiif, .-_Z46__device_stub__Z21SetMatrixVauleMinMaxYPfiiiifPfiiiif
.globl _Z21SetMatrixVauleMinMaxYPfiiiif
.type _Z21SetMatrixVauleMinMaxYPfiiiif, @function
_Z21SetMatrixVauleMinMaxYPfiiiif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21SetMatrixVauleMinMaxYPfiiiifPfiiiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21SetMatrixVauleMinMaxYPfiiiif, .-_Z21SetMatrixVauleMinMaxYPfiiiif
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21SetMatrixVauleMinMaxYPfiiiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21SetMatrixVauleMinMaxYPfiiiif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void SetMatrixVauleMinMaxY( float* matrix, int cols, int size, int id_min, int id_max, float value)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int id_row = id / cols;
if (id_row >= id_min && id_row <= id_max && id < size)
matrix[id] = value;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void SetMatrixVauleMinMaxY( float* matrix, int cols, int size, int id_min, int id_max, float value)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int id_row = id / cols;
if (id_row >= id_min && id_row <= id_max && id < size)
matrix[id] = value;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void SetMatrixVauleMinMaxY( float* matrix, int cols, int size, int id_min, int id_max, float value)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int id_row = id / cols;
if (id_row >= id_min && id_row <= id_max && id < size)
matrix[id] = value;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21SetMatrixVauleMinMaxYPfiiiif
.globl _Z21SetMatrixVauleMinMaxYPfiiiif
.p2align 8
.type _Z21SetMatrixVauleMinMaxYPfiiiif,@function
_Z21SetMatrixVauleMinMaxYPfiiiif:
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x20
s_load_b32 s3, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s8, s4, 31
s_mul_i32 s2, s2, s15
s_add_i32 s4, s4, s8
s_and_b32 s3, s3, 0xffff
s_xor_b32 s4, s4, s8
s_add_i32 s2, s2, s14
v_cvt_f32_u32_e32 v1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_sub_i32 s2, 0, s4
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_gt_i32_e64 s3, s5, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s8, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s4
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v3
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v2
v_cmp_le_i32_e32 vcc_lo, s6, v0
v_cmp_ge_i32_e64 s2, s7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21SetMatrixVauleMinMaxYPfiiiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21SetMatrixVauleMinMaxYPfiiiif, .Lfunc_end0-_Z21SetMatrixVauleMinMaxYPfiiiif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21SetMatrixVauleMinMaxYPfiiiif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21SetMatrixVauleMinMaxYPfiiiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void SetMatrixVauleMinMaxY( float* matrix, int cols, int size, int id_min, int id_max, float value)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int id_row = id / cols;
if (id_row >= id_min && id_row <= id_max && id < size)
matrix[id] = value;
} | .text
.file "SetMatrixVauleMinMaxY.hip"
.globl _Z36__device_stub__SetMatrixVauleMinMaxYPfiiiif # -- Begin function _Z36__device_stub__SetMatrixVauleMinMaxYPfiiiif
.p2align 4, 0x90
.type _Z36__device_stub__SetMatrixVauleMinMaxYPfiiiif,@function
_Z36__device_stub__SetMatrixVauleMinMaxYPfiiiif: # @_Z36__device_stub__SetMatrixVauleMinMaxYPfiiiif
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21SetMatrixVauleMinMaxYPfiiiif, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z36__device_stub__SetMatrixVauleMinMaxYPfiiiif, .Lfunc_end0-_Z36__device_stub__SetMatrixVauleMinMaxYPfiiiif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21SetMatrixVauleMinMaxYPfiiiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21SetMatrixVauleMinMaxYPfiiiif,@object # @_Z21SetMatrixVauleMinMaxYPfiiiif
.section .rodata,"a",@progbits
.globl _Z21SetMatrixVauleMinMaxYPfiiiif
.p2align 3, 0x0
_Z21SetMatrixVauleMinMaxYPfiiiif:
.quad _Z36__device_stub__SetMatrixVauleMinMaxYPfiiiif
.size _Z21SetMatrixVauleMinMaxYPfiiiif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21SetMatrixVauleMinMaxYPfiiiif"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__SetMatrixVauleMinMaxYPfiiiif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21SetMatrixVauleMinMaxYPfiiiif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21SetMatrixVauleMinMaxYPfiiiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R9, c[0x0][0x168] ; /* 0x00005a0000097a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e260000002600 */
/*0030*/ I2F.RP R4, R9 ; /* 0x0000000900047306 */
/* 0x000e620000209400 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea60000002100 */
/*0060*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e620000001000 */
/*0070*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0205 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fe200078e0207 */
/*0090*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x002fc80007ffe0ff */
/*00a0*/ IABS R4, R0 ; /* 0x0000000000047213 */
/* 0x000fe20000000000 */
/*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00d0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*00e0*/ IMAD R5, R6, R9, RZ ; /* 0x0000000906057224 */
/* 0x000fc800078e02ff */
/*00f0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*0100*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD.MOV R2, RZ, RZ, -R3 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a03 */
/*0120*/ IMAD R2, R9, R2, R4 ; /* 0x0000000209027224 */
/* 0x000fca00078e0204 */
/*0130*/ ISETP.GT.U32.AND P2, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fda0003f44070 */
/*0140*/ @!P2 IADD3 R2, R2, -R9.reuse, RZ ; /* 0x800000090202a210 */
/* 0x080fe40007ffe0ff */
/*0150*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0160*/ ISETP.GE.U32.AND P0, PT, R2, R9, PT ; /* 0x000000090200720c */
/* 0x000fe40003f06070 */
/*0170*/ LOP3.LUT R2, R0, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0000027a12 */
/* 0x000fe400078e3cff */
/*0180*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f45270 */
/*0190*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f26270 */
/*01a0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fcc0007ffe0ff */
/*01b0*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*01c0*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff03aa12 */
/* 0x000fc800078e33ff */
/*01d0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fc80003f06270 */
/*01e0*/ ISETP.GT.OR P0, PT, R3, c[0x0][0x174], !P0 ; /* 0x00005d0003007a0c */
/* 0x000fc80004704670 */
/*01f0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x16c], P0 ; /* 0x00005b0000007a0c */
/* 0x000fda0000706670 */
/*0200*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0220*/ MOV R5, c[0x0][0x178] ; /* 0x00005e0000057a02 */
/* 0x000fe20000000f00 */
/*0230*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0240*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0250*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21SetMatrixVauleMinMaxYPfiiiif
.globl _Z21SetMatrixVauleMinMaxYPfiiiif
.p2align 8
.type _Z21SetMatrixVauleMinMaxYPfiiiif,@function
_Z21SetMatrixVauleMinMaxYPfiiiif:
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x20
s_load_b32 s3, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s8, s4, 31
s_mul_i32 s2, s2, s15
s_add_i32 s4, s4, s8
s_and_b32 s3, s3, 0xffff
s_xor_b32 s4, s4, s8
s_add_i32 s2, s2, s14
v_cvt_f32_u32_e32 v1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_sub_i32 s2, 0, s4
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_gt_i32_e64 s3, s5, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s8, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s4
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v3
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v2
v_cmp_le_i32_e32 vcc_lo, s6, v0
v_cmp_ge_i32_e64 s2, s7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21SetMatrixVauleMinMaxYPfiiiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21SetMatrixVauleMinMaxYPfiiiif, .Lfunc_end0-_Z21SetMatrixVauleMinMaxYPfiiiif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21SetMatrixVauleMinMaxYPfiiiif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21SetMatrixVauleMinMaxYPfiiiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001782a9_00000000-6_SetMatrixVauleMinMaxY.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z21SetMatrixVauleMinMaxYPfiiiifPfiiiif
.type _Z46__device_stub__Z21SetMatrixVauleMinMaxYPfiiiifPfiiiif, @function
_Z46__device_stub__Z21SetMatrixVauleMinMaxYPfiiiifPfiiiif:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21SetMatrixVauleMinMaxYPfiiiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z21SetMatrixVauleMinMaxYPfiiiifPfiiiif, .-_Z46__device_stub__Z21SetMatrixVauleMinMaxYPfiiiifPfiiiif
.globl _Z21SetMatrixVauleMinMaxYPfiiiif
.type _Z21SetMatrixVauleMinMaxYPfiiiif, @function
_Z21SetMatrixVauleMinMaxYPfiiiif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21SetMatrixVauleMinMaxYPfiiiifPfiiiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21SetMatrixVauleMinMaxYPfiiiif, .-_Z21SetMatrixVauleMinMaxYPfiiiif
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21SetMatrixVauleMinMaxYPfiiiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21SetMatrixVauleMinMaxYPfiiiif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "SetMatrixVauleMinMaxY.hip"
.globl _Z36__device_stub__SetMatrixVauleMinMaxYPfiiiif # -- Begin function _Z36__device_stub__SetMatrixVauleMinMaxYPfiiiif
.p2align 4, 0x90
.type _Z36__device_stub__SetMatrixVauleMinMaxYPfiiiif,@function
_Z36__device_stub__SetMatrixVauleMinMaxYPfiiiif: # @_Z36__device_stub__SetMatrixVauleMinMaxYPfiiiif
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21SetMatrixVauleMinMaxYPfiiiif, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z36__device_stub__SetMatrixVauleMinMaxYPfiiiif, .Lfunc_end0-_Z36__device_stub__SetMatrixVauleMinMaxYPfiiiif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21SetMatrixVauleMinMaxYPfiiiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21SetMatrixVauleMinMaxYPfiiiif,@object # @_Z21SetMatrixVauleMinMaxYPfiiiif
.section .rodata,"a",@progbits
.globl _Z21SetMatrixVauleMinMaxYPfiiiif
.p2align 3, 0x0
_Z21SetMatrixVauleMinMaxYPfiiiif:
.quad _Z36__device_stub__SetMatrixVauleMinMaxYPfiiiif
.size _Z21SetMatrixVauleMinMaxYPfiiiif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21SetMatrixVauleMinMaxYPfiiiif"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__SetMatrixVauleMinMaxYPfiiiif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21SetMatrixVauleMinMaxYPfiiiif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void blur(unsigned char* input_image, unsigned char* output_image, int const width, int const height) {
unsigned int const pixel_offset = blockIdx.x * blockDim.x + threadIdx.x;
int const x = pixel_offset % width;
int const y = pixel_offset / width;
int const filter_size = 5;
if (pixel_offset < (width * height)) {
float output_red = 0;
float output_green = 0;
float output_blue = 0;
int hits = 0;
for (int ox = -filter_size; ox <= filter_size; ++ox) {
for (int oy = -filter_size; oy <= filter_size; ++oy) {
if ((x + ox) >= 0 && (x + ox) < width && (y + oy) >= 0 && (y + oy) < height) {
int const color_offset = (pixel_offset + ox + oy * width) * 3;
output_red += input_image[color_offset];
output_green += input_image[color_offset + 1];
output_blue += input_image[color_offset + 2];
++hits;
}
}
}
output_image[pixel_offset * 3] = output_red / hits;
output_image[pixel_offset * 3 + 1] = output_green / hits;
output_image[pixel_offset * 3 + 2] = output_blue / hits;
}
}
void filter(unsigned char* input_image, unsigned char* output_image, unsigned int const width, unsigned int const height) {
unsigned char *dev_input;
unsigned char *dev_output;
unsigned int const size = width * height * 3;
cudaMallocManaged(reinterpret_cast<void **>(&dev_input), size * sizeof(unsigned char));
cudaMallocManaged(reinterpret_cast<void **>(&dev_output), size * sizeof(unsigned char));
memcpy(dev_input, input_image, size * sizeof(unsigned char));
cudaDeviceSynchronize();
dim3 blockDims { 128 };
dim3 gridDims { (width * height + 127) / 128 };
blur<<< gridDims, blockDims >>>(dev_input, dev_output, width, height);
cudaDeviceSynchronize();
memcpy(output_image, dev_output, size * sizeof(unsigned char));
cudaFree(dev_input);
cudaFree(dev_output);
} | .file "tmpxft_000e73c2_00000000-6_filter.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z4blurPhS_iiPhS_ii
.type _Z27__device_stub__Z4blurPhS_iiPhS_ii, @function
_Z27__device_stub__Z4blurPhS_iiPhS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4blurPhS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z27__device_stub__Z4blurPhS_iiPhS_ii, .-_Z27__device_stub__Z4blurPhS_iiPhS_ii
.globl _Z4blurPhS_ii
.type _Z4blurPhS_ii, @function
_Z4blurPhS_ii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z4blurPhS_iiPhS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z4blurPhS_ii, .-_Z4blurPhS_ii
.globl _Z6filterPhS_jj
.type _Z6filterPhS_jj, @function
_Z6filterPhS_jj:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r15
movq %rsi, %r14
movl %edx, %r12d
movl %ecx, %r13d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %edx, %ebx
imull %ecx, %ebx
leal (%rbx,%rbx,2), %ebp
movq %rsp, %rdi
movl $1, %edx
movq %rbp, %rsi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movq %rbp, %rsi
call cudaMallocManaged@PLT
movq %rbp, %rdx
movq %r15, %rsi
movq (%rsp), %rdi
call memcpy@PLT
call cudaDeviceSynchronize@PLT
movl $128, 16(%rsp)
movl $1, 20(%rsp)
addl $127, %ebx
shrl $7, %ebx
movl %ebx, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaDeviceSynchronize@PLT
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq %r14, %rdi
call memcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %r13d, %ecx
movl %r12d, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z27__device_stub__Z4blurPhS_iiPhS_ii
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size _Z6filterPhS_jj, .-_Z6filterPhS_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4blurPhS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4blurPhS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void blur(unsigned char* input_image, unsigned char* output_image, int const width, int const height) {
unsigned int const pixel_offset = blockIdx.x * blockDim.x + threadIdx.x;
int const x = pixel_offset % width;
int const y = pixel_offset / width;
int const filter_size = 5;
if (pixel_offset < (width * height)) {
float output_red = 0;
float output_green = 0;
float output_blue = 0;
int hits = 0;
for (int ox = -filter_size; ox <= filter_size; ++ox) {
for (int oy = -filter_size; oy <= filter_size; ++oy) {
if ((x + ox) >= 0 && (x + ox) < width && (y + oy) >= 0 && (y + oy) < height) {
int const color_offset = (pixel_offset + ox + oy * width) * 3;
output_red += input_image[color_offset];
output_green += input_image[color_offset + 1];
output_blue += input_image[color_offset + 2];
++hits;
}
}
}
output_image[pixel_offset * 3] = output_red / hits;
output_image[pixel_offset * 3 + 1] = output_green / hits;
output_image[pixel_offset * 3 + 2] = output_blue / hits;
}
}
void filter(unsigned char* input_image, unsigned char* output_image, unsigned int const width, unsigned int const height) {
unsigned char *dev_input;
unsigned char *dev_output;
unsigned int const size = width * height * 3;
cudaMallocManaged(reinterpret_cast<void **>(&dev_input), size * sizeof(unsigned char));
cudaMallocManaged(reinterpret_cast<void **>(&dev_output), size * sizeof(unsigned char));
memcpy(dev_input, input_image, size * sizeof(unsigned char));
cudaDeviceSynchronize();
dim3 blockDims { 128 };
dim3 gridDims { (width * height + 127) / 128 };
blur<<< gridDims, blockDims >>>(dev_input, dev_output, width, height);
cudaDeviceSynchronize();
memcpy(output_image, dev_output, size * sizeof(unsigned char));
cudaFree(dev_input);
cudaFree(dev_output);
} | #include <hip/hip_runtime.h>
__global__ void blur(unsigned char* input_image, unsigned char* output_image, int const width, int const height) {
unsigned int const pixel_offset = blockIdx.x * blockDim.x + threadIdx.x;
int const x = pixel_offset % width;
int const y = pixel_offset / width;
int const filter_size = 5;
if (pixel_offset < (width * height)) {
float output_red = 0;
float output_green = 0;
float output_blue = 0;
int hits = 0;
for (int ox = -filter_size; ox <= filter_size; ++ox) {
for (int oy = -filter_size; oy <= filter_size; ++oy) {
if ((x + ox) >= 0 && (x + ox) < width && (y + oy) >= 0 && (y + oy) < height) {
int const color_offset = (pixel_offset + ox + oy * width) * 3;
output_red += input_image[color_offset];
output_green += input_image[color_offset + 1];
output_blue += input_image[color_offset + 2];
++hits;
}
}
}
output_image[pixel_offset * 3] = output_red / hits;
output_image[pixel_offset * 3 + 1] = output_green / hits;
output_image[pixel_offset * 3 + 2] = output_blue / hits;
}
}
void filter(unsigned char* input_image, unsigned char* output_image, unsigned int const width, unsigned int const height) {
unsigned char *dev_input;
unsigned char *dev_output;
unsigned int const size = width * height * 3;
hipMallocManaged(reinterpret_cast<void **>(&dev_input), size * sizeof(unsigned char));
hipMallocManaged(reinterpret_cast<void **>(&dev_output), size * sizeof(unsigned char));
memcpy(dev_input, input_image, size * sizeof(unsigned char));
hipDeviceSynchronize();
dim3 blockDims { 128 };
dim3 gridDims { (width * height + 127) / 128 };
blur<<< gridDims, blockDims >>>(dev_input, dev_output, width, height);
hipDeviceSynchronize();
memcpy(output_image, dev_output, size * sizeof(unsigned char));
hipFree(dev_input);
hipFree(dev_output);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void blur(unsigned char* input_image, unsigned char* output_image, int const width, int const height) {
unsigned int const pixel_offset = blockIdx.x * blockDim.x + threadIdx.x;
int const x = pixel_offset % width;
int const y = pixel_offset / width;
int const filter_size = 5;
if (pixel_offset < (width * height)) {
float output_red = 0;
float output_green = 0;
float output_blue = 0;
int hits = 0;
for (int ox = -filter_size; ox <= filter_size; ++ox) {
for (int oy = -filter_size; oy <= filter_size; ++oy) {
if ((x + ox) >= 0 && (x + ox) < width && (y + oy) >= 0 && (y + oy) < height) {
int const color_offset = (pixel_offset + ox + oy * width) * 3;
output_red += input_image[color_offset];
output_green += input_image[color_offset + 1];
output_blue += input_image[color_offset + 2];
++hits;
}
}
}
output_image[pixel_offset * 3] = output_red / hits;
output_image[pixel_offset * 3 + 1] = output_green / hits;
output_image[pixel_offset * 3 + 2] = output_blue / hits;
}
}
void filter(unsigned char* input_image, unsigned char* output_image, unsigned int const width, unsigned int const height) {
unsigned char *dev_input;
unsigned char *dev_output;
unsigned int const size = width * height * 3;
hipMallocManaged(reinterpret_cast<void **>(&dev_input), size * sizeof(unsigned char));
hipMallocManaged(reinterpret_cast<void **>(&dev_output), size * sizeof(unsigned char));
memcpy(dev_input, input_image, size * sizeof(unsigned char));
hipDeviceSynchronize();
dim3 blockDims { 128 };
dim3 gridDims { (width * height + 127) / 128 };
blur<<< gridDims, blockDims >>>(dev_input, dev_output, width, height);
hipDeviceSynchronize();
memcpy(output_image, dev_output, size * sizeof(unsigned char));
hipFree(dev_input);
hipFree(dev_output);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4blurPhS_ii
.globl _Z4blurPhS_ii
.p2align 8
.type _Z4blurPhS_ii,@function
_Z4blurPhS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s2
s_mul_i32 s2, s5, s4
v_add_nc_u32_e32 v2, s15, v0
v_cmp_gt_u32_e32 vcc_lo, s2, v2
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_10
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s2, 0, s4
s_load_b64 s[6:7], s[0:1], 0x0
s_mul_i32 s3, s4, 3
s_mov_b32 s8, -5
v_rcp_iflag_f32_e32 v0, v0
v_mov_b32_e32 v6, 0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v1, s2, v0
s_mul_i32 s2, s4, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v7, s2, v2
v_mul_hi_u32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v0, v1
v_mad_u64_u32 v[0:1], null, v2, v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, v1, s4
v_add_nc_u32_e32 v3, 1, v1
v_sub_nc_u32_e32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_dual_cndmask_b32 v1, v1, v3 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, 1, v1
v_cmp_le_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v5, v1, v3, vcc_lo
v_mad_u64_u32 v[0:1], null, v7, 3, -15
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v1, 0
v_mul_lo_u32 v4, v5, s4
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v7, v2, v4
v_mov_b32_e32 v4, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v0, 3, v0
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, 6
s_cbranch_scc1 .LBB0_9
.LBB0_3:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v8, s8, v7
s_mov_b32 s10, -5
v_cmp_lt_i32_e32 vcc_lo, -1, v8
v_cmp_gt_i32_e64 s2, s4, v8
v_mov_b32_e32 v8, v0
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s9, vcc_lo, s2
s_branch .LBB0_6
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v8, s3, v8
s_add_i32 s10, s10, 1
s_cmp_eq_u32 s10, 6
s_cbranch_scc1 .LBB0_2
.LBB0_6:
s_and_saveexec_b32 s11, s9
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v9, s10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v9
v_cmp_gt_i32_e64 s2, s5, v9
s_and_b32 s12, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s12
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v10, 31, v8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s6, v8
v_add_nc_u32_e32 v6, 1, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
s_clause 0x2
global_load_u8 v11, v[9:10], off
global_load_u8 v12, v[9:10], off offset:1
global_load_u8 v9, v[9:10], off offset:2
s_waitcnt vmcnt(2)
v_cvt_f32_ubyte0_e32 v10, v11
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v11, v12
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v9, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v3, v3, v10 :: v_dual_add_f32 v4, v4, v11
v_add_f32_e32 v1, v1, v9
s_branch .LBB0_4
.LBB0_9:
s_set_inst_prefetch_distance 0x2
v_cvt_f32_i32_e32 v0, v6
s_load_b64 s[0:1], s[0:1], 0x8
v_lshl_add_u32 v2, v2, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_scale_f32 v5, null, v0, v0, v3
v_div_scale_f32 v6, null, v0, v0, v4
v_div_scale_f32 v7, null, v0, v0, v1
v_rcp_f32_e32 v8, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v9, v6
v_div_scale_f32 v11, vcc_lo, v3, v0, v3
v_rcp_f32_e32 v10, v7
v_div_scale_f32 v12, s2, v4, v0, v4
v_div_scale_f32 v16, s3, v1, v0, v1
s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f32 v13, -v5, v8, 1.0
s_waitcnt_depctr 0xfff
v_fma_f32 v14, -v6, v9, 1.0
v_fma_f32 v15, -v7, v10, 1.0
v_dual_fmac_f32 v8, v13, v8 :: v_dual_fmac_f32 v9, v14, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v13, v11, v8 :: v_dual_mul_f32 v14, v12, v9
v_fma_f32 v17, -v5, v13, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v10, v15, v10
v_fma_f32 v18, -v6, v14, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v13, v17, v8
v_dual_mul_f32 v15, v16, v10 :: v_dual_fmac_f32 v14, v18, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v5, v13, v11
v_fma_f32 v19, -v7, v15, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v6, -v6, v14, v12
v_div_fmas_f32 v5, v5, v8, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v15, v19, v10
s_mov_b32 vcc_lo, s2
v_div_fmas_f32 v6, v6, v9, v14
s_mov_b32 vcc_lo, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_fma_f32 v7, -v7, v15, v16
v_div_fixup_f32 v3, v5, v0, v3
v_add_nc_u32_e32 v5, 2, v2
v_div_fixup_f32 v4, v6, v0, v4
v_div_fmas_f32 v7, v7, v10, v15
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_i32_f32_e32 v3, v3
v_cvt_i32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fixup_f32 v0, v7, v0, v1
v_add_nc_u32_e32 v1, 1, v2
v_cvt_i32_f32_e32 v0, v0
s_waitcnt lgkmcnt(0)
s_clause 0x2
global_store_b8 v2, v3, s[0:1]
global_store_b8 v1, v4, s[0:1]
global_store_b8 v5, v0, s[0:1]
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4blurPhS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4blurPhS_ii, .Lfunc_end0-_Z4blurPhS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4blurPhS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4blurPhS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void blur(unsigned char* input_image, unsigned char* output_image, int const width, int const height) {
unsigned int const pixel_offset = blockIdx.x * blockDim.x + threadIdx.x;
int const x = pixel_offset % width;
int const y = pixel_offset / width;
int const filter_size = 5;
if (pixel_offset < (width * height)) {
float output_red = 0;
float output_green = 0;
float output_blue = 0;
int hits = 0;
for (int ox = -filter_size; ox <= filter_size; ++ox) {
for (int oy = -filter_size; oy <= filter_size; ++oy) {
if ((x + ox) >= 0 && (x + ox) < width && (y + oy) >= 0 && (y + oy) < height) {
int const color_offset = (pixel_offset + ox + oy * width) * 3;
output_red += input_image[color_offset];
output_green += input_image[color_offset + 1];
output_blue += input_image[color_offset + 2];
++hits;
}
}
}
output_image[pixel_offset * 3] = output_red / hits;
output_image[pixel_offset * 3 + 1] = output_green / hits;
output_image[pixel_offset * 3 + 2] = output_blue / hits;
}
}
void filter(unsigned char* input_image, unsigned char* output_image, unsigned int const width, unsigned int const height) {
unsigned char *dev_input;
unsigned char *dev_output;
unsigned int const size = width * height * 3;
hipMallocManaged(reinterpret_cast<void **>(&dev_input), size * sizeof(unsigned char));
hipMallocManaged(reinterpret_cast<void **>(&dev_output), size * sizeof(unsigned char));
memcpy(dev_input, input_image, size * sizeof(unsigned char));
hipDeviceSynchronize();
dim3 blockDims { 128 };
dim3 gridDims { (width * height + 127) / 128 };
blur<<< gridDims, blockDims >>>(dev_input, dev_output, width, height);
hipDeviceSynchronize();
memcpy(output_image, dev_output, size * sizeof(unsigned char));
hipFree(dev_input);
hipFree(dev_output);
} | .text
.file "filter.hip"
.globl _Z19__device_stub__blurPhS_ii # -- Begin function _Z19__device_stub__blurPhS_ii
.p2align 4, 0x90
.type _Z19__device_stub__blurPhS_ii,@function
_Z19__device_stub__blurPhS_ii: # @_Z19__device_stub__blurPhS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4blurPhS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__blurPhS_ii, .Lfunc_end0-_Z19__device_stub__blurPhS_ii
.cfi_endproc
# -- End function
.globl _Z6filterPhS_jj # -- Begin function _Z6filterPhS_jj
.p2align 4, 0x90
.type _Z6filterPhS_jj,@function
_Z6filterPhS_jj: # @_Z6filterPhS_jj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r15d
movq %rsi, %rbx
movq %rdi, %r13
movl %ecx, %r12d
imull %edx, %r12d
leal (%r12,%r12,2), %r14d
leaq 16(%rsp), %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
callq memcpy@PLT
callq hipDeviceSynchronize
addl $127, %r12d
shrl $7, %r12d
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r12
orq $128, %rdx
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r15d, 28(%rsp)
movl %ebp, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4blurPhS_ii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
callq memcpy@PLT
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6filterPhS_jj, .Lfunc_end1-_Z6filterPhS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4blurPhS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4blurPhS_ii,@object # @_Z4blurPhS_ii
.section .rodata,"a",@progbits
.globl _Z4blurPhS_ii
.p2align 3, 0x0
_Z4blurPhS_ii:
.quad _Z19__device_stub__blurPhS_ii
.size _Z4blurPhS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4blurPhS_ii"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__blurPhS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4blurPhS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e73c2_00000000-6_filter.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z4blurPhS_iiPhS_ii
.type _Z27__device_stub__Z4blurPhS_iiPhS_ii, @function
_Z27__device_stub__Z4blurPhS_iiPhS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4blurPhS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z27__device_stub__Z4blurPhS_iiPhS_ii, .-_Z27__device_stub__Z4blurPhS_iiPhS_ii
.globl _Z4blurPhS_ii
.type _Z4blurPhS_ii, @function
_Z4blurPhS_ii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z4blurPhS_iiPhS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z4blurPhS_ii, .-_Z4blurPhS_ii
.globl _Z6filterPhS_jj
.type _Z6filterPhS_jj, @function
_Z6filterPhS_jj:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r15
movq %rsi, %r14
movl %edx, %r12d
movl %ecx, %r13d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %edx, %ebx
imull %ecx, %ebx
leal (%rbx,%rbx,2), %ebp
movq %rsp, %rdi
movl $1, %edx
movq %rbp, %rsi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movq %rbp, %rsi
call cudaMallocManaged@PLT
movq %rbp, %rdx
movq %r15, %rsi
movq (%rsp), %rdi
call memcpy@PLT
call cudaDeviceSynchronize@PLT
movl $128, 16(%rsp)
movl $1, 20(%rsp)
addl $127, %ebx
shrl $7, %ebx
movl %ebx, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaDeviceSynchronize@PLT
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq %r14, %rdi
call memcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %r13d, %ecx
movl %r12d, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z27__device_stub__Z4blurPhS_iiPhS_ii
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size _Z6filterPhS_jj, .-_Z6filterPhS_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4blurPhS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4blurPhS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "filter.hip"
.globl _Z19__device_stub__blurPhS_ii # -- Begin function _Z19__device_stub__blurPhS_ii
.p2align 4, 0x90
.type _Z19__device_stub__blurPhS_ii,@function
_Z19__device_stub__blurPhS_ii: # @_Z19__device_stub__blurPhS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4blurPhS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__blurPhS_ii, .Lfunc_end0-_Z19__device_stub__blurPhS_ii
.cfi_endproc
# -- End function
.globl _Z6filterPhS_jj # -- Begin function _Z6filterPhS_jj
.p2align 4, 0x90
.type _Z6filterPhS_jj,@function
_Z6filterPhS_jj: # @_Z6filterPhS_jj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r15d
movq %rsi, %rbx
movq %rdi, %r13
movl %ecx, %r12d
imull %edx, %r12d
leal (%r12,%r12,2), %r14d
leaq 16(%rsp), %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
callq memcpy@PLT
callq hipDeviceSynchronize
addl $127, %r12d
shrl $7, %r12d
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r12
orq $128, %rdx
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r15d, 28(%rsp)
movl %ebp, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4blurPhS_ii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
callq memcpy@PLT
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6filterPhS_jj, .Lfunc_end1-_Z6filterPhS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4blurPhS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4blurPhS_ii,@object # @_Z4blurPhS_ii
.section .rodata,"a",@progbits
.globl _Z4blurPhS_ii
.p2align 3, 0x0
_Z4blurPhS_ii:
.quad _Z19__device_stub__blurPhS_ii
.size _Z4blurPhS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4blurPhS_ii"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__blurPhS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4blurPhS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #pragma once
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__global__ void LinearAddIntsKernel(int *d_out, const int *d_in, unsigned int length)
{
__shared__ int cache[512];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
int cumer = 0;
while (tid < length)
{
cumer += d_in[tid];
tid += blockDim.x * gridDim.x;
}
cache[cacheIndex] = cumer;
__syncthreads();
int i = blockDim.x / 2;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
for (int i = 0; i < blockDim.x; i++)
{
d_out[blockIdx.x] = cache[0];
}
}
}
__global__ void BlockAddInts_32_Kernel(int *d_out, const int *d_in)
{
__shared__ int cache[1024];
int cacheIndex = threadIdx.y + threadIdx.x * blockDim.x;
int span = gridDim.x * blockDim.x;
int rowIn = threadIdx.y + blockIdx.y * blockDim.y;
int colIn = threadIdx.x + blockIdx.x * blockDim.x;
int indexIn = rowIn + colIn * span;
int indexOut = blockIdx.y + blockIdx.x * gridDim.x;
cache[cacheIndex] = d_in[indexIn];
__syncthreads();
int i = 512;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
d_out[indexOut] = cache[0];
}
}
__global__ void BlockAddInts_16_Kernel(int *d_out, const int *d_in)
{
__shared__ int cache[256];
int cacheIndex = threadIdx.y + threadIdx.x * blockDim.x;
int span = gridDim.x * blockDim.x;
int rowIn = threadIdx.y + blockIdx.y * blockDim.y;
int colIn = threadIdx.x + blockIdx.x * blockDim.x;
int indexIn = rowIn + colIn * span;
int indexOut = blockIdx.y + blockIdx.x * gridDim.x;
cache[cacheIndex] = d_in[indexIn];
__syncthreads();
int i = 128;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
d_out[indexOut] = cache[0];
}
}
__global__ void LinearAddFloatsKernel(float *d_out, const float *d_in, unsigned int length)
{
__shared__ float cache[512];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
int cumer = 0;
while (tid < length)
{
cumer += d_in[tid];
tid += blockDim.x * gridDim.x;
}
cache[cacheIndex] = cumer;
__syncthreads();
int i = blockDim.x / 2;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
for (int i = 0; i < blockDim.x; i++)
{
d_out[blockIdx.x] = cache[0];
}
}
}
__global__ void BlockAddFloats_32_Kernel(float *d_out, const float *d_in)
{
__shared__ float cache[1024];
int cacheIndex = threadIdx.y + threadIdx.x * blockDim.x;
int span = gridDim.x * blockDim.x;
int rowIn = threadIdx.y + blockIdx.y * blockDim.y;
int colIn = threadIdx.x + blockIdx.x * blockDim.x;
int indexIn = rowIn + colIn * span;
int indexOut = blockIdx.y + blockIdx.x * gridDim.x;
cache[cacheIndex] = d_in[indexIn];
__syncthreads();
int i = 512;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
d_out[indexOut] = cache[0];
}
}
__global__ void BlockAddFloats_16_Kernel(float *d_out, const float *d_in)
{
__shared__ float cache[256];
int cacheIndex = threadIdx.y + threadIdx.x * blockDim.x;
int span = gridDim.x * blockDim.x;
int rowIn = threadIdx.y + blockIdx.y * blockDim.y;
int colIn = threadIdx.x + blockIdx.x * blockDim.x;
int indexIn = rowIn + colIn * span;
int indexOut = blockIdx.y + blockIdx.x * gridDim.x;
cache[cacheIndex] = d_in[indexIn];
__syncthreads();
int i = 128;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
d_out[indexOut] = cache[0];
}
} | .file "tmpxft_001b8e55_00000000-6_CuArrayKernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z19LinearAddIntsKernelPiPKijPiPKij
.type _Z43__device_stub__Z19LinearAddIntsKernelPiPKijPiPKij, @function
_Z43__device_stub__Z19LinearAddIntsKernelPiPKijPiPKij:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19LinearAddIntsKernelPiPKij(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z19LinearAddIntsKernelPiPKijPiPKij, .-_Z43__device_stub__Z19LinearAddIntsKernelPiPKijPiPKij
.globl _Z19LinearAddIntsKernelPiPKij
.type _Z19LinearAddIntsKernelPiPKij, @function
_Z19LinearAddIntsKernelPiPKij:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19LinearAddIntsKernelPiPKijPiPKij
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19LinearAddIntsKernelPiPKij, .-_Z19LinearAddIntsKernelPiPKij
.globl _Z45__device_stub__Z22BlockAddInts_32_KernelPiPKiPiPKi
.type _Z45__device_stub__Z22BlockAddInts_32_KernelPiPKiPiPKi, @function
_Z45__device_stub__Z22BlockAddInts_32_KernelPiPKiPiPKi:
.LFB2053:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z22BlockAddInts_32_KernelPiPKi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z45__device_stub__Z22BlockAddInts_32_KernelPiPKiPiPKi, .-_Z45__device_stub__Z22BlockAddInts_32_KernelPiPKiPiPKi
.globl _Z22BlockAddInts_32_KernelPiPKi
.type _Z22BlockAddInts_32_KernelPiPKi, @function
_Z22BlockAddInts_32_KernelPiPKi:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z22BlockAddInts_32_KernelPiPKiPiPKi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z22BlockAddInts_32_KernelPiPKi, .-_Z22BlockAddInts_32_KernelPiPKi
.globl _Z45__device_stub__Z22BlockAddInts_16_KernelPiPKiPiPKi
.type _Z45__device_stub__Z22BlockAddInts_16_KernelPiPKiPiPKi, @function
_Z45__device_stub__Z22BlockAddInts_16_KernelPiPKiPiPKi:
.LFB2055:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z22BlockAddInts_16_KernelPiPKi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z45__device_stub__Z22BlockAddInts_16_KernelPiPKiPiPKi, .-_Z45__device_stub__Z22BlockAddInts_16_KernelPiPKiPiPKi
.globl _Z22BlockAddInts_16_KernelPiPKi
.type _Z22BlockAddInts_16_KernelPiPKi, @function
_Z22BlockAddInts_16_KernelPiPKi:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z22BlockAddInts_16_KernelPiPKiPiPKi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z22BlockAddInts_16_KernelPiPKi, .-_Z22BlockAddInts_16_KernelPiPKi
.globl _Z45__device_stub__Z21LinearAddFloatsKernelPfPKfjPfPKfj
.type _Z45__device_stub__Z21LinearAddFloatsKernelPfPKfjPfPKfj, @function
_Z45__device_stub__Z21LinearAddFloatsKernelPfPKfjPfPKfj:
.LFB2057:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21LinearAddFloatsKernelPfPKfj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z45__device_stub__Z21LinearAddFloatsKernelPfPKfjPfPKfj, .-_Z45__device_stub__Z21LinearAddFloatsKernelPfPKfjPfPKfj
.globl _Z21LinearAddFloatsKernelPfPKfj
.type _Z21LinearAddFloatsKernelPfPKfj, @function
_Z21LinearAddFloatsKernelPfPKfj:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z21LinearAddFloatsKernelPfPKfjPfPKfj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z21LinearAddFloatsKernelPfPKfj, .-_Z21LinearAddFloatsKernelPfPKfj
.globl _Z47__device_stub__Z24BlockAddFloats_32_KernelPfPKfPfPKf
.type _Z47__device_stub__Z24BlockAddFloats_32_KernelPfPKfPfPKf, @function
_Z47__device_stub__Z24BlockAddFloats_32_KernelPfPKfPfPKf:
.LFB2059:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z24BlockAddFloats_32_KernelPfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z47__device_stub__Z24BlockAddFloats_32_KernelPfPKfPfPKf, .-_Z47__device_stub__Z24BlockAddFloats_32_KernelPfPKfPfPKf
.globl _Z24BlockAddFloats_32_KernelPfPKf
.type _Z24BlockAddFloats_32_KernelPfPKf, @function
_Z24BlockAddFloats_32_KernelPfPKf:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z24BlockAddFloats_32_KernelPfPKfPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z24BlockAddFloats_32_KernelPfPKf, .-_Z24BlockAddFloats_32_KernelPfPKf
.globl _Z47__device_stub__Z24BlockAddFloats_16_KernelPfPKfPfPKf
.type _Z47__device_stub__Z24BlockAddFloats_16_KernelPfPKfPfPKf, @function
_Z47__device_stub__Z24BlockAddFloats_16_KernelPfPKfPfPKf:
.LFB2061:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z24BlockAddFloats_16_KernelPfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z47__device_stub__Z24BlockAddFloats_16_KernelPfPKfPfPKf, .-_Z47__device_stub__Z24BlockAddFloats_16_KernelPfPKfPfPKf
.globl _Z24BlockAddFloats_16_KernelPfPKf
.type _Z24BlockAddFloats_16_KernelPfPKf, @function
_Z24BlockAddFloats_16_KernelPfPKf:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z24BlockAddFloats_16_KernelPfPKfPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z24BlockAddFloats_16_KernelPfPKf, .-_Z24BlockAddFloats_16_KernelPfPKf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24BlockAddFloats_16_KernelPfPKf"
.align 8
.LC1:
.string "_Z24BlockAddFloats_32_KernelPfPKf"
.align 8
.LC2:
.string "_Z21LinearAddFloatsKernelPfPKfj"
.align 8
.LC3:
.string "_Z22BlockAddInts_16_KernelPiPKi"
.align 8
.LC4:
.string "_Z22BlockAddInts_32_KernelPiPKi"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "_Z19LinearAddIntsKernelPiPKij"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2064:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24BlockAddFloats_16_KernelPfPKf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z24BlockAddFloats_32_KernelPfPKf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z21LinearAddFloatsKernelPfPKfj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z22BlockAddInts_16_KernelPiPKi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z22BlockAddInts_32_KernelPiPKi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z19LinearAddIntsKernelPiPKij(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #pragma once
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__global__ void LinearAddIntsKernel(int *d_out, const int *d_in, unsigned int length)
{
__shared__ int cache[512];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
int cumer = 0;
while (tid < length)
{
cumer += d_in[tid];
tid += blockDim.x * gridDim.x;
}
cache[cacheIndex] = cumer;
__syncthreads();
int i = blockDim.x / 2;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
for (int i = 0; i < blockDim.x; i++)
{
d_out[blockIdx.x] = cache[0];
}
}
}
__global__ void BlockAddInts_32_Kernel(int *d_out, const int *d_in)
{
__shared__ int cache[1024];
int cacheIndex = threadIdx.y + threadIdx.x * blockDim.x;
int span = gridDim.x * blockDim.x;
int rowIn = threadIdx.y + blockIdx.y * blockDim.y;
int colIn = threadIdx.x + blockIdx.x * blockDim.x;
int indexIn = rowIn + colIn * span;
int indexOut = blockIdx.y + blockIdx.x * gridDim.x;
cache[cacheIndex] = d_in[indexIn];
__syncthreads();
int i = 512;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
d_out[indexOut] = cache[0];
}
}
__global__ void BlockAddInts_16_Kernel(int *d_out, const int *d_in)
{
__shared__ int cache[256];
int cacheIndex = threadIdx.y + threadIdx.x * blockDim.x;
int span = gridDim.x * blockDim.x;
int rowIn = threadIdx.y + blockIdx.y * blockDim.y;
int colIn = threadIdx.x + blockIdx.x * blockDim.x;
int indexIn = rowIn + colIn * span;
int indexOut = blockIdx.y + blockIdx.x * gridDim.x;
cache[cacheIndex] = d_in[indexIn];
__syncthreads();
int i = 128;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
d_out[indexOut] = cache[0];
}
}
__global__ void LinearAddFloatsKernel(float *d_out, const float *d_in, unsigned int length)
{
__shared__ float cache[512];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
int cumer = 0;
while (tid < length)
{
cumer += d_in[tid];
tid += blockDim.x * gridDim.x;
}
cache[cacheIndex] = cumer;
__syncthreads();
int i = blockDim.x / 2;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
for (int i = 0; i < blockDim.x; i++)
{
d_out[blockIdx.x] = cache[0];
}
}
}
__global__ void BlockAddFloats_32_Kernel(float *d_out, const float *d_in)
{
__shared__ float cache[1024];
int cacheIndex = threadIdx.y + threadIdx.x * blockDim.x;
int span = gridDim.x * blockDim.x;
int rowIn = threadIdx.y + blockIdx.y * blockDim.y;
int colIn = threadIdx.x + blockIdx.x * blockDim.x;
int indexIn = rowIn + colIn * span;
int indexOut = blockIdx.y + blockIdx.x * gridDim.x;
cache[cacheIndex] = d_in[indexIn];
__syncthreads();
int i = 512;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
d_out[indexOut] = cache[0];
}
}
__global__ void BlockAddFloats_16_Kernel(float *d_out, const float *d_in)
{
__shared__ float cache[256];
int cacheIndex = threadIdx.y + threadIdx.x * blockDim.x;
int span = gridDim.x * blockDim.x;
int rowIn = threadIdx.y + blockIdx.y * blockDim.y;
int colIn = threadIdx.x + blockIdx.x * blockDim.x;
int indexIn = rowIn + colIn * span;
int indexOut = blockIdx.y + blockIdx.x * gridDim.x;
cache[cacheIndex] = d_in[indexIn];
__syncthreads();
int i = 128;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
d_out[indexOut] = cache[0];
}
} | #pragma once
#include "hip/hip_runtime.h"
__global__ void LinearAddIntsKernel(int *d_out, const int *d_in, unsigned int length)
{
__shared__ int cache[512];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
int cumer = 0;
while (tid < length)
{
cumer += d_in[tid];
tid += blockDim.x * gridDim.x;
}
cache[cacheIndex] = cumer;
__syncthreads();
int i = blockDim.x / 2;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
for (int i = 0; i < blockDim.x; i++)
{
d_out[blockIdx.x] = cache[0];
}
}
}
__global__ void BlockAddInts_32_Kernel(int *d_out, const int *d_in)
{
__shared__ int cache[1024];
int cacheIndex = threadIdx.y + threadIdx.x * blockDim.x;
int span = gridDim.x * blockDim.x;
int rowIn = threadIdx.y + blockIdx.y * blockDim.y;
int colIn = threadIdx.x + blockIdx.x * blockDim.x;
int indexIn = rowIn + colIn * span;
int indexOut = blockIdx.y + blockIdx.x * gridDim.x;
cache[cacheIndex] = d_in[indexIn];
__syncthreads();
int i = 512;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
d_out[indexOut] = cache[0];
}
}
__global__ void BlockAddInts_16_Kernel(int *d_out, const int *d_in)
{
__shared__ int cache[256];
int cacheIndex = threadIdx.y + threadIdx.x * blockDim.x;
int span = gridDim.x * blockDim.x;
int rowIn = threadIdx.y + blockIdx.y * blockDim.y;
int colIn = threadIdx.x + blockIdx.x * blockDim.x;
int indexIn = rowIn + colIn * span;
int indexOut = blockIdx.y + blockIdx.x * gridDim.x;
cache[cacheIndex] = d_in[indexIn];
__syncthreads();
int i = 128;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
d_out[indexOut] = cache[0];
}
}
__global__ void LinearAddFloatsKernel(float *d_out, const float *d_in, unsigned int length)
{
__shared__ float cache[512];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
int cumer = 0;
while (tid < length)
{
cumer += d_in[tid];
tid += blockDim.x * gridDim.x;
}
cache[cacheIndex] = cumer;
__syncthreads();
int i = blockDim.x / 2;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
for (int i = 0; i < blockDim.x; i++)
{
d_out[blockIdx.x] = cache[0];
}
}
}
__global__ void BlockAddFloats_32_Kernel(float *d_out, const float *d_in)
{
__shared__ float cache[1024];
int cacheIndex = threadIdx.y + threadIdx.x * blockDim.x;
int span = gridDim.x * blockDim.x;
int rowIn = threadIdx.y + blockIdx.y * blockDim.y;
int colIn = threadIdx.x + blockIdx.x * blockDim.x;
int indexIn = rowIn + colIn * span;
int indexOut = blockIdx.y + blockIdx.x * gridDim.x;
cache[cacheIndex] = d_in[indexIn];
__syncthreads();
int i = 512;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
d_out[indexOut] = cache[0];
}
}
__global__ void BlockAddFloats_16_Kernel(float *d_out, const float *d_in)
{
__shared__ float cache[256];
int cacheIndex = threadIdx.y + threadIdx.x * blockDim.x;
int span = gridDim.x * blockDim.x;
int rowIn = threadIdx.y + blockIdx.y * blockDim.y;
int colIn = threadIdx.x + blockIdx.x * blockDim.x;
int indexIn = rowIn + colIn * span;
int indexOut = blockIdx.y + blockIdx.x * gridDim.x;
cache[cacheIndex] = d_in[indexIn];
__syncthreads();
int i = 128;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
d_out[indexOut] = cache[0];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma once
#include "hip/hip_runtime.h"
__global__ void LinearAddIntsKernel(int *d_out, const int *d_in, unsigned int length)
{
__shared__ int cache[512];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
int cumer = 0;
while (tid < length)
{
cumer += d_in[tid];
tid += blockDim.x * gridDim.x;
}
cache[cacheIndex] = cumer;
__syncthreads();
int i = blockDim.x / 2;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
for (int i = 0; i < blockDim.x; i++)
{
d_out[blockIdx.x] = cache[0];
}
}
}
__global__ void BlockAddInts_32_Kernel(int *d_out, const int *d_in)
{
__shared__ int cache[1024];
int cacheIndex = threadIdx.y + threadIdx.x * blockDim.x;
int span = gridDim.x * blockDim.x;
int rowIn = threadIdx.y + blockIdx.y * blockDim.y;
int colIn = threadIdx.x + blockIdx.x * blockDim.x;
int indexIn = rowIn + colIn * span;
int indexOut = blockIdx.y + blockIdx.x * gridDim.x;
cache[cacheIndex] = d_in[indexIn];
__syncthreads();
int i = 512;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
d_out[indexOut] = cache[0];
}
}
__global__ void BlockAddInts_16_Kernel(int *d_out, const int *d_in)
{
__shared__ int cache[256];
int cacheIndex = threadIdx.y + threadIdx.x * blockDim.x;
int span = gridDim.x * blockDim.x;
int rowIn = threadIdx.y + blockIdx.y * blockDim.y;
int colIn = threadIdx.x + blockIdx.x * blockDim.x;
int indexIn = rowIn + colIn * span;
int indexOut = blockIdx.y + blockIdx.x * gridDim.x;
cache[cacheIndex] = d_in[indexIn];
__syncthreads();
int i = 128;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
d_out[indexOut] = cache[0];
}
}
__global__ void LinearAddFloatsKernel(float *d_out, const float *d_in, unsigned int length)
{
__shared__ float cache[512];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
int cumer = 0;
while (tid < length)
{
cumer += d_in[tid];
tid += blockDim.x * gridDim.x;
}
cache[cacheIndex] = cumer;
__syncthreads();
int i = blockDim.x / 2;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
for (int i = 0; i < blockDim.x; i++)
{
d_out[blockIdx.x] = cache[0];
}
}
}
__global__ void BlockAddFloats_32_Kernel(float *d_out, const float *d_in)
{
__shared__ float cache[1024];
int cacheIndex = threadIdx.y + threadIdx.x * blockDim.x;
int span = gridDim.x * blockDim.x;
int rowIn = threadIdx.y + blockIdx.y * blockDim.y;
int colIn = threadIdx.x + blockIdx.x * blockDim.x;
int indexIn = rowIn + colIn * span;
int indexOut = blockIdx.y + blockIdx.x * gridDim.x;
cache[cacheIndex] = d_in[indexIn];
__syncthreads();
int i = 512;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
d_out[indexOut] = cache[0];
}
}
__global__ void BlockAddFloats_16_Kernel(float *d_out, const float *d_in)
{
__shared__ float cache[256];
int cacheIndex = threadIdx.y + threadIdx.x * blockDim.x;
int span = gridDim.x * blockDim.x;
int rowIn = threadIdx.y + blockIdx.y * blockDim.y;
int colIn = threadIdx.x + blockIdx.x * blockDim.x;
int indexIn = rowIn + colIn * span;
int indexOut = blockIdx.y + blockIdx.x * gridDim.x;
cache[cacheIndex] = d_in[indexIn];
__syncthreads();
int i = 128;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
d_out[indexOut] = cache[0];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19LinearAddIntsKernelPiPKij
.globl _Z19LinearAddIntsKernelPiPKij
.p2align 8
.type _Z19LinearAddIntsKernelPiPKij,@function
_Z19LinearAddIntsKernelPiPKij:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b32 s7, s[0:1], 0x10
s_add_u32 s4, s0, 24
s_mov_b32 s2, s15
s_addc_u32 s5, s1, 0
v_mov_b32_e32 v3, 0
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cmpx_gt_u32_e64 s7, v1
s_cbranch_execz .LBB0_4
s_load_b32 s10, s[4:5], 0x0
s_load_b64 s[4:5], s[0:1], 0x8
v_mov_b32_e32 v3, 0
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s10, s3
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s10, v1
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s7, v1
global_load_b32 v2, v[4:5], off
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v2, v3
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s9
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s8
v_cmp_lt_u16_e64 s4, s6, 2
v_lshlrev_b32_e32 v1, 2, v0
s_and_b32 vcc_lo, exec_lo, s4
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_9
s_mov_b32 s4, s3
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_gt_u32 s4, 3
s_mov_b32 s4, s5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_9
.LBB0_7:
s_lshr_b32 s5, s4, 1
s_mov_b32 s6, exec_lo
v_cmpx_gt_u32_e64 s5, v0
s_cbranch_execz .LBB0_6
v_add_lshl_u32 v2, s5, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_6
.LBB0_9:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_cmp_lg_u32 s3, 0
s_mov_b32 s3, 0
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s4, vcc_lo, s4
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19LinearAddIntsKernelPiPKij
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19LinearAddIntsKernelPiPKij, .Lfunc_end0-_Z19LinearAddIntsKernelPiPKij
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z22BlockAddInts_32_KernelPiPKi
.globl _Z22BlockAddInts_32_KernelPiPKi
.p2align 8
.type _Z22BlockAddInts_32_KernelPiPKi,@function
_Z22BlockAddInts_32_KernelPiPKi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s3, 0xffff
s_lshr_b32 s3, s3, 16
v_mad_u64_u32 v[2:3], null, s14, s6, v[1:2]
s_mul_i32 s4, s2, s6
s_mul_i32 s3, s15, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s4, v2
s_load_b64 s[4:5], s[0:1], 0x8
v_add3_u32 v2, s3, v0, v2
v_mad_u32_u24 v0, v1, s6, v0
s_movk_i32 s3, 0x200
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b32_e32 v1, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB1_2
.p2align 6
.LBB1_1:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 31
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s3, s4
s_add_i32 s3, s3, 1
s_ashr_i32 s4, s4, 1
s_cmp_gt_u32 s3, 2
s_mov_b32 s3, s4
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_4
.LBB1_2:
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB1_1
v_add_lshl_u32 v2, s3, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB1_1
.LBB1_4:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_6
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_mul_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s15
ds_load_b32 v1, v0
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22BlockAddInts_32_KernelPiPKi
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z22BlockAddInts_32_KernelPiPKi, .Lfunc_end1-_Z22BlockAddInts_32_KernelPiPKi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z22BlockAddInts_16_KernelPiPKi
.globl _Z22BlockAddInts_16_KernelPiPKi
.p2align 8
.type _Z22BlockAddInts_16_KernelPiPKi,@function
_Z22BlockAddInts_16_KernelPiPKi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s3, 0xffff
s_lshr_b32 s3, s3, 16
v_mad_u64_u32 v[2:3], null, s14, s6, v[1:2]
s_mul_i32 s4, s2, s6
s_mul_i32 s3, s15, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s4, v2
s_load_b64 s[4:5], s[0:1], 0x8
v_add3_u32 v2, s3, v0, v2
v_mad_u32_u24 v0, v1, s6, v0
s_movk_i32 s3, 0x80
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b32_e32 v1, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB2_2
.p2align 6
.LBB2_1:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 31
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s3, s4
s_add_i32 s3, s3, 1
s_ashr_i32 s4, s4, 1
s_cmp_gt_u32 s3, 2
s_mov_b32 s3, s4
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB2_4
.LBB2_2:
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB2_1
v_add_lshl_u32 v2, s3, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB2_1
.LBB2_4:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB2_6
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_mul_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s15
ds_load_b32 v1, v0
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB2_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22BlockAddInts_16_KernelPiPKi
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z22BlockAddInts_16_KernelPiPKi, .Lfunc_end2-_Z22BlockAddInts_16_KernelPiPKi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z21LinearAddFloatsKernelPfPKfj
.globl _Z21LinearAddFloatsKernelPfPKfj
.p2align 8
.type _Z21LinearAddFloatsKernelPfPKfj,@function
_Z21LinearAddFloatsKernelPfPKfj:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b32 s7, s[0:1], 0x10
s_add_u32 s4, s0, 24
s_mov_b32 s2, s15
s_addc_u32 s5, s1, 0
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
v_cmpx_gt_u32_e64 s7, v1
s_cbranch_execz .LBB3_4
s_load_b32 s10, s[4:5], 0x0
s_load_b64 s[4:5], s[0:1], 0x8
v_mov_b32_e32 v3, 0
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s10, s3
.LBB3_2:
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v2, v2, v3 :: v_dual_add_nc_u32 v1, s10, v1
v_cmp_le_u32_e32 vcc_lo, s7, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cvt_i32_f32_e32 v3, v2
s_or_b32 s9, vcc_lo, s9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB3_2
s_or_b32 exec_lo, exec_lo, s9
v_cvt_f32_i32_e32 v2, v3
.LBB3_4:
s_or_b32 exec_lo, exec_lo, s8
v_cmp_lt_u16_e64 s4, s6, 2
v_lshlrev_b32_e32 v1, 2, v0
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 vcc_lo, exec_lo, s4
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB3_9
s_mov_b32 s4, s3
s_branch .LBB3_7
.p2align 6
.LBB3_6:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_gt_u32 s4, 3
s_mov_b32 s4, s5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB3_9
.LBB3_7:
s_lshr_b32 s5, s4, 1
s_mov_b32 s6, exec_lo
v_cmpx_gt_u32_e64 s5, v0
s_cbranch_execz .LBB3_6
v_add_lshl_u32 v2, s5, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB3_6
.LBB3_9:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_cmp_lg_u32 s3, 0
s_mov_b32 s3, 0
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s4, vcc_lo, s4
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB3_11
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB3_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21LinearAddFloatsKernelPfPKfj
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z21LinearAddFloatsKernelPfPKfj, .Lfunc_end3-_Z21LinearAddFloatsKernelPfPKfj
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z24BlockAddFloats_32_KernelPfPKf
.globl _Z24BlockAddFloats_32_KernelPfPKf
.p2align 8
.type _Z24BlockAddFloats_32_KernelPfPKf,@function
_Z24BlockAddFloats_32_KernelPfPKf:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s3, 0xffff
s_lshr_b32 s3, s3, 16
v_mad_u64_u32 v[2:3], null, s14, s6, v[1:2]
s_mul_i32 s4, s2, s6
s_mul_i32 s3, s15, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s4, v2
s_load_b64 s[4:5], s[0:1], 0x8
v_add3_u32 v2, s3, v0, v2
v_mad_u32_u24 v0, v1, s6, v0
s_movk_i32 s3, 0x200
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b32_e32 v1, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB4_2
.p2align 6
.LBB4_1:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 31
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s3, s4
s_add_i32 s3, s3, 1
s_ashr_i32 s4, s4, 1
s_cmp_gt_u32 s3, 2
s_mov_b32 s3, s4
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB4_4
.LBB4_2:
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB4_1
v_add_lshl_u32 v2, s3, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB4_1
.LBB4_4:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB4_6
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_mul_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s15
ds_load_b32 v1, v0
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB4_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24BlockAddFloats_32_KernelPfPKf
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z24BlockAddFloats_32_KernelPfPKf, .Lfunc_end4-_Z24BlockAddFloats_32_KernelPfPKf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z24BlockAddFloats_16_KernelPfPKf
.globl _Z24BlockAddFloats_16_KernelPfPKf
.p2align 8
.type _Z24BlockAddFloats_16_KernelPfPKf,@function
_Z24BlockAddFloats_16_KernelPfPKf:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s3, 0xffff
s_lshr_b32 s3, s3, 16
v_mad_u64_u32 v[2:3], null, s14, s6, v[1:2]
s_mul_i32 s4, s2, s6
s_mul_i32 s3, s15, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s4, v2
s_load_b64 s[4:5], s[0:1], 0x8
v_add3_u32 v2, s3, v0, v2
v_mad_u32_u24 v0, v1, s6, v0
s_movk_i32 s3, 0x80
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b32_e32 v1, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB5_2
.p2align 6
.LBB5_1:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 31
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s3, s4
s_add_i32 s3, s3, 1
s_ashr_i32 s4, s4, 1
s_cmp_gt_u32 s3, 2
s_mov_b32 s3, s4
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB5_4
.LBB5_2:
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB5_1
v_add_lshl_u32 v2, s3, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB5_1
.LBB5_4:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB5_6
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_mul_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s15
ds_load_b32 v1, v0
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB5_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24BlockAddFloats_16_KernelPfPKf
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end5:
.size _Z24BlockAddFloats_16_KernelPfPKf, .Lfunc_end5-_Z24BlockAddFloats_16_KernelPfPKf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19LinearAddIntsKernelPiPKij
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19LinearAddIntsKernelPiPKij.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22BlockAddInts_32_KernelPiPKi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22BlockAddInts_32_KernelPiPKi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22BlockAddInts_16_KernelPiPKi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22BlockAddInts_16_KernelPiPKi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21LinearAddFloatsKernelPfPKfj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21LinearAddFloatsKernelPfPKfj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24BlockAddFloats_32_KernelPfPKf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24BlockAddFloats_32_KernelPfPKf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24BlockAddFloats_16_KernelPfPKf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24BlockAddFloats_16_KernelPfPKf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma once
#include "hip/hip_runtime.h"
__global__ void LinearAddIntsKernel(int *d_out, const int *d_in, unsigned int length)
{
__shared__ int cache[512];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
int cumer = 0;
while (tid < length)
{
cumer += d_in[tid];
tid += blockDim.x * gridDim.x;
}
cache[cacheIndex] = cumer;
__syncthreads();
int i = blockDim.x / 2;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
for (int i = 0; i < blockDim.x; i++)
{
d_out[blockIdx.x] = cache[0];
}
}
}
__global__ void BlockAddInts_32_Kernel(int *d_out, const int *d_in)
{
__shared__ int cache[1024];
int cacheIndex = threadIdx.y + threadIdx.x * blockDim.x;
int span = gridDim.x * blockDim.x;
int rowIn = threadIdx.y + blockIdx.y * blockDim.y;
int colIn = threadIdx.x + blockIdx.x * blockDim.x;
int indexIn = rowIn + colIn * span;
int indexOut = blockIdx.y + blockIdx.x * gridDim.x;
cache[cacheIndex] = d_in[indexIn];
__syncthreads();
int i = 512;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
d_out[indexOut] = cache[0];
}
}
__global__ void BlockAddInts_16_Kernel(int *d_out, const int *d_in)
{
__shared__ int cache[256];
int cacheIndex = threadIdx.y + threadIdx.x * blockDim.x;
int span = gridDim.x * blockDim.x;
int rowIn = threadIdx.y + blockIdx.y * blockDim.y;
int colIn = threadIdx.x + blockIdx.x * blockDim.x;
int indexIn = rowIn + colIn * span;
int indexOut = blockIdx.y + blockIdx.x * gridDim.x;
cache[cacheIndex] = d_in[indexIn];
__syncthreads();
int i = 128;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
d_out[indexOut] = cache[0];
}
}
__global__ void LinearAddFloatsKernel(float *d_out, const float *d_in, unsigned int length)
{
__shared__ float cache[512];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
int cumer = 0;
while (tid < length)
{
cumer += d_in[tid];
tid += blockDim.x * gridDim.x;
}
cache[cacheIndex] = cumer;
__syncthreads();
int i = blockDim.x / 2;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
for (int i = 0; i < blockDim.x; i++)
{
d_out[blockIdx.x] = cache[0];
}
}
}
__global__ void BlockAddFloats_32_Kernel(float *d_out, const float *d_in)
{
__shared__ float cache[1024];
int cacheIndex = threadIdx.y + threadIdx.x * blockDim.x;
int span = gridDim.x * blockDim.x;
int rowIn = threadIdx.y + blockIdx.y * blockDim.y;
int colIn = threadIdx.x + blockIdx.x * blockDim.x;
int indexIn = rowIn + colIn * span;
int indexOut = blockIdx.y + blockIdx.x * gridDim.x;
cache[cacheIndex] = d_in[indexIn];
__syncthreads();
int i = 512;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
d_out[indexOut] = cache[0];
}
}
__global__ void BlockAddFloats_16_Kernel(float *d_out, const float *d_in)
{
__shared__ float cache[256];
int cacheIndex = threadIdx.y + threadIdx.x * blockDim.x;
int span = gridDim.x * blockDim.x;
int rowIn = threadIdx.y + blockIdx.y * blockDim.y;
int colIn = threadIdx.x + blockIdx.x * blockDim.x;
int indexIn = rowIn + colIn * span;
int indexOut = blockIdx.y + blockIdx.x * gridDim.x;
cache[cacheIndex] = d_in[indexIn];
__syncthreads();
int i = 128;
while (i != 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (cacheIndex == 0)
{
d_out[indexOut] = cache[0];
}
} | .text
.file "CuArrayKernels.hip"
.globl _Z34__device_stub__LinearAddIntsKernelPiPKij # -- Begin function _Z34__device_stub__LinearAddIntsKernelPiPKij
.p2align 4, 0x90
.type _Z34__device_stub__LinearAddIntsKernelPiPKij,@function
_Z34__device_stub__LinearAddIntsKernelPiPKij: # @_Z34__device_stub__LinearAddIntsKernelPiPKij
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19LinearAddIntsKernelPiPKij, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z34__device_stub__LinearAddIntsKernelPiPKij, .Lfunc_end0-_Z34__device_stub__LinearAddIntsKernelPiPKij
.cfi_endproc
# -- End function
.globl _Z37__device_stub__BlockAddInts_32_KernelPiPKi # -- Begin function _Z37__device_stub__BlockAddInts_32_KernelPiPKi
.p2align 4, 0x90
.type _Z37__device_stub__BlockAddInts_32_KernelPiPKi,@function
_Z37__device_stub__BlockAddInts_32_KernelPiPKi: # @_Z37__device_stub__BlockAddInts_32_KernelPiPKi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z22BlockAddInts_32_KernelPiPKi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z37__device_stub__BlockAddInts_32_KernelPiPKi, .Lfunc_end1-_Z37__device_stub__BlockAddInts_32_KernelPiPKi
.cfi_endproc
# -- End function
.globl _Z37__device_stub__BlockAddInts_16_KernelPiPKi # -- Begin function _Z37__device_stub__BlockAddInts_16_KernelPiPKi
.p2align 4, 0x90
.type _Z37__device_stub__BlockAddInts_16_KernelPiPKi,@function
_Z37__device_stub__BlockAddInts_16_KernelPiPKi: # @_Z37__device_stub__BlockAddInts_16_KernelPiPKi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z22BlockAddInts_16_KernelPiPKi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z37__device_stub__BlockAddInts_16_KernelPiPKi, .Lfunc_end2-_Z37__device_stub__BlockAddInts_16_KernelPiPKi
.cfi_endproc
# -- End function
.globl _Z36__device_stub__LinearAddFloatsKernelPfPKfj # -- Begin function _Z36__device_stub__LinearAddFloatsKernelPfPKfj
.p2align 4, 0x90
.type _Z36__device_stub__LinearAddFloatsKernelPfPKfj,@function
_Z36__device_stub__LinearAddFloatsKernelPfPKfj: # @_Z36__device_stub__LinearAddFloatsKernelPfPKfj
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21LinearAddFloatsKernelPfPKfj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z36__device_stub__LinearAddFloatsKernelPfPKfj, .Lfunc_end3-_Z36__device_stub__LinearAddFloatsKernelPfPKfj
.cfi_endproc
# -- End function
.globl _Z39__device_stub__BlockAddFloats_32_KernelPfPKf # -- Begin function _Z39__device_stub__BlockAddFloats_32_KernelPfPKf
.p2align 4, 0x90
.type _Z39__device_stub__BlockAddFloats_32_KernelPfPKf,@function
_Z39__device_stub__BlockAddFloats_32_KernelPfPKf: # @_Z39__device_stub__BlockAddFloats_32_KernelPfPKf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z24BlockAddFloats_32_KernelPfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z39__device_stub__BlockAddFloats_32_KernelPfPKf, .Lfunc_end4-_Z39__device_stub__BlockAddFloats_32_KernelPfPKf
.cfi_endproc
# -- End function
.globl _Z39__device_stub__BlockAddFloats_16_KernelPfPKf # -- Begin function _Z39__device_stub__BlockAddFloats_16_KernelPfPKf
.p2align 4, 0x90
.type _Z39__device_stub__BlockAddFloats_16_KernelPfPKf,@function
_Z39__device_stub__BlockAddFloats_16_KernelPfPKf: # @_Z39__device_stub__BlockAddFloats_16_KernelPfPKf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z24BlockAddFloats_16_KernelPfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end5:
.size _Z39__device_stub__BlockAddFloats_16_KernelPfPKf, .Lfunc_end5-_Z39__device_stub__BlockAddFloats_16_KernelPfPKf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19LinearAddIntsKernelPiPKij, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22BlockAddInts_32_KernelPiPKi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22BlockAddInts_16_KernelPiPKi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21LinearAddFloatsKernelPfPKfj, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24BlockAddFloats_32_KernelPfPKf, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24BlockAddFloats_16_KernelPfPKf, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19LinearAddIntsKernelPiPKij,@object # @_Z19LinearAddIntsKernelPiPKij
.section .rodata,"a",@progbits
.globl _Z19LinearAddIntsKernelPiPKij
.p2align 3, 0x0
_Z19LinearAddIntsKernelPiPKij:
.quad _Z34__device_stub__LinearAddIntsKernelPiPKij
.size _Z19LinearAddIntsKernelPiPKij, 8
.type _Z22BlockAddInts_32_KernelPiPKi,@object # @_Z22BlockAddInts_32_KernelPiPKi
.globl _Z22BlockAddInts_32_KernelPiPKi
.p2align 3, 0x0
_Z22BlockAddInts_32_KernelPiPKi:
.quad _Z37__device_stub__BlockAddInts_32_KernelPiPKi
.size _Z22BlockAddInts_32_KernelPiPKi, 8
.type _Z22BlockAddInts_16_KernelPiPKi,@object # @_Z22BlockAddInts_16_KernelPiPKi
.globl _Z22BlockAddInts_16_KernelPiPKi
.p2align 3, 0x0
_Z22BlockAddInts_16_KernelPiPKi:
.quad _Z37__device_stub__BlockAddInts_16_KernelPiPKi
.size _Z22BlockAddInts_16_KernelPiPKi, 8
.type _Z21LinearAddFloatsKernelPfPKfj,@object # @_Z21LinearAddFloatsKernelPfPKfj
.globl _Z21LinearAddFloatsKernelPfPKfj
.p2align 3, 0x0
_Z21LinearAddFloatsKernelPfPKfj:
.quad _Z36__device_stub__LinearAddFloatsKernelPfPKfj
.size _Z21LinearAddFloatsKernelPfPKfj, 8
.type _Z24BlockAddFloats_32_KernelPfPKf,@object # @_Z24BlockAddFloats_32_KernelPfPKf
.globl _Z24BlockAddFloats_32_KernelPfPKf
.p2align 3, 0x0
_Z24BlockAddFloats_32_KernelPfPKf:
.quad _Z39__device_stub__BlockAddFloats_32_KernelPfPKf
.size _Z24BlockAddFloats_32_KernelPfPKf, 8
.type _Z24BlockAddFloats_16_KernelPfPKf,@object # @_Z24BlockAddFloats_16_KernelPfPKf
.globl _Z24BlockAddFloats_16_KernelPfPKf
.p2align 3, 0x0
_Z24BlockAddFloats_16_KernelPfPKf:
.quad _Z39__device_stub__BlockAddFloats_16_KernelPfPKf
.size _Z24BlockAddFloats_16_KernelPfPKf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19LinearAddIntsKernelPiPKij"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z22BlockAddInts_32_KernelPiPKi"
.size .L__unnamed_2, 32
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z22BlockAddInts_16_KernelPiPKi"
.size .L__unnamed_3, 32
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z21LinearAddFloatsKernelPfPKfj"
.size .L__unnamed_4, 32
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z24BlockAddFloats_32_KernelPfPKf"
.size .L__unnamed_5, 34
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z24BlockAddFloats_16_KernelPfPKf"
.size .L__unnamed_6, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__LinearAddIntsKernelPiPKij
.addrsig_sym _Z37__device_stub__BlockAddInts_32_KernelPiPKi
.addrsig_sym _Z37__device_stub__BlockAddInts_16_KernelPiPKi
.addrsig_sym _Z36__device_stub__LinearAddFloatsKernelPfPKfj
.addrsig_sym _Z39__device_stub__BlockAddFloats_32_KernelPfPKf
.addrsig_sym _Z39__device_stub__BlockAddFloats_16_KernelPfPKf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19LinearAddIntsKernelPiPKij
.addrsig_sym _Z22BlockAddInts_32_KernelPiPKi
.addrsig_sym _Z22BlockAddInts_16_KernelPiPKi
.addrsig_sym _Z21LinearAddFloatsKernelPfPKfj
.addrsig_sym _Z24BlockAddFloats_32_KernelPfPKf
.addrsig_sym _Z24BlockAddFloats_16_KernelPfPKf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b8e55_00000000-6_CuArrayKernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z19LinearAddIntsKernelPiPKijPiPKij
.type _Z43__device_stub__Z19LinearAddIntsKernelPiPKijPiPKij, @function
_Z43__device_stub__Z19LinearAddIntsKernelPiPKijPiPKij:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19LinearAddIntsKernelPiPKij(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z19LinearAddIntsKernelPiPKijPiPKij, .-_Z43__device_stub__Z19LinearAddIntsKernelPiPKijPiPKij
.globl _Z19LinearAddIntsKernelPiPKij
.type _Z19LinearAddIntsKernelPiPKij, @function
_Z19LinearAddIntsKernelPiPKij:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19LinearAddIntsKernelPiPKijPiPKij
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19LinearAddIntsKernelPiPKij, .-_Z19LinearAddIntsKernelPiPKij
.globl _Z45__device_stub__Z22BlockAddInts_32_KernelPiPKiPiPKi
.type _Z45__device_stub__Z22BlockAddInts_32_KernelPiPKiPiPKi, @function
_Z45__device_stub__Z22BlockAddInts_32_KernelPiPKiPiPKi:
.LFB2053:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z22BlockAddInts_32_KernelPiPKi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z45__device_stub__Z22BlockAddInts_32_KernelPiPKiPiPKi, .-_Z45__device_stub__Z22BlockAddInts_32_KernelPiPKiPiPKi
.globl _Z22BlockAddInts_32_KernelPiPKi
.type _Z22BlockAddInts_32_KernelPiPKi, @function
_Z22BlockAddInts_32_KernelPiPKi:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z22BlockAddInts_32_KernelPiPKiPiPKi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z22BlockAddInts_32_KernelPiPKi, .-_Z22BlockAddInts_32_KernelPiPKi
.globl _Z45__device_stub__Z22BlockAddInts_16_KernelPiPKiPiPKi
.type _Z45__device_stub__Z22BlockAddInts_16_KernelPiPKiPiPKi, @function
_Z45__device_stub__Z22BlockAddInts_16_KernelPiPKiPiPKi:
.LFB2055:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z22BlockAddInts_16_KernelPiPKi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z45__device_stub__Z22BlockAddInts_16_KernelPiPKiPiPKi, .-_Z45__device_stub__Z22BlockAddInts_16_KernelPiPKiPiPKi
.globl _Z22BlockAddInts_16_KernelPiPKi
.type _Z22BlockAddInts_16_KernelPiPKi, @function
_Z22BlockAddInts_16_KernelPiPKi:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z22BlockAddInts_16_KernelPiPKiPiPKi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z22BlockAddInts_16_KernelPiPKi, .-_Z22BlockAddInts_16_KernelPiPKi
.globl _Z45__device_stub__Z21LinearAddFloatsKernelPfPKfjPfPKfj
.type _Z45__device_stub__Z21LinearAddFloatsKernelPfPKfjPfPKfj, @function
_Z45__device_stub__Z21LinearAddFloatsKernelPfPKfjPfPKfj:
.LFB2057:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21LinearAddFloatsKernelPfPKfj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z45__device_stub__Z21LinearAddFloatsKernelPfPKfjPfPKfj, .-_Z45__device_stub__Z21LinearAddFloatsKernelPfPKfjPfPKfj
.globl _Z21LinearAddFloatsKernelPfPKfj
.type _Z21LinearAddFloatsKernelPfPKfj, @function
_Z21LinearAddFloatsKernelPfPKfj:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z21LinearAddFloatsKernelPfPKfjPfPKfj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z21LinearAddFloatsKernelPfPKfj, .-_Z21LinearAddFloatsKernelPfPKfj
.globl _Z47__device_stub__Z24BlockAddFloats_32_KernelPfPKfPfPKf
.type _Z47__device_stub__Z24BlockAddFloats_32_KernelPfPKfPfPKf, @function
_Z47__device_stub__Z24BlockAddFloats_32_KernelPfPKfPfPKf:
.LFB2059:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z24BlockAddFloats_32_KernelPfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z47__device_stub__Z24BlockAddFloats_32_KernelPfPKfPfPKf, .-_Z47__device_stub__Z24BlockAddFloats_32_KernelPfPKfPfPKf
.globl _Z24BlockAddFloats_32_KernelPfPKf
.type _Z24BlockAddFloats_32_KernelPfPKf, @function
_Z24BlockAddFloats_32_KernelPfPKf:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z24BlockAddFloats_32_KernelPfPKfPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z24BlockAddFloats_32_KernelPfPKf, .-_Z24BlockAddFloats_32_KernelPfPKf
.globl _Z47__device_stub__Z24BlockAddFloats_16_KernelPfPKfPfPKf
.type _Z47__device_stub__Z24BlockAddFloats_16_KernelPfPKfPfPKf, @function
_Z47__device_stub__Z24BlockAddFloats_16_KernelPfPKfPfPKf:
.LFB2061:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z24BlockAddFloats_16_KernelPfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z47__device_stub__Z24BlockAddFloats_16_KernelPfPKfPfPKf, .-_Z47__device_stub__Z24BlockAddFloats_16_KernelPfPKfPfPKf
.globl _Z24BlockAddFloats_16_KernelPfPKf
.type _Z24BlockAddFloats_16_KernelPfPKf, @function
_Z24BlockAddFloats_16_KernelPfPKf:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z24BlockAddFloats_16_KernelPfPKfPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z24BlockAddFloats_16_KernelPfPKf, .-_Z24BlockAddFloats_16_KernelPfPKf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24BlockAddFloats_16_KernelPfPKf"
.align 8
.LC1:
.string "_Z24BlockAddFloats_32_KernelPfPKf"
.align 8
.LC2:
.string "_Z21LinearAddFloatsKernelPfPKfj"
.align 8
.LC3:
.string "_Z22BlockAddInts_16_KernelPiPKi"
.align 8
.LC4:
.string "_Z22BlockAddInts_32_KernelPiPKi"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "_Z19LinearAddIntsKernelPiPKij"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2064:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24BlockAddFloats_16_KernelPfPKf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z24BlockAddFloats_32_KernelPfPKf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z21LinearAddFloatsKernelPfPKfj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z22BlockAddInts_16_KernelPiPKi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z22BlockAddInts_32_KernelPiPKi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z19LinearAddIntsKernelPiPKij(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CuArrayKernels.hip"
.globl _Z34__device_stub__LinearAddIntsKernelPiPKij # -- Begin function _Z34__device_stub__LinearAddIntsKernelPiPKij
.p2align 4, 0x90
.type _Z34__device_stub__LinearAddIntsKernelPiPKij,@function
_Z34__device_stub__LinearAddIntsKernelPiPKij: # @_Z34__device_stub__LinearAddIntsKernelPiPKij
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19LinearAddIntsKernelPiPKij, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z34__device_stub__LinearAddIntsKernelPiPKij, .Lfunc_end0-_Z34__device_stub__LinearAddIntsKernelPiPKij
.cfi_endproc
# -- End function
.globl _Z37__device_stub__BlockAddInts_32_KernelPiPKi # -- Begin function _Z37__device_stub__BlockAddInts_32_KernelPiPKi
.p2align 4, 0x90
.type _Z37__device_stub__BlockAddInts_32_KernelPiPKi,@function
_Z37__device_stub__BlockAddInts_32_KernelPiPKi: # @_Z37__device_stub__BlockAddInts_32_KernelPiPKi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z22BlockAddInts_32_KernelPiPKi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z37__device_stub__BlockAddInts_32_KernelPiPKi, .Lfunc_end1-_Z37__device_stub__BlockAddInts_32_KernelPiPKi
.cfi_endproc
# -- End function
.globl _Z37__device_stub__BlockAddInts_16_KernelPiPKi # -- Begin function _Z37__device_stub__BlockAddInts_16_KernelPiPKi
.p2align 4, 0x90
.type _Z37__device_stub__BlockAddInts_16_KernelPiPKi,@function
_Z37__device_stub__BlockAddInts_16_KernelPiPKi: # @_Z37__device_stub__BlockAddInts_16_KernelPiPKi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z22BlockAddInts_16_KernelPiPKi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z37__device_stub__BlockAddInts_16_KernelPiPKi, .Lfunc_end2-_Z37__device_stub__BlockAddInts_16_KernelPiPKi
.cfi_endproc
# -- End function
.globl _Z36__device_stub__LinearAddFloatsKernelPfPKfj # -- Begin function _Z36__device_stub__LinearAddFloatsKernelPfPKfj
.p2align 4, 0x90
.type _Z36__device_stub__LinearAddFloatsKernelPfPKfj,@function
_Z36__device_stub__LinearAddFloatsKernelPfPKfj: # @_Z36__device_stub__LinearAddFloatsKernelPfPKfj
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21LinearAddFloatsKernelPfPKfj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z36__device_stub__LinearAddFloatsKernelPfPKfj, .Lfunc_end3-_Z36__device_stub__LinearAddFloatsKernelPfPKfj
.cfi_endproc
# -- End function
.globl _Z39__device_stub__BlockAddFloats_32_KernelPfPKf # -- Begin function _Z39__device_stub__BlockAddFloats_32_KernelPfPKf
.p2align 4, 0x90
.type _Z39__device_stub__BlockAddFloats_32_KernelPfPKf,@function
_Z39__device_stub__BlockAddFloats_32_KernelPfPKf: # @_Z39__device_stub__BlockAddFloats_32_KernelPfPKf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z24BlockAddFloats_32_KernelPfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z39__device_stub__BlockAddFloats_32_KernelPfPKf, .Lfunc_end4-_Z39__device_stub__BlockAddFloats_32_KernelPfPKf
.cfi_endproc
# -- End function
.globl _Z39__device_stub__BlockAddFloats_16_KernelPfPKf # -- Begin function _Z39__device_stub__BlockAddFloats_16_KernelPfPKf
.p2align 4, 0x90
.type _Z39__device_stub__BlockAddFloats_16_KernelPfPKf,@function
_Z39__device_stub__BlockAddFloats_16_KernelPfPKf: # @_Z39__device_stub__BlockAddFloats_16_KernelPfPKf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z24BlockAddFloats_16_KernelPfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end5:
.size _Z39__device_stub__BlockAddFloats_16_KernelPfPKf, .Lfunc_end5-_Z39__device_stub__BlockAddFloats_16_KernelPfPKf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19LinearAddIntsKernelPiPKij, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22BlockAddInts_32_KernelPiPKi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22BlockAddInts_16_KernelPiPKi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21LinearAddFloatsKernelPfPKfj, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24BlockAddFloats_32_KernelPfPKf, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24BlockAddFloats_16_KernelPfPKf, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19LinearAddIntsKernelPiPKij,@object # @_Z19LinearAddIntsKernelPiPKij
.section .rodata,"a",@progbits
.globl _Z19LinearAddIntsKernelPiPKij
.p2align 3, 0x0
_Z19LinearAddIntsKernelPiPKij:
.quad _Z34__device_stub__LinearAddIntsKernelPiPKij
.size _Z19LinearAddIntsKernelPiPKij, 8
.type _Z22BlockAddInts_32_KernelPiPKi,@object # @_Z22BlockAddInts_32_KernelPiPKi
.globl _Z22BlockAddInts_32_KernelPiPKi
.p2align 3, 0x0
_Z22BlockAddInts_32_KernelPiPKi:
.quad _Z37__device_stub__BlockAddInts_32_KernelPiPKi
.size _Z22BlockAddInts_32_KernelPiPKi, 8
.type _Z22BlockAddInts_16_KernelPiPKi,@object # @_Z22BlockAddInts_16_KernelPiPKi
.globl _Z22BlockAddInts_16_KernelPiPKi
.p2align 3, 0x0
_Z22BlockAddInts_16_KernelPiPKi:
.quad _Z37__device_stub__BlockAddInts_16_KernelPiPKi
.size _Z22BlockAddInts_16_KernelPiPKi, 8
.type _Z21LinearAddFloatsKernelPfPKfj,@object # @_Z21LinearAddFloatsKernelPfPKfj
.globl _Z21LinearAddFloatsKernelPfPKfj
.p2align 3, 0x0
_Z21LinearAddFloatsKernelPfPKfj:
.quad _Z36__device_stub__LinearAddFloatsKernelPfPKfj
.size _Z21LinearAddFloatsKernelPfPKfj, 8
.type _Z24BlockAddFloats_32_KernelPfPKf,@object # @_Z24BlockAddFloats_32_KernelPfPKf
.globl _Z24BlockAddFloats_32_KernelPfPKf
.p2align 3, 0x0
_Z24BlockAddFloats_32_KernelPfPKf:
.quad _Z39__device_stub__BlockAddFloats_32_KernelPfPKf
.size _Z24BlockAddFloats_32_KernelPfPKf, 8
.type _Z24BlockAddFloats_16_KernelPfPKf,@object # @_Z24BlockAddFloats_16_KernelPfPKf
.globl _Z24BlockAddFloats_16_KernelPfPKf
.p2align 3, 0x0
_Z24BlockAddFloats_16_KernelPfPKf:
.quad _Z39__device_stub__BlockAddFloats_16_KernelPfPKf
.size _Z24BlockAddFloats_16_KernelPfPKf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19LinearAddIntsKernelPiPKij"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z22BlockAddInts_32_KernelPiPKi"
.size .L__unnamed_2, 32
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z22BlockAddInts_16_KernelPiPKi"
.size .L__unnamed_3, 32
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z21LinearAddFloatsKernelPfPKfj"
.size .L__unnamed_4, 32
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z24BlockAddFloats_32_KernelPfPKf"
.size .L__unnamed_5, 34
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z24BlockAddFloats_16_KernelPfPKf"
.size .L__unnamed_6, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__LinearAddIntsKernelPiPKij
.addrsig_sym _Z37__device_stub__BlockAddInts_32_KernelPiPKi
.addrsig_sym _Z37__device_stub__BlockAddInts_16_KernelPiPKi
.addrsig_sym _Z36__device_stub__LinearAddFloatsKernelPfPKfj
.addrsig_sym _Z39__device_stub__BlockAddFloats_32_KernelPfPKf
.addrsig_sym _Z39__device_stub__BlockAddFloats_16_KernelPfPKf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19LinearAddIntsKernelPiPKij
.addrsig_sym _Z22BlockAddInts_32_KernelPiPKi
.addrsig_sym _Z22BlockAddInts_16_KernelPiPKi
.addrsig_sym _Z21LinearAddFloatsKernelPfPKfj
.addrsig_sym _Z24BlockAddFloats_32_KernelPfPKf
.addrsig_sym _Z24BlockAddFloats_16_KernelPfPKf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void perturbByE( float *tmppos, float4 *mypos, float eps, float *E, float *masses, int k, int m, int N ) {
int dof = blockIdx.x * blockDim.x + threadIdx.x;
if( dof >= N ) {
return;
}
int atom = dof / 3;
int axis = dof % 3;
if( axis == 0 ) {
tmppos[dof] = mypos[atom].x;
mypos[atom].x += eps * E[dof * m + k] / sqrt( masses[atom] );
} else if( axis == 1 ) {
tmppos[dof] = mypos[atom].y;
mypos[atom].y += eps * E[dof * m + k] / sqrt( masses[atom] );
} else {
tmppos[dof] = mypos[atom].z;
mypos[atom].z += eps * E[dof * m + k] / sqrt( masses[atom] );
}
} | code for sm_80
Function : _Z10perturbByEPfP6float4fS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x190], PT ; /* 0x0000640004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.HI R0, R4, 0x55555556, RZ ; /* 0x5555555604007827 */
/* 0x000fe200078e02ff */
/*0070*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff057624 */
/* 0x000fe200078e00ff */
/*00a0*/ LEA.HI R3, R0, R0, RZ, 0x1 ; /* 0x0000000000037211 */
/* 0x000fe200078f08ff */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x10 ; /* 0x00000010ff027424 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD R6, R4, R5, c[0x0][0x188] ; /* 0x0000620004067624 */
/* 0x000fe400078e0205 */
/*00d0*/ IMAD R0, R3, -0x3, R4 ; /* 0xfffffffd03007824 */
/* 0x000fc400078e0204 */
/*00e0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc600078e0209 */
/*00f0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0100*/ IMAD.WIDE R6, R6, R9, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0209 */
/*0110*/ IMAD.WIDE R8, R3, R9, c[0x0][0x180] ; /* 0x0000600003087625 */
/* 0x000fc800078e0209 */
/*0120*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc800078e0202 */
/*0130*/ @!P0 BRA 0x640 ; /* 0x0000050000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f05270 */
/*0150*/ @!P0 BRA 0x3d0 ; /* 0x0000027000008947 */
/* 0x000fea0003800000 */
/*0160*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000804020b7981 */
/* 0x000ea8000c1e1900 */
/*0170*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0041e8000c101904 */
/*0180*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*01a0*/ BSSY B0, 0x2a0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*01b0*/ IADD3 R0, R8, -0xd000000, RZ ; /* 0xf300000008007810 */
/* 0x004fe20007ffe0ff */
/*01c0*/ MUFU.RSQ R13, R8 ; /* 0x00000008000d7308 */
/* 0x0000660000001400 */
/*01d0*/ ISETP.GT.U32.AND P0, PT, R0, 0x727fffff, PT ; /* 0x727fffff0000780c */
/* 0x000fe20003f04070 */
/*01e0*/ FMUL R0, R6, c[0x0][0x170] ; /* 0x00005c0006007a20 */
/* 0x008fd80000400000 */
/*01f0*/ @!P0 BRA 0x250 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0200*/ IMAD.MOV.U32 R9, RZ, RZ, R8 ; /* 0x000000ffff097224 */
/* 0x003fe200078e0008 */
/*0210*/ MOV R10, 0x230 ; /* 0x00000230000a7802 */
/* 0x000fe40000000f00 */
/*0220*/ CALL.REL.NOINC 0x8b0 ; /* 0x0000068000007944 */
/* 0x000fea0003c00000 */
/*0230*/ MOV R5, R6 ; /* 0x0000000600057202 */
/* 0x000fe20000000f00 */
/*0240*/ BRA 0x290 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0250*/ FMUL.FTZ R5, R8, R13 ; /* 0x0000000d08057220 */
/* 0x003fe40000410000 */
/*0260*/ FMUL.FTZ R13, R13, 0.5 ; /* 0x3f0000000d0d7820 */
/* 0x000fe40000410000 */
/*0270*/ FFMA R8, -R5, R5, R8 ; /* 0x0000000505087223 */
/* 0x000fc80000000108 */
/*0280*/ FFMA R5, R8, R13, R5 ; /* 0x0000000d08057223 */
/* 0x000fe40000000005 */
/*0290*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02a0*/ MUFU.RCP R4, R5 ; /* 0x0000000500047308 */
/* 0x000e220000001000 */
/*02b0*/ BSSY B0, 0x390 ; /* 0x000000d000007945 */
/* 0x000fee0003800000 */
/*02c0*/ FCHK P0, R0, R5 ; /* 0x0000000500007302 */
/* 0x000e620000000000 */
/*02d0*/ FFMA R7, R4, -R5, 1 ; /* 0x3f80000004077423 */
/* 0x001fc80000000805 */
/*02e0*/ FFMA R7, R4, R7, R4 ; /* 0x0000000704077223 */
/* 0x000fc80000000004 */
/*02f0*/ FFMA R4, R0, R7, RZ ; /* 0x0000000700047223 */
/* 0x000fc800000000ff */
/*0300*/ FFMA R6, R4, -R5, R0 ; /* 0x8000000504067223 */
/* 0x000fc80000000000 */
/*0310*/ FFMA R4, R7, R6, R4 ; /* 0x0000000607047223 */
/* 0x000fe20000000004 */
/*0320*/ @!P0 BRA 0x380 ; /* 0x0000005000008947 */
/* 0x002fea0003800000 */
/*0330*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0340*/ MOV R0, 0x370 ; /* 0x0000037000007802 */
/* 0x000fe20000000f00 */
/*0350*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0005 */
/*0360*/ CALL.REL.NOINC 0xa20 ; /* 0x000006b000007944 */
/* 0x000fea0003c00000 */
/*0370*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fe40000000f00 */
/*0380*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0390*/ LDG.E R5, [R2.64+0x8] ; /* 0x0000080402057981 */
/* 0x000ea4000c1e1900 */
/*03a0*/ FADD R5, R5, R4 ; /* 0x0000000405057221 */
/* 0x004fca0000000000 */
/*03b0*/ STG.E [R2.64+0x8], R5 ; /* 0x0000080502007986 */
/* 0x000fe2000c101904 */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000404020b7981 */
/* 0x000ea8000c1e1900 */
/*03e0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0041e8000c101904 */
/*03f0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*0410*/ BSSY B0, 0x510 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0420*/ IADD3 R0, R8, -0xd000000, RZ ; /* 0xf300000008007810 */
/* 0x004fe20007ffe0ff */
/*0430*/ MUFU.RSQ R13, R8 ; /* 0x00000008000d7308 */
/* 0x0000660000001400 */
/*0440*/ ISETP.GT.U32.AND P0, PT, R0, 0x727fffff, PT ; /* 0x727fffff0000780c */
/* 0x000fe20003f04070 */
/*0450*/ FMUL R0, R6, c[0x0][0x170] ; /* 0x00005c0006007a20 */
/* 0x008fd80000400000 */
/*0460*/ @!P0 BRA 0x4c0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0470*/ IMAD.MOV.U32 R9, RZ, RZ, R8 ; /* 0x000000ffff097224 */
/* 0x003fe200078e0008 */
/*0480*/ MOV R10, 0x4a0 ; /* 0x000004a0000a7802 */
/* 0x000fe40000000f00 */
/*0490*/ CALL.REL.NOINC 0x8b0 ; /* 0x0000041000007944 */
/* 0x000fea0003c00000 */
/*04a0*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0006 */
/*04b0*/ BRA 0x500 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*04c0*/ FMUL.FTZ R5, R8, R13 ; /* 0x0000000d08057220 */
/* 0x003fe40000410000 */
/*04d0*/ FMUL.FTZ R13, R13, 0.5 ; /* 0x3f0000000d0d7820 */
/* 0x000fe40000410000 */
/*04e0*/ FFMA R8, -R5, R5, R8 ; /* 0x0000000505087223 */
/* 0x000fc80000000108 */
/*04f0*/ FFMA R5, R8, R13, R5 ; /* 0x0000000d08057223 */
/* 0x000fe40000000005 */
/*0500*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0510*/ MUFU.RCP R4, R5 ; /* 0x0000000500047308 */
/* 0x000e220000001000 */
/*0520*/ BSSY B0, 0x600 ; /* 0x000000d000007945 */
/* 0x000fee0003800000 */
/*0530*/ FCHK P0, R0, R5 ; /* 0x0000000500007302 */
/* 0x000e620000000000 */
/*0540*/ FFMA R7, R4, -R5, 1 ; /* 0x3f80000004077423 */
/* 0x001fc80000000805 */
/*0550*/ FFMA R7, R4, R7, R4 ; /* 0x0000000704077223 */
/* 0x000fc80000000004 */
/*0560*/ FFMA R4, R0, R7, RZ ; /* 0x0000000700047223 */
/* 0x000fc800000000ff */
/*0570*/ FFMA R6, R4, -R5, R0 ; /* 0x8000000504067223 */
/* 0x000fc80000000000 */
/*0580*/ FFMA R4, R7, R6, R4 ; /* 0x0000000607047223 */
/* 0x000fe20000000004 */
/*0590*/ @!P0 BRA 0x5f0 ; /* 0x0000005000008947 */
/* 0x002fea0003800000 */
/*05a0*/ MOV R7, R0 ; /* 0x0000000000077202 */
/* 0x000fe20000000f00 */
/*05b0*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0005 */
/*05c0*/ MOV R0, 0x5e0 ; /* 0x000005e000007802 */
/* 0x000fe40000000f00 */
/*05d0*/ CALL.REL.NOINC 0xa20 ; /* 0x0000044000007944 */
/* 0x000fea0003c00000 */
/*05e0*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0006 */
/*05f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0600*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea4000c1e1900 */
/*0610*/ FADD R5, R5, R4 ; /* 0x0000000405057221 */
/* 0x004fca0000000000 */
/*0620*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe2000c101904 */
/*0630*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0640*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea8000c1e1900 */
/*0650*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0041e8000c101904 */
/*0660*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*0670*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*0680*/ BSSY B0, 0x780 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0690*/ IADD3 R0, R8, -0xd000000, RZ ; /* 0xf300000008007810 */
/* 0x004fe20007ffe0ff */
/*06a0*/ MUFU.RSQ R13, R8 ; /* 0x00000008000d7308 */
/* 0x0000660000001400 */
/*06b0*/ ISETP.GT.U32.AND P0, PT, R0, 0x727fffff, PT ; /* 0x727fffff0000780c */
/* 0x000fe20003f04070 */
/*06c0*/ FMUL R0, R6, c[0x0][0x170] ; /* 0x00005c0006007a20 */
/* 0x008fd80000400000 */
/*06d0*/ @!P0 BRA 0x730 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*06e0*/ MOV R9, R8 ; /* 0x0000000800097202 */
/* 0x003fe40000000f00 */
/*06f0*/ MOV R10, 0x710 ; /* 0x00000710000a7802 */
/* 0x000fe40000000f00 */
/*0700*/ CALL.REL.NOINC 0x8b0 ; /* 0x000001a000007944 */
/* 0x000fea0003c00000 */
/*0710*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0006 */
/*0720*/ BRA 0x770 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0730*/ FMUL.FTZ R5, R8, R13 ; /* 0x0000000d08057220 */
/* 0x003fe40000410000 */
/*0740*/ FMUL.FTZ R13, R13, 0.5 ; /* 0x3f0000000d0d7820 */
/* 0x000fe40000410000 */
/*0750*/ FFMA R8, -R5, R5, R8 ; /* 0x0000000505087223 */
/* 0x000fc80000000108 */
/*0760*/ FFMA R5, R8, R13, R5 ; /* 0x0000000d08057223 */
/* 0x000fe40000000005 */
/*0770*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0780*/ MUFU.RCP R4, R5 ; /* 0x0000000500047308 */
/* 0x000e220000001000 */
/*0790*/ BSSY B0, 0x870 ; /* 0x000000d000007945 */
/* 0x000fee0003800000 */
/*07a0*/ FCHK P0, R0, R5 ; /* 0x0000000500007302 */
/* 0x000e620000000000 */
/*07b0*/ FFMA R7, R4, -R5, 1 ; /* 0x3f80000004077423 */
/* 0x001fc80000000805 */
/*07c0*/ FFMA R7, R4, R7, R4 ; /* 0x0000000704077223 */
/* 0x000fc80000000004 */
/*07d0*/ FFMA R4, R0, R7, RZ ; /* 0x0000000700047223 */
/* 0x000fc800000000ff */
/*07e0*/ FFMA R6, R4, -R5, R0 ; /* 0x8000000504067223 */
/* 0x000fc80000000000 */
/*07f0*/ FFMA R4, R7, R6, R4 ; /* 0x0000000607047223 */
/* 0x000fe20000000004 */
/*0800*/ @!P0 BRA 0x860 ; /* 0x0000005000008947 */
/* 0x002fea0003800000 */
/*0810*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0820*/ MOV R8, R5 ; /* 0x0000000500087202 */
/* 0x000fe40000000f00 */
/*0830*/ MOV R0, 0x850 ; /* 0x0000085000007802 */
/* 0x000fe40000000f00 */
/*0840*/ CALL.REL.NOINC 0xa20 ; /* 0x000001d000007944 */
/* 0x000fea0003c00000 */
/*0850*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0006 */
/*0860*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0870*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea4000c1e1900 */
/*0880*/ FADD R5, R5, R4 ; /* 0x0000000405057221 */
/* 0x004fca0000000000 */
/*0890*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*08a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08b0*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c0ff */
/*08c0*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff048224 */
/* 0x000fe200078e0009 */
/*08d0*/ @!P0 BRA 0x9e0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*08e0*/ FSETP.GEU.FTZ.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720b */
/* 0x000fda0003f1e000 */
/*08f0*/ @!P0 MOV R4, 0x7fffffff ; /* 0x7fffffff00048802 */
/* 0x000fe20000000f00 */
/*0900*/ @!P0 BRA 0x9e0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0910*/ FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fda0003f1c200 */
/*0920*/ @P0 FADD.FTZ R4, R9, 1 ; /* 0x3f80000009040421 */
/* 0x000fe20000010000 */
/*0930*/ @P0 BRA 0x9e0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0940*/ FSETP.NEU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fda0003f1d200 */
/*0950*/ @P0 FFMA R5, R9, 1.84467440737095516160e+19, RZ ; /* 0x5f80000009050823 */
/* 0x000fc800000000ff */
/*0960*/ @P0 MUFU.RSQ R4, R5 ; /* 0x0000000500040308 */
/* 0x000e240000001400 */
/*0970*/ @P0 FMUL.FTZ R6, R5, R4 ; /* 0x0000000405060220 */
/* 0x001fe40000410000 */
/*0980*/ @P0 FMUL.FTZ R8, R4, 0.5 ; /* 0x3f00000004080820 */
/* 0x000fe40000410000 */
/*0990*/ @P0 FADD.FTZ R7, -R6.reuse, -RZ ; /* 0x800000ff06070221 */
/* 0x040fe40000010100 */
/*09a0*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff048224 */
/* 0x000fe400078e0009 */
/*09b0*/ @P0 FFMA R7, R6, R7, R5 ; /* 0x0000000706070223 */
/* 0x000fc80000000005 */
/*09c0*/ @P0 FFMA R7, R7, R8, R6 ; /* 0x0000000807070223 */
/* 0x000fc80000000006 */
/*09d0*/ @P0 FMUL.FTZ R4, R7, 2.3283064365386962891e-10 ; /* 0x2f80000007040820 */
/* 0x000fc80000410000 */
/*09e0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*09f0*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x000fe20000000f00 */
/*0a00*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fc800078e000a */
/*0a10*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff5e004007950 */
/* 0x000fea0003c3ffff */
/*0a20*/ SHF.R.U32.HI R5, RZ, 0x17, R8 ; /* 0x00000017ff057819 */
/* 0x000fe20000011608 */
/*0a30*/ BSSY B1, 0x1080 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0a40*/ SHF.R.U32.HI R4, RZ, 0x17, R7.reuse ; /* 0x00000017ff047819 */
/* 0x100fe40000011607 */
/*0a50*/ LOP3.LUT R12, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff050c7812 */
/* 0x000fe400078ec0ff */
/*0a60*/ LOP3.LUT R10, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff040a7812 */
/* 0x000fe200078ec0ff */
/*0a70*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0007 */
/*0a80*/ IADD3 R11, R12, -0x1, RZ ; /* 0xffffffff0c0b7810 */
/* 0x000fe40007ffe0ff */
/*0a90*/ IADD3 R9, R10, -0x1, RZ ; /* 0xffffffff0a097810 */
/* 0x000fc40007ffe0ff */
/*0aa0*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fe40003f04070 */
/*0ab0*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x000fe40000000f00 */
/*0ac0*/ ISETP.GT.U32.OR P0, PT, R9, 0xfd, P0 ; /* 0x000000fd0900780c */
/* 0x000fda0000704470 */
/*0ad0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff068224 */
/* 0x000fe200078e00ff */
/*0ae0*/ @!P0 BRA 0xc60 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0af0*/ FSETP.GTU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f1c200 */
/*0b00*/ FSETP.GTU.FTZ.AND P1, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fc80003f3c200 */
/*0b10*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0b20*/ @P0 BRA 0x1060 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0b30*/ LOP3.LUT P0, RZ, R5, 0x7fffffff, R4, 0xc8, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fda000780c804 */
/*0b40*/ @!P0 BRA 0x1040 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0b50*/ FSETP.NEU.FTZ.AND P2, PT, |R7|.reuse, +INF , PT ; /* 0x7f8000000700780b */
/* 0x040fe40003f5d200 */
/*0b60*/ FSETP.NEU.FTZ.AND P1, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f3d200 */
/*0b70*/ FSETP.NEU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fd60003f1d200 */
/*0b80*/ @!P1 BRA !P2, 0x1040 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0b90*/ LOP3.LUT P2, RZ, R4, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff04ff7812 */
/* 0x000fc8000784c0ff */
/*0ba0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0bb0*/ @P1 BRA 0x1020 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0bc0*/ LOP3.LUT P1, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000782c0ff */
/*0bd0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0be0*/ @P0 BRA 0xff0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0bf0*/ ISETP.GE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f06270 */
/*0c00*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0c10*/ @P0 MOV R6, RZ ; /* 0x000000ff00060202 */
/* 0x000fe20000000f00 */
/*0c20*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, -0x40 ; /* 0xffffffc0ff068424 */
/* 0x000fe400078e00ff */
/*0c30*/ @!P0 FFMA R4, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007048823 */
/* 0x000fe400000000ff */
/*0c40*/ @!P1 FFMA R5, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f80000008059823 */
/* 0x000fe200000000ff */
/*0c50*/ @!P1 IADD3 R6, R6, 0x40, RZ ; /* 0x0000004006069810 */
/* 0x000fe40007ffe0ff */
/*0c60*/ LEA R8, R12, 0xc0800000, 0x17 ; /* 0xc08000000c087811 */
/* 0x000fe200078eb8ff */
/*0c70*/ BSSY B2, 0xfe0 ; /* 0x0000036000027945 */
/* 0x000fe60003800000 */
/*0c80*/ IADD3 R8, -R8, R5, RZ ; /* 0x0000000508087210 */
/* 0x000fc40007ffe1ff */
/*0c90*/ IADD3 R5, R10, -0x7f, RZ ; /* 0xffffff810a057810 */
/* 0x000fe40007ffe0ff */
/*0ca0*/ MUFU.RCP R7, R8 ; /* 0x0000000800077308 */
/* 0x000e220000001000 */
/*0cb0*/ FADD.FTZ R9, -R8, -RZ ; /* 0x800000ff08097221 */
/* 0x000fe40000010100 */
/*0cc0*/ IMAD R4, R5, -0x800000, R4 ; /* 0xff80000005047824 */
/* 0x000fe400078e0204 */
/*0cd0*/ FFMA R10, R7, R9, 1 ; /* 0x3f800000070a7423 */
/* 0x001fc80000000009 */
/*0ce0*/ FFMA R11, R7, R10, R7 ; /* 0x0000000a070b7223 */
/* 0x000fc80000000007 */
/*0cf0*/ FFMA R7, R4, R11, RZ ; /* 0x0000000b04077223 */
/* 0x000fc800000000ff */
/*0d00*/ FFMA R10, R9, R7, R4 ; /* 0x00000007090a7223 */
/* 0x000fc80000000004 */
/*0d10*/ FFMA R10, R11, R10, R7 ; /* 0x0000000a0b0a7223 */
/* 0x000fe20000000007 */
/*0d20*/ IADD3 R7, R5, 0x7f, -R12 ; /* 0x0000007f05077810 */
/* 0x000fc60007ffe80c */
/*0d30*/ FFMA R9, R9, R10, R4 ; /* 0x0000000a09097223 */
/* 0x000fe40000000004 */
/*0d40*/ IMAD.IADD R7, R7, 0x1, R6 ; /* 0x0000000107077824 */
/* 0x000fe400078e0206 */
/*0d50*/ FFMA R4, R11, R9, R10 ; /* 0x000000090b047223 */
/* 0x000fca000000000a */
/*0d60*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*0d70*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fc800078ec0ff */
/*0d80*/ IADD3 R12, R5, R7, RZ ; /* 0x00000007050c7210 */
/* 0x000fc80007ffe0ff */
/*0d90*/ IADD3 R5, R12, -0x1, RZ ; /* 0xffffffff0c057810 */
/* 0x000fc80007ffe0ff */
/*0da0*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0db0*/ @!P0 BRA 0xfc0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0dc0*/ ISETP.GT.AND P0, PT, R12, 0xfe, PT ; /* 0x000000fe0c00780c */
/* 0x000fda0003f04270 */
/*0dd0*/ @P0 BRA 0xf90 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0de0*/ ISETP.GE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fda0003f06270 */
/*0df0*/ @P0 BRA 0xfd0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0e00*/ ISETP.GE.AND P0, PT, R12, -0x18, PT ; /* 0xffffffe80c00780c */
/* 0x000fe40003f06270 */
/*0e10*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*0e20*/ @!P0 BRA 0xfd0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0e30*/ FFMA.RZ R5, R11.reuse, R9.reuse, R10.reuse ; /* 0x000000090b057223 */
/* 0x1c0fe2000000c00a */
/*0e40*/ IADD3 R8, R12.reuse, 0x20, RZ ; /* 0x000000200c087810 */
/* 0x040fe20007ffe0ff */
/*0e50*/ FFMA.RM R6, R11, R9.reuse, R10.reuse ; /* 0x000000090b067223 */
/* 0x180fe2000000400a */
/*0e60*/ ISETP.NE.AND P2, PT, R12.reuse, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x040fe40003f45270 */
/*0e70*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0e80*/ FFMA.RP R5, R11, R9, R10 ; /* 0x000000090b057223 */
/* 0x000fe2000000800a */
/*0e90*/ ISETP.NE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f25270 */
/*0ea0*/ IMAD.MOV R9, RZ, RZ, -R12 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a0c */
/*0eb0*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0ec0*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0ed0*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0ee0*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0ef0*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0f00*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0f10*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0f20*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0f30*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0f40*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0f50*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fc800078ec0ff */
/*0f60*/ IADD3 R5, R8, R5, RZ ; /* 0x0000000508057210 */
/* 0x000fc80007ffe0ff */
/*0f70*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*0f80*/ BRA 0xfd0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0f90*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*0fa0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0fb0*/ BRA 0xfd0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0fc0*/ IMAD R4, R7, 0x800000, R4 ; /* 0x0080000007047824 */
/* 0x000fe400078e0204 */
/*0fd0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0fe0*/ BRA 0x1070 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0ff0*/ LOP3.LUT R4, R5, 0x80000000, R4, 0x48, !PT ; /* 0x8000000005047812 */
/* 0x000fc800078e4804 */
/*1000*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*1010*/ BRA 0x1070 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1020*/ LOP3.LUT R4, R5, 0x80000000, R4, 0x48, !PT ; /* 0x8000000005047812 */
/* 0x000fe200078e4804 */
/*1030*/ BRA 0x1070 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1040*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*1050*/ BRA 0x1070 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1060*/ FADD.FTZ R4, R7, R8 ; /* 0x0000000807047221 */
/* 0x000fe40000010000 */
/*1070*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*1080*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*1090*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x001fe20000000f00 */
/*10a0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0000 */
/*10b0*/ RET.REL.NODEC R4 0x0 ; /* 0xffffef4004007950 */
/* 0x000fea0003c3ffff */
/*10c0*/ BRA 0x10c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void perturbByE( float *tmppos, float4 *mypos, float eps, float *E, float *masses, int k, int m, int N ) {
int dof = blockIdx.x * blockDim.x + threadIdx.x;
if( dof >= N ) {
return;
}
int atom = dof / 3;
int axis = dof % 3;
if( axis == 0 ) {
tmppos[dof] = mypos[atom].x;
mypos[atom].x += eps * E[dof * m + k] / sqrt( masses[atom] );
} else if( axis == 1 ) {
tmppos[dof] = mypos[atom].y;
mypos[atom].y += eps * E[dof * m + k] / sqrt( masses[atom] );
} else {
tmppos[dof] = mypos[atom].z;
mypos[atom].z += eps * E[dof * m + k] / sqrt( masses[atom] );
}
} | .file "tmpxft_0007168d_00000000-6_perturbByE.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z10perturbByEPfP6float4fS_S_iiiPfP6float4fS_S_iii
.type _Z46__device_stub__Z10perturbByEPfP6float4fS_S_iiiPfP6float4fS_S_iii, @function
_Z46__device_stub__Z10perturbByEPfP6float4fS_S_iiiPfP6float4fS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movss %xmm0, 28(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movl %r8d, 24(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
leaq 208(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10perturbByEPfP6float4fS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z10perturbByEPfP6float4fS_S_iiiPfP6float4fS_S_iii, .-_Z46__device_stub__Z10perturbByEPfP6float4fS_S_iiiPfP6float4fS_S_iii
.globl _Z10perturbByEPfP6float4fS_S_iii
.type _Z10perturbByEPfP6float4fS_S_iii, @function
_Z10perturbByEPfP6float4fS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z46__device_stub__Z10perturbByEPfP6float4fS_S_iiiPfP6float4fS_S_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10perturbByEPfP6float4fS_S_iii, .-_Z10perturbByEPfP6float4fS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z10perturbByEPfP6float4fS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10perturbByEPfP6float4fS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void perturbByE( float *tmppos, float4 *mypos, float eps, float *E, float *masses, int k, int m, int N ) {
int dof = blockIdx.x * blockDim.x + threadIdx.x;
if( dof >= N ) {
return;
}
int atom = dof / 3;
int axis = dof % 3;
if( axis == 0 ) {
tmppos[dof] = mypos[atom].x;
mypos[atom].x += eps * E[dof * m + k] / sqrt( masses[atom] );
} else if( axis == 1 ) {
tmppos[dof] = mypos[atom].y;
mypos[atom].y += eps * E[dof * m + k] / sqrt( masses[atom] );
} else {
tmppos[dof] = mypos[atom].z;
mypos[atom].z += eps * E[dof * m + k] / sqrt( masses[atom] );
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void perturbByE( float *tmppos, float4 *mypos, float eps, float *E, float *masses, int k, int m, int N ) {
int dof = blockIdx.x * blockDim.x + threadIdx.x;
if( dof >= N ) {
return;
}
int atom = dof / 3;
int axis = dof % 3;
if( axis == 0 ) {
tmppos[dof] = mypos[atom].x;
mypos[atom].x += eps * E[dof * m + k] / sqrt( masses[atom] );
} else if( axis == 1 ) {
tmppos[dof] = mypos[atom].y;
mypos[atom].y += eps * E[dof * m + k] / sqrt( masses[atom] );
} else {
tmppos[dof] = mypos[atom].z;
mypos[atom].z += eps * E[dof * m + k] / sqrt( masses[atom] );
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void perturbByE( float *tmppos, float4 *mypos, float eps, float *E, float *masses, int k, int m, int N ) {
int dof = blockIdx.x * blockDim.x + threadIdx.x;
if( dof >= N ) {
return;
}
int atom = dof / 3;
int axis = dof % 3;
if( axis == 0 ) {
tmppos[dof] = mypos[atom].x;
mypos[atom].x += eps * E[dof * m + k] / sqrt( masses[atom] );
} else if( axis == 1 ) {
tmppos[dof] = mypos[atom].y;
mypos[atom].y += eps * E[dof * m + k] / sqrt( masses[atom] );
} else {
tmppos[dof] = mypos[atom].z;
mypos[atom].z += eps * E[dof * m + k] / sqrt( masses[atom] );
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii
.globl _Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii
.p2align 8
.type _Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii,@function
_Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s3, s[0:1], 0x30
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v2
s_cbranch_execz .LBB0_11
v_mul_hi_i32 v0, v2, 0x55555556
s_clause 0x3
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b32 s12, s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x28
s_mov_b32 s1, 0
s_mov_b32 s0, 0
v_lshrrev_b32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v0, v1
v_ashrrev_i32_e32 v5, 31, v4
v_lshl_add_u32 v3, v4, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 4, v[4:5]
v_sub_nc_u32_e32 v3, v2, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
s_mov_b32 s10, exec_lo
v_cmpx_lt_i32_e32 0, v3
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB0_5
s_mov_b32 s0, -1
s_mov_b32 s11, exec_lo
v_cmpx_eq_u32_e32 1, v3
s_cbranch_execz .LBB0_4
global_load_b32 v10, v[0:1], off offset:4
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[8:9], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_add_co_u32 v6, vcc_lo, s8, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v10, off
global_load_b32 v3, v[8:9], off
v_mad_u64_u32 v[6:7], null, v2, s3, s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v6, v[6:7], off
global_load_b32 v7, v[0:1], off offset:4
s_waitcnt vmcnt(2)
v_mul_f32_e32 v8, 0x4f800000, v3
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v8, vcc_lo
v_sqrt_f32_e32 v8, v3
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v9, -1, v8
v_add_nc_u32_e32 v10, 1, v8
s_waitcnt vmcnt(1)
v_mul_f32_e32 v6, s12, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v11, -v9, v8, v3
v_fma_f32 v12, -v10, v8, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v11
v_cndmask_b32_e64 v8, v8, v9, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v12
v_cndmask_b32_e64 v8, v8, v10, s0
s_xor_b32 s0, exec_lo, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, 0x37800000, v8
v_cndmask_b32_e32 v8, v8, v9, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v3, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v8, v3, vcc_lo
v_div_scale_f32 v8, null, v3, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v9, v8
s_waitcnt_depctr 0xfff
v_fma_f32 v10, -v8, v9, 1.0
v_fmac_f32_e32 v9, v10, v9
v_div_scale_f32 v10, vcc_lo, v6, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, v10, v9
v_fma_f32 v12, -v8, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, v12, v9
v_fma_f32 v8, -v8, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v8, v8, v9, v11
v_div_fixup_f32 v3, v8, v3, v6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v3, v7, v3
global_store_b32 v[0:1], v3, off offset:4
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
.LBB0_5:
s_and_not1_saveexec_b32 s10, s10
v_cmp_ne_u32_e32 vcc_lo, 0, v3
s_and_not1_b32 s0, s0, exec_lo
s_mov_b32 s1, exec_lo
s_and_b32 s11, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s0, s0, s11
s_or_b32 exec_lo, exec_lo, s10
v_ashrrev_i32_e32 v3, 31, v2
s_and_saveexec_b32 s10, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB0_9
global_load_b32 v10, v[0:1], off offset:8
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_lshlrev_b64 v[8:9], 2, v[4:5]
s_and_not1_b32 s1, s1, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v10, off
v_mad_u64_u32 v[6:7], null, v2, s3, s[2:3]
global_load_b32 v8, v[8:9], off
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v6, v[6:7], off
global_load_b32 v7, v[0:1], off offset:8
s_waitcnt vmcnt(2)
v_mul_f32_e32 v9, 0x4f800000, v8
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v8
s_waitcnt vmcnt(1)
v_mul_f32_e32 v6, s12, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v8, v8, v9, vcc_lo
v_sqrt_f32_e32 v9, v8
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v10, -1, v9
v_add_nc_u32_e32 v11, 1, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v12, -v10, v9, v8
v_fma_f32 v13, -v11, v9, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v12
v_cndmask_b32_e64 v9, v9, v10, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v13
v_cndmask_b32_e64 v9, v9, v11, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, 0x37800000, v9
v_cndmask_b32_e32 v9, v9, v10, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v8, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v8, v9, v8, vcc_lo
v_div_scale_f32 v9, null, v8, v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v10, v9
s_waitcnt_depctr 0xfff
v_fma_f32 v11, -v9, v10, 1.0
v_fmac_f32_e32 v10, v11, v10
v_div_scale_f32 v11, vcc_lo, v6, v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v12, v11, v10
v_fma_f32 v13, -v9, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v12, v13, v10
v_fma_f32 v9, -v9, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v9, v9, v10, v12
v_div_fixup_f32 v6, v9, v8, v6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v6, v7, v6
global_store_b32 v[0:1], v6, off offset:8
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_11
global_load_b32 v8, v[0:1], off
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_lshlrev_b64 v[3:4], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v8, off
global_load_b32 v5, v[3:4], off
v_mad_u64_u32 v[3:4], null, v2, s3, s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(2)
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v5
v_mul_f32_e32 v4, 0x4f800000, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v5, v4, vcc_lo
v_sqrt_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v7, 1, v5
v_add_nc_u32_e32 v6, -1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v9, -v7, v5, v4
v_fma_f32 v8, -v6, v5, v4
s_waitcnt vmcnt(1)
v_mul_f32_e32 v2, s12, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v8
v_cndmask_b32_e64 v5, v5, v6, s0
v_cmp_lt_f32_e64 s0, 0, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v5, v5, v7, s0
v_mul_f32_e32 v6, 0x37800000, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v4, 0x260
v_cndmask_b32_e32 v4, v5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v5, null, v4, v4, v2
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v6
v_div_scale_f32 v7, vcc_lo, v2, v4, v2
v_mul_f32_e32 v8, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v5, v8, v7
v_fmac_f32_e32 v8, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v5, v8, v7
v_div_fmas_f32 v5, v5, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v5, v4, v2
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii, .Lfunc_end0-_Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void perturbByE( float *tmppos, float4 *mypos, float eps, float *E, float *masses, int k, int m, int N ) {
int dof = blockIdx.x * blockDim.x + threadIdx.x;
if( dof >= N ) {
return;
}
int atom = dof / 3;
int axis = dof % 3;
if( axis == 0 ) {
tmppos[dof] = mypos[atom].x;
mypos[atom].x += eps * E[dof * m + k] / sqrt( masses[atom] );
} else if( axis == 1 ) {
tmppos[dof] = mypos[atom].y;
mypos[atom].y += eps * E[dof * m + k] / sqrt( masses[atom] );
} else {
tmppos[dof] = mypos[atom].z;
mypos[atom].z += eps * E[dof * m + k] / sqrt( masses[atom] );
}
} | .text
.file "perturbByE.hip"
.globl _Z25__device_stub__perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii # -- Begin function _Z25__device_stub__perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii
.p2align 4, 0x90
.type _Z25__device_stub__perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii,@function
_Z25__device_stub__perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii: # @_Z25__device_stub__perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movss %xmm0, 12(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z25__device_stub__perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii, .Lfunc_end0-_Z25__device_stub__perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii,@object # @_Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii
.section .rodata,"a",@progbits
.globl _Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii
.p2align 3, 0x0
_Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii:
.quad _Z25__device_stub__perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii
.size _Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii"
.size .L__unnamed_1, 50
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007168d_00000000-6_perturbByE.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z10perturbByEPfP6float4fS_S_iiiPfP6float4fS_S_iii
.type _Z46__device_stub__Z10perturbByEPfP6float4fS_S_iiiPfP6float4fS_S_iii, @function
_Z46__device_stub__Z10perturbByEPfP6float4fS_S_iiiPfP6float4fS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movss %xmm0, 28(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movl %r8d, 24(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
leaq 208(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10perturbByEPfP6float4fS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z10perturbByEPfP6float4fS_S_iiiPfP6float4fS_S_iii, .-_Z46__device_stub__Z10perturbByEPfP6float4fS_S_iiiPfP6float4fS_S_iii
.globl _Z10perturbByEPfP6float4fS_S_iii
.type _Z10perturbByEPfP6float4fS_S_iii, @function
_Z10perturbByEPfP6float4fS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z46__device_stub__Z10perturbByEPfP6float4fS_S_iiiPfP6float4fS_S_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10perturbByEPfP6float4fS_S_iii, .-_Z10perturbByEPfP6float4fS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z10perturbByEPfP6float4fS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10perturbByEPfP6float4fS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "perturbByE.hip"
.globl _Z25__device_stub__perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii # -- Begin function _Z25__device_stub__perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii
.p2align 4, 0x90
.type _Z25__device_stub__perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii,@function
_Z25__device_stub__perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii: # @_Z25__device_stub__perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movss %xmm0, 12(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z25__device_stub__perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii, .Lfunc_end0-_Z25__device_stub__perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii,@object # @_Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii
.section .rodata,"a",@progbits
.globl _Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii
.p2align 3, 0x0
_Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii:
.quad _Z25__device_stub__perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii
.size _Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii"
.size .L__unnamed_1, 50
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10perturbByEPfP15HIP_vector_typeIfLj4EEfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/functional.h>
__global__ void calc_pi(double *dev, double step) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
double x = (i + 0.5) * step;
dev[i] = 4.0 /(1.0 + x * x);
}
int main() {
static long num_steps = 1000000000;
static int gpu_threads = 1024;
double step;
double pi, sum = 0.0;
step = 1.0 / (double) num_steps;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, NULL);
thrust::device_vector<double> dev(num_steps);
calc_pi<<<ceil((double) num_steps/gpu_threads), gpu_threads>>>(thrust::raw_pointer_cast(dev.data()), step);
sum = thrust::reduce(dev.begin(), dev.end(), (double) 0, thrust::plus<double>());
pi = step * sum;
cudaEventRecord(stop, NULL);
cudaEventSynchronize(stop);
float msecTotal = 0.0f;
cudaEventElapsedTime(&msecTotal, start, stop);
printf("O valor de pi calculado com %ld passos levou \n", num_steps);
printf("%.2f milisegundo(s) e chegou no valor: \n", msecTotal);
printf("%.17f\n", pi);
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/functional.h>
__global__ void calc_pi(double *dev, double step) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
double x = (i + 0.5) * step;
dev[i] = 4.0 /(1.0 + x * x);
}
int main() {
static long num_steps = 1000000000;
static int gpu_threads = 1024;
double step;
double pi, sum = 0.0;
step = 1.0 / (double) num_steps;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, NULL);
thrust::device_vector<double> dev(num_steps);
calc_pi<<<ceil((double) num_steps/gpu_threads), gpu_threads>>>(thrust::raw_pointer_cast(dev.data()), step);
sum = thrust::reduce(dev.begin(), dev.end(), (double) 0, thrust::plus<double>());
pi = step * sum;
hipEventRecord(stop, NULL);
hipEventSynchronize(stop);
float msecTotal = 0.0f;
hipEventElapsedTime(&msecTotal, start, stop);
printf("O valor de pi calculado com %ld passos levou \n", num_steps);
printf("%.2f milisegundo(s) e chegou no valor: \n", msecTotal);
printf("%.17f\n", pi);
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "stdio.h"
#include "cuda_runtime.h"
#include <cuda_runtime_api.h>
#include "device_launch_parameters.h"
#define THREADS 1024
#define gpu_error_check(ans) { gpu_assert((ans), __FILE__, __LINE__); }
inline void gpu_assert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void swap(int* array, int first, int second)
{
int tmp = array[first];
array[first] = array[second];
array[second] = tmp;
}
__device__
void swap_gpu(int* array, int first, int second)
{
int tmp = array[first];
array[first] = array[second];
array[second] = tmp;
}
__global__
void bitonic_exchange_gpu(int* dev_values, int depth, unsigned long step)
{
/* Sorting partners: i and pair_for_i */
unsigned int i, pair_for_i;
/* Orient tells in which part of bitonic (sub-)sequence elements are (descending or ascending) */
unsigned int orient_i, orient_pair_for_i;
i = threadIdx.x + blockDim.x * blockIdx.x;
pair_for_i = i + depth;
orient_pair_for_i = pair_for_i & step;
orient_i = i & step;
/*
If current array[i] is the second for other array[j] (i<j) so we just do nothing
It can be seen if for some a[i], a[pair_for_i] located in other bitonic (sub-)sequence
For example, a[i] in ascending part, a[pair_for_i] in descending
*/
if (orient_i != 0 && orient_pair_for_i == 0
|| orient_i == 0 && orient_pair_for_i != 0)
{
return;
}
if (orient_i == 0)
{
/* Sort ascending */
if (dev_values[i]>dev_values[pair_for_i])
{
swap_gpu(dev_values, i, pair_for_i);
}
}
else
{
/* Sort descending */
if (dev_values[i]<dev_values[pair_for_i])
{
swap_gpu(dev_values, i, pair_for_i);
}
}
}
void bitonic_sort_gpu(int* array, unsigned long size)
{
size_t size_mem_array = size * sizeof(int);
int* array_gpu;
gpu_error_check(cudaMalloc(&array_gpu, size_mem_array));
gpu_error_check(cudaMemcpy(array_gpu, array, size_mem_array, cudaMemcpyHostToDevice));
dim3 blocks = (size < THREADS) ? size : size / THREADS;
dim3 threadsPerBlock = (size < THREADS) ? 1 : THREADS;
for (int step = 2; step <= size; step <<= 1)
{
for (int depth = step >> 1; depth >= 1; depth >>= 1)
{
bitonic_exchange_gpu<<<blocks, threadsPerBlock>>>(array_gpu, depth , step);
}
}
gpu_error_check(cudaMemcpy(array, array_gpu, size_mem_array, cudaMemcpyDeviceToHost));
cudaFree(&array_gpu);
}
void bitonic_exchange(int* array, int depth, int step, unsigned long size)
{
for (int i = 0; i < size; i++)
{
unsigned int pair_for_i;
unsigned int orient_i, orient_pair_for_i;
pair_for_i = i + depth;
orient_pair_for_i = pair_for_i & step;
orient_i = i & step;
if (orient_i != 0 && orient_pair_for_i == 0
|| orient_i == 0 && orient_pair_for_i != 0)
{
continue;
}
if (orient_i == 0)
{
if (array[i] > array[pair_for_i])
{
swap(array, i, pair_for_i);
}
}
else
{
if (array[i] < array[pair_for_i])
{
swap(array, i, pair_for_i);
}
}
}
}
void bitonic_sort(int* array, unsigned long size)
{
for (int step = 2; step <= size; step <<= 1)
{
for (int j = step >> 1 ; j >= 1; j >>= 1)
{
bitonic_exchange(array, j, step, size);
}
}
} | code for sm_80
Function : _Z20bitonic_exchange_gpuPiim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ IADD3 R8, R6.reuse, c[0x0][0x168], RZ ; /* 0x00005a0006087a10 */
/* 0x040fe40007ffe0ff */
/*0050*/ LOP3.LUT P1, RZ, R6, c[0x0][0x170], RZ, 0xc0, !PT ; /* 0x00005c0006ff7a12 */
/* 0x000fe4000782c0ff */
/*0060*/ LOP3.LUT P0, RZ, R8, c[0x0][0x170], RZ, 0xc0, !PT ; /* 0x00005c0008ff7a12 */
/* 0x000fc8000780c0ff */
/*0070*/ PLOP3.LUT P0, PT, P1, !PT, P0, 0x5a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f1eb02 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00b0*/ IMAD.WIDE.U32 R2, R6, R9, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0009 */
/*00c0*/ IMAD.WIDE.U32 R4, R8, R9.reuse, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x080fe400078e0009 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000168000c1e1900 */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000162000c1e1900 */
/*00f0*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0100*/ IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fe200078e0209 */
/*0110*/ @!P1 BRA 0x190 ; /* 0x0000007000009947 */
/* 0x000fea0003800000 */
/*0120*/ ISETP.GE.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x020fda0003f06270 */
/*0130*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0140*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x001ee8000c1e1900 */
/*0160*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x004fe8000c101904 */
/*0170*/ STG.E [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x008fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ ISETP.GT.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x020fda0003f04270 */
/*01a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01b0*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x000ea8000c1e1900 */
/*01c0*/ LDG.E R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x001ee8000c1e1900 */
/*01d0*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x004fe8000c101904 */
/*01e0*/ STG.E [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x008fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "stdio.h"
#include "cuda_runtime.h"
#include <cuda_runtime_api.h>
#include "device_launch_parameters.h"
#define THREADS 1024
#define gpu_error_check(ans) { gpu_assert((ans), __FILE__, __LINE__); }
inline void gpu_assert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void swap(int* array, int first, int second)
{
int tmp = array[first];
array[first] = array[second];
array[second] = tmp;
}
__device__
void swap_gpu(int* array, int first, int second)
{
int tmp = array[first];
array[first] = array[second];
array[second] = tmp;
}
__global__
void bitonic_exchange_gpu(int* dev_values, int depth, unsigned long step)
{
/* Sorting partners: i and pair_for_i */
unsigned int i, pair_for_i;
/* Orient tells in which part of bitonic (sub-)sequence elements are (descending or ascending) */
unsigned int orient_i, orient_pair_for_i;
i = threadIdx.x + blockDim.x * blockIdx.x;
pair_for_i = i + depth;
orient_pair_for_i = pair_for_i & step;
orient_i = i & step;
/*
If current array[i] is the second for other array[j] (i<j) so we just do nothing
It can be seen if for some a[i], a[pair_for_i] located in other bitonic (sub-)sequence
For example, a[i] in ascending part, a[pair_for_i] in descending
*/
if (orient_i != 0 && orient_pair_for_i == 0
|| orient_i == 0 && orient_pair_for_i != 0)
{
return;
}
if (orient_i == 0)
{
/* Sort ascending */
if (dev_values[i]>dev_values[pair_for_i])
{
swap_gpu(dev_values, i, pair_for_i);
}
}
else
{
/* Sort descending */
if (dev_values[i]<dev_values[pair_for_i])
{
swap_gpu(dev_values, i, pair_for_i);
}
}
}
void bitonic_sort_gpu(int* array, unsigned long size)
{
size_t size_mem_array = size * sizeof(int);
int* array_gpu;
gpu_error_check(cudaMalloc(&array_gpu, size_mem_array));
gpu_error_check(cudaMemcpy(array_gpu, array, size_mem_array, cudaMemcpyHostToDevice));
dim3 blocks = (size < THREADS) ? size : size / THREADS;
dim3 threadsPerBlock = (size < THREADS) ? 1 : THREADS;
for (int step = 2; step <= size; step <<= 1)
{
for (int depth = step >> 1; depth >= 1; depth >>= 1)
{
bitonic_exchange_gpu<<<blocks, threadsPerBlock>>>(array_gpu, depth , step);
}
}
gpu_error_check(cudaMemcpy(array, array_gpu, size_mem_array, cudaMemcpyDeviceToHost));
cudaFree(&array_gpu);
}
void bitonic_exchange(int* array, int depth, int step, unsigned long size)
{
for (int i = 0; i < size; i++)
{
unsigned int pair_for_i;
unsigned int orient_i, orient_pair_for_i;
pair_for_i = i + depth;
orient_pair_for_i = pair_for_i & step;
orient_i = i & step;
if (orient_i != 0 && orient_pair_for_i == 0
|| orient_i == 0 && orient_pair_for_i != 0)
{
continue;
}
if (orient_i == 0)
{
if (array[i] > array[pair_for_i])
{
swap(array, i, pair_for_i);
}
}
else
{
if (array[i] < array[pair_for_i])
{
swap(array, i, pair_for_i);
}
}
}
}
void bitonic_sort(int* array, unsigned long size)
{
for (int step = 2; step <= size; step <<= 1)
{
for (int j = step >> 1 ; j >= 1; j >>= 1)
{
bitonic_exchange(array, j, step, size);
}
}
} | .file "tmpxft_0002a2a4_00000000-6_bitonic_sorts.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4swapPiii
.type _Z4swapPiii, @function
_Z4swapPiii:
.LFB2058:
.cfi_startproc
endbr64
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rcx
movl (%rcx), %esi
movslq %edx, %rdx
leaq (%rdi,%rdx,4), %rax
movl (%rax), %edx
movl %edx, (%rcx)
movl %esi, (%rax)
ret
.cfi_endproc
.LFE2058:
.size _Z4swapPiii, .-_Z4swapPiii
.globl _Z8swap_gpuPiii
.type _Z8swap_gpuPiii, @function
_Z8swap_gpuPiii:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z8swap_gpuPiii, .-_Z8swap_gpuPiii
.globl _Z16bitonic_exchangePiiim
.type _Z16bitonic_exchangePiiim, @function
_Z16bitonic_exchangePiiim:
.LFB2061:
.cfi_startproc
endbr64
testq %rcx, %rcx
je .L13
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r13
movl %edx, %r12d
movq %rcx, %r14
movl %esi, %ebp
movl $0, %ebx
jmp .L10
.L9:
movl %ebp, %eax
movl 0(%r13,%rax,4), %eax
cmpl %eax, 0(%r13,%rbx,4)
jl .L16
.L8:
addq $1, %rbx
addl $1, %ebp
cmpq %rbx, %r14
je .L17
.L10:
movl %ebx, %esi
movl %r12d, %ecx
andl %ebx, %ecx
setne %dl
testl %r12d, %ebp
setne %al
cmpb %al, %dl
jne .L8
testl %ecx, %ecx
jne .L9
movl %ebp, %eax
movl 0(%r13,%rax,4), %eax
cmpl %eax, 0(%r13,%rbx,4)
jle .L8
movl %ebp, %edx
movq %r13, %rdi
call _Z4swapPiii
jmp .L8
.L16:
movl %ebp, %edx
movq %r13, %rdi
call _Z4swapPiii
jmp .L8
.L17:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE2061:
.size _Z16bitonic_exchangePiiim, .-_Z16bitonic_exchangePiiim
.globl _Z12bitonic_sortPim
.type _Z12bitonic_sortPim, @function
_Z12bitonic_sortPim:
.LFB2062:
.cfi_startproc
endbr64
cmpq $1, %rsi
jbe .L26
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rdi, %r13
movq %rsi, %r12
movl $2, %ebp
.L22:
movl %ebp, %ebx
sarl %ebx
testl %ebx, %ebx
jle .L20
.L21:
movq %r12, %rcx
movl %ebp, %edx
movl %ebx, %esi
movq %r13, %rdi
call _Z16bitonic_exchangePiiim
sarl %ebx
testl %ebx, %ebx
jg .L21
.L20:
addl %ebp, %ebp
movslq %ebp, %rax
cmpq %rax, %r12
jnb .L22
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE2062:
.size _Z12bitonic_sortPim, .-_Z12bitonic_sortPim
.globl _Z42__device_stub__Z20bitonic_exchange_gpuPiimPiim
.type _Z42__device_stub__Z20bitonic_exchange_gpuPiimPiim, @function
_Z42__device_stub__Z20bitonic_exchange_gpuPiimPiim:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20bitonic_exchange_gpuPiim(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z42__device_stub__Z20bitonic_exchange_gpuPiimPiim, .-_Z42__device_stub__Z20bitonic_exchange_gpuPiimPiim
.globl _Z20bitonic_exchange_gpuPiim
.type _Z20bitonic_exchange_gpuPiim, @function
_Z20bitonic_exchange_gpuPiim:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z20bitonic_exchange_gpuPiimPiim
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z20bitonic_exchange_gpuPiim, .-_Z20bitonic_exchange_gpuPiim
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/KanashinDmitry/spbu-se2019-autumn/master/Task06/bitonic_sorts.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "GPUassert: %s %s %d\n"
.text
.globl _Z16bitonic_sort_gpuPim
.type _Z16bitonic_sort_gpuPim, @function
_Z16bitonic_sort_gpuPim:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 0(,%rsi,4), %r15
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L52
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L53
cmpq $1023, %r13
jbe .L40
movq %r13, %rax
shrq $10, %rax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
.L41:
movl $2, %r12d
movl $2, %ebp
jmp .L46
.L52:
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $82, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L53:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $83, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L40:
movl %r13d, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
cmpq $1, %r13
ja .L41
.L42:
movl $2, %ecx
movq %r15, %rdx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L54
leaq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
sarl %ebx
testl %ebx, %ebx
jle .L43
.L45:
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L44
movq %rbp, %rdx
movl %ebx, %esi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z20bitonic_exchange_gpuPiimPiim
jmp .L44
.L43:
addl %r12d, %r12d
movslq %r12d, %rbp
cmpq %rbp, %r13
jb .L42
.L46:
movl %r12d, %ebx
sarl %ebx
testl %ebx, %ebx
jg .L45
jmp .L43
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $96, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z16bitonic_sort_gpuPim, .-_Z16bitonic_sort_gpuPim
.section .rodata.str1.1
.LC2:
.string "_Z20bitonic_exchange_gpuPiim"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z20bitonic_exchange_gpuPiim(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "stdio.h"
#include "cuda_runtime.h"
#include <cuda_runtime_api.h>
#include "device_launch_parameters.h"
#define THREADS 1024
#define gpu_error_check(ans) { gpu_assert((ans), __FILE__, __LINE__); }
inline void gpu_assert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void swap(int* array, int first, int second)
{
int tmp = array[first];
array[first] = array[second];
array[second] = tmp;
}
__device__
void swap_gpu(int* array, int first, int second)
{
int tmp = array[first];
array[first] = array[second];
array[second] = tmp;
}
__global__
void bitonic_exchange_gpu(int* dev_values, int depth, unsigned long step)
{
/* Sorting partners: i and pair_for_i */
unsigned int i, pair_for_i;
/* Orient tells in which part of bitonic (sub-)sequence elements are (descending or ascending) */
unsigned int orient_i, orient_pair_for_i;
i = threadIdx.x + blockDim.x * blockIdx.x;
pair_for_i = i + depth;
orient_pair_for_i = pair_for_i & step;
orient_i = i & step;
/*
If current array[i] is the second for other array[j] (i<j) so we just do nothing
It can be seen if for some a[i], a[pair_for_i] located in other bitonic (sub-)sequence
For example, a[i] in ascending part, a[pair_for_i] in descending
*/
if (orient_i != 0 && orient_pair_for_i == 0
|| orient_i == 0 && orient_pair_for_i != 0)
{
return;
}
if (orient_i == 0)
{
/* Sort ascending */
if (dev_values[i]>dev_values[pair_for_i])
{
swap_gpu(dev_values, i, pair_for_i);
}
}
else
{
/* Sort descending */
if (dev_values[i]<dev_values[pair_for_i])
{
swap_gpu(dev_values, i, pair_for_i);
}
}
}
void bitonic_sort_gpu(int* array, unsigned long size)
{
size_t size_mem_array = size * sizeof(int);
int* array_gpu;
gpu_error_check(cudaMalloc(&array_gpu, size_mem_array));
gpu_error_check(cudaMemcpy(array_gpu, array, size_mem_array, cudaMemcpyHostToDevice));
dim3 blocks = (size < THREADS) ? size : size / THREADS;
dim3 threadsPerBlock = (size < THREADS) ? 1 : THREADS;
for (int step = 2; step <= size; step <<= 1)
{
for (int depth = step >> 1; depth >= 1; depth >>= 1)
{
bitonic_exchange_gpu<<<blocks, threadsPerBlock>>>(array_gpu, depth , step);
}
}
gpu_error_check(cudaMemcpy(array, array_gpu, size_mem_array, cudaMemcpyDeviceToHost));
cudaFree(&array_gpu);
}
void bitonic_exchange(int* array, int depth, int step, unsigned long size)
{
for (int i = 0; i < size; i++)
{
unsigned int pair_for_i;
unsigned int orient_i, orient_pair_for_i;
pair_for_i = i + depth;
orient_pair_for_i = pair_for_i & step;
orient_i = i & step;
if (orient_i != 0 && orient_pair_for_i == 0
|| orient_i == 0 && orient_pair_for_i != 0)
{
continue;
}
if (orient_i == 0)
{
if (array[i] > array[pair_for_i])
{
swap(array, i, pair_for_i);
}
}
else
{
if (array[i] < array[pair_for_i])
{
swap(array, i, pair_for_i);
}
}
}
}
void bitonic_sort(int* array, unsigned long size)
{
for (int step = 2; step <= size; step <<= 1)
{
for (int j = step >> 1 ; j >= 1; j >>= 1)
{
bitonic_exchange(array, j, step, size);
}
}
} | #include "stdio.h"
#include "hip/hip_runtime.h"
#include <hip/hip_runtime_api.h>
#define THREADS 1024
#define gpu_error_check(ans) { gpu_assert((ans), __FILE__, __LINE__); }
inline void gpu_assert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void swap(int* array, int first, int second)
{
int tmp = array[first];
array[first] = array[second];
array[second] = tmp;
}
__device__
void swap_gpu(int* array, int first, int second)
{
int tmp = array[first];
array[first] = array[second];
array[second] = tmp;
}
__global__
void bitonic_exchange_gpu(int* dev_values, int depth, unsigned long step)
{
/* Sorting partners: i and pair_for_i */
unsigned int i, pair_for_i;
/* Orient tells in which part of bitonic (sub-)sequence elements are (descending or ascending) */
unsigned int orient_i, orient_pair_for_i;
i = threadIdx.x + blockDim.x * blockIdx.x;
pair_for_i = i + depth;
orient_pair_for_i = pair_for_i & step;
orient_i = i & step;
/*
If current array[i] is the second for other array[j] (i<j) so we just do nothing
It can be seen if for some a[i], a[pair_for_i] located in other bitonic (sub-)sequence
For example, a[i] in ascending part, a[pair_for_i] in descending
*/
if (orient_i != 0 && orient_pair_for_i == 0
|| orient_i == 0 && orient_pair_for_i != 0)
{
return;
}
if (orient_i == 0)
{
/* Sort ascending */
if (dev_values[i]>dev_values[pair_for_i])
{
swap_gpu(dev_values, i, pair_for_i);
}
}
else
{
/* Sort descending */
if (dev_values[i]<dev_values[pair_for_i])
{
swap_gpu(dev_values, i, pair_for_i);
}
}
}
void bitonic_sort_gpu(int* array, unsigned long size)
{
size_t size_mem_array = size * sizeof(int);
int* array_gpu;
gpu_error_check(hipMalloc(&array_gpu, size_mem_array));
gpu_error_check(hipMemcpy(array_gpu, array, size_mem_array, hipMemcpyHostToDevice));
dim3 blocks = (size < THREADS) ? size : size / THREADS;
dim3 threadsPerBlock = (size < THREADS) ? 1 : THREADS;
for (int step = 2; step <= size; step <<= 1)
{
for (int depth = step >> 1; depth >= 1; depth >>= 1)
{
bitonic_exchange_gpu<<<blocks, threadsPerBlock>>>(array_gpu, depth , step);
}
}
gpu_error_check(hipMemcpy(array, array_gpu, size_mem_array, hipMemcpyDeviceToHost));
hipFree(&array_gpu);
}
void bitonic_exchange(int* array, int depth, int step, unsigned long size)
{
for (int i = 0; i < size; i++)
{
unsigned int pair_for_i;
unsigned int orient_i, orient_pair_for_i;
pair_for_i = i + depth;
orient_pair_for_i = pair_for_i & step;
orient_i = i & step;
if (orient_i != 0 && orient_pair_for_i == 0
|| orient_i == 0 && orient_pair_for_i != 0)
{
continue;
}
if (orient_i == 0)
{
if (array[i] > array[pair_for_i])
{
swap(array, i, pair_for_i);
}
}
else
{
if (array[i] < array[pair_for_i])
{
swap(array, i, pair_for_i);
}
}
}
}
void bitonic_sort(int* array, unsigned long size)
{
for (int step = 2; step <= size; step <<= 1)
{
for (int j = step >> 1 ; j >= 1; j >>= 1)
{
bitonic_exchange(array, j, step, size);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "stdio.h"
#include "hip/hip_runtime.h"
#include <hip/hip_runtime_api.h>
#define THREADS 1024
#define gpu_error_check(ans) { gpu_assert((ans), __FILE__, __LINE__); }
inline void gpu_assert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void swap(int* array, int first, int second)
{
int tmp = array[first];
array[first] = array[second];
array[second] = tmp;
}
__device__
void swap_gpu(int* array, int first, int second)
{
int tmp = array[first];
array[first] = array[second];
array[second] = tmp;
}
__global__
void bitonic_exchange_gpu(int* dev_values, int depth, unsigned long step)
{
/* Sorting partners: i and pair_for_i */
unsigned int i, pair_for_i;
/* Orient tells in which part of bitonic (sub-)sequence elements are (descending or ascending) */
unsigned int orient_i, orient_pair_for_i;
i = threadIdx.x + blockDim.x * blockIdx.x;
pair_for_i = i + depth;
orient_pair_for_i = pair_for_i & step;
orient_i = i & step;
/*
If current array[i] is the second for other array[j] (i<j) so we just do nothing
It can be seen if for some a[i], a[pair_for_i] located in other bitonic (sub-)sequence
For example, a[i] in ascending part, a[pair_for_i] in descending
*/
if (orient_i != 0 && orient_pair_for_i == 0
|| orient_i == 0 && orient_pair_for_i != 0)
{
return;
}
if (orient_i == 0)
{
/* Sort ascending */
if (dev_values[i]>dev_values[pair_for_i])
{
swap_gpu(dev_values, i, pair_for_i);
}
}
else
{
/* Sort descending */
if (dev_values[i]<dev_values[pair_for_i])
{
swap_gpu(dev_values, i, pair_for_i);
}
}
}
void bitonic_sort_gpu(int* array, unsigned long size)
{
size_t size_mem_array = size * sizeof(int);
int* array_gpu;
gpu_error_check(hipMalloc(&array_gpu, size_mem_array));
gpu_error_check(hipMemcpy(array_gpu, array, size_mem_array, hipMemcpyHostToDevice));
dim3 blocks = (size < THREADS) ? size : size / THREADS;
dim3 threadsPerBlock = (size < THREADS) ? 1 : THREADS;
for (int step = 2; step <= size; step <<= 1)
{
for (int depth = step >> 1; depth >= 1; depth >>= 1)
{
bitonic_exchange_gpu<<<blocks, threadsPerBlock>>>(array_gpu, depth , step);
}
}
gpu_error_check(hipMemcpy(array, array_gpu, size_mem_array, hipMemcpyDeviceToHost));
hipFree(&array_gpu);
}
void bitonic_exchange(int* array, int depth, int step, unsigned long size)
{
for (int i = 0; i < size; i++)
{
unsigned int pair_for_i;
unsigned int orient_i, orient_pair_for_i;
pair_for_i = i + depth;
orient_pair_for_i = pair_for_i & step;
orient_i = i & step;
if (orient_i != 0 && orient_pair_for_i == 0
|| orient_i == 0 && orient_pair_for_i != 0)
{
continue;
}
if (orient_i == 0)
{
if (array[i] > array[pair_for_i])
{
swap(array, i, pair_for_i);
}
}
else
{
if (array[i] < array[pair_for_i])
{
swap(array, i, pair_for_i);
}
}
}
}
void bitonic_sort(int* array, unsigned long size)
{
for (int step = 2; step <= size; step <<= 1)
{
for (int j = step >> 1 ; j >= 1; j >>= 1)
{
bitonic_exchange(array, j, step, size);
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20bitonic_exchange_gpuPiim
.globl _Z20bitonic_exchange_gpuPiim
.p2align 8
.type _Z20bitonic_exchange_gpuPiim,@function
_Z20bitonic_exchange_gpuPiim:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_add_nc_u32_e32 v3, s3, v1
v_and_b32_e32 v2, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v0, s4, v3
v_cmp_eq_u32_e32 vcc_lo, 0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e64 s2, 0, v0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_9
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_cmp_eq_u32_e64 s2, 0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_9
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v2, v4
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s2, v5
v_add_co_ci_u32_e64 v5, s0, s3, v6, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s2, v7
v_add_co_ci_u32_e64 v7, s0, s3, v8, s0
s_clause 0x1
global_load_b32 v0, v[4:5], off
global_load_b32 v5, v[6:7], off
s_and_saveexec_b32 s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_6
s_mov_b32 s1, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v0, v5
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_clause 0x1
global_load_b32 v4, v[2:3], off
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(1)
global_store_b32 v[0:1], v4, off
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v5, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s1
.LBB0_6:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_9
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v0, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_9
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_clause 0x1
global_load_b32 v4, v[2:3], off
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(1)
global_store_b32 v[0:1], v4, off
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v5, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20bitonic_exchange_gpuPiim
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20bitonic_exchange_gpuPiim, .Lfunc_end0-_Z20bitonic_exchange_gpuPiim
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20bitonic_exchange_gpuPiim
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20bitonic_exchange_gpuPiim.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "stdio.h"
#include "hip/hip_runtime.h"
#include <hip/hip_runtime_api.h>
#define THREADS 1024
#define gpu_error_check(ans) { gpu_assert((ans), __FILE__, __LINE__); }
inline void gpu_assert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
void swap(int* array, int first, int second)
{
int tmp = array[first];
array[first] = array[second];
array[second] = tmp;
}
__device__
void swap_gpu(int* array, int first, int second)
{
int tmp = array[first];
array[first] = array[second];
array[second] = tmp;
}
__global__
void bitonic_exchange_gpu(int* dev_values, int depth, unsigned long step)
{
/* Sorting partners: i and pair_for_i */
unsigned int i, pair_for_i;
/* Orient tells in which part of bitonic (sub-)sequence elements are (descending or ascending) */
unsigned int orient_i, orient_pair_for_i;
i = threadIdx.x + blockDim.x * blockIdx.x;
pair_for_i = i + depth;
orient_pair_for_i = pair_for_i & step;
orient_i = i & step;
/*
If current array[i] is the second for other array[j] (i<j) so we just do nothing
It can be seen if for some a[i], a[pair_for_i] located in other bitonic (sub-)sequence
For example, a[i] in ascending part, a[pair_for_i] in descending
*/
if (orient_i != 0 && orient_pair_for_i == 0
|| orient_i == 0 && orient_pair_for_i != 0)
{
return;
}
if (orient_i == 0)
{
/* Sort ascending */
if (dev_values[i]>dev_values[pair_for_i])
{
swap_gpu(dev_values, i, pair_for_i);
}
}
else
{
/* Sort descending */
if (dev_values[i]<dev_values[pair_for_i])
{
swap_gpu(dev_values, i, pair_for_i);
}
}
}
void bitonic_sort_gpu(int* array, unsigned long size)
{
size_t size_mem_array = size * sizeof(int);
int* array_gpu;
gpu_error_check(hipMalloc(&array_gpu, size_mem_array));
gpu_error_check(hipMemcpy(array_gpu, array, size_mem_array, hipMemcpyHostToDevice));
dim3 blocks = (size < THREADS) ? size : size / THREADS;
dim3 threadsPerBlock = (size < THREADS) ? 1 : THREADS;
for (int step = 2; step <= size; step <<= 1)
{
for (int depth = step >> 1; depth >= 1; depth >>= 1)
{
bitonic_exchange_gpu<<<blocks, threadsPerBlock>>>(array_gpu, depth , step);
}
}
gpu_error_check(hipMemcpy(array, array_gpu, size_mem_array, hipMemcpyDeviceToHost));
hipFree(&array_gpu);
}
void bitonic_exchange(int* array, int depth, int step, unsigned long size)
{
for (int i = 0; i < size; i++)
{
unsigned int pair_for_i;
unsigned int orient_i, orient_pair_for_i;
pair_for_i = i + depth;
orient_pair_for_i = pair_for_i & step;
orient_i = i & step;
if (orient_i != 0 && orient_pair_for_i == 0
|| orient_i == 0 && orient_pair_for_i != 0)
{
continue;
}
if (orient_i == 0)
{
if (array[i] > array[pair_for_i])
{
swap(array, i, pair_for_i);
}
}
else
{
if (array[i] < array[pair_for_i])
{
swap(array, i, pair_for_i);
}
}
}
}
void bitonic_sort(int* array, unsigned long size)
{
for (int step = 2; step <= size; step <<= 1)
{
for (int j = step >> 1 ; j >= 1; j >>= 1)
{
bitonic_exchange(array, j, step, size);
}
}
} | .text
.file "bitonic_sorts.hip"
.globl _Z4swapPiii # -- Begin function _Z4swapPiii
.p2align 4, 0x90
.type _Z4swapPiii,@function
_Z4swapPiii: # @_Z4swapPiii
.cfi_startproc
# %bb.0:
movslq %esi, %rax
movl (%rdi,%rax,4), %ecx
movslq %edx, %rdx
movl (%rdi,%rdx,4), %esi
movl %esi, (%rdi,%rax,4)
movl %ecx, (%rdi,%rdx,4)
retq
.Lfunc_end0:
.size _Z4swapPiii, .Lfunc_end0-_Z4swapPiii
.cfi_endproc
# -- End function
.globl _Z35__device_stub__bitonic_exchange_gpuPiim # -- Begin function _Z35__device_stub__bitonic_exchange_gpuPiim
.p2align 4, 0x90
.type _Z35__device_stub__bitonic_exchange_gpuPiim,@function
_Z35__device_stub__bitonic_exchange_gpuPiim: # @_Z35__device_stub__bitonic_exchange_gpuPiim
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20bitonic_exchange_gpuPiim, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z35__device_stub__bitonic_exchange_gpuPiim, .Lfunc_end1-_Z35__device_stub__bitonic_exchange_gpuPiim
.cfi_endproc
# -- End function
.globl _Z16bitonic_sort_gpuPim # -- Begin function _Z16bitonic_sort_gpuPim
.p2align 4, 0x90
.type _Z16bitonic_sort_gpuPim,@function
_Z16bitonic_sort_gpuPim: # @_Z16bitonic_sort_gpuPim
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %r14
movq %rsi, 24(%rsp) # 8-byte Spill
leaq (,%rsi,4), %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_Z10gpu_assert10hipError_tPKcib.exit
movq 8(%rsp), %rdi
movq %r14, 32(%rsp) # 8-byte Spill
movq %r14, %rsi
movq %rbx, 40(%rsp) # 8-byte Spill
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_4
# %bb.5: # %_Z10gpu_assert10hipError_tPKcib.exit27
movq 24(%rsp), %rsi # 8-byte Reload
movq %rsi, %rcx
shrq $10, %rcx
movabsq $4294967296, %rax # imm = 0x100000000
leaq 1(%rax), %rdx
cmpq $1024, %rsi # imm = 0x400
cmovbq %rsi, %rcx
leaq 1024(%rax), %r12
cmovbq %rdx, %r12
cmpq $2, %rsi
jae .LBB2_6
.LBB2_9: # %._crit_edge36
movq 8(%rsp), %rsi
movq 32(%rsp), %rdi # 8-byte Reload
movq 40(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_10
# %bb.11: # %_Z10gpu_assert10hipError_tPKcib.exit29
leaq 8(%rsp), %rdi
callq hipFree
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_6: # %.lr.ph35
.cfi_def_cfa_offset 192
movl %ecx, %r13d
orq %rax, %r13
movl $2, %r15d
movl $2, %ebx
leaq 112(%rsp), %rbp
jmp .LBB2_7
.p2align 4, 0x90
.LBB2_8: # %._crit_edge
# in Loop: Header=BB2_7 Depth=1
addl %r15d, %r15d
movslq %r15d, %rbx
cmpq 24(%rsp), %rbx # 8-byte Folded Reload
ja .LBB2_9
.LBB2_7: # =>This Loop Header: Depth=1
# Child Loop BB2_12 Depth 2
movl %r15d, %r14d
sarl %r14d
testl %r14d, %r14d
jg .LBB2_12
jmp .LBB2_8
.p2align 4, 0x90
.LBB2_14: # in Loop: Header=BB2_12 Depth=2
movl %r14d, %eax
shrl %eax
cmpl $2, %r14d
movl %eax, %r14d
jb .LBB2_8
.LBB2_12: # %.lr.ph
# Parent Loop BB2_7 Depth=1
# => This Inner Loop Header: Depth=2
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13: # in Loop: Header=BB2_12 Depth=2
movq 8(%rsp), %rax
movq %rax, 104(%rsp)
movl %r14d, 20(%rsp)
movq %rbx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z20bitonic_exchange_gpuPiim, %edi
movq %rbp, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_14
.LBB2_1:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $82, %r8d
jmp .LBB2_2
.LBB2_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $83, %r8d
jmp .LBB2_2
.LBB2_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $96, %r8d
.LBB2_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end2:
.size _Z16bitonic_sort_gpuPim, .Lfunc_end2-_Z16bitonic_sort_gpuPim
.cfi_endproc
# -- End function
.globl _Z16bitonic_exchangePiiim # -- Begin function _Z16bitonic_exchangePiiim
.p2align 4, 0x90
.type _Z16bitonic_exchangePiiim,@function
_Z16bitonic_exchangePiiim: # @_Z16bitonic_exchangePiiim
.cfi_startproc
# %bb.0:
testq %rcx, %rcx
je .LBB3_11
# %bb.1: # %.lr.ph.preheader
movslq %esi, %rax
leaq (%rdi,%rax,4), %rsi
movl %eax, %r8d
xorl %r9d, %r9d
jmp .LBB3_2
.LBB3_9: # in Loop: Header=BB3_2 Depth=1
movl (%rdi,%r9,4), %r10d
movl (%rsi,%r9,4), %r11d
movl %r11d, (%rdi,%r9,4)
movl %r10d, (%rsi,%r9,4)
.p2align 4, 0x90
.LBB3_10: # in Loop: Header=BB3_2 Depth=1
incq %r9
cmpq %r9, %rcx
je .LBB3_11
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leal (%r8,%r9), %r10d
andl %edx, %r10d
testl %edx, %r9d
je .LBB3_4
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
testl %r10d, %r10d
je .LBB3_10
.LBB3_4: # in Loop: Header=BB3_2 Depth=1
testl %edx, %r9d
jne .LBB3_6
# %bb.5: # in Loop: Header=BB3_2 Depth=1
testl %r10d, %r10d
jne .LBB3_10
.LBB3_6: # in Loop: Header=BB3_2 Depth=1
leaq (%rax,%r9), %r11
movl (%rdi,%r9,4), %r10d
movl %r11d, %r11d
movl (%rdi,%r11,4), %r11d
testl %edx, %r9d
je .LBB3_7
# %bb.8: # in Loop: Header=BB3_2 Depth=1
cmpl %r11d, %r10d
jl .LBB3_9
jmp .LBB3_10
.LBB3_7: # in Loop: Header=BB3_2 Depth=1
cmpl %r11d, %r10d
jg .LBB3_9
jmp .LBB3_10
.LBB3_11: # %._crit_edge
retq
.Lfunc_end3:
.size _Z16bitonic_exchangePiiim, .Lfunc_end3-_Z16bitonic_exchangePiiim
.cfi_endproc
# -- End function
.globl _Z12bitonic_sortPim # -- Begin function _Z12bitonic_sortPim
.p2align 4, 0x90
.type _Z12bitonic_sortPim,@function
_Z12bitonic_sortPim: # @_Z12bitonic_sortPim
.cfi_startproc
# %bb.0:
cmpq $2, %rsi
jae .LBB4_1
.LBB4_4: # %._crit_edge16
retq
.LBB4_1: # %.lr.ph15.preheader
movl $2, %eax
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_3: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
addl %eax, %eax
movslq %eax, %rcx
cmpq %rsi, %rcx
ja .LBB4_4
.LBB4_2: # %.lr.ph15
# =>This Loop Header: Depth=1
# Child Loop BB4_5 Depth 2
# Child Loop BB4_6 Depth 3
movl %eax, %edx
sarl %edx
testl %edx, %edx
jg .LBB4_5
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_15: # %_Z16bitonic_exchangePiiim.exit
# in Loop: Header=BB4_5 Depth=2
movl %ecx, %edx
shrl %edx
cmpl $2, %ecx
jb .LBB4_3
.LBB4_5: # %.lr.ph
# Parent Loop BB4_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_6 Depth 3
movl %edx, %ecx
leaq (%rdi,%rcx,4), %rdx
xorl %r8d, %r8d
jmp .LBB4_6
.LBB4_13: # %.sink.split
# in Loop: Header=BB4_6 Depth=3
movl (%rdx,%r8,4), %r9d
movl %r9d, (%rdi,%r8,4)
movl %r10d, (%rdx,%r8,4)
.p2align 4, 0x90
.LBB4_14: # in Loop: Header=BB4_6 Depth=3
incq %r8
cmpq %r8, %rsi
je .LBB4_15
.LBB4_6: # %.lr.ph.i
# Parent Loop BB4_2 Depth=1
# Parent Loop BB4_5 Depth=2
# => This Inner Loop Header: Depth=3
leaq (%rcx,%r8), %r9
movl %eax, %r10d
andl %r9d, %r10d
testl %r8d, %eax
je .LBB4_8
# %bb.7: # %.lr.ph.i
# in Loop: Header=BB4_6 Depth=3
testl %r10d, %r10d
je .LBB4_14
.LBB4_8: # in Loop: Header=BB4_6 Depth=3
testl %r8d, %eax
jne .LBB4_10
# %bb.9: # in Loop: Header=BB4_6 Depth=3
testl %r10d, %r10d
jne .LBB4_14
.LBB4_10: # in Loop: Header=BB4_6 Depth=3
movl (%rdi,%r8,4), %r10d
movl %r9d, %r9d
movl (%rdi,%r9,4), %r9d
testl %r8d, %eax
je .LBB4_11
# %bb.12: # in Loop: Header=BB4_6 Depth=3
cmpl %r9d, %r10d
jl .LBB4_13
jmp .LBB4_14
.LBB4_11: # in Loop: Header=BB4_6 Depth=3
cmpl %r9d, %r10d
jg .LBB4_13
jmp .LBB4_14
.Lfunc_end4:
.size _Z12bitonic_sortPim, .Lfunc_end4-_Z12bitonic_sortPim
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20bitonic_exchange_gpuPiim, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20bitonic_exchange_gpuPiim,@object # @_Z20bitonic_exchange_gpuPiim
.section .rodata,"a",@progbits
.globl _Z20bitonic_exchange_gpuPiim
.p2align 3, 0x0
_Z20bitonic_exchange_gpuPiim:
.quad _Z35__device_stub__bitonic_exchange_gpuPiim
.size _Z20bitonic_exchange_gpuPiim, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/KanashinDmitry/spbu-se2019-autumn/master/Task06/bitonic_sorts.hip"
.size .L.str, 123
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.1, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20bitonic_exchange_gpuPiim"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__bitonic_exchange_gpuPiim
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20bitonic_exchange_gpuPiim
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20bitonic_exchange_gpuPiim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ IADD3 R8, R6.reuse, c[0x0][0x168], RZ ; /* 0x00005a0006087a10 */
/* 0x040fe40007ffe0ff */
/*0050*/ LOP3.LUT P1, RZ, R6, c[0x0][0x170], RZ, 0xc0, !PT ; /* 0x00005c0006ff7a12 */
/* 0x000fe4000782c0ff */
/*0060*/ LOP3.LUT P0, RZ, R8, c[0x0][0x170], RZ, 0xc0, !PT ; /* 0x00005c0008ff7a12 */
/* 0x000fc8000780c0ff */
/*0070*/ PLOP3.LUT P0, PT, P1, !PT, P0, 0x5a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f1eb02 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00b0*/ IMAD.WIDE.U32 R2, R6, R9, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0009 */
/*00c0*/ IMAD.WIDE.U32 R4, R8, R9.reuse, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x080fe400078e0009 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000168000c1e1900 */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000162000c1e1900 */
/*00f0*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0100*/ IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fe200078e0209 */
/*0110*/ @!P1 BRA 0x190 ; /* 0x0000007000009947 */
/* 0x000fea0003800000 */
/*0120*/ ISETP.GE.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x020fda0003f06270 */
/*0130*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0140*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x001ee8000c1e1900 */
/*0160*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x004fe8000c101904 */
/*0170*/ STG.E [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x008fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ ISETP.GT.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x020fda0003f04270 */
/*01a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01b0*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x000ea8000c1e1900 */
/*01c0*/ LDG.E R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x001ee8000c1e1900 */
/*01d0*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x004fe8000c101904 */
/*01e0*/ STG.E [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x008fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20bitonic_exchange_gpuPiim
.globl _Z20bitonic_exchange_gpuPiim
.p2align 8
.type _Z20bitonic_exchange_gpuPiim,@function
_Z20bitonic_exchange_gpuPiim:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_add_nc_u32_e32 v3, s3, v1
v_and_b32_e32 v2, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v0, s4, v3
v_cmp_eq_u32_e32 vcc_lo, 0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e64 s2, 0, v0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_9
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_cmp_eq_u32_e64 s2, 0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_9
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v2, v4
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s2, v5
v_add_co_ci_u32_e64 v5, s0, s3, v6, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s2, v7
v_add_co_ci_u32_e64 v7, s0, s3, v8, s0
s_clause 0x1
global_load_b32 v0, v[4:5], off
global_load_b32 v5, v[6:7], off
s_and_saveexec_b32 s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_6
s_mov_b32 s1, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v0, v5
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_clause 0x1
global_load_b32 v4, v[2:3], off
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(1)
global_store_b32 v[0:1], v4, off
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v5, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s1
.LBB0_6:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_9
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v0, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_9
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_clause 0x1
global_load_b32 v4, v[2:3], off
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(1)
global_store_b32 v[0:1], v4, off
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v5, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20bitonic_exchange_gpuPiim
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20bitonic_exchange_gpuPiim, .Lfunc_end0-_Z20bitonic_exchange_gpuPiim
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20bitonic_exchange_gpuPiim
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20bitonic_exchange_gpuPiim.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002a2a4_00000000-6_bitonic_sorts.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4swapPiii
.type _Z4swapPiii, @function
_Z4swapPiii:
.LFB2058:
.cfi_startproc
endbr64
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rcx
movl (%rcx), %esi
movslq %edx, %rdx
leaq (%rdi,%rdx,4), %rax
movl (%rax), %edx
movl %edx, (%rcx)
movl %esi, (%rax)
ret
.cfi_endproc
.LFE2058:
.size _Z4swapPiii, .-_Z4swapPiii
.globl _Z8swap_gpuPiii
.type _Z8swap_gpuPiii, @function
_Z8swap_gpuPiii:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z8swap_gpuPiii, .-_Z8swap_gpuPiii
.globl _Z16bitonic_exchangePiiim
.type _Z16bitonic_exchangePiiim, @function
_Z16bitonic_exchangePiiim:
.LFB2061:
.cfi_startproc
endbr64
testq %rcx, %rcx
je .L13
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r13
movl %edx, %r12d
movq %rcx, %r14
movl %esi, %ebp
movl $0, %ebx
jmp .L10
.L9:
movl %ebp, %eax
movl 0(%r13,%rax,4), %eax
cmpl %eax, 0(%r13,%rbx,4)
jl .L16
.L8:
addq $1, %rbx
addl $1, %ebp
cmpq %rbx, %r14
je .L17
.L10:
movl %ebx, %esi
movl %r12d, %ecx
andl %ebx, %ecx
setne %dl
testl %r12d, %ebp
setne %al
cmpb %al, %dl
jne .L8
testl %ecx, %ecx
jne .L9
movl %ebp, %eax
movl 0(%r13,%rax,4), %eax
cmpl %eax, 0(%r13,%rbx,4)
jle .L8
movl %ebp, %edx
movq %r13, %rdi
call _Z4swapPiii
jmp .L8
.L16:
movl %ebp, %edx
movq %r13, %rdi
call _Z4swapPiii
jmp .L8
.L17:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE2061:
.size _Z16bitonic_exchangePiiim, .-_Z16bitonic_exchangePiiim
.globl _Z12bitonic_sortPim
.type _Z12bitonic_sortPim, @function
_Z12bitonic_sortPim:
.LFB2062:
.cfi_startproc
endbr64
cmpq $1, %rsi
jbe .L26
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rdi, %r13
movq %rsi, %r12
movl $2, %ebp
.L22:
movl %ebp, %ebx
sarl %ebx
testl %ebx, %ebx
jle .L20
.L21:
movq %r12, %rcx
movl %ebp, %edx
movl %ebx, %esi
movq %r13, %rdi
call _Z16bitonic_exchangePiiim
sarl %ebx
testl %ebx, %ebx
jg .L21
.L20:
addl %ebp, %ebp
movslq %ebp, %rax
cmpq %rax, %r12
jnb .L22
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE2062:
.size _Z12bitonic_sortPim, .-_Z12bitonic_sortPim
.globl _Z42__device_stub__Z20bitonic_exchange_gpuPiimPiim
.type _Z42__device_stub__Z20bitonic_exchange_gpuPiimPiim, @function
_Z42__device_stub__Z20bitonic_exchange_gpuPiimPiim:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20bitonic_exchange_gpuPiim(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z42__device_stub__Z20bitonic_exchange_gpuPiimPiim, .-_Z42__device_stub__Z20bitonic_exchange_gpuPiimPiim
.globl _Z20bitonic_exchange_gpuPiim
.type _Z20bitonic_exchange_gpuPiim, @function
_Z20bitonic_exchange_gpuPiim:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z20bitonic_exchange_gpuPiimPiim
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z20bitonic_exchange_gpuPiim, .-_Z20bitonic_exchange_gpuPiim
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/KanashinDmitry/spbu-se2019-autumn/master/Task06/bitonic_sorts.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "GPUassert: %s %s %d\n"
.text
.globl _Z16bitonic_sort_gpuPim
.type _Z16bitonic_sort_gpuPim, @function
_Z16bitonic_sort_gpuPim:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 0(,%rsi,4), %r15
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L52
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L53
cmpq $1023, %r13
jbe .L40
movq %r13, %rax
shrq $10, %rax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
.L41:
movl $2, %r12d
movl $2, %ebp
jmp .L46
.L52:
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $82, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L53:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $83, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L40:
movl %r13d, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
cmpq $1, %r13
ja .L41
.L42:
movl $2, %ecx
movq %r15, %rdx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L54
leaq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
sarl %ebx
testl %ebx, %ebx
jle .L43
.L45:
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L44
movq %rbp, %rdx
movl %ebx, %esi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z20bitonic_exchange_gpuPiimPiim
jmp .L44
.L43:
addl %r12d, %r12d
movslq %r12d, %rbp
cmpq %rbp, %r13
jb .L42
.L46:
movl %r12d, %ebx
sarl %ebx
testl %ebx, %ebx
jg .L45
jmp .L43
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $96, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z16bitonic_sort_gpuPim, .-_Z16bitonic_sort_gpuPim
.section .rodata.str1.1
.LC2:
.string "_Z20bitonic_exchange_gpuPiim"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z20bitonic_exchange_gpuPiim(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bitonic_sorts.hip"
.globl _Z4swapPiii # -- Begin function _Z4swapPiii
.p2align 4, 0x90
.type _Z4swapPiii,@function
_Z4swapPiii: # @_Z4swapPiii
.cfi_startproc
# %bb.0:
movslq %esi, %rax
movl (%rdi,%rax,4), %ecx
movslq %edx, %rdx
movl (%rdi,%rdx,4), %esi
movl %esi, (%rdi,%rax,4)
movl %ecx, (%rdi,%rdx,4)
retq
.Lfunc_end0:
.size _Z4swapPiii, .Lfunc_end0-_Z4swapPiii
.cfi_endproc
# -- End function
.globl _Z35__device_stub__bitonic_exchange_gpuPiim # -- Begin function _Z35__device_stub__bitonic_exchange_gpuPiim
.p2align 4, 0x90
.type _Z35__device_stub__bitonic_exchange_gpuPiim,@function
_Z35__device_stub__bitonic_exchange_gpuPiim: # @_Z35__device_stub__bitonic_exchange_gpuPiim
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20bitonic_exchange_gpuPiim, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z35__device_stub__bitonic_exchange_gpuPiim, .Lfunc_end1-_Z35__device_stub__bitonic_exchange_gpuPiim
.cfi_endproc
# -- End function
.globl _Z16bitonic_sort_gpuPim # -- Begin function _Z16bitonic_sort_gpuPim
.p2align 4, 0x90
.type _Z16bitonic_sort_gpuPim,@function
_Z16bitonic_sort_gpuPim: # @_Z16bitonic_sort_gpuPim
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %r14
movq %rsi, 24(%rsp) # 8-byte Spill
leaq (,%rsi,4), %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_Z10gpu_assert10hipError_tPKcib.exit
movq 8(%rsp), %rdi
movq %r14, 32(%rsp) # 8-byte Spill
movq %r14, %rsi
movq %rbx, 40(%rsp) # 8-byte Spill
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_4
# %bb.5: # %_Z10gpu_assert10hipError_tPKcib.exit27
movq 24(%rsp), %rsi # 8-byte Reload
movq %rsi, %rcx
shrq $10, %rcx
movabsq $4294967296, %rax # imm = 0x100000000
leaq 1(%rax), %rdx
cmpq $1024, %rsi # imm = 0x400
cmovbq %rsi, %rcx
leaq 1024(%rax), %r12
cmovbq %rdx, %r12
cmpq $2, %rsi
jae .LBB2_6
.LBB2_9: # %._crit_edge36
movq 8(%rsp), %rsi
movq 32(%rsp), %rdi # 8-byte Reload
movq 40(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_10
# %bb.11: # %_Z10gpu_assert10hipError_tPKcib.exit29
leaq 8(%rsp), %rdi
callq hipFree
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_6: # %.lr.ph35
.cfi_def_cfa_offset 192
movl %ecx, %r13d
orq %rax, %r13
movl $2, %r15d
movl $2, %ebx
leaq 112(%rsp), %rbp
jmp .LBB2_7
.p2align 4, 0x90
.LBB2_8: # %._crit_edge
# in Loop: Header=BB2_7 Depth=1
addl %r15d, %r15d
movslq %r15d, %rbx
cmpq 24(%rsp), %rbx # 8-byte Folded Reload
ja .LBB2_9
.LBB2_7: # =>This Loop Header: Depth=1
# Child Loop BB2_12 Depth 2
movl %r15d, %r14d
sarl %r14d
testl %r14d, %r14d
jg .LBB2_12
jmp .LBB2_8
.p2align 4, 0x90
.LBB2_14: # in Loop: Header=BB2_12 Depth=2
movl %r14d, %eax
shrl %eax
cmpl $2, %r14d
movl %eax, %r14d
jb .LBB2_8
.LBB2_12: # %.lr.ph
# Parent Loop BB2_7 Depth=1
# => This Inner Loop Header: Depth=2
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13: # in Loop: Header=BB2_12 Depth=2
movq 8(%rsp), %rax
movq %rax, 104(%rsp)
movl %r14d, 20(%rsp)
movq %rbx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z20bitonic_exchange_gpuPiim, %edi
movq %rbp, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_14
.LBB2_1:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $82, %r8d
jmp .LBB2_2
.LBB2_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $83, %r8d
jmp .LBB2_2
.LBB2_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $96, %r8d
.LBB2_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end2:
.size _Z16bitonic_sort_gpuPim, .Lfunc_end2-_Z16bitonic_sort_gpuPim
.cfi_endproc
# -- End function
.globl _Z16bitonic_exchangePiiim # -- Begin function _Z16bitonic_exchangePiiim
.p2align 4, 0x90
.type _Z16bitonic_exchangePiiim,@function
_Z16bitonic_exchangePiiim: # @_Z16bitonic_exchangePiiim
.cfi_startproc
# %bb.0:
testq %rcx, %rcx
je .LBB3_11
# %bb.1: # %.lr.ph.preheader
movslq %esi, %rax
leaq (%rdi,%rax,4), %rsi
movl %eax, %r8d
xorl %r9d, %r9d
jmp .LBB3_2
.LBB3_9: # in Loop: Header=BB3_2 Depth=1
movl (%rdi,%r9,4), %r10d
movl (%rsi,%r9,4), %r11d
movl %r11d, (%rdi,%r9,4)
movl %r10d, (%rsi,%r9,4)
.p2align 4, 0x90
.LBB3_10: # in Loop: Header=BB3_2 Depth=1
incq %r9
cmpq %r9, %rcx
je .LBB3_11
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leal (%r8,%r9), %r10d
andl %edx, %r10d
testl %edx, %r9d
je .LBB3_4
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
testl %r10d, %r10d
je .LBB3_10
.LBB3_4: # in Loop: Header=BB3_2 Depth=1
testl %edx, %r9d
jne .LBB3_6
# %bb.5: # in Loop: Header=BB3_2 Depth=1
testl %r10d, %r10d
jne .LBB3_10
.LBB3_6: # in Loop: Header=BB3_2 Depth=1
leaq (%rax,%r9), %r11
movl (%rdi,%r9,4), %r10d
movl %r11d, %r11d
movl (%rdi,%r11,4), %r11d
testl %edx, %r9d
je .LBB3_7
# %bb.8: # in Loop: Header=BB3_2 Depth=1
cmpl %r11d, %r10d
jl .LBB3_9
jmp .LBB3_10
.LBB3_7: # in Loop: Header=BB3_2 Depth=1
cmpl %r11d, %r10d
jg .LBB3_9
jmp .LBB3_10
.LBB3_11: # %._crit_edge
retq
.Lfunc_end3:
.size _Z16bitonic_exchangePiiim, .Lfunc_end3-_Z16bitonic_exchangePiiim
.cfi_endproc
# -- End function
.globl _Z12bitonic_sortPim # -- Begin function _Z12bitonic_sortPim
.p2align 4, 0x90
.type _Z12bitonic_sortPim,@function
_Z12bitonic_sortPim: # @_Z12bitonic_sortPim
.cfi_startproc
# %bb.0:
cmpq $2, %rsi
jae .LBB4_1
.LBB4_4: # %._crit_edge16
retq
.LBB4_1: # %.lr.ph15.preheader
movl $2, %eax
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_3: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
addl %eax, %eax
movslq %eax, %rcx
cmpq %rsi, %rcx
ja .LBB4_4
.LBB4_2: # %.lr.ph15
# =>This Loop Header: Depth=1
# Child Loop BB4_5 Depth 2
# Child Loop BB4_6 Depth 3
movl %eax, %edx
sarl %edx
testl %edx, %edx
jg .LBB4_5
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_15: # %_Z16bitonic_exchangePiiim.exit
# in Loop: Header=BB4_5 Depth=2
movl %ecx, %edx
shrl %edx
cmpl $2, %ecx
jb .LBB4_3
.LBB4_5: # %.lr.ph
# Parent Loop BB4_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_6 Depth 3
movl %edx, %ecx
leaq (%rdi,%rcx,4), %rdx
xorl %r8d, %r8d
jmp .LBB4_6
.LBB4_13: # %.sink.split
# in Loop: Header=BB4_6 Depth=3
movl (%rdx,%r8,4), %r9d
movl %r9d, (%rdi,%r8,4)
movl %r10d, (%rdx,%r8,4)
.p2align 4, 0x90
.LBB4_14: # in Loop: Header=BB4_6 Depth=3
incq %r8
cmpq %r8, %rsi
je .LBB4_15
.LBB4_6: # %.lr.ph.i
# Parent Loop BB4_2 Depth=1
# Parent Loop BB4_5 Depth=2
# => This Inner Loop Header: Depth=3
leaq (%rcx,%r8), %r9
movl %eax, %r10d
andl %r9d, %r10d
testl %r8d, %eax
je .LBB4_8
# %bb.7: # %.lr.ph.i
# in Loop: Header=BB4_6 Depth=3
testl %r10d, %r10d
je .LBB4_14
.LBB4_8: # in Loop: Header=BB4_6 Depth=3
testl %r8d, %eax
jne .LBB4_10
# %bb.9: # in Loop: Header=BB4_6 Depth=3
testl %r10d, %r10d
jne .LBB4_14
.LBB4_10: # in Loop: Header=BB4_6 Depth=3
movl (%rdi,%r8,4), %r10d
movl %r9d, %r9d
movl (%rdi,%r9,4), %r9d
testl %r8d, %eax
je .LBB4_11
# %bb.12: # in Loop: Header=BB4_6 Depth=3
cmpl %r9d, %r10d
jl .LBB4_13
jmp .LBB4_14
.LBB4_11: # in Loop: Header=BB4_6 Depth=3
cmpl %r9d, %r10d
jg .LBB4_13
jmp .LBB4_14
.Lfunc_end4:
.size _Z12bitonic_sortPim, .Lfunc_end4-_Z12bitonic_sortPim
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20bitonic_exchange_gpuPiim, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20bitonic_exchange_gpuPiim,@object # @_Z20bitonic_exchange_gpuPiim
.section .rodata,"a",@progbits
.globl _Z20bitonic_exchange_gpuPiim
.p2align 3, 0x0
_Z20bitonic_exchange_gpuPiim:
.quad _Z35__device_stub__bitonic_exchange_gpuPiim
.size _Z20bitonic_exchange_gpuPiim, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/KanashinDmitry/spbu-se2019-autumn/master/Task06/bitonic_sorts.hip"
.size .L.str, 123
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.1, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20bitonic_exchange_gpuPiim"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__bitonic_exchange_gpuPiim
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20bitonic_exchange_gpuPiim
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <fstream>
#include <iostream>
#include <iomanip>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <math.h>
using namespace std;
//Execute 1 thread per pixel of output image.
//Each thread handles all four channels of the output pixels
__global__ void encode_per_pixel_kernel(uchar4* const d_destImg,
const char* const d_binData,
int numBytesData)
{
//Get pixel index
//Theres two pixels per byte of data
//Thread 2 would be pixel 2 and working on byte 1 nibble 0
//Thread 3 would be pixel 3 and working on byte 1 nibble 1
//Thread 4 would be pixel 4 and working on byte 2 nibble 0
//Thread 5 would be pixel 5 and working on byte 2 nibble 1
int pixel = threadIdx.x + blockDim.x * blockIdx.x;
if(pixel >= 2 * numBytesData)
return;
//Calculate which nibble (0 or 1) in the byte
//and which byte (0 to numBytesData)
int byteIndex = pixel / 2;
int nibble = pixel % 2;
char dataByte = d_binData[byteIndex];
//Let's work with a local copy. We only need two global accesses this way.
uchar4 outputPixel = d_destImg[pixel];
//Channel 0 (first bit in the nibble)
int offset = (7 - 4 * nibble);
bool bit = (dataByte >> offset) & 1;
outputPixel.x = outputPixel.x & ~1 | bit;
//Channel 1 (2nd bit)
offset -= 1;
bit = (dataByte >> offset) & 1;
outputPixel.y = outputPixel.y & ~1 | bit;
//Channel 2 (3rd bit)
offset -= 1;
bit = (dataByte >> offset) & 1;
outputPixel.z = outputPixel.z & ~1 | bit;
//Channel 3 (4th bit) This is the alpha channel
offset -= 1;
bit = (dataByte >> offset) & 1;
outputPixel.w = outputPixel.w & ~1 | bit;
d_destImg[pixel] = outputPixel;
}
//1 channel per bit of data
//8 channels per byte of data
//This calls requires two global memory accesses
__global__ void encode_per_channel_kernel(uchar4* const d_destImg,
const char* const d_binData,
int numBytesData)
{
//1 thread per bit of data
//Thread 0 works on pixel 0 channel 0 byte 0 nibble 0 bit 0
//Thread 1 works on pixel 0 channel 1 byte 0 nibble 0 bit 1
//Thread 2 works on pixel 0 channel 2 byte 0 nibble 0 bit 2
//Thread 3 works on pixel 0 channel 3 byte 0 nibble 0 bit 3
//Thread 4 works on pixel 1 channel 0 byte 0 nubble 1 bit 0
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if(idx >= 8 * numBytesData)
return;
//Calculate channel (0-4) and pixel (0 - 2*numBytes - 1)
int channel = idx % 4;
int pixel = idx / 4;
//Calculate which nibble (0 or 1) in the byte
//and which byte (0 to numBytesData - 1)
int byteIndex = pixel / 2;
int nibble = pixel % 2;
char dataByte = d_binData[byteIndex];
//Let's work with a local copy.
uchar4 outputPixel = d_destImg[pixel];
//Get the bit
//Offset should be 7 for channel 0, nibble 0
//Offset should be 0 for channel 3, nibble 1
int offset = (7 - 4 * nibble) - channel;
bool bit = (dataByte >> offset) & 1;
if(channel == 0) {
outputPixel.x = outputPixel.x & ~1 | bit;
} else if(channel == 1){
outputPixel.y = outputPixel.y & ~1 | bit;
} else if(channel == 2){
outputPixel.z = outputPixel.z & ~1 | bit;
} else if(channel == 3){
outputPixel.w = outputPixel.w & ~1 | bit;
}
d_destImg[pixel] = outputPixel;
}
/**
| 10 11 12 15 ; 11 255 12 0 |
| 15 10 13 5 ; 15 14 19 80 | Original image (each set of 4 is 1 pixel).
| 12 14 16 21 ; 14 18 10 16 |
| 11 11 11 11 ; 10 10 10 10 |
and
[ 1001 0110 1111 0000 1010 0101 0100 1100] Data file
=
| 11 10 12 15 ; 10 255 13 0 |
| 15 11 13 5 ; 14 14 18 80 | Encoded image
| 13 14 17 20 ; 14 19 10 17 |
| 11 10 11 11 ; 11 11 10 10 |
To encode the data, we will use the least significant bit approach by
modifying the LSB of each channel of each pixel of th input image. The
LSB will match the corresponding bit of the input data. The data can be
decoded by reading the LSB from the encoded image.
For example, if the channel byte is 0001 1001 (value of 25) and we want to
encode a 1, the byte would remain the same. If we want to encode a 0, the
byte would become 0001 1000 (value of 24).
If the channel byte is 0010 1110 (value of 46), and we want to encode a 1,
then the byte would become 0010 1111 (value of 47). If we want to encode a
0, then the byte would remain the same.
*/
void encode_parallel(const uchar4* const h_sourceImg,
uchar4* const h_destImg,
const char* const h_binData,
int numBytesData,
const size_t numRowsSource, const size_t numColsSource)
{
//Allocate device memory
uchar4* d_destImg;
char* d_binData;
cudaMalloc(&d_destImg, sizeof(uchar4) * numRowsSource * numColsSource);
cudaMalloc(&d_binData, sizeof(char) * numBytesData);
cudaMemcpy(d_destImg, h_sourceImg, sizeof(uchar4) * numRowsSource * numColsSource, cudaMemcpyHostToDevice);
cudaMemcpy(d_binData, h_binData, numBytesData, cudaMemcpyHostToDevice);
//Each thread handles 1 pixel
//This means 1 thread per 4 bits of data (2 threads per byte)
int numThreads = numBytesData * 2.0;
int threadsPerBlock = 1024;
int numBlocks = ceil((float)numThreads / threadsPerBlock);
encode_per_pixel_kernel<<<numBlocks, threadsPerBlock>>>(d_destImg, d_binData, numBytesData);
//Each thread handles 1 channel of 1 pixel
//This means 1 thread per bit of data (8 threads per byte)
//int numThreads = numBytesData * 8;
//int threadsPerBlock = 1024;
//int numBlocks = ceil((float)numThreads / threadsPerBlock);
//encode_per_channel_kernel<<<numBlocks, threadsPerBlock>>>(d_destImg, d_binData, numBytesData);
cudaMemcpy(h_destImg, d_destImg, sizeof(uchar4) * numRowsSource * numColsSource, cudaMemcpyDeviceToHost);
//Free memory
cudaFree(d_destImg);
cudaFree(d_binData);
} | code for sm_80
Function : _Z25encode_per_channel_kernelP6uchar4PKci
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ USHF.L.U32 UR4, UR4, 0x3, URZ ; /* 0x0000000304047899 */
/* 0x000fe2000800063f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011400 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ LEA.HI R2, R3.reuse, R0.reuse, RZ, 0x3 ; /* 0x0000000003027211 */
/* 0x0c0fe400078f18ff */
/*00b0*/ LEA.HI R6, R3, R0, RZ, 0x2 ; /* 0x0000000003067211 */
/* 0x000fe400078f10ff */
/*00c0*/ SHF.R.S32.HI R5, RZ, 0x3, R2 ; /* 0x00000003ff057819 */
/* 0x000fe20000011402 */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*00e0*/ SHF.R.S32.HI R7, RZ, 0x2, R6 ; /* 0x00000002ff077819 */
/* 0x000fe40000011406 */
/*00f0*/ IADD3 R4, P0, R5, c[0x0][0x168], RZ ; /* 0x00005a0005047a10 */
/* 0x000fc60007f1e0ff */
/*0100*/ IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fe200078e0202 */
/*0110*/ LEA.HI.X.SX32 R5, R5, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0005057a11 */
/* 0x000fc800000f0eff */
/*0120*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E.S8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0000e2000c1e1300 */
/*0140*/ LEA.HI R8, R6.reuse, R7, RZ, 0x1 ; /* 0x0000000706087211 */
/* 0x040fe200078f08ff */
/*0150*/ BSSY B0, 0x3c0 ; /* 0x0000026000007945 */
/* 0x000fe20003800000 */
/*0160*/ LOP3.LUT R9, R6, 0xfffffffc, RZ, 0xc0, !PT ; /* 0xfffffffc06097812 */
/* 0x000fe400078ec0ff */
/*0170*/ LOP3.LUT R8, R8, 0x3ffffffe, RZ, 0xc0, !PT ; /* 0x3ffffffe08087812 */
/* 0x000fc600078ec0ff */
/*0180*/ IMAD.IADD R9, R0, 0x1, -R9 ; /* 0x0000000100097824 */
/* 0x000fe400078e0a09 */
/*0190*/ IMAD.IADD R8, R7, 0x1, -R8 ; /* 0x0000000107087824 */
/* 0x000fe400078e0a08 */
/*01a0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*01b0*/ IADD3 R7, -R9.reuse, 0x7, RZ ; /* 0x0000000709077810 */
/* 0x040fe40007ffe1ff */
/*01c0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc60003f05270 */
/*01d0*/ IMAD R7, R8, -0x4, R7 ; /* 0xfffffffc08077824 */
/* 0x000fca00078e0207 */
/*01e0*/ SHF.L.U32 R7, R0, R7, RZ ; /* 0x0000000700077219 */
/* 0x000fe400000006ff */
/*01f0*/ PRMT R0, R10.reuse, 0x7770, RZ ; /* 0x000077700a007816 */
/* 0x044fe400000000ff */
/*0200*/ PRMT R5, R10.reuse, 0x7772, RZ ; /* 0x000077720a057816 */
/* 0x041fe400000000ff */
/*0210*/ LOP3.LUT R7, R7, R4, RZ, 0xc0, !PT ; /* 0x0000000407077212 */
/* 0x008fe400078ec0ff */
/*0220*/ PRMT R4, R10.reuse, 0x7771, RZ ; /* 0x000077710a047816 */
/* 0x040fe400000000ff */
/*0230*/ PRMT R6, R10, 0x7773, RZ ; /* 0x000077730a067816 */
/* 0x000fc400000000ff */
/*0240*/ PRMT R11, R4, 0x7610, R11 ; /* 0x00007610040b7816 */
/* 0x000fe2000000000b */
/*0250*/ @!P0 BRA 0x380 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0260*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f05270 */
/*0270*/ @!P0 BRA 0x340 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0280*/ ISETP.NE.AND P0, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x000fda0003f05270 */
/*0290*/ @!P0 BRA 0x300 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*02a0*/ ISETP.NE.AND P0, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fda0003f05270 */
/*02b0*/ @P0 BRA 0x3b0 ; /* 0x000000f000000947 */
/* 0x000fea0003800000 */
/*02c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05270 */
/*02d0*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc80004000000 */
/*02e0*/ LOP3.LUT R6, R7, 0xfffe, R6, 0xf8, !PT ; /* 0x0000fffe07067812 */
/* 0x000fe200078ef806 */
/*02f0*/ BRA 0x3b0 ; /* 0x000000b000007947 */
/* 0x000fea0003800000 */
/*0300*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05270 */
/*0310*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0320*/ LOP3.LUT R5, R4, 0xfffe, R5, 0xf8, !PT ; /* 0x0000fffe04057812 */
/* 0x000fe200078ef805 */
/*0330*/ BRA 0x3b0 ; /* 0x0000007000007947 */
/* 0x000fea0003800000 */
/*0340*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05270 */
/*0350*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0360*/ LOP3.LUT R11, R4, 0xfffe, R11, 0xf8, !PT ; /* 0x0000fffe040b7812 */
/* 0x000fe200078ef80b */
/*0370*/ BRA 0x3b0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0380*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05270 */
/*0390*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc80004000000 */
/*03a0*/ LOP3.LUT R0, R7, 0xfffe, R0, 0xf8, !PT ; /* 0x0000fffe07007812 */
/* 0x000fe400078ef800 */
/*03b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03c0*/ PRMT R0, R11, 0x7604, R0 ; /* 0x000076040b007816 */
/* 0x000fc80000000000 */
/*03d0*/ PRMT R5, R5, 0x7054, R0 ; /* 0x0000705405057816 */
/* 0x000fc80000000000 */
/*03e0*/ PRMT R5, R6, 0x654, R5 ; /* 0x0000065406057816 */
/* 0x000fca0000000005 */
/*03f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0400*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0410*/ BRA 0x410; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z23encode_per_pixel_kernelP6uchar4PKci
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fe2000800063f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ LEA.HI R6, R0, R0, RZ, 0x1 ; /* 0x0000000000067211 */
/* 0x000fe200078f08ff */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ SHF.R.S32.HI R2, RZ, 0x1, R6 ; /* 0x00000001ff027819 */
/* 0x000fc80000011406 */
/*00c0*/ IADD3 R4, P0, R2, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ LEA.HI.X.SX32 R5, R2, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0002057a11 */
/* 0x000fe200000f0eff */
/*00e0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0203 */
/*00f0*/ LDG.E.S8 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x0000a8000c1e1300 */
/*0100*/ LDG.E R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x000ee2000c1e1900 */
/*0110*/ LOP3.LUT R7, R6, 0x3ffffffe, RZ, 0xc0, !PT ; /* 0x3ffffffe06077812 */
/* 0x000fe200078ec0ff */
/*0120*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fc800078e00ff */
/*0130*/ IMAD.IADD R7, R0, 0x1, -R7 ; /* 0x0000000100077824 */
/* 0x000fe400078e0a07 */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, -0x4 ; /* 0xfffffffcff007424 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD R7, R7, R0, 0x7 ; /* 0x0000000707077424 */
/* 0x000fca00078e0200 */
/*0160*/ IADD3 R0, R7.reuse, -0x1, RZ ; /* 0xffffffff07007810 */
/* 0x040fe40007ffe0ff */
/*0170*/ IADD3 R6, R7.reuse, -0x2, RZ ; /* 0xfffffffe07067810 */
/* 0x040fe40007ffe0ff */
/*0180*/ IADD3 R10, R7, -0x3, RZ ; /* 0xfffffffd070a7810 */
/* 0x000fe40007ffe0ff */
/*0190*/ SHF.L.U32 R7, R11.reuse, R7, RZ ; /* 0x000000070b077219 */
/* 0x040fe400000006ff */
/*01a0*/ SHF.L.U32 R5, R11.reuse, R0, RZ ; /* 0x000000000b057219 */
/* 0x041fe400000006ff */
/*01b0*/ SHF.L.U32 R9, R11, R6, RZ ; /* 0x000000060b097219 */
/* 0x000fc400000006ff */
/*01c0*/ SHF.L.U32 R11, R11, R10, RZ ; /* 0x0000000a0b0b7219 */
/* 0x000fe400000006ff */
/*01d0*/ LOP3.LUT P0, RZ, R7, R8.reuse, RZ, 0xc0, !PT ; /* 0x0000000807ff7212 */
/* 0x084fe4000780c0ff */
/*01e0*/ LOP3.LUT P1, RZ, R5, R8.reuse, RZ, 0xc0, !PT ; /* 0x0000000805ff7212 */
/* 0x080fe4000782c0ff */
/*01f0*/ LOP3.LUT P2, RZ, R9, R8, RZ, 0xc0, !PT ; /* 0x0000000809ff7212 */
/* 0x000fe4000784c0ff */
/*0200*/ PRMT R0, R12.reuse, 0x7770, RZ ; /* 0x000077700c007816 */
/* 0x048fe400000000ff */
/*0210*/ PRMT R4, R12, 0x7771, RZ ; /* 0x000077710c047816 */
/* 0x000fc400000000ff */
/*0220*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fe40004000000 */
/*0230*/ SEL R9, RZ, 0x1, !P1 ; /* 0x00000001ff097807 */
/* 0x000fe40004800000 */
/*0240*/ PRMT R5, R12, 0x7772, RZ ; /* 0x000077720c057816 */
/* 0x000fe400000000ff */
/*0250*/ SEL R6, RZ, 0x1, !P2 ; /* 0x00000001ff067807 */
/* 0x000fe40005000000 */
/*0260*/ LOP3.LUT P0, RZ, R11, R8, RZ, 0xc0, !PT ; /* 0x000000080bff7212 */
/* 0x000fe4000780c0ff */
/*0270*/ LOP3.LUT R7, R7, 0xfffe, R0, 0xf8, !PT ; /* 0x0000fffe07077812 */
/* 0x000fc400078ef800 */
/*0280*/ LOP3.LUT R4, R9, 0xfffe, R4, 0xf8, !PT ; /* 0x0000fffe09047812 */
/* 0x000fe400078ef804 */
/*0290*/ LOP3.LUT R6, R6, 0xfffe, R5, 0xf8, !PT ; /* 0x0000fffe06067812 */
/* 0x000fe400078ef805 */
/*02a0*/ PRMT R0, R12, 0x7773, RZ ; /* 0x000077730c007816 */
/* 0x000fe400000000ff */
/*02b0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fe40004000000 */
/*02c0*/ PRMT R7, R4, 0x7604, R7 ; /* 0x0000760404077816 */
/* 0x000fe40000000007 */
/*02d0*/ LOP3.LUT R0, R5, 0xfffe, R0, 0xf8, !PT ; /* 0x0000fffe05007812 */
/* 0x000fc400078ef800 */
/*02e0*/ PRMT R7, R6, 0x7054, R7 ; /* 0x0000705406077816 */
/* 0x000fc80000000007 */
/*02f0*/ PRMT R7, R0, 0x654, R7 ; /* 0x0000065400077816 */
/* 0x000fca0000000007 */
/*0300*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <fstream>
#include <iostream>
#include <iomanip>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <math.h>
using namespace std;
//Execute 1 thread per pixel of output image.
//Each thread handles all four channels of the output pixels
__global__ void encode_per_pixel_kernel(uchar4* const d_destImg,
const char* const d_binData,
int numBytesData)
{
//Get pixel index
//Theres two pixels per byte of data
//Thread 2 would be pixel 2 and working on byte 1 nibble 0
//Thread 3 would be pixel 3 and working on byte 1 nibble 1
//Thread 4 would be pixel 4 and working on byte 2 nibble 0
//Thread 5 would be pixel 5 and working on byte 2 nibble 1
int pixel = threadIdx.x + blockDim.x * blockIdx.x;
if(pixel >= 2 * numBytesData)
return;
//Calculate which nibble (0 or 1) in the byte
//and which byte (0 to numBytesData)
int byteIndex = pixel / 2;
int nibble = pixel % 2;
char dataByte = d_binData[byteIndex];
//Let's work with a local copy. We only need two global accesses this way.
uchar4 outputPixel = d_destImg[pixel];
//Channel 0 (first bit in the nibble)
int offset = (7 - 4 * nibble);
bool bit = (dataByte >> offset) & 1;
outputPixel.x = outputPixel.x & ~1 | bit;
//Channel 1 (2nd bit)
offset -= 1;
bit = (dataByte >> offset) & 1;
outputPixel.y = outputPixel.y & ~1 | bit;
//Channel 2 (3rd bit)
offset -= 1;
bit = (dataByte >> offset) & 1;
outputPixel.z = outputPixel.z & ~1 | bit;
//Channel 3 (4th bit) This is the alpha channel
offset -= 1;
bit = (dataByte >> offset) & 1;
outputPixel.w = outputPixel.w & ~1 | bit;
d_destImg[pixel] = outputPixel;
}
//1 channel per bit of data
//8 channels per byte of data
//This calls requires two global memory accesses
__global__ void encode_per_channel_kernel(uchar4* const d_destImg,
const char* const d_binData,
int numBytesData)
{
//1 thread per bit of data
//Thread 0 works on pixel 0 channel 0 byte 0 nibble 0 bit 0
//Thread 1 works on pixel 0 channel 1 byte 0 nibble 0 bit 1
//Thread 2 works on pixel 0 channel 2 byte 0 nibble 0 bit 2
//Thread 3 works on pixel 0 channel 3 byte 0 nibble 0 bit 3
//Thread 4 works on pixel 1 channel 0 byte 0 nubble 1 bit 0
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if(idx >= 8 * numBytesData)
return;
//Calculate channel (0-4) and pixel (0 - 2*numBytes - 1)
int channel = idx % 4;
int pixel = idx / 4;
//Calculate which nibble (0 or 1) in the byte
//and which byte (0 to numBytesData - 1)
int byteIndex = pixel / 2;
int nibble = pixel % 2;
char dataByte = d_binData[byteIndex];
//Let's work with a local copy.
uchar4 outputPixel = d_destImg[pixel];
//Get the bit
//Offset should be 7 for channel 0, nibble 0
//Offset should be 0 for channel 3, nibble 1
int offset = (7 - 4 * nibble) - channel;
bool bit = (dataByte >> offset) & 1;
if(channel == 0) {
outputPixel.x = outputPixel.x & ~1 | bit;
} else if(channel == 1){
outputPixel.y = outputPixel.y & ~1 | bit;
} else if(channel == 2){
outputPixel.z = outputPixel.z & ~1 | bit;
} else if(channel == 3){
outputPixel.w = outputPixel.w & ~1 | bit;
}
d_destImg[pixel] = outputPixel;
}
/**
| 10 11 12 15 ; 11 255 12 0 |
| 15 10 13 5 ; 15 14 19 80 | Original image (each set of 4 is 1 pixel).
| 12 14 16 21 ; 14 18 10 16 |
| 11 11 11 11 ; 10 10 10 10 |
and
[ 1001 0110 1111 0000 1010 0101 0100 1100] Data file
=
| 11 10 12 15 ; 10 255 13 0 |
| 15 11 13 5 ; 14 14 18 80 | Encoded image
| 13 14 17 20 ; 14 19 10 17 |
| 11 10 11 11 ; 11 11 10 10 |
To encode the data, we will use the least significant bit approach by
modifying the LSB of each channel of each pixel of th input image. The
LSB will match the corresponding bit of the input data. The data can be
decoded by reading the LSB from the encoded image.
For example, if the channel byte is 0001 1001 (value of 25) and we want to
encode a 1, the byte would remain the same. If we want to encode a 0, the
byte would become 0001 1000 (value of 24).
If the channel byte is 0010 1110 (value of 46), and we want to encode a 1,
then the byte would become 0010 1111 (value of 47). If we want to encode a
0, then the byte would remain the same.
*/
void encode_parallel(const uchar4* const h_sourceImg,
uchar4* const h_destImg,
const char* const h_binData,
int numBytesData,
const size_t numRowsSource, const size_t numColsSource)
{
//Allocate device memory
uchar4* d_destImg;
char* d_binData;
cudaMalloc(&d_destImg, sizeof(uchar4) * numRowsSource * numColsSource);
cudaMalloc(&d_binData, sizeof(char) * numBytesData);
cudaMemcpy(d_destImg, h_sourceImg, sizeof(uchar4) * numRowsSource * numColsSource, cudaMemcpyHostToDevice);
cudaMemcpy(d_binData, h_binData, numBytesData, cudaMemcpyHostToDevice);
//Each thread handles 1 pixel
//This means 1 thread per 4 bits of data (2 threads per byte)
int numThreads = numBytesData * 2.0;
int threadsPerBlock = 1024;
int numBlocks = ceil((float)numThreads / threadsPerBlock);
encode_per_pixel_kernel<<<numBlocks, threadsPerBlock>>>(d_destImg, d_binData, numBytesData);
//Each thread handles 1 channel of 1 pixel
//This means 1 thread per bit of data (8 threads per byte)
//int numThreads = numBytesData * 8;
//int threadsPerBlock = 1024;
//int numBlocks = ceil((float)numThreads / threadsPerBlock);
//encode_per_channel_kernel<<<numBlocks, threadsPerBlock>>>(d_destImg, d_binData, numBytesData);
cudaMemcpy(h_destImg, d_destImg, sizeof(uchar4) * numRowsSource * numColsSource, cudaMemcpyDeviceToHost);
//Free memory
cudaFree(d_destImg);
cudaFree(d_binData);
} | .file "tmpxft_001a59bf_00000000-6_encode.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4042:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4042:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z23encode_per_pixel_kernelP6uchar4PKciP6uchar4PKci
.type _Z53__device_stub__Z23encode_per_pixel_kernelP6uchar4PKciP6uchar4PKci, @function
_Z53__device_stub__Z23encode_per_pixel_kernelP6uchar4PKciP6uchar4PKci:
.LFB4064:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23encode_per_pixel_kernelP6uchar4PKci(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4064:
.size _Z53__device_stub__Z23encode_per_pixel_kernelP6uchar4PKciP6uchar4PKci, .-_Z53__device_stub__Z23encode_per_pixel_kernelP6uchar4PKciP6uchar4PKci
.globl _Z23encode_per_pixel_kernelP6uchar4PKci
.type _Z23encode_per_pixel_kernelP6uchar4PKci, @function
_Z23encode_per_pixel_kernelP6uchar4PKci:
.LFB4065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z23encode_per_pixel_kernelP6uchar4PKciP6uchar4PKci
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4065:
.size _Z23encode_per_pixel_kernelP6uchar4PKci, .-_Z23encode_per_pixel_kernelP6uchar4PKci
.globl _Z15encode_parallelPK6uchar4PS_PKcimm
.type _Z15encode_parallelPK6uchar4PS_PKcimm, @function
_Z15encode_parallelPK6uchar4PS_PKcimm:
.LFB4039:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
imulq %r9, %r8
leaq 0(,%r8,4), %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movslq %ebp, %r15
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
addsd %xmm0, %xmm0
cvttsd2sil %xmm0, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC4(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L12
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L12:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
cvttss2sil %xmm3, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
movl $2, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %ebp, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z53__device_stub__Z23encode_per_pixel_kernelP6uchar4PKciP6uchar4PKci
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4039:
.size _Z15encode_parallelPK6uchar4PS_PKcimm, .-_Z15encode_parallelPK6uchar4PS_PKcimm
.globl _Z55__device_stub__Z25encode_per_channel_kernelP6uchar4PKciP6uchar4PKci
.type _Z55__device_stub__Z25encode_per_channel_kernelP6uchar4PKciP6uchar4PKci, @function
_Z55__device_stub__Z25encode_per_channel_kernelP6uchar4PKciP6uchar4PKci:
.LFB4066:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25encode_per_channel_kernelP6uchar4PKci(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4066:
.size _Z55__device_stub__Z25encode_per_channel_kernelP6uchar4PKciP6uchar4PKci, .-_Z55__device_stub__Z25encode_per_channel_kernelP6uchar4PKciP6uchar4PKci
.globl _Z25encode_per_channel_kernelP6uchar4PKci
.type _Z25encode_per_channel_kernelP6uchar4PKci, @function
_Z25encode_per_channel_kernelP6uchar4PKci:
.LFB4067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z25encode_per_channel_kernelP6uchar4PKciP6uchar4PKci
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4067:
.size _Z25encode_per_channel_kernelP6uchar4PKci, .-_Z25encode_per_channel_kernelP6uchar4PKci
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z25encode_per_channel_kernelP6uchar4PKci"
.align 8
.LC6:
.string "_Z23encode_per_pixel_kernelP6uchar4PKci"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4069:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z25encode_per_channel_kernelP6uchar4PKci(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z23encode_per_pixel_kernelP6uchar4PKci(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4069:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 981467136
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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