system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "myqueue.cuh"
#include <iostream>
using namespace std;
template<class T>
MyQueue<T>::MyQueue() : frontPtr(NULL), backPtr(NULL), count(0)
{
}
template<class T>
__device__ __host__ bool MyQueue<T>::isEmpty() {
return(count == 0);
}
template<class T>
__device__ __host__ void MyQueue<T>::push(T data) {
Node *newOne = new Node;
newOne->date = data;
newOne->next = NULL;
if (isEmpty()) {
frontPtr = newOne;
}
else {
backPtr->next = newOne;
}
backPtr = newOne;
count++;
}
template<class T>
__device__ __host__ T MyQueue<T>::pop() {
if (isEmpty()) {
printf("Nothing inside\n");
}
else {
Node *temp = frontPtr;
T tr = temp->data;
if (frontPtr == backPtr) {
frontPtr = NULL;
backPtr = NULL;
}
else {
frontPtr = frontPtr->next;
}
delete temp;
count--;
return tr;
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "myqueue.cuh"
#include <iostream>
using namespace std;
template<class T>
MyQueue<T>::MyQueue() : frontPtr(NULL), backPtr(NULL), count(0)
{
}
template<class T>
__device__ __host__ bool MyQueue<T>::isEmpty() {
return(count == 0);
}
template<class T>
__device__ __host__ void MyQueue<T>::push(T data) {
Node *newOne = new Node;
newOne->date = data;
newOne->next = NULL;
if (isEmpty()) {
frontPtr = newOne;
}
else {
backPtr->next = newOne;
}
backPtr = newOne;
count++;
}
template<class T>
__device__ __host__ T MyQueue<T>::pop() {
if (isEmpty()) {
printf("Nothing inside\n");
}
else {
Node *temp = frontPtr;
T tr = temp->data;
if (frontPtr == backPtr) {
frontPtr = NULL;
backPtr = NULL;
}
else {
frontPtr = frontPtr->next;
}
delete temp;
count--;
return tr;
}
} | .file "tmpxft_0012290b_00000000-6_myqueue.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "myqueue.cuh"
#include <iostream>
using namespace std;
template<class T>
MyQueue<T>::MyQueue() : frontPtr(NULL), backPtr(NULL), count(0)
{
}
template<class T>
__device__ __host__ bool MyQueue<T>::isEmpty() {
return(count == 0);
}
template<class T>
__device__ __host__ void MyQueue<T>::push(T data) {
Node *newOne = new Node;
newOne->date = data;
newOne->next = NULL;
if (isEmpty()) {
frontPtr = newOne;
}
else {
backPtr->next = newOne;
}
backPtr = newOne;
count++;
}
template<class T>
__device__ __host__ T MyQueue<T>::pop() {
if (isEmpty()) {
printf("Nothing inside\n");
}
else {
Node *temp = frontPtr;
T tr = temp->data;
if (frontPtr == backPtr) {
frontPtr = NULL;
backPtr = NULL;
}
else {
frontPtr = frontPtr->next;
}
delete temp;
count--;
return tr;
}
} | #ifndef MYQUEUE_H
#define MYQUEUE_H
#include <cstddef>
template<class T>
class MyQueue
{
public:
MyQueue();
__device__ __host__ bool isEmpty();
__device__ __host__ void push(T data);
__device__ __host__ T pop();
private:
struct Node {
T date;
Node *next;
};
Node *frontPtr;
Node *backPtr;
int count;
};
#endif // MYQUEUE_H |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef MYQUEUE_H
#define MYQUEUE_H
#include <cstddef>
template<class T>
class MyQueue
{
public:
MyQueue();
__device__ __host__ bool isEmpty();
__device__ __host__ void push(T data);
__device__ __host__ T pop();
private:
struct Node {
T date;
Node *next;
};
Node *frontPtr;
Node *backPtr;
int count;
};
#endif // MYQUEUE_H | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef MYQUEUE_H
#define MYQUEUE_H
#include <cstddef>
template<class T>
class MyQueue
{
public:
MyQueue();
__device__ __host__ bool isEmpty();
__device__ __host__ void push(T data);
__device__ __host__ T pop();
private:
struct Node {
T date;
Node *next;
};
Node *frontPtr;
Node *backPtr;
int count;
};
#endif // MYQUEUE_H | .text
.file "myqueue.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012290b_00000000-6_myqueue.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "myqueue.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void kring_Az(double *x, double *y, double *z, double xMax, double yMax, double zMax, double omegaX, double omegaY, double omegaZ, double omega, double fudge, double *A){
int gid = getGid3d3d();
int xid = blockDim.x*blockIdx.x + threadIdx.x;
int yid = blockDim.y*blockIdx.y + threadIdx.y;
double rad = sqrt(x[xid]*x[xid] + y[yid]*y[yid]);
A[gid] = omega * exp(-rad*rad / (0.0001*xMax)) * 0.01;
} | code for sm_80
Function : _Z8kring_AzPdS_S_ddddddddS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R6, SR_TID.Y ; /* 0x0000000000067919 */
/* 0x000e280000002200 */
/*0050*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e680000002500 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0070*/ IMAD R12, R7, c[0x0][0x4], R6 ; /* 0x00000100070c7a24 */
/* 0x001fc800078e0206 */
/*0080*/ IMAD.WIDE R12, R12, R11, c[0x0][0x168] ; /* 0x00005a000c0c7625 */
/* 0x000fc800078e020b */
/*0090*/ IMAD R10, R9, c[0x0][0x0], R0 ; /* 0x00000000090a7a24 */
/* 0x002fe400078e0200 */
/*00a0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea4000c1e1b00 */
/*00b0*/ IMAD.WIDE R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fcc00078e020b */
/*00c0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee2000c1e1b00 */
/*00d0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x0 ; /* 0x00000000ff107424 */
/* 0x000fe200078e00ff */
/*00e0*/ BSSY B0, 0x2a0 ; /* 0x000001b000007945 */
/* 0x000fe20003800000 */
/*00f0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff117424 */
/* 0x000fe200078e00ff */
/*0100*/ S2R R8, SR_CTAID.Z ; /* 0x0000000000087919 */
/* 0x000e280000002700 */
/*0110*/ S2R R19, SR_TID.Z ; /* 0x0000000000137919 */
/* 0x000e620000002300 */
/*0120*/ IMAD R8, R8, c[0x0][0x10], R7 ; /* 0x0000040008087a24 */
/* 0x001fc800078e0207 */
/*0130*/ IMAD R8, R8, c[0x0][0xc], R9 ; /* 0x0000030008087a24 */
/* 0x000fc800078e0209 */
/*0140*/ IMAD R7, R8, c[0x0][0x8], R19 ; /* 0x0000020008077a24 */
/* 0x002fc800078e0213 */
/*0150*/ IMAD R7, R7, c[0x0][0x4], R6 ; /* 0x0000010007077a24 */
/* 0x000fc800078e0206 */
/*0160*/ IMAD R0, R7, c[0x0][0x0], R0 ; /* 0x0000000007007a24 */
/* 0x000fe200078e0200 */
/*0170*/ DMUL R2, R12, R12 ; /* 0x0000000c0c027228 */
/* 0x004ecc0000000000 */
/*0180*/ DFMA R2, R10, R10, R2 ; /* 0x0000000a0a02722b */
/* 0x008e0c0000000002 */
/*0190*/ MUFU.RSQ64H R5, R3 ; /* 0x0000000300057308 */
/* 0x001e280000001c00 */
/*01a0*/ IADD3 R4, R3, -0x3500000, RZ ; /* 0xfcb0000003047810 */
/* 0x000fc80007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R4, 0x7ca00000, PT ; /* 0x7ca000000400780c */
/* 0x000fe40003f06070 */
/*01c0*/ DMUL R14, R4, R4 ; /* 0x00000004040e7228 */
/* 0x001e0c0000000000 */
/*01d0*/ DFMA R14, R2, -R14, 1 ; /* 0x3ff00000020e742b */
/* 0x001e0c000000080e */
/*01e0*/ DFMA R12, R14, R16, 0.5 ; /* 0x3fe000000e0c742b */
/* 0x001fc80000000010 */
/*01f0*/ DMUL R14, R4, R14 ; /* 0x0000000e040e7228 */
/* 0x000e0c0000000000 */
/*0200*/ DFMA R12, R12, R14, R4 ; /* 0x0000000e0c0c722b */
/* 0x001e0c0000000004 */
/*0210*/ DMUL R10, R2, R12 ; /* 0x0000000c020a7228 */
/* 0x001e080000000000 */
/*0220*/ IADD3 R17, R13, -0x100000, RZ ; /* 0xfff000000d117810 */
/* 0x000fe20007ffe0ff */
/*0230*/ IMAD.MOV.U32 R16, RZ, RZ, R12 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000c */
/*0240*/ DFMA R14, R10, -R10, R2 ; /* 0x8000000a0a0e722b */
/* 0x001e0c0000000002 */
/*0250*/ DFMA R8, R14, R16, R10 ; /* 0x000000100e08722b */
/* 0x001062000000000a */
/*0260*/ @!P0 BRA 0x290 ; /* 0x0000002000008947 */
/* 0x000fea0003800000 */
/*0270*/ MOV R6, 0x290 ; /* 0x0000029000067802 */
/* 0x000fca0000000f00 */
/*0280*/ CALL.REL.NOINC 0xcb0 ; /* 0x00000a2000007944 */
/* 0x003fea0003c00000 */
/*0290*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff067624 */
/* 0x000fe200078e00ff */
/*02b0*/ DMUL R12, R8, R8 ; /* 0x00000008080c7228 */
/* 0x002e620000000000 */
/*02c0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff077624 */
/* 0x000fe200078e00ff */
/*02d0*/ BSSY B0, 0x400 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*02e0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x001fc800078e00ff */
/*02f0*/ DMUL R6, R6, c[0x2][0x0] ; /* 0x0080000006067a28 */
/* 0x000e060000000000 */
/*0300*/ FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ; /* 0x036000000d00780b */
/* 0x002fc60003f2e200 */
/*0310*/ MUFU.RCP64H R3, R7 ; /* 0x0000000700037308 */
/* 0x001e240000001800 */
/*0320*/ DFMA R4, -R6, R2, 1 ; /* 0x3ff000000604742b */
/* 0x001e0c0000000102 */
/*0330*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x001e0c0000000004 */
/*0340*/ DFMA R4, R2, R4, R2 ; /* 0x000000040204722b */
/* 0x001e0c0000000002 */
/*0350*/ DFMA R2, -R6, R4, 1 ; /* 0x3ff000000602742b */
/* 0x001e0c0000000104 */
/*0360*/ DFMA R2, R4, R2, R4 ; /* 0x000000020402722b */
/* 0x001e0c0000000004 */
/*0370*/ DMUL R4, R12, R2 ; /* 0x000000020c047228 */
/* 0x001e0c0000000000 */
/*0380*/ DFMA R8, -R6, R4, R12 ; /* 0x000000040608722b */
/* 0x001e0c000000010c */
/*0390*/ DFMA R2, R2, R8, R4 ; /* 0x000000080202722b */
/* 0x001e140000000004 */
/*03a0*/ FFMA R4, RZ, R7, R3 ; /* 0x00000007ff047223 */
/* 0x001fca0000000003 */
/*03b0*/ FSETP.GT.AND P0, PT, |R4|, 1.469367938527859385e-39, PT ; /* 0x001000000400780b */
/* 0x000fda0003f04200 */
/*03c0*/ @P0 BRA P1, 0x3f0 ; /* 0x0000002000000947 */
/* 0x000fea0000800000 */
/*03d0*/ MOV R10, 0x3f0 ; /* 0x000003f0000a7802 */
/* 0x000fe40000000f00 */
/*03e0*/ CALL.REL.NOINC 0x6c0 ; /* 0x000002d000007944 */
/* 0x000fea0003c00000 */
/*03f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0400*/ IMAD.MOV.U32 R4, RZ, RZ, 0x652b82fe ; /* 0x652b82feff047424 */
/* 0x000fe200078e00ff */
/*0410*/ FSETP.GEU.AND P0, PT, |R3|, 4.1917929649353027344, PT ; /* 0x4086232b0300780b */
/* 0x000fe20003f0e200 */
/*0420*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff057424 */
/* 0x000fe200078e00ff */
/*0430*/ BSSY B0, 0x660 ; /* 0x0000022000007945 */
/* 0x000fe20003800000 */
/*0440*/ IMAD.MOV.U32 R10, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff0a7424 */
/* 0x000fe400078e00ff */
/*0450*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff0b7424 */
/* 0x000fe400078e00ff */
/*0460*/ DFMA R4, R2, R4, 6.75539944105574400000e+15 ; /* 0x433800000204742b */
/* 0x000e8c0000000004 */
/*0470*/ DADD R6, R4, -6.75539944105574400000e+15 ; /* 0xc338000004067429 */
/* 0x004e8c0000000000 */
/*0480*/ DFMA R8, R6, c[0x2][0x8], R2 ; /* 0x0080020006087a2b */
/* 0x004e8c0000000002 */
/*0490*/ DFMA R6, R6, c[0x2][0x10], R8 ; /* 0x0080040006067a2b */
/* 0x004e8c0000000008 */
/*04a0*/ DFMA R8, R6, R10, c[0x2][0x18] ; /* 0x008006000608762b */
/* 0x004e8c000000000a */
/*04b0*/ DFMA R8, R6, R8, c[0x2][0x20] ; /* 0x008008000608762b */
/* 0x004e8c0000000008 */
/*04c0*/ DFMA R8, R6, R8, c[0x2][0x28] ; /* 0x00800a000608762b */
/* 0x004e8c0000000008 */
/*04d0*/ DFMA R8, R6, R8, c[0x2][0x30] ; /* 0x00800c000608762b */
/* 0x004e8c0000000008 */
/*04e0*/ DFMA R8, R6, R8, c[0x2][0x38] ; /* 0x00800e000608762b */
/* 0x004e8c0000000008 */
/*04f0*/ DFMA R8, R6, R8, c[0x2][0x40] ; /* 0x008010000608762b */
/* 0x004e8c0000000008 */
/*0500*/ DFMA R8, R6, R8, c[0x2][0x48] ; /* 0x008012000608762b */
/* 0x004e8c0000000008 */
/*0510*/ DFMA R8, R6, R8, c[0x2][0x50] ; /* 0x008014000608762b */
/* 0x004e8c0000000008 */
/*0520*/ DFMA R8, R6, R8, c[0x2][0x58] ; /* 0x008016000608762b */
/* 0x004e8c0000000008 */
/*0530*/ DFMA R8, R6, R8, 1 ; /* 0x3ff000000608742b */
/* 0x004e8c0000000008 */
/*0540*/ DFMA R8, R6, R8, 1 ; /* 0x3ff000000608742b */
/* 0x004e940000000008 */
/*0550*/ IMAD R7, R4, 0x100000, R9 ; /* 0x0010000004077824 */
/* 0x004fe400078e0209 */
/*0560*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0008 */
/*0570*/ @!P0 BRA 0x650 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0580*/ FSETP.GEU.AND P1, PT, |R3|, 4.2275390625, PT ; /* 0x408748000300780b */
/* 0x000fe20003f2e200 */
/*0590*/ DADD R6, R2, +INF ; /* 0x7ff0000002067429 */
/* 0x000fc80000000000 */
/*05a0*/ DSETP.GEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200722a */
/* 0x000e8c0003f0e000 */
/*05b0*/ FSEL R6, R6, RZ, P0 ; /* 0x000000ff06067208 */
/* 0x004fe40000000000 */
/*05c0*/ @!P1 LEA.HI R5, R4, R4, RZ, 0x1 ; /* 0x0000000404059211 */
/* 0x000fe200078f08ff */
/*05d0*/ @!P1 IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff029224 */
/* 0x000fe200078e0008 */
/*05e0*/ FSEL R7, R7, RZ, P0 ; /* 0x000000ff07077208 */
/* 0x000fe40000000000 */
/*05f0*/ @!P1 SHF.R.S32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff059819 */
/* 0x000fca0000011405 */
/*0600*/ @!P1 IMAD.IADD R4, R4, 0x1, -R5 ; /* 0x0000000104049824 */
/* 0x000fe400078e0a05 */
/*0610*/ @!P1 IMAD R3, R5, 0x100000, R9 ; /* 0x0010000005039824 */
/* 0x000fc600078e0209 */
/*0620*/ @!P1 LEA R5, R4, 0x3ff00000, 0x14 ; /* 0x3ff0000004059811 */
/* 0x000fe200078ea0ff */
/*0630*/ @!P1 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff049224 */
/* 0x000fcc00078e00ff */
/*0640*/ @!P1 DMUL R6, R2, R4 ; /* 0x0000000402069228 */
/* 0x0004cc0000000000 */
/*0650*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0660*/ DMUL R6, R6, c[0x0][0x1a8] ; /* 0x00006a0006067a28 */
/* 0x008ee20000000000 */
/*0670*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x004fc800078e00ff */
/*0680*/ IMAD.WIDE R2, R0, R3, c[0x0][0x1b8] ; /* 0x00006e0000027625 */
/* 0x000fe200078e0203 */
/*0690*/ DMUL R6, R6, c[0x2][0x60] ; /* 0x0080180006067a28 */
/* 0x008e8e0000000000 */
/*06a0*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x004fe2000c101b04 */
/*06b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06c0*/ FSETP.GEU.AND P0, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f0e200 */
/*06d0*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000d */
/*06e0*/ LOP3.LUT R4, R7.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff07047812 */
/* 0x040fe200078ec0ff */
/*06f0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000c */
/*0700*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fe200078ec0ff */
/*0710*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0c7424 */
/* 0x000fe200078e00ff */
/*0720*/ FSETP.GEU.AND P2, PT, |R3|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000300780b */
/* 0x040fe20003f4e200 */
/*0730*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*0740*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0750*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0006 */
/*0760*/ LOP3.LUT R11, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000030b7812 */
/* 0x000fe200078ec0ff */
/*0770*/ BSSY B1, 0xc70 ; /* 0x000004f000017945 */
/* 0x000fe40003800000 */
/*0780*/ @!P0 DMUL R4, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006048828 */
/* 0x000e220000000000 */
/*0790*/ ISETP.GE.U32.AND P1, PT, R11, R16, PT ; /* 0x000000100b00720c */
/* 0x000fe20003f26070 */
/*07a0*/ IMAD.MOV.U32 R17, RZ, RZ, R11 ; /* 0x000000ffff117224 */
/* 0x000fc600078e000b */
/*07b0*/ SEL R9, R12.reuse, 0x63400000, !P1 ; /* 0x634000000c097807 */
/* 0x040fe20004800000 */
/*07c0*/ MUFU.RCP64H R15, R5 ; /* 0x00000005000f7308 */
/* 0x001e220000001800 */
/*07d0*/ @!P2 LOP3.LUT R8, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000708a812 */
/* 0x000fe200078ec0ff */
/*07e0*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*07f0*/ LOP3.LUT R9, R9, 0x800fffff, R3, 0xf8, !PT ; /* 0x800fffff09097812 */
/* 0x000fe400078ef803 */
/*0800*/ @!P2 ISETP.GE.U32.AND P3, PT, R11, R8, PT ; /* 0x000000080b00a20c */
/* 0x000fe20003f66070 */
/*0810*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0002 */
/*0820*/ @!P0 LOP3.LUT R16, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005108812 */
/* 0x000fe400078ec0ff */
/*0830*/ @!P2 SEL R13, R12, 0x63400000, !P3 ; /* 0x634000000c0da807 */
/* 0x000fc40005800000 */
/*0840*/ IADD3 R22, R16, -0x1, RZ ; /* 0xffffffff10167810 */
/* 0x000fe40007ffe0ff */
/*0850*/ @!P2 LOP3.LUT R13, R13, 0x80000000, R3, 0xf8, !PT ; /* 0x800000000d0da812 */
/* 0x000fe200078ef803 */
/*0860*/ DFMA R18, R14, -R4, 1 ; /* 0x3ff000000e12742b */
/* 0x001e060000000804 */
/*0870*/ @!P2 LOP3.LUT R21, R13, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000d15a812 */
/* 0x000fc600078efcff */
/*0880*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e080000000012 */
/*0890*/ @!P2 DFMA R8, R8, 2, -R20 ; /* 0x400000000808a82b */
/* 0x000e480000000814 */
/*08a0*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e0c000000000e */
/*08b0*/ @!P2 LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000911a812 */
/* 0x002fe200078ec0ff */
/*08c0*/ DFMA R18, R14, -R4, 1 ; /* 0x3ff000000e12742b */
/* 0x001e060000000804 */
/*08d0*/ IADD3 R13, R17, -0x1, RZ ; /* 0xffffffff110d7810 */
/* 0x000fc60007ffe0ff */
/*08e0*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*08f0*/ ISETP.GT.U32.AND P0, PT, R13, 0x7feffffe, PT ; /* 0x7feffffe0d00780c */
/* 0x000fc80003f04070 */
/*0900*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fe20000704470 */
/*0910*/ DMUL R18, R14, R8 ; /* 0x000000080e127228 */
/* 0x001e0c0000000000 */
/*0920*/ DFMA R20, R18, -R4, R8 ; /* 0x800000041214722b */
/* 0x001e0c0000000008 */
/*0930*/ DFMA R14, R14, R20, R18 ; /* 0x000000140e0e722b */
/* 0x0010620000000012 */
/*0940*/ @P0 BRA 0xb10 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0950*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fc800078ec0ff */
/*0960*/ ISETP.GE.U32.AND P0, PT, R11.reuse, R16, PT ; /* 0x000000100b00720c */
/* 0x040fe20003f06070 */
/*0970*/ IMAD.IADD R2, R11, 0x1, -R16 ; /* 0x000000010b027824 */
/* 0x000fc600078e0a10 */
/*0980*/ SEL R11, R12, 0x63400000, !P0 ; /* 0x634000000c0b7807 */
/* 0x000fe40004000000 */
/*0990*/ IMNMX R2, R2, -0x46a00000, !PT ; /* 0xb960000002027817 */
/* 0x000fc80007800200 */
/*09a0*/ IMNMX R2, R2, 0x46a00000, PT ; /* 0x46a0000002027817 */
/* 0x000fca0003800200 */
/*09b0*/ IMAD.IADD R11, R2, 0x1, -R11 ; /* 0x00000001020b7824 */
/* 0x000fe400078e0a0b */
/*09c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*09d0*/ IADD3 R3, R11, 0x7fe00000, RZ ; /* 0x7fe000000b037810 */
/* 0x000fcc0007ffe0ff */
/*09e0*/ DMUL R12, R14, R2 ; /* 0x000000020e0c7228 */
/* 0x002e540000000000 */
/*09f0*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x002fda0003f0c200 */
/*0a00*/ @P0 BRA 0xc60 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0a10*/ DFMA R4, R14, -R4, R8 ; /* 0x800000040e04722b */
/* 0x000e620000000008 */
/*0a20*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fd200078e00ff */
/*0a30*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x042fe40003f0d000 */
/*0a40*/ LOP3.LUT R7, R5, 0x80000000, R7, 0x48, !PT ; /* 0x8000000005077812 */
/* 0x000fc800078e4807 */
/*0a50*/ LOP3.LUT R3, R7, R3, RZ, 0xfc, !PT ; /* 0x0000000307037212 */
/* 0x000fce00078efcff */
/*0a60*/ @!P0 BRA 0xc60 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0a70*/ IMAD.MOV R5, RZ, RZ, -R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a0b */
/*0a80*/ DMUL.RP R2, R14, R2 ; /* 0x000000020e027228 */
/* 0x000e620000008000 */
/*0a90*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*0aa0*/ DFMA R4, R12, -R4, R14 ; /* 0x800000040c04722b */
/* 0x000e86000000000e */
/*0ab0*/ LOP3.LUT R7, R3, R7, RZ, 0x3c, !PT ; /* 0x0000000703077212 */
/* 0x002fc600078e3cff */
/*0ac0*/ IADD3 R4, -R11, -0x43300000, RZ ; /* 0xbcd000000b047810 */
/* 0x004fc80007ffe1ff */
/*0ad0*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*0ae0*/ FSEL R12, R2, R12, !P0 ; /* 0x0000000c020c7208 */
/* 0x000fe40004000000 */
/*0af0*/ FSEL R13, R7, R13, !P0 ; /* 0x0000000d070d7208 */
/* 0x000fe20004000000 */
/*0b00*/ BRA 0xc60 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0b10*/ DSETP.NAN.AND P0, PT, R2, R2, PT ; /* 0x000000020200722a */
/* 0x000e9c0003f08000 */
/*0b20*/ @P0 BRA 0xc40 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0b30*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e9c0003f08000 */
/*0b40*/ @P0 BRA 0xc10 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0b50*/ ISETP.NE.AND P0, PT, R17, R16, PT ; /* 0x000000101100720c */
/* 0x000fe20003f05270 */
/*0b60*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0b70*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0b80*/ @!P0 BRA 0xc60 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0b90*/ ISETP.NE.AND P0, PT, R17, 0x7ff00000, PT ; /* 0x7ff000001100780c */
/* 0x000fe40003f05270 */
/*0ba0*/ LOP3.LUT R13, R3, 0x80000000, R7, 0x48, !PT ; /* 0x80000000030d7812 */
/* 0x000fe400078e4807 */
/*0bb0*/ ISETP.EQ.OR P0, PT, R16, RZ, !P0 ; /* 0x000000ff1000720c */
/* 0x000fda0004702670 */
/*0bc0*/ @P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d020812 */
/* 0x000fe200078efcff */
/*0bd0*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*0be0*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*0bf0*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R2 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0002 */
/*0c00*/ BRA 0xc60 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0c10*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*0c20*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0006 */
/*0c30*/ BRA 0xc60 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0c40*/ LOP3.LUT R13, R3, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000030d7812 */
/* 0x000fe200078efcff */
/*0c50*/ IMAD.MOV.U32 R12, RZ, RZ, R2 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0002 */
/*0c60*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0c70*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fe400078e00ff */
/*0c80*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x000fc400078e000c */
/*0c90*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000d */
/*0ca0*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff3500a007950 */
/* 0x000fec0003c3ffff */
/*0cb0*/ ISETP.GE.U32.AND P0, PT, R4, -0x3400000, PT ; /* 0xfcc000000400780c */
/* 0x000fe20003f06070 */
/*0cc0*/ BSSY B1, 0xf10 ; /* 0x0000024000017945 */
/* 0x000fe20003800000 */
/*0cd0*/ IMAD.MOV.U32 R13, RZ, RZ, R17 ; /* 0x000000ffff0d7224 */
/* 0x000fd600078e0011 */
/*0ce0*/ @!P0 BRA 0xd70 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0cf0*/ DFMA.RM R10, R14, R12, R10 ; /* 0x0000000c0e0a722b */
/* 0x000e14000000400a */
/*0d00*/ IADD3 R4, P0, R10, 0x1, RZ ; /* 0x000000010a047810 */
/* 0x001fca0007f1e0ff */
/*0d10*/ IMAD.X R5, RZ, RZ, R11, P0 ; /* 0x000000ffff057224 */
/* 0x000fcc00000e060b */
/*0d20*/ DFMA.RP R2, -R10, R4, R2 ; /* 0x000000040a02722b */
/* 0x000e0c0000008102 */
/*0d30*/ DSETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200722a */
/* 0x001e0c0003f04000 */
/*0d40*/ FSEL R4, R4, R10, P0 ; /* 0x0000000a04047208 */
/* 0x001fe40000000000 */
/*0d50*/ FSEL R5, R5, R11, P0 ; /* 0x0000000b05057208 */
/* 0x000fe20000000000 */
/*0d60*/ BRA 0xf00 ; /* 0x0000019000007947 */
/* 0x000fea0003800000 */
/*0d70*/ DSETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200722a */
/* 0x000e1c0003f05000 */
/*0d80*/ @!P0 BRA 0xef0 ; /* 0x0000016000008947 */
/* 0x001fea0003800000 */
/*0d90*/ ISETP.GE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f06270 */
/*0da0*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff048424 */
/* 0x000fe400078e00ff */
/*0db0*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, -0x80000 ; /* 0xfff80000ff058424 */
/* 0x000fe200078e00ff */
/*0dc0*/ @!P0 BRA 0xf00 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0dd0*/ ISETP.GT.AND P0, PT, R3, 0x7fefffff, PT ; /* 0x7fefffff0300780c */
/* 0x000fda0003f04270 */
/*0de0*/ @P0 BRA 0xef0 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0df0*/ DMUL R2, R2, 8.11296384146066816958e+31 ; /* 0x4690000002027828 */
/* 0x000e220000000000 */
/*0e00*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe400078e00ff */
/*0e10*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe400078e00ff */
/*0e20*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff0b7424 */
/* 0x000fe200078e00ff */
/*0e30*/ MUFU.RSQ64H R5, R3 ; /* 0x0000000300057308 */
/* 0x001e240000001c00 */
/*0e40*/ DMUL R8, R4, R4 ; /* 0x0000000404087228 */
/* 0x001e0c0000000000 */
/*0e50*/ DFMA R8, R2, -R8, 1 ; /* 0x3ff000000208742b */
/* 0x001e0c0000000808 */
/*0e60*/ DFMA R10, R8, R10, 0.5 ; /* 0x3fe00000080a742b */
/* 0x001fc8000000000a */
/*0e70*/ DMUL R8, R4, R8 ; /* 0x0000000804087228 */
/* 0x000e0c0000000000 */
/*0e80*/ DFMA R8, R10, R8, R4 ; /* 0x000000080a08722b */
/* 0x001e0c0000000004 */
/*0e90*/ DMUL R4, R2, R8 ; /* 0x0000000802047228 */
/* 0x0010480000000000 */
/*0ea0*/ IADD3 R9, R9, -0x100000, RZ ; /* 0xfff0000009097810 */
/* 0x001fe40007ffe0ff */
/*0eb0*/ DFMA R10, R4, -R4, R2 ; /* 0x80000004040a722b */
/* 0x002e0c0000000002 */
/*0ec0*/ DFMA R4, R8, R10, R4 ; /* 0x0000000a0804722b */
/* 0x001e140000000004 */
/*0ed0*/ IADD3 R5, R5, -0x3500000, RZ ; /* 0xfcb0000005057810 */
/* 0x001fe20007ffe0ff */
/*0ee0*/ BRA 0xf00 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0ef0*/ DADD R4, R2, R2 ; /* 0x0000000002047229 */
/* 0x00004c0000000002 */
/*0f00*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0f10*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fe400078e00ff */
/*0f20*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x002fe400078e0004 */
/*0f30*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0005 */
/*0f40*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff0b006007950 */
/* 0x000fec0003c3ffff */
/*0f50*/ BRA 0xf50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void kring_Az(double *x, double *y, double *z, double xMax, double yMax, double zMax, double omegaX, double omegaY, double omegaZ, double omega, double fudge, double *A){
int gid = getGid3d3d();
int xid = blockDim.x*blockIdx.x + threadIdx.x;
int yid = blockDim.y*blockIdx.y + threadIdx.y;
double rad = sqrt(x[xid]*x[xid] + y[yid]*y[yid]);
A[gid] = omega * exp(-rad*rad / (0.0001*xMax)) * 0.01;
} | .file "tmpxft_0007a599_00000000-6_kring_Az.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10getGid3d3dv
.type _Z10getGid3d3dv, @function
_Z10getGid3d3dv:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10getGid3d3dv, .-_Z10getGid3d3dv
.globl _Z41__device_stub__Z8kring_AzPdS_S_ddddddddS_PdS_S_ddddddddS_
.type _Z41__device_stub__Z8kring_AzPdS_S_ddddddddS_PdS_S_ddddddddS_, @function
_Z41__device_stub__Z8kring_AzPdS_S_ddddddddS_PdS_S_ddddddddS_:
.LFB2052:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movsd %xmm0, 64(%rsp)
movsd %xmm1, 56(%rsp)
movsd %xmm2, 48(%rsp)
movsd %xmm3, 40(%rsp)
movsd %xmm4, 32(%rsp)
movsd %xmm5, 24(%rsp)
movsd %xmm6, 16(%rsp)
movsd %xmm7, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rax
movq %rax, 200(%rsp)
leaq 40(%rsp), %rax
movq %rax, 208(%rsp)
leaq 32(%rsp), %rax
movq %rax, 216(%rsp)
leaq 24(%rsp), %rax
movq %rax, 224(%rsp)
leaq 16(%rsp), %rax
movq %rax, 232(%rsp)
leaq 8(%rsp), %rax
movq %rax, 240(%rsp)
movq %rsp, %rax
movq %rax, 248(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 104(%rsp)
.cfi_def_cfa_offset 304
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z8kring_AzPdS_S_ddddddddS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z41__device_stub__Z8kring_AzPdS_S_ddddddddS_PdS_S_ddddddddS_, .-_Z41__device_stub__Z8kring_AzPdS_S_ddddddddS_PdS_S_ddddddddS_
.globl _Z8kring_AzPdS_S_ddddddddS_
.type _Z8kring_AzPdS_S_ddddddddS_, @function
_Z8kring_AzPdS_S_ddddddddS_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z8kring_AzPdS_S_ddddddddS_PdS_S_ddddddddS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z8kring_AzPdS_S_ddddddddS_, .-_Z8kring_AzPdS_S_ddddddddS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8kring_AzPdS_S_ddddddddS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8kring_AzPdS_S_ddddddddS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void kring_Az(double *x, double *y, double *z, double xMax, double yMax, double zMax, double omegaX, double omegaY, double omegaZ, double omega, double fudge, double *A){
int gid = getGid3d3d();
int xid = blockDim.x*blockIdx.x + threadIdx.x;
int yid = blockDim.y*blockIdx.y + threadIdx.y;
double rad = sqrt(x[xid]*x[xid] + y[yid]*y[yid]);
A[gid] = omega * exp(-rad*rad / (0.0001*xMax)) * 0.01;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void kring_Az(double *x, double *y, double *z, double xMax, double yMax, double zMax, double omegaX, double omegaY, double omegaZ, double omega, double fudge, double *A){
int gid = getGid3d3d();
int xid = blockDim.x*blockIdx.x + threadIdx.x;
int yid = blockDim.y*blockIdx.y + threadIdx.y;
double rad = sqrt(x[xid]*x[xid] + y[yid]*y[yid]);
A[gid] = omega * exp(-rad*rad / (0.0001*xMax)) * 0.01;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void kring_Az(double *x, double *y, double *z, double xMax, double yMax, double zMax, double omegaX, double omegaY, double omegaZ, double omega, double fudge, double *A){
int gid = getGid3d3d();
int xid = blockDim.x*blockIdx.x + threadIdx.x;
int yid = blockDim.y*blockIdx.y + threadIdx.y;
double rad = sqrt(x[xid]*x[xid] + y[yid]*y[yid]);
A[gid] = omega * exp(-rad*rad / (0.0001*xMax)) * 0.01;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8kring_AzPdS_S_ddddddddS_
.globl _Z8kring_AzPdS_S_ddddddddS_
.p2align 8
.type _Z8kring_AzPdS_S_ddddddddS_,@function
_Z8kring_AzPdS_S_ddddddddS_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x58
s_load_b64 s[2:3], s[0:1], 0x6c
s_add_u32 s8, s0, 0x60
s_addc_u32 s9, s1, 0
v_bfe_u32 v1, v0, 10, 10
s_load_b128 s[16:19], s[0:1], 0x0
v_and_b32_e32 v4, 0x3ff, v0
s_mov_b32 s11, 0xbf1a36e2
s_mov_b32 s10, 0xeb1c432d
v_bfe_u32 v0, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s7, s7, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s14
s_mul_i32 s7, s7, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s12, s7, s13
s_cmp_lt_u32 s13, s6
s_load_b64 s[6:7], s[0:1], 0x18
s_cselect_b32 s15, 12, 18
s_lshr_b32 s20, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s14, s20, v[1:2]
v_mad_u64_u32 v[5:6], null, s13, s2, v[4:5]
s_load_b64 s[0:1], s[0:1], 0x48
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s18, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s19, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s16, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s17, v6, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[5:6], v[5:6], off
s_waitcnt vmcnt(1)
v_mul_f64 v[2:3], v[2:3], v[2:3]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[5:6], v[5:6], v[2:3]
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[2:3]
v_cndmask_b32_e64 v5, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v5, 8, v5
v_ldexp_f64 v[2:3], v[2:3], v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rsq_f64_e32 v[5:6], v[2:3]
s_waitcnt_depctr 0xfff
v_mul_f64 v[7:8], v[2:3], v[5:6]
v_mul_f64 v[5:6], v[5:6], 0.5
v_fma_f64 v[9:10], -v[5:6], v[7:8], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
v_fma_f64 v[5:6], v[5:6], v[9:10], v[5:6]
v_fma_f64 v[9:10], -v[7:8], v[7:8], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[9:10], v[5:6], v[7:8]
v_fma_f64 v[9:10], -v[7:8], v[7:8], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[5:6], v[9:10], v[5:6], v[7:8]
v_cndmask_b32_e64 v7, 0, 0xffffff80, vcc_lo
v_cmp_class_f64_e64 vcc_lo, v[2:3], 0x260
v_ldexp_f64 v[5:6], v[5:6], v7
s_delay_alu instid0(VALU_DEP_1)
v_dual_cndmask_b32 v3, v6, v3 :: v_dual_cndmask_b32 v2, v5, v2
s_waitcnt lgkmcnt(0)
v_mul_f64 v[5:6], s[6:7], s[10:11]
s_mov_b32 s7, 0x3ff71547
s_mov_b32 s6, 0x652b82fe
s_mov_b32 s11, 0x3e5ade15
v_mul_f64 v[2:3], v[2:3], v[2:3]
s_mov_b32 s10, 0x6a5dcb37
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[7:8], null, v[5:6], v[5:6], v[2:3]
v_div_scale_f64 v[13:14], vcc_lo, v[2:3], v[5:6], v[2:3]
v_rcp_f64_e32 v[9:10], v[7:8]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_mul_f64 v[11:12], v[13:14], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[7:8], v[11:12], v[13:14]
v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[11:12]
v_mov_b32_e32 v11, s15
global_load_u16 v11, v11, s[8:9]
v_div_fixup_f64 v[2:3], v[7:8], v[5:6], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_mul_f64 v[5:6], v[2:3], s[6:7]
s_mov_b32 s7, 0xbfe62e42
s_mov_b32 s6, 0xfefa39ef
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[2:3]
v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[2:3]
v_rndne_f64_e32 v[5:6], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f64 v[7:8], v[5:6], s[6:7], v[2:3]
s_mov_b32 s7, 0xbc7abc9e
s_mov_b32 s6, 0x3b39803f
v_cvt_i32_f64_e32 v12, v[5:6]
v_fma_f64 v[7:8], v[5:6], s[6:7], v[7:8]
s_mov_b32 s7, 0x3e928af3
s_mov_b32 s6, 0xfca7ab0c
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[9:10], v[7:8], s[10:11], s[6:7]
s_mov_b32 s7, 0x3ec71dee
s_mov_b32 s6, 0x623fde64
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[9:10], v[7:8], v[9:10], s[6:7]
s_mov_b32 s7, 0x3efa0199
s_mov_b32 s6, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[9:10], v[7:8], v[9:10], s[6:7]
s_mov_b32 s7, 0x3f2a01a0
s_mov_b32 s6, 0x14761f6e
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[9:10], v[7:8], v[9:10], s[6:7]
s_mov_b32 s7, 0x3f56c16c
s_mov_b32 s6, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[9:10], v[7:8], v[9:10], s[6:7]
s_mov_b32 s7, 0x3f811111
s_mov_b32 s6, 0x11122322
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[9:10], v[7:8], v[9:10], s[6:7]
s_mov_b32 s7, 0x3fa55555
s_mov_b32 s6, 0x555502a1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[9:10], v[7:8], v[9:10], s[6:7]
s_mov_b32 s7, 0x3fc55555
s_mov_b32 s6, 0x55555511
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[9:10], v[7:8], v[9:10], s[6:7]
s_mov_b32 s7, 0x3fe00000
s_mov_b32 s6, 11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[9:10], v[7:8], v[9:10], s[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[7:8], v[9:10], 1.0
v_fma_f64 v[5:6], v[7:8], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[5:6], v[5:6], v12
v_cndmask_b32_e32 v6, 0x7ff00000, v6, vcc_lo
s_and_b32 vcc_lo, s2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, 0, v5, vcc_lo
v_cndmask_b32_e64 v3, 0, v6, s2
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], s[0:1]
s_and_b32 s0, s3, 0xffff
s_mov_b32 s1, 0x3f847ae1
v_mad_u64_u32 v[5:6], null, s12, s0, v[0:1]
s_mov_b32 s0, 0x47ae147b
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_f64 v[2:3], v[2:3], s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[6:7], null, v5, s20, v[1:2]
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[0:1], null, v6, v11, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8kring_AzPdS_S_ddddddddS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 352
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8kring_AzPdS_S_ddddddddS_, .Lfunc_end0-_Z8kring_AzPdS_S_ddddddddS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 8
.value_kind: by_value
- .offset: 56
.size: 8
.value_kind: by_value
- .offset: 64
.size: 8
.value_kind: by_value
- .offset: 72
.size: 8
.value_kind: by_value
- .offset: 80
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 88
.size: 8
.value_kind: global_buffer
- .offset: 96
.size: 4
.value_kind: hidden_block_count_x
- .offset: 100
.size: 4
.value_kind: hidden_block_count_y
- .offset: 104
.size: 4
.value_kind: hidden_block_count_z
- .offset: 108
.size: 2
.value_kind: hidden_group_size_x
- .offset: 110
.size: 2
.value_kind: hidden_group_size_y
- .offset: 112
.size: 2
.value_kind: hidden_group_size_z
- .offset: 114
.size: 2
.value_kind: hidden_remainder_x
- .offset: 116
.size: 2
.value_kind: hidden_remainder_y
- .offset: 118
.size: 2
.value_kind: hidden_remainder_z
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 152
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 160
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 352
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8kring_AzPdS_S_ddddddddS_
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _Z8kring_AzPdS_S_ddddddddS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ unsigned int getGid3d3d(){
int blockId = blockIdx.x + blockIdx.y * gridDim.x
+ gridDim.x * gridDim.y * blockIdx.z;
int threadId = blockId * (blockDim.x * blockDim.y * blockDim.z)
+ (threadIdx.y * blockDim.x)
+ (threadIdx.z * (blockDim.x * blockDim.y)) + threadIdx.x;
return threadId;
}
__global__ void kring_Az(double *x, double *y, double *z, double xMax, double yMax, double zMax, double omegaX, double omegaY, double omegaZ, double omega, double fudge, double *A){
int gid = getGid3d3d();
int xid = blockDim.x*blockIdx.x + threadIdx.x;
int yid = blockDim.y*blockIdx.y + threadIdx.y;
double rad = sqrt(x[xid]*x[xid] + y[yid]*y[yid]);
A[gid] = omega * exp(-rad*rad / (0.0001*xMax)) * 0.01;
} | .text
.file "kring_Az.hip"
.globl _Z23__device_stub__kring_AzPdS_S_ddddddddS_ # -- Begin function _Z23__device_stub__kring_AzPdS_S_ddddddddS_
.p2align 4, 0x90
.type _Z23__device_stub__kring_AzPdS_S_ddddddddS_,@function
_Z23__device_stub__kring_AzPdS_S_ddddddddS_: # @_Z23__device_stub__kring_AzPdS_S_ddddddddS_
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 136(%rsp)
movq %rsi, 128(%rsp)
movq %rdx, 120(%rsp)
movsd %xmm0, 112(%rsp)
movsd %xmm1, 104(%rsp)
movsd %xmm2, 96(%rsp)
movsd %xmm3, 88(%rsp)
movsd %xmm4, 80(%rsp)
movsd %xmm5, 72(%rsp)
movsd %xmm6, 64(%rsp)
movsd %xmm7, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 80(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 64(%rsp), %rax
movq %rax, 216(%rsp)
leaq 56(%rsp), %rax
movq %rax, 224(%rsp)
leaq 48(%rsp), %rax
movq %rax, 232(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z8kring_AzPdS_S_ddddddddS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end0:
.size _Z23__device_stub__kring_AzPdS_S_ddddddddS_, .Lfunc_end0-_Z23__device_stub__kring_AzPdS_S_ddddddddS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8kring_AzPdS_S_ddddddddS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8kring_AzPdS_S_ddddddddS_,@object # @_Z8kring_AzPdS_S_ddddddddS_
.section .rodata,"a",@progbits
.globl _Z8kring_AzPdS_S_ddddddddS_
.p2align 3, 0x0
_Z8kring_AzPdS_S_ddddddddS_:
.quad _Z23__device_stub__kring_AzPdS_S_ddddddddS_
.size _Z8kring_AzPdS_S_ddddddddS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8kring_AzPdS_S_ddddddddS_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__kring_AzPdS_S_ddddddddS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8kring_AzPdS_S_ddddddddS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007a599_00000000-6_kring_Az.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10getGid3d3dv
.type _Z10getGid3d3dv, @function
_Z10getGid3d3dv:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10getGid3d3dv, .-_Z10getGid3d3dv
.globl _Z41__device_stub__Z8kring_AzPdS_S_ddddddddS_PdS_S_ddddddddS_
.type _Z41__device_stub__Z8kring_AzPdS_S_ddddddddS_PdS_S_ddddddddS_, @function
_Z41__device_stub__Z8kring_AzPdS_S_ddddddddS_PdS_S_ddddddddS_:
.LFB2052:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movsd %xmm0, 64(%rsp)
movsd %xmm1, 56(%rsp)
movsd %xmm2, 48(%rsp)
movsd %xmm3, 40(%rsp)
movsd %xmm4, 32(%rsp)
movsd %xmm5, 24(%rsp)
movsd %xmm6, 16(%rsp)
movsd %xmm7, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rax
movq %rax, 200(%rsp)
leaq 40(%rsp), %rax
movq %rax, 208(%rsp)
leaq 32(%rsp), %rax
movq %rax, 216(%rsp)
leaq 24(%rsp), %rax
movq %rax, 224(%rsp)
leaq 16(%rsp), %rax
movq %rax, 232(%rsp)
leaq 8(%rsp), %rax
movq %rax, 240(%rsp)
movq %rsp, %rax
movq %rax, 248(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 104(%rsp)
.cfi_def_cfa_offset 304
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z8kring_AzPdS_S_ddddddddS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z41__device_stub__Z8kring_AzPdS_S_ddddddddS_PdS_S_ddddddddS_, .-_Z41__device_stub__Z8kring_AzPdS_S_ddddddddS_PdS_S_ddddddddS_
.globl _Z8kring_AzPdS_S_ddddddddS_
.type _Z8kring_AzPdS_S_ddddddddS_, @function
_Z8kring_AzPdS_S_ddddddddS_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z8kring_AzPdS_S_ddddddddS_PdS_S_ddddddddS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z8kring_AzPdS_S_ddddddddS_, .-_Z8kring_AzPdS_S_ddddddddS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8kring_AzPdS_S_ddddddddS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8kring_AzPdS_S_ddddddddS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kring_Az.hip"
.globl _Z23__device_stub__kring_AzPdS_S_ddddddddS_ # -- Begin function _Z23__device_stub__kring_AzPdS_S_ddddddddS_
.p2align 4, 0x90
.type _Z23__device_stub__kring_AzPdS_S_ddddddddS_,@function
_Z23__device_stub__kring_AzPdS_S_ddddddddS_: # @_Z23__device_stub__kring_AzPdS_S_ddddddddS_
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 136(%rsp)
movq %rsi, 128(%rsp)
movq %rdx, 120(%rsp)
movsd %xmm0, 112(%rsp)
movsd %xmm1, 104(%rsp)
movsd %xmm2, 96(%rsp)
movsd %xmm3, 88(%rsp)
movsd %xmm4, 80(%rsp)
movsd %xmm5, 72(%rsp)
movsd %xmm6, 64(%rsp)
movsd %xmm7, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 80(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 64(%rsp), %rax
movq %rax, 216(%rsp)
leaq 56(%rsp), %rax
movq %rax, 224(%rsp)
leaq 48(%rsp), %rax
movq %rax, 232(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z8kring_AzPdS_S_ddddddddS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end0:
.size _Z23__device_stub__kring_AzPdS_S_ddddddddS_, .Lfunc_end0-_Z23__device_stub__kring_AzPdS_S_ddddddddS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8kring_AzPdS_S_ddddddddS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8kring_AzPdS_S_ddddddddS_,@object # @_Z8kring_AzPdS_S_ddddddddS_
.section .rodata,"a",@progbits
.globl _Z8kring_AzPdS_S_ddddddddS_
.p2align 3, 0x0
_Z8kring_AzPdS_S_ddddddddS_:
.quad _Z23__device_stub__kring_AzPdS_S_ddddddddS_
.size _Z8kring_AzPdS_S_ddddddddS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8kring_AzPdS_S_ddddddddS_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__kring_AzPdS_S_ddddddddS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8kring_AzPdS_S_ddddddddS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "lambert_implement.h"
#include "brdf_common.h"
__global__ void
lambert_kernel(float3* pos, unsigned int width, float reflectance)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
float3 pin = pos[y*width+x];
float r = reflectance / 3.14159265;
pos[y*width+x] = scale(normalize(pin), r);
}
extern "C" void lambert_brdf(float3 *pos, unsigned numVertices, unsigned width, float reflectance)
{
dim3 block(8, 8, 1);
unsigned height = numVertices / width;
dim3 grid(width / block.x, height / block.y, 1);
lambert_kernel<<< grid, block>>>(pos, width, reflectance);
} | code for sm_80
Function : _Z14lambert_kernelP6float3jf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fc400078e0205 */
/*0080*/ IMAD.MOV.U32 R2, RZ, RZ, 0xc ; /* 0x0000000cff027424 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD R3, R3, c[0x0][0x168], R0 ; /* 0x00005a0003037a24 */
/* 0x000fc800078e0200 */
/*00a0*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0002 */
/*00b0*/ LDG.E R4, [R2.64+0x4] ; /* 0x0000040402047981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ee8000c1e1900 */
/*00d0*/ LDG.E R5, [R2.64+0x8] ; /* 0x0000080402057981 */
/* 0x000f22000c1e1900 */
/*00e0*/ BSSY B0, 0x1e0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*00f0*/ FMUL R7, R4, R4 ; /* 0x0000000404077220 */
/* 0x004fc80000400000 */
/*0100*/ FFMA R0, R8, R8, R7 ; /* 0x0000000808007223 */
/* 0x008fc80000000007 */
/*0110*/ FFMA R0, R5, R5, R0 ; /* 0x0000000505007223 */
/* 0x010fc80000000000 */
/*0120*/ MUFU.RSQ R7, R0 ; /* 0x0000000000077308 */
/* 0x0000620000001400 */
/*0130*/ IADD3 R6, R0, -0xd000000, RZ ; /* 0xf300000000067810 */
/* 0x000fc80007ffe0ff */
/*0140*/ ISETP.GT.U32.AND P0, PT, R6, 0x727fffff, PT ; /* 0x727fffff0600780c */
/* 0x000fda0003f04070 */
/*0150*/ @!P0 BRA 0x190 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0160*/ MOV R12, 0x180 ; /* 0x00000180000c7802 */
/* 0x003fe40000000f00 */
/*0170*/ CALL.REL.NOINC 0xb90 ; /* 0x00000a1000007944 */
/* 0x000fea0003c00000 */
/*0180*/ BRA 0x1d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0190*/ FMUL.FTZ R9, R0, R7 ; /* 0x0000000700097220 */
/* 0x003fe40000410000 */
/*01a0*/ FMUL.FTZ R7, R7, 0.5 ; /* 0x3f00000007077820 */
/* 0x000fe40000410000 */
/*01b0*/ FFMA R0, -R9, R9, R0 ; /* 0x0000000909007223 */
/* 0x000fc80000000100 */
/*01c0*/ FFMA R9, R0, R7, R9 ; /* 0x0000000700097223 */
/* 0x000fe40000000009 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ F2F.F64.F32 R6, R9 ; /* 0x0000000900067310 */
/* 0x000e220000201800 */
/*01f0*/ BSSY B0, 0x500 ; /* 0x0000030000007945 */
/* 0x000fe20003800000 */
/*0200*/ IMAD.MOV.U32 R0, RZ, RZ, 0x3f13cd36 ; /* 0x3f13cd36ff007424 */
/* 0x000fe200078e00ff */
/*0210*/ DSETP.GT.AND P0, PT, R6, c[0x2][0x0], PT ; /* 0x008000000600762a */
/* 0x0010640003f04000 */
/*0220*/ IMAD.MOV.U32 R6, RZ, RZ, 0x3f13cd36 ; /* 0x3f13cd36ff067424 */
/* 0x001fe400078e00ff */
/*0230*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3f13cd36 ; /* 0x3f13cd36ff077424 */
/* 0x000fd400078e00ff */
/*0240*/ @!P0 BRA 0x4f0 ; /* 0x000002a000008947 */
/* 0x002fea0003800000 */
/*0250*/ MUFU.RCP R0, R9 ; /* 0x0000000900007308 */
/* 0x000e220000001000 */
/*0260*/ BSSY B1, 0x330 ; /* 0x000000c000017945 */
/* 0x000fee0003800000 */
/*0270*/ FCHK P0, R8, R9 ; /* 0x0000000908007302 */
/* 0x000e620000000000 */
/*0280*/ FFMA R7, R0, -R9, 1 ; /* 0x3f80000000077423 */
/* 0x001fc80000000809 */
/*0290*/ FFMA R7, R0, R7, R0 ; /* 0x0000000700077223 */
/* 0x000fc80000000000 */
/*02a0*/ FFMA R0, R8, R7, RZ ; /* 0x0000000708007223 */
/* 0x000fc800000000ff */
/*02b0*/ FFMA R6, R0, -R9, R8 ; /* 0x8000000900067223 */
/* 0x000fc80000000008 */
/*02c0*/ FFMA R7, R7, R6, R0 ; /* 0x0000000607077223 */
/* 0x000fe20000000000 */
/*02d0*/ @!P0 BRA 0x320 ; /* 0x0000004000008947 */
/* 0x002fea0003800000 */
/*02e0*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*02f0*/ MOV R0, 0x310 ; /* 0x0000031000007802 */
/* 0x000fe40000000f00 */
/*0300*/ CALL.REL.NOINC 0xd00 ; /* 0x000009f000007944 */
/* 0x000fea0003c00000 */
/*0310*/ IMAD.MOV.U32 R7, RZ, RZ, R8 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0008 */
/*0320*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0330*/ MUFU.RCP R0, R9 ; /* 0x0000000900007308 */
/* 0x000e220000001000 */
/*0340*/ BSSY B1, 0x410 ; /* 0x000000c000017945 */
/* 0x000fee0003800000 */
/*0350*/ FCHK P0, R4, R9 ; /* 0x0000000904007302 */
/* 0x000e620000000000 */
/*0360*/ FFMA R11, R0, -R9, 1 ; /* 0x3f800000000b7423 */
/* 0x001fc80000000809 */
/*0370*/ FFMA R13, R0, R11, R0 ; /* 0x0000000b000d7223 */
/* 0x000fc80000000000 */
/*0380*/ FFMA R0, R4, R13, RZ ; /* 0x0000000d04007223 */
/* 0x000fc800000000ff */
/*0390*/ FFMA R11, R0, -R9, R4 ; /* 0x80000009000b7223 */
/* 0x000fc80000000004 */
/*03a0*/ FFMA R6, R13, R11, R0 ; /* 0x0000000b0d067223 */
/* 0x000fe20000000000 */
/*03b0*/ @!P0 BRA 0x400 ; /* 0x0000004000008947 */
/* 0x002fea0003800000 */
/*03c0*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0004 */
/*03d0*/ MOV R0, 0x3f0 ; /* 0x000003f000007802 */
/* 0x000fe40000000f00 */
/*03e0*/ CALL.REL.NOINC 0xd00 ; /* 0x0000091000007944 */
/* 0x000fea0003c00000 */
/*03f0*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0008 */
/*0400*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0410*/ MUFU.RCP R0, R9 ; /* 0x0000000900007308 */
/* 0x000e220000001000 */
/*0420*/ BSSY B1, 0x4f0 ; /* 0x000000c000017945 */
/* 0x000fee0003800000 */
/*0430*/ FCHK P0, R5, R9 ; /* 0x0000000905007302 */
/* 0x000e620000000000 */
/*0440*/ FFMA R11, R0, -R9, 1 ; /* 0x3f800000000b7423 */
/* 0x001fc80000000809 */
/*0450*/ FFMA R4, R0, R11, R0 ; /* 0x0000000b00047223 */
/* 0x000fc80000000000 */
/*0460*/ FFMA R0, R5, R4, RZ ; /* 0x0000000405007223 */
/* 0x000fc800000000ff */
/*0470*/ FFMA R11, R0, -R9, R5 ; /* 0x80000009000b7223 */
/* 0x000fc80000000005 */
/*0480*/ FFMA R0, R4, R11, R0 ; /* 0x0000000b04007223 */
/* 0x000fe20000000000 */
/*0490*/ @!P0 BRA 0x4e0 ; /* 0x0000004000008947 */
/* 0x002fea0003800000 */
/*04a0*/ IMAD.MOV.U32 R12, RZ, RZ, R5 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0005 */
/*04b0*/ MOV R0, 0x4d0 ; /* 0x000004d000007802 */
/* 0x000fe40000000f00 */
/*04c0*/ CALL.REL.NOINC 0xd00 ; /* 0x0000083000007944 */
/* 0x000fea0003c00000 */
/*04d0*/ IMAD.MOV.U32 R0, RZ, RZ, R8 ; /* 0x000000ffff007224 */
/* 0x001fe400078e0008 */
/*04e0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ MUFU.RCP64H R5, 3.1415920257568359375 ; /* 0x400921fb00057908 */
/* 0x000e220000001800 */
/*0510*/ MOV R10, 0x53c8d4f1 ; /* 0x53c8d4f1000a7802 */
/* 0x000fe20000000f00 */
/*0520*/ IMAD.MOV.U32 R11, RZ, RZ, 0x400921fb ; /* 0x400921fbff0b7424 */
/* 0x000fe400078e00ff */
/*0530*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fcc00078e00ff */
/*0540*/ DFMA R8, R4, -R10, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c000000080a */
/*0550*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0560*/ DFMA R4, R4, R8, R4 ; /* 0x000000080404722b */
/* 0x0010480000000004 */
/*0570*/ F2F.F64.F32 R8, c[0x0][0x16c] ; /* 0x00005b0000087b10 */
/* 0x001e240000201800 */
/*0580*/ DFMA R10, R4, -R10, 1 ; /* 0x3ff00000040a742b */
/* 0x002e4c000000080a */
/*0590*/ DFMA R10, R4, R10, R4 ; /* 0x0000000a040a722b */
/* 0x002e0c0000000004 */
/*05a0*/ DMUL R4, R8, R10 ; /* 0x0000000a08047228 */
/* 0x001e220000000000 */
/*05b0*/ FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT ; /* 0x036000000900780b */
/* 0x000fca0003f2e200 */
/*05c0*/ DFMA R12, R4, c[0x2][0x8], R8 ; /* 0x00800200040c7a2b */
/* 0x001e0c0000000008 */
/*05d0*/ DFMA R4, R10, R12, R4 ; /* 0x0000000c0a04722b */
/* 0x001e140000000004 */
/*05e0*/ FFMA R10, RZ, 2.1426990032196044922, R5 ; /* 0x400921fbff0a7823 */
/* 0x001fca0000000005 */
/*05f0*/ FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; /* 0x001000000a00780b */
/* 0x000fda0003f04200 */
/*0600*/ @P0 BRA P1, 0x630 ; /* 0x0000002000000947 */
/* 0x000fea0000800000 */
/*0610*/ MOV R12, 0x630 ; /* 0x00000630000c7802 */
/* 0x000fe40000000f00 */
/*0620*/ CALL.REL.NOINC 0x6b0 ; /* 0x0000008000007944 */
/* 0x000fea0003c00000 */
/*0630*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x000e240000301000 */
/*0640*/ FMUL R7, R5.reuse, R7 ; /* 0x0000000705077220 */
/* 0x041fe40000400000 */
/*0650*/ FMUL R9, R5.reuse, R6 ; /* 0x0000000605097220 */
/* 0x040fe40000400000 */
/*0660*/ FMUL R11, R5, R0 ; /* 0x00000000050b7220 */
/* 0x000fe20000400000 */
/*0670*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0680*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x000fe8000c101904 */
/*0690*/ STG.E [R2.64+0x8], R11 ; /* 0x0000080b02007986 */
/* 0x000fe2000c101904 */
/*06a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3ff921fb ; /* 0x3ff921fbff057424 */
/* 0x000fe200078e00ff */
/*06c0*/ FSETP.GEU.AND P1, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f2e200 */
/*06d0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x53c8d4f1 ; /* 0x53c8d4f1ff047424 */
/* 0x000fe200078e00ff */
/*06e0*/ LOP3.LUT R13, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090d7812 */
/* 0x000fe200078ec0ff */
/*06f0*/ MUFU.RCP64H R11, R5 ; /* 0x00000005000b7308 */
/* 0x000e220000001800 */
/*0700*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fc400078e00ff */
/*0710*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff127424 */
/* 0x000fe200078e00ff */
/*0720*/ ISETP.GE.U32.AND P0, PT, R13, 0x40000000, PT ; /* 0x400000000d00780c */
/* 0x000fe20003f06070 */
/*0730*/ IMAD.MOV.U32 R23, RZ, RZ, 0x40000000 ; /* 0x40000000ff177424 */
/* 0x000fe200078e00ff */
/*0740*/ MOV R22, R13 ; /* 0x0000000d00167202 */
/* 0x000fc80000000f00 */
/*0750*/ IADD3 R24, R23, -0x1, RZ ; /* 0xffffffff17187810 */
/* 0x000fe20007ffe0ff */
/*0760*/ DFMA R14, R10, -R4, 1 ; /* 0x3ff000000a0e742b */
/* 0x001e0c0000000804 */
/*0770*/ DFMA R16, R14, R14, R14 ; /* 0x0000000e0e10722b */
/* 0x001064000000000e */
/*0780*/ SEL R15, R18, 0x63400000, !P0 ; /* 0x63400000120f7807 */
/* 0x001fc80004000000 */
/*0790*/ @!P1 LOP3.LUT R14, R15.reuse, 0x80000000, R9.reuse, 0xf8, !PT ; /* 0x800000000f0e9812 */
/* 0x140fe200078ef809 */
/*07a0*/ DFMA R18, R10, R16, R10 ; /* 0x000000100a12722b */
/* 0x002064000000000a */
/*07b0*/ LOP3.LUT R11, R15, 0x800fffff, R9, 0xf8, !PT ; /* 0x800fffff0f0b7812 */
/* 0x001fe200078ef809 */
/*07c0*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0008 */
/*07d0*/ @!P1 LOP3.LUT R17, R14, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000e119812 */
/* 0x000fe200078efcff */
/*07e0*/ @!P1 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff109224 */
/* 0x000fe200078e00ff */
/*07f0*/ DFMA R20, R18, -R4, 1 ; /* 0x3ff000001214742b */
/* 0x002e0a0000000804 */
/*0800*/ @!P1 DFMA R10, R10, 2, -R16 ; /* 0x400000000a0a982b */
/* 0x000e480000000810 */
/*0810*/ DFMA R16, R18, R20, R18 ; /* 0x000000141210722b */
/* 0x001e0c0000000012 */
/*0820*/ @!P1 LOP3.LUT R22, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b169812 */
/* 0x002fe200078ec0ff */
/*0830*/ DMUL R18, R16, R10 ; /* 0x0000000a10127228 */
/* 0x001e060000000000 */
/*0840*/ IADD3 R14, R22, -0x1, RZ ; /* 0xffffffff160e7810 */
/* 0x000fc60007ffe0ff */
/*0850*/ DFMA R20, R18, -R4, R10 ; /* 0x800000041214722b */
/* 0x001e22000000000a */
/*0860*/ ISETP.GT.U32.AND P0, PT, R14, 0x7feffffe, PT ; /* 0x7feffffe0e00780c */
/* 0x000fc80003f04070 */
/*0870*/ ISETP.GT.U32.OR P0, PT, R24, 0x7feffffe, P0 ; /* 0x7feffffe1800780c */
/* 0x000fe20000704470 */
/*0880*/ DFMA R16, R16, R20, R18 ; /* 0x000000141010722b */
/* 0x0010580000000012 */
/*0890*/ @P0 BRA 0xa40 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*08a0*/ IADD3 R13, R13, -0x40000000, RZ ; /* 0xc00000000d0d7810 */
/* 0x003fc80007ffe0ff */
/*08b0*/ IMNMX R13, R13, -0x46a00000, !PT ; /* 0xb96000000d0d7817 */
/* 0x000fc80007800200 */
/*08c0*/ IMNMX R8, R13, 0x46a00000, PT ; /* 0x46a000000d087817 */
/* 0x000fca0003800200 */
/*08d0*/ IMAD.IADD R13, R8, 0x1, -R15 ; /* 0x00000001080d7824 */
/* 0x000fe400078e0a0f */
/*08e0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*08f0*/ IADD3 R9, R13, 0x7fe00000, RZ ; /* 0x7fe000000d097810 */
/* 0x000fcc0007ffe0ff */
/*0900*/ DMUL R14, R16, R8 ; /* 0x00000008100e7228 */
/* 0x000e140000000000 */
/*0910*/ FSETP.GTU.AND P0, PT, |R15|, 1.469367938527859385e-39, PT ; /* 0x001000000f00780b */
/* 0x001fda0003f0c200 */
/*0920*/ @P0 BRA 0xb50 ; /* 0x0000022000000947 */
/* 0x000fea0003800000 */
/*0930*/ DFMA R4, R16, -R4, R10 ; /* 0x800000041004722b */
/* 0x000e22000000000a */
/*0940*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd200078e00ff */
/*0950*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*0960*/ LOP3.LUT R4, R5, 0x400921fb, RZ, 0x3c, !PT ; /* 0x400921fb05047812 */
/* 0x000fc800078e3cff */
/*0970*/ LOP3.LUT R11, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x80000000040b7812 */
/* 0x000fc800078ec0ff */
/*0980*/ LOP3.LUT R9, R11, R9, RZ, 0xfc, !PT ; /* 0x000000090b097212 */
/* 0x000fc600078efcff */
/*0990*/ @!P0 BRA 0xb50 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*09a0*/ IMAD.MOV R5, RZ, RZ, -R13 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a0d */
/*09b0*/ DMUL.RP R8, R16, R8 ; /* 0x0000000810087228 */
/* 0x000e220000008000 */
/*09c0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*09d0*/ IADD3 R13, -R13, -0x43300000, RZ ; /* 0xbcd000000d0d7810 */
/* 0x000fca0007ffe1ff */
/*09e0*/ DFMA R4, R14, -R4, R16 ; /* 0x800000040e04722b */
/* 0x000e460000000010 */
/*09f0*/ LOP3.LUT R11, R9, R11, RZ, 0x3c, !PT ; /* 0x0000000b090b7212 */
/* 0x001fce00078e3cff */
/*0a00*/ FSETP.NEU.AND P0, PT, |R5|, R13, PT ; /* 0x0000000d0500720b */
/* 0x002fc80003f0d200 */
/*0a10*/ FSEL R14, R8, R14, !P0 ; /* 0x0000000e080e7208 */
/* 0x000fe40004000000 */
/*0a20*/ FSEL R15, R11, R15, !P0 ; /* 0x0000000f0b0f7208 */
/* 0x000fe20004000000 */
/*0a30*/ BRA 0xb50 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*0a40*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x003e1c0003f08000 */
/*0a50*/ @P0 BRA 0xb30 ; /* 0x000000d000000947 */
/* 0x001fea0003800000 */
/*0a60*/ ISETP.NE.AND P0, PT, R22, R23, PT ; /* 0x000000171600720c */
/* 0x000fe20003f05270 */
/*0a70*/ IMAD.MOV.U32 R14, RZ, RZ, 0x0 ; /* 0x00000000ff0e7424 */
/* 0x000fe400078e00ff */
/*0a80*/ IMAD.MOV.U32 R15, RZ, RZ, -0x80000 ; /* 0xfff80000ff0f7424 */
/* 0x000fd400078e00ff */
/*0a90*/ @!P0 BRA 0xb50 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ ISETP.NE.AND P0, PT, R22, 0x7ff00000, PT ; /* 0x7ff000001600780c */
/* 0x000fe40003f05270 */
/*0ab0*/ LOP3.LUT R8, R9, 0x400921fb, RZ, 0x3c, !PT ; /* 0x400921fb09087812 */
/* 0x000fe400078e3cff */
/*0ac0*/ ISETP.EQ.OR P0, PT, R23, RZ, !P0 ; /* 0x000000ff1700720c */
/* 0x000fe40004702670 */
/*0ad0*/ LOP3.LUT R15, R8, 0x80000000, RZ, 0xc0, !PT ; /* 0x80000000080f7812 */
/* 0x000fd600078ec0ff */
/*0ae0*/ @P0 LOP3.LUT R4, R15, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000f040812 */
/* 0x000fe400078efcff */
/*0af0*/ @!P0 MOV R14, RZ ; /* 0x000000ff000e8202 */
/* 0x000fe20000000f00 */
/*0b00*/ @P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e0224 */
/* 0x000fe400078e00ff */
/*0b10*/ @P0 IMAD.MOV.U32 R15, RZ, RZ, R4 ; /* 0x000000ffff0f0224 */
/* 0x000fe200078e0004 */
/*0b20*/ BRA 0xb50 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0b30*/ LOP3.LUT R15, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090f7812 */
/* 0x000fe200078efcff */
/*0b40*/ IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0008 */
/*0b50*/ IMAD.MOV.U32 R13, RZ, RZ, 0x0 ; /* 0x00000000ff0d7424 */
/* 0x000fe400078e00ff */
/*0b60*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000e */
/*0b70*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000f */
/*0b80*/ RET.REL.NODEC R12 0x0 ; /* 0xfffff4700c007950 */
/* 0x000fec0003c3ffff */
/*0b90*/ LOP3.LUT P0, RZ, R0, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff00ff7812 */
/* 0x000fda000780c0ff */
/*0ba0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff068224 */
/* 0x000fe200078e0000 */
/*0bb0*/ @!P0 BRA 0xcc0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0bc0*/ FSETP.GEU.FTZ.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fda0003f1e000 */
/*0bd0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff068424 */
/* 0x000fe200078e00ff */
/*0be0*/ @!P0 BRA 0xcc0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0bf0*/ FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f1c200 */
/*0c00*/ @P0 FADD.FTZ R6, R0, 1 ; /* 0x3f80000000060421 */
/* 0x000fe20000010000 */
/*0c10*/ @P0 BRA 0xcc0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0c20*/ FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f1d200 */
/*0c30*/ @P0 FFMA R7, R0, 1.84467440737095516160e+19, RZ ; /* 0x5f80000000070823 */
/* 0x000fc800000000ff */
/*0c40*/ @P0 MUFU.RSQ R6, R7 ; /* 0x0000000700060308 */
/* 0x000e240000001400 */
/*0c50*/ @P0 FMUL.FTZ R10, R7, R6 ; /* 0x00000006070a0220 */
/* 0x001fe40000410000 */
/*0c60*/ @P0 FMUL.FTZ R11, R6, 0.5 ; /* 0x3f000000060b0820 */
/* 0x000fe20000410000 */
/*0c70*/ @!P0 MOV R6, R0 ; /* 0x0000000000068202 */
/* 0x000fe20000000f00 */
/*0c80*/ @P0 FADD.FTZ R9, -R10, -RZ ; /* 0x800000ff0a090221 */
/* 0x000fc80000010100 */
/*0c90*/ @P0 FFMA R9, R10, R9, R7 ; /* 0x000000090a090223 */
/* 0x000fc80000000007 */
/*0ca0*/ @P0 FFMA R9, R9, R11, R10 ; /* 0x0000000b09090223 */
/* 0x000fc8000000000a */
/*0cb0*/ @P0 FMUL.FTZ R6, R9, 2.3283064365386962891e-10 ; /* 0x2f80000009060820 */
/* 0x000fc80000410000 */
/*0cc0*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0006 */
/*0cd0*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000c */
/*0ce0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*0cf0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff30006007950 */
/* 0x000fea0003c3ffff */
/*0d00*/ SHF.R.U32.HI R11, RZ, 0x17, R9.reuse ; /* 0x00000017ff0b7819 */
/* 0x100fe20000011609 */
/*0d10*/ BSSY B2, 0x1360 ; /* 0x0000064000027945 */
/* 0x000fe20003800000 */
/*0d20*/ SHF.R.U32.HI R8, RZ, 0x17, R12.reuse ; /* 0x00000017ff087819 */
/* 0x100fe2000001160c */
/*0d30*/ IMAD.MOV.U32 R13, RZ, RZ, R9 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0009 */
/*0d40*/ LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0b0b7812 */
/* 0x000fe400078ec0ff */
/*0d50*/ LOP3.LUT R16, R8, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff08107812 */
/* 0x000fe200078ec0ff */
/*0d60*/ IMAD.MOV.U32 R8, RZ, RZ, R12 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000c */
/*0d70*/ IADD3 R15, R11, -0x1, RZ ; /* 0xffffffff0b0f7810 */
/* 0x000fe40007ffe0ff */
/*0d80*/ IADD3 R14, R16, -0x1, RZ ; /* 0xffffffff100e7810 */
/* 0x000fc40007ffe0ff */
/*0d90*/ ISETP.GT.U32.AND P0, PT, R15, 0xfd, PT ; /* 0x000000fd0f00780c */
/* 0x000fc80003f04070 */
/*0da0*/ ISETP.GT.U32.OR P0, PT, R14, 0xfd, P0 ; /* 0x000000fd0e00780c */
/* 0x000fda0000704470 */
/*0db0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*0dc0*/ @!P0 BRA 0xf40 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0dd0*/ FSETP.GTU.FTZ.AND P0, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fe40003f1c200 */
/*0de0*/ FSETP.GTU.FTZ.AND P1, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fc80003f3c200 */
/*0df0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0e00*/ @P0 BRA 0x1340 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0e10*/ LOP3.LUT P0, RZ, R13, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff0dff7812 */
/* 0x000fda000780c808 */
/*0e20*/ @!P0 BRA 0x1320 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0e30*/ FSETP.NEU.FTZ.AND P2, PT, |R12|.reuse, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x040fe40003f5d200 */
/*0e40*/ FSETP.NEU.FTZ.AND P1, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe40003f3d200 */
/*0e50*/ FSETP.NEU.FTZ.AND P0, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fd60003f1d200 */
/*0e60*/ @!P1 BRA !P2, 0x1320 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0e70*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*0e80*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0e90*/ @P1 BRA 0x1300 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0ea0*/ LOP3.LUT P1, RZ, R13, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0dff7812 */
/* 0x000fc8000782c0ff */
/*0eb0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0ec0*/ @P0 BRA 0x12d0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0ed0*/ ISETP.GE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f06270 */
/*0ee0*/ ISETP.GE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fd60003f26270 */
/*0ef0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0f00*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*0f10*/ @!P0 FFMA R8, R12, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000c088823 */
/* 0x000fe400000000ff */
/*0f20*/ @!P1 FFMA R13, R9, 1.84467440737095516160e+19, RZ ; /* 0x5f800000090d9823 */
/* 0x000fe200000000ff */
/*0f30*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*0f40*/ LEA R12, R11, 0xc0800000, 0x17 ; /* 0xc08000000b0c7811 */
/* 0x000fe200078eb8ff */
/*0f50*/ BSSY B3, 0x12c0 ; /* 0x0000036000037945 */
/* 0x000fe60003800000 */
/*0f60*/ IADD3 R13, -R12, R13, RZ ; /* 0x0000000d0c0d7210 */
/* 0x000fc40007ffe1ff */
/*0f70*/ IADD3 R12, R16, -0x7f, RZ ; /* 0xffffff81100c7810 */
/* 0x000fe40007ffe0ff */
/*0f80*/ MUFU.RCP R14, R13 ; /* 0x0000000d000e7308 */
/* 0x0000620000001000 */
/*0f90*/ FADD.FTZ R15, -R13, -RZ ; /* 0x800000ff0d0f7221 */
/* 0x000fe40000010100 */
/*0fa0*/ IMAD R8, R12.reuse, -0x800000, R8 ; /* 0xff8000000c087824 */
/* 0x040fe200078e0208 */
/*0fb0*/ IADD3 R13, R12, 0x7f, -R11 ; /* 0x0000007f0c0d7810 */
/* 0x001fca0007ffe80b */
/*0fc0*/ IMAD.IADD R13, R13, 0x1, R10 ; /* 0x000000010d0d7824 */
/* 0x000fe400078e020a */
/*0fd0*/ FFMA R17, R14, R15, 1 ; /* 0x3f8000000e117423 */
/* 0x002fc8000000000f */
/*0fe0*/ FFMA R19, R14, R17, R14 ; /* 0x000000110e137223 */
/* 0x000fc8000000000e */
/*0ff0*/ FFMA R14, R8, R19, RZ ; /* 0x00000013080e7223 */
/* 0x000fc800000000ff */
/*1000*/ FFMA R17, R15, R14, R8 ; /* 0x0000000e0f117223 */
/* 0x000fc80000000008 */
/*1010*/ FFMA R14, R19, R17, R14 ; /* 0x00000011130e7223 */
/* 0x000fc8000000000e */
/*1020*/ FFMA R15, R15, R14, R8 ; /* 0x0000000e0f0f7223 */
/* 0x000fc80000000008 */
/*1030*/ FFMA R8, R19, R15, R14 ; /* 0x0000000f13087223 */
/* 0x000fca000000000e */
/*1040*/ SHF.R.U32.HI R11, RZ, 0x17, R8 ; /* 0x00000017ff0b7819 */
/* 0x000fc80000011608 */
/*1050*/ LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0b0b7812 */
/* 0x000fca00078ec0ff */
/*1060*/ IMAD.IADD R16, R11, 0x1, R13 ; /* 0x000000010b107824 */
/* 0x000fca00078e020d */
/*1070*/ IADD3 R10, R16, -0x1, RZ ; /* 0xffffffff100a7810 */
/* 0x000fc80007ffe0ff */
/*1080*/ ISETP.GE.U32.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f06070 */
/*1090*/ @!P0 BRA 0x12a0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*10a0*/ ISETP.GT.AND P0, PT, R16, 0xfe, PT ; /* 0x000000fe1000780c */
/* 0x000fda0003f04270 */
/*10b0*/ @P0 BRA 0x1270 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*10c0*/ ISETP.GE.AND P0, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x000fda0003f06270 */
/*10d0*/ @P0 BRA 0x12b0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*10e0*/ ISETP.GE.AND P0, PT, R16, -0x18, PT ; /* 0xffffffe81000780c */
/* 0x000fe40003f06270 */
/*10f0*/ LOP3.LUT R8, R8, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000008087812 */
/* 0x000fd600078ec0ff */
/*1100*/ @!P0 BRA 0x12b0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*1110*/ FFMA.RZ R10, R19.reuse, R15.reuse, R14.reuse ; /* 0x0000000f130a7223 */
/* 0x1c0fe2000000c00e */
/*1120*/ IADD3 R13, R16.reuse, 0x20, RZ ; /* 0x00000020100d7810 */
/* 0x040fe20007ffe0ff */
/*1130*/ FFMA.RM R11, R19.reuse, R15.reuse, R14.reuse ; /* 0x0000000f130b7223 */
/* 0x1c0fe2000000400e */
/*1140*/ ISETP.NE.AND P2, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe40003f45270 */
/*1150*/ LOP3.LUT R12, R10, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0a0c7812 */
/* 0x000fe200078ec0ff */
/*1160*/ FFMA.RP R10, R19, R15, R14 ; /* 0x0000000f130a7223 */
/* 0x000fe2000000800e */
/*1170*/ ISETP.NE.AND P1, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f25270 */
/*1180*/ IMAD.MOV R14, RZ, RZ, -R16 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0a10 */
/*1190*/ LOP3.LUT R12, R12, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000c0c7812 */
/* 0x000fe400078efcff */
/*11a0*/ FSETP.NEU.FTZ.AND P0, PT, R10, R11, PT ; /* 0x0000000b0a00720b */
/* 0x000fc40003f1d000 */
/*11b0*/ SHF.L.U32 R13, R12, R13, RZ ; /* 0x0000000d0c0d7219 */
/* 0x000fe400000006ff */
/*11c0*/ SEL R11, R14, RZ, P2 ; /* 0x000000ff0e0b7207 */
/* 0x000fe40001000000 */
/*11d0*/ ISETP.NE.AND P1, PT, R13, RZ, P1 ; /* 0x000000ff0d00720c */
/* 0x000fe40000f25270 */
/*11e0*/ SHF.R.U32.HI R11, RZ, R11, R12 ; /* 0x0000000bff0b7219 */
/* 0x000fe4000001160c */
/*11f0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*1200*/ SHF.R.U32.HI R13, RZ, 0x1, R11 ; /* 0x00000001ff0d7819 */
/* 0x000fc4000001160b */
/*1210*/ SEL R10, RZ, 0x1, !P0 ; /* 0x00000001ff0a7807 */
/* 0x000fc80004000000 */
/*1220*/ LOP3.LUT R10, R10, 0x1, R13, 0xf8, !PT ; /* 0x000000010a0a7812 */
/* 0x000fc800078ef80d */
/*1230*/ LOP3.LUT R10, R10, R11, RZ, 0xc0, !PT ; /* 0x0000000b0a0a7212 */
/* 0x000fca00078ec0ff */
/*1240*/ IMAD.IADD R13, R13, 0x1, R10 ; /* 0x000000010d0d7824 */
/* 0x000fca00078e020a */
/*1250*/ LOP3.LUT R8, R13, R8, RZ, 0xfc, !PT ; /* 0x000000080d087212 */
/* 0x000fe200078efcff */
/*1260*/ BRA 0x12b0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*1270*/ LOP3.LUT R8, R8, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000008087812 */
/* 0x000fc800078ec0ff */
/*1280*/ LOP3.LUT R8, R8, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000008087812 */
/* 0x000fe200078efcff */
/*1290*/ BRA 0x12b0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*12a0*/ IMAD R8, R13, 0x800000, R8 ; /* 0x008000000d087824 */
/* 0x000fe400078e0208 */
/*12b0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*12c0*/ BRA 0x1350 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*12d0*/ LOP3.LUT R8, R13, 0x80000000, R8, 0x48, !PT ; /* 0x800000000d087812 */
/* 0x000fc800078e4808 */
/*12e0*/ LOP3.LUT R8, R8, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000008087812 */
/* 0x000fe200078efcff */
/*12f0*/ BRA 0x1350 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1300*/ LOP3.LUT R8, R13, 0x80000000, R8, 0x48, !PT ; /* 0x800000000d087812 */
/* 0x000fe200078e4808 */
/*1310*/ BRA 0x1350 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1320*/ MUFU.RSQ R8, -QNAN ; /* 0xffc0000000087908 */
/* 0x000e220000001400 */
/*1330*/ BRA 0x1350 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1340*/ FADD.FTZ R8, R12, R9 ; /* 0x000000090c087221 */
/* 0x000fe40000010000 */
/*1350*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*1360*/ IMAD.MOV.U32 R10, RZ, RZ, R0 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0000 */
/*1370*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fc800078e00ff */
/*1380*/ RET.REL.NODEC R10 0x0 ; /* 0xffffec700a007950 */
/* 0x000fea0003c3ffff */
/*1390*/ BRA 0x1390; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*13a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "lambert_implement.h"
#include "brdf_common.h"
__global__ void
lambert_kernel(float3* pos, unsigned int width, float reflectance)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
float3 pin = pos[y*width+x];
float r = reflectance / 3.14159265;
pos[y*width+x] = scale(normalize(pin), r);
}
extern "C" void lambert_brdf(float3 *pos, unsigned numVertices, unsigned width, float reflectance)
{
dim3 block(8, 8, 1);
unsigned height = numVertices / width;
dim3 grid(width / block.x, height / block.y, 1);
lambert_kernel<<< grid, block>>>(pos, width, reflectance);
} | .file "tmpxft_00038700_00000000-6_lambert.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2041:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2041:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z14lambert_kernelP6float3jfP6float3jf
.type _Z42__device_stub__Z14lambert_kernelP6float3jfP6float3jf, @function
_Z42__device_stub__Z14lambert_kernelP6float3jfP6float3jf:
.LFB2063:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14lambert_kernelP6float3jf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z42__device_stub__Z14lambert_kernelP6float3jfP6float3jf, .-_Z42__device_stub__Z14lambert_kernelP6float3jfP6float3jf
.globl _Z14lambert_kernelP6float3jf
.type _Z14lambert_kernelP6float3jf, @function
_Z14lambert_kernelP6float3jf:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z14lambert_kernelP6float3jfP6float3jf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _Z14lambert_kernelP6float3jf, .-_Z14lambert_kernelP6float3jf
.globl lambert_brdf
.type lambert_brdf, @function
lambert_brdf:
.LFB2038:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %eax
movl %edx, %ebx
movss %xmm0, 12(%rsp)
shrl $3, %edx
movl %edx, 36(%rsp)
movl $0, %edx
divl %ebx
shrl $3, %eax
movl %eax, 40(%rsp)
movl $8, 24(%rsp)
movl $8, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movss 12(%rsp), %xmm0
movl %ebx, %esi
movq %rbp, %rdi
call _Z42__device_stub__Z14lambert_kernelP6float3jfP6float3jf
jmp .L11
.cfi_endproc
.LFE2038:
.size lambert_brdf, .-lambert_brdf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14lambert_kernelP6float3jf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14lambert_kernelP6float3jf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "lambert_implement.h"
#include "brdf_common.h"
__global__ void
lambert_kernel(float3* pos, unsigned int width, float reflectance)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
float3 pin = pos[y*width+x];
float r = reflectance / 3.14159265;
pos[y*width+x] = scale(normalize(pin), r);
}
extern "C" void lambert_brdf(float3 *pos, unsigned numVertices, unsigned width, float reflectance)
{
dim3 block(8, 8, 1);
unsigned height = numVertices / width;
dim3 grid(width / block.x, height / block.y, 1);
lambert_kernel<<< grid, block>>>(pos, width, reflectance);
} | #include <hip/hip_runtime.h>
#include "lambert_implement.h"
#include "brdf_common.h"
__global__ void
lambert_kernel(float3* pos, unsigned int width, float reflectance)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
float3 pin = pos[y*width+x];
float r = reflectance / 3.14159265;
pos[y*width+x] = scale(normalize(pin), r);
}
extern "C" void lambert_brdf(float3 *pos, unsigned numVertices, unsigned width, float reflectance)
{
dim3 block(8, 8, 1);
unsigned height = numVertices / width;
dim3 grid(width / block.x, height / block.y, 1);
lambert_kernel<<< grid, block>>>(pos, width, reflectance);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "lambert_implement.h"
#include "brdf_common.h"
__global__ void
lambert_kernel(float3* pos, unsigned int width, float reflectance)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
float3 pin = pos[y*width+x];
float r = reflectance / 3.14159265;
pos[y*width+x] = scale(normalize(pin), r);
}
extern "C" void lambert_brdf(float3 *pos, unsigned numVertices, unsigned width, float reflectance)
{
dim3 block(8, 8, 1);
unsigned height = numVertices / width;
dim3 grid(width / block.x, height / block.y, 1);
lambert_kernel<<< grid, block>>>(pos, width, reflectance);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf
.globl _Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf
.p2align 8
.type _Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf,@function
_Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s5, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_load_b64 s[2:3], s[0:1], 0x0
s_mul_i32 s14, s14, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s5
v_add3_u32 v0, s14, v0, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, 12, s[2:3]
s_mov_b32 s3, 0x3ee4f8b5
global_load_b96 v[0:2], v[3:4], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v5, v1, v1
v_fmac_f32_e32 v5, v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v2, v2
v_mul_f32_e32 v6, 0x4f800000, v5
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_sqrt_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v7, -1, v6
v_add_nc_u32_e32 v8, 1, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v9, -v7, v6, v5
v_fma_f32 v10, -v8, v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v9
v_cndmask_b32_e64 v6, v6, v7, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v10
v_cndmask_b32_e64 v6, v6, v8, s2
v_mov_b32_e32 v8, 0x3f13cd36
s_mov_b32 s2, 0x88e368f1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, 0x37800000, v6
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v5, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v6, v5, vcc_lo
v_cvt_f64_f32_e32 v[6:7], v5
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_f64_e32 vcc_lo, s[2:3], v[6:7]
v_dual_mov_b32 v6, 0x3f13cd36 :: v_dual_mov_b32 v7, 0x3f13cd36
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
v_div_scale_f32 v6, null, v5, v5, v0
v_div_scale_f32 v7, null, v5, v5, v1
v_div_scale_f32 v8, null, v5, v5, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v9, v6
v_rcp_f32_e32 v10, v7
v_div_scale_f32 v12, vcc_lo, v0, v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(TRANS32_DEP_3)
v_rcp_f32_e32 v11, v8
v_div_scale_f32 v13, s2, v1, v5, v1
v_div_scale_f32 v17, s3, v2, v5, v2
v_fma_f32 v14, -v6, v9, 1.0
s_waitcnt_depctr 0xfff
v_fma_f32 v15, -v7, v10, 1.0
v_fma_f32 v16, -v8, v11, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v9, v14, v9 :: v_dual_fmac_f32 v10, v15, v10
v_dual_mul_f32 v14, v12, v9 :: v_dual_mul_f32 v15, v13, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v18, -v6, v14, v12
v_fmac_f32_e32 v11, v16, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v19, -v7, v15, v13
v_fmac_f32_e32 v14, v18, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mul_f32 v16, v17, v11 :: v_dual_fmac_f32 v15, v19, v10
v_fma_f32 v6, -v6, v14, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v20, -v8, v16, v17
v_fma_f32 v7, -v7, v15, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fmas_f32 v6, v6, v9, v14
v_fmac_f32_e32 v16, v20, v11
s_mov_b32 vcc_lo, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v7, v7, v10, v15
s_mov_b32 vcc_lo, s3
v_fma_f32 v8, -v8, v16, v17
v_div_fixup_f32 v6, v6, v5, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f32 v7, v7, v5, v1
v_div_fmas_f32 v8, v8, v11, v16
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v8, v8, v5, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_load_b32 s0, s[0:1], 0xc
s_mov_b32 s1, 0x400921fb
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[0:1], s0
s_mov_b32 s0, 0x53c8d4f1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_div_scale_f64 v[9:10], null, s[0:1], s[0:1], v[0:1]
v_div_scale_f64 v[15:16], vcc_lo, v[0:1], s[0:1], v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[11:12], v[9:10]
s_waitcnt_depctr 0xfff
v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[13:14], v[15:16], v[11:12]
v_fma_f64 v[9:10], -v[9:10], v[13:14], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[9:10], v[9:10], v[11:12], v[13:14]
v_div_fixup_f64 v[0:1], v[9:10], s[0:1], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[0:1]
v_mul_f32_e32 v0, v6, v2
v_mul_f32_e32 v1, v7, v2
v_mul_f32_e32 v2, v8, v2
global_store_b96 v[3:4], v[0:2], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf, .Lfunc_end0-_Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "lambert_implement.h"
#include "brdf_common.h"
__global__ void
lambert_kernel(float3* pos, unsigned int width, float reflectance)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
float3 pin = pos[y*width+x];
float r = reflectance / 3.14159265;
pos[y*width+x] = scale(normalize(pin), r);
}
extern "C" void lambert_brdf(float3 *pos, unsigned numVertices, unsigned width, float reflectance)
{
dim3 block(8, 8, 1);
unsigned height = numVertices / width;
dim3 grid(width / block.x, height / block.y, 1);
lambert_kernel<<< grid, block>>>(pos, width, reflectance);
} | .text
.file "lambert.hip"
.globl _Z29__device_stub__lambert_kernelP15HIP_vector_typeIfLj3EEjf # -- Begin function _Z29__device_stub__lambert_kernelP15HIP_vector_typeIfLj3EEjf
.p2align 4, 0x90
.type _Z29__device_stub__lambert_kernelP15HIP_vector_typeIfLj3EEjf,@function
_Z29__device_stub__lambert_kernelP15HIP_vector_typeIfLj3EEjf: # @_Z29__device_stub__lambert_kernelP15HIP_vector_typeIfLj3EEjf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__lambert_kernelP15HIP_vector_typeIfLj3EEjf, .Lfunc_end0-_Z29__device_stub__lambert_kernelP15HIP_vector_typeIfLj3EEjf
.cfi_endproc
# -- End function
.globl lambert_brdf # -- Begin function lambert_brdf
.p2align 4, 0x90
.type lambert_brdf,@function
lambert_brdf: # @lambert_brdf
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movss %xmm0, 12(%rsp) # 4-byte Spill
movl %edx, %ebx
movl %esi, %eax
movq %rdi, %r14
xorl %edx, %edx
divl %ebx
# kill: def $eax killed $eax def $rax
movl %ebx, %edi
shrl $3, %edi
shrl $3, %eax
shlq $32, %rax
orq %rax, %rdi
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r14, 72(%rsp)
movl %ebx, 20(%rsp)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size lambert_brdf, .Lfunc_end1-lambert_brdf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf,@object # @_Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf
.section .rodata,"a",@progbits
.globl _Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf
.p2align 3, 0x0
_Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf:
.quad _Z29__device_stub__lambert_kernelP15HIP_vector_typeIfLj3EEjf
.size _Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__lambert_kernelP15HIP_vector_typeIfLj3EEjf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00038700_00000000-6_lambert.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2041:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2041:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z14lambert_kernelP6float3jfP6float3jf
.type _Z42__device_stub__Z14lambert_kernelP6float3jfP6float3jf, @function
_Z42__device_stub__Z14lambert_kernelP6float3jfP6float3jf:
.LFB2063:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14lambert_kernelP6float3jf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z42__device_stub__Z14lambert_kernelP6float3jfP6float3jf, .-_Z42__device_stub__Z14lambert_kernelP6float3jfP6float3jf
.globl _Z14lambert_kernelP6float3jf
.type _Z14lambert_kernelP6float3jf, @function
_Z14lambert_kernelP6float3jf:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z14lambert_kernelP6float3jfP6float3jf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _Z14lambert_kernelP6float3jf, .-_Z14lambert_kernelP6float3jf
.globl lambert_brdf
.type lambert_brdf, @function
lambert_brdf:
.LFB2038:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %eax
movl %edx, %ebx
movss %xmm0, 12(%rsp)
shrl $3, %edx
movl %edx, 36(%rsp)
movl $0, %edx
divl %ebx
shrl $3, %eax
movl %eax, 40(%rsp)
movl $8, 24(%rsp)
movl $8, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movss 12(%rsp), %xmm0
movl %ebx, %esi
movq %rbp, %rdi
call _Z42__device_stub__Z14lambert_kernelP6float3jfP6float3jf
jmp .L11
.cfi_endproc
.LFE2038:
.size lambert_brdf, .-lambert_brdf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14lambert_kernelP6float3jf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14lambert_kernelP6float3jf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lambert.hip"
.globl _Z29__device_stub__lambert_kernelP15HIP_vector_typeIfLj3EEjf # -- Begin function _Z29__device_stub__lambert_kernelP15HIP_vector_typeIfLj3EEjf
.p2align 4, 0x90
.type _Z29__device_stub__lambert_kernelP15HIP_vector_typeIfLj3EEjf,@function
_Z29__device_stub__lambert_kernelP15HIP_vector_typeIfLj3EEjf: # @_Z29__device_stub__lambert_kernelP15HIP_vector_typeIfLj3EEjf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__lambert_kernelP15HIP_vector_typeIfLj3EEjf, .Lfunc_end0-_Z29__device_stub__lambert_kernelP15HIP_vector_typeIfLj3EEjf
.cfi_endproc
# -- End function
.globl lambert_brdf # -- Begin function lambert_brdf
.p2align 4, 0x90
.type lambert_brdf,@function
lambert_brdf: # @lambert_brdf
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movss %xmm0, 12(%rsp) # 4-byte Spill
movl %edx, %ebx
movl %esi, %eax
movq %rdi, %r14
xorl %edx, %edx
divl %ebx
# kill: def $eax killed $eax def $rax
movl %ebx, %edi
shrl $3, %edi
shrl $3, %eax
shlq $32, %rax
orq %rax, %rdi
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r14, 72(%rsp)
movl %ebx, 20(%rsp)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size lambert_brdf, .Lfunc_end1-lambert_brdf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf,@object # @_Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf
.section .rodata,"a",@progbits
.globl _Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf
.p2align 3, 0x0
_Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf:
.quad _Z29__device_stub__lambert_kernelP15HIP_vector_typeIfLj3EEjf
.size _Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__lambert_kernelP15HIP_vector_typeIfLj3EEjf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14lambert_kernelP15HIP_vector_typeIfLj3EEjf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <cmath>
#define n 10000
#define BLOCK 1000
__global__ void Su(float *a,float *b,float *h)
{
int i = threadIdx.x + blockIdx.x*blockDim.x;
b[i] = (*h)*sqrtf(1 - a[i] * a[i]);
}
int main()
{
float a = 0, b = 1;
float h = ((b - a)*1.0) / n;
float x[n],S[n];//CPU
float *dev_S,*dev_x,*dev_h;//GPU
x[0] = a;
for (int i = 1; i < n; i++)
{
x[i] = i*h;
}
int size = sizeof(float);
cudaMalloc((void**)&dev_S, n*size);
cudaMalloc((void**)&dev_x, n*size);
cudaMalloc((void**)&dev_h, size);
cudaMemcpy(dev_x, &x,n*size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_h, &h, size, cudaMemcpyHostToDevice);
Su<<< BLOCK,n/BLOCK >>>(dev_x,dev_S,dev_h);
cudaDeviceSynchronize();
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess)
{
printf( "GPUassert: %s %s %d\n", cudaGetErrorString(err));
}
cudaMemcpy(&S, dev_S, n*size, cudaMemcpyDeviceToHost);
float p = 0.0;
for (int i = 0; i < n; i++)
{
p=p+S[i];
}
cudaFree(dev_S);
printf("Pi = %f ", 4*p);
getchar();
} | code for sm_80
Function : _Z2SuPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0080*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*00a0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000162000c1e1900 */
/*00b0*/ BSSY B0, 0x1a0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*00c0*/ FFMA R7, -R4, R4, 1 ; /* 0x3f80000004077423 */
/* 0x004fc80000000104 */
/*00d0*/ MUFU.RSQ R8, R7 ; /* 0x0000000700087308 */
/* 0x0000620000001400 */
/*00e0*/ IADD3 R9, R7, -0xd000000, RZ ; /* 0xf300000007097810 */
/* 0x000fc80007ffe0ff */
/*00f0*/ ISETP.GT.U32.AND P0, PT, R9, 0x727fffff, PT ; /* 0x727fffff0900780c */
/* 0x000fda0003f04070 */
/*0100*/ @!P0 BRA 0x150 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0110*/ MOV R9, 0x130 ; /* 0x0000013000097802 */
/* 0x003fe40000000f00 */
/*0120*/ CALL.REL.NOINC 0x1f0 ; /* 0x000000c000007944 */
/* 0x020fea0003c00000 */
/*0130*/ MOV R3, R4 ; /* 0x0000000400037202 */
/* 0x000fe20000000f00 */
/*0140*/ BRA 0x190 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0150*/ FMUL.FTZ R2, R7, R8 ; /* 0x0000000807027220 */
/* 0x003fe40000410000 */
/*0160*/ FMUL.FTZ R8, R8, 0.5 ; /* 0x3f00000008087820 */
/* 0x000fe40000410000 */
/*0170*/ FFMA R3, -R2, R2, R7 ; /* 0x0000000202037223 */
/* 0x000fc80000000107 */
/*0180*/ FFMA R3, R3, R8, R2 ; /* 0x0000000803037223 */
/* 0x000fe40000000002 */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*01b0*/ FMUL R5, R6, R3 ; /* 0x0000000306057220 */
/* 0x020fd20000400000 */
/*01c0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0207 */
/*01d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c0ff */
/*0200*/ @!P0 MOV R2, R7 ; /* 0x0000000700028202 */
/* 0x000fe20000000f00 */
/*0210*/ @!P0 BRA 0x320 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0220*/ FSETP.GEU.FTZ.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720b */
/* 0x000fda0003f1e000 */
/*0230*/ @!P0 MOV R2, 0x7fffffff ; /* 0x7fffffff00028802 */
/* 0x000fe20000000f00 */
/*0240*/ @!P0 BRA 0x320 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0250*/ FSETP.GTU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fda0003f1c200 */
/*0260*/ @P0 FADD.FTZ R2, R7, 1 ; /* 0x3f80000007020421 */
/* 0x000fe20000010000 */
/*0270*/ @P0 BRA 0x320 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0280*/ FSETP.NEU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fda0003f1d200 */
/*0290*/ @P0 FFMA R3, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007030823 */
/* 0x000fc800000000ff */
/*02a0*/ @P0 MUFU.RSQ R2, R3 ; /* 0x0000000300020308 */
/* 0x000e240000001400 */
/*02b0*/ @P0 FMUL.FTZ R4, R3, R2 ; /* 0x0000000203040220 */
/* 0x001fe40000410000 */
/*02c0*/ @P0 FMUL.FTZ R8, R2, 0.5 ; /* 0x3f00000002080820 */
/* 0x000fe20000410000 */
/*02d0*/ @!P0 MOV R2, R7 ; /* 0x0000000700028202 */
/* 0x000fe20000000f00 */
/*02e0*/ @P0 FADD.FTZ R5, -R4, -RZ ; /* 0x800000ff04050221 */
/* 0x000fc80000010100 */
/*02f0*/ @P0 FFMA R5, R4, R5, R3 ; /* 0x0000000504050223 */
/* 0x000fc80000000003 */
/*0300*/ @P0 FFMA R5, R5, R8, R4 ; /* 0x0000000805050223 */
/* 0x000fc80000000004 */
/*0310*/ @P0 FMUL.FTZ R2, R5, 2.3283064365386962891e-10 ; /* 0x2f80000005020820 */
/* 0x000fc80000410000 */
/*0320*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0330*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fe40000000f00 */
/*0340*/ MOV R2, R9 ; /* 0x0000000900027202 */
/* 0x000fc80000000f00 */
/*0350*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffca002007950 */
/* 0x000fea0003c3ffff */
/*0360*/ BRA 0x360; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <cmath>
#define n 10000
#define BLOCK 1000
__global__ void Su(float *a,float *b,float *h)
{
int i = threadIdx.x + blockIdx.x*blockDim.x;
b[i] = (*h)*sqrtf(1 - a[i] * a[i]);
}
int main()
{
float a = 0, b = 1;
float h = ((b - a)*1.0) / n;
float x[n],S[n];//CPU
float *dev_S,*dev_x,*dev_h;//GPU
x[0] = a;
for (int i = 1; i < n; i++)
{
x[i] = i*h;
}
int size = sizeof(float);
cudaMalloc((void**)&dev_S, n*size);
cudaMalloc((void**)&dev_x, n*size);
cudaMalloc((void**)&dev_h, size);
cudaMemcpy(dev_x, &x,n*size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_h, &h, size, cudaMemcpyHostToDevice);
Su<<< BLOCK,n/BLOCK >>>(dev_x,dev_S,dev_h);
cudaDeviceSynchronize();
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess)
{
printf( "GPUassert: %s %s %d\n", cudaGetErrorString(err));
}
cudaMemcpy(&S, dev_S, n*size, cudaMemcpyDeviceToHost);
float p = 0.0;
for (int i = 0; i < n; i++)
{
p=p+S[i];
}
cudaFree(dev_S);
printf("Pi = %f ", 4*p);
getchar();
} | .file "tmpxft_0000b2f3_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z2SuPfS_S_PfS_S_
.type _Z25__device_stub__Z2SuPfS_S_PfS_S_, @function
_Z25__device_stub__Z2SuPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z2SuPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z2SuPfS_S_PfS_S_, .-_Z25__device_stub__Z2SuPfS_S_PfS_S_
.globl _Z2SuPfS_S_
.type _Z2SuPfS_S_, @function
_Z2SuPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z2SuPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z2SuPfS_S_, .-_Z2SuPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "GPUassert: %s %s %d\n"
.LC4:
.string "Pi = %f "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq -77824(%rsp), %r11
.cfi_def_cfa 11, 77840
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2256, %rsp
.cfi_def_cfa_offset 80096
movq %fs:40, %rax
movq %rax, 80072(%rsp)
xorl %eax, %eax
movl $0x38d1b717, 12(%rsp)
movl $0x00000000, 64(%rsp)
movl $1, %eax
movss .LC1(%rip), %xmm1
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, 64(%rsp,%rax,4)
addq $1, %rax
cmpq $10000, %rax
jne .L12
leaq 16(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $40000, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1000, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L13:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L21
.L14:
leaq 40064(%rsp), %rbx
movl $2, %ecx
movl $40000, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 80064(%rsp), %rdx
movl $0x00000000, %ebx
.L15:
movd %ebx, %xmm2
addss (%rax), %xmm2
movd %xmm2, %ebx
addq $4, %rax
cmpq %rdx, %rax
jne .L15
movq 16(%rsp), %rdi
call cudaFree@PLT
movd %ebx, %xmm0
mulss .LC3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
movq 80072(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $80080, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq 32(%rsp), %rdx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z25__device_stub__Z2SuPfS_S_PfS_S_
jmp .L13
.L21:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z2SuPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z2SuPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 953267991
.align 4
.LC3:
.long 1082130432
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <cmath>
#define n 10000
#define BLOCK 1000
__global__ void Su(float *a,float *b,float *h)
{
int i = threadIdx.x + blockIdx.x*blockDim.x;
b[i] = (*h)*sqrtf(1 - a[i] * a[i]);
}
int main()
{
float a = 0, b = 1;
float h = ((b - a)*1.0) / n;
float x[n],S[n];//CPU
float *dev_S,*dev_x,*dev_h;//GPU
x[0] = a;
for (int i = 1; i < n; i++)
{
x[i] = i*h;
}
int size = sizeof(float);
cudaMalloc((void**)&dev_S, n*size);
cudaMalloc((void**)&dev_x, n*size);
cudaMalloc((void**)&dev_h, size);
cudaMemcpy(dev_x, &x,n*size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_h, &h, size, cudaMemcpyHostToDevice);
Su<<< BLOCK,n/BLOCK >>>(dev_x,dev_S,dev_h);
cudaDeviceSynchronize();
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess)
{
printf( "GPUassert: %s %s %d\n", cudaGetErrorString(err));
}
cudaMemcpy(&S, dev_S, n*size, cudaMemcpyDeviceToHost);
float p = 0.0;
for (int i = 0; i < n; i++)
{
p=p+S[i];
}
cudaFree(dev_S);
printf("Pi = %f ", 4*p);
getchar();
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <cmath>
#define n 10000
#define BLOCK 1000
__global__ void Su(float *a,float *b,float *h)
{
int i = threadIdx.x + blockIdx.x*blockDim.x;
b[i] = (*h)*sqrtf(1 - a[i] * a[i]);
}
int main()
{
float a = 0, b = 1;
float h = ((b - a)*1.0) / n;
float x[n],S[n];//CPU
float *dev_S,*dev_x,*dev_h;//GPU
x[0] = a;
for (int i = 1; i < n; i++)
{
x[i] = i*h;
}
int size = sizeof(float);
hipMalloc((void**)&dev_S, n*size);
hipMalloc((void**)&dev_x, n*size);
hipMalloc((void**)&dev_h, size);
hipMemcpy(dev_x, &x,n*size, hipMemcpyHostToDevice);
hipMemcpy(dev_h, &h, size, hipMemcpyHostToDevice);
Su<<< BLOCK,n/BLOCK >>>(dev_x,dev_S,dev_h);
hipDeviceSynchronize();
hipError_t err = hipGetLastError();
if (err != hipSuccess)
{
printf( "GPUassert: %s %s %d\n", hipGetErrorString(err));
}
hipMemcpy(&S, dev_S, n*size, hipMemcpyDeviceToHost);
float p = 0.0;
for (int i = 0; i < n; i++)
{
p=p+S[i];
}
hipFree(dev_S);
printf("Pi = %f ", 4*p);
getchar();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <cmath>
#define n 10000
#define BLOCK 1000
__global__ void Su(float *a,float *b,float *h)
{
int i = threadIdx.x + blockIdx.x*blockDim.x;
b[i] = (*h)*sqrtf(1 - a[i] * a[i]);
}
int main()
{
float a = 0, b = 1;
float h = ((b - a)*1.0) / n;
float x[n],S[n];//CPU
float *dev_S,*dev_x,*dev_h;//GPU
x[0] = a;
for (int i = 1; i < n; i++)
{
x[i] = i*h;
}
int size = sizeof(float);
hipMalloc((void**)&dev_S, n*size);
hipMalloc((void**)&dev_x, n*size);
hipMalloc((void**)&dev_h, size);
hipMemcpy(dev_x, &x,n*size, hipMemcpyHostToDevice);
hipMemcpy(dev_h, &h, size, hipMemcpyHostToDevice);
Su<<< BLOCK,n/BLOCK >>>(dev_x,dev_S,dev_h);
hipDeviceSynchronize();
hipError_t err = hipGetLastError();
if (err != hipSuccess)
{
printf( "GPUassert: %s %s %d\n", hipGetErrorString(err));
}
hipMemcpy(&S, dev_S, n*size, hipMemcpyDeviceToHost);
float p = 0.0;
for (int i = 0; i < n; i++)
{
p=p+S[i];
}
hipFree(dev_S);
printf("Pi = %f ", 4*p);
getchar();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2SuPfS_S_
.globl _Z2SuPfS_S_
.p2align 8
.type _Z2SuPfS_S_,@function
_Z2SuPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
s_waitcnt lgkmcnt(0)
s_load_b32 s1, s[2:3], 0x0
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_fma_f32 v2, -v2, v2, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
v_fma_f32 v6, -v4, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v5, v3, v2
v_cmp_ge_f32_e64 s0, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v3, v4, s0
v_cmp_lt_f32_e64 s0, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v5, s0
v_mul_f32_e32 v4, 0x37800000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_mul_f32_e32 v2, s1, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2SuPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2SuPfS_S_, .Lfunc_end0-_Z2SuPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2SuPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z2SuPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <cmath>
#define n 10000
#define BLOCK 1000
__global__ void Su(float *a,float *b,float *h)
{
int i = threadIdx.x + blockIdx.x*blockDim.x;
b[i] = (*h)*sqrtf(1 - a[i] * a[i]);
}
int main()
{
float a = 0, b = 1;
float h = ((b - a)*1.0) / n;
float x[n],S[n];//CPU
float *dev_S,*dev_x,*dev_h;//GPU
x[0] = a;
for (int i = 1; i < n; i++)
{
x[i] = i*h;
}
int size = sizeof(float);
hipMalloc((void**)&dev_S, n*size);
hipMalloc((void**)&dev_x, n*size);
hipMalloc((void**)&dev_h, size);
hipMemcpy(dev_x, &x,n*size, hipMemcpyHostToDevice);
hipMemcpy(dev_h, &h, size, hipMemcpyHostToDevice);
Su<<< BLOCK,n/BLOCK >>>(dev_x,dev_S,dev_h);
hipDeviceSynchronize();
hipError_t err = hipGetLastError();
if (err != hipSuccess)
{
printf( "GPUassert: %s %s %d\n", hipGetErrorString(err));
}
hipMemcpy(&S, dev_S, n*size, hipMemcpyDeviceToHost);
float p = 0.0;
for (int i = 0; i < n; i++)
{
p=p+S[i];
}
hipFree(dev_S);
printf("Pi = %f ", 4*p);
getchar();
} | .text
.file "kernel.hip"
.globl _Z17__device_stub__SuPfS_S_ # -- Begin function _Z17__device_stub__SuPfS_S_
.p2align 4, 0x90
.type _Z17__device_stub__SuPfS_S_,@function
_Z17__device_stub__SuPfS_S_: # @_Z17__device_stub__SuPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z2SuPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z17__device_stub__SuPfS_S_, .Lfunc_end0-_Z17__device_stub__SuPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x38d1b717 # float 9.99999974E-5
.LCPI1_1:
.long 0x40800000 # float 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $80120, %rsp # imm = 0x138F8
.cfi_def_cfa_offset 80128
movl $953267991, 20(%rsp) # imm = 0x38D1B717
movl $0, 40112(%rsp)
movl $1, %eax
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
mulss %xmm0, %xmm1
movss %xmm1, 40112(%rsp,%rax,4)
incq %rax
cmpq $10000, %rax # imm = 0x2710
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 32(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 32(%rsp), %rdi
leaq 40112(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 20(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967306, %rdx # imm = 0x10000000A
leaq 990(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq 8(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z2SuPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
je .LBB1_6
# %bb.5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_6:
movq 8(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
addss 112(%rsp,%rax,4), %xmm0
incq %rax
cmpq $10000, %rax # imm = 0x2710
jne .LBB1_7
# %bb.8:
movq 8(%rsp), %rdi
movss %xmm0, 16(%rsp) # 4-byte Spill
callq hipFree
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
mulss .LCPI1_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq stdin(%rip), %rdi
callq getc
xorl %eax, %eax
addq $80120, %rsp # imm = 0x138F8
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2SuPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2SuPfS_S_,@object # @_Z2SuPfS_S_
.section .rodata,"a",@progbits
.globl _Z2SuPfS_S_
.p2align 3, 0x0
_Z2SuPfS_S_:
.quad _Z17__device_stub__SuPfS_S_
.size _Z2SuPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPUassert: %s %s %d\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Pi = %f "
.size .L.str.1, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z2SuPfS_S_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__SuPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2SuPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z2SuPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0080*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*00a0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000162000c1e1900 */
/*00b0*/ BSSY B0, 0x1a0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*00c0*/ FFMA R7, -R4, R4, 1 ; /* 0x3f80000004077423 */
/* 0x004fc80000000104 */
/*00d0*/ MUFU.RSQ R8, R7 ; /* 0x0000000700087308 */
/* 0x0000620000001400 */
/*00e0*/ IADD3 R9, R7, -0xd000000, RZ ; /* 0xf300000007097810 */
/* 0x000fc80007ffe0ff */
/*00f0*/ ISETP.GT.U32.AND P0, PT, R9, 0x727fffff, PT ; /* 0x727fffff0900780c */
/* 0x000fda0003f04070 */
/*0100*/ @!P0 BRA 0x150 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0110*/ MOV R9, 0x130 ; /* 0x0000013000097802 */
/* 0x003fe40000000f00 */
/*0120*/ CALL.REL.NOINC 0x1f0 ; /* 0x000000c000007944 */
/* 0x020fea0003c00000 */
/*0130*/ MOV R3, R4 ; /* 0x0000000400037202 */
/* 0x000fe20000000f00 */
/*0140*/ BRA 0x190 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0150*/ FMUL.FTZ R2, R7, R8 ; /* 0x0000000807027220 */
/* 0x003fe40000410000 */
/*0160*/ FMUL.FTZ R8, R8, 0.5 ; /* 0x3f00000008087820 */
/* 0x000fe40000410000 */
/*0170*/ FFMA R3, -R2, R2, R7 ; /* 0x0000000202037223 */
/* 0x000fc80000000107 */
/*0180*/ FFMA R3, R3, R8, R2 ; /* 0x0000000803037223 */
/* 0x000fe40000000002 */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*01b0*/ FMUL R5, R6, R3 ; /* 0x0000000306057220 */
/* 0x020fd20000400000 */
/*01c0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0207 */
/*01d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c0ff */
/*0200*/ @!P0 MOV R2, R7 ; /* 0x0000000700028202 */
/* 0x000fe20000000f00 */
/*0210*/ @!P0 BRA 0x320 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0220*/ FSETP.GEU.FTZ.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720b */
/* 0x000fda0003f1e000 */
/*0230*/ @!P0 MOV R2, 0x7fffffff ; /* 0x7fffffff00028802 */
/* 0x000fe20000000f00 */
/*0240*/ @!P0 BRA 0x320 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0250*/ FSETP.GTU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fda0003f1c200 */
/*0260*/ @P0 FADD.FTZ R2, R7, 1 ; /* 0x3f80000007020421 */
/* 0x000fe20000010000 */
/*0270*/ @P0 BRA 0x320 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0280*/ FSETP.NEU.FTZ.AND P0, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fda0003f1d200 */
/*0290*/ @P0 FFMA R3, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007030823 */
/* 0x000fc800000000ff */
/*02a0*/ @P0 MUFU.RSQ R2, R3 ; /* 0x0000000300020308 */
/* 0x000e240000001400 */
/*02b0*/ @P0 FMUL.FTZ R4, R3, R2 ; /* 0x0000000203040220 */
/* 0x001fe40000410000 */
/*02c0*/ @P0 FMUL.FTZ R8, R2, 0.5 ; /* 0x3f00000002080820 */
/* 0x000fe20000410000 */
/*02d0*/ @!P0 MOV R2, R7 ; /* 0x0000000700028202 */
/* 0x000fe20000000f00 */
/*02e0*/ @P0 FADD.FTZ R5, -R4, -RZ ; /* 0x800000ff04050221 */
/* 0x000fc80000010100 */
/*02f0*/ @P0 FFMA R5, R4, R5, R3 ; /* 0x0000000504050223 */
/* 0x000fc80000000003 */
/*0300*/ @P0 FFMA R5, R5, R8, R4 ; /* 0x0000000805050223 */
/* 0x000fc80000000004 */
/*0310*/ @P0 FMUL.FTZ R2, R5, 2.3283064365386962891e-10 ; /* 0x2f80000005020820 */
/* 0x000fc80000410000 */
/*0320*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0330*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fe40000000f00 */
/*0340*/ MOV R2, R9 ; /* 0x0000000900027202 */
/* 0x000fc80000000f00 */
/*0350*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffca002007950 */
/* 0x000fea0003c3ffff */
/*0360*/ BRA 0x360; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2SuPfS_S_
.globl _Z2SuPfS_S_
.p2align 8
.type _Z2SuPfS_S_,@function
_Z2SuPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
s_waitcnt lgkmcnt(0)
s_load_b32 s1, s[2:3], 0x0
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_fma_f32 v2, -v2, v2, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
v_fma_f32 v6, -v4, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v5, v3, v2
v_cmp_ge_f32_e64 s0, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v3, v4, s0
v_cmp_lt_f32_e64 s0, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v5, s0
v_mul_f32_e32 v4, 0x37800000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_mul_f32_e32 v2, s1, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2SuPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2SuPfS_S_, .Lfunc_end0-_Z2SuPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2SuPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z2SuPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000b2f3_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z2SuPfS_S_PfS_S_
.type _Z25__device_stub__Z2SuPfS_S_PfS_S_, @function
_Z25__device_stub__Z2SuPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z2SuPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z2SuPfS_S_PfS_S_, .-_Z25__device_stub__Z2SuPfS_S_PfS_S_
.globl _Z2SuPfS_S_
.type _Z2SuPfS_S_, @function
_Z2SuPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z2SuPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z2SuPfS_S_, .-_Z2SuPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "GPUassert: %s %s %d\n"
.LC4:
.string "Pi = %f "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq -77824(%rsp), %r11
.cfi_def_cfa 11, 77840
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2256, %rsp
.cfi_def_cfa_offset 80096
movq %fs:40, %rax
movq %rax, 80072(%rsp)
xorl %eax, %eax
movl $0x38d1b717, 12(%rsp)
movl $0x00000000, 64(%rsp)
movl $1, %eax
movss .LC1(%rip), %xmm1
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, 64(%rsp,%rax,4)
addq $1, %rax
cmpq $10000, %rax
jne .L12
leaq 16(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $40000, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1000, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L13:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L21
.L14:
leaq 40064(%rsp), %rbx
movl $2, %ecx
movl $40000, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 80064(%rsp), %rdx
movl $0x00000000, %ebx
.L15:
movd %ebx, %xmm2
addss (%rax), %xmm2
movd %xmm2, %ebx
addq $4, %rax
cmpq %rdx, %rax
jne .L15
movq 16(%rsp), %rdi
call cudaFree@PLT
movd %ebx, %xmm0
mulss .LC3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
movq 80072(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $80080, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq 32(%rsp), %rdx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z25__device_stub__Z2SuPfS_S_PfS_S_
jmp .L13
.L21:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z2SuPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z2SuPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 953267991
.align 4
.LC3:
.long 1082130432
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z17__device_stub__SuPfS_S_ # -- Begin function _Z17__device_stub__SuPfS_S_
.p2align 4, 0x90
.type _Z17__device_stub__SuPfS_S_,@function
_Z17__device_stub__SuPfS_S_: # @_Z17__device_stub__SuPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z2SuPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z17__device_stub__SuPfS_S_, .Lfunc_end0-_Z17__device_stub__SuPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x38d1b717 # float 9.99999974E-5
.LCPI1_1:
.long 0x40800000 # float 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $80120, %rsp # imm = 0x138F8
.cfi_def_cfa_offset 80128
movl $953267991, 20(%rsp) # imm = 0x38D1B717
movl $0, 40112(%rsp)
movl $1, %eax
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
mulss %xmm0, %xmm1
movss %xmm1, 40112(%rsp,%rax,4)
incq %rax
cmpq $10000, %rax # imm = 0x2710
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 32(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 32(%rsp), %rdi
leaq 40112(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 20(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967306, %rdx # imm = 0x10000000A
leaq 990(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq 8(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z2SuPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
je .LBB1_6
# %bb.5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_6:
movq 8(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
addss 112(%rsp,%rax,4), %xmm0
incq %rax
cmpq $10000, %rax # imm = 0x2710
jne .LBB1_7
# %bb.8:
movq 8(%rsp), %rdi
movss %xmm0, 16(%rsp) # 4-byte Spill
callq hipFree
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
mulss .LCPI1_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq stdin(%rip), %rdi
callq getc
xorl %eax, %eax
addq $80120, %rsp # imm = 0x138F8
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2SuPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2SuPfS_S_,@object # @_Z2SuPfS_S_
.section .rodata,"a",@progbits
.globl _Z2SuPfS_S_
.p2align 3, 0x0
_Z2SuPfS_S_:
.quad _Z17__device_stub__SuPfS_S_
.size _Z2SuPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPUassert: %s %s %d\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Pi = %f "
.size .L.str.1, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z2SuPfS_S_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__SuPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2SuPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C" { __global__ void multiply_step(size_t* size, double* in, double* out,double* factor) {
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < size[0];
i += gridDim.x * blockDim.x) {
out[i] = in[i] * factor[0];
}
}
}
extern "C" { __global__ void add_step(size_t* size, double* in, double* in2, double* out) {
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < size[0];
i += gridDim.x * blockDim.x) {
out[i] = in[i] + in2[i];
}
}
}
extern "C" { __global__ void triad_step(size_t* size, double* in, double* in2, double* out,double* factor) {
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < size[0];
i += gridDim.x * blockDim.x) {
out[i] = in[i] + in2[i] * factor[0];
}
}
} | code for sm_80
Function : triad_step
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*0050*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */
/* 0x001fca00078e0200 */
/*0080*/ SHF.R.S32.HI R9, RZ, 0x1f, R7 ; /* 0x0000001fff097819 */
/* 0x000fe40000011407 */
/*0090*/ ISETP.GT.U32.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x004fc80003f04070 */
/*00a0*/ ISETP.GT.U32.AND.EX P0, PT, R5, R9, PT, P0 ; /* 0x000000090500720c */
/* 0x000fda0003f04100 */
/*00b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R16, RZ, RZ, R9 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0009 */
/*00d0*/ IMAD.MOV.U32 R0, RZ, RZ, R7.reuse ; /* 0x000000ffff007224 */
/* 0x100fe400078e0007 */
/*00e0*/ IMAD.MOV.U32 R17, RZ, RZ, R7 ; /* 0x000000ffff117224 */
/* 0x000fe400078e0007 */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff047624 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff057624 */
/* 0x000fc600078e00ff */
/*0110*/ IMAD.SHL.U32 R14, R17.reuse, 0x8, RZ ; /* 0x00000008110e7824 */
/* 0x040fe200078e00ff */
/*0120*/ SHF.L.U64.HI R15, R17, 0x3, R16 ; /* 0x00000003110f7819 */
/* 0x000fe20000010210 */
/*0130*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea6000c1e1b00 */
/*0140*/ IADD3 R10, P1, R14, c[0x0][0x168], RZ ; /* 0x00005a000e0a7a10 */
/* 0x000fc40007f3e0ff */
/*0150*/ IADD3 R12, P0, R14, c[0x0][0x170], RZ ; /* 0x00005c000e0c7a10 */
/* 0x000fe40007f1e0ff */
/*0160*/ IADD3.X R11, R15.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b000f0b7a10 */
/* 0x040fe40000ffe4ff */
/*0170*/ IADD3.X R13, R15, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d000f0d7a10 */
/* 0x000fc800007fe4ff */
/*0180*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1b00 */
/*0190*/ LDG.E.64 R8, [R12.64] ; /* 0x000000040c087981 */
/* 0x000ea2000c1e1b00 */
/*01a0*/ IADD3 R14, P0, R14, c[0x0][0x178], RZ ; /* 0x00005e000e0e7a10 */
/* 0x000fc80007f1e0ff */
/*01b0*/ IADD3.X R15, R15, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000f0f7a10 */
/* 0x000fe200007fe4ff */
/*01c0*/ DFMA R6, R6, R8, R10 ; /* 0x000000080606722b */
/* 0x004e0e000000000a */
/*01d0*/ STG.E.64 [R14.64], R6 ; /* 0x000000060e007986 */
/* 0x0011e8000c101b04 */
/*01e0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1b00 */
/*01f0*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff117624 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD R17, R17, c[0x0][0x0], R0 ; /* 0x0000000011117a24 */
/* 0x000fca00078e0200 */
/*0210*/ SHF.R.S32.HI R16, RZ, 0x1f, R17.reuse ; /* 0x0000001fff107819 */
/* 0x100fe20000011411 */
/*0220*/ IMAD.MOV.U32 R0, RZ, RZ, R17 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0011 */
/*0230*/ ISETP.GT.U32.AND P0, PT, R8, R17, PT ; /* 0x000000110800720c */
/* 0x004fc80003f04070 */
/*0240*/ ISETP.GT.U32.AND.EX P0, PT, R9, R16, PT, P0 ; /* 0x000000100900720c */
/* 0x000fda0003f04100 */
/*0250*/ @P0 BRA 0x110 ; /* 0xfffffeb000000947 */
/* 0x001fea000383ffff */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : add_step
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*0050*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */
/* 0x001fca00078e0200 */
/*0080*/ SHF.R.S32.HI R9, RZ, 0x1f, R7 ; /* 0x0000001fff097819 */
/* 0x000fe40000011407 */
/*0090*/ ISETP.GT.U32.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x004fc80003f04070 */
/*00a0*/ ISETP.GT.U32.AND.EX P0, PT, R5, R9, PT, P0 ; /* 0x000000090500720c */
/* 0x000fda0003f04100 */
/*00b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R0, RZ, RZ, R7.reuse ; /* 0x000000ffff007224 */
/* 0x100fe400078e0007 */
/*00d0*/ IMAD.MOV.U32 R15, RZ, RZ, R7 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e0007 */
/*00e0*/ IMAD.SHL.U32 R12, R15.reuse, 0x8, RZ ; /* 0x000000080f0c7824 */
/* 0x040fe200078e00ff */
/*00f0*/ SHF.L.U64.HI R13, R15, 0x3, R9 ; /* 0x000000030f0d7819 */
/* 0x000fc80000010209 */
/*0100*/ IADD3 R8, P0, R12.reuse, c[0x0][0x170], RZ ; /* 0x00005c000c087a10 */
/* 0x040fe40007f1e0ff */
/*0110*/ IADD3 R10, P1, R12, c[0x0][0x168], RZ ; /* 0x00005a000c0a7a10 */
/* 0x000fe40007f3e0ff */
/*0120*/ IADD3.X R9, R13.reuse, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d000d097a10 */
/* 0x040fe400007fe4ff */
/*0130*/ IADD3.X R11, R13, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b000d0b7a10 */
/* 0x000fc60000ffe4ff */
/*0140*/ LDG.E.64 R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x000ea8000c1e1b00 */
/*0150*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x000ea2000c1e1b00 */
/*0160*/ IADD3 R12, P0, R12, c[0x0][0x178], RZ ; /* 0x00005e000c0c7a10 */
/* 0x000fc80007f1e0ff */
/*0170*/ IADD3.X R13, R13, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000d0d7a10 */
/* 0x000fe200007fe4ff */
/*0180*/ DADD R4, R4, R6 ; /* 0x0000000004047229 */
/* 0x004e0e0000000006 */
/*0190*/ STG.E.64 [R12.64], R4 ; /* 0x000000040c007986 */
/* 0x0011e8000c101b04 */
/*01a0*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1b00 */
/*01b0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff0f7624 */
/* 0x000fc800078e00ff */
/*01c0*/ IMAD R15, R15, c[0x0][0x0], R0 ; /* 0x000000000f0f7a24 */
/* 0x000fc800078e0200 */
/*01d0*/ IMAD.MOV.U32 R0, RZ, RZ, R15.reuse ; /* 0x000000ffff007224 */
/* 0x100fe200078e000f */
/*01e0*/ SHF.R.S32.HI R9, RZ, 0x1f, R15 ; /* 0x0000001fff097819 */
/* 0x000fe4000001140f */
/*01f0*/ ISETP.GT.U32.AND P0, PT, R6, R15, PT ; /* 0x0000000f0600720c */
/* 0x004fc80003f04070 */
/*0200*/ ISETP.GT.U32.AND.EX P0, PT, R7, R9, PT, P0 ; /* 0x000000090700720c */
/* 0x000fda0003f04100 */
/*0210*/ @P0 BRA 0xe0 ; /* 0xfffffec000000947 */
/* 0x001fea000383ffff */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : multiply_step
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*0050*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */
/* 0x001fca00078e0200 */
/*0080*/ SHF.R.S32.HI R9, RZ, 0x1f, R7 ; /* 0x0000001fff097819 */
/* 0x000fe40000011407 */
/*0090*/ ISETP.GT.U32.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x004fc80003f04070 */
/*00a0*/ ISETP.GT.U32.AND.EX P0, PT, R5, R9, PT, P0 ; /* 0x000000090500720c */
/* 0x000fda0003f04100 */
/*00b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R14, RZ, RZ, R9 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0009 */
/*00d0*/ MOV R15, R7 ; /* 0x00000007000f7202 */
/* 0x000fe20000000f00 */
/*00e0*/ IMAD.MOV.U32 R0, RZ, RZ, R7 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0007 */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fc600078e00ff */
/*0110*/ IMAD.SHL.U32 R12, R15.reuse, 0x8, RZ ; /* 0x000000080f0c7824 */
/* 0x040fe200078e00ff */
/*0120*/ SHF.L.U64.HI R13, R15, 0x3, R14 ; /* 0x000000030f0d7819 */
/* 0x000fe2000001020e */
/*0130*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea6000c1e1b00 */
/*0140*/ IADD3 R10, P0, R12, c[0x0][0x168], RZ ; /* 0x00005a000c0a7a10 */
/* 0x000fc80007f1e0ff */
/*0150*/ IADD3.X R11, R13, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b000d0b7a10 */
/* 0x000fca00007fe4ff */
/*0160*/ LDG.E.64 R8, [R10.64] ; /* 0x000000040a087981 */
/* 0x000ea2000c1e1b00 */
/*0170*/ IADD3 R12, P0, R12, c[0x0][0x170], RZ ; /* 0x00005c000c0c7a10 */
/* 0x000fc80007f1e0ff */
/*0180*/ IADD3.X R13, R13, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d000d0d7a10 */
/* 0x000fe200007fe4ff */
/*0190*/ DMUL R6, R6, R8 ; /* 0x0000000806067228 */
/* 0x004e0e0000000000 */
/*01a0*/ STG.E.64 [R12.64], R6 ; /* 0x000000060c007986 */
/* 0x0011e8000c101b04 */
/*01b0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1b00 */
/*01c0*/ MOV R15, c[0x0][0xc] ; /* 0x00000300000f7a02 */
/* 0x000fca0000000f00 */
/*01d0*/ IMAD R15, R15, c[0x0][0x0], R0 ; /* 0x000000000f0f7a24 */
/* 0x000fca00078e0200 */
/*01e0*/ SHF.R.S32.HI R14, RZ, 0x1f, R15.reuse ; /* 0x0000001fff0e7819 */
/* 0x100fe2000001140f */
/*01f0*/ IMAD.MOV.U32 R0, RZ, RZ, R15 ; /* 0x000000ffff007224 */
/* 0x000fe200078e000f */
/*0200*/ ISETP.GT.U32.AND P0, PT, R8, R15, PT ; /* 0x0000000f0800720c */
/* 0x004fc80003f04070 */
/*0210*/ ISETP.GT.U32.AND.EX P0, PT, R9, R14, PT, P0 ; /* 0x0000000e0900720c */
/* 0x000fda0003f04100 */
/*0220*/ @P0 BRA 0x110 ; /* 0xfffffee000000947 */
/* 0x001fea000383ffff */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C" { __global__ void multiply_step(size_t* size, double* in, double* out,double* factor) {
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < size[0];
i += gridDim.x * blockDim.x) {
out[i] = in[i] * factor[0];
}
}
}
extern "C" { __global__ void add_step(size_t* size, double* in, double* in2, double* out) {
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < size[0];
i += gridDim.x * blockDim.x) {
out[i] = in[i] + in2[i];
}
}
}
extern "C" { __global__ void triad_step(size_t* size, double* in, double* in2, double* out,double* factor) {
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < size[0];
i += gridDim.x * blockDim.x) {
out[i] = in[i] + in2[i] * factor[0];
}
}
} | .file "tmpxft_000ab2d5_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z13multiply_stepPmPdS0_S0_PmPdS0_S0_
.type _Z41__device_stub__Z13multiply_stepPmPdS0_S0_PmPdS0_S0_, @function
_Z41__device_stub__Z13multiply_stepPmPdS0_S0_PmPdS0_S0_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq multiply_step(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z13multiply_stepPmPdS0_S0_PmPdS0_S0_, .-_Z41__device_stub__Z13multiply_stepPmPdS0_S0_PmPdS0_S0_
.globl multiply_step
.type multiply_step, @function
multiply_step:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z13multiply_stepPmPdS0_S0_PmPdS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size multiply_step, .-multiply_step
.globl _Z35__device_stub__Z8add_stepPmPdS0_S0_PmPdS0_S0_
.type _Z35__device_stub__Z8add_stepPmPdS0_S0_PmPdS0_S0_, @function
_Z35__device_stub__Z8add_stepPmPdS0_S0_PmPdS0_S0_:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq add_step(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z35__device_stub__Z8add_stepPmPdS0_S0_PmPdS0_S0_, .-_Z35__device_stub__Z8add_stepPmPdS0_S0_PmPdS0_S0_
.globl add_step
.type add_step, @function
add_step:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z8add_stepPmPdS0_S0_PmPdS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size add_step, .-add_step
.globl _Z41__device_stub__Z10triad_stepPmPdS0_S0_S0_PmPdS0_S0_S0_
.type _Z41__device_stub__Z10triad_stepPmPdS0_S0_S0_PmPdS0_S0_S0_, @function
_Z41__device_stub__Z10triad_stepPmPdS0_S0_S0_PmPdS0_S0_S0_:
.LFB2055:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq triad_step(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z41__device_stub__Z10triad_stepPmPdS0_S0_S0_PmPdS0_S0_S0_, .-_Z41__device_stub__Z10triad_stepPmPdS0_S0_S0_PmPdS0_S0_S0_
.globl triad_step
.type triad_step, @function
triad_step:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z10triad_stepPmPdS0_S0_S0_PmPdS0_S0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size triad_step, .-triad_step
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "triad_step"
.LC1:
.string "add_step"
.LC2:
.string "multiply_step"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq triad_step(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq add_step(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq multiply_step(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C" { __global__ void multiply_step(size_t* size, double* in, double* out,double* factor) {
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < size[0];
i += gridDim.x * blockDim.x) {
out[i] = in[i] * factor[0];
}
}
}
extern "C" { __global__ void add_step(size_t* size, double* in, double* in2, double* out) {
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < size[0];
i += gridDim.x * blockDim.x) {
out[i] = in[i] + in2[i];
}
}
}
extern "C" { __global__ void triad_step(size_t* size, double* in, double* in2, double* out,double* factor) {
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < size[0];
i += gridDim.x * blockDim.x) {
out[i] = in[i] + in2[i] * factor[0];
}
}
} | #include <hip/hip_runtime.h>
extern "C" { __global__ void multiply_step(size_t* size, double* in, double* out,double* factor) {
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < size[0];
i += gridDim.x * blockDim.x) {
out[i] = in[i] * factor[0];
}
}
}
extern "C" { __global__ void add_step(size_t* size, double* in, double* in2, double* out) {
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < size[0];
i += gridDim.x * blockDim.x) {
out[i] = in[i] + in2[i];
}
}
}
extern "C" { __global__ void triad_step(size_t* size, double* in, double* in2, double* out,double* factor) {
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < size[0];
i += gridDim.x * blockDim.x) {
out[i] = in[i] + in2[i] * factor[0];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C" { __global__ void multiply_step(size_t* size, double* in, double* out,double* factor) {
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < size[0];
i += gridDim.x * blockDim.x) {
out[i] = in[i] * factor[0];
}
}
}
extern "C" { __global__ void add_step(size_t* size, double* in, double* in2, double* out) {
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < size[0];
i += gridDim.x * blockDim.x) {
out[i] = in[i] + in2[i];
}
}
}
extern "C" { __global__ void triad_step(size_t* size, double* in, double* in2, double* out,double* factor) {
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < size[0];
i += gridDim.x * blockDim.x) {
out[i] = in[i] + in2[i] * factor[0];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected multiply_step
.globl multiply_step
.p2align 8
.type multiply_step,@function
multiply_step:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x2c
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_load_b64 s[2:3], s[2:3], 0x0
s_and_b32 s10, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s11, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[8:9], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s15, s11
s_mul_i32 s1, s11, s10
v_mad_u64_u32 v[3:4], null, s15, s10, v[0:1]
v_mov_b32_e32 v0, 0
s_mov_b32 s10, 0
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[5:6], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v1, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v6, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[3:4]
global_load_b64 v[7:8], v0, s[8:9]
global_load_b64 v[1:2], v[1:2], off
s_or_b32 s10, vcc_lo, s10
s_waitcnt vmcnt(0)
v_mul_f64 v[7:8], v[1:2], v[7:8]
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
v_add_co_u32 v4, s0, s6, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, s7, v6, s0
v_add_nc_u32_e32 v3, s1, v3
global_store_b64 v[4:5], v[7:8], off
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel multiply_step
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size multiply_step, .Lfunc_end0-multiply_step
.section .AMDGPU.csdata,"",@progbits
.text
.protected add_step
.globl add_step
.p2align 8
.type add_step,@function
add_step:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x2c
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_load_b64 s[2:3], s[2:3], 0x0
s_and_b32 s10, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB1_3
s_load_b32 s11, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[8:9], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s15, s11
s_mul_i32 s1, s11, s10
v_mad_u64_u32 v[3:4], null, s15, s10, v[0:1]
s_mov_b32 s10, 0
.p2align 6
.LBB1_2:
v_lshlrev_b64 v[5:6], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v0, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v6, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[3:4]
global_load_b64 v[0:1], v[0:1], off
global_load_b64 v[7:8], v[7:8], off
s_or_b32 s10, vcc_lo, s10
s_waitcnt vmcnt(0)
v_add_f64 v[7:8], v[0:1], v[7:8]
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
v_add_co_u32 v4, s0, s8, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, s9, v6, s0
v_add_nc_u32_e32 v3, s1, v3
global_store_b64 v[4:5], v[7:8], off
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel add_step
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size add_step, .Lfunc_end1-add_step
.section .AMDGPU.csdata,"",@progbits
.text
.protected triad_step
.globl triad_step
.p2align 8
.type triad_step,@function
triad_step:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x34
s_add_u32 s4, s0, 40
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_load_b64 s[2:3], s[2:3], 0x0
s_and_b32 s12, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB2_3
s_load_b32 s13, s[4:5], 0x0
s_load_b256 s[4:11], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s15, s13
s_mul_i32 s1, s13, s12
v_mad_u64_u32 v[3:4], null, s15, s12, v[0:1]
v_mov_b32_e32 v0, 0
s_mov_b32 s12, 0
.p2align 6
.LBB2_2:
v_lshlrev_b64 v[5:6], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v1, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v6, vcc_lo
global_load_b64 v[9:10], v0, s[10:11]
global_load_b64 v[1:2], v[1:2], off
global_load_b64 v[7:8], v[7:8], off
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[3:4]
s_or_b32 s12, vcc_lo, s12
s_waitcnt vmcnt(0)
v_fma_f64 v[7:8], v[7:8], v[9:10], v[1:2]
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
v_add_co_u32 v4, s0, s8, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, s9, v6, s0
v_add_nc_u32_e32 v3, s1, v3
global_store_b64 v[4:5], v[7:8], off
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execnz .LBB2_2
.LBB2_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel triad_step
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size triad_step, .Lfunc_end2-triad_step
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: multiply_step
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: multiply_step.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: add_step
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: add_step.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: triad_step
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: triad_step.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C" { __global__ void multiply_step(size_t* size, double* in, double* out,double* factor) {
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < size[0];
i += gridDim.x * blockDim.x) {
out[i] = in[i] * factor[0];
}
}
}
extern "C" { __global__ void add_step(size_t* size, double* in, double* in2, double* out) {
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < size[0];
i += gridDim.x * blockDim.x) {
out[i] = in[i] + in2[i];
}
}
}
extern "C" { __global__ void triad_step(size_t* size, double* in, double* in2, double* out,double* factor) {
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < size[0];
i += gridDim.x * blockDim.x) {
out[i] = in[i] + in2[i] * factor[0];
}
}
} | .text
.file "kernels.hip"
.globl __device_stub__multiply_step # -- Begin function __device_stub__multiply_step
.p2align 4, 0x90
.type __device_stub__multiply_step,@function
__device_stub__multiply_step: # @__device_stub__multiply_step
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $multiply_step, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__multiply_step, .Lfunc_end0-__device_stub__multiply_step
.cfi_endproc
# -- End function
.globl __device_stub__add_step # -- Begin function __device_stub__add_step
.p2align 4, 0x90
.type __device_stub__add_step,@function
__device_stub__add_step: # @__device_stub__add_step
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $add_step, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size __device_stub__add_step, .Lfunc_end1-__device_stub__add_step
.cfi_endproc
# -- End function
.globl __device_stub__triad_step # -- Begin function __device_stub__triad_step
.p2align 4, 0x90
.type __device_stub__triad_step,@function
__device_stub__triad_step: # @__device_stub__triad_step
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $triad_step, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end2:
.size __device_stub__triad_step, .Lfunc_end2-__device_stub__triad_step
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $multiply_step, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $add_step, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $triad_step, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type multiply_step,@object # @multiply_step
.section .rodata,"a",@progbits
.globl multiply_step
.p2align 3, 0x0
multiply_step:
.quad __device_stub__multiply_step
.size multiply_step, 8
.type add_step,@object # @add_step
.globl add_step
.p2align 3, 0x0
add_step:
.quad __device_stub__add_step
.size add_step, 8
.type triad_step,@object # @triad_step
.globl triad_step
.p2align 3, 0x0
triad_step:
.quad __device_stub__triad_step
.size triad_step, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "multiply_step"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "add_step"
.size .L__unnamed_2, 9
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "triad_step"
.size .L__unnamed_3, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__multiply_step
.addrsig_sym __device_stub__add_step
.addrsig_sym __device_stub__triad_step
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym multiply_step
.addrsig_sym add_step
.addrsig_sym triad_step
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : triad_step
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*0050*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */
/* 0x001fca00078e0200 */
/*0080*/ SHF.R.S32.HI R9, RZ, 0x1f, R7 ; /* 0x0000001fff097819 */
/* 0x000fe40000011407 */
/*0090*/ ISETP.GT.U32.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x004fc80003f04070 */
/*00a0*/ ISETP.GT.U32.AND.EX P0, PT, R5, R9, PT, P0 ; /* 0x000000090500720c */
/* 0x000fda0003f04100 */
/*00b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R16, RZ, RZ, R9 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0009 */
/*00d0*/ IMAD.MOV.U32 R0, RZ, RZ, R7.reuse ; /* 0x000000ffff007224 */
/* 0x100fe400078e0007 */
/*00e0*/ IMAD.MOV.U32 R17, RZ, RZ, R7 ; /* 0x000000ffff117224 */
/* 0x000fe400078e0007 */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff047624 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff057624 */
/* 0x000fc600078e00ff */
/*0110*/ IMAD.SHL.U32 R14, R17.reuse, 0x8, RZ ; /* 0x00000008110e7824 */
/* 0x040fe200078e00ff */
/*0120*/ SHF.L.U64.HI R15, R17, 0x3, R16 ; /* 0x00000003110f7819 */
/* 0x000fe20000010210 */
/*0130*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea6000c1e1b00 */
/*0140*/ IADD3 R10, P1, R14, c[0x0][0x168], RZ ; /* 0x00005a000e0a7a10 */
/* 0x000fc40007f3e0ff */
/*0150*/ IADD3 R12, P0, R14, c[0x0][0x170], RZ ; /* 0x00005c000e0c7a10 */
/* 0x000fe40007f1e0ff */
/*0160*/ IADD3.X R11, R15.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b000f0b7a10 */
/* 0x040fe40000ffe4ff */
/*0170*/ IADD3.X R13, R15, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d000f0d7a10 */
/* 0x000fc800007fe4ff */
/*0180*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1b00 */
/*0190*/ LDG.E.64 R8, [R12.64] ; /* 0x000000040c087981 */
/* 0x000ea2000c1e1b00 */
/*01a0*/ IADD3 R14, P0, R14, c[0x0][0x178], RZ ; /* 0x00005e000e0e7a10 */
/* 0x000fc80007f1e0ff */
/*01b0*/ IADD3.X R15, R15, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000f0f7a10 */
/* 0x000fe200007fe4ff */
/*01c0*/ DFMA R6, R6, R8, R10 ; /* 0x000000080606722b */
/* 0x004e0e000000000a */
/*01d0*/ STG.E.64 [R14.64], R6 ; /* 0x000000060e007986 */
/* 0x0011e8000c101b04 */
/*01e0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1b00 */
/*01f0*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff117624 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD R17, R17, c[0x0][0x0], R0 ; /* 0x0000000011117a24 */
/* 0x000fca00078e0200 */
/*0210*/ SHF.R.S32.HI R16, RZ, 0x1f, R17.reuse ; /* 0x0000001fff107819 */
/* 0x100fe20000011411 */
/*0220*/ IMAD.MOV.U32 R0, RZ, RZ, R17 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0011 */
/*0230*/ ISETP.GT.U32.AND P0, PT, R8, R17, PT ; /* 0x000000110800720c */
/* 0x004fc80003f04070 */
/*0240*/ ISETP.GT.U32.AND.EX P0, PT, R9, R16, PT, P0 ; /* 0x000000100900720c */
/* 0x000fda0003f04100 */
/*0250*/ @P0 BRA 0x110 ; /* 0xfffffeb000000947 */
/* 0x001fea000383ffff */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : add_step
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*0050*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */
/* 0x001fca00078e0200 */
/*0080*/ SHF.R.S32.HI R9, RZ, 0x1f, R7 ; /* 0x0000001fff097819 */
/* 0x000fe40000011407 */
/*0090*/ ISETP.GT.U32.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x004fc80003f04070 */
/*00a0*/ ISETP.GT.U32.AND.EX P0, PT, R5, R9, PT, P0 ; /* 0x000000090500720c */
/* 0x000fda0003f04100 */
/*00b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R0, RZ, RZ, R7.reuse ; /* 0x000000ffff007224 */
/* 0x100fe400078e0007 */
/*00d0*/ IMAD.MOV.U32 R15, RZ, RZ, R7 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e0007 */
/*00e0*/ IMAD.SHL.U32 R12, R15.reuse, 0x8, RZ ; /* 0x000000080f0c7824 */
/* 0x040fe200078e00ff */
/*00f0*/ SHF.L.U64.HI R13, R15, 0x3, R9 ; /* 0x000000030f0d7819 */
/* 0x000fc80000010209 */
/*0100*/ IADD3 R8, P0, R12.reuse, c[0x0][0x170], RZ ; /* 0x00005c000c087a10 */
/* 0x040fe40007f1e0ff */
/*0110*/ IADD3 R10, P1, R12, c[0x0][0x168], RZ ; /* 0x00005a000c0a7a10 */
/* 0x000fe40007f3e0ff */
/*0120*/ IADD3.X R9, R13.reuse, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d000d097a10 */
/* 0x040fe400007fe4ff */
/*0130*/ IADD3.X R11, R13, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b000d0b7a10 */
/* 0x000fc60000ffe4ff */
/*0140*/ LDG.E.64 R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x000ea8000c1e1b00 */
/*0150*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x000ea2000c1e1b00 */
/*0160*/ IADD3 R12, P0, R12, c[0x0][0x178], RZ ; /* 0x00005e000c0c7a10 */
/* 0x000fc80007f1e0ff */
/*0170*/ IADD3.X R13, R13, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000d0d7a10 */
/* 0x000fe200007fe4ff */
/*0180*/ DADD R4, R4, R6 ; /* 0x0000000004047229 */
/* 0x004e0e0000000006 */
/*0190*/ STG.E.64 [R12.64], R4 ; /* 0x000000040c007986 */
/* 0x0011e8000c101b04 */
/*01a0*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1b00 */
/*01b0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff0f7624 */
/* 0x000fc800078e00ff */
/*01c0*/ IMAD R15, R15, c[0x0][0x0], R0 ; /* 0x000000000f0f7a24 */
/* 0x000fc800078e0200 */
/*01d0*/ IMAD.MOV.U32 R0, RZ, RZ, R15.reuse ; /* 0x000000ffff007224 */
/* 0x100fe200078e000f */
/*01e0*/ SHF.R.S32.HI R9, RZ, 0x1f, R15 ; /* 0x0000001fff097819 */
/* 0x000fe4000001140f */
/*01f0*/ ISETP.GT.U32.AND P0, PT, R6, R15, PT ; /* 0x0000000f0600720c */
/* 0x004fc80003f04070 */
/*0200*/ ISETP.GT.U32.AND.EX P0, PT, R7, R9, PT, P0 ; /* 0x000000090700720c */
/* 0x000fda0003f04100 */
/*0210*/ @P0 BRA 0xe0 ; /* 0xfffffec000000947 */
/* 0x001fea000383ffff */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : multiply_step
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*0050*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */
/* 0x001fca00078e0200 */
/*0080*/ SHF.R.S32.HI R9, RZ, 0x1f, R7 ; /* 0x0000001fff097819 */
/* 0x000fe40000011407 */
/*0090*/ ISETP.GT.U32.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x004fc80003f04070 */
/*00a0*/ ISETP.GT.U32.AND.EX P0, PT, R5, R9, PT, P0 ; /* 0x000000090500720c */
/* 0x000fda0003f04100 */
/*00b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R14, RZ, RZ, R9 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0009 */
/*00d0*/ MOV R15, R7 ; /* 0x00000007000f7202 */
/* 0x000fe20000000f00 */
/*00e0*/ IMAD.MOV.U32 R0, RZ, RZ, R7 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0007 */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fc600078e00ff */
/*0110*/ IMAD.SHL.U32 R12, R15.reuse, 0x8, RZ ; /* 0x000000080f0c7824 */
/* 0x040fe200078e00ff */
/*0120*/ SHF.L.U64.HI R13, R15, 0x3, R14 ; /* 0x000000030f0d7819 */
/* 0x000fe2000001020e */
/*0130*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea6000c1e1b00 */
/*0140*/ IADD3 R10, P0, R12, c[0x0][0x168], RZ ; /* 0x00005a000c0a7a10 */
/* 0x000fc80007f1e0ff */
/*0150*/ IADD3.X R11, R13, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b000d0b7a10 */
/* 0x000fca00007fe4ff */
/*0160*/ LDG.E.64 R8, [R10.64] ; /* 0x000000040a087981 */
/* 0x000ea2000c1e1b00 */
/*0170*/ IADD3 R12, P0, R12, c[0x0][0x170], RZ ; /* 0x00005c000c0c7a10 */
/* 0x000fc80007f1e0ff */
/*0180*/ IADD3.X R13, R13, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d000d0d7a10 */
/* 0x000fe200007fe4ff */
/*0190*/ DMUL R6, R6, R8 ; /* 0x0000000806067228 */
/* 0x004e0e0000000000 */
/*01a0*/ STG.E.64 [R12.64], R6 ; /* 0x000000060c007986 */
/* 0x0011e8000c101b04 */
/*01b0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1b00 */
/*01c0*/ MOV R15, c[0x0][0xc] ; /* 0x00000300000f7a02 */
/* 0x000fca0000000f00 */
/*01d0*/ IMAD R15, R15, c[0x0][0x0], R0 ; /* 0x000000000f0f7a24 */
/* 0x000fca00078e0200 */
/*01e0*/ SHF.R.S32.HI R14, RZ, 0x1f, R15.reuse ; /* 0x0000001fff0e7819 */
/* 0x100fe2000001140f */
/*01f0*/ IMAD.MOV.U32 R0, RZ, RZ, R15 ; /* 0x000000ffff007224 */
/* 0x000fe200078e000f */
/*0200*/ ISETP.GT.U32.AND P0, PT, R8, R15, PT ; /* 0x0000000f0800720c */
/* 0x004fc80003f04070 */
/*0210*/ ISETP.GT.U32.AND.EX P0, PT, R9, R14, PT, P0 ; /* 0x0000000e0900720c */
/* 0x000fda0003f04100 */
/*0220*/ @P0 BRA 0x110 ; /* 0xfffffee000000947 */
/* 0x001fea000383ffff */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected multiply_step
.globl multiply_step
.p2align 8
.type multiply_step,@function
multiply_step:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x2c
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_load_b64 s[2:3], s[2:3], 0x0
s_and_b32 s10, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s11, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[8:9], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s15, s11
s_mul_i32 s1, s11, s10
v_mad_u64_u32 v[3:4], null, s15, s10, v[0:1]
v_mov_b32_e32 v0, 0
s_mov_b32 s10, 0
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[5:6], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v1, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v6, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[3:4]
global_load_b64 v[7:8], v0, s[8:9]
global_load_b64 v[1:2], v[1:2], off
s_or_b32 s10, vcc_lo, s10
s_waitcnt vmcnt(0)
v_mul_f64 v[7:8], v[1:2], v[7:8]
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
v_add_co_u32 v4, s0, s6, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, s7, v6, s0
v_add_nc_u32_e32 v3, s1, v3
global_store_b64 v[4:5], v[7:8], off
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel multiply_step
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size multiply_step, .Lfunc_end0-multiply_step
.section .AMDGPU.csdata,"",@progbits
.text
.protected add_step
.globl add_step
.p2align 8
.type add_step,@function
add_step:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x2c
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_load_b64 s[2:3], s[2:3], 0x0
s_and_b32 s10, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB1_3
s_load_b32 s11, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[8:9], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s15, s11
s_mul_i32 s1, s11, s10
v_mad_u64_u32 v[3:4], null, s15, s10, v[0:1]
s_mov_b32 s10, 0
.p2align 6
.LBB1_2:
v_lshlrev_b64 v[5:6], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v0, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v6, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[3:4]
global_load_b64 v[0:1], v[0:1], off
global_load_b64 v[7:8], v[7:8], off
s_or_b32 s10, vcc_lo, s10
s_waitcnt vmcnt(0)
v_add_f64 v[7:8], v[0:1], v[7:8]
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
v_add_co_u32 v4, s0, s8, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, s9, v6, s0
v_add_nc_u32_e32 v3, s1, v3
global_store_b64 v[4:5], v[7:8], off
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel add_step
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size add_step, .Lfunc_end1-add_step
.section .AMDGPU.csdata,"",@progbits
.text
.protected triad_step
.globl triad_step
.p2align 8
.type triad_step,@function
triad_step:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x34
s_add_u32 s4, s0, 40
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_load_b64 s[2:3], s[2:3], 0x0
s_and_b32 s12, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB2_3
s_load_b32 s13, s[4:5], 0x0
s_load_b256 s[4:11], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s15, s13
s_mul_i32 s1, s13, s12
v_mad_u64_u32 v[3:4], null, s15, s12, v[0:1]
v_mov_b32_e32 v0, 0
s_mov_b32 s12, 0
.p2align 6
.LBB2_2:
v_lshlrev_b64 v[5:6], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v1, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v6, vcc_lo
global_load_b64 v[9:10], v0, s[10:11]
global_load_b64 v[1:2], v[1:2], off
global_load_b64 v[7:8], v[7:8], off
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[3:4]
s_or_b32 s12, vcc_lo, s12
s_waitcnt vmcnt(0)
v_fma_f64 v[7:8], v[7:8], v[9:10], v[1:2]
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
v_add_co_u32 v4, s0, s8, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, s9, v6, s0
v_add_nc_u32_e32 v3, s1, v3
global_store_b64 v[4:5], v[7:8], off
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execnz .LBB2_2
.LBB2_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel triad_step
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size triad_step, .Lfunc_end2-triad_step
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: multiply_step
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: multiply_step.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: add_step
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: add_step.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: triad_step
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: triad_step.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ab2d5_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z13multiply_stepPmPdS0_S0_PmPdS0_S0_
.type _Z41__device_stub__Z13multiply_stepPmPdS0_S0_PmPdS0_S0_, @function
_Z41__device_stub__Z13multiply_stepPmPdS0_S0_PmPdS0_S0_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq multiply_step(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z13multiply_stepPmPdS0_S0_PmPdS0_S0_, .-_Z41__device_stub__Z13multiply_stepPmPdS0_S0_PmPdS0_S0_
.globl multiply_step
.type multiply_step, @function
multiply_step:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z13multiply_stepPmPdS0_S0_PmPdS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size multiply_step, .-multiply_step
.globl _Z35__device_stub__Z8add_stepPmPdS0_S0_PmPdS0_S0_
.type _Z35__device_stub__Z8add_stepPmPdS0_S0_PmPdS0_S0_, @function
_Z35__device_stub__Z8add_stepPmPdS0_S0_PmPdS0_S0_:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq add_step(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z35__device_stub__Z8add_stepPmPdS0_S0_PmPdS0_S0_, .-_Z35__device_stub__Z8add_stepPmPdS0_S0_PmPdS0_S0_
.globl add_step
.type add_step, @function
add_step:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z8add_stepPmPdS0_S0_PmPdS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size add_step, .-add_step
.globl _Z41__device_stub__Z10triad_stepPmPdS0_S0_S0_PmPdS0_S0_S0_
.type _Z41__device_stub__Z10triad_stepPmPdS0_S0_S0_PmPdS0_S0_S0_, @function
_Z41__device_stub__Z10triad_stepPmPdS0_S0_S0_PmPdS0_S0_S0_:
.LFB2055:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq triad_step(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z41__device_stub__Z10triad_stepPmPdS0_S0_S0_PmPdS0_S0_S0_, .-_Z41__device_stub__Z10triad_stepPmPdS0_S0_S0_PmPdS0_S0_S0_
.globl triad_step
.type triad_step, @function
triad_step:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z10triad_stepPmPdS0_S0_S0_PmPdS0_S0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size triad_step, .-triad_step
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "triad_step"
.LC1:
.string "add_step"
.LC2:
.string "multiply_step"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq triad_step(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq add_step(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq multiply_step(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernels.hip"
.globl __device_stub__multiply_step # -- Begin function __device_stub__multiply_step
.p2align 4, 0x90
.type __device_stub__multiply_step,@function
__device_stub__multiply_step: # @__device_stub__multiply_step
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $multiply_step, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__multiply_step, .Lfunc_end0-__device_stub__multiply_step
.cfi_endproc
# -- End function
.globl __device_stub__add_step # -- Begin function __device_stub__add_step
.p2align 4, 0x90
.type __device_stub__add_step,@function
__device_stub__add_step: # @__device_stub__add_step
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $add_step, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size __device_stub__add_step, .Lfunc_end1-__device_stub__add_step
.cfi_endproc
# -- End function
.globl __device_stub__triad_step # -- Begin function __device_stub__triad_step
.p2align 4, 0x90
.type __device_stub__triad_step,@function
__device_stub__triad_step: # @__device_stub__triad_step
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $triad_step, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end2:
.size __device_stub__triad_step, .Lfunc_end2-__device_stub__triad_step
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $multiply_step, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $add_step, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $triad_step, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type multiply_step,@object # @multiply_step
.section .rodata,"a",@progbits
.globl multiply_step
.p2align 3, 0x0
multiply_step:
.quad __device_stub__multiply_step
.size multiply_step, 8
.type add_step,@object # @add_step
.globl add_step
.p2align 3, 0x0
add_step:
.quad __device_stub__add_step
.size add_step, 8
.type triad_step,@object # @triad_step
.globl triad_step
.p2align 3, 0x0
triad_step:
.quad __device_stub__triad_step
.size triad_step, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "multiply_step"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "add_step"
.size .L__unnamed_2, 9
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "triad_step"
.size .L__unnamed_3, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__multiply_step
.addrsig_sym __device_stub__add_step
.addrsig_sym __device_stub__triad_step
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym multiply_step
.addrsig_sym add_step
.addrsig_sym triad_step
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include <cuda.h>
#include <curand.h>
#include <curand_kernel.h>
#include <sys/types.h>
#include <unistd.h>
#include <signal.h>
#include <assert.h>
#include <ctype.h>
#include <sys/time.h>
//number of threads PER BLOCK
#define NTHREADS 1024
#define NBLOCKS 1024
#define TOTALTHREADS (NTHREADS*NBLOCKS)
// uncomment the below line to see output of prime numbers
#define DEBUG
void usage();
__global__ void Sieve(char* arr, unsigned long long max, unsigned long long start);
void printResult(char* arr, unsigned long long max);
int main(int argc, char** argv){
unsigned long long max;
int ret;
char* array;
char* cuda_array;
//makes sure user has correct input
if (argc != 2){
usage();
}
max = atoll(argv[1]);
//creates array of size user input on CPU
array = (char*)malloc(sizeof(char) * max);
if(array == NULL){
printf("malloc failed\n");
exit(1);
}
//creates array of size user input on gpu
ret = cudaMalloc(&cuda_array, sizeof(char) * max);
if (ret != cudaSuccess){
printf("cudaMalloc of size %lld failed to return %d\n", max, ret);
exit(1);
}
//memset all values to 1 which is the signature of being prime
memset(array, 1, max);
// 0 and 1 are not prime numbers
array[0] = 0;
array[1] = 0;
//copy contents of CPU array into GPU array
cudaMemcpy((void*)cuda_array, array, max, cudaMemcpyHostToDevice);
unsigned long long sqrtMax;
sqrtMax = (unsigned long long)(sqrt((double)max));
/*can only summon so many threads at one so the for loop allows us to
do so repetitevly*/
for (unsigned long long i=0; i*TOTALTHREADS < sqrtMax; i++)
{
Sieve<<<NBLOCKS, NTHREADS>>>((char *)cuda_array, max, i*TOTALTHREADS);
}
//copy gpu array data to cpu array
cudaMemcpy(array, (void*)cuda_array, max, cudaMemcpyDeviceToHost);
#ifdef DEBUG
printResult((char*)array, max);
#endif
//free gpu array and cpu array
cudaFree((void*)cuda_array);
free(array);
}
//prints out correct usage if user does not provide proper input
void usage(){
printf("usage: ./cudaSieve [maxInt]\n");
exit(1);
}
__global__
void Sieve(char* arr, unsigned long long max, unsigned long long start){
unsigned long long base = blockIdx.x * blockDim.x + threadIdx.x + start;
unsigned long long next;
unsigned long long sqrtMax;
sqrtMax = (unsigned long long)sqrt((double)max);
if (base > sqrtMax){
return;
}
//check if base has been marked yet, if not then mark off all muliples of base
if(arr[base] == 1){
for(next = base + base; next < max; next += base){
arr[next] = 0;
}
}
}
//prints out result of numbers in interval that are prime
void printResult(char* arr, unsigned long long max){
unsigned long long i;
for (i = 0; i < max; i++){
if(arr[i] == 1){
printf("%lld\n", i);
}
}
printf("\n");
} | code for sm_80
Function : _Z5SievePcyy
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.F64.U64 R4, c[0x0][0x168] ; /* 0x00005a0000047b12 */
/* 0x000e220000301800 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0030*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff097424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e660000002100 */
/*0060*/ MUFU.RSQ64H R7, R5 ; /* 0x0000000500077308 */
/* 0x001e220000001c00 */
/*0070*/ IADD3 R6, R5, -0x3500000, RZ ; /* 0xfcb0000005067810 */
/* 0x000fc80007ffe0ff */
/*0080*/ ISETP.GE.U32.AND P0, PT, R6, 0x7ca00000, PT ; /* 0x7ca000000600780c */
/* 0x000fe20003f06070 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R13 ; /* 0x0000000000007a24 */
/* 0x002fe200078e020d */
/*00a0*/ DMUL R2, R6, R6 ; /* 0x0000000606027228 */
/* 0x001e080000000000 */
/*00b0*/ IADD3 R0, P1, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a10 */
/* 0x000fe40007f3e0ff */
/*00c0*/ DFMA R2, R4, -R2, 1 ; /* 0x3ff000000402742b */
/* 0x001e0c0000000802 */
/*00d0*/ DFMA R8, R2, R8, 0.5 ; /* 0x3fe000000208742b */
/* 0x001fc80000000008 */
/*00e0*/ DMUL R2, R6, R2 ; /* 0x0000000206027228 */
/* 0x000e0c0000000000 */
/*00f0*/ DFMA R10, R8, R2, R6 ; /* 0x00000002080a722b */
/* 0x0010640000000006 */
/*0100*/ IMAD.X R3, RZ, RZ, c[0x0][0x174], P1 ; /* 0x00005d00ff037624 */
/* 0x001fc800008e06ff */
/*0110*/ DMUL R8, R4, R10 ; /* 0x0000000a04087228 */
/* 0x002e080000000000 */
/*0120*/ IADD3 R17, R11, -0x100000, RZ ; /* 0xfff000000b117810 */
/* 0x000fe20007ffe0ff */
/*0130*/ IMAD.MOV.U32 R16, RZ, RZ, R10 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000a */
/*0140*/ DFMA R12, R8, -R8, R4 ; /* 0x80000008080c722b */
/* 0x001e0c0000000004 */
/*0150*/ DFMA R14, R12, R16, R8 ; /* 0x000000100c0e722b */
/* 0x0010620000000008 */
/*0160*/ @!P0 BRA 0x190 ; /* 0x0000002000008947 */
/* 0x000ff20003800000 */
/*0170*/ MOV R2, 0x190 ; /* 0x0000019000027802 */
/* 0x000fe40000000f00 */
/*0180*/ CALL.REL.NOINC 0x310 ; /* 0x0000018000007944 */
/* 0x003fea0003c00000 */
/*0190*/ F2I.U64.F64.TRUNC R14, R14 ; /* 0x0000000e000e7311 */
/* 0x002e64000030d800 */
/*01a0*/ ISETP.GT.U32.AND P0, PT, R0, R14, PT ; /* 0x0000000e0000720c */
/* 0x002fc80003f04070 */
/*01b0*/ ISETP.GT.U32.AND.EX P0, PT, R3, R15, PT, P0 ; /* 0x0000000f0300720c */
/* 0x000fda0003f04100 */
/*01c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01d0*/ IADD3 R4, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x000fe20007f1e0ff */
/*01e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*01f0*/ IADD3.X R5, R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003057a10 */
/* 0x000fca00007fe4ff */
/*0200*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1100 */
/*0210*/ ISETP.NE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x004fda0003f05270 */
/*0220*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0230*/ IMAD.SHL.U32 R7, R0.reuse, 0x2, RZ ; /* 0x0000000200077824 */
/* 0x040fe200078e00ff */
/*0240*/ SHF.L.U64.HI R2, R0, 0x1, R3 ; /* 0x0000000100027819 */
/* 0x000fc80000010203 */
/*0250*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fc80003f06070 */
/*0260*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x16c], PT, P0 ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06100 */
/*0270*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0280*/ IADD3 R4, P0, R7.reuse, c[0x0][0x160], RZ ; /* 0x0000580007047a10 */
/* 0x040fe40007f1e0ff */
/*0290*/ IADD3 R7, P1, R7, R0, RZ ; /* 0x0000000007077210 */
/* 0x000fe40007f3e0ff */
/*02a0*/ IADD3.X R5, R2.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590002057a10 */
/* 0x040fe400007fe4ff */
/*02b0*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fe20003f06070 */
/*02c0*/ IMAD.X R2, R2, 0x1, R3, P1 ; /* 0x0000000102027824 */
/* 0x000fe400008e0603 */
/*02d0*/ STG.E.U8 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0003e6000c101104 */
/*02e0*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x16c], PT, P0 ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06100 */
/*02f0*/ @!P0 BRA 0x280 ; /* 0xffffff8000008947 */
/* 0x002fea000383ffff */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ ISETP.GE.U32.AND P0, PT, R6, -0x3400000, PT ; /* 0xfcc000000600780c */
/* 0x000fe20003f06070 */
/*0320*/ IMAD.MOV.U32 R11, RZ, RZ, R17 ; /* 0x000000ffff0b7224 */
/* 0x000fd800078e0011 */
/*0330*/ @!P0 BRA 0x3c0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0340*/ DFMA.RM R8, R12, R10, R8 ; /* 0x0000000a0c08722b */
/* 0x000e140000004008 */
/*0350*/ IADD3 R6, P0, R8, 0x1, RZ ; /* 0x0000000108067810 */
/* 0x001fca0007f1e0ff */
/*0360*/ IMAD.X R7, RZ, RZ, R9, P0 ; /* 0x000000ffff077224 */
/* 0x000fcc00000e0609 */
/*0370*/ DFMA.RP R4, -R8, R6, R4 ; /* 0x000000060804722b */
/* 0x000e0c0000008104 */
/*0380*/ DSETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x001e0c0003f04000 */
/*0390*/ FSEL R6, R6, R8, P0 ; /* 0x0000000806067208 */
/* 0x001fe40000000000 */
/*03a0*/ FSEL R7, R7, R9, P0 ; /* 0x0000000907077208 */
/* 0x000fe20000000000 */
/*03b0*/ BRA 0x550 ; /* 0x0000019000007947 */
/* 0x000fea0003800000 */
/*03c0*/ DSETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x000e1c0003f05000 */
/*03d0*/ @!P0 BRA 0x540 ; /* 0x0000016000008947 */
/* 0x001fea0003800000 */
/*03e0*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f06270 */
/*03f0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff068424 */
/* 0x000fe400078e00ff */
/*0400*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x80000 ; /* 0xfff80000ff078424 */
/* 0x000fe200078e00ff */
/*0410*/ @!P0 BRA 0x550 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0420*/ ISETP.GT.AND P0, PT, R5, 0x7fefffff, PT ; /* 0x7fefffff0500780c */
/* 0x000fda0003f04270 */
/*0430*/ @P0 BRA 0x540 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0440*/ DMUL R4, R4, 8.11296384146066816958e+31 ; /* 0x4690000004047828 */
/* 0x000e220000000000 */
/*0450*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0460*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe400078e00ff */
/*0470*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff0b7424 */
/* 0x000fe200078e00ff */
/*0480*/ MUFU.RSQ64H R7, R5 ; /* 0x0000000500077308 */
/* 0x001e240000001c00 */
/*0490*/ DMUL R8, R6, R6 ; /* 0x0000000606087228 */
/* 0x001e0c0000000000 */
/*04a0*/ DFMA R8, R4, -R8, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000808 */
/*04b0*/ DFMA R10, R8, R10, 0.5 ; /* 0x3fe00000080a742b */
/* 0x001fc8000000000a */
/*04c0*/ DMUL R8, R6, R8 ; /* 0x0000000806087228 */
/* 0x000e0c0000000000 */
/*04d0*/ DFMA R8, R10, R8, R6 ; /* 0x000000080a08722b */
/* 0x001e0c0000000006 */
/*04e0*/ DMUL R6, R4, R8 ; /* 0x0000000804067228 */
/* 0x0010480000000000 */
/*04f0*/ IADD3 R9, R9, -0x100000, RZ ; /* 0xfff0000009097810 */
/* 0x001fe40007ffe0ff */
/*0500*/ DFMA R10, R6, -R6, R4 ; /* 0x80000006060a722b */
/* 0x002e0c0000000004 */
/*0510*/ DFMA R6, R8, R10, R6 ; /* 0x0000000a0806722b */
/* 0x001e140000000006 */
/*0520*/ IADD3 R7, R7, -0x3500000, RZ ; /* 0xfcb0000007077810 */
/* 0x001fe20007ffe0ff */
/*0530*/ BRA 0x550 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0540*/ DADD R6, R4, R4 ; /* 0x0000000004067229 */
/* 0x00004c0000000004 */
/*0550*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0002 */
/*0560*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fe400078e00ff */
/*0570*/ IMAD.MOV.U32 R14, RZ, RZ, R6 ; /* 0x000000ffff0e7224 */
/* 0x002fe400078e0006 */
/*0580*/ IMAD.MOV.U32 R15, RZ, RZ, R7 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e0007 */
/*0590*/ RET.REL.NODEC R4 0x0 ; /* 0xfffffa6004007950 */
/* 0x000fec0003c3ffff */
/*05a0*/ BRA 0x5a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include <cuda.h>
#include <curand.h>
#include <curand_kernel.h>
#include <sys/types.h>
#include <unistd.h>
#include <signal.h>
#include <assert.h>
#include <ctype.h>
#include <sys/time.h>
//number of threads PER BLOCK
#define NTHREADS 1024
#define NBLOCKS 1024
#define TOTALTHREADS (NTHREADS*NBLOCKS)
// uncomment the below line to see output of prime numbers
#define DEBUG
void usage();
__global__ void Sieve(char* arr, unsigned long long max, unsigned long long start);
void printResult(char* arr, unsigned long long max);
int main(int argc, char** argv){
unsigned long long max;
int ret;
char* array;
char* cuda_array;
//makes sure user has correct input
if (argc != 2){
usage();
}
max = atoll(argv[1]);
//creates array of size user input on CPU
array = (char*)malloc(sizeof(char) * max);
if(array == NULL){
printf("malloc failed\n");
exit(1);
}
//creates array of size user input on gpu
ret = cudaMalloc(&cuda_array, sizeof(char) * max);
if (ret != cudaSuccess){
printf("cudaMalloc of size %lld failed to return %d\n", max, ret);
exit(1);
}
//memset all values to 1 which is the signature of being prime
memset(array, 1, max);
// 0 and 1 are not prime numbers
array[0] = 0;
array[1] = 0;
//copy contents of CPU array into GPU array
cudaMemcpy((void*)cuda_array, array, max, cudaMemcpyHostToDevice);
unsigned long long sqrtMax;
sqrtMax = (unsigned long long)(sqrt((double)max));
/*can only summon so many threads at one so the for loop allows us to
do so repetitevly*/
for (unsigned long long i=0; i*TOTALTHREADS < sqrtMax; i++)
{
Sieve<<<NBLOCKS, NTHREADS>>>((char *)cuda_array, max, i*TOTALTHREADS);
}
//copy gpu array data to cpu array
cudaMemcpy(array, (void*)cuda_array, max, cudaMemcpyDeviceToHost);
#ifdef DEBUG
printResult((char*)array, max);
#endif
//free gpu array and cpu array
cudaFree((void*)cuda_array);
free(array);
}
//prints out correct usage if user does not provide proper input
void usage(){
printf("usage: ./cudaSieve [maxInt]\n");
exit(1);
}
__global__
void Sieve(char* arr, unsigned long long max, unsigned long long start){
unsigned long long base = blockIdx.x * blockDim.x + threadIdx.x + start;
unsigned long long next;
unsigned long long sqrtMax;
sqrtMax = (unsigned long long)sqrt((double)max);
if (base > sqrtMax){
return;
}
//check if base has been marked yet, if not then mark off all muliples of base
if(arr[base] == 1){
for(next = base + base; next < max; next += base){
arr[next] = 0;
}
}
}
//prints out result of numbers in interval that are prime
void printResult(char* arr, unsigned long long max){
unsigned long long i;
for (i = 0; i < max; i++){
if(arr[i] == 1){
printf("%lld\n", i);
}
}
printf("\n");
} | .file "tmpxft_00151a5c_00000000-6_cudaSieve.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2289:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2289:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "usage: ./cudaSieve [maxInt]\n"
.text
.globl _Z5usagev
.type _Z5usagev, @function
_Z5usagev:
.LFB2285:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2285:
.size _Z5usagev, .-_Z5usagev
.section .rodata.str1.1
.LC1:
.string "%lld\n"
.LC2:
.string "\n"
.text
.globl _Z11printResultPcy
.type _Z11printResultPcy, @function
_Z11printResultPcy:
.LFB2286:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
testq %rsi, %rsi
je .L6
movq %rdi, %r12
movq %rsi, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r13
jmp .L8
.L7:
addq $1, %rbx
cmpq %rbx, %rbp
je .L6
.L8:
cmpb $1, (%r12,%rbx)
jne .L7
movq %rbx, %rdx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L7
.L6:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2286:
.size _Z11printResultPcy, .-_Z11printResultPcy
.globl _Z26__device_stub__Z5SievePcyyPcyy
.type _Z26__device_stub__Z5SievePcyyPcyy, @function
_Z26__device_stub__Z5SievePcyyPcyy:
.LFB2311:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5SievePcyy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2311:
.size _Z26__device_stub__Z5SievePcyyPcyy, .-_Z26__device_stub__Z5SievePcyyPcyy
.globl _Z5SievePcyy
.type _Z5SievePcyy, @function
_Z5SievePcyy:
.LFB2312:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5SievePcyyPcyy
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2312:
.size _Z5SievePcyy, .-_Z5SievePcyy
.section .rodata.str1.1
.LC3:
.string "malloc failed\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "cudaMalloc of size %lld failed to return %d\n"
.text
.globl main
.type main, @function
main:
.LFB2284:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L39
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtoll@PLT
movq %rax, %rbp
movq %rax, %rdi
call malloc@PLT
movq %rax, %r13
testq %rax, %rax
je .L40
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L41
movq %rbp, %rcx
movq %rbp, %rdx
movl $1, %esi
movq %r13, %rdi
call __memset_chk@PLT
movb $0, 0(%r13)
movb $0, 1(%r13)
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testq %rbp, %rbp
js .L24
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
.L25:
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L37
sqrtsd %xmm0, %xmm0
.L28:
comisd .LC6(%rip), %xmm0
jnb .L29
cvttsd2siq %xmm0, %r12
.L30:
testq %r12, %r12
je .L31
movl $0, %ebx
jmp .L33
.L39:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L42
call _Z5usagev
.L42:
call __stack_chk_fail@PLT
.L40:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %ecx
movq %rbp, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L24:
movq %rbp, %rax
shrq %rax
movq %rbp, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L25
.L37:
call sqrt@PLT
jmp .L28
.L29:
subsd .LC6(%rip), %xmm0
cvttsd2siq %xmm0, %r12
btcq $63, %r12
jmp .L30
.L32:
addq $1048576, %rbx
cmpq %r12, %rbx
jnb .L31
.L33:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L32
movq %rbx, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z5SievePcyyPcyy
jmp .L32
.L31:
movl $2, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %rbp, %rsi
movq %r13, %rdi
call _Z11printResultPcy
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2284:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z5SievePcyy"
.LC8:
.string "precalc_xorwow_matrix"
.LC9:
.string "precalc_xorwow_offset_matrix"
.LC10:
.string "mrg32k3aM1"
.LC11:
.string "mrg32k3aM2"
.LC12:
.string "mrg32k3aM1SubSeq"
.LC13:
.string "mrg32k3aM2SubSeq"
.LC14:
.string "mrg32k3aM1Seq"
.LC15:
.string "mrg32k3aM2Seq"
.LC16:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2314:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z5SievePcyy(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2314:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1138753536
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include <cuda.h>
#include <curand.h>
#include <curand_kernel.h>
#include <sys/types.h>
#include <unistd.h>
#include <signal.h>
#include <assert.h>
#include <ctype.h>
#include <sys/time.h>
//number of threads PER BLOCK
#define NTHREADS 1024
#define NBLOCKS 1024
#define TOTALTHREADS (NTHREADS*NBLOCKS)
// uncomment the below line to see output of prime numbers
#define DEBUG
void usage();
__global__ void Sieve(char* arr, unsigned long long max, unsigned long long start);
void printResult(char* arr, unsigned long long max);
int main(int argc, char** argv){
unsigned long long max;
int ret;
char* array;
char* cuda_array;
//makes sure user has correct input
if (argc != 2){
usage();
}
max = atoll(argv[1]);
//creates array of size user input on CPU
array = (char*)malloc(sizeof(char) * max);
if(array == NULL){
printf("malloc failed\n");
exit(1);
}
//creates array of size user input on gpu
ret = cudaMalloc(&cuda_array, sizeof(char) * max);
if (ret != cudaSuccess){
printf("cudaMalloc of size %lld failed to return %d\n", max, ret);
exit(1);
}
//memset all values to 1 which is the signature of being prime
memset(array, 1, max);
// 0 and 1 are not prime numbers
array[0] = 0;
array[1] = 0;
//copy contents of CPU array into GPU array
cudaMemcpy((void*)cuda_array, array, max, cudaMemcpyHostToDevice);
unsigned long long sqrtMax;
sqrtMax = (unsigned long long)(sqrt((double)max));
/*can only summon so many threads at one so the for loop allows us to
do so repetitevly*/
for (unsigned long long i=0; i*TOTALTHREADS < sqrtMax; i++)
{
Sieve<<<NBLOCKS, NTHREADS>>>((char *)cuda_array, max, i*TOTALTHREADS);
}
//copy gpu array data to cpu array
cudaMemcpy(array, (void*)cuda_array, max, cudaMemcpyDeviceToHost);
#ifdef DEBUG
printResult((char*)array, max);
#endif
//free gpu array and cpu array
cudaFree((void*)cuda_array);
free(array);
}
//prints out correct usage if user does not provide proper input
void usage(){
printf("usage: ./cudaSieve [maxInt]\n");
exit(1);
}
__global__
void Sieve(char* arr, unsigned long long max, unsigned long long start){
unsigned long long base = blockIdx.x * blockDim.x + threadIdx.x + start;
unsigned long long next;
unsigned long long sqrtMax;
sqrtMax = (unsigned long long)sqrt((double)max);
if (base > sqrtMax){
return;
}
//check if base has been marked yet, if not then mark off all muliples of base
if(arr[base] == 1){
for(next = base + base; next < max; next += base){
arr[next] = 0;
}
}
}
//prints out result of numbers in interval that are prime
void printResult(char* arr, unsigned long long max){
unsigned long long i;
for (i = 0; i < max; i++){
if(arr[i] == 1){
printf("%lld\n", i);
}
}
printf("\n");
} | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <sys/types.h>
#include <unistd.h>
#include <signal.h>
#include <assert.h>
#include <ctype.h>
#include <sys/time.h>
//number of threads PER BLOCK
#define NTHREADS 1024
#define NBLOCKS 1024
#define TOTALTHREADS (NTHREADS*NBLOCKS)
// uncomment the below line to see output of prime numbers
#define DEBUG
void usage();
__global__ void Sieve(char* arr, unsigned long long max, unsigned long long start);
void printResult(char* arr, unsigned long long max);
int main(int argc, char** argv){
unsigned long long max;
int ret;
char* array;
char* cuda_array;
//makes sure user has correct input
if (argc != 2){
usage();
}
max = atoll(argv[1]);
//creates array of size user input on CPU
array = (char*)malloc(sizeof(char) * max);
if(array == NULL){
printf("malloc failed\n");
exit(1);
}
//creates array of size user input on gpu
ret = hipMalloc(&cuda_array, sizeof(char) * max);
if (ret != hipSuccess){
printf("hipMalloc of size %lld failed to return %d\n", max, ret);
exit(1);
}
//memset all values to 1 which is the signature of being prime
memset(array, 1, max);
// 0 and 1 are not prime numbers
array[0] = 0;
array[1] = 0;
//copy contents of CPU array into GPU array
hipMemcpy((void*)cuda_array, array, max, hipMemcpyHostToDevice);
unsigned long long sqrtMax;
sqrtMax = (unsigned long long)(sqrt((double)max));
/*can only summon so many threads at one so the for loop allows us to
do so repetitevly*/
for (unsigned long long i=0; i*TOTALTHREADS < sqrtMax; i++)
{
Sieve<<<NBLOCKS, NTHREADS>>>((char *)cuda_array, max, i*TOTALTHREADS);
}
//copy gpu array data to cpu array
hipMemcpy(array, (void*)cuda_array, max, hipMemcpyDeviceToHost);
#ifdef DEBUG
printResult((char*)array, max);
#endif
//free gpu array and cpu array
hipFree((void*)cuda_array);
free(array);
}
//prints out correct usage if user does not provide proper input
void usage(){
printf("usage: ./cudaSieve [maxInt]\n");
exit(1);
}
__global__
void Sieve(char* arr, unsigned long long max, unsigned long long start){
unsigned long long base = blockIdx.x * blockDim.x + threadIdx.x + start;
unsigned long long next;
unsigned long long sqrtMax;
sqrtMax = (unsigned long long)sqrt((double)max);
if (base > sqrtMax){
return;
}
//check if base has been marked yet, if not then mark off all muliples of base
if(arr[base] == 1){
for(next = base + base; next < max; next += base){
arr[next] = 0;
}
}
}
//prints out result of numbers in interval that are prime
void printResult(char* arr, unsigned long long max){
unsigned long long i;
for (i = 0; i < max; i++){
if(arr[i] == 1){
printf("%lld\n", i);
}
}
printf("\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <sys/types.h>
#include <unistd.h>
#include <signal.h>
#include <assert.h>
#include <ctype.h>
#include <sys/time.h>
//number of threads PER BLOCK
#define NTHREADS 1024
#define NBLOCKS 1024
#define TOTALTHREADS (NTHREADS*NBLOCKS)
// uncomment the below line to see output of prime numbers
#define DEBUG
void usage();
__global__ void Sieve(char* arr, unsigned long long max, unsigned long long start);
void printResult(char* arr, unsigned long long max);
int main(int argc, char** argv){
unsigned long long max;
int ret;
char* array;
char* cuda_array;
//makes sure user has correct input
if (argc != 2){
usage();
}
max = atoll(argv[1]);
//creates array of size user input on CPU
array = (char*)malloc(sizeof(char) * max);
if(array == NULL){
printf("malloc failed\n");
exit(1);
}
//creates array of size user input on gpu
ret = hipMalloc(&cuda_array, sizeof(char) * max);
if (ret != hipSuccess){
printf("hipMalloc of size %lld failed to return %d\n", max, ret);
exit(1);
}
//memset all values to 1 which is the signature of being prime
memset(array, 1, max);
// 0 and 1 are not prime numbers
array[0] = 0;
array[1] = 0;
//copy contents of CPU array into GPU array
hipMemcpy((void*)cuda_array, array, max, hipMemcpyHostToDevice);
unsigned long long sqrtMax;
sqrtMax = (unsigned long long)(sqrt((double)max));
/*can only summon so many threads at one so the for loop allows us to
do so repetitevly*/
for (unsigned long long i=0; i*TOTALTHREADS < sqrtMax; i++)
{
Sieve<<<NBLOCKS, NTHREADS>>>((char *)cuda_array, max, i*TOTALTHREADS);
}
//copy gpu array data to cpu array
hipMemcpy(array, (void*)cuda_array, max, hipMemcpyDeviceToHost);
#ifdef DEBUG
printResult((char*)array, max);
#endif
//free gpu array and cpu array
hipFree((void*)cuda_array);
free(array);
}
//prints out correct usage if user does not provide proper input
void usage(){
printf("usage: ./cudaSieve [maxInt]\n");
exit(1);
}
__global__
void Sieve(char* arr, unsigned long long max, unsigned long long start){
unsigned long long base = blockIdx.x * blockDim.x + threadIdx.x + start;
unsigned long long next;
unsigned long long sqrtMax;
sqrtMax = (unsigned long long)sqrt((double)max);
if (base > sqrtMax){
return;
}
//check if base has been marked yet, if not then mark off all muliples of base
if(arr[base] == 1){
for(next = base + base; next < max; next += base){
arr[next] = 0;
}
}
}
//prints out result of numbers in interval that are prime
void printResult(char* arr, unsigned long long max){
unsigned long long i;
for (i = 0; i < max; i++){
if(arr[i] == 1){
printf("%lld\n", i);
}
}
printf("\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5SievePcyy
.globl _Z5SievePcyy
.p2align 8
.type _Z5SievePcyy,@function
_Z5SievePcyy:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
v_cvt_f64_u32_e32 v[1:2], s5
v_cvt_f64_u32_e32 v[3:4], s4
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[1:2], v[1:2], 32
v_add_f64 v[1:2], v[1:2], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[1:2]
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
s_and_b32 s3, vcc_lo, exec_lo
s_cselect_b32 s3, 0xffffff80, 0
v_lshlrev_b32_e32 v3, 8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[1:2], v[1:2], v3
v_rsq_f64_e32 v[3:4], v[1:2]
v_cmp_class_f64_e64 vcc_lo, v[1:2], 0x260
s_waitcnt_depctr 0xfff
v_mul_f64 v[5:6], v[1:2], v[3:4]
v_mul_f64 v[3:4], v[3:4], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[3:4], v[5:6], 0.5
v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
v_fma_f64 v[3:4], v[3:4], v[7:8], v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[5:6], v[5:6], v[1:2]
v_fma_f64 v[5:6], v[7:8], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[5:6], v[5:6], v[1:2]
v_fma_f64 v[3:4], v[7:8], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[3:4], v[3:4], s3
v_dual_cndmask_b32 v2, v4, v2 :: v_dual_cndmask_b32 v1, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_trunc_f64_e32 v[1:2], v[1:2]
v_ldexp_f64 v[3:4], v[1:2], 0xffffffe0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f64_e32 v[3:4], v[3:4]
v_fma_f64 v[1:2], v[3:4], 0xc1f00000, v[1:2]
v_cvt_u32_f64_e32 v3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_u32_f64_e32 v2, v[1:2]
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
v_add_co_u32 v0, s2, v4, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, 0, s7, s2
s_mov_b32 s2, exec_lo
v_cmpx_le_u64_e64 v[0:1], v[2:3]
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_u8 v4, v[2:3], off
v_lshlrev_b64 v[2:3], 1, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[2:3]
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e64 s0, 1, v4
s_and_b32 s0, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v4, 0
s_mov_b32 s0, 0
.LBB0_3:
v_add_co_u32 v5, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, v3, v1, vcc_lo
global_store_b8 v[5:6], v4, off
v_cmp_le_u64_e32 vcc_lo, s[4:5], v[2:3]
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5SievePcyy
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5SievePcyy, .Lfunc_end0-_Z5SievePcyy
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5SievePcyy
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5SievePcyy.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <sys/types.h>
#include <unistd.h>
#include <signal.h>
#include <assert.h>
#include <ctype.h>
#include <sys/time.h>
//number of threads PER BLOCK
#define NTHREADS 1024
#define NBLOCKS 1024
#define TOTALTHREADS (NTHREADS*NBLOCKS)
// uncomment the below line to see output of prime numbers
#define DEBUG
void usage();
__global__ void Sieve(char* arr, unsigned long long max, unsigned long long start);
void printResult(char* arr, unsigned long long max);
int main(int argc, char** argv){
unsigned long long max;
int ret;
char* array;
char* cuda_array;
//makes sure user has correct input
if (argc != 2){
usage();
}
max = atoll(argv[1]);
//creates array of size user input on CPU
array = (char*)malloc(sizeof(char) * max);
if(array == NULL){
printf("malloc failed\n");
exit(1);
}
//creates array of size user input on gpu
ret = hipMalloc(&cuda_array, sizeof(char) * max);
if (ret != hipSuccess){
printf("hipMalloc of size %lld failed to return %d\n", max, ret);
exit(1);
}
//memset all values to 1 which is the signature of being prime
memset(array, 1, max);
// 0 and 1 are not prime numbers
array[0] = 0;
array[1] = 0;
//copy contents of CPU array into GPU array
hipMemcpy((void*)cuda_array, array, max, hipMemcpyHostToDevice);
unsigned long long sqrtMax;
sqrtMax = (unsigned long long)(sqrt((double)max));
/*can only summon so many threads at one so the for loop allows us to
do so repetitevly*/
for (unsigned long long i=0; i*TOTALTHREADS < sqrtMax; i++)
{
Sieve<<<NBLOCKS, NTHREADS>>>((char *)cuda_array, max, i*TOTALTHREADS);
}
//copy gpu array data to cpu array
hipMemcpy(array, (void*)cuda_array, max, hipMemcpyDeviceToHost);
#ifdef DEBUG
printResult((char*)array, max);
#endif
//free gpu array and cpu array
hipFree((void*)cuda_array);
free(array);
}
//prints out correct usage if user does not provide proper input
void usage(){
printf("usage: ./cudaSieve [maxInt]\n");
exit(1);
}
__global__
void Sieve(char* arr, unsigned long long max, unsigned long long start){
unsigned long long base = blockIdx.x * blockDim.x + threadIdx.x + start;
unsigned long long next;
unsigned long long sqrtMax;
sqrtMax = (unsigned long long)sqrt((double)max);
if (base > sqrtMax){
return;
}
//check if base has been marked yet, if not then mark off all muliples of base
if(arr[base] == 1){
for(next = base + base; next < max; next += base){
arr[next] = 0;
}
}
}
//prints out result of numbers in interval that are prime
void printResult(char* arr, unsigned long long max){
unsigned long long i;
for (i = 0; i < max; i++){
if(arr[i] == 1){
printf("%lld\n", i);
}
}
printf("\n");
} | .text
.file "cudaSieve.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI0_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_2:
.quad 0x43e0000000000000 # double 9.2233720368547758E+18
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB0_1
# %bb.3:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtoll
movq %rax, %rbx
movq %rax, %rdi
callq malloc
testq %rax, %rax
je .LBB0_4
# %bb.5:
movq %rax, %r14
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB0_20
# %bb.6:
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
callq memset@PLT
movw $0, (%r14)
movq (%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rbx, %xmm1
punpckldq .LCPI0_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI0_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB0_8
# %bb.7:
sqrtsd %xmm0, %xmm0
jmp .LBB0_9
.LBB0_8: # %call.sqrt
callq sqrt
.LBB0_9: # %.split
cvttsd2si %xmm0, %rax
movq %rax, %rcx
sarq $63, %rcx
subsd .LCPI0_2(%rip), %xmm0
cvttsd2si %xmm0, %rbp
andq %rcx, %rbp
orq %rax, %rbp
je .LBB0_14
# %bb.10: # %.lr.ph
movabsq $4294968320, %r15 # imm = 0x100000400
xorl %r12d, %r12d
leaq 80(%rsp), %r13
jmp .LBB0_11
.p2align 4, 0x90
.LBB0_13: # in Loop: Header=BB0_11 Depth=1
addq $1048576, %r12 # imm = 0x100000
cmpq %rbp, %r12
jae .LBB0_14
.LBB0_11: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_13
# %bb.12: # in Loop: Header=BB0_11 Depth=1
movq (%rsp), %rax
movq %rax, 72(%rsp)
movq %rbx, 64(%rsp)
movq %r12, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z5SievePcyy, %edi
movq %r13, %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB0_13
.LBB0_14: # %._crit_edge
movq (%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testq %rbx, %rbx
je .LBB0_19
# %bb.15: # %.lr.ph.i.preheader
xorl %r15d, %r15d
jmp .LBB0_16
.p2align 4, 0x90
.LBB0_18: # in Loop: Header=BB0_16 Depth=1
incq %r15
cmpq %r15, %rbx
je .LBB0_19
.LBB0_16: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
cmpb $1, (%r14,%r15)
jne .LBB0_18
# %bb.17: # in Loop: Header=BB0_16 Depth=1
movl $.L.str.3, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
jmp .LBB0_18
.LBB0_19: # %_Z11printResultPcy.exit
movl $10, %edi
callq putchar@PLT
movq (%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 160
movl $.Lstr.1, %edi
jmp .LBB0_2
.LBB0_4:
movl $.Lstr, %edi
.LBB0_2:
callq puts@PLT
movl $1, %edi
callq exit
.LBB0_20:
movl $.L.str.1, %edi
movq %rbx, %rsi
movl %eax, %edx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z5usagev # -- Begin function _Z5usagev
.p2align 4, 0x90
.type _Z5usagev,@function
_Z5usagev: # @_Z5usagev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z5usagev, .Lfunc_end1-_Z5usagev
.cfi_endproc
# -- End function
.globl _Z20__device_stub__SievePcyy # -- Begin function _Z20__device_stub__SievePcyy
.p2align 4, 0x90
.type _Z20__device_stub__SievePcyy,@function
_Z20__device_stub__SievePcyy: # @_Z20__device_stub__SievePcyy
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5SievePcyy, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z20__device_stub__SievePcyy, .Lfunc_end2-_Z20__device_stub__SievePcyy
.cfi_endproc
# -- End function
.globl _Z11printResultPcy # -- Begin function _Z11printResultPcy
.p2align 4, 0x90
.type _Z11printResultPcy,@function
_Z11printResultPcy: # @_Z11printResultPcy
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB3_6
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
xorl %r15d, %r15d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_4: # in Loop: Header=BB3_2 Depth=1
incq %r15
cmpq %r15, %rbx
je .LBB3_5
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpb $1, (%r14,%r15)
jne .LBB3_4
# %bb.3: # in Loop: Header=BB3_2 Depth=1
movl $.L.str.3, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
jmp .LBB3_4
.LBB3_5:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB3_6: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end3:
.size _Z11printResultPcy, .Lfunc_end3-_Z11printResultPcy
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5SievePcyy, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "hipMalloc of size %lld failed to return %d\n"
.size .L.str.1, 44
.type _Z5SievePcyy,@object # @_Z5SievePcyy
.section .rodata,"a",@progbits
.globl _Z5SievePcyy
.p2align 3, 0x0
_Z5SievePcyy:
.quad _Z20__device_stub__SievePcyy
.size _Z5SievePcyy, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%lld\n"
.size .L.str.3, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5SievePcyy"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "malloc failed"
.size .Lstr, 14
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "usage: ./cudaSieve [maxInt]"
.size .Lstr.1, 28
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__SievePcyy
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5SievePcyy
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5SievePcyy
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.F64.U64 R4, c[0x0][0x168] ; /* 0x00005a0000047b12 */
/* 0x000e220000301800 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0030*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff097424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e660000002100 */
/*0060*/ MUFU.RSQ64H R7, R5 ; /* 0x0000000500077308 */
/* 0x001e220000001c00 */
/*0070*/ IADD3 R6, R5, -0x3500000, RZ ; /* 0xfcb0000005067810 */
/* 0x000fc80007ffe0ff */
/*0080*/ ISETP.GE.U32.AND P0, PT, R6, 0x7ca00000, PT ; /* 0x7ca000000600780c */
/* 0x000fe20003f06070 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R13 ; /* 0x0000000000007a24 */
/* 0x002fe200078e020d */
/*00a0*/ DMUL R2, R6, R6 ; /* 0x0000000606027228 */
/* 0x001e080000000000 */
/*00b0*/ IADD3 R0, P1, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a10 */
/* 0x000fe40007f3e0ff */
/*00c0*/ DFMA R2, R4, -R2, 1 ; /* 0x3ff000000402742b */
/* 0x001e0c0000000802 */
/*00d0*/ DFMA R8, R2, R8, 0.5 ; /* 0x3fe000000208742b */
/* 0x001fc80000000008 */
/*00e0*/ DMUL R2, R6, R2 ; /* 0x0000000206027228 */
/* 0x000e0c0000000000 */
/*00f0*/ DFMA R10, R8, R2, R6 ; /* 0x00000002080a722b */
/* 0x0010640000000006 */
/*0100*/ IMAD.X R3, RZ, RZ, c[0x0][0x174], P1 ; /* 0x00005d00ff037624 */
/* 0x001fc800008e06ff */
/*0110*/ DMUL R8, R4, R10 ; /* 0x0000000a04087228 */
/* 0x002e080000000000 */
/*0120*/ IADD3 R17, R11, -0x100000, RZ ; /* 0xfff000000b117810 */
/* 0x000fe20007ffe0ff */
/*0130*/ IMAD.MOV.U32 R16, RZ, RZ, R10 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000a */
/*0140*/ DFMA R12, R8, -R8, R4 ; /* 0x80000008080c722b */
/* 0x001e0c0000000004 */
/*0150*/ DFMA R14, R12, R16, R8 ; /* 0x000000100c0e722b */
/* 0x0010620000000008 */
/*0160*/ @!P0 BRA 0x190 ; /* 0x0000002000008947 */
/* 0x000ff20003800000 */
/*0170*/ MOV R2, 0x190 ; /* 0x0000019000027802 */
/* 0x000fe40000000f00 */
/*0180*/ CALL.REL.NOINC 0x310 ; /* 0x0000018000007944 */
/* 0x003fea0003c00000 */
/*0190*/ F2I.U64.F64.TRUNC R14, R14 ; /* 0x0000000e000e7311 */
/* 0x002e64000030d800 */
/*01a0*/ ISETP.GT.U32.AND P0, PT, R0, R14, PT ; /* 0x0000000e0000720c */
/* 0x002fc80003f04070 */
/*01b0*/ ISETP.GT.U32.AND.EX P0, PT, R3, R15, PT, P0 ; /* 0x0000000f0300720c */
/* 0x000fda0003f04100 */
/*01c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01d0*/ IADD3 R4, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x000fe20007f1e0ff */
/*01e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*01f0*/ IADD3.X R5, R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003057a10 */
/* 0x000fca00007fe4ff */
/*0200*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1100 */
/*0210*/ ISETP.NE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x004fda0003f05270 */
/*0220*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0230*/ IMAD.SHL.U32 R7, R0.reuse, 0x2, RZ ; /* 0x0000000200077824 */
/* 0x040fe200078e00ff */
/*0240*/ SHF.L.U64.HI R2, R0, 0x1, R3 ; /* 0x0000000100027819 */
/* 0x000fc80000010203 */
/*0250*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fc80003f06070 */
/*0260*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x16c], PT, P0 ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06100 */
/*0270*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0280*/ IADD3 R4, P0, R7.reuse, c[0x0][0x160], RZ ; /* 0x0000580007047a10 */
/* 0x040fe40007f1e0ff */
/*0290*/ IADD3 R7, P1, R7, R0, RZ ; /* 0x0000000007077210 */
/* 0x000fe40007f3e0ff */
/*02a0*/ IADD3.X R5, R2.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590002057a10 */
/* 0x040fe400007fe4ff */
/*02b0*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fe20003f06070 */
/*02c0*/ IMAD.X R2, R2, 0x1, R3, P1 ; /* 0x0000000102027824 */
/* 0x000fe400008e0603 */
/*02d0*/ STG.E.U8 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0003e6000c101104 */
/*02e0*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x16c], PT, P0 ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06100 */
/*02f0*/ @!P0 BRA 0x280 ; /* 0xffffff8000008947 */
/* 0x002fea000383ffff */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ ISETP.GE.U32.AND P0, PT, R6, -0x3400000, PT ; /* 0xfcc000000600780c */
/* 0x000fe20003f06070 */
/*0320*/ IMAD.MOV.U32 R11, RZ, RZ, R17 ; /* 0x000000ffff0b7224 */
/* 0x000fd800078e0011 */
/*0330*/ @!P0 BRA 0x3c0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0340*/ DFMA.RM R8, R12, R10, R8 ; /* 0x0000000a0c08722b */
/* 0x000e140000004008 */
/*0350*/ IADD3 R6, P0, R8, 0x1, RZ ; /* 0x0000000108067810 */
/* 0x001fca0007f1e0ff */
/*0360*/ IMAD.X R7, RZ, RZ, R9, P0 ; /* 0x000000ffff077224 */
/* 0x000fcc00000e0609 */
/*0370*/ DFMA.RP R4, -R8, R6, R4 ; /* 0x000000060804722b */
/* 0x000e0c0000008104 */
/*0380*/ DSETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x001e0c0003f04000 */
/*0390*/ FSEL R6, R6, R8, P0 ; /* 0x0000000806067208 */
/* 0x001fe40000000000 */
/*03a0*/ FSEL R7, R7, R9, P0 ; /* 0x0000000907077208 */
/* 0x000fe20000000000 */
/*03b0*/ BRA 0x550 ; /* 0x0000019000007947 */
/* 0x000fea0003800000 */
/*03c0*/ DSETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x000e1c0003f05000 */
/*03d0*/ @!P0 BRA 0x540 ; /* 0x0000016000008947 */
/* 0x001fea0003800000 */
/*03e0*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f06270 */
/*03f0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff068424 */
/* 0x000fe400078e00ff */
/*0400*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x80000 ; /* 0xfff80000ff078424 */
/* 0x000fe200078e00ff */
/*0410*/ @!P0 BRA 0x550 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0420*/ ISETP.GT.AND P0, PT, R5, 0x7fefffff, PT ; /* 0x7fefffff0500780c */
/* 0x000fda0003f04270 */
/*0430*/ @P0 BRA 0x540 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0440*/ DMUL R4, R4, 8.11296384146066816958e+31 ; /* 0x4690000004047828 */
/* 0x000e220000000000 */
/*0450*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*0460*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe400078e00ff */
/*0470*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff0b7424 */
/* 0x000fe200078e00ff */
/*0480*/ MUFU.RSQ64H R7, R5 ; /* 0x0000000500077308 */
/* 0x001e240000001c00 */
/*0490*/ DMUL R8, R6, R6 ; /* 0x0000000606087228 */
/* 0x001e0c0000000000 */
/*04a0*/ DFMA R8, R4, -R8, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000808 */
/*04b0*/ DFMA R10, R8, R10, 0.5 ; /* 0x3fe00000080a742b */
/* 0x001fc8000000000a */
/*04c0*/ DMUL R8, R6, R8 ; /* 0x0000000806087228 */
/* 0x000e0c0000000000 */
/*04d0*/ DFMA R8, R10, R8, R6 ; /* 0x000000080a08722b */
/* 0x001e0c0000000006 */
/*04e0*/ DMUL R6, R4, R8 ; /* 0x0000000804067228 */
/* 0x0010480000000000 */
/*04f0*/ IADD3 R9, R9, -0x100000, RZ ; /* 0xfff0000009097810 */
/* 0x001fe40007ffe0ff */
/*0500*/ DFMA R10, R6, -R6, R4 ; /* 0x80000006060a722b */
/* 0x002e0c0000000004 */
/*0510*/ DFMA R6, R8, R10, R6 ; /* 0x0000000a0806722b */
/* 0x001e140000000006 */
/*0520*/ IADD3 R7, R7, -0x3500000, RZ ; /* 0xfcb0000007077810 */
/* 0x001fe20007ffe0ff */
/*0530*/ BRA 0x550 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0540*/ DADD R6, R4, R4 ; /* 0x0000000004067229 */
/* 0x00004c0000000004 */
/*0550*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0002 */
/*0560*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fe400078e00ff */
/*0570*/ IMAD.MOV.U32 R14, RZ, RZ, R6 ; /* 0x000000ffff0e7224 */
/* 0x002fe400078e0006 */
/*0580*/ IMAD.MOV.U32 R15, RZ, RZ, R7 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e0007 */
/*0590*/ RET.REL.NODEC R4 0x0 ; /* 0xfffffa6004007950 */
/* 0x000fec0003c3ffff */
/*05a0*/ BRA 0x5a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5SievePcyy
.globl _Z5SievePcyy
.p2align 8
.type _Z5SievePcyy,@function
_Z5SievePcyy:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
v_cvt_f64_u32_e32 v[1:2], s5
v_cvt_f64_u32_e32 v[3:4], s4
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[1:2], v[1:2], 32
v_add_f64 v[1:2], v[1:2], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[1:2]
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
s_and_b32 s3, vcc_lo, exec_lo
s_cselect_b32 s3, 0xffffff80, 0
v_lshlrev_b32_e32 v3, 8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[1:2], v[1:2], v3
v_rsq_f64_e32 v[3:4], v[1:2]
v_cmp_class_f64_e64 vcc_lo, v[1:2], 0x260
s_waitcnt_depctr 0xfff
v_mul_f64 v[5:6], v[1:2], v[3:4]
v_mul_f64 v[3:4], v[3:4], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[3:4], v[5:6], 0.5
v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
v_fma_f64 v[3:4], v[3:4], v[7:8], v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[5:6], v[5:6], v[1:2]
v_fma_f64 v[5:6], v[7:8], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[5:6], v[5:6], v[1:2]
v_fma_f64 v[3:4], v[7:8], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[3:4], v[3:4], s3
v_dual_cndmask_b32 v2, v4, v2 :: v_dual_cndmask_b32 v1, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_trunc_f64_e32 v[1:2], v[1:2]
v_ldexp_f64 v[3:4], v[1:2], 0xffffffe0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f64_e32 v[3:4], v[3:4]
v_fma_f64 v[1:2], v[3:4], 0xc1f00000, v[1:2]
v_cvt_u32_f64_e32 v3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_u32_f64_e32 v2, v[1:2]
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
v_add_co_u32 v0, s2, v4, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, 0, s7, s2
s_mov_b32 s2, exec_lo
v_cmpx_le_u64_e64 v[0:1], v[2:3]
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_u8 v4, v[2:3], off
v_lshlrev_b64 v[2:3], 1, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[2:3]
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e64 s0, 1, v4
s_and_b32 s0, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v4, 0
s_mov_b32 s0, 0
.LBB0_3:
v_add_co_u32 v5, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, v3, v1, vcc_lo
global_store_b8 v[5:6], v4, off
v_cmp_le_u64_e32 vcc_lo, s[4:5], v[2:3]
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5SievePcyy
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5SievePcyy, .Lfunc_end0-_Z5SievePcyy
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5SievePcyy
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5SievePcyy.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00151a5c_00000000-6_cudaSieve.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2289:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2289:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "usage: ./cudaSieve [maxInt]\n"
.text
.globl _Z5usagev
.type _Z5usagev, @function
_Z5usagev:
.LFB2285:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2285:
.size _Z5usagev, .-_Z5usagev
.section .rodata.str1.1
.LC1:
.string "%lld\n"
.LC2:
.string "\n"
.text
.globl _Z11printResultPcy
.type _Z11printResultPcy, @function
_Z11printResultPcy:
.LFB2286:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
testq %rsi, %rsi
je .L6
movq %rdi, %r12
movq %rsi, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r13
jmp .L8
.L7:
addq $1, %rbx
cmpq %rbx, %rbp
je .L6
.L8:
cmpb $1, (%r12,%rbx)
jne .L7
movq %rbx, %rdx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L7
.L6:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2286:
.size _Z11printResultPcy, .-_Z11printResultPcy
.globl _Z26__device_stub__Z5SievePcyyPcyy
.type _Z26__device_stub__Z5SievePcyyPcyy, @function
_Z26__device_stub__Z5SievePcyyPcyy:
.LFB2311:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5SievePcyy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2311:
.size _Z26__device_stub__Z5SievePcyyPcyy, .-_Z26__device_stub__Z5SievePcyyPcyy
.globl _Z5SievePcyy
.type _Z5SievePcyy, @function
_Z5SievePcyy:
.LFB2312:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5SievePcyyPcyy
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2312:
.size _Z5SievePcyy, .-_Z5SievePcyy
.section .rodata.str1.1
.LC3:
.string "malloc failed\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "cudaMalloc of size %lld failed to return %d\n"
.text
.globl main
.type main, @function
main:
.LFB2284:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L39
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtoll@PLT
movq %rax, %rbp
movq %rax, %rdi
call malloc@PLT
movq %rax, %r13
testq %rax, %rax
je .L40
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L41
movq %rbp, %rcx
movq %rbp, %rdx
movl $1, %esi
movq %r13, %rdi
call __memset_chk@PLT
movb $0, 0(%r13)
movb $0, 1(%r13)
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testq %rbp, %rbp
js .L24
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
.L25:
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L37
sqrtsd %xmm0, %xmm0
.L28:
comisd .LC6(%rip), %xmm0
jnb .L29
cvttsd2siq %xmm0, %r12
.L30:
testq %r12, %r12
je .L31
movl $0, %ebx
jmp .L33
.L39:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L42
call _Z5usagev
.L42:
call __stack_chk_fail@PLT
.L40:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %ecx
movq %rbp, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L24:
movq %rbp, %rax
shrq %rax
movq %rbp, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L25
.L37:
call sqrt@PLT
jmp .L28
.L29:
subsd .LC6(%rip), %xmm0
cvttsd2siq %xmm0, %r12
btcq $63, %r12
jmp .L30
.L32:
addq $1048576, %rbx
cmpq %r12, %rbx
jnb .L31
.L33:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L32
movq %rbx, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z5SievePcyyPcyy
jmp .L32
.L31:
movl $2, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %rbp, %rsi
movq %r13, %rdi
call _Z11printResultPcy
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2284:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z5SievePcyy"
.LC8:
.string "precalc_xorwow_matrix"
.LC9:
.string "precalc_xorwow_offset_matrix"
.LC10:
.string "mrg32k3aM1"
.LC11:
.string "mrg32k3aM2"
.LC12:
.string "mrg32k3aM1SubSeq"
.LC13:
.string "mrg32k3aM2SubSeq"
.LC14:
.string "mrg32k3aM1Seq"
.LC15:
.string "mrg32k3aM2Seq"
.LC16:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2314:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z5SievePcyy(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2314:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1138753536
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaSieve.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI0_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_2:
.quad 0x43e0000000000000 # double 9.2233720368547758E+18
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB0_1
# %bb.3:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtoll
movq %rax, %rbx
movq %rax, %rdi
callq malloc
testq %rax, %rax
je .LBB0_4
# %bb.5:
movq %rax, %r14
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB0_20
# %bb.6:
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
callq memset@PLT
movw $0, (%r14)
movq (%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rbx, %xmm1
punpckldq .LCPI0_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI0_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB0_8
# %bb.7:
sqrtsd %xmm0, %xmm0
jmp .LBB0_9
.LBB0_8: # %call.sqrt
callq sqrt
.LBB0_9: # %.split
cvttsd2si %xmm0, %rax
movq %rax, %rcx
sarq $63, %rcx
subsd .LCPI0_2(%rip), %xmm0
cvttsd2si %xmm0, %rbp
andq %rcx, %rbp
orq %rax, %rbp
je .LBB0_14
# %bb.10: # %.lr.ph
movabsq $4294968320, %r15 # imm = 0x100000400
xorl %r12d, %r12d
leaq 80(%rsp), %r13
jmp .LBB0_11
.p2align 4, 0x90
.LBB0_13: # in Loop: Header=BB0_11 Depth=1
addq $1048576, %r12 # imm = 0x100000
cmpq %rbp, %r12
jae .LBB0_14
.LBB0_11: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_13
# %bb.12: # in Loop: Header=BB0_11 Depth=1
movq (%rsp), %rax
movq %rax, 72(%rsp)
movq %rbx, 64(%rsp)
movq %r12, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z5SievePcyy, %edi
movq %r13, %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB0_13
.LBB0_14: # %._crit_edge
movq (%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testq %rbx, %rbx
je .LBB0_19
# %bb.15: # %.lr.ph.i.preheader
xorl %r15d, %r15d
jmp .LBB0_16
.p2align 4, 0x90
.LBB0_18: # in Loop: Header=BB0_16 Depth=1
incq %r15
cmpq %r15, %rbx
je .LBB0_19
.LBB0_16: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
cmpb $1, (%r14,%r15)
jne .LBB0_18
# %bb.17: # in Loop: Header=BB0_16 Depth=1
movl $.L.str.3, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
jmp .LBB0_18
.LBB0_19: # %_Z11printResultPcy.exit
movl $10, %edi
callq putchar@PLT
movq (%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 160
movl $.Lstr.1, %edi
jmp .LBB0_2
.LBB0_4:
movl $.Lstr, %edi
.LBB0_2:
callq puts@PLT
movl $1, %edi
callq exit
.LBB0_20:
movl $.L.str.1, %edi
movq %rbx, %rsi
movl %eax, %edx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z5usagev # -- Begin function _Z5usagev
.p2align 4, 0x90
.type _Z5usagev,@function
_Z5usagev: # @_Z5usagev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z5usagev, .Lfunc_end1-_Z5usagev
.cfi_endproc
# -- End function
.globl _Z20__device_stub__SievePcyy # -- Begin function _Z20__device_stub__SievePcyy
.p2align 4, 0x90
.type _Z20__device_stub__SievePcyy,@function
_Z20__device_stub__SievePcyy: # @_Z20__device_stub__SievePcyy
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5SievePcyy, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z20__device_stub__SievePcyy, .Lfunc_end2-_Z20__device_stub__SievePcyy
.cfi_endproc
# -- End function
.globl _Z11printResultPcy # -- Begin function _Z11printResultPcy
.p2align 4, 0x90
.type _Z11printResultPcy,@function
_Z11printResultPcy: # @_Z11printResultPcy
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB3_6
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
xorl %r15d, %r15d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_4: # in Loop: Header=BB3_2 Depth=1
incq %r15
cmpq %r15, %rbx
je .LBB3_5
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpb $1, (%r14,%r15)
jne .LBB3_4
# %bb.3: # in Loop: Header=BB3_2 Depth=1
movl $.L.str.3, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
jmp .LBB3_4
.LBB3_5:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB3_6: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end3:
.size _Z11printResultPcy, .Lfunc_end3-_Z11printResultPcy
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5SievePcyy, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "hipMalloc of size %lld failed to return %d\n"
.size .L.str.1, 44
.type _Z5SievePcyy,@object # @_Z5SievePcyy
.section .rodata,"a",@progbits
.globl _Z5SievePcyy
.p2align 3, 0x0
_Z5SievePcyy:
.quad _Z20__device_stub__SievePcyy
.size _Z5SievePcyy, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%lld\n"
.size .L.str.3, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5SievePcyy"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "malloc failed"
.size .Lstr, 14
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "usage: ./cudaSieve [maxInt]"
.size .Lstr.1, 28
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__SievePcyy
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5SievePcyy
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #ifndef __CUDA_RUNTIME_H__
#include "cuda_runtime.h"
#endif // !"cuda_runtime.h"
#ifndef __DEVICE_LAUNCH_PARAMETERS_H__
#include "device_launch_parameters.h"
#endif // !__DEVICE_LAUNCH_PARAMETERS_H__
// Constants
const int MAX_N = (2147483648 / 8); // N = maxInt32 / 8 = (2147483648 / 8) = 268,435,456 queens
// GPU-local variables
__device__ int board[MAX_N] = { 0 }; // list of queen positions, where board[x] = y
__device__ short occ_col[MAX_N]; // column occupancy (unique x)
__device__ short occ_row[MAX_N]; // row occupancy (unique y)
__device__ short occ_adiag[2 * MAX_N]; // ascending diagonal occupancy (unique x+y)
__device__ short occ_ddiag[2 * MAX_N]; // decending diagonal occupancy (unique x-y)
__device__ short collision_flag[1] = { 0 }; // Flag raised if any 2 Queens can attack each other
using namespace std;
// Adds queen to occupancy arrays and checks for collisions
__device__ void register_q(int x, int y, int num_queens)
{
if (occ_col[x] != 0 || occ_row[y] != 0 || occ_adiag[(x + y)] != 0 || occ_ddiag[num_queens + (x - y)] != 0) {
collision_flag[0] = 1;
}
occ_col[x] = 1;
occ_row[y] = 1;
occ_adiag[x + y] = 1;
occ_ddiag[num_queens + (x - y)] = 1;
return;
}
// Equation 1
__device__ void case1(int i, int N) {
int x, y, x1, y1;
x = i;
y = 2 * i;
x1 = N / 2 + i;
y1 = 2 * i - 1;
register_q(x - 1, y - 1, N);
register_q(x1 - 1, y1 - 1, N);
board[x - 1] = y - 1;
board[x1 - 1] = y1 - 1;
return;
}
// Equation 2
__device__ void case2(int i, int N) {
int x, y, x1, y1;
x = i;
y = 1 + ((2 * (i - 1) + N / 2 - 1) % N);
x1 = N + 1 - i;
y1 = N - ((2 * (i - 1) + N / 2 - 1) % N);
register_q(x - 1, y - 1, N);
register_q(x1 - 1, y1 - 1, N);
board[x - 1] = y - 1;
board[x1 - 1] = y1 - 1;
return;
}
// Main GPU kernel
__global__ void N_Queens_Kernel(int num_queens)
{
// Each thread places 2 queens
int i = (blockDim.x * blockIdx.x + threadIdx.x) + 1;
if (i > (num_queens - num_queens % 2) / 2) {
return;
}
// Case 1, N is even and (N-2) mod 6 is not 0
if (num_queens % 2 == 0 && (num_queens - 2) % 6 != 0) {
case1(i, num_queens);
}
// Case 2, N is even and N mod 6 is not 0
else if (num_queens % 2 == 0 && num_queens % 6 != 0) {
case2(i, num_queens);
}
// Case 3, N is odd, and (N-3) mod 6 is not 0
else if ((num_queens - 1) % 2 == 0 && (num_queens - 3) % 6 != 0) {
case1(i, num_queens - 1);
if (blockIdx.x == 0 && threadIdx.x == 0) {
board[num_queens - 1] = num_queens - 1;
}
}
// Case 4, N is odd and (N-1) mod 6 is not 0
else if ((num_queens - 1) % 2 == 0 && (num_queens - 1) % 6 != 0) {
case2(i, num_queens - 1);
if (blockIdx.x == 0 && threadIdx.x == 0) {
board[num_queens - 1] = num_queens - 1;
}
}
return;
}
// Resets board and occupancy grid
__global__ void clearBuffers(int num_queens) {
int i = (blockDim.x * blockIdx.x + threadIdx.x);
board[2 * i] = 0;
board[2 * i + 1] = 0;
occ_col[2 * i] = 0;
occ_col[2 * i + 1] = 0;
occ_row[2 * i] = 0;
occ_row[2 * i + 1] = 0;
occ_adiag[2 * i] = 0;
occ_adiag[2 * i + 1] = 0;
occ_adiag[2 * i + num_queens] = 0;
occ_adiag[2 * i + 1 + num_queens] = 0;
occ_ddiag[2 * i] = 0;
occ_ddiag[2 * i + 1] = 0;
occ_ddiag[2 * i + num_queens] = 0;
occ_ddiag[2 * i + 1 + num_queens] = 0;
if (blockIdx.x == 0 && threadIdx.x == 0) {
collision_flag[0] = 0;
}
}
// Returns symbol addresses for interface variables
int* getBoardAddr() {
int* board_ptr = 0;
cudaGetSymbolAddress((void**)&board_ptr, board);
return board_ptr;
}
int* getFlagAddr() {
int* cflag_ptr = 0;
cudaGetSymbolAddress((void**)&cflag_ptr, collision_flag);
return cflag_ptr;
}
int getMaxN() {
int N = MAX_N;
return N;
}
// Frees all memory prior to shutdown
void memPurge() {
cudaFree(board);
cudaFree(collision_flag);
cudaFree(occ_col);
cudaFree(occ_row);
cudaFree(occ_adiag);
cudaFree(occ_ddiag);
} | .file "tmpxft_0000fc39_00000000-6_gpu_code.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2036:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2036:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10register_qiii
.type _Z10register_qiii, @function
_Z10register_qiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10register_qiii, .-_Z10register_qiii
.globl _Z5case1ii
.type _Z5case1ii, @function
_Z5case1ii:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z5case1ii, .-_Z5case1ii
.globl _Z5case2ii
.type _Z5case2ii, @function
_Z5case2ii:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z5case2ii, .-_Z5case2ii
.globl _Z12getBoardAddrv
.type _Z12getBoardAddrv, @function
_Z12getBoardAddrv:
.LFB2030:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq %rsp, %rdi
leaq _ZL5board(%rip), %rsi
call cudaGetSymbolAddress@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L12
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2030:
.size _Z12getBoardAddrv, .-_Z12getBoardAddrv
.globl _Z11getFlagAddrv
.type _Z11getFlagAddrv, @function
_Z11getFlagAddrv:
.LFB2031:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq %rsp, %rdi
leaq _ZL14collision_flag(%rip), %rsi
call cudaGetSymbolAddress@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L16
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2031:
.size _Z11getFlagAddrv, .-_Z11getFlagAddrv
.globl _Z7getMaxNv
.type _Z7getMaxNv, @function
_Z7getMaxNv:
.LFB2032:
.cfi_startproc
endbr64
movl $268435456, %eax
ret
.cfi_endproc
.LFE2032:
.size _Z7getMaxNv, .-_Z7getMaxNv
.globl _Z8memPurgev
.type _Z8memPurgev, @function
_Z8memPurgev:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL5board(%rip), %rdi
call cudaFree@PLT
leaq _ZL14collision_flag(%rip), %rdi
call cudaFree@PLT
leaq _ZL7occ_col(%rip), %rdi
call cudaFree@PLT
leaq _ZL7occ_row(%rip), %rdi
call cudaFree@PLT
leaq _ZL9occ_adiag(%rip), %rdi
call cudaFree@PLT
leaq _ZL9occ_ddiag(%rip), %rdi
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _Z8memPurgev, .-_Z8memPurgev
.globl _Z34__device_stub__Z15N_Queens_Kernelii
.type _Z34__device_stub__Z15N_Queens_Kernelii, @function
_Z34__device_stub__Z15N_Queens_Kernelii:
.LFB2058:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15N_Queens_Kerneli(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z34__device_stub__Z15N_Queens_Kernelii, .-_Z34__device_stub__Z15N_Queens_Kernelii
.globl _Z15N_Queens_Kerneli
.type _Z15N_Queens_Kerneli, @function
_Z15N_Queens_Kerneli:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z15N_Queens_Kernelii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z15N_Queens_Kerneli, .-_Z15N_Queens_Kerneli
.globl _Z31__device_stub__Z12clearBuffersii
.type _Z31__device_stub__Z12clearBuffersii, @function
_Z31__device_stub__Z12clearBuffersii:
.LFB2060:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12clearBuffersi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z31__device_stub__Z12clearBuffersii, .-_Z31__device_stub__Z12clearBuffersii
.globl _Z12clearBuffersi
.type _Z12clearBuffersi, @function
_Z12clearBuffersi:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12clearBuffersii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z12clearBuffersi, .-_Z12clearBuffersi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12clearBuffersi"
.LC1:
.string "_Z15N_Queens_Kerneli"
.LC2:
.string "board"
.LC3:
.string "occ_col"
.LC4:
.string "occ_row"
.LC5:
.string "occ_adiag"
.LC6:
.string "occ_ddiag"
.LC7:
.string "collision_flag"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12clearBuffersi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15N_Queens_Kerneli(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1073741824, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5board(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $536870912, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7occ_col(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $536870912, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7occ_row(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1073741824, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9occ_adiag(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1073741824, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9occ_ddiag(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL14collision_flag(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL14collision_flag
.comm _ZL14collision_flag,2,2
.local _ZL9occ_ddiag
.comm _ZL9occ_ddiag,1073741824,32
.local _ZL9occ_adiag
.comm _ZL9occ_adiag,1073741824,32
.local _ZL7occ_row
.comm _ZL7occ_row,536870912,32
.local _ZL7occ_col
.comm _ZL7occ_col,536870912,32
.local _ZL5board
.comm _ZL5board,1073741824,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #ifndef __CUDA_RUNTIME_H__
#include "cuda_runtime.h"
#endif // !"cuda_runtime.h"
#ifndef __DEVICE_LAUNCH_PARAMETERS_H__
#include "device_launch_parameters.h"
#endif // !__DEVICE_LAUNCH_PARAMETERS_H__
// Constants
const int MAX_N = (2147483648 / 8); // N = maxInt32 / 8 = (2147483648 / 8) = 268,435,456 queens
// GPU-local variables
__device__ int board[MAX_N] = { 0 }; // list of queen positions, where board[x] = y
__device__ short occ_col[MAX_N]; // column occupancy (unique x)
__device__ short occ_row[MAX_N]; // row occupancy (unique y)
__device__ short occ_adiag[2 * MAX_N]; // ascending diagonal occupancy (unique x+y)
__device__ short occ_ddiag[2 * MAX_N]; // decending diagonal occupancy (unique x-y)
__device__ short collision_flag[1] = { 0 }; // Flag raised if any 2 Queens can attack each other
using namespace std;
// Adds queen to occupancy arrays and checks for collisions
__device__ void register_q(int x, int y, int num_queens)
{
if (occ_col[x] != 0 || occ_row[y] != 0 || occ_adiag[(x + y)] != 0 || occ_ddiag[num_queens + (x - y)] != 0) {
collision_flag[0] = 1;
}
occ_col[x] = 1;
occ_row[y] = 1;
occ_adiag[x + y] = 1;
occ_ddiag[num_queens + (x - y)] = 1;
return;
}
// Equation 1
__device__ void case1(int i, int N) {
int x, y, x1, y1;
x = i;
y = 2 * i;
x1 = N / 2 + i;
y1 = 2 * i - 1;
register_q(x - 1, y - 1, N);
register_q(x1 - 1, y1 - 1, N);
board[x - 1] = y - 1;
board[x1 - 1] = y1 - 1;
return;
}
// Equation 2
__device__ void case2(int i, int N) {
int x, y, x1, y1;
x = i;
y = 1 + ((2 * (i - 1) + N / 2 - 1) % N);
x1 = N + 1 - i;
y1 = N - ((2 * (i - 1) + N / 2 - 1) % N);
register_q(x - 1, y - 1, N);
register_q(x1 - 1, y1 - 1, N);
board[x - 1] = y - 1;
board[x1 - 1] = y1 - 1;
return;
}
// Main GPU kernel
__global__ void N_Queens_Kernel(int num_queens)
{
// Each thread places 2 queens
int i = (blockDim.x * blockIdx.x + threadIdx.x) + 1;
if (i > (num_queens - num_queens % 2) / 2) {
return;
}
// Case 1, N is even and (N-2) mod 6 is not 0
if (num_queens % 2 == 0 && (num_queens - 2) % 6 != 0) {
case1(i, num_queens);
}
// Case 2, N is even and N mod 6 is not 0
else if (num_queens % 2 == 0 && num_queens % 6 != 0) {
case2(i, num_queens);
}
// Case 3, N is odd, and (N-3) mod 6 is not 0
else if ((num_queens - 1) % 2 == 0 && (num_queens - 3) % 6 != 0) {
case1(i, num_queens - 1);
if (blockIdx.x == 0 && threadIdx.x == 0) {
board[num_queens - 1] = num_queens - 1;
}
}
// Case 4, N is odd and (N-1) mod 6 is not 0
else if ((num_queens - 1) % 2 == 0 && (num_queens - 1) % 6 != 0) {
case2(i, num_queens - 1);
if (blockIdx.x == 0 && threadIdx.x == 0) {
board[num_queens - 1] = num_queens - 1;
}
}
return;
}
// Resets board and occupancy grid
__global__ void clearBuffers(int num_queens) {
int i = (blockDim.x * blockIdx.x + threadIdx.x);
board[2 * i] = 0;
board[2 * i + 1] = 0;
occ_col[2 * i] = 0;
occ_col[2 * i + 1] = 0;
occ_row[2 * i] = 0;
occ_row[2 * i + 1] = 0;
occ_adiag[2 * i] = 0;
occ_adiag[2 * i + 1] = 0;
occ_adiag[2 * i + num_queens] = 0;
occ_adiag[2 * i + 1 + num_queens] = 0;
occ_ddiag[2 * i] = 0;
occ_ddiag[2 * i + 1] = 0;
occ_ddiag[2 * i + num_queens] = 0;
occ_ddiag[2 * i + 1 + num_queens] = 0;
if (blockIdx.x == 0 && threadIdx.x == 0) {
collision_flag[0] = 0;
}
}
// Returns symbol addresses for interface variables
int* getBoardAddr() {
int* board_ptr = 0;
cudaGetSymbolAddress((void**)&board_ptr, board);
return board_ptr;
}
int* getFlagAddr() {
int* cflag_ptr = 0;
cudaGetSymbolAddress((void**)&cflag_ptr, collision_flag);
return cflag_ptr;
}
int getMaxN() {
int N = MAX_N;
return N;
}
// Frees all memory prior to shutdown
void memPurge() {
cudaFree(board);
cudaFree(collision_flag);
cudaFree(occ_col);
cudaFree(occ_row);
cudaFree(occ_adiag);
cudaFree(occ_ddiag);
} | #ifndef __CUDA_RUNTIME_H__
#include "hip/hip_runtime.h"
#endif // !"cuda_runtime.h"
#ifndef __DEVICE_LAUNCH_PARAMETERS_H__
#endif // !__DEVICE_LAUNCH_PARAMETERS_H__
// Constants
const int MAX_N = (2147483648 / 8); // N = maxInt32 / 8 = (2147483648 / 8) = 268,435,456 queens
// GPU-local variables
__device__ int board[MAX_N] = { 0 }; // list of queen positions, where board[x] = y
__device__ short occ_col[MAX_N]; // column occupancy (unique x)
__device__ short occ_row[MAX_N]; // row occupancy (unique y)
__device__ short occ_adiag[2 * MAX_N]; // ascending diagonal occupancy (unique x+y)
__device__ short occ_ddiag[2 * MAX_N]; // decending diagonal occupancy (unique x-y)
__device__ short collision_flag[1] = { 0 }; // Flag raised if any 2 Queens can attack each other
using namespace std;
// Adds queen to occupancy arrays and checks for collisions
__device__ void register_q(int x, int y, int num_queens)
{
if (occ_col[x] != 0 || occ_row[y] != 0 || occ_adiag[(x + y)] != 0 || occ_ddiag[num_queens + (x - y)] != 0) {
collision_flag[0] = 1;
}
occ_col[x] = 1;
occ_row[y] = 1;
occ_adiag[x + y] = 1;
occ_ddiag[num_queens + (x - y)] = 1;
return;
}
// Equation 1
__device__ void case1(int i, int N) {
int x, y, x1, y1;
x = i;
y = 2 * i;
x1 = N / 2 + i;
y1 = 2 * i - 1;
register_q(x - 1, y - 1, N);
register_q(x1 - 1, y1 - 1, N);
board[x - 1] = y - 1;
board[x1 - 1] = y1 - 1;
return;
}
// Equation 2
__device__ void case2(int i, int N) {
int x, y, x1, y1;
x = i;
y = 1 + ((2 * (i - 1) + N / 2 - 1) % N);
x1 = N + 1 - i;
y1 = N - ((2 * (i - 1) + N / 2 - 1) % N);
register_q(x - 1, y - 1, N);
register_q(x1 - 1, y1 - 1, N);
board[x - 1] = y - 1;
board[x1 - 1] = y1 - 1;
return;
}
// Main GPU kernel
__global__ void N_Queens_Kernel(int num_queens)
{
// Each thread places 2 queens
int i = (blockDim.x * blockIdx.x + threadIdx.x) + 1;
if (i > (num_queens - num_queens % 2) / 2) {
return;
}
// Case 1, N is even and (N-2) mod 6 is not 0
if (num_queens % 2 == 0 && (num_queens - 2) % 6 != 0) {
case1(i, num_queens);
}
// Case 2, N is even and N mod 6 is not 0
else if (num_queens % 2 == 0 && num_queens % 6 != 0) {
case2(i, num_queens);
}
// Case 3, N is odd, and (N-3) mod 6 is not 0
else if ((num_queens - 1) % 2 == 0 && (num_queens - 3) % 6 != 0) {
case1(i, num_queens - 1);
if (blockIdx.x == 0 && threadIdx.x == 0) {
board[num_queens - 1] = num_queens - 1;
}
}
// Case 4, N is odd and (N-1) mod 6 is not 0
else if ((num_queens - 1) % 2 == 0 && (num_queens - 1) % 6 != 0) {
case2(i, num_queens - 1);
if (blockIdx.x == 0 && threadIdx.x == 0) {
board[num_queens - 1] = num_queens - 1;
}
}
return;
}
// Resets board and occupancy grid
__global__ void clearBuffers(int num_queens) {
int i = (blockDim.x * blockIdx.x + threadIdx.x);
board[2 * i] = 0;
board[2 * i + 1] = 0;
occ_col[2 * i] = 0;
occ_col[2 * i + 1] = 0;
occ_row[2 * i] = 0;
occ_row[2 * i + 1] = 0;
occ_adiag[2 * i] = 0;
occ_adiag[2 * i + 1] = 0;
occ_adiag[2 * i + num_queens] = 0;
occ_adiag[2 * i + 1 + num_queens] = 0;
occ_ddiag[2 * i] = 0;
occ_ddiag[2 * i + 1] = 0;
occ_ddiag[2 * i + num_queens] = 0;
occ_ddiag[2 * i + 1 + num_queens] = 0;
if (blockIdx.x == 0 && threadIdx.x == 0) {
collision_flag[0] = 0;
}
}
// Returns symbol addresses for interface variables
int* getBoardAddr() {
int* board_ptr = 0;
hipGetSymbolAddress((void**)&board_ptr, HIP_SYMBOL(board));
return board_ptr;
}
int* getFlagAddr() {
int* cflag_ptr = 0;
hipGetSymbolAddress((void**)&cflag_ptr, HIP_SYMBOL(collision_flag));
return cflag_ptr;
}
int getMaxN() {
int N = MAX_N;
return N;
}
// Frees all memory prior to shutdown
void memPurge() {
hipFree(board);
hipFree(collision_flag);
hipFree(occ_col);
hipFree(occ_row);
hipFree(occ_adiag);
hipFree(occ_ddiag);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef __CUDA_RUNTIME_H__
#include "hip/hip_runtime.h"
#endif // !"cuda_runtime.h"
#ifndef __DEVICE_LAUNCH_PARAMETERS_H__
#endif // !__DEVICE_LAUNCH_PARAMETERS_H__
// Constants
const int MAX_N = (2147483648 / 8); // N = maxInt32 / 8 = (2147483648 / 8) = 268,435,456 queens
// GPU-local variables
__device__ int board[MAX_N] = { 0 }; // list of queen positions, where board[x] = y
__device__ short occ_col[MAX_N]; // column occupancy (unique x)
__device__ short occ_row[MAX_N]; // row occupancy (unique y)
__device__ short occ_adiag[2 * MAX_N]; // ascending diagonal occupancy (unique x+y)
__device__ short occ_ddiag[2 * MAX_N]; // decending diagonal occupancy (unique x-y)
__device__ short collision_flag[1] = { 0 }; // Flag raised if any 2 Queens can attack each other
using namespace std;
// Adds queen to occupancy arrays and checks for collisions
__device__ void register_q(int x, int y, int num_queens)
{
if (occ_col[x] != 0 || occ_row[y] != 0 || occ_adiag[(x + y)] != 0 || occ_ddiag[num_queens + (x - y)] != 0) {
collision_flag[0] = 1;
}
occ_col[x] = 1;
occ_row[y] = 1;
occ_adiag[x + y] = 1;
occ_ddiag[num_queens + (x - y)] = 1;
return;
}
// Equation 1
__device__ void case1(int i, int N) {
int x, y, x1, y1;
x = i;
y = 2 * i;
x1 = N / 2 + i;
y1 = 2 * i - 1;
register_q(x - 1, y - 1, N);
register_q(x1 - 1, y1 - 1, N);
board[x - 1] = y - 1;
board[x1 - 1] = y1 - 1;
return;
}
// Equation 2
__device__ void case2(int i, int N) {
int x, y, x1, y1;
x = i;
y = 1 + ((2 * (i - 1) + N / 2 - 1) % N);
x1 = N + 1 - i;
y1 = N - ((2 * (i - 1) + N / 2 - 1) % N);
register_q(x - 1, y - 1, N);
register_q(x1 - 1, y1 - 1, N);
board[x - 1] = y - 1;
board[x1 - 1] = y1 - 1;
return;
}
// Main GPU kernel
__global__ void N_Queens_Kernel(int num_queens)
{
// Each thread places 2 queens
int i = (blockDim.x * blockIdx.x + threadIdx.x) + 1;
if (i > (num_queens - num_queens % 2) / 2) {
return;
}
// Case 1, N is even and (N-2) mod 6 is not 0
if (num_queens % 2 == 0 && (num_queens - 2) % 6 != 0) {
case1(i, num_queens);
}
// Case 2, N is even and N mod 6 is not 0
else if (num_queens % 2 == 0 && num_queens % 6 != 0) {
case2(i, num_queens);
}
// Case 3, N is odd, and (N-3) mod 6 is not 0
else if ((num_queens - 1) % 2 == 0 && (num_queens - 3) % 6 != 0) {
case1(i, num_queens - 1);
if (blockIdx.x == 0 && threadIdx.x == 0) {
board[num_queens - 1] = num_queens - 1;
}
}
// Case 4, N is odd and (N-1) mod 6 is not 0
else if ((num_queens - 1) % 2 == 0 && (num_queens - 1) % 6 != 0) {
case2(i, num_queens - 1);
if (blockIdx.x == 0 && threadIdx.x == 0) {
board[num_queens - 1] = num_queens - 1;
}
}
return;
}
// Resets board and occupancy grid
__global__ void clearBuffers(int num_queens) {
int i = (blockDim.x * blockIdx.x + threadIdx.x);
board[2 * i] = 0;
board[2 * i + 1] = 0;
occ_col[2 * i] = 0;
occ_col[2 * i + 1] = 0;
occ_row[2 * i] = 0;
occ_row[2 * i + 1] = 0;
occ_adiag[2 * i] = 0;
occ_adiag[2 * i + 1] = 0;
occ_adiag[2 * i + num_queens] = 0;
occ_adiag[2 * i + 1 + num_queens] = 0;
occ_ddiag[2 * i] = 0;
occ_ddiag[2 * i + 1] = 0;
occ_ddiag[2 * i + num_queens] = 0;
occ_ddiag[2 * i + 1 + num_queens] = 0;
if (blockIdx.x == 0 && threadIdx.x == 0) {
collision_flag[0] = 0;
}
}
// Returns symbol addresses for interface variables
int* getBoardAddr() {
int* board_ptr = 0;
hipGetSymbolAddress((void**)&board_ptr, HIP_SYMBOL(board));
return board_ptr;
}
int* getFlagAddr() {
int* cflag_ptr = 0;
hipGetSymbolAddress((void**)&cflag_ptr, HIP_SYMBOL(collision_flag));
return cflag_ptr;
}
int getMaxN() {
int N = MAX_N;
return N;
}
// Frees all memory prior to shutdown
void memPurge() {
hipFree(board);
hipFree(collision_flag);
hipFree(occ_col);
hipFree(occ_row);
hipFree(occ_adiag);
hipFree(occ_ddiag);
} | .text
.file "gpu_code.hip"
.globl _Z30__device_stub__N_Queens_Kerneli # -- Begin function _Z30__device_stub__N_Queens_Kerneli
.p2align 4, 0x90
.type _Z30__device_stub__N_Queens_Kerneli,@function
_Z30__device_stub__N_Queens_Kerneli: # @_Z30__device_stub__N_Queens_Kerneli
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z15N_Queens_Kerneli, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z30__device_stub__N_Queens_Kerneli, .Lfunc_end0-_Z30__device_stub__N_Queens_Kerneli
.cfi_endproc
# -- End function
.globl _Z27__device_stub__clearBuffersi # -- Begin function _Z27__device_stub__clearBuffersi
.p2align 4, 0x90
.type _Z27__device_stub__clearBuffersi,@function
_Z27__device_stub__clearBuffersi: # @_Z27__device_stub__clearBuffersi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z12clearBuffersi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z27__device_stub__clearBuffersi, .Lfunc_end1-_Z27__device_stub__clearBuffersi
.cfi_endproc
# -- End function
.globl _Z12getBoardAddrv # -- Begin function _Z12getBoardAddrv
.p2align 4, 0x90
.type _Z12getBoardAddrv,@function
_Z12getBoardAddrv: # @_Z12getBoardAddrv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq $0, (%rsp)
movq %rsp, %rdi
movl $board, %esi
callq hipGetSymbolAddress
movq (%rsp), %rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12getBoardAddrv, .Lfunc_end2-_Z12getBoardAddrv
.cfi_endproc
# -- End function
.globl _Z11getFlagAddrv # -- Begin function _Z11getFlagAddrv
.p2align 4, 0x90
.type _Z11getFlagAddrv,@function
_Z11getFlagAddrv: # @_Z11getFlagAddrv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq $0, (%rsp)
movq %rsp, %rdi
movl $collision_flag, %esi
callq hipGetSymbolAddress
movq (%rsp), %rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11getFlagAddrv, .Lfunc_end3-_Z11getFlagAddrv
.cfi_endproc
# -- End function
.globl _Z7getMaxNv # -- Begin function _Z7getMaxNv
.p2align 4, 0x90
.type _Z7getMaxNv,@function
_Z7getMaxNv: # @_Z7getMaxNv
.cfi_startproc
# %bb.0:
movl $268435456, %eax # imm = 0x10000000
retq
.Lfunc_end4:
.size _Z7getMaxNv, .Lfunc_end4-_Z7getMaxNv
.cfi_endproc
# -- End function
.globl _Z8memPurgev # -- Begin function _Z8memPurgev
.p2align 4, 0x90
.type _Z8memPurgev,@function
_Z8memPurgev: # @_Z8memPurgev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $board, %edi
callq hipFree
movl $collision_flag, %edi
callq hipFree
movl $occ_col, %edi
callq hipFree
movl $occ_row, %edi
callq hipFree
movl $occ_adiag, %edi
callq hipFree
movl $occ_ddiag, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp hipFree # TAILCALL
.Lfunc_end5:
.size _Z8memPurgev, .Lfunc_end5-_Z8memPurgev
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15N_Queens_Kerneli, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12clearBuffersi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $board, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $1073741824, %r9d # imm = 0x40000000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $occ_col, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $536870912, %r9d # imm = 0x20000000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $occ_row, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $536870912, %r9d # imm = 0x20000000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $occ_adiag, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $1073741824, %r9d # imm = 0x40000000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $occ_ddiag, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $1073741824, %r9d # imm = 0x40000000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $collision_flag, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movl $2, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type board,@object # @board
.local board
.comm board,1073741824,16
.type occ_col,@object # @occ_col
.local occ_col
.comm occ_col,536870912,16
.type occ_row,@object # @occ_row
.local occ_row
.comm occ_row,536870912,16
.type occ_adiag,@object # @occ_adiag
.local occ_adiag
.comm occ_adiag,1073741824,16
.type occ_ddiag,@object # @occ_ddiag
.local occ_ddiag
.comm occ_ddiag,1073741824,16
.type collision_flag,@object # @collision_flag
.local collision_flag
.comm collision_flag,2,2
.type _Z15N_Queens_Kerneli,@object # @_Z15N_Queens_Kerneli
.section .rodata,"a",@progbits
.globl _Z15N_Queens_Kerneli
.p2align 3, 0x0
_Z15N_Queens_Kerneli:
.quad _Z30__device_stub__N_Queens_Kerneli
.size _Z15N_Queens_Kerneli, 8
.type _Z12clearBuffersi,@object # @_Z12clearBuffersi
.globl _Z12clearBuffersi
.p2align 3, 0x0
_Z12clearBuffersi:
.quad _Z27__device_stub__clearBuffersi
.size _Z12clearBuffersi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15N_Queens_Kerneli"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12clearBuffersi"
.size .L__unnamed_2, 18
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "board"
.size .L__unnamed_3, 6
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "occ_col"
.size .L__unnamed_4, 8
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "occ_row"
.size .L__unnamed_5, 8
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "occ_adiag"
.size .L__unnamed_6, 10
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "occ_ddiag"
.size .L__unnamed_7, 10
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "collision_flag"
.size .L__unnamed_8, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__N_Queens_Kerneli
.addrsig_sym _Z27__device_stub__clearBuffersi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym board
.addrsig_sym occ_col
.addrsig_sym occ_row
.addrsig_sym occ_adiag
.addrsig_sym occ_ddiag
.addrsig_sym collision_flag
.addrsig_sym _Z15N_Queens_Kerneli
.addrsig_sym _Z12clearBuffersi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000fc39_00000000-6_gpu_code.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2036:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2036:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10register_qiii
.type _Z10register_qiii, @function
_Z10register_qiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10register_qiii, .-_Z10register_qiii
.globl _Z5case1ii
.type _Z5case1ii, @function
_Z5case1ii:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z5case1ii, .-_Z5case1ii
.globl _Z5case2ii
.type _Z5case2ii, @function
_Z5case2ii:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z5case2ii, .-_Z5case2ii
.globl _Z12getBoardAddrv
.type _Z12getBoardAddrv, @function
_Z12getBoardAddrv:
.LFB2030:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq %rsp, %rdi
leaq _ZL5board(%rip), %rsi
call cudaGetSymbolAddress@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L12
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2030:
.size _Z12getBoardAddrv, .-_Z12getBoardAddrv
.globl _Z11getFlagAddrv
.type _Z11getFlagAddrv, @function
_Z11getFlagAddrv:
.LFB2031:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq %rsp, %rdi
leaq _ZL14collision_flag(%rip), %rsi
call cudaGetSymbolAddress@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L16
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2031:
.size _Z11getFlagAddrv, .-_Z11getFlagAddrv
.globl _Z7getMaxNv
.type _Z7getMaxNv, @function
_Z7getMaxNv:
.LFB2032:
.cfi_startproc
endbr64
movl $268435456, %eax
ret
.cfi_endproc
.LFE2032:
.size _Z7getMaxNv, .-_Z7getMaxNv
.globl _Z8memPurgev
.type _Z8memPurgev, @function
_Z8memPurgev:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL5board(%rip), %rdi
call cudaFree@PLT
leaq _ZL14collision_flag(%rip), %rdi
call cudaFree@PLT
leaq _ZL7occ_col(%rip), %rdi
call cudaFree@PLT
leaq _ZL7occ_row(%rip), %rdi
call cudaFree@PLT
leaq _ZL9occ_adiag(%rip), %rdi
call cudaFree@PLT
leaq _ZL9occ_ddiag(%rip), %rdi
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _Z8memPurgev, .-_Z8memPurgev
.globl _Z34__device_stub__Z15N_Queens_Kernelii
.type _Z34__device_stub__Z15N_Queens_Kernelii, @function
_Z34__device_stub__Z15N_Queens_Kernelii:
.LFB2058:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15N_Queens_Kerneli(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z34__device_stub__Z15N_Queens_Kernelii, .-_Z34__device_stub__Z15N_Queens_Kernelii
.globl _Z15N_Queens_Kerneli
.type _Z15N_Queens_Kerneli, @function
_Z15N_Queens_Kerneli:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z15N_Queens_Kernelii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z15N_Queens_Kerneli, .-_Z15N_Queens_Kerneli
.globl _Z31__device_stub__Z12clearBuffersii
.type _Z31__device_stub__Z12clearBuffersii, @function
_Z31__device_stub__Z12clearBuffersii:
.LFB2060:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12clearBuffersi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z31__device_stub__Z12clearBuffersii, .-_Z31__device_stub__Z12clearBuffersii
.globl _Z12clearBuffersi
.type _Z12clearBuffersi, @function
_Z12clearBuffersi:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12clearBuffersii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z12clearBuffersi, .-_Z12clearBuffersi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12clearBuffersi"
.LC1:
.string "_Z15N_Queens_Kerneli"
.LC2:
.string "board"
.LC3:
.string "occ_col"
.LC4:
.string "occ_row"
.LC5:
.string "occ_adiag"
.LC6:
.string "occ_ddiag"
.LC7:
.string "collision_flag"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12clearBuffersi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15N_Queens_Kerneli(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1073741824, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5board(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $536870912, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7occ_col(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $536870912, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7occ_row(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1073741824, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9occ_adiag(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1073741824, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9occ_ddiag(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL14collision_flag(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL14collision_flag
.comm _ZL14collision_flag,2,2
.local _ZL9occ_ddiag
.comm _ZL9occ_ddiag,1073741824,32
.local _ZL9occ_adiag
.comm _ZL9occ_adiag,1073741824,32
.local _ZL7occ_row
.comm _ZL7occ_row,536870912,32
.local _ZL7occ_col
.comm _ZL7occ_col,536870912,32
.local _ZL5board
.comm _ZL5board,1073741824,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_code.hip"
.globl _Z30__device_stub__N_Queens_Kerneli # -- Begin function _Z30__device_stub__N_Queens_Kerneli
.p2align 4, 0x90
.type _Z30__device_stub__N_Queens_Kerneli,@function
_Z30__device_stub__N_Queens_Kerneli: # @_Z30__device_stub__N_Queens_Kerneli
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z15N_Queens_Kerneli, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z30__device_stub__N_Queens_Kerneli, .Lfunc_end0-_Z30__device_stub__N_Queens_Kerneli
.cfi_endproc
# -- End function
.globl _Z27__device_stub__clearBuffersi # -- Begin function _Z27__device_stub__clearBuffersi
.p2align 4, 0x90
.type _Z27__device_stub__clearBuffersi,@function
_Z27__device_stub__clearBuffersi: # @_Z27__device_stub__clearBuffersi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z12clearBuffersi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z27__device_stub__clearBuffersi, .Lfunc_end1-_Z27__device_stub__clearBuffersi
.cfi_endproc
# -- End function
.globl _Z12getBoardAddrv # -- Begin function _Z12getBoardAddrv
.p2align 4, 0x90
.type _Z12getBoardAddrv,@function
_Z12getBoardAddrv: # @_Z12getBoardAddrv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq $0, (%rsp)
movq %rsp, %rdi
movl $board, %esi
callq hipGetSymbolAddress
movq (%rsp), %rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12getBoardAddrv, .Lfunc_end2-_Z12getBoardAddrv
.cfi_endproc
# -- End function
.globl _Z11getFlagAddrv # -- Begin function _Z11getFlagAddrv
.p2align 4, 0x90
.type _Z11getFlagAddrv,@function
_Z11getFlagAddrv: # @_Z11getFlagAddrv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq $0, (%rsp)
movq %rsp, %rdi
movl $collision_flag, %esi
callq hipGetSymbolAddress
movq (%rsp), %rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11getFlagAddrv, .Lfunc_end3-_Z11getFlagAddrv
.cfi_endproc
# -- End function
.globl _Z7getMaxNv # -- Begin function _Z7getMaxNv
.p2align 4, 0x90
.type _Z7getMaxNv,@function
_Z7getMaxNv: # @_Z7getMaxNv
.cfi_startproc
# %bb.0:
movl $268435456, %eax # imm = 0x10000000
retq
.Lfunc_end4:
.size _Z7getMaxNv, .Lfunc_end4-_Z7getMaxNv
.cfi_endproc
# -- End function
.globl _Z8memPurgev # -- Begin function _Z8memPurgev
.p2align 4, 0x90
.type _Z8memPurgev,@function
_Z8memPurgev: # @_Z8memPurgev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $board, %edi
callq hipFree
movl $collision_flag, %edi
callq hipFree
movl $occ_col, %edi
callq hipFree
movl $occ_row, %edi
callq hipFree
movl $occ_adiag, %edi
callq hipFree
movl $occ_ddiag, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp hipFree # TAILCALL
.Lfunc_end5:
.size _Z8memPurgev, .Lfunc_end5-_Z8memPurgev
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15N_Queens_Kerneli, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12clearBuffersi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $board, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $1073741824, %r9d # imm = 0x40000000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $occ_col, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $536870912, %r9d # imm = 0x20000000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $occ_row, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $536870912, %r9d # imm = 0x20000000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $occ_adiag, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $1073741824, %r9d # imm = 0x40000000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $occ_ddiag, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $1073741824, %r9d # imm = 0x40000000
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $collision_flag, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movl $2, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type board,@object # @board
.local board
.comm board,1073741824,16
.type occ_col,@object # @occ_col
.local occ_col
.comm occ_col,536870912,16
.type occ_row,@object # @occ_row
.local occ_row
.comm occ_row,536870912,16
.type occ_adiag,@object # @occ_adiag
.local occ_adiag
.comm occ_adiag,1073741824,16
.type occ_ddiag,@object # @occ_ddiag
.local occ_ddiag
.comm occ_ddiag,1073741824,16
.type collision_flag,@object # @collision_flag
.local collision_flag
.comm collision_flag,2,2
.type _Z15N_Queens_Kerneli,@object # @_Z15N_Queens_Kerneli
.section .rodata,"a",@progbits
.globl _Z15N_Queens_Kerneli
.p2align 3, 0x0
_Z15N_Queens_Kerneli:
.quad _Z30__device_stub__N_Queens_Kerneli
.size _Z15N_Queens_Kerneli, 8
.type _Z12clearBuffersi,@object # @_Z12clearBuffersi
.globl _Z12clearBuffersi
.p2align 3, 0x0
_Z12clearBuffersi:
.quad _Z27__device_stub__clearBuffersi
.size _Z12clearBuffersi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15N_Queens_Kerneli"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12clearBuffersi"
.size .L__unnamed_2, 18
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "board"
.size .L__unnamed_3, 6
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "occ_col"
.size .L__unnamed_4, 8
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "occ_row"
.size .L__unnamed_5, 8
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "occ_adiag"
.size .L__unnamed_6, 10
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "occ_ddiag"
.size .L__unnamed_7, 10
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "collision_flag"
.size .L__unnamed_8, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__N_Queens_Kerneli
.addrsig_sym _Z27__device_stub__clearBuffersi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym board
.addrsig_sym occ_col
.addrsig_sym occ_row
.addrsig_sym occ_adiag
.addrsig_sym occ_ddiag
.addrsig_sym collision_flag
.addrsig_sym _Z15N_Queens_Kerneli
.addrsig_sym _Z12clearBuffersi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* test_kernel.cu
it does not contain anything for the moment
device AJOUTER +1 en parallèle à chaque élément du tableau
*/
//kernel !
__global__ void kernel_1(int* T_device)
{
T_device[0] += 1;
}
__global__ void inc_gpu(int* a, int n)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < n)
a[id]++;
} | code for sm_80
Function : _Z7inc_gpuPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8kernel_1Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0050*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* test_kernel.cu
it does not contain anything for the moment
device AJOUTER +1 en parallèle à chaque élément du tableau
*/
//kernel !
__global__ void kernel_1(int* T_device)
{
T_device[0] += 1;
}
__global__ void inc_gpu(int* a, int n)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < n)
a[id]++;
} | .file "tmpxft_0017c004_00000000-6_test_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z8kernel_1PiPi
.type _Z27__device_stub__Z8kernel_1PiPi, @function
_Z27__device_stub__Z8kernel_1PiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8kernel_1Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z8kernel_1PiPi, .-_Z27__device_stub__Z8kernel_1PiPi
.globl _Z8kernel_1Pi
.type _Z8kernel_1Pi, @function
_Z8kernel_1Pi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z8kernel_1PiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8kernel_1Pi, .-_Z8kernel_1Pi
.globl _Z27__device_stub__Z7inc_gpuPiiPii
.type _Z27__device_stub__Z7inc_gpuPiiPii, @function
_Z27__device_stub__Z7inc_gpuPiiPii:
.LFB2053:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7inc_gpuPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z27__device_stub__Z7inc_gpuPiiPii, .-_Z27__device_stub__Z7inc_gpuPiiPii
.globl _Z7inc_gpuPii
.type _Z7inc_gpuPii, @function
_Z7inc_gpuPii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7inc_gpuPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z7inc_gpuPii, .-_Z7inc_gpuPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7inc_gpuPii"
.LC1:
.string "_Z8kernel_1Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7inc_gpuPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8kernel_1Pi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* test_kernel.cu
it does not contain anything for the moment
device AJOUTER +1 en parallèle à chaque élément du tableau
*/
//kernel !
__global__ void kernel_1(int* T_device)
{
T_device[0] += 1;
}
__global__ void inc_gpu(int* a, int n)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < n)
a[id]++;
} | #include <hip/hip_runtime.h>
/* test_kernel.cu
it does not contain anything for the moment
device AJOUTER +1 en parallèle à chaque élément du tableau
*/
//kernel !
__global__ void kernel_1(int* T_device)
{
T_device[0] += 1;
}
__global__ void inc_gpu(int* a, int n)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < n)
a[id]++;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/* test_kernel.cu
it does not contain anything for the moment
device AJOUTER +1 en parallèle à chaque élément du tableau
*/
//kernel !
__global__ void kernel_1(int* T_device)
{
T_device[0] += 1;
}
__global__ void inc_gpu(int* a, int n)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < n)
a[id]++;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8kernel_1Pi
.globl _Z8kernel_1Pi
.p2align 8
.type _Z8kernel_1Pi,@function
_Z8kernel_1Pi:
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8kernel_1Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8kernel_1Pi, .Lfunc_end0-_Z8kernel_1Pi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7inc_gpuPii
.globl _Z7inc_gpuPii
.p2align 8
.type _Z7inc_gpuPii,@function
_Z7inc_gpuPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7inc_gpuPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7inc_gpuPii, .Lfunc_end1-_Z7inc_gpuPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8kernel_1Pi
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z8kernel_1Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7inc_gpuPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7inc_gpuPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/* test_kernel.cu
it does not contain anything for the moment
device AJOUTER +1 en parallèle à chaque élément du tableau
*/
//kernel !
__global__ void kernel_1(int* T_device)
{
T_device[0] += 1;
}
__global__ void inc_gpu(int* a, int n)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < n)
a[id]++;
} | .text
.file "test_kernel.hip"
.globl _Z23__device_stub__kernel_1Pi # -- Begin function _Z23__device_stub__kernel_1Pi
.p2align 4, 0x90
.type _Z23__device_stub__kernel_1Pi,@function
_Z23__device_stub__kernel_1Pi: # @_Z23__device_stub__kernel_1Pi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8kernel_1Pi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z23__device_stub__kernel_1Pi, .Lfunc_end0-_Z23__device_stub__kernel_1Pi
.cfi_endproc
# -- End function
.globl _Z22__device_stub__inc_gpuPii # -- Begin function _Z22__device_stub__inc_gpuPii
.p2align 4, 0x90
.type _Z22__device_stub__inc_gpuPii,@function
_Z22__device_stub__inc_gpuPii: # @_Z22__device_stub__inc_gpuPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7inc_gpuPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z22__device_stub__inc_gpuPii, .Lfunc_end1-_Z22__device_stub__inc_gpuPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8kernel_1Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7inc_gpuPii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8kernel_1Pi,@object # @_Z8kernel_1Pi
.section .rodata,"a",@progbits
.globl _Z8kernel_1Pi
.p2align 3, 0x0
_Z8kernel_1Pi:
.quad _Z23__device_stub__kernel_1Pi
.size _Z8kernel_1Pi, 8
.type _Z7inc_gpuPii,@object # @_Z7inc_gpuPii
.globl _Z7inc_gpuPii
.p2align 3, 0x0
_Z7inc_gpuPii:
.quad _Z22__device_stub__inc_gpuPii
.size _Z7inc_gpuPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8kernel_1Pi"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7inc_gpuPii"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__kernel_1Pi
.addrsig_sym _Z22__device_stub__inc_gpuPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8kernel_1Pi
.addrsig_sym _Z7inc_gpuPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7inc_gpuPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8kernel_1Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0050*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8kernel_1Pi
.globl _Z8kernel_1Pi
.p2align 8
.type _Z8kernel_1Pi,@function
_Z8kernel_1Pi:
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8kernel_1Pi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8kernel_1Pi, .Lfunc_end0-_Z8kernel_1Pi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7inc_gpuPii
.globl _Z7inc_gpuPii
.p2align 8
.type _Z7inc_gpuPii,@function
_Z7inc_gpuPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7inc_gpuPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7inc_gpuPii, .Lfunc_end1-_Z7inc_gpuPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8kernel_1Pi
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z8kernel_1Pi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7inc_gpuPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7inc_gpuPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017c004_00000000-6_test_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z8kernel_1PiPi
.type _Z27__device_stub__Z8kernel_1PiPi, @function
_Z27__device_stub__Z8kernel_1PiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8kernel_1Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z8kernel_1PiPi, .-_Z27__device_stub__Z8kernel_1PiPi
.globl _Z8kernel_1Pi
.type _Z8kernel_1Pi, @function
_Z8kernel_1Pi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z8kernel_1PiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8kernel_1Pi, .-_Z8kernel_1Pi
.globl _Z27__device_stub__Z7inc_gpuPiiPii
.type _Z27__device_stub__Z7inc_gpuPiiPii, @function
_Z27__device_stub__Z7inc_gpuPiiPii:
.LFB2053:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7inc_gpuPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z27__device_stub__Z7inc_gpuPiiPii, .-_Z27__device_stub__Z7inc_gpuPiiPii
.globl _Z7inc_gpuPii
.type _Z7inc_gpuPii, @function
_Z7inc_gpuPii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7inc_gpuPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z7inc_gpuPii, .-_Z7inc_gpuPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7inc_gpuPii"
.LC1:
.string "_Z8kernel_1Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7inc_gpuPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8kernel_1Pi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test_kernel.hip"
.globl _Z23__device_stub__kernel_1Pi # -- Begin function _Z23__device_stub__kernel_1Pi
.p2align 4, 0x90
.type _Z23__device_stub__kernel_1Pi,@function
_Z23__device_stub__kernel_1Pi: # @_Z23__device_stub__kernel_1Pi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8kernel_1Pi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z23__device_stub__kernel_1Pi, .Lfunc_end0-_Z23__device_stub__kernel_1Pi
.cfi_endproc
# -- End function
.globl _Z22__device_stub__inc_gpuPii # -- Begin function _Z22__device_stub__inc_gpuPii
.p2align 4, 0x90
.type _Z22__device_stub__inc_gpuPii,@function
_Z22__device_stub__inc_gpuPii: # @_Z22__device_stub__inc_gpuPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7inc_gpuPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z22__device_stub__inc_gpuPii, .Lfunc_end1-_Z22__device_stub__inc_gpuPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8kernel_1Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7inc_gpuPii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8kernel_1Pi,@object # @_Z8kernel_1Pi
.section .rodata,"a",@progbits
.globl _Z8kernel_1Pi
.p2align 3, 0x0
_Z8kernel_1Pi:
.quad _Z23__device_stub__kernel_1Pi
.size _Z8kernel_1Pi, 8
.type _Z7inc_gpuPii,@object # @_Z7inc_gpuPii
.globl _Z7inc_gpuPii
.p2align 3, 0x0
_Z7inc_gpuPii:
.quad _Z22__device_stub__inc_gpuPii
.size _Z7inc_gpuPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8kernel_1Pi"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7inc_gpuPii"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__kernel_1Pi
.addrsig_sym _Z22__device_stub__inc_gpuPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8kernel_1Pi
.addrsig_sym _Z7inc_gpuPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <type_traits>
template <typename... Ls>
struct apply_impl
{
using type = std::integral_constant<bool,true>;
};
template <typename... Args>
using apply = typename apply_impl<Args...>::type;
template<typename T>
using type_impl = std::integral_constant<bool,T::value>;
template<typename P, typename T>
struct nope
{
using that = apply<P, T>;
using type = std::integral_constant<bool,that::value>;
// using type = type_impl<that>;
};
int main(int, char*[])
{
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <type_traits>
template <typename... Ls>
struct apply_impl
{
using type = std::integral_constant<bool,true>;
};
template <typename... Args>
using apply = typename apply_impl<Args...>::type;
template<typename T>
using type_impl = std::integral_constant<bool,T::value>;
template<typename P, typename T>
struct nope
{
using that = apply<P, T>;
using type = std::integral_constant<bool,that::value>;
// using type = type_impl<that>;
};
int main(int, char*[])
{
return 0;
} | .file "tmpxft_000a8a84_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE2027:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <type_traits>
template <typename... Ls>
struct apply_impl
{
using type = std::integral_constant<bool,true>;
};
template <typename... Args>
using apply = typename apply_impl<Args...>::type;
template<typename T>
using type_impl = std::integral_constant<bool,T::value>;
template<typename P, typename T>
struct nope
{
using that = apply<P, T>;
using type = std::integral_constant<bool,that::value>;
// using type = type_impl<that>;
};
int main(int, char*[])
{
return 0;
} | #include <hip/hip_runtime.h>
#include <type_traits>
template <typename... Ls>
struct apply_impl
{
using type = std::integral_constant<bool,true>;
};
template <typename... Args>
using apply = typename apply_impl<Args...>::type;
template<typename T>
using type_impl = std::integral_constant<bool,T::value>;
template<typename P, typename T>
struct nope
{
using that = apply<P, T>;
using type = std::integral_constant<bool,that::value>;
// using type = type_impl<that>;
};
int main(int, char*[])
{
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <type_traits>
template <typename... Ls>
struct apply_impl
{
using type = std::integral_constant<bool,true>;
};
template <typename... Args>
using apply = typename apply_impl<Args...>::type;
template<typename T>
using type_impl = std::integral_constant<bool,T::value>;
template<typename P, typename T>
struct nope
{
using that = apply<P, T>;
using type = std::integral_constant<bool,that::value>;
// using type = type_impl<that>;
};
int main(int, char*[])
{
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <type_traits>
template <typename... Ls>
struct apply_impl
{
using type = std::integral_constant<bool,true>;
};
template <typename... Args>
using apply = typename apply_impl<Args...>::type;
template<typename T>
using type_impl = std::integral_constant<bool,T::value>;
template<typename P, typename T>
struct nope
{
using that = apply<P, T>;
using type = std::integral_constant<bool,that::value>;
// using type = type_impl<that>;
};
int main(int, char*[])
{
return 0;
} | .text
.file "main.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a8a84_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE2027:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdlib.h>
#include <cmath>
#include <stdio.h>
#include <sys/time.h>
void check_upper();
void print_a();
void print_b();
void print_x();
void print_m();
void check_result();
void initialize_data();
void partial_pivoting(int row);
float* a_get(int row, int col);
pthread_barrier_t barrier;
float* a;
float* a_d;
float* b_d;
float* b;
float* x;
int n;
int thread_amount;
int kek;
int BLOCK_SIZE;
__global__ void gauss_solve(int row, float* A, float* B, int n) {
int idx = blockIdx.x * blockDim.x + threadIdx.x ;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
if (idx >= n || idx <= row || idy < row || idy >= n) return;
__shared__ float m[32];
__shared__ float tmp[32];
m[tx] = A[idx*n+row]/A[row*n+row];
tmp[ty] = A[row*n + idy];
__syncthreads();
A[idx*n+idy] -= m[tx] * tmp[ty];
if (idy == n-1) B[idx]-= m[tx]*B[row];
}
__global__ void part_pivot(int row, float* A, float* B, int n) {
float ksave = -1.0f;
int ki = 0;
for (int col = row; col < n; col++) {
if (abs(A[col*n + row]) > ksave) {
ksave = abs(A[col*n + row]);
ki = col;
}
}
// Swap rows
for (int col = row; col < n; col++) {
float tmp = A[ki*n + col];
A[ki*n + col] = A[row*n + col];
A[row*n + col] = tmp;
}
}
void gauss_elim() {
size_t size = n * n * sizeof(float);
cudaMalloc(&a_d, size);
size_t size_b = n * sizeof(float);
cudaMalloc(&b_d, size_b);
cudaMemcpy(a_d, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(b_d, b, size_b, cudaMemcpyHostToDevice);
dim3 threadsPerBlock(BLOCK_SIZE, BLOCK_SIZE);
size_t blocks_needed = ceil(n / (float)BLOCK_SIZE);
dim3 numBlocks(blocks_needed, blocks_needed);
for (int row = 0; row < n; row++) {
part_pivot<<<dim3(1,1),dim3(1,1)>>>(row, a_d, b_d, n);
//cudaDeviceSynchronize();
gauss_solve<<<numBlocks, threadsPerBlock>>>(row, a_d, b_d, n);
//cudaDeviceSynchronize();
}
cudaMemcpy(a, a_d, size, cudaMemcpyDeviceToHost);
cudaMemcpy(b, b_d, size_b, cudaMemcpyDeviceToHost);
cudaFree(a_d);
cudaFree(b_d);
}
int main(int argc, char* argv[]) {
if (argc != 3) {
std::cout << "Invalid input. Number of arguments should be 2.\n";
return 0;
}
n = atoi(argv[1]);
BLOCK_SIZE = atoi(argv[2]);
BLOCK_SIZE = std::min(BLOCK_SIZE, 32);
initialize_data();
// Get current system time
struct timeval tp;
gettimeofday(&tp, NULL);
long int start = tp.tv_sec * 1000 + tp.tv_usec / 1000;
gauss_elim();
// Backwards solving
for (int i = n-1; i >= 0; i--) {
x[i] = b[i];
for (int j = i+1; j < n; j++) {
x[i]-= a[i*n + j]*x[j];
}
x[i]/=a[i*n + i];
}
gettimeofday(&tp, NULL);
long int end = tp.tv_sec * 1000 + tp.tv_usec / 1000;
std::cout << "Execution time = " << end-start << " ms.\n";
check_result();
check_upper();
free(a);
delete[] b;
delete[] x;
}
/**
* Allocates memory and randomizes values for the matrix and vectors
* */
void initialize_data() {
a = (float*) malloc(n*n*sizeof(float));
b = new float[n];
x = new float[n];
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
a[i*n+j] = 1 + drand48() * 9;
}
b[i] = drand48() * 9;
}
}
/**
* Checks and prints the final result by calculating the L2-norm of
* Ax-b
* */
void check_result() {
float* r = new float[n];
for (int i = 0; i < n; i++) {
r[i] = 0;
for (int j = 0; j < n; j++) {
r[i] += a[i*n + j]*x[j];
}
r[i]-=b[i];
}
float result = 0;
for (int i = 0; i < n; i++) {
result += r[i]*r[i];
}
result = sqrt(result);
std::cerr << "Error factor: " << result << ".\n";
}
/**
* Prints the matrix A
* */
void print_a() {
std::cout << "A: \n";
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
std::cout << (int)a[i*n + j] << " ";
}
std::cout << "\n";
}
std::cout << "\n\n";
}
void print_b() {
std::cout << "B: \n";
for (int i = 0; i < n; i++) {
std::cout << b[i] << "\n";
}
std::cout << "\n\n";
}
void print_x() {
std::cout << "X: \n";
for (int i = 0; i < n; i++) {
std::cout << x[i] << "\n";
}
std::cout << "\n\n";
}
void check_upper() {
std::cout << "Check if upper: \n";
for (int i = 0; i < n; i++) {
for (int j = 0; j < i; j++) {
if(((int)a[i*n+j]!=0))
std::cout << "Value: " << (int)a[i*n + j] << " at " << i << "," << j << "\n";
}
}
} | .file "tmpxft_0009482a_00000000-6_cuda_code.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3680:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3680:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15initialize_datav
.type _Z15initialize_datav, @function
_Z15initialize_datav:
.LFB3672:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl n(%rip), %ebx
movl %ebx, %edi
imull %ebx, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, a(%rip)
movslq %ebx, %rbx
movabsq $2305843009213693950, %rax
cmpq %rbx, %rax
jb .L4
leaq 0(,%rbx,4), %rdi
call _Znam@PLT
movq %rax, b(%rip)
movslq n(%rip), %rax
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L18
leaq 0(,%rax,4), %rdi
call _Znam@PLT
movq %rax, x(%rip)
movl $0, %r12d
cmpl $0, n(%rip)
jg .L7
.L3:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.L18:
call __cxa_throw_bad_array_new_length@PLT
.L9:
call drand48@PLT
movl %ebp, %eax
imull n(%rip), %eax
addl %ebx, %eax
cltq
mulsd .LC0(%rip), %xmm0
addsd .LC1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movq a(%rip), %rdx
movss %xmm0, (%rdx,%rax,4)
addl $1, %ebx
cmpl %ebx, n(%rip)
jg .L9
.L10:
call drand48@PLT
mulsd .LC0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movq b(%rip), %rax
movss %xmm0, (%rax,%r12,4)
addq $1, %r12
cmpl %r12d, n(%rip)
jle .L3
.L7:
movl %r12d, %ebp
movl $0, %ebx
cmpl $0, n(%rip)
jg .L9
jmp .L10
.cfi_endproc
.LFE3672:
.size _Z15initialize_datav, .-_Z15initialize_datav
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Error factor: "
.LC4:
.string ".\n"
.text
.globl _Z12check_resultv
.type _Z12check_resultv, @function
_Z12check_resultv:
.LFB3673:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movslq n(%rip), %rax
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L20
leaq 0(,%rax,4), %rdi
call _Znam@PLT
movl n(%rip), %ebp
pxor %xmm1, %xmm1
testl %ebp, %ebp
jle .L22
movq a(%rip), %r12
movq x(%rip), %rdi
movq %rax, %r8
movq b(%rip), %r10
movslq %ebp, %rsi
salq $2, %rsi
leaq (%rax,%rsi), %r11
movl $0, %r9d
.L24:
movq %rax, %rbx
movslq %r9d, %rdx
leaq (%r12,%rdx,4), %rcx
movl $0, %edx
pxor %xmm1, %xmm1
.L23:
movss (%rcx,%rdx), %xmm0
mulss (%rdi,%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rdx
cmpq %rsi, %rdx
jne .L23
subss (%r10), %xmm1
movss %xmm1, (%rbx)
addq $4, %rax
addq $4, %r10
addl %ebp, %r9d
cmpq %r11, %rax
jne .L24
pxor %xmm1, %xmm1
.L25:
movss (%r8), %xmm0
mulss %xmm0, %xmm0
addss %xmm0, %xmm1
addq $4, %r8
cmpq %r11, %r8
jne .L25
pxor %xmm0, %xmm0
ucomiss %xmm1, %xmm0
ja .L32
.L22:
sqrtss %xmm1, %xmm1
movss %xmm1, 12(%rsp)
.L28:
movl $14, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $2, %edx
leaq .LC4(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.L32:
movaps %xmm1, %xmm0
call sqrtf@PLT
movss %xmm0, 12(%rsp)
jmp .L28
.cfi_endproc
.LFE3673:
.size _Z12check_resultv, .-_Z12check_resultv
.section .rodata.str1.1
.LC5:
.string "A: \n"
.LC6:
.string " "
.LC7:
.string "\n"
.LC8:
.string "\n\n"
.text
.globl _Z7print_av
.type _Z7print_av, @function
_Z7print_av:
.LFB3674:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $4, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $0, %ebp
leaq _ZSt4cout(%rip), %r12
leaq .LC6(%rip), %r13
leaq .LC7(%rip), %r14
cmpl $0, n(%rip)
jg .L35
.L36:
movl $2, %edx
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
imull %ebp, %eax
addl %ebx, %eax
cltq
movq a(%rip), %rdx
cvttss2sil (%rdx,%rax,4), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addl $1, %ebx
movl n(%rip), %eax
cmpl %ebx, %eax
jg .L37
.L38:
movl $1, %edx
movq %r14, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addl $1, %ebp
cmpl %ebp, n(%rip)
jle .L36
.L35:
movl n(%rip), %eax
movl $0, %ebx
testl %eax, %eax
jg .L37
jmp .L38
.cfi_endproc
.LFE3674:
.size _Z7print_av, .-_Z7print_av
.section .rodata.str1.1
.LC9:
.string "B: \n"
.text
.globl _Z7print_bv
.type _Z7print_bv, @function
_Z7print_bv:
.LFB3675:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl $4, %edx
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
cmpl $0, n(%rip)
jle .L46
movl $0, %ebx
leaq _ZSt4cout(%rip), %r12
leaq .LC7(%rip), %rbp
.L47:
movq b(%rip), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpl %ebx, n(%rip)
jg .L47
.L46:
movl $2, %edx
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _Z7print_bv, .-_Z7print_bv
.section .rodata.str1.1
.LC10:
.string "X: \n"
.text
.globl _Z7print_xv
.type _Z7print_xv, @function
_Z7print_xv:
.LFB3676:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl $4, %edx
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
cmpl $0, n(%rip)
jle .L51
movl $0, %ebx
leaq _ZSt4cout(%rip), %r12
leaq .LC7(%rip), %rbp
.L52:
movq x(%rip), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpl %ebx, n(%rip)
jg .L52
.L51:
movl $2, %edx
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _Z7print_xv, .-_Z7print_xv
.section .rodata.str1.1
.LC11:
.string "Check if upper: \n"
.LC12:
.string "Value: "
.LC13:
.string " at "
.LC14:
.string ","
.text
.globl _Z11check_upperv
.type _Z11check_upperv, @function
_Z11check_upperv:
.LFB3677:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl $17, %edx
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $0, %r13d
leaq _ZSt4cout(%rip), %r14
cmpl $0, n(%rip)
jg .L56
.L55:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
leal 1(%rbx), %eax
cmpl %ebx, %r13d
je .L60
movl %eax, %ebx
.L59:
movl %ebp, %eax
imull n(%rip), %eax
addl %ebx, %eax
cltq
movq a(%rip), %rdx
cvttss2sil (%rdx,%rax,4), %eax
testl %eax, %eax
je .L58
movl $7, %edx
leaq .LC12(%rip), %rsi
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %eax
imull n(%rip), %eax
addl %ebx, %eax
cltq
movq a(%rip), %rdx
cvttss2sil (%rdx,%rax,4), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %r12
movl $4, %edx
leaq .LC13(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %r12
movl $1, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC7(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L58
.L60:
movl %ebp, %r13d
.L56:
leal 1(%r13), %ebp
cmpl %ebp, n(%rip)
jle .L55
testl %ebp, %ebp
jle .L60
movl $0, %ebx
leaq .LC14(%rip), %r15
jmp .L59
.cfi_endproc
.LFE3677:
.size _Z11check_upperv, .-_Z11check_upperv
.globl _Z35__device_stub__Z11gauss_solveiPfS_iiPfS_i
.type _Z35__device_stub__Z11gauss_solveiPfS_iiPfS_i, @function
_Z35__device_stub__Z11gauss_solveiPfS_iiPfS_i:
.LFB3702:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L70
.L66:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L71
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11gauss_solveiPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L66
.L71:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3702:
.size _Z35__device_stub__Z11gauss_solveiPfS_iiPfS_i, .-_Z35__device_stub__Z11gauss_solveiPfS_iiPfS_i
.globl _Z11gauss_solveiPfS_i
.type _Z11gauss_solveiPfS_i, @function
_Z11gauss_solveiPfS_i:
.LFB3703:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11gauss_solveiPfS_iiPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _Z11gauss_solveiPfS_i, .-_Z11gauss_solveiPfS_i
.globl _Z34__device_stub__Z10part_pivotiPfS_iiPfS_i
.type _Z34__device_stub__Z10part_pivotiPfS_iiPfS_i, @function
_Z34__device_stub__Z10part_pivotiPfS_iiPfS_i:
.LFB3704:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L78
.L74:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L79
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L78:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10part_pivotiPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L74
.L79:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3704:
.size _Z34__device_stub__Z10part_pivotiPfS_iiPfS_i, .-_Z34__device_stub__Z10part_pivotiPfS_iiPfS_i
.globl _Z10part_pivotiPfS_i
.type _Z10part_pivotiPfS_i, @function
_Z10part_pivotiPfS_i:
.LFB3705:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10part_pivotiPfS_iiPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3705:
.size _Z10part_pivotiPfS_i, .-_Z10part_pivotiPfS_i
.globl _Z10gauss_elimv
.type _Z10gauss_elimv, @function
_Z10gauss_elimv:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movl n(%rip), %ebp
imull %ebp, %ebp
movslq %ebp, %rbp
salq $2, %rbp
movq %rbp, %rsi
leaq a_d(%rip), %rdi
call cudaMalloc@PLT
movslq n(%rip), %r12
salq $2, %r12
movq %r12, %rsi
leaq b_d(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq a(%rip), %rsi
movq a_d(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq b(%rip), %rsi
movq b_d(%rip), %rdi
call cudaMemcpy@PLT
movl BLOCK_SIZE(%rip), %eax
movl %eax, (%rsp)
movl %eax, 4(%rsp)
movl $1, 8(%rsp)
movl n(%rip), %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
divss %xmm1, %xmm0
movaps %xmm0, %xmm1
movss .LC19(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC15(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L83
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC17(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L83:
comiss .LC18(%rip), %xmm1
jnb .L84
cvttss2siq %xmm1, %rax
.L85:
movl %eax, 12(%rsp)
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
testl %edx, %edx
jle .L86
movl $0, %ebx
jmp .L89
.L84:
subss .LC18(%rip), %xmm1
cvttss2siq %xmm1, %rax
btcq $63, %rax
jmp .L85
.L92:
movl n(%rip), %ecx
movq b_d(%rip), %rdx
movq a_d(%rip), %rsi
movl %ebx, %edi
call _Z34__device_stub__Z10part_pivotiPfS_iiPfS_i
jmp .L87
.L88:
addl $1, %ebx
cmpl %ebx, n(%rip)
jle .L86
.L89:
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L92
.L87:
movl 8(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq (%rsp), %rdx
movq 12(%rsp), %rdi
movl 20(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L88
movl n(%rip), %ecx
movq b_d(%rip), %rdx
movq a_d(%rip), %rsi
movl %ebx, %edi
call _Z35__device_stub__Z11gauss_solveiPfS_iiPfS_i
jmp .L88
.L86:
movl $2, %ecx
movq %rbp, %rdx
movq a_d(%rip), %rsi
movq a(%rip), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %r12, %rdx
movq b_d(%rip), %rsi
movq b(%rip), %rdi
call cudaMemcpy@PLT
movq a_d(%rip), %rdi
call cudaFree@PLT
movq b_d(%rip), %rdi
call cudaFree@PLT
addq $48, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z10gauss_elimv, .-_Z10gauss_elimv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC20:
.string "Invalid input. Number of arguments should be 2.\n"
.section .rodata.str1.1
.LC21:
.string "Execution time = "
.LC22:
.string " ms.\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
cmpl $3, %edi
je .L94
leaq .LC20(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L95:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L105
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L94:
.cfi_restore_state
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, n(%rip)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl $32, %edx
cmpl %edx, %eax
cmovg %edx, %eax
movl %eax, BLOCK_SIZE(%rip)
call _Z15initialize_datav
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000, (%rsp), %rbx
movq 8(%rsp), %rax
movl $1000, %ecx
cqto
idivq %rcx
addq %rax, %rbx
call _Z10gauss_elimv
movl n(%rip), %edi
movl %edi, %eax
subl $1, %eax
js .L96
cltq
leaq 0(,%rax,4), %rsi
.L99:
leal -1(%rdi), %r9d
movq b(%rip), %rax
movss (%rax,%rsi), %xmm0
movq x(%rip), %rax
movss %xmm0, (%rax,%rsi)
movl %edi, %edx
movl n(%rip), %eax
cmpl %eax, %edi
jge .L97
movslq %edi, %rcx
salq $2, %rcx
.L98:
movq x(%rip), %r10
leaq (%r10,%rsi), %r8
imull %r9d, %eax
addl %edx, %eax
cltq
movq a(%rip), %r11
movss (%r11,%rax,4), %xmm1
mulss (%r10,%rcx), %xmm1
movss (%r8), %xmm0
subss %xmm1, %xmm0
movss %xmm0, (%r8)
addl $1, %edx
movl n(%rip), %eax
addq $4, %rcx
cmpl %edx, %eax
jg .L98
.L97:
movq %rsi, %rdx
addq x(%rip), %rdx
imull %r9d, %eax
addl %r9d, %eax
cltq
movss (%rdx), %xmm0
movq a(%rip), %rcx
divss (%rcx,%rax,4), %xmm0
movss %xmm0, (%rdx)
subq $4, %rsi
subl $1, %edi
jne .L99
.L96:
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
imulq $1000, (%rsp), %rbp
movq 8(%rsp), %rax
movl $1000, %ecx
cqto
idivq %rcx
addq %rax, %rbp
leaq .LC21(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
subq %rbx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC22(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _Z12check_resultv
call _Z11check_upperv
movq a(%rip), %rdi
call free@PLT
movq b(%rip), %rdi
testq %rdi, %rdi
je .L100
call _ZdaPv@PLT
.L100:
movq x(%rip), %rdi
testq %rdi, %rdi
je .L95
call _ZdaPv@PLT
jmp .L95
.L105:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC23:
.string "_Z10part_pivotiPfS_i"
.LC24:
.string "_Z11gauss_solveiPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3707:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _Z10part_pivotiPfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _Z11gauss_solveiPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3707:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl BLOCK_SIZE
.bss
.align 4
.type BLOCK_SIZE, @object
.size BLOCK_SIZE, 4
BLOCK_SIZE:
.zero 4
.globl kek
.align 4
.type kek, @object
.size kek, 4
kek:
.zero 4
.globl thread_amount
.align 4
.type thread_amount, @object
.size thread_amount, 4
thread_amount:
.zero 4
.globl n
.align 4
.type n, @object
.size n, 4
n:
.zero 4
.globl x
.align 8
.type x, @object
.size x, 8
x:
.zero 8
.globl b
.align 8
.type b, @object
.size b, 8
b:
.zero 8
.globl b_d
.align 8
.type b_d, @object
.size b_d, 8
b_d:
.zero 8
.globl a_d
.align 8
.type a_d, @object
.size a_d, 8
a_d:
.zero 8
.globl a
.align 8
.type a, @object
.size a, 8
a:
.zero 8
.globl barrier
.align 32
.type barrier, @object
.size barrier, 32
barrier:
.zero 32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1075970048
.align 8
.LC1:
.long 0
.long 1072693248
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC15:
.long 1258291200
.align 4
.LC17:
.long 1065353216
.align 4
.LC18:
.long 1593835520
.align 4
.LC19:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdlib.h>
#include <cmath>
#include <stdio.h>
#include <sys/time.h>
void check_upper();
void print_a();
void print_b();
void print_x();
void print_m();
void check_result();
void initialize_data();
void partial_pivoting(int row);
float* a_get(int row, int col);
pthread_barrier_t barrier;
float* a;
float* a_d;
float* b_d;
float* b;
float* x;
int n;
int thread_amount;
int kek;
int BLOCK_SIZE;
__global__ void gauss_solve(int row, float* A, float* B, int n) {
int idx = blockIdx.x * blockDim.x + threadIdx.x ;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
if (idx >= n || idx <= row || idy < row || idy >= n) return;
__shared__ float m[32];
__shared__ float tmp[32];
m[tx] = A[idx*n+row]/A[row*n+row];
tmp[ty] = A[row*n + idy];
__syncthreads();
A[idx*n+idy] -= m[tx] * tmp[ty];
if (idy == n-1) B[idx]-= m[tx]*B[row];
}
__global__ void part_pivot(int row, float* A, float* B, int n) {
float ksave = -1.0f;
int ki = 0;
for (int col = row; col < n; col++) {
if (abs(A[col*n + row]) > ksave) {
ksave = abs(A[col*n + row]);
ki = col;
}
}
// Swap rows
for (int col = row; col < n; col++) {
float tmp = A[ki*n + col];
A[ki*n + col] = A[row*n + col];
A[row*n + col] = tmp;
}
}
void gauss_elim() {
size_t size = n * n * sizeof(float);
cudaMalloc(&a_d, size);
size_t size_b = n * sizeof(float);
cudaMalloc(&b_d, size_b);
cudaMemcpy(a_d, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(b_d, b, size_b, cudaMemcpyHostToDevice);
dim3 threadsPerBlock(BLOCK_SIZE, BLOCK_SIZE);
size_t blocks_needed = ceil(n / (float)BLOCK_SIZE);
dim3 numBlocks(blocks_needed, blocks_needed);
for (int row = 0; row < n; row++) {
part_pivot<<<dim3(1,1),dim3(1,1)>>>(row, a_d, b_d, n);
//cudaDeviceSynchronize();
gauss_solve<<<numBlocks, threadsPerBlock>>>(row, a_d, b_d, n);
//cudaDeviceSynchronize();
}
cudaMemcpy(a, a_d, size, cudaMemcpyDeviceToHost);
cudaMemcpy(b, b_d, size_b, cudaMemcpyDeviceToHost);
cudaFree(a_d);
cudaFree(b_d);
}
int main(int argc, char* argv[]) {
if (argc != 3) {
std::cout << "Invalid input. Number of arguments should be 2.\n";
return 0;
}
n = atoi(argv[1]);
BLOCK_SIZE = atoi(argv[2]);
BLOCK_SIZE = std::min(BLOCK_SIZE, 32);
initialize_data();
// Get current system time
struct timeval tp;
gettimeofday(&tp, NULL);
long int start = tp.tv_sec * 1000 + tp.tv_usec / 1000;
gauss_elim();
// Backwards solving
for (int i = n-1; i >= 0; i--) {
x[i] = b[i];
for (int j = i+1; j < n; j++) {
x[i]-= a[i*n + j]*x[j];
}
x[i]/=a[i*n + i];
}
gettimeofday(&tp, NULL);
long int end = tp.tv_sec * 1000 + tp.tv_usec / 1000;
std::cout << "Execution time = " << end-start << " ms.\n";
check_result();
check_upper();
free(a);
delete[] b;
delete[] x;
}
/**
* Allocates memory and randomizes values for the matrix and vectors
* */
void initialize_data() {
a = (float*) malloc(n*n*sizeof(float));
b = new float[n];
x = new float[n];
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
a[i*n+j] = 1 + drand48() * 9;
}
b[i] = drand48() * 9;
}
}
/**
* Checks and prints the final result by calculating the L2-norm of
* Ax-b
* */
void check_result() {
float* r = new float[n];
for (int i = 0; i < n; i++) {
r[i] = 0;
for (int j = 0; j < n; j++) {
r[i] += a[i*n + j]*x[j];
}
r[i]-=b[i];
}
float result = 0;
for (int i = 0; i < n; i++) {
result += r[i]*r[i];
}
result = sqrt(result);
std::cerr << "Error factor: " << result << ".\n";
}
/**
* Prints the matrix A
* */
void print_a() {
std::cout << "A: \n";
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
std::cout << (int)a[i*n + j] << " ";
}
std::cout << "\n";
}
std::cout << "\n\n";
}
void print_b() {
std::cout << "B: \n";
for (int i = 0; i < n; i++) {
std::cout << b[i] << "\n";
}
std::cout << "\n\n";
}
void print_x() {
std::cout << "X: \n";
for (int i = 0; i < n; i++) {
std::cout << x[i] << "\n";
}
std::cout << "\n\n";
}
void check_upper() {
std::cout << "Check if upper: \n";
for (int i = 0; i < n; i++) {
for (int j = 0; j < i; j++) {
if(((int)a[i*n+j]!=0))
std::cout << "Value: " << (int)a[i*n + j] << " at " << i << "," << j << "\n";
}
}
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdlib.h>
#include <cmath>
#include <stdio.h>
#include <sys/time.h>
void check_upper();
void print_a();
void print_b();
void print_x();
void print_m();
void check_result();
void initialize_data();
void partial_pivoting(int row);
float* a_get(int row, int col);
pthread_barrier_t barrier;
float* a;
float* a_d;
float* b_d;
float* b;
float* x;
int n;
int thread_amount;
int kek;
int BLOCK_SIZE;
__global__ void gauss_solve(int row, float* A, float* B, int n) {
int idx = blockIdx.x * blockDim.x + threadIdx.x ;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
if (idx >= n || idx <= row || idy < row || idy >= n) return;
__shared__ float m[32];
__shared__ float tmp[32];
m[tx] = A[idx*n+row]/A[row*n+row];
tmp[ty] = A[row*n + idy];
__syncthreads();
A[idx*n+idy] -= m[tx] * tmp[ty];
if (idy == n-1) B[idx]-= m[tx]*B[row];
}
__global__ void part_pivot(int row, float* A, float* B, int n) {
float ksave = -1.0f;
int ki = 0;
for (int col = row; col < n; col++) {
if (abs(A[col*n + row]) > ksave) {
ksave = abs(A[col*n + row]);
ki = col;
}
}
// Swap rows
for (int col = row; col < n; col++) {
float tmp = A[ki*n + col];
A[ki*n + col] = A[row*n + col];
A[row*n + col] = tmp;
}
}
void gauss_elim() {
size_t size = n * n * sizeof(float);
hipMalloc(&a_d, size);
size_t size_b = n * sizeof(float);
hipMalloc(&b_d, size_b);
hipMemcpy(a_d, a, size, hipMemcpyHostToDevice);
hipMemcpy(b_d, b, size_b, hipMemcpyHostToDevice);
dim3 threadsPerBlock(BLOCK_SIZE, BLOCK_SIZE);
size_t blocks_needed = ceil(n / (float)BLOCK_SIZE);
dim3 numBlocks(blocks_needed, blocks_needed);
for (int row = 0; row < n; row++) {
part_pivot<<<dim3(1,1),dim3(1,1)>>>(row, a_d, b_d, n);
//cudaDeviceSynchronize();
gauss_solve<<<numBlocks, threadsPerBlock>>>(row, a_d, b_d, n);
//cudaDeviceSynchronize();
}
hipMemcpy(a, a_d, size, hipMemcpyDeviceToHost);
hipMemcpy(b, b_d, size_b, hipMemcpyDeviceToHost);
hipFree(a_d);
hipFree(b_d);
}
int main(int argc, char* argv[]) {
if (argc != 3) {
std::cout << "Invalid input. Number of arguments should be 2.\n";
return 0;
}
n = atoi(argv[1]);
BLOCK_SIZE = atoi(argv[2]);
BLOCK_SIZE = std::min(BLOCK_SIZE, 32);
initialize_data();
// Get current system time
struct timeval tp;
gettimeofday(&tp, NULL);
long int start = tp.tv_sec * 1000 + tp.tv_usec / 1000;
gauss_elim();
// Backwards solving
for (int i = n-1; i >= 0; i--) {
x[i] = b[i];
for (int j = i+1; j < n; j++) {
x[i]-= a[i*n + j]*x[j];
}
x[i]/=a[i*n + i];
}
gettimeofday(&tp, NULL);
long int end = tp.tv_sec * 1000 + tp.tv_usec / 1000;
std::cout << "Execution time = " << end-start << " ms.\n";
check_result();
check_upper();
free(a);
delete[] b;
delete[] x;
}
/**
* Allocates memory and randomizes values for the matrix and vectors
* */
void initialize_data() {
a = (float*) malloc(n*n*sizeof(float));
b = new float[n];
x = new float[n];
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
a[i*n+j] = 1 + drand48() * 9;
}
b[i] = drand48() * 9;
}
}
/**
* Checks and prints the final result by calculating the L2-norm of
* Ax-b
* */
void check_result() {
float* r = new float[n];
for (int i = 0; i < n; i++) {
r[i] = 0;
for (int j = 0; j < n; j++) {
r[i] += a[i*n + j]*x[j];
}
r[i]-=b[i];
}
float result = 0;
for (int i = 0; i < n; i++) {
result += r[i]*r[i];
}
result = sqrt(result);
std::cerr << "Error factor: " << result << ".\n";
}
/**
* Prints the matrix A
* */
void print_a() {
std::cout << "A: \n";
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
std::cout << (int)a[i*n + j] << " ";
}
std::cout << "\n";
}
std::cout << "\n\n";
}
void print_b() {
std::cout << "B: \n";
for (int i = 0; i < n; i++) {
std::cout << b[i] << "\n";
}
std::cout << "\n\n";
}
void print_x() {
std::cout << "X: \n";
for (int i = 0; i < n; i++) {
std::cout << x[i] << "\n";
}
std::cout << "\n\n";
}
void check_upper() {
std::cout << "Check if upper: \n";
for (int i = 0; i < n; i++) {
for (int j = 0; j < i; j++) {
if(((int)a[i*n+j]!=0))
std::cout << "Value: " << (int)a[i*n + j] << " at " << i << "," << j << "\n";
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdlib.h>
#include <cmath>
#include <stdio.h>
#include <sys/time.h>
void check_upper();
void print_a();
void print_b();
void print_x();
void print_m();
void check_result();
void initialize_data();
void partial_pivoting(int row);
float* a_get(int row, int col);
pthread_barrier_t barrier;
float* a;
float* a_d;
float* b_d;
float* b;
float* x;
int n;
int thread_amount;
int kek;
int BLOCK_SIZE;
__global__ void gauss_solve(int row, float* A, float* B, int n) {
int idx = blockIdx.x * blockDim.x + threadIdx.x ;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
if (idx >= n || idx <= row || idy < row || idy >= n) return;
__shared__ float m[32];
__shared__ float tmp[32];
m[tx] = A[idx*n+row]/A[row*n+row];
tmp[ty] = A[row*n + idy];
__syncthreads();
A[idx*n+idy] -= m[tx] * tmp[ty];
if (idy == n-1) B[idx]-= m[tx]*B[row];
}
__global__ void part_pivot(int row, float* A, float* B, int n) {
float ksave = -1.0f;
int ki = 0;
for (int col = row; col < n; col++) {
if (abs(A[col*n + row]) > ksave) {
ksave = abs(A[col*n + row]);
ki = col;
}
}
// Swap rows
for (int col = row; col < n; col++) {
float tmp = A[ki*n + col];
A[ki*n + col] = A[row*n + col];
A[row*n + col] = tmp;
}
}
void gauss_elim() {
size_t size = n * n * sizeof(float);
hipMalloc(&a_d, size);
size_t size_b = n * sizeof(float);
hipMalloc(&b_d, size_b);
hipMemcpy(a_d, a, size, hipMemcpyHostToDevice);
hipMemcpy(b_d, b, size_b, hipMemcpyHostToDevice);
dim3 threadsPerBlock(BLOCK_SIZE, BLOCK_SIZE);
size_t blocks_needed = ceil(n / (float)BLOCK_SIZE);
dim3 numBlocks(blocks_needed, blocks_needed);
for (int row = 0; row < n; row++) {
part_pivot<<<dim3(1,1),dim3(1,1)>>>(row, a_d, b_d, n);
//cudaDeviceSynchronize();
gauss_solve<<<numBlocks, threadsPerBlock>>>(row, a_d, b_d, n);
//cudaDeviceSynchronize();
}
hipMemcpy(a, a_d, size, hipMemcpyDeviceToHost);
hipMemcpy(b, b_d, size_b, hipMemcpyDeviceToHost);
hipFree(a_d);
hipFree(b_d);
}
int main(int argc, char* argv[]) {
if (argc != 3) {
std::cout << "Invalid input. Number of arguments should be 2.\n";
return 0;
}
n = atoi(argv[1]);
BLOCK_SIZE = atoi(argv[2]);
BLOCK_SIZE = std::min(BLOCK_SIZE, 32);
initialize_data();
// Get current system time
struct timeval tp;
gettimeofday(&tp, NULL);
long int start = tp.tv_sec * 1000 + tp.tv_usec / 1000;
gauss_elim();
// Backwards solving
for (int i = n-1; i >= 0; i--) {
x[i] = b[i];
for (int j = i+1; j < n; j++) {
x[i]-= a[i*n + j]*x[j];
}
x[i]/=a[i*n + i];
}
gettimeofday(&tp, NULL);
long int end = tp.tv_sec * 1000 + tp.tv_usec / 1000;
std::cout << "Execution time = " << end-start << " ms.\n";
check_result();
check_upper();
free(a);
delete[] b;
delete[] x;
}
/**
* Allocates memory and randomizes values for the matrix and vectors
* */
void initialize_data() {
a = (float*) malloc(n*n*sizeof(float));
b = new float[n];
x = new float[n];
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
a[i*n+j] = 1 + drand48() * 9;
}
b[i] = drand48() * 9;
}
}
/**
* Checks and prints the final result by calculating the L2-norm of
* Ax-b
* */
void check_result() {
float* r = new float[n];
for (int i = 0; i < n; i++) {
r[i] = 0;
for (int j = 0; j < n; j++) {
r[i] += a[i*n + j]*x[j];
}
r[i]-=b[i];
}
float result = 0;
for (int i = 0; i < n; i++) {
result += r[i]*r[i];
}
result = sqrt(result);
std::cerr << "Error factor: " << result << ".\n";
}
/**
* Prints the matrix A
* */
void print_a() {
std::cout << "A: \n";
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
std::cout << (int)a[i*n + j] << " ";
}
std::cout << "\n";
}
std::cout << "\n\n";
}
void print_b() {
std::cout << "B: \n";
for (int i = 0; i < n; i++) {
std::cout << b[i] << "\n";
}
std::cout << "\n\n";
}
void print_x() {
std::cout << "X: \n";
for (int i = 0; i < n; i++) {
std::cout << x[i] << "\n";
}
std::cout << "\n\n";
}
void check_upper() {
std::cout << "Check if upper: \n";
for (int i = 0; i < n; i++) {
for (int j = 0; j < i; j++) {
if(((int)a[i*n+j]!=0))
std::cout << "Value: " << (int)a[i*n + j] << " at " << i << "," << j << "\n";
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11gauss_solveiPfS_i
.globl _Z11gauss_solveiPfS_i
.p2align 8
.type _Z11gauss_solveiPfS_i,@function
_Z11gauss_solveiPfS_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s5, s[0:1], 0x18
s_load_b32 s6, s[0:1], 0x0
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[3:4]
v_mad_u64_u32 v[1:2], null, s15, s2, v[4:5]
v_cmp_gt_i32_e32 vcc_lo, s5, v0
v_cmp_lt_i32_e64 s2, s6, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_le_i32_e64 s3, s6, v1
v_cmp_gt_i32_e64 s4, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s4, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
v_mul_lo_u32 v2, v0, s5
s_load_b64 s[2:3], s[0:1], 0x8
s_mul_i32 s4, s5, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s4, s6
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[8:9], s[8:9], 2
v_add_nc_u32_e32 v5, s6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s2, s8
s_addc_u32 s9, s3, s9
s_add_i32 s5, s5, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v7, v[5:6], off
v_add_nc_u32_e32 v5, s4, v1
s_load_b32 s4, s[8:9], 0x0
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v8, v[5:6], off
s_waitcnt vmcnt(1) lgkmcnt(0)
v_div_scale_f32 v6, null, s4, s4, v7
v_div_scale_f32 v10, vcc_lo, v7, s4, v7
v_rcp_f32_e32 v9, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v6, v9, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v5, v9
v_mul_f32_e32 v11, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v6, v11, v10
v_fmac_f32_e32 v11, v5, v9
v_add_nc_u32_e32 v5, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v2, -v6, v11, v10
v_lshlrev_b32_e32 v10, 2, v4
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fmas_f32 v2, v2, v9, v11
v_lshlrev_b32_e32 v9, 2, v3
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_3)
v_div_fixup_f32 v2, v2, s4, v7
ds_store_b32 v9, v2
s_waitcnt vmcnt(0)
ds_store_b32 v10, v8 offset:128
v_add_co_u32 v3, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v6, vcc_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_load_b32 v5, v[3:4], off
ds_load_b32 v2, v9
ds_load_b32 v6, v10 offset:128
v_cmp_eq_u32_e32 vcc_lo, s5, v1
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f32 v5, -v2, v6, v5
global_store_b32 v[3:4], v5, off
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v1, 31, v0
s_ashr_i32 s7, s6, 31
v_mov_b32_e32 v3, 0
s_lshl_b64 s[2:3], s[6:7], 2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_clause 0x1
global_load_b32 v3, v3, s[0:1]
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(0)
v_fma_f32 v2, -v2, v3, v4
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11gauss_solveiPfS_i
.amdhsa_group_segment_fixed_size 256
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11gauss_solveiPfS_i, .Lfunc_end0-_Z11gauss_solveiPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10part_pivotiPfS_i
.globl _Z10part_pivotiPfS_i
.p2align 8
.type _Z10part_pivotiPfS_i,@function
_Z10part_pivotiPfS_i:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s5, s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s5, s4
s_cbranch_scc1 .LBB1_3
v_mov_b32_e32 v0, -1.0
s_add_i32 s2, s4, 1
s_mov_b32 s7, s5
s_mul_i32 s2, s5, s2
.LBB1_2:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[8:9], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_add_u32 s8, s0, s8
s_addc_u32 s9, s1, s9
s_load_b32 s3, s[8:9], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_gt_f32_e64 s8, |s3|, v0
v_cndmask_b32_e64 v0, v0, |s3|, s8
s_and_b32 s3, s8, exec_lo
s_cselect_b32 s6, s7, s6
s_add_i32 s7, s7, 1
s_add_i32 s2, s2, s4
s_cmp_ge_i32 s7, s4
s_cbranch_scc0 .LBB1_2
.LBB1_3:
s_cmp_ge_i32 s5, s4
s_cbranch_scc1 .LBB1_6
s_add_i32 s2, s4, 1
s_mul_i32 s6, s6, s4
s_mul_i32 s2, s5, s2
v_mov_b32_e32 v0, 0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_add_u32 s2, s0, s2
s_addc_u32 s3, s1, s3
s_add_i32 s6, s5, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s7, s6, 31
s_lshl_b64 s[6:7], s[6:7], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s0, s6
s_addc_u32 s1, s1, s7
.LBB1_5:
s_clause 0x1
global_load_b32 v1, v0, s[2:3]
global_load_b32 v2, v0, s[0:1]
s_add_i32 s5, s5, 1
s_waitcnt vmcnt(1)
global_store_b32 v0, v1, s[0:1]
s_waitcnt vmcnt(0)
global_store_b32 v0, v2, s[2:3]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_ge_i32 s5, s4
s_cbranch_scc0 .LBB1_5
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10part_pivotiPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 10
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10part_pivotiPfS_i, .Lfunc_end1-_Z10part_pivotiPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 256
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11gauss_solveiPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11gauss_solveiPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10part_pivotiPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z10part_pivotiPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdlib.h>
#include <cmath>
#include <stdio.h>
#include <sys/time.h>
void check_upper();
void print_a();
void print_b();
void print_x();
void print_m();
void check_result();
void initialize_data();
void partial_pivoting(int row);
float* a_get(int row, int col);
pthread_barrier_t barrier;
float* a;
float* a_d;
float* b_d;
float* b;
float* x;
int n;
int thread_amount;
int kek;
int BLOCK_SIZE;
__global__ void gauss_solve(int row, float* A, float* B, int n) {
int idx = blockIdx.x * blockDim.x + threadIdx.x ;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
if (idx >= n || idx <= row || idy < row || idy >= n) return;
__shared__ float m[32];
__shared__ float tmp[32];
m[tx] = A[idx*n+row]/A[row*n+row];
tmp[ty] = A[row*n + idy];
__syncthreads();
A[idx*n+idy] -= m[tx] * tmp[ty];
if (idy == n-1) B[idx]-= m[tx]*B[row];
}
__global__ void part_pivot(int row, float* A, float* B, int n) {
float ksave = -1.0f;
int ki = 0;
for (int col = row; col < n; col++) {
if (abs(A[col*n + row]) > ksave) {
ksave = abs(A[col*n + row]);
ki = col;
}
}
// Swap rows
for (int col = row; col < n; col++) {
float tmp = A[ki*n + col];
A[ki*n + col] = A[row*n + col];
A[row*n + col] = tmp;
}
}
void gauss_elim() {
size_t size = n * n * sizeof(float);
hipMalloc(&a_d, size);
size_t size_b = n * sizeof(float);
hipMalloc(&b_d, size_b);
hipMemcpy(a_d, a, size, hipMemcpyHostToDevice);
hipMemcpy(b_d, b, size_b, hipMemcpyHostToDevice);
dim3 threadsPerBlock(BLOCK_SIZE, BLOCK_SIZE);
size_t blocks_needed = ceil(n / (float)BLOCK_SIZE);
dim3 numBlocks(blocks_needed, blocks_needed);
for (int row = 0; row < n; row++) {
part_pivot<<<dim3(1,1),dim3(1,1)>>>(row, a_d, b_d, n);
//cudaDeviceSynchronize();
gauss_solve<<<numBlocks, threadsPerBlock>>>(row, a_d, b_d, n);
//cudaDeviceSynchronize();
}
hipMemcpy(a, a_d, size, hipMemcpyDeviceToHost);
hipMemcpy(b, b_d, size_b, hipMemcpyDeviceToHost);
hipFree(a_d);
hipFree(b_d);
}
int main(int argc, char* argv[]) {
if (argc != 3) {
std::cout << "Invalid input. Number of arguments should be 2.\n";
return 0;
}
n = atoi(argv[1]);
BLOCK_SIZE = atoi(argv[2]);
BLOCK_SIZE = std::min(BLOCK_SIZE, 32);
initialize_data();
// Get current system time
struct timeval tp;
gettimeofday(&tp, NULL);
long int start = tp.tv_sec * 1000 + tp.tv_usec / 1000;
gauss_elim();
// Backwards solving
for (int i = n-1; i >= 0; i--) {
x[i] = b[i];
for (int j = i+1; j < n; j++) {
x[i]-= a[i*n + j]*x[j];
}
x[i]/=a[i*n + i];
}
gettimeofday(&tp, NULL);
long int end = tp.tv_sec * 1000 + tp.tv_usec / 1000;
std::cout << "Execution time = " << end-start << " ms.\n";
check_result();
check_upper();
free(a);
delete[] b;
delete[] x;
}
/**
* Allocates memory and randomizes values for the matrix and vectors
* */
void initialize_data() {
a = (float*) malloc(n*n*sizeof(float));
b = new float[n];
x = new float[n];
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
a[i*n+j] = 1 + drand48() * 9;
}
b[i] = drand48() * 9;
}
}
/**
* Checks and prints the final result by calculating the L2-norm of
* Ax-b
* */
void check_result() {
float* r = new float[n];
for (int i = 0; i < n; i++) {
r[i] = 0;
for (int j = 0; j < n; j++) {
r[i] += a[i*n + j]*x[j];
}
r[i]-=b[i];
}
float result = 0;
for (int i = 0; i < n; i++) {
result += r[i]*r[i];
}
result = sqrt(result);
std::cerr << "Error factor: " << result << ".\n";
}
/**
* Prints the matrix A
* */
void print_a() {
std::cout << "A: \n";
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
std::cout << (int)a[i*n + j] << " ";
}
std::cout << "\n";
}
std::cout << "\n\n";
}
void print_b() {
std::cout << "B: \n";
for (int i = 0; i < n; i++) {
std::cout << b[i] << "\n";
}
std::cout << "\n\n";
}
void print_x() {
std::cout << "X: \n";
for (int i = 0; i < n; i++) {
std::cout << x[i] << "\n";
}
std::cout << "\n\n";
}
void check_upper() {
std::cout << "Check if upper: \n";
for (int i = 0; i < n; i++) {
for (int j = 0; j < i; j++) {
if(((int)a[i*n+j]!=0))
std::cout << "Value: " << (int)a[i*n + j] << " at " << i << "," << j << "\n";
}
}
} | .text
.file "cuda_code.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__gauss_solveiPfS_i # -- Begin function _Z26__device_stub__gauss_solveiPfS_i
.p2align 4, 0x90
.type _Z26__device_stub__gauss_solveiPfS_i,@function
_Z26__device_stub__gauss_solveiPfS_i: # @_Z26__device_stub__gauss_solveiPfS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11gauss_solveiPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__gauss_solveiPfS_i, .Lfunc_end0-_Z26__device_stub__gauss_solveiPfS_i
.cfi_endproc
# -- End function
.globl _Z25__device_stub__part_pivotiPfS_i # -- Begin function _Z25__device_stub__part_pivotiPfS_i
.p2align 4, 0x90
.type _Z25__device_stub__part_pivotiPfS_i,@function
_Z25__device_stub__part_pivotiPfS_i: # @_Z25__device_stub__part_pivotiPfS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10part_pivotiPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__part_pivotiPfS_i, .Lfunc_end1-_Z25__device_stub__part_pivotiPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10gauss_elimv
.LCPI2_0:
.long 0x5f000000 # float 9.22337203E+18
.text
.globl _Z10gauss_elimv
.p2align 4, 0x90
.type _Z10gauss_elimv,@function
_Z10gauss_elimv: # @_Z10gauss_elimv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl n(%rip), %ebx
imull %ebx, %ebx
shlq $2, %rbx
movl $a_d, %edi
movq %rbx, %rsi
callq hipMalloc
movslq n(%rip), %r14
shlq $2, %r14
movl $b_d, %edi
movq %r14, %rsi
callq hipMalloc
movq a_d(%rip), %rdi
movq a(%rip), %rsi
movq %rbx, 128(%rsp) # 8-byte Spill
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq b_d(%rip), %rdi
movq b(%rip), %rsi
movq %r14, 120(%rsp) # 8-byte Spill
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl BLOCK_SIZE(%rip), %ebx
movl n(%rip), %ebp
cvtsi2ss %ebp, %xmm0
cvtsi2ss %ebx, %xmm1
divss %xmm1, %xmm0
callq ceilf@PLT
testl %ebp, %ebp
jle .LBB2_7
# %bb.1: # %.lr.ph
movq %rbx, %r15
shlq $32, %r15
orq %rbx, %r15
cvttss2si %xmm0, %rax
movq %rax, %rcx
sarq $63, %rcx
subss .LCPI2_0(%rip), %xmm0
cvttss2si %xmm0, %r12
andq %rcx, %r12
orq %rax, %r12
movl %r12d, %eax
shlq $32, %r12
orq %rax, %r12
xorl %ebx, %ebx
movabsq $4294967297, %r13 # imm = 0x100000001
leaq 72(%rsp), %rbp
leaq 80(%rsp), %r14
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_2 Depth=1
incl %ebx
cmpl n(%rip), %ebx
jge .LBB2_7
.LBB2_2: # =>This Inner Loop Header: Depth=1
movq %r13, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=1
movq a_d(%rip), %rax
movq b_d(%rip), %rcx
movl n(%rip), %edx
movl %ebx, 12(%rsp)
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movl %edx, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z10part_pivotiPfS_i, %edi
movq %r14, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4: # in Loop: Header=BB2_2 Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5: # in Loop: Header=BB2_2 Depth=1
movq a_d(%rip), %rax
movq b_d(%rip), %rcx
movl n(%rip), %edx
movl %ebx, 12(%rsp)
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
movl %edx, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z11gauss_solveiPfS_i, %edi
movq %r14, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_6
.LBB2_7: # %._crit_edge
movq a(%rip), %rdi
movq a_d(%rip), %rsi
movq 128(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq b(%rip), %rdi
movq b_d(%rip), %rsi
movq 120(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq a_d(%rip), %rdi
callq hipFree
movq b_d(%rip), %rdi
callq hipFree
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10gauss_elimv, .Lfunc_end2-_Z10gauss_elimv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $3, %edi
jne .LBB3_1
# %bb.2:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, n(%rip)
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cmpl $32, %eax
movl $32, %ecx
cmovll %eax, %ecx
movl %ecx, BLOCK_SIZE(%rip)
callq _Z15initialize_datav
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %r14
movabsq $-2361183241434822607, %rax # imm = 0xDF3B645A1CAC0831
imulq 16(%rsp)
movq %rdx, %rbx
movq %rdx, %rax
shrq $63, %rax
sarq $7, %rbx
addq %rax, %rbx
callq _Z10gauss_elimv
movl n(%rip), %eax
testl %eax, %eax
jle .LBB3_8
# %bb.3: # %.lr.ph32
movq b(%rip), %rcx
movq x(%rip), %rdx
movq a(%rip), %rsi
leal 1(%rax), %edi
movq %rax, %r8
imulq %rax, %r8
leaq (%rsi,%r8,4), %r8
leaq (,%rax,4), %r9
xorq $-4, %r9
leaq (%rdx,%rax,4), %r10
xorl %r11d, %r11d
movq %rax, %r15
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_4 Depth=1
movl %edi, %ebp
imull %r12d, %ebp
movslq %ebp, %r13
movss (%rdx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss (%rsi,%r13,4), %xmm0
movss %xmm0, (%rdx,%r12,4)
addq %r9, %r8
addq $-4, %r10
incq %r11
cmpq $1, %r15
movq %r12, %r15
jle .LBB3_8
.LBB3_4: # =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
leaq -1(%r15), %r12
movss -4(%rcx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, -4(%rdx,%r15,4)
cmpq %rax, %r15
jge .LBB3_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB3_4 Depth=1
movss (%rdx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_4 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r8,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r10,%r13,4), %xmm1
subss %xmm1, %xmm0
movss %xmm0, (%rdx,%r12,4)
incq %r13
cmpl %r13d, %r11d
jne .LBB3_6
jmp .LBB3_7
.LBB3_1:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $48, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB3_12
.LBB3_8: # %._crit_edge33
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movabsq $2361183241434822607, %rax # imm = 0x20C49BA5E353F7CF
imulq 16(%rsp)
movq 8(%rsp), %r15
subq %r14, %r15
movq %rdx, %r14
shrq $63, %r14
sarq $7, %rdx
addq %rdx, %r14
addq %rbx, %r14
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
imulq $1000, %r15, %rsi # imm = 0x3E8
addq %r14, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movl $.L.str.2, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq _Z12check_resultv
callq _Z11check_upperv
movq a(%rip), %rdi
callq free
movq b(%rip), %rdi
testq %rdi, %rdi
je .LBB3_10
# %bb.9:
callq _ZdaPv
.LBB3_10:
movq x(%rip), %rdi
testq %rdi, %rdi
je .LBB3_12
# %bb.11:
callq _ZdaPv
.LBB3_12:
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z15initialize_datav
.LCPI4_0:
.quad 0x4022000000000000 # double 9
.LCPI4_1:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z15initialize_datav
.p2align 4, 0x90
.type _Z15initialize_datav,@function
_Z15initialize_datav: # @_Z15initialize_datav
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movslq n(%rip), %rbx
movl %ebx, %edi
imull %edi, %edi
shlq $2, %rdi
callq malloc
leaq (,%rbx,4), %rcx
testq %rbx, %rbx
movq %rax, a(%rip)
movq $-1, %rbx
cmovnsq %rcx, %rbx
movq %rbx, %rdi
callq _Znam
movq %rax, b(%rip)
movq %rbx, %rdi
callq _Znam
movq %rax, x(%rip)
cmpl $0, n(%rip)
jle .LBB4_6
# %bb.1: # %.preheader.preheader
xorl %ebx, %ebx
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_5: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
callq drand48
movsd .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movq b(%rip), %rax
movss %xmm0, (%rax,%rbx,4)
incq %rbx
movslq n(%rip), %rax
cmpq %rax, %rbx
jge .LBB4_6
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
cmpl $0, n(%rip)
jle .LBB4_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB4_2 Depth=1
movslq %ebx, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_4: # %.lr.ph
# Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
callq drand48
movsd .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd .LCPI4_0(%rip), %xmm0
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movq a(%rip), %rax
movslq n(%rip), %rcx
imulq %r14, %rcx
addq %r15, %rcx
movss %xmm0, (%rax,%rcx,4)
incq %r15
cmpl n(%rip), %r15d
jl .LBB4_4
jmp .LBB4_5
.LBB4_6: # %._crit_edge10
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z15initialize_datav, .Lfunc_end4-_Z15initialize_datav
.cfi_endproc
# -- End function
.globl _Z12check_resultv # -- Begin function _Z12check_resultv
.p2align 4, 0x90
.type _Z12check_resultv,@function
_Z12check_resultv: # @_Z12check_resultv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movslq n(%rip), %rbx
leaq (,%rbx,4), %rax
testq %rbx, %rbx
movq $-1, %rdi
cmovnsq %rax, %rdi
callq _Znam
movl %ebx, %ecx
testq %rbx, %rbx
jle .LBB5_5
# %bb.1: # %.lr.ph29
movq a(%rip), %rdx
movq x(%rip), %rsi
xorl %edi, %edi
movq b(%rip), %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
movl %edi, %r10d
leaq (%rdx,%r10,4), %r10
movl $0, (%rax,%r9,4)
xorps %xmm0, %xmm0
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB5_3: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r10,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rsi,%r11,4), %xmm1
addss %xmm1, %xmm0
incq %r11
cmpq %r11, %rcx
jne .LBB5_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
movss %xmm0, (%rax,%r9,4)
subss (%r8,%r9,4), %xmm0
movss %xmm0, (%rax,%r9,4)
incq %r9
addl %ecx, %edi
cmpq %rcx, %r9
jne .LBB5_2
.LBB5_5: # %.preheader
xorps %xmm1, %xmm1
xorps %xmm0, %xmm0
testl %ecx, %ecx
jle .LBB5_8
# %bb.6: # %.lr.ph32.preheader
xorl %edx, %edx
.p2align 4, 0x90
.LBB5_7: # %.lr.ph32
# =>This Inner Loop Header: Depth=1
movss (%rax,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
mulss %xmm2, %xmm2
addss %xmm2, %xmm0
incq %rdx
cmpq %rdx, %rcx
jne .LBB5_7
.LBB5_8: # %._crit_edge33
ucomiss %xmm1, %xmm0
jb .LBB5_10
# %bb.9:
sqrtss %xmm0, %xmm0
jmp .LBB5_11
.LBB5_10: # %call.sqrt
callq sqrtf@PLT
.LBB5_11: # %._crit_edge33.split
movss %xmm0, 12(%rsp) # 4-byte Spill
movl $_ZSt4cerr, %edi
movl $.L.str.3, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cerr, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.4, %esi
movl $2, %edx
movq %rax, %rdi
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l # TAILCALL
.Lfunc_end5:
.size _Z12check_resultv, .Lfunc_end5-_Z12check_resultv
.cfi_endproc
# -- End function
.globl _Z11check_upperv # -- Begin function _Z11check_upperv
.p2align 4, 0x90
.type _Z11check_upperv,@function
_Z11check_upperv: # @_Z11check_upperv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, n(%rip)
jle .LBB6_8
# %bb.1: # %.preheader.preheader
xorl %ebx, %ebx
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_7: # %._crit_edge
# in Loop: Header=BB6_2 Depth=1
incq %rbx
cmpl n(%rip), %ebx
jge .LBB6_8
.LBB6_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB6_4 Depth 2
testl %ebx, %ebx
je .LBB6_7
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB6_2 Depth=1
movslq %ebx, %r12
xorl %r14d, %r14d
jmp .LBB6_4
.p2align 4, 0x90
.LBB6_6: # in Loop: Header=BB6_4 Depth=2
incq %r14
cmpl %r14d, %ebx
je .LBB6_7
.LBB6_4: # %.lr.ph
# Parent Loop BB6_2 Depth=1
# => This Inner Loop Header: Depth=2
movq a(%rip), %rax
movslq n(%rip), %rcx
imulq %r12, %rcx
addq %r14, %rcx
cvttss2si (%rax,%rcx,4), %eax
testl %eax, %eax
je .LBB6_6
# %bb.5: # in Loop: Header=BB6_4 Depth=2
movl $_ZSt4cout, %edi
movl $.L.str.12, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq a(%rip), %rax
movslq n(%rip), %rcx
imulq %r12, %rcx
addq %r14, %rcx
cvttss2si (%rax,%rcx,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.13, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.14, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
movl %r14d, %esi
callq _ZNSolsEi
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB6_6
.LBB6_8: # %._crit_edge14
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z11check_upperv, .Lfunc_end6-_Z11check_upperv
.cfi_endproc
# -- End function
.globl _Z7print_av # -- Begin function _Z7print_av
.p2align 4, 0x90
.type _Z7print_av,@function
_Z7print_av: # @_Z7print_av
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, n(%rip)
jle .LBB7_6
# %bb.1: # %.preheader.preheader
xorl %ebx, %ebx
jmp .LBB7_2
.p2align 4, 0x90
.LBB7_5: # %._crit_edge
# in Loop: Header=BB7_2 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incl %ebx
cmpl n(%rip), %ebx
jge .LBB7_6
.LBB7_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB7_4 Depth 2
movl n(%rip), %eax
testl %eax, %eax
jle .LBB7_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB7_2 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB7_4: # %.lr.ph
# Parent Loop BB7_2 Depth=1
# => This Inner Loop Header: Depth=2
movq a(%rip), %rcx
imull %ebx, %eax
cltq
addq %r14, %rax
cvttss2si (%rcx,%rax,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl n(%rip), %eax
incq %r14
cmpl %eax, %r14d
jl .LBB7_4
jmp .LBB7_5
.LBB7_6: # %._crit_edge10
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $2, %edx
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l # TAILCALL
.Lfunc_end7:
.size _Z7print_av, .Lfunc_end7-_Z7print_av
.cfi_endproc
# -- End function
.globl _Z7print_bv # -- Begin function _Z7print_bv
.p2align 4, 0x90
.type _Z7print_bv,@function
_Z7print_bv: # @_Z7print_bv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, n(%rip)
jle .LBB8_3
# %bb.1: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB8_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq b(%rip), %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
movslq n(%rip), %rax
cmpq %rax, %rbx
jl .LBB8_2
.LBB8_3: # %._crit_edge
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $2, %edx
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l # TAILCALL
.Lfunc_end8:
.size _Z7print_bv, .Lfunc_end8-_Z7print_bv
.cfi_endproc
# -- End function
.globl _Z7print_xv # -- Begin function _Z7print_xv
.p2align 4, 0x90
.type _Z7print_xv,@function
_Z7print_xv: # @_Z7print_xv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, n(%rip)
jle .LBB9_3
# %bb.1: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB9_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq x(%rip), %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
movslq n(%rip), %rax
cmpq %rax, %rbx
jl .LBB9_2
.LBB9_3: # %._crit_edge
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $2, %edx
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l # TAILCALL
.Lfunc_end9:
.size _Z7print_xv, .Lfunc_end9-_Z7print_xv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11gauss_solveiPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10part_pivotiPfS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type barrier,@object # @barrier
.bss
.globl barrier
.p2align 3, 0x0
barrier:
.zero 32
.size barrier, 32
.type a,@object # @a
.globl a
.p2align 3, 0x0
a:
.quad 0
.size a, 8
.type a_d,@object # @a_d
.globl a_d
.p2align 3, 0x0
a_d:
.quad 0
.size a_d, 8
.type b_d,@object # @b_d
.globl b_d
.p2align 3, 0x0
b_d:
.quad 0
.size b_d, 8
.type b,@object # @b
.globl b
.p2align 3, 0x0
b:
.quad 0
.size b, 8
.type x,@object # @x
.globl x
.p2align 3, 0x0
x:
.quad 0
.size x, 8
.type n,@object # @n
.globl n
.p2align 2, 0x0
n:
.long 0 # 0x0
.size n, 4
.type thread_amount,@object # @thread_amount
.globl thread_amount
.p2align 2, 0x0
thread_amount:
.long 0 # 0x0
.size thread_amount, 4
.type kek,@object # @kek
.globl kek
.p2align 2, 0x0
kek:
.long 0 # 0x0
.size kek, 4
.type BLOCK_SIZE,@object # @BLOCK_SIZE
.globl BLOCK_SIZE
.p2align 2, 0x0
BLOCK_SIZE:
.long 0 # 0x0
.size BLOCK_SIZE, 4
.type _Z11gauss_solveiPfS_i,@object # @_Z11gauss_solveiPfS_i
.section .rodata,"a",@progbits
.globl _Z11gauss_solveiPfS_i
.p2align 3, 0x0
_Z11gauss_solveiPfS_i:
.quad _Z26__device_stub__gauss_solveiPfS_i
.size _Z11gauss_solveiPfS_i, 8
.type _Z10part_pivotiPfS_i,@object # @_Z10part_pivotiPfS_i
.globl _Z10part_pivotiPfS_i
.p2align 3, 0x0
_Z10part_pivotiPfS_i:
.quad _Z25__device_stub__part_pivotiPfS_i
.size _Z10part_pivotiPfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Invalid input. Number of arguments should be 2.\n"
.size .L.str, 49
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Execution time = "
.size .L.str.1, 18
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " ms.\n"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error factor: "
.size .L.str.3, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz ".\n"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "A: \n"
.size .L.str.5, 5
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " "
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\n"
.size .L.str.7, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\n\n"
.size .L.str.8, 3
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "B: \n"
.size .L.str.9, 5
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "X: \n"
.size .L.str.10, 5
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Check if upper: \n"
.size .L.str.11, 18
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Value: "
.size .L.str.12, 8
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " at "
.size .L.str.13, 5
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz ","
.size .L.str.14, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11gauss_solveiPfS_i"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10part_pivotiPfS_i"
.size .L__unnamed_2, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__gauss_solveiPfS_i
.addrsig_sym _Z25__device_stub__part_pivotiPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym a_d
.addrsig_sym b_d
.addrsig_sym _Z11gauss_solveiPfS_i
.addrsig_sym _Z10part_pivotiPfS_i
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define LISTSIZE 10000000
#define MAXNUM 10000
#define THREAD_PER_BLOCK 1024
__global__ void gpu_countsort(int* globalTable_d, int* unsort){
__shared__ int table[MAXNUM];
if(threadIdx.x == 0) memset(table, 0, sizeof(int)*MAXNUM);
__syncthreads();//block level synchronization
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < LISTSIZE){
int num = unsort[index];
atomicAdd(&table[num-1], 1);
}
__syncthreads();
if(threadIdx.x == 0){
for(int i=0; i<MAXNUM; i++){
atomicAdd(&(globalTable_d[i]), table[i]);
}
}
}
void genList(int** unsort){
*unsort = (int*)malloc(sizeof(int) * LISTSIZE);
for(int i=0; i<LISTSIZE; i++){
(*unsort)[i] = rand()%MAXNUM + 1;
}
}
int main()
{
float time;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int *unsort;
genList(&unsort);
int *unsort_d, *table_d;
int listSize = LISTSIZE * sizeof(int);
int tableSize = MAXNUM * sizeof(int);
cudaMalloc((void**)&unsort_d, listSize);
cudaMemcpy(unsort_d, unsort, listSize, cudaMemcpyHostToDevice);
cudaMalloc((void**)&table_d, tableSize);
cudaMemset(table_d, 0, tableSize);
int blockNum;
blockNum = (LISTSIZE/THREAD_PER_BLOCK) + ( LISTSIZE%THREAD_PER_BLOCK==0 ?0:1 );
cudaEventRecord(start, 0);
gpu_countsort<<<blockNum, THREAD_PER_BLOCK>>>(table_d, unsort_d);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
cudaDeviceSynchronize();
printf("time in gpu: %31.f ms\n", time);
int *table, *sort;
sort = (int*)malloc(listSize);
memset(sort, 0, listSize);
table = (int*)malloc(tableSize);
cudaMemcpy(table, table_d, tableSize, cudaMemcpyDeviceToHost);
int index=0;
for(int i=0; i<MAXNUM; i++){
for(int j=0; j<table[i]; j++) sort[index++] = i+1;
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("time in cpu: %31.f ms\n", time);
// for(int i=0; i<LISTSIZE; i++) printf("%d ", sort[i]);
cudaFree(unsort_d);
cudaFree(table_d);
free(unsort);
free(table);
return 0;
} | code for sm_80
Function : _Z13gpu_countsortPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0xb60 ; /* 0x00000b2000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fe20003f45270 */
/*0060*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x002fca00078e0200 */
/*0070*/ ISETP.GT.AND P1, PT, R2, 0x98967f, PT ; /* 0x0098967f0200780c */
/* 0x000fce0003f24270 */
/*0080*/ @P2 BRA 0xb50 ; /* 0x00000ac000002947 */
/* 0x000fea0003800000 */
/*0090*/ STS.128 [RZ], RZ ; /* 0x000000ffff007388 */
/* 0x000fe20000000c00 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x12 ; /* 0x00000012ff007424 */
/* 0x000fe200078e00ff */
/*00b0*/ UMOV UR4, 0x48 ; /* 0x0000004800047882 */
/* 0x000fe40000000000 */
/*00c0*/ STS.128 [0x10], RZ ; /* 0x000010ffff007388 */
/* 0x000fe80000000c00 */
/*00d0*/ STS.128 [0x20], RZ ; /* 0x000020ffff007388 */
/* 0x000fe80000000c00 */
/*00e0*/ STS.128 [0x30], RZ ; /* 0x000030ffff007388 */
/* 0x000fe80000000c00 */
/*00f0*/ STS.64 [0x40], RZ ; /* 0x000040ffff007388 */
/* 0x000fe40000000a00 */
/*0100*/ IADD3 R0, R0, 0xa1, RZ ; /* 0x000000a100007810 */
/* 0x000fe20007ffe0ff */
/*0110*/ STS [UR4], RZ ; /* 0x000000ffff007988 */
/* 0x000fe60008000804 */
/*0120*/ ISETP.GE.U32.AND P0, PT, R0, 0x2710, PT ; /* 0x000027100000780c */
/* 0x000fe20003f06070 */
/*0130*/ STS [UR4+0x4], RZ ; /* 0x000004ffff007988 */
/* 0x000fe80008000804 */
/*0140*/ STS [UR4+0x8], RZ ; /* 0x000008ffff007988 */
/* 0x000fe80008000804 */
/*0150*/ STS [UR4+0xc], RZ ; /* 0x00000cffff007988 */
/* 0x000fe80008000804 */
/*0160*/ STS [UR4+0x10], RZ ; /* 0x000010ffff007988 */
/* 0x000fe80008000804 */
/*0170*/ STS [UR4+0x14], RZ ; /* 0x000014ffff007988 */
/* 0x000fe80008000804 */
/*0180*/ STS [UR4+0x18], RZ ; /* 0x000018ffff007988 */
/* 0x000fe80008000804 */
/*0190*/ STS [UR4+0x1c], RZ ; /* 0x00001cffff007988 */
/* 0x000fe80008000804 */
/*01a0*/ STS [UR4+0x20], RZ ; /* 0x000020ffff007988 */
/* 0x000fe80008000804 */
/*01b0*/ STS [UR4+0x24], RZ ; /* 0x000024ffff007988 */
/* 0x000fe80008000804 */
/*01c0*/ STS [UR4+0x28], RZ ; /* 0x000028ffff007988 */
/* 0x000fe80008000804 */
/*01d0*/ STS [UR4+0x2c], RZ ; /* 0x00002cffff007988 */
/* 0x000fe80008000804 */
/*01e0*/ STS [UR4+0x30], RZ ; /* 0x000030ffff007988 */
/* 0x000fe80008000804 */
/*01f0*/ STS [UR4+0x34], RZ ; /* 0x000034ffff007988 */
/* 0x000fe80008000804 */
/*0200*/ STS [UR4+0x38], RZ ; /* 0x000038ffff007988 */
/* 0x000fe80008000804 */
/*0210*/ STS [UR4+0x3c], RZ ; /* 0x00003cffff007988 */
/* 0x000fe80008000804 */
/*0220*/ STS [UR4+0x40], RZ ; /* 0x000040ffff007988 */
/* 0x000fe80008000804 */
/*0230*/ STS [UR4+0x44], RZ ; /* 0x000044ffff007988 */
/* 0x000fe80008000804 */
/*0240*/ STS [UR4+0x48], RZ ; /* 0x000048ffff007988 */
/* 0x000fe80008000804 */
/*0250*/ STS [UR4+0x4c], RZ ; /* 0x00004cffff007988 */
/* 0x000fe80008000804 */
/*0260*/ STS [UR4+0x50], RZ ; /* 0x000050ffff007988 */
/* 0x000fe80008000804 */
/*0270*/ STS [UR4+0x54], RZ ; /* 0x000054ffff007988 */
/* 0x000fe80008000804 */
/*0280*/ STS [UR4+0x58], RZ ; /* 0x000058ffff007988 */
/* 0x000fe80008000804 */
/*0290*/ STS [UR4+0x5c], RZ ; /* 0x00005cffff007988 */
/* 0x000fe80008000804 */
/*02a0*/ STS [UR4+0x60], RZ ; /* 0x000060ffff007988 */
/* 0x000fe80008000804 */
/*02b0*/ STS [UR4+0x64], RZ ; /* 0x000064ffff007988 */
/* 0x000fe80008000804 */
/*02c0*/ STS [UR4+0x68], RZ ; /* 0x000068ffff007988 */
/* 0x000fe80008000804 */
/*02d0*/ STS [UR4+0x6c], RZ ; /* 0x00006cffff007988 */
/* 0x000fe80008000804 */
/*02e0*/ STS [UR4+0x70], RZ ; /* 0x000070ffff007988 */
/* 0x000fe80008000804 */
/*02f0*/ STS [UR4+0x74], RZ ; /* 0x000074ffff007988 */
/* 0x000fe80008000804 */
/*0300*/ STS [UR4+0x78], RZ ; /* 0x000078ffff007988 */
/* 0x000fe80008000804 */
/*0310*/ STS [UR4+0x7c], RZ ; /* 0x00007cffff007988 */
/* 0x000fe80008000804 */
/*0320*/ STS [UR4+0x80], RZ ; /* 0x000080ffff007988 */
/* 0x000fe80008000804 */
/*0330*/ STS [UR4+0x84], RZ ; /* 0x000084ffff007988 */
/* 0x000fe80008000804 */
/*0340*/ STS [UR4+0x88], RZ ; /* 0x000088ffff007988 */
/* 0x000fe80008000804 */
/*0350*/ STS [UR4+0x8c], RZ ; /* 0x00008cffff007988 */
/* 0x000fe80008000804 */
/*0360*/ STS [UR4+0x90], RZ ; /* 0x000090ffff007988 */
/* 0x000fe80008000804 */
/*0370*/ STS [UR4+0x94], RZ ; /* 0x000094ffff007988 */
/* 0x000fe80008000804 */
/*0380*/ STS [UR4+0x98], RZ ; /* 0x000098ffff007988 */
/* 0x000fe80008000804 */
/*0390*/ STS [UR4+0x9c], RZ ; /* 0x00009cffff007988 */
/* 0x000fe80008000804 */
/*03a0*/ STS [UR4+0xa0], RZ ; /* 0x0000a0ffff007988 */
/* 0x000fe80008000804 */
/*03b0*/ STS [UR4+0xa4], RZ ; /* 0x0000a4ffff007988 */
/* 0x000fe80008000804 */
/*03c0*/ STS [UR4+0xa8], RZ ; /* 0x0000a8ffff007988 */
/* 0x000fe80008000804 */
/*03d0*/ STS [UR4+0xac], RZ ; /* 0x0000acffff007988 */
/* 0x000fe80008000804 */
/*03e0*/ STS [UR4+0xb0], RZ ; /* 0x0000b0ffff007988 */
/* 0x000fe80008000804 */
/*03f0*/ STS [UR4+0xb4], RZ ; /* 0x0000b4ffff007988 */
/* 0x000fe80008000804 */
/*0400*/ STS [UR4+0xb8], RZ ; /* 0x0000b8ffff007988 */
/* 0x000fe80008000804 */
/*0410*/ STS [UR4+0xbc], RZ ; /* 0x0000bcffff007988 */
/* 0x000fe80008000804 */
/*0420*/ STS [UR4+0xc0], RZ ; /* 0x0000c0ffff007988 */
/* 0x000fe80008000804 */
/*0430*/ STS [UR4+0xc4], RZ ; /* 0x0000c4ffff007988 */
/* 0x000fe80008000804 */
/*0440*/ STS [UR4+0xc8], RZ ; /* 0x0000c8ffff007988 */
/* 0x000fe80008000804 */
/*0450*/ STS [UR4+0xcc], RZ ; /* 0x0000ccffff007988 */
/* 0x000fe80008000804 */
/*0460*/ STS [UR4+0xd0], RZ ; /* 0x0000d0ffff007988 */
/* 0x000fe80008000804 */
/*0470*/ STS [UR4+0xd4], RZ ; /* 0x0000d4ffff007988 */
/* 0x000fe80008000804 */
/*0480*/ STS [UR4+0xd8], RZ ; /* 0x0000d8ffff007988 */
/* 0x000fe80008000804 */
/*0490*/ STS [UR4+0xdc], RZ ; /* 0x0000dcffff007988 */
/* 0x000fe80008000804 */
/*04a0*/ STS [UR4+0xe0], RZ ; /* 0x0000e0ffff007988 */
/* 0x000fe80008000804 */
/*04b0*/ STS [UR4+0xe4], RZ ; /* 0x0000e4ffff007988 */
/* 0x000fe80008000804 */
/*04c0*/ STS [UR4+0xe8], RZ ; /* 0x0000e8ffff007988 */
/* 0x000fe80008000804 */
/*04d0*/ STS [UR4+0xec], RZ ; /* 0x0000ecffff007988 */
/* 0x000fe80008000804 */
/*04e0*/ STS [UR4+0xf0], RZ ; /* 0x0000f0ffff007988 */
/* 0x000fe80008000804 */
/*04f0*/ STS [UR4+0xf4], RZ ; /* 0x0000f4ffff007988 */
/* 0x000fe80008000804 */
/*0500*/ STS [UR4+0xf8], RZ ; /* 0x0000f8ffff007988 */
/* 0x000fe80008000804 */
/*0510*/ STS [UR4+0xfc], RZ ; /* 0x0000fcffff007988 */
/* 0x000fe80008000804 */
/*0520*/ STS [UR4+0x100], RZ ; /* 0x000100ffff007988 */
/* 0x000fe80008000804 */
/*0530*/ STS [UR4+0x104], RZ ; /* 0x000104ffff007988 */
/* 0x000fe80008000804 */
/*0540*/ STS [UR4+0x108], RZ ; /* 0x000108ffff007988 */
/* 0x000fe80008000804 */
/*0550*/ STS [UR4+0x10c], RZ ; /* 0x00010cffff007988 */
/* 0x000fe80008000804 */
/*0560*/ STS [UR4+0x110], RZ ; /* 0x000110ffff007988 */
/* 0x000fe80008000804 */
/*0570*/ STS [UR4+0x114], RZ ; /* 0x000114ffff007988 */
/* 0x000fe80008000804 */
/*0580*/ STS [UR4+0x118], RZ ; /* 0x000118ffff007988 */
/* 0x000fe80008000804 */
/*0590*/ STS [UR4+0x11c], RZ ; /* 0x00011cffff007988 */
/* 0x000fe80008000804 */
/*05a0*/ STS [UR4+0x120], RZ ; /* 0x000120ffff007988 */
/* 0x000fe80008000804 */
/*05b0*/ STS [UR4+0x124], RZ ; /* 0x000124ffff007988 */
/* 0x000fe80008000804 */
/*05c0*/ STS [UR4+0x128], RZ ; /* 0x000128ffff007988 */
/* 0x000fe80008000804 */
/*05d0*/ STS [UR4+0x12c], RZ ; /* 0x00012cffff007988 */
/* 0x000fe80008000804 */
/*05e0*/ STS [UR4+0x130], RZ ; /* 0x000130ffff007988 */
/* 0x000fe80008000804 */
/*05f0*/ STS [UR4+0x134], RZ ; /* 0x000134ffff007988 */
/* 0x000fe80008000804 */
/*0600*/ STS [UR4+0x138], RZ ; /* 0x000138ffff007988 */
/* 0x000fe80008000804 */
/*0610*/ STS [UR4+0x13c], RZ ; /* 0x00013cffff007988 */
/* 0x000fe80008000804 */
/*0620*/ STS [UR4+0x140], RZ ; /* 0x000140ffff007988 */
/* 0x000fe80008000804 */
/*0630*/ STS [UR4+0x144], RZ ; /* 0x000144ffff007988 */
/* 0x000fe80008000804 */
/*0640*/ STS [UR4+0x148], RZ ; /* 0x000148ffff007988 */
/* 0x000fe80008000804 */
/*0650*/ STS [UR4+0x14c], RZ ; /* 0x00014cffff007988 */
/* 0x000fe80008000804 */
/*0660*/ STS [UR4+0x150], RZ ; /* 0x000150ffff007988 */
/* 0x000fe80008000804 */
/*0670*/ STS [UR4+0x154], RZ ; /* 0x000154ffff007988 */
/* 0x000fe80008000804 */
/*0680*/ STS [UR4+0x158], RZ ; /* 0x000158ffff007988 */
/* 0x000fe80008000804 */
/*0690*/ STS [UR4+0x15c], RZ ; /* 0x00015cffff007988 */
/* 0x000fe80008000804 */
/*06a0*/ STS [UR4+0x160], RZ ; /* 0x000160ffff007988 */
/* 0x000fe80008000804 */
/*06b0*/ STS [UR4+0x164], RZ ; /* 0x000164ffff007988 */
/* 0x000fe80008000804 */
/*06c0*/ STS [UR4+0x168], RZ ; /* 0x000168ffff007988 */
/* 0x000fe80008000804 */
/*06d0*/ STS [UR4+0x16c], RZ ; /* 0x00016cffff007988 */
/* 0x000fe80008000804 */
/*06e0*/ STS [UR4+0x170], RZ ; /* 0x000170ffff007988 */
/* 0x000fe80008000804 */
/*06f0*/ STS [UR4+0x174], RZ ; /* 0x000174ffff007988 */
/* 0x000fe80008000804 */
/*0700*/ STS [UR4+0x178], RZ ; /* 0x000178ffff007988 */
/* 0x000fe80008000804 */
/*0710*/ STS [UR4+0x17c], RZ ; /* 0x00017cffff007988 */
/* 0x000fe80008000804 */
/*0720*/ STS [UR4+0x180], RZ ; /* 0x000180ffff007988 */
/* 0x000fe80008000804 */
/*0730*/ STS [UR4+0x184], RZ ; /* 0x000184ffff007988 */
/* 0x000fe80008000804 */
/*0740*/ STS [UR4+0x188], RZ ; /* 0x000188ffff007988 */
/* 0x000fe80008000804 */
/*0750*/ STS [UR4+0x18c], RZ ; /* 0x00018cffff007988 */
/* 0x000fe80008000804 */
/*0760*/ STS [UR4+0x190], RZ ; /* 0x000190ffff007988 */
/* 0x000fe80008000804 */
/*0770*/ STS [UR4+0x194], RZ ; /* 0x000194ffff007988 */
/* 0x000fe80008000804 */
/*0780*/ STS [UR4+0x198], RZ ; /* 0x000198ffff007988 */
/* 0x000fe80008000804 */
/*0790*/ STS [UR4+0x19c], RZ ; /* 0x00019cffff007988 */
/* 0x000fe80008000804 */
/*07a0*/ STS [UR4+0x1a0], RZ ; /* 0x0001a0ffff007988 */
/* 0x000fe80008000804 */
/*07b0*/ STS [UR4+0x1a4], RZ ; /* 0x0001a4ffff007988 */
/* 0x000fe80008000804 */
/*07c0*/ STS [UR4+0x1a8], RZ ; /* 0x0001a8ffff007988 */
/* 0x000fe80008000804 */
/*07d0*/ STS [UR4+0x1ac], RZ ; /* 0x0001acffff007988 */
/* 0x000fe80008000804 */
/*07e0*/ STS [UR4+0x1b0], RZ ; /* 0x0001b0ffff007988 */
/* 0x000fe80008000804 */
/*07f0*/ STS [UR4+0x1b4], RZ ; /* 0x0001b4ffff007988 */
/* 0x000fe80008000804 */
/*0800*/ STS [UR4+0x1b8], RZ ; /* 0x0001b8ffff007988 */
/* 0x000fe80008000804 */
/*0810*/ STS [UR4+0x1bc], RZ ; /* 0x0001bcffff007988 */
/* 0x000fe80008000804 */
/*0820*/ STS [UR4+0x1c0], RZ ; /* 0x0001c0ffff007988 */
/* 0x000fe80008000804 */
/*0830*/ STS [UR4+0x1c4], RZ ; /* 0x0001c4ffff007988 */
/* 0x000fe80008000804 */
/*0840*/ STS [UR4+0x1c8], RZ ; /* 0x0001c8ffff007988 */
/* 0x000fe80008000804 */
/*0850*/ STS [UR4+0x1cc], RZ ; /* 0x0001ccffff007988 */
/* 0x000fe80008000804 */
/*0860*/ STS [UR4+0x1d0], RZ ; /* 0x0001d0ffff007988 */
/* 0x000fe80008000804 */
/*0870*/ STS [UR4+0x1d4], RZ ; /* 0x0001d4ffff007988 */
/* 0x000fe80008000804 */
/*0880*/ STS [UR4+0x1d8], RZ ; /* 0x0001d8ffff007988 */
/* 0x000fe80008000804 */
/*0890*/ STS [UR4+0x1dc], RZ ; /* 0x0001dcffff007988 */
/* 0x000fe80008000804 */
/*08a0*/ STS [UR4+0x1e0], RZ ; /* 0x0001e0ffff007988 */
/* 0x000fe80008000804 */
/*08b0*/ STS [UR4+0x1e4], RZ ; /* 0x0001e4ffff007988 */
/* 0x000fe80008000804 */
/*08c0*/ STS [UR4+0x1e8], RZ ; /* 0x0001e8ffff007988 */
/* 0x000fe80008000804 */
/*08d0*/ STS [UR4+0x1ec], RZ ; /* 0x0001ecffff007988 */
/* 0x000fe80008000804 */
/*08e0*/ STS [UR4+0x1f0], RZ ; /* 0x0001f0ffff007988 */
/* 0x000fe80008000804 */
/*08f0*/ STS [UR4+0x1f4], RZ ; /* 0x0001f4ffff007988 */
/* 0x000fe80008000804 */
/*0900*/ STS [UR4+0x1f8], RZ ; /* 0x0001f8ffff007988 */
/* 0x000fe80008000804 */
/*0910*/ STS [UR4+0x1fc], RZ ; /* 0x0001fcffff007988 */
/* 0x000fe80008000804 */
/*0920*/ STS [UR4+0x200], RZ ; /* 0x000200ffff007988 */
/* 0x000fe80008000804 */
/*0930*/ STS [UR4+0x204], RZ ; /* 0x000204ffff007988 */
/* 0x000fe80008000804 */
/*0940*/ STS [UR4+0x208], RZ ; /* 0x000208ffff007988 */
/* 0x000fe80008000804 */
/*0950*/ STS [UR4+0x20c], RZ ; /* 0x00020cffff007988 */
/* 0x000fe80008000804 */
/*0960*/ STS [UR4+0x210], RZ ; /* 0x000210ffff007988 */
/* 0x000fe80008000804 */
/*0970*/ STS [UR4+0x214], RZ ; /* 0x000214ffff007988 */
/* 0x000fe80008000804 */
/*0980*/ STS [UR4+0x218], RZ ; /* 0x000218ffff007988 */
/* 0x000fe80008000804 */
/*0990*/ STS [UR4+0x21c], RZ ; /* 0x00021cffff007988 */
/* 0x000fe80008000804 */
/*09a0*/ STS [UR4+0x220], RZ ; /* 0x000220ffff007988 */
/* 0x000fe80008000804 */
/*09b0*/ STS [UR4+0x224], RZ ; /* 0x000224ffff007988 */
/* 0x000fe80008000804 */
/*09c0*/ STS [UR4+0x228], RZ ; /* 0x000228ffff007988 */
/* 0x000fe80008000804 */
/*09d0*/ STS [UR4+0x22c], RZ ; /* 0x00022cffff007988 */
/* 0x000fe80008000804 */
/*09e0*/ STS [UR4+0x230], RZ ; /* 0x000230ffff007988 */
/* 0x000fe80008000804 */
/*09f0*/ STS [UR4+0x234], RZ ; /* 0x000234ffff007988 */
/* 0x000fe80008000804 */
/*0a00*/ STS [UR4+0x238], RZ ; /* 0x000238ffff007988 */
/* 0x000fe80008000804 */
/*0a10*/ STS [UR4+0x23c], RZ ; /* 0x00023cffff007988 */
/* 0x000fe80008000804 */
/*0a20*/ STS [UR4+0x240], RZ ; /* 0x000240ffff007988 */
/* 0x000fe80008000804 */
/*0a30*/ STS [UR4+0x244], RZ ; /* 0x000244ffff007988 */
/* 0x000fe80008000804 */
/*0a40*/ STS [UR4+0x248], RZ ; /* 0x000248ffff007988 */
/* 0x000fe80008000804 */
/*0a50*/ STS [UR4+0x24c], RZ ; /* 0x00024cffff007988 */
/* 0x000fe80008000804 */
/*0a60*/ STS [UR4+0x250], RZ ; /* 0x000250ffff007988 */
/* 0x000fe80008000804 */
/*0a70*/ STS [UR4+0x254], RZ ; /* 0x000254ffff007988 */
/* 0x000fe80008000804 */
/*0a80*/ STS [UR4+0x258], RZ ; /* 0x000258ffff007988 */
/* 0x000fe80008000804 */
/*0a90*/ STS [UR4+0x25c], RZ ; /* 0x00025cffff007988 */
/* 0x000fe80008000804 */
/*0aa0*/ STS [UR4+0x260], RZ ; /* 0x000260ffff007988 */
/* 0x000fe80008000804 */
/*0ab0*/ STS [UR4+0x264], RZ ; /* 0x000264ffff007988 */
/* 0x000fe80008000804 */
/*0ac0*/ STS [UR4+0x268], RZ ; /* 0x000268ffff007988 */
/* 0x000fe80008000804 */
/*0ad0*/ STS [UR4+0x26c], RZ ; /* 0x00026cffff007988 */
/* 0x000fe80008000804 */
/*0ae0*/ STS [UR4+0x270], RZ ; /* 0x000270ffff007988 */
/* 0x000fe80008000804 */
/*0af0*/ STS [UR4+0x274], RZ ; /* 0x000274ffff007988 */
/* 0x000fe80008000804 */
/*0b00*/ STS [UR4+0x278], RZ ; /* 0x000278ffff007988 */
/* 0x000fe80008000804 */
/*0b10*/ STS [UR4+0x27c], RZ ; /* 0x00027cffff007988 */
/* 0x000fe80008000804 */
/*0b20*/ STS [UR4+0x280], RZ ; /* 0x000280ffff007988 */
/* 0x000fe20008000804 */
/*0b30*/ UIADD3 UR4, UR4, 0x284, URZ ; /* 0x0000028404047890 */
/* 0x000fe2000fffe03f */
/*0b40*/ @!P0 BRA 0x100 ; /* 0xfffff5b000008947 */
/* 0x000fee000383ffff */
/*0b50*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b60*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0b70*/ BSSY B0, 0xbe0 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0b80*/ @P1 BRA 0xbd0 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*0b90*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0ba0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0203 */
/*0bb0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*0bc0*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ+-0x4] ; /* 0xfffffc0002ff7f8c */
/* 0x0041e4000d00403f */
/*0bd0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0be0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0bf0*/ @P2 EXIT ; /* 0x000000000000294d */
/* 0x000fea0003800000 */
/*0c00*/ MOV R20, c[0x0][0x160] ; /* 0x0000580000147a02 */
/* 0x000fe20000000f00 */
/*0c10*/ IMAD.MOV.U32 R21, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff157624 */
/* 0x000fe200078e00ff */
/*0c20*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0c30*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fc400078e00ff */
/*0c40*/ LDS.128 R4, [UR4] ; /* 0x00000004ff047984 */
/* 0x002e620008000c00 */
/*0c50*/ MOV R2, R20 ; /* 0x0000001400027202 */
/* 0x001fe20000000f00 */
/*0c60*/ IMAD.MOV.U32 R3, RZ, RZ, R21 ; /* 0x000000ffff037224 */
/* 0x000fc400078e0015 */
/*0c70*/ LDS.128 R8, [UR4+0x10] ; /* 0x00001004ff087984 */
/* 0x000e280008000c00 */
/*0c80*/ LDS.128 R12, [UR4+0x20] ; /* 0x00002004ff0c7984 */
/* 0x000ea80008000c00 */
/*0c90*/ LDS.128 R16, [UR4+0x30] ; /* 0x00003004ff107984 */
/* 0x000ee20008000c00 */
/*0ca0*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x000fc80007ffe0ff */
/*0cb0*/ ISETP.NE.AND P0, PT, R0, 0x2710, PT ; /* 0x000027100000780c */
/* 0x000fe20003f05270 */
/*0cc0*/ UIADD3 UR4, UR4, 0x40, URZ ; /* 0x0000004004047890 */
/* 0x000fe2000fffe03f */
/*0cd0*/ IADD3 R20, P1, R2, 0x40, RZ ; /* 0x0000004002147810 */
/* 0x000fe20007f3e0ff */
/*0ce0*/ RED.E.ADD.STRONG.GPU [R2.64], R4 ; /* 0x000000040200798e */
/* 0x0023e8000c10e186 */
/*0cf0*/ RED.E.ADD.STRONG.GPU [R2.64+0x4], R5 ; /* 0x000004050200798e */
/* 0x0003e8000c10e186 */
/*0d00*/ RED.E.ADD.STRONG.GPU [R2.64+0x8], R6 ; /* 0x000008060200798e */
/* 0x0003e8000c10e186 */
/*0d10*/ RED.E.ADD.STRONG.GPU [R2.64+0xc], R7 ; /* 0x00000c070200798e */
/* 0x0003e8000c10e186 */
/*0d20*/ RED.E.ADD.STRONG.GPU [R2.64+0x10], R8 ; /* 0x000010080200798e */
/* 0x0013e8000c10e186 */
/*0d30*/ RED.E.ADD.STRONG.GPU [R2.64+0x14], R9 ; /* 0x000014090200798e */
/* 0x0003e8000c10e186 */
/*0d40*/ RED.E.ADD.STRONG.GPU [R2.64+0x18], R10 ; /* 0x0000180a0200798e */
/* 0x0003e8000c10e186 */
/*0d50*/ RED.E.ADD.STRONG.GPU [R2.64+0x1c], R11 ; /* 0x00001c0b0200798e */
/* 0x0003e8000c10e186 */
/*0d60*/ RED.E.ADD.STRONG.GPU [R2.64+0x20], R12 ; /* 0x0000200c0200798e */
/* 0x0043e8000c10e186 */
/*0d70*/ RED.E.ADD.STRONG.GPU [R2.64+0x24], R13 ; /* 0x0000240d0200798e */
/* 0x0003e8000c10e186 */
/*0d80*/ RED.E.ADD.STRONG.GPU [R2.64+0x28], R14 ; /* 0x0000280e0200798e */
/* 0x0003e8000c10e186 */
/*0d90*/ RED.E.ADD.STRONG.GPU [R2.64+0x2c], R15 ; /* 0x00002c0f0200798e */
/* 0x0003e8000c10e186 */
/*0da0*/ RED.E.ADD.STRONG.GPU [R2.64+0x30], R16 ; /* 0x000030100200798e */
/* 0x0083e8000c10e186 */
/*0db0*/ RED.E.ADD.STRONG.GPU [R2.64+0x34], R17 ; /* 0x000034110200798e */
/* 0x0003e8000c10e186 */
/*0dc0*/ RED.E.ADD.STRONG.GPU [R2.64+0x38], R18 ; /* 0x000038120200798e */
/* 0x0003e2000c10e186 */
/*0dd0*/ IADD3.X R21, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff157210 */
/* 0x000fc60000ffe4ff */
/*0de0*/ RED.E.ADD.STRONG.GPU [R2.64+0x3c], R19 ; /* 0x00003c130200798e */
/* 0x0003e2000c10e186 */
/*0df0*/ @P0 BRA 0xc40 ; /* 0xfffffe4000000947 */
/* 0x000fea000383ffff */
/*0e00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e10*/ BRA 0xe10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define LISTSIZE 10000000
#define MAXNUM 10000
#define THREAD_PER_BLOCK 1024
__global__ void gpu_countsort(int* globalTable_d, int* unsort){
__shared__ int table[MAXNUM];
if(threadIdx.x == 0) memset(table, 0, sizeof(int)*MAXNUM);
__syncthreads();//block level synchronization
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < LISTSIZE){
int num = unsort[index];
atomicAdd(&table[num-1], 1);
}
__syncthreads();
if(threadIdx.x == 0){
for(int i=0; i<MAXNUM; i++){
atomicAdd(&(globalTable_d[i]), table[i]);
}
}
}
void genList(int** unsort){
*unsort = (int*)malloc(sizeof(int) * LISTSIZE);
for(int i=0; i<LISTSIZE; i++){
(*unsort)[i] = rand()%MAXNUM + 1;
}
}
int main()
{
float time;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int *unsort;
genList(&unsort);
int *unsort_d, *table_d;
int listSize = LISTSIZE * sizeof(int);
int tableSize = MAXNUM * sizeof(int);
cudaMalloc((void**)&unsort_d, listSize);
cudaMemcpy(unsort_d, unsort, listSize, cudaMemcpyHostToDevice);
cudaMalloc((void**)&table_d, tableSize);
cudaMemset(table_d, 0, tableSize);
int blockNum;
blockNum = (LISTSIZE/THREAD_PER_BLOCK) + ( LISTSIZE%THREAD_PER_BLOCK==0 ?0:1 );
cudaEventRecord(start, 0);
gpu_countsort<<<blockNum, THREAD_PER_BLOCK>>>(table_d, unsort_d);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
cudaDeviceSynchronize();
printf("time in gpu: %31.f ms\n", time);
int *table, *sort;
sort = (int*)malloc(listSize);
memset(sort, 0, listSize);
table = (int*)malloc(tableSize);
cudaMemcpy(table, table_d, tableSize, cudaMemcpyDeviceToHost);
int index=0;
for(int i=0; i<MAXNUM; i++){
for(int j=0; j<table[i]; j++) sort[index++] = i+1;
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("time in cpu: %31.f ms\n", time);
// for(int i=0; i<LISTSIZE; i++) printf("%d ", sort[i]);
cudaFree(unsort_d);
cudaFree(table_d);
free(unsort);
free(table);
return 0;
} | .file "tmpxft_0013ca3a_00000000-6_countsort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7genListPPi
.type _Z7genListPPi, @function
_Z7genListPPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
movl $40000000, %edi
call malloc@PLT
movq %rax, 0(%rbp)
movl $0, %ebx
.L4:
call rand@PLT
movq 0(%rbp), %rcx
movslq %eax, %rdx
imulq $1759218605, %rdx, %rdx
sarq $44, %rdx
movl %eax, %esi
sarl $31, %esi
subl %esi, %edx
imull $10000, %edx, %edx
subl %edx, %eax
addl $1, %eax
movl %eax, (%rcx,%rbx)
addq $4, %rbx
cmpq $40000000, %rbx
jne .L4
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z7genListPPi, .-_Z7genListPPi
.globl _Z35__device_stub__Z13gpu_countsortPiS_PiS_
.type _Z35__device_stub__Z13gpu_countsortPiS_PiS_, @function
_Z35__device_stub__Z13gpu_countsortPiS_PiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13gpu_countsortPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z35__device_stub__Z13gpu_countsortPiS_PiS_, .-_Z35__device_stub__Z13gpu_countsortPiS_PiS_
.globl _Z13gpu_countsortPiS_
.type _Z13gpu_countsortPiS_, @function
_Z13gpu_countsortPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13gpu_countsortPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13gpu_countsortPiS_, .-_Z13gpu_countsortPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "time in gpu: %31.f ms\n"
.LC1:
.string "time in cpu: %31.f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call _Z7genListPPi
leaq 32(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
movq 24(%rsp), %r12
movl $1, %ecx
movl $40000000, %edx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 40(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl $40000, %edx
movl $0, %esi
movq 40(%rsp), %rdi
call cudaMemset@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $9766, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L16:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
call cudaDeviceSynchronize@PLT
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $40000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $40000000, %edx
movl $0, %esi
movq %rax, %rdi
call memset@PLT
movl $40000, %edi
call malloc@PLT
movq %rax, %rbp
movl $2, %ecx
movl $40000, %edx
movq 40(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movl $1, %edx
movl $0, %edi
jmp .L17
.L25:
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z35__device_stub__Z13gpu_countsortPiS_PiS_
jmp .L16
.L20:
movslq %edi, %r8
leaq (%rbx,%r8,4), %rax
movslq %esi, %rcx
addq %r8, %rcx
leaq (%rbx,%rcx,4), %rcx
.L18:
movl %edx, (%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L18
addl %esi, %edi
.L21:
addq $1, %rdx
cmpq $10001, %rdx
je .L19
.L17:
movl -4(%rbp,%rdx,4), %esi
testl %esi, %esi
jg .L20
jmp .L21
.L19:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z13gpu_countsortPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13gpu_countsortPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define LISTSIZE 10000000
#define MAXNUM 10000
#define THREAD_PER_BLOCK 1024
__global__ void gpu_countsort(int* globalTable_d, int* unsort){
__shared__ int table[MAXNUM];
if(threadIdx.x == 0) memset(table, 0, sizeof(int)*MAXNUM);
__syncthreads();//block level synchronization
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < LISTSIZE){
int num = unsort[index];
atomicAdd(&table[num-1], 1);
}
__syncthreads();
if(threadIdx.x == 0){
for(int i=0; i<MAXNUM; i++){
atomicAdd(&(globalTable_d[i]), table[i]);
}
}
}
void genList(int** unsort){
*unsort = (int*)malloc(sizeof(int) * LISTSIZE);
for(int i=0; i<LISTSIZE; i++){
(*unsort)[i] = rand()%MAXNUM + 1;
}
}
int main()
{
float time;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int *unsort;
genList(&unsort);
int *unsort_d, *table_d;
int listSize = LISTSIZE * sizeof(int);
int tableSize = MAXNUM * sizeof(int);
cudaMalloc((void**)&unsort_d, listSize);
cudaMemcpy(unsort_d, unsort, listSize, cudaMemcpyHostToDevice);
cudaMalloc((void**)&table_d, tableSize);
cudaMemset(table_d, 0, tableSize);
int blockNum;
blockNum = (LISTSIZE/THREAD_PER_BLOCK) + ( LISTSIZE%THREAD_PER_BLOCK==0 ?0:1 );
cudaEventRecord(start, 0);
gpu_countsort<<<blockNum, THREAD_PER_BLOCK>>>(table_d, unsort_d);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
cudaDeviceSynchronize();
printf("time in gpu: %31.f ms\n", time);
int *table, *sort;
sort = (int*)malloc(listSize);
memset(sort, 0, listSize);
table = (int*)malloc(tableSize);
cudaMemcpy(table, table_d, tableSize, cudaMemcpyDeviceToHost);
int index=0;
for(int i=0; i<MAXNUM; i++){
for(int j=0; j<table[i]; j++) sort[index++] = i+1;
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("time in cpu: %31.f ms\n", time);
// for(int i=0; i<LISTSIZE; i++) printf("%d ", sort[i]);
cudaFree(unsort_d);
cudaFree(table_d);
free(unsort);
free(table);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define LISTSIZE 10000000
#define MAXNUM 10000
#define THREAD_PER_BLOCK 1024
__global__ void gpu_countsort(int* globalTable_d, int* unsort){
__shared__ int table[MAXNUM];
if(threadIdx.x == 0) memset(table, 0, sizeof(int)*MAXNUM);
__syncthreads();//block level synchronization
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < LISTSIZE){
int num = unsort[index];
atomicAdd(&table[num-1], 1);
}
__syncthreads();
if(threadIdx.x == 0){
for(int i=0; i<MAXNUM; i++){
atomicAdd(&(globalTable_d[i]), table[i]);
}
}
}
void genList(int** unsort){
*unsort = (int*)malloc(sizeof(int) * LISTSIZE);
for(int i=0; i<LISTSIZE; i++){
(*unsort)[i] = rand()%MAXNUM + 1;
}
}
int main()
{
float time;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int *unsort;
genList(&unsort);
int *unsort_d, *table_d;
int listSize = LISTSIZE * sizeof(int);
int tableSize = MAXNUM * sizeof(int);
hipMalloc((void**)&unsort_d, listSize);
hipMemcpy(unsort_d, unsort, listSize, hipMemcpyHostToDevice);
hipMalloc((void**)&table_d, tableSize);
hipMemset(table_d, 0, tableSize);
int blockNum;
blockNum = (LISTSIZE/THREAD_PER_BLOCK) + ( LISTSIZE%THREAD_PER_BLOCK==0 ?0:1 );
hipEventRecord(start, 0);
gpu_countsort<<<blockNum, THREAD_PER_BLOCK>>>(table_d, unsort_d);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
hipDeviceSynchronize();
printf("time in gpu: %31.f ms\n", time);
int *table, *sort;
sort = (int*)malloc(listSize);
memset(sort, 0, listSize);
table = (int*)malloc(tableSize);
hipMemcpy(table, table_d, tableSize, hipMemcpyDeviceToHost);
int index=0;
for(int i=0; i<MAXNUM; i++){
for(int j=0; j<table[i]; j++) sort[index++] = i+1;
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("time in cpu: %31.f ms\n", time);
// for(int i=0; i<LISTSIZE; i++) printf("%d ", sort[i]);
hipFree(unsort_d);
hipFree(table_d);
free(unsort);
free(table);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define LISTSIZE 10000000
#define MAXNUM 10000
#define THREAD_PER_BLOCK 1024
__global__ void gpu_countsort(int* globalTable_d, int* unsort){
__shared__ int table[MAXNUM];
if(threadIdx.x == 0) memset(table, 0, sizeof(int)*MAXNUM);
__syncthreads();//block level synchronization
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < LISTSIZE){
int num = unsort[index];
atomicAdd(&table[num-1], 1);
}
__syncthreads();
if(threadIdx.x == 0){
for(int i=0; i<MAXNUM; i++){
atomicAdd(&(globalTable_d[i]), table[i]);
}
}
}
void genList(int** unsort){
*unsort = (int*)malloc(sizeof(int) * LISTSIZE);
for(int i=0; i<LISTSIZE; i++){
(*unsort)[i] = rand()%MAXNUM + 1;
}
}
int main()
{
float time;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int *unsort;
genList(&unsort);
int *unsort_d, *table_d;
int listSize = LISTSIZE * sizeof(int);
int tableSize = MAXNUM * sizeof(int);
hipMalloc((void**)&unsort_d, listSize);
hipMemcpy(unsort_d, unsort, listSize, hipMemcpyHostToDevice);
hipMalloc((void**)&table_d, tableSize);
hipMemset(table_d, 0, tableSize);
int blockNum;
blockNum = (LISTSIZE/THREAD_PER_BLOCK) + ( LISTSIZE%THREAD_PER_BLOCK==0 ?0:1 );
hipEventRecord(start, 0);
gpu_countsort<<<blockNum, THREAD_PER_BLOCK>>>(table_d, unsort_d);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
hipDeviceSynchronize();
printf("time in gpu: %31.f ms\n", time);
int *table, *sort;
sort = (int*)malloc(listSize);
memset(sort, 0, listSize);
table = (int*)malloc(tableSize);
hipMemcpy(table, table_d, tableSize, hipMemcpyDeviceToHost);
int index=0;
for(int i=0; i<MAXNUM; i++){
for(int j=0; j<table[i]; j++) sort[index++] = i+1;
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("time in cpu: %31.f ms\n", time);
// for(int i=0; i<LISTSIZE; i++) printf("%d ", sort[i]);
hipFree(unsort_d);
hipFree(table_d);
free(unsort);
free(table);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13gpu_countsortPiS_
.globl _Z13gpu_countsortPiS_
.p2align 8
.type _Z13gpu_countsortPiS_,@function
_Z13gpu_countsortPiS_:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s5, 0
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v1, 0
s_mov_b32 s2, 0xffff63c0
s_mov_b32 s3, -1
.LBB0_2:
v_mov_b32_e32 v2, s5
s_add_i32 s5, s5, 4
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
ds_store_b8 v2, v1
ds_store_b8 v2, v1 offset:1
ds_store_b8 v2, v1 offset:2
ds_store_b8 v2, v1 offset:3
s_cmp_lg_u64 s[2:3], 0
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_load_b32 s2, s[0:1], 0x1c
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmpx_gt_i32_e32 0x989680, v1
s_cbranch_execz .LBB0_5
s_load_b64 s[4:5], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, s2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s2, s5, v1, s2
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 1
s_waitcnt vmcnt(0)
v_lshl_add_u32 v0, v0, 2, -4
ds_add_u32 v0, v1
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_10
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b32 s2, 0
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s2, s2, 4
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmpk_lg_u32 s2, 0x9c40
s_cbranch_scc0 .LBB0_10
.LBB0_8:
s_mov_b32 s4, exec_lo
s_mov_b32 s3, exec_lo
v_mbcnt_lo_u32_b32 v1, s4, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v1, s2
s_bcnt1_i32_b32 s4, s4
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, v1, s4
global_atomic_add_u32 v0, v1, s[0:1]
s_branch .LBB0_7
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13gpu_countsortPiS_
.amdhsa_group_segment_fixed_size 40000
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13gpu_countsortPiS_, .Lfunc_end0-_Z13gpu_countsortPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 40000
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13gpu_countsortPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13gpu_countsortPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define LISTSIZE 10000000
#define MAXNUM 10000
#define THREAD_PER_BLOCK 1024
__global__ void gpu_countsort(int* globalTable_d, int* unsort){
__shared__ int table[MAXNUM];
if(threadIdx.x == 0) memset(table, 0, sizeof(int)*MAXNUM);
__syncthreads();//block level synchronization
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < LISTSIZE){
int num = unsort[index];
atomicAdd(&table[num-1], 1);
}
__syncthreads();
if(threadIdx.x == 0){
for(int i=0; i<MAXNUM; i++){
atomicAdd(&(globalTable_d[i]), table[i]);
}
}
}
void genList(int** unsort){
*unsort = (int*)malloc(sizeof(int) * LISTSIZE);
for(int i=0; i<LISTSIZE; i++){
(*unsort)[i] = rand()%MAXNUM + 1;
}
}
int main()
{
float time;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int *unsort;
genList(&unsort);
int *unsort_d, *table_d;
int listSize = LISTSIZE * sizeof(int);
int tableSize = MAXNUM * sizeof(int);
hipMalloc((void**)&unsort_d, listSize);
hipMemcpy(unsort_d, unsort, listSize, hipMemcpyHostToDevice);
hipMalloc((void**)&table_d, tableSize);
hipMemset(table_d, 0, tableSize);
int blockNum;
blockNum = (LISTSIZE/THREAD_PER_BLOCK) + ( LISTSIZE%THREAD_PER_BLOCK==0 ?0:1 );
hipEventRecord(start, 0);
gpu_countsort<<<blockNum, THREAD_PER_BLOCK>>>(table_d, unsort_d);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
hipDeviceSynchronize();
printf("time in gpu: %31.f ms\n", time);
int *table, *sort;
sort = (int*)malloc(listSize);
memset(sort, 0, listSize);
table = (int*)malloc(tableSize);
hipMemcpy(table, table_d, tableSize, hipMemcpyDeviceToHost);
int index=0;
for(int i=0; i<MAXNUM; i++){
for(int j=0; j<table[i]; j++) sort[index++] = i+1;
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("time in cpu: %31.f ms\n", time);
// for(int i=0; i<LISTSIZE; i++) printf("%d ", sort[i]);
hipFree(unsort_d);
hipFree(table_d);
free(unsort);
free(table);
return 0;
} | .text
.file "countsort.hip"
.globl _Z28__device_stub__gpu_countsortPiS_ # -- Begin function _Z28__device_stub__gpu_countsortPiS_
.p2align 4, 0x90
.type _Z28__device_stub__gpu_countsortPiS_,@function
_Z28__device_stub__gpu_countsortPiS_: # @_Z28__device_stub__gpu_countsortPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13gpu_countsortPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__gpu_countsortPiS_, .Lfunc_end0-_Z28__device_stub__gpu_countsortPiS_
.cfi_endproc
# -- End function
.globl _Z7genListPPi # -- Begin function _Z7genListPPi
.p2align 4, 0x90
.type _Z7genListPPi,@function
_Z7genListPPi: # @_Z7genListPPi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, (%rbx)
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1759218605, %rax, %rcx # imm = 0x68DB8BAD
movq %rcx, %rdx
shrq $63, %rdx
sarq $44, %rcx
addl %edx, %ecx
imull $10000, %ecx, %ecx # imm = 0x2710
negl %ecx
addl %ecx, %eax
incl %eax
movq (%rbx), %rcx
movl %eax, (%rcx,%r14,4)
incq %r14
cmpq $10000000, %r14 # imm = 0x989680
jne .LBB1_1
# %bb.2:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z7genListPPi, .Lfunc_end1-_Z7genListPPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1759218605, %rax, %rcx # imm = 0x68DB8BAD
movq %rcx, %rdx
shrq $63, %rdx
sarq $44, %rcx
addl %edx, %ecx
imull $10000, %ecx, %ecx # imm = 0x2710
negl %ecx
addl %ecx, %eax
incl %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $10000000, %r14 # imm = 0x989680
jne .LBB2_1
# %bb.2: # %_Z7genListPPi.exit
leaq 16(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
movq 16(%rsp), %rdi
movl $40000000, %edx # imm = 0x2625A00
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movq 8(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
xorl %esi, %esi
callq hipMemset
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 8742(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 32(%rsp)
leaq 96(%rsp), %rax
movq %rax, 40(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z13gpu_countsortPiS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq (%rsp), %rdx
leaq 32(%rsp), %r15
movq %r15, %rdi
callq hipEventElapsedTime
callq hipDeviceSynchronize
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r14
movq 8(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq (%rsp), %rdx
movq %r15, %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13gpu_countsortPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13gpu_countsortPiS_,@object # @_Z13gpu_countsortPiS_
.section .rodata,"a",@progbits
.globl _Z13gpu_countsortPiS_
.p2align 3, 0x0
_Z13gpu_countsortPiS_:
.quad _Z28__device_stub__gpu_countsortPiS_
.size _Z13gpu_countsortPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "time in gpu: %31.f ms\n"
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "time in cpu: %31.f ms\n"
.size .L.str.1, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13gpu_countsortPiS_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__gpu_countsortPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13gpu_countsortPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13gpu_countsortPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0xb60 ; /* 0x00000b2000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fe20003f45270 */
/*0060*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x002fca00078e0200 */
/*0070*/ ISETP.GT.AND P1, PT, R2, 0x98967f, PT ; /* 0x0098967f0200780c */
/* 0x000fce0003f24270 */
/*0080*/ @P2 BRA 0xb50 ; /* 0x00000ac000002947 */
/* 0x000fea0003800000 */
/*0090*/ STS.128 [RZ], RZ ; /* 0x000000ffff007388 */
/* 0x000fe20000000c00 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x12 ; /* 0x00000012ff007424 */
/* 0x000fe200078e00ff */
/*00b0*/ UMOV UR4, 0x48 ; /* 0x0000004800047882 */
/* 0x000fe40000000000 */
/*00c0*/ STS.128 [0x10], RZ ; /* 0x000010ffff007388 */
/* 0x000fe80000000c00 */
/*00d0*/ STS.128 [0x20], RZ ; /* 0x000020ffff007388 */
/* 0x000fe80000000c00 */
/*00e0*/ STS.128 [0x30], RZ ; /* 0x000030ffff007388 */
/* 0x000fe80000000c00 */
/*00f0*/ STS.64 [0x40], RZ ; /* 0x000040ffff007388 */
/* 0x000fe40000000a00 */
/*0100*/ IADD3 R0, R0, 0xa1, RZ ; /* 0x000000a100007810 */
/* 0x000fe20007ffe0ff */
/*0110*/ STS [UR4], RZ ; /* 0x000000ffff007988 */
/* 0x000fe60008000804 */
/*0120*/ ISETP.GE.U32.AND P0, PT, R0, 0x2710, PT ; /* 0x000027100000780c */
/* 0x000fe20003f06070 */
/*0130*/ STS [UR4+0x4], RZ ; /* 0x000004ffff007988 */
/* 0x000fe80008000804 */
/*0140*/ STS [UR4+0x8], RZ ; /* 0x000008ffff007988 */
/* 0x000fe80008000804 */
/*0150*/ STS [UR4+0xc], RZ ; /* 0x00000cffff007988 */
/* 0x000fe80008000804 */
/*0160*/ STS [UR4+0x10], RZ ; /* 0x000010ffff007988 */
/* 0x000fe80008000804 */
/*0170*/ STS [UR4+0x14], RZ ; /* 0x000014ffff007988 */
/* 0x000fe80008000804 */
/*0180*/ STS [UR4+0x18], RZ ; /* 0x000018ffff007988 */
/* 0x000fe80008000804 */
/*0190*/ STS [UR4+0x1c], RZ ; /* 0x00001cffff007988 */
/* 0x000fe80008000804 */
/*01a0*/ STS [UR4+0x20], RZ ; /* 0x000020ffff007988 */
/* 0x000fe80008000804 */
/*01b0*/ STS [UR4+0x24], RZ ; /* 0x000024ffff007988 */
/* 0x000fe80008000804 */
/*01c0*/ STS [UR4+0x28], RZ ; /* 0x000028ffff007988 */
/* 0x000fe80008000804 */
/*01d0*/ STS [UR4+0x2c], RZ ; /* 0x00002cffff007988 */
/* 0x000fe80008000804 */
/*01e0*/ STS [UR4+0x30], RZ ; /* 0x000030ffff007988 */
/* 0x000fe80008000804 */
/*01f0*/ STS [UR4+0x34], RZ ; /* 0x000034ffff007988 */
/* 0x000fe80008000804 */
/*0200*/ STS [UR4+0x38], RZ ; /* 0x000038ffff007988 */
/* 0x000fe80008000804 */
/*0210*/ STS [UR4+0x3c], RZ ; /* 0x00003cffff007988 */
/* 0x000fe80008000804 */
/*0220*/ STS [UR4+0x40], RZ ; /* 0x000040ffff007988 */
/* 0x000fe80008000804 */
/*0230*/ STS [UR4+0x44], RZ ; /* 0x000044ffff007988 */
/* 0x000fe80008000804 */
/*0240*/ STS [UR4+0x48], RZ ; /* 0x000048ffff007988 */
/* 0x000fe80008000804 */
/*0250*/ STS [UR4+0x4c], RZ ; /* 0x00004cffff007988 */
/* 0x000fe80008000804 */
/*0260*/ STS [UR4+0x50], RZ ; /* 0x000050ffff007988 */
/* 0x000fe80008000804 */
/*0270*/ STS [UR4+0x54], RZ ; /* 0x000054ffff007988 */
/* 0x000fe80008000804 */
/*0280*/ STS [UR4+0x58], RZ ; /* 0x000058ffff007988 */
/* 0x000fe80008000804 */
/*0290*/ STS [UR4+0x5c], RZ ; /* 0x00005cffff007988 */
/* 0x000fe80008000804 */
/*02a0*/ STS [UR4+0x60], RZ ; /* 0x000060ffff007988 */
/* 0x000fe80008000804 */
/*02b0*/ STS [UR4+0x64], RZ ; /* 0x000064ffff007988 */
/* 0x000fe80008000804 */
/*02c0*/ STS [UR4+0x68], RZ ; /* 0x000068ffff007988 */
/* 0x000fe80008000804 */
/*02d0*/ STS [UR4+0x6c], RZ ; /* 0x00006cffff007988 */
/* 0x000fe80008000804 */
/*02e0*/ STS [UR4+0x70], RZ ; /* 0x000070ffff007988 */
/* 0x000fe80008000804 */
/*02f0*/ STS [UR4+0x74], RZ ; /* 0x000074ffff007988 */
/* 0x000fe80008000804 */
/*0300*/ STS [UR4+0x78], RZ ; /* 0x000078ffff007988 */
/* 0x000fe80008000804 */
/*0310*/ STS [UR4+0x7c], RZ ; /* 0x00007cffff007988 */
/* 0x000fe80008000804 */
/*0320*/ STS [UR4+0x80], RZ ; /* 0x000080ffff007988 */
/* 0x000fe80008000804 */
/*0330*/ STS [UR4+0x84], RZ ; /* 0x000084ffff007988 */
/* 0x000fe80008000804 */
/*0340*/ STS [UR4+0x88], RZ ; /* 0x000088ffff007988 */
/* 0x000fe80008000804 */
/*0350*/ STS [UR4+0x8c], RZ ; /* 0x00008cffff007988 */
/* 0x000fe80008000804 */
/*0360*/ STS [UR4+0x90], RZ ; /* 0x000090ffff007988 */
/* 0x000fe80008000804 */
/*0370*/ STS [UR4+0x94], RZ ; /* 0x000094ffff007988 */
/* 0x000fe80008000804 */
/*0380*/ STS [UR4+0x98], RZ ; /* 0x000098ffff007988 */
/* 0x000fe80008000804 */
/*0390*/ STS [UR4+0x9c], RZ ; /* 0x00009cffff007988 */
/* 0x000fe80008000804 */
/*03a0*/ STS [UR4+0xa0], RZ ; /* 0x0000a0ffff007988 */
/* 0x000fe80008000804 */
/*03b0*/ STS [UR4+0xa4], RZ ; /* 0x0000a4ffff007988 */
/* 0x000fe80008000804 */
/*03c0*/ STS [UR4+0xa8], RZ ; /* 0x0000a8ffff007988 */
/* 0x000fe80008000804 */
/*03d0*/ STS [UR4+0xac], RZ ; /* 0x0000acffff007988 */
/* 0x000fe80008000804 */
/*03e0*/ STS [UR4+0xb0], RZ ; /* 0x0000b0ffff007988 */
/* 0x000fe80008000804 */
/*03f0*/ STS [UR4+0xb4], RZ ; /* 0x0000b4ffff007988 */
/* 0x000fe80008000804 */
/*0400*/ STS [UR4+0xb8], RZ ; /* 0x0000b8ffff007988 */
/* 0x000fe80008000804 */
/*0410*/ STS [UR4+0xbc], RZ ; /* 0x0000bcffff007988 */
/* 0x000fe80008000804 */
/*0420*/ STS [UR4+0xc0], RZ ; /* 0x0000c0ffff007988 */
/* 0x000fe80008000804 */
/*0430*/ STS [UR4+0xc4], RZ ; /* 0x0000c4ffff007988 */
/* 0x000fe80008000804 */
/*0440*/ STS [UR4+0xc8], RZ ; /* 0x0000c8ffff007988 */
/* 0x000fe80008000804 */
/*0450*/ STS [UR4+0xcc], RZ ; /* 0x0000ccffff007988 */
/* 0x000fe80008000804 */
/*0460*/ STS [UR4+0xd0], RZ ; /* 0x0000d0ffff007988 */
/* 0x000fe80008000804 */
/*0470*/ STS [UR4+0xd4], RZ ; /* 0x0000d4ffff007988 */
/* 0x000fe80008000804 */
/*0480*/ STS [UR4+0xd8], RZ ; /* 0x0000d8ffff007988 */
/* 0x000fe80008000804 */
/*0490*/ STS [UR4+0xdc], RZ ; /* 0x0000dcffff007988 */
/* 0x000fe80008000804 */
/*04a0*/ STS [UR4+0xe0], RZ ; /* 0x0000e0ffff007988 */
/* 0x000fe80008000804 */
/*04b0*/ STS [UR4+0xe4], RZ ; /* 0x0000e4ffff007988 */
/* 0x000fe80008000804 */
/*04c0*/ STS [UR4+0xe8], RZ ; /* 0x0000e8ffff007988 */
/* 0x000fe80008000804 */
/*04d0*/ STS [UR4+0xec], RZ ; /* 0x0000ecffff007988 */
/* 0x000fe80008000804 */
/*04e0*/ STS [UR4+0xf0], RZ ; /* 0x0000f0ffff007988 */
/* 0x000fe80008000804 */
/*04f0*/ STS [UR4+0xf4], RZ ; /* 0x0000f4ffff007988 */
/* 0x000fe80008000804 */
/*0500*/ STS [UR4+0xf8], RZ ; /* 0x0000f8ffff007988 */
/* 0x000fe80008000804 */
/*0510*/ STS [UR4+0xfc], RZ ; /* 0x0000fcffff007988 */
/* 0x000fe80008000804 */
/*0520*/ STS [UR4+0x100], RZ ; /* 0x000100ffff007988 */
/* 0x000fe80008000804 */
/*0530*/ STS [UR4+0x104], RZ ; /* 0x000104ffff007988 */
/* 0x000fe80008000804 */
/*0540*/ STS [UR4+0x108], RZ ; /* 0x000108ffff007988 */
/* 0x000fe80008000804 */
/*0550*/ STS [UR4+0x10c], RZ ; /* 0x00010cffff007988 */
/* 0x000fe80008000804 */
/*0560*/ STS [UR4+0x110], RZ ; /* 0x000110ffff007988 */
/* 0x000fe80008000804 */
/*0570*/ STS [UR4+0x114], RZ ; /* 0x000114ffff007988 */
/* 0x000fe80008000804 */
/*0580*/ STS [UR4+0x118], RZ ; /* 0x000118ffff007988 */
/* 0x000fe80008000804 */
/*0590*/ STS [UR4+0x11c], RZ ; /* 0x00011cffff007988 */
/* 0x000fe80008000804 */
/*05a0*/ STS [UR4+0x120], RZ ; /* 0x000120ffff007988 */
/* 0x000fe80008000804 */
/*05b0*/ STS [UR4+0x124], RZ ; /* 0x000124ffff007988 */
/* 0x000fe80008000804 */
/*05c0*/ STS [UR4+0x128], RZ ; /* 0x000128ffff007988 */
/* 0x000fe80008000804 */
/*05d0*/ STS [UR4+0x12c], RZ ; /* 0x00012cffff007988 */
/* 0x000fe80008000804 */
/*05e0*/ STS [UR4+0x130], RZ ; /* 0x000130ffff007988 */
/* 0x000fe80008000804 */
/*05f0*/ STS [UR4+0x134], RZ ; /* 0x000134ffff007988 */
/* 0x000fe80008000804 */
/*0600*/ STS [UR4+0x138], RZ ; /* 0x000138ffff007988 */
/* 0x000fe80008000804 */
/*0610*/ STS [UR4+0x13c], RZ ; /* 0x00013cffff007988 */
/* 0x000fe80008000804 */
/*0620*/ STS [UR4+0x140], RZ ; /* 0x000140ffff007988 */
/* 0x000fe80008000804 */
/*0630*/ STS [UR4+0x144], RZ ; /* 0x000144ffff007988 */
/* 0x000fe80008000804 */
/*0640*/ STS [UR4+0x148], RZ ; /* 0x000148ffff007988 */
/* 0x000fe80008000804 */
/*0650*/ STS [UR4+0x14c], RZ ; /* 0x00014cffff007988 */
/* 0x000fe80008000804 */
/*0660*/ STS [UR4+0x150], RZ ; /* 0x000150ffff007988 */
/* 0x000fe80008000804 */
/*0670*/ STS [UR4+0x154], RZ ; /* 0x000154ffff007988 */
/* 0x000fe80008000804 */
/*0680*/ STS [UR4+0x158], RZ ; /* 0x000158ffff007988 */
/* 0x000fe80008000804 */
/*0690*/ STS [UR4+0x15c], RZ ; /* 0x00015cffff007988 */
/* 0x000fe80008000804 */
/*06a0*/ STS [UR4+0x160], RZ ; /* 0x000160ffff007988 */
/* 0x000fe80008000804 */
/*06b0*/ STS [UR4+0x164], RZ ; /* 0x000164ffff007988 */
/* 0x000fe80008000804 */
/*06c0*/ STS [UR4+0x168], RZ ; /* 0x000168ffff007988 */
/* 0x000fe80008000804 */
/*06d0*/ STS [UR4+0x16c], RZ ; /* 0x00016cffff007988 */
/* 0x000fe80008000804 */
/*06e0*/ STS [UR4+0x170], RZ ; /* 0x000170ffff007988 */
/* 0x000fe80008000804 */
/*06f0*/ STS [UR4+0x174], RZ ; /* 0x000174ffff007988 */
/* 0x000fe80008000804 */
/*0700*/ STS [UR4+0x178], RZ ; /* 0x000178ffff007988 */
/* 0x000fe80008000804 */
/*0710*/ STS [UR4+0x17c], RZ ; /* 0x00017cffff007988 */
/* 0x000fe80008000804 */
/*0720*/ STS [UR4+0x180], RZ ; /* 0x000180ffff007988 */
/* 0x000fe80008000804 */
/*0730*/ STS [UR4+0x184], RZ ; /* 0x000184ffff007988 */
/* 0x000fe80008000804 */
/*0740*/ STS [UR4+0x188], RZ ; /* 0x000188ffff007988 */
/* 0x000fe80008000804 */
/*0750*/ STS [UR4+0x18c], RZ ; /* 0x00018cffff007988 */
/* 0x000fe80008000804 */
/*0760*/ STS [UR4+0x190], RZ ; /* 0x000190ffff007988 */
/* 0x000fe80008000804 */
/*0770*/ STS [UR4+0x194], RZ ; /* 0x000194ffff007988 */
/* 0x000fe80008000804 */
/*0780*/ STS [UR4+0x198], RZ ; /* 0x000198ffff007988 */
/* 0x000fe80008000804 */
/*0790*/ STS [UR4+0x19c], RZ ; /* 0x00019cffff007988 */
/* 0x000fe80008000804 */
/*07a0*/ STS [UR4+0x1a0], RZ ; /* 0x0001a0ffff007988 */
/* 0x000fe80008000804 */
/*07b0*/ STS [UR4+0x1a4], RZ ; /* 0x0001a4ffff007988 */
/* 0x000fe80008000804 */
/*07c0*/ STS [UR4+0x1a8], RZ ; /* 0x0001a8ffff007988 */
/* 0x000fe80008000804 */
/*07d0*/ STS [UR4+0x1ac], RZ ; /* 0x0001acffff007988 */
/* 0x000fe80008000804 */
/*07e0*/ STS [UR4+0x1b0], RZ ; /* 0x0001b0ffff007988 */
/* 0x000fe80008000804 */
/*07f0*/ STS [UR4+0x1b4], RZ ; /* 0x0001b4ffff007988 */
/* 0x000fe80008000804 */
/*0800*/ STS [UR4+0x1b8], RZ ; /* 0x0001b8ffff007988 */
/* 0x000fe80008000804 */
/*0810*/ STS [UR4+0x1bc], RZ ; /* 0x0001bcffff007988 */
/* 0x000fe80008000804 */
/*0820*/ STS [UR4+0x1c0], RZ ; /* 0x0001c0ffff007988 */
/* 0x000fe80008000804 */
/*0830*/ STS [UR4+0x1c4], RZ ; /* 0x0001c4ffff007988 */
/* 0x000fe80008000804 */
/*0840*/ STS [UR4+0x1c8], RZ ; /* 0x0001c8ffff007988 */
/* 0x000fe80008000804 */
/*0850*/ STS [UR4+0x1cc], RZ ; /* 0x0001ccffff007988 */
/* 0x000fe80008000804 */
/*0860*/ STS [UR4+0x1d0], RZ ; /* 0x0001d0ffff007988 */
/* 0x000fe80008000804 */
/*0870*/ STS [UR4+0x1d4], RZ ; /* 0x0001d4ffff007988 */
/* 0x000fe80008000804 */
/*0880*/ STS [UR4+0x1d8], RZ ; /* 0x0001d8ffff007988 */
/* 0x000fe80008000804 */
/*0890*/ STS [UR4+0x1dc], RZ ; /* 0x0001dcffff007988 */
/* 0x000fe80008000804 */
/*08a0*/ STS [UR4+0x1e0], RZ ; /* 0x0001e0ffff007988 */
/* 0x000fe80008000804 */
/*08b0*/ STS [UR4+0x1e4], RZ ; /* 0x0001e4ffff007988 */
/* 0x000fe80008000804 */
/*08c0*/ STS [UR4+0x1e8], RZ ; /* 0x0001e8ffff007988 */
/* 0x000fe80008000804 */
/*08d0*/ STS [UR4+0x1ec], RZ ; /* 0x0001ecffff007988 */
/* 0x000fe80008000804 */
/*08e0*/ STS [UR4+0x1f0], RZ ; /* 0x0001f0ffff007988 */
/* 0x000fe80008000804 */
/*08f0*/ STS [UR4+0x1f4], RZ ; /* 0x0001f4ffff007988 */
/* 0x000fe80008000804 */
/*0900*/ STS [UR4+0x1f8], RZ ; /* 0x0001f8ffff007988 */
/* 0x000fe80008000804 */
/*0910*/ STS [UR4+0x1fc], RZ ; /* 0x0001fcffff007988 */
/* 0x000fe80008000804 */
/*0920*/ STS [UR4+0x200], RZ ; /* 0x000200ffff007988 */
/* 0x000fe80008000804 */
/*0930*/ STS [UR4+0x204], RZ ; /* 0x000204ffff007988 */
/* 0x000fe80008000804 */
/*0940*/ STS [UR4+0x208], RZ ; /* 0x000208ffff007988 */
/* 0x000fe80008000804 */
/*0950*/ STS [UR4+0x20c], RZ ; /* 0x00020cffff007988 */
/* 0x000fe80008000804 */
/*0960*/ STS [UR4+0x210], RZ ; /* 0x000210ffff007988 */
/* 0x000fe80008000804 */
/*0970*/ STS [UR4+0x214], RZ ; /* 0x000214ffff007988 */
/* 0x000fe80008000804 */
/*0980*/ STS [UR4+0x218], RZ ; /* 0x000218ffff007988 */
/* 0x000fe80008000804 */
/*0990*/ STS [UR4+0x21c], RZ ; /* 0x00021cffff007988 */
/* 0x000fe80008000804 */
/*09a0*/ STS [UR4+0x220], RZ ; /* 0x000220ffff007988 */
/* 0x000fe80008000804 */
/*09b0*/ STS [UR4+0x224], RZ ; /* 0x000224ffff007988 */
/* 0x000fe80008000804 */
/*09c0*/ STS [UR4+0x228], RZ ; /* 0x000228ffff007988 */
/* 0x000fe80008000804 */
/*09d0*/ STS [UR4+0x22c], RZ ; /* 0x00022cffff007988 */
/* 0x000fe80008000804 */
/*09e0*/ STS [UR4+0x230], RZ ; /* 0x000230ffff007988 */
/* 0x000fe80008000804 */
/*09f0*/ STS [UR4+0x234], RZ ; /* 0x000234ffff007988 */
/* 0x000fe80008000804 */
/*0a00*/ STS [UR4+0x238], RZ ; /* 0x000238ffff007988 */
/* 0x000fe80008000804 */
/*0a10*/ STS [UR4+0x23c], RZ ; /* 0x00023cffff007988 */
/* 0x000fe80008000804 */
/*0a20*/ STS [UR4+0x240], RZ ; /* 0x000240ffff007988 */
/* 0x000fe80008000804 */
/*0a30*/ STS [UR4+0x244], RZ ; /* 0x000244ffff007988 */
/* 0x000fe80008000804 */
/*0a40*/ STS [UR4+0x248], RZ ; /* 0x000248ffff007988 */
/* 0x000fe80008000804 */
/*0a50*/ STS [UR4+0x24c], RZ ; /* 0x00024cffff007988 */
/* 0x000fe80008000804 */
/*0a60*/ STS [UR4+0x250], RZ ; /* 0x000250ffff007988 */
/* 0x000fe80008000804 */
/*0a70*/ STS [UR4+0x254], RZ ; /* 0x000254ffff007988 */
/* 0x000fe80008000804 */
/*0a80*/ STS [UR4+0x258], RZ ; /* 0x000258ffff007988 */
/* 0x000fe80008000804 */
/*0a90*/ STS [UR4+0x25c], RZ ; /* 0x00025cffff007988 */
/* 0x000fe80008000804 */
/*0aa0*/ STS [UR4+0x260], RZ ; /* 0x000260ffff007988 */
/* 0x000fe80008000804 */
/*0ab0*/ STS [UR4+0x264], RZ ; /* 0x000264ffff007988 */
/* 0x000fe80008000804 */
/*0ac0*/ STS [UR4+0x268], RZ ; /* 0x000268ffff007988 */
/* 0x000fe80008000804 */
/*0ad0*/ STS [UR4+0x26c], RZ ; /* 0x00026cffff007988 */
/* 0x000fe80008000804 */
/*0ae0*/ STS [UR4+0x270], RZ ; /* 0x000270ffff007988 */
/* 0x000fe80008000804 */
/*0af0*/ STS [UR4+0x274], RZ ; /* 0x000274ffff007988 */
/* 0x000fe80008000804 */
/*0b00*/ STS [UR4+0x278], RZ ; /* 0x000278ffff007988 */
/* 0x000fe80008000804 */
/*0b10*/ STS [UR4+0x27c], RZ ; /* 0x00027cffff007988 */
/* 0x000fe80008000804 */
/*0b20*/ STS [UR4+0x280], RZ ; /* 0x000280ffff007988 */
/* 0x000fe20008000804 */
/*0b30*/ UIADD3 UR4, UR4, 0x284, URZ ; /* 0x0000028404047890 */
/* 0x000fe2000fffe03f */
/*0b40*/ @!P0 BRA 0x100 ; /* 0xfffff5b000008947 */
/* 0x000fee000383ffff */
/*0b50*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b60*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0b70*/ BSSY B0, 0xbe0 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0b80*/ @P1 BRA 0xbd0 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*0b90*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0ba0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0203 */
/*0bb0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*0bc0*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ+-0x4] ; /* 0xfffffc0002ff7f8c */
/* 0x0041e4000d00403f */
/*0bd0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0be0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0bf0*/ @P2 EXIT ; /* 0x000000000000294d */
/* 0x000fea0003800000 */
/*0c00*/ MOV R20, c[0x0][0x160] ; /* 0x0000580000147a02 */
/* 0x000fe20000000f00 */
/*0c10*/ IMAD.MOV.U32 R21, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff157624 */
/* 0x000fe200078e00ff */
/*0c20*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0c30*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fc400078e00ff */
/*0c40*/ LDS.128 R4, [UR4] ; /* 0x00000004ff047984 */
/* 0x002e620008000c00 */
/*0c50*/ MOV R2, R20 ; /* 0x0000001400027202 */
/* 0x001fe20000000f00 */
/*0c60*/ IMAD.MOV.U32 R3, RZ, RZ, R21 ; /* 0x000000ffff037224 */
/* 0x000fc400078e0015 */
/*0c70*/ LDS.128 R8, [UR4+0x10] ; /* 0x00001004ff087984 */
/* 0x000e280008000c00 */
/*0c80*/ LDS.128 R12, [UR4+0x20] ; /* 0x00002004ff0c7984 */
/* 0x000ea80008000c00 */
/*0c90*/ LDS.128 R16, [UR4+0x30] ; /* 0x00003004ff107984 */
/* 0x000ee20008000c00 */
/*0ca0*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x000fc80007ffe0ff */
/*0cb0*/ ISETP.NE.AND P0, PT, R0, 0x2710, PT ; /* 0x000027100000780c */
/* 0x000fe20003f05270 */
/*0cc0*/ UIADD3 UR4, UR4, 0x40, URZ ; /* 0x0000004004047890 */
/* 0x000fe2000fffe03f */
/*0cd0*/ IADD3 R20, P1, R2, 0x40, RZ ; /* 0x0000004002147810 */
/* 0x000fe20007f3e0ff */
/*0ce0*/ RED.E.ADD.STRONG.GPU [R2.64], R4 ; /* 0x000000040200798e */
/* 0x0023e8000c10e186 */
/*0cf0*/ RED.E.ADD.STRONG.GPU [R2.64+0x4], R5 ; /* 0x000004050200798e */
/* 0x0003e8000c10e186 */
/*0d00*/ RED.E.ADD.STRONG.GPU [R2.64+0x8], R6 ; /* 0x000008060200798e */
/* 0x0003e8000c10e186 */
/*0d10*/ RED.E.ADD.STRONG.GPU [R2.64+0xc], R7 ; /* 0x00000c070200798e */
/* 0x0003e8000c10e186 */
/*0d20*/ RED.E.ADD.STRONG.GPU [R2.64+0x10], R8 ; /* 0x000010080200798e */
/* 0x0013e8000c10e186 */
/*0d30*/ RED.E.ADD.STRONG.GPU [R2.64+0x14], R9 ; /* 0x000014090200798e */
/* 0x0003e8000c10e186 */
/*0d40*/ RED.E.ADD.STRONG.GPU [R2.64+0x18], R10 ; /* 0x0000180a0200798e */
/* 0x0003e8000c10e186 */
/*0d50*/ RED.E.ADD.STRONG.GPU [R2.64+0x1c], R11 ; /* 0x00001c0b0200798e */
/* 0x0003e8000c10e186 */
/*0d60*/ RED.E.ADD.STRONG.GPU [R2.64+0x20], R12 ; /* 0x0000200c0200798e */
/* 0x0043e8000c10e186 */
/*0d70*/ RED.E.ADD.STRONG.GPU [R2.64+0x24], R13 ; /* 0x0000240d0200798e */
/* 0x0003e8000c10e186 */
/*0d80*/ RED.E.ADD.STRONG.GPU [R2.64+0x28], R14 ; /* 0x0000280e0200798e */
/* 0x0003e8000c10e186 */
/*0d90*/ RED.E.ADD.STRONG.GPU [R2.64+0x2c], R15 ; /* 0x00002c0f0200798e */
/* 0x0003e8000c10e186 */
/*0da0*/ RED.E.ADD.STRONG.GPU [R2.64+0x30], R16 ; /* 0x000030100200798e */
/* 0x0083e8000c10e186 */
/*0db0*/ RED.E.ADD.STRONG.GPU [R2.64+0x34], R17 ; /* 0x000034110200798e */
/* 0x0003e8000c10e186 */
/*0dc0*/ RED.E.ADD.STRONG.GPU [R2.64+0x38], R18 ; /* 0x000038120200798e */
/* 0x0003e2000c10e186 */
/*0dd0*/ IADD3.X R21, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff157210 */
/* 0x000fc60000ffe4ff */
/*0de0*/ RED.E.ADD.STRONG.GPU [R2.64+0x3c], R19 ; /* 0x00003c130200798e */
/* 0x0003e2000c10e186 */
/*0df0*/ @P0 BRA 0xc40 ; /* 0xfffffe4000000947 */
/* 0x000fea000383ffff */
/*0e00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e10*/ BRA 0xe10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13gpu_countsortPiS_
.globl _Z13gpu_countsortPiS_
.p2align 8
.type _Z13gpu_countsortPiS_,@function
_Z13gpu_countsortPiS_:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s5, 0
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v1, 0
s_mov_b32 s2, 0xffff63c0
s_mov_b32 s3, -1
.LBB0_2:
v_mov_b32_e32 v2, s5
s_add_i32 s5, s5, 4
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
ds_store_b8 v2, v1
ds_store_b8 v2, v1 offset:1
ds_store_b8 v2, v1 offset:2
ds_store_b8 v2, v1 offset:3
s_cmp_lg_u64 s[2:3], 0
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_load_b32 s2, s[0:1], 0x1c
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmpx_gt_i32_e32 0x989680, v1
s_cbranch_execz .LBB0_5
s_load_b64 s[4:5], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, s2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s2, s5, v1, s2
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 1
s_waitcnt vmcnt(0)
v_lshl_add_u32 v0, v0, 2, -4
ds_add_u32 v0, v1
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_10
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b32 s2, 0
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s2, s2, 4
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmpk_lg_u32 s2, 0x9c40
s_cbranch_scc0 .LBB0_10
.LBB0_8:
s_mov_b32 s4, exec_lo
s_mov_b32 s3, exec_lo
v_mbcnt_lo_u32_b32 v1, s4, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v1, s2
s_bcnt1_i32_b32 s4, s4
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, v1, s4
global_atomic_add_u32 v0, v1, s[0:1]
s_branch .LBB0_7
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13gpu_countsortPiS_
.amdhsa_group_segment_fixed_size 40000
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13gpu_countsortPiS_, .Lfunc_end0-_Z13gpu_countsortPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 40000
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13gpu_countsortPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13gpu_countsortPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013ca3a_00000000-6_countsort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7genListPPi
.type _Z7genListPPi, @function
_Z7genListPPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
movl $40000000, %edi
call malloc@PLT
movq %rax, 0(%rbp)
movl $0, %ebx
.L4:
call rand@PLT
movq 0(%rbp), %rcx
movslq %eax, %rdx
imulq $1759218605, %rdx, %rdx
sarq $44, %rdx
movl %eax, %esi
sarl $31, %esi
subl %esi, %edx
imull $10000, %edx, %edx
subl %edx, %eax
addl $1, %eax
movl %eax, (%rcx,%rbx)
addq $4, %rbx
cmpq $40000000, %rbx
jne .L4
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z7genListPPi, .-_Z7genListPPi
.globl _Z35__device_stub__Z13gpu_countsortPiS_PiS_
.type _Z35__device_stub__Z13gpu_countsortPiS_PiS_, @function
_Z35__device_stub__Z13gpu_countsortPiS_PiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13gpu_countsortPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z35__device_stub__Z13gpu_countsortPiS_PiS_, .-_Z35__device_stub__Z13gpu_countsortPiS_PiS_
.globl _Z13gpu_countsortPiS_
.type _Z13gpu_countsortPiS_, @function
_Z13gpu_countsortPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13gpu_countsortPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13gpu_countsortPiS_, .-_Z13gpu_countsortPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "time in gpu: %31.f ms\n"
.LC1:
.string "time in cpu: %31.f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call _Z7genListPPi
leaq 32(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
movq 24(%rsp), %r12
movl $1, %ecx
movl $40000000, %edx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 40(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl $40000, %edx
movl $0, %esi
movq 40(%rsp), %rdi
call cudaMemset@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $9766, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L16:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
call cudaDeviceSynchronize@PLT
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $40000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $40000000, %edx
movl $0, %esi
movq %rax, %rdi
call memset@PLT
movl $40000, %edi
call malloc@PLT
movq %rax, %rbp
movl $2, %ecx
movl $40000, %edx
movq 40(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movl $1, %edx
movl $0, %edi
jmp .L17
.L25:
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z35__device_stub__Z13gpu_countsortPiS_PiS_
jmp .L16
.L20:
movslq %edi, %r8
leaq (%rbx,%r8,4), %rax
movslq %esi, %rcx
addq %r8, %rcx
leaq (%rbx,%rcx,4), %rcx
.L18:
movl %edx, (%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L18
addl %esi, %edi
.L21:
addq $1, %rdx
cmpq $10001, %rdx
je .L19
.L17:
movl -4(%rbp,%rdx,4), %esi
testl %esi, %esi
jg .L20
jmp .L21
.L19:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z13gpu_countsortPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13gpu_countsortPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "countsort.hip"
.globl _Z28__device_stub__gpu_countsortPiS_ # -- Begin function _Z28__device_stub__gpu_countsortPiS_
.p2align 4, 0x90
.type _Z28__device_stub__gpu_countsortPiS_,@function
_Z28__device_stub__gpu_countsortPiS_: # @_Z28__device_stub__gpu_countsortPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13gpu_countsortPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__gpu_countsortPiS_, .Lfunc_end0-_Z28__device_stub__gpu_countsortPiS_
.cfi_endproc
# -- End function
.globl _Z7genListPPi # -- Begin function _Z7genListPPi
.p2align 4, 0x90
.type _Z7genListPPi,@function
_Z7genListPPi: # @_Z7genListPPi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, (%rbx)
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1759218605, %rax, %rcx # imm = 0x68DB8BAD
movq %rcx, %rdx
shrq $63, %rdx
sarq $44, %rcx
addl %edx, %ecx
imull $10000, %ecx, %ecx # imm = 0x2710
negl %ecx
addl %ecx, %eax
incl %eax
movq (%rbx), %rcx
movl %eax, (%rcx,%r14,4)
incq %r14
cmpq $10000000, %r14 # imm = 0x989680
jne .LBB1_1
# %bb.2:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z7genListPPi, .Lfunc_end1-_Z7genListPPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1759218605, %rax, %rcx # imm = 0x68DB8BAD
movq %rcx, %rdx
shrq $63, %rdx
sarq $44, %rcx
addl %edx, %ecx
imull $10000, %ecx, %ecx # imm = 0x2710
negl %ecx
addl %ecx, %eax
incl %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $10000000, %r14 # imm = 0x989680
jne .LBB2_1
# %bb.2: # %_Z7genListPPi.exit
leaq 16(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
movq 16(%rsp), %rdi
movl $40000000, %edx # imm = 0x2625A00
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movq 8(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
xorl %esi, %esi
callq hipMemset
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 8742(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 32(%rsp)
leaq 96(%rsp), %rax
movq %rax, 40(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z13gpu_countsortPiS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq (%rsp), %rdx
leaq 32(%rsp), %r15
movq %r15, %rdi
callq hipEventElapsedTime
callq hipDeviceSynchronize
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r14
movq 8(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq (%rsp), %rdx
movq %r15, %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13gpu_countsortPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13gpu_countsortPiS_,@object # @_Z13gpu_countsortPiS_
.section .rodata,"a",@progbits
.globl _Z13gpu_countsortPiS_
.p2align 3, 0x0
_Z13gpu_countsortPiS_:
.quad _Z28__device_stub__gpu_countsortPiS_
.size _Z13gpu_countsortPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "time in gpu: %31.f ms\n"
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "time in cpu: %31.f ms\n"
.size .L.str.1, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13gpu_countsortPiS_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__gpu_countsortPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13gpu_countsortPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
extern "C"
// CUDA allocating function, with naive error handling
double* cuda_allocate(const size_t size) {
double *dev_matrix;
if (cudaMalloc((void**)&dev_matrix, size) != cudaSuccess) {
printf("Error allocating\n");
return 0;
}
else {
return dev_matrix;
}
}
// cuda copy with naive error handling (0 = host to device, 1 = device to host)
void cuda_copy(double* dest, double* src, const size_t size, const size_t dir) {
// copy inputs to/from device (0 is from device to host)
if (dir == 0) {
if (cudaMemcpy(dest, src, size, cudaMemcpyHostToDevice) != cudaSuccess) {
printf("NOCOPY!\n\n");
}
}
else{
if (cudaMemcpy(dest, src, size, cudaMemcpyDeviceToHost) != cudaSuccess) {
printf("NOCOPY!\n\n");
}
}
}
// CUDA free with naive error handling
void cuda_free(double* matrix){
if (cudaFree(matrix) != cudaSuccess) {
printf("NOFREE!\n\n");
}
}
// populate function
void populate(double* matrix_in, const size_t size){
for (size_t i = 0; i < size*size; i++) {
matrix_in[i] = i;
}
}
void print_matrix(const double* matrix_in, const size_t n) {
for (size_t i = 0; i < n; i++) {
for (size_t j = 0; j < n; j++) {
printf("%0.f ", matrix_in[i*n+j]);
}
printf("\n");
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
extern "C"
// CUDA allocating function, with naive error handling
double* cuda_allocate(const size_t size) {
double *dev_matrix;
if (cudaMalloc((void**)&dev_matrix, size) != cudaSuccess) {
printf("Error allocating\n");
return 0;
}
else {
return dev_matrix;
}
}
// cuda copy with naive error handling (0 = host to device, 1 = device to host)
void cuda_copy(double* dest, double* src, const size_t size, const size_t dir) {
// copy inputs to/from device (0 is from device to host)
if (dir == 0) {
if (cudaMemcpy(dest, src, size, cudaMemcpyHostToDevice) != cudaSuccess) {
printf("NOCOPY!\n\n");
}
}
else{
if (cudaMemcpy(dest, src, size, cudaMemcpyDeviceToHost) != cudaSuccess) {
printf("NOCOPY!\n\n");
}
}
}
// CUDA free with naive error handling
void cuda_free(double* matrix){
if (cudaFree(matrix) != cudaSuccess) {
printf("NOFREE!\n\n");
}
}
// populate function
void populate(double* matrix_in, const size_t size){
for (size_t i = 0; i < size*size; i++) {
matrix_in[i] = i;
}
}
void print_matrix(const double* matrix_in, const size_t n) {
for (size_t i = 0; i < n; i++) {
for (size_t j = 0; j < n; j++) {
printf("%0.f ", matrix_in[i*n+j]);
}
printf("\n");
}
} | .file "tmpxft_000fa927_00000000-6_utils.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error allocating\n"
.text
.globl cuda_allocate
.type cuda_allocate, @function
cuda_allocate:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rsi
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call cudaMalloc@PLT
movl %eax, %edx
movq (%rsp), %rax
testl %edx, %edx
jne .L8
.L3:
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L9
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L3
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size cuda_allocate, .-cuda_allocate
.section .rodata.str1.1
.LC1:
.string "NOCOPY!\n\n"
.text
.globl _Z9cuda_copyPdS_mm
.type _Z9cuda_copyPdS_mm, @function
_Z9cuda_copyPdS_mm:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
testq %rcx, %rcx
jne .L11
movl $1, %ecx
call cudaMemcpy@PLT
testl %eax, %eax
jne .L14
.L10:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L10
.L11:
movl $2, %ecx
call cudaMemcpy@PLT
testl %eax, %eax
je .L10
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L10
.cfi_endproc
.LFE2058:
.size _Z9cuda_copyPdS_mm, .-_Z9cuda_copyPdS_mm
.section .rodata.str1.1
.LC2:
.string "NOFREE!\n\n"
.text
.globl _Z9cuda_freePd
.type _Z9cuda_freePd, @function
_Z9cuda_freePd:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaFree@PLT
testl %eax, %eax
jne .L18
.L15:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L15
.cfi_endproc
.LFE2059:
.size _Z9cuda_freePd, .-_Z9cuda_freePd
.globl _Z8populatePdm
.type _Z8populatePdm, @function
_Z8populatePdm:
.LFB2060:
.cfi_startproc
endbr64
imulq %rsi, %rsi
testq %rsi, %rsi
je .L19
movl $0, %eax
jmp .L23
.L21:
movq %rax, %rdx
shrq %rdx
movq %rax, %rcx
andl $1, %ecx
orq %rcx, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
.L22:
movsd %xmm0, (%rdi,%rax,8)
addq $1, %rax
cmpq %rax, %rsi
je .L19
.L23:
testq %rax, %rax
js .L21
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
jmp .L22
.L19:
ret
.cfi_endproc
.LFE2060:
.size _Z8populatePdm, .-_Z8populatePdm
.section .rodata.str1.1
.LC3:
.string "%0.f "
.LC4:
.string "\n"
.text
.globl _Z12print_matrixPKdm
.type _Z12print_matrixPKdm, @function
_Z12print_matrixPKdm:
.LFB2061:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L31
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %r13
leaq 0(,%rsi,8), %rax
movq %rax, 8(%rsp)
movq %rdi, %rbp
movl $0, %r15d
leaq .LC3(%rip), %r14
.L27:
movl $0, %ebx
.L28:
movsd 0(%rbp,%rbx,8), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %r12
addq $1, %rbx
cmpq %rbx, %r13
jne .L28
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 1(%r15), %rax
movq 8(%rsp), %rdx
addq %rdx, %rbp
cmpq %r12, %r15
je .L25
movq %rax, %r15
jmp .L27
.L25:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2061:
.size _Z12print_matrixPKdm, .-_Z12print_matrixPKdm
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
extern "C"
// CUDA allocating function, with naive error handling
double* cuda_allocate(const size_t size) {
double *dev_matrix;
if (cudaMalloc((void**)&dev_matrix, size) != cudaSuccess) {
printf("Error allocating\n");
return 0;
}
else {
return dev_matrix;
}
}
// cuda copy with naive error handling (0 = host to device, 1 = device to host)
void cuda_copy(double* dest, double* src, const size_t size, const size_t dir) {
// copy inputs to/from device (0 is from device to host)
if (dir == 0) {
if (cudaMemcpy(dest, src, size, cudaMemcpyHostToDevice) != cudaSuccess) {
printf("NOCOPY!\n\n");
}
}
else{
if (cudaMemcpy(dest, src, size, cudaMemcpyDeviceToHost) != cudaSuccess) {
printf("NOCOPY!\n\n");
}
}
}
// CUDA free with naive error handling
void cuda_free(double* matrix){
if (cudaFree(matrix) != cudaSuccess) {
printf("NOFREE!\n\n");
}
}
// populate function
void populate(double* matrix_in, const size_t size){
for (size_t i = 0; i < size*size; i++) {
matrix_in[i] = i;
}
}
void print_matrix(const double* matrix_in, const size_t n) {
for (size_t i = 0; i < n; i++) {
for (size_t j = 0; j < n; j++) {
printf("%0.f ", matrix_in[i*n+j]);
}
printf("\n");
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
extern "C"
// CUDA allocating function, with naive error handling
double* cuda_allocate(const size_t size) {
double *dev_matrix;
if (hipMalloc((void**)&dev_matrix, size) != hipSuccess) {
printf("Error allocating\n");
return 0;
}
else {
return dev_matrix;
}
}
// cuda copy with naive error handling (0 = host to device, 1 = device to host)
void cuda_copy(double* dest, double* src, const size_t size, const size_t dir) {
// copy inputs to/from device (0 is from device to host)
if (dir == 0) {
if (hipMemcpy(dest, src, size, hipMemcpyHostToDevice) != hipSuccess) {
printf("NOCOPY!\n\n");
}
}
else{
if (hipMemcpy(dest, src, size, hipMemcpyDeviceToHost) != hipSuccess) {
printf("NOCOPY!\n\n");
}
}
}
// CUDA free with naive error handling
void cuda_free(double* matrix){
if (hipFree(matrix) != hipSuccess) {
printf("NOFREE!\n\n");
}
}
// populate function
void populate(double* matrix_in, const size_t size){
for (size_t i = 0; i < size*size; i++) {
matrix_in[i] = i;
}
}
void print_matrix(const double* matrix_in, const size_t n) {
for (size_t i = 0; i < n; i++) {
for (size_t j = 0; j < n; j++) {
printf("%0.f ", matrix_in[i*n+j]);
}
printf("\n");
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
extern "C"
// CUDA allocating function, with naive error handling
double* cuda_allocate(const size_t size) {
double *dev_matrix;
if (hipMalloc((void**)&dev_matrix, size) != hipSuccess) {
printf("Error allocating\n");
return 0;
}
else {
return dev_matrix;
}
}
// cuda copy with naive error handling (0 = host to device, 1 = device to host)
void cuda_copy(double* dest, double* src, const size_t size, const size_t dir) {
// copy inputs to/from device (0 is from device to host)
if (dir == 0) {
if (hipMemcpy(dest, src, size, hipMemcpyHostToDevice) != hipSuccess) {
printf("NOCOPY!\n\n");
}
}
else{
if (hipMemcpy(dest, src, size, hipMemcpyDeviceToHost) != hipSuccess) {
printf("NOCOPY!\n\n");
}
}
}
// CUDA free with naive error handling
void cuda_free(double* matrix){
if (hipFree(matrix) != hipSuccess) {
printf("NOFREE!\n\n");
}
}
// populate function
void populate(double* matrix_in, const size_t size){
for (size_t i = 0; i < size*size; i++) {
matrix_in[i] = i;
}
}
void print_matrix(const double* matrix_in, const size_t n) {
for (size_t i = 0; i < n; i++) {
for (size_t j = 0; j < n; j++) {
printf("%0.f ", matrix_in[i*n+j]);
}
printf("\n");
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
extern "C"
// CUDA allocating function, with naive error handling
double* cuda_allocate(const size_t size) {
double *dev_matrix;
if (hipMalloc((void**)&dev_matrix, size) != hipSuccess) {
printf("Error allocating\n");
return 0;
}
else {
return dev_matrix;
}
}
// cuda copy with naive error handling (0 = host to device, 1 = device to host)
void cuda_copy(double* dest, double* src, const size_t size, const size_t dir) {
// copy inputs to/from device (0 is from device to host)
if (dir == 0) {
if (hipMemcpy(dest, src, size, hipMemcpyHostToDevice) != hipSuccess) {
printf("NOCOPY!\n\n");
}
}
else{
if (hipMemcpy(dest, src, size, hipMemcpyDeviceToHost) != hipSuccess) {
printf("NOCOPY!\n\n");
}
}
}
// CUDA free with naive error handling
void cuda_free(double* matrix){
if (hipFree(matrix) != hipSuccess) {
printf("NOFREE!\n\n");
}
}
// populate function
void populate(double* matrix_in, const size_t size){
for (size_t i = 0; i < size*size; i++) {
matrix_in[i] = i;
}
}
void print_matrix(const double* matrix_in, const size_t n) {
for (size_t i = 0; i < n; i++) {
for (size_t j = 0; j < n; j++) {
printf("%0.f ", matrix_in[i*n+j]);
}
printf("\n");
}
} | .text
.file "utils.hip"
.globl cuda_allocate # -- Begin function cuda_allocate
.p2align 4, 0x90
.type cuda_allocate,@function
cuda_allocate: # @cuda_allocate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rdi, %rsi
movq %rsp, %rdi
callq hipMalloc
testl %eax, %eax
je .LBB0_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 16
movq (%rsp), %rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size cuda_allocate, .Lfunc_end0-cuda_allocate
.cfi_endproc
# -- End function
.globl _Z9cuda_copyPdS_mm # -- Begin function _Z9cuda_copyPdS_mm
.p2align 4, 0x90
.type _Z9cuda_copyPdS_mm,@function
_Z9cuda_copyPdS_mm: # @_Z9cuda_copyPdS_mm
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
testq %rcx, %rcx
je .LBB1_1
# %bb.2:
movl $2, %ecx
jmp .LBB1_3
.LBB1_1:
movl $1, %ecx
.LBB1_3:
callq hipMemcpy
testl %eax, %eax
je .LBB1_4
# %bb.5: # %.sink.split
movl $.Lstr.2, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB1_4:
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9cuda_copyPdS_mm, .Lfunc_end1-_Z9cuda_copyPdS_mm
.cfi_endproc
# -- End function
.globl _Z9cuda_freePd # -- Begin function _Z9cuda_freePd
.p2align 4, 0x90
.type _Z9cuda_freePd,@function
_Z9cuda_freePd: # @_Z9cuda_freePd
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq hipFree
testl %eax, %eax
je .LBB2_1
# %bb.2:
movl $.Lstr.3, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB2_1:
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9cuda_freePd, .Lfunc_end2-_Z9cuda_freePd
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z8populatePdm
.LCPI3_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI3_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.text
.globl _Z8populatePdm
.p2align 4, 0x90
.type _Z8populatePdm,@function
_Z8populatePdm: # @_Z8populatePdm
.cfi_startproc
# %bb.0:
imulq %rsi, %rsi
testq %rsi, %rsi
je .LBB3_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
movdqa .LCPI3_0(%rip), %xmm0 # xmm0 = [1127219200,1160773632,0,0]
movapd .LCPI3_1(%rip), %xmm1 # xmm1 = [4.503599627370496E+15,1.9342813113834067E+25]
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rax, %xmm2
punpckldq %xmm0, %xmm2 # xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
subpd %xmm1, %xmm2
movapd %xmm2, %xmm3
unpckhpd %xmm2, %xmm3 # xmm3 = xmm3[1],xmm2[1]
addsd %xmm2, %xmm3
movsd %xmm3, (%rdi,%rax,8)
incq %rax
cmpq %rax, %rsi
jne .LBB3_2
.LBB3_3: # %._crit_edge
retq
.Lfunc_end3:
.size _Z8populatePdm, .Lfunc_end3-_Z8populatePdm
.cfi_endproc
# -- End function
.globl _Z12print_matrixPKdm # -- Begin function _Z12print_matrixPKdm
.p2align 4, 0x90
.type _Z12print_matrixPKdm,@function
_Z12print_matrixPKdm: # @_Z12print_matrixPKdm
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB4_6
# %bb.1: # %.preheader.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
leaq (,%rsi,8), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r14,%r13,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r13
cmpq %r13, %rbx
jne .LBB4_3
# %bb.4: # in Loop: Header=BB4_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addq %r15, %r14
cmpq %rbx, %r12
jne .LBB4_2
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB4_6: # %._crit_edge
retq
.Lfunc_end4:
.size _Z12print_matrixPKdm, .Lfunc_end4-_Z12print_matrixPKdm
.cfi_endproc
# -- End function
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%0.f "
.size .L.str.3, 6
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error allocating"
.size .Lstr, 17
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "NOCOPY!\n"
.size .Lstr.2, 9
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "NOFREE!\n"
.size .Lstr.3, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fa927_00000000-6_utils.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error allocating\n"
.text
.globl cuda_allocate
.type cuda_allocate, @function
cuda_allocate:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rsi
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call cudaMalloc@PLT
movl %eax, %edx
movq (%rsp), %rax
testl %edx, %edx
jne .L8
.L3:
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L9
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L3
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size cuda_allocate, .-cuda_allocate
.section .rodata.str1.1
.LC1:
.string "NOCOPY!\n\n"
.text
.globl _Z9cuda_copyPdS_mm
.type _Z9cuda_copyPdS_mm, @function
_Z9cuda_copyPdS_mm:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
testq %rcx, %rcx
jne .L11
movl $1, %ecx
call cudaMemcpy@PLT
testl %eax, %eax
jne .L14
.L10:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L10
.L11:
movl $2, %ecx
call cudaMemcpy@PLT
testl %eax, %eax
je .L10
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L10
.cfi_endproc
.LFE2058:
.size _Z9cuda_copyPdS_mm, .-_Z9cuda_copyPdS_mm
.section .rodata.str1.1
.LC2:
.string "NOFREE!\n\n"
.text
.globl _Z9cuda_freePd
.type _Z9cuda_freePd, @function
_Z9cuda_freePd:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaFree@PLT
testl %eax, %eax
jne .L18
.L15:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L15
.cfi_endproc
.LFE2059:
.size _Z9cuda_freePd, .-_Z9cuda_freePd
.globl _Z8populatePdm
.type _Z8populatePdm, @function
_Z8populatePdm:
.LFB2060:
.cfi_startproc
endbr64
imulq %rsi, %rsi
testq %rsi, %rsi
je .L19
movl $0, %eax
jmp .L23
.L21:
movq %rax, %rdx
shrq %rdx
movq %rax, %rcx
andl $1, %ecx
orq %rcx, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
.L22:
movsd %xmm0, (%rdi,%rax,8)
addq $1, %rax
cmpq %rax, %rsi
je .L19
.L23:
testq %rax, %rax
js .L21
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
jmp .L22
.L19:
ret
.cfi_endproc
.LFE2060:
.size _Z8populatePdm, .-_Z8populatePdm
.section .rodata.str1.1
.LC3:
.string "%0.f "
.LC4:
.string "\n"
.text
.globl _Z12print_matrixPKdm
.type _Z12print_matrixPKdm, @function
_Z12print_matrixPKdm:
.LFB2061:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L31
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %r13
leaq 0(,%rsi,8), %rax
movq %rax, 8(%rsp)
movq %rdi, %rbp
movl $0, %r15d
leaq .LC3(%rip), %r14
.L27:
movl $0, %ebx
.L28:
movsd 0(%rbp,%rbx,8), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %r12
addq $1, %rbx
cmpq %rbx, %r13
jne .L28
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 1(%r15), %rax
movq 8(%rsp), %rdx
addq %rdx, %rbp
cmpq %r12, %r15
je .L25
movq %rax, %r15
jmp .L27
.L25:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2061:
.size _Z12print_matrixPKdm, .-_Z12print_matrixPKdm
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "utils.hip"
.globl cuda_allocate # -- Begin function cuda_allocate
.p2align 4, 0x90
.type cuda_allocate,@function
cuda_allocate: # @cuda_allocate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rdi, %rsi
movq %rsp, %rdi
callq hipMalloc
testl %eax, %eax
je .LBB0_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 16
movq (%rsp), %rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size cuda_allocate, .Lfunc_end0-cuda_allocate
.cfi_endproc
# -- End function
.globl _Z9cuda_copyPdS_mm # -- Begin function _Z9cuda_copyPdS_mm
.p2align 4, 0x90
.type _Z9cuda_copyPdS_mm,@function
_Z9cuda_copyPdS_mm: # @_Z9cuda_copyPdS_mm
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
testq %rcx, %rcx
je .LBB1_1
# %bb.2:
movl $2, %ecx
jmp .LBB1_3
.LBB1_1:
movl $1, %ecx
.LBB1_3:
callq hipMemcpy
testl %eax, %eax
je .LBB1_4
# %bb.5: # %.sink.split
movl $.Lstr.2, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB1_4:
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9cuda_copyPdS_mm, .Lfunc_end1-_Z9cuda_copyPdS_mm
.cfi_endproc
# -- End function
.globl _Z9cuda_freePd # -- Begin function _Z9cuda_freePd
.p2align 4, 0x90
.type _Z9cuda_freePd,@function
_Z9cuda_freePd: # @_Z9cuda_freePd
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq hipFree
testl %eax, %eax
je .LBB2_1
# %bb.2:
movl $.Lstr.3, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB2_1:
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9cuda_freePd, .Lfunc_end2-_Z9cuda_freePd
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z8populatePdm
.LCPI3_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI3_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.text
.globl _Z8populatePdm
.p2align 4, 0x90
.type _Z8populatePdm,@function
_Z8populatePdm: # @_Z8populatePdm
.cfi_startproc
# %bb.0:
imulq %rsi, %rsi
testq %rsi, %rsi
je .LBB3_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
movdqa .LCPI3_0(%rip), %xmm0 # xmm0 = [1127219200,1160773632,0,0]
movapd .LCPI3_1(%rip), %xmm1 # xmm1 = [4.503599627370496E+15,1.9342813113834067E+25]
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rax, %xmm2
punpckldq %xmm0, %xmm2 # xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
subpd %xmm1, %xmm2
movapd %xmm2, %xmm3
unpckhpd %xmm2, %xmm3 # xmm3 = xmm3[1],xmm2[1]
addsd %xmm2, %xmm3
movsd %xmm3, (%rdi,%rax,8)
incq %rax
cmpq %rax, %rsi
jne .LBB3_2
.LBB3_3: # %._crit_edge
retq
.Lfunc_end3:
.size _Z8populatePdm, .Lfunc_end3-_Z8populatePdm
.cfi_endproc
# -- End function
.globl _Z12print_matrixPKdm # -- Begin function _Z12print_matrixPKdm
.p2align 4, 0x90
.type _Z12print_matrixPKdm,@function
_Z12print_matrixPKdm: # @_Z12print_matrixPKdm
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB4_6
# %bb.1: # %.preheader.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
leaq (,%rsi,8), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r14,%r13,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r13
cmpq %r13, %rbx
jne .LBB4_3
# %bb.4: # in Loop: Header=BB4_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addq %r15, %r14
cmpq %rbx, %r12
jne .LBB4_2
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB4_6: # %._crit_edge
retq
.Lfunc_end4:
.size _Z12print_matrixPKdm, .Lfunc_end4-_Z12print_matrixPKdm
.cfi_endproc
# -- End function
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "%0.f "
.size .L.str.3, 6
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error allocating"
.size .Lstr, 17
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "NOCOPY!\n"
.size .Lstr.2, 9
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "NOFREE!\n"
.size .Lstr.3, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* File: matmult-cuda-double.cu
*
* Purpose:
*
* Input:
*
* Output:
*
* Compile: nvcc -o matmult-cuda-double.o matmult-cuda-double.cu
*
* Run: ./matmult-cuda-double.o
*
* Algorithm:
*
* Note:
*
* */
#include <stdio.h>
#include <cuda_runtime.h>
__global__ void VecAdd(double* A, double* B, double* C, int N)
{
int index = blockIdx.x * blockDim.x + threadIdx.x; //indice del vector
int ix; //ix indica el renglon
int iy; //iy toma valores solo entre 0 a N-1
double result; //Acumula la suma del renglon por la columna
int k; // Iterador
if(index < N * N)
{
ix = index / N;
iy = index % N;
result = 0.0;
for(k = 0; k < N; k++)
result += A[k + N * ix] * B[k * N + iy ];
C[iy + N * ix] = result;
}
}
// Host code
int main()
{
//Variables
int N; // Tamaño de la matriz cuadrada.
int i; // Indice del renglon.
int j; // Indice de la columna.
size_t size; // Tamaño total en memoria.
double* h_A; // Matriz A en el equipo.
double* h_B; // Matriz B en el equipo.
double* h_C; // Matriz C (resultado) en el equipo.
double* d_A; // Matriz A en la memoria de la GPU.
double* d_B; // Matriz B en la memoria de la GPU.
double* d_C; // Matriz C (resultado) en la memoria de la GPU.
int Tam; // Numero de datos que se manejan
int NumHilos; // Hilos por bloque
int numBlock; // Numero de bloques necesario para procesar los datos
//Asignacion de variables
N = 2500;
size = N * sizeof(double) * N;
//En la memoria del equipo
h_A = (double*)malloc(size);
h_B = (double*)malloc(size);
h_C = (double*)malloc(size);
//En la memoria de la GPU
cudaMalloc(&d_A, size);
cudaMalloc(&d_B, size);
cudaMalloc(&d_C, size);
//
Tam = N * N;
NumHilos = 1024;
numBlock = Tam / NumHilos;
if(Tam % NumHilos > 0) //Si sobran datos, aumenta los bloques en 1
numBlock++;
// LLena los arreglos A y B
for(i = 0;i < N;i++) //Renglon
for(j = 0;j < N;j++) // Columna
{
h_A[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
h_B[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
}
//Copia los arreglos de memoria del CPU a memoria de la GPU
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
// Invoke kernel
VecAdd<<<numBlock, NumHilos >>>(d_A, d_B, d_C, N);
//Copia el resultado de la multiplicacion de memoria de la GPU a memoria de la CPU
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
/*
//Imprime la matriz A
printf("Matriz A\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2e ", h_A[j + i * N]);
printf("\n");
}
//Imprime la matriz B
printf("Matriz B\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2e ", h_B[j + i * N]);
printf("\n");
}
//Imprime la matriz C
printf("Matriz C\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2e ", h_C[j + i * N]);
printf("\n");
}*/
//Libera la memoria utilizada.
// Free device memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
// Free host memory
free(h_A);
free(h_B);
free(h_C);
} | code for sm_80
Function : _Z6VecAddPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ MOV R5, c[0x0][0x178] ; /* 0x00005e0000057a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R7, R5, c[0x0][0x178], RZ ; /* 0x00005e0005077a24 */
/* 0x000fe400078e02ff */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R4 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0204 */
/*0060*/ ISETP.GE.AND P0, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R2, c[0x0][0x178] ; /* 0x00005e0000027a13 */
/* 0x000fe20000000000 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IABS R10, R6 ; /* 0x00000006000a7213 */
/* 0x000fe20000000000 */
/*00b0*/ CS2R R16, SRZ ; /* 0x0000000000107805 */
/* 0x000fe2000001ff00 */
/*00c0*/ I2F.RP R0, R2 ; /* 0x0000000200007306 */
/* 0x000e220000209400 */
/*00d0*/ ISETP.GE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fce0003f26270 */
/*00e0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R8, R0, 0xffffffe, RZ ; /* 0x0ffffffe00087810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*0110*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x001fe200000001ff */
/*0120*/ IMAD.MOV R7, RZ, RZ, -R9 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a09 */
/*0130*/ IMAD R7, R7, R2, RZ ; /* 0x0000000207077224 */
/* 0x000fca00078e02ff */
/*0140*/ IMAD.HI.U32 R9, R9, R7, R8 ; /* 0x0000000709097227 */
/* 0x000fe200078e0008 */
/*0150*/ MOV R7, R10 ; /* 0x0000000a00077202 */
/* 0x000fca0000000f00 */
/*0160*/ IMAD.HI.U32 R9, R9, R7, RZ ; /* 0x0000000709097227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fc800078e0a09 */
/*0180*/ IMAD R7, R2, R9, R7 ; /* 0x0000000902077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GT.U32.AND P0, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fda0003f04070 */
/*01a0*/ @!P0 IADD3 R7, R7, -R2, RZ ; /* 0x8000000207078210 */
/* 0x000fe40007ffe0ff */
/*01b0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f05270 */
/*01c0*/ ISETP.GT.U32.AND P2, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fda0003f44070 */
/*01d0*/ @!P2 IADD3 R7, R7, -R2, RZ ; /* 0x800000020707a210 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.GE.AND P2, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fc60003f46270 */
/*01f0*/ @!P1 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff079224 */
/* 0x000fe200078e0a07 */
/*0200*/ @!P0 LOP3.LUT R7, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff078a12 */
/* 0x000fd200078e33ff */
/*0210*/ @!P2 BRA 0xd90 ; /* 0x00000b700000a947 */
/* 0x000fea0003800000 */
/*0220*/ IADD3 R0, R5.reuse, -0x1, RZ ; /* 0xffffffff05007810 */
/* 0x040fe20007ffe0ff */
/*0230*/ CS2R R16, SRZ ; /* 0x0000000000107805 */
/* 0x000fe2000001ff00 */
/*0240*/ LOP3.LUT R24, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305187812 */
/* 0x000fe400078ec0ff */
/*0250*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*0260*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fd60000000f00 */
/*0270*/ @!P0 BRA 0xc30 ; /* 0x000009b000008947 */
/* 0x000fea0003800000 */
/*0280*/ IADD3 R2, -R24, c[0x0][0x178], RZ ; /* 0x00005e0018027a10 */
/* 0x000fe20007ffe1ff */
/*0290*/ HFMA2.MMA R22, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff167435 */
/* 0x000fe200000001ff */
/*02a0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*02b0*/ IMAD.IADD R25, R6, 0x1, -R7 ; /* 0x0000000106197824 */
/* 0x000fe200078e0a07 */
/*02c0*/ ISETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f04270 */
/*02d0*/ CS2R R16, SRZ ; /* 0x0000000000107805 */
/* 0x000fe2000001ff00 */
/*02e0*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fca0000000f00 */
/*02f0*/ IMAD.WIDE R22, R7, R22, c[0x0][0x168] ; /* 0x00005a0007167625 */
/* 0x000fcc00078e0216 */
/*0300*/ @!P0 BRA 0xaa0 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0310*/ ISETP.GT.AND P1, PT, R2, 0xc, PT ; /* 0x0000000c0200780c */
/* 0x000fe40003f24270 */
/*0320*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0330*/ @!P1 BRA 0x7e0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0340*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0350*/ MOV R26, UR6 ; /* 0x00000006001a7c02 */
/* 0x000fe20008000f00 */
/*0360*/ IMAD.U32 R27, RZ, RZ, UR7 ; /* 0x00000007ff1b7e24 */
/* 0x000fe2000f8e00ff */
/*0370*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000ea6000c1e1b00 */
/*0380*/ IMAD.WIDE R26, R25, 0x8, R26 ; /* 0x00000008191a7825 */
/* 0x000fca00078e021a */
/*0390*/ LDG.E.64 R8, [R26.64] ; /* 0x000000041a087981 */
/* 0x001ea2000c1e1b00 */
/*03a0*/ IMAD.WIDE R20, R5, 0x8, R22 ; /* 0x0000000805147825 */
/* 0x000fc600078e0216 */
/*03b0*/ LDG.E.64 R14, [R26.64+0x8] ; /* 0x000008041a0e7981 */
/* 0x000ee8000c1e1b00 */
/*03c0*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000ee2000c1e1b00 */
/*03d0*/ IMAD.WIDE R18, R5, 0x8, R20 ; /* 0x0000000805127825 */
/* 0x000fe200078e0214 */
/*03e0*/ DFMA R16, R12, R8, R16 ; /* 0x000000080c10722b */
/* 0x0060c80000000010 */
/*03f0*/ LDG.E.64 R8, [R18.64] ; /* 0x0000000412087981 */
/* 0x001ea8000c1e1b00 */
/*0400*/ LDG.E.64 R12, [R26.64+0x10] ; /* 0x000010041a0c7981 */
/* 0x000ea2000c1e1b00 */
/*0410*/ IMAD.WIDE R28, R5.reuse, 0x8, R18 ; /* 0x00000008051c7825 */
/* 0x040fe200078e0212 */
/*0420*/ DFMA R14, R10, R14, R16 ; /* 0x0000000e0a0e722b */
/* 0x0080a40000000010 */
/*0430*/ LDG.E.64 R16, [R26.64+0x18] ; /* 0x000018041a107981 */
/* 0x001ee8000c1e1b00 */
/*0440*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000ee2000c1e1b00 */
/*0450*/ IMAD.WIDE R22, R5, 0x8, R28 ; /* 0x0000000805167825 */
/* 0x000fe200078e021c */
/*0460*/ DFMA R12, R8, R12, R14 ; /* 0x0000000c080c722b */
/* 0x0040c4000000000e */
/*0470*/ LDG.E.64 R14, [R26.64+0x20] ; /* 0x000020041a0e7981 */
/* 0x001ea8000c1e1b00 */
/*0480*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x000ea2000c1e1b00 */
/*0490*/ IMAD.WIDE R20, R5.reuse, 0x8, R22 ; /* 0x0000000805147825 */
/* 0x040fe200078e0216 */
/*04a0*/ DFMA R16, R10, R16, R12 ; /* 0x000000100a10722b */
/* 0x0080a4000000000c */
/*04b0*/ LDG.E.64 R12, [R26.64+0x28] ; /* 0x000028041a0c7981 */
/* 0x001ee8000c1e1b00 */
/*04c0*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000ee2000c1e1b00 */
/*04d0*/ IMAD.WIDE R18, R5, 0x8, R20 ; /* 0x0000000805127825 */
/* 0x000fe200078e0214 */
/*04e0*/ DFMA R14, R8, R14, R16 ; /* 0x0000000e080e722b */
/* 0x0040c40000000010 */
/*04f0*/ LDG.E.64 R16, [R26.64+0x30] ; /* 0x000030041a107981 */
/* 0x001ea8000c1e1b00 */
/*0500*/ LDG.E.64 R8, [R18.64] ; /* 0x0000000412087981 */
/* 0x0000a2000c1e1b00 */
/*0510*/ IMAD.WIDE R28, R5.reuse, 0x8, R18 ; /* 0x00000008051c7825 */
/* 0x040fe200078e0212 */
/*0520*/ DFMA R12, R10, R12, R14 ; /* 0x0000000c0a0c722b */
/* 0x0082a4000000000e */
/*0530*/ LDG.E.64 R14, [R26.64+0x38] ; /* 0x000038041a0e7981 */
/* 0x002ee8000c1e1b00 */
/*0540*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x0002e8000c1e1b00 */
/*0550*/ LDG.E.64 R18, [R26.64+0x48] ; /* 0x000048041a127981 */
/* 0x001f22000c1e1b00 */
/*0560*/ IMAD.WIDE R28, R5, 0x8, R28 ; /* 0x00000008051c7825 */
/* 0x002fe200078e021c */
/*0570*/ DFMA R16, R8, R16, R12 ; /* 0x000000100810722b */
/* 0x0040c4000000000c */
/*0580*/ LDG.E.64 R12, [R26.64+0x40] ; /* 0x000040041a0c7981 */
/* 0x001ea8000c1e1b00 */
/*0590*/ LDG.E.64 R8, [R28.64] ; /* 0x000000041c087981 */
/* 0x000ea2000c1e1b00 */
/*05a0*/ IMAD.WIDE R22, R5, 0x8, R28 ; /* 0x0000000805167825 */
/* 0x000fe200078e021c */
/*05b0*/ DFMA R14, R10, R14, R16 ; /* 0x0000000e0a0e722b */
/* 0x0080880000000010 */
/*05c0*/ LDG.E.64 R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x001122000c1e1b00 */
/*05d0*/ IMAD.WIDE R20, R5.reuse, 0x8, R22 ; /* 0x0000000805147825 */
/* 0x040fe200078e0216 */
/*05e0*/ DFMA R12, R8, R12, R14 ; /* 0x0000000c080c722b */
/* 0x004324000000000e */
/*05f0*/ LDG.E.64 R22, [R26.64+0x60] ; /* 0x000060041a167981 */
/* 0x001ea8000c1e1b00 */
/*0600*/ LDG.E.64 R14, [R26.64+0x50] ; /* 0x000050041a0e7981 */
/* 0x002ee8000c1e1b00 */
/*0610*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ee2000c1e1b00 */
/*0620*/ IMAD.WIDE R16, R5, 0x8, R20 ; /* 0x0000000805107825 */
/* 0x000fe200078e0214 */
/*0630*/ DFMA R18, R10, R18, R12 ; /* 0x000000120a12722b */
/* 0x0100c4000000000c */
/*0640*/ LDG.E.64 R10, [R26.64+0x58] ; /* 0x000058041a0a7981 */
/* 0x001f28000c1e1b00 */
/*0650*/ LDG.E.64 R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000124000c1e1b00 */
/*0660*/ IMAD.WIDE R16, R5, 0x8, R16 ; /* 0x0000000805107825 */
/* 0x001fe200078e0210 */
/*0670*/ DFMA R14, R8, R14, R18 ; /* 0x0000000e080e722b */
/* 0x0081080000000012 */
/*0680*/ LDG.E.64 R8, [R16.64] ; /* 0x0000000410087981 */
/* 0x0010a2000c1e1b00 */
/*0690*/ IMAD.WIDE R28, R5, 0x8, R16 ; /* 0x00000008051c7825 */
/* 0x000fc600078e0210 */
/*06a0*/ LDG.E.64 R18, [R26.64+0x68] ; /* 0x000068041a127981 */
/* 0x000ee2000c1e1b00 */
/*06b0*/ DFMA R10, R12, R10, R14 ; /* 0x0000000a0c0a722b */
/* 0x010286000000000e */
/*06c0*/ LDG.E.64 R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x0008e8000c1e1b00 */
/*06d0*/ LDG.E.64 R14, [R26.64+0x78] ; /* 0x000078041a0e7981 */
/* 0x002f62000c1e1b00 */
/*06e0*/ IMAD.WIDE R28, R5, 0x8, R28 ; /* 0x00000008051c7825 */
/* 0x010fcc00078e021c */
/*06f0*/ IMAD.WIDE R12, R5, 0x8, R28 ; /* 0x00000008050c7825 */
/* 0x000fca00078e021c */
/*0700*/ LDG.E.64 R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x001f62000c1e1b00 */
/*0710*/ DFMA R22, R8, R22, R10 ; /* 0x000000160816722b */
/* 0x0040c6000000000a */
/*0720*/ LDG.E.64 R8, [R26.64+0x70] ; /* 0x000070041a087981 */
/* 0x001ea8000c1e1b00 */
/*0730*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000ea2000c1e1b00 */
/*0740*/ IADD3 R2, R2, -0x10, RZ ; /* 0xfffffff002027810 */
/* 0x000fe20007ffe0ff */
/*0750*/ DFMA R18, R20, R18, R22 ; /* 0x000000121412722b */
/* 0x0080860000000016 */
/*0760*/ ISETP.GT.AND P1, PT, R2, 0xc, PT ; /* 0x0000000c0200780c */
/* 0x000fe20003f24270 */
/*0770*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fe2000ff1e03f */
/*0780*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x000fc60007ffe0ff */
/*0790*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*07a0*/ IMAD.WIDE R22, R5, 0x8, R12 ; /* 0x0000000805167825 */
/* 0x001fe200078e020c */
/*07b0*/ DFMA R8, R10, R8, R18 ; /* 0x000000080a08722b */
/* 0x004f4c0000000012 */
/*07c0*/ DFMA R16, R16, R14, R8 ; /* 0x0000000e1010722b */
/* 0x0200620000000008 */
/*07d0*/ @P1 BRA 0x350 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*07e0*/ ISETP.GT.AND P1, PT, R2, 0x4, PT ; /* 0x000000040200780c */
/* 0x000fda0003f24270 */
/*07f0*/ @!P1 BRA 0xa80 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0800*/ MOV R26, UR6 ; /* 0x00000006001a7c02 */
/* 0x000fe20008000f00 */
/*0810*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000ea2000c1e1b00 */
/*0820*/ MOV R27, UR7 ; /* 0x00000007001b7c02 */
/* 0x000fca0008000f00 */
/*0830*/ IMAD.WIDE R26, R25, 0x8, R26 ; /* 0x00000008191a7825 */
/* 0x000fca00078e021a */
/*0840*/ LDG.E.64 R10, [R26.64] ; /* 0x000000041a0a7981 */
/* 0x000ea2000c1e1b00 */
/*0850*/ IMAD.WIDE R28, R5, 0x8, R22 ; /* 0x00000008051c7825 */
/* 0x000fc600078e0216 */
/*0860*/ LDG.E.64 R14, [R26.64+0x8] ; /* 0x000008041a0e7981 */
/* 0x001ee8000c1e1b00 */
/*0870*/ LDG.E.64 R8, [R28.64] ; /* 0x000000041c087981 */
/* 0x000ee2000c1e1b00 */
/*0880*/ IMAD.WIDE R20, R5, 0x8, R28 ; /* 0x0000000805147825 */
/* 0x000fe200078e021c */
/*0890*/ DFMA R16, R12, R10, R16 ; /* 0x0000000a0c10722b */
/* 0x0060c80000000010 */
/*08a0*/ LDG.E.64 R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x0010a8000c1e1b00 */
/*08b0*/ LDG.E.64 R10, [R26.64+0x10] ; /* 0x000010041a0a7981 */
/* 0x000ea2000c1e1b00 */
/*08c0*/ IMAD.WIDE R18, R5.reuse, 0x8, R20 ; /* 0x0000000805127825 */
/* 0x040fe200078e0214 */
/*08d0*/ DFMA R14, R8, R14, R16 ; /* 0x0000000e080e722b */
/* 0x0082a40000000010 */
/*08e0*/ LDG.E.64 R16, [R26.64+0x18] ; /* 0x000018041a107981 */
/* 0x002ee8000c1e1b00 */
/*08f0*/ LDG.E.64 R8, [R18.64] ; /* 0x0000000412087981 */
/* 0x000ee2000c1e1b00 */
/*0900*/ IMAD.WIDE R22, R5, 0x8, R18 ; /* 0x0000000805167825 */
/* 0x000fc600078e0212 */
/*0910*/ LDG.E.64 R20, [R26.64+0x38] ; /* 0x000038041a147981 */
/* 0x001f22000c1e1b00 */
/*0920*/ DFMA R10, R12, R10, R14 ; /* 0x0000000a0c0a722b */
/* 0x0040c6000000000e */
/*0930*/ LDG.E.64 R12, [R26.64+0x20] ; /* 0x000020041a0c7981 */
/* 0x001ea8000c1e1b00 */
/*0940*/ LDG.E.64 R14, [R22.64] ; /* 0x00000004160e7981 */
/* 0x0000a2000c1e1b00 */
/*0950*/ IMAD.WIDE R28, R5.reuse, 0x8, R22 ; /* 0x00000008051c7825 */
/* 0x040fe200078e0216 */
/*0960*/ DFMA R16, R8, R16, R10 ; /* 0x000000100810722b */
/* 0x0082a4000000000a */
/*0970*/ LDG.E.64 R8, [R26.64+0x28] ; /* 0x000028041a087981 */
/* 0x002ee8000c1e1b00 */
/*0980*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x0002e4000c1e1b00 */
/*0990*/ IMAD.WIDE R28, R5, 0x8, R28 ; /* 0x00000008051c7825 */
/* 0x002fcc00078e021c */
/*09a0*/ IMAD.WIDE R18, R5, 0x8, R28 ; /* 0x0000000805127825 */
/* 0x000fca00078e021c */
/*09b0*/ LDG.E.64 R22, [R18.64] ; /* 0x0000000412167981 */
/* 0x001f22000c1e1b00 */
/*09c0*/ DFMA R12, R14, R12, R16 ; /* 0x0000000c0e0c722b */
/* 0x0040c60000000010 */
/*09d0*/ LDG.E.64 R14, [R26.64+0x30] ; /* 0x000030041a0e7981 */
/* 0x001ea8000c1e1b00 */
/*09e0*/ LDG.E.64 R16, [R28.64] ; /* 0x000000041c107981 */
/* 0x000ea2000c1e1b00 */
/*09f0*/ DFMA R8, R10, R8, R12 ; /* 0x000000080a08722b */
/* 0x008ea2000000000c */
/*0a00*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0a10*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0a20*/ IADD3 R0, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fe40007ffe0ff */
/*0a30*/ IADD3 R2, R2, -0x8, RZ ; /* 0xfffffff802027810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a50*/ DFMA R16, R16, R14, R8 ; /* 0x0000000e1010722b */
/* 0x004f0c0000000008 */
/*0a60*/ DFMA R16, R22, R20, R16 ; /* 0x000000141610722b */
/* 0x0100640000000010 */
/*0a70*/ IMAD.WIDE R22, R5, 0x8, R18 ; /* 0x0000000805167825 */
/* 0x001fc800078e0212 */
/*0a80*/ ISETP.NE.OR P0, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */
/* 0x002fda0000705670 */
/*0a90*/ @!P0 BRA 0xc30 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x001fe20008000f00 */
/*0ab0*/ IMAD.U32 R8, RZ, RZ, UR6 ; /* 0x00000006ff087e24 */
/* 0x000fe2000f8e00ff */
/*0ac0*/ LDG.E.64 R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x000ea6000c1e1b00 */
/*0ad0*/ IMAD.WIDE R8, R25, 0x8, R8 ; /* 0x0000000819087825 */
/* 0x000fca00078e0208 */
/*0ae0*/ LDG.E.64 R26, [R8.64] ; /* 0x00000004081a7981 */
/* 0x000ea2000c1e1b00 */
/*0af0*/ IMAD.WIDE R14, R5, 0x8, R22 ; /* 0x00000008050e7825 */
/* 0x000fc600078e0216 */
/*0b00*/ LDG.E.64 R10, [R8.64+0x8] ; /* 0x00000804080a7981 */
/* 0x000ee8000c1e1b00 */
/*0b10*/ LDG.E.64 R12, [R14.64] ; /* 0x000000040e0c7981 */
/* 0x0000e8000c1e1b00 */
/*0b20*/ LDG.E.64 R28, [R8.64+0x18] ; /* 0x00001804081c7981 */
/* 0x000f22000c1e1b00 */
/*0b30*/ IMAD.WIDE R14, R5, 0x8, R14 ; /* 0x00000008050e7825 */
/* 0x001fca00078e020e */
/*0b40*/ LDG.E.64 R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000f62000c1e1b00 */
/*0b50*/ DFMA R26, R18, R26, R16 ; /* 0x0000001a121a722b */
/* 0x0040c60000000010 */
/*0b60*/ LDG.E.64 R16, [R8.64+0x10] ; /* 0x0000100408107981 */
/* 0x001f62000c1e1b00 */
/*0b70*/ IMAD.WIDE R18, R5, 0x8, R14 ; /* 0x0000000805127825 */
/* 0x000fca00078e020e */
/*0b80*/ LDG.E.64 R22, [R18.64] ; /* 0x0000000412167981 */
/* 0x000f22000c1e1b00 */
/*0b90*/ IADD3 R2, R2, -0x4, RZ ; /* 0xfffffffc02027810 */
/* 0x000fe20007ffe0ff */
/*0ba0*/ DFMA R10, R12, R10, R26 ; /* 0x0000000a0c0a722b */
/* 0x008f46000000001a */
/*0bb0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0bc0*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0bd0*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fc60007ffe0ff */
/*0be0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0bf0*/ DFMA R16, R20, R16, R10 ; /* 0x000000101410722b */
/* 0x020f0c000000000a */
/*0c00*/ DFMA R16, R22, R28, R16 ; /* 0x0000001c1610722b */
/* 0x0100640000000010 */
/*0c10*/ IMAD.WIDE R22, R5, 0x8, R18 ; /* 0x0000000805167825 */
/* 0x001fe200078e0212 */
/*0c20*/ @P0 BRA 0xaa0 ; /* 0xfffffe7000000947 */
/* 0x002fea000383ffff */
/*0c30*/ ISETP.NE.AND P0, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fda0003f05270 */
/*0c40*/ @!P0 BRA 0xd90 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0c50*/ IADD3 R4, R4, R0, RZ ; /* 0x0000000004047210 */
/* 0x000fe20007ffe0ff */
/*0c60*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x001fe400078e00ff */
/*0c70*/ IMAD R0, R0, c[0x0][0x178], R7 ; /* 0x00005e0000007a24 */
/* 0x000fe400078e0207 */
/*0c80*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x000fca00078e0204 */
/*0c90*/ IADD3 R2, -R7, R4, RZ ; /* 0x0000000407027210 */
/* 0x000fca0007ffe1ff */
/*0ca0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0209 */
/*0cb0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fe200078e0209 */
/*0cc0*/ MOV R0, R2 ; /* 0x0000000200007202 */
/* 0x000fe40000000f00 */
/*0cd0*/ MOV R7, R3 ; /* 0x0000000300077202 */
/* 0x000fc60000000f00 */
/*0ce0*/ IMAD.MOV.U32 R10, RZ, RZ, R0 ; /* 0x000000ffff0a7224 */
/* 0x001fe200078e0000 */
/*0cf0*/ MOV R11, R7 ; /* 0x00000007000b7202 */
/* 0x000fe20000000f00 */
/*0d00*/ LDG.E.64 R2, [R8.64] ; /* 0x0000000408027981 */
/* 0x0000aa000c1e1b00 */
/*0d10*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1b00 */
/*0d20*/ IADD3 R24, R24, -0x1, RZ ; /* 0xffffffff18187810 */
/* 0x000fc40007ffe0ff */
/*0d30*/ IADD3 R0, P1, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fe40007f3e0ff */
/*0d40*/ ISETP.NE.AND P0, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fe20003f05270 */
/*0d50*/ IMAD.WIDE R8, R5, 0x8, R8 ; /* 0x0000000805087825 */
/* 0x001fe200078e0208 */
/*0d60*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0d70*/ DFMA R16, R2, R10, R16 ; /* 0x0000000a0210722b */
/* 0x0060540000000010 */
/*0d80*/ @P0 BRA 0xce0 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0d90*/ MOV R7, 0x8 ; /* 0x0000000800077802 */
/* 0x000fca0000000f00 */
/*0da0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fca00078e0207 */
/*0db0*/ STG.E.64 [R6.64], R16 ; /* 0x0000001006007986 */
/* 0x002fe2000c101b04 */
/*0dc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0dd0*/ BRA 0xdd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* File: matmult-cuda-double.cu
*
* Purpose:
*
* Input:
*
* Output:
*
* Compile: nvcc -o matmult-cuda-double.o matmult-cuda-double.cu
*
* Run: ./matmult-cuda-double.o
*
* Algorithm:
*
* Note:
*
* */
#include <stdio.h>
#include <cuda_runtime.h>
__global__ void VecAdd(double* A, double* B, double* C, int N)
{
int index = blockIdx.x * blockDim.x + threadIdx.x; //indice del vector
int ix; //ix indica el renglon
int iy; //iy toma valores solo entre 0 a N-1
double result; //Acumula la suma del renglon por la columna
int k; // Iterador
if(index < N * N)
{
ix = index / N;
iy = index % N;
result = 0.0;
for(k = 0; k < N; k++)
result += A[k + N * ix] * B[k * N + iy ];
C[iy + N * ix] = result;
}
}
// Host code
int main()
{
//Variables
int N; // Tamaño de la matriz cuadrada.
int i; // Indice del renglon.
int j; // Indice de la columna.
size_t size; // Tamaño total en memoria.
double* h_A; // Matriz A en el equipo.
double* h_B; // Matriz B en el equipo.
double* h_C; // Matriz C (resultado) en el equipo.
double* d_A; // Matriz A en la memoria de la GPU.
double* d_B; // Matriz B en la memoria de la GPU.
double* d_C; // Matriz C (resultado) en la memoria de la GPU.
int Tam; // Numero de datos que se manejan
int NumHilos; // Hilos por bloque
int numBlock; // Numero de bloques necesario para procesar los datos
//Asignacion de variables
N = 2500;
size = N * sizeof(double) * N;
//En la memoria del equipo
h_A = (double*)malloc(size);
h_B = (double*)malloc(size);
h_C = (double*)malloc(size);
//En la memoria de la GPU
cudaMalloc(&d_A, size);
cudaMalloc(&d_B, size);
cudaMalloc(&d_C, size);
//
Tam = N * N;
NumHilos = 1024;
numBlock = Tam / NumHilos;
if(Tam % NumHilos > 0) //Si sobran datos, aumenta los bloques en 1
numBlock++;
// LLena los arreglos A y B
for(i = 0;i < N;i++) //Renglon
for(j = 0;j < N;j++) // Columna
{
h_A[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
h_B[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
}
//Copia los arreglos de memoria del CPU a memoria de la GPU
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
// Invoke kernel
VecAdd<<<numBlock, NumHilos >>>(d_A, d_B, d_C, N);
//Copia el resultado de la multiplicacion de memoria de la GPU a memoria de la CPU
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
/*
//Imprime la matriz A
printf("Matriz A\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2e ", h_A[j + i * N]);
printf("\n");
}
//Imprime la matriz B
printf("Matriz B\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2e ", h_B[j + i * N]);
printf("\n");
}
//Imprime la matriz C
printf("Matriz C\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2e ", h_C[j + i * N]);
printf("\n");
}*/
//Libera la memoria utilizada.
// Free device memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
// Free host memory
free(h_A);
free(h_B);
free(h_C);
} | .file "tmpxft_0008644c_00000000-6_matmult-cuda-double.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6VecAddPdS_S_iPdS_S_i
.type _Z30__device_stub__Z6VecAddPdS_S_iPdS_S_i, @function
_Z30__device_stub__Z6VecAddPdS_S_iPdS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z6VecAddPdS_S_iPdS_S_i, .-_Z30__device_stub__Z6VecAddPdS_S_iPdS_S_i
.globl _Z6VecAddPdS_S_i
.type _Z6VecAddPdS_S_i, @function
_Z6VecAddPdS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6VecAddPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6VecAddPdS_S_i, .-_Z6VecAddPdS_S_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $50000000, %edi
call malloc@PLT
movq %rax, %r13
movq %rax, 8(%rsp)
movl $50000000, %edi
call malloc@PLT
movq %rax, %r12
movq %rax, 16(%rsp)
movl $50000000, %edi
call malloc@PLT
movq %rax, 24(%rsp)
leaq 40(%rsp), %rdi
movl $50000000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $50000000, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $50000000, %esi
call cudaMalloc@PLT
movl $0, %r15d
movl $11, %r14d
.L12:
movl %r14d, %ebp
movl $0, %ebx
.L13:
call rand@PLT
cltd
idivl %ebp
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
mulsd .LC0(%rip), %xmm0
movsd %xmm0, 0(%r13,%rbx)
call rand@PLT
cltd
idivl %ebp
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
mulsd .LC0(%rip), %xmm0
movsd %xmm0, (%r12,%rbx)
addq $8, %rbx
cmpq $20000, %rbx
jne .L13
addl $11, %r14d
addl $2500, %r15d
addq $20000, %r13
addq $20000, %r12
cmpl $6250000, %r15d
jne .L12
movl $1, %ecx
movl $50000000, %edx
movq 8(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $50000000, %edx
movq 16(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 76(%rsp)
movl $1, 80(%rsp)
movl $6104, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movl $2, %ecx
movl $50000000, %edx
movq 56(%rsp), %rsi
movq 24(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $2500, %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z30__device_stub__Z6VecAddPdS_S_iPdS_S_i
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z6VecAddPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 515396076
.long 1072819077
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* File: matmult-cuda-double.cu
*
* Purpose:
*
* Input:
*
* Output:
*
* Compile: nvcc -o matmult-cuda-double.o matmult-cuda-double.cu
*
* Run: ./matmult-cuda-double.o
*
* Algorithm:
*
* Note:
*
* */
#include <stdio.h>
#include <cuda_runtime.h>
__global__ void VecAdd(double* A, double* B, double* C, int N)
{
int index = blockIdx.x * blockDim.x + threadIdx.x; //indice del vector
int ix; //ix indica el renglon
int iy; //iy toma valores solo entre 0 a N-1
double result; //Acumula la suma del renglon por la columna
int k; // Iterador
if(index < N * N)
{
ix = index / N;
iy = index % N;
result = 0.0;
for(k = 0; k < N; k++)
result += A[k + N * ix] * B[k * N + iy ];
C[iy + N * ix] = result;
}
}
// Host code
int main()
{
//Variables
int N; // Tamaño de la matriz cuadrada.
int i; // Indice del renglon.
int j; // Indice de la columna.
size_t size; // Tamaño total en memoria.
double* h_A; // Matriz A en el equipo.
double* h_B; // Matriz B en el equipo.
double* h_C; // Matriz C (resultado) en el equipo.
double* d_A; // Matriz A en la memoria de la GPU.
double* d_B; // Matriz B en la memoria de la GPU.
double* d_C; // Matriz C (resultado) en la memoria de la GPU.
int Tam; // Numero de datos que se manejan
int NumHilos; // Hilos por bloque
int numBlock; // Numero de bloques necesario para procesar los datos
//Asignacion de variables
N = 2500;
size = N * sizeof(double) * N;
//En la memoria del equipo
h_A = (double*)malloc(size);
h_B = (double*)malloc(size);
h_C = (double*)malloc(size);
//En la memoria de la GPU
cudaMalloc(&d_A, size);
cudaMalloc(&d_B, size);
cudaMalloc(&d_C, size);
//
Tam = N * N;
NumHilos = 1024;
numBlock = Tam / NumHilos;
if(Tam % NumHilos > 0) //Si sobran datos, aumenta los bloques en 1
numBlock++;
// LLena los arreglos A y B
for(i = 0;i < N;i++) //Renglon
for(j = 0;j < N;j++) // Columna
{
h_A[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
h_B[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
}
//Copia los arreglos de memoria del CPU a memoria de la GPU
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
// Invoke kernel
VecAdd<<<numBlock, NumHilos >>>(d_A, d_B, d_C, N);
//Copia el resultado de la multiplicacion de memoria de la GPU a memoria de la CPU
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
/*
//Imprime la matriz A
printf("Matriz A\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2e ", h_A[j + i * N]);
printf("\n");
}
//Imprime la matriz B
printf("Matriz B\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2e ", h_B[j + i * N]);
printf("\n");
}
//Imprime la matriz C
printf("Matriz C\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2e ", h_C[j + i * N]);
printf("\n");
}*/
//Libera la memoria utilizada.
// Free device memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
// Free host memory
free(h_A);
free(h_B);
free(h_C);
} | /* File: matmult-cuda-double.cu
*
* Purpose:
*
* Input:
*
* Output:
*
* Compile: nvcc -o matmult-cuda-double.o matmult-cuda-double.cu
*
* Run: ./matmult-cuda-double.o
*
* Algorithm:
*
* Note:
*
* */
#include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void VecAdd(double* A, double* B, double* C, int N)
{
int index = blockIdx.x * blockDim.x + threadIdx.x; //indice del vector
int ix; //ix indica el renglon
int iy; //iy toma valores solo entre 0 a N-1
double result; //Acumula la suma del renglon por la columna
int k; // Iterador
if(index < N * N)
{
ix = index / N;
iy = index % N;
result = 0.0;
for(k = 0; k < N; k++)
result += A[k + N * ix] * B[k * N + iy ];
C[iy + N * ix] = result;
}
}
// Host code
int main()
{
//Variables
int N; // Tamaño de la matriz cuadrada.
int i; // Indice del renglon.
int j; // Indice de la columna.
size_t size; // Tamaño total en memoria.
double* h_A; // Matriz A en el equipo.
double* h_B; // Matriz B en el equipo.
double* h_C; // Matriz C (resultado) en el equipo.
double* d_A; // Matriz A en la memoria de la GPU.
double* d_B; // Matriz B en la memoria de la GPU.
double* d_C; // Matriz C (resultado) en la memoria de la GPU.
int Tam; // Numero de datos que se manejan
int NumHilos; // Hilos por bloque
int numBlock; // Numero de bloques necesario para procesar los datos
//Asignacion de variables
N = 2500;
size = N * sizeof(double) * N;
//En la memoria del equipo
h_A = (double*)malloc(size);
h_B = (double*)malloc(size);
h_C = (double*)malloc(size);
//En la memoria de la GPU
hipMalloc(&d_A, size);
hipMalloc(&d_B, size);
hipMalloc(&d_C, size);
//
Tam = N * N;
NumHilos = 1024;
numBlock = Tam / NumHilos;
if(Tam % NumHilos > 0) //Si sobran datos, aumenta los bloques en 1
numBlock++;
// LLena los arreglos A y B
for(i = 0;i < N;i++) //Renglon
for(j = 0;j < N;j++) // Columna
{
h_A[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
h_B[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
}
//Copia los arreglos de memoria del CPU a memoria de la GPU
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
// Invoke kernel
VecAdd<<<numBlock, NumHilos >>>(d_A, d_B, d_C, N);
//Copia el resultado de la multiplicacion de memoria de la GPU a memoria de la CPU
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
/*
//Imprime la matriz A
printf("Matriz A\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2e ", h_A[j + i * N]);
printf("\n");
}
//Imprime la matriz B
printf("Matriz B\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2e ", h_B[j + i * N]);
printf("\n");
}
//Imprime la matriz C
printf("Matriz C\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2e ", h_C[j + i * N]);
printf("\n");
}*/
//Libera la memoria utilizada.
// Free device memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// Free host memory
free(h_A);
free(h_B);
free(h_C);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* File: matmult-cuda-double.cu
*
* Purpose:
*
* Input:
*
* Output:
*
* Compile: nvcc -o matmult-cuda-double.o matmult-cuda-double.cu
*
* Run: ./matmult-cuda-double.o
*
* Algorithm:
*
* Note:
*
* */
#include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void VecAdd(double* A, double* B, double* C, int N)
{
int index = blockIdx.x * blockDim.x + threadIdx.x; //indice del vector
int ix; //ix indica el renglon
int iy; //iy toma valores solo entre 0 a N-1
double result; //Acumula la suma del renglon por la columna
int k; // Iterador
if(index < N * N)
{
ix = index / N;
iy = index % N;
result = 0.0;
for(k = 0; k < N; k++)
result += A[k + N * ix] * B[k * N + iy ];
C[iy + N * ix] = result;
}
}
// Host code
int main()
{
//Variables
int N; // Tamaño de la matriz cuadrada.
int i; // Indice del renglon.
int j; // Indice de la columna.
size_t size; // Tamaño total en memoria.
double* h_A; // Matriz A en el equipo.
double* h_B; // Matriz B en el equipo.
double* h_C; // Matriz C (resultado) en el equipo.
double* d_A; // Matriz A en la memoria de la GPU.
double* d_B; // Matriz B en la memoria de la GPU.
double* d_C; // Matriz C (resultado) en la memoria de la GPU.
int Tam; // Numero de datos que se manejan
int NumHilos; // Hilos por bloque
int numBlock; // Numero de bloques necesario para procesar los datos
//Asignacion de variables
N = 2500;
size = N * sizeof(double) * N;
//En la memoria del equipo
h_A = (double*)malloc(size);
h_B = (double*)malloc(size);
h_C = (double*)malloc(size);
//En la memoria de la GPU
hipMalloc(&d_A, size);
hipMalloc(&d_B, size);
hipMalloc(&d_C, size);
//
Tam = N * N;
NumHilos = 1024;
numBlock = Tam / NumHilos;
if(Tam % NumHilos > 0) //Si sobran datos, aumenta los bloques en 1
numBlock++;
// LLena los arreglos A y B
for(i = 0;i < N;i++) //Renglon
for(j = 0;j < N;j++) // Columna
{
h_A[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
h_B[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
}
//Copia los arreglos de memoria del CPU a memoria de la GPU
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
// Invoke kernel
VecAdd<<<numBlock, NumHilos >>>(d_A, d_B, d_C, N);
//Copia el resultado de la multiplicacion de memoria de la GPU a memoria de la CPU
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
/*
//Imprime la matriz A
printf("Matriz A\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2e ", h_A[j + i * N]);
printf("\n");
}
//Imprime la matriz B
printf("Matriz B\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2e ", h_B[j + i * N]);
printf("\n");
}
//Imprime la matriz C
printf("Matriz C\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2e ", h_C[j + i * N]);
printf("\n");
}*/
//Libera la memoria utilizada.
// Free device memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// Free host memory
free(h_A);
free(h_B);
free(h_C);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPdS_S_i
.globl _Z6VecAddPdS_S_i
.p2align 8
.type _Z6VecAddPdS_S_i,@function
_Z6VecAddPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mul_i32 s3, s2, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_6
s_ashr_i32 s3, s2, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s4, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s4, s4, s3
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s5, 0, s4
s_cmp_lt_i32 s2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v2, v0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v7, v0, v3
v_mul_lo_u32 v2, v7, s2
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v1, v2
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[3:4], 3, v[2:3]
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[8:9], 3, v[5:6]
v_add_nc_u32_e32 v5, s2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
global_load_b64 v[10:11], v[3:4], off
global_load_b64 v[8:9], v[8:9], off
v_add_co_u32 v3, vcc_lo, v3, 8
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[1:2], v[10:11], v[8:9], v[1:2]
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v7, s2, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b64 v[3:4], v[1:2], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPdS_S_i, .Lfunc_end0-_Z6VecAddPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6VecAddPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* File: matmult-cuda-double.cu
*
* Purpose:
*
* Input:
*
* Output:
*
* Compile: nvcc -o matmult-cuda-double.o matmult-cuda-double.cu
*
* Run: ./matmult-cuda-double.o
*
* Algorithm:
*
* Note:
*
* */
#include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void VecAdd(double* A, double* B, double* C, int N)
{
int index = blockIdx.x * blockDim.x + threadIdx.x; //indice del vector
int ix; //ix indica el renglon
int iy; //iy toma valores solo entre 0 a N-1
double result; //Acumula la suma del renglon por la columna
int k; // Iterador
if(index < N * N)
{
ix = index / N;
iy = index % N;
result = 0.0;
for(k = 0; k < N; k++)
result += A[k + N * ix] * B[k * N + iy ];
C[iy + N * ix] = result;
}
}
// Host code
int main()
{
//Variables
int N; // Tamaño de la matriz cuadrada.
int i; // Indice del renglon.
int j; // Indice de la columna.
size_t size; // Tamaño total en memoria.
double* h_A; // Matriz A en el equipo.
double* h_B; // Matriz B en el equipo.
double* h_C; // Matriz C (resultado) en el equipo.
double* d_A; // Matriz A en la memoria de la GPU.
double* d_B; // Matriz B en la memoria de la GPU.
double* d_C; // Matriz C (resultado) en la memoria de la GPU.
int Tam; // Numero de datos que se manejan
int NumHilos; // Hilos por bloque
int numBlock; // Numero de bloques necesario para procesar los datos
//Asignacion de variables
N = 2500;
size = N * sizeof(double) * N;
//En la memoria del equipo
h_A = (double*)malloc(size);
h_B = (double*)malloc(size);
h_C = (double*)malloc(size);
//En la memoria de la GPU
hipMalloc(&d_A, size);
hipMalloc(&d_B, size);
hipMalloc(&d_C, size);
//
Tam = N * N;
NumHilos = 1024;
numBlock = Tam / NumHilos;
if(Tam % NumHilos > 0) //Si sobran datos, aumenta los bloques en 1
numBlock++;
// LLena los arreglos A y B
for(i = 0;i < N;i++) //Renglon
for(j = 0;j < N;j++) // Columna
{
h_A[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
h_B[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
}
//Copia los arreglos de memoria del CPU a memoria de la GPU
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
// Invoke kernel
VecAdd<<<numBlock, NumHilos >>>(d_A, d_B, d_C, N);
//Copia el resultado de la multiplicacion de memoria de la GPU a memoria de la CPU
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
/*
//Imprime la matriz A
printf("Matriz A\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2e ", h_A[j + i * N]);
printf("\n");
}
//Imprime la matriz B
printf("Matriz B\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2e ", h_B[j + i * N]);
printf("\n");
}
//Imprime la matriz C
printf("Matriz C\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2e ", h_C[j + i * N]);
printf("\n");
}*/
//Libera la memoria utilizada.
// Free device memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// Free host memory
free(h_A);
free(h_B);
free(h_C);
} | .text
.file "matmult-cuda-double.hip"
.globl _Z21__device_stub__VecAddPdS_S_i # -- Begin function _Z21__device_stub__VecAddPdS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPdS_S_i,@function
_Z21__device_stub__VecAddPdS_S_i: # @_Z21__device_stub__VecAddPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPdS_S_i, .Lfunc_end0-_Z21__device_stub__VecAddPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3ff1eb851eb851ec # double 1.1200000000000001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $50000000, %edi # imm = 0x2FAF080
callq malloc
movq %rax, %r13
movl $50000000, %edi # imm = 0x2FAF080
callq malloc
movq %rax, %rbp
movl $50000000, %edi # imm = 0x2FAF080
callq malloc
movq %rax, 40(%rsp) # 8-byte Spill
leaq 24(%rsp), %rdi
movl $50000000, %esi # imm = 0x2FAF080
callq hipMalloc
leaq 16(%rsp), %rdi
movl $50000000, %esi # imm = 0x2FAF080
callq hipMalloc
leaq 8(%rsp), %rdi
movl $50000000, %esi # imm = 0x2FAF080
callq hipMalloc
xorl %r12d, %r12d
movq %r13, %r14
movq %rbp, 48(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
leal (%r12,%r12,4), %eax
leal (%r12,%rax,2), %r15d
addl $11, %r15d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltd
idivl %r15d
xorps %xmm0, %xmm0
cvtsi2sd %edx, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, (%r13,%rbx,8)
callq rand
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
cltd
idivl %r15d
xorps %xmm0, %xmm0
cvtsi2sd %edx, %xmm0
mulsd %xmm1, %xmm0
movsd %xmm0, (%rbp,%rbx,8)
incq %rbx
cmpq $2500, %rbx # imm = 0x9C4
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r12
addq $20000, %rbp # imm = 0x4E20
addq $20000, %r13 # imm = 0x4E20
cmpq $2500, %r12 # imm = 0x9C4
jne .LBB1_1
# %bb.4:
movq 24(%rsp), %rdi
movl $50000000, %edx # imm = 0x2FAF080
movq %r14, %rbx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $50000000, %edx # imm = 0x2FAF080
movq 48(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 5080(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $2500, 36(%rsp) # imm = 0x9C4
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z6VecAddPdS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movl $50000000, %edx # imm = 0x2FAF080
movq 40(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPdS_S_i,@object # @_Z6VecAddPdS_S_i
.section .rodata,"a",@progbits
.globl _Z6VecAddPdS_S_i
.p2align 3, 0x0
_Z6VecAddPdS_S_i:
.quad _Z21__device_stub__VecAddPdS_S_i
.size _Z6VecAddPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6VecAddPdS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6VecAddPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ MOV R5, c[0x0][0x178] ; /* 0x00005e0000057a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R7, R5, c[0x0][0x178], RZ ; /* 0x00005e0005077a24 */
/* 0x000fe400078e02ff */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R4 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0204 */
/*0060*/ ISETP.GE.AND P0, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R2, c[0x0][0x178] ; /* 0x00005e0000027a13 */
/* 0x000fe20000000000 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IABS R10, R6 ; /* 0x00000006000a7213 */
/* 0x000fe20000000000 */
/*00b0*/ CS2R R16, SRZ ; /* 0x0000000000107805 */
/* 0x000fe2000001ff00 */
/*00c0*/ I2F.RP R0, R2 ; /* 0x0000000200007306 */
/* 0x000e220000209400 */
/*00d0*/ ISETP.GE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fce0003f26270 */
/*00e0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R8, R0, 0xffffffe, RZ ; /* 0x0ffffffe00087810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*0110*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x001fe200000001ff */
/*0120*/ IMAD.MOV R7, RZ, RZ, -R9 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a09 */
/*0130*/ IMAD R7, R7, R2, RZ ; /* 0x0000000207077224 */
/* 0x000fca00078e02ff */
/*0140*/ IMAD.HI.U32 R9, R9, R7, R8 ; /* 0x0000000709097227 */
/* 0x000fe200078e0008 */
/*0150*/ MOV R7, R10 ; /* 0x0000000a00077202 */
/* 0x000fca0000000f00 */
/*0160*/ IMAD.HI.U32 R9, R9, R7, RZ ; /* 0x0000000709097227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fc800078e0a09 */
/*0180*/ IMAD R7, R2, R9, R7 ; /* 0x0000000902077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GT.U32.AND P0, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fda0003f04070 */
/*01a0*/ @!P0 IADD3 R7, R7, -R2, RZ ; /* 0x8000000207078210 */
/* 0x000fe40007ffe0ff */
/*01b0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f05270 */
/*01c0*/ ISETP.GT.U32.AND P2, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fda0003f44070 */
/*01d0*/ @!P2 IADD3 R7, R7, -R2, RZ ; /* 0x800000020707a210 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.GE.AND P2, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fc60003f46270 */
/*01f0*/ @!P1 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff079224 */
/* 0x000fe200078e0a07 */
/*0200*/ @!P0 LOP3.LUT R7, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff078a12 */
/* 0x000fd200078e33ff */
/*0210*/ @!P2 BRA 0xd90 ; /* 0x00000b700000a947 */
/* 0x000fea0003800000 */
/*0220*/ IADD3 R0, R5.reuse, -0x1, RZ ; /* 0xffffffff05007810 */
/* 0x040fe20007ffe0ff */
/*0230*/ CS2R R16, SRZ ; /* 0x0000000000107805 */
/* 0x000fe2000001ff00 */
/*0240*/ LOP3.LUT R24, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305187812 */
/* 0x000fe400078ec0ff */
/*0250*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*0260*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fd60000000f00 */
/*0270*/ @!P0 BRA 0xc30 ; /* 0x000009b000008947 */
/* 0x000fea0003800000 */
/*0280*/ IADD3 R2, -R24, c[0x0][0x178], RZ ; /* 0x00005e0018027a10 */
/* 0x000fe20007ffe1ff */
/*0290*/ HFMA2.MMA R22, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff167435 */
/* 0x000fe200000001ff */
/*02a0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*02b0*/ IMAD.IADD R25, R6, 0x1, -R7 ; /* 0x0000000106197824 */
/* 0x000fe200078e0a07 */
/*02c0*/ ISETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f04270 */
/*02d0*/ CS2R R16, SRZ ; /* 0x0000000000107805 */
/* 0x000fe2000001ff00 */
/*02e0*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fca0000000f00 */
/*02f0*/ IMAD.WIDE R22, R7, R22, c[0x0][0x168] ; /* 0x00005a0007167625 */
/* 0x000fcc00078e0216 */
/*0300*/ @!P0 BRA 0xaa0 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0310*/ ISETP.GT.AND P1, PT, R2, 0xc, PT ; /* 0x0000000c0200780c */
/* 0x000fe40003f24270 */
/*0320*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0330*/ @!P1 BRA 0x7e0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0340*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0350*/ MOV R26, UR6 ; /* 0x00000006001a7c02 */
/* 0x000fe20008000f00 */
/*0360*/ IMAD.U32 R27, RZ, RZ, UR7 ; /* 0x00000007ff1b7e24 */
/* 0x000fe2000f8e00ff */
/*0370*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000ea6000c1e1b00 */
/*0380*/ IMAD.WIDE R26, R25, 0x8, R26 ; /* 0x00000008191a7825 */
/* 0x000fca00078e021a */
/*0390*/ LDG.E.64 R8, [R26.64] ; /* 0x000000041a087981 */
/* 0x001ea2000c1e1b00 */
/*03a0*/ IMAD.WIDE R20, R5, 0x8, R22 ; /* 0x0000000805147825 */
/* 0x000fc600078e0216 */
/*03b0*/ LDG.E.64 R14, [R26.64+0x8] ; /* 0x000008041a0e7981 */
/* 0x000ee8000c1e1b00 */
/*03c0*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000ee2000c1e1b00 */
/*03d0*/ IMAD.WIDE R18, R5, 0x8, R20 ; /* 0x0000000805127825 */
/* 0x000fe200078e0214 */
/*03e0*/ DFMA R16, R12, R8, R16 ; /* 0x000000080c10722b */
/* 0x0060c80000000010 */
/*03f0*/ LDG.E.64 R8, [R18.64] ; /* 0x0000000412087981 */
/* 0x001ea8000c1e1b00 */
/*0400*/ LDG.E.64 R12, [R26.64+0x10] ; /* 0x000010041a0c7981 */
/* 0x000ea2000c1e1b00 */
/*0410*/ IMAD.WIDE R28, R5.reuse, 0x8, R18 ; /* 0x00000008051c7825 */
/* 0x040fe200078e0212 */
/*0420*/ DFMA R14, R10, R14, R16 ; /* 0x0000000e0a0e722b */
/* 0x0080a40000000010 */
/*0430*/ LDG.E.64 R16, [R26.64+0x18] ; /* 0x000018041a107981 */
/* 0x001ee8000c1e1b00 */
/*0440*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000ee2000c1e1b00 */
/*0450*/ IMAD.WIDE R22, R5, 0x8, R28 ; /* 0x0000000805167825 */
/* 0x000fe200078e021c */
/*0460*/ DFMA R12, R8, R12, R14 ; /* 0x0000000c080c722b */
/* 0x0040c4000000000e */
/*0470*/ LDG.E.64 R14, [R26.64+0x20] ; /* 0x000020041a0e7981 */
/* 0x001ea8000c1e1b00 */
/*0480*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x000ea2000c1e1b00 */
/*0490*/ IMAD.WIDE R20, R5.reuse, 0x8, R22 ; /* 0x0000000805147825 */
/* 0x040fe200078e0216 */
/*04a0*/ DFMA R16, R10, R16, R12 ; /* 0x000000100a10722b */
/* 0x0080a4000000000c */
/*04b0*/ LDG.E.64 R12, [R26.64+0x28] ; /* 0x000028041a0c7981 */
/* 0x001ee8000c1e1b00 */
/*04c0*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000ee2000c1e1b00 */
/*04d0*/ IMAD.WIDE R18, R5, 0x8, R20 ; /* 0x0000000805127825 */
/* 0x000fe200078e0214 */
/*04e0*/ DFMA R14, R8, R14, R16 ; /* 0x0000000e080e722b */
/* 0x0040c40000000010 */
/*04f0*/ LDG.E.64 R16, [R26.64+0x30] ; /* 0x000030041a107981 */
/* 0x001ea8000c1e1b00 */
/*0500*/ LDG.E.64 R8, [R18.64] ; /* 0x0000000412087981 */
/* 0x0000a2000c1e1b00 */
/*0510*/ IMAD.WIDE R28, R5.reuse, 0x8, R18 ; /* 0x00000008051c7825 */
/* 0x040fe200078e0212 */
/*0520*/ DFMA R12, R10, R12, R14 ; /* 0x0000000c0a0c722b */
/* 0x0082a4000000000e */
/*0530*/ LDG.E.64 R14, [R26.64+0x38] ; /* 0x000038041a0e7981 */
/* 0x002ee8000c1e1b00 */
/*0540*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x0002e8000c1e1b00 */
/*0550*/ LDG.E.64 R18, [R26.64+0x48] ; /* 0x000048041a127981 */
/* 0x001f22000c1e1b00 */
/*0560*/ IMAD.WIDE R28, R5, 0x8, R28 ; /* 0x00000008051c7825 */
/* 0x002fe200078e021c */
/*0570*/ DFMA R16, R8, R16, R12 ; /* 0x000000100810722b */
/* 0x0040c4000000000c */
/*0580*/ LDG.E.64 R12, [R26.64+0x40] ; /* 0x000040041a0c7981 */
/* 0x001ea8000c1e1b00 */
/*0590*/ LDG.E.64 R8, [R28.64] ; /* 0x000000041c087981 */
/* 0x000ea2000c1e1b00 */
/*05a0*/ IMAD.WIDE R22, R5, 0x8, R28 ; /* 0x0000000805167825 */
/* 0x000fe200078e021c */
/*05b0*/ DFMA R14, R10, R14, R16 ; /* 0x0000000e0a0e722b */
/* 0x0080880000000010 */
/*05c0*/ LDG.E.64 R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x001122000c1e1b00 */
/*05d0*/ IMAD.WIDE R20, R5.reuse, 0x8, R22 ; /* 0x0000000805147825 */
/* 0x040fe200078e0216 */
/*05e0*/ DFMA R12, R8, R12, R14 ; /* 0x0000000c080c722b */
/* 0x004324000000000e */
/*05f0*/ LDG.E.64 R22, [R26.64+0x60] ; /* 0x000060041a167981 */
/* 0x001ea8000c1e1b00 */
/*0600*/ LDG.E.64 R14, [R26.64+0x50] ; /* 0x000050041a0e7981 */
/* 0x002ee8000c1e1b00 */
/*0610*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ee2000c1e1b00 */
/*0620*/ IMAD.WIDE R16, R5, 0x8, R20 ; /* 0x0000000805107825 */
/* 0x000fe200078e0214 */
/*0630*/ DFMA R18, R10, R18, R12 ; /* 0x000000120a12722b */
/* 0x0100c4000000000c */
/*0640*/ LDG.E.64 R10, [R26.64+0x58] ; /* 0x000058041a0a7981 */
/* 0x001f28000c1e1b00 */
/*0650*/ LDG.E.64 R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000124000c1e1b00 */
/*0660*/ IMAD.WIDE R16, R5, 0x8, R16 ; /* 0x0000000805107825 */
/* 0x001fe200078e0210 */
/*0670*/ DFMA R14, R8, R14, R18 ; /* 0x0000000e080e722b */
/* 0x0081080000000012 */
/*0680*/ LDG.E.64 R8, [R16.64] ; /* 0x0000000410087981 */
/* 0x0010a2000c1e1b00 */
/*0690*/ IMAD.WIDE R28, R5, 0x8, R16 ; /* 0x00000008051c7825 */
/* 0x000fc600078e0210 */
/*06a0*/ LDG.E.64 R18, [R26.64+0x68] ; /* 0x000068041a127981 */
/* 0x000ee2000c1e1b00 */
/*06b0*/ DFMA R10, R12, R10, R14 ; /* 0x0000000a0c0a722b */
/* 0x010286000000000e */
/*06c0*/ LDG.E.64 R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x0008e8000c1e1b00 */
/*06d0*/ LDG.E.64 R14, [R26.64+0x78] ; /* 0x000078041a0e7981 */
/* 0x002f62000c1e1b00 */
/*06e0*/ IMAD.WIDE R28, R5, 0x8, R28 ; /* 0x00000008051c7825 */
/* 0x010fcc00078e021c */
/*06f0*/ IMAD.WIDE R12, R5, 0x8, R28 ; /* 0x00000008050c7825 */
/* 0x000fca00078e021c */
/*0700*/ LDG.E.64 R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x001f62000c1e1b00 */
/*0710*/ DFMA R22, R8, R22, R10 ; /* 0x000000160816722b */
/* 0x0040c6000000000a */
/*0720*/ LDG.E.64 R8, [R26.64+0x70] ; /* 0x000070041a087981 */
/* 0x001ea8000c1e1b00 */
/*0730*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000ea2000c1e1b00 */
/*0740*/ IADD3 R2, R2, -0x10, RZ ; /* 0xfffffff002027810 */
/* 0x000fe20007ffe0ff */
/*0750*/ DFMA R18, R20, R18, R22 ; /* 0x000000121412722b */
/* 0x0080860000000016 */
/*0760*/ ISETP.GT.AND P1, PT, R2, 0xc, PT ; /* 0x0000000c0200780c */
/* 0x000fe20003f24270 */
/*0770*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fe2000ff1e03f */
/*0780*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x000fc60007ffe0ff */
/*0790*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*07a0*/ IMAD.WIDE R22, R5, 0x8, R12 ; /* 0x0000000805167825 */
/* 0x001fe200078e020c */
/*07b0*/ DFMA R8, R10, R8, R18 ; /* 0x000000080a08722b */
/* 0x004f4c0000000012 */
/*07c0*/ DFMA R16, R16, R14, R8 ; /* 0x0000000e1010722b */
/* 0x0200620000000008 */
/*07d0*/ @P1 BRA 0x350 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*07e0*/ ISETP.GT.AND P1, PT, R2, 0x4, PT ; /* 0x000000040200780c */
/* 0x000fda0003f24270 */
/*07f0*/ @!P1 BRA 0xa80 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0800*/ MOV R26, UR6 ; /* 0x00000006001a7c02 */
/* 0x000fe20008000f00 */
/*0810*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000ea2000c1e1b00 */
/*0820*/ MOV R27, UR7 ; /* 0x00000007001b7c02 */
/* 0x000fca0008000f00 */
/*0830*/ IMAD.WIDE R26, R25, 0x8, R26 ; /* 0x00000008191a7825 */
/* 0x000fca00078e021a */
/*0840*/ LDG.E.64 R10, [R26.64] ; /* 0x000000041a0a7981 */
/* 0x000ea2000c1e1b00 */
/*0850*/ IMAD.WIDE R28, R5, 0x8, R22 ; /* 0x00000008051c7825 */
/* 0x000fc600078e0216 */
/*0860*/ LDG.E.64 R14, [R26.64+0x8] ; /* 0x000008041a0e7981 */
/* 0x001ee8000c1e1b00 */
/*0870*/ LDG.E.64 R8, [R28.64] ; /* 0x000000041c087981 */
/* 0x000ee2000c1e1b00 */
/*0880*/ IMAD.WIDE R20, R5, 0x8, R28 ; /* 0x0000000805147825 */
/* 0x000fe200078e021c */
/*0890*/ DFMA R16, R12, R10, R16 ; /* 0x0000000a0c10722b */
/* 0x0060c80000000010 */
/*08a0*/ LDG.E.64 R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x0010a8000c1e1b00 */
/*08b0*/ LDG.E.64 R10, [R26.64+0x10] ; /* 0x000010041a0a7981 */
/* 0x000ea2000c1e1b00 */
/*08c0*/ IMAD.WIDE R18, R5.reuse, 0x8, R20 ; /* 0x0000000805127825 */
/* 0x040fe200078e0214 */
/*08d0*/ DFMA R14, R8, R14, R16 ; /* 0x0000000e080e722b */
/* 0x0082a40000000010 */
/*08e0*/ LDG.E.64 R16, [R26.64+0x18] ; /* 0x000018041a107981 */
/* 0x002ee8000c1e1b00 */
/*08f0*/ LDG.E.64 R8, [R18.64] ; /* 0x0000000412087981 */
/* 0x000ee2000c1e1b00 */
/*0900*/ IMAD.WIDE R22, R5, 0x8, R18 ; /* 0x0000000805167825 */
/* 0x000fc600078e0212 */
/*0910*/ LDG.E.64 R20, [R26.64+0x38] ; /* 0x000038041a147981 */
/* 0x001f22000c1e1b00 */
/*0920*/ DFMA R10, R12, R10, R14 ; /* 0x0000000a0c0a722b */
/* 0x0040c6000000000e */
/*0930*/ LDG.E.64 R12, [R26.64+0x20] ; /* 0x000020041a0c7981 */
/* 0x001ea8000c1e1b00 */
/*0940*/ LDG.E.64 R14, [R22.64] ; /* 0x00000004160e7981 */
/* 0x0000a2000c1e1b00 */
/*0950*/ IMAD.WIDE R28, R5.reuse, 0x8, R22 ; /* 0x00000008051c7825 */
/* 0x040fe200078e0216 */
/*0960*/ DFMA R16, R8, R16, R10 ; /* 0x000000100810722b */
/* 0x0082a4000000000a */
/*0970*/ LDG.E.64 R8, [R26.64+0x28] ; /* 0x000028041a087981 */
/* 0x002ee8000c1e1b00 */
/*0980*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x0002e4000c1e1b00 */
/*0990*/ IMAD.WIDE R28, R5, 0x8, R28 ; /* 0x00000008051c7825 */
/* 0x002fcc00078e021c */
/*09a0*/ IMAD.WIDE R18, R5, 0x8, R28 ; /* 0x0000000805127825 */
/* 0x000fca00078e021c */
/*09b0*/ LDG.E.64 R22, [R18.64] ; /* 0x0000000412167981 */
/* 0x001f22000c1e1b00 */
/*09c0*/ DFMA R12, R14, R12, R16 ; /* 0x0000000c0e0c722b */
/* 0x0040c60000000010 */
/*09d0*/ LDG.E.64 R14, [R26.64+0x30] ; /* 0x000030041a0e7981 */
/* 0x001ea8000c1e1b00 */
/*09e0*/ LDG.E.64 R16, [R28.64] ; /* 0x000000041c107981 */
/* 0x000ea2000c1e1b00 */
/*09f0*/ DFMA R8, R10, R8, R12 ; /* 0x000000080a08722b */
/* 0x008ea2000000000c */
/*0a00*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0a10*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0a20*/ IADD3 R0, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fe40007ffe0ff */
/*0a30*/ IADD3 R2, R2, -0x8, RZ ; /* 0xfffffff802027810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a50*/ DFMA R16, R16, R14, R8 ; /* 0x0000000e1010722b */
/* 0x004f0c0000000008 */
/*0a60*/ DFMA R16, R22, R20, R16 ; /* 0x000000141610722b */
/* 0x0100640000000010 */
/*0a70*/ IMAD.WIDE R22, R5, 0x8, R18 ; /* 0x0000000805167825 */
/* 0x001fc800078e0212 */
/*0a80*/ ISETP.NE.OR P0, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */
/* 0x002fda0000705670 */
/*0a90*/ @!P0 BRA 0xc30 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x001fe20008000f00 */
/*0ab0*/ IMAD.U32 R8, RZ, RZ, UR6 ; /* 0x00000006ff087e24 */
/* 0x000fe2000f8e00ff */
/*0ac0*/ LDG.E.64 R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x000ea6000c1e1b00 */
/*0ad0*/ IMAD.WIDE R8, R25, 0x8, R8 ; /* 0x0000000819087825 */
/* 0x000fca00078e0208 */
/*0ae0*/ LDG.E.64 R26, [R8.64] ; /* 0x00000004081a7981 */
/* 0x000ea2000c1e1b00 */
/*0af0*/ IMAD.WIDE R14, R5, 0x8, R22 ; /* 0x00000008050e7825 */
/* 0x000fc600078e0216 */
/*0b00*/ LDG.E.64 R10, [R8.64+0x8] ; /* 0x00000804080a7981 */
/* 0x000ee8000c1e1b00 */
/*0b10*/ LDG.E.64 R12, [R14.64] ; /* 0x000000040e0c7981 */
/* 0x0000e8000c1e1b00 */
/*0b20*/ LDG.E.64 R28, [R8.64+0x18] ; /* 0x00001804081c7981 */
/* 0x000f22000c1e1b00 */
/*0b30*/ IMAD.WIDE R14, R5, 0x8, R14 ; /* 0x00000008050e7825 */
/* 0x001fca00078e020e */
/*0b40*/ LDG.E.64 R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000f62000c1e1b00 */
/*0b50*/ DFMA R26, R18, R26, R16 ; /* 0x0000001a121a722b */
/* 0x0040c60000000010 */
/*0b60*/ LDG.E.64 R16, [R8.64+0x10] ; /* 0x0000100408107981 */
/* 0x001f62000c1e1b00 */
/*0b70*/ IMAD.WIDE R18, R5, 0x8, R14 ; /* 0x0000000805127825 */
/* 0x000fca00078e020e */
/*0b80*/ LDG.E.64 R22, [R18.64] ; /* 0x0000000412167981 */
/* 0x000f22000c1e1b00 */
/*0b90*/ IADD3 R2, R2, -0x4, RZ ; /* 0xfffffffc02027810 */
/* 0x000fe20007ffe0ff */
/*0ba0*/ DFMA R10, R12, R10, R26 ; /* 0x0000000a0c0a722b */
/* 0x008f46000000001a */
/*0bb0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0bc0*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0bd0*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fc60007ffe0ff */
/*0be0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0bf0*/ DFMA R16, R20, R16, R10 ; /* 0x000000101410722b */
/* 0x020f0c000000000a */
/*0c00*/ DFMA R16, R22, R28, R16 ; /* 0x0000001c1610722b */
/* 0x0100640000000010 */
/*0c10*/ IMAD.WIDE R22, R5, 0x8, R18 ; /* 0x0000000805167825 */
/* 0x001fe200078e0212 */
/*0c20*/ @P0 BRA 0xaa0 ; /* 0xfffffe7000000947 */
/* 0x002fea000383ffff */
/*0c30*/ ISETP.NE.AND P0, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fda0003f05270 */
/*0c40*/ @!P0 BRA 0xd90 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0c50*/ IADD3 R4, R4, R0, RZ ; /* 0x0000000004047210 */
/* 0x000fe20007ffe0ff */
/*0c60*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x001fe400078e00ff */
/*0c70*/ IMAD R0, R0, c[0x0][0x178], R7 ; /* 0x00005e0000007a24 */
/* 0x000fe400078e0207 */
/*0c80*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x000fca00078e0204 */
/*0c90*/ IADD3 R2, -R7, R4, RZ ; /* 0x0000000407027210 */
/* 0x000fca0007ffe1ff */
/*0ca0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0209 */
/*0cb0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fe200078e0209 */
/*0cc0*/ MOV R0, R2 ; /* 0x0000000200007202 */
/* 0x000fe40000000f00 */
/*0cd0*/ MOV R7, R3 ; /* 0x0000000300077202 */
/* 0x000fc60000000f00 */
/*0ce0*/ IMAD.MOV.U32 R10, RZ, RZ, R0 ; /* 0x000000ffff0a7224 */
/* 0x001fe200078e0000 */
/*0cf0*/ MOV R11, R7 ; /* 0x00000007000b7202 */
/* 0x000fe20000000f00 */
/*0d00*/ LDG.E.64 R2, [R8.64] ; /* 0x0000000408027981 */
/* 0x0000aa000c1e1b00 */
/*0d10*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1b00 */
/*0d20*/ IADD3 R24, R24, -0x1, RZ ; /* 0xffffffff18187810 */
/* 0x000fc40007ffe0ff */
/*0d30*/ IADD3 R0, P1, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fe40007f3e0ff */
/*0d40*/ ISETP.NE.AND P0, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fe20003f05270 */
/*0d50*/ IMAD.WIDE R8, R5, 0x8, R8 ; /* 0x0000000805087825 */
/* 0x001fe200078e0208 */
/*0d60*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0d70*/ DFMA R16, R2, R10, R16 ; /* 0x0000000a0210722b */
/* 0x0060540000000010 */
/*0d80*/ @P0 BRA 0xce0 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0d90*/ MOV R7, 0x8 ; /* 0x0000000800077802 */
/* 0x000fca0000000f00 */
/*0da0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fca00078e0207 */
/*0db0*/ STG.E.64 [R6.64], R16 ; /* 0x0000001006007986 */
/* 0x002fe2000c101b04 */
/*0dc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0dd0*/ BRA 0xdd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPdS_S_i
.globl _Z6VecAddPdS_S_i
.p2align 8
.type _Z6VecAddPdS_S_i,@function
_Z6VecAddPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mul_i32 s3, s2, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_6
s_ashr_i32 s3, s2, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s4, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s4, s4, s3
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s5, 0, s4
s_cmp_lt_i32 s2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v2, v0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v7, v0, v3
v_mul_lo_u32 v2, v7, s2
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v1, v2
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[3:4], 3, v[2:3]
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[8:9], 3, v[5:6]
v_add_nc_u32_e32 v5, s2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
global_load_b64 v[10:11], v[3:4], off
global_load_b64 v[8:9], v[8:9], off
v_add_co_u32 v3, vcc_lo, v3, 8
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[1:2], v[10:11], v[8:9], v[1:2]
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v7, s2, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b64 v[3:4], v[1:2], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPdS_S_i, .Lfunc_end0-_Z6VecAddPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6VecAddPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008644c_00000000-6_matmult-cuda-double.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6VecAddPdS_S_iPdS_S_i
.type _Z30__device_stub__Z6VecAddPdS_S_iPdS_S_i, @function
_Z30__device_stub__Z6VecAddPdS_S_iPdS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z6VecAddPdS_S_iPdS_S_i, .-_Z30__device_stub__Z6VecAddPdS_S_iPdS_S_i
.globl _Z6VecAddPdS_S_i
.type _Z6VecAddPdS_S_i, @function
_Z6VecAddPdS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6VecAddPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6VecAddPdS_S_i, .-_Z6VecAddPdS_S_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $50000000, %edi
call malloc@PLT
movq %rax, %r13
movq %rax, 8(%rsp)
movl $50000000, %edi
call malloc@PLT
movq %rax, %r12
movq %rax, 16(%rsp)
movl $50000000, %edi
call malloc@PLT
movq %rax, 24(%rsp)
leaq 40(%rsp), %rdi
movl $50000000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $50000000, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $50000000, %esi
call cudaMalloc@PLT
movl $0, %r15d
movl $11, %r14d
.L12:
movl %r14d, %ebp
movl $0, %ebx
.L13:
call rand@PLT
cltd
idivl %ebp
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
mulsd .LC0(%rip), %xmm0
movsd %xmm0, 0(%r13,%rbx)
call rand@PLT
cltd
idivl %ebp
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
mulsd .LC0(%rip), %xmm0
movsd %xmm0, (%r12,%rbx)
addq $8, %rbx
cmpq $20000, %rbx
jne .L13
addl $11, %r14d
addl $2500, %r15d
addq $20000, %r13
addq $20000, %r12
cmpl $6250000, %r15d
jne .L12
movl $1, %ecx
movl $50000000, %edx
movq 8(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $50000000, %edx
movq 16(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 76(%rsp)
movl $1, 80(%rsp)
movl $6104, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movl $2, %ecx
movl $50000000, %edx
movq 56(%rsp), %rsi
movq 24(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $2500, %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z30__device_stub__Z6VecAddPdS_S_iPdS_S_i
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z6VecAddPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 515396076
.long 1072819077
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matmult-cuda-double.hip"
.globl _Z21__device_stub__VecAddPdS_S_i # -- Begin function _Z21__device_stub__VecAddPdS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPdS_S_i,@function
_Z21__device_stub__VecAddPdS_S_i: # @_Z21__device_stub__VecAddPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPdS_S_i, .Lfunc_end0-_Z21__device_stub__VecAddPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3ff1eb851eb851ec # double 1.1200000000000001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $50000000, %edi # imm = 0x2FAF080
callq malloc
movq %rax, %r13
movl $50000000, %edi # imm = 0x2FAF080
callq malloc
movq %rax, %rbp
movl $50000000, %edi # imm = 0x2FAF080
callq malloc
movq %rax, 40(%rsp) # 8-byte Spill
leaq 24(%rsp), %rdi
movl $50000000, %esi # imm = 0x2FAF080
callq hipMalloc
leaq 16(%rsp), %rdi
movl $50000000, %esi # imm = 0x2FAF080
callq hipMalloc
leaq 8(%rsp), %rdi
movl $50000000, %esi # imm = 0x2FAF080
callq hipMalloc
xorl %r12d, %r12d
movq %r13, %r14
movq %rbp, 48(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
leal (%r12,%r12,4), %eax
leal (%r12,%rax,2), %r15d
addl $11, %r15d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltd
idivl %r15d
xorps %xmm0, %xmm0
cvtsi2sd %edx, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, (%r13,%rbx,8)
callq rand
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
cltd
idivl %r15d
xorps %xmm0, %xmm0
cvtsi2sd %edx, %xmm0
mulsd %xmm1, %xmm0
movsd %xmm0, (%rbp,%rbx,8)
incq %rbx
cmpq $2500, %rbx # imm = 0x9C4
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r12
addq $20000, %rbp # imm = 0x4E20
addq $20000, %r13 # imm = 0x4E20
cmpq $2500, %r12 # imm = 0x9C4
jne .LBB1_1
# %bb.4:
movq 24(%rsp), %rdi
movl $50000000, %edx # imm = 0x2FAF080
movq %r14, %rbx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $50000000, %edx # imm = 0x2FAF080
movq 48(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 5080(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $2500, 36(%rsp) # imm = 0x9C4
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z6VecAddPdS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movl $50000000, %edx # imm = 0x2FAF080
movq 40(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPdS_S_i,@object # @_Z6VecAddPdS_S_i
.section .rodata,"a",@progbits
.globl _Z6VecAddPdS_S_i
.p2align 3, 0x0
_Z6VecAddPdS_S_i:
.quad _Z21__device_stub__VecAddPdS_S_i
.size _Z6VecAddPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6VecAddPdS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
__global__ void saxpy(unsigned num_streams, unsigned addr, int n, float *x)
{
__shared__ float A[1000];
int id = blockIdx.x*blockDim.x + threadIdx.x;
float a = 0, b = 0, c = 0, d = 0, e = 0, f = 0, g = 0, h = 0;
if (id == 0) {
for (int i = 0 ; i < 1000 ; i += 8) {
a = A[i];
b = A[i + 1];
c = A[i + 2];
d = A[i + 3];
e = A[i + 4];
f = A[i + 5];
g = A[i + 6];
h = A[i + 7];
}
*x = a + b + c + d + e + f + g + h;
}
}
int main(void)
{
int N = 1000;
// Perform SAXPY on 1M elements
float *h_x = (float *)malloc(N*sizeof(float));
float *d_x = (float *)100;
float *d_x_copy;
cudaMalloc(&d_x_copy, N*sizeof(float));
// cudaMalloc(&d_x, 2*sizeof(float));
for (int i = 1 ; i <= N ; i++)
h_x[i-1] = (float)i;
cudaMemcpy(d_x, h_x, N*sizeof(float), cudaMemcpyHostToDevice);
float *h_dummy = (float *)malloc(sizeof(float));
float *d_dummy;
cudaMalloc(&d_dummy, sizeof(float));
saxpy<<<1, 8>>>(1, 100u, N, d_dummy);
cudaMemcpy(h_dummy, d_dummy, sizeof(float), cudaMemcpyDeviceToHost);
printf("%f\n", *h_dummy);
} | code for sm_80
Function : _Z5saxpyjjiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
__global__ void saxpy(unsigned num_streams, unsigned addr, int n, float *x)
{
__shared__ float A[1000];
int id = blockIdx.x*blockDim.x + threadIdx.x;
float a = 0, b = 0, c = 0, d = 0, e = 0, f = 0, g = 0, h = 0;
if (id == 0) {
for (int i = 0 ; i < 1000 ; i += 8) {
a = A[i];
b = A[i + 1];
c = A[i + 2];
d = A[i + 3];
e = A[i + 4];
f = A[i + 5];
g = A[i + 6];
h = A[i + 7];
}
*x = a + b + c + d + e + f + g + h;
}
}
int main(void)
{
int N = 1000;
// Perform SAXPY on 1M elements
float *h_x = (float *)malloc(N*sizeof(float));
float *d_x = (float *)100;
float *d_x_copy;
cudaMalloc(&d_x_copy, N*sizeof(float));
// cudaMalloc(&d_x, 2*sizeof(float));
for (int i = 1 ; i <= N ; i++)
h_x[i-1] = (float)i;
cudaMemcpy(d_x, h_x, N*sizeof(float), cudaMemcpyHostToDevice);
float *h_dummy = (float *)malloc(sizeof(float));
float *d_dummy;
cudaMalloc(&d_dummy, sizeof(float));
saxpy<<<1, 8>>>(1, 100u, N, d_dummy);
cudaMemcpy(h_dummy, d_dummy, sizeof(float), cudaMemcpyDeviceToHost);
printf("%f\n", *h_dummy);
} | .file "tmpxft_00074336_00000000-6_kernel_params.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z5saxpyjjiPfjjiPf
.type _Z27__device_stub__Z5saxpyjjiPfjjiPf, @function
_Z27__device_stub__Z5saxpyjjiPfjjiPf:
.LFB2095:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyjjiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z27__device_stub__Z5saxpyjjiPfjjiPf, .-_Z27__device_stub__Z5saxpyjjiPfjjiPf
.globl _Z5saxpyjjiPf
.type _Z5saxpyjjiPf, @function
_Z5saxpyjjiPf:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5saxpyjjiPfjjiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z5saxpyjjiPf, .-_Z5saxpyjjiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4000, %edi
call malloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $4000, %esi
call cudaMalloc@PLT
movl $1, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -4(%rbx,%rax,4)
addq $1, %rax
cmpq $1001, %rax
jne .L12
movl $1, %ecx
movl $4000, %edx
movq %rbx, %rsi
movl $100, %edi
call cudaMemcpy@PLT
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $8, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rcx
movl $1000, %edx
movl $100, %esi
movl $1, %edi
call _Z27__device_stub__Z5saxpyjjiPfjjiPf
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z5saxpyjjiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyjjiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
__global__ void saxpy(unsigned num_streams, unsigned addr, int n, float *x)
{
__shared__ float A[1000];
int id = blockIdx.x*blockDim.x + threadIdx.x;
float a = 0, b = 0, c = 0, d = 0, e = 0, f = 0, g = 0, h = 0;
if (id == 0) {
for (int i = 0 ; i < 1000 ; i += 8) {
a = A[i];
b = A[i + 1];
c = A[i + 2];
d = A[i + 3];
e = A[i + 4];
f = A[i + 5];
g = A[i + 6];
h = A[i + 7];
}
*x = a + b + c + d + e + f + g + h;
}
}
int main(void)
{
int N = 1000;
// Perform SAXPY on 1M elements
float *h_x = (float *)malloc(N*sizeof(float));
float *d_x = (float *)100;
float *d_x_copy;
cudaMalloc(&d_x_copy, N*sizeof(float));
// cudaMalloc(&d_x, 2*sizeof(float));
for (int i = 1 ; i <= N ; i++)
h_x[i-1] = (float)i;
cudaMemcpy(d_x, h_x, N*sizeof(float), cudaMemcpyHostToDevice);
float *h_dummy = (float *)malloc(sizeof(float));
float *d_dummy;
cudaMalloc(&d_dummy, sizeof(float));
saxpy<<<1, 8>>>(1, 100u, N, d_dummy);
cudaMemcpy(h_dummy, d_dummy, sizeof(float), cudaMemcpyDeviceToHost);
printf("%f\n", *h_dummy);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
__global__ void saxpy(unsigned num_streams, unsigned addr, int n, float *x)
{
__shared__ float A[1000];
int id = blockIdx.x*blockDim.x + threadIdx.x;
float a = 0, b = 0, c = 0, d = 0, e = 0, f = 0, g = 0, h = 0;
if (id == 0) {
for (int i = 0 ; i < 1000 ; i += 8) {
a = A[i];
b = A[i + 1];
c = A[i + 2];
d = A[i + 3];
e = A[i + 4];
f = A[i + 5];
g = A[i + 6];
h = A[i + 7];
}
*x = a + b + c + d + e + f + g + h;
}
}
int main(void)
{
int N = 1000;
// Perform SAXPY on 1M elements
float *h_x = (float *)malloc(N*sizeof(float));
float *d_x = (float *)100;
float *d_x_copy;
hipMalloc(&d_x_copy, N*sizeof(float));
// cudaMalloc(&d_x, 2*sizeof(float));
for (int i = 1 ; i <= N ; i++)
h_x[i-1] = (float)i;
hipMemcpy(d_x, h_x, N*sizeof(float), hipMemcpyHostToDevice);
float *h_dummy = (float *)malloc(sizeof(float));
float *d_dummy;
hipMalloc(&d_dummy, sizeof(float));
saxpy<<<1, 8>>>(1, 100u, N, d_dummy);
hipMemcpy(h_dummy, d_dummy, sizeof(float), hipMemcpyDeviceToHost);
printf("%f\n", *h_dummy);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
__global__ void saxpy(unsigned num_streams, unsigned addr, int n, float *x)
{
__shared__ float A[1000];
int id = blockIdx.x*blockDim.x + threadIdx.x;
float a = 0, b = 0, c = 0, d = 0, e = 0, f = 0, g = 0, h = 0;
if (id == 0) {
for (int i = 0 ; i < 1000 ; i += 8) {
a = A[i];
b = A[i + 1];
c = A[i + 2];
d = A[i + 3];
e = A[i + 4];
f = A[i + 5];
g = A[i + 6];
h = A[i + 7];
}
*x = a + b + c + d + e + f + g + h;
}
}
int main(void)
{
int N = 1000;
// Perform SAXPY on 1M elements
float *h_x = (float *)malloc(N*sizeof(float));
float *d_x = (float *)100;
float *d_x_copy;
hipMalloc(&d_x_copy, N*sizeof(float));
// cudaMalloc(&d_x, 2*sizeof(float));
for (int i = 1 ; i <= N ; i++)
h_x[i-1] = (float)i;
hipMemcpy(d_x, h_x, N*sizeof(float), hipMemcpyHostToDevice);
float *h_dummy = (float *)malloc(sizeof(float));
float *d_dummy;
hipMalloc(&d_dummy, sizeof(float));
saxpy<<<1, 8>>>(1, 100u, N, d_dummy);
hipMemcpy(h_dummy, d_dummy, sizeof(float), hipMemcpyDeviceToHost);
printf("%f\n", *h_dummy);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyjjiPf
.globl _Z5saxpyjjiPf
.p2align 8
.type _Z5saxpyjjiPf,@function
_Z5saxpyjjiPf:
s_load_b32 s2, s[0:1], 0x24
v_sub_nc_u32_e32 v0, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e64 s15, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v0, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyjjiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyjjiPf, .Lfunc_end0-_Z5saxpyjjiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyjjiPf
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z5saxpyjjiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 1
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
__global__ void saxpy(unsigned num_streams, unsigned addr, int n, float *x)
{
__shared__ float A[1000];
int id = blockIdx.x*blockDim.x + threadIdx.x;
float a = 0, b = 0, c = 0, d = 0, e = 0, f = 0, g = 0, h = 0;
if (id == 0) {
for (int i = 0 ; i < 1000 ; i += 8) {
a = A[i];
b = A[i + 1];
c = A[i + 2];
d = A[i + 3];
e = A[i + 4];
f = A[i + 5];
g = A[i + 6];
h = A[i + 7];
}
*x = a + b + c + d + e + f + g + h;
}
}
int main(void)
{
int N = 1000;
// Perform SAXPY on 1M elements
float *h_x = (float *)malloc(N*sizeof(float));
float *d_x = (float *)100;
float *d_x_copy;
hipMalloc(&d_x_copy, N*sizeof(float));
// cudaMalloc(&d_x, 2*sizeof(float));
for (int i = 1 ; i <= N ; i++)
h_x[i-1] = (float)i;
hipMemcpy(d_x, h_x, N*sizeof(float), hipMemcpyHostToDevice);
float *h_dummy = (float *)malloc(sizeof(float));
float *d_dummy;
hipMalloc(&d_dummy, sizeof(float));
saxpy<<<1, 8>>>(1, 100u, N, d_dummy);
hipMemcpy(h_dummy, d_dummy, sizeof(float), hipMemcpyDeviceToHost);
printf("%f\n", *h_dummy);
} | .text
.file "kernel_params.hip"
.globl _Z20__device_stub__saxpyjjiPf # -- Begin function _Z20__device_stub__saxpyjjiPf
.p2align 4, 0x90
.type _Z20__device_stub__saxpyjjiPf,@function
_Z20__device_stub__saxpyjjiPf: # @_Z20__device_stub__saxpyjjiPf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyjjiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyjjiPf, .Lfunc_end0-_Z20__device_stub__saxpyjjiPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
movl $4000, %edi # imm = 0xFA0
callq malloc
movq %rax, %rbx
leaq 120(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rax,4)
movq %rcx, %rax
cmpq $1000, %rcx # imm = 0x3E8
jne .LBB1_1
# %bb.2:
movl $100, %edi
movl $4000, %edx # imm = 0xFA0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $4, %edi
callq malloc
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 7(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movl $1, 12(%rsp)
movl $100, 8(%rsp)
movl $1000, 4(%rsp) # imm = 0x3E8
movq %rax, 72(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyjjiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyjjiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyjjiPf,@object # @_Z5saxpyjjiPf
.section .rodata,"a",@progbits
.globl _Z5saxpyjjiPf
.p2align 3, 0x0
_Z5saxpyjjiPf:
.quad _Z20__device_stub__saxpyjjiPf
.size _Z5saxpyjjiPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5saxpyjjiPf"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyjjiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyjjiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5saxpyjjiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyjjiPf
.globl _Z5saxpyjjiPf
.p2align 8
.type _Z5saxpyjjiPf,@function
_Z5saxpyjjiPf:
s_load_b32 s2, s[0:1], 0x24
v_sub_nc_u32_e32 v0, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e64 s15, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v0, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyjjiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyjjiPf, .Lfunc_end0-_Z5saxpyjjiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyjjiPf
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z5saxpyjjiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 1
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00074336_00000000-6_kernel_params.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z5saxpyjjiPfjjiPf
.type _Z27__device_stub__Z5saxpyjjiPfjjiPf, @function
_Z27__device_stub__Z5saxpyjjiPfjjiPf:
.LFB2095:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyjjiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z27__device_stub__Z5saxpyjjiPfjjiPf, .-_Z27__device_stub__Z5saxpyjjiPfjjiPf
.globl _Z5saxpyjjiPf
.type _Z5saxpyjjiPf, @function
_Z5saxpyjjiPf:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5saxpyjjiPfjjiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z5saxpyjjiPf, .-_Z5saxpyjjiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4000, %edi
call malloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $4000, %esi
call cudaMalloc@PLT
movl $1, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -4(%rbx,%rax,4)
addq $1, %rax
cmpq $1001, %rax
jne .L12
movl $1, %ecx
movl $4000, %edx
movq %rbx, %rsi
movl $100, %edi
call cudaMemcpy@PLT
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $8, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rcx
movl $1000, %edx
movl $100, %esi
movl $1, %edi
call _Z27__device_stub__Z5saxpyjjiPfjjiPf
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z5saxpyjjiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyjjiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_params.hip"
.globl _Z20__device_stub__saxpyjjiPf # -- Begin function _Z20__device_stub__saxpyjjiPf
.p2align 4, 0x90
.type _Z20__device_stub__saxpyjjiPf,@function
_Z20__device_stub__saxpyjjiPf: # @_Z20__device_stub__saxpyjjiPf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyjjiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyjjiPf, .Lfunc_end0-_Z20__device_stub__saxpyjjiPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
movl $4000, %edi # imm = 0xFA0
callq malloc
movq %rax, %rbx
leaq 120(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rax,4)
movq %rcx, %rax
cmpq $1000, %rcx # imm = 0x3E8
jne .LBB1_1
# %bb.2:
movl $100, %edi
movl $4000, %edx # imm = 0xFA0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $4, %edi
callq malloc
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 7(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movl $1, 12(%rsp)
movl $100, 8(%rsp)
movl $1000, 4(%rsp) # imm = 0x3E8
movq %rax, 72(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyjjiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyjjiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyjjiPf,@object # @_Z5saxpyjjiPf
.section .rodata,"a",@progbits
.globl _Z5saxpyjjiPf
.p2align 3, 0x0
_Z5saxpyjjiPf:
.quad _Z20__device_stub__saxpyjjiPf
.size _Z5saxpyjjiPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5saxpyjjiPf"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyjjiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyjjiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
{
__global__ void vabs(const int n, const double *a, double *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{b[i]=fabs(a[i]);}
}
} | code for sm_80
Function : vabs
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ DADD R6, -RZ, |R2| ; /* 0x00000000ff067229 */
/* 0x004e0e0000000502 */
/*00c0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe2000c101b04 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
{
__global__ void vabs(const int n, const double *a, double *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{b[i]=fabs(a[i]);}
}
} | .file "tmpxft_00128cee_00000000-6_vabs.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z4vabsiPKdPdiPKdPd
.type _Z27__device_stub__Z4vabsiPKdPdiPKdPd, @function
_Z27__device_stub__Z4vabsiPKdPdiPKdPd:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq vabs(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z4vabsiPKdPdiPKdPd, .-_Z27__device_stub__Z4vabsiPKdPdiPKdPd
.globl vabs
.type vabs, @function
vabs:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z4vabsiPKdPdiPKdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size vabs, .-vabs
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "vabs"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq vabs(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
{
__global__ void vabs(const int n, const double *a, double *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{b[i]=fabs(a[i]);}
}
} | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void vabs(const int n, const double *a, double *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{b[i]=fabs(a[i]);}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void vabs(const int n, const double *a, double *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{b[i]=fabs(a[i]);}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected vabs
.globl vabs
.p2align 8
.type vabs,@function
vabs:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v3, 0x7fffffff, v3
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel vabs
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size vabs, .Lfunc_end0-vabs
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: vabs
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: vabs.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void vabs(const int n, const double *a, double *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{b[i]=fabs(a[i]);}
}
} | .text
.file "vabs.hip"
.globl __device_stub__vabs # -- Begin function __device_stub__vabs
.p2align 4, 0x90
.type __device_stub__vabs,@function
__device_stub__vabs: # @__device_stub__vabs
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $vabs, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__vabs, .Lfunc_end0-__device_stub__vabs
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $vabs, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type vabs,@object # @vabs
.section .rodata,"a",@progbits
.globl vabs
.p2align 3, 0x0
vabs:
.quad __device_stub__vabs
.size vabs, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "vabs"
.size .L__unnamed_1, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__vabs
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym vabs
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : vabs
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ DADD R6, -RZ, |R2| ; /* 0x00000000ff067229 */
/* 0x004e0e0000000502 */
/*00c0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe2000c101b04 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected vabs
.globl vabs
.p2align 8
.type vabs,@function
vabs:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v3, 0x7fffffff, v3
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel vabs
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size vabs, .Lfunc_end0-vabs
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: vabs
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: vabs.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00128cee_00000000-6_vabs.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z4vabsiPKdPdiPKdPd
.type _Z27__device_stub__Z4vabsiPKdPdiPKdPd, @function
_Z27__device_stub__Z4vabsiPKdPdiPKdPd:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq vabs(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z4vabsiPKdPdiPKdPd, .-_Z27__device_stub__Z4vabsiPKdPdiPKdPd
.globl vabs
.type vabs, @function
vabs:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z4vabsiPKdPdiPKdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size vabs, .-vabs
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "vabs"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq vabs(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vabs.hip"
.globl __device_stub__vabs # -- Begin function __device_stub__vabs
.p2align 4, 0x90
.type __device_stub__vabs,@function
__device_stub__vabs: # @__device_stub__vabs
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $vabs, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__vabs, .Lfunc_end0-__device_stub__vabs
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $vabs, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type vabs,@object # @vabs
.section .rodata,"a",@progbits
.globl vabs
.p2align 3, 0x0
vabs:
.quad __device_stub__vabs
.size vabs, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "vabs"
.size .L__unnamed_1, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__vabs
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym vabs
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Copyright 2015 Thomas Luu
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
File: plog.cu
Computation of the Lambert W-function by Halley's Method.
Single and double precision implementations.
Initial guesses based on:
D.A. Barry, J.-Y. Parlange, L. Li, H. Prommer, C.J. Cunningham, and
F. Stagnitti. Analytical approximations for real values of the Lambert
W-function. Mathematics and Computers in Simulation, 53(1):95-103, 2000.
D.A. Barry, J.-Y. Parlange, L. Li, H. Prommer, C.J. Cunningham, and
F. Stagnitti. Erratum to analytical approximations for real values of the
Lambert W-function. Mathematics and computers in simulation, 59(6):543-543,
2002.
*/
#ifndef PLOG
#define PLOG
__host__ __device__ double plog(double x)
{
if (x == 0.0) {
return 0.0;
}
double w0, w1;
if (x > 0.0) {
w0 = log(1.2 * x / log(2.4 * x / log1p(2.4 * x)));
} else {
double v = 1.4142135623730950488 * sqrt(1 + 2.7182818284590452354 * x);
double N2 = 10.242640687119285146 + 1.9797586132081854940 * v;
double N1 = 0.29289321881345247560 * (1.4142135623730950488 + N2);
w0 = -1.0 + v * (N2 + v) / (N2 + v + N1 * v);
}
while (true) {
double e = exp(w0);
double f = w0 * e - x;
w1 = w0 + ((f+f) * (1.0 + w0)) / (f * (2.0 + w0) - (e+e) * (1.0 + w0) * (1.0 + w0));
if (fabs(w0 / w1 - 1.0) < 1.4901161193847656e-8) {
break;
}
w0 = w1;
}
return w1;
}
__host__ __device__ float plog(float x)
{
if (x == 0.0f) {
return 0.0f;
}
float w0, w1;
if (x > 0.0f) {
w0 = log(1.2f * x / log(2.4f * x / log1p(2.4f * x)));
} else {
float v = 1.4142135623730950488f * sqrt(1 + 2.7182818284590452354f * x);
float N2 = 10.242640687119285146f + 1.9797586132081854940f * v;
float N1 = 0.29289321881345247560f * (1.4142135623730950488f + N2);
w0 = -1.0f + v * (N2 + v) / (N2 + v + N1 * v);
}
while (true) {
float e = exp(w0);
float f = w0 * e - x;
w1 = w0 + ((f+f) * (1.0f + w0)) / (f * (2.0f + w0) - (e+e) * (1.0f + w0) * (1.0f + w0));
if (fabs(w0 / w1 - 1.0f) < 0.00034526698300124390840f) {
break;
}
w0 = w1;
}
return w1;
}
#endif | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Copyright 2015 Thomas Luu
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
File: plog.cu
Computation of the Lambert W-function by Halley's Method.
Single and double precision implementations.
Initial guesses based on:
D.A. Barry, J.-Y. Parlange, L. Li, H. Prommer, C.J. Cunningham, and
F. Stagnitti. Analytical approximations for real values of the Lambert
W-function. Mathematics and Computers in Simulation, 53(1):95-103, 2000.
D.A. Barry, J.-Y. Parlange, L. Li, H. Prommer, C.J. Cunningham, and
F. Stagnitti. Erratum to analytical approximations for real values of the
Lambert W-function. Mathematics and computers in simulation, 59(6):543-543,
2002.
*/
#ifndef PLOG
#define PLOG
__host__ __device__ double plog(double x)
{
if (x == 0.0) {
return 0.0;
}
double w0, w1;
if (x > 0.0) {
w0 = log(1.2 * x / log(2.4 * x / log1p(2.4 * x)));
} else {
double v = 1.4142135623730950488 * sqrt(1 + 2.7182818284590452354 * x);
double N2 = 10.242640687119285146 + 1.9797586132081854940 * v;
double N1 = 0.29289321881345247560 * (1.4142135623730950488 + N2);
w0 = -1.0 + v * (N2 + v) / (N2 + v + N1 * v);
}
while (true) {
double e = exp(w0);
double f = w0 * e - x;
w1 = w0 + ((f+f) * (1.0 + w0)) / (f * (2.0 + w0) - (e+e) * (1.0 + w0) * (1.0 + w0));
if (fabs(w0 / w1 - 1.0) < 1.4901161193847656e-8) {
break;
}
w0 = w1;
}
return w1;
}
__host__ __device__ float plog(float x)
{
if (x == 0.0f) {
return 0.0f;
}
float w0, w1;
if (x > 0.0f) {
w0 = log(1.2f * x / log(2.4f * x / log1p(2.4f * x)));
} else {
float v = 1.4142135623730950488f * sqrt(1 + 2.7182818284590452354f * x);
float N2 = 10.242640687119285146f + 1.9797586132081854940f * v;
float N1 = 0.29289321881345247560f * (1.4142135623730950488f + N2);
w0 = -1.0f + v * (N2 + v) / (N2 + v + N1 * v);
}
while (true) {
float e = exp(w0);
float f = w0 * e - x;
w1 = w0 + ((f+f) * (1.0f + w0)) / (f * (2.0f + w0) - (e+e) * (1.0f + w0) * (1.0f + w0));
if (fabs(w0 / w1 - 1.0f) < 0.00034526698300124390840f) {
break;
}
w0 = w1;
}
return w1;
}
#endif | .file "tmpxft_0008ebf7_00000000-6_plog.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4plogd
.type _Z4plogd, @function
_Z4plogd:
.LFB2027:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movapd %xmm0, %xmm7
movsd %xmm0, 8(%rsp)
pxor %xmm0, %xmm0
ucomisd %xmm0, %xmm7
jp .L15
movsd %xmm0, (%rsp)
je .L3
.L15:
pxor %xmm0, %xmm0
movsd 8(%rsp), %xmm7
comisd %xmm0, %xmm7
jbe .L18
movapd %xmm7, %xmm5
mulsd .LC1(%rip), %xmm5
movapd %xmm5, %xmm0
movq %xmm5, %rbx
call log1p@PLT
movapd %xmm0, %xmm1
movq %rbx, %xmm0
divsd %xmm1, %xmm0
call log@PLT
movapd %xmm0, %xmm1
movsd 8(%rsp), %xmm0
mulsd .LC2(%rip), %xmm0
divsd %xmm1, %xmm0
call log@PLT
movsd %xmm0, (%rsp)
.L12:
movsd (%rsp), %xmm0
call exp@PLT
movsd (%rsp), %xmm6
movapd %xmm6, %xmm4
mulsd %xmm0, %xmm4
subsd 8(%rsp), %xmm4
movsd .LC4(%rip), %xmm5
addsd %xmm6, %xmm5
movapd %xmm6, %xmm1
movapd %xmm4, %xmm2
addsd %xmm4, %xmm2
mulsd %xmm5, %xmm2
movsd .LC9(%rip), %xmm3
addsd %xmm6, %xmm3
mulsd %xmm4, %xmm3
addsd %xmm0, %xmm0
mulsd %xmm5, %xmm0
mulsd %xmm5, %xmm0
subsd %xmm0, %xmm3
divsd %xmm3, %xmm2
movapd %xmm2, %xmm0
addsd %xmm6, %xmm0
movsd %xmm0, (%rsp)
divsd %xmm0, %xmm1
subsd .LC4(%rip), %xmm1
andpd .LC10(%rip), %xmm1
movsd .LC11(%rip), %xmm7
comisd %xmm1, %xmm7
jbe .L12
.L3:
movsd (%rsp), %xmm0
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movsd 8(%rsp), %xmm0
mulsd .LC3(%rip), %xmm0
addsd .LC4(%rip), %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L19
sqrtsd %xmm0, %xmm0
.L11:
movsd .LC5(%rip), %xmm4
mulsd %xmm4, %xmm0
movapd %xmm0, %xmm1
mulsd .LC6(%rip), %xmm1
addsd .LC7(%rip), %xmm1
movapd %xmm0, %xmm3
addsd %xmm1, %xmm3
movapd %xmm3, %xmm2
mulsd %xmm0, %xmm2
addsd %xmm4, %xmm1
mulsd .LC8(%rip), %xmm1
mulsd %xmm0, %xmm1
addsd %xmm3, %xmm1
divsd %xmm1, %xmm2
subsd .LC4(%rip), %xmm2
movsd %xmm2, (%rsp)
jmp .L12
.L19:
call sqrt@PLT
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z4plogd, .-_Z4plogd
.globl _Z4plogf
.type _Z4plogf, @function
_Z4plogf:
.LFB2028:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movaps %xmm0, %xmm7
movss %xmm0, 12(%rsp)
pxor %xmm0, %xmm0
ucomiss %xmm0, %xmm7
jp .L33
movss %xmm0, 8(%rsp)
je .L21
.L33:
pxor %xmm0, %xmm0
movss 12(%rsp), %xmm7
comiss %xmm0, %xmm7
jbe .L36
movaps %xmm7, %xmm5
mulss .LC13(%rip), %xmm5
movaps %xmm5, %xmm0
movd %xmm5, %ebx
call log1pf@PLT
movaps %xmm0, %xmm1
movd %ebx, %xmm0
divss %xmm1, %xmm0
call logf@PLT
movaps %xmm0, %xmm1
movss 12(%rsp), %xmm0
mulss .LC14(%rip), %xmm0
divss %xmm1, %xmm0
call logf@PLT
movss %xmm0, 8(%rsp)
.L30:
movss 8(%rsp), %xmm0
call expf@PLT
movss 8(%rsp), %xmm6
movaps %xmm6, %xmm4
mulss %xmm0, %xmm4
subss 12(%rsp), %xmm4
movss .LC16(%rip), %xmm5
addss %xmm6, %xmm5
movaps %xmm6, %xmm1
movaps %xmm4, %xmm2
addss %xmm4, %xmm2
mulss %xmm5, %xmm2
movss .LC21(%rip), %xmm3
addss %xmm6, %xmm3
mulss %xmm4, %xmm3
addss %xmm0, %xmm0
mulss %xmm5, %xmm0
mulss %xmm5, %xmm0
subss %xmm0, %xmm3
divss %xmm3, %xmm2
movaps %xmm2, %xmm0
addss %xmm6, %xmm0
movss %xmm0, 8(%rsp)
divss %xmm0, %xmm1
subss .LC16(%rip), %xmm1
andps .LC22(%rip), %xmm1
movss .LC23(%rip), %xmm7
comiss %xmm1, %xmm7
jbe .L30
.L21:
movss 8(%rsp), %xmm0
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movss 12(%rsp), %xmm0
mulss .LC15(%rip), %xmm0
addss .LC16(%rip), %xmm0
pxor %xmm1, %xmm1
ucomiss %xmm0, %xmm1
ja .L37
sqrtss %xmm0, %xmm0
.L29:
movss .LC17(%rip), %xmm4
mulss %xmm4, %xmm0
movaps %xmm0, %xmm1
mulss .LC18(%rip), %xmm1
addss .LC19(%rip), %xmm1
movaps %xmm0, %xmm3
addss %xmm1, %xmm3
movaps %xmm3, %xmm2
mulss %xmm0, %xmm2
addss %xmm4, %xmm1
mulss .LC20(%rip), %xmm1
mulss %xmm0, %xmm1
addss %xmm3, %xmm1
divss %xmm1, %xmm2
subss .LC16(%rip), %xmm2
movss %xmm2, 8(%rsp)
jmp .L30
.L37:
call sqrtf@PLT
jmp .L29
.cfi_endproc
.LFE2028:
.size _Z4plogf, .-_Z4plogf
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 858993459
.long 1073951539
.align 8
.LC2:
.long 858993459
.long 1072902963
.align 8
.LC3:
.long -1961601175
.long 1074118410
.align 8
.LC4:
.long 0
.long 1072693248
.align 8
.LC5:
.long 1719614413
.long 1073127582
.align 8
.LC6:
.long 1578844522
.long 1073720599
.align 8
.LC7:
.long 1718597229
.long 1076132923
.align 8
.LC8:
.long 855738471
.long 1070776003
.align 8
.LC9:
.long 0
.long 1073741824
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC10:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC11:
.long 0
.long 1045430272
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC13:
.long 1075419546
.align 4
.LC14:
.long 1067030938
.align 4
.LC15:
.long 1076754516
.align 4
.LC16:
.long 1065353216
.align 4
.LC17:
.long 1068827891
.align 4
.LC18:
.long 1073572027
.align 4
.LC19:
.long 1092870619
.align 4
.LC20:
.long 1050015258
.set .LC21,.LC9+4
.section .rodata.cst16
.align 16
.LC22:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4
.align 4
.LC23:
.long 968164595
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Copyright 2015 Thomas Luu
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
File: plog.cu
Computation of the Lambert W-function by Halley's Method.
Single and double precision implementations.
Initial guesses based on:
D.A. Barry, J.-Y. Parlange, L. Li, H. Prommer, C.J. Cunningham, and
F. Stagnitti. Analytical approximations for real values of the Lambert
W-function. Mathematics and Computers in Simulation, 53(1):95-103, 2000.
D.A. Barry, J.-Y. Parlange, L. Li, H. Prommer, C.J. Cunningham, and
F. Stagnitti. Erratum to analytical approximations for real values of the
Lambert W-function. Mathematics and computers in simulation, 59(6):543-543,
2002.
*/
#ifndef PLOG
#define PLOG
__host__ __device__ double plog(double x)
{
if (x == 0.0) {
return 0.0;
}
double w0, w1;
if (x > 0.0) {
w0 = log(1.2 * x / log(2.4 * x / log1p(2.4 * x)));
} else {
double v = 1.4142135623730950488 * sqrt(1 + 2.7182818284590452354 * x);
double N2 = 10.242640687119285146 + 1.9797586132081854940 * v;
double N1 = 0.29289321881345247560 * (1.4142135623730950488 + N2);
w0 = -1.0 + v * (N2 + v) / (N2 + v + N1 * v);
}
while (true) {
double e = exp(w0);
double f = w0 * e - x;
w1 = w0 + ((f+f) * (1.0 + w0)) / (f * (2.0 + w0) - (e+e) * (1.0 + w0) * (1.0 + w0));
if (fabs(w0 / w1 - 1.0) < 1.4901161193847656e-8) {
break;
}
w0 = w1;
}
return w1;
}
__host__ __device__ float plog(float x)
{
if (x == 0.0f) {
return 0.0f;
}
float w0, w1;
if (x > 0.0f) {
w0 = log(1.2f * x / log(2.4f * x / log1p(2.4f * x)));
} else {
float v = 1.4142135623730950488f * sqrt(1 + 2.7182818284590452354f * x);
float N2 = 10.242640687119285146f + 1.9797586132081854940f * v;
float N1 = 0.29289321881345247560f * (1.4142135623730950488f + N2);
w0 = -1.0f + v * (N2 + v) / (N2 + v + N1 * v);
}
while (true) {
float e = exp(w0);
float f = w0 * e - x;
w1 = w0 + ((f+f) * (1.0f + w0)) / (f * (2.0f + w0) - (e+e) * (1.0f + w0) * (1.0f + w0));
if (fabs(w0 / w1 - 1.0f) < 0.00034526698300124390840f) {
break;
}
w0 = w1;
}
return w1;
}
#endif | /*
Copyright 2015 Thomas Luu
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
File: plog.cu
Computation of the Lambert W-function by Halley's Method.
Single and double precision implementations.
Initial guesses based on:
D.A. Barry, J.-Y. Parlange, L. Li, H. Prommer, C.J. Cunningham, and
F. Stagnitti. Analytical approximations for real values of the Lambert
W-function. Mathematics and Computers in Simulation, 53(1):95-103, 2000.
D.A. Barry, J.-Y. Parlange, L. Li, H. Prommer, C.J. Cunningham, and
F. Stagnitti. Erratum to analytical approximations for real values of the
Lambert W-function. Mathematics and computers in simulation, 59(6):543-543,
2002.
*/
#ifndef PLOG
#define PLOG
__host__ __device__ double plog(double x)
{
if (x == 0.0) {
return 0.0;
}
double w0, w1;
if (x > 0.0) {
w0 = log(1.2 * x / log(2.4 * x / log1p(2.4 * x)));
} else {
double v = 1.4142135623730950488 * sqrt(1 + 2.7182818284590452354 * x);
double N2 = 10.242640687119285146 + 1.9797586132081854940 * v;
double N1 = 0.29289321881345247560 * (1.4142135623730950488 + N2);
w0 = -1.0 + v * (N2 + v) / (N2 + v + N1 * v);
}
while (true) {
double e = exp(w0);
double f = w0 * e - x;
w1 = w0 + ((f+f) * (1.0 + w0)) / (f * (2.0 + w0) - (e+e) * (1.0 + w0) * (1.0 + w0));
if (fabs(w0 / w1 - 1.0) < 1.4901161193847656e-8) {
break;
}
w0 = w1;
}
return w1;
}
__host__ __device__ float plog(float x)
{
if (x == 0.0f) {
return 0.0f;
}
float w0, w1;
if (x > 0.0f) {
w0 = log(1.2f * x / log(2.4f * x / log1p(2.4f * x)));
} else {
float v = 1.4142135623730950488f * sqrt(1 + 2.7182818284590452354f * x);
float N2 = 10.242640687119285146f + 1.9797586132081854940f * v;
float N1 = 0.29289321881345247560f * (1.4142135623730950488f + N2);
w0 = -1.0f + v * (N2 + v) / (N2 + v + N1 * v);
}
while (true) {
float e = exp(w0);
float f = w0 * e - x;
w1 = w0 + ((f+f) * (1.0f + w0)) / (f * (2.0f + w0) - (e+e) * (1.0f + w0) * (1.0f + w0));
if (fabs(w0 / w1 - 1.0f) < 0.00034526698300124390840f) {
break;
}
w0 = w1;
}
return w1;
}
#endif |
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