code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module sim_ALU ();
parameter SIZE = 32;
reg [SIZE-1:0] A, B; //定义测试输入信号
reg [3:0] OP;
reg CLK;
wire [SIZE-1:0] F;
wire CF;
initial begin
OP = 4'b0000;
B = 32'hfffffff9;
A = 32'h00000003;
CLK = 0;
fork
repeat (100) #5 OP = (OP + 1) % 8;
repeat (200) #3 CLK = ~CLK;
... | 6.893135 |
module sim_ARMCPU ();
reg CLK; //控制信号输入
wire [63:0] WriteData, DataAdr;
wire MemWrite, MemRead;
//integer i;
initial begin
CLK = 0;
fork
repeat (100) #10 CLK = ~CLK;
join
end
ARM_CPU_pipeline ARM_CPU_pipeline_1 (
CLK,
WriteData,
DataAdr,
MemWrite,
MemRead... | 6.81067 |
module sim_bxu ();
parameter DATA_BITWIDTH = 8;
parameter CODE_BITWIDTH = 16;
parameter ADDR_BITWIDTH = 16;
reg clk = 0;
reg rst_n = 0;
initial #20 rst_n <= 1;
always #5 clk <= ~clk;
reg [7:0] data_rx = 0;
reg ready_rx = 0;
wire done_rx;
wire [7:0] data_tx;
wire ready_tx;
reg done_tx = 0;
... | 6.658601 |
module: cache
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sim_cache;
// Inputs
reg clk;
reg rst;
reg [31:0] addr;
reg store;
reg edit;
reg invalid;
reg [31:0] din;
// ... | 6.526211 |
module sim_camera (
input i_cam_in_clk,
input i_cam_rst,
input i_flash,
output o_pix_clk,
output reg o_flash_strobe = 0,
output reg o_vsync = 0,
output reg o_hsync = 0,
output reg [7:0] o_pix_data = 0
);
//Local Parameters
localparam START = 4'h0;
lo... | 7.042699 |
module sim_camera (
input xclk,
input n_rst,
output pclk,
output reg vsync,
output reg href,
output reg [7:0] data
);
parameter WIDTH = 640; // Image width
parameter HEIGHT = 480; // Image height
parameter INFILE = "input.hex"; // image file
parameter sizeOfWidth = 8; // data width
... | 7.042699 |
module top_module (
input a,
input b,
output q
); //
assign q = a & b; // Fix me
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = ~(a^b^c^d); // Determined by even number of 1's whenever output is 1. Satisfied all conditions-hence XNOR.
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = (a | b) & (c | d); // Fix me
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = b | c; // Fix me
endmodule
| 7.203305 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module sim_control ();
reg clk = 'b0;
wire [31:0] pc, npc, ins;
wire en;
always #10 clk = ~clk;
pcP4 apc4 (
pc,
npc
);
irom sim_irom (
pc,
ins
);
regPc apc (
clk,
en,
npc,
pc
);
pcControl apcc (
ins,
'b0,
en
);
control acu (
... | 6.686967 |
module Sim_CP0 (
output wire INT,
output wire CP0ToReg,
output wire [31:0] id_dout,
output wire [31:0] epc_out,
output wire eret
);
reg [31:0] id_instr;
reg [31:0] wb_instr;
reg [31:0] wb_din;
reg [31:0] ex_pc;
reg [ 2:0] intsrc;
reg clk, rst;
always @* #3 clk <=... | 7.697075 |
module sim_div_clock ();
reg clk, cs, rst;
reg [2:0] din_a;
reg [2:0] addr_a;
reg we_a, oe_a;
wire [2:0] dout_a;
reg [2:0] din_b;
reg [2:0] addr_b;
reg we_b, oe_b;
wire [2:0] dout_b;
wire [2:0] memout;
reg clk_rst;
reg load;
initial begin
clk = 0;
clk_rst = 0;
#5 clk_rst = 1;
... | 6.643132 |
module // sim_double_ram
//`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////////
//// Company:
//// Engineer:
////
//// Create Date: 2019/12/23 16:22:09
//// Design Name:
//// Module Name: sim_double_ram_sy
//// Project Name:
//// Target Devices:
//// Tool Vers... | 6.530468 |
module sim_dp_rom (
input wire clk,
/* Instruction bus. */
input wire i_access,
input wire i_cs,
input wire [11:0] i_addr,
output reg [31:0] i_data,
output reg i_ack,
/* Data bus. */
input wire d_access,
input wire d_cs,
input wire [11:0] d_addr,
input wire [3:0] d_bytese... | 7.050835 |
module tb ();
// Clock
reg clk;
initial clk <= 1'b0;
always #0.5 clk <= ~clk;
// Reset
reg rst;
initial begin
rst <= 1'b0;
#2 rst <= 1'b1;
#2 rst <= 1'b0;
end
// Filter control
reg [2:0] fcnt;
reg [3:0] dcnt;
initial begin
fcnt <= 0;
dcnt <= 0;
end
// MAC cycle count... | 7.022577 |
module tb ();
// Clock
reg clk;
initial clk <= 1'b0;
always #0.5 clk <= ~clk;
// Reset
reg rst;
initial begin
rst <= 1'b0;
#2 rst <= 1'b1;
#2 rst <= 1'b0;
end
// Filter control
reg [2:0] fcnt;
reg [3:0] dcnt;
initial begin
fcnt <= 0;
dcnt <= 0;
end
// MAC cycle count... | 7.022577 |
module tb ();
// Clock
reg clk;
initial clk <= 1'b0;
always #0.5 clk <= ~clk;
// Reset
reg rst;
initial begin
rst <= 1'b0;
#1 rst <= 1'b1;
#2 rst <= 1'b0;
end
// Input data / reference
reg signed [19:0] A;
reg signed [17:0] B;
reg signed [37:0] C;
always @(posedge clk) begin
... | 7.022577 |
module tb ();
// Clock
reg clk;
initial clk <= 1'b0;
always #0.5 clk <= ~clk;
// Reset
reg rst;
initial begin
rst <= 1'b0;
#1 rst <= 1'b1;
#2 rst <= 1'b0;
end
// Input data / reference
reg signed [19:0] A;
reg signed [17:0] B;
reg signed [37:0] C;
always @(posedge clk) begin
... | 7.022577 |
module tb ();
// Clock
reg clk;
initial clk <= 1'b0;
always #0.5 clk <= ~clk;
// Reset
reg rst;
initial begin
rst <= 1'b0;
#1 rst <= 1'b1;
#2 rst <= 1'b0;
end
// Input data / reference
reg signed [19:0] A;
reg signed [17:0] B;
reg signed [37:0] C;
// Shift data change half a cl... | 7.022577 |
module tb ();
// Clock
reg clk;
initial clk <= 1'b0;
always #0.5 clk <= ~clk;
// Reset
reg rst;
initial begin
rst <= 1'b0;
#1 rst <= 1'b1;
#2 rst <= 1'b0;
end
// Input data / reference
reg signed [19:0] A;
reg signed [17:0] B;
reg signed [37:0] C;
// Shift data change half a cl... | 7.022577 |
module tb ();
// Clock
reg clk;
initial clk <= 1'b0;
always #1 clk <= ~clk;
// Data Clock
reg dclk;
initial dclk <= 1'b0;
always #2 dclk <= ~dclk;
// Input data / reference
reg [ 9:0] A0;
reg [ 9:0] A1;
reg [ 8:0] B0;
reg [ 8:0] B1;
reg [18:0] C0;
reg [18:0] C1;
always @(negedge dc... | 7.022577 |
module tb ();
// Clock
reg clk;
initial clk <= 1'b0;
always #1 clk <= ~clk;
// Data Clock
reg dclk;
initial dclk <= 1'b0;
always #2 dclk <= ~dclk;
// Input data / reference
reg [ 9:0] A0;
reg [ 9:0] A1;
reg [ 8:0] B0;
reg [ 8:0] B1;
reg [18:0] C0;
reg [18:0] C1;
always @(negedge dc... | 7.022577 |
module sirv_duelport_ram #(
parameter DP = 2048,
parameter FORCE_X2ZERO = 0,
parameter DW = 32,
parameter MW = 4,
parameter AW = 32
) (
input clk,
input rst_n,
input cs,
input req_a,
input req_b,
input [DW-1 : 0] di... | 7.292946 |
module sim_encoder83_case ();
reg [7:0] I; //8位
wire [3:1] Y_case, Y_precase;
integer i;
initial begin
I = 1;
for (i = 0; i < 7; i = i + 1) #10 I = I * 2;
#10 I = 128;
while (I > 0) #5 I = I - 1;
end
encoder83_case encoder83_case_1 (
I,
Y_case
); // 编码器8-3
pre_encoder83_c... | 6.575901 |
module sim_env;
reg tstclk;
reg tstclr;
wire [15:0] topdin;
wire [ 7:0] topdout;
wire toprw;
wire [ 7:0] topadrs;
always begin
tstclk <= 1'b0;
#5;
tstclk <= 1'b1;
#5;
end
toplevel dut_top (
.clk (tstclk),
.clr (tstclr),
.din (topdin),
.... | 6.772634 |
module sim_fifo_asy;
// Inputs
reg rst;
reg clk_w;
reg en_w;
reg [31:0] data_w;
reg clk_r;
reg en_r;
// Outputs
wire full_w;
wire near_full_w;
wire [7:0] space_count;
wire [31:0] data_r;
wire empty_r;
wire near_empty_r;
wire [7:0] data_count;
// Instantiate the Unit Under Test (UUT)
... | 6.593498 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module sim_ifetch ();
reg sys_clk;
reg rst_n;
wire [31:0] ins_out;
wire [31:0] pc_out;
initial begin
sys_clk = 0;
rst_n = 0;
#8 rst_n = 1;
end
always #5 sys_clk = ~sys_clk;
ifetch fetch (
.sys_clk(sys_clk),
.rst_n (rst_n),
.ins_out(ins_out),
.pc_out (pc_out)
);... | 6.504913 |
module Sim_InstructionWordSpliter (
output wire [ 5:0] opcode,
output wire [ 4:0] rs,
output wire [ 4:0] rt,
output wire [ 4:0] rd,
output wire [ 4:0] shamt,
output wire [ 5:0] funct,
output wire [15:0] immediate
);
reg [31:0] instr_word;
initial begin
// test opcode
#0 instr_w... | 6.529356 |
module Sim_InterruptSampler (
output wire indication
);
reg clk, rst;
reg intsrc;
always @* #3 clk <= ~clk;
initial begin
// initializations
#0 clk = 0;
#0 rst = 0;
#0 intsrc = 0;
#5 rst = 1;
#6 rst = 0;
// yield single shot interrupt signal
#6 intsrc = 1;
#6 intsrc = ... | 6.764351 |
module sim_jtag (
input clk,
input rst_n,
output reg tdi,
output reg tms,
output reg tclk,
input tdo
);
int port;
int sock;
int fd;
int err;
initial begin
fd = -1;
if ($value$plusargs("jtag_port=%d", port) == 0) port = `DEFAULT_DEBUG_PORT_JTAG;
$display("using deb... | 6.932764 |
module Sim_LHSpecialRegisters (
output wire [31:0] lo,
output wire [31:0] hi
);
reg clk;
reg [63:0] result;
reg ready;
initial begin
#0 clk = 0;
#0 ready = 0;
#0 result = 0;
// floating result, should have no effets on lo and hi
#5 result = 64'h1122334455667788;
/... | 7.229232 |
module \$mul (
A,
B,
Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
generate
if (A_SIGNED) begin : A_BUF
wire signed [A_WIDTH-1:0] val = A;
end else begin : A_BUF
wire [A_WID... | 7.524175 |
module sim_mux8 ();
reg I0, I1, I2, I3, I4, I5, I6, I7, s0, s1, s2;
wire out;
mux8_2 st (
I0,
I1,
I2,
I3,
I4,
I5,
I6,
I7,
s0,
s1,
s2,
out
);
initial begin
#0 I0 = 1;
I1 = 0;
I2 = 0;
I3 = 0;
I4 = 0;
I5 = 0;
I6 =... | 6.612649 |
module sim_output (
input clk,
input resetn,
input output_rdy,
output output_ack,
input [4:0] output_data
);
`define IDLE 0
`define WRITE 1
`define ACK 2
reg [2:0] status;
reg [2:0] status_next;
wire [7:0] tape_data;
always @(posedge clk) begin
if (~resetn) begin
status... | 6.718795 |
module sim_pc_irom ();
reg clk = 'b0;
wire [31:0] pc, pc4, ins;
wire en;
always #10 clk = ~clk;
pcP4 apc4 (
pc,
pc4
);
irom sim_irom (
pc,
ins
);
regPc apc (
clk,
en,
'b0,
pc4,
pc
);
pcControl apcc (
ins,
'b0,
en
);
wire [... | 6.632034 |
modules. It's not so much a processor as a
// bus arbitrator and interrupt handler. Just enough to try out those functions.
//
// Copyright 2015 Noel Chiappa and David Bridgham
`timescale 1 ns / 1 ns
module sim_proc
(
input BDMR,
input BSACK,
output reg BSYNC = 1,
output reg BRPLY = 1,
output re... | 6.825384 |
module sim_RAM4Kx32 ();
parameter Addr_Width = 8; //参数化地址线宽
parameter Data_Width = 32; //参数化数据线宽
parameter SIZE = 2 ** Addr_Width; //参数化大小1024
reg [Data_Width-1:0] Dataw; //数据，输入输出类型
wire [Data_Width-1:0] Data; //数据，输入输出类型
reg [Addr_Width-1:0] Addr; //地址
reg Rst; //复位信号
reg R_W; //1读_0写信号
r... | 7.295222 |
module sim_register ();
integer i;
wire [7:0] Q; // 状态信号Q，～Q //不能用reg
reg [7:0] D; // 激励信号
reg OE, CLK; //使能信号EN， 复位信号RST
initial begin
D = 8'b1000_1001;
OE = 0;
CLK = 0;
fork
#150 D = ~D;
repeat (20) #5 OE = ~OE;
repeat (20) #10 CLK = ~CLK;
join
end
registe... | 6.927626 |
module sim_sdp_mem #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input wire clk,
input wire we,
input wire [ADDR_WIDTH-1:0] raddr,
input wire [ADDR_WIDTH-1:0] waddr,
input wire [DATA_WIDTH-1:0] din,
output reg [DATA_WIDTH-1:0] dout
);
... | 7.761478 |
module top_module (
input clk,
input a,
output q
);
always @(posedge clk) q <= ~a;
endmodule
| 7.203305 |
module top_module (
input clock,
input a,
output p,
output q
);
//Inferring latch(level-sensitive)
always @(clock) begin
if (clock) begin
p <= a;
end
end
//Inferring FF
always @(negedge clock) begin
q <= a;
end
endmodule
| 7.203305 |
module sim_shiftregister ();
integer i;
wire [3:0] Q; // 状态信号Q，～Q //不能用reg
reg [3:0] D; // 激励信号
reg S1, S0, Dsl, Dsr, CLK, CR; //使能信号EN， 复位信号RST
initial begin
D = 4'b0101;
Dsl = 0;
Dsr = 1;
CR = 0;
CLK = 0;
S1 = 1;
S0 = 1;
fork
#12 CR = ~CR;
repeat (100) #... | 6.520248 |
module sim_shift_reg_act ();
reg clk;
reg enable;
reg [ 15:0] input_data;
wire [399:0] result;
initial begin
input_data <= 8'h00;
end
always begin
#3 clk = 1'b0;
enable = 1'b0;
#3 clk = 1'b1;
#3 clk = 1'b0;
#3 clk = 1'b1;
enable = 1'b1;
input_data <= ... | 6.880516 |
module sim_sp_mem #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input wire clk,
input wire we,
input wire [ADDR_WIDTH-1:0] addr,
input wire [DATA_WIDTH-1:0] din,
output reg [DATA_WIDTH-1:0] dout
);
// (* RAM_STYLE="{AUTO | BLOCK | BLO... | 7.793029 |
module \$_INV_ (
A,
Y
);
input A;
output Y;
assign Y = ~A;
endmodule
| 7.441169 |
module \$_AND_ (
A,
B,
Y
);
input A, B;
output Y;
assign Y = A & B;
endmodule
| 7.391345 |
module \$_OR_ (
A,
B,
Y
);
input A, B;
output Y;
assign Y = A | B;
endmodule
| 7.534826 |
module \$_XOR_ (
A,
B,
Y
);
input A, B;
output Y;
assign Y = A ^ B;
endmodule
| 8.065982 |
module \$_MUX_ (
A,
B,
S,
Y
);
input A, B, S;
output reg Y;
always @* begin
if (S) Y = B;
else Y = A;
end
endmodule
| 7.162711 |
module \$_DFF_N_ (
D,
Q,
C
);
input D, C;
output reg Q;
always @(negedge C) begin
Q <= D;
end
endmodule
| 7.090598 |
module \$_DFF_NN0_ (
D,
Q,
C,
R
);
input D, C, R;
output reg Q;
always @(negedge C or negedge R) begin
if (R == 0) Q <= 0;
else Q <= D;
end
endmodule
| 6.560896 |
module \$_DFF_PN0_ (
D,
Q,
C,
R
);
input D, C, R;
output reg Q;
always @(posedge C or negedge R) begin
if (R == 0) Q <= 0;
else Q <= D;
end
endmodule
| 6.500064 |
module \$_DFF_PN1_ (
D,
Q,
C,
R
);
input D, C, R;
output reg Q;
always @(posedge C or negedge R) begin
if (R == 0) Q <= 1;
else Q <= D;
end
endmodule
| 6.619954 |
module sim_uc (
//output reg [7:0]port_out,
//input [7:0]port_in
);
reg [7:0] port_out;
wire [7:0] port_in = port_out;
reg rst = 0;
reg clk = 0;
always #(1) clk <= ~clk; // clocking device
//wire pgm_re;
wire [`BUS_ADDR_PGM_LEN-1:0] pgm_addr;
wire [15:0] pgm_data;
wire data_re;
wire dat... | 7.012663 |
module sinal (
output [6:0] Pos,
input sinal
);
assign Pos = (sinal ? ~7'b1000000 : ~7'b0000000);
endmodule
| 7.501475 |
module sinc3 (
data_adc,
clk_adc,
rstn_adc,
DATA,
word_clk,
mode
);
input clk_adc;
input rstn_adc;
input data_adc;
input [1:0] mode;
output [15:0] DATA;
output word_clk;
integer location;
integer info_file;
reg [35:0] ip_data1;
reg [35:0] acc1;
reg [35:0] acc2;
reg [35:0]... | 6.861998 |
module sinc3Filter #(
parameter OSR = 16 // Output width is 3*ceil(log2(OSR))+1
) (
input clk,
input en, ///< Enable (use to clock at slower rate)
input in,
output reg signed [3*$clog2(OSR):0] out
);
// Parameters
///////////////////////////////////////////////////////////////////////////
... | 7.863541 |
module sincf #(
parameter win = 1,
wout = 5
) (
input clk,
input [win-1:0] din,
output reg [wout-1:0] dout
);
reg [win-1:0] mem[23:0];
genvar i;
generate
for (i = 23; i > 0; i = i - 1) begin : meminput
always @(posedge clk) mem[i] <= mem[i-1];
end
endgenerate
always @(p... | 7.124945 |
module sincostop (
clk,
reset,
eksi,
aci,
mode_switch,
out
);
input clk, reset;
input [2:0] aci;
input eksi;
input mode_switch;
output signed [16:0] out; // FORMAT : Q7.10
wire signed [16:0] SinOut;
wire signed [16:0] CosOut;
wire signed [16:0] sin_min;
reg [2:0] count = 3... | 7.642597 |
module sincos_cal (
i_clk,
i_reset,
iv_degree,
ov_sin,
ov_cos
);
input i_clk, i_reset;
input [6:0] iv_degree;
output [10:0] ov_cos, ov_sin;
reg [6:0] address;
always @(*) begin
if (i_reset) address <= 7'd0;
else begin
if (iv_degree >= 7'd90) address <= 7'b1111111;
e... | 6.670525 |
module SinCos_Calculation (
input wire clk,
input wire rst_n,
input wire [`Angle_DataWidth-1 : 0] angle,
output wire [`SinCos_Tab_DataWidth-1 : 0] sin,
output wire [`SinCos_Tab_DataWidth-1 : 0] cos
);
wire [`SinCos_Tab_DataWidth-1 : 0] wire_sin, wire_cos;
wire [`SinSos_Tab_Depth-1:0] addr_sin_... | 7.391827 |
module SinCos_cal_demo #(
parameter N = 16
) (
input wire clk,
input wire rst_n,
input wire [3:0] angle,
output wire [N-1:0] sin
);
SINCOS_TAB_demo math_tab (
.sys_clk(clk),
.rst_n (rst_n),
.addra (angle),
.sin_val(sin)
);
endmodule
| 7.413197 |
module SINCOS_TAB (
input wire sys_clk,
input wire rst_n,
input wire [`SinSos_Tab_Depth-1 : 0] addr_sin,
input wire [`SinSos_Tab_Depth-1 : 0] addr_cos,
output wire [`SinCos_Tab_DataWidth-1 : 0] data_sin,
output wire [`SinCos_Tab_DataWidth-1 : 0] data_cos
);
reg [`SinCos_Tab_DataWidth-1:0] rom... | 6.869612 |
module SINCOS_TAB_demo #(
parameter N = 4,
parameter Depth = 1 << N
) (
input wire sys_clk,
input wire rst_n,
input wire [N-1:0] addra,
output wire [15:0] sin_val
);
reg [15:0] rom_tab [Depth-1:0];
reg [15:0] reg_temp;
//生成rom的数据
genvar i;
generate
for (i = 0; i < Depth; i = i +... | 6.57232 |
module Sincronizador (
incambiarfuncion,
incambiarsalida,
inrst,
inbtup,
inbtdown,
outcambiarfuncion,
outcambiarsalida,
outrst,
outbtup,
outbtdown,
clk
);
input wire incambiarfuncion, incambiarsalida, inrst, inbtup, inbtdown, clk;
output wire outcambiarfuncion, outcambiar... | 7.187674 |
module sinc_memory #(
parameter RAM_WIDTH = 16, // Specify RAM data width
parameter RAM_DEPTH = 2048,
//parameter ADDR_NB = $clog2(RAM_DEPTH), // Specify RAM depth (number of entries)
parameter INIT_FILE = "" // Specify name/location of RAM initialization file if... | 10.259588 |
module SineGen #(
parameter div_factor_freq0 = 32'd3,
div_factor_freq1 = 32'd1,
depth_p = 10'd11, // the number of samples in one period of the signal
width_p = 10'd16 // the number of bits used to represent amplitude value
) (
input clk, //input clock sign... | 8.181262 |
module sinegenerator #(
parameter BITSIZE = 24,
parameter PHASESIZE = 16,
parameter TABLESIZE = 9,
)(
input wire enable,
input wire lrclk,
input wire [PHASESIZE-1:0] freq,
output reg [BITSIZE-1:0] out,
);
reg [BITSIZE-1:0] quartertable [0:((2**TABLESIZE)-1)];
if (BITSIZE == 24) begin
if (TABLE... | 6.897177 |
module SineGen_tb ();
reg clk; // input clock signal
reg reset; // input reset signal
// signal used for controlling the operation
reg Start0, Start1;
wire Done0, Done1;
wire freq_trig0, freq_trig1;
reg freq_trig_mask0, freq_trig_mask1;
wire [15:0] sine_out0, sine_out1;
parameter div_factor_fre... | 7.605101 |
module SINE_WAVES #(
parameter addr_width = 12,
data_width = 9
) (
input wire clk,
input wire [addr_width-1:0] addr,
output reg [data_width-1:0] dout
);
`ifdef WITH_64K
(* ram_style = "distributed" *) reg [data_width-1:0] sine_rom[2**addr_width-1:0];
`else
(* ram_style = "block" *) reg [data_wi... | 8.062697 |
module sine_wave_gen (
Clk,
data_out
);
//declare input and output
input Clk;
output [7:0] data_out;
//declare the sine ROM - 30 registers each 8 bit wide.
reg [7:0] sine[0:29];
//Internal signals
integer i;
reg [7:0] data_out;
//Initialize the sine rom with samples.
initial begin
i... | 6.660409 |
module: sineWaveExample
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sineWaveExampleTest;
// Inputs
reg Clk;
// Outputs
wire [7:0] data_out;
// Instantiate t... | 6.618192 |
module Sine_Cosine_Generator_8KHz (
input clk,
output reg [31:0] sinus,
output reg [31:0] cosinus
);
parameter SIZE = 32; // Sine and Cosine LUT Size
reg signed [31:0] rom_memory_sinus [SIZE-1:0];
reg signed [31:0] rom_memory_cosinus [SIZE-1:0];
integer i;
integer j;
initial begin
// ... | 7.04204 |
module sine_func (
input clk,
rst_n,
input [9:0] x, //input has a 10-bit resolution(from 0 to 2pi)
output [7:0] y //output has 8-bit resolution(from -1 to 1)
);
reg [7:0] y_q = 0, y_d;
reg [7:0] x_addr; //determines the address to be inserted in ROM
wire [6:0] dout;
always @(posedge clk, n... | 7.747306 |
module sine_reader (
input clk,
input reset,
input [19:0] step_size,
input generate_next,
output sample_ready,
output wire [15:0] sample
);
//states
localparam SWIDTH = 22;
wire [SWIDTH - 1:0] addr;
dffre #(
.WIDTH(SWIDTH)
) state_reg (
.clk(clk),
.r (reset),
... | 6.975531 |
module sine_reader_tb ();
reg clk, reset, generate_next;
reg [19:0] step_size;
wire sample_ready;
wire [15:0] sample;
sine_reader reader (
.clk(clk),
.reset(reset),
.step_size(step_size),
.generate_next(generate_next),
.sample_ready(sample_ready),
.sample(sample)
);
/... | 7.546746 |
module sine_tone #(
parameter WIDTH = 32,
parameter SR_PHASE_INC_ADDR = 129,
parameter SR_CARTESIAN_ADDR = 130
) (
input clk,
input reset,
input clear,
input enable,
input set_stb,
input [WIDTH-1:0] set_data,
input [7:0] set_addr,
output [WIDTH-1:0] o_tdata,
output o_tlas... | 6.548267 |
module Sine_Wave_Generator #(
parameter PHASE_WIDTH = 10,
parameter SAMPLE_WIDTH = 16,
parameter OFFSET_ENABLE = 0
) (
input wire clk,
input wire rst,
//input wire smpl_en,
input wire [PHASE_WIDTH - 1 : 0] smpl_phase,
//output reg smpl_valid,
output reg [SAMPLE_WIDTH - 1 : 0] smpl... | 6.849902 |
module sine_wave_gen_quarter #(
parameter ROM_DEPTH = 32768,
ROM_WIDTH = 16
) (
input wire i_clk,
input wire i_rst,
input wire [31:0] i_phase_step, //freq will increase as i_phase_step increases
output reg signed [15:0] o_gen_out = 0
);
reg signed [ROM_W... | 6.660409 |
module sine_wave_gen_tb ();
reg clk = 0;
wire signed [15:0] sine_wave;
reg [31:0] phase_step = 16'd50;
reg rst = 0;
//clock gen
always begin
#2 clk = ~clk;
end
integer i, sine_wave_file;
initial begin
sine_wave_file = $fopen("sine_wave_file.csv", "w");
//sweep up in frequency and rec... | 6.660409 |
module singcyc (
iClk,
iRst_n,
iSwitch,
oLED,
oDigi,
_oPC,
_oPCNext
);
input iClk;
input iRst_n;
input [7:0] iSwitch;
output [7:0] oLED;
output [11:0] oDigi;
output [31:0] _oPC;
output [31:0] _oPCNext;
wire DataMemRd;
wire DataMemWr;
wire [31:0] DataMemAdd... | 6.633494 |
module SignE (
//Entradas
input [15:0] SEInp,
//Salidas
output reg [31:0] SEOut
);
//2- Delcaracion de señales --> NA(No aplica)
//3- Cuerpo del modulo
//Bloque Always
always @* begin //Inicio_A
SEOut = {{16{SEInp[15]}}, SEInp};
end //Fin_A
endmodule
| 7.148093 |
module singleAdd (
input clk,
input hit,
input carry,
output reg [3:0] Q
);
initial Q <= 4'b0000;
always @(posedge clk or negedge carry) begin
if (carry == 1'b0) Q <= 4'b0000;
else if (hit == 1'b1) Q <= Q + 4'b0001;
end
endmodule
| 7.03884 |
module SingleClockRAM #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 15
) (
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] addr,
input we,
clk,
output [(DATA_WIDTH-1):0] q
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
// Variable to hold t... | 8.038224 |
module SingleCycleARM (
input CLK,
input reset,
output wire [31:0] PC,
input [31:0] Instr,
output wire MemWrite,
output wire [31:0] ALUResult,
output wire [31:0] WriteData,
input wire [31:0] ReadData
);
wire [3:0] ALUFlags;
wire RegWrite, ALUSrc, MemtoReg, PCSrc, MOVInstr, link;
w... | 6.79694 |
module SingleCycleCpu_tb ();
reg clk;
reg rst;
wire [31:0] instruction;
wire [31:0] pcOut;
reg [4:0] readRegisterDebug;
wire [31:0] readDataDebug;
SingleCycleCpu uut (
clk,
rst,
instruction,
pcOut,
readRegisterDebug,
readDataDebug
);
initial begin
$dumpfile(... | 8.117842 |
module regFile (
R1,
R2,
W1,
D1,
We,
clk,
O1,
O2
); // 6 i/p , 2 o/p
input [4:0] R1, R2; //address '5 bits
input [4:0] W1;
input [31:0] D1; // data to be saved '32 bits
input We;
input clk;
output [31:0] O1, O2; //output data from R1,R2 '32 bits
reg [31:0] index[0:3... | 7.797802 |
module testRegFile; //inputs are reg - 2 i/p , 6 o/p
reg [4:0] R1, R2; //address '5 bits
reg [4:0] W1;
reg [31:0] D1; // data to be saved '32 bits
reg We;
reg clk;
wire [31:0] in1, in2; //output data from R1,R2 '32 bits
integer i;
always begin
#1 clk = ~clk;
end
initial begin
c... | 6.762491 |
module dataMem (
R1,
D1,
We,
Re,
clk,
O1
); // 5 i/p , 1 o/p
input [31:0] R1; //address '32 bits
input [31:0] D1; // data to be saved '32 bits
input We, Re;
input clk;
output reg [31:0] O1; //output data from R1 '32 bits
reg [7:0] index[0:2**32 -1]; // first is number of mem... | 6.754704 |
module InstMem (
R1,
W1,
D1,
We,
clk,
O1
); // 4 i/p , 1 o/p
input [31:0] R1, W1; //address '32 bits
input [31:0] D1;
input clk, We;
output reg [31:0] O1; //output data from R1'32 bits
reg [7:0] index[0:2**32 -1]; // first is number of mem size , second is number of memvalues
... | 6.646235 |
module testALU;
reg [31:0] data1, data2;
reg [3:0] control_signals;
wire zero, overflow;
wire [31:0] result;
initial begin
$monitor($time, " R1=%d , R2=%d,control=%d, Result=%d, zeroFlag=%d, overflow=%d", data1,
data2, control_signals, sh_am, result, zero, overflow);
#1 data1 = 1;
... | 6.737869 |
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