code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module TBUFX16 (
Y,
A,
OE
);
output Y;
input A, OE;
// Function
bufif1 (Y, A, OE);
// Timing
specify
(A => Y) = 0;
(OE => Y) = 0;
endspecify
endmodule
| 6.879027 |
module TBUFX2 (
Y,
A,
OE
);
output Y;
input A, OE;
// Function
bufif1 (Y, A, OE);
// Timing
specify
(A => Y) = 0;
(OE => Y) = 0;
endspecify
endmodule
| 6.905349 |
module TBUFX20 (
Y,
A,
OE
);
output Y;
input A, OE;
// Function
bufif1 (Y, A, OE);
// Timing
specify
(A => Y) = 0;
(OE => Y) = 0;
endspecify
endmodule
| 7.162916 |
module TBUFX6 (
Y,
A,
OE
);
output Y;
input A, OE;
// Function
bufif1 (Y, A, OE);
// Timing
specify
(A => Y) = 0;
(OE => Y) = 0;
endspecify
endmodule
| 6.649416 |
module TBUFX8 (
Y,
A,
OE
);
output Y;
input A, OE;
// Function
bufif1 (Y, A, OE);
// Timing
specify
(A => Y) = 0;
(OE => Y) = 0;
endspecify
endmodule
| 6.928405 |
module TBUFXL (
Y,
A,
OE
);
output Y;
input A, OE;
// Function
bufif1 (Y, A, OE);
// Timing
specify
(A => Y) = 0;
(OE => Y) = 0;
endspecify
endmodule
| 6.635503 |
module slpf (
clk,
in,
out
);
output out;
input clk;
input in;
// Three buffers (as shift register) for the low pass filter
wire ubuff1;
wire ubuff2;
wire ubuff3;
// Signals from the ANDs of the buffers
wire ubuff12;
wire ubuff13;
wire ubuff23;
//The low pass filter: if any of the bits are low, the output is low
DFF(
.D(in), .CLK(clk), .Q(ubuff1)
); DFF(
.D(ubuff1), .CLK(clk), .Q(ubuff2)
); DFF(
.D(ubuff2), .CLK(clk), .Q(ubuff3)
);
and prod (out, ubuff1, ubuff2, ubuff3);
endmodule
| 6.722847 |
module slr_cross #(
parameter REGS_BEFORE = 1,
parameter REGS_AFTER = 1,
parameter WIDTH = 16
) (
input wire clk,
input wire [WIDTH-1 : 0] d,
output wire [WIDTH-1 : 0] q,
input wire sreset
);
(* shreg_extract="no" *)
reg [ WIDTH-1:0] regs_before;
(* USER_SLL_REG="true", shreg_extract="no" *)
reg [WIDTH-1 : 0] laguna_tx;
(* USER_SLL_REG="true", shreg_extract="no" *)
reg [WIDTH-1 : 0] laguna_rx;
(* shreg_extract="no" *)
reg [ WIDTH-1:0] regs_after;
generate
if (REGS_BEFORE == 0) begin
always @* regs_before = d;
end else begin
always @(posedge clk) regs_before <= sreset ? 0 : d;
end
endgenerate
always @(posedge clk) begin
laguna_tx <= regs_before;
laguna_rx <= laguna_tx;
end
generate
if (REGS_AFTER == 0) begin
always @* regs_after = laguna_rx;
end else begin
always @(posedge clk) regs_after <= sreset ? 0 : laguna_rx;
end
endgenerate
assign q = regs_after;
endmodule
| 7.475964 |
module SLT (
input signed [31:0] a,
input signed [31:0] b,
output signed [31:0] r
);
assign r = (a < b) ? 1 : 0;
endmodule
| 7.651592 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
.CI(CIN),
.CO(inst1_CO)
);
assign O = inst0_O;
assign COUT = inst1_CO;
endmodule
| 7.610141 |
module Add2_CIN (
input [1:0] I0,
input [1:0] I1,
input CIN,
output [1:0] O
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
FullAdder inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(inst0_O),
.COUT(inst0_COUT)
);
FullAdder inst1 (
.I0(I0[1]),
.I1(I1[1]),
.CIN(inst0_COUT),
.O(inst1_O),
.COUT(inst1_COUT)
);
assign O = {inst1_O, inst0_O};
endmodule
| 6.821676 |
module SLT2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] inst0_O;
wire inst1_O;
Sub2 inst0 (
.I0(I0),
.I1(I1),
.O (inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h008E)
) inst1 (
.I0(inst0_O[1]),
.I1(I0[1]),
.I2(I1[1]),
.I3(1'b0),
.O (inst1_O)
);
assign O = inst1_O;
endmodule
| 6.651349 |
module main (
input [3:0] J1,
output J3
);
wire inst0_O;
SLT2 inst0 (
.I0({J1[1], J1[0]}),
.I1({J1[3], J1[2]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module SLT2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] inst0_O;
wire inst1_O;
Sub2_cin1 inst0 (
.I0(I0),
.I1(I1),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) inst1 (
.I0(inst0_O[1]),
.I1(I0[1]),
.I2(I1[1]),
.O (inst1_O)
);
assign O = inst1_O;
endmodule
| 6.651349 |
module SLT2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] inst0_O;
wire inst1_O;
Sub2_cin1 inst0 (
.I0(I0),
.I1(I1),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) inst1 (
.I0(inst0_O[1]),
.I1(I0[1]),
.I2(I1[1]),
.O (inst1_O)
);
assign O = inst1_O;
endmodule
| 6.651349 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
.CI(CIN),
.CO(inst1_CO)
);
assign O = inst0_O;
assign COUT = inst1_CO;
endmodule
| 7.610141 |
module Add4_CIN (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
wire inst2_O;
wire inst2_COUT;
wire inst3_O;
wire inst3_COUT;
FullAdder inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(inst0_O),
.COUT(inst0_COUT)
);
FullAdder inst1 (
.I0(I0[1]),
.I1(I1[1]),
.CIN(inst0_COUT),
.O(inst1_O),
.COUT(inst1_COUT)
);
FullAdder inst2 (
.I0(I0[2]),
.I1(I1[2]),
.CIN(inst1_COUT),
.O(inst2_O),
.COUT(inst2_COUT)
);
FullAdder inst3 (
.I0(I0[3]),
.I1(I1[3]),
.CIN(inst2_COUT),
.O(inst3_O),
.COUT(inst3_COUT)
);
assign O = {inst3_O, inst2_O, inst1_O, inst0_O};
endmodule
| 7.507677 |
module SLT4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] inst0_O;
wire inst1_O;
Sub4 inst0 (
.I0(I0),
.I1(I1),
.O (inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h008E)
) inst1 (
.I0(inst0_O[3]),
.I1(I0[3]),
.I2(I1[3]),
.I3(1'b0),
.O (inst1_O)
);
assign O = inst1_O;
endmodule
| 7.061606 |
module main (
input [7:0] J1,
output J3
);
wire inst0_O;
SLT4 inst0 (
.I0({J1[3], J1[2], J1[1], J1[0]}),
.I1({J1[7], J1[6], J1[5], J1[4]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module SLT4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] inst0_O;
wire inst1_O;
Sub4_cin1 inst0 (
.I0(I0),
.I1(I1),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) inst1 (
.I0(inst0_O[3]),
.I1(I0[3]),
.I2(I1[3]),
.O (inst1_O)
);
assign O = inst1_O;
endmodule
| 7.061606 |
module main (
input [7:0] SWITCH,
output LED
);
wire inst0_O;
SLT4 inst0 (
.I0({SWITCH[3], SWITCH[2], SWITCH[1], SWITCH[0]}),
.I1({SWITCH[7], SWITCH[6], SWITCH[5], SWITCH[4]}),
.O (inst0_O)
);
assign LED = inst0_O;
endmodule
| 7.081372 |
module SLT4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] inst0_O;
wire inst1_O;
Sub4_cin1 inst0 (
.I0(I0),
.I1(I1),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) inst1 (
.I0(inst0_O[3]),
.I1(I0[3]),
.I2(I1[3]),
.O (inst1_O)
);
assign O = inst1_O;
endmodule
| 7.061606 |
module slt_32bit (
out,
a,
b
);
output out;
input a, b;
reg [31:0] out;
wire [31:0] a, b;
always @(a or b) begin
if (a < b) out <= #2 32'h00000001;
else out <= #2 32'h00000000;
end
endmodule
| 6.81171 |
module SLTI (
Op,
slti_output
);
input wire [31:26] Op;
output wire slti_output;
wire NOTOp26;
wire NOTOp28;
wire NOTOp30;
wire NOTOp31;
assign slti_output = Op[29] & NOTOp31 & NOTOp30 & NOTOp28 & Op[27] & NOTOp26;
assign NOTOp31 = ~Op[31];
assign NOTOp30 = ~Op[30];
assign NOTOp28 = ~Op[28];
assign NOTOp26 = ~Op[26];
endmodule
| 7.066291 |
module SltiFunction (
input rs, // A
input immediate, // mB
output rt // slti
);
assign rt = (rs < immediate) ? 1 : 0;
endmodule
| 9.076799 |
module Sltsrcb (
ALUSrcB,
B,
Outimm,
SrcB
);
input [31:0] B, Outimm;
input ALUSrcB;
output [31:0] SrcB;
assign SrcB = ({32{ALUSrcB}} & Outimm) | (~{32{ALUSrcB}} & B);
endmodule
| 6.751776 |
module SLTU (
input [31:0] a,
input [31:0] b,
output [31:0] r,
output carry
);
assign r = (a < b) ? 1 : 0;
assign carry = (a < b) ? 1 : 0;
endmodule
| 7.205271 |
module SLT_n_bit (
SLT_out,
R2,
R3
);
parameter word_size = 32;
input [word_size-1:0] R2, R3;
output SLT_out;
wire [word_size-1:0] SUB_out;
wire c_out;
SUB_n_bit #(word_size) S1 (
c_out,
{SLT_out, SUB_out[word_size-1:1]},
R2,
R3
);
endmodule
| 7.227191 |
module slt_operator (
X,
Y,
Z
);
//parameter definitions
parameter BUSSIZE = 32;
//port definitions - customize for different bit widths
input wire [BUSSIZE-1:0] X, Y;
output wire [BUSSIZE-1:0] Z;
wire overflow;
wire [BUSSIZE-1:0] out;
cla_adder_32bit SUB_op (
.A(X),
.B(~Y),
.S(out),
.C0(1),
.C32(),
.Pg(),
.Gg(),
.overflow(overflow)
);
assign Z[BUSSIZE-1:1] = 0;
assign Z[0] = overflow ? ~out[BUSSIZE-1] : out[BUSSIZE-1];
endmodule
| 7.103161 |
module SlvAxi4ProtConvAXI4ID #(
parameter [0:0] ZERO_SLAVE_ID = 1'b1, // zero ID field
parameter integer ID_WIDTH = 1, // number of bits for ID (ie AID, WID, BID) - valid 1-8
parameter integer SLV_AXI4PRT_ADDRDEPTH = 8 // Number transations width - 1 => 2 transations, 2 => 4 transations, etc.
) (
//===================================== Global Signals ========================================================================
input wire ACLK,
input wire sysReset,
// External side
//Slave Read Address Ports
output wire [ID_WIDTH-1:0] SLAVE_AID,
output wire SLAVE_AVALID,
input wire SLAVE_AREADY,
// Slave Read Data Ports
input wire [ID_WIDTH-1:0] SLAVE_ID,
output wire SLAVE_READY,
input wire SLAVE_VALID,
input wire SLAVE_LAST,
// Slave Read Address Ports
input wire [ID_WIDTH-1:0] int_slaveAID,
input wire int_slaveAVALID,
output wire int_slaveAREADY,
// Slave Read Data Ports
output wire [ID_WIDTH-1:0] int_slaveID,
output wire int_slaveVALID,
input wire int_slaveREADY
);
wire fifoEmpty;
wire fifoFull;
wire fifoNearlyFull;
wire [ID_WIDTH-1:0] IDFifoOut;
wire fifoWr;
wire fifoRd;
generate
if (ZERO_SLAVE_ID) begin
FIFO #(
.MEM_DEPTH(2 ** SLV_AXI4PRT_ADDRDEPTH),
.DATA_WIDTH_IN(ID_WIDTH),
.DATA_WIDTH_OUT(ID_WIDTH),
.NEARLY_FULL_THRESH((2 ** SLV_AXI4PRT_ADDRDEPTH) - 1),
.NEARLY_EMPTY_THRESH(0)
) rdata_interleave_fifo (
.rst(sysReset),
.clk(ACLK),
.wr_en(fifoWr),
.rd_en(fifoRd),
.data_in(int_slaveAID),
.data_out(IDFifoOut),
.zero_data(1'b0),
.fifo_full(fifoFull),
.fifo_empty(fifoEmpty),
.fifo_nearly_full(fifoNearlyFull),
.fifo_nearly_empty(),
.fifo_one_from_full()
);
assign fifoWr = int_slaveAREADY & int_slaveAVALID;
assign fifoRd = SLAVE_READY & SLAVE_VALID & SLAVE_LAST;
assign SLAVE_READY = ~fifoEmpty & int_slaveREADY;
assign SLAVE_AID = 0;
assign int_slaveID = IDFifoOut;
assign int_slaveAREADY = ~fifoNearlyFull & SLAVE_AREADY;
assign SLAVE_AVALID = int_slaveAVALID & ~fifoNearlyFull;
assign int_slaveVALID = SLAVE_VALID & ~fifoEmpty;
end else begin
assign int_slaveAREADY = SLAVE_AREADY;
assign SLAVE_AID = int_slaveAID;
assign int_slaveID = SLAVE_ID;
assign SLAVE_READY = int_slaveREADY;
assign SLAVE_AVALID = int_slaveAVALID;
assign int_slaveVALID = SLAVE_VALID;
end
endgenerate
endmodule
| 7.385033 |
modules library
// Project : vslzw
// -----------------------------------------------------------------------------
// File : slzw_lib.v
// Author : Simon Southwell
// Created : 2022-02-02
// Standard : Verilog 2001
// -----------------------------------------------------------------------------
// Description:
// This file contains the base utility modules for the SLZW codec
// -----------------------------------------------------------------------------
// Copyright (c) 2022 Simon Southwell
// -----------------------------------------------------------------------------
//
// This is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// It is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this code. If not, see <http://www.gnu.org/licenses/>.
//
// -----------------------------------------------------------------------------
`timescale 1ns / 10ps
// -----------------------------------------------------------------------------
// DEFINITIONS
// -----------------------------------------------------------------------------
`ifndef RESET
//`RESET
`define RESET or negedge reset_n
`endif
// -----------------------------------------------------------------------------
// Hash
// -----------------------------------------------------------------------------
module slzw_hash
(
input [12:0] code,
input [7:0] byte,
output [13:0] haddr
);
wire [13:0] num1 = {1'b0, byte[4:0], byte[7:0]};
wire [13:0] num2 = {1'b0, code[ 0], code[ 1], code[ 2], code[ 3],
code[ 4], code[ 5], code[ 6], code[ 7],
code[ 8], code[ 9], code[10], code[11],
code[12]};
assign haddr = num1 + num2;
endmodule
| 7.11392 |
module slzw_mem_occupied
#(parameter
MEMSIZE = 10240
)
(
input clk,
input reset_n,
input clr,
input [13:0] waddr,
input [13:0] raddr,
input set,
output occupied,
output busy
);
localparam OCCMEMSIZE = MEMSIZE/32;
reg [31:0] occmem [0:OCCMEMSIZE-1];
reg set_last;
reg [13:0] addr_last;
reg [31:0] rval;
reg clr_last;
reg [8:0] clr_count;
wire out_of_range = (waddr > (OCCMEMSIZE[13:0]-14'b1)) ? 1'b1 : 1'b0;
assign occupied = rval[waddr[4:0]] | (set_last && (addr_last == waddr)) | out_of_range;
assign busy = (clr_count > 9'h000);
always @ (posedge clk `RESET)
begin
if (reset_n == 1'b0)
begin
set_last <= 1'b0;
clr_last <= 1'b0;
clr_count <= 9'h000;
end
else
begin
// Carry some signals over to the next cycle
clr_last <= clr;
set_last <= set;
addr_last <= waddr;
// If a valid address, read the occupied flag memory
if (!out_of_range)
begin
rval <= occmem[raddr[13:5]];
end
// If a rising edge on the clear input, or already clearing, reset the memory
if ((clr && !clr_last && clr_count == 9'h000) || busy)
begin
occmem[clr_count] <= 32'h00000000;
clr_count <= clr_count + 9'h001;
if (clr_count == (OCCMEMSIZE[8:0]-9'd1))
begin
clr_count <= 9'h00;
end
end
// When not clearing, and setting an occupied bit, OR the
// relevant bit of the value just read with 1.
else if (set_last && !out_of_range)
begin
occmem[addr_last[13:5]] <= rval | (32'h1 << addr_last[4:0]);
end
end
end
endmodule
| 6.506855 |
module slzw_dictmem
#(parameter
MEMSIZE = 10240,
WIDTH = 8
)
(
input clk,
input [13:0] waddr,
input write,
input [WIDTH-1:0] wdata,
input [13:0] raddr,
output reg [WIDTH-1:0] rdata
);
reg [WIDTH-1:0] mem[0:MEMSIZE];
always @ (posedge clk)
begin
rdata <= mem[raddr];
if (write)
begin
mem[waddr] <= wdata;
end
end
endmodule
| 6.906678 |
module slzw_fifo
#(parameter
DEPTH = 8,
WIDTH = 32,
NEARLYFULL = (DEPTH/2)
)
(
input clk,
input reset_n,
input clr,
input write,
input [WIDTH-1:0] wdata,
input read,
output reg [WIDTH-1:0] rdata,
output reg empty,
output reg full,
output reg nearly_full
);
localparam LOG2DEPTH = $clog2(DEPTH);
reg [WIDTH-1:0] mem [0:DEPTH-1];
reg [LOG2DEPTH:0] wptr;
reg [LOG2DEPTH:0] rptr;
// The number of words in the FIFO is the write pointer minus the read pointer
wire [LOG2DEPTH:0] word_count = (wptr - rptr);
always @(posedge clk `RESET)
begin
if (reset_n == 1'b0)
begin
wptr <= {LOG2DEPTH{1'b0}};
rptr <= {LOG2DEPTH{1'b0}};
empty <= 1'b1;
full <= 1'b0;
nearly_full <= 1'b0;
end
else
begin
// If a write arrives, and not full, write to memory and update write pointer
if (write && ~full)
begin
mem[wptr[LOG2DEPTH-1:0]] <= wdata;
wptr <= wptr + 1;
end
// If a read arrives, and not empty, fetch data from memory and update read pointer
if (read && ~empty)
begin
rdata <= mem[rptr[LOG2DEPTH-1:0]];
rptr <= rptr + 1;
end
// If writing, but not reading, update full status when last space being written.
// The nearly full flag is asserted when about to reach the threshold, or is greater.
// A write (without read) always clears the empty flag
if (write & ~(read & ~empty))
begin
full <= (word_count == DEPTH-1) ? 1'b1 : 1'b0;
nearly_full <= (word_count >= NEARLYFULL-1) ? 1'b1 : 1'b0;
empty <= 1'b0;
end
// If reading (but not writing), update empty status when last data is being read.
// The nearly full flag is deasserted when about to drop below the threshold, or
// is smaller. A read (without a write), always clears the full status.
if (read & ~(write & ~full))
begin
empty <= (word_count == 1) ? 1'b1 : 1'b0;
nearly_full <= (word_count <= NEARLYFULL) ? 1'b0 : 1'b1;
full <= 1'b0;
end
end
end
endmodule
| 6.57222 |
module Sl_3 (
//Entradas
input [25:0] SLInp_3,
//Salidas
output reg [27:0] SLOut_3
);
//2- Delcaracion de señales --> NA(No aplica)
//3- Cuerpo del modulo
assign SLOut_3 = SLInp_3 << 2;
endmodule
| 6.942169 |
module is a very simple sequential machine that behaves based off
// a vending machine that only accepts nickels 'n' and dimes 'd' one input at a time.
// ALthough there is nothing preventing multiple inputs at the same time, there should
// only be ONE input per clock cycle.
// The output is achieved when 15 cents has been deposited (the fourth state is reached).
// This machine DOES NOT consider more than one output for the deposit.
module sm
( n,
d,
clk,
rst,
op,
state,
nstate
);
input n;
input d;
input clk;
input rst;
output op;
output [1:0] state;
output [1:0] nstate;
// 2 bit register allows for 4 states to be created in this state machine
reg [1:0] state;
reg [1:0] nstate;
reg op;
// Design implementation
//reset and update state
always @( posedge rst or posedge clk )
begin //if this were (*) it would be updating every 1ps (timescale). This would not work. So what we do it
if ( rst ) //update it at every positive edge of the rst or clk. When it goes from 0 to 1.
begin
state <= 2'b00;
nstate <= 2'b00;
end
else
state <= nstate;
end
//calculating the next state
always @( state or d or n )
begin
case ( state )
2'b00: if ( n )
nstate <= 2'b01;
else if ( d )
nstate <= 2'b10;
2'b01: if ( n )
nstate <= 2'b10;
else if ( d )
nstate <= 2'b11;
2'b10: if ( n )
nstate <= 2'b11;
else if ( d )
nstate <= 2'b11;
2'b11: if ( n )
nstate <= 2'b01;
else if ( d )
nstate <= 2'b10;
else
nstate <= 2'b00;
default: nstate <= 2'b00;
endcase
end
//output
always @( state )
begin
case ( state )
2'b11: op <= 1'b1;
default: op <= 1'b0;
endcase
end
endmodule
| 6.962172 |
module SM1 (
output wire RO_ENABLE,
output wire WR_ENABLE,
input wire DAVAIL,
input wire ROREQUEST,
input wire TRIGGER,
input wire clk,
input wire RODONE_n,
input wire rst
);
// state bits
parameter IDLE = 3'b000, // extra=0 WR_ENABLE=0 RO_ENABLE=0
ADC_RUNNING = 3'b010, // extra=0 WR_ENABLE=1 RO_ENABLE=0
READOUT = 3'b001, // extra=0 WR_ENABLE=0 RO_ENABLE=1
TRIGGERED = 3'b100; // extra=1 WR_ENABLE=0 RO_ENABLE=0
reg [2:0] state;
reg [2:0] nextstate;
// comb always block
always @* begin
nextstate = state; // default to hold value because implied_loopback is set
case (state)
IDLE: begin
if (DAVAIL) begin
nextstate = ADC_RUNNING;
end
end
ADC_RUNNING: begin
if (TRIGGER) begin
nextstate = TRIGGERED;
end else if (!DAVAIL) begin
nextstate = IDLE;
end
end
READOUT: begin
//if (ROREQUEST) begin
if (RODONE_n) begin
nextstate = READOUT;
end else if (DAVAIL) begin
nextstate = ADC_RUNNING;
end else if (!DAVAIL) begin
nextstate = IDLE;
end
end
TRIGGERED: begin
if (ROREQUEST) begin
nextstate = READOUT;
end
end
endcase
end
// Assign reg'd outputs to state bits
assign RO_ENABLE = state[0];
assign WR_ENABLE = state[1];
// sequential always block
always @(posedge clk) begin
if (rst) state <= IDLE;
else state <= nextstate;
end
// This code allows you to see state names in simulation
`ifndef SYNTHESIS
reg [87:0] statename;
always @* begin
case (state)
IDLE: statename = "IDLE";
ADC_RUNNING: statename = "ADC_RUNNING";
READOUT: statename = "READOUT";
TRIGGERED: statename = "TRIGGERED";
default: statename = "XXXXXXXXXXX";
endcase
end
`endif
endmodule
| 7.554918 |
modules for a point ( for motor ) one coming from lfr module and second turn
// so this module is to filter those signals
module SM1511_FILTER(
input clk_50,node,
input [7:0]lfr,
input [7:0]nd,
output [7:0] speed
);
reg [7:0] speed2;
assign speed = speed2;
always @(posedge clk_50)
begin
if(node == 0)
speed2=lfr;
else
speed2=nd;
end
endmodule
| 6.505147 |
module sm2201_interface_board
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// Test scenario:
// 1. Read from register 106 (~7us) multiple times
// 2. Possibly we are expect that on isa data will be all 0
////////////////////////////////////////////////////////////////////////////////
module sm2201_interface_board_bus_passivity_testbench;
// isa input signals
reg isa_clk;
reg isa_ior;
reg isa_iow;
reg isa_reset;
reg isa_ale;
reg isa_aen;
wire q_r_debug;
reg [9:0] isa_addr;
wire [7:0] isa_data;
reg [31:0] counter;
reg [1:0] operation; // 0 - read, 1 - write
reg [31:0] state;
wire cb_b_b1;
// isa output signals
wire [7:0] isa_irq;
wire isa_chrdy;
// CAMAC input signals
reg cb_prr;
reg cb_zk4;
wire [15:0] cb_data;
reg [15:0] cb_data_out;
//wire [15:0] cb_data_in;
//reg [15:0] cb_data_in_buffer;
wire [11:0] cb_addr;
reg [7:0] isa_data_out;
//wire [7:0] isa_data_in;
assign cb_data = cb_b_b1 == 1'b1 ? cb_data_out : 16'b0000000000000000; //cb_data_in;
//assign isa_data = q_r_debug == 1'b1 ? isa_data_out : 8'bz;// isa_data_in;
//assign cb_data_in = cb_data_in_buffer;
localparam reg[31:0] WRITE_ADDR_INT_REG_READY = 0;
localparam reg[31:0] WRITE_ADDR_INT_REG_SEND = 1;
// Instantiate the Unit Under Test (UUT)
sm2201_interface_board
uut (
// isa inputs
.isa_clk(isa_clk),
.isa_reset(isa_reset),
.isa_ior(isa_ior),
.isa_iow(isa_iow),
.isa_addr(isa_addr),
.isa_data(isa_data),
.isa_ale(isa_ale),
.isa_aen(isa_aen),
// isa outputs
.isa_chrdy(isa_chrdy),
// debug
.q_r_debug(q_r_debug),
// CAMAC inputs
.cb_prr(cb_prr),
.cb_zk4(cb_zk4),
.cb_cx1(cb_cx1),
.cb_data(cb_data),
.cb_addr(cb_addr),
.cb_b_b1(cb_b_b1)
);
initial
begin
// initial ISA
isa_reset <= 0;
isa_clk <= 0;
isa_ior <= 1;
isa_iow <= 1;
isa_addr <= 34;
isa_ale <= 0;
isa_aen <= 0;
// initial CAMAC
cb_prr <= 1;
cb_zk4 <= 1;
isa_data_out <= 16'b0000000000000000;
cb_data_out <= //16'b0000000000000000;
16'b1111111111111111; // because we have opened inputs
//cb_data_in_buffer <= 8'b00000000;
counter <= 0;
operation <= 0;
end
// we are model ISA logic
always
begin
#75 isa_clk <= ~isa_clk;
#150 counter <= counter + 1;
if (counter == 100)
begin
isa_addr <= 262; // 106h
isa_ale <= 1'b1;
end
if (counter == 110)
isa_ale <= 1'b0;
if (counter == 120)
isa_ior <= 1'b0;
if (counter == 200)
isa_ior <= 1'b1;
end
endmodule
| 6.62461 |
module sm2201_interface_board
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sm2201_interface_board_testbench;
// isa input signals
reg isa_clk;
reg isa_ior;
wire isa_iow;
reg isa_reset;
reg isa_ale;
reg isa_aen;
wire q_r_debug;
reg [9:0] isa_addr;
wire [7:0] isa_data;
reg [31:0] counter;
reg [1:0] operation; // 0 - read, 1 - write
// isa output signals
wire [7:0] isa_irq;
wire isa_chrdy;
// CAMAC input signals
reg cb_prr;
reg cb_zk4;
wire [15:0] cb_data;
reg [15:0] cb_data_out;
wire [15:0] cb_data_in;
wire [11:0] cb_addr;
reg [7:0] isa_data_out;
wire [7:0] isa_data_in;
assign cb_data = q_r_debug == 1'b0 ? cb_data_out : cb_data_in;//16'b0000000000000000;
assign isa_data = q_r_debug == 1'b1 ? isa_data_out :isa_data_in;//8'b1010001;
assign isa_iow = ~ isa_ior;
// Instantiate the Unit Under Test (UUT)
sm2201_interface_board
uut (
// isa inputs
.isa_clk(isa_clk),
.isa_reset(isa_reset),
.isa_ior(isa_ior),
.isa_iow(isa_iow),
.isa_addr(isa_addr),
.isa_data(isa_data),
.isa_ale(isa_ale),
.isa_aen(isa_aen),
// isa outputs
.isa_chrdy(isa_chrdy),
// debug
.q_r_debug(q_r_debug),
// CAMAC inputs
.cb_prr(cb_prr),
.cb_zk4(cb_zk4),
.cb_cx1(cb_cx1),
.cb_data(cb_data),
.cb_addr(cb_addr)
);
initial
begin
// initial ISA
isa_reset <= 0;
isa_clk <= 0;
isa_ior <= 1;
isa_addr <= 240;
isa_ale <= 0;
isa_aen <= 0;
// initial CAMAC
cb_prr <= 1;
cb_zk4 <= 1;
isa_data_out <= 8'b00011000;
cb_data_out <= 16'b1111111111111111;
counter <= 0;
operation <= 0;
end
// we are model ISA logic
always
begin
#60 isa_clk <= ~isa_clk;
#120 counter <= counter + 1;
// ISA ALE, IOR, IOW generation
if (counter == 10)
begin
isa_ale <= 1;
end
else if (counter == 20)
begin
if (operation == 0)
isa_ior <= 0;
end
else if (counter == 44)
begin
isa_ale <= 0;
end
else if (counter == 146)
begin
if (operation == 0)
isa_ior <= 1;
counter <= 10;
operation <= operation + 1;
if (operation == 1)
begin
isa_addr <= isa_addr + 1;
operation <= 0;
end
// isa addresses range from 100-13E
if (isa_addr == 318)
begin
isa_addr <= 256;
end
end
end
endmodule
| 6.62461 |
module sm2201_interface_board
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// Test scenario:
// 1. Write CAMAC crate + station number TO Address and Interrupt register (ISA Addr 106h)
// 2.
// 3.
// 4.
// 5.
////////////////////////////////////////////////////////////////////////////////
module sm2201_interface_read_camac_testbench;
// isa input signals
reg isa_clk;
reg isa_ior;
reg isa_iow;
reg isa_reset;
reg isa_ale;
wire isa_aen;
wire q_r_debug;
reg [9:0] isa_addr;
wire [7:0] isa_data;
reg [31:0] counter;
reg [1:0] operation; // 0 - read, 1 - write
reg [31:0] state;
wire cb_b_b1;
// isa output signals
wire [7:0] isa_irq;
wire isa_chrdy;
// CAMAC input signals
reg cb_prr;
reg cb_zk4;
wire [15:0] cb_data;
reg [15:0] cb_data_out;
//wire [15:0] cb_data_in;
//reg [15:0] cb_data_in_buffer;
wire [11:0] cb_addr;
reg [7:0] isa_data_out;
//wire [7:0] isa_data_in;
assign cb_data = cb_b_b1 == 1'b1 ? cb_data_out : 16'bz; //cb_data_in;
assign isa_data = q_r_debug == 1'b1 ? isa_data_out : 8'bz;// isa_data_in;
assign isa_aen = isa_ale;
//assign cb_data_in = cb_data_in_buffer;
localparam reg[31:0] WRITE_ADDR_INT_REG_READY = 0;
localparam reg[31:0] WRITE_ADDR_INT_REG_SEND = 1;
// Instantiate the Unit Under Test (UUT)
sm2201_interface_board
uut (
// isa inputs
.isa_clk(isa_clk),
.isa_reset(isa_reset),
.isa_ior(isa_ior),
.isa_iow(isa_iow),
.isa_addr(isa_addr),
.isa_data(isa_data),
.isa_ale(isa_ale),
.isa_aen(isa_aen),
// isa outputs
.isa_chrdy(isa_chrdy),
// debug
.q_r_debug(q_r_debug),
// CAMAC inputs
.cb_prr(cb_prr),
.cb_zk4(cb_zk4),
.cb_cx1(cb_cx1),
.cb_data(cb_data),
.cb_addr(cb_addr),
.cb_b_b1(cb_b_b1)
);
initial
begin
// initial ISA
isa_reset <= 0;
isa_clk <= 0;
isa_ior <= 1;
isa_iow <= 1;
isa_addr <= 240;
isa_ale <= 0;
// initial CAMAC
cb_prr <= 1;
cb_zk4 <= 1;
isa_data_out <= 16'b0000000000000000;
cb_data_out <= 16'b1100001000111000;
//cb_data_in_buffer <= 8'b00000000;
counter <= 0;
operation <= 0;
end
// we are model ISA logic
always
begin
#60 isa_clk <= ~isa_clk;
#120 counter <= counter + 1;
// ISA ALE
if (counter == 50)
begin
isa_ale <= 1;
end
if (counter == 84)
begin
isa_ale <= 0;
end
if (counter > 85 && counter < 186)
begin
if (counter == 86)
begin
operation <= 1'b1;
isa_addr <= 262; // 106h
isa_iow <= 1'b0;
isa_data_out <= 8'b10100110;
end
if (counter == 115)
begin
isa_iow <= 1'b1;
end
if (counter == 155)
begin
isa_addr <= 263;//308; // 2nd byte
isa_iow <= 1'b0;
isa_data_out <= 8'b00000000;
end
if (counter == 180)
begin
isa_iow <= 1'b1;
end
// todo: switch addr and isa data possibly
end
if (counter == 190)
begin
counter <= 0;
end
end
endmodule
| 6.62461 |
module sm3_core (
input i_clk, //clock
input i_rst, //reset high valid
input i_start, //high valid(only one clock)
input [511:0] i_data, //hash data input
input [255:0] i_vin, //hash init value input(not change before o_done valid)
output [255:0] o_vout, //hash value output
output o_done
); //high valid(only one clock)
localparam DLY = 1;
wire [31:0] A, B, C, D, E, F, G, H;
wire [31:0] W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15;
wire [31:0] W16x, W16, W0j, SS1x, SS1, SS2, TT1, TT2, Tjl;
reg [31:0] r_A, r_B, r_C, r_D, r_E, r_F, r_G, r_H, r_Tjl;
reg [511:0] r_W;
reg [6:0] r_cnt;
wire s_busy;
assign {A, B, C, D, E, F, G, H} = i_start ? i_vin : {r_A, r_B, r_C, r_D, r_E, r_F, r_G, r_H};
assign {W0, W1, W2, W3, W4, W5, W6, W7} = i_start ? i_data[511:256] : r_W[511:256];
assign {W8, W9, W10, W11, W12, W13, W14, W15} = i_start ? i_data[255:0] : r_W[255:0];
assign W16x = W0 ^ W7 ^ {W13[16:0], W13[31:17]};
assign W16 = (W16x^{W16x[16:0],W16x[31:17]}^{W16x[8:0],W16x[31:9]})^{W3[24:0],W3[31:25]}^W10;
assign W0j = W0 ^ W4;
assign Tjl = i_start ? 32'h79cc4519 : r_Tjl;
assign SS1x = {A[19:0], A[31:20]} + E + Tjl;
assign SS1 = {SS1x[24:0], SS1x[31:25]};
assign SS2 = SS1 ^ {A[19:0], A[31:20]};
assign TT1 = (r_cnt<=7'd15) ? ((A^B^C)+D+SS2+W0j) : (((A&B)|(A&C)|(B&C))+D+SS2+W0j);
assign TT2 = (r_cnt<=7'd15) ? ((E^F^G)+H+SS1+W0) : (((E&F)|((~E)&G))+H+SS1+W0);
always @(posedge i_clk) begin
if (i_rst) begin
r_A <= #DLY 32'd0;
r_B <= #DLY 32'd0;
r_C <= #DLY 32'd0;
r_D <= #DLY 32'd0;
r_E <= #DLY 32'd0;
r_F <= #DLY 32'd0;
r_G <= #DLY 32'd0;
r_H <= #DLY 32'd0;
end else if (s_busy) begin
r_D <= #DLY C;
r_C <= #DLY{B[22:0], B[31:23]};
r_B <= #DLY A;
r_A <= #DLY TT1;
r_H <= #DLY G;
r_G <= #DLY{F[12:0], F[31:13]};
r_F <= #DLY E;
r_E <= #DLY(TT2 ^ {TT2[22:0], TT2[31:23]} ^ {TT2[14:0], TT2[31:15]});
end
end
always @(posedge i_clk) begin
if (i_rst) r_W <= #DLY 512'd0;
else if (s_busy)
r_W <= #DLY{W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, W16};
end
always @(posedge i_clk) begin
if (i_rst) r_cnt <= #DLY 7'd0;
else if (i_start) r_cnt <= #DLY 7'd1;
else if ((r_cnt != 7'd0) && (r_cnt != 7'd64)) r_cnt <= #DLY r_cnt + 7'd1;
else r_cnt <= #DLY 7'd0;
end
always @(posedge i_clk) begin
if (i_rst) r_Tjl <= #DLY 32'h0;
else if (r_cnt == 7'd15) r_Tjl <= #DLY 32'h9d8a7a87; //32'h7a879d8a<<16;
else if (s_busy) r_Tjl <= #DLY{Tjl[30:0], Tjl[31]};
end
assign s_busy = ((r_cnt != 7'd0) || (i_start == 1'b1)) ? 1'b1 : 1'b0;
assign o_done = (r_cnt == 7'd64) ? 1'b1 : 1'b0;
assign o_vout = (r_cnt == 7'd64) ? i_vin ^ {A, B, C, D, E, F, G, H} : 256'b0;
endmodule
| 6.644136 |
module sm4_core (
input i_clk,
input i_rst,
input i_flag, //1-encrypt,0-decrypt
input [127:0] i_key,
input i_key_en,
output o_key_ok,
input [127:0] i_din,
input i_din_en,
output [127:0] o_dout,
output o_dout_en
);
wire [ 31:0] s_sbox_din_ke;
wire [ 31:0] s_sbox_din_dp;
wire [ 31:0] s_sbox_din;
wire [ 31:0] s_sbox_dout;
wire [1023:0] s_exkey;
//key expand
sm4_keyex u_keyex (
.i_clk (i_clk ),
.i_rst (i_rst ),
.i_key (i_key ),
.i_key_en (i_key_en ),
.o_exkey (s_exkey ),
.o_key_ok (o_key_ok ),
.o_sbox_use (s_sbox_use_ke ),
.o_sbox_din (s_sbox_din_ke ),
.i_sbox_dout(s_sbox_dout )
);
//data encrypt or decrypt
sm4_dpc u_dpc (
.i_clk (i_clk ),
.i_rst (i_rst ),
.i_flag (i_flag ),
.i_keyex (s_exkey ),
.i_din (i_din ),
.i_din_en (i_din_en ),
.o_dout (o_dout ),
.o_dout_en (o_dout_en ),
.o_sbox_din (s_sbox_din_dp ),
.i_sbox_dout(s_sbox_dout )
);
//s-core subbytes
assign s_sbox_din = (s_sbox_use_ke == 1'b1) ? s_sbox_din_ke : s_sbox_din_dp;
sm4_sbox u_sm4_sbox0 (
.din (s_sbox_din[7:0]),
.dout(s_sbox_dout[7:0])
);
sm4_sbox u_sm4_sbox1 (
.din (s_sbox_din[15:8]),
.dout(s_sbox_dout[15:8])
);
sm4_sbox u_sm4_sbox2 (
.din (s_sbox_din[23:16]),
.dout(s_sbox_dout[23:16])
);
sm4_sbox u_sm4_sbox3 (
.din (s_sbox_din[31:24]),
.dout(s_sbox_dout[31:24])
);
endmodule
| 6.794798 |
module sm4_dpc (
input i_clk,
input i_rst,
input i_flag, //1-encrpt,0-decrypt
input [1023:0] i_keyex,
input [ 127:0] i_din,
input i_din_en,
output [ 127:0] o_dout,
output o_dout_en,
output [ 31:0] o_sbox_din,
input [ 31:0] i_sbox_dout
);
localparam DLY = 1;
reg [4:0] r_count;
reg [127:0] r_din;
reg [1023:0] r_keyex;
wire [127:0] s_din;
wire [31:0] s_ikey;
wire [31:0] s_rkey;
function [127:0] SWAP;
input [127:0] D;
begin
SWAP = {D[31:0], D[63:32], D[95:64], D[127:96]};
end
endfunction
function [31:0] L;
input [31:0] D;
begin
L = D ^ {D[29:0], D[31:30]} ^ {D[21:0], D[31:22]} ^ {D[13:0], D[31:14]} ^ {D[7:0], D[31:8]};
end
endfunction
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) r_count <= #DLY 5'b0;
else if (i_din_en) r_count <= #DLY 5'd1;
else if (r_count != 5'd0) r_count <= #DLY r_count + 5'd1;
end
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) r_keyex <= #DLY 1024'b0;
else if (i_din_en) begin
if (i_flag) r_keyex <= #DLY{i_keyex[32*31-1:0], 32'b0};
else r_keyex <= #DLY{32'b0, i_keyex[32*32-1:32]};
end else if (r_count != 5'd0) begin
if (i_flag) r_keyex <= #DLY{r_keyex[32*31-1:0], 32'b0};
else r_keyex <= #DLY{32'b0, r_keyex[32*32-1:32]};
end
end
assign s_ikey = i_flag ? i_keyex[32*32-1:32*31] : i_keyex[31:0];
assign s_rkey = i_flag ? r_keyex[32*32-1:32*31] : r_keyex[31:0];
assign s_din = i_din_en ? i_din : r_din;
assign o_sbox_din = i_din_en ? (s_ikey^s_din[127:96]^s_din[95:64]^s_din[63:32]):(s_rkey^s_din[127:96]^s_din[95:64]^s_din[63:32]);
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) r_din <= #DLY 128'b0;
else r_din <= #DLY{L(i_sbox_dout) ^ s_din[31:0], s_din[127:32]};
end
assign o_dout = SWAP({L(i_sbox_dout) ^ s_din[31:0], s_din[127:32]});
assign o_dout_en = (r_count == 5'd31) ? 1'b1 : 1'b0;
endmodule
| 7.382222 |
module sm4_keyex (
input i_clk,
input i_rst,
input [ 127:0] i_key, //key
input i_key_en, //key init flag
output [128*8-1:0] o_exkey, //round key
output o_key_ok, //key init ok
output o_sbox_use,
output [ 31:0] o_sbox_din,
input [ 31:0] i_sbox_dout
);
localparam DLY = 1;
localparam [127:0] FK = {32'hb27022dc, 32'h677d9197, 32'h56aa3350, 32'ha3b1bac6};
reg [ 4:0] r_count;
reg [1023:0] r_exkey;
reg [ 127:0] r_key;
reg r_key_ok;
wire [ 127:0] s_key;
wire [ 31:0] s_rk_next;
wire [ 31:0] s_ck;
wire s_busy;
function [31:0] Lr;
input [31:0] D;
begin
Lr = D ^ {D[18:0], D[31:19]} ^ {D[8:0], D[31:9]};
end
endfunction
;
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) begin
r_exkey <= #DLY 1024'b0;
end else if (s_busy) begin
r_exkey <= #DLY{r_exkey[32*31-1:0], s_rk_next};
end
end
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) r_count <= #DLY 5'd0;
else if (i_key_en) r_count <= #DLY 5'd1;
else if (r_count != 4'd0) r_count <= #DLY r_count + 5'd1;
end
assign s_busy = ((r_count != 5'd0) || (i_key_en == 1'b1)) ? 1'b1 : 1'b0;
assign s_key = i_key_en ? i_key ^ FK : r_key;
assign s_rk_next = s_key[31:0] ^ Lr(i_sbox_dout);
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) r_key <= #DLY 128'b0;
else if (s_busy) r_key <= #DLY{s_rk_next, s_key[127:32]};
end
//Round CK
sm4_ck u_ck (
.round(r_count),
.dout (s_ck)
);
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) r_key_ok <= #DLY 1'b0;
else if (i_key_en) r_key_ok <= #DLY 1'b0;
else if (r_count == 5'd31) r_key_ok <= #DLY 1'b1;
end
assign o_key_ok = r_key_ok & (~i_key_en);
assign o_exkey = r_exkey;
assign o_sbox_din = s_key[127:96] ^ s_key[95:64] ^ s_key[63:32] ^ s_ck;
assign o_sbox_use = s_busy;
endmodule
| 8.347973 |
module
//
// Finds arithmetic operations needed. Latches on the positive edge of the
// clock. There are 8 different types of operations, which come from bits
// 3-5 of the instruction.
//
module alu(res, opra, oprb, cin, cout, zout, sout, parity, auxcar, sel);
input [7:0] opra; // Input A
input [7:0] oprb; // Input B
input cin; // Carry in
output cout; // Carry out
output zout; // Zero out
output sout; // Sign out
output parity; // parity
output auxcar; // auxiliary carry
input [2:0] sel; // Operation select
output [7:0] res; // Result of alu operation
reg cout; // Carry out
reg zout; // Zero out
reg sout; // sign out
reg parity; // parity
reg auxcar; // auxiliary carry
reg [7:0] resi; // Result of alu operation intermediate
reg [7:0] res; // Result of alu operation
always @(opra, oprb, cin, sel, res, resi) begin
case (sel)
`aluop_add: begin // add
{ cout, resi } = opra+oprb; // find result and carry
// auxcar = ((opra[3:0]+oprb[3:0]) >> 4) & 1'b1; // find auxiliary carry
// if ((opra[3:0]+oprb[3:0])>>4) auxcar=1'b1; else auxcar=1'b0;
auxcar = (((opra[3:0]+oprb[3:0]) >> 4) & 1'b1) ? 1'b1 : 1'b0 ; // find auxiliary carry
end
`aluop_adc: begin // adc
{ cout, resi } = opra+oprb+cin; // find result and carry
auxcar = (((opra[3:0]+oprb[3:0]+cin) >> 4) & 1'b1) ? 1'b1 : 1'b0; // find auxiliary carry
end
`aluop_sub, `aluop_cmp: begin // sub/cmp
{ cout, resi } = opra-oprb; // find result and carry
auxcar = (((opra[3:0]-oprb[3:0]) >> 4) & 1'b1) ? 1'b1 : 1'b0; // find auxiliary borrow
end
`aluop_sbb: begin // sbb
{ cout, resi } = opra-oprb-cin; // find result and carry
auxcar = (((opra[3:0]-oprb[3:0]-cin >> 4)) & 1'b1) ? 1'b1 : 1'b0; // find auxiliary borrow
end
`aluop_and: begin // ana
{ cout, resi } = {1'b0, opra&oprb}; // find result and carry
auxcar = 1'b0; // clear auxillary carry
end
`aluop_xor: begin // xra
{ cout, resi } = {1'b0, opra^oprb}; // find result and carry
auxcar = 1'b0; // clear auxillary carry
end
`aluop_or: begin // ora
{ cout, resi } = {1'b0, opra|oprb}; // find result and carry
auxcar = 1'b0; // clear auxillary carry
end
endcase
if (sel != `aluop_cmp) res = resi; else res = opra;
zout <= ~|resi; // set zero flag from result
sout <= resi[7]; // set sign flag from result
parity <= ~^resi; // set parity flag from result
end
endmodule
| 7.196583 |
module smadder #(
parameter N = 4
) (
input wire [N-1:0] a,
b,
output reg [N-1:0] sum
);
reg [N-2:0] mag_a, mag_b, mag_sum, max, min;
reg sgn_a, sgn_b, sgn_sum;
always @* begin
mag_a = a[N-2:0];
mag_b = b[N-2:0];
sgn_a = a[N-1];
sgn_b = b[N-1];
// GET Min & Max
if (mag_a > mag_b) begin
max = mag_a;
min = mag_b;
sgn_sum = sgn_a;
end else begin
max = mag_b;
min = mag_a;
sgn_sum = sgn_b;
end
if (sgn_a == sgn_b) mag_sum = max + min;
else mag_sum = max - min;
sum = {sgn_sum, mag_sum};
end
endmodule
| 6.550301 |
module mux4 (
din_0, // Mux first input
din_1, // Mux Second input
din_2, // Mux Thirsd input
din_3, // Mux Fourth input
sel, // Select input
mux_out // Mux output
);
//-----------Input Ports---------------
input din_0, din_1, din_2, din_3;
input [1:0] sel;
//-----------Output Ports---------------
output mux_out;
//------------Internal Variables--------
reg mux_out;
reg mid01, mid23;
//-------------Code Starts Here---------
mux2 mux1 (
.din_0(din_0),
.din_1(din_1),
.sel(sel[0]),
.mux_out(mid01)
);
mux2 mux2 (
.din_0(din_2),
.din_1(din_3),
.sel(sel[0]),
.mux_out(mid23)
);
mux2 mux12 (
.din_0(mid01),
.din_1(mid23),
.sel(sel[1]),
.mux_out(mux_out)
);
endmodule
| 6.593444 |
module SMALL14_CPU_reset_clk_0_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else data_out <= data_in_d1;
end
endmodule
| 7.049085 |
module smallALU (
in_0,
in_1,
out, // difference e1 and e2
sign_out // if e1 > e2 sign = 0 else = 1
);
input [7:0] in_0;
input [7:0] in_1;
output [7:0] out;
output sign_out;
wire [7:0] out_12, out_21;
wire cout_12, cout_21;
FS_8 FS_EXP_12 (
.a(in_0),
.b(in_1),
.cin(1'b0),
.out(out_12),
.cout(cout_12)
);
FS_8 FS_EXP_21 (
.a(in_1),
.b(in_0),
.cin(1'b0),
.out(out_21),
.cout(cout_21)
);
assign out = ({8{!cout_12}} & (out_12)) | ({8{cout_12}} & (out_21)); // differnence e1-e2
assign sign_out = cout_12;
endmodule
| 7.961141 |
module smallALU_CLA (
in_0,
in_1,
out, // difference e1 and e2
sign_out // if e1 > e2 sign = 0 else = 1
);
input [7:0] in_0;
input [7:0] in_1;
output [7:0] out;
output sign_out;
wire [7:0] out_12, out_21;
wire cout_12, cout_21;
SUB_CLA_8 SUB_CLA_EXP_12 (
.iA(in_0),
.iB(in_1),
.iC(1'b0),
.oS(out_12),
.oC(cout_12),
.oP(),
.oG()
);
SUB_CLA_8 SUB_CLA_EXP_21 (
.iA(in_1),
.iB(in_0),
.iC(1'b0),
.oS(out_21),
.oC(cout_21),
.oP(),
.oG()
);
assign out = ({8{!cout_12}} & (out_12)) | ({8{cout_12}} & (out_21)); // differnence e1-e2
assign sign_out = cout_12;
endmodule
| 7.432032 |
module IntXbar_4 (
input auto_int_in_3_0,
input auto_int_in_2_0,
input auto_int_in_1_0,
input auto_int_in_1_1,
input auto_int_in_0_0,
output auto_int_out_0,
output auto_int_out_1,
output auto_int_out_2,
output auto_int_out_3,
output auto_int_out_4,
output [29:0] io_covSum,
output metaAssert
);
wire [29:0] IntXbar_4_covSum;
assign auto_int_out_0 = auto_int_in_0_0; // @[LazyModule.scala 173:49]
assign auto_int_out_1 = auto_int_in_1_0; // @[LazyModule.scala 173:49]
assign auto_int_out_2 = auto_int_in_1_1; // @[LazyModule.scala 173:49]
assign auto_int_out_3 = auto_int_in_2_0; // @[LazyModule.scala 173:49]
assign auto_int_out_4 = auto_int_in_3_0; // @[LazyModule.scala 173:49]
assign IntXbar_4_covSum = 30'h0;
assign io_covSum = IntXbar_4_covSum;
assign metaAssert = 1'h0;
endmodule
| 6.908358 |
module BundleBroadcast (
input auto_in_0_clock,
output auto_out_0_clock,
output [29:0] io_covSum,
output metaAssert
);
wire [29:0] BundleBroadcast_covSum;
assign auto_out_0_clock = auto_in_0_clock; // @[LazyModule.scala 173:49]
assign BundleBroadcast_covSum = 30'h0;
assign io_covSum = BundleBroadcast_covSum;
assign metaAssert = 1'h0;
endmodule
| 6.590851 |
module IntSyncCrossingSink (
input clock,
input auto_in_sync_0,
output auto_out_0,
output [29:0] io_covSum,
output metaAssert,
input metaReset,
input SynchronizerShiftReg_w1_d3_halt
);
wire SynchronizerShiftReg_w1_d3_clock; // @[ShiftReg.scala 47:23]
wire SynchronizerShiftReg_w1_d3_io_d; // @[ShiftReg.scala 47:23]
wire SynchronizerShiftReg_w1_d3_io_q; // @[ShiftReg.scala 47:23]
wire [29:0] SynchronizerShiftReg_w1_d3_io_covSum; // @[ShiftReg.scala 47:23]
wire SynchronizerShiftReg_w1_d3_metaAssert; // @[ShiftReg.scala 47:23]
wire SynchronizerShiftReg_w1_d3_metaReset; // @[ShiftReg.scala 47:23]
wire [29:0] IntSyncCrossingSink_covSum;
wire [29:0] SynchronizerShiftReg_w1_d3_sum;
wire SynchronizerShiftReg_w1_d3_metaAssert_wire;
SynchronizerShiftReg_w1_d3 SynchronizerShiftReg_w1_d3 ( // @[ShiftReg.scala 47:23]
.clock(SynchronizerShiftReg_w1_d3_clock),
.io_d(SynchronizerShiftReg_w1_d3_io_d),
.io_q(SynchronizerShiftReg_w1_d3_io_q),
.io_covSum(SynchronizerShiftReg_w1_d3_io_covSum),
.metaAssert(SynchronizerShiftReg_w1_d3_metaAssert),
.metaReset(SynchronizerShiftReg_w1_d3_metaReset)
);
assign auto_out_0 = SynchronizerShiftReg_w1_d3_io_q; // @[LazyModule.scala 173:49]
assign SynchronizerShiftReg_w1_d3_clock = clock;
assign SynchronizerShiftReg_w1_d3_io_d = auto_in_sync_0; // @[ShiftReg.scala 49:16]
assign IntSyncCrossingSink_covSum = 30'h0;
assign SynchronizerShiftReg_w1_d3_sum = IntSyncCrossingSink_covSum + SynchronizerShiftReg_w1_d3_io_covSum;
assign io_covSum = SynchronizerShiftReg_w1_d3_sum;
assign SynchronizerShiftReg_w1_d3_metaAssert_wire = SynchronizerShiftReg_w1_d3_metaAssert;
assign metaAssert = SynchronizerShiftReg_w1_d3_metaAssert_wire;
assign SynchronizerShiftReg_w1_d3_metaReset = metaReset | SynchronizerShiftReg_w1_d3_halt;
endmodule
| 6.689384 |
module IntSyncCrossingSink_1 (
input auto_in_sync_0,
input auto_in_sync_1,
output auto_out_0,
output auto_out_1,
output [29:0] io_covSum,
output metaAssert
);
wire [29:0] IntSyncCrossingSink_1_covSum;
assign auto_out_0 = auto_in_sync_0; // @[LazyModule.scala 173:49]
assign auto_out_1 = auto_in_sync_1; // @[LazyModule.scala 173:49]
assign IntSyncCrossingSink_1_covSum = 30'h0;
assign io_covSum = IntSyncCrossingSink_1_covSum;
assign metaAssert = 1'h0;
endmodule
| 6.689384 |
module IntSyncCrossingSink_2 (
input auto_in_sync_0,
output auto_out_0,
output [29:0] io_covSum,
output metaAssert
);
wire [29:0] IntSyncCrossingSink_2_covSum;
assign auto_out_0 = auto_in_sync_0; // @[LazyModule.scala 173:49]
assign IntSyncCrossingSink_2_covSum = 30'h0;
assign io_covSum = IntSyncCrossingSink_2_covSum;
assign metaAssert = 1'h0;
endmodule
| 6.689384 |
module HellaCacheArbiter (
output io_requestor_0_req_ready,
input io_requestor_0_req_valid,
input [39:0] io_requestor_0_req_bits_addr,
input io_requestor_0_s1_kill,
output io_requestor_0_s2_nack,
output io_requestor_0_resp_valid,
output [63:0] io_requestor_0_resp_bits_data,
output io_requestor_0_s2_xcpt_ae_ld,
input io_mem_req_ready,
output io_mem_req_valid,
output [39:0] io_mem_req_bits_addr,
output io_mem_s1_kill,
input io_mem_s2_nack,
input io_mem_resp_valid,
input [63:0] io_mem_resp_bits_data,
input io_mem_s2_xcpt_ae_ld,
output [29:0] io_covSum,
output metaAssert
);
wire [29:0] HellaCacheArbiter_covSum;
assign io_requestor_0_req_ready = io_mem_req_ready; // @[HellaCacheArbiter.scala 17:12]
assign io_requestor_0_s2_nack = io_mem_s2_nack; // @[HellaCacheArbiter.scala 17:12]
assign io_requestor_0_resp_valid = io_mem_resp_valid; // @[HellaCacheArbiter.scala 17:12]
assign io_requestor_0_resp_bits_data = io_mem_resp_bits_data; // @[HellaCacheArbiter.scala 17:12]
assign io_requestor_0_s2_xcpt_ae_ld = io_mem_s2_xcpt_ae_ld; // @[HellaCacheArbiter.scala 17:12]
assign io_mem_req_valid = io_requestor_0_req_valid; // @[HellaCacheArbiter.scala 17:12]
assign io_mem_req_bits_addr = io_requestor_0_req_bits_addr; // @[HellaCacheArbiter.scala 17:12]
assign io_mem_s1_kill = io_requestor_0_s1_kill; // @[HellaCacheArbiter.scala 17:12]
assign HellaCacheArbiter_covSum = 30'h0;
assign io_covSum = HellaCacheArbiter_covSum;
assign metaAssert = 1'h0;
endmodule
| 6.932065 |
module SynchronizerShiftReg_w1_d3 (
input clock,
input io_d,
output io_q,
output [29:0] io_covSum,
output metaAssert,
input metaReset
);
reg sync_0; // @[ShiftReg.scala 114:16]
reg [31:0] _RAND_0;
reg sync_1; // @[ShiftReg.scala 114:16]
reg [31:0] _RAND_1;
reg sync_2; // @[ShiftReg.scala 114:16]
reg [31:0] _RAND_2;
wire [29:0] SynchronizerShiftReg_w1_d3_covSum;
assign io_q = sync_0; // @[ShiftReg.scala 123:8]
assign SynchronizerShiftReg_w1_d3_covSum = 30'h0;
assign io_covSum = SynchronizerShiftReg_w1_d3_covSum;
assign metaAssert = 1'h0;
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
sync_0 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
sync_1 = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
sync_2 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`endif // SYNTHESIS
always @(posedge clock) begin
if (metaReset) begin
sync_0 <= 1'h0;
end else begin
sync_0 <= sync_1;
end
if (metaReset) begin
sync_1 <= 1'h0;
end else begin
sync_1 <= sync_2;
end
if (metaReset) begin
sync_2 <= 1'h0;
end else begin
sync_2 <= io_d;
end
end
endmodule
| 6.820992 |
module _1_60 (
input [ 2:0] io_x,
output [ 2:0] io_y,
output [29:0] io_covSum,
output metaAssert
);
wire [29:0] _1_60_covSum;
assign io_y = io_x; // @[package.scala 218:12]
assign _1_60_covSum = 30'h0;
assign io_covSum = _1_60_covSum;
assign metaAssert = 1'h0;
endmodule
| 7.68074 |
module _1_61 (
input [53:0] io_x_ppn,
input io_x_d,
input io_x_a,
input io_x_g,
input io_x_u,
input io_x_x,
input io_x_w,
input io_x_r,
input io_x_v,
output [53:0] io_y_ppn,
output io_y_d,
output io_y_a,
output io_y_g,
output io_y_u,
output io_y_x,
output io_y_w,
output io_y_r,
output io_y_v,
output [29:0] io_covSum,
output metaAssert
);
wire [29:0] _1_61_covSum;
assign io_y_ppn = io_x_ppn; // @[package.scala 218:12]
assign io_y_d = io_x_d; // @[package.scala 218:12]
assign io_y_a = io_x_a; // @[package.scala 218:12]
assign io_y_g = io_x_g; // @[package.scala 218:12]
assign io_y_u = io_x_u; // @[package.scala 218:12]
assign io_y_x = io_x_x; // @[package.scala 218:12]
assign io_y_w = io_x_w; // @[package.scala 218:12]
assign io_y_r = io_x_r; // @[package.scala 218:12]
assign io_y_v = io_x_v; // @[package.scala 218:12]
assign _1_61_covSum = 30'h0;
assign io_covSum = _1_61_covSum;
assign metaAssert = 1'h0;
endmodule
| 7.641073 |
module _1 (
input [19:0] io_x_ppn,
input io_x_u,
input io_x_ae,
input io_x_sw,
input io_x_sx,
input io_x_sr,
input io_x_pw,
input io_x_px,
input io_x_pr,
input io_x_pal,
input io_x_paa,
input io_x_eff,
input io_x_c,
output [19:0] io_y_ppn,
output io_y_u,
output io_y_ae,
output io_y_sw,
output io_y_sx,
output io_y_sr,
output io_y_pw,
output io_y_px,
output io_y_pr,
output io_y_pal,
output io_y_paa,
output io_y_eff,
output io_y_c,
output [29:0] io_covSum,
output metaAssert
);
wire [29:0] _1_covSum;
assign io_y_ppn = io_x_ppn; // @[package.scala 218:12]
assign io_y_u = io_x_u; // @[package.scala 218:12]
assign io_y_ae = io_x_ae; // @[package.scala 218:12]
assign io_y_sw = io_x_sw; // @[package.scala 218:12]
assign io_y_sx = io_x_sx; // @[package.scala 218:12]
assign io_y_sr = io_x_sr; // @[package.scala 218:12]
assign io_y_pw = io_x_pw; // @[package.scala 218:12]
assign io_y_px = io_x_px; // @[package.scala 218:12]
assign io_y_pr = io_x_pr; // @[package.scala 218:12]
assign io_y_pal = io_x_pal; // @[package.scala 218:12]
assign io_y_paa = io_x_paa; // @[package.scala 218:12]
assign io_y_eff = io_x_eff; // @[package.scala 218:12]
assign io_y_c = io_x_c; // @[package.scala 218:12]
assign _1_covSum = 30'h0;
assign io_covSum = _1_covSum;
assign metaAssert = 1'h0;
endmodule
| 8.316516 |
module BranchDecode_3 (
input [31:0] io_inst,
input [39:0] io_pc,
output io_is_br,
output io_is_jal,
output io_is_jalr,
output io_is_call,
output [39:0] io_target,
output [ 2:0] io_cfi_type,
output [29:0] io_covSum,
output metaAssert
);
wire [31:0] _T; // @[Decode.scala 14:65]
wire _T_1; // @[Decode.scala 14:121]
wire [31:0] _T_2; // @[Decode.scala 14:65]
wire _T_3; // @[Decode.scala 14:121]
wire bpd_csignals_0; // @[Decode.scala 15:30]
wire [31:0] _T_5; // @[Decode.scala 14:65]
wire bpd_csignals_1; // @[Decode.scala 14:121]
wire [31:0] _T_7; // @[Decode.scala 14:65]
wire bpd_csignals_2; // @[Decode.scala 14:121]
wire _T_16; // @[decode.scala 622:28]
wire _T_18; // @[decode.scala 622:61]
wire [19:0] _T_26; // @[Bitwise.scala 71:12]
wire [31:0] _T_35; // @[consts.scala 373:27]
wire [39:0] _GEN_0; // @[consts.scala 373:17]
wire [39:0] _T_38; // @[consts.scala 373:17]
wire [39:0] _T_41; // @[consts.scala 373:52]
wire [11:0] _T_44; // @[Bitwise.scala 71:12]
wire [31:0] _T_55; // @[consts.scala 379:27]
wire [39:0] _GEN_1; // @[consts.scala 379:17]
wire [39:0] _T_58; // @[consts.scala 379:17]
wire [39:0] _T_61; // @[consts.scala 379:52]
wire [2:0] _T_63; // @[decode.scala 632:8]
wire [2:0] _T_64; // @[decode.scala 630:8]
wire [29:0] BranchDecode_3_covSum;
assign _T = io_inst & 32'h207f; // @[Decode.scala 14:65]
assign _T_1 = _T == 32'h63; // @[Decode.scala 14:121]
assign _T_2 = io_inst & 32'h407f; // @[Decode.scala 14:65]
assign _T_3 = _T_2 == 32'h4063; // @[Decode.scala 14:121]
assign bpd_csignals_0 = _T_1 | _T_3; // @[Decode.scala 15:30]
assign _T_5 = io_inst & 32'h7f; // @[Decode.scala 14:65]
assign bpd_csignals_1 = _T_5 == 32'h6f; // @[Decode.scala 14:121]
assign _T_7 = io_inst & 32'h707f; // @[Decode.scala 14:65]
assign bpd_csignals_2 = _T_7 == 32'h67; // @[Decode.scala 14:121]
assign _T_16 = bpd_csignals_1 | bpd_csignals_2; // @[decode.scala 622:28]
assign _T_18 = io_inst[11:7] == 5'h1; // @[decode.scala 622:61]
assign _T_26 = io_inst[31] ? 20'hfffff : 20'h0; // @[Bitwise.scala 71:12]
assign _T_35 = {
_T_26, io_inst[7], io_inst[30:25], io_inst[11:8], 1'h0
}; // @[consts.scala 373:27]
assign _GEN_0 = {{8{_T_35[31]}}, _T_35}; // @[consts.scala 373:17]
assign _T_38 = $signed(io_pc) + $signed(_GEN_0); // @[consts.scala 373:17]
assign _T_41 = $signed(_T_38) & -40'sh2; // @[consts.scala 373:52]
assign _T_44 = io_inst[31] ? 12'hfff : 12'h0; // @[Bitwise.scala 71:12]
assign _T_55 = {
_T_44, io_inst[19:12], io_inst[20], io_inst[30:25], io_inst[24:21], 1'h0
}; // @[consts.scala 379:27]
assign _GEN_1 = {{8{_T_55[31]}}, _T_55}; // @[consts.scala 379:17]
assign _T_58 = $signed(io_pc) + $signed(_GEN_1); // @[consts.scala 379:17]
assign _T_61 = $signed(_T_58) & -40'sh2; // @[consts.scala 379:52]
assign _T_63 = bpd_csignals_0 ? 3'h1 : 3'h0; // @[decode.scala 632:8]
assign _T_64 = bpd_csignals_1 ? 3'h2 : _T_63; // @[decode.scala 630:8]
assign io_is_br = _T_1 | _T_3; // @[decode.scala 619:14]
assign io_is_jal = _T_5 == 32'h6f; // @[decode.scala 620:14]
assign io_is_jalr = _T_7 == 32'h67; // @[decode.scala 621:14]
assign io_is_call = _T_16 & _T_18; // @[decode.scala 622:14]
assign io_target = bpd_csignals_0 ? _T_41 : _T_61; // @[decode.scala 625:13]
assign io_cfi_type = bpd_csignals_2 ? 3'h3 : _T_64; // @[decode.scala 627:15]
assign BranchDecode_3_covSum = 30'h0;
assign io_covSum = BranchDecode_3_covSum;
assign metaAssert = 1'h0;
endmodule
| 7.279076 |
module UOPCodeFDivDecoder (
input [ 8:0] io_uopc,
output io_sigs_singleIn,
output io_sigs_div,
output io_sigs_sqrt,
output [29:0] io_covSum,
output metaAssert
);
wire [8:0] _T_2; // @[Decode.scala 14:65]
wire _T_3; // @[Decode.scala 14:121]
wire [8:0] _T_4; // @[Decode.scala 14:65]
wire _T_5; // @[Decode.scala 14:121]
wire [8:0] _T_7; // @[Decode.scala 14:65]
wire [8:0] _T_10; // @[Decode.scala 14:65]
wire _T_11; // @[Decode.scala 14:121]
wire [8:0] _T_12; // @[Decode.scala 14:65]
wire _T_13; // @[Decode.scala 14:121]
wire [29:0] UOPCodeFDivDecoder_covSum;
assign _T_2 = io_uopc & 9'ha; // @[Decode.scala 14:65]
assign _T_3 = _T_2 == 9'h0; // @[Decode.scala 14:121]
assign _T_4 = io_uopc & 9'h9; // @[Decode.scala 14:65]
assign _T_5 = _T_4 == 9'h0; // @[Decode.scala 14:121]
assign _T_7 = io_uopc & 9'h1; // @[Decode.scala 14:65]
assign _T_10 = io_uopc & 9'h4; // @[Decode.scala 14:65]
assign _T_11 = _T_10 == 9'h0; // @[Decode.scala 14:121]
assign _T_12 = io_uopc & 9'h3; // @[Decode.scala 14:65]
assign _T_13 = _T_12 == 9'h3; // @[Decode.scala 14:121]
assign io_sigs_singleIn = _T_7 == 9'h1; // @[fdiv.scala 61:40]
assign io_sigs_div = _T_3 | _T_5; // @[fdiv.scala 61:40]
assign io_sigs_sqrt = _T_11 | _T_13; // @[fdiv.scala 61:40]
assign UOPCodeFDivDecoder_covSum = 30'h0;
assign io_covSum = UOPCodeFDivDecoder_covSum;
assign metaAssert = 1'h0;
endmodule
| 7.175893 |
module FMADecoder (
input [ 8:0] io_uopc,
output [ 1:0] io_cmd,
output [29:0] io_covSum,
output metaAssert
);
wire [8:0] _T; // @[Decode.scala 14:65]
wire _T_1; // @[Decode.scala 14:121]
wire [8:0] _T_2; // @[Decode.scala 14:65]
wire _T_3; // @[Decode.scala 14:121]
wire [8:0] _T_4; // @[Decode.scala 14:65]
wire _T_5; // @[Decode.scala 14:121]
wire [8:0] _T_6; // @[Decode.scala 14:65]
wire _T_7; // @[Decode.scala 14:121]
wire _T_9; // @[Decode.scala 15:30]
wire _T_10; // @[Decode.scala 15:30]
wire _T_11; // @[Decode.scala 15:30]
wire [8:0] _T_12; // @[Decode.scala 14:65]
wire _T_13; // @[Decode.scala 14:121]
wire _T_15; // @[Decode.scala 14:121]
wire [8:0] _T_16; // @[Decode.scala 14:65]
wire _T_17; // @[Decode.scala 14:121]
wire _T_19; // @[Decode.scala 15:30]
wire _T_20; // @[Decode.scala 15:30]
wire [29:0] FMADecoder_covSum;
assign _T = io_uopc & 9'h27; // @[Decode.scala 14:65]
assign _T_1 = _T == 9'h0; // @[Decode.scala 14:121]
assign _T_2 = io_uopc & 9'h12; // @[Decode.scala 14:65]
assign _T_3 = _T_2 == 9'h2; // @[Decode.scala 14:121]
assign _T_4 = io_uopc & 9'hb; // @[Decode.scala 14:65]
assign _T_5 = _T_4 == 9'hb; // @[Decode.scala 14:121]
assign _T_6 = io_uopc & 9'he; // @[Decode.scala 14:65]
assign _T_7 = _T_6 == 9'he; // @[Decode.scala 14:121]
assign _T_9 = _T_1 | _T_3; // @[Decode.scala 15:30]
assign _T_10 = _T_9 | _T_5; // @[Decode.scala 15:30]
assign _T_11 = _T_10 | _T_7; // @[Decode.scala 15:30]
assign _T_12 = io_uopc & 9'h13; // @[Decode.scala 14:65]
assign _T_13 = _T_12 == 9'h0; // @[Decode.scala 14:121]
assign _T_15 = _T_12 == 9'h3; // @[Decode.scala 14:121]
assign _T_16 = io_uopc & 9'hf; // @[Decode.scala 14:65]
assign _T_17 = _T_16 == 9'hf; // @[Decode.scala 14:121]
assign _T_19 = _T_13 | _T_15; // @[Decode.scala 15:30]
assign _T_20 = _T_19 | _T_17; // @[Decode.scala 15:30]
assign io_cmd = {_T_20, _T_11}; // @[fpu.scala 152:10]
assign FMADecoder_covSum = 30'h0;
assign io_covSum = FMADecoder_covSum;
assign metaAssert = 1'h0;
endmodule
| 6.646488 |
module RoundAnyRawFNToRecFN_5 (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [24:0] io_in_sig,
output [64:0] io_out,
output [29:0] io_covSum,
output metaAssert
);
wire [11:0] _GEN_0; // @[RoundAnyRawFNToRecFN.scala 102:25]
wire [12:0] _T_3; // @[RoundAnyRawFNToRecFN.scala 102:25]
wire [12:0] sAdjustedExp; // @[RoundAnyRawFNToRecFN.scala 104:31]
wire [55:0] adjustedSig; // @[RoundAnyRawFNToRecFN.scala 112:22]
wire [12:0] _T_6; // @[RoundAnyRawFNToRecFN.scala 134:55]
wire [11:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala 134:55]
wire [51:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala 138:28]
wire isNaNOut; // @[RoundAnyRawFNToRecFN.scala 233:34]
wire signOut; // @[RoundAnyRawFNToRecFN.scala 248:22]
wire [11:0] _T_22; // @[RoundAnyRawFNToRecFN.scala 251:18]
wire [11:0] _T_24; // @[RoundAnyRawFNToRecFN.scala 250:24]
wire [11:0] _T_32; // @[RoundAnyRawFNToRecFN.scala 263:18]
wire [11:0] _T_34; // @[RoundAnyRawFNToRecFN.scala 262:17]
wire [11:0] _T_39; // @[RoundAnyRawFNToRecFN.scala 275:16]
wire [11:0] _T_40; // @[RoundAnyRawFNToRecFN.scala 274:15]
wire [11:0] _T_41; // @[RoundAnyRawFNToRecFN.scala 276:16]
wire [11:0] expOut; // @[RoundAnyRawFNToRecFN.scala 275:77]
wire _T_42; // @[RoundAnyRawFNToRecFN.scala 278:22]
wire [51:0] _T_44; // @[RoundAnyRawFNToRecFN.scala 279:16]
wire [51:0] fractOut; // @[RoundAnyRawFNToRecFN.scala 278:12]
wire [12:0] _T_48; // @[Cat.scala 29:58]
wire [29:0] RoundAnyRawFNToRecFN_5_covSum;
assign _GEN_0 = {{2{io_in_sExp[9]}}, io_in_sExp}; // @[RoundAnyRawFNToRecFN.scala 102:25]
assign _T_3 = $signed(_GEN_0) + 12'sh700; // @[RoundAnyRawFNToRecFN.scala 102:25]
assign sAdjustedExp = {1'b0, $signed(_T_3[11:0])}; // @[RoundAnyRawFNToRecFN.scala 104:31]
assign adjustedSig = {io_in_sig, 31'h0}; // @[RoundAnyRawFNToRecFN.scala 112:22]
assign _T_6 = {{1'd0}, sAdjustedExp[11:0]}; // @[RoundAnyRawFNToRecFN.scala 134:55]
assign common_expOut = _T_6[11:0]; // @[RoundAnyRawFNToRecFN.scala 134:55]
assign common_fractOut = adjustedSig[53:2]; // @[RoundAnyRawFNToRecFN.scala 138:28]
assign isNaNOut = io_invalidExc | io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 233:34]
assign signOut = isNaNOut ? 1'h0 : io_in_sign; // @[RoundAnyRawFNToRecFN.scala 248:22]
assign _T_22 = io_in_isZero ? 12'he00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala 251:18]
assign _T_24 = common_expOut & ~_T_22; // @[RoundAnyRawFNToRecFN.scala 250:24]
assign _T_32 = io_in_isInf ? 12'h200 : 12'h0; // @[RoundAnyRawFNToRecFN.scala 263:18]
assign _T_34 = _T_24 & ~_T_32; // @[RoundAnyRawFNToRecFN.scala 262:17]
assign _T_39 = io_in_isInf ? 12'hc00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala 275:16]
assign _T_40 = _T_34 | _T_39; // @[RoundAnyRawFNToRecFN.scala 274:15]
assign _T_41 = isNaNOut ? 12'he00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala 276:16]
assign expOut = _T_40 | _T_41; // @[RoundAnyRawFNToRecFN.scala 275:77]
assign _T_42 = isNaNOut | io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 278:22]
assign _T_44 = isNaNOut ? 52'h8000000000000 : 52'h0; // @[RoundAnyRawFNToRecFN.scala 279:16]
assign fractOut = _T_42 ? _T_44 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala 278:12]
assign _T_48 = {signOut, expOut}; // @[Cat.scala 29:58]
assign io_out = {_T_48, fractOut}; // @[RoundAnyRawFNToRecFN.scala 284:12]
assign RoundAnyRawFNToRecFN_5_covSum = 30'h0;
assign io_covSum = RoundAnyRawFNToRecFN_5_covSum;
assign metaAssert = 1'h0;
endmodule
| 7.169444 |
module RoundRawFNToRecFN_2 (
input io_invalidExc,
input io_infiniteExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [64:0] io_out,
output [ 4:0] io_exceptionFlags,
output [29:0] io_covSum,
output metaAssert
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_sign; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [12:0] roundAnyRawFNToRecFN_io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [55:0] roundAnyRawFNToRecFN_io_in_sig; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [2:0] roundAnyRawFNToRecFN_io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [64:0] roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [4:0] roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [29:0] roundAnyRawFNToRecFN_io_covSum; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_metaAssert; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [29:0] RoundRawFNToRecFN_2_covSum;
wire [29:0] roundAnyRawFNToRecFN_sum;
wire roundAnyRawFNToRecFN_metaAssert_wire;
RoundAnyRawFNToRecFN_7 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala 307:15]
.io_invalidExc(roundAnyRawFNToRecFN_io_invalidExc),
.io_infiniteExc(roundAnyRawFNToRecFN_io_infiniteExc),
.io_in_isNaN(roundAnyRawFNToRecFN_io_in_isNaN),
.io_in_isInf(roundAnyRawFNToRecFN_io_in_isInf),
.io_in_isZero(roundAnyRawFNToRecFN_io_in_isZero),
.io_in_sign(roundAnyRawFNToRecFN_io_in_sign),
.io_in_sExp(roundAnyRawFNToRecFN_io_in_sExp),
.io_in_sig(roundAnyRawFNToRecFN_io_in_sig),
.io_roundingMode(roundAnyRawFNToRecFN_io_roundingMode),
.io_out(roundAnyRawFNToRecFN_io_out),
.io_exceptionFlags(roundAnyRawFNToRecFN_io_exceptionFlags),
.io_covSum(roundAnyRawFNToRecFN_io_covSum),
.metaAssert(roundAnyRawFNToRecFN_metaAssert)
);
assign io_out = roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 315:23]
assign io_exceptionFlags = roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 316:23]
assign roundAnyRawFNToRecFN_io_invalidExc = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 310:44]
assign roundAnyRawFNToRecFN_io_infiniteExc = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala 311:44]
assign roundAnyRawFNToRecFN_io_in_isNaN = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isInf = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isZero = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sign = io_in_sign; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sExp = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sig = io_in_sig; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_roundingMode = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 313:44]
assign RoundRawFNToRecFN_2_covSum = 30'h0;
assign roundAnyRawFNToRecFN_sum = RoundRawFNToRecFN_2_covSum + roundAnyRawFNToRecFN_io_covSum;
assign io_covSum = roundAnyRawFNToRecFN_sum;
assign roundAnyRawFNToRecFN_metaAssert_wire = roundAnyRawFNToRecFN_metaAssert;
assign metaAssert = roundAnyRawFNToRecFN_metaAssert_wire;
endmodule
| 6.992477 |
module RoundRawFNToRecFN (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
input io_detectTininess,
output [64:0] io_out,
output [ 4:0] io_exceptionFlags,
output [29:0] io_covSum,
output metaAssert
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_sign; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [12:0] roundAnyRawFNToRecFN_io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [55:0] roundAnyRawFNToRecFN_io_in_sig; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [2:0] roundAnyRawFNToRecFN_io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_detectTininess; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [64:0] roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [4:0] roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [29:0] roundAnyRawFNToRecFN_io_covSum; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_metaAssert; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [29:0] RoundRawFNToRecFN_covSum;
wire [29:0] roundAnyRawFNToRecFN_sum;
wire roundAnyRawFNToRecFN_metaAssert_wire;
RoundAnyRawFNToRecFN_2 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala 307:15]
.io_invalidExc(roundAnyRawFNToRecFN_io_invalidExc),
.io_in_isNaN(roundAnyRawFNToRecFN_io_in_isNaN),
.io_in_isInf(roundAnyRawFNToRecFN_io_in_isInf),
.io_in_isZero(roundAnyRawFNToRecFN_io_in_isZero),
.io_in_sign(roundAnyRawFNToRecFN_io_in_sign),
.io_in_sExp(roundAnyRawFNToRecFN_io_in_sExp),
.io_in_sig(roundAnyRawFNToRecFN_io_in_sig),
.io_roundingMode(roundAnyRawFNToRecFN_io_roundingMode),
.io_detectTininess(roundAnyRawFNToRecFN_io_detectTininess),
.io_out(roundAnyRawFNToRecFN_io_out),
.io_exceptionFlags(roundAnyRawFNToRecFN_io_exceptionFlags),
.io_covSum(roundAnyRawFNToRecFN_io_covSum),
.metaAssert(roundAnyRawFNToRecFN_metaAssert)
);
assign io_out = roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 315:23]
assign io_exceptionFlags = roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 316:23]
assign roundAnyRawFNToRecFN_io_invalidExc = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 310:44]
assign roundAnyRawFNToRecFN_io_in_isNaN = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isInf = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isZero = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sign = io_in_sign; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sExp = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sig = io_in_sig; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_roundingMode = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 313:44]
assign roundAnyRawFNToRecFN_io_detectTininess = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala 314:44]
assign RoundRawFNToRecFN_covSum = 30'h0;
assign roundAnyRawFNToRecFN_sum = RoundRawFNToRecFN_covSum + roundAnyRawFNToRecFN_io_covSum;
assign io_covSum = roundAnyRawFNToRecFN_sum;
assign roundAnyRawFNToRecFN_metaAssert_wire = roundAnyRawFNToRecFN_metaAssert;
assign metaAssert = roundAnyRawFNToRecFN_metaAssert_wire;
endmodule
| 6.992477 |
module RoundRawFNToRecFN_1 (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [26:0] io_in_sig,
input [ 2:0] io_roundingMode,
input io_detectTininess,
output [32:0] io_out,
output [ 4:0] io_exceptionFlags,
output [29:0] io_covSum,
output metaAssert
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_sign; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [9:0] roundAnyRawFNToRecFN_io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [26:0] roundAnyRawFNToRecFN_io_in_sig; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [2:0] roundAnyRawFNToRecFN_io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_detectTininess; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [32:0] roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [4:0] roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [29:0] roundAnyRawFNToRecFN_io_covSum; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_metaAssert; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [29:0] RoundRawFNToRecFN_1_covSum;
wire [29:0] roundAnyRawFNToRecFN_sum;
wire roundAnyRawFNToRecFN_metaAssert_wire;
RoundAnyRawFNToRecFN_3 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala 307:15]
.io_invalidExc(roundAnyRawFNToRecFN_io_invalidExc),
.io_in_isNaN(roundAnyRawFNToRecFN_io_in_isNaN),
.io_in_isInf(roundAnyRawFNToRecFN_io_in_isInf),
.io_in_isZero(roundAnyRawFNToRecFN_io_in_isZero),
.io_in_sign(roundAnyRawFNToRecFN_io_in_sign),
.io_in_sExp(roundAnyRawFNToRecFN_io_in_sExp),
.io_in_sig(roundAnyRawFNToRecFN_io_in_sig),
.io_roundingMode(roundAnyRawFNToRecFN_io_roundingMode),
.io_detectTininess(roundAnyRawFNToRecFN_io_detectTininess),
.io_out(roundAnyRawFNToRecFN_io_out),
.io_exceptionFlags(roundAnyRawFNToRecFN_io_exceptionFlags),
.io_covSum(roundAnyRawFNToRecFN_io_covSum),
.metaAssert(roundAnyRawFNToRecFN_metaAssert)
);
assign io_out = roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 315:23]
assign io_exceptionFlags = roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 316:23]
assign roundAnyRawFNToRecFN_io_invalidExc = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 310:44]
assign roundAnyRawFNToRecFN_io_in_isNaN = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isInf = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isZero = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sign = io_in_sign; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sExp = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sig = io_in_sig; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_roundingMode = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 313:44]
assign roundAnyRawFNToRecFN_io_detectTininess = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala 314:44]
assign RoundRawFNToRecFN_1_covSum = 30'h0;
assign roundAnyRawFNToRecFN_sum = RoundRawFNToRecFN_1_covSum + roundAnyRawFNToRecFN_io_covSum;
assign io_covSum = roundAnyRawFNToRecFN_sum;
assign roundAnyRawFNToRecFN_metaAssert_wire = roundAnyRawFNToRecFN_metaAssert;
assign metaAssert = roundAnyRawFNToRecFN_metaAssert_wire;
endmodule
| 6.992477 |
module IntXbar_4 (
input auto_int_in_3_0,
input auto_int_in_2_0,
input auto_int_in_1_0,
input auto_int_in_1_1,
input auto_int_in_0_0,
output auto_int_out_0,
output auto_int_out_1,
output auto_int_out_2,
output auto_int_out_3,
output auto_int_out_4,
output [29:0] io_covSum,
output metaAssert
);
wire [29:0] IntXbar_4_covSum;
assign auto_int_out_0 = auto_int_in_0_0; // @[LazyModule.scala 181:49]
assign auto_int_out_1 = auto_int_in_1_0; // @[LazyModule.scala 181:49]
assign auto_int_out_2 = auto_int_in_1_1; // @[LazyModule.scala 181:49]
assign auto_int_out_3 = auto_int_in_2_0; // @[LazyModule.scala 181:49]
assign auto_int_out_4 = auto_int_in_3_0; // @[LazyModule.scala 181:49]
assign IntXbar_4_covSum = 30'h0;
assign io_covSum = IntXbar_4_covSum;
assign metaAssert = 1'h0;
endmodule
| 6.908358 |
module IntSyncAsyncCrossingSink (
input clock,
input auto_in_sync_0,
output auto_out_0,
output [29:0] io_covSum,
output metaAssert,
input metaReset,
input SynchronizerShiftReg_w1_d3_halt
);
wire SynchronizerShiftReg_w1_d3_clock; // @[ShiftReg.scala 45:23]
wire SynchronizerShiftReg_w1_d3_io_d; // @[ShiftReg.scala 45:23]
wire SynchronizerShiftReg_w1_d3_io_q; // @[ShiftReg.scala 45:23]
wire [29:0] SynchronizerShiftReg_w1_d3_io_covSum; // @[ShiftReg.scala 45:23]
wire SynchronizerShiftReg_w1_d3_metaAssert; // @[ShiftReg.scala 45:23]
wire SynchronizerShiftReg_w1_d3_metaReset; // @[ShiftReg.scala 45:23]
wire SynchronizerShiftReg_w1_d3_NonSyncResetSynchronizerPrimitiveShiftReg_d3_halt; // @[ShiftReg.scala 45:23]
wire [29:0] IntSyncAsyncCrossingSink_covSum;
wire [29:0] SynchronizerShiftReg_w1_d3_sum;
wire SynchronizerShiftReg_w1_d3_metaAssert_wire;
SynchronizerShiftReg_w1_d3 SynchronizerShiftReg_w1_d3 ( // @[ShiftReg.scala 45:23]
.clock(SynchronizerShiftReg_w1_d3_clock),
.io_d(SynchronizerShiftReg_w1_d3_io_d),
.io_q(SynchronizerShiftReg_w1_d3_io_q),
.io_covSum(SynchronizerShiftReg_w1_d3_io_covSum),
.metaAssert(SynchronizerShiftReg_w1_d3_metaAssert),
.metaReset(SynchronizerShiftReg_w1_d3_metaReset),
.NonSyncResetSynchronizerPrimitiveShiftReg_d3_halt(SynchronizerShiftReg_w1_d3_NonSyncResetSynchronizerPrimitiveShiftReg_d3_halt)
);
assign auto_out_0 = SynchronizerShiftReg_w1_d3_io_q; // @[LazyModule.scala 181:49]
assign SynchronizerShiftReg_w1_d3_clock = clock;
assign SynchronizerShiftReg_w1_d3_io_d = auto_in_sync_0; // @[ShiftReg.scala 47:16]
assign IntSyncAsyncCrossingSink_covSum = 30'h0;
assign SynchronizerShiftReg_w1_d3_sum = IntSyncAsyncCrossingSink_covSum + SynchronizerShiftReg_w1_d3_io_covSum;
assign io_covSum = SynchronizerShiftReg_w1_d3_sum;
assign SynchronizerShiftReg_w1_d3_metaAssert_wire = SynchronizerShiftReg_w1_d3_metaAssert;
assign metaAssert = SynchronizerShiftReg_w1_d3_metaAssert_wire;
assign SynchronizerShiftReg_w1_d3_metaReset = metaReset | SynchronizerShiftReg_w1_d3_halt;
endmodule
| 6.70996 |
module HellaCacheArbiter (
output io_requestor_0_req_ready,
input io_requestor_0_req_valid,
input [39:0] io_requestor_0_req_bits_addr,
input io_requestor_0_s1_kill,
output io_requestor_0_s2_nack,
output io_requestor_0_resp_valid,
output [63:0] io_requestor_0_resp_bits_data,
output io_requestor_0_s2_xcpt_ae_ld,
input io_mem_req_ready,
output io_mem_req_valid,
output [39:0] io_mem_req_bits_addr,
output io_mem_s1_kill,
input io_mem_s2_nack,
input io_mem_resp_valid,
input [63:0] io_mem_resp_bits_data,
input io_mem_s2_xcpt_ae_ld,
output [29:0] io_covSum,
output metaAssert
);
wire [29:0] HellaCacheArbiter_covSum;
assign io_requestor_0_req_ready = io_mem_req_ready; // @[HellaCacheArbiter.scala 17:12]
assign io_requestor_0_s2_nack = io_mem_s2_nack; // @[HellaCacheArbiter.scala 17:12]
assign io_requestor_0_resp_valid = io_mem_resp_valid; // @[HellaCacheArbiter.scala 17:12]
assign io_requestor_0_resp_bits_data = io_mem_resp_bits_data; // @[HellaCacheArbiter.scala 17:12]
assign io_requestor_0_s2_xcpt_ae_ld = io_mem_s2_xcpt_ae_ld; // @[HellaCacheArbiter.scala 17:12]
assign io_mem_req_valid = io_requestor_0_req_valid; // @[HellaCacheArbiter.scala 17:12]
assign io_mem_req_bits_addr = io_requestor_0_req_bits_addr; // @[HellaCacheArbiter.scala 17:12]
assign io_mem_s1_kill = io_requestor_0_s1_kill; // @[HellaCacheArbiter.scala 17:12]
assign HellaCacheArbiter_covSum = 30'h0;
assign io_covSum = HellaCacheArbiter_covSum;
assign metaAssert = 1'h0;
endmodule
| 6.932065 |
module SynchronizerShiftReg_w1_d3 (
input clock,
input io_d,
output io_q,
output [29:0] io_covSum,
output metaAssert,
input metaReset,
input NonSyncResetSynchronizerPrimitiveShiftReg_d3_halt
);
wire NonSyncResetSynchronizerPrimitiveShiftReg_d3_clock; // @[ShiftReg.scala 45:23]
wire NonSyncResetSynchronizerPrimitiveShiftReg_d3_io_d; // @[ShiftReg.scala 45:23]
wire NonSyncResetSynchronizerPrimitiveShiftReg_d3_io_q; // @[ShiftReg.scala 45:23]
wire [29:0] NonSyncResetSynchronizerPrimitiveShiftReg_d3_io_covSum; // @[ShiftReg.scala 45:23]
wire NonSyncResetSynchronizerPrimitiveShiftReg_d3_metaAssert; // @[ShiftReg.scala 45:23]
wire NonSyncResetSynchronizerPrimitiveShiftReg_d3_metaReset; // @[ShiftReg.scala 45:23]
wire [29:0] SynchronizerShiftReg_w1_d3_covSum;
wire [29:0] NonSyncResetSynchronizerPrimitiveShiftReg_d3_sum;
wire NonSyncResetSynchronizerPrimitiveShiftReg_d3_metaAssert_wire;
NonSyncResetSynchronizerPrimitiveShiftReg_d3 NonSyncResetSynchronizerPrimitiveShiftReg_d3 ( // @[ShiftReg.scala 45:23]
.clock(NonSyncResetSynchronizerPrimitiveShiftReg_d3_clock),
.io_d(NonSyncResetSynchronizerPrimitiveShiftReg_d3_io_d),
.io_q(NonSyncResetSynchronizerPrimitiveShiftReg_d3_io_q),
.io_covSum(NonSyncResetSynchronizerPrimitiveShiftReg_d3_io_covSum),
.metaAssert(NonSyncResetSynchronizerPrimitiveShiftReg_d3_metaAssert),
.metaReset(NonSyncResetSynchronizerPrimitiveShiftReg_d3_metaReset)
);
assign io_q = NonSyncResetSynchronizerPrimitiveShiftReg_d3_io_q; // @[SynchronizerReg.scala 165:8]
assign NonSyncResetSynchronizerPrimitiveShiftReg_d3_clock = clock;
assign NonSyncResetSynchronizerPrimitiveShiftReg_d3_io_d = io_d; // @[ShiftReg.scala 47:16]
assign SynchronizerShiftReg_w1_d3_covSum = 30'h0;
assign NonSyncResetSynchronizerPrimitiveShiftReg_d3_sum = SynchronizerShiftReg_w1_d3_covSum + NonSyncResetSynchronizerPrimitiveShiftReg_d3_io_covSum;
assign io_covSum = NonSyncResetSynchronizerPrimitiveShiftReg_d3_sum;
assign NonSyncResetSynchronizerPrimitiveShiftReg_d3_metaAssert_wire = NonSyncResetSynchronizerPrimitiveShiftReg_d3_metaAssert;
assign metaAssert = NonSyncResetSynchronizerPrimitiveShiftReg_d3_metaAssert_wire;
assign NonSyncResetSynchronizerPrimitiveShiftReg_d3_metaReset = metaReset | NonSyncResetSynchronizerPrimitiveShiftReg_d3_halt;
endmodule
| 6.820992 |
module package_Anon_60 (
input [ 2:0] io_x,
output [ 2:0] io_y,
output [29:0] io_covSum,
output metaAssert
);
wire [29:0] package_Anon_60_covSum;
assign io_y = io_x; // @[package.scala 218:12]
assign package_Anon_60_covSum = 30'h0;
assign io_covSum = package_Anon_60_covSum;
assign metaAssert = 1'h0;
endmodule
| 7.042728 |
module package_Anon_61 (
input [53:0] io_x_ppn,
input io_x_d,
input io_x_a,
input io_x_g,
input io_x_u,
input io_x_x,
input io_x_w,
input io_x_r,
input io_x_v,
output [53:0] io_y_ppn,
output io_y_d,
output io_y_a,
output io_y_g,
output io_y_u,
output io_y_x,
output io_y_w,
output io_y_r,
output io_y_v,
output [29:0] io_covSum,
output metaAssert
);
wire [29:0] package_Anon_61_covSum;
assign io_y_ppn = io_x_ppn; // @[package.scala 218:12]
assign io_y_d = io_x_d; // @[package.scala 218:12]
assign io_y_a = io_x_a; // @[package.scala 218:12]
assign io_y_g = io_x_g; // @[package.scala 218:12]
assign io_y_u = io_x_u; // @[package.scala 218:12]
assign io_y_x = io_x_x; // @[package.scala 218:12]
assign io_y_w = io_x_w; // @[package.scala 218:12]
assign io_y_r = io_x_r; // @[package.scala 218:12]
assign io_y_v = io_x_v; // @[package.scala 218:12]
assign package_Anon_61_covSum = 30'h0;
assign io_covSum = package_Anon_61_covSum;
assign metaAssert = 1'h0;
endmodule
| 7.042728 |
module package_Anon (
input [19:0] io_x_ppn,
input io_x_u,
input io_x_ae,
input io_x_sw,
input io_x_sx,
input io_x_sr,
input io_x_pw,
input io_x_px,
input io_x_pr,
input io_x_pal,
input io_x_paa,
input io_x_eff,
input io_x_c,
output [19:0] io_y_ppn,
output io_y_u,
output io_y_ae,
output io_y_sw,
output io_y_sx,
output io_y_sr,
output io_y_pw,
output io_y_px,
output io_y_pr,
output io_y_pal,
output io_y_paa,
output io_y_eff,
output io_y_c,
output [29:0] io_covSum,
output metaAssert
);
wire [29:0] package_Anon_covSum;
assign io_y_ppn = io_x_ppn; // @[package.scala 218:12]
assign io_y_u = io_x_u; // @[package.scala 218:12]
assign io_y_ae = io_x_ae; // @[package.scala 218:12]
assign io_y_sw = io_x_sw; // @[package.scala 218:12]
assign io_y_sx = io_x_sx; // @[package.scala 218:12]
assign io_y_sr = io_x_sr; // @[package.scala 218:12]
assign io_y_pw = io_x_pw; // @[package.scala 218:12]
assign io_y_px = io_x_px; // @[package.scala 218:12]
assign io_y_pr = io_x_pr; // @[package.scala 218:12]
assign io_y_pal = io_x_pal; // @[package.scala 218:12]
assign io_y_paa = io_x_paa; // @[package.scala 218:12]
assign io_y_eff = io_x_eff; // @[package.scala 218:12]
assign io_y_c = io_x_c; // @[package.scala 218:12]
assign package_Anon_covSum = 30'h0;
assign io_covSum = package_Anon_covSum;
assign metaAssert = 1'h0;
endmodule
| 7.745937 |
module UOPCodeFDivDecoder (
input [ 6:0] io_uopc,
output io_sigs_singleIn,
output io_sigs_div,
output io_sigs_sqrt,
output [29:0] io_covSum,
output metaAssert
);
wire [6:0] _T_2; // @[Decode.scala 14:65]
wire _T_3; // @[Decode.scala 14:121]
wire [6:0] _T_4; // @[Decode.scala 14:65]
wire _T_5; // @[Decode.scala 14:121]
wire [6:0] _T_7; // @[Decode.scala 14:65]
wire [6:0] _T_10; // @[Decode.scala 14:65]
wire _T_11; // @[Decode.scala 14:121]
wire [6:0] _T_12; // @[Decode.scala 14:65]
wire _T_13; // @[Decode.scala 14:121]
wire [29:0] UOPCodeFDivDecoder_covSum;
assign _T_2 = io_uopc & 7'ha; // @[Decode.scala 14:65]
assign _T_3 = _T_2 == 7'h0; // @[Decode.scala 14:121]
assign _T_4 = io_uopc & 7'h9; // @[Decode.scala 14:65]
assign _T_5 = _T_4 == 7'h0; // @[Decode.scala 14:121]
assign _T_7 = io_uopc & 7'h1; // @[Decode.scala 14:65]
assign _T_10 = io_uopc & 7'h4; // @[Decode.scala 14:65]
assign _T_11 = _T_10 == 7'h0; // @[Decode.scala 14:121]
assign _T_12 = io_uopc & 7'h3; // @[Decode.scala 14:65]
assign _T_13 = _T_12 == 7'h3; // @[Decode.scala 14:121]
assign io_sigs_singleIn = _T_7 == 7'h1; // @[fdiv.scala 61:40]
assign io_sigs_div = _T_3 | _T_5; // @[fdiv.scala 61:40]
assign io_sigs_sqrt = _T_11 | _T_13; // @[fdiv.scala 61:40]
assign UOPCodeFDivDecoder_covSum = 30'h0;
assign io_covSum = UOPCodeFDivDecoder_covSum;
assign metaAssert = 1'h0;
endmodule
| 7.175893 |
module FMADecoder (
input [ 6:0] io_uopc,
output [ 1:0] io_cmd,
output [29:0] io_covSum,
output metaAssert
);
wire [6:0] _T; // @[Decode.scala 14:65]
wire _T_1; // @[Decode.scala 14:121]
wire [6:0] _T_2; // @[Decode.scala 14:65]
wire _T_3; // @[Decode.scala 14:121]
wire [6:0] _T_4; // @[Decode.scala 14:65]
wire _T_5; // @[Decode.scala 14:121]
wire [6:0] _T_6; // @[Decode.scala 14:65]
wire _T_7; // @[Decode.scala 14:121]
wire _T_9; // @[Decode.scala 15:30]
wire _T_10; // @[Decode.scala 15:30]
wire _T_11; // @[Decode.scala 15:30]
wire [6:0] _T_12; // @[Decode.scala 14:65]
wire _T_13; // @[Decode.scala 14:121]
wire _T_15; // @[Decode.scala 14:121]
wire [6:0] _T_16; // @[Decode.scala 14:65]
wire _T_17; // @[Decode.scala 14:121]
wire _T_19; // @[Decode.scala 15:30]
wire _T_20; // @[Decode.scala 15:30]
wire [29:0] FMADecoder_covSum;
assign _T = io_uopc & 7'h27; // @[Decode.scala 14:65]
assign _T_1 = _T == 7'h0; // @[Decode.scala 14:121]
assign _T_2 = io_uopc & 7'h12; // @[Decode.scala 14:65]
assign _T_3 = _T_2 == 7'h2; // @[Decode.scala 14:121]
assign _T_4 = io_uopc & 7'hb; // @[Decode.scala 14:65]
assign _T_5 = _T_4 == 7'hb; // @[Decode.scala 14:121]
assign _T_6 = io_uopc & 7'he; // @[Decode.scala 14:65]
assign _T_7 = _T_6 == 7'he; // @[Decode.scala 14:121]
assign _T_9 = _T_1 | _T_3; // @[Decode.scala 15:30]
assign _T_10 = _T_9 | _T_5; // @[Decode.scala 15:30]
assign _T_11 = _T_10 | _T_7; // @[Decode.scala 15:30]
assign _T_12 = io_uopc & 7'h13; // @[Decode.scala 14:65]
assign _T_13 = _T_12 == 7'h0; // @[Decode.scala 14:121]
assign _T_15 = _T_12 == 7'h3; // @[Decode.scala 14:121]
assign _T_16 = io_uopc & 7'hf; // @[Decode.scala 14:65]
assign _T_17 = _T_16 == 7'hf; // @[Decode.scala 14:121]
assign _T_19 = _T_13 | _T_15; // @[Decode.scala 15:30]
assign _T_20 = _T_19 | _T_17; // @[Decode.scala 15:30]
assign io_cmd = {_T_20, _T_11}; // @[fpu.scala 152:10]
assign FMADecoder_covSum = 30'h0;
assign io_covSum = FMADecoder_covSum;
assign metaAssert = 1'h0;
endmodule
| 6.646488 |
module RoundAnyRawFNToRecFN_5 (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [24:0] io_in_sig,
output [64:0] io_out,
output [29:0] io_covSum,
output metaAssert
);
wire [11:0] _GEN_0; // @[RoundAnyRawFNToRecFN.scala 102:25]
wire [12:0] _T_3; // @[RoundAnyRawFNToRecFN.scala 102:25]
wire [12:0] sAdjustedExp; // @[RoundAnyRawFNToRecFN.scala 104:31]
wire [55:0] adjustedSig; // @[RoundAnyRawFNToRecFN.scala 112:22]
wire [12:0] _T_6; // @[RoundAnyRawFNToRecFN.scala 134:55]
wire [11:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala 134:55]
wire [51:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala 138:28]
wire isNaNOut; // @[RoundAnyRawFNToRecFN.scala 233:34]
wire signOut; // @[RoundAnyRawFNToRecFN.scala 248:22]
wire [11:0] _T_22; // @[RoundAnyRawFNToRecFN.scala 251:18]
wire [11:0] _T_24; // @[RoundAnyRawFNToRecFN.scala 250:24]
wire [11:0] _T_32; // @[RoundAnyRawFNToRecFN.scala 263:18]
wire [11:0] _T_34; // @[RoundAnyRawFNToRecFN.scala 262:17]
wire [11:0] _T_39; // @[RoundAnyRawFNToRecFN.scala 275:16]
wire [11:0] _T_40; // @[RoundAnyRawFNToRecFN.scala 274:15]
wire [11:0] _T_41; // @[RoundAnyRawFNToRecFN.scala 276:16]
wire [11:0] expOut; // @[RoundAnyRawFNToRecFN.scala 275:77]
wire _T_42; // @[RoundAnyRawFNToRecFN.scala 278:22]
wire [51:0] _T_44; // @[RoundAnyRawFNToRecFN.scala 279:16]
wire [51:0] fractOut; // @[RoundAnyRawFNToRecFN.scala 278:12]
wire [12:0] _T_48; // @[Cat.scala 29:58]
wire [29:0] RoundAnyRawFNToRecFN_5_covSum;
assign _GEN_0 = {{2{io_in_sExp[9]}}, io_in_sExp}; // @[RoundAnyRawFNToRecFN.scala 102:25]
assign _T_3 = $signed(_GEN_0) + 12'sh700; // @[RoundAnyRawFNToRecFN.scala 102:25]
assign sAdjustedExp = {1'b0, $signed(_T_3[11:0])}; // @[RoundAnyRawFNToRecFN.scala 104:31]
assign adjustedSig = {io_in_sig, 31'h0}; // @[RoundAnyRawFNToRecFN.scala 112:22]
assign _T_6 = {{1'd0}, sAdjustedExp[11:0]}; // @[RoundAnyRawFNToRecFN.scala 134:55]
assign common_expOut = _T_6[11:0]; // @[RoundAnyRawFNToRecFN.scala 134:55]
assign common_fractOut = adjustedSig[53:2]; // @[RoundAnyRawFNToRecFN.scala 138:28]
assign isNaNOut = io_invalidExc | io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 233:34]
assign signOut = isNaNOut ? 1'h0 : io_in_sign; // @[RoundAnyRawFNToRecFN.scala 248:22]
assign _T_22 = io_in_isZero ? 12'he00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala 251:18]
assign _T_24 = common_expOut & ~_T_22; // @[RoundAnyRawFNToRecFN.scala 250:24]
assign _T_32 = io_in_isInf ? 12'h200 : 12'h0; // @[RoundAnyRawFNToRecFN.scala 263:18]
assign _T_34 = _T_24 & ~_T_32; // @[RoundAnyRawFNToRecFN.scala 262:17]
assign _T_39 = io_in_isInf ? 12'hc00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala 275:16]
assign _T_40 = _T_34 | _T_39; // @[RoundAnyRawFNToRecFN.scala 274:15]
assign _T_41 = isNaNOut ? 12'he00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala 276:16]
assign expOut = _T_40 | _T_41; // @[RoundAnyRawFNToRecFN.scala 275:77]
assign _T_42 = isNaNOut | io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 278:22]
assign _T_44 = isNaNOut ? 52'h8000000000000 : 52'h0; // @[RoundAnyRawFNToRecFN.scala 279:16]
assign fractOut = _T_42 ? _T_44 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala 278:12]
assign _T_48 = {signOut, expOut}; // @[Cat.scala 29:58]
assign io_out = {_T_48, fractOut}; // @[RoundAnyRawFNToRecFN.scala 284:12]
assign RoundAnyRawFNToRecFN_5_covSum = 30'h0;
assign io_covSum = RoundAnyRawFNToRecFN_5_covSum;
assign metaAssert = 1'h0;
endmodule
| 7.169444 |
module RoundRawFNToRecFN_2 (
input io_invalidExc,
input io_infiniteExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [64:0] io_out,
output [ 4:0] io_exceptionFlags,
output [29:0] io_covSum,
output metaAssert
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_sign; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [12:0] roundAnyRawFNToRecFN_io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [55:0] roundAnyRawFNToRecFN_io_in_sig; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [2:0] roundAnyRawFNToRecFN_io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [64:0] roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [4:0] roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [29:0] roundAnyRawFNToRecFN_io_covSum; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_metaAssert; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [29:0] RoundRawFNToRecFN_2_covSum;
wire [29:0] roundAnyRawFNToRecFN_sum;
wire roundAnyRawFNToRecFN_metaAssert_wire;
RoundAnyRawFNToRecFN_7 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala 307:15]
.io_invalidExc(roundAnyRawFNToRecFN_io_invalidExc),
.io_infiniteExc(roundAnyRawFNToRecFN_io_infiniteExc),
.io_in_isNaN(roundAnyRawFNToRecFN_io_in_isNaN),
.io_in_isInf(roundAnyRawFNToRecFN_io_in_isInf),
.io_in_isZero(roundAnyRawFNToRecFN_io_in_isZero),
.io_in_sign(roundAnyRawFNToRecFN_io_in_sign),
.io_in_sExp(roundAnyRawFNToRecFN_io_in_sExp),
.io_in_sig(roundAnyRawFNToRecFN_io_in_sig),
.io_roundingMode(roundAnyRawFNToRecFN_io_roundingMode),
.io_out(roundAnyRawFNToRecFN_io_out),
.io_exceptionFlags(roundAnyRawFNToRecFN_io_exceptionFlags),
.io_covSum(roundAnyRawFNToRecFN_io_covSum),
.metaAssert(roundAnyRawFNToRecFN_metaAssert)
);
assign io_out = roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 315:23]
assign io_exceptionFlags = roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 316:23]
assign roundAnyRawFNToRecFN_io_invalidExc = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 310:44]
assign roundAnyRawFNToRecFN_io_infiniteExc = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala 311:44]
assign roundAnyRawFNToRecFN_io_in_isNaN = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isInf = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isZero = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sign = io_in_sign; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sExp = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sig = io_in_sig; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_roundingMode = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 313:44]
assign RoundRawFNToRecFN_2_covSum = 30'h0;
assign roundAnyRawFNToRecFN_sum = RoundRawFNToRecFN_2_covSum + roundAnyRawFNToRecFN_io_covSum;
assign io_covSum = roundAnyRawFNToRecFN_sum;
assign roundAnyRawFNToRecFN_metaAssert_wire = roundAnyRawFNToRecFN_metaAssert;
assign metaAssert = roundAnyRawFNToRecFN_metaAssert_wire;
endmodule
| 6.992477 |
module RoundRawFNToRecFN (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
input io_detectTininess,
output [64:0] io_out,
output [ 4:0] io_exceptionFlags,
output [29:0] io_covSum,
output metaAssert
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_sign; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [12:0] roundAnyRawFNToRecFN_io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [55:0] roundAnyRawFNToRecFN_io_in_sig; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [2:0] roundAnyRawFNToRecFN_io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_detectTininess; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [64:0] roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [4:0] roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [29:0] roundAnyRawFNToRecFN_io_covSum; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_metaAssert; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [29:0] RoundRawFNToRecFN_covSum;
wire [29:0] roundAnyRawFNToRecFN_sum;
wire roundAnyRawFNToRecFN_metaAssert_wire;
RoundAnyRawFNToRecFN_2 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala 307:15]
.io_invalidExc(roundAnyRawFNToRecFN_io_invalidExc),
.io_in_isNaN(roundAnyRawFNToRecFN_io_in_isNaN),
.io_in_isInf(roundAnyRawFNToRecFN_io_in_isInf),
.io_in_isZero(roundAnyRawFNToRecFN_io_in_isZero),
.io_in_sign(roundAnyRawFNToRecFN_io_in_sign),
.io_in_sExp(roundAnyRawFNToRecFN_io_in_sExp),
.io_in_sig(roundAnyRawFNToRecFN_io_in_sig),
.io_roundingMode(roundAnyRawFNToRecFN_io_roundingMode),
.io_detectTininess(roundAnyRawFNToRecFN_io_detectTininess),
.io_out(roundAnyRawFNToRecFN_io_out),
.io_exceptionFlags(roundAnyRawFNToRecFN_io_exceptionFlags),
.io_covSum(roundAnyRawFNToRecFN_io_covSum),
.metaAssert(roundAnyRawFNToRecFN_metaAssert)
);
assign io_out = roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 315:23]
assign io_exceptionFlags = roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 316:23]
assign roundAnyRawFNToRecFN_io_invalidExc = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 310:44]
assign roundAnyRawFNToRecFN_io_in_isNaN = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isInf = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isZero = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sign = io_in_sign; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sExp = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sig = io_in_sig; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_roundingMode = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 313:44]
assign roundAnyRawFNToRecFN_io_detectTininess = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala 314:44]
assign RoundRawFNToRecFN_covSum = 30'h0;
assign roundAnyRawFNToRecFN_sum = RoundRawFNToRecFN_covSum + roundAnyRawFNToRecFN_io_covSum;
assign io_covSum = roundAnyRawFNToRecFN_sum;
assign roundAnyRawFNToRecFN_metaAssert_wire = roundAnyRawFNToRecFN_metaAssert;
assign metaAssert = roundAnyRawFNToRecFN_metaAssert_wire;
endmodule
| 6.992477 |
module RoundRawFNToRecFN_1 (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [26:0] io_in_sig,
input [ 2:0] io_roundingMode,
input io_detectTininess,
output [32:0] io_out,
output [ 4:0] io_exceptionFlags,
output [29:0] io_covSum,
output metaAssert
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_in_sign; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [9:0] roundAnyRawFNToRecFN_io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [26:0] roundAnyRawFNToRecFN_io_in_sig; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [2:0] roundAnyRawFNToRecFN_io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_io_detectTininess; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [32:0] roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [4:0] roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [29:0] roundAnyRawFNToRecFN_io_covSum; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire roundAnyRawFNToRecFN_metaAssert; // @[RoundAnyRawFNToRecFN.scala 307:15]
wire [29:0] RoundRawFNToRecFN_1_covSum;
wire [29:0] roundAnyRawFNToRecFN_sum;
wire roundAnyRawFNToRecFN_metaAssert_wire;
RoundAnyRawFNToRecFN_3 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala 307:15]
.io_invalidExc(roundAnyRawFNToRecFN_io_invalidExc),
.io_in_isNaN(roundAnyRawFNToRecFN_io_in_isNaN),
.io_in_isInf(roundAnyRawFNToRecFN_io_in_isInf),
.io_in_isZero(roundAnyRawFNToRecFN_io_in_isZero),
.io_in_sign(roundAnyRawFNToRecFN_io_in_sign),
.io_in_sExp(roundAnyRawFNToRecFN_io_in_sExp),
.io_in_sig(roundAnyRawFNToRecFN_io_in_sig),
.io_roundingMode(roundAnyRawFNToRecFN_io_roundingMode),
.io_detectTininess(roundAnyRawFNToRecFN_io_detectTininess),
.io_out(roundAnyRawFNToRecFN_io_out),
.io_exceptionFlags(roundAnyRawFNToRecFN_io_exceptionFlags),
.io_covSum(roundAnyRawFNToRecFN_io_covSum),
.metaAssert(roundAnyRawFNToRecFN_metaAssert)
);
assign io_out = roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 315:23]
assign io_exceptionFlags = roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 316:23]
assign roundAnyRawFNToRecFN_io_invalidExc = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 310:44]
assign roundAnyRawFNToRecFN_io_in_isNaN = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isInf = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_isZero = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sign = io_in_sign; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sExp = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_in_sig = io_in_sig; // @[RoundAnyRawFNToRecFN.scala 312:44]
assign roundAnyRawFNToRecFN_io_roundingMode = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 313:44]
assign roundAnyRawFNToRecFN_io_detectTininess = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala 314:44]
assign RoundRawFNToRecFN_1_covSum = 30'h0;
assign roundAnyRawFNToRecFN_sum = RoundRawFNToRecFN_1_covSum + roundAnyRawFNToRecFN_io_covSum;
assign io_covSum = roundAnyRawFNToRecFN_sum;
assign roundAnyRawFNToRecFN_metaAssert_wire = roundAnyRawFNToRecFN_metaAssert;
assign metaAssert = roundAnyRawFNToRecFN_metaAssert_wire;
endmodule
| 6.992477 |
module SmallOdds4Filter (
output io_in_ready,
input io_in_valid,
input [31:0] io_in_bits,
input io_out_ready,
output io_out_valid,
output [31:0] io_out_bits
);
wire _T_16 = io_in_bits < 32'ha; // @[SmallOdds4.scala 28:38]
assign io_in_ready = io_out_ready; // @[SmallOdds4.scala 19:17]
assign io_out_valid = io_out_ready & io_in_valid & _T_16; // @[SmallOdds4.scala 22:49]
assign io_out_bits = io_in_bits; // @[SmallOdds4.scala 20:17]
endmodule
| 6.891035 |
module SmallOdds4Filter_1 (
output io_in_ready,
input io_in_valid,
input [31:0] io_in_bits,
input io_out_ready,
output io_out_valid,
output [31:0] io_out_bits
);
wire [31:0] _T_16 = io_in_bits & 32'h1; // @[SmallOdds4.scala 30:52]
wire _T_18 = _T_16 == 32'h1; // @[SmallOdds4.scala 30:59]
assign io_in_ready = io_out_ready; // @[SmallOdds4.scala 19:17]
assign io_out_valid = io_out_ready & io_in_valid & _T_18; // @[SmallOdds4.scala 22:49]
assign io_out_bits = io_in_bits; // @[SmallOdds4.scala 20:17]
endmodule
| 6.891035 |
module smallRAM (
wr,
Di,
CS,
address,
clk,
Do
);
input CS, wr, clk;
input [5:0] address;
input [7:0] Di;
output reg [7:0] Do;
reg [7:0] memArray[0:63];
reg [7:0] memOut;
always @(posedge clk) begin
if (CS) memArray[address] = Di;
end
always @(posedge clk) begin
memOut = memArray[address];
Do = (CS && wr) ? memOut : 8'b0;
end
endmodule
| 7.897952 |
module smallRAM (
wr,
Di,
CS,
address,
clk,
Do
);
input CS, wr, clk;
input [5:0] address;
input [7:0] Di;
output reg [7:0] Do;
reg [7:0] memArray[0:63];
reg [7:0] memOut;
always @(posedge clk) begin
if (CS && wr) memArray[address] = Di;
end
always @(posedge clk) begin
memOut = memArray[address];
Do = (CS && !wr) ? memOut : 8'b0;
end
endmodule
| 7.897952 |
module smallRAM (
rw,
dataIn,
CS,
address,
clk,
dataOut
);
input rw;
input [7:0] dataIn;
input [5:0] address;
input CS;
input clk;
parameter adr_width = 6;
parameter ram_depth = 1 << adr_width;
reg [7:0] memOut;
//reg[7:0]mem[0:ram_depth-1];
reg [7:0] mem[63:0];
output [7:0] dataOut;
always @(rw) begin
if (CS && rw) //Write
mem[address] = dataIn;
end
always @(clk) begin
memOut = mem[address]; //Read
end
assign dataOut = CS ? memOut : 8'b0;
//assign dataOut = CS?mem[address]:8'b0;
endmodule
| 7.897952 |
module SmallSerDes #(
parameter BYPASS_GCLK_FF = "FALSE", // TRUE, FALSE
parameter DATA_RATE_OQ = "DDR", // SDR, DDR | Data Rate setting
parameter DATA_RATE_OT = "DDR", // SDR, DDR, BUF | Tristate Rate setting.
parameter integer DATA_WIDTH = 2, // {1..8}
parameter OUTPUT_MODE = "SINGLE_ENDED", // SINGLE_ENDED, DIFFERENTIAL
parameter SERDES_MODE = "NONE", // NONE, MASTER, SLAVE
parameter integer TRAIN_PATTERN = 0 // {0..15}
) (
input wire CLK0,
input wire CLK1,
input wire CLKDIV,
input wire D1,
input wire D2,
input wire D3,
input wire D4,
input wire IOCE,
input wire OCE,
input wire RST,
input wire SHIFTIN1,
input wire SHIFTIN2,
input wire SHIFTIN3,
input wire SHIFTIN4,
input wire T1,
input wire T2,
input wire T3,
input wire T4,
input wire TCE,
input wire TRAIN,
output wire OQ,
output wire SHIFTOUT1,
output wire SHIFTOUT2,
output wire SHIFTOUT3,
output wire SHIFTOUT4,
output wire TQ
);
OSERDES2 #(
.BYPASS_GCLK_FF(BYPASS_GCLK_FF), // TRUE, FALSE
.DATA_RATE_OQ (DATA_RATE_OQ), // SDR, DDR | Data Rate setting
.DATA_RATE_OT (DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting.
.DATA_WIDTH (DATA_WIDTH), // {1..8}
.OUTPUT_MODE (OUTPUT_MODE), // SINGLE_ENDED, DIFFERENTIAL
.SERDES_MODE (SERDES_MODE), // NONE, MASTER, SLAVE
.TRAIN_PATTERN (TRAIN_PATTERN) // {0..15}
) serdes0 (
.OQ(OQ),
.SHIFTOUT1(SHIFTOUT1),
.SHIFTOUT2(SHIFTOUT2),
.SHIFTOUT3(SHIFTOUT3),
.SHIFTOUT4(SHIFTOUT4),
.TQ(TQ),
.CLK0(CLK0),
.CLK1(CLK1),
.CLKDIV(CLKDIV),
.D1(D1),
.D2(D2),
.D3(D3),
.D4(D4),
.IOCE(IOCE),
.OCE(OCE),
.RST(RST),
.SHIFTIN1(SHIFTIN1),
.SHIFTIN2(SHIFTIN2),
.SHIFTIN3(SHIFTIN3),
.SHIFTIN4(SHIFTIN4),
.T1(T1),
.T2(T2),
.T3(T3),
.T4(T4),
.TCE(TCE),
.TRAIN(TRAIN)
);
endmodule
| 7.981978 |
module small_async_fifo #(
parameter DSIZE = 8,
parameter ASIZE = 3,
parameter ALMOST_FULL_SIZE = 5,
parameter ALMOST_EMPTY_SIZE = 3
) (
//wr interface
output wfull,
output w_almost_full,
input [DSIZE-1:0] wdata,
input winc,
wclk,
wrst_n,
//rd interface
output [DSIZE-1:0] rdata,
output rempty,
output r_almost_empty,
input rinc,
rclk,
rrst_n
);
wire [ASIZE-1:0] waddr, raddr;
wire [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr;
sync_r2w #(ASIZE) sync_r2w (
.wq2_rptr(wq2_rptr),
.rptr(rptr),
.wclk(wclk),
.wrst_n(wrst_n)
);
sync_w2r #(ASIZE) sync_w2r (
.rq2_wptr(rq2_wptr),
.wptr(wptr),
.rclk(rclk),
.rrst_n(rrst_n)
);
fifo_mem #(DSIZE, ASIZE) fifo_mem (
.rdata (rdata),
.wdata (wdata),
.waddr (waddr),
.raddr (raddr),
.wclken(winc),
.wfull (wfull),
.wclk (wclk),
.wrst_n(wrst_n)
);
rptr_empty #(
.ADDRSIZE(ASIZE),
.ALMOST_EMPTY_SIZE(ALMOST_EMPTY_SIZE)
) rptr_empty (
.rempty(rempty),
.r_almost_empty(r_almost_empty),
.raddr(raddr),
.rptr(rptr),
.rq2_wptr(rq2_wptr),
.rinc(rinc),
.rclk(rclk),
.rrst_n(rrst_n)
);
wptr_full #(
.ADDRSIZE(ASIZE),
.ALMOST_FULL_SIZE(ALMOST_FULL_SIZE)
) wptr_full (
.wfull(wfull),
.w_almost_full(w_almost_full),
.waddr(waddr),
.wptr(wptr),
.wq2_rptr(wq2_rptr),
.winc(winc),
.wclk(wclk),
.wrst_n(wrst_n)
);
endmodule
| 7.661631 |
module rptr_empty #(
parameter ADDRSIZE = 3,
parameter ALMOST_EMPTY_SIZE = 3
) (
output reg rempty,
output reg r_almost_empty,
output [ADDRSIZE-1:0] raddr,
output reg [ADDRSIZE : 0] rptr,
input [ADDRSIZE : 0] rq2_wptr,
input rinc,
rclk,
rrst_n
);
reg [ADDRSIZE:0] rbin;
wire [ADDRSIZE:0] rgraynext, rbinnext;
reg [ADDRSIZE : 0] rq2_wptr_bin;
integer i;
//------------------
// GRAYSTYLE2 pointer
//------------------
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) {rbin, rptr} <= 0;
else {rbin, rptr} <= {rbinnext, rgraynext};
// Memory read-address pointer (okay to use binary to address memory)
assign raddr = rbin[ADDRSIZE-1:0];
assign rbinnext = rbin + (rinc & ~rempty);
assign rgraynext = (rbinnext >> 1) ^ rbinnext;
//--------------------------------------------------------------
// FIFO empty when the next rptr == synchronized wptr or on reset
//--------------------------------------------------------------
wire rempty_val = (rgraynext == rq2_wptr);
// Gray code to Binary code conversion
always @(rq2_wptr) for (i = 0; i < (ADDRSIZE + 1); i = i + 1) rq2_wptr_bin[i] = ^(rq2_wptr >> i);
wire [ADDRSIZE:0] subtract = (rbinnext + ALMOST_EMPTY_SIZE) - rq2_wptr_bin;
wire r_almost_empty_val = ~subtract[ADDRSIZE];
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) begin
rempty <= 1'b1;
r_almost_empty <= 1'b1;
end else begin
rempty <= rempty_val;
r_almost_empty <= r_almost_empty_val;
end
endmodule
| 7.624786 |
module wptr_full #(
parameter ADDRSIZE = 3,
parameter ALMOST_FULL_SIZE = 5
) (
output reg wfull,
output reg w_almost_full,
output [ADDRSIZE-1:0] waddr,
output reg [ADDRSIZE : 0] wptr,
input [ADDRSIZE : 0] wq2_rptr,
input winc,
wclk,
wrst_n
);
reg [ADDRSIZE:0] wbin;
wire [ADDRSIZE:0] wgraynext, wbinnext;
reg [ADDRSIZE : 0] wq2_rptr_bin;
integer i;
// GRAYSTYLE2 pointer
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) {wbin, wptr} <= 0;
else {wbin, wptr} <= {wbinnext, wgraynext};
// Memory write-address pointer (okay to use binary to address memory)
assign waddr = wbin[ADDRSIZE-1:0];
assign wbinnext = wbin + (winc & ~wfull);
assign wgraynext = (wbinnext >> 1) ^ wbinnext;
//-----------------------------------------------------------------
// Simplified version of the three necessary full-tests:
// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&
// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&
// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
//-----------------------------------------------------------------
wire wfull_val = (wgraynext == {~wq2_rptr[ADDRSIZE:ADDRSIZE-1], wq2_rptr[ADDRSIZE-2:0]});
// Gray code to Binary code conversion
always @(wq2_rptr) for (i = 0; i < (ADDRSIZE + 1); i = i + 1) wq2_rptr_bin[i] = ^(wq2_rptr >> i);
wire [ADDRSIZE : 0] subtract = wbinnext - wq2_rptr_bin - ALMOST_FULL_SIZE;
wire w_almost_full_val = ~subtract[ADDRSIZE];
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) begin
wfull <= 1'b0;
w_almost_full <= 1'b0;
end else begin
wfull <= wfull_val;
w_almost_full <= w_almost_full_val;
end
endmodule
| 7.819773 |
module fifo_mem #(
parameter DATASIZE = 8, // Memory data word width
parameter ADDRSIZE = 3
) // Number of mem address bits
(
output [DATASIZE-1:0] rdata,
input [DATASIZE-1:0] wdata,
input [ADDRSIZE-1:0] waddr,
raddr,
input wclken,
wfull,
wclk,
wrst_n
);
//wire [DATASIZE-1:0] rdata;
// RTL Verilog memory model
localparam DEPTH = 1 << ADDRSIZE;
reg [DATASIZE-1:0] mem[0:DEPTH-1];
reg [ ADDRSIZE:0] i;
assign rdata = mem[raddr];
always @(posedge wclk)
if (~wrst_n)
for (i = 0; i < DEPTH; i = i + 1) begin : mem_reset
mem[i] <= 0;
end
// endgenerate
else if (wclken && !wfull) mem[waddr] <= wdata;
endmodule
| 7.22504 |
module dual_port_sync_sram_16x1_no_hold (
write_clk,
write_capture_data,
write_address,
write_data,
read_clk,
read_enable,
read_address,
read_data
);
input write_clk, write_capture_data;
input [3:0] write_address;
input write_data;
input read_clk, read_enable;
input [3:0] read_address;
output read_data;
`ifdef FIFOS_ARE_MADE_FROM_FLOPS
`else // FIFOS_ARE_MADE_FROM_FLOPS
`endif // FIFOS_ARE_MADE_FROM_FLOPS
`ifdef USE_VENDOR_SUPPLIED_DUAL_PORT_x16_SRAM_PRIMITIVE
`else // USE_VENDOR_SUPPLIED_DUAL_PORT_x16_SRAM_PRIMITIVE
// store 16 bits of state
reg PCI_Fifo_Mem[0:15]; // address values, not bits in address
// write port
always @(posedge write_clk) begin
if (write_capture_data) begin
PCI_Fifo_Mem[write_address[3:0]] <= write_data;
end
`NO_ELSE; // can't do blah <= blah, because address may be unknown
end
// Xilinx 4000 series and newer FPGAs contain a dual-port SRAM primitive with
// synchronous write and asynchronous read. Latch the read address to make
// this primitive behave like a synchronous read SRAM
// read port
reg [3:0] latched_read_data;
always @(posedge read_clk) begin
latched_read_data <= read_enable ? PCI_Fifo_Mem[read_address[3:0]] : latched_read_data;
end
assign read_data = latched_read_data;
`endif // USE_VENDOR_SUPPLIED_DUAL_PORT_x16_SRAM_PRIMITIVE
endmodule
| 7.218562 |
module small_fifo #(
parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2 ** MAX_DEPTH_BITS - 1
) (
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output reg [WIDTH-1:0] dout, // Data out
output full,
output nearly_full,
output prog_full,
output empty,
input reset,
input clk
);
localparam MAX_DEPTH = 2 ** MAX_DEPTH_BITS;
reg [WIDTH-1:0] queue[MAX_DEPTH - 1 : 0];
reg [MAX_DEPTH_BITS - 1 : 0] rd_ptr;
reg [MAX_DEPTH_BITS - 1 : 0] wr_ptr;
reg [MAX_DEPTH_BITS : 0] depth;
// Sample the data
always @(posedge clk) if (wr_en) queue[wr_ptr] <= din;
always @(posedge clk)
if (reset) dout <= 0;
else if (rd_en) dout <= queue[rd_ptr];
always @(posedge clk) begin
if (reset) begin
rd_ptr <= 'h0;
wr_ptr <= 'h0;
depth <= 'h0;
end else begin
if (wr_en) wr_ptr <= wr_ptr + 'h1;
if (rd_en) rd_ptr <= rd_ptr + 'h1;
if (wr_en & ~rd_en) depth <= depth + 'h1;
else if (~wr_en & rd_en) depth <= depth - 'h1;
end
end
//assign dout = queue[rd_ptr];
assign full = depth == MAX_DEPTH;
assign prog_full = (depth >= PROG_FULL_THRESHOLD);
assign nearly_full = depth >= MAX_DEPTH - 1;
assign empty = depth == 'h0;
// synthesis translate_off
always @(posedge clk) begin
if (wr_en && depth == MAX_DEPTH && !rd_en)
$display($time, " ERROR: Attempt to write to full FIFO: %m");
if (rd_en && depth == 'h0) $display($time, " ERROR: Attempt to read an empty FIFO: %m");
end
// synthesis translate_on
endmodule
| 8.156562 |
module Small_FIFO_Testbench ();
// Setup fake clock
reg i_Clk = 1;
always #1 i_Clk = !i_Clk;
// Local vars
reg ri_Rst = 1'b1;
reg [7:0] ri_Byte = 8'b0;
reg ri_Append_Now = 0;
reg ri_Shift_Now = 0;
wire [7:0] wo_Byte;
wire [2:0] wo_Free_Space;
// Instantiate unit to test
Small_FIFO Small_FIFO (
.i_Rst(ri_Rst),
.i_Clk(i_Clk),
.i_Byte(ri_Byte),
.i_Append_Now(ri_Append_Now),
.i_Shift_Now(ri_Shift_Now),
.o_Byte(wo_Byte),
.o_Free_Space(wo_Free_Space)
);
// Test code
initial begin
#2 ri_Rst = 1'b0;
#4 ri_Byte = 8'b00101010;
ri_Append_Now = 1'b1;
#2 ri_Byte = ~ri_Byte;
#2 ri_Shift_Now = 1'b1;
ri_Byte = ~ri_Byte;
#2 ri_Shift_Now = 1'b0;
ri_Byte = ~ri_Byte;
#2 ri_Shift_Now = 1'b1;
ri_Byte = ~ri_Byte;
#2 ri_Byte = ~ri_Byte;
#2 ri_Byte = ~ri_Byte;
#2 ri_Append_Now = 1'b0;
#16 $finish;
end
initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
endmodule
| 6.931689 |
module small_fifo_twothresh #(
parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2 ** MAX_DEPTH_BITS - 1,
parameter PROG_FULL_THRESHOLD_EARLY = 2 ** MAX_DEPTH_BITS - 1
) (
input [ WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input [MAX_DEPTH_BITS-1:0] threshold, // threshold
input rd_en, // Read the next word
output reg [ WIDTH-1:0] dout, // Data out
output full,
output nearly_full,
output prog_full,
output empty,
output reg [MAX_DEPTH_BITS:0] depth, // queue length
input reset,
input clk
);
parameter MAX_DEPTH = 2 ** MAX_DEPTH_BITS;
reg [WIDTH-1:0] queue[MAX_DEPTH - 1 : 0];
reg [MAX_DEPTH_BITS - 1 : 0] rd_ptr;
reg [MAX_DEPTH_BITS - 1 : 0] wr_ptr;
//reg [MAX_DEPTH_BITS : 0] depth;
// Sample the data
always @(posedge clk) begin
if (wr_en) queue[wr_ptr] <= din;
if (rd_en)
dout <=
// synthesis translate_off
#1
// synthesis translate_on
queue[rd_ptr];
end
always @(posedge clk) begin
if (reset) begin
rd_ptr <= 'h0;
wr_ptr <= 'h0;
depth <= 'h0;
end else begin
if (wr_en) wr_ptr <= wr_ptr + 'h1;
if (rd_en) rd_ptr <= rd_ptr + 'h1;
if (wr_en & ~rd_en)
depth <=
// synthesis translate_off
#1
// synthesis translate_on
depth + 'h1;
else if (~wr_en & rd_en)
depth <=
// synthesis translate_off
#1
// synthesis translate_on
depth - 'h1;
end
end
assign full = depth == MAX_DEPTH;
// assign nearly_full = depth >= MAX_DEPTH-1;
assign nearly_full = (depth >= threshold);
assign prog_full = (depth >= threshold - 1600 * 3 / 32); // compare in #words
assign empty = depth == 'h0;
// synthesis translate_off
always @(posedge clk) begin
if (wr_en && depth == MAX_DEPTH && !rd_en)
$display($time, " ERROR: Attempt to write to full FIFO: %m");
if (rd_en && depth == 'h0) $display($time, " ERROR: Attempt to read an empty FIFO: %m");
end
// synthesis translate_on
endmodule
| 7.996578 |
module small_fifo_tester ();
reg [31:0] din = 0;
reg wr_en = 0;
reg rd_en = 0;
wire [31:0] dout;
wire full;
wire nearly_full;
wire prog_full;
wire empty;
reg clk = 0;
reg reset = 0;
integer count = 0;
always #8 clk = ~clk;
small_fifo #(
.WIDTH(32),
.MAX_DEPTH_BITS(3),
.PROG_FULL_THRESHOLD(4)
) fifo (
.din (din),
.wr_en (wr_en),
.rd_en (rd_en),
.dout (dout),
.full (full),
.nearly_full(nearly_full),
.prog_full (prog_full),
.empty (empty),
.reset (reset),
.clk (clk)
);
always @(posedge clk) begin
count <= count + 1;
reset <= 0;
wr_en <= 0;
rd_en <= 0;
if (count < 2) begin
reset <= 1'b1;
end else if (count < 2 + 8) begin
wr_en <= 1;
din <= din + 1'b1;
end else if (count < 2 + 8 + 3) begin
rd_en <= 1;
end else if (count < 2 + 8 + 3 + 2) begin
din <= din + 1'b1;
wr_en <= 1'b1;
end else if (count < 2 + 8 + 3 + 2 + 8) begin
din <= din + 1'b1;
wr_en <= 1'b1;
rd_en <= 1'b1;
end else if (count < 2 + 8 + 3 + 2 + 8 + 4) begin
rd_en <= 1'b1;
end else if (count < 2 + 8 + 3 + 2 + 8 + 4 + 8) begin
din <= din + 1'b1;
wr_en <= 1'b1;
rd_en <= 1'b1;
end
end // always @ (posedge clk)
endmodule
| 6.640033 |
module small_fifo #(
parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2 ** MAX_DEPTH_BITS - 1
) (
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output reg [WIDTH-1:0] dout, // Data out
output full,
output nearly_full,
output prog_full,
output empty,
input reset,
input clk
);
parameter MAX_DEPTH = 2 ** MAX_DEPTH_BITS;
reg [WIDTH-1:0] queue[MAX_DEPTH - 1 : 0];
reg [MAX_DEPTH_BITS - 1 : 0] rd_ptr;
reg [MAX_DEPTH_BITS - 1 : 0] wr_ptr;
reg [MAX_DEPTH_BITS : 0] depth;
// Sample the data
always @(posedge clk) begin
if (wr_en) queue[wr_ptr] <= din;
if (rd_en)
dout <=
// synthesis translate_off
#1
// synthesis translate_on
queue[rd_ptr];
end
always @(posedge clk) begin
if (reset) begin
rd_ptr <= 'h0;
wr_ptr <= 'h0;
depth <= 'h0;
end else begin
if (wr_en) wr_ptr <= wr_ptr + 'h1;
if (rd_en) rd_ptr <= rd_ptr + 'h1;
if (wr_en & ~rd_en)
depth <=
// synthesis translate_off
#1
// synthesis translate_on
depth + 'h1;
else if (~wr_en & rd_en)
depth <=
// synthesis translate_off
#1
// synthesis translate_on
depth - 'h1;
end
end
//assign dout = queue[rd_ptr];
assign full = depth == MAX_DEPTH;
assign prog_full = (depth >= PROG_FULL_THRESHOLD);
assign nearly_full = depth >= MAX_DEPTH - 1;
assign empty = depth == 'h0;
// synthesis translate_off
always @(posedge clk) begin
if (wr_en && depth == MAX_DEPTH && !rd_en)
$display($time, " ERROR: Attempt to write to full FIFO: %m");
if (rd_en && depth == 'h0) $display($time, " ERROR: Attempt to read an empty FIFO: %m");
end
// synthesis translate_on
endmodule
| 8.156562 |
module small_hb_dec #(
parameter WIDTH = 18
) (
input clk,
input rst,
input bypass,
input run,
input stb_in,
input [WIDTH-1:0] data_in,
output reg stb_out,
output [WIDTH-1:0] data_out
);
reg stb_in_d1;
reg [WIDTH-1:0] data_in_d1;
always @(posedge clk) stb_in_d1 <= stb_in;
always @(posedge clk) data_in_d1 <= data_in;
wire go;
reg phase, go_d1, go_d2, go_d3, go_d4;
always @(posedge clk)
if (rst | ~run) phase <= 0;
else if (stb_in_d1) phase <= ~phase;
assign go = stb_in_d1 & phase;
always @(posedge clk)
if (rst | ~run) begin
go_d1 <= 0;
go_d2 <= 0;
go_d3 <= 0;
go_d4 <= 0;
end else begin
go_d1 <= go;
go_d2 <= go_d1;
go_d3 <= go_d2;
go_d4 <= go_d3;
end
wire [17:0] coeff_a = -10690;
wire [17:0] coeff_b = 75809;
reg [WIDTH-1:0] d1, d2, d3, d4, d5, d6;
always @(posedge clk)
if (stb_in_d1 | rst) begin
d1 <= data_in_d1;
d2 <= d1;
d3 <= d2;
d4 <= d3;
d5 <= d4;
d6 <= d5;
end
reg [17:0] sum_a, sum_b, middle, middle_d1;
wire [17:0] sum_a_unreg, sum_b_unreg;
add2 #(
.WIDTH(18)
) add2_a (
.in1(data_in_d1),
.in2(d6),
.sum(sum_a_unreg)
);
add2 #(
.WIDTH(18)
) add2_b (
.in1(d2),
.in2(d4),
.sum(sum_b_unreg)
);
always @(posedge clk)
if (go) begin
sum_a <= sum_a_unreg;
sum_b <= sum_b_unreg;
middle <= d3;
end
always @(posedge clk) if (go_d1) middle_d1 <= middle;
wire [17:0] sum = go_d1 ? sum_b : sum_a;
wire [17:0] coeff = go_d1 ? coeff_b : coeff_a;
wire [35:0] prod;
MULT18X18S mult (
.C (clk),
.CE(go_d1 | go_d2),
.R (rst),
.P (prod),
.A (coeff),
.B (sum)
);
reg [35:0] accum;
always @(posedge clk)
if (rst) accum <= 0;
else if (go_d2) accum <= {middle_d1[17], middle_d1[17], middle_d1, 16'd0} + {prod};
else if (go_d3) accum <= accum + {prod};
wire [17:0] accum_rnd;
round #(
.bits_in (36),
.bits_out(18)
) round_acc (
.in (accum),
.out(accum_rnd)
);
reg [17:0] final_sum;
always @(posedge clk)
if (bypass) final_sum <= data_in_d1;
else if (go_d4) final_sum <= accum_rnd;
assign data_out = final_sum;
always @(posedge clk)
if (rst) stb_out <= 0;
else if (bypass) stb_out <= stb_in_d1;
else stb_out <= go_d4;
endmodule
| 7.293552 |
module hb_dec_tb ();
// Parameters for instantiation
parameter clocks = 9'd2; // Number of clocks per input
parameter decim = 1; // Sets the filter to decimate
parameter rate = 2; // Sets the decimation rate
reg clock;
reg reset;
reg enable;
reg strobe_in;
reg signed [17:0] data_in;
wire strobe_out;
wire signed [17:0] data_out;
initial begin
$dumpfile("hb_dec_tb.vcd");
$dumpvars(0, hb_dec_tb);
end
// Setup the clock
initial clock = 1'b0;
always #5 clock <= ~clock;
// Come out of reset after a while
initial reset = 1'b1;
initial #1000 reset = 1'b0;
// Enable the entire system
initial enable = 1'b1;
// Instantiate UUT
/*
halfband_ideal
#(
.decim ( decim ),
.rate ( rate )
) uut(
.clock ( clock ),
.reset ( reset ),
.enable ( enable ),
.strobe_in ( strobe_in ),
.data_in ( data_in ),
.strobe_out ( strobe_out ),
.data_out ( data_out )
) ;
*/
small_hb_dec #(
.WIDTH(18)
) uut (
.clk(clock),
.rst(reset),
.bypass(0),
.stb_in(strobe_in),
.data_in(data_in),
.stb_out(strobe_out),
.data_out(data_out)
);
integer i, ri, ro, infile, outfile;
always @(posedge clock) begin
if (strobe_out) $display(data_out);
end
// Setup file IO
initial begin
infile = $fopen("input.dat", "r");
outfile = $fopen("output.dat", "r");
$timeformat(-9, 2, " ns", 10);
end
reg endofsim;
reg signed [17:0] compare;
integer noe;
initial noe = 0;
initial begin
// Initialize inputs
strobe_in <= 1'd0;
data_in <= 18'd0;
// Wait for reset to go away
@(negedge reset) #0;
// While we're still simulating ...
while (!endofsim) begin
// Write the input from the file or 0 if EOF...
@(posedge clock) begin
//#1 ;
strobe_in <= 1'b1;
if (!$feof(infile)) ri = $fscanf(infile, "%d", data_in);
else data_in <= 18'd0;
end
// Clocked in - set the strobe to 0 if the number of
// clocks per sample is greater than 1
if (clocks > 1) begin
@(posedge clock) begin
strobe_in <= 1'b0;
end
// Wait for the specified number of cycles
for (i = 0; i < (clocks - 2); i = i + 1) begin
@(posedge clock) #1;
end
end
end
// Print out the number of errors that occured
if (noe) $display("FAILED: %d errors during simulation", noe);
else $display("PASSED: Simulation successful");
$finish;
end
// Output comparison of simulated values versus known good values
always @(posedge clock) begin
if (reset) endofsim <= 1'b0;
else begin
if (!$feof(outfile)) begin
if (strobe_out) begin
ro = $fscanf(outfile, "%d\n", compare);
if (compare != data_out) begin
//$display( "%t: %d != %d", $realtime, data_out, compare ) ;
noe = noe + 1;
end
end
end else begin
// Signal end of simulation when no more outputs
endofsim <= 1'b1;
end
end
end
endmodule
| 7.173056 |
module small_hb_int_tb ();
// Parameters for instantiation
parameter clocks = 8'd1; // Number of clocks per output
parameter decim = 1; // Sets the filter to decimate
parameter rate = 2; // Sets the decimation rate
reg clock;
reg reset;
reg enable;
wire strobe_in;
reg signed [17:0] data_in;
wire strobe_out;
wire signed [17:0] data_out;
initial begin
$dumpfile("small_hb_int_tb.vcd");
$dumpvars(0, small_hb_int_tb);
end
// Setup the clock
initial clock = 1'b0;
always #5 clock <= ~clock;
// Come out of reset after a while
initial reset = 1'b1;
initial #1000 reset = 1'b0;
always @(posedge clock) enable <= ~reset;
// Instantiate UUT
/*
halfband_ideal
#(
.decim ( decim ),
.rate ( rate )
) uut(
.clock ( clock ),
.reset ( reset ),
.enable ( enable ),
.strobe_in ( strobe_in ),
.data_in ( data_in ),
.strobe_out ( strobe_out ),
.data_out ( data_out )
) ;
*/
cic_strober #(
.WIDTH(8)
) out_strober (
.clock(clock),
.reset(reset),
.enable(enable),
.rate(clocks),
.strobe_fast(1),
.strobe_slow(strobe_out)
);
cic_strober #(
.WIDTH(8)
) in_strober (
.clock(clock),
.reset(reset),
.enable(enable),
.rate(2),
.strobe_fast(strobe_out),
.strobe_slow(strobe_in)
);
small_hb_int #(
.WIDTH(18)
) uut (
.clk(clock),
.rst(reset),
.bypass(0),
.stb_in(strobe_in),
.data_in(data_in),
.stb_out(strobe_out),
.output_rate(clocks),
.data_out(data_out)
);
integer i, ri, ro, infile, outfile;
always @(posedge clock) begin
if (strobe_out) $display(data_out);
end
// Setup file IO
initial begin
infile = $fopen("input.dat", "r");
outfile = $fopen("output.dat", "r");
$timeformat(-9, 2, " ns", 10);
end
reg endofsim;
reg signed [17:0] compare;
integer noe;
initial noe = 0;
initial begin
// Initialize inputs
data_in <= 18'd0;
// Wait for reset to go away
@(negedge reset) #0;
// While we're still simulating ...
while (!endofsim) begin
// Write the input from the file or 0 if EOF...
@(negedge clock) begin
if (strobe_in)
if (!$feof(infile)) ri <= #1 $fscanf(infile, "%d", data_in);
else data_in <= 18'd0;
end
end
// Print out the number of errors that occured
if (noe) $display("FAILED: %d errors during simulation", noe);
else $display("PASSED: Simulation successful");
$finish;
end
// Output comparison of simulated values versus known good values
always @(posedge clock) begin
if (reset) endofsim <= 1'b0;
else begin
if (!$feof(outfile)) begin
if (strobe_out) begin
ro = $fscanf(outfile, "%d\n", compare);
if (compare != data_out) begin
//$display( "%t: %d != %d", $realtime, data_out, compare ) ;
noe = noe + 1;
end
end
end else begin
// Signal end of simulation when no more outputs
if ($feof(infile)) endofsim <= 1'b1;
end
end
end
endmodule
| 7.632595 |
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