code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module TBUFX16 (
Y,
A,
OE
);
output Y;
input A, OE;
// Function
bufif1 (Y, A, OE);
// Timing
specify
(A => Y) = 0;
(OE => Y) = 0;
endspecify
endmodule
| 6.879027 |
module TBUFX2 (
Y,
A,
OE
);
output Y;
input A, OE;
// Function
bufif1 (Y, A, OE);
// Timing
specify
(A => Y) = 0;
(OE => Y) = 0;
endspecify
endmodule
| 6.905349 |
module TBUFX20 (
Y,
A,
OE
);
output Y;
input A, OE;
// Function
bufif1 (Y, A, OE);
// Timing
specify
(A => Y) = 0;
(OE => Y) = 0;
endspecify
endmodule
| 7.162916 |
module TBUFX6 (
Y,
A,
OE
);
output Y;
input A, OE;
// Function
bufif1 (Y, A, OE);
// Timing
specify
(A => Y) = 0;
(OE => Y) = 0;
endspecify
endmodule
| 6.649416 |
module TBUFX8 (
Y,
A,
OE
);
output Y;
input A, OE;
// Function
bufif1 (Y, A, OE);
// Timing
specify
(A => Y) = 0;
(OE => Y) = 0;
endspecify
endmodule
| 6.928405 |
module TBUFXL (
Y,
A,
OE
);
output Y;
input A, OE;
// Function
bufif1 (Y, A, OE);
// Timing
specify
(A => Y) = 0;
(OE => Y) = 0;
endspecify
endmodule
| 6.635503 |
module slpf (
clk,
in,
out
);
output out;
input clk;
input in;
// Three buffers (as shift register) for the low pass filter
wire ubuff1;
wire ubuff2;
wire ubuff3;
// Signals from the ANDs of the buffers
wire ubuff12;
wire ubuff13;
wire ubuff23;
//The low pass filter: if any of th... | 6.722847 |
module slr_cross #(
parameter REGS_BEFORE = 1,
parameter REGS_AFTER = 1,
parameter WIDTH = 16
) (
input wire clk,
input wire [WIDTH-1 : 0] d,
output wire [WIDTH-1 : 0] q,
input wire sreset
);
(* shreg_extract="no" *)
reg [ WIDTH-1:0] regs_before;
... | 7.475964 |
module SLT (
input signed [31:0] a,
input signed [31:0] b,
output signed [31:0] r
);
assign r = (a < b) ? 1 : 0;
endmodule
| 7.651592 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
... | 7.610141 |
module Add2_CIN (
input [1:0] I0,
input [1:0] I1,
input CIN,
output [1:0] O
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
FullAdder inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(inst0_O),
.COUT(inst0_COUT)
);
FullAdder inst1 (
.I0(I0[1... | 6.821676 |
module SLT2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] inst0_O;
wire inst1_O;
Sub2 inst0 (
.I0(I0),
.I1(I1),
.O (inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h008E)
) inst1 (
.I0(inst0_O[1]),
.I1(I0[1]),
.I2(I1[1]),
.I3(1'b0),
... | 6.651349 |
module main (
input [3:0] J1,
output J3
);
wire inst0_O;
SLT2 inst0 (
.I0({J1[1], J1[0]}),
.I1({J1[3], J1[2]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module SLT2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] inst0_O;
wire inst1_O;
Sub2_cin1 inst0 (
.I0(I0),
.I1(I1),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) inst1 (
.I0(inst0_O[1]),
.I1(I0[1]),
.I2(I1[1]),
.O (inst1_O)
);
... | 6.651349 |
module SLT2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] inst0_O;
wire inst1_O;
Sub2_cin1 inst0 (
.I0(I0),
.I1(I1),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) inst1 (
.I0(inst0_O[1]),
.I1(I0[1]),
.I2(I1[1]),
.O (inst1_O)
);
... | 6.651349 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
... | 7.610141 |
module Add4_CIN (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
wire inst2_O;
wire inst2_COUT;
wire inst3_O;
wire inst3_COUT;
FullAdder inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(ins... | 7.507677 |
module SLT4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] inst0_O;
wire inst1_O;
Sub4 inst0 (
.I0(I0),
.I1(I1),
.O (inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h008E)
) inst1 (
.I0(inst0_O[3]),
.I1(I0[3]),
.I2(I1[3]),
.I3(1'b0),
... | 7.061606 |
module main (
input [7:0] J1,
output J3
);
wire inst0_O;
SLT4 inst0 (
.I0({J1[3], J1[2], J1[1], J1[0]}),
.I1({J1[7], J1[6], J1[5], J1[4]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module SLT4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] inst0_O;
wire inst1_O;
Sub4_cin1 inst0 (
.I0(I0),
.I1(I1),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) inst1 (
.I0(inst0_O[3]),
.I1(I0[3]),
.I2(I1[3]),
.O (inst1_O)
);
... | 7.061606 |
module main (
input [7:0] SWITCH,
output LED
);
wire inst0_O;
SLT4 inst0 (
.I0({SWITCH[3], SWITCH[2], SWITCH[1], SWITCH[0]}),
.I1({SWITCH[7], SWITCH[6], SWITCH[5], SWITCH[4]}),
.O (inst0_O)
);
assign LED = inst0_O;
endmodule
| 7.081372 |
module SLT4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] inst0_O;
wire inst1_O;
Sub4_cin1 inst0 (
.I0(I0),
.I1(I1),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) inst1 (
.I0(inst0_O[3]),
.I1(I0[3]),
.I2(I1[3]),
.O (inst1_O)
);
... | 7.061606 |
module slt_32bit (
out,
a,
b
);
output out;
input a, b;
reg [31:0] out;
wire [31:0] a, b;
always @(a or b) begin
if (a < b) out <= #2 32'h00000001;
else out <= #2 32'h00000000;
end
endmodule
| 6.81171 |
module SLTI (
Op,
slti_output
);
input wire [31:26] Op;
output wire slti_output;
wire NOTOp26;
wire NOTOp28;
wire NOTOp30;
wire NOTOp31;
assign slti_output = Op[29] & NOTOp31 & NOTOp30 & NOTOp28 & Op[27] & NOTOp26;
assign NOTOp31 = ~Op[31];
assign NOTOp30 = ~Op[30];
assign NOTOp28 ... | 7.066291 |
module SltiFunction (
input rs, // A
input immediate, // mB
output rt // slti
);
assign rt = (rs < immediate) ? 1 : 0;
endmodule
| 9.076799 |
module Sltsrcb (
ALUSrcB,
B,
Outimm,
SrcB
);
input [31:0] B, Outimm;
input ALUSrcB;
output [31:0] SrcB;
assign SrcB = ({32{ALUSrcB}} & Outimm) | (~{32{ALUSrcB}} & B);
endmodule
| 6.751776 |
module SLTU (
input [31:0] a,
input [31:0] b,
output [31:0] r,
output carry
);
assign r = (a < b) ? 1 : 0;
assign carry = (a < b) ? 1 : 0;
endmodule
| 7.205271 |
module SLT_n_bit (
SLT_out,
R2,
R3
);
parameter word_size = 32;
input [word_size-1:0] R2, R3;
output SLT_out;
wire [word_size-1:0] SUB_out;
wire c_out;
SUB_n_bit #(word_size) S1 (
c_out,
{SLT_out, SUB_out[word_size-1:1]},
R2,
R3
);
endmodule
| 7.227191 |
module slt_operator (
X,
Y,
Z
);
//parameter definitions
parameter BUSSIZE = 32;
//port definitions - customize for different bit widths
input wire [BUSSIZE-1:0] X, Y;
output wire [BUSSIZE-1:0] Z;
wire overflow;
wire [BUSSIZE-1:0] out;
cla_adder_32bit SUB_op (
.A(X),
.B(~Y),
... | 7.103161 |
module SlvAxi4ProtConvAXI4ID #(
parameter [0:0] ZERO_SLAVE_ID = 1'b1, // zero ID field
parameter integer ID_WIDTH = 1, // number of bits for ID (ie AID, WID, BID) - valid 1-8
parameter integer SLV_AXI4PRT_ADDRDEPTH = 8 // Number transations width - 1 => 2 transations, 2 => 4 transations, etc.
) (
... | 7.385033 |
modules library
// Project : vslzw
// -----------------------------------------------------------------------------
// File : slzw_lib.v
// Author : Simon Southwell
// Created : 2022-02-02
// Standard : Verilog 2001
// -----------------------------------------------------------------------------
... | 7.11392 |
module slzw_mem_occupied
#(parameter
MEMSIZE = 10240
)
(
input clk,
input reset_n,
input clr,
input [13:0] waddr,
input [13:0] raddr,
input set,
output occupied,
output busy
);
localparam OCCMEMSI... | 6.506855 |
module slzw_dictmem
#(parameter
MEMSIZE = 10240,
WIDTH = 8
)
(
input clk,
input [13:0] waddr,
input write,
input [WIDTH-1:0] wdata,
input [13:0] raddr,
output reg [WIDTH... | 6.906678 |
module slzw_fifo
#(parameter
DEPTH = 8,
WIDTH = 32,
NEARLYFULL = (DEPTH/2)
)
(
input clk,
input reset_n,
input clr,
input write,
input [WIDTH... | 6.57222 |
module Sl_3 (
//Entradas
input [25:0] SLInp_3,
//Salidas
output reg [27:0] SLOut_3
);
//2- Delcaracion de señales --> NA(No aplica)
//3- Cuerpo del modulo
assign SLOut_3 = SLInp_3 << 2;
endmodule
| 6.942169 |
module is a very simple sequential machine that behaves based off
// a vending machine that only accepts nickels 'n' and dimes 'd' one input at a time.
// ALthough there is nothing preventing multiple inputs at the same time, there should
// only be ONE input per clock cycle.
// The output is achieved when 15 cents ha... | 6.962172 |
module SM1 (
output wire RO_ENABLE,
output wire WR_ENABLE,
input wire DAVAIL,
input wire ROREQUEST,
input wire TRIGGER,
input wire clk,
input wire RODONE_n,
input wire rst
);
// state bits
parameter IDLE = 3'b000, // extra=0 WR_ENABLE=0 RO_ENABLE=0
ADC_RUNNING = 3'b010, /... | 7.554918 |
modules for a point ( for motor ) one coming from lfr module and second turn
// so this module is to filter those signals
module SM1511_FILTER(
input clk_50,node,
input [7:0]lfr,
input [7:0]nd,
output [7:0] speed
);
reg [7:0] speed2;
assign speed = speed2;
always @(posedge clk_5... | 6.505147 |
module sm2201_interface_board
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// Test scenario:
// 1. Read from register 106 (~7us) multiple times
// 2. Possibly we are expect that on isa data will be all 0
/////////////////////////////////////////////////////////////... | 6.62461 |
module sm2201_interface_board
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sm2201_interface_board_testbench;
// isa input signals
reg isa_clk;
reg isa_ior;
wire i... | 6.62461 |
module sm2201_interface_board
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// Test scenario:
// 1. Write CAMAC crate + station number TO Address and Interrupt register (ISA Addr 106h)
// 2.
// 3.
// 4.
// 5.
////////////////////////////////////////////////... | 6.62461 |
module sm3_core (
input i_clk, //clock
input i_rst, //reset high valid
input i_start, //high valid(only one clock)
input [511:0] i_data, //hash data input
input [255:0] i_vin, //hash init value input(not change before o_done valid)
output [255:0] o_vout,... | 6.644136 |
module sm4_core (
input i_clk,
input i_rst,
input i_flag, //1-encrypt,0-decrypt
input [127:0] i_key,
input i_key_en,
output o_key_ok,
input [127:0] i_din,
input i_din_en,
output [127:0] o_dout,
output o_dout_en
);
... | 6.794798 |
module sm4_dpc (
input i_clk,
input i_rst,
input i_flag, //1-encrpt,0-decrypt
input [1023:0] i_keyex,
input [ 127:0] i_din,
input i_din_en,
output [ 127:0] o_dout,
output o_dout_en,
output [ 31:0] o_sbox_din,
input [ 31:0... | 7.382222 |
module sm4_keyex (
input i_clk,
input i_rst,
input [ 127:0] i_key, //key
input i_key_en, //key init flag
output [128*8-1:0] o_exkey, //round key
output o_key_ok, //key init ok
output o_sbox_use,
output [ ... | 8.347973 |
module
//
// Finds arithmetic operations needed. Latches on the positive edge of the
// clock. There are 8 different types of operations, which come from bits
// 3-5 of the instruction.
//
module alu(res, opra, oprb, cin, cout, zout, sout, parity, auxcar, sel);
input [7:0] opra; // Input A
input [7:0] oprb;... | 7.196583 |
module smadder #(
parameter N = 4
) (
input wire [N-1:0] a,
b,
output reg [N-1:0] sum
);
reg [N-2:0] mag_a, mag_b, mag_sum, max, min;
reg sgn_a, sgn_b, sgn_sum;
always @* begin
mag_a = a[N-2:0];
mag_b = b[N-2:0];
sgn_a = a[N-1];
sgn_b = b[N-1];
// GET Min & Max
if (ma... | 6.550301 |
module mux4 (
din_0, // Mux first input
din_1, // Mux Second input
din_2, // Mux Thirsd input
din_3, // Mux Fourth input
sel, // Select input
mux_out // Mux output
);
//-----------Input Ports---------------
input din_0, din_1, din_2, din_3;
input [1:0] sel;
//-----------Output Port... | 6.593444 |
module SMALL14_CPU_reset_clk_0_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRES... | 7.049085 |
module smallALU (
in_0,
in_1,
out, // difference e1 and e2
sign_out // if e1 > e2 sign = 0 else = 1
);
input [7:0] in_0;
input [7:0] in_1;
output [7:0] out;
output sign_out;
wire [7:0] out_12, out_21;
wire cout_12, cout_21;
FS_8 FS_EXP_12 (
.a(in_0),
.b(in_1),
.cin(... | 7.961141 |
module smallALU_CLA (
in_0,
in_1,
out, // difference e1 and e2
sign_out // if e1 > e2 sign = 0 else = 1
);
input [7:0] in_0;
input [7:0] in_1;
output [7:0] out;
output sign_out;
wire [7:0] out_12, out_21;
wire cout_12, cout_21;
SUB_CLA_8 SUB_CLA_EXP_12 (
.iA(in_0),
.iB(in... | 7.432032 |
module IntXbar_4 (
input auto_int_in_3_0,
input auto_int_in_2_0,
input auto_int_in_1_0,
input auto_int_in_1_1,
input auto_int_in_0_0,
output auto_int_out_0,
output auto_int_out_1,
output auto_int_out_2,
output auto_i... | 6.908358 |
module BundleBroadcast (
input auto_in_0_clock,
output auto_out_0_clock,
output [29:0] io_covSum,
output metaAssert
);
wire [29:0] BundleBroadcast_covSum;
assign auto_out_0_clock = auto_in_0_clock; // @[LazyModule.scala 173:49]
assign BundleBroadcast_covSum = 30'h0;
assign... | 6.590851 |
module IntSyncCrossingSink (
input clock,
input auto_in_sync_0,
output auto_out_0,
output [29:0] io_covSum,
output metaAssert,
input metaReset,
input SynchronizerShiftReg_w1_d3_halt
);
wire SynchronizerShiftReg_w1_d3_clock; // @[ShiftReg.scala... | 6.689384 |
module IntSyncCrossingSink_1 (
input auto_in_sync_0,
input auto_in_sync_1,
output auto_out_0,
output auto_out_1,
output [29:0] io_covSum,
output metaAssert
);
wire [29:0] IntSyncCrossingSink_1_covSum;
assign auto_out_0 = auto_in_sync_0; // @[LazyModule.s... | 6.689384 |
module IntSyncCrossingSink_2 (
input auto_in_sync_0,
output auto_out_0,
output [29:0] io_covSum,
output metaAssert
);
wire [29:0] IntSyncCrossingSink_2_covSum;
assign auto_out_0 = auto_in_sync_0; // @[LazyModule.scala 173:49]
assign IntSyncCrossingSink_2_covSum = 30'h0;
as... | 6.689384 |
module HellaCacheArbiter (
output io_requestor_0_req_ready,
input io_requestor_0_req_valid,
input [39:0] io_requestor_0_req_bits_addr,
input io_requestor_0_s1_kill,
output io_requestor_0_s2_nack,
output io_requestor_0_resp_valid,
output [63:0] io_request... | 6.932065 |
module SynchronizerShiftReg_w1_d3 (
input clock,
input io_d,
output io_q,
output [29:0] io_covSum,
output metaAssert,
input metaReset
);
reg sync_0; // @[ShiftReg.scala 114:16]
reg [31:0] _RAND_0;
reg sync_1; // @[ShiftReg.scala 114:16]
reg [31:0] ... | 6.820992 |
module _1_60 (
input [ 2:0] io_x,
output [ 2:0] io_y,
output [29:0] io_covSum,
output metaAssert
);
wire [29:0] _1_60_covSum;
assign io_y = io_x; // @[package.scala 218:12]
assign _1_60_covSum = 30'h0;
assign io_covSum = _1_60_covSum;
assign metaAssert = 1'h0;
endmodule
| 7.68074 |
module _1_61 (
input [53:0] io_x_ppn,
input io_x_d,
input io_x_a,
input io_x_g,
input io_x_u,
input io_x_x,
input io_x_w,
input io_x_r,
input io_x_v,
output [53:0] io_y_ppn,
output io_y_d,
output ... | 7.641073 |
module _1 (
input [19:0] io_x_ppn,
input io_x_u,
input io_x_ae,
input io_x_sw,
input io_x_sx,
input io_x_sr,
input io_x_pw,
input io_x_px,
input io_x_pr,
input io_x_pal,
input io_x_paa,
input... | 8.316516 |
module BranchDecode_3 (
input [31:0] io_inst,
input [39:0] io_pc,
output io_is_br,
output io_is_jal,
output io_is_jalr,
output io_is_call,
output [39:0] io_target,
output [ 2:0] io_cfi_type,
output [29:0] io_covSum,
output metaAssert
);
wire... | 7.279076 |
module UOPCodeFDivDecoder (
input [ 8:0] io_uopc,
output io_sigs_singleIn,
output io_sigs_div,
output io_sigs_sqrt,
output [29:0] io_covSum,
output metaAssert
);
wire [8:0] _T_2; // @[Decode.scala 14:65]
wire _T_3; // @[Decode.scala 14:121]
wire [8:0] _T_4; ... | 7.175893 |
module FMADecoder (
input [ 8:0] io_uopc,
output [ 1:0] io_cmd,
output [29:0] io_covSum,
output metaAssert
);
wire [8:0] _T; // @[Decode.scala 14:65]
wire _T_1; // @[Decode.scala 14:121]
wire [8:0] _T_2; // @[Decode.scala 14:65]
wire _T_3; // @[Decode.scala 14:121]
wire [8:0] _T_4;... | 6.646488 |
module RoundAnyRawFNToRecFN_5 (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [24:0] io_in_sig,
output [64:0] io_out,
output [29:0] io_covSum,
output ... | 7.169444 |
module RoundRawFNToRecFN_2 (
input io_invalidExc,
input io_infiniteExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
ou... | 6.992477 |
module RoundRawFNToRecFN (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
input io_detectTininess,
o... | 6.992477 |
module RoundRawFNToRecFN_1 (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [26:0] io_in_sig,
input [ 2:0] io_roundingMode,
input io_detectTininess,
... | 6.992477 |
module IntXbar_4 (
input auto_int_in_3_0,
input auto_int_in_2_0,
input auto_int_in_1_0,
input auto_int_in_1_1,
input auto_int_in_0_0,
output auto_int_out_0,
output auto_int_out_1,
output auto_int_out_2,
output auto_i... | 6.908358 |
module IntSyncAsyncCrossingSink (
input clock,
input auto_in_sync_0,
output auto_out_0,
output [29:0] io_covSum,
output metaAssert,
input metaReset,
input SynchronizerShiftReg_w1_d3_halt
);
wire SynchronizerShiftReg_w1_d3_clock; // @[ShiftReg.... | 6.70996 |
module HellaCacheArbiter (
output io_requestor_0_req_ready,
input io_requestor_0_req_valid,
input [39:0] io_requestor_0_req_bits_addr,
input io_requestor_0_s1_kill,
output io_requestor_0_s2_nack,
output io_requestor_0_resp_valid,
output [63:0] io_request... | 6.932065 |
module SynchronizerShiftReg_w1_d3 (
input clock,
input io_d,
output io_q,
output [29:0] io_covSum,
output metaAssert,
input metaReset,
input NonSyncResetSynchronizerPrimitiveShiftReg_d3_halt
);
wire NonSyncResetSynchronizerPrimitiveShiftReg_d3_... | 6.820992 |
module package_Anon_60 (
input [ 2:0] io_x,
output [ 2:0] io_y,
output [29:0] io_covSum,
output metaAssert
);
wire [29:0] package_Anon_60_covSum;
assign io_y = io_x; // @[package.scala 218:12]
assign package_Anon_60_covSum = 30'h0;
assign io_covSum = package_Anon_60_covSum;
assign met... | 7.042728 |
module package_Anon_61 (
input [53:0] io_x_ppn,
input io_x_d,
input io_x_a,
input io_x_g,
input io_x_u,
input io_x_x,
input io_x_w,
input io_x_r,
input io_x_v,
output [53:0] io_y_ppn,
output io_y_d,
o... | 7.042728 |
module package_Anon (
input [19:0] io_x_ppn,
input io_x_u,
input io_x_ae,
input io_x_sw,
input io_x_sx,
input io_x_sr,
input io_x_pw,
input io_x_px,
input io_x_pr,
input io_x_pal,
input io_x_paa,... | 7.745937 |
module UOPCodeFDivDecoder (
input [ 6:0] io_uopc,
output io_sigs_singleIn,
output io_sigs_div,
output io_sigs_sqrt,
output [29:0] io_covSum,
output metaAssert
);
wire [6:0] _T_2; // @[Decode.scala 14:65]
wire _T_3; // @[Decode.scala 14:121]
wire [6:0] _T_4; ... | 7.175893 |
module FMADecoder (
input [ 6:0] io_uopc,
output [ 1:0] io_cmd,
output [29:0] io_covSum,
output metaAssert
);
wire [6:0] _T; // @[Decode.scala 14:65]
wire _T_1; // @[Decode.scala 14:121]
wire [6:0] _T_2; // @[Decode.scala 14:65]
wire _T_3; // @[Decode.scala 14:121]
wire [6:0] _T_4;... | 6.646488 |
module RoundAnyRawFNToRecFN_5 (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [24:0] io_in_sig,
output [64:0] io_out,
output [29:0] io_covSum,
output ... | 7.169444 |
module RoundRawFNToRecFN_2 (
input io_invalidExc,
input io_infiniteExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
ou... | 6.992477 |
module RoundRawFNToRecFN (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
input io_detectTininess,
o... | 6.992477 |
module RoundRawFNToRecFN_1 (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [26:0] io_in_sig,
input [ 2:0] io_roundingMode,
input io_detectTininess,
... | 6.992477 |
module SmallOdds4Filter (
output io_in_ready,
input io_in_valid,
input [31:0] io_in_bits,
input io_out_ready,
output io_out_valid,
output [31:0] io_out_bits
);
wire _T_16 = io_in_bits < 32'ha; // @[SmallOdds4.scala 28:38]
assign io_in_ready = io_out_ready; /... | 6.891035 |
module SmallOdds4Filter_1 (
output io_in_ready,
input io_in_valid,
input [31:0] io_in_bits,
input io_out_ready,
output io_out_valid,
output [31:0] io_out_bits
);
wire [31:0] _T_16 = io_in_bits & 32'h1; // @[SmallOdds4.scala 30:52]
wire _T_18 = _T_16 == 32'h1; ... | 6.891035 |
module smallRAM (
wr,
Di,
CS,
address,
clk,
Do
);
input CS, wr, clk;
input [5:0] address;
input [7:0] Di;
output reg [7:0] Do;
reg [7:0] memArray[0:63];
reg [7:0] memOut;
always @(posedge clk) begin
if (CS) memArray[address] = Di;
end
always @(posedge clk) begin
m... | 7.897952 |
module smallRAM (
wr,
Di,
CS,
address,
clk,
Do
);
input CS, wr, clk;
input [5:0] address;
input [7:0] Di;
output reg [7:0] Do;
reg [7:0] memArray[0:63];
reg [7:0] memOut;
always @(posedge clk) begin
if (CS && wr) memArray[address] = Di;
end
always @(posedge clk) begin... | 7.897952 |
module smallRAM (
rw,
dataIn,
CS,
address,
clk,
dataOut
);
input rw;
input [7:0] dataIn;
input [5:0] address;
input CS;
input clk;
parameter adr_width = 6;
parameter ram_depth = 1 << adr_width;
reg [7:0] memOut;
//reg[7:0]mem[0:ram_depth-1];
reg [7:0] mem[63:0];
output... | 7.897952 |
module SmallSerDes #(
parameter BYPASS_GCLK_FF = "FALSE", // TRUE, FALSE
parameter DATA_RATE_OQ = "DDR", // SDR, DDR | Data Rate setting
parameter DATA_RATE_OT = "DDR", // SDR, DDR, BUF | Tristate Rate setting.
parameter integer DATA_WIDTH ... | 7.981978 |
module small_async_fifo #(
parameter DSIZE = 8,
parameter ASIZE = 3,
parameter ALMOST_FULL_SIZE = 5,
parameter ALMOST_EMPTY_SIZE = 3
) (
//wr interface
output wfull,
output w_almost_full,
input [DSIZE-1:0] wdata,
input winc,
wclk,
wrst_n,
//rd interface
output [DSIZE... | 7.661631 |
module rptr_empty #(
parameter ADDRSIZE = 3,
parameter ALMOST_EMPTY_SIZE = 3
) (
output reg rempty,
output reg r_almost_empty,
output [ADDRSIZE-1:0] raddr,
output reg [ADDRSIZE : 0] rptr,
input [ADDRSIZE : 0] rq2_wptr,
input rinc,
rclk,
rrst_n
);
reg [ADDRSIZE:0] rbin;
wire ... | 7.624786 |
module wptr_full #(
parameter ADDRSIZE = 3,
parameter ALMOST_FULL_SIZE = 5
) (
output reg wfull,
output reg w_almost_full,
output [ADDRSIZE-1:0] waddr,
output reg [ADDRSIZE : 0] wptr,
input [ADDRSIZE : 0] wq2_rptr,
input winc,
wclk,
wrst_n
);
reg [ADDRSIZE:0] wbin;
wire [ADD... | 7.819773 |
module fifo_mem #(
parameter DATASIZE = 8, // Memory data word width
parameter ADDRSIZE = 3
) // Number of mem address bits
(
output [DATASIZE-1:0] rdata,
input [DATASIZE-1:0] wdata,
input [ADDRSIZE-1:0] waddr,
raddr,
input wclken,
wfull,
wclk,
wrst_n
);
//wire [DATASIZE-1:... | 7.22504 |
module dual_port_sync_sram_16x1_no_hold (
write_clk,
write_capture_data,
write_address,
write_data,
read_clk,
read_enable,
read_address,
read_data
);
input write_clk, write_capture_data;
input [3:0] write_address;
input write_data;
input read_clk, read_enable;
input [3:0] read... | 7.218562 |
module small_fifo #(
parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2 ** MAX_DEPTH_BITS - 1
) (
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output reg [WIDTH-1:0] dout, // Dat... | 8.156562 |
module Small_FIFO_Testbench ();
// Setup fake clock
reg i_Clk = 1;
always #1 i_Clk = !i_Clk;
// Local vars
reg ri_Rst = 1'b1;
reg [7:0] ri_Byte = 8'b0;
reg ri_Append_Now = 0;
reg ri_Shift_Now = 0;
wire [7:0] wo_Byte;
wire [2:0] wo_Free_Space;
// Instantiate unit to test
Small_FIFO Small_FIFO (... | 6.931689 |
module small_fifo_twothresh #(
parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2 ** MAX_DEPTH_BITS - 1,
parameter PROG_FULL_THRESHOLD_EARLY = 2 ** MAX_DEPTH_BITS - 1
) (
input [ WIDTH-1:0] din, // Data in
input wr_en, //... | 7.996578 |
module small_fifo_tester ();
reg [31:0] din = 0;
reg wr_en = 0;
reg rd_en = 0;
wire [31:0] dout;
wire full;
wire nearly_full;
wire prog_full;
wire empty;
reg clk = 0;
reg reset = 0;
integer count = ... | 6.640033 |
module small_fifo #(
parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2 ** MAX_DEPTH_BITS - 1
) (
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output reg [WIDTH-1:0] dout, // Dat... | 8.156562 |
module small_hb_dec #(
parameter WIDTH = 18
) (
input clk,
input rst,
input bypass,
input run,
input stb_in,
input [WIDTH-1:0] data_in,
output reg stb_out,
output [WIDTH-1:0] data_out
);
reg stb_in_d1;
reg [WIDTH-1:0] data_in_d1;
always @(posedge clk) stb_in_d1 <= stb_in;
... | 7.293552 |
module hb_dec_tb ();
// Parameters for instantiation
parameter clocks = 9'd2; // Number of clocks per input
parameter decim = 1; // Sets the filter to decimate
parameter rate = 2; // Sets the decimation rate
reg clock;
reg reset;
reg enable;
reg ... | 7.173056 |
module small_hb_int_tb ();
// Parameters for instantiation
parameter clocks = 8'd1; // Number of clocks per output
parameter decim = 1; // Sets the filter to decimate
parameter rate = 2; // Sets the decimation rate
reg clock;
reg reset;
reg enable;
wire ... | 7.632595 |
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