code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module mux2 (
din_0, // Mux first input
din_1, // Mux Second input
sel, // Select input
mux_out // Mux output
);
//-----------Input Ports---------------
input din_0, din_1, sel;
//-----------Output Ports---------------
output mux_out;
//------------Internal Variables--------
reg mux_out;... | 7.210125 |
module small_mem (
CLK,
A,
D,
WE,
SPO
);
parameter addr_width = 3;
parameter data_width = 9;
input CLK;
input [addr_width-1:0] A;
input [data_width-1:0] D;
input WE;
output [data_width-1:0] SPO;
reg [data_width-1:0] mem[2**addr_width-1:0];
always @(posedge CLK) begin
if (WE) ... | 7.662759 |
module small_reg #(
parameter number_bits = 22
) (
input [2*number_bits-1:0] data_in,
input clk_50,
input rst_n,
input en,
output reg [2*number_bits-1:0] data_out
);
always @(posedge clk_50 or negedge rst_n) begin
if (!rst_n) data_out <= 0;
else if (en) data_out <= data_in;
end
endmo... | 8.263513 |
module processing_element (
reset,
clk,
b_data_sel,
in_a,
in_a_chain,
in_b,
in_c,
out_a,
out_a_chain,
out_b,
out_b0,
out_b1,
out_c,
b_data_valid_ping,
b_data_valid_pong,
mode
);
input reset;
input clk;
input b_data_sel;
input b_data_valid_ping;
... | 6.504296 |
module norm_sub (
input enable_norm,
input [`DWIDTH-1:0] mean,
input [`DWIDTH-1:0] inv_var,
input in_data_available,
input [`DWIDTH-1:0] inp_data,
output [`DWIDTH-1:0] out_data,
output out_data_available,
input validity_mask,
input clk,
input reset
);
reg out_data_available_in... | 6.769809 |
module ram (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
parameter AW = 11;
parameter MW = 8;
parameter DW = 8;
input [AW-1:0] addr0;
input [AW-1:0] addr1;
input [MW*DW-1:0] d0;
input [MW*DW-1:0] d1;
input [MW-1:0] we0;
input [MW-1:0] we1;
output reg [MW*DW-1... | 6.838627 |
module control (
input clk,
input reset,
input start_tpu,
input enable_matmul,
input enable_norm,
input enable_activation,
input enable_pool,
output reg start_mat_mul,
input done_mat_mul,
input done_norm,
input done_pool,
input done_activation,
input save_output_to_ac... | 7.715617 |
module smartbextdep (
input clock,
input bdep,
input [31:0] rs1,
input [31:0] rs2,
output reg [31:0] rd
);
wire din_mode;
wire [31:0] din_value;
wire [31:0] din_mask;
wire [31:0] dout_result;
assign din_mode = bdep;
assign din_value = rs1;
assign din_mask = rs2;
smartbextd... | 7.384523 |
module SmartHomeSystem (
input arst, // async reset
input clk, // clock posedge
input request,
input confirm,
input gds_din, // gas detector input
output [ 2:0] gds_dout, // gas detector output
input [ 1:0] password,
in... | 6.964961 |
module smart_buffer (
clock,
dataIn,
bit_done,
dataOut,
count,
full,
empty,
computer_ack_reset,
scrambler_reset,
arbiter_reset,
counter_reset,
ready_to_read
);
input clock, dataIn, bit_done, computer_ack_reset;
output full;
output empty;
output counter_reset;
o... | 7.30672 |
module smart_parking (
input entry,
input [7:0] parking_capacity,
input exit,
input [2:0] pattern,
input [7:0] time_out,
input [7:0] time_in,
output [7:0] new_capacity,
output [7:0] time_total,
output [3:0] parked,
output [3:0] empty
);
wire [7:0] parking_capacity_new;
wire... | 6.878364 |
module smash_fifo #(
parameter ADDR_SIZE = 1,
parameter DATA_SIZE = 32
) (
input i_clk,
i_rst,
input [DATA_SIZE - 1:0] i_data,
output [DATA_SIZE - 1:0] o_data,
input i_read,
input i_write,
output o_full,
output ... | 7.653411 |
module clkgen (
clkout,
tck_cts_0,
rst_b,
osc_clk,
cclk,
tck,
end_of_startup,
sample_mode_done,
md_spi,
md_jtag
);
output clkout;
input tck_cts_0;
input rst_b;
input osc_clk;
input cclk;
input tck;
input end_of_startup;
input sample_mode_done;
input md_spi;
in... | 6.653049 |
module clkgen (
rst_b,
VSS,
VDD,
tck_cts_0,
osc_clk_ovi_netlink_0,
clkout,
md_jtag,
md_spi,
sample_mode_done,
end_of_startup,
tck,
cclk,
osc_clk
);
input rst_b;
input VSS;
input VDD;
input tck_cts_0;
input osc_clk_ovi_netlink_0;
output clkout;
input md_j... | 6.653049 |
module clkgen (
osc_clk,
clkout_b,
j_tck_GB_G2B8I1ASTHIRNet269,
osc_clkASTHIRNet254,
spi_clk_out_GBASTHIRNet161,
clk_bASTHIRNet147,
j_tck_GBASTHIRNet101,
osc_clk_G1B8I1ASTHIRNet70,
rst_b,
spi_clk_out_GB_G4B1I2ASTHIRNet306,
cclk,
tck,
end_of_startup,
sample_mode_do... | 6.653049 |
module clkgen (
rst_b,
osc_clk,
cclk,
tck,
sample_mode_done,
md_spi,
md_jtag,
clkout,
clkout_b,
sample_mode_done_2,
spi_clk_in_2,
spi_clk_out_2,
tck_pad_2,
osc_clk_2,
sample_mode_done_1,
spi_clk_out_14,
tck_pad_8,
osc_clk_8,
spi_clk_in_6,
c... | 6.653049 |
module clkgen (
rst_b,
osc_clk,
cclk,
tck,
sample_mode_done,
md_spi,
md_jtag,
clkout,
clkout_b,
sample_mode_done_2,
spi_clk_in_2,
spi_clk_out_2,
tck_pad_2,
osc_clk_2,
sample_mode_done_1,
spi_clk_out_14,
tck_pad_8,
osc_clk_8,
spi_clk_in_6,
c... | 6.653049 |
module clkgen (
osc_clk,
clkout_b,
j_tck_GB_G2B8I1ASTHIRNet269,
osc_clkASTHIRNet254,
spi_clk_out_GBASTHIRNet161,
clk_bASTHIRNet147,
j_tck_GBASTHIRNet101,
osc_clk_G1B8I1ASTHIRNet70,
rst_b,
spi_clk_out_GB_G4B1I2ASTHIRNet306,
cclk,
tck,
end_of_startup,
sample_mode_do... | 6.653049 |
module clkgen (
clkout,
tck_cts_0,
rst_b,
osc_clk,
cclk,
tck,
end_of_startup,
sample_mode_done,
md_spi,
md_jtag
);
output clkout;
input tck_cts_0;
input rst_b;
input osc_clk;
input cclk;
input tck;
input end_of_startup;
input sample_mode_done;
input md_spi;
in... | 6.653049 |
module clkgen (
clkout,
tck_cts_0,
rst_b,
osc_clk,
cclk,
tck,
end_of_startup,
sample_mode_done,
md_spi,
md_jtag
);
output clkout;
input tck_cts_0;
input rst_b;
input osc_clk;
input cclk;
input tck;
input end_of_startup;
input sample_mode_done;
input md_spi;
in... | 6.653049 |
module SMC (
// Input signals0308
mode,
W_0,
V_GS_0,
V_DS_0,
W_1,
V_GS_1,
V_DS_1,
W_2,
V_GS_2,
V_DS_2,
W_3,
V_GS_3,
V_DS_3,
W_4,
V_GS_4,
V_DS_4,
W_5,
V_GS_5,
V_DS_5,
// Output signals
out_n
);
//==================================... | 6.818609 |
module SMC (
// Input signals
mode,
W_0,
V_GS_0,
V_DS_0,
W_1,
V_GS_1,
V_DS_1,
W_2,
V_GS_2,
V_DS_2,
W_3,
V_GS_3,
V_DS_3,
W_4,
V_GS_4,
V_DS_4,
W_5,
V_GS_5,
V_DS_5,
// Output signals
out_n
);
//======================================... | 6.818609 |
module SMC (
// Input signals
mode,
W_0,
V_GS_0,
V_DS_0,
W_1,
V_GS_1,
V_DS_1,
W_2,
V_GS_2,
V_DS_2,
W_3,
V_GS_3,
V_DS_3,
W_4,
V_GS_4,
V_DS_4,
W_5,
V_GS_5,
V_DS_5,
// Output signals
out_n
);
//======================================... | 6.818609 |
module
// BBQ bbq0(.meat(meat_0), .vagetable(vagetable_0), .water(water_0),.cost(cost[0]));
// --------------------------------------------------
// Example for continuous assignment
// assign out_n = XXX;
// --------------------------------------------------
// Example for procedure assignment
// always@(*) begin
//... | 6.804069 |
module Sorting (
i0,
i1,
i2,
i3,
i4,
i5,
n0,
n1,
n2,
n3,
n4,
n5
);
input wire [9:0] i0, i1, i2, i3, i4, i5;
output wire [9:0] n0, n1, n2, n3, n4, n5;
reg [9:0] tmp [0:5];
reg [9:0] swp;
integer i, j;
assign n0 = tmp[0];
assign n1 = tmp[1];
assign n2 = tm... | 6.901184 |
module MAX_min_Calculation (
mode,
n0,
n1,
n2,
n3,
n4,
n5,
out_n
);
input wire [1:0] mode;
input wire [9:0] n0, n1, n2, n3, n4, n5;
output reg [9:0] out_n;
always @(*) begin
case (mode)
2'b00: out_n = n3 + n4 + n5;
2'b01: out_n = (3 * n3) + (4 * n4) + (5 * n5);
... | 6.704127 |
module smdsixbutton (
input clk,
input p7, // DB9_PIN7 (SEL)
output reg [5:0] p = 6'b111111, // {DB9_PIN1, DB9_PIN2, DB9_PIN3, DB9_PIN4, DB9_PIN6, DB9_PIN9}
input up, // Up button
input dw, // Down button
input lf, // Left button
input rg, // Right button
input a, // A button
... | 7.352916 |
module smdsixbutton_tb;
// Inputs
reg p7; // Clock from Sega Mega Drive
reg up; // Up button
reg dw; // Down button
reg lf; // Left button
reg rg; // Right button
reg a; // A button
reg b; // B button
reg c; // C button
reg st; // Start button
reg x; // X button
reg y; // Y button
r... | 7.121867 |
module SMEMemoryMux (
input Select,
input [9:0] ReadAddressIn0, // Expanded for Rel 0 on 6/18
input [9:0] ReadAddressIn1, // Expanded for Rel 0 on 6/18
output [9:0] ReadAddressOut, // Expanded for Rel 0 on 6/18
input [9:0] WriteAddressIn0,
input [9:0] WriteAddressIn1,
output [9:0] W... | 6.685625 |
module SMEM_12x128 (
input clk,
output wire [11:0] DO,
input we,
input [11:0] DI,
input [6:0] Adr_wr,
input [6:0] Adr_rd
);
reg [11:0] MEM[127:0];
assign DO = MEM[Adr_rd];
initial // SMEM_12x128.txt
$readmemh("SMEM_12x128.txt", MEM, 0, 127);
always @(posedge clk) begin
MEM[A... | 7.239993 |
module fast_pattern_sme_wrapper (
input wire clk,
input wire rst,
// AXI Stream input
input wire [7:0] s_axis_tdata,
input wire s_axis_tvalid,
// Preamble state (7B data and 1B len)
input wire [8*8-1:0] preamble_state,
input wire reload,
// Match output
input ... | 6.896434 |
module smg (
clk,
data,
sm_wei,
sm_duan,
rst
);
input clk, rst;
input [15:0] data;
output [3:0] sm_wei;
output [7:0] sm_duan;
//----------------------------------------------------------
//ƵƵΪ100Hz
integer clk_cnt; //Ƶڼ
reg clk_100Hz;
always @(posedge clk)
if (rst == 1) begin ... | 7.175966 |
module smg_basemod (
input CLOCK,
RESET,
input [23:0] iData, //输入的数据
output [7:0] DIG, //八段数码管
output [5:0] SEL //位选
);
wire [9:0] DataU1;
smg_funcmod U1 (
.CLOCK(CLOCK),
.RESET(RESET),
.iData(iData), // < top
.oData(DataU1) // > U2
);
smg_encode_immdmod U2 (
... | 7.249227 |
module name: smg_clkdiv
////////////////////////////////
module smg_clkdiv
(
input clk_50MHz,
input rst,
output reg clk_1khz,
output reg clk_1hz,
output reg rdsig_nextdata
);
reg[15:0] cnt1;
reg[9:0] cnt2;
reg clk_1hz_buf;
//1khz分频
always @(posedge clk_50MHz or negedge rst)
begin
if(!rst)begin
clk_1kh... | 6.820156 |
module smg_control_module (
input CLK,
input RSTn,
input [23:0] Number_Sig,
output [3:0] Number_Data
);
/******************************************/
parameter T1MS = 16'd49999; //1ms
/******************************************/
reg [15:0] C1;
always @(posedge CLK or negedge RSTn)
if ... | 6.732436 |
module name: smg_demo
////////////////////////////////////
module smg_demo
(
input clk_50MHz,
input rst,
input[7:0] data,
output[5:0] smg_sig,
output[7:0] smg_data,
output rdsig_nextdata
);
wire clk_1khz, clk_1hz;
//clkdiv
smg_clkdiv smg_clkdiv_inst
(
.clk_50MHz(clk_50MHz),
.rst(rst),
.clk_1khz... | 6.701033 |
module name: smg_display
//功能说明：将串口接收的数据译码成16进制显示在两位数码管上
////////////////////////////////
module smg_display
(
input clk_1khz,
input clk_1hz,
input rst,
input[7:0] data,
output reg[5:0] smg_sig,
output reg[7:0] smg_data
);
//共阳数码管0~F编码:A~G、DP => data[0]~data[7]
parameter d0 = 8'hc0;
parameter d1 = 8... | 7.634222 |
module smg_encode_immdmod //译码器模块
(
input [3:0] iData, //三位输入
output [7:0] oData //八位输出
);
parameter _0 = 8'b0100_0000, _1 = 8'b0111_1001, _2 = 8'b0010_0100,
_3 = 8'b0011_0000, _4 = 8'b0001_1001, _5 = 8'b0001_0010,
_6 = 8'b0000_0010, _7 = 8'b0111_1000, _8 = 8'b0000_0000,
_9 = 8'... | 6.778864 |
module smg_interface (
input CLK,
input RSTn,
input [23:0] Number_Sig,
output [7:0] SMG_Data,
output [5:0] Scan_Sig
);
/******************************************/
wire [3:0] Number_Data;
smg_control_module U1 (
.CLK(CLK),
.RSTn(RSTn),
.Number_Sig(Number_Sig), // input - ... | 6.837269 |
module smg_ip_model (
clk,
data,
sm_wei,
sm_duan
);
input clk;
input [15:0] data;
output [3:0] sm_wei;
output [7:0] sm_duan;
//----------------------------------------------------------
//Ƶ
integer clk_cnt;
reg clk_400Hz;
always @(posedge clk)
if (clk_cnt == 32'd100000) begin
... | 7.777711 |
module smg_scan_module (
input CLK,
input RSTn,
output [5:0] Scan_Sig
);
/*****************************/
parameter T1MS = 16'd49999;
/*****************************/
reg [15:0] C1;
always @(posedge CLK or negedge RSTn)
if (!RSTn) C1 <= 16'd0;
else if (C1 == T1MS) C1 <= 16'd0;
else ... | 6.694266 |
module AND2HD1X (
A,
B,
Z
);
input A;
input B;
output Z;
and (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.817886 |
module AND2HD2X (
A,
B,
Z
);
input A;
input B;
output Z;
and (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.976181 |
module AND2HD2XSPG (
A,
B,
Z
);
input A;
input B;
output Z;
and (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.27383 |
module AND2HD4X (
A,
B,
Z
);
input A;
input B;
output Z;
and (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.723828 |
module AND2HD4XSPG (
A,
B,
Z
);
input A;
input B;
output Z;
and (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.985417 |
module AND2HDLX (
A,
B,
Z
);
input A;
input B;
output Z;
and (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.498798 |
module AND4HD2X (
A,
B,
C,
D,
Z
);
input A;
input B;
input C;
input D;
output Z;
and (I0_out, A, B);
and (I1_out, I0_out, C);
and (Z, I1_out, D);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
(D *> Z) = (0, 0);
endspecify
... | 6.690188 |
module BUFHD12X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.509705 |
module BUFCLKHD12X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.662943 |
module BUFCLKHD16X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.834503 |
module BUFCLKHD1X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.90195 |
module BUFCLKHD20X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.960907 |
module BUFCLKHD2X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.142603 |
module BUFCLKHD30X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.874562 |
module BUFCLKHD3X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.65332 |
module BUFCLKHD40X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.770549 |
module BUFCLKHD4X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.835126 |
module BUFCLKHD80X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.806863 |
module BUFCLKHD8X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.009914 |
module BUFCLKHDLX (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.513653 |
module BUFHD16X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.514206 |
module BUFHD1X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.336505 |
module BUFHD20X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.704684 |
module BUFHD2X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.947518 |
module BUFHD3X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.281553 |
module BUFHD4X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.576532 |
module BUFHD8X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.610824 |
module BUFHD8XSPG (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.988551 |
module BUFHDLX (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.022094 |
module BUFTSHD12X (
A,
E,
Z
);
input A;
input E;
output Z;
bufif1 (Z, A, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.588689 |
module BUFTSHD16X (
A,
E,
Z
);
input A;
input E;
output Z;
bufif1 (Z, A, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.841718 |
module BUFTSHD1X (
A,
E,
Z
);
input A;
input E;
output Z;
bufif1 (Z, A, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.793334 |
module BUFTSHD20X (
A,
E,
Z
);
input A;
input E;
output Z;
bufif1 (Z, A, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.954639 |
module BUFTSHD2X (
A,
E,
Z
);
input A;
input E;
output Z;
bufif1 (Z, A, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.839328 |
module BUFTSHD3X (
A,
E,
Z
);
input A;
input E;
output Z;
bufif1 (Z, A, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.609872 |
module BUFTSHD4X (
A,
E,
Z
);
input A;
input E;
output Z;
bufif1 (Z, A, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 7.023161 |
module BUFTSHD8X (
A,
E,
Z
);
input A;
input E;
output Z;
bufif1 (Z, A, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 7.118051 |
module BUFTSHDLX (
A,
E,
Z
);
input A;
input E;
output Z;
bufif1 (Z, A, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.52179 |
module DEL1HD1X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.361073 |
module DEL1HD1XSPG (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.097495 |
module DEL1HD2X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.705398 |
module DEL2HD1X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.8431 |
module DEL2HD1XSPG (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.432799 |
module DEL2HD2X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.852211 |
module DEL3HD1X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.220929 |
module DEL3HD2X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.490349 |
module DEL4HD1X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.575301 |
module DEL4HD1XSPG (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.178899 |
module DEL4HD2X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.785041 |
module INVHD12X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.776426 |
module INVCLKHD12X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.525768 |
module INVCLKHD16X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.739497 |
module INVCLKHD1X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.696387 |
module INVCLKHD20X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.034745 |
module INVCLKHD2X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.120877 |
module INVCLKHD30X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.856909 |
module INVCLKHD3X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.561527 |
module INVCLKHD40X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.645565 |
module INVCLKHD4X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.693005 |
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