code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module mux2 (
din_0, // Mux first input
din_1, // Mux Second input
sel, // Select input
mux_out // Mux output
);
//-----------Input Ports---------------
input din_0, din_1, sel;
//-----------Output Ports---------------
output mux_out;
//------------Internal Variables--------
reg mux_out;
//-------------Code Starts Here---------
always @* begin : MUX
case (sel)
1'b0: mux_out = din_0;
1'b1: mux_out = din_1;
endcase
end
endmodule
| 7.210125 |
module small_mem (
CLK,
A,
D,
WE,
SPO
);
parameter addr_width = 3;
parameter data_width = 9;
input CLK;
input [addr_width-1:0] A;
input [data_width-1:0] D;
input WE;
output [data_width-1:0] SPO;
reg [data_width-1:0] mem[2**addr_width-1:0];
always @(posedge CLK) begin
if (WE) begin
mem[A] = D;
end
end
assign SPO = mem[A];
endmodule
| 7.662759 |
module small_reg #(
parameter number_bits = 22
) (
input [2*number_bits-1:0] data_in,
input clk_50,
input rst_n,
input en,
output reg [2*number_bits-1:0] data_out
);
always @(posedge clk_50 or negedge rst_n) begin
if (!rst_n) data_out <= 0;
else if (en) data_out <= data_in;
end
endmodule
| 8.263513 |
module processing_element (
reset,
clk,
b_data_sel,
in_a,
in_a_chain,
in_b,
in_c,
out_a,
out_a_chain,
out_b,
out_b0,
out_b1,
out_c,
b_data_valid_ping,
b_data_valid_pong,
mode
);
input reset;
input clk;
input b_data_sel;
input b_data_valid_ping;
input b_data_valid_pong;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_a_chain;
input [`DWIDTH-1:0] in_b;
input [`DWIDTH-1:0] in_c;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_a_chain;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_b0;
output [`DWIDTH-1:0] out_b1;
output [`DWIDTH-1:0] out_c;
input mode;
`ifdef complex_dsp
wire [18:0] scanout;
wire [63:0] chainout; //unconnected
wire [63:0] result;
wire [17:0] ax;
wire [18:0] ay;
wire [35:0] bx;
wire [63:0] chainin;
wire [18:0] scanin;
wire [11:0] mode_sigs;
assign mode_sigs = 12'b010101010101; //Any value of mode_sigs (structural, not functional, correctness)
assign ax = {{(18 - `DWIDTH) {1'b0}}, in_a};
assign ay = {{(19 - `DWIDTH) {1'b0}}, in_b};
assign bx = 36'b0;
assign scanin = {{(18 - `DWIDTH) {1'b0}}, in_a_chain};
assign chainin = in_c;
//We will instantiate DSP slices with input chaining and output chaining.
//Input chaining is only supported in the 18x19 mode or the 27x27 mode.
//We will use the input chain provided by the DSP for the A input. For B, the chain will be manual.
mult_add_int u_pe (
.clk(clk),
.reset(reset),
.mode_sigs(mode_sigs),
.ax(ax),
.ay(ay),
.bx(bx),
.chainin(chainin),
.scanin(scanin),
.result(result),
.chainout(chainout),
.scanout(scanout)
);
reg [`DWIDTH-1:0] out_b0;
reg [`DWIDTH-1:0] out_b1;
wire [`DWIDTH-1:0] in_mac;
wire [`DWIDTH-1:0] out_c;
assign out_c = result;
assign in_mac = (b_data_sel == 0) ? out_b0 : out_b1;
assign out_a = result;
assign out_a_chain = scanout;
always @(posedge clk) begin
if (reset) begin
out_b0 <= 0;
end
if (b_data_valid_ping == 1) begin
out_b0 <= in_b;
end
end
always @(posedge clk) begin
if (reset) begin
out_b1 <= 0;
end
if (b_data_valid_pong == 1) begin
out_b1 <= in_b;
end
end
`else
reg [`DWIDTH-1:0] out_a;
reg [`DWIDTH-1:0] out_b;
reg [`DWIDTH-1:0] out_b0;
reg [`DWIDTH-1:0] out_b1;
wire [`DWIDTH-1:0] in_mac;
wire [`DWIDTH-1:0] out_c;
wire [`DWIDTH-1:0] out_mac;
assign out_c = out_mac;
assign in_mac = (b_data_sel == 0) ? out_b0 : out_b1;
seq_mac u_mac (
.a(out_a),
.b(in_mac),
.c(in_c),
.out(out_mac),
.reset(reset),
.clk(clk)
);
always @(posedge clk) begin
if (reset) begin
out_a <= 0;
end else begin
out_a <= mode ? in_a : in_a_chain;
end
end
assign out_a_chain = out_a;
always @(posedge clk) begin
if (reset) begin
out_b <= 0;
end else begin
out_b <= in_b;
end
end
always @(posedge clk) begin
if (reset) begin
out_b0 <= 0;
end
if (b_data_valid_ping == 1) begin
out_b0 <= in_b;
end
end
always @(posedge clk) begin
if (reset) begin
out_b1 <= 0;
end
if (b_data_valid_pong == 1) begin
out_b1 <= in_b;
end
end
`endif
endmodule
| 6.504296 |
module norm_sub (
input enable_norm,
input [`DWIDTH-1:0] mean,
input [`DWIDTH-1:0] inv_var,
input in_data_available,
input [`DWIDTH-1:0] inp_data,
output [`DWIDTH-1:0] out_data,
output out_data_available,
input validity_mask,
input clk,
input reset
);
reg out_data_available_internal;
wire [`DWIDTH-1:0] out_data_internal;
reg [`DWIDTH-1:0] mean_applied_data;
reg [`DWIDTH-1:0] variance_applied_data;
reg norm_in_progress;
//Muxing logic to handle the case when this block is disabled
assign out_data_available = (enable_norm) ? out_data_available_internal : in_data_available;
assign out_data = (enable_norm) ? out_data_internal : inp_data;
always @(posedge clk) begin
if ((reset || ~enable_norm)) begin
mean_applied_data <= 0;
variance_applied_data <= 0;
end else if (in_data_available || norm_in_progress) begin
//Let's apply mean and variance as the input data comes in.
//We have a pipeline here. First stage does the add (to apply the mean)
//and second stage does the multiplication (to apply the variance).
//Note: the following loop is not a loop across multiple columns of data.
//This loop will run in 2 cycle on the same column of data that comes into
//this module in 1 clock.
if (validity_mask == 1'b1) begin
mean_applied_data <= (inp_data - mean);
variance_applied_data <= (mean_applied_data * inv_var);
end else begin
mean_applied_data <= (inp_data);
variance_applied_data <= (mean_applied_data);
end
end else begin
mean_applied_data <= 0;
variance_applied_data <= 0;
end
end
//The data is normalized in two cycles so we are shifting in_data_available by 2 to generate out_data_available
always @(posedge clk) begin
norm_in_progress <= in_data_available;
out_data_available_internal <= norm_in_progress;
end
assign out_data_internal = variance_applied_data;
endmodule
| 6.769809 |
module ram (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
parameter AW = 11;
parameter MW = 8;
parameter DW = 8;
input [AW-1:0] addr0;
input [AW-1:0] addr1;
input [MW*DW-1:0] d0;
input [MW*DW-1:0] d1;
input [MW-1:0] we0;
input [MW-1:0] we1;
output reg [MW*DW-1:0] q0;
output reg [MW*DW-1:0] q1;
input clk;
`ifndef hard_mem
reg [MW*DW-1:0] ram[((1 << AW)-1):0];
wire we0_coalesced;
assign we0_coalesced = |we0;
wire we1_coalesced;
assign we1_coalesced = |we1;
always @(posedge clk) begin
if (we0_coalesced) ram[addr0] <= d0;
q0 <= ram[addr0];
end
always @(posedge clk) begin
if (we1_coalesced) ram[addr1] <= d1;
q1 <= ram[addr1];
end
`else
defparam u_dual_port_ram.ADDR_WIDTH = AW; defparam u_dual_port_ram.DATA_WIDTH = MW * DW;
dual_port_ram u_dual_port_ram (
.addr1(addr0),
.we1 (we0_coalesced),
.data1(d0),
.out1 (q0),
.addr2(addr1),
.we2 (we1_coalesced),
.data2(d1),
.out2 (q1),
.clk (clk)
);
`endif
endmodule
| 6.838627 |
module control (
input clk,
input reset,
input start_tpu,
input enable_matmul,
input enable_norm,
input enable_activation,
input enable_pool,
output reg start_mat_mul,
input done_mat_mul,
input done_norm,
input done_pool,
input done_activation,
input save_output_to_accum,
output reg done_tpu
);
reg [3:0] state;
`define STATE_INIT 4'b0000
`define STATE_MATMUL 4'b0001
`define STATE_NORM 4'b0010
`define STATE_POOL 4'b0011
`define STATE_ACTIVATION 4'b0100
`define STATE_DONE 4'b0101
//////////////////////////////////////////////////////
// Assumption: We will always run matmul first. That is, matmul is not optional.
// The other blocks - norm, act, pool - are optional.
// Assumption: Order is fixed: Matmul -> Norm -> Pool -> Activation
//////////////////////////////////////////////////////
always @(posedge clk) begin
if (reset) begin
state <= `STATE_INIT;
start_mat_mul <= 1'b0;
done_tpu <= 1'b0;
end else begin
case (state)
`STATE_INIT: begin
if ((start_tpu == 1'b1) && (done_tpu == 1'b0)) begin
if (enable_matmul == 1'b1) begin
start_mat_mul <= 1'b1;
state <= `STATE_MATMUL;
end
end
end
//start_mat_mul is kinda used as a reset in some logic
//inside the matmul unit. So, we can't make it 0 right away after
//asserting it.
`STATE_MATMUL: begin
if (done_mat_mul == 1'b1) begin
start_mat_mul <= 1'b0;
if (save_output_to_accum) begin
state <= `STATE_DONE;
end else if (enable_norm) begin
state <= `STATE_NORM;
end else if (enable_pool) begin
state <= `STATE_POOL;
end else if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end else begin
start_mat_mul <= 1'b1;
end
end
`STATE_NORM: begin
if (done_norm == 1'b1) begin
if (enable_pool) begin
state <= `STATE_POOL;
end else if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end
end
`STATE_POOL: begin
if (done_pool == 1'b1) begin
if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end
end
`STATE_ACTIVATION: begin
if (done_activation == 1'b1) begin
state <= `STATE_DONE;
end
end
`STATE_DONE: begin
//We need to write start_tpu to 0 in the CFG block to get out of this state
if (start_tpu == 1'b0) begin
state <= `STATE_INIT;
done_tpu <= 0;
end else begin
done_tpu <= 1;
end
end
endcase
end
end
endmodule
| 7.715617 |
module smartbextdep (
input clock,
input bdep,
input [31:0] rs1,
input [31:0] rs2,
output reg [31:0] rd
);
wire din_mode;
wire [31:0] din_value;
wire [31:0] din_mask;
wire [31:0] dout_result;
assign din_mode = bdep;
assign din_value = rs1;
assign din_mask = rs2;
smartbextdep_direct smartbextdep_direct_inst (
.din_mode (din_mode ),
.din_value (din_value ),
.din_mask (din_mask ),
.dout_result(dout_result)
);
always @(posedge clock) begin
rd <= dout_result;
end
endmodule
| 7.384523 |
module SmartHomeSystem (
input arst, // async reset
input clk, // clock posedge
input request,
input confirm,
input gds_din, // gas detector input
output [ 2:0] gds_dout, // gas detector output
input [ 1:0] password,
input [34:0] confdata,
input [31:0] tc_base,
input [15:0] adc_data,
output [31:0] tempc,
input [ 7:0] speed,
output [ 3:0] chs_power,
output chs_mode,
output pwm_data,
input [ 3:0] tcode,
output [ 3:0] wshade,
output [ 3:0] lightnum,
output [15:0] lightstate,
input dance_load,
output [ 7:0] dance_qdata,
output [ 2:0] dbg_state
);
wire [ 7:0] tc_ref;
wire [ 7:0] chs_conf;
wire [ 3:0] ulight;
wire [ 3:0] lenght;
wire [ 7:0] dance_pdata;
wire dance_din;
wire mem_wren;
wire [34:0] mem_in;
wire [34:0] mem_out;
wire [ 1:0] syskey;
assign tc_ref = mem_out[7:0];
assign chs_conf = mem_out[15:8];
assign lenght = mem_out[23:20];
assign ulight = mem_out[19:16];
assign dance_din = mem_out[32];
assign dance_pdata = mem_out[31:24];
assign syskey = mem_out[34:33];
TemperatureCalculator Module1 (
.tc_base (tc_base ),
.tc_ref (tc_ref ),
.adc_data(adc_data),
.tempc (tempc )
);
GasDetectorSensor Module2 (
.arst(arst),
.clk (clk),
.din (gds_din),
.dout(gds_dout)
);
CoolHeatSystem Module3 (
.arst (arst),
.clk (clk),
.speed (speed),
.chs_conf (chs_conf),
.chs_power(chs_power),
.chs_mode (chs_mode),
.pwm_data (pwm_data)
);
LightingSystem Module4 (
.tcode (tcode),
.ulight (ulight),
.lenght (lenght),
.wshade (wshade),
.lightnum (lightnum),
.lightstate(lightstate)
);
LightDance Module5 (
.arst (arst),
.clk (clk),
.din (dance_din),
.load (dance_load),
.pdata(dance_pdata),
.qdata(dance_qdata)
);
MemoryUnit Module6 (
.arst(arst),
.clk (clk),
.wren(mem_wren),
.din (mem_in),
.dout(mem_out)
);
ControlUnit Module7 (
.arst (arst),
.clk (clk),
.request (request),
.confirm (confirm),
.password (password),
.syskey (syskey),
.configin (confdata),
.configout(mem_in),
.write_en (mem_wren),
.dbg_state(dbg_state)
);
endmodule
| 6.964961 |
module smart_buffer (
clock,
dataIn,
bit_done,
dataOut,
count,
full,
empty,
computer_ack_reset,
scrambler_reset,
arbiter_reset,
counter_reset,
ready_to_read
);
input clock, dataIn, bit_done, computer_ack_reset;
output full;
output empty;
output counter_reset;
output arbiter_reset;
output scrambler_reset;
output reg ready_to_read;
output [7:0] dataOut;
output reg [3:0] count = 0;
assign full = (count == 8) ? 1'b1 : 1'b0;
assign empty = (count == 0) ? 1'b1 : 1'b0;
reg [7:0] tmp; // the internal buffer/memory. dataOut has full access to this
reg reset_r, reset_l, bit_done_on, bit_done_r1;
wire reset_counter = computer_ack_reset | reset_l;
wire reset_out = computer_ack_reset | reset_r;
assign {arbiter_reset, scrambler_reset} = {2{reset_out}};
assign counter_reset = reset_counter;
assign dataOut = tmp;
// Since "dataIn" and "bit_done" are two signals that come from the race arbiter (an asynchronous module)
// and this module is clocked, we need to use a FIFO to make sure the buffer successfully captures these signals.
// sync dataIn and bit_done
reg [3:0] sync_din_r, sync_done_r; // instantiating two FIFOs each four registers long
// First always block to define FIFO logic. Either reset or otherwise, shift into FIFO (on MSB side) on each clock cycle.
always @(posedge clock or posedge computer_ack_reset) begin
if (computer_ack_reset) begin
sync_din_r <= 4'h0;
sync_done_r <= 4'h0;
bit_done_on <= 1'b0;
end else begin
sync_din_r <= {dataIn, sync_din_r[3:1]};
sync_done_r <= {bit_done, sync_done_r[3:1]};
bit_done_on <= sync_done_r[1] & ~sync_done_r[0]; // bit_done_on is negative-edge triggered
end
end
// Second always block to define reset_r (local reset for scrambler and arbiter) logic. We want to make sure that reset_r
// asserts at least two clock cycles from the time bit_done_on is asserted to ensure sufficient time to store the bit from
// data FIFO. From there, reset_l (for the counter) is asserted one clock cycle after reset_r (three clock cycles after
// bit_done_on)
always @(posedge clock or posedge computer_ack_reset) begin
if (computer_ack_reset) {reset_l, reset_r, bit_done_r1} <= 3'b000;
else
{reset_l, reset_r, bit_done_r1} <= {
reset_r, bit_done_r1, bit_done_on
}; // delay reset_r = 2 cycles from bit_done_on
end
// Third always block to define internal storage behavior.
always @(posedge clock or posedge computer_ack_reset) begin
if (computer_ack_reset) tmp <= 8'bXXXXXXXX;
else if (bit_done_on) tmp <= {tmp[6:0], sync_din_r[0]}; // read in from FIFO (on LSB) side
end
// Fourth always block to define when the response is "ready_to_read"
always @(posedge clock or posedge computer_ack_reset) begin
if (computer_ack_reset) begin
ready_to_read <= 1'b0;
count <= 0;
end else if (bit_done_on) begin
count <= count + 1;
if (count == 7) ready_to_read <= 1'b1;
end
end
endmodule
| 7.30672 |
module smart_parking (
input entry,
input [7:0] parking_capacity,
input exit,
input [2:0] pattern,
input [7:0] time_out,
input [7:0] time_in,
output [7:0] new_capacity,
output [7:0] time_total,
output [3:0] parked,
output [3:0] empty
);
wire [7:0] parking_capacity_new;
wire [7:0] cap;
update_capacity update_capacity0 (
entry,
parking_capacity,
parking_capacity_new,
cap
);
wire [2:0] park_number;
entry_park entry_park0 (
entry,
parking_capacity,
park_number
);
wire [2:0] token;
token_production token_production0 (
park_number,
pattern,
token
);
wire [7:0] park_location;
exit_park exit_park0 (
exit,
token,
pattern,
park_location
);
calculate_new_capacity calculate_new_capacity0 (
park_location,
parking_capacity_new,
new_capacity
);
parking_capacity_counter parking_capacity_counter0 (
new_capacity,
parked,
empty
);
time_calculate time_calculate0 (
time_out,
time_in,
time_total
);
endmodule
| 6.878364 |
module smash_fifo #(
parameter ADDR_SIZE = 1,
parameter DATA_SIZE = 32
) (
input i_clk,
i_rst,
input [DATA_SIZE - 1:0] i_data,
output [DATA_SIZE - 1:0] o_data,
input i_read,
input i_write,
output o_full,
output o_empty
);
reg [DATA_SIZE - 1:0] mem[0:2 ** (ADDR_SIZE - 1)];
reg [ADDR_SIZE - 1:0] read_ptr;
reg [ADDR_SIZE - 1:0] write_ptr;
reg empty;
assign o_empty = empty;
assign o_full = !empty && (read_ptr == write_ptr);
assign o_data = mem[read_ptr];
always @(posedge i_clk) begin
if (i_rst) begin
read_ptr <= 'd0;
write_ptr <= 'd0;
empty <= 'b1;
end else begin
if (i_write && !o_full) begin
if (i_read && !empty) begin
mem[write_ptr] <= i_data;
end else begin
write_ptr <= write_ptr + 'd1;
mem[write_ptr] <= i_data;
empty <= 'b0;
end
end else if (i_read && !empty) begin
read_ptr <= read_ptr + 'd1;
if ((read_ptr + 'd1) == write_ptr) begin
empty <= 'b1;
end
end
end
end
endmodule
| 7.653411 |
module clkgen (
clkout,
tck_cts_0,
rst_b,
osc_clk,
cclk,
tck,
end_of_startup,
sample_mode_done,
md_spi,
md_jtag
);
output clkout;
input tck_cts_0;
input rst_b;
input osc_clk;
input cclk;
input tck;
input end_of_startup;
input sample_mode_done;
input md_spi;
input md_jtag;
clk_gfsw_0 clksw2 (
.rst_b(rst_b),
.clka(clksw1_out),
.clkb(tck),
.sel(sel_jtag_clk),
.clkout(clkout),
.clkb_cts_0(tck_cts_0)
);
clk_gfsw_1 clksw1 (
.rst_b(rst_b),
.clka(cclk_int),
.clkb(osc_clk),
.sel(sel_spi_clk),
.clkout(clksw1_out)
);
SEH_ND2B_1 U3 (
.A(md_spi),
.B(sample_mode_done),
.X(sel_spi_clk)
);
SEH_NR2B_1 U2 (
.A(cclk),
.B(end_of_startup),
.X(cclk_int)
);
SEH_AN2_S_0P5 U1 (
.A1(sample_mode_done),
.A2(md_jtag)
, .X (sel_jtag_clk)
);
endmodule
| 6.653049 |
module clkgen (
rst_b,
VSS,
VDD,
tck_cts_0,
osc_clk_ovi_netlink_0,
clkout,
md_jtag,
md_spi,
sample_mode_done,
end_of_startup,
tck,
cclk,
osc_clk
);
input rst_b;
input VSS;
input VDD;
input tck_cts_0;
input osc_clk_ovi_netlink_0;
output clkout;
input md_jtag;
input md_spi;
input sample_mode_done;
input end_of_startup;
input tck;
input cclk;
input osc_clk;
clk_gfsw_0 clksw2 (
.rst_b(rst_b),
.clka(clksw1_out),
.clkb(tck),
.sel(sel_jtag_clk),
.clkout(clkout),
.VSS(1'b0),
.VDD(1'b1),
.clkb_cts_0(tck_cts_0)
);
clk_gfsw_1 clksw1 (
.rst_b(rst_b),
.clka(cclk_int),
.clkb(osc_clk),
.sel(sel_spi_clk),
.clkout(clksw1_out),
.VSS(1'b0),
.VDD(1'b1),
.clkb_ovi_netlink_0(osc_clk_ovi_netlink_0)
);
AN2XD1BWPHVT U3 (
.A1(md_jtag),
.A2(sample_mode_done)
, .Z (sel_jtag_clk)
);
INR2D1BWPHVT U2 (
.A1(cclk),
.ZN(cclk_int),
.B1(end_of_startup)
);
IND2D1BWPHVT U1 (
.A1(md_spi),
.B1(sample_mode_done)
, .ZN(sel_spi_clk)
);
endmodule
| 6.653049 |
module clkgen (
osc_clk,
clkout_b,
j_tck_GB_G2B8I1ASTHIRNet269,
osc_clkASTHIRNet254,
spi_clk_out_GBASTHIRNet161,
clk_bASTHIRNet147,
j_tck_GBASTHIRNet101,
osc_clk_G1B8I1ASTHIRNet70,
rst_b,
spi_clk_out_GB_G4B1I2ASTHIRNet306,
cclk,
tck,
end_of_startup,
sample_mode_done,
md_spi,
md_jtag,
clkout
);
input osc_clk;
output clkout_b;
input j_tck_GB_G2B8I1ASTHIRNet269;
input osc_clkASTHIRNet254;
output spi_clk_out_GBASTHIRNet161;
output clk_bASTHIRNet147;
input j_tck_GBASTHIRNet101;
input osc_clk_G1B8I1ASTHIRNet70;
input rst_b;
input spi_clk_out_GB_G4B1I2ASTHIRNet306;
input cclk;
input tck;
input end_of_startup;
input sample_mode_done;
input md_spi;
input md_jtag;
output clkout;
/* wire declarations */
wire clksw1_outASTHIRNet197;
wire n58ASTHIRNet174;
wire n55;
wire sel_jtag_clk;
wire sel_spi_clk;
wire n54;
wire n57;
wire n56;
clk_gfsw_1 clksw1 (
.osc_clkASTHIRNet252(osc_clkASTHIRNet254),
.clksw1_outASTHIRNet198(clksw1_outASTHIRNet197),
.n58ASTHIRNet176(n58ASTHIRNet174),
.osc_clk_G1B8I1ASTHIRNet68(osc_clk_G1B8I1ASTHIRNet70),
.rst_b(rst_b),
.sel(n55)
);
clk_gfsw_0 clksw2 (
.j_tck_GB_G2B8I1ASTHIRNet267(j_tck_GB_G2B8I1ASTHIRNet269),
.clksw1_outASTHIRNet200(clksw1_outASTHIRNet197),
.spi_clk_out_GBASTHIRNet159(spi_clk_out_GBASTHIRNet161),
.j_tck_GBASTHIRNet99(j_tck_GBASTHIRNet101),
.rst_b(rst_b),
.sel(sel_jtag_clk)
);
BUFFD0HVT U7 (
.I(sel_spi_clk),
.Z(n54)
);
CKBD0HVT U8 (
.I(n54),
.Z(n55)
);
CKBD0HVT U9 (
.I(n57),
.Z(n56)
);
INVD0HVT U10 (
.I (sample_mode_done),
.ZN(n57)
);
OR2D0HVT U11 (
.Z (sel_spi_clk),
.A1(md_spi),
.A2(n56)
);
IND2D4HVT U12 (
.A1(end_of_startup),
.B1(cclk),
.ZN(n58ASTHIRNet174)
);
AN2D2HVT U13 (
.A2(sample_mode_done),
.Z (sel_jtag_clk),
.A1(md_jtag)
);
CKND16HVT S_2 (
.ZN(clk_bASTHIRNet147)
, .I (spi_clk_out_GB_G4B1I2ASTHIRNet306)
);
endmodule
| 6.653049 |
module clkgen (
rst_b,
osc_clk,
cclk,
tck,
sample_mode_done,
md_spi,
md_jtag,
clkout,
clkout_b,
sample_mode_done_2,
spi_clk_in_2,
spi_clk_out_2,
tck_pad_2,
osc_clk_2,
sample_mode_done_1,
spi_clk_out_14,
tck_pad_8,
osc_clk_8,
spi_clk_in_6,
clk_b_1
);
input rst_b, osc_clk, cclk, tck, sample_mode_done, md_spi, md_jtag,
sample_mode_done_2, spi_clk_in_2, tck_pad_2, osc_clk_2, spi_clk_out_14,
tck_pad_8, osc_clk_8, spi_clk_in_6;
output clkout, clkout_b, spi_clk_out_2, sample_mode_done_1, clk_b_1;
wire clksw1_out, sel_jtag_clk, sel_spi_clk, clksw1_out_1, clksw1_out_2,
clksw1_out_3, clksw1_out_4, clksw1_out_5;
clk_gfsw_0 clksw2 (
.rst_b(rst_b),
.clka(),
.clkb(),
.sel(sel_jtag_clk),
.clkout(),
.spi_clk_out_2(spi_clk_out_2),
.tck_pad_2(tck_pad_2),
.clksw1_out_1(clksw1_out),
.tck_pad_8(tck_pad_8),
.clksw1_out_3(clksw1_out_3)
);
clk_gfsw_1 clksw1 (
.rst_b(rst_b),
.clka(),
.clkb(),
.sel(sel_spi_clk),
.clkout(),
.clksw1_out_1(clksw1_out),
.osc_clk_2(osc_clk_2),
.spi_clk_in_2(spi_clk_in_2),
.spi_clk_in_6(spi_clk_in_6),
.osc_clk_8(osc_clk_8)
);
CKAN2D1HVT U12_C1 (
.A1(sample_mode_done_2),
.A2(md_jtag),
.Z (sel_jtag_clk)
);
IND2D2HVT U11_C1 (
.A1(md_spi),
.B1(sample_mode_done_1),
.ZN(sel_spi_clk)
);
CKBD1HVT CLK_SYNC_SKEW_12 (
.I(clksw1_out_2),
.Z(clksw1_out_3)
);
CKBD1HVT CLK_SYNC_SKEW_14 (
.I(clksw1_out_4),
.Z(clksw1_out_5)
);
CKBD1HVT CLK_SYNC_SKEW_13 (
.I(clksw1_out_1),
.Z(clksw1_out_4)
);
CKBD1HVT CLK_SYNC_SKEW_11 (
.I(clksw1_out_5),
.Z(clksw1_out_2)
);
CKBD1HVT CLK_SYNC_SKEW_10 (
.I(clksw1_out),
.Z(clksw1_out_1)
);
CKND16HVT S_0_C1 (
.I (spi_clk_out_14),
.ZN(clk_b_1)
);
BUFFD2HVT OPTHOLD_G_70 (
.I(sample_mode_done_2),
.Z(sample_mode_done_1)
);
endmodule
| 6.653049 |
module clkgen (
rst_b,
osc_clk,
cclk,
tck,
sample_mode_done,
md_spi,
md_jtag,
clkout,
clkout_b,
sample_mode_done_2,
spi_clk_in_2,
spi_clk_out_2,
tck_pad_2,
osc_clk_2,
sample_mode_done_1,
spi_clk_out_14,
tck_pad_8,
osc_clk_8,
spi_clk_in_6,
clk_b_1
);
input rst_b, osc_clk, cclk, tck, sample_mode_done, md_spi, md_jtag,
sample_mode_done_2, spi_clk_in_2, tck_pad_2, osc_clk_2, spi_clk_out_14,
tck_pad_8, osc_clk_8, spi_clk_in_6;
output clkout, clkout_b, spi_clk_out_2, sample_mode_done_1, clk_b_1;
wire clksw1_out, sel_jtag_clk, sel_spi_clk, clksw1_out_1, clksw1_out_2,
clksw1_out_3, clksw1_out_4, clksw1_out_5;
clk_gfsw_0 clksw2 (
.rst_b(rst_b),
.clka(),
.clkb(),
.sel(sel_jtag_clk),
.clkout(),
.spi_clk_out_2(spi_clk_out_2),
.tck_pad_2(tck_pad_2),
.clksw1_out_1(clksw1_out),
.tck_pad_8(tck_pad_8),
.clksw1_out_3(clksw1_out_3)
);
clk_gfsw_1 clksw1 (
.rst_b(rst_b),
.clka(),
.clkb(),
.sel(sel_spi_clk),
.clkout(),
.clksw1_out_1(clksw1_out),
.osc_clk_2(osc_clk_2),
.spi_clk_in_2(spi_clk_in_2),
.spi_clk_in_6(spi_clk_in_6),
.osc_clk_8(osc_clk_8)
);
CKAN2D1HVT U12_C1 (
.A1(sample_mode_done_2),
.A2(md_jtag),
.Z (sel_jtag_clk)
);
IND2D2HVT U11_C1 (
.A1(md_spi),
.B1(sample_mode_done_1),
.ZN(sel_spi_clk)
);
CKBD1HVT CLK_SYNC_SKEW_12 (
.I(clksw1_out_2),
.Z(clksw1_out_3)
);
CKBD1HVT CLK_SYNC_SKEW_14 (
.I(clksw1_out_4),
.Z(clksw1_out_5)
);
CKBD1HVT CLK_SYNC_SKEW_13 (
.I(clksw1_out_1),
.Z(clksw1_out_4)
);
CKBD1HVT CLK_SYNC_SKEW_11 (
.I(clksw1_out_5),
.Z(clksw1_out_2)
);
CKBD1HVT CLK_SYNC_SKEW_10 (
.I(clksw1_out),
.Z(clksw1_out_1)
);
CKND16HVT S_0_C1 (
.I (spi_clk_out_14),
.ZN(clk_b_1)
);
BUFFD2HVT OPTHOLD_G_70 (
.I(sample_mode_done_2),
.Z(sample_mode_done_1)
);
endmodule
| 6.653049 |
module clkgen (
osc_clk,
clkout_b,
j_tck_GB_G2B8I1ASTHIRNet269,
osc_clkASTHIRNet254,
spi_clk_out_GBASTHIRNet161,
clk_bASTHIRNet147,
j_tck_GBASTHIRNet101,
osc_clk_G1B8I1ASTHIRNet70,
rst_b,
spi_clk_out_GB_G4B1I2ASTHIRNet306,
cclk,
tck,
end_of_startup,
sample_mode_done,
md_spi,
md_jtag,
clkout
);
input osc_clk;
output clkout_b;
input j_tck_GB_G2B8I1ASTHIRNet269;
input osc_clkASTHIRNet254;
output spi_clk_out_GBASTHIRNet161;
output clk_bASTHIRNet147;
input j_tck_GBASTHIRNet101;
input osc_clk_G1B8I1ASTHIRNet70;
input rst_b;
input spi_clk_out_GB_G4B1I2ASTHIRNet306;
input cclk;
input tck;
input end_of_startup;
input sample_mode_done;
input md_spi;
input md_jtag;
output clkout;
/* wire declarations */
wire clksw1_outASTHIRNet197;
wire n58ASTHIRNet174;
wire n55;
wire sel_jtag_clk;
wire sel_spi_clk;
wire n54;
wire n57;
wire n56;
clk_gfsw_1 clksw1 (
.osc_clkASTHIRNet252(osc_clkASTHIRNet254),
.clksw1_outASTHIRNet198(clksw1_outASTHIRNet197),
.n58ASTHIRNet176(n58ASTHIRNet174),
.osc_clk_G1B8I1ASTHIRNet68(osc_clk_G1B8I1ASTHIRNet70),
.rst_b(rst_b),
.sel(n55)
);
clk_gfsw_0 clksw2 (
.j_tck_GB_G2B8I1ASTHIRNet267(j_tck_GB_G2B8I1ASTHIRNet269),
.clksw1_outASTHIRNet200(clksw1_outASTHIRNet197),
.spi_clk_out_GBASTHIRNet159(spi_clk_out_GBASTHIRNet161),
.j_tck_GBASTHIRNet99(j_tck_GBASTHIRNet101),
.rst_b(rst_b),
.sel(sel_jtag_clk)
);
BUFFD0HVT U7 (
.I(sel_spi_clk),
.Z(n54)
);
CKBD0HVT U8 (
.I(n54),
.Z(n55)
);
CKBD0HVT U9 (
.I(n57),
.Z(n56)
);
INVD0HVT U10 (
.I (sample_mode_done),
.ZN(n57)
);
OR2D0HVT U11 (
.Z (sel_spi_clk),
.A1(md_spi),
.A2(n56)
);
IND2D4HVT U12 (
.A1(end_of_startup),
.B1(cclk),
.ZN(n58ASTHIRNet174)
);
AN2D2HVT U13 (
.A2(sample_mode_done),
.Z (sel_jtag_clk),
.A1(md_jtag)
);
CKND16HVT S_2 (
.ZN(clk_bASTHIRNet147)
, .I (spi_clk_out_GB_G4B1I2ASTHIRNet306)
);
endmodule
| 6.653049 |
module clkgen (
clkout,
tck_cts_0,
rst_b,
osc_clk,
cclk,
tck,
end_of_startup,
sample_mode_done,
md_spi,
md_jtag
);
output clkout;
input tck_cts_0;
input rst_b;
input osc_clk;
input cclk;
input tck;
input end_of_startup;
input sample_mode_done;
input md_spi;
input md_jtag;
clk_gfsw_0 clksw2 (
.rst_b(rst_b),
.clka(clksw1_out),
.clkb(tck),
.sel(sel_jtag_clk),
.clkout(clkout),
.clkb_cts_0(tck_cts_0)
);
clk_gfsw_1 clksw1 (
.rst_b(rst_b),
.clka(cclk_int),
.clkb(osc_clk),
.sel(sel_spi_clk),
.clkout(clksw1_out)
);
SEH_ND2B_1 U3 (
.A(md_spi),
.B(sample_mode_done),
.X(sel_spi_clk)
);
SEH_NR2B_1 U2 (
.A(cclk),
.B(end_of_startup),
.X(cclk_int)
);
SEH_AN2_S_0P5 U1 (
.A1(sample_mode_done),
.A2(md_jtag)
, .X (sel_jtag_clk)
);
endmodule
| 6.653049 |
module clkgen (
clkout,
tck_cts_0,
rst_b,
osc_clk,
cclk,
tck,
end_of_startup,
sample_mode_done,
md_spi,
md_jtag
);
output clkout;
input tck_cts_0;
input rst_b;
input osc_clk;
input cclk;
input tck;
input end_of_startup;
input sample_mode_done;
input md_spi;
input md_jtag;
clk_gfsw_0 clksw2 (
.rst_b(rst_b),
.clka(clksw1_out),
.clkb(tck),
.sel(sel_jtag_clk),
.clkout(clkout),
.clkb_cts_0(tck_cts_0)
);
clk_gfsw_1 clksw1 (
.rst_b(rst_b),
.clka(cclk_int),
.clkb(osc_clk),
.sel(sel_spi_clk),
.clkout(clksw1_out)
);
SEH_ND2B_1 U3 (
.A(md_spi),
.B(sample_mode_done),
.X(sel_spi_clk)
);
SEH_NR2B_1 U2 (
.A(cclk),
.B(end_of_startup),
.X(cclk_int)
);
SEH_AN2_S_0P5 U1 (
.A1(sample_mode_done),
.A2(md_jtag)
, .X (sel_jtag_clk)
);
endmodule
| 6.653049 |
module SMC (
// Input signals0308
mode,
W_0,
V_GS_0,
V_DS_0,
W_1,
V_GS_1,
V_DS_1,
W_2,
V_GS_2,
V_DS_2,
W_3,
V_GS_3,
V_DS_3,
W_4,
V_GS_4,
V_DS_4,
W_5,
V_GS_5,
V_DS_5,
// Output signals
out_n
);
//================================================================
// INPUT AND OUTPUT DECLARATION
//================================================================
input [2:0] W_0, V_GS_0, V_DS_0;
input [2:0] W_1, V_GS_1, V_DS_1;
input [2:0] W_2, V_GS_2, V_DS_2;
input [2:0] W_3, V_GS_3, V_DS_3;
input [2:0] W_4, V_GS_4, V_DS_4;
input [2:0] W_5, V_GS_5, V_DS_5;
input [1:0] mode;
output [9:0] out_n; // use this if using continuous assignment for out_n // Ex: assign out_n = XXX;
//output reg [9:0] out_n; // use this if using procedure assignment for out_n // Ex: always@(*) begin out_n = XXX; end
//================================================================
// Wire & Registers
//================================================================
// Declare the wire/reg you would use in your circuit
// remember
// wire for port connection and cont. assignment
// reg for proc. assignment
wire [2:0] V_G1_0 = V_GS_0 - 1;
wire [2:0] V_G1_1 = V_GS_1 - 1;
wire [2:0] V_G1_2 = V_GS_2 - 1;
wire [2:0] V_G1_3 = V_GS_3 - 1;
wire [2:0] V_G1_4 = V_GS_4 - 1;
wire [2:0] V_G1_5 = V_GS_5 - 1;
wire [7:0] outig0, outig1, outig2, outig3, outig4, outig5;
wire [7:0] outsort0, outsort1, outsort2;
wire [6:0] nx3 = outsort0 / 3;
wire [6:0] ny3 = outsort1 / 3;
wire [6:0] nz3 = outsort2 / 3;
assign out_n = (mode[0]) ? (({nx3, 1'b0} + nx3) + 4 * (ny3) + 5 * (nz3)) : (nx3 + ny3 + nz3);
//================================================================
// DESIGN
//================================================================
// --------------------------------------------------
// write your design here
// --------------------------------------------------
GET_I_OR_G get_i_or_g0 (
.mode(mode[0]),
.W(W_0),
.G(V_G1_0),
.D(V_DS_0),
.out(outig0)
);
GET_I_OR_G get_i_or_g1 (
.mode(mode[0]),
.W(W_1),
.G(V_G1_1),
.D(V_DS_1),
.out(outig1)
);
GET_I_OR_G get_i_or_g2 (
.mode(mode[0]),
.W(W_2),
.G(V_G1_2),
.D(V_DS_2),
.out(outig2)
);
GET_I_OR_G get_i_or_g3 (
.mode(mode[0]),
.W(W_3),
.G(V_G1_3),
.D(V_DS_3),
.out(outig3)
);
GET_I_OR_G get_i_or_g4 (
.mode(mode[0]),
.W(W_4),
.G(V_G1_4),
.D(V_DS_4),
.out(outig4)
);
GET_I_OR_G get_i_or_g5 (
.mode(mode[0]),
.W(W_5),
.G(V_G1_5),
.D(V_DS_5),
.out(outig5)
);
SORT sort (
.mode(mode[1]),
.in0 (outig0),
.in1 (outig1),
.in2 (outig2),
.in3 (outig3),
.in4 (outig4),
.in5 (outig5),
.out0(outsort0),
.out1(outsort1),
.out2(outsort2)
);
endmodule
| 6.818609 |
module SMC (
// Input signals
mode,
W_0,
V_GS_0,
V_DS_0,
W_1,
V_GS_1,
V_DS_1,
W_2,
V_GS_2,
V_DS_2,
W_3,
V_GS_3,
V_DS_3,
W_4,
V_GS_4,
V_DS_4,
W_5,
V_GS_5,
V_DS_5,
// Output signals
out_n
);
//================================================================
// INPUT AND OUTPUT DECLARATION
//================================================================
input [2:0] W_0, V_GS_0, V_DS_0;
input [2:0] W_1, V_GS_1, V_DS_1;
input [2:0] W_2, V_GS_2, V_DS_2;
input [2:0] W_3, V_GS_3, V_DS_3;
input [2:0] W_4, V_GS_4, V_DS_4;
input [2:0] W_5, V_GS_5, V_DS_5;
input [1:0] mode;
//output [8:0] out_n; // use this if using continuous assignment for out_n // Ex: assign out_n = XXX;
output reg [9:0] out_n; // use this if using procedure assignment for out_n // Ex: always@(*) begin out_n = XXX; end
//================================================================
// Wire & Registers
//================================================================
// Declare the wire/reg you would use in your circuit
// remember
// wire for port connection and cont. assignment
// reg for proc. assignment
wire [7:0] I_0, I_1, I_2, I_3, I_4, I_5;
wire [7:0] G_0, G_1, G_2, G_3, G_4, G_5;
reg [7:0] IG_0, IG_1, IG_2, IG_3, IG_4, IG_5;
reg [7:0] IG0, IG1, IG2, IG3, IG4, IG5;
wire [7:0] IG_out0, IG_out1, IG_out2;
reg [6:0] IG_out_div0, IG_out_div1, IG_out_div2;
reg [9:0] op0, op1, op2, out_n_med;
//================================================================
// DESIGN
//================================================================
// --------------------------------------------------
// write your design here
// --------------------------------------------------
CALCULATE cal0 (
.W(W_0),
.V_GS(V_GS_0),
.V_DS(V_DS_0),
.I(I_0),
.G(G_0)
);
CALCULATE cal1 (
.W(W_1),
.V_GS(V_GS_1),
.V_DS(V_DS_1),
.I(I_1),
.G(G_1)
);
CALCULATE cal2 (
.W(W_2),
.V_GS(V_GS_2),
.V_DS(V_DS_2),
.I(I_2),
.G(G_2)
);
CALCULATE cal3 (
.W(W_3),
.V_GS(V_GS_3),
.V_DS(V_DS_3),
.I(I_3),
.G(G_3)
);
CALCULATE cal4 (
.W(W_4),
.V_GS(V_GS_4),
.V_DS(V_DS_4),
.I(I_4),
.G(G_4)
);
CALCULATE cal5 (
.W(W_5),
.V_GS(V_GS_5),
.V_DS(V_DS_5),
.I(I_5),
.G(G_5)
);
PICK pick (
.in0 (IG0),
.in1 (IG1),
.in2 (IG2),
.in3 (IG3),
.in4 (IG4),
.in5 (IG5),
.out0(IG_out0),
.out1(IG_out1),
.out2(IG_out2),
.mode(mode[1])
);
always @(*) begin
if (mode[0] == 0) begin
IG_0 = G_0;
IG_1 = G_1;
IG_2 = G_2;
IG_3 = G_3;
IG_4 = G_4;
IG_5 = G_5;
end else begin
IG_0 = I_0;
IG_1 = I_1;
IG_2 = I_2;
IG_3 = I_3;
IG_4 = I_4;
IG_5 = I_5;
end
if (mode[1] == 0) begin
IG0 = ~IG_0;
IG1 = ~IG_1;
IG2 = ~IG_2;
IG3 = ~IG_3;
IG4 = ~IG_4;
IG5 = ~IG_5;
end else begin
IG0 = IG_0;
IG1 = IG_1;
IG2 = IG_2;
IG3 = IG_3;
IG4 = IG_4;
IG5 = IG_5;
end
IG_out_div0 = IG_out0 / 3;
IG_out_div1 = IG_out1 / 3;
IG_out_div2 = IG_out2 / 3;
if (mode[0] == 0) begin
op0 = IG_out_div0;
op1 = IG_out_div1;
op2 = IG_out_div2;
end else begin
op0 = 2 * IG_out_div0 + IG_out_div0;
op1 = 4 * IG_out_div1;
op2 = 4 * IG_out_div2 + IG_out_div2;
end
out_n = op0 + op1 + op2;
end
endmodule
| 6.818609 |
module SMC (
// Input signals
mode,
W_0,
V_GS_0,
V_DS_0,
W_1,
V_GS_1,
V_DS_1,
W_2,
V_GS_2,
V_DS_2,
W_3,
V_GS_3,
V_DS_3,
W_4,
V_GS_4,
V_DS_4,
W_5,
V_GS_5,
V_DS_5,
// Output signals
out_n
);
//================================================================
// INPUT AND OUTPUT DECLARATION
//================================================================
input [2:0] W_0, V_GS_0, V_DS_0;
input [2:0] W_1, V_GS_1, V_DS_1;
input [2:0] W_2, V_GS_2, V_DS_2;
input [2:0] W_3, V_GS_3, V_DS_3;
input [2:0] W_4, V_GS_4, V_DS_4;
input [2:0] W_5, V_GS_5, V_DS_5;
input [1:0] mode;
//output [8:0] out_n; // use this if using continuous assignment for out_n // Ex: assign out_n = XXX;
output reg [9:0] out_n; // use this if using procedure assignment for out_n // Ex: always@(*) begin out_n = XXX; end
//================================================================
// Wire & Registers
//================================================================
// Declare the wire/reg you would use in your circuit
// remember
// wire for port connection and cont. assignment
// reg for proc. assignment
wire [9:0] line_A_0, line_A_1, line_A_2, line_A_3, line_A_4, line_A_5;
wire [9:0] line_B_0, line_B_1, line_B_2, line_B_3, line_B_4, line_B_5;
wire [9:0] line_out;
//================================================================
// DESIGN
//================================================================
// --------------------------------------------------
// write your design here
// --------------------------------------------------
ID_gm_Calculation ID_gm_Calculation_A (
.W_0(W_0),
.V_GS_0(V_GS_0),
.V_DS_0(V_DS_0),
.output_line_0(line_A_0),
.W_1(W_1),
.V_GS_1(V_GS_1),
.V_DS_1(V_DS_1),
.output_line_1(line_A_1),
.W_2(W_2),
.V_GS_2(V_GS_2),
.V_DS_2(V_DS_2),
.output_line_2(line_A_2),
.W_3(W_3),
.V_GS_3(V_GS_3),
.V_DS_3(V_DS_3),
.output_line_3(line_A_3),
.W_4(W_4),
.V_GS_4(V_GS_4),
.V_DS_4(V_DS_4),
.output_line_4(line_A_4),
.W_5(W_5),
.V_GS_5(V_GS_5),
.V_DS_5(V_DS_5),
.output_line_5(line_A_5),
.mode(mode[0])
);
Sorting Sorting_A (
.i0(line_A_0),
.i1(line_A_1),
.i2(line_A_2),
.i3(line_A_3),
.i4(line_A_4),
.i5(line_A_5),
.n0(line_B_0),
.n1(line_B_1),
.n2(line_B_2),
.n3(line_B_3),
.n4(line_B_4),
.n5(line_B_5)
);
MAX_min_Calculation MAX_min_Calculation_A (
.mode(mode),
.n0(line_B_0),
.n1(line_B_1),
.n2(line_B_2),
.n3(line_B_3),
.n4(line_B_4),
.n5(line_B_5),
.out_n(line_out)
);
always @(*) begin
out_n = line_out;
end
endmodule
| 6.818609 |
module
// BBQ bbq0(.meat(meat_0), .vagetable(vagetable_0), .water(water_0),.cost(cost[0]));
// --------------------------------------------------
// Example for continuous assignment
// assign out_n = XXX;
// --------------------------------------------------
// Example for procedure assignment
// always@(*) begin
// out_n = XXX;
// end
// --------------------------------------------------
// Example for case statement
// always @(*) begin
// case(op)
// 2'b00: output_reg = a + b;
// 2'b10: output_reg = a - b;
// 2'b01: output_reg = a * b;
// 2'b11: output_reg = a / b;
// default: output_reg = 0;
// endcase
// end
// --------------------------------------------------
//===== ID_gm_Calculation =====
module ID_gm_Calculation(W_0,V_GS_0,V_DS_0,output_line_0,
W_1,V_GS_1,V_DS_1,output_line_1,
W_2,V_GS_2,V_DS_2,output_line_2,
W_3,V_GS_3,V_DS_3,output_line_3,
W_4,V_GS_4,V_DS_4,output_line_4,
W_5,V_GS_5,V_DS_5,output_line_5,mode);
input wire [2:0]W_0,V_GS_0,V_DS_0,W_1,V_GS_1,V_DS_1,W_2,V_GS_2,V_DS_2,W_3,V_GS_3,V_DS_3,W_4,V_GS_4,V_DS_4,W_5,V_GS_5,V_DS_5;
input wire mode;
output wire [9:0]output_line_0,output_line_1,output_line_2,output_line_3,output_line_4,output_line_5;
wire [9:0]result_line_0,result_line_1,result_line_2,result_line_3,result_line_4,result_line_5;
reg [9:0]result_0,result_1,result_2,result_3,result_4,result_5;
assign output_line_0=result_0;
assign output_line_1=result_1;
assign output_line_2=result_2;
assign output_line_3=result_3;
assign output_line_4=result_4;
assign output_line_5=result_5;
ID_gm_Calculator_unit ID_gm_Calculator_unit_0(.w(W_0),.v_gs(V_GS_0),.v_ds(V_DS_0),.id_gm_select(mode),.result(result_line_0)),
ID_gm_Calculator_unit_1(.w(W_1),.v_gs(V_GS_1),.v_ds(V_DS_1),.id_gm_select(mode),.result(result_line_1)),
ID_gm_Calculator_unit_2(.w(W_2),.v_gs(V_GS_2),.v_ds(V_DS_2),.id_gm_select(mode),.result(result_line_2)),
ID_gm_Calculator_unit_3(.w(W_3),.v_gs(V_GS_3),.v_ds(V_DS_3),.id_gm_select(mode),.result(result_line_3)),
ID_gm_Calculator_unit_4(.w(W_4),.v_gs(V_GS_4),.v_ds(V_DS_4),.id_gm_select(mode),.result(result_line_4)),
ID_gm_Calculator_unit_5(.w(W_5),.v_gs(V_GS_5),.v_ds(V_DS_5),.id_gm_select(mode),.result(result_line_5));
always@(*)begin
result_0=result_line_0;
result_1=result_line_1;
result_2=result_line_2;
result_3=result_line_3;
result_4=result_line_4;
result_5=result_line_5;
end
endmodule
| 6.804069 |
module Sorting (
i0,
i1,
i2,
i3,
i4,
i5,
n0,
n1,
n2,
n3,
n4,
n5
);
input wire [9:0] i0, i1, i2, i3, i4, i5;
output wire [9:0] n0, n1, n2, n3, n4, n5;
reg [9:0] tmp [0:5];
reg [9:0] swp;
integer i, j;
assign n0 = tmp[0];
assign n1 = tmp[1];
assign n2 = tmp[2];
assign n3 = tmp[3];
assign n4 = tmp[4];
assign n5 = tmp[5];
always @(*) begin
tmp[0] = i0;
tmp[1] = i1;
tmp[2] = i2;
tmp[3] = i3;
tmp[4] = i4;
tmp[5] = i5;
for (i = 0; i < 5; i = i + 1) begin
for (j = 0; j < 5 - i; j = j + 1) begin
if (tmp[j] < tmp[j+1]) begin
swp = tmp[j];
tmp[j] = tmp[j+1];
tmp[j+1] = swp;
end
end
end
end
endmodule
| 6.901184 |
module MAX_min_Calculation (
mode,
n0,
n1,
n2,
n3,
n4,
n5,
out_n
);
input wire [1:0] mode;
input wire [9:0] n0, n1, n2, n3, n4, n5;
output reg [9:0] out_n;
always @(*) begin
case (mode)
2'b00: out_n = n3 + n4 + n5;
2'b01: out_n = (3 * n3) + (4 * n4) + (5 * n5);
2'b10: out_n = n0 + n1 + n2;
2'b11: out_n = (3 * n0) + (4 * n1) + (5 * n2);
endcase
end
endmodule
| 6.704127 |
module smdsixbutton (
input clk,
input p7, // DB9_PIN7 (SEL)
output reg [5:0] p = 6'b111111, // {DB9_PIN1, DB9_PIN2, DB9_PIN3, DB9_PIN4, DB9_PIN6, DB9_PIN9}
input up, // Up button
input dw, // Down button
input lf, // Left button
input rg, // Right button
input a, // A button
input b, // B button
input c, // C button
input st, // Start button
input x, // X button
input y, // Y button
input z, // Z button
input md, // Mode button
input hm // Home button (Analogue Mega Sg)
);
parameter TIMEOUT = 14'd8000; // For 10Mhz oscillator
//parameter TIMEOUT = 14'd16000; // For 20Mhz oscillator
reg [13:0] clk_counter = TIMEOUT;
reg [1:0] hi_count = 2'b0;
reg mode_set = 1'b0;
reg three_button_mode = 1'b0;
reg last_p7_1 = 1'b0;
reg last_p7_2 = 1'b0;
always @(posedge clk) begin
last_p7_1 <= p7;
last_p7_2 <= last_p7_1;
if (!mode_set) begin
three_button_mode <= !md;
mode_set <= 1'b1;
end
if (!three_button_mode) begin
if (clk_counter == 0) begin
$display("Reset!");
clk_counter <= TIMEOUT;
hi_count <= 0;
end else begin
if (last_p7_1 && !last_p7_2) begin
hi_count <= hi_count + 2'b1;
clk_counter <= TIMEOUT;
end else begin
clk_counter <= clk_counter - 2'b1;
end
end
end
end
always @(*) begin
$display("hi_count=%d", hi_count);
case ({
hi_count, last_p7_2
})
3'b000: p = {up, dw, 1'b0, 1'b0, a, st};
3'b001: p = {up, dw, lf, rg, b, c};
3'b010: p = {up, dw, 1'b0, 1'b0, a, st};
3'b011: p = {up, dw, lf, rg, b, c};
3'b100: p = {1'b0, 1'b0, 1'b0, 1'b0, a, st};
3'b101: p = {up, dw, lf, rg, b, c};
3'b110: p = {hm, 1'b1, 1'b1, 1'b1, a, st};
3'b111: p = {z, y, x, md, 1'b1, 1'b1};
endcase
end
endmodule
| 7.352916 |
module smdsixbutton_tb;
// Inputs
reg p7; // Clock from Sega Mega Drive
reg up; // Up button
reg dw; // Down button
reg lf; // Left button
reg rg; // Right button
reg a; // A button
reg b; // B button
reg c; // C button
reg st; // Start button
reg x; // X button
reg y; // Y button
reg z; // Z button
reg md; // Mode button
reg hm; // Home button
reg clk = 1'd0;
integer j, k;
// Outputs
wire [5:0] p;
// Instantiate the Unit Under Test (UUT)
smdsixbutton joystick (
.p7 (p7),
.up (up),
.dw (dw),
.lf (lf),
.rg (rg),
.a (a),
.b (b),
.c (c),
.st (st),
.x (x),
.y (y),
.z (z),
.md (md),
.clk(clk),
.hm (hm),
.p(p)
);
//always #50 clk <= !clk; // 20Mhz
always #100 clk <= !clk; // 10Mhz
initial begin
$timeformat(-3, 2, " ms", 10);
$dumpfile("smdsixbutton.vcd");
$dumpvars(0, joystick);
// Initialize Inputs
up = 0;
dw = 1;
lf = 1;
rg = 1;
a = 1;
b = 1;
c = 1;
st = 1;
x = 1;
y = 0;
z = 1;
md = 1;
hm = 1;
p7 = 1;
#1660000 $display("delay");
for (j = 0; j < 20; j = j + 1) begin
#13000 p7 = 0;
#13000 p7 = 1;
#13000 p7 = 0;
#13000 p7 = 1;
#13000 p7 = 0;
#13000 p7 = 1;
#13000 p7 = 0;
#13000 p7 = 1;
#1660000 $display("delay");
end
$finish();
end
initial begin
$monitor("p7=%d,p1=%d,p2=%d,p3=%d,p4=%d,p6=%d,p9=%d,time=%t \n", p7, p[5], p[4], p[3], p[2],
p[1], p[0], $time);
end
endmodule
| 7.121867 |
module SMEMemoryMux (
input Select,
input [9:0] ReadAddressIn0, // Expanded for Rel 0 on 6/18
input [9:0] ReadAddressIn1, // Expanded for Rel 0 on 6/18
output [9:0] ReadAddressOut, // Expanded for Rel 0 on 6/18
input [9:0] WriteAddressIn0,
input [9:0] WriteAddressIn1,
output [9:0] WriteAddressOut,
input [8:0] DataToMemoryIn0,
input [8:0] DataToMemoryIn1,
output [8:0] DataToMemoryOut,
input [17:0] DataFromMemoryIn0,
input [17:0] DataFromMemoryIn1,
output [17:0] DataFromMemoryOut,
input ReadEnableIn0,
input ReadEnableIn1,
output ReadEnableOut,
input WriteEnableIn0,
input WriteEnableIn1,
output WriteEnableOut,
input ReadClockIn0,
input ReadClockIn1,
output ReadClockOut
);
assign ReadAddressOut = (Select) ? ReadAddressIn1 : ReadAddressIn0;
assign WriteAddressOut = (Select) ? WriteAddressIn1 : WriteAddressIn0;
assign DataToMemoryOut = (Select) ? DataToMemoryIn1 : DataToMemoryIn0;
assign DataFromMemoryOut = (Select) ? DataFromMemoryIn1 : DataFromMemoryIn0;
assign ReadEnableOut = (Select) ? ReadEnableIn1 : ReadEnableIn0;
assign WriteEnableOut = (Select) ? WriteEnableIn1 : WriteEnableIn0;
assign ReadClockOut = (Select) ? ReadClockIn1 : ReadClockIn0;
endmodule
| 6.685625 |
module SMEM_12x128 (
input clk,
output wire [11:0] DO,
input we,
input [11:0] DI,
input [6:0] Adr_wr,
input [6:0] Adr_rd
);
reg [11:0] MEM[127:0];
assign DO = MEM[Adr_rd];
initial // SMEM_12x128.txt
$readmemh("SMEM_12x128.txt", MEM, 0, 127);
always @(posedge clk) begin
MEM[Adr_wr] <= we ? DI : MEM[Adr_wr];
end
endmodule
| 7.239993 |
module fast_pattern_sme_wrapper (
input wire clk,
input wire rst,
// AXI Stream input
input wire [7:0] s_axis_tdata,
input wire s_axis_tvalid,
// Preamble state (7B data and 1B len)
input wire [8*8-1:0] preamble_state,
input wire reload,
// Match output
input wire next_index,
output reg [12:0] match_index,
output reg match_valid,
output reg match_error,
// Last bytes (7B data and 1B len)
output wire [8*8-1:0] last_bytes_state,
// merged state
output reg [7:0] match_valid_stat,
output reg [7:0] match_error_stat
);
///////////////////////////////////////////////
////////// Selecting input data ///////////
///////////////////////////////////////////////
wire [7:0] muxed_data;
wire muxed_data_v;
reg [2:0] preamble_ptr;
assign muxed_data = preamble_ptr > 0 ? preamble_state[preamble_ptr*8+:8] : s_axis_tdata;
assign muxed_data_v = preamble_ptr > 0 ? 1'b1 : s_axis_tvalid;
always @(posedge clk)
if (rst) preamble_ptr <= 3'b0;
else if (reload) preamble_ptr <= preamble_state[2:0];
else if (preamble_ptr > 0) preamble_ptr <= preamble_ptr - 3'd1;
///////////////////////////////////////////////
////////// Check for fast patterns ////////////
///////////////////////////////////////////////
wire [4636-1:0] sme_output;
fast_pattern_sme SME (
.clk(clk),
.rst(rst | reload),
.s_axis_tdata(muxed_data),
.s_axis_tvalid(muxed_data_v),
.match(sme_output)
);
// Encoding the output matches
wire [8*13-1:0] shrinker_output;
wire [ 7:0] match_valids;
wire [ 7:0] match_errors;
spaced_2lvl_penc #(
.INPUT_WIDTH(4636),
.PENC1_SIZE (32),
.PENC2_SIZE (32),
.BIN_COUNT (8)
) match_shrinker (
.clk(clk),
.rst(rst),
.one_hot(sme_output),
.index (shrinker_output),
.valid (match_valids),
.error (match_errors)
);
reg [ 7:0] selected_match;
reg [ 7:0] selected_match_r;
reg [12:0] selected_match_index;
reg selected_match_error;
reg [ 7:0] match_mask;
integer k;
always @(*) begin
selected_match = 8'd1;
selected_match_index = shrinker_output[0*13+:13];
selected_match_error = match_errors[0];
for (k = 7; k >= 0; k = k - 1)
if (match_valids[k] & match_mask[k]) begin
selected_match = 8'd1 << k;
selected_match_index = shrinker_output[k*13+:13];
selected_match_error = match_errors[k];
end
end
always @(posedge clk) begin
selected_match_r <= selected_match;
match_index <= selected_match_index;
match_error <= selected_match_error;
match_valid <= |(match_valids & match_mask);
match_valid_stat <= match_valids & match_mask;
match_error_stat <= match_errors & match_mask;
if (rst) begin
match_valid <= 1'b0;
match_valid_stat <= 8'd0;
match_error_stat <= 8'd0;
end
end
always @(posedge clk) begin
if (rst || reload) match_mask <= 8'hFF;
else if (next_index) match_mask <= match_mask & ~selected_match_r;
end
///////////////////////////////////////////////
////////// Keeping last bytes logic ///////////
///////////////////////////////////////////////
reg [7:0] byte_reg[0:6];
reg [2:0] byte_reg_len;
integer j;
always @(posedge clk) begin
if (s_axis_tvalid) begin
byte_reg[0] <= s_axis_tdata;
for (j = 6; j > 0; j = j - 1) byte_reg[j] <= byte_reg[j-1];
if (byte_reg_len < 7) byte_reg_len <= byte_reg_len + 3'd1;
end
if (rst || reload) // Flush the pipe
byte_reg_len <= 3'd0;
end
genvar i;
generate
for (i = 1; i < 8; i = i + 1) begin : last_byte_remap
assign last_bytes_state[i*8+:8] = byte_reg[i-1];
end
endgenerate
assign last_bytes_state[7:0] = {5'd0, byte_reg_len};
endmodule
| 6.896434 |
module smg (
clk,
data,
sm_wei,
sm_duan,
rst
);
input clk, rst;
input [15:0] data;
output [3:0] sm_wei;
output [7:0] sm_duan;
//----------------------------------------------------------
//ƵƵΪ100Hz
integer clk_cnt; //Ƶڼ
reg clk_100Hz;
always @(posedge clk)
if (rst == 1) begin //ܷƵʾ
clk_cnt <= 1'b0;
clk_100Hz <= 1'b0;
end else if (clk_cnt == 32'd25000) begin
clk_cnt <= 1'b0; //ڽ¼
clk_100Hz <= ~clk_100Hz; //ʱӷת
end else clk_cnt <= clk_cnt + 1'b1; //Ƶڼ+1ֹȥһʱ
//----------------------------------------------------------
//λ
//reg [2:0]wei_ctrl;
//always @(posedge clk_100Hz)
//begin
// if(rst == 1) begin
// wei_ctrl <= 0;
// end
// else begin
// wei_ctrl <= wei_ctrl + 1;
// if(wei_ctrl == 3'b100) wei_ctrl <= 3'b0;
// end
//end
//ÿƵ˵ʱ4λ˸
//Ӿ˿ĸʾIJͬ
reg [3:0] wei_ctrl = 4'b1110;
always @(posedge clk_100Hz) wei_ctrl <= {wei_ctrl[2:0], wei_ctrl[3]};
//οƣÿһλܵ8ledƵ
reg [3:0] duan_ctrl;
always @(wei_ctrl)
case (wei_ctrl)
4'b1110: duan_ctrl = data[3:0];
4'b1101: duan_ctrl = data[7:4];
4'b1011: duan_ctrl = data[11:8];
4'b0111: duan_ctrl = data[15:12];
default: duan_ctrl = 4'hf;
endcase
//----------------------------------------------------------
//ģ飺8ledƵĽ룬ledƶӦλ˸͵ƽƣ
reg [7:0] duan;
always @(duan_ctrl)
case (duan_ctrl)
4'h0: duan = 8'b1100_0000; //0
4'h1: duan = 8'b1111_1001; //1
4'h2: duan = 8'b1010_0100; //2
4'h3: duan = 8'b1011_0000; //3
4'h4: duan = 8'b1001_1001; //4
4'h5: duan = 8'b1001_0010; //5
4'h6: duan = 8'b1000_0010; //6
4'h7: duan = 8'b1111_1000; //7
4'h8: duan = 8'b1000_0000; //8
4'h9: duan = 8'b1001_0000; //9
4'ha: duan = 8'b1000_1000; //a
4'hb: duan = 8'b1000_0011; //b
4'hc: duan = 8'b1100_0110; //c
4'hd: duan = 8'b1010_0001; //d
4'he: duan = 8'b1000_0110; //e
4'hf: duan = 8'b1000_1110; //f
default: duan = 8'b1100_0000; //0
endcase
//----------------------------------------------------------
assign sm_wei = wei_ctrl;
assign sm_duan = duan;
endmodule
| 7.175966 |
module smg_basemod (
input CLOCK,
RESET,
input [23:0] iData, //输入的数据
output [7:0] DIG, //八段数码管
output [5:0] SEL //位选
);
wire [9:0] DataU1;
smg_funcmod U1 (
.CLOCK(CLOCK),
.RESET(RESET),
.iData(iData), // < top
.oData(DataU1) // > U2
);
smg_encode_immdmod U2 (
.iData(DataU1[9:6]), // < U1
.oData(DIG) // > top
);
assign SEL = DataU1[5:0];
endmodule
| 7.249227 |
module name: smg_clkdiv
////////////////////////////////
module smg_clkdiv
(
input clk_50MHz,
input rst,
output reg clk_1khz,
output reg clk_1hz,
output reg rdsig_nextdata
);
reg[15:0] cnt1;
reg[9:0] cnt2;
reg clk_1hz_buf;
//1khz分频
always @(posedge clk_50MHz or negedge rst)
begin
if(!rst)begin
clk_1khz <= 1'b0;
cnt1 <= 16'd0;
end
else if(cnt1 == 16'd24999)begin
clk_1khz <= !clk_1khz;
cnt1 <= 16'd0;
end
else begin
cnt1 <= cnt1 + 16'd1;
end
end
//1hz分频
always @(posedge clk_1khz or negedge rst)
begin
if(!rst)begin
clk_1hz <= 1'b0;
cnt2 <= 10'd0;
end
else if(cnt2 == 10'd499)begin
clk_1hz <= !clk_1hz;
cnt2 <= 10'd0;
end
else begin
cnt2 <= cnt2 + 10'd1;
end
end
//得到fifo读取信号:1hz信号下降沿后，持续50MHz的一个时钟周期的高电平
always @(posedge clk_50MHz)
begin
clk_1hz_buf <= clk_1hz;
rdsig_nextdata <= clk_1hz_buf & (~clk_1hz);
end
endmodule
| 6.820156 |
module smg_control_module (
input CLK,
input RSTn,
input [23:0] Number_Sig,
output [3:0] Number_Data
);
/******************************************/
parameter T1MS = 16'd49999; //1ms
/******************************************/
reg [15:0] C1;
always @(posedge CLK or negedge RSTn)
if (!RSTn) C1 <= 16'd0;
else if (C1 == T1MS) C1 <= 16'd0;
else C1 <= C1 + 1'b1;
/******************************************/
reg [3:0] i;
reg [3:0] rNumber;
always @(posedge CLK or negedge RSTn)
if (!RSTn) begin
i <= 4'd0;
rNumber <= 4'd0;
end else
case (i)
0:
if (C1 == T1MS) i <= i + 1'b1;
else rNumber <= Number_Sig[23:20]; //ʮλʾ
1:
if (C1 == T1MS) i <= i + 1'b1;
else rNumber <= Number_Sig[19:16]; //λʾ
2:
if (C1 == T1MS) i <= i + 1'b1;
else rNumber <= Number_Sig[15:12]; //ǧλʾ
3:
if (C1 == T1MS) i <= i + 1'b1;
else rNumber <= Number_Sig[11:8]; //λʾ
4:
if (C1 == T1MS) i <= i + 1'b1;
else rNumber <= Number_Sig[7:4]; //ʮλʾ
5:
if (C1 == T1MS) i <= 4'd0;
else rNumber <= Number_Sig[3:0]; //λʾ
endcase
/******************************************/
assign Number_Data = rNumber;
/******************************************/
endmodule
| 6.732436 |
module name: smg_demo
////////////////////////////////////
module smg_demo
(
input clk_50MHz,
input rst,
input[7:0] data,
output[5:0] smg_sig,
output[7:0] smg_data,
output rdsig_nextdata
);
wire clk_1khz, clk_1hz;
//clkdiv
smg_clkdiv smg_clkdiv_inst
(
.clk_50MHz(clk_50MHz),
.rst(rst),
.clk_1khz(clk_1khz),
.clk_1hz(clk_1hz),
.rdsig_nextdata(rdsig_nextdata)
);
//display
smg_display smg_display_inst
(
.clk_1khz(clk_1khz),
.clk_1hz(clk_1hz),
.rst(rst),
.data(data),
.smg_sig(smg_sig),
.smg_data(smg_data)
);
endmodule
| 6.701033 |
module name: smg_display
//功能说明：将串口接收的数据译码成16进制显示在两位数码管上
////////////////////////////////
module smg_display
(
input clk_1khz,
input clk_1hz,
input rst,
input[7:0] data,
output reg[5:0] smg_sig,
output reg[7:0] smg_data
);
//共阳数码管0~F编码:A~G、DP => data[0]~data[7]
parameter d0 = 8'hc0;
parameter d1 = 8'hf9;
parameter d2 = 8'ha4;
parameter d3 = 8'hb0;
parameter d4 = 8'h99;
parameter d5 = 8'h92;
parameter d6 = 8'h82;
parameter d7 = 8'hf8;
parameter d8 = 8'h80;
parameter d9 = 8'h90;
parameter da = 8'h88;
parameter db = 8'h83;
parameter dc = 8'hc6;
parameter dd = 8'ha1;
parameter de = 8'h86;
parameter df = 8'h8e;
parameter smg_sig1 = 6'b111110;
parameter smg_sig2 = 6'b111101;
reg[7:0] smg_data1, smg_data2;
reg smg_sig_cnt;
//数据译码
always @(posedge clk_1hz or negedge rst)
begin
if(!rst)begin
smg_data1 <= d0;
end
else begin
case(data[3:0])
4'd0:smg_data1 <= d0;
4'd1:smg_data1 <= d1;
4'd2:smg_data1 <= d2;
4'd3:smg_data1 <= d3;
4'd4:smg_data1 <= d4;
4'd5:smg_data1 <= d5;
4'd6:smg_data1 <= d6;
4'd7:smg_data1 <= d7;
4'd8:smg_data1 <= d8;
4'd9:smg_data1 <= d9;
4'd10:smg_data1 <= da;
4'd11:smg_data1 <= db;
4'd12:smg_data1 <= dc;
4'd13:smg_data1 <= dd;
4'd14:smg_data1 <= de;
4'd15:smg_data1 <= df;
default:smg_data1 <= d0;
endcase
end
end
always @(posedge clk_1hz or negedge rst)
begin
if(!rst)begin
smg_data2 <= d0;
end
else begin
case(data[7:4])
4'd0:smg_data2 <= d0;
4'd1:smg_data2 <= d1;
4'd2:smg_data2 <= d2;
4'd3:smg_data2 <= d3;
4'd4:smg_data2 <= d4;
4'd5:smg_data2 <= d5;
4'd6:smg_data2 <= d6;
4'd7:smg_data2 <= d7;
4'd8:smg_data2 <= d8;
4'd9:smg_data2 <= d9;
4'd10:smg_data2 <= da;
4'd11:smg_data2 <= db;
4'd12:smg_data2 <= dc;
4'd13:smg_data2 <= dd;
4'd14:smg_data2 <= de;
4'd15:smg_data2 <= df;
default:smg_data2 <= d0;
endcase
end
end
//扫描显示
always @(posedge clk_1khz)
begin
smg_sig_cnt <= !smg_sig_cnt;
case(smg_sig_cnt)
1'b0:begin
smg_sig <= smg_sig1;
smg_data <= smg_data1;
end
1'b1:begin
smg_sig <= smg_sig2;
smg_data <= smg_data2;
end
default:begin
smg_sig <= smg_sig1;
smg_data <= smg_data1;
end
endcase
end
endmodule
| 7.634222 |
module smg_encode_immdmod //译码器模块
(
input [3:0] iData, //三位输入
output [7:0] oData //八位输出
);
parameter _0 = 8'b0100_0000, _1 = 8'b0111_1001, _2 = 8'b0010_0100,
_3 = 8'b0011_0000, _4 = 8'b0001_1001, _5 = 8'b0001_0010,
_6 = 8'b0000_0010, _7 = 8'b0111_1000, _8 = 8'b0000_0000,
_9 = 8'b0001_0000, _A = 8'b0000_1000, _B = 8'b0000_0011,
_C = 8'b0100_0110, _D = 8'b0010_0001, _E = 8'b0000_0110,
_F = 8'b0000_1110;
reg [7:0] D = 8'b1111_1111;
always @(*)
if (iData == 4'd0) D = _0;
else if (iData == 4'd1) D = _1;
else if (iData == 4'd2) D = _2;
else if (iData == 4'd3) D = _3;
else if (iData == 4'd4) D = _4;
else if (iData == 4'd5) D = _5;
else if (iData == 4'd6) D = _6;
else if (iData == 4'd7) D = _7;
else if (iData == 4'd8) D = _8;
else if (iData == 4'd9) D = _9;
else if (iData == 4'hA) D = _A;
else if (iData == 4'hB) D = _B;
else if (iData == 4'hC) D = _C;
else if (iData == 4'hD) D = _D;
else if (iData == 4'hE) D = _E;
else if (iData == 4'hF) D = _F;
else D = 8'dx;
assign oData = D;
endmodule
| 6.778864 |
module smg_interface (
input CLK,
input RSTn,
input [23:0] Number_Sig,
output [7:0] SMG_Data,
output [5:0] Scan_Sig
);
/******************************************/
wire [3:0] Number_Data;
smg_control_module U1 (
.CLK(CLK),
.RSTn(RSTn),
.Number_Sig(Number_Sig), // input - from top
.Number_Data(Number_Data) // output - to U2
);
/******************************************/
smg_encode_module U2 (
.CLK (CLK),
.RSTn (RSTn),
.Number_Data(Number_Data), // input - from U2
.SMG_Data (SMG_Data) // output - to top
);
/*******************************************/
smg_scan_module U3 (
.CLK(CLK),
.RSTn(RSTn),
.Scan_Sig(Scan_Sig) // output - to top
);
/*******************************************/
endmodule
| 6.837269 |
module smg_ip_model (
clk,
data,
sm_wei,
sm_duan
);
input clk;
input [15:0] data;
output [3:0] sm_wei;
output [7:0] sm_duan;
//----------------------------------------------------------
//Ƶ
integer clk_cnt;
reg clk_400Hz;
always @(posedge clk)
if (clk_cnt == 32'd100000) begin
clk_cnt <= 1'b0;
clk_400Hz <= ~clk_400Hz;
end else clk_cnt <= clk_cnt + 1'b1;
//----------------------------------------------------------
//λ
reg [3:0] wei_ctrl = 4'b1110;
always @(posedge clk_400Hz) wei_ctrl <= {wei_ctrl[2:0], wei_ctrl[3]};
//ο
reg [3:0] duan_ctrl;
always @(wei_ctrl)
case (wei_ctrl)
4'b1110: duan_ctrl = data[3:0];
4'b1101: duan_ctrl = data[7:4];
4'b1011: duan_ctrl = data[11:8];
4'b0111: duan_ctrl = data[15:12];
default: duan_ctrl = 4'hf;
endcase
//----------------------------------------------------------
//ģ
reg [7:0] duan;
always @(duan_ctrl)
case (duan_ctrl)
4'h0: duan = 8'b1100_0000; //0
4'h1: duan = 8'b1111_1001; //1
4'h2: duan = 8'b1010_0100; //2
4'h3: duan = 8'b1011_0000; //3
4'h4: duan = 8'b1001_1001; //4
4'h5: duan = 8'b1001_0010; //5
4'h6: duan = 8'b1000_0010; //6
4'h7: duan = 8'b1111_1000; //7
4'h8: duan = 8'b1000_0000; //8
4'h9: duan = 8'b1001_0000; //9
4'ha: duan = 8'b1000_1000; //a
4'hb: duan = 8'b1000_0011; //b
4'hc: duan = 8'b1100_0110; //c
4'hd: duan = 8'b1010_0001; //d
4'he: duan = 8'b1000_0110; //e
4'hf: duan = 8'b1000_1110; //f
// 4'hf:duan=8'b1111_1111;//ʾ
default: duan = 8'b1100_0000; //0
endcase
//----------------------------------------------------------
assign sm_wei = wei_ctrl;
assign sm_duan = duan;
endmodule
| 7.777711 |
module smg_scan_module (
input CLK,
input RSTn,
output [5:0] Scan_Sig
);
/*****************************/
parameter T1MS = 16'd49999;
/*****************************/
reg [15:0] C1;
always @(posedge CLK or negedge RSTn)
if (!RSTn) C1 <= 16'd0;
else if (C1 == T1MS) C1 <= 16'd0;
else C1 <= C1 + 1'b1;
/*******************************/
reg [3:0] i;
reg [5:0] rScan;
always @(posedge CLK or negedge RSTn)
if (!RSTn) begin
i <= 4'd0;
rScan <= 6'b100_000;
end else
case (i)
0:
if (C1 == T1MS) i <= i + 1'b1;
else rScan <= 6'b011_111; //һѡͨ
1:
if (C1 == T1MS) i <= i + 1'b1;
else rScan <= 6'b101_111; //ڶѡͨ
2:
if (C1 == T1MS) i <= i + 1'b1;
else rScan <= 6'b110_111; //ѡͨ
3:
if (C1 == T1MS) i <= i + 1'b1;
else rScan <= 6'b111_011; //ĸѡͨ
4:
if (C1 == T1MS) i <= i + 1'b1;
else rScan <= 6'b111_101; //ѡͨ
5:
if (C1 == T1MS) i <= 4'd0;
else rScan <= 6'b111_110; //ѡͨ
endcase
/******************************/
assign Scan_Sig = rScan;
/******************************/
endmodule
| 6.694266 |
module AND2HD1X (
A,
B,
Z
);
input A;
input B;
output Z;
and (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.817886 |
module AND2HD2X (
A,
B,
Z
);
input A;
input B;
output Z;
and (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.976181 |
module AND2HD2XSPG (
A,
B,
Z
);
input A;
input B;
output Z;
and (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.27383 |
module AND2HD4X (
A,
B,
Z
);
input A;
input B;
output Z;
and (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.723828 |
module AND2HD4XSPG (
A,
B,
Z
);
input A;
input B;
output Z;
and (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.985417 |
module AND2HDLX (
A,
B,
Z
);
input A;
input B;
output Z;
and (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.498798 |
module AND4HD2X (
A,
B,
C,
D,
Z
);
input A;
input B;
input C;
input D;
output Z;
and (I0_out, A, B);
and (I1_out, I0_out, C);
and (Z, I1_out, D);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
(D *> Z) = (0, 0);
endspecify
endmodule
| 6.690188 |
module BUFHD12X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.509705 |
module BUFCLKHD12X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.662943 |
module BUFCLKHD16X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.834503 |
module BUFCLKHD1X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.90195 |
module BUFCLKHD20X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.960907 |
module BUFCLKHD2X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.142603 |
module BUFCLKHD30X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.874562 |
module BUFCLKHD3X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.65332 |
module BUFCLKHD40X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.770549 |
module BUFCLKHD4X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.835126 |
module BUFCLKHD80X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.806863 |
module BUFCLKHD8X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.009914 |
module BUFCLKHDLX (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.513653 |
module BUFHD16X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.514206 |
module BUFHD1X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.336505 |
module BUFHD20X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.704684 |
module BUFHD2X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.947518 |
module BUFHD3X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.281553 |
module BUFHD4X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.576532 |
module BUFHD8X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.610824 |
module BUFHD8XSPG (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.988551 |
module BUFHDLX (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.022094 |
module BUFTSHD12X (
A,
E,
Z
);
input A;
input E;
output Z;
bufif1 (Z, A, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.588689 |
module BUFTSHD16X (
A,
E,
Z
);
input A;
input E;
output Z;
bufif1 (Z, A, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.841718 |
module BUFTSHD1X (
A,
E,
Z
);
input A;
input E;
output Z;
bufif1 (Z, A, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.793334 |
module BUFTSHD20X (
A,
E,
Z
);
input A;
input E;
output Z;
bufif1 (Z, A, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.954639 |
module BUFTSHD2X (
A,
E,
Z
);
input A;
input E;
output Z;
bufif1 (Z, A, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.839328 |
module BUFTSHD3X (
A,
E,
Z
);
input A;
input E;
output Z;
bufif1 (Z, A, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.609872 |
module BUFTSHD4X (
A,
E,
Z
);
input A;
input E;
output Z;
bufif1 (Z, A, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 7.023161 |
module BUFTSHD8X (
A,
E,
Z
);
input A;
input E;
output Z;
bufif1 (Z, A, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 7.118051 |
module BUFTSHDLX (
A,
E,
Z
);
input A;
input E;
output Z;
bufif1 (Z, A, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.52179 |
module DEL1HD1X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.361073 |
module DEL1HD1XSPG (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.097495 |
module DEL1HD2X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.705398 |
module DEL2HD1X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.8431 |
module DEL2HD1XSPG (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.432799 |
module DEL2HD2X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.852211 |
module DEL3HD1X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.220929 |
module DEL3HD2X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.490349 |
module DEL4HD1X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.575301 |
module DEL4HD1XSPG (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.178899 |
module DEL4HD2X (
A,
Z
);
input A;
output Z;
buf (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.785041 |
module INVHD12X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.776426 |
module INVCLKHD12X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.525768 |
module INVCLKHD16X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.739497 |
module INVCLKHD1X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.696387 |
module INVCLKHD20X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.034745 |
module INVCLKHD2X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.120877 |
module INVCLKHD30X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.856909 |
module INVCLKHD3X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.561527 |
module INVCLKHD40X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.645565 |
module INVCLKHD4X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.693005 |
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