code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module INVCLKHD8X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.810403 |
module INVHD16X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.721336 |
module INVHD1X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.792668 |
module INVHD20X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 8.13066 |
module INVHD2X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 8.195566 |
module INVHD2XSPG (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.751444 |
module INVHD3X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.452585 |
module INVHD4X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.719795 |
module INVHD8X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.966713 |
module INVHDLX (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.2645 |
module INVHDPX (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.901676 |
module INVTSHD12X (
A,
E,
Z
);
input A;
input E;
output Z;
not (I0_out, A);
bufif1 (Z, I0_out, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.65957 |
module INVTSHD16X (
A,
E,
Z
);
input A;
input E;
output Z;
not (I0_out, A);
bufif1 (Z, I0_out, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.896506 |
module INVTSHD1X (
A,
E,
Z
);
input A;
input E;
output Z;
not (I0_out, A);
bufif1 (Z, I0_out, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.916146 |
module INVTSHD20X (
A,
E,
Z
);
input A;
input E;
output Z;
not (I0_out, A);
bufif1 (Z, I0_out, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 7.069507 |
module INVTSHD2X (
A,
E,
Z
);
input A;
input E;
output Z;
not (I0_out, A);
bufif1 (Z, I0_out, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 7.136902 |
module INVTSHD3X (
A,
E,
Z
);
input A;
input E;
output Z;
not (I0_out, A);
bufif1 (Z, I0_out, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.80726 |
module INVTSHD4X (
A,
E,
Z
);
input A;
input E;
output Z;
not (I0_out, A);
bufif1 (Z, I0_out, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 7.203494 |
module INVTSHD8X (
A,
E,
Z
);
input A;
input E;
output Z;
not (I0_out, A);
bufif1 (Z, I0_out, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 7.154052 |
module INVTSHDLX (
A,
E,
Z
);
input A;
input E;
output Z;
not (I0_out, A);
bufif1 (Z, I0_out, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.640116 |
module MUX2HD4X (
A,
B,
S0,
Z
);
input A;
input B;
input S0;
output Z;
udp_mux2(
Z, A, B, S0
);
not (I1_out, A);
and (\!A&B , I1_out, B);
not (I3_out, B);
and (\A&!B , A, I3_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
ifnone (S0 *> Z) ... | 6.522191 |
module NAND2B1HD2X (
AN,
B,
Z
);
input AN;
input B;
output Z;
not (I0_out, AN);
and (I1_out, I0_out, B);
not (Z, I1_out);
specify
// path delays
(AN *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.601919 |
module NAND2B1HD4X (
AN,
B,
Z
);
input AN;
input B;
output Z;
not (I0_out, AN);
and (I1_out, I0_out, B);
not (Z, I1_out);
specify
// path delays
(AN *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.67366 |
module NAND2HD1X (
A,
B,
Z
);
input A;
input B;
output Z;
and (I0_out, A, B);
not (Z, I0_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.911576 |
module NAND2HD2X (
A,
B,
Z
);
input A;
input B;
output Z;
and (I0_out, A, B);
not (Z, I0_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.206971 |
module NAND2HD2XSPG (
A,
B,
Z
);
input A;
input B;
output Z;
and (I0_out, A, B);
not (Z, I0_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.602272 |
module NAND2HD4X (
A,
B,
Z
);
input A;
input B;
output Z;
and (I0_out, A, B);
not (Z, I0_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.20664 |
module NAND2HD4XSPG (
A,
B,
Z
);
input A;
input B;
output Z;
and (I0_out, A, B);
not (Z, I0_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.560978 |
module NAND2HDLX (
A,
B,
Z
);
input A;
input B;
output Z;
and (I0_out, A, B);
not (Z, I0_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.074508 |
module NAND3B1HD2X (
AN,
B,
C,
Z
);
input AN;
input B;
input C;
output Z;
not (I0_out, AN);
and (I1_out, I0_out, B);
and (I2_out, I1_out, C);
not (Z, I2_out);
specify
// path delays
(AN *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
endspecify
endmodule
| 6.561134 |
module NAND3B1HD4X (
AN,
B,
C,
Z
);
input AN;
input B;
input C;
output Z;
not (I0_out, AN);
and (I1_out, I0_out, B);
and (I2_out, I1_out, C);
not (Z, I2_out);
specify
// path delays
(AN *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
endspecify
endmodule
| 6.627907 |
module NAND3HD2X (
A,
B,
C,
Z
);
input A;
input B;
input C;
output Z;
and (I0_out, A, B);
and (I1_out, I0_out, C);
not (Z, I1_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
endspecify
endmodule
| 6.634066 |
module NAND3HD4X (
A,
B,
C,
Z
);
input A;
input B;
input C;
output Z;
and (I0_out, A, B);
and (I1_out, I0_out, C);
not (Z, I1_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
endspecify
endmodule
| 6.854232 |
module NAND4B1HD4X (
AN,
B,
C,
D,
Z
);
input AN;
input B;
input C;
input D;
output Z;
not (I0_out, AN);
and (I1_out, I0_out, B);
and (I2_out, I1_out, C);
and (I3_out, I2_out, D);
not (Z, I3_out);
specify
// path delays
(AN *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C... | 6.545882 |
module NAND4B2HD2X (
AN,
BN,
C,
D,
Z
);
input AN;
input BN;
input C;
input D;
output Z;
not (I0_out, AN);
not (I1_out, BN);
and (I2_out, I0_out, I1_out);
and (I3_out, I2_out, C);
and (I4_out, I3_out, D);
not (Z, I4_out);
specify
// path delays
(AN *> Z) = (0, 0);
... | 6.639877 |
module NAND4B2HD4X (
AN,
BN,
C,
D,
Z
);
input AN;
input BN;
input C;
input D;
output Z;
not (I0_out, AN);
not (I1_out, BN);
and (I2_out, I0_out, I1_out);
and (I3_out, I2_out, C);
and (I4_out, I3_out, D);
not (Z, I4_out);
specify
// path delays
(AN *> Z) = (0, 0);
... | 6.616936 |
module NAND4B2HDLX (
AN,
BN,
C,
D,
Z
);
input AN;
input BN;
input C;
input D;
output Z;
not (I0_out, BN);
not (I1_out, AN);
and (I2_out, I0_out, I1_out);
and (I3_out, I2_out, C);
and (I4_out, I3_out, D);
not (Z, I4_out);
specify
// path delays
(AN *> Z) = (0, 0);
... | 6.519688 |
module NAND4HD1X (
A,
B,
C,
D,
Z
);
input A;
input B;
input C;
input D;
output Z;
and (I0_out, A, B);
and (I1_out, I0_out, C);
and (I2_out, I1_out, D);
not (Z, I2_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
(D *> Z) ... | 6.630576 |
module NAND4HD2X (
A,
B,
C,
D,
Z
);
input A;
input B;
input C;
input D;
output Z;
and (I0_out, A, B);
and (I1_out, I0_out, C);
and (I2_out, I1_out, D);
not (Z, I2_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
(D *> Z) ... | 6.824832 |
module NAND4HD4X (
A,
B,
C,
D,
Z
);
input A;
input B;
input C;
input D;
output Z;
and (I0_out, A, B);
and (I1_out, I0_out, C);
and (I2_out, I1_out, D);
not (Z, I2_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
(D *> Z) ... | 6.741927 |
module NAND4HDLX (
A,
B,
C,
D,
Z
);
input A;
input B;
input C;
input D;
output Z;
and (I0_out, A, B);
and (I1_out, I0_out, C);
and (I2_out, I1_out, D);
not (Z, I2_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
(D *> Z) ... | 6.541568 |
module NOR2HD1X (
A,
B,
Z
);
input A;
input B;
output Z;
or (I0_out, A, B);
not (Z, I0_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.845095 |
module NOR2HD2X (
A,
B,
Z
);
input A;
input B;
output Z;
or (I0_out, A, B);
not (Z, I0_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.935641 |
module NOR2HD2XSPG (
A,
B,
Z
);
input A;
input B;
output Z;
or (I0_out, A, B);
not (Z, I0_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.611237 |
module NOR2HD4X (
A,
B,
Z
);
input A;
input B;
output Z;
or (I0_out, A, B);
not (Z, I0_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.600856 |
module NOR2HDLX (
A,
B,
Z
);
input A;
input B;
output Z;
or (I0_out, A, B);
not (Z, I0_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.586261 |
module OR2HD1X (
A,
B,
Z
);
input A;
input B;
output Z;
or (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.815768 |
module OR2HD2X (
A,
B,
Z
);
input A;
input B;
output Z;
or (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.702762 |
module OR2HD2XSPG (
A,
B,
Z
);
input A;
input B;
output Z;
or (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.949428 |
module OR2HD4X (
A,
B,
Z
);
input A;
input B;
output Z;
or (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.494581 |
module OR2HD4XSPG (
A,
B,
Z
);
input A;
input B;
output Z;
or (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.69115 |
module OR2HDLX (
A,
B,
Z
);
input A;
input B;
output Z;
or (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.063837 |
module OR3HD1X (
A,
B,
C,
Z
);
input A;
input B;
input C;
output Z;
or (I0_out, A, B);
or (Z, I0_out, C);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
endspecify
endmodule
| 6.50562 |
module OR3HD2X (
A,
B,
C,
Z
);
input A;
input B;
input C;
output Z;
or (I0_out, A, B);
or (Z, I0_out, C);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
endspecify
endmodule
| 6.694567 |
module OR3HD4X (
A,
B,
C,
Z
);
input A;
input B;
input C;
output Z;
or (I0_out, A, B);
or (Z, I0_out, C);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
endspecify
endmodule
| 6.544805 |
module OR4HD1X (
A,
B,
C,
D,
Z
);
input A;
input B;
input C;
input D;
output Z;
or (I0_out, A, B);
or (I1_out, I0_out, C);
or (Z, I1_out, D);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
(D *> Z) = (0, 0);
endspecify
endm... | 6.848575 |
module OR4HD2X (
A,
B,
C,
D,
Z
);
input A;
input B;
input C;
input D;
output Z;
or (I0_out, A, B);
or (I1_out, I0_out, C);
or (Z, I1_out, D);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
(D *> Z) = (0, 0);
endspecify
endm... | 6.944529 |
module OR4HD4X (
A,
B,
C,
D,
Z
);
input A;
input B;
input C;
input D;
output Z;
or (I0_out, A, B);
or (I1_out, I0_out, C);
or (Z, I1_out, D);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
(D *> Z) = (0, 0);
endspecify
endm... | 6.792504 |
module XOR2HD1X (
A,
B,
Z
);
input A;
input B;
output Z;
xor (Z, A, B);
not (\!B , B);
not (\!A , A);
specify
// path delays
ifnone (A *> Z) = (0, 0);
if (B) (A *> Z) = (0, 0);
if (!B) (A *> Z) = (0, 0);
ifnone (B *> Z) = (0, 0);
if (A) (B *> Z) = (0, 0);
if (!A) ... | 6.801861 |
module XOR2HD2X (
A,
B,
Z
);
input A;
input B;
output Z;
xor (Z, A, B);
not (\!B , B);
not (\!A , A);
specify
// path delays
ifnone (A *> Z) = (0, 0);
if (B) (A *> Z) = (0, 0);
if (!B) (A *> Z) = (0, 0);
ifnone (B *> Z) = (0, 0);
if (A) (B *> Z) = (0, 0);
if (!A) ... | 6.800078 |
module XOR2HD4X (
A,
B,
Z
);
input A;
input B;
output Z;
xor (Z, A, B);
not (\!B , B);
not (\!A , A);
specify
// path delays
ifnone (A *> Z) = (0, 0);
if (B) (A *> Z) = (0, 0);
if (!B) (A *> Z) = (0, 0);
ifnone (B *> Z) = (0, 0);
if (A) (B *> Z) = (0, 0);
if (!A) ... | 6.631982 |
module smii (
eth_clk,
eth_rst,
eth_sync_pad_o,
eth_tx_pad_o,
eth_rx_pad_i,
mtxd,
mtxen,
mtxerr,
mtx_clk,
mrxd,
mrxdv,
mrxerr,
mrx_clk,
mcoll,
mcrs,
speed,
duplex,
link
);
input eth_clk;
input eth_rst; // active high reset synchronous to ethe... | 7.937404 |
module obufdff (
input d,
output reg pad,
input clk,
input rst
);
always @(posedge clk or posedge rst)
if (rst) pad <= #1 1'b0;
else pad <= #1 d;
endmodule
| 7.663367 |
module iobuftri (
input i,
input oe,
output o,
inout pad
);
assign #1 pad = oe ? i : 1'bz;
assign #1 i = pad;
endmodule
| 7.052328 |
module smii_txrx (
output tx,
input rx,
input [ 3:0] mtxd,
input mtxen,
input mtxerr,
output mtx_clk,
output reg [ 3:0] mrxd,
output reg mrxdv,
output reg mrxerr,
output mrx_clk,
output ... | 6.863317 |
module generic_fifo (
async_rst_n,
psh_clk,
psh_we,
psh_d,
psh_full,
pop_clk,
pop_re,
pop_q,
pop_empty,
almost_empty
);
parameter dw = 8;
parameter size = 16;
parameter size_log_2 = 4;
/* Asynch. reset, active low */
input async_rst_n;
/* Push side signals */
inp... | 7.803344 |
module
*
* Generate sync to PHY, and for internal statemachines
*
* Julius Baxter, julius.baxter@orsoc.se
*
*/
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ... | 6.793667 |
module sml (
clk,
w,
out
);
input clk, w;
output reg out;
localparam [2:0]
zero = 3'b000,
one = 3'b001,
two = 3'b010,
three = 3'b011,
four = 3'b100,
five = 3'b101,
six = 3'b110,
seven = 3'b111;
reg [2:0] stateMealy_reg, stateMealy_next;
always @(posedge clk) begin
stateMeal... | 6.746902 |
module SMMemory (
// General Interface
input ResetIn,
input SMBusyIn,
//Read Interface
input [ 9:0] ReadAddressIn,
output [17:0] ReadDataOut,
input ReadSelectIn,
input ReadClockIn,
//Write Interface
input [9:0] WriteAddressIn,
input [8:0] WriteDataIn,
i... | 6.898166 |
module smoldvi #(
// Defaults are for 640x480p 60 Hz (from CEA 861D).
// All horizontal timings are in pixels.
// All vertical timings are in scanlines.
parameter H_SYNC_POLARITY = 1'b0, // 0 for active-low pulse
parameter H_FRONT_PORCH = 16,
parameter H_SYNC_WIDTH = 96,
parameter H_BA... | 9.610443 |
module takes a half-rate bit clock (5x pixel clock) and drives a
// pseudodifferential pixel clock using DDR outputs.
module smoldvi_clock_driver (
input wire clk_x5,
input wire rst_n_x5,
output wire qp,
output wire qn
);
reg [9:0] ring_ctr;
always @ (posedge clk_x5 or negedge rst_n_x5... | 6.797335 |
module smoldvi_fast_gearbox #(
parameter W_IN = 10,
parameter W_OUT = 2,
// You should set this by hand, it may be hugely pessimistic *or* optimistic:
parameter STORAGE_SIZE = W_IN * W_OUT
) (
input wire clk_in,
input wire rst_n_in,
input wire [W_IN-1:0] din,
input... | 6.783879 |
module smoldvi_timing #(
// Defaults are for 640x480p 60 Hz (from CEA 861D).
// All horizontal timings are in pixels.
// All vertical timings are in scanlines.
parameter H_SYNC_POLARITY = 1'b0, // 0 for active-low pulse
parameter H_FRONT_PORCH = 16,
parameter H_SYNC_WIDTH = 96,
paramet... | 9.973404 |
module smoldvi_tmds_encode (
input wire clk,
input wire rst_n,
input wire [1:0] c,
input wire [7:0] d,
input wire den,
output reg [9:0] q
);
reg [2:0] popcount;
wire low_balance = !popcount[2];
always @(*) begin : count_d_pop
integer i;
popcount = 3'd0;
// Ignore d[0]... | 6.814431 |
module smoother #(
parameter HBLKS = 10,
parameter VBLKS = 10,
parameter SMOOTH_T = 1400
) (
input clk_i,
input rst_ni,
input [$clog2(HBLKS)-1:0] ht_cur_i,
input [$clog2(VBLKS)-1:0] vt_cur_i,
input [2:0] mode_i,
output reg [2:0] mode_o
);
localparam FANTASY = SMOOTH_T * 148500;
... | 7.94992 |
module smpldbit_reg2 (
input wire clock,
input wire reset,
input wire [1:0] ctrl, // bittime fsm: smpldbit_reg_ctrl
output wire smpldbit, // MAC, destuff, biterrordetect
input wire puffer // edgepuffer: puffer
);
//tmrg default triplicate
//tmrg tmr_error ... | 7.948356 |
module smplfir #(
// {{{
parameter IW = 15,
localparam OW = IW + 1
// }}}
) (
// {{{
input wire i_clk,
i_ce,
input wire [(IW-1):0] i_val,
output reg [(OW-1):0] o_val
// }}}
);
reg [(IW-1):0] delayed;
initial delayed = 0;
always @(posedge i_clk) if (i_ce) delayed <= i_val... | 7.04023 |
module BufferCC_5 (
input io_dataIn,
output io_dataOut,
input clocking_GCLK25,
input system_cores_1_debugReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clocking_GCLK25 or posedge system_cores_1_debugReset... | 6.82712 |
module BufferCC_4 (
input io_dataIn,
output io_dataOut,
input clocking_GCLK25,
input system_cores_0_debugReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clocking_GCLK25 or posedge system_cores_0_debugReset... | 6.634474 |
module BufferCC_3 (
input io_dataIn,
output io_dataOut,
input clocking_GCLK25,
input sdramCd_logic_outputReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clocking_GCLK25 or posedge sdramCd_logic_outputReset... | 6.792516 |
module FlowCCByToggle (
input io_input_valid,
input io_input_payload_last,
input [0:0] io_input_payload_fragment,
output io_output_valid,
output io_output_payload_last,
output [0:0] io_output_payload_fragment,
input tck,
input clocking_GCLK25,
... | 7.790686 |
module BufferCC_1 (
input io_dataIn,
output io_dataOut,
input clocking_GCLK25,
input systemCd_logic_outputReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clocking_GCLK25) begin
if (systemCd_logic_outpu... | 6.574801 |
module BufferCC (
input io_dataIn,
output io_dataOut,
input clocking_GCLK25,
input debugCd_logic_outputReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clocking_GCLK25) begin
buffers_0 <= io_dataIn;
... | 6.712921 |
module SMPS_ZVS_Controller (
input clk,
input [23:0] SMPS_50V_VSense,
input [23:0] SMPS_50V_CSense,
output SMPS_Driver1,
output SMPS_Driver2,
output SMPS_Driver3,
output SMPS_Driver4
);
// Manages the SMPS Driver, VSense and CSense are useful for keeping a stable 50V value
// CSense all... | 7.106035 |
module SMPTE274_tb ();
reg clk;
reg RST;
reg EN;
reg [9 : 0] i_data_Y, i_data_C;
wire [11 : 0] PIX_CNT_o;
wire [10 : 0] LINE_CNT_o;
wire [9 : 0] Y_data_o, C_data_o;
wire VSYNC_o;
wire HSYNC_o;
wire DATA_RQ_o;
integer data_file; // file handler
integer... | 7.352572 |
module smpu_comp_hit (
biu_pad_haddr,
biu_pad_hprot,
smpu_entry,
smpu_entry0,
smpu_hit,
smpu_hsec
);
// &Ports; @20
input [31:0] biu_pad_haddr;
input [3 : 0] biu_pad_hprot;
input [31:0] smpu_entry;
input [31:0] smpu_entry0;
output smpu_hit;
output smpu_hsec;
// &Regs; @21
reg... | 6.583609 |
module sms_sram_bk2 (
hrst_b,
ram_addr,
ram_clk,
ram_rdata,
ram_sel,
ram_size,
ram_wdata,
ram_write
);
input hrst_b;
input [15:0] ram_addr;
input ram_clk;
input ram_sel;
input [2 : 0] ram_size;
input [31:0] ram_wdata;
input ram_write;
output [31:0] ram_rdata;
reg [3 : ... | 6.953215 |
module SMScheduler (
input reset,
input clk,
input stall_i,
input [`SIZE_SM_LOG-1:0] nSM_i, //allowed SM number
//input [`SIZE_SM-1:0] SMEnMask_i, //follow "nSM_i"
input [`SIZE_GRAN-1:0] granu_i,
input swapDone_i,
//notBraRcv
input branch_i,
input issuedbranch_i,
input r... | 6.716861 |
module sms_sram_1M_bk2 (
hrst_b,
ram_addr,
ram_clk,
ram_rdata,
ram_sel,
ram_size,
ram_wdata,
ram_write
);
input hrst_b;
input [31:0] ram_addr;
input ram_clk;
input ram_sel;
input [2 : 0] ram_size;
input [31:0] ram_wdata;
input ram_write;
output [31:0] ram_rdata;
reg [3... | 6.741091 |
module CrossBarCell (
input [63:0] io_fw_left,
input [63:0] io_fw_top,
output [63:0] io_fw_bottom,
output [63:0] io_fw_right,
input io_sel
);
assign io_fw_bottom = io_sel ? io_fw_left : io_fw_top; // @[CrossBarSwitch.scala 15:17 CrossBarSwitch.scala 16:18 CrossBarSwitch.scala 18:18]
as... | 7.603405 |
module CLOScell4 (
input clock,
input [63:0] io_in4_0,
input [63:0] io_in4_1,
input [63:0] io_in4_2,
input [63:0] io_in4_3,
output [63:0] io_out4_0,
output [63:0] io_out4_1,
output [63:0] io_out4_2,
output [63:0] io_out4_3,
input [ 7:0] io_ctrl
);
wire CrossBarSwit... | 7.132057 |
module smToTc #(
parameter DW = 8
) (
input [DW-1:0] a,
output [DW-1:0] w
);
wire [DW-2:0] mag;
wire [DW-1:0] temp;
wire sign;
assign sign = a[DW-1];
assign mag = a[DW-2:0];
assign temp = {1'b0, mag};
assign w = (sign) ? (~temp + 1'b1) : temp;
endmodule
| 6.616318 |
module SMULT16_ser4 (
output reg [255:0] product,
output V,
input [15:0] scalar,
input [255:0] vecin,
input start,
output reg done,
input clk1,
input clk2
);
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;
... | 6.599763 |
module SMULT16_ser8 (
output reg [255:0] product,
output V,
input [15:0] scalar,
input [255:0] vecin,
input start,
output reg done,
input clk1,
input clk2
);
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;
... | 6.840863 |
module SMULT16 (
output [255:0] product,
output V,
input [15:0] scalar,
input [255:0] vecin,
input start,
output done
);
wire [15:0] Ov;
assign V = Ov[0] | Ov[1] | Ov[2] | Ov[3] | Ov[4] | Ov[5] | Ov[6] |
Ov[7] | Ov[8] | Ov[9] | Ov[10] | Ov[11] | Ov[12] | Ov[13] | Ov[14]|Ov[15];... | 6.714901 |
module SMULT16p (
output [255:0] product,
output V,
input Clk1,
input Clk2,
input [15:0] scalar,
input [255:0] vecin,
input start,
output reg done
);
reg [ 1:0] state;
wire [15:0] Ov;
assign V = Ov[0] | Ov[1] | Ov[2] | Ov[3] | Ov[4] | Ov[5] | Ov[6] |
Ov[7] | Ov[8] | O... | 6.982493 |
module SMULT16ser (
output reg [15:0] product,
output reg V,
input Clk1,
input Clk2,
input [15:0] scalar,
input [15:0] vecin,
input start,
output reg write,
output reg done
);
wire Ov;
wire [15:0] element;
reg [4:0] state;
VMULT mult (
.product(element),
.Overfl... | 6.535417 |
module SMULT16serp (
output reg [15:0] product,
output reg V,
input Clk1,
input Clk2,
input [15:0] scalar,
input [15:0] vecin,
input start,
output reg write,
output reg done
);
wire Ov;
wire [15:0] element;
reg [4:0] state;
VMULTp mult (
.product(element),
.Over... | 6.757078 |
module sMult_pipe #(
parameter WI1 = 4, //length of the integer part, operand 1
WF1 = 3, //length of the fraction part, operand 1
WI2 = 2, //length of the integer part, operand 2
WF2 = 5, //length of the fraction part, operand 2
//WIR = 6, //the length for the integer part of the required outpu... | 7.290757 |
module smux (
input a,
input b,
input sel,
output out
);
assign out = (a & sel) | (b & (~sel));
endmodule
| 7.179673 |
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