code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module INVCLKHD8X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 6.810403 |
module INVHD16X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.721336 |
module INVHD1X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.792668 |
module INVHD20X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 8.13066 |
module INVHD2X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 8.195566 |
module INVHD2XSPG (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.751444 |
module INVHD3X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.452585 |
module INVHD4X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.719795 |
module INVHD8X (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.966713 |
module INVHDLX (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.2645 |
module INVHDPX (
A,
Z
);
input A;
output Z;
not (Z, A);
specify
// path delays
(A *> Z) = (0, 0);
endspecify
endmodule
| 7.901676 |
module INVTSHD12X (
A,
E,
Z
);
input A;
input E;
output Z;
not (I0_out, A);
bufif1 (Z, I0_out, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.65957 |
module INVTSHD16X (
A,
E,
Z
);
input A;
input E;
output Z;
not (I0_out, A);
bufif1 (Z, I0_out, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.896506 |
module INVTSHD1X (
A,
E,
Z
);
input A;
input E;
output Z;
not (I0_out, A);
bufif1 (Z, I0_out, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.916146 |
module INVTSHD20X (
A,
E,
Z
);
input A;
input E;
output Z;
not (I0_out, A);
bufif1 (Z, I0_out, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 7.069507 |
module INVTSHD2X (
A,
E,
Z
);
input A;
input E;
output Z;
not (I0_out, A);
bufif1 (Z, I0_out, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 7.136902 |
module INVTSHD3X (
A,
E,
Z
);
input A;
input E;
output Z;
not (I0_out, A);
bufif1 (Z, I0_out, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.80726 |
module INVTSHD4X (
A,
E,
Z
);
input A;
input E;
output Z;
not (I0_out, A);
bufif1 (Z, I0_out, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 7.203494 |
module INVTSHD8X (
A,
E,
Z
);
input A;
input E;
output Z;
not (I0_out, A);
bufif1 (Z, I0_out, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 7.154052 |
module INVTSHDLX (
A,
E,
Z
);
input A;
input E;
output Z;
not (I0_out, A);
bufif1 (Z, I0_out, E);
specify
// path delays
(A *> Z) = (0, 0);
(E *> Z) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.640116 |
module MUX2HD4X (
A,
B,
S0,
Z
);
input A;
input B;
input S0;
output Z;
udp_mux2(
Z, A, B, S0
);
not (I1_out, A);
and (\!A&B , I1_out, B);
not (I3_out, B);
and (\A&!B , A, I3_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
ifnone (S0 *> Z) = (0, 0);
if (!A & B) (S0 *> Z) = (0, 0);
if (A & !B) (S0 *> Z) = (0, 0);
endspecify
endmodule
| 6.522191 |
module NAND2B1HD2X (
AN,
B,
Z
);
input AN;
input B;
output Z;
not (I0_out, AN);
and (I1_out, I0_out, B);
not (Z, I1_out);
specify
// path delays
(AN *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.601919 |
module NAND2B1HD4X (
AN,
B,
Z
);
input AN;
input B;
output Z;
not (I0_out, AN);
and (I1_out, I0_out, B);
not (Z, I1_out);
specify
// path delays
(AN *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.67366 |
module NAND2HD1X (
A,
B,
Z
);
input A;
input B;
output Z;
and (I0_out, A, B);
not (Z, I0_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.911576 |
module NAND2HD2X (
A,
B,
Z
);
input A;
input B;
output Z;
and (I0_out, A, B);
not (Z, I0_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.206971 |
module NAND2HD2XSPG (
A,
B,
Z
);
input A;
input B;
output Z;
and (I0_out, A, B);
not (Z, I0_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.602272 |
module NAND2HD4X (
A,
B,
Z
);
input A;
input B;
output Z;
and (I0_out, A, B);
not (Z, I0_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.20664 |
module NAND2HD4XSPG (
A,
B,
Z
);
input A;
input B;
output Z;
and (I0_out, A, B);
not (Z, I0_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.560978 |
module NAND2HDLX (
A,
B,
Z
);
input A;
input B;
output Z;
and (I0_out, A, B);
not (Z, I0_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.074508 |
module NAND3B1HD2X (
AN,
B,
C,
Z
);
input AN;
input B;
input C;
output Z;
not (I0_out, AN);
and (I1_out, I0_out, B);
and (I2_out, I1_out, C);
not (Z, I2_out);
specify
// path delays
(AN *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
endspecify
endmodule
| 6.561134 |
module NAND3B1HD4X (
AN,
B,
C,
Z
);
input AN;
input B;
input C;
output Z;
not (I0_out, AN);
and (I1_out, I0_out, B);
and (I2_out, I1_out, C);
not (Z, I2_out);
specify
// path delays
(AN *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
endspecify
endmodule
| 6.627907 |
module NAND3HD2X (
A,
B,
C,
Z
);
input A;
input B;
input C;
output Z;
and (I0_out, A, B);
and (I1_out, I0_out, C);
not (Z, I1_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
endspecify
endmodule
| 6.634066 |
module NAND3HD4X (
A,
B,
C,
Z
);
input A;
input B;
input C;
output Z;
and (I0_out, A, B);
and (I1_out, I0_out, C);
not (Z, I1_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
endspecify
endmodule
| 6.854232 |
module NAND4B1HD4X (
AN,
B,
C,
D,
Z
);
input AN;
input B;
input C;
input D;
output Z;
not (I0_out, AN);
and (I1_out, I0_out, B);
and (I2_out, I1_out, C);
and (I3_out, I2_out, D);
not (Z, I3_out);
specify
// path delays
(AN *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
(D *> Z) = (0, 0);
endspecify
endmodule
| 6.545882 |
module NAND4B2HD2X (
AN,
BN,
C,
D,
Z
);
input AN;
input BN;
input C;
input D;
output Z;
not (I0_out, AN);
not (I1_out, BN);
and (I2_out, I0_out, I1_out);
and (I3_out, I2_out, C);
and (I4_out, I3_out, D);
not (Z, I4_out);
specify
// path delays
(AN *> Z) = (0, 0);
(BN *> Z) = (0, 0);
(C *> Z) = (0, 0);
(D *> Z) = (0, 0);
endspecify
endmodule
| 6.639877 |
module NAND4B2HD4X (
AN,
BN,
C,
D,
Z
);
input AN;
input BN;
input C;
input D;
output Z;
not (I0_out, AN);
not (I1_out, BN);
and (I2_out, I0_out, I1_out);
and (I3_out, I2_out, C);
and (I4_out, I3_out, D);
not (Z, I4_out);
specify
// path delays
(AN *> Z) = (0, 0);
(BN *> Z) = (0, 0);
(C *> Z) = (0, 0);
(D *> Z) = (0, 0);
endspecify
endmodule
| 6.616936 |
module NAND4B2HDLX (
AN,
BN,
C,
D,
Z
);
input AN;
input BN;
input C;
input D;
output Z;
not (I0_out, BN);
not (I1_out, AN);
and (I2_out, I0_out, I1_out);
and (I3_out, I2_out, C);
and (I4_out, I3_out, D);
not (Z, I4_out);
specify
// path delays
(AN *> Z) = (0, 0);
(BN *> Z) = (0, 0);
(C *> Z) = (0, 0);
(D *> Z) = (0, 0);
endspecify
endmodule
| 6.519688 |
module NAND4HD1X (
A,
B,
C,
D,
Z
);
input A;
input B;
input C;
input D;
output Z;
and (I0_out, A, B);
and (I1_out, I0_out, C);
and (I2_out, I1_out, D);
not (Z, I2_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
(D *> Z) = (0, 0);
endspecify
endmodule
| 6.630576 |
module NAND4HD2X (
A,
B,
C,
D,
Z
);
input A;
input B;
input C;
input D;
output Z;
and (I0_out, A, B);
and (I1_out, I0_out, C);
and (I2_out, I1_out, D);
not (Z, I2_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
(D *> Z) = (0, 0);
endspecify
endmodule
| 6.824832 |
module NAND4HD4X (
A,
B,
C,
D,
Z
);
input A;
input B;
input C;
input D;
output Z;
and (I0_out, A, B);
and (I1_out, I0_out, C);
and (I2_out, I1_out, D);
not (Z, I2_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
(D *> Z) = (0, 0);
endspecify
endmodule
| 6.741927 |
module NAND4HDLX (
A,
B,
C,
D,
Z
);
input A;
input B;
input C;
input D;
output Z;
and (I0_out, A, B);
and (I1_out, I0_out, C);
and (I2_out, I1_out, D);
not (Z, I2_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
(D *> Z) = (0, 0);
endspecify
endmodule
| 6.541568 |
module NOR2HD1X (
A,
B,
Z
);
input A;
input B;
output Z;
or (I0_out, A, B);
not (Z, I0_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.845095 |
module NOR2HD2X (
A,
B,
Z
);
input A;
input B;
output Z;
or (I0_out, A, B);
not (Z, I0_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.935641 |
module NOR2HD2XSPG (
A,
B,
Z
);
input A;
input B;
output Z;
or (I0_out, A, B);
not (Z, I0_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.611237 |
module NOR2HD4X (
A,
B,
Z
);
input A;
input B;
output Z;
or (I0_out, A, B);
not (Z, I0_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.600856 |
module NOR2HDLX (
A,
B,
Z
);
input A;
input B;
output Z;
or (I0_out, A, B);
not (Z, I0_out);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.586261 |
module OR2HD1X (
A,
B,
Z
);
input A;
input B;
output Z;
or (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.815768 |
module OR2HD2X (
A,
B,
Z
);
input A;
input B;
output Z;
or (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.702762 |
module OR2HD2XSPG (
A,
B,
Z
);
input A;
input B;
output Z;
or (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.949428 |
module OR2HD4X (
A,
B,
Z
);
input A;
input B;
output Z;
or (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.494581 |
module OR2HD4XSPG (
A,
B,
Z
);
input A;
input B;
output Z;
or (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 6.69115 |
module OR2HDLX (
A,
B,
Z
);
input A;
input B;
output Z;
or (Z, A, B);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
endspecify
endmodule
| 7.063837 |
module OR3HD1X (
A,
B,
C,
Z
);
input A;
input B;
input C;
output Z;
or (I0_out, A, B);
or (Z, I0_out, C);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
endspecify
endmodule
| 6.50562 |
module OR3HD2X (
A,
B,
C,
Z
);
input A;
input B;
input C;
output Z;
or (I0_out, A, B);
or (Z, I0_out, C);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
endspecify
endmodule
| 6.694567 |
module OR3HD4X (
A,
B,
C,
Z
);
input A;
input B;
input C;
output Z;
or (I0_out, A, B);
or (Z, I0_out, C);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
endspecify
endmodule
| 6.544805 |
module OR4HD1X (
A,
B,
C,
D,
Z
);
input A;
input B;
input C;
input D;
output Z;
or (I0_out, A, B);
or (I1_out, I0_out, C);
or (Z, I1_out, D);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
(D *> Z) = (0, 0);
endspecify
endmodule
| 6.848575 |
module OR4HD2X (
A,
B,
C,
D,
Z
);
input A;
input B;
input C;
input D;
output Z;
or (I0_out, A, B);
or (I1_out, I0_out, C);
or (Z, I1_out, D);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
(D *> Z) = (0, 0);
endspecify
endmodule
| 6.944529 |
module OR4HD4X (
A,
B,
C,
D,
Z
);
input A;
input B;
input C;
input D;
output Z;
or (I0_out, A, B);
or (I1_out, I0_out, C);
or (Z, I1_out, D);
specify
// path delays
(A *> Z) = (0, 0);
(B *> Z) = (0, 0);
(C *> Z) = (0, 0);
(D *> Z) = (0, 0);
endspecify
endmodule
| 6.792504 |
module XOR2HD1X (
A,
B,
Z
);
input A;
input B;
output Z;
xor (Z, A, B);
not (\!B , B);
not (\!A , A);
specify
// path delays
ifnone (A *> Z) = (0, 0);
if (B) (A *> Z) = (0, 0);
if (!B) (A *> Z) = (0, 0);
ifnone (B *> Z) = (0, 0);
if (A) (B *> Z) = (0, 0);
if (!A) (B *> Z) = (0, 0);
endspecify
endmodule
| 6.801861 |
module XOR2HD2X (
A,
B,
Z
);
input A;
input B;
output Z;
xor (Z, A, B);
not (\!B , B);
not (\!A , A);
specify
// path delays
ifnone (A *> Z) = (0, 0);
if (B) (A *> Z) = (0, 0);
if (!B) (A *> Z) = (0, 0);
ifnone (B *> Z) = (0, 0);
if (A) (B *> Z) = (0, 0);
if (!A) (B *> Z) = (0, 0);
endspecify
endmodule
| 6.800078 |
module XOR2HD4X (
A,
B,
Z
);
input A;
input B;
output Z;
xor (Z, A, B);
not (\!B , B);
not (\!A , A);
specify
// path delays
ifnone (A *> Z) = (0, 0);
if (B) (A *> Z) = (0, 0);
if (!B) (A *> Z) = (0, 0);
ifnone (B *> Z) = (0, 0);
if (A) (B *> Z) = (0, 0);
if (!A) (B *> Z) = (0, 0);
endspecify
endmodule
| 6.631982 |
module smii (
eth_clk,
eth_rst,
eth_sync_pad_o,
eth_tx_pad_o,
eth_rx_pad_i,
mtxd,
mtxen,
mtxerr,
mtx_clk,
mrxd,
mrxdv,
mrxerr,
mrx_clk,
mcoll,
mcrs,
speed,
duplex,
link
);
input eth_clk;
input eth_rst; // active high reset synchronous to ethernet clock
// SMII
output reg eth_sync_pad_o /*synthesis syn_useioff=1 syn_allow_retiming=0 syn_noprune=1*/;
output reg eth_tx_pad_o /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
input eth_rx_pad_i;
// MII
// TX
input [3:0] mtxd;
input mtxen;
input mtxerr;
output mtx_clk;
// RX
output [3:0] mrxd;
output mrxdv;
output mrxerr;
output mrx_clk;
output mcoll;
output mcrs;
output speed;
output duplex;
output link;
// Wires from pads
wire smii_tx;
reg smii_rx /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
// Sync generation
wire [10:1] tx_smii_state;
wire [10:1] next_tx_smii_state;
wire [10:1] rx_smii_state;
wire smii_sync;
smii_sync smii_sync0 (
.sync(smii_sync),
.tx_state(tx_smii_state),
.next_tx_state(next_tx_smii_state),
.rx_state(rx_smii_state),
.clk(eth_clk),
.rst(eth_rst)
);
// IOB regs for SMII
always @(posedge eth_clk) eth_sync_pad_o <= smii_sync;
always @(posedge eth_clk) eth_tx_pad_o <= smii_tx;
always @(posedge eth_clk) smii_rx <= eth_rx_pad_i;
smii_if smii_if0 (
// SMII signals
.tx (smii_tx),
.rx (smii_rx),
.tx_smii_state (tx_smii_state[10:1]),
.next_tx_smii_state(next_tx_smii_state[10:1]),
.rx_smii_state (rx_smii_state[10:1]),
// MAC MII receive
.mrxd (mrxd[3:0]),
.mrxdv (mrxdv),
.mrxerr (mrxerr),
.mrx_clk (mrx_clk),
// MAC MII transmit
.mtx_clk (mtx_clk),
.mtxd (mtxd[3:0]),
.mtxen (mtxen),
.mtxerr (mtxerr),
// Collision
.mcoll (mcoll),
// Carrier sense
.mcrs (mcrs),
// Speedy ethernet
.speed (speed),
// Duplex indicator
.duplex (duplex),
// Linke indicator
.link (link),
// Clocks, resets
.eth_clk (eth_clk),
.eth_rst (eth_rst)
);
endmodule
| 7.937404 |
module obufdff (
input d,
output reg pad,
input clk,
input rst
);
always @(posedge clk or posedge rst)
if (rst) pad <= #1 1'b0;
else pad <= #1 d;
endmodule
| 7.663367 |
module iobuftri (
input i,
input oe,
output o,
inout pad
);
assign #1 pad = oe ? i : 1'bz;
assign #1 i = pad;
endmodule
| 7.052328 |
module smii_txrx (
output tx,
input rx,
input [ 3:0] mtxd,
input mtxen,
input mtxerr,
output mtx_clk,
output reg [ 3:0] mrxd,
output reg mrxdv,
output reg mrxerr,
output mrx_clk,
output mcoll,
output reg mcrs,
input [1:10] state,
input clk,
input rst
);
reg [0:7] tx_data_reg;
reg tx_data_reg_valid;
reg a0;
reg state_data;
reg [3:0] rx_tmp;
reg speed;
reg duplex;
reg link;
reg jabber;
reg mtx_clk_tmp, mrx_clk_tmp;
reg [3:0] tx_cnt;
reg [3:0] rx_cnt;
always @(posedge clk or posedge rst)
if (rst) tx_cnt <= 4'd0;
else if (speed) tx_cnt <= 4'd0;
else if (state[10])
if (tx_cnt == 4'd9) tx_cnt <= 4'd0;
else tx_cnt <= tx_cnt + 4'd1;
always @(posedge clk or posedge rst)
if (rst) mtx_clk_tmp <= 1'b0;
else if ((state[10] | state[5]) & (tx_cnt == 4'd0)) mtx_clk_tmp <= 1'b1;
else if (state[2] | state[7]) mtx_clk_tmp <= 1'b0;
gbuf bufg1 (
.CLK(mtx_clk_tmp),
.GL (mtx_clk)
);
always @(posedge clk or posedge rst)
if (rst) begin
tx_data_reg <= 8'd0;
tx_data_reg_valid <= 1'b0;
a0 <= 1'b0;
end else if ((state[4] | state[9]) & (tx_cnt == 4'd0)) begin
if (!mtxen) a0 <= 1'b0;
else a0 <= ~a0;
if (!mtxen & !a0) tx_data_reg_valid <= 1'b0;
else if (a0) tx_data_reg_valid <= 1'b1;
if (mtxen & !a0) tx_data_reg[0:3] <= {mtxd[0], mtxd[1], mtxd[2], mtxd[3]};
else if (mtxen & a0) tx_data_reg[4:7] <= {mtxd[0], mtxd[1], mtxd[2], mtxd[3]};
end
always @(posedge clk or posedge rst)
if (rst) state_data <= 1'b0;
else if (state[1] & (tx_cnt == 4'd0)) state_data <= tx_data_reg_valid;
assign tx = state[1] ? mtxerr :
state[2] ? ((tx_data_reg_valid & (tx_cnt == 4'd0)) | state_data) :
state_data ? |(state[2:10] & tx_data_reg) :
|(state[2:10] & {mtxerr,speed,duplex,link,jabber,3'b111});
always @(posedge clk or posedge rst)
if (rst) rx_cnt <= 4'd0;
else if (speed) rx_cnt <= 4'd0;
else if (!mrxdv & state[8] & rx_tmp[3]) rx_cnt <= 4'd9;
else if (state[10])
if (rx_cnt == 4'd9) rx_cnt <= 4'd0;
else rx_cnt <= rx_cnt + 4'd1;
always @(posedge clk or posedge rst)
if (rst) begin
{mcrs, mrxdv, mrxerr, speed, duplex, link, jabber} <= 7'b0001110;
rx_tmp <= 4'h0;
mrxd <= 4'h0;
end else begin
rx_tmp[2:0] <= {rx, rx_tmp[2:1]};
if (state[3]) mcrs <= rx;
if (state[4]) rx_tmp[3] <= rx;
if (rx_tmp[3]) begin
if (state[8]) {mrxdv, mrxd} <= #1{rx_tmp[3], rx, rx_tmp[2:0]};
else if (state[2]) mrxd <= #1{rx, rx_tmp[2:0]};
end else begin
if (state[5]) mrxerr <= #1 rx;
if (state[6]) speed <= #1 rx;
if (state[7]) duplex <= #1 rx;
if (state[8]) begin
link <= #1 rx;
mrxdv <= #1 1'b0;
end
if (state[9]) jabber <= #1 rx;
end
end
always @(posedge clk or posedge rst)
if (rst) mrx_clk_tmp <= 1'b0;
else if ((state[1] | state[6]) & (rx_cnt == 4'd0)) mrx_clk_tmp <= 1'b1;
else if (state[3] | state[8]) mrx_clk_tmp <= 1'b0;
gbuf bufg2 (
.CLK(mrx_clk_tmp),
.GL (mrx_clk)
);
assign mcoll = mcrs & mtxen;
endmodule
| 6.863317 |
module generic_fifo (
async_rst_n,
psh_clk,
psh_we,
psh_d,
psh_full,
pop_clk,
pop_re,
pop_q,
pop_empty,
almost_empty
);
parameter dw = 8;
parameter size = 16;
parameter size_log_2 = 4;
/* Asynch. reset, active low */
input async_rst_n;
/* Push side signals */
input psh_clk;
input psh_we;
input [dw-1:0] psh_d;
output psh_full;
/* Pop side signals */
input pop_clk;
input pop_re;
//output reg [dw-1:0] pop_q;
output reg [dw-1:0] pop_q;
output pop_empty;
output wire almost_empty;
integer i;
/* Actual FIFO memory */
reg [dw-1:0] fifo_mem[0:size-1];
initial begin
for (i = 0; i < size; i = i + 1) begin
fifo_mem[i] = {dw{1'b0}};
end
end
/* FIFO position ptr regs */
reg [size_log_2 - 1 : 0] wr_ptr, rd_ptr, ctr;
/* FIFO full signal for push side */
//assign psh_full = (ptr == size-1) ? 1 : 0;
/* This full logic means we all but one slot in the FIFO */
assign psh_full = ctr == size;
/* FIFO empty signal for pop side */
//assign pop_empty = (ptr == 0) ? 1 : 0;
//assign pop_empty = ctr==0;
assign pop_empty = rd_ptr == wr_ptr;
assign almost_empty = ctr < 16;
always @(posedge pop_re or negedge async_rst_n) begin
if (!async_rst_n) begin
rd_ptr <= 0;
pop_q <= 0;
end else begin
if (!pop_empty) begin
pop_q <= fifo_mem[rd_ptr];
ctr <= ctr - 1;
rd_ptr <= rd_ptr + 1;
end
end
end
always @(posedge psh_we or negedge async_rst_n) begin
if (!async_rst_n) begin
for (i = 0; i < size; i = i + 1) fifo_mem[i] <= 0;
wr_ptr <= 0;
ctr <= 0;
end else begin
fifo_mem[wr_ptr] <= psh_d;
wr_ptr <= #1 wr_ptr + 1;
ctr <= ctr + 1;
end
end
endmodule
| 7.803344 |
module
*
* Generate sync to PHY, and for internal statemachines
*
* Julius Baxter, julius.baxter@orsoc.se
*
*/
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module smii_sync
(
// SMII sync
output sync,
// internal
output [10:1] tx_state,
output [10:1] next_tx_state,
output [10:1] rx_state,
// clock amd reset
input clk,
input rst
);
reg [10:1] next_tx_state_r;
reg [10:1] tx_state_r;
reg [10:1] rx_state_int;
reg [10:1] rx_state_int2;
reg [10:1] rx_state_int3;
// sync shall go high every 10:th cycle
always @ (posedge clk)
if (rst)
begin
next_tx_state_r <= 10'b0000000010;
tx_state_r <= 0;
end
else
begin
tx_state_r <= next_tx_state_r;
next_tx_state_r <= {next_tx_state_r[9:1],next_tx_state_r[10]};
end
assign tx_state = tx_state_r;
assign next_tx_state = next_tx_state_r;
assign sync = tx_state_r[1];
always @(posedge clk)
begin
rx_state_int <= {tx_state_r[9:1],tx_state_r[10]};
rx_state_int2 <= rx_state_int;
rx_state_int3 <= rx_state_int2;
end
// rx_state counter is 2 clocks behind tx state due to flops in and out of
// FPGA
assign rx_state = rx_state_int3;
endmodule
| 6.793667 |
module sml (
clk,
w,
out
);
input clk, w;
output reg out;
localparam [2:0]
zero = 3'b000,
one = 3'b001,
two = 3'b010,
three = 3'b011,
four = 3'b100,
five = 3'b101,
six = 3'b110,
seven = 3'b111;
reg [2:0] stateMealy_reg, stateMealy_next;
always @(posedge clk) begin
stateMealy_reg <= stateMealy_next;
end
always @(stateMealy_reg, w) begin
stateMealy_next = stateMealy_reg;
out = 1'b0;
case (stateMealy_reg)
zero: if (w) stateMealy_next = one;
one: if (w) stateMealy_next = two;
two: if (w) stateMealy_next = three;
three: if (w) stateMealy_next = four;
four:
if (w) begin
stateMealy_next = zero;
out = 1'b1;
end
five: if (w) stateMealy_next = zero;
six: if (w) stateMealy_next = zero;
seven: if (w) stateMealy_next = zero;
endcase
end
endmodule
| 6.746902 |
module SMMemory (
// General Interface
input ResetIn,
input SMBusyIn,
//Read Interface
input [ 9:0] ReadAddressIn,
output [17:0] ReadDataOut,
input ReadSelectIn,
input ReadClockIn,
//Write Interface
input [9:0] WriteAddressIn,
input [8:0] WriteDataIn,
input WriteSelectIn,
input [9:0] WriteAddressIn_TLC,
input [8:0] WriteDataIn_TLC,
input WriteSelectIn_TLC,
input WriteClockIn,
output [ 9:0] SMMemory_WriteAddressIn_TLC_o,
output [ 8:0] SMMemory_ReadAddressIn_o,
output SMMemory_WriteSelectIn_TLC_o,
output SMMemory_ReadSelect_RAM0_o,
output SMMemory_WriteClockIn_o,
output SMMemory_ReadClockIn_o,
output [ 8:0] SMMemory_WriteDataIn_TLC_o,
input [17:0] SMMemory_ReadDataOut_SRAM_i,
output [ 9:0] SMMemory_WriteAddressIn_o,
output SMMemory_WriteSelectIn_o,
output SMMemory_ReadSelect_RAM1_o,
output SMMemory_WriteDataIn_o,
input [17:0] SMMemory_ReadDataOut_SRAM1_i
);
// Define local variables
//
wire [17:0] ReadDataOut_SRAM;
wire [17:0] ReadDataOut_SRAM_1;
reg ReadDataSel;
wire ReadSelect_RAM0;
wire ReadSelect_RAM1;
wire SMMemoryBankSelect;
// generate individual read enables
assign ReadSelect_RAM0 = ReadSelectIn && !ReadAddressIn[9];
assign ReadSelect_RAM1 = ReadSelectIn && ReadAddressIn[9];
// Mux the read data
always @(posedge ReadClockIn) ReadDataSel <= ReadAddressIn[9];
assign SMMemoryBankSelect = SMBusyIn ? ReadAddressIn[9] : ReadDataSel;
assign ReadDataOut = SMMemoryBankSelect ? ReadDataOut_SRAM_1 : ReadDataOut_SRAM;
// Instantiate the Memory Blocks
//
assign SMMemory_WriteAddressIn_TLC_o = WriteAddressIn_TLC;
assign SMMemory_ReadAddressIn_o[8:0] = ReadAddressIn[8:0];
assign SMMemory_WriteSelectIn_TLC_o = WriteSelectIn_TLC;
assign SMMemory_ReadSelect_RAM0_o = ReadSelect_RAM0;
assign SMMemory_WriteClockIn_o = WriteClockIn;
assign SMMemory_ReadClockIn_o = ReadClockIn;
assign SMMemory_WriteDataIn_TLC_o = WriteDataIn_TLC;
assign ReadDataOut_SRAM = SMMemory_ReadDataOut_SRAM_i;
assign SMMemory_WriteAddressIn_o = WriteAddressIn;
assign SMMemory_WriteSelectIn_o = WriteSelectIn;
assign SMMemory_ReadSelect_RAM1_o = ReadSelect_RAM1;
assign SMMemory_WriteDataIn_o = WriteDataIn;
assign ReadDataOut_SRAM1 = SMMemory_ReadDataOut_SRAM1_i;
endmodule
| 6.898166 |
module smoldvi #(
// Defaults are for 640x480p 60 Hz (from CEA 861D).
// All horizontal timings are in pixels.
// All vertical timings are in scanlines.
parameter H_SYNC_POLARITY = 1'b0, // 0 for active-low pulse
parameter H_FRONT_PORCH = 16,
parameter H_SYNC_WIDTH = 96,
parameter H_BACK_PORCH = 48,
parameter H_ACTIVE_PIXELS = 640,
parameter V_SYNC_POLARITY = 1'b0, // 0 for active-low pulse
parameter V_FRONT_PORCH = 10,
parameter V_SYNC_WIDTH = 2,
parameter V_BACK_PORCH = 33,
parameter V_ACTIVE_LINES = 480,
parameter RGB_BITS = 6 // 1 to 7 bits, inclusive
) (
// Full-rate pixel clock, half-rate bit clock. Must have exact 1:5 frequency
// ratio, and a common root oscillator
input wire clk_pix,
input wire rst_n_pix,
input wire clk_bit,
input wire rst_n_bit,
input wire en,
input wire [RGB_BITS-1:0] r,
input wire [RGB_BITS-1:0] g,
input wire [RGB_BITS-1:0] b,
output wire rgb_rdy,
// {CK, D2, D1, D0}
output wire [3:0] dvi_p,
output wire [3:0] dvi_n
);
wire hsync;
wire vsync;
wire den;
reg den_prev;
reg rgb_rdy_prev;
assign rgb_rdy = den && den_prev && !rgb_rdy_prev;
always @(posedge clk_pix or negedge rst_n_pix) begin
if (!rst_n_pix) begin
den_prev <= 1'b0;
rgb_rdy_prev <= 1'b0;
end else begin
den_prev <= den;
rgb_rdy_prev <= rgb_rdy;
end
end
smoldvi_timing #(
.H_SYNC_POLARITY(H_SYNC_POLARITY),
.H_FRONT_PORCH (H_FRONT_PORCH),
.H_SYNC_WIDTH (H_SYNC_WIDTH),
.H_BACK_PORCH (H_BACK_PORCH),
.H_ACTIVE_PIXELS(H_ACTIVE_PIXELS),
.V_SYNC_POLARITY(V_SYNC_POLARITY),
.V_FRONT_PORCH (V_FRONT_PORCH),
.V_SYNC_WIDTH (V_SYNC_WIDTH),
.V_BACK_PORCH (V_BACK_PORCH),
.V_ACTIVE_LINES (V_ACTIVE_LINES)
) inst_dvi_timing (
.clk (clk_pix),
.rst_n(rst_n_pix),
.en (en),
.vsync(vsync),
.hsync(hsync),
.den (den)
);
localparam [8-RGB_BITS-1:0] RGB_PAD = {8 - RGB_BITS{1'b0}};
wire [9:0] tmds0;
wire [9:0] tmds1;
wire [9:0] tmds2;
smoldvi_tmds_encode tmds0_encoder (
.clk (clk_pix),
.rst_n(rst_n_pix),
.c ({vsync, hsync}),
.d ({b, RGB_PAD}),
.den (den),
.q (tmds0)
);
smoldvi_tmds_encode tmds1_encoder (
.clk (clk_pix),
.rst_n(rst_n_pix),
.c (2'b00),
.d ({g, RGB_PAD}),
.den (den),
.q (tmds1)
);
smoldvi_tmds_encode tmds2_encoder (
.clk (clk_pix),
.rst_n(rst_n_pix),
.c (2'b00),
.d ({r, RGB_PAD}),
.den (den),
.q (tmds2)
);
smoldvi_serialiser ser_d0 (
.clk_pix (clk_pix),
.rst_n_pix(rst_n_pix),
.clk_x5 (clk_bit),
.rst_n_x5 (rst_n_bit),
.d (tmds0),
.qp(dvi_p[0]),
.qn(dvi_n[0])
);
smoldvi_serialiser ser_d1 (
.clk_pix (clk_pix),
.rst_n_pix(rst_n_pix),
.clk_x5 (clk_bit),
.rst_n_x5 (rst_n_bit),
.d (tmds1),
.qp(dvi_p[1]),
.qn(dvi_n[1])
);
smoldvi_serialiser ser_d2 (
.clk_pix (clk_pix),
.rst_n_pix(rst_n_pix),
.clk_x5 (clk_bit),
.rst_n_x5 (rst_n_bit),
.d (tmds2),
.qp(dvi_p[2]),
.qn(dvi_n[2])
);
smoldvi_clock_driver ser_ck (
.clk_x5 (clk_bit),
.rst_n_x5(rst_n_bit),
.qp(dvi_p[3]),
.qn(dvi_n[3])
);
endmodule
| 9.610443 |
module takes a half-rate bit clock (5x pixel clock) and drives a
// pseudodifferential pixel clock using DDR outputs.
module smoldvi_clock_driver (
input wire clk_x5,
input wire rst_n_x5,
output wire qp,
output wire qn
);
reg [9:0] ring_ctr;
always @ (posedge clk_x5 or negedge rst_n_x5) begin
if (!rst_n_x5) begin
ring_ctr <= 10'b11111_00000;
end else begin
ring_ctr <= {ring_ctr[1:0], ring_ctr[9:2]};
end
end
ddr_out ddrp (
.clk (clk_x5),
.rst_n (rst_n_x5),
.d_rise (ring_ctr[0]),
.d_fall (ring_ctr[1]),
.e (1),
.q (qp)
);
ddr_out ddrn (
.clk (clk_x5),
.rst_n (rst_n_x5),
.d_rise (ring_ctr[5]),
.d_fall (ring_ctr[6]),
.e (1),
.q (qn)
);
endmodule
| 6.797335 |
module smoldvi_fast_gearbox #(
parameter W_IN = 10,
parameter W_OUT = 2,
// You should set this by hand, it may be hugely pessimistic *or* optimistic:
parameter STORAGE_SIZE = W_IN * W_OUT
) (
input wire clk_in,
input wire rst_n_in,
input wire [W_IN-1:0] din,
input wire clk_out,
input wire rst_n_out,
output reg [W_OUT-1:0] dout
);
localparam N_IN = STORAGE_SIZE / W_IN;
localparam N_OUT = STORAGE_SIZE / W_OUT;
(* keep = 1'b1 *) reg [STORAGE_SIZE-1:0] launch_reg;
(* keep = 1'b1 *) reg [STORAGE_SIZE-1:0] capture_reg;
// ----------------------------------------------------------------------------
// Apply transitions to sections of launch register, in a circular manner,
// across successive clk_in cycles
(* keep = 1'b1 *) reg [STORAGE_SIZE-1:0] launch_reg;
reg [N_IN-1:0] wmask;
always @(posedge clk_in or negedge rst_n_in) begin
if (!rst_n_in) begin
wmask <= {{N_IN - 1{1'b0}}, 1'b1};
end else begin
wmask <= {wmask[N_IN-2:0], wmask[N_IN-1]};
end
end
always @(posedge clk_in) begin : wport
integer i;
for (i = 0; i < N_IN; i = i + 1) begin
if (wmask[i]) launch_reg[i*W_IN+:W_IN] <= din;
end
end
// ----------------------------------------------------------------------------
// Apply enables to sections of capture register, in a circular manner, across
// successive clk_out cycles (hopefully staying distant from the transitions!)
(* keep = 1'b1 *) reg [STORAGE_SIZE-1:0] capture_reg;
reg [N_OUT-1:0] rmask;
always @(posedge clk_out or negedge rst_n_out) begin
if (!rst_n_out) begin
// Reads start as far as possible from writes
rmask <= {{N_OUT - 1{1'b0}}, 1'b1} << (N_OUT / 2);
end else begin
rmask <= {rmask[N_OUT-2:0], rmask[N_OUT-1]};
end
end
always @(posedge clk_out) begin : capture_proc
integer i;
for (i = 0; i < N_OUT; i = i + 1) begin
if (rmask[i]) capture_reg[i*W_OUT+:W_OUT] <= launch_reg[i*W_OUT+:W_OUT];
end
end
// ----------------------------------------------------------------------------
// CDC done, now on to the muxing
wire [N_OUT-1:0] rmask_delayed = {rmask[0], rmask[N_OUT-1:1]};
reg [STORAGE_SIZE-1:0] captured_masked;
always @(posedge clk_out) begin : output_mask
integer i;
for (i = 0; i < STORAGE_SIZE; i = i + 1) begin
captured_masked[i] <= capture_reg[i] && rmask_delayed[i/W_OUT];
end
end
// Do the OR reduction in one cycle. For 20 storage flops this is a 10:1
// reduction, which costs 2 LUT delays. Easiest way to reduce further is to add
// an empty pipe stage afterward and tell the tools to retime :) OR reductions
// are very retimable.
reg [W_OUT-1:0] muxed;
always @(*) begin : output_mux
integer i, j;
for (i = 0; i < W_OUT; i = i + 1) begin
muxed[i] = 1'b0;
for (j = 0; j < N_OUT; j = j + 1) begin
muxed[i] = muxed[i] || captured_masked[j*W_OUT+i];
end
end
end
always @(posedge clk_out) begin
dout <= muxed;
end
endmodule
| 6.783879 |
module smoldvi_timing #(
// Defaults are for 640x480p 60 Hz (from CEA 861D).
// All horizontal timings are in pixels.
// All vertical timings are in scanlines.
parameter H_SYNC_POLARITY = 1'b0, // 0 for active-low pulse
parameter H_FRONT_PORCH = 16,
parameter H_SYNC_WIDTH = 96,
parameter H_BACK_PORCH = 48,
parameter H_ACTIVE_PIXELS = 640,
parameter V_SYNC_POLARITY = 1'b0, // 0 for active-low pulse
parameter V_FRONT_PORCH = 10,
parameter V_SYNC_WIDTH = 2,
parameter V_BACK_PORCH = 33,
parameter V_ACTIVE_LINES = 480
) (
input wire clk,
input wire rst_n,
input wire en,
output reg vsync,
output reg hsync,
output reg den
);
parameter W_H_CTR = $clog2(H_ACTIVE_PIXELS);
parameter W_V_CTR = $clog2(V_ACTIVE_LINES);
// ----------------------------------------------------------------------------
// Horizontal timing state machine
localparam W_STATE = 2;
localparam S_FRONT_PORCH = 2'h0;
localparam S_SYNC = 2'h1;
localparam S_BACK_PORCH = 2'h2;
localparam S_ACTIVE = 2'h3;
reg [W_H_CTR-1:0] h_ctr;
reg [W_STATE-1:0] h_state;
reg in_active_vertical_period;
reg v_advance;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
h_state <= S_FRONT_PORCH;
h_ctr <= {W_H_CTR{1'b0}};
hsync <= !H_SYNC_POLARITY;
den <= 1'b0;
v_advance <= 1'b0;
end else if (!en) begin
hsync <= !H_SYNC_POLARITY;
den <= 1'b0;
h_ctr <= {W_H_CTR{1'b0}};
h_state <= S_FRONT_PORCH;
v_advance <= 1'b0;
end else begin
h_ctr <= h_ctr - 1'b1;
v_advance <= h_state == S_ACTIVE && h_ctr == 1;
case (h_state)
S_FRONT_PORCH:
if (h_ctr == 0) begin
h_ctr <= H_SYNC_WIDTH - 1;
h_state <= S_SYNC;
hsync <= H_SYNC_POLARITY;
end
S_SYNC:
if (h_ctr == 0) begin
h_ctr <= H_BACK_PORCH - 1;
h_state <= S_BACK_PORCH;
hsync <= !H_SYNC_POLARITY;
end
S_BACK_PORCH:
if (h_ctr == 0) begin
h_ctr <= H_ACTIVE_PIXELS - 1;
h_state <= S_ACTIVE;
den <= in_active_vertical_period;
end
S_ACTIVE:
if (h_ctr == 0) begin
h_ctr <= H_FRONT_PORCH - 1;
h_state <= S_FRONT_PORCH;
den <= 1'b0;
end
endcase
end
end
// ----------------------------------------------------------------------------
// Vertical timing state machine
reg [W_V_CTR-1:0] v_ctr;
reg [W_STATE-1:0] v_state;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
v_state <= S_FRONT_PORCH;
v_ctr <= {W_V_CTR{1'b0}};
vsync <= !V_SYNC_POLARITY;
in_active_vertical_period <= 1'b0;
end else if (!en) begin
vsync <= !V_SYNC_POLARITY;
in_active_vertical_period <= 1'b0;
v_ctr <= {W_V_CTR{1'b0}};
v_state <= S_FRONT_PORCH;
end else if (v_advance) begin
v_ctr <= v_ctr - 1'b1;
case (v_state)
S_FRONT_PORCH:
if (v_ctr == 0) begin
v_ctr <= V_SYNC_WIDTH - 1;
v_state <= S_SYNC;
vsync <= V_SYNC_POLARITY;
end
S_SYNC:
if (v_ctr == 0) begin
v_ctr <= V_BACK_PORCH - 1;
v_state <= S_BACK_PORCH;
vsync <= !V_SYNC_POLARITY;
end
S_BACK_PORCH:
if (v_ctr == 0) begin
v_ctr <= V_ACTIVE_LINES - 1;
v_state <= S_ACTIVE;
in_active_vertical_period <= 1'b1;
end
S_ACTIVE:
if (v_ctr == 0) begin
v_ctr <= V_FRONT_PORCH - 1;
v_state <= S_FRONT_PORCH;
in_active_vertical_period <= 1'b0;
end
endcase
end
end
endmodule
| 9.973404 |
module smoldvi_tmds_encode (
input wire clk,
input wire rst_n,
input wire [1:0] c,
input wire [7:0] d,
input wire den,
output reg [9:0] q
);
reg [2:0] popcount;
wire low_balance = !popcount[2];
always @(*) begin : count_d_pop
integer i;
popcount = 3'd0;
// Ignore d[0] as it's implicitly masked
for (i = 1; i < 8; i = i + 1) popcount = popcount + {2'h0, d[i]};
end
reg [7:0] d_reduced;
reg symbol_is_second;
always @(*) begin : reduce_d
integer i;
d_reduced = 8'h0;
for (i = 1; i < 8; i = i + 1) d_reduced[i] = d_reduced[i-1] ^ d[i];
end
wire [9:0] pixel_q = {
!low_balance, low_balance, d_reduced ^ (8'h55 & {8{!low_balance}}) ^ {8{symbol_is_second}}
};
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
symbol_is_second <= 1'b0;
q <= 10'd0;
end else begin
if (den) begin
symbol_is_second <= !symbol_is_second;
q <= pixel_q;
end else begin
symbol_is_second <= 1'b0;
case (c)
2'b00: q <= 10'b1101010100;
2'b01: q <= 10'b0010101011;
2'b10: q <= 10'b0101010100;
2'b11: q <= 10'b1010101011;
endcase
end
end
end
endmodule
| 6.814431 |
module smoother #(
parameter HBLKS = 10,
parameter VBLKS = 10,
parameter SMOOTH_T = 1400
) (
input clk_i,
input rst_ni,
input [$clog2(HBLKS)-1:0] ht_cur_i,
input [$clog2(VBLKS)-1:0] vt_cur_i,
input [2:0] mode_i,
output reg [2:0] mode_o
);
localparam FANTASY = SMOOTH_T * 148500;
localparam PHASE = HBLKS / 2 + VBLKS / 2;
localparam FAN_PHASE_DIV = FANTASY / PHASE;
reg [$clog2(FAN_PHASE_DIV)-1:0] fc;
always @(posedge clk_i, negedge rst_ni) begin
if (~rst_ni) begin
fc <= 0;
end else if (fc < FAN_PHASE_DIV - 1) begin
fc <= fc + 1;
end else begin
fc <= 0;
end
end
reg [2:0] modes[0:PHASE-1];
genvar i;
generate
for (i = 0; i < PHASE; i = i + 1) begin : g
always @(posedge clk_i) begin
if (~|fc) begin
modes[i] <= i == 0 ? mode_i : modes[i-1];
end
end
end
endgenerate
wire [$clog2(
PHASE
)-1:0] h_rel = ht_cur_i < HBLKS / 2 ? HBLKS / 2 - ht_cur_i - 1 : ht_cur_i - HBLKS / 2;
wire [$clog2(
PHASE
)-1:0] v_rel = vt_cur_i < VBLKS / 2 ? VBLKS / 2 - vt_cur_i - 1 : vt_cur_i - VBLKS / 2;
reg [$clog2(PHASE)-1:0] rel_r;
always @(posedge clk_i, negedge rst_ni) begin
if (~rst_ni) begin
rel_r <= PHASE - 1;
end else begin
rel_r <= h_rel + v_rel;
end
end
reg [2:0] mode_rr;
always @(posedge clk_i) begin
{mode_rr, mode_o} <= {modes[rel_r], mode_rr};
end
endmodule
| 7.94992 |
module smpldbit_reg2 (
input wire clock,
input wire reset,
input wire [1:0] ctrl, // bittime fsm: smpldbit_reg_ctrl
output wire smpldbit, // MAC, destuff, biterrordetect
input wire puffer // edgepuffer: puffer
);
//tmrg default triplicate
//tmrg tmr_error false
reg smpldbit_i;
//triplication signals
wire smpldbit_iVoted = smpldbit_i;
assign smpldbit = smpldbit_iVoted;
always @(posedge clock, negedge reset) begin
if (reset == 1'b0) smpldbit_i <= 1'b1;
else begin
case (ctrl)
2'b01: smpldbit_i <= 1'b1; // rezessiv
2'b10: smpldbit_i <= puffer; // versp�tet
default: smpldbit_i <= smpldbit_iVoted;
endcase
end
end
endmodule
| 7.948356 |
module smplfir #(
// {{{
parameter IW = 15,
localparam OW = IW + 1
// }}}
) (
// {{{
input wire i_clk,
i_ce,
input wire [(IW-1):0] i_val,
output reg [(OW-1):0] o_val
// }}}
);
reg [(IW-1):0] delayed;
initial delayed = 0;
always @(posedge i_clk) if (i_ce) delayed <= i_val;
always @(posedge i_clk) if (i_ce) o_val <= i_val + delayed;
endmodule
| 7.04023 |
module BufferCC_5 (
input io_dataIn,
output io_dataOut,
input clocking_GCLK25,
input system_cores_1_debugReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clocking_GCLK25 or posedge system_cores_1_debugReset) begin
if (system_cores_1_debugReset) begin
buffers_0 <= 1'b1;
buffers_1 <= 1'b1;
end else begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
end
endmodule
| 6.82712 |
module BufferCC_4 (
input io_dataIn,
output io_dataOut,
input clocking_GCLK25,
input system_cores_0_debugReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clocking_GCLK25 or posedge system_cores_0_debugReset) begin
if (system_cores_0_debugReset) begin
buffers_0 <= 1'b1;
buffers_1 <= 1'b1;
end else begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
end
endmodule
| 6.634474 |
module BufferCC_3 (
input io_dataIn,
output io_dataOut,
input clocking_GCLK25,
input sdramCd_logic_outputReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clocking_GCLK25 or posedge sdramCd_logic_outputReset) begin
if (sdramCd_logic_outputReset) begin
buffers_0 <= 1'b1;
buffers_1 <= 1'b1;
end else begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
end
endmodule
| 6.792516 |
module FlowCCByToggle (
input io_input_valid,
input io_input_payload_last,
input [0:0] io_input_payload_fragment,
output io_output_valid,
output io_output_payload_last,
output [0:0] io_output_payload_fragment,
input tck,
input clocking_GCLK25,
input debugCd_logic_outputReset
);
wire inputArea_target_buffercc_io_dataOut;
wire outHitSignal;
reg inputArea_target = 0;
reg inputArea_data_last;
reg [0:0] inputArea_data_fragment;
wire outputArea_target;
reg outputArea_hit;
wire outputArea_flow_valid;
wire outputArea_flow_payload_last;
wire [0:0] outputArea_flow_payload_fragment;
reg outputArea_flow_regNext_valid;
reg outputArea_flow_regNext_payload_last;
reg [0:0] outputArea_flow_regNext_payload_fragment;
BufferCC inputArea_target_buffercc (
.io_dataIn (inputArea_target), //i
.io_dataOut (inputArea_target_buffercc_io_dataOut), //o
.clocking_GCLK25 (clocking_GCLK25), //i
.debugCd_logic_outputReset(debugCd_logic_outputReset) //i
);
assign outputArea_target = inputArea_target_buffercc_io_dataOut;
assign outputArea_flow_valid = (outputArea_target != outputArea_hit);
assign outputArea_flow_payload_last = inputArea_data_last;
assign outputArea_flow_payload_fragment = inputArea_data_fragment;
assign io_output_valid = outputArea_flow_regNext_valid;
assign io_output_payload_last = outputArea_flow_regNext_payload_last;
assign io_output_payload_fragment = outputArea_flow_regNext_payload_fragment;
always @(posedge tck) begin
if (io_input_valid) begin
inputArea_target <= (!inputArea_target);
inputArea_data_last <= io_input_payload_last;
inputArea_data_fragment <= io_input_payload_fragment;
end
end
always @(posedge clocking_GCLK25) begin
outputArea_hit <= outputArea_target;
outputArea_flow_regNext_payload_last <= outputArea_flow_payload_last;
outputArea_flow_regNext_payload_fragment <= outputArea_flow_payload_fragment;
end
always @(posedge clocking_GCLK25) begin
if (debugCd_logic_outputReset) begin
outputArea_flow_regNext_valid <= 1'b0;
end else begin
outputArea_flow_regNext_valid <= outputArea_flow_valid;
end
end
endmodule
| 7.790686 |
module BufferCC_1 (
input io_dataIn,
output io_dataOut,
input clocking_GCLK25,
input systemCd_logic_outputReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clocking_GCLK25) begin
if (systemCd_logic_outputReset) begin
buffers_0 <= 1'b0;
buffers_1 <= 1'b0;
end else begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
end
endmodule
| 6.574801 |
module BufferCC (
input io_dataIn,
output io_dataOut,
input clocking_GCLK25,
input debugCd_logic_outputReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clocking_GCLK25) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
| 6.712921 |
module SMPS_ZVS_Controller (
input clk,
input [23:0] SMPS_50V_VSense,
input [23:0] SMPS_50V_CSense,
output SMPS_Driver1,
output SMPS_Driver2,
output SMPS_Driver3,
output SMPS_Driver4
);
// Manages the SMPS Driver, VSense and CSense are useful for keeping a stable 50V value
// CSense allows to sense a large and sudden current draw to force the SMPS drivers to max out if over spec.
reg [7:0] DutyCycle; // 0 to 65535
reg CLK1, CLK2, CLK3, CLK4;
reg [7:0] phase; // main phase
reg [8:0] mainPhase1; // phase of first pwm
wire PWMCLK;
reg [7:0] phase2, phase4; // 180* phase out of sync
reg rst3, rst4;
initial begin
DutyCycle = 102; // enforced 40% Duty cycle
CLK1 = 0;
CLK2 = 0;
CLK3 = 0;
CLK4 = 0;
phase = 0; // primary phase that is calculated
phase2 = 255; // phase length is doubled due to CLK*2 (would be 127)
phase4 = 255;
rst3 = 0;
rst4 = 0;
mainPhase1 = 0;
end
defparam sc1.Divider = 4; // approx 5MHz
SubClock sc1 (
clk,
PWMCLK
);
PWMR p1 (
CLK1,
0,
DutyCycle,
SMPS_Driver1
); // 90kHz
PWMR p2 (
CLK2,
0,
DutyCycle,
SMPS_Driver2
); // 90kHz
PWMR p3 (
CLK3,
rst3,
DutyCycle,
SMPS_Driver3
); // 90kHz
PWMR p4 (
CLK4,
rst4,
DutyCycle,
SMPS_Driver4
); // 90kHz
always @(posedge PWMCLK) begin
// phase changes div=9 (8.7)
rst3 = 0;
rst4 = 0;
CLK1 = ~CLK1; // CLK1 is enforced
mainPhase1 = mainPhase1 + 1; // mainPhase used to sync other phases
// enforce CLK2 is 180* out of sync
if (phase2 == 0) begin
CLK2 = ~CLK2;
end
phase2 = (phase2 > 0) ? phase2 - 1 : 0;
// doubly enforce that the other phases are different
if (phase == 0) begin // phase complete
CLK3 = ~CLK3;
if (phase4 == 0) begin // phase complete
CLK4 = ~CLK4;
end else phase4 = (phase4 == 0) ? 255 : phase4;
phase4 = (phase4 > 0) ? phase4 - 1 : 0;
// recalculate phase difference
// reset PWM after mainPhase1 hits 0
if (mainPhase1 == 0) begin
// recalc
rst3 = 1;
rst4 = 1;
phase4 = 255;
// double 24-bit variables make the LUT expensive, better/easier to just calculate
// if over 50.5V, no duty
if (SMPS_50V_VSense < 12007693) begin
phase = ((SMPS_50V_VSense > SMPS_50V_CSense) ? // Find Max value
(SMPS_50V_VSense - SMPS_50V_CSense) : // find difference
(SMPS_50V_CSense - SMPS_50V_VSense)) >> 17; // 25-bit to 8-bit
end else phase = 0;
end
end else phase = (phase == 0) ? 255 : phase;
phase = (phase > 0) ? phase - 1 : 0;
end
endmodule
| 7.106035 |
module SMPTE274_tb ();
reg clk;
reg RST;
reg EN;
reg [9 : 0] i_data_Y, i_data_C;
wire [11 : 0] PIX_CNT_o;
wire [10 : 0] LINE_CNT_o;
wire [9 : 0] Y_data_o, C_data_o;
wire VSYNC_o;
wire HSYNC_o;
wire DATA_RQ_o;
integer data_file; // file handler
integer scan_file; // file handler
reg [9 : 0] captured_data;
`define NULL 0
SMPTE274 data (
.CLK_74M (clk),
.RST (RST),
.EN (EN),
.i_data_Y (i_data_Y),
.i_data_C (i_data_C),
.PIX_CNT_o (PIX_CNT_o),
.LINE_CNT_o(LINE_CNT_o),
.Y_data_o (Y_data_o),
.C_data_o (C_data_o),
.VSYNC_o (VSYNC_o),
.HSYNC_o (HSYNC_o),
.DATA_RQ_o (DATA_RQ_o)
);
initial begin
data_file = $fopen("out.dat", "r");
if (data_file == `NULL) begin
$display("data_file handle was NULL");
$finish;
end
#1 RST <= 1;
clk <= 0;
EN <= 0;
i_data_Y <= 10'h011;
i_data_C <= 10'h0CC;
#1 RST <= 0;
EN <= 1;
end
always begin
#1 clk = !clk;
end
always @(posedge clk) begin
if (DATA_RQ_o) scan_file = $fscanf(data_file, "%d\n", captured_data);
else captured_data <= 10'h000;
if (!$feof(data_file)) begin
i_data_Y <= captured_data;
end
end
endmodule
| 7.352572 |
module smpu_comp_hit (
biu_pad_haddr,
biu_pad_hprot,
smpu_entry,
smpu_entry0,
smpu_hit,
smpu_hsec
);
// &Ports; @20
input [31:0] biu_pad_haddr;
input [3 : 0] biu_pad_hprot;
input [31:0] smpu_entry;
input [31:0] smpu_entry0;
output smpu_hit;
output smpu_hsec;
// &Regs; @21
reg [ 22:0] addr_mask;
// &Wires; @22
wire addr_match;
wire [ 31:0] biu_pad_haddr;
wire [3 : 0] biu_pad_hprot;
wire [ 31:0] smpu_entry;
wire [ 31:0] smpu_entry0;
wire smpu_hit;
wire smpu_hsec;
// &Force("bus", "biu_pad_haddr", 31, 0); @25
// &Force("bus", "biu_pad_hprot", 3, 0); @26
assign smpu_hit = 1'b0;
// &Force("nonport", "addr_match"); @32
assign addr_match = {(smpu_entry[0] & !biu_pad_hprot[2]),
(addr_mask[22:0] & biu_pad_haddr[31:9])}
== { 1'b1, smpu_entry[31:9]};
assign smpu_hsec = {(smpu_entry0[0] & biu_pad_hprot[2]),
(addr_mask[22:0] & biu_pad_haddr[31:9])}
== { 1'b1, smpu_entry0[31:9]};
//Generate the address mask for the addr
// &CombBeg; @44
always @(smpu_entry[4:1]) begin
case (smpu_entry[4:1])
4'b0111: addr_mask[22:0] = 23'h7f_ffff;
4'b1000: addr_mask[22:0] = 23'h7f_fffe;
4'b1001: addr_mask[22:0] = 23'h7f_fffc;
default: addr_mask[22:0] = 23'h00_0000;
endcase
// &CombEnd; @51
end
// &ModuleEnd; @54
endmodule
| 6.583609 |
module sms_sram_bk2 (
hrst_b,
ram_addr,
ram_clk,
ram_rdata,
ram_sel,
ram_size,
ram_wdata,
ram_write
);
input hrst_b;
input [15:0] ram_addr;
input ram_clk;
input ram_sel;
input [2 : 0] ram_size;
input [31:0] ram_wdata;
input ram_write;
output [31:0] ram_rdata;
reg [3 : 0] byte_sel_b;
reg mbk_cen_f_b;
reg [ 31:0] ram_rdata;
wire [3 : 0] byte_wen_b;
wire hrst_b;
wire mbk_cen_b;
wire mbk_wen_b;
wire [ 31:0] ram0_rdata;
wire [ 15:0] ram_addr;
wire ram_clk;
wire ram_sel;
wire [2 : 0] ram_size;
wire [ 31:0] ram_wdata;
wire ram_write;
parameter [2:0] BYTE = 3'b000, HALFWORD = 3'b001, WORD = 3'b010;
assign mbk_cen_b = ~ram_sel;
always @(ram_addr[1:0] or ram_size[2:0]) begin
case (ram_size[2:0]) // synopsys parallel_case
BYTE:
case (ram_addr[1:0]) // synopsys parallel_case
2'b00: byte_sel_b[3:0] = 4'b1110;
2'b01: byte_sel_b[3:0] = 4'b1101;
2'b10: byte_sel_b[3:0] = 4'b1011;
2'b11: byte_sel_b[3:0] = 4'b0111;
endcase
HALFWORD:
case (ram_addr[1]) // synopsys parallel_case
1'b0: byte_sel_b[3:0] = 4'b1100;
1'b1: byte_sel_b[3:0] = 4'b0011;
endcase
WORD: byte_sel_b[3:0] = 4'b0000;
default: byte_sel_b[3:0] = 4'b1111;
endcase
end
assign mbk_wen_b = ~ram_write;
always @(posedge ram_clk or negedge hrst_b) begin
if (!hrst_b) mbk_cen_f_b <= 1'b0;
else mbk_cen_f_b <= mbk_cen_b;
end
always @(mbk_cen_f_b or ram0_rdata[31:0]) begin
case (mbk_cen_f_b)
1'b0: ram_rdata[31:0] = ram0_rdata[31:0];
1'b1: ram_rdata[31:0] = 32'b0;
endcase
end
parameter DATAWIDTH = 32;
parameter ADDRWIDTH = 14;
parameter MEMDEPTH = 2 ** (ADDRWIDTH);
assign byte_wen_b[3:0] = byte_sel_b[3:0] | {4{mbk_wen_b}};
fpga_spram #(DATAWIDTH, ADDRWIDTH, MEMDEPTH) x_fpga_spram (
.A (ram_addr[15:2]),
.BWEN(byte_wen_b[3:0]),
.CEN (mbk_cen_b),
.CLK (ram_clk),
.D (ram_wdata[31:0]),
.Q (ram0_rdata[31:0])
);
endmodule
| 6.953215 |
module SMScheduler (
input reset,
input clk,
input stall_i,
input [`SIZE_SM_LOG-1:0] nSM_i, //allowed SM number
//input [`SIZE_SM-1:0] SMEnMask_i, //follow "nSM_i"
input [`SIZE_GRAN-1:0] granu_i,
input swapDone_i,
//notBraRcv
input branch_i,
input issuedbranch_i,
input reconv_i,
//notLdSt
input lsuStallFront_i,
input frontendLdSt_i,
input issuedLdSt_i,
input fuLdSt_i,
input aguLdSt_i,
output [`SIZE_SM_LOG-1:0] sm_o,
output reg stallRun_o
);
reg [`SIZE_SM_LOG-1:0] sm;
reg [`SIZE_GRAN-1:0] cycCnt;
wire notBraRcv;
wire notLdSt;
assign notBraRcv = ~reconv_i && ~issuedbranch_i && ~branch_i;
assign notLdSt = lsuStallFront_i ? (~issuedLdSt_i && ~fuLdSt_i && ~aguLdSt_i) : (~frontendLdSt_i && ~issuedLdSt_i && ~fuLdSt_i);
assign sm_o = sm;
always @(posedge clk) begin
if (reset) begin
sm <= 0;
cycCnt <= 0;
end else begin
if (~stall_i) begin
if (cycCnt < granu_i) begin
stallRun_o <= 1'b0;
cycCnt <= cycCnt + 1;
end else begin
if (notBraRcv && notLdSt) begin //satisfy shifting condition
if (swapDone_i) begin
stallRun_o <= 1'b0;
cycCnt <= 0;
if (sm == nSM_i) sm <= 0;
else sm <= sm + 1;
end else if (~swapDone_i) begin
stallRun_o <= 1'b1;
end
end
end
end
end
end
endmodule
| 6.716861 |
module sms_sram_1M_bk2 (
hrst_b,
ram_addr,
ram_clk,
ram_rdata,
ram_sel,
ram_size,
ram_wdata,
ram_write
);
input hrst_b;
input [31:0] ram_addr;
input ram_clk;
input ram_sel;
input [2 : 0] ram_size;
input [31:0] ram_wdata;
input ram_write;
output [31:0] ram_rdata;
reg [3 : 0] byte_sel_b;
reg mbk_cen_f_b;
reg [ 31:0] ram_rdata;
wire [3 : 0] byte_wen_b;
wire hrst_b;
wire mbk_cen_b;
wire mbk_wen_b;
wire [ 31:0] ram0_rdata;
wire [ 31:0] ram_addr;
wire ram_clk;
wire ram_sel;
wire [2 : 0] ram_size;
wire [ 31:0] ram_wdata;
wire ram_write;
parameter [2:0] BYTE = 3'b000, HALFWORD = 3'b001, WORD = 3'b010;
assign mbk_cen_b = ~ram_sel;
always @(ram_addr[1:0] or ram_size[2:0]) begin
case (ram_size[2:0]) // synopsys parallel_case
BYTE:
case (ram_addr[1:0]) // synopsys parallel_case
2'b00: byte_sel_b[3:0] = 4'b1110;
2'b01: byte_sel_b[3:0] = 4'b1101;
2'b10: byte_sel_b[3:0] = 4'b1011;
2'b11: byte_sel_b[3:0] = 4'b0111;
endcase
HALFWORD:
case (ram_addr[1]) // synopsys parallel_case
1'b0: byte_sel_b[3:0] = 4'b1100;
1'b1: byte_sel_b[3:0] = 4'b0011;
endcase
WORD: byte_sel_b[3:0] = 4'b0000;
default: byte_sel_b[3:0] = 4'b1111;
endcase
end
assign mbk_wen_b = ~ram_write;
always @(posedge ram_clk or negedge hrst_b) begin
if (!hrst_b) mbk_cen_f_b <= 1'b0;
else mbk_cen_f_b <= mbk_cen_b;
end
always @(mbk_cen_f_b or ram0_rdata[31:0]) begin
case (mbk_cen_f_b)
1'b0: ram_rdata[31:0] = ram0_rdata[31:0];
1'b1: ram_rdata[31:0] = 32'b0;
endcase
end
parameter DATAWIDTH = 32;
parameter ADDRWIDTH = 18;
parameter MEMDEPTH = 2 ** (ADDRWIDTH);
assign byte_wen_b[3:0] = byte_sel_b[3:0] | {4{mbk_wen_b}};
fpga_spram #(DATAWIDTH, ADDRWIDTH, MEMDEPTH) x_fpga_spram (
.A (ram_addr[19:2]),
.BWEN(byte_wen_b[3:0]),
.CEN (mbk_cen_b),
.CLK (ram_clk),
.D (ram_wdata[31:0]),
.Q (ram0_rdata[31:0])
);
endmodule
| 6.741091 |
module CrossBarCell (
input [63:0] io_fw_left,
input [63:0] io_fw_top,
output [63:0] io_fw_bottom,
output [63:0] io_fw_right,
input io_sel
);
assign io_fw_bottom = io_sel ? io_fw_left : io_fw_top; // @[CrossBarSwitch.scala 15:17 CrossBarSwitch.scala 16:18 CrossBarSwitch.scala 18:18]
assign io_fw_right = io_fw_left; // @[CrossBarSwitch.scala 14:15]
endmodule
| 7.603405 |
module CLOScell4 (
input clock,
input [63:0] io_in4_0,
input [63:0] io_in4_1,
input [63:0] io_in4_2,
input [63:0] io_in4_3,
output [63:0] io_out4_0,
output [63:0] io_out4_1,
output [63:0] io_out4_2,
output [63:0] io_out4_3,
input [ 7:0] io_ctrl
);
wire CrossBarSwitch_clock; // @[BuildingBlock.scala 17:21]
wire [63:0] CrossBarSwitch_io_fw_left_0; // @[BuildingBlock.scala 17:21]
wire [63:0] CrossBarSwitch_io_fw_left_1; // @[BuildingBlock.scala 17:21]
wire [63:0] CrossBarSwitch_io_fw_left_2; // @[BuildingBlock.scala 17:21]
wire [63:0] CrossBarSwitch_io_fw_left_3; // @[BuildingBlock.scala 17:21]
wire [63:0] CrossBarSwitch_io_fw_bottom_0; // @[BuildingBlock.scala 17:21]
wire [63:0] CrossBarSwitch_io_fw_bottom_1; // @[BuildingBlock.scala 17:21]
wire [63:0] CrossBarSwitch_io_fw_bottom_2; // @[BuildingBlock.scala 17:21]
wire [63:0] CrossBarSwitch_io_fw_bottom_3; // @[BuildingBlock.scala 17:21]
wire [1:0] CrossBarSwitch_io_select_0; // @[BuildingBlock.scala 17:21]
wire [1:0] CrossBarSwitch_io_select_1; // @[BuildingBlock.scala 17:21]
wire [1:0] CrossBarSwitch_io_select_2; // @[BuildingBlock.scala 17:21]
wire [1:0] CrossBarSwitch_io_select_3; // @[BuildingBlock.scala 17:21]
CrossBarSwitch CrossBarSwitch ( // @[BuildingBlock.scala 17:21]
.clock(CrossBarSwitch_clock),
.io_fw_left_0(CrossBarSwitch_io_fw_left_0),
.io_fw_left_1(CrossBarSwitch_io_fw_left_1),
.io_fw_left_2(CrossBarSwitch_io_fw_left_2),
.io_fw_left_3(CrossBarSwitch_io_fw_left_3),
.io_fw_bottom_0(CrossBarSwitch_io_fw_bottom_0),
.io_fw_bottom_1(CrossBarSwitch_io_fw_bottom_1),
.io_fw_bottom_2(CrossBarSwitch_io_fw_bottom_2),
.io_fw_bottom_3(CrossBarSwitch_io_fw_bottom_3),
.io_select_0(CrossBarSwitch_io_select_0),
.io_select_1(CrossBarSwitch_io_select_1),
.io_select_2(CrossBarSwitch_io_select_2),
.io_select_3(CrossBarSwitch_io_select_3)
);
assign io_out4_0 = CrossBarSwitch_io_fw_bottom_0; // @[BuildingBlock.scala 22:11]
assign io_out4_1 = CrossBarSwitch_io_fw_bottom_1; // @[BuildingBlock.scala 22:11]
assign io_out4_2 = CrossBarSwitch_io_fw_bottom_2; // @[BuildingBlock.scala 22:11]
assign io_out4_3 = CrossBarSwitch_io_fw_bottom_3; // @[BuildingBlock.scala 22:11]
assign CrossBarSwitch_clock = clock;
assign CrossBarSwitch_io_fw_left_0 = io_in4_0; // @[BuildingBlock.scala 21:17]
assign CrossBarSwitch_io_fw_left_1 = io_in4_1; // @[BuildingBlock.scala 21:17]
assign CrossBarSwitch_io_fw_left_2 = io_in4_2; // @[BuildingBlock.scala 21:17]
assign CrossBarSwitch_io_fw_left_3 = io_in4_3; // @[BuildingBlock.scala 21:17]
assign CrossBarSwitch_io_select_0 = io_ctrl[7:6]; // @[BuildingBlock.scala 19:31]
assign CrossBarSwitch_io_select_1 = io_ctrl[5:4]; // @[BuildingBlock.scala 19:31]
assign CrossBarSwitch_io_select_2 = io_ctrl[3:2]; // @[BuildingBlock.scala 19:31]
assign CrossBarSwitch_io_select_3 = io_ctrl[1:0]; // @[BuildingBlock.scala 19:31]
endmodule
| 7.132057 |
module smToTc #(
parameter DW = 8
) (
input [DW-1:0] a,
output [DW-1:0] w
);
wire [DW-2:0] mag;
wire [DW-1:0] temp;
wire sign;
assign sign = a[DW-1];
assign mag = a[DW-2:0];
assign temp = {1'b0, mag};
assign w = (sign) ? (~temp + 1'b1) : temp;
endmodule
| 6.616318 |
module SMULT16_ser4 (
output reg [255:0] product,
output V,
input [15:0] scalar,
input [255:0] vecin,
input start,
output reg done,
input clk1,
input clk2
);
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;
reg [15:0] Ov;
wire [3:0] Overpart;
wire [63:0] Prodpart;
reg donev;
reg [3:0] ovfl;
reg [2:0] state, nextstate;
reg [63:0] prod;
reg [63:0] In1, In2;
assign V = Ov;
//assign done = donev;
SMUL MUL1 (
Prodpart[15:0],
Overpart[0],
In1[15:0],
In2[15:0]
);
SMUL MUL2 (
Prodpart[31:16],
Overpart[1],
In1[31:16],
In2[31:16]
);
SMUL MUL3 (
Prodpart[47:32],
Overpart[2],
In1[47:32],
In2[47:32]
);
SMUL MUL4 (
Prodpart[63:48],
Overpart[3],
In1[63:48],
In2[63:48]
);
always @(posedge clk2) begin
if (start == 1'b0) begin
state <= S0;
prod <= 64'h0;
ovfl <= 4'h0;
end else begin
state <= nextstate;
prod <= Prodpart;
ovfl <= Overpart;
end
end
always @(state) begin
case (state)
S0: begin
In1 = vecin[63:0];
In2 = {scalar, scalar, scalar, scalar};
product = 0;
Ov = 0;
nextstate = S1;
end
S1: begin
In1 = vecin[127:64];
In2 = {scalar, scalar, scalar, scalar};
product[63:0] = prod;
Ov[3:0] = ovfl;
nextstate = S2;
end
S2: begin
In1 = vecin[191:128];
In2 = {scalar, scalar, scalar, scalar};
product[127:64] = prod;
Ov[7:4] = ovfl;
nextstate = S3;
end
S3: begin
In1 = vecin[255:192];
In2 = {scalar, scalar, scalar, scalar};
product[191:128] = prod;
Ov[11:8] = ovfl;
nextstate = S4;
donev = 1'b0;
end
S4: begin
In1 = vecin[255:192];
In2 = scalar;
product[255:192] = prod;
Ov[15:11] = ovfl;
nextstate = S0;
end
endcase
end
always @(posedge clk1) begin
if (state == 3'b100) done <= 1'b1;
else done <= 1'b0;
end
endmodule
| 6.599763 |
module SMULT16_ser8 (
output reg [255:0] product,
output V,
input [15:0] scalar,
input [255:0] vecin,
input start,
output reg done,
input clk1,
input clk2
);
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;
reg [15:0] Ov;
wire [7:0] Overpart;
wire [127:0] Prodpart;
reg donev;
reg [7:0] ovfl;
reg [1:0] state, nextstate;
reg [127:0] prod;
reg [127:0] In1, In2;
assign V = Ov;
//assign done = donev;
SMUL MUL1 (
Prodpart[15:0],
Overpart[0],
In1[15:0],
In2[15:0]
);
SMUL MUL2 (
Prodpart[31:16],
Overpart[1],
In1[31:16],
In2[31:16]
);
SMUL MUL3 (
Prodpart[47:32],
Overpart[2],
In1[47:32],
In2[47:32]
);
SMUL MUL4 (
Prodpart[63:48],
Overpart[3],
In1[63:48],
In2[63:48]
);
SMUL MUL5 (
Prodpart[79:64],
Overpart[0],
In1[79:64],
In2[79:64]
);
SMUL MUL6 (
Prodpart[95:80],
Overpart[1],
In1[95:80],
In2[95:80]
);
SMUL MUL7 (
Prodpart[111:96],
Overpart[2],
In1[111:96],
In2[111:96]
);
SMUL MUL8 (
Prodpart[127:112],
Overpart[3],
In1[127:112],
In2[127:112]
);
always @(posedge clk2) begin
if (start == 1'b0) begin
state <= S0;
prod <= 64'h0;
ovfl <= 4'h0;
end else begin
state <= nextstate;
prod <= Prodpart;
ovfl <= Overpart;
end
end
always @(state) begin
case (state)
S0: begin
In1 = vecin[127:0];
In2 = {scalar, scalar, scalar, scalar};
product = 0;
Ov = 0;
nextstate = S1;
end
S1: begin
In1 = vecin[255:128];
In2 = {scalar, scalar, scalar, scalar};
product[63:0] = prod;
Ov[7:0] = ovfl;
nextstate = S2;
end
S2: begin
In1 = vecin[255:128];
In2 = {scalar, scalar, scalar, scalar};
product[255:128] = prod;
Ov[15:8] = ovfl;
nextstate = S0;
end
endcase
end
always @(posedge clk1) begin
if (state == 2'b10) done <= 1'b1;
else done <= 1'b0;
end
endmodule
| 6.840863 |
module SMULT16 (
output [255:0] product,
output V,
input [15:0] scalar,
input [255:0] vecin,
input start,
output done
);
wire [15:0] Ov;
assign V = Ov[0] | Ov[1] | Ov[2] | Ov[3] | Ov[4] | Ov[5] | Ov[6] |
Ov[7] | Ov[8] | Ov[9] | Ov[10] | Ov[11] | Ov[12] | Ov[13] | Ov[14]|Ov[15];
assign done = start; //this module finishes operation in one cycle
VMULT mult[15:0] (
.product(product),
.Overflow(Ov[15:0]),
.A(scalar),
.B(vecin)
);
endmodule
| 6.714901 |
module SMULT16p (
output [255:0] product,
output V,
input Clk1,
input Clk2,
input [15:0] scalar,
input [255:0] vecin,
input start,
output reg done
);
reg [ 1:0] state;
wire [15:0] Ov;
assign V = Ov[0] | Ov[1] | Ov[2] | Ov[3] | Ov[4] | Ov[5] | Ov[6] |
Ov[7] | Ov[8] | Ov[9] | Ov[10] | Ov[11] | Ov[12] | Ov[13] | Ov[14]|Ov[15];
VMULTp mult[15:0] (
.product(product),
.Overflow(Ov[15:0]),
.Clk2(Clk2),
.A(scalar),
.B(vecin)
);
always @(posedge Clk1) begin
if (state == 2'b10) done <= 1'b1;
else done <= 1'b0;
end
always @(posedge Clk2) begin
if (start) begin
if (state == 2'b10) begin
state <= state;
end else begin
state <= state + 1;
end
end else begin
state <= 2'b00;
end
end //state machine always
endmodule
| 6.982493 |
module SMULT16ser (
output reg [15:0] product,
output reg V,
input Clk1,
input Clk2,
input [15:0] scalar,
input [15:0] vecin,
input start,
output reg write,
output reg done
);
wire Ov;
wire [15:0] element;
reg [4:0] state;
VMULT mult (
.product(element),
.Overflow(Ov),
.A(scalar),
.B(vecin)
);
always @(posedge Clk1) begin
case (state)
5'b10000: begin
done <= 1'b1;
write <= write;
end
5'b00001: begin
done <= done;
write <= 1'b1;
end
5'b00000: begin
done <= 1'b0;
write <= 1'b0;
end
default: begin
done <= done;
write <= write;
end
endcase
end
always @(posedge Clk2) begin
product <= element;
if (start) begin
V <= Ov | V;
if (state == 5'b10000) begin
state <= state;
end else begin
state <= state + 1;
end
end else begin
state <= 5'b00000;
V <= 1'b0;
end
end //always
endmodule
| 6.535417 |
module SMULT16serp (
output reg [15:0] product,
output reg V,
input Clk1,
input Clk2,
input [15:0] scalar,
input [15:0] vecin,
input start,
output reg write,
output reg done
);
wire Ov;
wire [15:0] element;
reg [4:0] state;
VMULTp mult (
.product(element),
.Overflow(Ov),
.A(scalar),
.B(vecin),
.Clk2(Clk2)
);
always @(posedge Clk1) begin
case (state)
5'b11111: begin
done <= 1'b1;
write <= write;
end
5'b00010: begin
done <= done;
write <= 1'b1;
end
5'b00000: begin
done <= 1'b0;
write <= 1'b0;
end
default: begin
done <= done;
write <= write;
end
endcase
end
always @(posedge Clk2) begin
product <= element;
if (start) begin
if (state == 5'b00000) begin
V <= V;
state <= state + 1;
end else if (state == 5'b11111) begin
state <= state;
V <= Ov | V;
end else begin
state <= state + 1;
V <= Ov | V;
end
end else begin
state <= 5'b00000;
V <= 1'b0;
end
end //always
endmodule
| 6.757078 |
module sMult_pipe #(
parameter WI1 = 4, //length of the integer part, operand 1
WF1 = 3, //length of the fraction part, operand 1
WI2 = 2, //length of the integer part, operand 2
WF2 = 5, //length of the fraction part, operand 2
//WIR = 6, //the length for the integer part of the required output
//WFR = 8, //the length of the fraction part of the required output
WIO = 4,
WFO = 15 //(WIR==1)?(WFR-1):WFR
) (
input CLK,
RST,
input signed [WI1+WF1-1 : 0] in1,
input signed [WI2+WF2-1 : 0] in2,
output reg signed [WIO+WFO-1 : 0] out
);
localparam intL = WI1 + WI2; //integer length of correct results
localparam frcL = WF1 + WF2; //fraction length of correct results
reg signed [intL+frcL-1 : 0] tmp; //The output with correct number of bits
reg [WIO-1 : 0] outI; //The integer part of the output
reg [WFO-1 : 0] outF; //The fractional part of the output
//assign tmp = in1 * in2;
always @(posedge CLK) tmp <= in1 * in2;
//--------------------adjusting the bitwidth for the fractional part----------------------------------------------------------
always @(posedge CLK) begin
if (WFO >= frcL) //append 0s to the lsb bits
outF <= {tmp[frcL-1:0], {(WFO - frcL) {1'b0}}};
else //WFO<(WF1+WF2): Truncate bits from the LSB bits
outF <= tmp[frcL-1 : frcL-WFO];
end
//----------------------------------------------------------------------------------------------------------------------------
//--------------------adjusting the bitwidth for the integer part-------------------------------------------------------------
always @(posedge CLK) begin
if (WIO >= intL) //sign extend the integer part
outI <= {{(WIO - intL) {tmp[intL+frcL-1]}}, tmp[intL+frcL-1:frcL]};
else begin //WIO<(WI1+WI2)
if (WIO == 1) outI <= tmp[intL+frcL-1];
else outI <= {tmp[intL+frcL-1], tmp[`X_trc:frcL]};
end
end
//----------------------------------------------------------------------------------------------------------------------------
//--------------------registering the output----------------------------------------------------------------------------------
always @* //(posedge CLK) //if wanna a registered multiplier decommented
if (!RST) out <= 0; //negative reset
else out <= {outI[WIO-1:0], outF[WFO-1:0]};
endmodule
| 7.290757 |
module smux (
input a,
input b,
input sel,
output out
);
assign out = (a & sel) | (b & (~sel));
endmodule
| 7.179673 |
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