code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module comp6_30 (
operand1,
operand2,
result,
signbit
);
input [5:0] operand1;
input [29:0] operand2;
input signbit;
output result;
wire gr;
comp_gr_6 comparator (
.gr (gr),
.in1(operand2[5:0]),
.in2(operand1)
);
// whenever operand2 is +ve and if any of bits [29:6... | 6.661777 |
module comp30_6 (
operand1,
operand2,
signbit,
result
);
input [29:0] operand1;
input [5:0] operand2;
input signbit;
output result;
wire gr;
comp_gr_6 comparator (
.gr (gr),
.in1(operand2),
.in2(operand1[5:0])
);
assign result = (signbit || ((~|(operand1[29:6])) &&... | 6.919514 |
module comp3_30 (
operand1,
operand2,
signbit,
result
);
input [2:0] operand1;
input [29:0] operand2;
input signbit;
output result;
wire less;
less_comp3 comparator (
.less(less),
.in1 (operand2[2:0]),
.in2 (operand1)
);
assign result = (signbit || ((~|operand2[29... | 7.171378 |
module less_comp3 (
in1,
in2,
less
);
input [2:0] in1;
input [2:0] in2;
output less;
assign less = (in1 < in2);
endmodule
| 6.705926 |
module sub2_32 (
result,
operand1,
operand2,
und_flw_bit
);
output [31:0] result;
output und_flw_bit;
input [31:0] operand1;
input [31:0] operand2;
wire c_out;
// since we already have adders, we would like to
// perform subtraction using adders
cla_adder_32 adder (
.in1 (oper... | 7.082705 |
module sm_0535UART_TRANSMITTER (
input CLOCK, //Clock input
input TX_DATA_VALID, //Input Bitstream
input [7:0] TX_BYTE,
output O_TX_SERIAL,
output O_TX_DONE
);
// different states
parameter IDLE = 3'b000,
TX_START_BIT = 3'b001,
TX_DATA_BITS = 3'b... | 6.872988 |
module sm_0535_colour_sensor_detection (
output S0,
output S1,
output S2,
output S3,
input signal,
output [2:0] color,
input clk
);
reg r_S0 = 0;
reg r_S1 = 1;
reg [1:0] r_color = 2'b00;
reg [6:0] r_red;
reg [6:0] r_blue;
reg [6:0] r_green;
reg [12:0] clk_counter = 0;
reg [... | 6.648214 |
module sm_0535_Line_follower (
input clk_adc,
clk_sm_bot,
input dout_adc,
output chip_select_adc,
din_adc,
clk_mod_adc,
output pwm_A1_A,
output pwm_A1_B,
output pwm_B1_A,
output pwm_B1_B,
output [1:0] Unit_at
);
wire [2:0] w_adc_data;
sm_0535_ADC_CONVERT line_sensor (
... | 6.997369 |
module sm_0535_SM_TOTALL (
// line_follow ports
input clk_adc,
clk_sm_bot,
clk_pwm,
input dout_adc,
output chip_select_adc,
din_adc,
clk_mod_adc,
output pwm_A1_A,
output pwm_A1_B,
output pwm_B1_A,
output pwm_B1_B,
output [3:0] z_current_node,
output [2:0] z_cu... | 7.058406 |
module sm_0535_UART_Receiver
// clocks per bit = freq. of clock / freq. of UART i.e., 25000000/115200 = 217
(
input CLOCK,
input i_RX_Serial,
output [7:0] o_RX_Byte
);
parameter IDLE = 3'b000,
RX_START_BIT = 3'b001,
RX_DATA_BITS = 3'b010,
RX_STOP_BIT = 3'b011,
CLEANUP ... | 6.724117 |
module sm_1p (
input clk,
reset,
x,
output reg y
);
reg [1:0] state;
parameter [1:0] S0 = 2'd0, S1 = 2'd1, S2 = 2'd2, S3 = 2'd3;
always @(posedge clk)
if (!reset) state <= 0;
else begin
case (state)
S0: begin
y <= 0;
if (x) state = S1;
else state... | 6.698469 |
module sm_21 (
input wire Zero,
input wire [1:0] Mem1,
output reg [1:0] PcCtrl1
);
always @(*) begin
case (Mem1)
2'b00: PcCtrl1 <= 3; // must jump
2'b01: begin // jump when != 0
if (Zero != 0) begin
PcCtrl1 <= 3;
end else begin
PcCtrl1 <= 1;
e... | 7.529134 |
module sm_2p (
input clk,
reset,
x,
output reg y
);
reg [1:0] state;
parameter [1:0] S0 = 2'd0, S1 = 2'd1, S2 = 2'd2, S3 = 2'd3;
always @(posedge clk)
if (!reset) state <= 0;
else begin
case (state)
S0: if (x) state = S1;
else state = S0;
S1: if (x) state = S2;
else... | 6.534643 |
module sm_add_test (
input wire clk,
input wire [1:0] btn,
input wire [7:0] sw,
output wire [3:0] an,
output wire [7:0] sseg
);
// signal declaration
wire [3:0] sum, mout, oct;
wire [7:0] led0, led1, led2, led3;
// instance of adder
sign_mag_add #(
.N(4)
) sm_adder_unit ... | 8.152652 |
module sm_ahb_master (
input clk,
input rst_n,
input [31:0] a, // address
input we, // write enable
input [31:0] wd, // write data
input valid, // read/write request
output ready, // read/write done
output [31:0] rd, // read data
output ... | 6.650792 |
module multi_ro (
output reg CHSEL,
output reg WR_EN,
input wire CLK,
input wire DAVAIL,
input wire RST
);
// state bits
parameter IDLE_BIT = 0, CH_SELECT_BIT = 1, READOUT_BIT = 2, WRITE_HEADER_BIT = 3;
parameter
IDLE = 4'b1<<IDLE_BIT,
CH_SELECT = 4'b1<<CH_SELECT_BIT,
... | 6.969485 |
module sm_clk_divider #(
parameter shift = 16,
bypass = 0
) (
input clkIn,
input rst_n,
input [3:0] devide,
input enable,
output clkOut
);
reg [39:0] cntr;
wire [39:0] cntrNext = cntr + 1;
//sm_register_we r_cntr(clkIn, rst_n, enable, cntrNext, cntr);
alw... | 7.194941 |
module sm_alu (
input [31:0] srcA,
input [31:0] srcB,
input [ 2:0] oper,
input [ 4:0] shift,
output zero,
output reg [31:0] result
);
always @(*) begin
case (oper)
default: result = srcA + srcB;
`ALU_ADD: result = srcA + srcB;
`ALU_OR: ... | 7.120672 |
module sm_register_file (
input clk,
input [ 4:0] a0,
input [ 4:0] a1,
input [ 4:0] a2,
input [ 4:0] a3,
output [31:0] rd0,
output [31:0] rd1,
output [31:0] rd2,
input [31:0] wd3,
input we3
);
reg [31:0] rf[31:0];
assign rd0 = (a0 != 0) ? rf[a0] : 32'b0;... | 7.126393 |
module sm_control (
input [5:0] cmdOper,
input [5:0] cmdFunk,
input aluZero,
output pcSrc,
output regDst,
output regWrite,
output aluSrc,
output [2:0] aluControl
);
wire branch;
wire condZero;
assign pcSrc = branch & (aluZero == condZero);
// cmd... | 7.251592 |
module sm_alu (
input [31:0] srcA,
input [31:0] srcB,
input [ 2:0] oper,
input [ 4:0] shift,
output zero,
output reg [31:0] result
);
localparam ALU_ADD = 3'b000,
ALU_OR = 3'b001,
ALU_LUI = 3'b010,
ALU_SRL = 3'b01... | 7.120672 |
module sm_register_file (
input clk,
input [ 4:0] a0,
input [ 4:0] a1,
input [ 4:0] a2,
input [ 4:0] a3,
output [31:0] rd0,
output [31:0] rd1,
output [31:0] rd2,
input [31:0] wd3,
input we3
);
reg [31:0] rf[31:0];
assign rd0 = (a0 != 0) ? rf[a0] : 32'b0... | 7.126393 |
module sm_fifoRTL (
wrClk,
rdClk,
rstSyncToWrClk,
rstSyncToRdClk,
dataIn,
dataOut,
fifoWEn,
fifoREn,
fifoFull,
fifoEmpty,
forceEmptySyncToWrClk,
forceEmptySyncToRdClk,
numElementsInFifo
);
//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
parameter FIFO_WIDTH = 8;... | 7.980621 |
module sm_gpio (
//bus side
input clk,
input rst_n,
input bSel,
input [31:0] bAddr,
input bWrite,
input [31:0] bWData,
output reg [31:0] bRData,
//pin side
input [`SM_GPIO_WIDTH - 1:0] gpioInput,
output [`SM_GPIO_WID... | 6.836966 |
module sm_hex_display (
input [3:0] digit,
output reg [6:0] seven_segments
);
always @*
case (digit)
'h0: seven_segments = 'b1000000; // g f e d c b a
'h1: seven_segments = 'b1111001;
'h2: seven_segments = 'b0100100; // --a--
'h3: seven_segments = 'b0110000; // | |
... | 7.448726 |
module sm_hex_display_8 (
input clock,
input resetn,
input [31:0] number,
output reg [6:0] seven_segments,
output reg dot,
output reg [7:0] anodes
);
function [6:0] bcd_to_seg(input [3:0] bcd);
case (bcd)
'h0: bcd_to_seg = 'b1000000; // g f e d c b a
'h1... | 7.448726 |
module sm_matrix (
//bus side
input clk,
input rst_n,
input [31:0] bAddr, // bus address
input bWrite, // bus write enable
input [31:0] bWData, // bus write data
output [31:0] bRData, // bus read data
//pin side
input [`SM_GPIO_WIDTH - 1:0] gpioI... | 6.69617 |
module sm_matrix_decoder (
input [31:0] bAddr,
output [ 5:0] bSel
);
// Decode based on most significant bits of the address
// RAM 0x00000000 - 0x00003fff
assign bSel[0] = (bAddr[15:14] == `SM_RAM_ADDR_MATCH);
// GPIO 0x00007f00 - 0x00007f0f
assign bSel[1] = (bAddr[15:4] == `SM_GPIO_ADDR_MATCH);... | 6.658731 |
module sm_matrix_mux (
input [5:0] bSel,
output reg [31:0] out,
input [31:0] in0,
input [31:0] in1,
input [31:0] in2,
input [31:0] in3,
input [31:0] in4,
input [31:0] in5
);
always @*
casez (bSel)
default: out = in0;
6'b?????1: out = in0;
6'b????10: out = in1;
... | 7.055001 |
module sm_para_1 (
nrst,
clk,
i1,
i2,
o1,
o2,
err
);
input nrst;
input clk;
input i1;
input i2;
output o1;
output o2;
output err;
reg o1;
reg o2;
reg err;
reg [2:0] cs; // current state
parameter [2:0] // one hot with zero idle
IDLE = 3'b000... | 6.91306 |
module sm_para_1_tb ();
reg t_clk;
reg t_nrst;
reg t_i1;
reg t_i2;
wire t_o1;
wire t_o2;
wire t_err;
// sm_para_1
sm_para_1 dut (
.clk (t_clk),
.nrst(t_nrst),
.i1 (t_i1),
.i2 (t_i2),
.o1 (t_o1),
.o2 (t_o2),
.err (t_err)
);
//Produce the clock
... | 6.589342 |
module sm_para_1_var (
nrst,
clk,
i1,
i2,
o1,
o2,
err
);
input nrst;
input clk;
input i1;
input i2;
output o1;
output o2;
output err;
reg o1;
reg o2;
reg err;
reg [2:0] cs; // current state
parameter [2:0] // one hot with zero idle
IDLE = 3'... | 6.636188 |
module sm_para_1_var_tb ();
reg t_clk;
reg t_nrst;
reg t_i1;
reg t_i2;
wire t_o1;
wire t_o2;
wire t_err;
// sm_para_1_var
sm_para_1_var dut (
.clk (t_clk),
.nrst(t_nrst),
.i1 (t_i1),
.i2 (t_i2),
.o1 (t_o1),
.o2 (t_o2),
.err (t_err)
);
//Produce ... | 6.636188 |
module sm_para_2 (
nrst,
clk,
i1,
i2,
o1,
o2,
err
);
input nrst;
input clk;
input i1;
input i2;
output o1;
output o2;
output err;
reg o1;
reg o2;
reg err;
reg [2:0] cs; // current_state
reg [2:0] ns; // next state
parameter [2:0] // one hot w... | 6.763086 |
module sm_para_2_task (
nrst,
clk,
i1,
i2,
o1,
o2,
err
);
input nrst;
input clk;
input i1;
input i2;
output o1;
output o2;
output err;
reg o1;
reg o2;
reg err;
reg [2:0] cs; // current_state
reg [2:0] ns; // next state
parameter [2:0] // one ... | 6.866722 |
module sm_para_2_task_tb ();
reg t_clk;
reg t_nrst;
reg t_i1;
reg t_i2;
wire t_o1;
wire t_o2;
wire t_err;
// sm_para_2_task
sm_para_2_task dut (
.clk (t_clk),
.nrst(t_nrst),
.i1 (t_i1),
.i2 (t_i2),
.o1 (t_o1),
.o2 (t_o2),
.err (t_err)
);
//Produ... | 6.866722 |
module sm_para_2_task_var (
nrst,
clk,
i1,
i2,
o1,
o2,
err
);
input nrst;
input clk;
input i1;
input i2;
output o1;
output o2;
output err;
reg o1;
reg o2;
reg err;
reg [2:0] cs; // current_state
reg [2:0] ns; // next state
parameter [2:0] // ... | 6.866722 |
module sm_para_2_task_var_tb ();
reg t_clk;
reg t_nrst;
reg t_i1;
reg t_i2;
wire t_o1;
wire t_o2;
wire t_err;
// sm_para_2_task_var
sm_para_2_task_var dut (
.clk (t_clk),
.nrst(t_nrst),
.i1 (t_i1),
.i2 (t_i2),
.o1 (t_o1),
.o2 (t_o2),
.err (t_err)
)... | 6.866722 |
module sm_para_3 (
nrst,
clk,
i1,
i2,
o1,
o2,
err
);
input nrst;
input clk;
input i1;
input i2;
output o1;
output o2;
output err;
reg o1;
reg o2;
reg err;
reg [2:0] cs; // current_state
reg [2:0] ns; // next state
parameter [2:0] // one hot w... | 6.908795 |
module sm_para_3_tb ();
reg t_clk;
reg t_nrst;
reg t_i1;
reg t_i2;
wire t_o1;
wire t_o2;
wire t_err;
// sm_para_3
sm_para_3 dut (
.clk (t_clk),
.nrst(t_nrst),
.i1 (t_i1),
.i2 (t_i2),
.o1 (t_o1),
.o2 (t_o2),
.err (t_err)
);
//Produce the clock
... | 6.647456 |
module sm_ram #(
parameter SIZE = 64
) (
input clk,
input [31:0] a,
input we,
input [31:0] wd,
output [31:0] rd
);
reg [31:0] ram[SIZE - 1:0];
assign rd = ram[a[31:2]];
always @(posedge clk) if (we) ram[a[31:2]] <= wd;
endmodule
| 7.612428 |
module sm_ram_busy #(
parameter WIDTH = 6 // memory internal bus width (determines RAM size)
) (
input clk,
input rst_n,
input [31:0] a, // address
input we, // write enable
input [31:0] wd, // write data
input valid, // read/write request
... | 8.36364 |
module sm_delay #(
parameter DELAY = 2 // busy delay, from 0 to 255
) (
input clk,
input rst_n,
input valid, // read/write request
output ready, // read/write done
output start // work started strobe
);
localparam EFFECTIVE_DELAY = (DELAY > 255) ? 255 : DELAY;
wire [7:0] delay;
wi... | 6.99741 |
module sm_ram_outbuf #(
parameter WIDTH = 6 // memory internal bus width (determines RAM size)
) (
input clk,
input rst_n,
input [31:0] a, // address
input we, // write enable
input [31:0] wd, // write data
input valid, // read/write request
... | 8.042476 |
module sm_register (
input clk,
input rst,
input [31 : 0] d,
output reg [31 : 0] q
);
always @(posedge clk or negedge rst)
if (~rst) q <= 32'b0;
else q <= d;
endmodule
| 7.145181 |
module sm_register_we (
input clk,
input rst,
input we,
input [31 : 0] d,
output reg [31 : 0] q
);
always @(posedge clk or negedge rst)
if (~rst) q <= 32'b0;
else if (we) q <= d;
endmodule
| 7.722957 |
module sm_rom #(
parameter SIZE = 64
) (
input [31:0] a,
output [31:0] rd
);
reg [31:0] rom[SIZE - 1:0];
assign rd = rom[a];
initial begin
$readmemh("program.hex", rom);
end
endmodule
| 8.636473 |
module sm_RxFifo (
busClk,
spiSysClk,
rstSyncToBusClk,
rstSyncToSpiClk,
fifoWEn,
fifoFull,
busAddress,
busWriteEn,
busStrobe_i,
busFifoSelect,
busDataIn,
busDataOut,
fifoDataIn
);
//FIFO_DEPTH = 2^ADDR_WIDTH
parameter FIFO_DEPTH = 64;
parameter ADDR_WIDTH = 6;
... | 7.12044 |
module sm_sdram_controller #(
parameter CAS_LATENCY = 3,
parameter INIT_CYCL = 100
) (
// control signals
input clkIn,
input rst_n,
input cs,
input we,
output reg re,
output reg ready,
input [ 5:0] a, // ro... | 7.191065 |
module sm_status (
input clk,
input rst_n,
input run,
output s00_idle, // idle status
output s01_ife0, // instruction fetch 0
output s02_ife1, // instruction fetch 1
output s03_exec, // execution
output s04_wtbk // data writeback
);
// status counter
reg [2:0] status_cntr;... | 7.417774 |
module SM_tb;
// parameter
parameter cyc = 120;
// I/O
reg clk, rst_n;
reg [12:0] instr;
wire fin;
wire d_valid;
wire [9:0] pc;
wire [19:0] out_data;
wire [2:0] err_code;
// memeory and answer
reg [35:0] MEM[0:1024];
// regs
reg [35:0] data;
reg [10:0] maxSize;
reg [9:0] result;
reg... | 7.260833 |
module
module sm_top
(
input clkIn,
input rst_n,
input [ 3:0 ] clkDevide,
input clkEnable,
output clk,
input [ 4:0 ] regAddr,
output [31:0 ] regData
);
//metastability input filters
wire [ 3:0 ] devide;
wire enable;
wi... | 6.817969 |
module sm_clk_divider #(
parameter shift = 16,
bypass = 0
) (
input clkIn,
input rst_n,
input [3:0] devide,
input enable,
output clkOut
);
wire [31:0] cntr;
wire [31:0] cntrNext = cntr + 1;
sm_register_we r_cntr (
clkIn,
rst_n,
enable,
... | 7.194941 |
module sm_TxFifo (
busClk,
spiSysClk,
rstSyncToBusClk,
rstSyncToSpiClk,
fifoREn,
fifoEmpty,
busAddress,
busWriteEn,
busStrobe_i,
busFifoSelect,
busDataIn,
busDataOut,
fifoDataOut
);
//FIFO_DEPTH = 2^ADDR_WIDTH
parameter FIFO_DEPTH = 64;
parameter ADDR_WIDTH = 6;... | 7.082185 |
module SN74194 (
P,
Q,
DSR,
DSL,
S1,
S0,
_MR,
CLOCK
);
parameter LENGTH = 4;
input DSR, DSL, S1, S0, _MR, CLOCK;
input [LENGTH-1:0] P;
output reg [LENGTH-1:0] Q;
always @(posedge CLOCK or negedge _MR)
if (_MR == 0) Q <= 0;
else
case ({
S1, S0
})
... | 7.023791 |
module SN74194v1 (
P,
Q,
DSR,
DSL,
S1,
S0,
_MR,
CLOCK
);
parameter LENGTH = 4;
input DSR, DSL, S1, S0, _MR, CLOCK;
input [LENGTH-1:0] P;
output reg [LENGTH-1:0] Q;
reg [LENGTH-1:0] NextQ;
//reg Q; //A warning will appear if dimension is not given.
// An error will occur i... | 7.509644 |
module SN74194v2 (
P,
Q,
DSR,
DSL,
S1,
S0,
_MR,
CLOCK
);
parameter LENGTH = 4;
input DSR, DSL, S1, S0, _MR, CLOCK;
input [LENGTH-1:0] P;
output reg [LENGTH-1:0] Q;
//reg Q; //A warning will appear if dimension is not given.
// An error will occur if posedge _MR is used beca... | 7.299687 |
module sn7473 (
input mclk,
input mrst,
input clk_n,
input j,
input k,
input clr_n,
output reg q,
output reg q_n
);
reg q_int;
wire clk_n_pedge, clk_n_nedge, clk_n_f;
wire clr_n_pedge, clr_n_f;
wire j_f, k_f;
/* verilator lint_off PINMISSING */
gfilt filt_clk_n (
.cl... | 6.807797 |
modules: N/A
*- Description: Implement the logic functions of a Quad 2-input AND gate
*-
*- Example of Usage:
You can assign the input and output pins of this module to the GPIOs of the STEPFPGA board
To observe the logic behavior, you may need additional components such as swiches, pushbuottons
LEDs, resistors.... | 6.670404 |
modules: N/A
*- Description: Implement the logic functions of a 3-to-8 Line Decoder/Demultiplexer with Inverting Output
*-
*- Example of Usage:
You can assign the input and output pins of this module to the GPIOs of the STEPFPGA board
To observe the logic behavior, you may need additional components such as swich... | 6.670404 |
modules: N/A
*- Description: Implement the logic functions of an 8-bit Parallel-load Shift Registers
*-
*- Example of Usage:
You can assign the input and output pins of this module to the GPIOs of the STEPFPGA board
To observe the logic behavior, you may need additional components such as swiches, pushbuottons
L... | 6.670404 |
modules: N/A
*- Description: Implement the logic functions of a 4-bit Binary Full Adder
*-
*- Example of Usage:
You can assign the input and output pins of this module to the GPIOs of the STEPFPGA board
To observe the logic behavior, you may need additional components such as swiches, pushbuottons
LEDs, resistor... | 6.670404 |
modules: N/A
*- Description: Implement the logic functions of a Dual 4-Stage Binary Counter
*-
*- Example of Usage:
You can assign the input and output pins of this module to the GPIOs of the STEPFPGA board
To observe the logic behavior, you may need additional components such as swiches, pushbuottons
LEDs, resi... | 6.670404 |
modules: N/A
*- Description: Implement the logic functions of a Dual Positive Edge Triggered D-Flipflop
*-
*- Example of Usage:
You can assign the input and output pins of this module to the GPIOs of the STEPFPGA board
To observe the logic behavior, you may need additional components such as swiches, pushbuottons... | 6.670404 |
module SN74LS00 (
input wire a1,
input wire b1,
output wire y1,
input wire a2,
input wire b2,
output wire y2,
input wire a3,
input wire b3,
output wire y3,
input wire a4,
input wire b4,
output wire y4
);
assign y1 = ~(a1 & b1);
assign y2 = ~(a2 & b2);
as... | 7.006551 |
module SN74LS04 (
input wire a1,
output wire y1,
input wire a2,
output wire y2,
input wire a3,
output wire y3,
input wire a4,
output wire y4,
input wire a5,
output wire y5,
input wire a6,
output wire y6
);
assign y1 = ~a1;
assign y2 = ~a2;
assign y3 = ~a... | 7.363943 |
module SN74LS07 (
input wire a1,
output wire y1,
input wire a2,
output wire y2,
input wire a3,
output wire y3,
input wire a4,
output wire y4,
input wire a5,
output wire y5,
input wire a6,
output wire y6
);
buf (y1, a1);
buf (y2, a2);
buf (y3, a3);
buf ... | 6.713973 |
module SN74LS195Abehavior (
Q,
P,
Q3not,
PE,
J,
K,
CP,
MR
);
parameter LENGTH = 4;
input PE, J, K, CP, MR;
input [LENGTH-1:0] P;
output reg [LENGTH-1:0] Q;
output Q3not;
always @(posedge CP or negedge MR)
if (MR == 0) Q <= 0;
else if (PE == 0) Q <= P;
else if (PE... | 7.187985 |
module SN74LS195ARelativeTime;
reg [3:0] P;
reg PE, J, K, CP, MR;
wire Q3not_gate, Q3not_behavior;
wire [3:0] Qbehavior, Qgates;
SN74LS195Agates GatesChip (
Qgates,
P,
Q3not_gate,
PE,
J,
K,
CP,
MR
);
SN74LS195Abehavior BehaviorChip (
Qbehavior,
... | 6.678164 |
modules, if separate G is needed
module sn74ls240(a, y, g_);
parameter WIDTH=4;
input [WIDTH-1:0] a;
output [WIDTH-1:0] y;
input g_;
assign y = (g_==1'b0) ? ~a : {WIDTH{1'bz}};
endmodule
| 8.240324 |
module sn74ls241 (
a1,
y1,
g1_,
a2,
y2,
g2
);
parameter WIDTH = 4;
input [WIDTH-1:0] a1, a2;
output [WIDTH-1:0] y1, y2;
input g1_, g2;
assign y1 = (g1_ == 1'b0) ? a1 : {WIDTH{1'bz}};
assign y2 = (g2 == 1'b1) ? a2 : {WIDTH{1'bz}};
endmodule
| 7.75239 |
module sn74ls244_testbench;
parameter WIDTH = 4;
reg [WIDTH-1:0] a1, a2;
reg g1_, g2;
wire [WIDTH-1:0] y1, y2;
sn74ls241 #(
.WIDTH(WIDTH)
) dut (
.a1 (a1),
.y1 (y1),
.g1_(g1_),
.a2 (a2),
.y2 (y2),
.g2 (g2)
);
`define assert(signame, signal, value) \
i... | 6.758324 |
modules, if separate G is needed
module sn74ls244(a, y, g_);
parameter WIDTH=4;
input [WIDTH-1:0] a;
output [WIDTH-1:0] y;
input g_;
assign y = (g_==1'b0) ? a : {WIDTH{1'bz}};
endmodule
| 8.240324 |
module sn74ls244_testbench;
parameter WIDTH = 8;
reg [WIDTH-1:0] a;
reg g_;
wire [WIDTH-1:0] y;
sn74ls244 #(
.WIDTH(WIDTH)
) dut (
.a (a),
.y (y),
.g_(g_)
);
`define assert(signame, signal, value) \
if (signal !== value) begin \
$display("Error: %s should be %b, but... | 6.758324 |
module sn74ls245 (
a,
b,
dir,
g_
);
parameter WIDTH = 8;
inout [WIDTH-1:0] a, b;
input dir, g_;
assign a = (g_ == 'b1 || dir == 'b1) ? {WIDTH{1'bZ}} : b;
assign b = (g_ == 'b1 || dir == 'b0) ? {WIDTH{1'bZ}} : a;
endmodule
| 6.922309 |
module SN74LS257 #(
parameter INVERTED_OUTPUT = 0
) (
input wire [3:0] a,
input wire [3:0] b,
input wire select,
input wire out_control,
output wire [3:0] y
);
wire [3:0] selection;
wire [3:0] internal_out;
assign selection = select == 0 ? a : b;
assign internal_out = INVERTED_OUTPUT == ... | 7.33012 |
module SN74LS27 (
input wire a1,
input wire b1,
input wire c1,
output wire y1,
input wire a2,
input wire b2,
input wire c2,
output wire y2,
input wire a3,
input wire b3,
input wire c3,
output wire y3
);
assign y1 = ~a1 & ~b1 & ~c1;
assign y2 = ~a2 & ~b2 & ... | 7.394513 |
module SN74LS374 (
input wire reset,
input wire [7:0] data,
input wire clk,
input wire out_control,
output wire [7:0] out
);
reg [7:0] out_reg;
assign out = out_control == 1'b1 ? /*8'bz*/ 8'b00000000 : out_reg;
always @(posedge clk) begin
if (reset == 1'b1) begin
out_reg <= 8'b00... | 6.743893 |
module: SN74LS374
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module SN74LS374_testbench;
// Inputs
reg [7:0] data;
reg clk;
reg out_control;
// Outputs
wire [... | 6.711014 |
module SN74LS73 (
j1,
clk1,
k1,
clrn1,
q1,
qn1,
j2,
clk2,
k2,
clrn2,
q2,
qn2
);
input wire j1;
input wire clk1;
input wire k1;
input wire clrn1;
output reg q1;
output wire qn1;
input wire j2;
input wire clk2;
input wire k2;
input wire clrn2;
outpu... | 6.787788 |
module SN74LS74 (
prn1,
d1,
clk1,
clrn1,
q1,
qn1,
prn2,
d2,
clk2,
clrn2,
q2,
qn2
);
input wire prn1;
input wire d1;
input wire clk1;
input wire clrn1;
output reg q1;
output wire qn1;
input wire prn2;
input wire d2;
input wire clk2;
input wire clrn2;... | 6.909097 |
module Snake_Control(
input CLK,
input RESET,
input Counter,
input [9:2] Pixel_Address_X,
input [8:2] Pixel_Address_Y,
input [7:0] Random_Target_Address_X,
input [6:0] Random_Target_Address_Y,
input [1:0] Direction_state,
input [1:0] MSM_State,
output [11:0] Colour,
output RE... | 7.012413 |
module vga_sync (
input wire clk,
reset,
output wire hsync,
vsync,
video_on,
p_tick,
output wire [9:0] pixel_x,
pixel_y
);
// constant declaration
// VGA 640-by-480 sync parameters
localparam HD = 640; // horizontal display area
localparam HF = 48; // h. front (left) border
l... | 8.903884 |
module ps2_rx (
input wire clk,
reset,
input wire ps2d,
ps2c,
rx_en,
output reg rx_done_tick,
output wire [7:0] dout
);
// symbolic state declaration
localparam [1:0] idle = 2'b00, dps = 2'b01, //data, parity, stop
load = 2'b10;
// signal declaration
reg [1:0] state_reg, state_n... | 7.235202 |
module snake (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
LEDR,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
... | 7.506897 |
module randomGrid (
clk,
rand_X,
rand_Y
);
input clk;
output reg [7:0] rand_X = 6;
output reg [6:0] rand_Y = 6;
// x and y will stop at random pixel.
integer max_height = 108;
integer max_width = 154;
always @(posedge clk) begin
if (rand_X === max_width) rand_X <= 6;
else rand_X <= r... | 6.526788 |
module delay_counter (
clk,
reset_n,
en_delay,
delayed_clk
);
input clk;
input reset_n;
input en_delay;
output delayed_clk;
reg [3:0] delay;
always @(posedge clk) begin
if (delay == 2) delay <= 0;
else if (en_delay) begin
delay <= delay + 1'b1;
end
end
assign delayed... | 6.853164 |
module
`include "../definitions/define.vh"
module SnakeGame (
// joystick input
input wire
res_x_one,
res_x_two,
res_y_one,
res_y_two,
input wire clk, // 50MHz
// VGA input
input wire
reset,
color, // swap between 2 outputs
// VGA output
output wire
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC... | 6.585576 |
module snakes (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R, ... | 8.659422 |
module randomApple (
clk,
rand_X,
rand_Y
);
input clk;
output reg [7:0] rand_X = 6;
output reg [6:0] rand_Y = 6;
// set the maximum height and width of the game interface.
// x and y will scan over every pixel.
integer max_height = 108;
integer max_width = 154;
always @(posedge clk) begin
... | 6.691568 |
module delay_counter (
clk,
reset_n,
en_delay,
delayed_clk
);
input clk;
input reset_n;
input en_delay;
output delayed_clk;
reg [3:0] delay;
// Register for the delay counter
always @(posedge clk) begin
// if (!reset_n)
// delay <= 20'd840000;
if (delay == 2) delay <= 0;
... | 6.853164 |
module hex_decoder (
hex_digit,
segments
);
input [3:0] hex_digit;
output reg [6:0] segments;
always @(*)
case (hex_digit)
4'h0: segments = 7'b100_0000;
4'h1: segments = 7'b111_1001;
4'h2: segments = 7'b010_0100;
4'h3: segments = 7'b011_0000;
4'h4: segments = 7'b001_1001... | 7.584821 |
module snake_control (
input CLK,
input RESET,
//input Counter,
input [9:0] Pixel_Address_X,
input [8:0] Pixel_Address_Y,
input [7:0] Random_Target_Address_X,
input [6:0] Random_Target_Address_Y,
input [1:0] Direction_state,
// input [1:0] MSM_State,
output reg [11:0] Colour,
... | 6.866116 |
module Snake_Controller (
CLK,
data,
keyboard_CLK,
Hsync,
Vsync,
R,
G,
B
);
input CLK, keyboard_CLK, data;
output [2:0] R, G;
output [1:0] B;
output Hsync, Vsync;
reg CLK25MHz;
wire [7:0] keycode;
wire led;
wire [9:0] XCoord, YCoord;
wire [7:0] pixel_out;
... | 7.012413 |
module snake_cpu_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire [31:0] q... | 6.6395 |
module snake_cpu_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire [31:0] q... | 6.6395 |
module snake_cpu_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
3'b000:... | 6.6395 |
module snake_cpu_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [24:0] cpu_d_address... | 6.6395 |
module snake_cpu_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
);
output [1:0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_input_tm_cnt;
wire [2:0] switch_for_mux;
... | 6.6395 |
module snake_cpu_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
);
output [3:0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [3:0] fifo_wrptr_inc;
always @(ge2_free or ge3_free or input_tm_cn... | 6.6395 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.