code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module comp6_30 (
operand1,
operand2,
result,
signbit
);
input [5:0] operand1;
input [29:0] operand2;
input signbit;
output result;
wire gr;
comp_gr_6 comparator (
.gr (gr),
.in1(operand2[5:0]),
.in2(operand1)
);
// whenever operand2 is +ve and if any of bits [29:6] is 1 or
// if it's lower 6 bits are greater than operand1, output is 1
assign result = (!(signbit) && ((|operand2[29:6]) || gr));
endmodule
| 6.661777 |
module comp30_6 (
operand1,
operand2,
signbit,
result
);
input [29:0] operand1;
input [5:0] operand2;
input signbit;
output result;
wire gr;
comp_gr_6 comparator (
.gr (gr),
.in1(operand2),
.in2(operand1[5:0])
);
assign result = (signbit || ((~|(operand1[29:6])) && gr));
endmodule
| 6.919514 |
module comp3_30 (
operand1,
operand2,
signbit,
result
);
input [2:0] operand1;
input [29:0] operand2;
input signbit;
output result;
wire less;
less_comp3 comparator (
.less(less),
.in1 (operand2[2:0]),
.in2 (operand1)
);
assign result = (signbit || ((~|operand2[29:3]) && less));
endmodule
| 7.171378 |
module less_comp3 (
in1,
in2,
less
);
input [2:0] in1;
input [2:0] in2;
output less;
assign less = (in1 < in2);
endmodule
| 6.705926 |
module sub2_32 (
result,
operand1,
operand2,
und_flw_bit
);
output [31:0] result;
output und_flw_bit;
input [31:0] operand1;
input [31:0] operand2;
wire c_out;
// since we already have adders, we would like to
// perform subtraction using adders
cla_adder_32 adder (
.in1 (operand1),
.in2 (~operand2),
.cin (1'b1),
.sum (result),
.cout(c_out)
);
// If an adder is used as a subtractor, we need to
// invert carry bit
assign und_flw_bit = !c_out;
endmodule
| 7.082705 |
module sm_0535UART_TRANSMITTER (
input CLOCK, //Clock input
input TX_DATA_VALID, //Input Bitstream
input [7:0] TX_BYTE,
output O_TX_SERIAL,
output O_TX_DONE
);
// different states
parameter IDLE = 3'b000,
TX_START_BIT = 3'b001,
TX_DATA_BITS = 3'b010,
TX_STOP_BIT = 3'b011,
CLEANUP = 3'b100;
// variables to assign values during code
reg r_tx_serial = 1;
reg r_tx_done = 1;
reg [3:0] Bit_Index = 0;
reg [2:0] current_state = IDLE;
reg [7:0] r_tx_byte;
integer counter = 1; // to count cycles to wait
integer wait_count = 434; // this many cycles to wait
// assigining output
assign O_TX_SERIAL = r_tx_serial;
assign O_TX_DONE = r_tx_done;
always @(posedge CLOCK) begin
case (current_state)
IDLE: begin
if (TX_DATA_VALID) begin
current_state <= TX_START_BIT;
counter <= 1;
r_tx_byte <= TX_BYTE;
r_tx_done <= 0;
end else begin
current_state <= IDLE;
r_tx_serial <= 1;
r_tx_done <= 1;
end
end
TX_START_BIT: begin
if (counter < wait_count) begin
r_tx_serial <= 0;
current_state <= TX_START_BIT;
counter <= counter + 1;
end else begin
counter <= 1;
current_state <= TX_DATA_BITS;
end
end
TX_DATA_BITS: begin
if (Bit_Index < 7) begin
if (counter < wait_count) begin
r_tx_serial <= r_tx_byte[Bit_Index];
counter <= counter + 1;
end else begin
counter = 1;
Bit_Index <= Bit_Index + 1;
end
end else begin
if (counter < wait_count) begin
r_tx_serial <= r_tx_byte[Bit_Index];
counter <= counter + 1;
end else begin
counter = 1;
current_state <= TX_STOP_BIT;
end
end
end
TX_STOP_BIT: begin
if (counter < wait_count) begin
r_tx_serial <= 1;
current_state <= TX_STOP_BIT;
counter <= counter + 1;
end else begin
current_state <= CLEANUP;
end
end
CLEANUP: begin
counter <= 1;
r_tx_done <= 1;
current_state <= IDLE;
Bit_Index <= 0;
end
endcase
end
endmodule
| 6.872988 |
module sm_0535_colour_sensor_detection (
output S0,
output S1,
output S2,
output S3,
input signal,
output [2:0] color,
input clk
);
reg r_S0 = 0;
reg r_S1 = 1;
reg [1:0] r_color = 2'b00;
reg [6:0] r_red;
reg [6:0] r_blue;
reg [6:0] r_green;
reg [12:0] clk_counter = 0;
reg [6:0] freq_counter = 0;
reg old_sig = 0;
assign S0 = r_S0;
assign S1 = r_S1;
assign S2 = r_color[0];
assign S3 = r_color[1];
assign color[0] = (6'h0B < r_red & r_red < 6'h14) & (6'h17 < r_blue & r_blue < 6'h23) & (6'h04 < r_green & r_green < 6'h08) ? 1:0; //r_red
assign color[1] = (6'h13 < r_blue & r_blue < 6'h01A) & (6'h07 < r_red & r_red < 6'h0A) & (6'h07 < r_green & r_green < 6'h0C) ? 1:0;//r_blue;
assign color[2] = (6'h05 < r_green & r_green < 6'h08) & (6'h03 < r_red & r_red < 6'h07) & (6'h19 < r_blue & r_blue < 6'h22) ? 1:0; //r_green;
always @(posedge clk) begin
clk_counter = clk_counter + 1;
if (signal != old_sig) begin
freq_counter = freq_counter + 1;
end
if (clk_counter == 1000) begin
case (r_color)
2'b00: begin
r_red = freq_counter;
r_color = 2'b01;
end
2'b01: begin
r_blue = freq_counter;
r_color = 2'b11;
end
2'b11: begin
r_green = freq_counter;
r_color = 2'b00;
end
endcase
clk_counter = 0;
freq_counter = 0;
end
old_sig = signal;
end
endmodule
| 6.648214 |
module sm_0535_Line_follower (
input clk_adc,
clk_sm_bot,
input dout_adc,
output chip_select_adc,
din_adc,
clk_mod_adc,
output pwm_A1_A,
output pwm_A1_B,
output pwm_B1_A,
output pwm_B1_B,
output [1:0] Unit_at
);
wire [2:0] w_adc_data;
sm_0535_ADC_CONVERT line_sensor (
.sclk(clk_adc),
.dout(dout_adc),
.chip_select(chip_select_adc),
.din(din_adc),
.ADC_data(w_adc_data),
.clk_module(clk_mod_adc)
);
sm_0535_sm_bot_core follow_algo (
.clk_core(clk_sm_bot),
.adc_data(w_adc_data),
.A1_A(pwm_A1_A),
.A1_B(pwm_A1_B),
.B1_A(pwm_B1_A),
.B1_B(pwm_B1_B),
.Unit_at(Unit_at)
);
endmodule
| 6.997369 |
module sm_0535_SM_TOTALL (
// line_follow ports
input clk_adc,
clk_sm_bot,
clk_pwm,
input dout_adc,
output chip_select_adc,
din_adc,
clk_mod_adc,
output pwm_A1_A,
output pwm_A1_B,
output pwm_B1_A,
output pwm_B1_B,
output [3:0] z_current_node,
output [2:0] z_current_unit,
// color_sensor ports
input clk_color,
input color_input,
output S0,
output S1,
output S2,
output S3,
output led_R,
output led_G,
output led_B,
// uart ports
input clk_uart,
output tx_serial,
input i_rx_serial
);
wire [2:0] w_color_in;
wire [7:0] w_tx_byte;
wire w_tx_data_valid;
wire w_tx_done;
wire [2:0] w_adc_data;
wire [2:0] w_unit_at;
wire w_start_detecting;
wire w_color_detected;
wire [6:0] w_speed_a1_a; // speed of right motor
wire [6:0] w_speed_a1_b; // speed of right motor
wire [6:0] w_speed_b1_a; // speed of left motor
wire [6:0] w_speed_b1_b; // speed of left motor
wire [7:0] w_rx_byte;
wire [16:0] w_paths_av;
// ADC block-----------------------------------------------------------------------------------------------------------
sm_0535_ADC_CONVERT line_sensor (
.sclk(clk_adc),
.dout(dout_adc),
.chip_select(chip_select_adc),
.din(din_adc),
.ADC_data(w_adc_data),
.clk_module(clk_mod_adc)
);
// sm_bot_core-----------------------------------------------------------------------------------------------------------
sm_0535_sm_bot_core follow_algo (
.clk_core(clk_sm_bot),
.adc_data(w_adc_data),
.color_detected(w_color_detected),
.speed_a1_a(w_speed_a1_a), // speed of right motor
.speed_a1_b(w_speed_a1_b), // speed of right motor
.speed_b1_a(w_speed_b1_a), // speed of left motor
.speed_b1_b(w_speed_b1_b), // speed of left motor
.path(w_paths_av),
.start_detecting(w_start_detecting),
.Unit_at(w_unit_at),
.o_current_node(z_current_node),
.o_current_unit(z_current_unit)
);
// color_sensor block-------------------------------------------------------------------------------------------------
sm_0535_colour_sensor_detection c_sd_1 (
.clk(clk_color),
.signal(color_input),
.S0(S0),
.S1(S1),
.S2(S2),
.S3(S3),
.color(w_color_in)
);
// uart controller block-----------------------------------------------------------------------------------------------------
sm_0535_uart_controller cont_tx (
.clk(clk_uart),
.o_tx_done(w_tx_done),
.color_in(w_color_in),
.Unit_at(w_unit_at),
.start_detecting_color(w_start_detecting),
.color_detected(w_color_detected),
.tx_data_valid(w_tx_data_valid),
.tx_byte(w_tx_byte),
.led_R(led_R),
.led_G(led_G),
.led_B(led_B)
);
// uart transmitter block---------------------------------------------------------------------------------------------
sm_0535UART_TRANSMITTER trans_1 (
.CLOCK(clk_uart),
.TX_DATA_VALID(w_tx_data_valid),
.TX_BYTE(w_tx_byte),
.O_TX_SERIAL(tx_serial),
.O_TX_DONE(w_tx_done)
);
// pwm block-------------------------------------------------------------------------------------------------------------
sm_0535_pwm speed_12 (
.clk(clk_pwm),
.speed_a1_a(w_speed_a1_a),
.speed_a1_b(w_speed_a1_b),
.speed_b1_a(w_speed_b1_a),
.speed_b1_b(w_speed_b1_b),
.A1_A(pwm_A1_A),
.A1_B(pwm_A1_B),
.B1_A(pwm_B1_A),
.B1_B(pwm_B1_B),
);
// uart reciever controller--------------------------------------------------------------------------------------------
sm_0535_uart_rx_controller cont_rx (
.clk(clk_uart),
.o_rx_byte(w_rx_byte),
.paths_av(w_paths_av) // this `16 bit shows availabilty of paths each bit show a single path
);
// uart reciever----------------------------------------------------------------------------------------------------
sm_0535_UART_Receiver rec_1 (
.CLOCK(clk_uart),
.i_RX_Serial(i_rx_serial),
.o_RX_Byte(w_rx_byte)
);
endmodule
| 7.058406 |
module sm_0535_UART_Receiver
// clocks per bit = freq. of clock / freq. of UART i.e., 25000000/115200 = 217
(
input CLOCK,
input i_RX_Serial,
output [7:0] o_RX_Byte
);
parameter IDLE = 3'b000,
RX_START_BIT = 3'b001,
RX_DATA_BITS = 3'b010,
RX_STOP_BIT = 3'b011,
CLEANUP = 3'b100;
integer r_Clock_Count = 1;
reg [3:0] r_Bit_Index = 0;
reg [7:0] r_RX_Byte = 0;
reg [7:0] temp_r_RX_Byte = 0;
reg [2:0] current_state = 0;
integer CLOCKS_PER_BIT = 434;
reg [2:0] r_current_state = 0;
assign o_RX_Byte = r_RX_Byte;
assign o_current_state = current_state;
always @(posedge CLOCK) begin
case (current_state)
IDLE: begin
if (!i_RX_Serial) begin
current_state <= RX_START_BIT;
r_current_state <= 1;
r_Clock_Count <= 1;
end else begin
current_state <= IDLE;
end
end
RX_START_BIT: begin
if (r_Clock_Count < (CLOCKS_PER_BIT - 1)) begin
r_Clock_Count <= r_Clock_Count + 1;
current_state <= RX_START_BIT;
end else begin
r_Clock_Count <= 1;
current_state <= RX_DATA_BITS;
end
end
RX_DATA_BITS: begin
if (r_Bit_Index < 8) begin
if (r_Clock_Count > CLOCKS_PER_BIT - 1) begin
temp_r_RX_Byte[r_Bit_Index] <= i_RX_Serial;
r_Clock_Count = 1;
r_Bit_Index <= r_Bit_Index + 1;
end else begin
r_Clock_Count <= r_Clock_Count + 1;
end
end else begin
r_Clock_Count = 1;
current_state <= RX_STOP_BIT;
end
end
RX_STOP_BIT: begin
current_state <= CLEANUP;
r_RX_Byte <= temp_r_RX_Byte;
end
CLEANUP: begin
temp_r_RX_Byte <= 0;
r_Clock_Count <= 1;
r_Bit_Index <= 0;
current_state <= IDLE;
end
endcase
end
endmodule
| 6.724117 |
module sm_1p (
input clk,
reset,
x,
output reg y
);
reg [1:0] state;
parameter [1:0] S0 = 2'd0, S1 = 2'd1, S2 = 2'd2, S3 = 2'd3;
always @(posedge clk)
if (!reset) state <= 0;
else begin
case (state)
S0: begin
y <= 0;
if (x) state = S1;
else state = S0;
end
S1: begin
y <= 1;
if (x) state = S2;
else state = S1;
end
S2: begin
y <= 0;
if (x) state = S3;
else state = S2;
end
S3: begin
y <= 1;
if (x) state = S0;
else state = S1;
end
endcase
end
endmodule
| 6.698469 |
module sm_21 (
input wire Zero,
input wire [1:0] Mem1,
output reg [1:0] PcCtrl1
);
always @(*) begin
case (Mem1)
2'b00: PcCtrl1 <= 3; // must jump
2'b01: begin // jump when != 0
if (Zero != 0) begin
PcCtrl1 <= 3;
end else begin
PcCtrl1 <= 1;
end
end
2'b10: begin // jump when == 0
if (Zero == 0) begin
PcCtrl1 <= 3;
end else begin
PcCtrl1 <= 1;
end
end
2'b11: PcCtrl1 <= 1; // must not jump
endcase
end
endmodule
| 7.529134 |
module sm_2p (
input clk,
reset,
x,
output reg y
);
reg [1:0] state;
parameter [1:0] S0 = 2'd0, S1 = 2'd1, S2 = 2'd2, S3 = 2'd3;
always @(posedge clk)
if (!reset) state <= 0;
else begin
case (state)
S0: if (x) state = S1;
else state = S0;
S1: if (x) state = S2;
else state = S1;
S2: if (x) state = S3;
else state = S2;
S3: if (x) state = S0;
else state = S1;
endcase
end
always @(*)
if (state == S1 | state == S3) y = 1;
else y = 0;
endmodule
| 6.534643 |
module sm_add_test (
input wire clk,
input wire [1:0] btn,
input wire [7:0] sw,
output wire [3:0] an,
output wire [7:0] sseg
);
// signal declaration
wire [3:0] sum, mout, oct;
wire [7:0] led0, led1, led2, led3;
// instance of adder
sign_mag_add #(
.N(4)
) sm_adder_unit (
.a (sw[3:0]),
.b (sw[7:4]),
.sum(sum)
);
// magnitude displayed on rightmost 7-seg LED
assign mout = (btn == 2'b00) ? sw[3:0] : (btn == 2'b01) ? sw[7:4] : sum;
assign oct = {1'b0, mout[2:0]};
// instance of hex decoder
hex_to_sseg sseg_unit (
.hex (oct),
.dp (1'b0),
.sseg(led0)
);
// sign displayed on 2nd 7-seg LED
// middle LED bar on for negative number
assign led1 = mout[3] ? 8'b11111110 : 8'b11111111;
// blank two other LEDs
assign led2 = 8'b11111111;
assign led3 = 8'b11111111;
// instance of 7-seg LED multiplex module
disp_mux disp_unit (
.clk(clk),
.reset(1'b0),
.in0(led0),
.in1(led1),
.in2(led2),
.in3(led3),
.an(an),
.sseg(sseg)
);
endmodule
| 8.152652 |
module sm_ahb_master (
input clk,
input rst_n,
input [31:0] a, // address
input we, // write enable
input [31:0] wd, // write data
input valid, // read/write request
output ready, // read/write done
output [31:0] rd, // read data
output HCLK,
output HRESETn,
output HWRITE,
output [ 1:0] HTRANS,
output [31:0] HADDR,
input [31:0] HRDATA,
output [31:0] HWDATA,
input HREADY,
input HRESP
);
assign HCLK = clk;
assign HRESETn = rst_n;
assign HWRITE = we;
assign HTRANS = valid ? `HTRANS_NONSEQ : `HTRANS_IDLE; //AHB single transfer only
assign HADDR = a;
wire ahbReady = HREADY & ~HRESP; // AHB peripheral Ready and NoError
wire memStart = valid;
wire memEnd = ~valid & ahbReady;
// memory request is pending
wire memWait;
wire memWait_next = memStart ? 1 : memEnd ? 0 : memWait;
sm_register_c r_memWait (
clk,
rst_n,
memWait_next,
memWait
);
// AHB Ready and Error status have meaning only when there was a request before
assign ready = memWait ? ahbReady : 1'b1;
assign rd = HRDATA;
sm_register_we #(32) r_hwdata (
clk,
rst_n,
valid,
wd,
HWDATA
);
endmodule
| 6.650792 |
module multi_ro (
output reg CHSEL,
output reg WR_EN,
input wire CLK,
input wire DAVAIL,
input wire RST
);
// state bits
parameter IDLE_BIT = 0, CH_SELECT_BIT = 1, READOUT_BIT = 2, WRITE_HEADER_BIT = 3;
parameter
IDLE = 4'b1<<IDLE_BIT,
CH_SELECT = 4'b1<<CH_SELECT_BIT,
READOUT = 4'b1<<READOUT_BIT,
WRITE_HEADER = 4'b1<<WRITE_HEADER_BIT,
XXX = 4'bx;
reg [3:0] state;
reg [3:0] nextstate;
// comb always block
always @* begin
nextstate = XXX; // default to x because default_state_is_x is set
case (1'b1) // synopsys parallel_case full_case
state[IDLE_BIT]: begin
if (DAVAIL) begin
nextstate = WRITE_HEADER;
end else begin
nextstate[IDLE] = 1'b1; // Added because implied_loopback is true
end
end
state[CH_SELECT_BIT]: begin
begin
nextstate = READOUT;
end
end
state[READOUT_BIT]: begin
if (DAVAIL) begin
nextstate = READOUT;
end else begin
nextstate = IDLE;
end
end
state[WRITE_HEADER_BIT]: begin
begin
nextstate = CH_SELECT;
end
end
endcase
end
// sequential always block
always @(posedge CLK) begin
if (RST) state <= IDLE;
else state <= nextstate;
end
// datapath sequential always block
always @(posedge CLK) begin
if (RST) begin
CHSEL <= 0;
WR_EN <= 0;
end else begin
CHSEL <= 0; // default
WR_EN <= 0; // default
case (1'b1) // synopsys parallel_case full_case
nextstate[IDLE_BIT]: begin
; // case must be complete for onehot
end
nextstate[CH_SELECT_BIT]: begin
CHSEL <= 1;
WR_EN <= 1;
end
nextstate[READOUT_BIT]: begin
CHSEL <= 1;
WR_EN <= 1;
end
nextstate[WRITE_HEADER_BIT]: begin
WR_EN <= 1;
end
endcase
end
end
// This code allows you to see state names in simulation
`ifndef SYNTHESIS
reg [95:0] statename;
always @* begin
case (1'b1)
state[IDLE_BIT]: statename = "IDLE";
state[CH_SELECT_BIT]: statename = "CH_SELECT";
state[READOUT_BIT]: statename = "READOUT";
state[WRITE_HEADER_BIT]: statename = "WRITE_HEADER";
default: statename = "XXXXXXXXXXXX";
endcase
end
`endif
endmodule
| 6.969485 |
module sm_clk_divider #(
parameter shift = 16,
bypass = 0
) (
input clkIn,
input rst_n,
input [3:0] devide,
input enable,
output clkOut
);
reg [39:0] cntr;
wire [39:0] cntrNext = cntr + 1;
//sm_register_we r_cntr(clkIn, rst_n, enable, cntrNext, cntr);
always @(posedge clkIn) cntr <= cntrNext;
assign clkOut = bypass ? clkIn : cntr[shift+devide];
endmodule
| 7.194941 |
module sm_alu (
input [31:0] srcA,
input [31:0] srcB,
input [ 2:0] oper,
input [ 4:0] shift,
output zero,
output reg [31:0] result
);
always @(*) begin
case (oper)
default: result = srcA + srcB;
`ALU_ADD: result = srcA + srcB;
`ALU_OR: result = srcA | srcB;
`ALU_LUI: result = (srcB << 16);
`ALU_SRL: result = srcB >> shift;
`ALU_SLTU: result = (srcA < srcB) ? 1 : 0;
`ALU_SUBU: result = srcA - srcB;
endcase
end
assign zero = (result == 0);
endmodule
| 7.120672 |
module sm_register_file (
input clk,
input [ 4:0] a0,
input [ 4:0] a1,
input [ 4:0] a2,
input [ 4:0] a3,
output [31:0] rd0,
output [31:0] rd1,
output [31:0] rd2,
input [31:0] wd3,
input we3
);
reg [31:0] rf[31:0];
assign rd0 = (a0 != 0) ? rf[a0] : 32'b0;
assign rd1 = (a1 != 0) ? rf[a1] : 32'b0;
assign rd2 = (a2 != 0) ? rf[a2] : 32'b0;
always @(posedge clk) if (we3) rf[a3] <= wd3;
endmodule
| 7.126393 |
module sm_control (
input [5:0] cmdOper,
input [5:0] cmdFunk,
input aluZero,
output pcSrc,
output regDst,
output regWrite,
output aluSrc,
output [2:0] aluControl
);
wire branch;
wire condZero;
assign pcSrc = branch & (aluZero == condZero);
// cmdOper values
localparam C_SPEC = 6'b000000, // Special instructions (depends on cmdFunk field)
C_ADDIU = 6'b001001, // I-type, Integer Add Immediate Unsigned
// Rd = Rs + Immed
C_BEQ = 6'b000100, // I-type, Branch On Equal
// if (Rs == Rt) PC += (int)offset
C_LUI = 6'b001111, // I-type, Load Upper Immediate
// Rt = Immed << 16
C_BNE = 6'b000101; // I-type, Branch on Not Equal
// if (Rs != Rt) PC += (int)offset
//C_MUL = 6'b011100;
// cmdFunk values
localparam F_ADDU = 6'b100001, // R-type, Integer Add Unsigned
// Rd = Rs + Rt
F_OR = 6'b100101, // R-type, Logical OR
// Rd = Rs | Rt
F_SRL = 6'b000010, // R-type, Shift Right Logical
// Rd = Rs∅ >> shift
F_SLTU = 6'b101011, // R-type, Set on Less Than Unsigned
// Rd = (Rs∅ < Rt∅) ? 1 : 0
F_SUBU = 6'b100011, // R-type, Unsigned Subtract
// Rd = Rs – Rt
F_ANY = 6'b??????;
reg [7:0] conf;
assign {branch, condZero, regDst, regWrite, aluSrc, aluControl} = conf;
always @(*) begin
casez ({
cmdOper, cmdFunk
})
default: conf = 8'b00;
{C_SPEC, F_ADDU} : conf = 8'b00110000;
{C_SPEC, F_OR} : conf = 8'b00110001;
{C_ADDIU, F_ANY} : conf = 8'b00011000;
{C_BEQ, F_ANY} : conf = 8'b11000000;
{C_LUI, F_ANY} : conf = 8'b00011010;
{C_SPEC, F_SRL} : conf = 8'b00110011;
{C_SPEC, F_SLTU} : conf = 8'b00110100;
{C_BNE, F_ANY} : conf = 8'b10000000;
{C_SPEC, F_SUBU} : conf = 8'b00110101;
endcase
end
endmodule
| 7.251592 |
module sm_alu (
input [31:0] srcA,
input [31:0] srcB,
input [ 2:0] oper,
input [ 4:0] shift,
output zero,
output reg [31:0] result
);
localparam ALU_ADD = 3'b000,
ALU_OR = 3'b001,
ALU_LUI = 3'b010,
ALU_SRL = 3'b011,
ALU_SLTU = 3'b100,
ALU_SUBU = 3'b101;
always @(*) begin
case (oper)
default: result = srcA + srcB;
ALU_ADD: result = srcA + srcB;
//ALU_MUL : result = srcA * scrB;
ALU_OR: result = srcA | srcB;
ALU_LUI: result = (srcB << 16);
ALU_SRL: result = srcB >> shift;
ALU_SLTU: result = (srcA < srcB) ? 1 : 0;
ALU_SUBU: result = srcA - srcB;
endcase
end
assign zero = (result == 0);
endmodule
| 7.120672 |
module sm_register_file (
input clk,
input [ 4:0] a0,
input [ 4:0] a1,
input [ 4:0] a2,
input [ 4:0] a3,
output [31:0] rd0,
output [31:0] rd1,
output [31:0] rd2,
input [31:0] wd3,
input we3
);
reg [31:0] rf[31:0];
assign rd0 = (a0 != 0) ? rf[a0] : 32'b0;
assign rd1 = (a1 != 0) ? rf[a1] : 32'b0;
assign rd2 = (a2 != 0) ? rf[a2] : 32'b0;
always @(posedge clk) if (we3) rf[a3] <= wd3;
endmodule
| 7.126393 |
module sm_fifoRTL (
wrClk,
rdClk,
rstSyncToWrClk,
rstSyncToRdClk,
dataIn,
dataOut,
fifoWEn,
fifoREn,
fifoFull,
fifoEmpty,
forceEmptySyncToWrClk,
forceEmptySyncToRdClk,
numElementsInFifo
);
//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
parameter FIFO_WIDTH = 8;
parameter FIFO_DEPTH = 64;
parameter ADDR_WIDTH = 6;
// Two clock domains within this module
// These ports are within 'wrClk' domain
input wrClk;
input rstSyncToWrClk;
input [FIFO_WIDTH-1:0] dataIn;
input fifoWEn;
input forceEmptySyncToWrClk;
output fifoFull;
// These ports are within 'rdClk' domain
input rdClk;
input rstSyncToRdClk;
output [FIFO_WIDTH-1:0] dataOut;
input fifoREn;
input forceEmptySyncToRdClk;
output fifoEmpty;
output [15:0] numElementsInFifo; //note that this implies a max fifo depth of 65536
wire wrClk;
wire rdClk;
wire rstSyncToWrClk;
wire rstSyncToRdClk;
wire [FIFO_WIDTH-1:0] dataIn;
reg [FIFO_WIDTH-1:0] dataOut;
wire fifoWEn;
wire fifoREn;
reg fifoFull;
reg fifoEmpty;
wire forceEmpty;
reg [15:0] numElementsInFifo;
// local registers
reg [ADDR_WIDTH:0] bufferInIndex;
reg [ADDR_WIDTH:0] bufferInIndexSyncToRdClk;
reg [ADDR_WIDTH:0] bufferOutIndex;
reg [ADDR_WIDTH:0] bufferOutIndexSyncToWrClk;
reg [ADDR_WIDTH-1:0] bufferInIndexToMem;
reg [ADDR_WIDTH-1:0] bufferOutIndexToMem;
reg [ADDR_WIDTH:0] bufferCnt;
reg fifoREnDelayed;
wire [FIFO_WIDTH-1:0] dataFromMem;
always @(posedge wrClk) begin
bufferOutIndexSyncToWrClk <= bufferOutIndex;
if (rstSyncToWrClk == 1'b1 || forceEmptySyncToWrClk == 1'b1) begin
fifoFull <= 1'b0;
bufferInIndex <= 0;
end else begin
if (fifoWEn == 1'b1) begin
bufferInIndex <= bufferInIndex + 1'b1;
end
if ((bufferOutIndexSyncToWrClk[ADDR_WIDTH-1:0] == bufferInIndex[ADDR_WIDTH-1:0]) &&
(bufferOutIndexSyncToWrClk[ADDR_WIDTH] != bufferInIndex[ADDR_WIDTH]) )
fifoFull <= 1'b1;
else fifoFull <= 1'b0;
end
end
always @(bufferInIndexSyncToRdClk or bufferOutIndex)
bufferCnt <= bufferInIndexSyncToRdClk - bufferOutIndex;
always @(posedge rdClk) begin
numElementsInFifo <= {
{16 - ADDR_WIDTH - 1{1'b0}}, bufferCnt
}; //pad bufferCnt with leading zeroes
bufferInIndexSyncToRdClk <= bufferInIndex;
if (rstSyncToRdClk == 1'b1 || forceEmptySyncToRdClk == 1'b1) begin
fifoEmpty <= 1'b1;
bufferOutIndex <= 0;
fifoREnDelayed <= 1'b0;
end else begin
fifoREnDelayed <= fifoREn;
if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
dataOut <= dataFromMem;
bufferOutIndex <= bufferOutIndex + 1'b1;
end
if (bufferInIndexSyncToRdClk == bufferOutIndex) fifoEmpty <= 1'b1;
else fifoEmpty <= 1'b0;
end
end
always @(bufferInIndex or bufferOutIndex) begin
bufferInIndexToMem <= bufferInIndex[ADDR_WIDTH-1:0];
bufferOutIndexToMem <= bufferOutIndex[ADDR_WIDTH-1:0];
end
sm_dpMem_dc #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_sm_dpMem_dc (
.addrIn (bufferInIndexToMem),
.addrOut(bufferOutIndexToMem),
.wrClk (wrClk),
.rdClk (rdClk),
.dataIn (dataIn),
.writeEn(fifoWEn),
.readEn (fifoREn),
.dataOut(dataFromMem)
);
endmodule
| 7.980621 |
module sm_gpio (
//bus side
input clk,
input rst_n,
input bSel,
input [31:0] bAddr,
input bWrite,
input [31:0] bWData,
output reg [31:0] bRData,
//pin side
input [`SM_GPIO_WIDTH - 1:0] gpioInput,
output [`SM_GPIO_WIDTH - 1:0] gpioOutput
);
wire [`SM_GPIO_WIDTH - 1:0] gpioIn; // debounced input signals
wire gpioOutWe; // output Pin value write enable
wire [`SM_GPIO_WIDTH - 1:0] gpioOut; // output Pin next value
assign gpioOut = bWData[`SM_GPIO_WIDTH-1:0];
assign gpioOutWe = bSel & bWrite & (bAddr[3:0] == `SM_GPIO_REG_OUTPUT);
sm_debouncer #(
.SIZE(`SM_GPIO_WIDTH)
) debounce (
clk,
gpioInput,
gpioIn
);
sm_register_we #(
.SIZE(`SM_GPIO_WIDTH)
) r_output (
clk,
rst_n,
gpioOutWe,
gpioOut,
gpioOutput
);
localparam BLANK_WIDTH = 32 - `SM_GPIO_WIDTH;
always @(*)
case (bAddr[3:0])
default: bRData = {{BLANK_WIDTH{1'b0}}, gpioIn};
`SM_GPIO_REG_INPUT: bRData = {{BLANK_WIDTH{1'b0}}, gpioIn};
`SM_GPIO_REG_OUTPUT: bRData = {{BLANK_WIDTH{1'b0}}, gpioOut};
endcase
endmodule
| 6.836966 |
module sm_hex_display (
input [3:0] digit,
output reg [6:0] seven_segments
);
always @*
case (digit)
'h0: seven_segments = 'b1000000; // g f e d c b a
'h1: seven_segments = 'b1111001;
'h2: seven_segments = 'b0100100; // --a--
'h3: seven_segments = 'b0110000; // | |
'h4: seven_segments = 'b0011001; // f b
'h5: seven_segments = 'b0010010; // | |
'h6: seven_segments = 'b0000010; // --g--
'h7: seven_segments = 'b1111000; // | |
'h8: seven_segments = 'b0000000; // e c
'h9: seven_segments = 'b0011000; // | |
'ha: seven_segments = 'b0001000; // --d--
'hb: seven_segments = 'b0000011;
'hc: seven_segments = 'b1000110;
'hd: seven_segments = 'b0100001;
'he: seven_segments = 'b0000110;
'hf: seven_segments = 'b0001110;
endcase
endmodule
| 7.448726 |
module sm_hex_display_8 (
input clock,
input resetn,
input [31:0] number,
output reg [6:0] seven_segments,
output reg dot,
output reg [7:0] anodes
);
function [6:0] bcd_to_seg(input [3:0] bcd);
case (bcd)
'h0: bcd_to_seg = 'b1000000; // g f e d c b a
'h1: bcd_to_seg = 'b1111001;
'h2: bcd_to_seg = 'b0100100; // --a--
'h3: bcd_to_seg = 'b0110000; // | |
'h4: bcd_to_seg = 'b0011001; // f b
'h5: bcd_to_seg = 'b0010010; // | |
'h6: bcd_to_seg = 'b0000010; // --g--
'h7: bcd_to_seg = 'b1111000; // | |
'h8: bcd_to_seg = 'b0000000; // e c
'h9: bcd_to_seg = 'b0011000; // | |
'ha: bcd_to_seg = 'b0001000; // --d--
'hb: bcd_to_seg = 'b0000011;
'hc: bcd_to_seg = 'b1000110;
'hd: bcd_to_seg = 'b0100001;
'he: bcd_to_seg = 'b0000110;
'hf: bcd_to_seg = 'b0001110;
endcase
endfunction
reg [2:0] i;
always @(posedge clock or negedge resetn) begin
if (!resetn) begin
seven_segments <= bcd_to_seg(0);
dot <= ~0;
anodes <= ~8'b00000001;
i <= 0;
end else begin
seven_segments <= bcd_to_seg(number[i*4+:4]);
dot <= ~0;
anodes <= ~(1 << i);
i <= i + 1;
end
end
endmodule
| 7.448726 |
module sm_matrix (
//bus side
input clk,
input rst_n,
input [31:0] bAddr, // bus address
input bWrite, // bus write enable
input [31:0] bWData, // bus write data
output [31:0] bRData, // bus read data
//pin side
input [`SM_GPIO_WIDTH - 1:0] gpioInput, // GPIO output pins
output [`SM_GPIO_WIDTH - 1:0] gpioOutput, // GPIO intput pins
output pwmOutput, // PWM output pin
output alsCS, // Ligth Sensor chip select
output alsSCK, // Light Sensor SPI clock
input alsSDO, // Light Sensor SPI data
// game side
input wire [ 0 : 0] left, // left key
input wire [ 0 : 0] right, // right key
output wire [ 0 : 0] hsync, // horizontal sync
output wire [ 0 : 0] vsync, // vertical sync
output wire [ 2 : 0] rgb // RGB
);
// bus wires
wire [ 5:0] bSel;
wire [31:0] bRData0;
wire [31:0] bRData1;
wire [31:0] bRData2;
wire [31:0] bRData3;
wire [31:0] bRData4;
// bus selector
sm_matrix_decoder decoder (
.bAddr(bAddr),
.bSel (bSel)
);
//bus read data mux
sm_matrix_mux mux (
.bSel(bSel),
.out (bRData),
.in0 (bRData0),
.in1 (bRData1),
.in2 (bRData2),
.in3 (bRData3),
.in4 (bRData4), //reserved
.in5 (32'b0) //reserved
);
// data memory
wire bWrite0 = bWrite & bSel[0];
sm_ram data_ram (
.clk(clk),
.a (bAddr),
.we (bWrite0),
.wd (bWData),
.rd (bRData0)
);
// GPIO
sm_gpio gpio (
.clk (clk),
.rst_n (rst_n),
.bSel (bSel[1]),
.bAddr (bAddr),
.bWrite (bWrite),
.bWData (bWData),
.bRData (bRData1),
.gpioInput (gpioInput),
.gpioOutput(gpioOutput)
);
// PWM
sm_pwm pwm (
.clk (clk),
.rst_n (rst_n),
.bSel (bSel[2]),
.bAddr (bAddr),
.bWrite (bWrite),
.bWData (bWData),
.bRData (bRData2),
.pwmOutput(pwmOutput)
);
// ALS
sm_als als (
.clk (clk),
.rst_n(rst_n),
.cs (alsCS),
.sck (alsSCK),
.sdo (alsSDO),
.value(bRData3)
);
racing_game_cpu_top racing_game_cpu_top_0 (
// clock and reset
.clk (clk), // clock
.reset (~rst_n), // reset
// cpu side
.bSel (bSel[4]), // select
.bAddr (bAddr), // address
.bWrite(bWrite), // write enable
.bWData(bWData), // write data
.bRData(bRData4), // read data
// game side
.left (left), // left key
.right (right), // right key
.hsync (hsync), // horizontal sync
.vsync (vsync), // vertical sync
.rgb (rgb) // RGB
);
endmodule
| 6.69617 |
module sm_matrix_decoder (
input [31:0] bAddr,
output [ 5:0] bSel
);
// Decode based on most significant bits of the address
// RAM 0x00000000 - 0x00003fff
assign bSel[0] = (bAddr[15:14] == `SM_RAM_ADDR_MATCH);
// GPIO 0x00007f00 - 0x00007f0f
assign bSel[1] = (bAddr[15:4] == `SM_GPIO_ADDR_MATCH);
// PWM 0x00007f10 - 0x00007f1f
assign bSel[2] = (bAddr[15:4] == `SM_PWM_ADDR_MATCH);
// ALS 0x00007f20 - 0x00007f2f
assign bSel[3] = (bAddr[15:4] == `SM_ALS_ADDR_MATCH);
// RACING 0x00008000 - 0x000080ff
assign bSel[4] = (bAddr[15:8] == `SM_RACING_ADDR_MATCH);
assign bSel[5] = 1'b0; // reserved
endmodule
| 6.658731 |
module sm_matrix_mux (
input [5:0] bSel,
output reg [31:0] out,
input [31:0] in0,
input [31:0] in1,
input [31:0] in2,
input [31:0] in3,
input [31:0] in4,
input [31:0] in5
);
always @*
casez (bSel)
default: out = in0;
6'b?????1: out = in0;
6'b????10: out = in1;
6'b???100: out = in2;
6'b??1000: out = in3;
6'b?10000: out = in4;
6'b100000: out = in5;
endcase
endmodule
| 7.055001 |
module sm_para_1 (
nrst,
clk,
i1,
i2,
o1,
o2,
err
);
input nrst;
input clk;
input i1;
input i2;
output o1;
output o2;
output err;
reg o1;
reg o2;
reg err;
reg [2:0] cs; // current state
parameter [2:0] // one hot with zero idle
IDLE = 3'b000, S1 = 3'b001, S2 = 3'b010, ERROR = 3'b100;
//
// 1 always block to describe state transition, state output and
// state transiton condition
//
always @(posedge clk or negedge nrst) begin
if (!nrst) begin
cs <= IDLE;
{o1, o2, err} <= 3'b000;
end else begin
case (cs)
IDLE: begin
if (~i1) begin
{o1, o2, err} <= 3'b000;
cs <= IDLE;
end
if (i1 && i2) begin
{o1, o2, err} <= 3'b100;
cs <= S1;
end
if (i1 && ~i2) begin
{o1, o2, err} <= 3'b111;
cs <= ERROR;
end
end
S1: begin
if (~i2) begin
{o1, o2, err} <= 3'b100;
cs <= S1;
end
if (i2 && i1) begin
{o1, o2, err} <= 3'b010;
cs <= S2;
end
if (i2 && (~i1)) begin
{o1, o2, err} <= 3'b111;
cs <= ERROR;
end
end
S2: begin
if (i2) begin
{o1, o2, err} <= 3'b010;
cs <= S2;
end
if (~i2 && i1) begin
{o1, o2, err} <= 3'b000;
cs <= IDLE;
end
if (~i2 && (~i1)) begin
{o1, o2, err} <= 3'b111;
cs <= ERROR;
end
end
ERROR: begin
if (i1) begin
{o1, o2, err} <= 3'b111;
cs <= ERROR;
end
if (~i1) begin
{o1, o2, err} <= 3'b000;
cs <= IDLE;
end
end
endcase
end
end
endmodule
| 6.91306 |
module sm_para_1_tb ();
reg t_clk;
reg t_nrst;
reg t_i1;
reg t_i2;
wire t_o1;
wire t_o2;
wire t_err;
// sm_para_1
sm_para_1 dut (
.clk (t_clk),
.nrst(t_nrst),
.i1 (t_i1),
.i2 (t_i2),
.o1 (t_o1),
.o2 (t_o2),
.err (t_err)
);
//Produce the clock
initial begin
t_clk = 0;
end
always #10 t_clk = ~t_clk;
//Generates a reset signal and the falling edge is effective
initial begin
t_nrst = 1;
@(posedge t_clk);
t_nrst = 0;
@(posedge t_clk);
t_nrst = 1;
end
//Control signal
initial begin
t_i1 = 1;
t_i2 = 0;
#20;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 0;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 0;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 0;
#12 t_i1 = 0;
t_i2 = 0;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 0;
#12 $finish;
end
endmodule
| 6.589342 |
module sm_para_1_var (
nrst,
clk,
i1,
i2,
o1,
o2,
err
);
input nrst;
input clk;
input i1;
input i2;
output o1;
output o2;
output err;
reg o1;
reg o2;
reg err;
reg [2:0] cs; // current state
parameter [2:0] // one hot with zero idle
IDLE = 3'b000, S1 = 3'b001, S2 = 3'b010, ERROR = 3'b100;
//
// 1 always block to describe state transition, state output and
// state transiton condition
//
always @(posedge clk or negedge nrst) begin
if (!nrst) begin
cs <= IDLE;
end else begin
case (cs)
IDLE: begin
if (~i1) begin
cs <= IDLE;
end
if (i1 && i2) begin
cs <= S1;
end
if (i1 && ~i2) begin
cs <= ERROR;
end
end
S1: begin
if (~i2) begin
cs <= S1;
end
if (i2 && i1) begin
cs <= S2;
end
if (i2 && (~i1)) begin
cs <= ERROR;
end
end
S2: begin
if (i2) begin
cs <= S2;
end
if (~i2 && i1) begin
cs <= IDLE;
end
if (~i2 && (~i1)) begin
cs <= ERROR;
end
end
ERROR: begin
if (i1) begin
cs <= ERROR;
end
if (~i1) begin
cs <= IDLE;
end
end
endcase
end
end
always @(posedge clk or negedge nrst) begin
if (!nrst) begin
{o1, o2, err} <= 3'b000;
end else begin
case (cs)
IDLE: begin
if (~i1) begin
{o1, o2, err} <= 3'b000;
end
if (i1 && i2) begin
{o1, o2, err} <= 3'b100;
end
if (i1 && ~i2) begin
{o1, o2, err} <= 3'b111;
end
end
S1: begin
if (~i2) begin
{o1, o2, err} <= 3'b100;
end
if (i2 && i1) begin
{o1, o2, err} <= 3'b010;
end
if (i2 && (~i1)) begin
{o1, o2, err} <= 3'b111;
end
end
S2: begin
if (i2) begin
{o1, o2, err} <= 3'b010;
end
if (~i2 && i1) begin
{o1, o2, err} <= 3'b000;
end
if (~i2 && (~i1)) begin
{o1, o2, err} <= 3'b111;
end
end
ERROR: begin
if (i1) begin
{o1, o2, err} <= 3'b111;
end
if (~i1) begin
{o1, o2, err} <= 3'b000;
end
end
endcase
end
end
endmodule
| 6.636188 |
module sm_para_1_var_tb ();
reg t_clk;
reg t_nrst;
reg t_i1;
reg t_i2;
wire t_o1;
wire t_o2;
wire t_err;
// sm_para_1_var
sm_para_1_var dut (
.clk (t_clk),
.nrst(t_nrst),
.i1 (t_i1),
.i2 (t_i2),
.o1 (t_o1),
.o2 (t_o2),
.err (t_err)
);
//Produce the clock
initial begin
t_clk = 0;
end
always #10 t_clk = ~t_clk;
//Generates a reset signal and the falling edge is effective
initial begin
t_nrst = 1;
@(posedge t_clk);
t_nrst = 0;
@(posedge t_clk);
t_nrst = 1;
end
//Control signal
initial begin
t_i1 = 1;
t_i2 = 0;
#20;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 0;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 0;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 0;
#12 t_i1 = 0;
t_i2 = 0;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 0;
#12 $finish;
end
endmodule
| 6.636188 |
module sm_para_2 (
nrst,
clk,
i1,
i2,
o1,
o2,
err
);
input nrst;
input clk;
input i1;
input i2;
output o1;
output o2;
output err;
reg o1;
reg o2;
reg err;
reg [2:0] cs; // current_state
reg [2:0] ns; // next state
parameter [2:0] // one hot with zero idle
IDLE = 3'b000, S1 = 3'b001, S2 = 3'b010, ERROR = 3'b100;
//
// sequential state transition
//
always @(posedge clk or negedge nrst) begin
if (!nrst) begin
cs <= IDLE;
end else begin
cs <= ns;
end
end
//
// combinational state transition condition judgment & state output
//
always @(cs or i1 or i2) begin
ns = IDLE;
{o1, o2, err} = 3'b000;
case (cs)
IDLE: begin
{o1, o2, err} = 3'b000;
if (~i1) begin
ns = IDLE;
end
if (i1 && i2) begin
ns = S1;
end
if (i1 && ~i2) begin
ns = ERROR;
end
end
S1: begin
{o1, o2, err} = 3'b100;
if (~i2) begin
ns = S1;
end
if (i2 && i1) begin
ns = S2;
end
if (i2 && (~i1)) begin
ns = ERROR;
end
end
S2: begin
{o1, o2, err} = 3'b010;
if (i2) begin
ns = S2;
end
if (~i2 && i1) begin
ns = IDLE;
end
if (~i2 && (~i1)) begin
ns = ERROR;
end
end
ERROR: begin
{o1, o2, err} = 3'b111;
if (i1) begin
ns = ERROR;
end
if (~i1) begin
ns = IDLE;
end
end
endcase
end
endmodule
| 6.763086 |
module sm_para_2_task (
nrst,
clk,
i1,
i2,
o1,
o2,
err
);
input nrst;
input clk;
input i1;
input i2;
output o1;
output o2;
output err;
reg o1;
reg o2;
reg err;
reg [2:0] cs; // current_state
reg [2:0] ns; // next state
parameter [2:0] // one hot with zero idle
IDLE = 3'b000, S1 = 3'b001, S2 = 3'b010, ERROR = 3'b100;
//
// sequential state transition
//
always @(posedge clk or negedge nrst) begin
if (!nrst) begin
cs <= IDLE;
end else begin
cs <= ns;
end
end
//
// Use output task to package state output
//
task IDLE_out;
{o1, o2, err} = 3'b000;
endtask
task S1_out;
{o1, o2, err} = 3'b100;
endtask
task S2_out;
{o1, o2, err} = 3'b010;
endtask
task ERROR_out;
{o1, o2, err} = 3'b111;
endtask
//
// combinational state transition condition judgment & state output
//
always @(cs or i1 or i2) begin
ns = IDLE;
IDLE_out;
case (cs)
IDLE: begin
IDLE_out;
if (~i1) begin
ns = IDLE;
end
if (i1 && i2) begin
ns = S1;
end
if (i1 && ~i2) begin
ns = ERROR;
end
end
S1: begin
S1_out;
if (~i2) begin
ns = S1;
end
if (i2 && i1) begin
ns = S2;
end
if (i2 && (~i1)) begin
ns = ERROR;
end
end
S2: begin
S2_out;
if (i2) begin
ns = S2;
end
if (~i2 && i1) begin
ns = IDLE;
end
if (~i2 && (~i1)) begin
ns = ERROR;
end
end
ERROR: begin
ERROR_out;
if (i1) begin
ns = ERROR;
end
if (~i1) begin
ns = IDLE;
end
end
endcase
end
endmodule
| 6.866722 |
module sm_para_2_task_tb ();
reg t_clk;
reg t_nrst;
reg t_i1;
reg t_i2;
wire t_o1;
wire t_o2;
wire t_err;
// sm_para_2_task
sm_para_2_task dut (
.clk (t_clk),
.nrst(t_nrst),
.i1 (t_i1),
.i2 (t_i2),
.o1 (t_o1),
.o2 (t_o2),
.err (t_err)
);
//Produce the clock
initial begin
t_clk = 0;
end
always #10 t_clk = ~t_clk;
//Generates a reset signal and the falling edge is effective
initial begin
t_nrst = 1;
@(posedge t_clk);
t_nrst = 0;
@(posedge t_clk);
t_nrst = 1;
end
//Control signal
initial begin
t_i1 = 1;
t_i2 = 0;
#20;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 0;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 0;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 0;
#12 t_i1 = 0;
t_i2 = 0;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 0;
#12 $finish;
end
endmodule
| 6.866722 |
module sm_para_2_task_var (
nrst,
clk,
i1,
i2,
o1,
o2,
err
);
input nrst;
input clk;
input i1;
input i2;
output o1;
output o2;
output err;
reg o1;
reg o2;
reg err;
reg [2:0] cs; // current_state
reg [2:0] ns; // next state
parameter [2:0] // one hot with zero idle
IDLE = 3'b000, S1 = 3'b001, S2 = 3'b010, ERROR = 3'b100;
//
// sequential state transition
//
always @(posedge clk or negedge nrst) begin
if (!nrst) begin
cs <= IDLE;
end else begin
cs <= ns;
end
end
//
// Use output task to package state output
//
task IDLE_out;
{o1, o2, err} = 3'b000;
endtask
task S1_out;
{o1, o2, err} = 3'b100;
endtask
task S2_out;
{o1, o2, err} = 3'b010;
endtask
task ERROR_out;
{o1, o2, err} = 3'b111;
endtask
//
// combinational state transition condition judgment
//
always @(cs or i1 or i2) begin
ns = IDLE;
case (cs)
IDLE: begin
if (~i1) begin
ns = IDLE;
end
if (i1 && i2) begin
ns = S1;
end
if (i1 && ~i2) begin
ns = ERROR;
end
end
S1: begin
if (~i2) begin
ns = S1;
end
if (i2 && i1) begin
ns = S2;
end
if (i2 && (~i1)) begin
ns = ERROR;
end
end
S2: begin
if (i2) begin
ns = S2;
end
if (~i2 && i1) begin
ns = IDLE;
end
if (~i2 && (~i1)) begin
ns = ERROR;
end
end
ERROR: begin
if (i1) begin
ns = ERROR;
end
if (~i1) begin
ns = IDLE;
end
end
endcase
end
//
// combinational state output
//
always @(cs) begin
IDLE_out;
case (cs)
IDLE: begin
IDLE_out;
end
S1: begin
S1_out;
end
S2: begin
S2_out;
end
ERROR: begin
ERROR_out;
end
endcase
end
endmodule
| 6.866722 |
module sm_para_2_task_var_tb ();
reg t_clk;
reg t_nrst;
reg t_i1;
reg t_i2;
wire t_o1;
wire t_o2;
wire t_err;
// sm_para_2_task_var
sm_para_2_task_var dut (
.clk (t_clk),
.nrst(t_nrst),
.i1 (t_i1),
.i2 (t_i2),
.o1 (t_o1),
.o2 (t_o2),
.err (t_err)
);
//Produce the clock
initial begin
t_clk = 0;
end
always #10 t_clk = ~t_clk;
//Generates a reset signal and the falling edge is effective
initial begin
t_nrst = 1;
@(posedge t_clk);
t_nrst = 0;
@(posedge t_clk);
t_nrst = 1;
end
//Control signal
initial begin
t_i1 = 1;
t_i2 = 0;
#20;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 0;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 0;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 0;
#12 t_i1 = 0;
t_i2 = 0;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 0;
#12 $finish;
end
endmodule
| 6.866722 |
module sm_para_3 (
nrst,
clk,
i1,
i2,
o1,
o2,
err
);
input nrst;
input clk;
input i1;
input i2;
output o1;
output o2;
output err;
reg o1;
reg o2;
reg err;
reg [2:0] cs; // current_state
reg [2:0] ns; // next state
parameter [2:0] // one hot with zero idle
IDLE = 3'b000, S1 = 3'b001, S2 = 3'b010, ERROR = 3'b100;
//
// 1st always block, sequential state transition
//
always @(posedge clk or negedge nrst) begin
if (!nrst) begin
cs <= IDLE;
end else begin
cs <= ns;
end
end
//
// 2nd always block, combinational state output
//
always @(cs or i1 or i2) begin
ns = IDLE;
case (cs)
IDLE: begin
if (~i1) begin
ns = IDLE;
end
if (i1 && i2) begin
ns = S1;
end
if (i1 && ~i2) begin
ns = ERROR;
end
end
S1: begin
if (~i2) begin
ns = S1;
end
if (i2 && i1) begin
ns = S2;
end
if (i2 && (~i1)) begin
ns = ERROR;
end
end
S2: begin
if (i2) begin
ns = S2;
end
if (~i2 && i1) begin
ns = IDLE;
end
if (~i2 && (~i1)) begin
ns = ERROR;
end
end
ERROR: begin
if (i1) begin
ns = ERROR;
end
if (~i1) begin
ns = IDLE;
end
end
endcase
end
//
// 3rd always block, the sequential state/FSM output
//
always @(posedge clk or negedge nrst) begin
if (!nrst) begin
{o1, o2, err} <= 3'b000;
end else begin
case (ns)
IDLE : {o1,o2,err} <= 3'b000;
S1 : {o1,o2,err} <= 3'b100;
S2 : {o1,o2,err} <= 3'b010;
ERROR: {o1,o2,err} <= 3'b111;
endcase
end
end
endmodule
| 6.908795 |
module sm_para_3_tb ();
reg t_clk;
reg t_nrst;
reg t_i1;
reg t_i2;
wire t_o1;
wire t_o2;
wire t_err;
// sm_para_3
sm_para_3 dut (
.clk (t_clk),
.nrst(t_nrst),
.i1 (t_i1),
.i2 (t_i2),
.o1 (t_o1),
.o2 (t_o2),
.err (t_err)
);
//Produce the clock
initial begin
t_clk = 0;
end
always #10 t_clk = ~t_clk;
//Generates a reset signal and the falling edge is effective
initial begin
t_nrst = 1;
@(posedge t_clk);
t_nrst = 0;
@(posedge t_clk);
t_nrst = 1;
end
//Control signal
initial begin
t_i1 = 1;
t_i2 = 0;
#20;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 0;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 0;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 0;
#12 t_i1 = 0;
t_i2 = 0;
#12 t_i1 = 1;
t_i2 = 1;
#12 t_i1 = 1;
t_i2 = 0;
#12 $finish;
end
endmodule
| 6.647456 |
module sm_ram #(
parameter SIZE = 64
) (
input clk,
input [31:0] a,
input we,
input [31:0] wd,
output [31:0] rd
);
reg [31:0] ram[SIZE - 1:0];
assign rd = ram[a[31:2]];
always @(posedge clk) if (we) ram[a[31:2]] <= wd;
endmodule
| 7.612428 |
module sm_ram_busy #(
parameter WIDTH = 6 // memory internal bus width (determines RAM size)
) (
input clk,
input rst_n,
input [31:0] a, // address
input we, // write enable
input [31:0] wd, // write data
input valid, // read/write request
output ready, // read/write done
output [31:0] rd // read data
);
// Input data buffer
wire ibuf_we;
wire [31:0] ram_a;
wire [31:0] ram_wd;
wire ram_we;
sm_register_we #(32) r_ram_a (
clk,
rst_n,
ibuf_we,
a,
ram_a
);
sm_register_we #(32) r_ram_wd (
clk,
rst_n,
ibuf_we,
wd,
ram_wd
);
sm_register_we r_ram_we (
clk,
rst_n,
ibuf_we,
we,
ram_we
);
// Valid to Ready delay
sm_delay #(`SM_CONFIG_BUSY_RAM_DELAY) dly (
.clk (clk),
.rst_n(rst_n),
.valid(valid),
.ready(ready),
.start(ibuf_we)
);
// Requested Memory
wire [31:0] ram_rd;
sm_ram #(WIDTH) ram (
.clk(clk),
.a (ram_a),
.we (ram_we),
.wd (ram_wd),
.rd (ram_rd)
);
`ifdef SIMULATION
assign rd = ready & ~ram_we ? ram_rd : 32'bx;
`else
assign rd = ram_rd;
`endif
endmodule
| 8.36364 |
module sm_delay #(
parameter DELAY = 2 // busy delay, from 0 to 255
) (
input clk,
input rst_n,
input valid, // read/write request
output ready, // read/write done
output start // work started strobe
);
localparam EFFECTIVE_DELAY = (DELAY > 255) ? 255 : DELAY;
wire [7:0] delay;
wire delay_min = (delay == 0);
wire delay_max = (delay == EFFECTIVE_DELAY);
wire [7:0] delay_next = delay_max ? 0 : delay_min & ~valid ? 0 : delay + 1;
sm_register_c #(8) r_delay (
clk,
rst_n,
delay_next,
delay
);
assign ready = delay_min;
assign start = delay_min & valid;
endmodule
| 6.99741 |
module sm_ram_outbuf #(
parameter WIDTH = 6 // memory internal bus width (determines RAM size)
) (
input clk,
input rst_n,
input [31:0] a, // address
input we, // write enable
input [31:0] wd, // write data
input valid, // read/write request
output ready, // read/write done
output [31:0] rd // read data
);
wire [31:0] ram_rd;
sm_ram #(WIDTH) ram (
.clk(clk),
.a (a),
.we (we),
.wd (wd),
.rd (ram_rd)
);
assign ready = 1'b1;
sm_register_we #(32) r_ram_rd (
clk,
rst_n,
valid,
ram_rd,
rd
);
endmodule
| 8.042476 |
module sm_register (
input clk,
input rst,
input [31 : 0] d,
output reg [31 : 0] q
);
always @(posedge clk or negedge rst)
if (~rst) q <= 32'b0;
else q <= d;
endmodule
| 7.145181 |
module sm_register_we (
input clk,
input rst,
input we,
input [31 : 0] d,
output reg [31 : 0] q
);
always @(posedge clk or negedge rst)
if (~rst) q <= 32'b0;
else if (we) q <= d;
endmodule
| 7.722957 |
module sm_rom #(
parameter SIZE = 64
) (
input [31:0] a,
output [31:0] rd
);
reg [31:0] rom[SIZE - 1:0];
assign rd = rom[a];
initial begin
$readmemh("program.hex", rom);
end
endmodule
| 8.636473 |
module sm_RxFifo (
busClk,
spiSysClk,
rstSyncToBusClk,
rstSyncToSpiClk,
fifoWEn,
fifoFull,
busAddress,
busWriteEn,
busStrobe_i,
busFifoSelect,
busDataIn,
busDataOut,
fifoDataIn
);
//FIFO_DEPTH = 2^ADDR_WIDTH
parameter FIFO_DEPTH = 64;
parameter ADDR_WIDTH = 6;
input busClk;
input spiSysClk;
input rstSyncToBusClk;
input rstSyncToSpiClk;
input fifoWEn;
output fifoFull;
input [2:0] busAddress;
input busWriteEn;
input busStrobe_i;
input busFifoSelect;
input [7:0] busDataIn;
output [7:0] busDataOut;
input [7:0] fifoDataIn;
wire busClk;
wire spiSysClk;
wire rstSyncToBusClk;
wire rstSyncToSpiClk;
wire fifoWEn;
wire fifoFull;
wire [2:0] busAddress;
wire busWriteEn;
wire busStrobe_i;
wire busFifoSelect;
wire [7:0] busDataIn;
wire [7:0] busDataOut;
wire [7:0] fifoDataIn;
//internal wires and regs
wire [7:0] dataFromFifoToBus;
wire fifoREn;
wire forceEmptySyncToBusClk;
wire forceEmptySyncToSpiClk;
wire [15:0] numElementsInFifo;
wire fifoEmpty; //not used
sm_fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_sm_fifo (
.wrClk(spiSysClk),
.rdClk(busClk),
.rstSyncToWrClk(rstSyncToSpiClk),
.rstSyncToRdClk(rstSyncToBusClk),
.dataIn(fifoDataIn),
.dataOut(dataFromFifoToBus),
.fifoWEn(fifoWEn),
.fifoREn(fifoREn),
.fifoFull(fifoFull),
.fifoEmpty(fifoEmpty),
.forceEmptySyncToWrClk(forceEmptySyncToSpiClk),
.forceEmptySyncToRdClk(forceEmptySyncToBusClk),
.numElementsInFifo(numElementsInFifo)
);
sm_RxfifoBI u_sm_RxfifoBI (
.address(busAddress),
.writeEn(busWriteEn),
.strobe_i(busStrobe_i),
.busClk(busClk),
.spiSysClk(spiSysClk),
.rstSyncToBusClk(rstSyncToBusClk),
.fifoSelect(busFifoSelect),
.fifoDataIn(dataFromFifoToBus),
.busDataIn(busDataIn),
.busDataOut(busDataOut),
.fifoREn(fifoREn),
.forceEmptySyncToBusClk(forceEmptySyncToBusClk),
.forceEmptySyncToSpiClk(forceEmptySyncToSpiClk),
.numElementsInFifo(numElementsInFifo)
);
endmodule
| 7.12044 |
module sm_sdram_controller #(
parameter CAS_LATENCY = 3,
parameter INIT_CYCL = 100
) (
// control signals
input clkIn,
input rst_n,
input cs,
input we,
output reg re,
output reg ready,
input [ 5:0] a, // row address
input [31:0] wd,
output [31:0] rd,
// sdram signals
output sd_clk,
output sd_cke,
output sd_cs,
output sd_we,
output sd_cas,
output sd_ras,
output sd_ldqm,
output sd_udqm,
output [ 1:0] sd_bs, // bank address
output reg [11:0] s_a,
inout [15:0] s_dq
);
localparam CMD_CYCL = 5;
assign sd_clk = clkIn;
assign sd_cke = `HIGHT;
assign sd_bs = 2'b01;
reg [4:0] command;
reg [15:0] wdata, rdata;
reg [31:0] wmem, rmem;
reg we_state;
reg [3:0] iter, cl, end_cycl;
assign s_dq = we_state ? wdata : `UNDEF16;
assign rd = rmem;
reg init;
initial begin
initialize;
load_register_mode;
end
always @(posedge clkIn) begin
if (~rst_n) begin
initialize;
end else if (cs & ~init) begin
ready = `LOW;
if (we && iter == 4'h0) begin
wmem = wd;
we_state = `HIGHT;
end
case (iter)
4'h0: command = `CMD_ACTIV;
4'h1: command = `CMD_ANOP;
4'h2: command = we_state ? `CMD_WRITE : `CMD_READ;
4'h5: command = `CMD_PRECH;
default: command = `CMD_NOP;
endcase
if (command == `CMD_ACTIV) end_cycl = we ? CMD_CYCL : CMD_CYCL + CAS_LATENCY;
iter = iter == end_cycl ? 4'h0 : we_state && iter == 4'h3 ? 4'h5 : iter + 4'h1;
if (we_state) begin
wdata = command == `CMD_WRITE ? wmem[15:0] : command == `CMD_NOP ? wmem[31:16] : 16'b0;
cl = cl == CAS_LATENCY + 1 || cl == CAS_LATENCY + 2 ? cl + 3'b001 : 3'b000;
end else begin
if (command == `CMD_READ) cl = 3'b0;
else if (command == `CMD_ACTIV || command[3:0] == `CMD_NOP || command == `CMD_PRECH)
cl = cl + 3'b001;
end
rmem[31:16] = cl == CAS_LATENCY + 3 ? s_dq : `UNDEF16;
rmem[15:0] = cl == CAS_LATENCY + 3 ? rdata : `UNDEF16;
rdata = cl == CAS_LATENCY + 1 || cl == CAS_LATENCY + 2 ? s_dq : `UNDEF16;
if (command == `CMD_ACTIV) begin
s_a[11:6] = 6'b0;
s_a[5:0] = a[5:0];
end else if (command != `CMD_PRECH) begin
s_a[11:1] = 10'h0;
s_a[0] = command == `CMD_NOP ? 1'h1 : 1'h0;
end
re = cl == CAS_LATENCY + 3 ? `HIGHT : `LOW;
if (we_state && command == `CMD_ACTIV) ready = `LOW;
if ((we_state && command == `CMD_PRECH) || cl == CAS_LATENCY + 3) begin
we_state = `LOW;
ready = `HIGHT;
s_a = 12'b0;
wmem = `UNDEF32;
wdata = `UNDEF16;
end
end
end
assign sd_cs = command[3];
assign sd_ras = command[2];
assign sd_cas = command[1];
assign sd_we = command[0];
assign sd_ldqm = `LOW;
assign sd_udqm = `LOW;
task initialize;
begin
init = `HIGHT;
command = `CMD_NOP;
wmem = `UNDEF32;
rmem = `UNDEF32;
s_a = 12'b0;
wdata = `UNDEF16;
rdata = `UNDEF16;
we_state = `LOW;
re = `LOW;
iter = 4'h0;
cl = 3'b0;
ready = `LOW;
#INIT_CYCL init = `LOW;
end
endtask
task load_register_mode;
begin
init = `HIGHT;
repeat (1) @(posedge clkIn);
command = `CMD_MODE;
s_a = `REG_MODE;
repeat (1) @(posedge clkIn);
ready = `HIGHT;
command = `CMD_NOP;
s_a = 12'b0;
iter = 4'h0;
cl = 3'b0;
init = `LOW;
end
endtask
endmodule
| 7.191065 |
module sm_status (
input clk,
input rst_n,
input run,
output s00_idle, // idle status
output s01_ife0, // instruction fetch 0
output s02_ife1, // instruction fetch 1
output s03_exec, // execution
output s04_wtbk // data writeback
);
// status counter
reg [2:0] status_cntr;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) status_cntr <= 3'd0;
else if ((status_cntr == 3'd0) && run) status_cntr <= 3'd1;
else if (status_cntr == 3'd4) status_cntr <= 3'd0;
else if (status_cntr >= 3'd1) status_cntr <= status_cntr + 3'd1;
end
// status decoder
function [4:0] status_decoder;
input [2:0] status_cntr;
begin
case (status_cntr)
3'd0: status_decoder = 5'b0_0001;
3'd1: status_decoder = 5'b0_0010;
3'd2: status_decoder = 5'b0_0100;
3'd3: status_decoder = 5'b0_1000;
3'd4: status_decoder = 5'b1_0000;
default: status_decoder = 5'd0;
endcase
end
endfunction
wire [4:0] decode_bits;
assign decode_bits = status_decoder(status_cntr);
assign s00_idle = decode_bits[0];
assign s01_ife0 = decode_bits[1];
assign s02_ife1 = decode_bits[2];
assign s03_exec = decode_bits[3];
assign s04_wtbk = decode_bits[4];
endmodule
| 7.417774 |
module SM_tb;
// parameter
parameter cyc = 120;
// I/O
reg clk, rst_n;
reg [12:0] instr;
wire fin;
wire d_valid;
wire [9:0] pc;
wire [19:0] out_data;
wire [2:0] err_code;
// memeory and answer
reg [35:0] MEM[0:1024];
// regs
reg [35:0] data;
reg [10:0] maxSize;
reg [9:0] result;
reg correct;
SM SM_0 (
.clk(clk),
.rst_n(rst_n),
.instr(instr),
.pc(pc),
.d_valid(d_valid),
.out_data(out_data),
.err_code(err_code),
.fin(fin)
);
always #(cyc / 2) clk = ~clk;
initial begin
`ifdef SDF
$sdf_annotate(`SDFFILE, SM_0);
$fsdbDumpfile("SM_syn.fsdb");
`else
$fsdbDumpfile("SM.fsdb");
`endif
$fsdbDumpvars;
end
initial begin
end
initial begin
`ifdef TEST1
$readmemb(`MEM1, MEM);
`elsif TEST2
$readmemb(`MEM2, MEM);
`elsif BON
$readmemb(`MEM_bon, MEM);
`else
$readmemb(`MEM3, MEM);
`endif
$display(" ");
// init values
rst_n = 1'b1;
clk = 1'b0;
instr = 'hz;
correct = 1'b1;
maxSize = 11'd1024;
result = 10'd0;
// init MO
@(negedge clk) rst_n = 1'b0;
#(cyc) rst_n = 1'b1;
//000_0000000001_000_xxxxxxxxxx_xxxxxxxxxx(...) -> instr(push 1), err_code, out_data(don't care)
//MEM = (36 bits) = (13 bits instr) + (3 bits err_code) + (20 bits out_data)
while (fin === 0) begin
if (pc < maxSize) begin
//negedge clk
data = MEM[pc];
instr = data[35:23];
#(cyc / 2);
if (instr[12:10] === `ADD || instr[12:10] === `SUB || instr[12:10] === `MUL) begin
if (d_valid === 1'b1 && out_data === data[19:0] && err_code === data[22:20]) begin
$display("GET ! pc = %d , your err_code = %d , answer err_code = %d", pc, err_code,
data[22:20]);
$display(" pc = %d , your out_data = %d , answer out_data = %d", pc,
$signed(out_data), $signed(data[19:0]));
result = result + 1'b1;
end
else if(d_valid === 1'b1 && (out_data !== data[19:0] || err_code !== data[22:20]))begin
$display("WA ! pc = %d , your err_code = %d , answer err_code = %d", pc, err_code,
data[22:20]);
$display(" pc = %d , your out_data = %d , answer out_data = %d", pc,
$signed(out_data), $signed(data[19:0]));
correct = 1'b0;
end
end else if (instr[12:10] === `PUSH) begin
//err_code
if (err_code !== data[22:20] && d_valid) begin
$display("WA ! pc = %d , your err_code = %d , answer err_code = %d", pc, err_code,
data[22:20]);
correct = 1'b0;
end else if (err_code === data[22:20] && d_valid) begin
$display("GET ! pc = %d , your err_code = %d , answer err_code = %d", pc, err_code,
data[22:20]);
result = result + 1'b1;
end
end else begin
if (err_code !== data[22:20] && d_valid) begin
$display("WA ! pc = %d , your err_code = %d , answer err_code = %d", pc, err_code,
data[22:20]);
correct = 1'b0;
end else if (err_code === data[22:20] && d_valid) begin
$display("GET ! pc = %d , your err_code = %d , answer err_code = %d", pc, err_code,
data[22:20]);
result = result + 1'b1;
end
end
end else begin
data = 'hz;
instr = data[35:23];
end
@(negedge clk);
end
//display
$display(" ");
//MEM[1023] = (36 bits) = (13 bits instr) + (23 bits result)
if (correct == 1'b1 && result != MEM[1024][22:0]) begin
$display("WRONG ANSWER!, Please Check Your d_vlid Signal");
end else if (correct == 1'b1 && result == MEM[1024][22:0]) begin
$display("Correct Answer!!");
end else begin
$display("WRONG ANSWER QAQ");
end
$display(" ");
$finish;
end
initial begin
#`TIMEOUT;
$display("-----------------------------------------------------\n");
$display("Error!!! Somethings' wrong with your code ...!\n");
$display("-------------------------FAIL------------------------\n");
$display("-----------------------------------------------------\n");
$finish;
end
endmodule
| 7.260833 |
module
module sm_top
(
input clkIn,
input rst_n,
input [ 3:0 ] clkDevide,
input clkEnable,
output clk,
input [ 4:0 ] regAddr,
output [31:0 ] regData
);
//metastability input filters
wire [ 3:0 ] devide;
wire enable;
wire [ 4:0 ] addr;
sm_debouncer #(.SIZE(4)) f0(clkIn, clkDevide, devide);
sm_debouncer #(.SIZE(1)) f1(clkIn, clkEnable, enable);
sm_debouncer #(.SIZE(5)) f2(clkIn, regAddr, addr );
//cores
//clock devider
sm_clk_divider sm_clk_divider
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.devide ( devide ),
.enable ( enable ),
.clkOut ( clk )
);
//instruction memory
wire [31:0] imAddr;
wire [31:0] imData;
sm_rom reset_rom(imAddr, imData);
sm_cpu sm_cpu
(
.clk ( clk ),
.rst_n ( rst_n ),
.regAddr ( addr ),
.regData ( regData ),
.imAddr ( imAddr ),
.imData ( imData )
);
endmodule
| 6.817969 |
module sm_clk_divider #(
parameter shift = 16,
bypass = 0
) (
input clkIn,
input rst_n,
input [3:0] devide,
input enable,
output clkOut
);
wire [31:0] cntr;
wire [31:0] cntrNext = cntr + 1;
sm_register_we r_cntr (
clkIn,
rst_n,
enable,
cntrNext,
cntr
);
assign clkOut = bypass ? clkIn : cntr[shift+devide];
endmodule
| 7.194941 |
module sm_TxFifo (
busClk,
spiSysClk,
rstSyncToBusClk,
rstSyncToSpiClk,
fifoREn,
fifoEmpty,
busAddress,
busWriteEn,
busStrobe_i,
busFifoSelect,
busDataIn,
busDataOut,
fifoDataOut
);
//FIFO_DEPTH = 2^ADDR_WIDTH
parameter FIFO_DEPTH = 64;
parameter ADDR_WIDTH = 6;
input busClk;
input spiSysClk;
input rstSyncToBusClk;
input rstSyncToSpiClk;
input fifoREn;
output fifoEmpty;
input [2:0] busAddress;
input busWriteEn;
input busStrobe_i;
input busFifoSelect;
input [7:0] busDataIn;
output [7:0] busDataOut;
output [7:0] fifoDataOut;
wire busClk;
wire spiSysClk;
wire rstSyncToBusClk;
wire rstSyncToSpiClk;
wire fifoREn;
wire fifoEmpty;
wire [2:0] busAddress;
wire busWriteEn;
wire busStrobe_i;
wire busFifoSelect;
wire [7:0] busDataIn;
wire [7:0] busDataOut;
wire [7:0] fifoDataOut;
//internal wires and regs
wire fifoWEn;
wire forceEmptySyncToSpiClk;
wire forceEmptySyncToBusClk;
wire [15:0] numElementsInFifo;
wire fifoFull;
sm_fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_sm_fifo (
.wrClk(busClk),
.rdClk(spiSysClk),
.rstSyncToWrClk(rstSyncToBusClk),
.rstSyncToRdClk(rstSyncToSpiClk),
.dataIn(busDataIn),
.dataOut(fifoDataOut),
.fifoWEn(fifoWEn),
.fifoREn(fifoREn),
.fifoFull(fifoFull),
.fifoEmpty(fifoEmpty),
.forceEmptySyncToWrClk(forceEmptySyncToBusClk),
.forceEmptySyncToRdClk(forceEmptySyncToSpiClk),
.numElementsInFifo(numElementsInFifo)
);
sm_TxfifoBI u_sm_TxfifoBI (
.address(busAddress),
.writeEn(busWriteEn),
.strobe_i(busStrobe_i),
.busClk(busClk),
.spiSysClk(spiSysClk),
.rstSyncToBusClk(rstSyncToBusClk),
.fifoSelect(busFifoSelect),
.busDataIn(busDataIn),
.busDataOut(busDataOut),
.fifoWEn(fifoWEn),
.forceEmptySyncToBusClk(forceEmptySyncToBusClk),
.forceEmptySyncToSpiClk(forceEmptySyncToSpiClk),
.numElementsInFifo(numElementsInFifo)
);
endmodule
| 7.082185 |
module SN74194 (
P,
Q,
DSR,
DSL,
S1,
S0,
_MR,
CLOCK
);
parameter LENGTH = 4;
input DSR, DSL, S1, S0, _MR, CLOCK;
input [LENGTH-1:0] P;
output reg [LENGTH-1:0] Q;
always @(posedge CLOCK or negedge _MR)
if (_MR == 0) Q <= 0;
else
case ({
S1, S0
})
0: Q <= Q;
1: Q <= {Q[LENGTH-2:0], DSR};
2: Q <= {DSL, Q[LENGTH-1:1]};
3: Q <= P;
endcase
endmodule
| 7.023791 |
module SN74194v1 (
P,
Q,
DSR,
DSL,
S1,
S0,
_MR,
CLOCK
);
parameter LENGTH = 4;
input DSR, DSL, S1, S0, _MR, CLOCK;
input [LENGTH-1:0] P;
output reg [LENGTH-1:0] Q;
reg [LENGTH-1:0] NextQ;
//reg Q; //A warning will appear if dimension is not given.
// An error will occur if posedge _MR is used because _MR is active low
//always @ (posedge CLOCK or posedge _MR)
always @(posedge CLOCK or negedge _MR)
if (_MR == 0) Q <= 0;
else Q <= NextQ;
//activity list does not include the clock signal
always @(Q or S1 or S0 or DSR or DSL or P)
case ({
S1, S0
})
0: NextQ <= Q; // hold
1: NextQ <= {Q[LENGTH-2:0], DSR}; // shift left
2: NextQ <= {DSL, Q[LENGTH-1:1]}; // shift right
3: NextQ <= P; // parallel load
endcase
endmodule
| 7.509644 |
module SN74194v2 (
P,
Q,
DSR,
DSL,
S1,
S0,
_MR,
CLOCK
);
parameter LENGTH = 4;
input DSR, DSL, S1, S0, _MR, CLOCK;
input [LENGTH-1:0] P;
output reg [LENGTH-1:0] Q;
//reg Q; //A warning will appear if dimension is not given.
// An error will occur if posedge _MR is used because _MR is active low
//always @ (posedge CLOCK or posedge _MR)
always @(posedge CLOCK or negedge _MR)
if (_MR == 0) Q <= 0;
else
case ({
S1, S0
})
0: Q <= Q; // hold
1: Q <= {Q[LENGTH-2:0], DSR}; // shift left
2: Q <= {DSL, Q[LENGTH-1:1]}; // shift right
3: Q <= P; // parallel load
endcase
endmodule
| 7.299687 |
module sn7473 (
input mclk,
input mrst,
input clk_n,
input j,
input k,
input clr_n,
output reg q,
output reg q_n
);
reg q_int;
wire clk_n_pedge, clk_n_nedge, clk_n_f;
wire clr_n_pedge, clr_n_f;
wire j_f, k_f;
/* verilator lint_off PINMISSING */
gfilt filt_clk_n (
.clk(mclk),
.rst(mrst),
.in(clk_n),
.pedge(clk_n_pedge),
.nedge(clk_n_nedge),
.filt(clk_n_f)
);
gfilt filt_clr_n (
.clk(mclk),
.rst(mrst),
.in(clr_n),
.pedge(clr_n_pedge),
.filt(clr_n_f)
);
gfilt filt_j (
.clk (mclk),
.rst (mrst),
.in (j),
.filt(j_f)
);
gfilt filt_k (
.clk (mclk),
.rst (mrst),
.in (k),
.filt(k_f)
);
/* lint_on */
always @(posedge mclk) begin
if (!clr_n_f) begin
q_int <= 1'b0;
q <= 1'b0;
q_n <= 1'b1;
end else if (clk_n_pedge || (clk_n_f && clr_n_pedge)) begin
if (j_f && !k_f) q_int <= 1'b1;
else if (!j_f && k_f) q_int <= 1'b0;
else if (j_f && k_f) q_int <= !q_int;
end else if (clk_n_nedge) begin
q <= q_int;
q_n <= !q_int;
end
end
/*
reg q_int;
reg old_clk_n;
reg old_j, old_old_j;
reg old_k, old_old_k;
reg old_clr_n;
always @(posedge mclk) begin
old_clr_n <= clr_n;
old_clk_n <= clk_n;
old_j <= j;
old_old_j <= old_j;
old_k <= k;
old_old_k <= old_k;
if (!clr_n && !old_clr_n) begin
q_int <= 1'b0;
q <= 1'b0;
q_n <= 1'b1;
end else if ((clk_n && !old_clk_n) || (clk_n && clr_n && !old_clr_n)) begin
if (old_old_j && !old_old_k) q_int <= 1'b1;
else if (!old_old_j && old_old_k) q_int <= 1'b0;
else if (old_old_j && old_old_k) q_int <= !q_int;
end else if (!clk_n && old_clk_n) begin
q <= q_int;
q_n <= !q_int;
end
end
*/
endmodule
| 6.807797 |
modules: N/A
*- Description: Implement the logic functions of a Quad 2-input AND gate
*-
*- Example of Usage:
You can assign the input and output pins of this module to the GPIOs of the STEPFPGA board
To observe the logic behavior, you may need additional components such as swiches, pushbuottons
LEDs, resistors...and build the circuit on a breadboard or other medias.
*- This code is for educational purposes only and hold no reliability for any industrial/commerical usages
*- Copyright of this code: MIT License
--------------------------------------------------------------------------------------------------- */
module sn74hc08 (pin1,pin2,pin3,pin4,pin5,pin6,pin7,pin8,
pin9,pin10,pin11,pin12,pin13,pin14);
input pin1,pin2,pin4,pin5,pin9,pin10,pin12,pin13;
output pin3,pin6,pin8,pin11;
output pin7,pin14; // connects to Vcc and GND
wire A1,B1,Y1,A2,B2,Y2,A3,B3,Y3,A4,B4,Y4;
assign A1 = pin1;
assign B1 = pin2;
assign A2 = pin4;
assign B2 = pin5;
assign A3 = pin9;
assign B3 = pin10;
assign A4 = pin12;
assign B4 = pin13;
assign pin3 = Y1;
assign pin6 = Y2;
assign pin8 = Y3;
assign pin11 = Y4;
assign pin7 = 1'b0;
assign pin14 = 1'b1;
assign Y1 = A1 & B1;
assign Y2 = A2 & B2;
assign Y3 = A3 & B3;
assign Y4 = A4 & B4;
endmodule
| 6.670404 |
modules: N/A
*- Description: Implement the logic functions of a 3-to-8 Line Decoder/Demultiplexer with Inverting Output
*-
*- Example of Usage:
You can assign the input and output pins of this module to the GPIOs of the STEPFPGA board
To observe the logic behavior, you may need additional components such as swiches, pushbuottons
LEDs, resistors...and build the circuit on a breadboard or other medias.
*- This code is for educational purposes only and hold no reliability for any industrial/commerical usages
*- Copyright of this code: MIT License
--------------------------------------------------------------------------------------------------- */
module sn74hc138 (pin1,pin2,pin3,pin4,pin5,pin6,pin7,pin8,
pin9,pin10,pin11,pin12,pin13,pin14,pin15,pin16);
input pin1,pin2,pin3; // 3 inputs corresponding to the address location
input pin4,pin5,pin6; // 3 inputs for Enable
output pin7,pin9,pin10,pin11,pin12,pin13,pin14,pin15;
output pin8,pin16; // connects to VCC and GND
// ***** intermediate signals *****
wire [2:0] a ;
reg [7:0] q ;
wire sel;
assign pin8 = 1'b0;
assign pin16 = 1'b1;
assign a = {pin3,pin2,pin1};
assign sel = (~pin4)&(~pin5)& pin6;
assign pin7 = q[7];
assign pin9 = q[6];
assign pin10 = q[5];
assign pin11 = q[4];
assign pin12 = q[3];
assign pin13 = q[2];
assign pin14 = q[1];
assign pin15 = q[0];
always@(a,sel) begin
if(!sel)
q = 8'b1111_1111;
else begin
case(a)
3'b000: q = 8'b1111_1110;
3'b001: q = 8'b1111_1101;
3'b000: q = 8'b1111_1011;
3'b000: q = 8'b1111_0111;
3'b000: q = 8'b1110_1111;
3'b000: q = 8'b1101_1111;
3'b000: q = 8'b1011_1111;
3'b000: q = 8'b0111_1111;
default:q = 8'b1111_1111;
endcase
end
end
endmodule
| 6.670404 |
modules: N/A
*- Description: Implement the logic functions of an 8-bit Parallel-load Shift Registers
*-
*- Example of Usage:
You can assign the input and output pins of this module to the GPIOs of the STEPFPGA board
To observe the logic behavior, you may need additional components such as swiches, pushbuottons
LEDs, resistors...and build the circuit on a breadboard or other medias.
*- This code is for educational purposes only and hold no reliability for any industrial/commerical usages
*- Copyright of this code: MIT License
--------------------------------------------------------------------------------------------------- */
module sn74hc165 (pin1,pin2,pin3,pin4,pin5,pin6,pin7,pin8,
pin9,pin10,pin11,pin12,pin13,pin14,pin15,pin16);
input pin3,pin4,pin5,pin6,pin11,pin12,pin13,pin14;
input pin2,pin15;
input pin1;
input pin10;
output pin8,pin16;
output pin7,pin9;
wire [7:0] data;
wire clk,load,sel;
reg [7:0] q;
assign pin8 = 1'b0;
assign pin16= 1'b1;
assign data[0]=pin11;
assign data[1]=pin12;
assign data[2]=pin13;
assign data[3]=pin14;
assign data[4]=pin3;
assign data[5]=pin4;
assign data[6]=pin5;
assign data[7]=pin6;
assign clk=pin2|pin15;
assign load=pin1;
assign pin9=q[7]; //Q
assign pin7=~q[7]; //~Q
assign sel=pin10;
always@(posedge clk or negedge load) begin
if(!load)
q<=data;
else
q<={q[6:0],sel};
end
endmodule
| 6.670404 |
modules: N/A
*- Description: Implement the logic functions of a 4-bit Binary Full Adder
*-
*- Example of Usage:
You can assign the input and output pins of this module to the GPIOs of the STEPFPGA board
To observe the logic behavior, you may need additional components such as swiches, pushbuottons
LEDs, resistors...and build the circuit on a breadboard or other medias.
*- This code is for educational purposes only and hold no reliability for any industrial/commerical usages
*- Copyright of this code: MIT License
--------------------------------------------------------------------------------------------------- */
module sn74hcf283 (pin1,pin2,pin3,pin4,pin5,pin6,pin7,pin8,
pin9,pin10,pin11,pin12,pin13,pin14,pin15,pin16);
input pin5,pin3,pin14,pin12,pin6,pin2,pin15,pin11; // two 4-bit Addends
input pin7; // Initial Carry input
output pin9; // Final Carry output
output pin8,pin16; // Connect to VCC and GND
output pin4,pin1,pin13,pin10; // 4-bit output Sum
wire [3:0] a,b,sum;
wire ci,co;
assign pin8 = 1'b0;
assign pin16 = 1'b1;
assign a[0] = pin5;
assign a[1] = pin3;
assign a[2] = pin14;
assign a[3] = pin12;
assign b[0] = pin6;
assign b[1] = pin2;
assign b[2] = pin15;
assign b[3] = pin11;
assign ci = pin7;
assign pin9 = co;
assign pin4 = sum[0];
assign pin1 = sum[1];
assign pin13 = sum[2];
assign pin10 = sum[3];
assign {co,sum} = a + b + ci;
endmodule
| 6.670404 |
modules: N/A
*- Description: Implement the logic functions of a Dual 4-Stage Binary Counter
*-
*- Example of Usage:
You can assign the input and output pins of this module to the GPIOs of the STEPFPGA board
To observe the logic behavior, you may need additional components such as swiches, pushbuottons
LEDs, resistors...and build the circuit on a breadboard or other medias.
*- This code is for educational purposes only and hold no reliability for any industrial/commerical usages
*- Copyright of this code: MIT License
--------------------------------------------------------------------------------------------------- */
module sn74hc393 (pin1,pin2,pin3,pin4,pin5,pin6,pin7,pin8,
pin9,pin10,pin11,pin12,pin13,pin14);
input pin1,pin13; // two Clock signal
input pin2,pin12; // two Clear enable signal
output pin7,pin14; // Connects to VCC and GND
output pin3,pin4,pin5,pin6,pin11,pin10,pin9,pin8; // two 4-bit Binary counter output
wire clk1,clk2,clr1,clr2;
reg [3:0] count1,count2;
assign pin7 = 1'b0;
assign pin14 = 1'b1;
assign clk1 = pin1;
assign clk2 = pin13;
assign clr1 = pin2;
assign clr2 = pin12;
assign pin3 = count1[0];
assign pin4 = count1[1];
assign pin5 = count1[2];
assign pin6 = count1[3];
assign pin11 = count2[0];
assign pin10 = count2[1];
assign pin9 = count2[2];
assign pin8 = count2[3];
always@(negedge clk1 or posedge clr1)begin
if(clr1)
count1 <= 4'b0000;
else begin
if(count1 == 4'b1111)
count1 <= 4'b0000;
else
count1 <= count1 + 1'b1;
end
end
always@(negedge clk2 or posedge clr2)begin
if(clr2)
count2 <= 4'b0000;
else begin
if(count2 == 4'b1111)
count2 <= 4'b0000;
else
count2 <= count2 + 1'b1;
end
end
endmodule
| 6.670404 |
modules: N/A
*- Description: Implement the logic functions of a Dual Positive Edge Triggered D-Flipflop
*-
*- Example of Usage:
You can assign the input and output pins of this module to the GPIOs of the STEPFPGA board
To observe the logic behavior, you may need additional components such as swiches, pushbuottons
LEDs, resistors...and build the circuit on a breadboard or other medias.
*- This code is for educational purposes only and hold no reliability for any industrial/commerical usages
*- Copyright of this code: MIT License
--------------------------------------------------------------------------------------------------- */
module sn74hc74 (pin1,pin2,pin3,pin4,pin5,pin6,pin7,pin8,
pin9,pin10,pin11,pin12,pin13,pin14);
input pin3,pin11; // 2 inputs for CLOCK
input pin1,pin13; // 2 inputs for RESET
input pin4,pin10; // 2 inputs for SET
input pin2,pin12; // 2 inputs for DATA
output pin7,pin14; // Connects to VCC and GND
output pin5,pin6,pin8,pin9;
wire clk1,clk2,reset1_n,reset2_n,set1_n,set2_n,d1,d2;
reg [1:0] q1,q2;
assign pin7 = 1'b0;
assign pin14 = 1'b1;
assign clk1 = pin3;
assign clk2 = pin11;
assign reset1_n = pin1;
assign reset2_n = pin13;
assign set1_n = pin4;
assign set2_n = pin10;
assign d1 = pin2;
assign d2 = pin12;
assign pin5 = q1[1]; //1Q
assign pin6 = q1[0]; //1Q'
assign pin9 = q2[1]; //2Q
assign pin8 = q2[0]; //2Q'
//Building the first channel of D flipflop;
always @(negedge reset1_n or negedge set1_n or posedge clk1) begin
if(reset1_n==0)
q1<=2'b01;
else if(set1_n==0)
q1<=2'b10;
else
q1<={d1,~d1};
end
//Building the second channel of D flipflop
always@(negedge reset2_n or negedge set2_n or posedge clk2) begin
if(reset2_n==0)
q2<=2'b01;
else if(set2_n==0)
q2<=2'b10;
else
q2<={d2,~d2};
end
endmodule
| 6.670404 |
module SN74LS00 (
input wire a1,
input wire b1,
output wire y1,
input wire a2,
input wire b2,
output wire y2,
input wire a3,
input wire b3,
output wire y3,
input wire a4,
input wire b4,
output wire y4
);
assign y1 = ~(a1 & b1);
assign y2 = ~(a2 & b2);
assign y3 = ~(a3 & b3);
assign y4 = ~(a4 & b4);
endmodule
| 7.006551 |
module SN74LS04 (
input wire a1,
output wire y1,
input wire a2,
output wire y2,
input wire a3,
output wire y3,
input wire a4,
output wire y4,
input wire a5,
output wire y5,
input wire a6,
output wire y6
);
assign y1 = ~a1;
assign y2 = ~a2;
assign y3 = ~a3;
assign y4 = ~a4;
assign y5 = ~a5;
assign y6 = ~a6;
endmodule
| 7.363943 |
module SN74LS07 (
input wire a1,
output wire y1,
input wire a2,
output wire y2,
input wire a3,
output wire y3,
input wire a4,
output wire y4,
input wire a5,
output wire y5,
input wire a6,
output wire y6
);
buf (y1, a1);
buf (y2, a2);
buf (y3, a3);
buf (y4, a4);
buf (y5, a5);
buf (y6, a6);
endmodule
| 6.713973 |
module SN74LS195Abehavior (
Q,
P,
Q3not,
PE,
J,
K,
CP,
MR
);
parameter LENGTH = 4;
input PE, J, K, CP, MR;
input [LENGTH-1:0] P;
output reg [LENGTH-1:0] Q;
output Q3not;
always @(posedge CP or negedge MR)
if (MR == 0) Q <= 0;
else if (PE == 0) Q <= P;
else if (PE == 1) Q <= {Q[LENGTH-2:0], (~Q[0] & J) | (Q[0] & K)};
assign Q3not = ~Q[3];
endmodule
| 7.187985 |
module SN74LS195ARelativeTime;
reg [3:0] P;
reg PE, J, K, CP, MR;
wire Q3not_gate, Q3not_behavior;
wire [3:0] Qbehavior, Qgates;
SN74LS195Agates GatesChip (
Qgates,
P,
Q3not_gate,
PE,
J,
K,
CP,
MR
);
SN74LS195Abehavior BehaviorChip (
Qbehavior,
P,
Q3not_behavior,
PE,
J,
K,
CP,
MR
);
initial begin
P = 0;
PE = 0;
J = 0;
K = 0;
CP = 0;
MR = 0;
end
always #5 CP = ~CP;
initial begin
MR = 1;
P = 4'b1010;
PE = 0;
J = 0;
K = 0;
#5; //reset
MR = 0;
P = 4'b1010;
PE = 0;
J = 0;
K = 0;
#18; //reset
MR = 1;
P = 4'b1010;
PE = 0;
J = 1;
K = 1;
#18; //parallel load
MR = 1;
P = 4'b1010;
PE = 1;
J = 1;
K = 1;
#18; //shift, set first stage
MR = 1;
P = 4'b1010;
PE = 1;
J = 0;
K = 0;
#18; //shift, reset first
MR = 1;
P = 4'b1010;
PE = 1;
J = 1;
K = 0;
#26; //shift, toggle first stage
MR = 1;
P = 4'b1010;
PE = 1;
J = 0;
K = 1;
#50; //shift, retain first stage
$stop;
end
endmodule
| 6.678164 |
modules, if separate G is needed
module sn74ls240(a, y, g_);
parameter WIDTH=4;
input [WIDTH-1:0] a;
output [WIDTH-1:0] y;
input g_;
assign y = (g_==1'b0) ? ~a : {WIDTH{1'bz}};
endmodule
| 8.240324 |
module sn74ls241 (
a1,
y1,
g1_,
a2,
y2,
g2
);
parameter WIDTH = 4;
input [WIDTH-1:0] a1, a2;
output [WIDTH-1:0] y1, y2;
input g1_, g2;
assign y1 = (g1_ == 1'b0) ? a1 : {WIDTH{1'bz}};
assign y2 = (g2 == 1'b1) ? a2 : {WIDTH{1'bz}};
endmodule
| 7.75239 |
module sn74ls244_testbench;
parameter WIDTH = 4;
reg [WIDTH-1:0] a1, a2;
reg g1_, g2;
wire [WIDTH-1:0] y1, y2;
sn74ls241 #(
.WIDTH(WIDTH)
) dut (
.a1 (a1),
.y1 (y1),
.g1_(g1_),
.a2 (a2),
.y2 (y2),
.g2 (g2)
);
`define assert(signame, signal, value) \
if (signal !== value) begin \
$display("Error: %s should be %b, but is %b", signame, signal, value); \
end
task tester;
input [80*8-1:0] descr;
input [WIDTH-1:0] a1val, a2val;
input g1val, g2val;
input [WIDTH-1:0] expecty1, expecty2;
begin
a1 <= a1val;
a2 <= a2val;
g1_ <= g1val;
g2 <= g2val;
#1 $display("%5g: %4b %4b %1b %1b | %4b %4b | %0s", $time, a1, a2, g1_, g2, y1, y2, descr);
`assert("y1", y1, expecty1);
`assert("y2", y2, expecty2);
end
endtask
initial begin
//Dump results of the simulation
$dumpfile("sn74ls244.vcd");
$dumpvars;
$display("-time: -a1- -a2- g1_ g2 | -y1- -y2- | descr");
// --a1--- --a2--- -g1_- -g2- -expy1- -expy2-
tester("tristate", 4'bxxxx, 4'bxxxx, 1'b1, 1'b0, 4'bzzzz, 4'bzzzz);
tester("load 0's", 4'b0000, 4'bxxxx, 1'b0, 1'b0, 4'b0000, 4'bzzzz);
tester("load 0's", 4'bxxxx, 4'b0000, 1'b1, 1'b1, 4'bzzzz, 4'b0000);
tester("load 1's", 4'b1111, 4'bxxxx, 1'b0, 1'b0, 4'b1111, 4'bzzzz);
tester("load 1's", 4'bxxxx, 4'b1111, 1'b1, 1'b1, 4'bzzzz, 4'b1111);
tester("load 10's", 4'b1010, 4'b0101, 1'b0, 1'b1, 4'b1010, 4'b0101);
#10 $finish;
end
endmodule
| 6.758324 |
modules, if separate G is needed
module sn74ls244(a, y, g_);
parameter WIDTH=4;
input [WIDTH-1:0] a;
output [WIDTH-1:0] y;
input g_;
assign y = (g_==1'b0) ? a : {WIDTH{1'bz}};
endmodule
| 8.240324 |
module sn74ls244_testbench;
parameter WIDTH = 8;
reg [WIDTH-1:0] a;
reg g_;
wire [WIDTH-1:0] y;
sn74ls244 #(
.WIDTH(WIDTH)
) dut (
.a (a),
.y (y),
.g_(g_)
);
`define assert(signame, signal, value) \
if (signal !== value) begin \
$display("Error: %s should be %b, but is %b", signame, signal, value); \
end
task tester;
input [80*8-1:0] descr;
input [WIDTH-1:0] aval;
input gval;
input [WIDTH-1:0] expecty;
begin
a <= aval;
g_ <= gval;
#1 $display("%5g: %8b %1b | %8b | %0s", $time, a, g_, y, descr);
`assert("y", y, expecty);
end
endtask
initial begin
//Dump results of the simulation
$dumpfile("sn74ls244.vcd");
$dumpvars;
$display("-time: ---a---- g_ | ---y---- | descr");
// -----a----- -g_- --expecty--
tester("load 1's", 8'b11111111, 1'b0, 8'b11111111);
tester("load 0's", 8'b00000000, 1'b0, 8'b00000000);
tester("load 10's", 8'b10101010, 1'b0, 8'b10101010);
tester("tristate", 8'bxxxxxxxx, 1'b1, 8'bzzzzzzzz);
#10 $finish;
end
endmodule
| 6.758324 |
module sn74ls245 (
a,
b,
dir,
g_
);
parameter WIDTH = 8;
inout [WIDTH-1:0] a, b;
input dir, g_;
assign a = (g_ == 'b1 || dir == 'b1) ? {WIDTH{1'bZ}} : b;
assign b = (g_ == 'b1 || dir == 'b0) ? {WIDTH{1'bZ}} : a;
endmodule
| 6.922309 |
module SN74LS257 #(
parameter INVERTED_OUTPUT = 0
) (
input wire [3:0] a,
input wire [3:0] b,
input wire select,
input wire out_control,
output wire [3:0] y
);
wire [3:0] selection;
wire [3:0] internal_out;
assign selection = select == 0 ? a : b;
assign internal_out = INVERTED_OUTPUT == 0 ? selection : ~selection;
assign y = out_control == 0 ? internal_out : 4'b0000;
endmodule
| 7.33012 |
module SN74LS27 (
input wire a1,
input wire b1,
input wire c1,
output wire y1,
input wire a2,
input wire b2,
input wire c2,
output wire y2,
input wire a3,
input wire b3,
input wire c3,
output wire y3
);
assign y1 = ~a1 & ~b1 & ~c1;
assign y2 = ~a2 & ~b2 & ~c2;
assign y3 = ~a3 & ~b3 & ~c3;
endmodule
| 7.394513 |
module SN74LS374 (
input wire reset,
input wire [7:0] data,
input wire clk,
input wire out_control,
output wire [7:0] out
);
reg [7:0] out_reg;
assign out = out_control == 1'b1 ? /*8'bz*/ 8'b00000000 : out_reg;
always @(posedge clk) begin
if (reset == 1'b1) begin
out_reg <= 8'b00000000;
end else begin
if (out_control == 1'b1) out_reg <= 8'b00000000;
out_reg <= data;
end
end
endmodule
| 6.743893 |
module: SN74LS374
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module SN74LS374_testbench;
// Inputs
reg [7:0] data;
reg clk;
reg out_control;
// Outputs
wire [7:0] out;
// Instantiate the Unit Under Test (UUT)
SN74LS374 uut (
.data(data),
.clk(clk),
.out_control(out_control),
.out(out)
);
//reg[15:0] counter;
initial begin
// Initialize Inputs
data = 0;
clk = 0;
out_control = 1;
//counter = 0;
// Wait 1 us for global reset to finish
#1000;
// Add stimulus here
out_control = 0;
end
always
begin
#100 data <= data + 1;
#10 clk <= ~clk;
// counter <= counter + 1;
end
endmodule
| 6.711014 |
module SN74LS73 (
j1,
clk1,
k1,
clrn1,
q1,
qn1,
j2,
clk2,
k2,
clrn2,
q2,
qn2
);
input wire j1;
input wire clk1;
input wire k1;
input wire clrn1;
output reg q1;
output wire qn1;
input wire j2;
input wire clk2;
input wire k2;
input wire clrn2;
output reg q2;
output wire qn2;
always @(posedge clk1 or negedge clrn1) begin
if (!clrn1) begin
q1 <= 0;
end else begin
q1 <= ~q1 & j1 | q1 & ~k1;
end
end
assign qn1 = ~q1;
always @(posedge clk2 or negedge clrn2) begin
if (!clrn2) begin
q2 <= 0;
end else begin
q2 <= ~q2 & j2 | q2 & ~k2;
end
end
assign qn2 = ~q2;
endmodule
| 6.787788 |
module SN74LS74 (
prn1,
d1,
clk1,
clrn1,
q1,
qn1,
prn2,
d2,
clk2,
clrn2,
q2,
qn2
);
input wire prn1;
input wire d1;
input wire clk1;
input wire clrn1;
output reg q1;
output wire qn1;
input wire prn2;
input wire d2;
input wire clk2;
input wire clrn2;
output reg q2;
output wire qn2;
always @(posedge clk1 or negedge clrn1 or negedge prn1) begin
if (!clrn1) begin
q1 <= 0;
end else if (!prn1) begin
q1 <= 1;
end else begin
q1 <= d1;
end
end
assign qn1 = ~q1;
always @(posedge clk2 or negedge clrn2 or negedge prn2) begin
if (!clrn2) begin
q2 <= 0;
end else if (!prn2) begin
q2 <= 1;
end else begin
q2 <= d2;
end
end
assign qn2 = ~q2;
endmodule
| 6.909097 |
module Snake_Control(
input CLK,
input RESET,
input Counter,
input [9:2] Pixel_Address_X,
input [8:2] Pixel_Address_Y,
input [7:0] Random_Target_Address_X,
input [6:0] Random_Target_Address_Y,
input [1:0] Direction_state,
input [1:0] MSM_State,
output [11:0] Colour,
output REACHED_TARGET
);
reg [7:0] SnakeState_X [0: SnakeLength-1];
reg [6:0] SnakeState_Y [0: SnakeLength-1];
//parameter
//Changing the position of the snake registers
//Shift the SnakeState X and Y
genvar PixNo;
generate
for (PixNo = 0; PixNo < Snakelength-1; Pix = PixNo+1)
begin: PixShift
always(posedge CLK) begin
if (RESET) begin
SnakeState_X[PixNo+1] <= 80;
SnakeState_Y[PixNo+1] <= 100;
end
else if (Counter == 0) begin
SnakeState_X[PixNo+1] <= SnakeState_X[PixNo];
SnakeState_Y[PixNo+1] <= SnakeState_Y[PixNo];
end
end
end
endgenerate
//Replace top snake state with new one based on direction
always@(posedge CLK)begin
if (RESET) begin
//Set the initial state of the snake
SnakeState_X[PixNo+1] <= 80;
SnakeState_Y[PixNo+1] <= 100;
end
else if (Counter == 0)begin
case (DIRECTION)
2'b00 :begin//up
if(SnakeState_Y[0]==0)
SnakeState_Y[0] <= MaxY;
else
SnakeState_Y[0] <= SnakeState_Y[0] - 1;
end
2'b01 :begin//left
if(SnakeState_X[0]==0)
SnakeState_X[0] <= MaxX;
else
SnakeState_X[0] <= SnakeState_X[0] - 1;
end
2'b10 :begin//right
if(SnakeState_X[0]==MaxX)
SnakeState_X[0] <= 0;
else
SnakeState_X[0] <= SnakeState_X[0] + 1;
end
2'b11 :begin//down
if(SnakeState_Y[0]==MaxY)
SnakeState_Y[0] <= 0;
else
SnakeState_Y[0] <= SnakeState_Y[0] + 1;
end
endcase
end
end
endmodule
| 7.012413 |
module vga_sync (
input wire clk,
reset,
output wire hsync,
vsync,
video_on,
p_tick,
output wire [9:0] pixel_x,
pixel_y
);
// constant declaration
// VGA 640-by-480 sync parameters
localparam HD = 640; // horizontal display area
localparam HF = 48; // h. front (left) border
localparam HB = 16; // h. back (right) border
localparam HR = 96; // h. retrace
localparam VD = 480; // vertical display area
localparam VF = 10; // v. front (top) border
localparam VB = 33; // v. back (bottom) border
localparam VR = 2; // v. retrace
// mod-2 counter
reg mod2_reg;
wire mod2_next;
// sync counters
reg [9:0] h_count_reg, h_count_next;
reg [9:0] v_count_reg, v_count_next;
// output buffer
reg v_sync_reg, h_sync_reg;
wire v_sync_next, h_sync_next;
// status signal
wire h_end, v_end, pixel_tick;
// body
// registers
always @(posedge clk, posedge reset)
if (reset) begin
mod2_reg <= 1'b0;
v_count_reg <= 0;
h_count_reg <= 0;
v_sync_reg <= 1'b0;
h_sync_reg <= 1'b0;
end else begin
mod2_reg <= mod2_next;
v_count_reg <= v_count_next;
h_count_reg <= h_count_next;
v_sync_reg <= v_sync_next;
h_sync_reg <= h_sync_next;
end
// mod-2 circuit to generate 25 MHz enable tick
assign mod2_next = ~mod2_reg;
assign pixel_tick = mod2_reg;
// status signals
// end of horizontal counter (799)
assign h_end = (h_count_reg == (HD + HF + HB + HR - 1));
// end of vertical counter (524)
assign v_end = (v_count_reg == (VD + VF + VB + VR - 1));
// next-state logic of mod-800 horizontal sync counter
always @*
if (pixel_tick) // 25 MHz pulse
if (h_end) h_count_next = 0;
else h_count_next = h_count_reg + 1;
else h_count_next = h_count_reg;
// next-state logic of mod-525 vertical sync counter
always @*
if (pixel_tick & h_end)
if (v_end) v_count_next = 0;
else v_count_next = v_count_reg + 1;
else v_count_next = v_count_reg;
// horizontal and vertical sync, buffered to avoid glitch
// h_sync_next asserted between 656 and 751(retrace)
assign h_sync_next = (h_count_reg >= (HD + HB) && h_count_reg <= (HD + HB + HR - 1));
// vh_sync_next asserted between 490 and 491
assign v_sync_next = (v_count_reg >= (VD + VB) && v_count_reg <= (VD + VB + VR - 1));
// video on/off
assign video_on = (h_count_reg < HD) && (v_count_reg < VD);
// output
assign hsync = h_sync_reg;
assign vsync = v_sync_reg;
assign pixel_x = h_count_reg;
assign pixel_y = v_count_reg;
assign p_tick = pixel_tick;
endmodule
| 8.903884 |
module ps2_rx (
input wire clk,
reset,
input wire ps2d,
ps2c,
rx_en,
output reg rx_done_tick,
output wire [7:0] dout
);
// symbolic state declaration
localparam [1:0] idle = 2'b00, dps = 2'b01, //data, parity, stop
load = 2'b10;
// signal declaration
reg [1:0] state_reg, state_next;
reg [7:0] filter_reg;
wire [7:0] filter_next;
reg f_ps2c_reg;
wire f_ps2c_next;
reg [3:0] n_reg, n_next;
reg [10:0] b_reg, b_next;
wire fall_edge;
// filter and falling-edge tick generation for ps2c
always @(posedge clk, posedge reset)
if (reset) begin
filter_reg <= 0;
f_ps2c_reg <= 0;
end else begin
filter_reg <= filter_next;
f_ps2c_reg <= f_ps2c_next;
end
assign filter_next = {ps2c, filter_reg[7:1]};
assign f_ps2c_next = (filter_reg==8'b11111111) ? 1'b1 :
(filter_reg==8'b00000000) ? 1'b0 :
f_ps2c_reg;
assign fall_edge = f_ps2c_reg & ~f_ps2c_next;
// FSMD state & data registers
always @(posedge clk, posedge reset)
if (reset) begin
state_reg <= idle;
n_reg <= 0;
b_reg <= 0;
end else begin
state_reg <= state_next;
n_reg <= n_next;
b_reg <= b_next;
end
// FSMD next-state logic
always @* begin
state_next = state_reg;
rx_done_tick = 1'b0;
n_next = n_reg;
b_next = b_reg;
case (state_reg)
idle:
if (fall_edge & rx_en) begin
// shift in start bit
b_next = {ps2d, b_reg[10:1]};
n_next = 4'b1001;
state_next = dps;
end
dps: // 8 data + 1 parity + 1 stop
if (fall_edge) begin
b_next = {ps2d, b_reg[10:1]};
if (n_reg == 0) state_next = load;
else n_next = n_reg - 1;
end
load: // 1 extra clock to complete the last shift
begin
state_next = idle;
rx_done_tick = 1'b1;
end
endcase
end
// output
assign dout = b_reg[8:1]; // data bits
endmodule
| 7.235202 |
module snake (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
LEDR,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B // VGA Blue[9:0]
);
input CLOCK_50; // 50 MHz
input [9:0] SW;
input [3:0] KEY;
output [9:0] LEDR;
// Declare your inputs and outputs here
// Do not change the following outputs
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK_N; // VGA BLANK
output VGA_SYNC_N; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
wire resetn;
assign resetn = SW[9];
// Create the colour, x, y and writeEn wires that are inputs to the controller.
wire [2:0] colour;
wire [7:0] x;
wire [6:0] y;
wire writeEn;
// Create an Instance of a VGA controller - there can be only one!
// Define the number of colours as well as the initial background
// image file (.MIF) for the controller.
vga_adapter VGA (
.resetn(resetn),
.clock(CLOCK_50),
.colour(colour),
.x(x),
.y(y),
.plot(1),
/* Signals for the DAC to drive the monitor. */
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK)
);
defparam VGA.RESOLUTION = "160x120"; defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1; defparam VGA.BACKGROUND_IMAGE = "black.mif";
//direction wire
wire w_k, a_k, s_k, d_k, left_k, right_k, up_k, down_k, space_k, enter_k;
keyboard_tracker #(
.PULSE_OR_HOLD(0)
) k0 (
.clock(CLOCK_50),
.reset(SW[9]),
.PS2_CLK(PS2_CLK),
.PS2_DAT(PS2_DAT),
.w(w_k),
.a(a_k),
.s(s_k),
.d(d_k),
.left(left_k),
.right(right_k),
.up(up_k),
.down(down_k),
.space(space_k),
.enter(enter_k)
);
assign LEDR[0] = w_k;
assign LEDR[1] = a_k;
assign LEDR[8] = KEY[1];
wire [4:0] direction;
// kbInput kbIn(CLOCK_50, KEY, SW, a_k, d_k, w_k, s_k, direction);
socInput socIn (
CLOCK_50,
KEY,
SW,
direction
);
datapath d0 (
.clk(CLOCK_50),
.direction(direction),
.inmenu(SW[0]),
.ingame(SW[1]),
.RGB(colour),
.x_pointer(x),
.y_pointer(y),
.inital_head(SW[2])
);
endmodule
| 7.506897 |
module randomGrid (
clk,
rand_X,
rand_Y
);
input clk;
output reg [7:0] rand_X = 6;
output reg [6:0] rand_Y = 6;
// x and y will stop at random pixel.
integer max_height = 108;
integer max_width = 154;
always @(posedge clk) begin
if (rand_X === max_width) rand_X <= 6;
else rand_X <= rand_X + 1;
end
always @(posedge clk) begin
if (rand_X === max_width) begin
if (rand_Y === max_height) rand_Y <= 6;
else rand_Y <= rand_Y + 1;
end
end
endmodule
| 6.526788 |
module delay_counter (
clk,
reset_n,
en_delay,
delayed_clk
);
input clk;
input reset_n;
input en_delay;
output delayed_clk;
reg [3:0] delay;
always @(posedge clk) begin
if (delay == 2) delay <= 0;
else if (en_delay) begin
delay <= delay + 1'b1;
end
end
assign delayed_clk = (delay == 2) ? 1 : 0;
endmodule
| 6.853164 |
module
`include "../definitions/define.vh"
module SnakeGame (
// joystick input
input wire
res_x_one,
res_x_two,
res_y_one,
res_y_two,
input wire clk, // 50MHz
// VGA input
input wire
reset,
color, // swap between 2 outputs
// VGA output
output wire
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_R, // VGA Red
VGA_G, // VGA Green
VGA_B, // VGA Blue
// Sseg output
output wire
[7:0] sseg_a_to_dp,
output wire
[3:0] sseg_an
// joystick output
//, output wire [0:1] dir_out // for debug
);
// Clock
wire vga_clk, update_clk;
VGA_clk vga_clk_gen (
clk,
vga_clk
);
game_upd_clk upd_clk(
.in_clk(vga_clk),
.reset(reset),
.x_in(mVGA_X),
.y_in(mVGA_Y),
.out_clk(update_clk)
);
// Game input
wire [0:1] dir;
joystick_input ji (
.one_resistor_x(res_x_one),
.two_resistors_x(res_x_two),
.one_resistor_y(res_y_one),
.two_resistors_y(res_y_two),
.clk(update_clk),
.direction(dir)
);
assign dir_out = dir; // for debug
// Game logic
wire [0:1] cur_ent_code;
wire `TAIL_SIZE game_score;
game_logic game_logic_module (
.vga_clk(vga_clk),
.update_clk(update_clk),
.reset(reset),
.direction(dir),
.x_in(mVGA_X),
.y_in(mVGA_Y),
.entity(cur_ent_code),
//.game_over(),
//.game_won(),
.tail_count(game_score)
);
// VGA
wire [9:0] mVGA_X;
wire [9:0] mVGA_Y;
wire mVGA_R;
wire mVGA_G;
wire mVGA_B;
wire sVGA_R;
wire sVGA_G;
wire sVGA_B;
VGA_Draw u3 // Drawing
( // Read Out Side
.oRed(mVGA_R),
.oGreen(mVGA_G),
.oBlue(mVGA_B),
.iVGA_X(mVGA_X),
.iVGA_Y(mVGA_Y),
.iVGA_CLK(vga_clk),
// Control Signals
.reset(reset),
.iColor_SW(color),
.ent(cur_ent_code)
);
VGA_Ctrl u2 // Setting up VGA Signal
( // Host Side
.oCurrent_X(mVGA_X),
.oCurrent_Y(mVGA_Y),
.iRed(mVGA_R),
.iGreen(mVGA_G),
.iBlue(mVGA_B),
// VGA Side
.oVGA_R(sVGA_R),
.oVGA_G(sVGA_G),
.oVGA_B(sVGA_B),
.oVGA_HS(VGA_HS),
.oVGA_VS(VGA_VS),
// Control Signal
.iCLK(vga_clk),
.reset(reset)
);
assign VGA_R = sVGA_R;
assign VGA_G = sVGA_G;
assign VGA_B = sVGA_B;
SSEG_Display sseg_d(
.clk_50M(clk),
.reset(reset),
.sseg_a_to_dp(sseg_a_to_dp),
.sseg_an(sseg_an),
.data(game_score)
);
endmodule
| 6.585576 |
module snakes (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B, // VGA Blue[9:0]
PS2_CLK,
PS2_DAT,
HEX0,
HEX1
);
input CLOCK_50; // 50 MHz
input [9:0] SW;
input [3:0] KEY;
// Declare your inputs and outputs here
// Do not change the following outputs
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK_N; // VGA BLANK
output VGA_SYNC_N; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
output [6:0] HEX0, HEX1;
inout PS2_CLK;
inout PS2_DAT;
wire resetn;
assign resetn = SW[9];
// Create the colour, x, y and writeEn wires that are inputs to the controller.
wire [2:0] colour;
wire [7:0] x;
wire [6:0] y;
wire writeEn;
wire [7:0] scores;
// Create an Instance of a VGA controller - there can be only one!
// Define the number of colours as well as the initial background
// image file (.MIF) for the controller.
vga_adapter VGA (
.resetn(resetn),
.clock(CLOCK_50),
.colour(colour),
.x(x),
.y(y),
.plot(1),
/* Signals for the DAC to drive the monitor. */
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK)
);
defparam VGA.RESOLUTION = "160x120"; defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1; defparam VGA.BACKGROUND_IMAGE = "black.mif";
wire w_k, a_k, s_k, d_k, left_k, right_k, up_k, down_k, space_k, enter_k;
keyboard_tracker #(
.PULSE_OR_HOLD(0)
) k0 (
.clock(CLOCK_50),
.reset(SW[9]),
.PS2_CLK(PS2_CLK),
.PS2_DAT(PS2_DAT),
.w(w_k),
.a(a_k),
.s(s_k),
.d(d_k),
.left(left_k),
.right(right_k),
.up(up_k),
.down(down_k),
.space(space_k),
.enter(enter_k)
);
datapath d0 (
.clk(CLOCK_50),
.direction(direction),
.game_reset(SW[1]),
.game_display(SW[0]),
.RGB(colour),
.x_position(x),
.y_position(y),
.snake_start(SW[2]),
.score(scores)
);
hex_decoder hex0 (
scores[3:0],
HEX0
);
hex_decoder hex1 (
scores[7:4],
HEX1
);
//direction wire
wire [3:0] direction;
kbInput kbIn (
CLOCK_50,
KEY,
SW,
a_k,
d_k,
w_k,
s_k,
direction,
reset
);
endmodule
| 8.659422 |
module randomApple (
clk,
rand_X,
rand_Y
);
input clk;
output reg [7:0] rand_X = 6;
output reg [6:0] rand_Y = 6;
// set the maximum height and width of the game interface.
// x and y will scan over every pixel.
integer max_height = 108;
integer max_width = 154;
always @(posedge clk) begin
if (rand_X == max_width) rand_X <= 6;
else rand_X <= rand_X + 1;
end
always @(posedge clk) begin
if (rand_X == max_width) begin
if (rand_Y === max_height) rand_Y <= 6;
else rand_Y <= rand_Y + 1;
end
end
endmodule
| 6.691568 |
module delay_counter (
clk,
reset_n,
en_delay,
delayed_clk
);
input clk;
input reset_n;
input en_delay;
output delayed_clk;
reg [3:0] delay;
// Register for the delay counter
always @(posedge clk) begin
// if (!reset_n)
// delay <= 20'd840000;
if (delay == 2) delay <= 0;
else if (en_delay) begin
delay <= delay + 1'b1;
end
end
assign delayed_clk = (delay == 2) ? 1 : 0;
endmodule
| 6.853164 |
module hex_decoder (
hex_digit,
segments
);
input [3:0] hex_digit;
output reg [6:0] segments;
always @(*)
case (hex_digit)
4'h0: segments = 7'b100_0000;
4'h1: segments = 7'b111_1001;
4'h2: segments = 7'b010_0100;
4'h3: segments = 7'b011_0000;
4'h4: segments = 7'b001_1001;
4'h5: segments = 7'b001_0010;
4'h6: segments = 7'b000_0010;
4'h7: segments = 7'b111_1000;
4'h8: segments = 7'b000_0000;
4'h9: segments = 7'b001_1000;
4'hA: segments = 7'b000_1000;
4'hB: segments = 7'b000_0011;
4'hC: segments = 7'b100_0110;
4'hD: segments = 7'b010_0001;
4'hE: segments = 7'b000_0110;
4'hF: segments = 7'b000_1110;
default: segments = 7'h7f;
endcase
endmodule
| 7.584821 |
module snake_control (
input CLK,
input RESET,
//input Counter,
input [9:0] Pixel_Address_X,
input [8:0] Pixel_Address_Y,
input [7:0] Random_Target_Address_X,
input [6:0] Random_Target_Address_Y,
input [1:0] Direction_state,
// input [1:0] MSM_State,
output reg [11:0] Colour,
output reg REACHED_TARGET
);
parameter SnakeLength = 7;
parameter MaxY = 120;
parameter MaxX = 160;
parameter CounterMax = 500;
reg Counter;
wire [7:0] AddrX;
wire [6:0] AddrY;
reg [7:0] SnakeState_X[0:SnakeLength-1];
reg [6:0] SnakeState_Y[0:SnakeLength-1];
assign AddrX = Pixel_Address_X[9:2];
assign AddrY = Pixel_Address_Y[8:2];
//parameter
always @(posedge CLK) begin
if (Counter > 0) begin
Counter <= Counter - 1;
end else begin
Counter <= CounterMax;
end
end
//Changing the position of the snake registers
//Shift the SnakeState X and Y
genvar PixNo;
generate
for (PixNo = 0; PixNo < SnakeLength - 1; PixNo = PixNo + 1) begin : PixShift
always @(posedge CLK) begin
if (RESET) begin
SnakeState_X[PixNo+1] <= 80;
SnakeState_Y[PixNo+1] <= 100;
end else if (Counter == 0) begin
SnakeState_X[PixNo+1] <= SnakeState_X[PixNo];
SnakeState_Y[PixNo+1] <= SnakeState_Y[PixNo];
end
end
end
endgenerate
//Replace top snake state with new one based on direction
always @(posedge CLK) begin
if (RESET) begin
//Set the initial state of the snake
SnakeState_X[PixNo+1] <= 80;
SnakeState_Y[PixNo+1] <= 100;
end else if (Counter == 0) begin
case (Direction_state)
2'b00: begin //up
if (SnakeState_Y[0] == 0) SnakeState_Y[0] <= MaxY;
else SnakeState_Y[0] <= SnakeState_Y[0] - 1;
end
2'b01: begin //left
if (SnakeState_X[0] == 0) SnakeState_X[0] <= MaxX;
else SnakeState_X[0] <= SnakeState_X[0] - 1;
end
2'b10: begin //right
if (SnakeState_X[0] == MaxX) SnakeState_X[0] <= 0;
else SnakeState_X[0] <= SnakeState_X[0] + 1;
end
2'b11: begin //down
if (SnakeState_Y[0] == MaxY) SnakeState_Y[0] <= 0;
else SnakeState_Y[0] <= SnakeState_Y[0] + 1;
end
endcase
end
end
always @(posedge CLK) begin
if ((SnakeState_X[0]==Random_Target_Address_X)&&(SnakeState_Y[0]==Random_Target_Address_Y))
REACHED_TARGET <= 1;
else REACHED_TARGET <= 0;
end
always @(posedge CLK) begin
if ((AddrX[0]==SnakeState_X[0]) &&(AddrY[0]==SnakeState_Y[0])
||(AddrX[1]==SnakeState_X[1]) &&(AddrY[1]==SnakeState_Y[1])
||(AddrX[2]==SnakeState_X[2]) &&(AddrY[2]==SnakeState_Y[2])
||(AddrX[3]==SnakeState_X[3]) &&(AddrY[3]==SnakeState_Y[3])
||(AddrX[4]==SnakeState_X[4]) &&(AddrY[4]==SnakeState_Y[4])
||(AddrX[5]==SnakeState_X[5]) &&(AddrY[5]==SnakeState_Y[5])
||(AddrX[6]==SnakeState_X[6]) &&(AddrY[6]==SnakeState_Y[6]))
Colour <= 12'b000011110000;
else if ((AddrX == Random_Target_Address_X) && (AddrY == Random_Target_Address_Y))
Colour <= 12'b111111110000;
else Colour <= 12'b111111111111;
end
endmodule
| 6.866116 |
module Snake_Controller (
CLK,
data,
keyboard_CLK,
Hsync,
Vsync,
R,
G,
B
);
input CLK, keyboard_CLK, data;
output [2:0] R, G;
output [1:0] B;
output Hsync, Vsync;
reg CLK25MHz;
wire [7:0] keycode;
wire led;
wire [9:0] XCoord, YCoord;
wire [7:0] pixel_out;
always @(posedge CLK) begin
CLK25MHz <= ~CLK25MHz;
end
VGA VGA_out1 (
CLK25MHz,
pixel_out,
Hsync,
Vsync,
R,
G,
B,
XCoord,
YCoord
);
Snake_VGA snakeVGA1 (
CLK25MHz,
keycode,
XCoord,
YCoord,
pixel_out
);
kbctrl kb1 (
keyboard_CLK,
data,
led,
keycode
);
endmodule
| 7.012413 |
module snake_cpu_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire [31:0] q;
wire [31:0] ram_data;
wire [31:0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram (
.address_a(wraddress),
.address_b(rdaddress),
.clock0(clock),
.data_a(ram_data),
.q_b(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0", the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0, the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32, the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32, the_altsyncram.widthad_a = 5, the_altsyncram.widthad_b = 5;
endmodule
| 6.6395 |
module snake_cpu_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire [31:0] q;
wire [31:0] ram_data;
wire [31:0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram (
.address_a(wraddress),
.address_b(rdaddress),
.clock0(clock),
.data_a(ram_data),
.q_b(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0", the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0, the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32, the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32, the_altsyncram.widthad_a = 5, the_altsyncram.widthad_b = 5;
endmodule
| 6.6395 |
module snake_cpu_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
3'b000: begin
td_mode = 4'b0000;
end // 3'b000
3'b001: begin
td_mode = 4'b1000;
end // 3'b001
3'b010: begin
td_mode = 4'b0100;
end // 3'b010
3'b011: begin
td_mode = 4'b1100;
end // 3'b011
3'b100: begin
td_mode = 4'b0010;
end // 3'b100
3'b101: begin
td_mode = 4'b1010;
end // 3'b101
3'b110: begin
td_mode = 4'b0101;
end // 3'b110
3'b111: begin
td_mode = 4'b1111;
end // 3'b111
endcase // ctrl_bits_for_mux
end
endmodule
| 6.6395 |
module snake_cpu_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [24:0] cpu_d_address;
input cpu_d_read;
input [31:0] cpu_d_readdata;
input cpu_d_wait;
input cpu_d_write;
input [31:0] cpu_d_writedata;
input jrst_n;
input [15:0] trc_ctrl;
reg [35:0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [31:0] cpu_d_address_0_padded;
wire [31:0] cpu_d_readdata_0_padded;
wire [31:0] cpu_d_writedata_0_padded;
reg [35:0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dummy_tie_off;
wire record_load_addr;
wire record_load_data;
wire record_store_addr;
wire record_store_data;
wire [ 3:0] td_mode_trc_ctrl;
assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
//snake_cpu_cpu_nios2_oci_trc_ctrl_td_mode, which is an e_instance
snake_cpu_cpu_nios2_oci_td_mode snake_cpu_cpu_nios2_oci_trc_ctrl_td_mode (
.ctrl (trc_ctrl[8 : 0]),
.td_mode(td_mode_trc_ctrl)
);
assign {record_load_addr, record_store_addr,
record_load_data, record_store_data} = td_mode_trc_ctrl;
always @(posedge clk or negedge jrst_n) begin
if (jrst_n == 0) begin
atm <= 0;
dtm <= 0;
end else begin
atm <= 0;
dtm <= 0;
end
end
assign dummy_tie_off = cpu_d_wait | cpu_d_read | cpu_d_write;
endmodule
| 6.6395 |
module snake_cpu_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
);
output [1:0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_input_tm_cnt;
wire [2:0] switch_for_mux;
assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
always @(switch_for_mux) begin
case (switch_for_mux)
3'b000: begin
compute_input_tm_cnt = 0;
end // 3'b000
3'b001: begin
compute_input_tm_cnt = 1;
end // 3'b001
3'b010: begin
compute_input_tm_cnt = 1;
end // 3'b010
3'b011: begin
compute_input_tm_cnt = 2;
end // 3'b011
3'b100: begin
compute_input_tm_cnt = 1;
end // 3'b100
3'b101: begin
compute_input_tm_cnt = 2;
end // 3'b101
3'b110: begin
compute_input_tm_cnt = 2;
end // 3'b110
3'b111: begin
compute_input_tm_cnt = 3;
end // 3'b111
endcase // switch_for_mux
end
endmodule
| 6.6395 |
module snake_cpu_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
);
output [3:0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [3:0] fifo_wrptr_inc;
always @(ge2_free or ge3_free or input_tm_cnt) begin
if (ge3_free & (input_tm_cnt == 3)) fifo_wrptr_inc = 3;
else if (ge2_free & (input_tm_cnt >= 2)) fifo_wrptr_inc = 2;
else if (input_tm_cnt >= 1) fifo_wrptr_inc = 1;
else fifo_wrptr_inc = 0;
end
endmodule
| 6.6395 |
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