code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module snake_cpu_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
);
output [4:0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [4:0] fifo_cnt_inc;
always @(empty or ge2_free... | 6.6395 |
module snake_cpu_cpu_nios2_oci_pib (
// outputs:
tr_data
);
output [35:0] tr_data;
wire [35:0] tr_data;
assign tr_data = 0;
endmodule
| 6.6395 |
module snake_cpu_cpu_nios2_oci_im (
// inputs:
clk,
jrst_n,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
);
output tracemem_on;
output [35:0] tracemem_trcdata;
output tracemem_tw;
output [6:0] tr... | 6.6395 |
module snake_cpu_cpu_nios2_performance_monitors;
endmodule
| 6.6395 |
module snake_cpu_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_oci... | 6.6395 |
module snake_cpu_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input [7:0] address;
input [3:0] byteenable;
input clock;
input [31:0] data;
input reset_req;
... | 6.6395 |
module for the classic snake game
// re-imagined in hardware.
// --------------------------------------------------------------------------
module snake_device (
input i_Clk,
input i_Rst,
input [3:0] i_Direction,
output wire [6:0] o_ScoreDisplay,
output wire [3:0] o_Red,
output wire [3:0] o_Green,
output wi... | 7.733567 |
module snake_game (
i_Clk,
i_Rst,
i_Direction,
i_FoodLocation,
o_Kill,
o_SnakeGrid,
o_Food,
o_Score
);
// Size of indexing for accessing locations on game grid.
parameter c_GRID_IDX_SZ = 10;
// Cell width and height of the snake game.
parameter c_WIDTH = 32;
parameter c_HEIGH... | 7.089979 |
module snake_hex2 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [7:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:0] wr... | 6.597919 |
module snake_master (
input wire sys_clk, //输入工作时钟,频率50MHz
input wire sys_rst_n, //输入复位信号,低电平有效
input wire key1,
input wire key2,
input wire key3,
input wire key4,
output wire ddc_scl,
output wire ddc_sda,
output wire tmds_clk_p,
output wire tmds_clk_... | 8.451556 |
module Snake_pll_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [2:1] CLK_OUT,
// High bits of counters driven by clocks
output [2:1] COUNT,
// Status and control signals
i... | 6.509577 |
module Snake_pll_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20... | 7.130611 |
modules.
// --------------------------------------------------------------------------
module snake_scoreboard
(
i_Clk,
i_Score,
o_ScoreDisplay,
o_SegmentSelect
);
// Four BCD digits
parameter SCORE_WIDTH = 16;
input wire i_Clk;
input wire [SCORE_WIDTH-1:0] i_Score;
output reg [6:0] o_ScoreDisplay;... | 6.986352 |
module for snake game.
// --------------------------------------------------------------------------
module snake_scoreboard_tb ();
`timescale 1ns/1ns
time clk_period = 100;
localparam N_TESTS = 5; // Number of test cases for UUT
localparam SCORE_WIDTH = 16; // Number of bits needed for 4-digit decimal
local... | 7.611139 |
module snake_seven_seg_display (
input CLOCK,
input [4:0] len,
output [3:0] an,
output [7:0] seg
);
reg SIGNAL = 0;
reg [3:0] anode;
reg [7:0] cath;
wire [7:0] cath_1, cath_2;
snake_output_decimal D (
len,
cath_1,
cath_2
);
always @(posedge CLOCK) begin
case (SIGNAL... | 6.768718 |
module Snake_top (
input clk,
input rst_n,
input [3:0] cmd_out,
output [1:0] gamestate,
output [1:0] direct,
output [3:0] scorel,
output [3:0] scorem,
output [ 5:0] food_x,
output [ 4:0] food_y,
output [999:0] map,
output [ 5:0] head_x,
output [ 4:0] head_y
);
w... | 7.006251 |
module random_props (
clk,
rand_X,
rand_Y
);
input clk;
output reg [7:0] rand_X;
output reg [6:0] rand_Y;
// set the maximum height and width of the game interface.
// x and y will scan over every pixel.
integer max_height = 100;
integer max_width = 140;
always @(posedge clk) begin
if ... | 6.88726 |
module delay_counter (
clk,
reset_n,
en_delay,
delayed_clk,
main_difficulty
);
input clk;
input reset_n;
input en_delay;
input [3:0] main_difficulty;
output delayed_clk;
reg [3:0] delay;
// Register for the delay counter
always @(posedge clk) begin
// if (!reset_n)
// de... | 6.853164 |
module to a VGA signal.
// --------------------------------------------------------------------------
module snake_to_vga
(
i_Clk,
i_Rst,
i_GameOver,
i_SnakeGrid,
i_Food,
o_Red,
o_Green,
o_Blue,
o_HSync,
o_VSync
);
parameter c_WIDTH = 32;
parameter c_HEIGHT = 32;
parameter c_GRID_IDX_SZ = 10... | 6.992135 |
module Sna_Request_Transimtter (
clock,
addr,
data,
read,
pov_addr,
is_valid,
is_on_off,
is_allocatable,
araddr,
arvalid,
arready,
awaddr,
awvalid,
awready,
wdata,
wvalid,
wready,
pov_addr_buffer
);
input clock;
input [31:0] addr;
input [31:0... | 6.866102 |
module snd (
input clk, // system clock
input rst, // system reset
input cs, // chip select
input we, // write enable
input [3:0] addr, // register select
input [7:0] din, // data bus input
output reg [7:0] dout, // data bus output
output snd_l, // left 1-bit DAC output
outpu... | 7.131703 |
module sndfifo (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrusedw
);
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output [11:0] rdusedw;
output [11:0] wrusedw;
wire [31:0] sub_wire0;
wire... | 6.896764 |
module sndfifo (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrusedw
);
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output [11:0] rdusedw;
output [11:0] wrusedw;
endmodule
| 6.896764 |
module snd_buffer (
input CLK,
input BCLK,
input RST_X,
input VIF_SNDRDATAVLD,
input [63:0] VIF_RDATA,
input FIFO_READ_R,
input FIFO_READ_L,
output BUF_WREADY,
output [31:0] FIFO_DOUT_R, //32 bit
output [31:0] FIFO_DOUT_L //32 ... | 6.616602 |
module snd_clkgen (
input CLK,
input RST_X,
output reg SND_LRCLK,
output reg SND_BCLK,
output reg SND_MCLK,
output [6:0] LRCLK_COUNT,
output [6:0] BCLK_COUNT,
output [6:0] MCLK_COUNT
);
reg [6:0] lrclk_count; //0-63 7bit
reg [6:0] bclk_count; //0-34 7bit
reg [6:0] mclk_count; ... | 6.88369 |
module snd_outgen (
input BCLK,
input RST_X,
input SND_LRCLK,
input [6:0] LRCLK_COUNT,
//input [31:0] FIFO_DOUT,
input [15:0] L_SNDDATA,
input [15:0] R_SNDDATA,
input [ 1:0] REG_CMD,
input [31:0] REG_STATUS,
input [31:0] REG_DELAY,
output reg FIFO_READ_R,
... | 7.479288 |
module trans_socket #(
parameter AW = 12, // NOT LESS THAN 10
parameter DW = 8, // 16 FOR SIMULATION ,8 FOR REAL USE
parameter MAX_PACK_LEN = 8100,
parameter PADDING_INFO_LEN = 0 //0...8
) (
input clk,
rst, //cfg if //axi stream to ether if
input [DW-1:0] fifo_dat,
input fifo_wr,
... | 7.586291 |
module sc_fifo_4_socket #(
parameter AW = 5,
parameter DW = 64
) (
input clk,
rst,
input [DW-1:0] din,
input wr,
rd,
output full,
empty,
output reg [DW-1:0] dout,
output [DW-1:0] fwft_dout,
output reg [AW:0] fifo_cntr
);
parameter MAX_FIFO_LEN = (1 << AW);
reg [DW-1:0... | 6.996741 |
module snd_vramctrl (
input CLK,
input RST_X,
input [22:0] REG_VRAMADR,
input BUF_WREADY,
input [ 1:0] REG_CMD,
input REG_LOOP,
input [31:0] REG_MUSIC,
input VIF_SNDACK,
input VIF_SNDRDATAVLD,
input [63:0] VIF_RDATA,
output ... | 7.310725 |
module snek (
CLOCK_50,
SW,
LEDR,
KEY,
// TODO: Keyboard inputs
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B
);
input CLOCK_50;
input [9:0] SW; //
input [3:0] KEY;
output [9:0] LEDR;
// TODO: Keyboard inputs
output VGA_CLK; // V... | 7.040318 |
module control (
input go,
input alive,
input resetn,
input clock,
output reg play,
output reg init,
output [1:0] current_s,
output [1:0] next_s
);
localparam S_START = 2'b0, S_INIT = 2'b1, S_PLAY = 2'b10;
reg [1:0] current_state, next_state;
assign current_s = current_state;
a... | 7.715617 |
module and the port sync module is that the port
// sync module has read and write enable signals to help realize the bus access. This
// module just observe the address bus for "address switches". Once this module synchronizes
// an address bus "switch" then logic in the 40Mhz domain can safely analyse Address A bus
/... | 7.845611 |
module snes_bus_sync_test ();
reg clk = 0;
reg cycle_clk = 0;
reg rst_n = 0;
reg [7:0] PA = 0;
reg [7:0] D = 0;
wire [7:0] PA_sync;
wire [7:0] D_sync;
wire event_latch;
reg PARD_n = 1;
snes_bus_sync bs (
.clk (clk), // clock (40 MHz and reset)
.rst_n (rst_n),
... | 6.552602 |
module snes_dejitter (
input MCLK_XTAL_i, //NTSC master clock source: 21.477272MHz from oscillator circuit
input MCLK_EXT_i, //PAL master clock source: 21.28137MHz (3-CHIP) or 17.73MHz (1-CHIP) from external source
input MCLK_SEL_i, //Output clock/csync mode: De-jitter/NTSC (0), Bypass/PAL (1)
input ... | 6.758675 |
module snes_gamepad
//
// Dependencies: snes_gamepad_ctrl
//
////////////////////////////////////////////////////////////////////////////////
module snes_gamepad_tb;
// INPUTS //////////////////////////////////////////////////////////////////////
reg clk;
reg rst;
reg rd;
reg snes_data... | 6.802858 |
module SNG (
seed,
data,
enable,
reset,
clk
);
input [7:0] seed;
output [7:0] data;
input enable;
input reset;
input clk;
reg [8:1] out_LFSR;
wire feedback;
assign feedback = out_LFSR[8] ^ out_LFSR[6] ^ out_LFSR[5] ^ out_LFSR[4];
always @(posedge clk or posedge reset) begin
... | 6.647348 |
module sng_test;
wire [7:0] data;
reg [7:0] seed;
reg enable;
reg reset;
reg clk;
//SNG(seed,data,enable,reset,clk);
SNG U1 (
.data(data),
.seed(seed),
.enable(enable),
.reset(reset),
.clk(clk)
);
initial begin
clk = 0;
reset = 1;
enable = 0;
seed = 8'b0... | 6.744349 |
module snif #(
parameter ADR_WIDTH = `ADR_WIDTH
) (
input wire clk_i,
input wire rst_i,
input wire [ADR_WIDTH-1:0] adr_i,
input wire we_i,
output wire detect_o
);
reg pulse_reg;
reg pulse_reg_next;
reg detect;
always @(posedge clk_i) begin : seq
if (rst_i) begin
pulse_reg <... | 7.185337 |
module SNI_RX (
arst_n,
fifo_afull,
fifo_din,
fifo_wren,
// Original FIFO Signal
fifo_EOD_in,
// SNI signal
RXC,
CRS,
RXD
);
// general interface
input wire arst_n; // async reset from user clock domain
// FIFO Interface signal
input wire fifo_afull; // fifo also_full
... | 7.496633 |
module SNN #(
parameter c_TOTAL_COLS = 800,
parameter c_TOTAL_ROWS = 525,
parameter c_ACTIVE_COLS = 640,
parameter c_ACTIVE_ROWS = 480
) (
input i_Clk,
input i_HSync,
input i_VSync,
// Button to determine whether Spike is being received
input i_Action_Potential,
// Output Vid... | 9.026486 |
module snn_network #(
parameter NUM_IN = 16,
parameter NUM_HIDDEN = 64,
parameter NUM_OUT = 8
) (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V power
input vssd1, // User area 1 digital ground
`endif
input wire clk,
... | 7.114656 |
module snn_tb;
initial begin
$dumpfile("snn.vcd");
$dumpvars(0, snn_tb);
#1;
end
reg clk;
reg RSTB;
reg power1, power2;
reg power3, power4;
wire gpio;
wire [37:0] mprj_io;
// IO Pads
// .state1(io_out[25:18]),
// .io_oeb(io_oeb[25:16])
///// convenience signals that match what t... | 6.51341 |
module SNN_top (
input i_Clk,
// Push Buttons
input i_Switch_1,
// VGA
output o_VGA_HSync,
output o_VGA_VSync,
output o_VGA_Red_0,
output o_VGA_Red_1,
output o_VGA_Red_2,
output o_VGA_Grn_0,
output o_VGA_Grn_1,
output o_VGA_Grn_2,
output o_VGA_Blu_0,
output o_VG... | 7.426416 |
module snoop (
input eclk,
input rstb,
input [3:0] stage,
input [3:0] pass_cnt,
input pass_cnt0, //Set during blake2b & collision XOR writing
input bucket_cnt_rst,
input wvalid,
input [`MEM_DATA_WIDTH-1:0] wdata,
output [`MEM_ADDR_WIDTH-1:0] ... | 6.93785 |
module SnoopP (
input clk,
input reset,
input [25:0] pc,
input [31:0] instr_in,
input stall,
// TESTER PORTS ONLY
input init_start,
output init_done,
input retrieve_start,
output retrieve_done,
// Avalon Profile Master ports
output avm_profileMaster_read,
output a... | 6.93175 |
module sInitializer ( // for sdram
input clk,
input reset,
input [25:0] pc,
input init_start,
output reg init_done,
output reg [`N2-1:0] addr_a,
output reg [25:0] addr_lo_data,
output reg [25:0] addr_hi_data,
output reg prof_init_start,
input prof_init_done,
//Avalon Bus... | 6.713009 |
module sRetriever (
input clk,
input reset,
input [25:0] pc,
input retrieve_start,
output reg retrieve_done,
output reg [`N2-1:0] count_a,
input [`CW-1:0] count_data,
//Avalon Bus side signals
output reg avm_profileMaster_write,
output reg [31:0]avm_profileMaster_address,
output reg [31:0]avm_profileMa... | 8.172321 |
module snoop_adapter (
clk,
reset,
kernel_clk,
kernel_reset,
address,
read,
readdata,
readdatavalid,
write,
writedata,
burstcount,
byteenable,
waitrequest,
burstbegin,
snoop_data,
snoop_valid,
snoop_ready,
export_address,
export_read,
ex... | 7.169538 |
module snowbro2_clock (
input CLK, //48mhz
input CLK96,
input CLK24,
input CLK6,
output CEN675,
output CEN675B,
output CEN2p7,
output CEN2p7B,
output CEN3p375,
output CEN3p375B,
output CEN1p6875,
output CEN1p6875B,
output CEN1350,
output CEN1350B
);
// 13.50mh... | 7.07318 |
module. This is one of the three queues used in
pingpangpungcontroller.v (refer to that file for details)
*/
module snqueue (
input wire clk,
input wire [1:0] token_from_cpu,
input wire en_from_cpu,
input wire [1:0] token_from_fwd,
input wire en_from_fwd,
input wire deq,
output wire [1:0] head
);
reg [1:... | 6.833535 |
module snurisc (
input reset,
input clk
);
wire [31:0] jump_reg_target;
wire [31:0] brjmp_target;
wire [31:0] data;
wire [31:0] wbdata;
wire [1:0] pc_sel;
wire im_status;
wire dm_status;
wire [11:0] imm12;
wire op1_sel;
wire op2_sel;
wire [3:0] alu_ctrl;
wire br_type;
wire dmem_fcn... | 6.514048 |
module SnxnLv4Inst4 (
input io_a,
input io_b,
output io_z
);
wire t0 = io_a + io_b; // @[Snxn100k.scala 72281:20]
wire inv0 = ~t0; // @[Snxn100k.scala 72282:15]
wire x0 = t0 ^ inv0; // @[Snxn100k.scala 72283:18]
wire invx0 = ~x0; // @[Snxn100k.scala 72284:15]
wire t1 = x0 + invx0; // @[Snxn... | 6.93941 |
module SnxnLv4Inst56 (
input io_a,
input io_b,
output io_z
);
wire t0 = io_a + io_b; // @[Snxn100k.scala 63383:20]
wire inv0 = ~t0; // @[Snxn100k.scala 63384:15]
wire x0 = t0 ^ inv0; // @[Snxn100k.scala 63385:18]
wire invx0 = ~x0; // @[Snxn100k.scala 63386:15]
wire t1 = x0 + invx0; // @[Snx... | 6.811338 |
module SnxnLv4Inst63 (
input io_a,
input io_b,
output io_z
);
wire t0 = io_a + io_b; // @[Snxn100k.scala 67495:20]
wire inv0 = ~t0; // @[Snxn100k.scala 67496:15]
wire x0 = t0 ^ inv0; // @[Snxn100k.scala 67497:18]
wire invx0 = ~x0; // @[Snxn100k.scala 67498:15]
wire t1 = x0 + invx0; // @[Snx... | 6.527747 |
module SnxnLv4Inst140 (
input io_a,
input io_b,
output io_z
);
wire t0 = io_a + io_b; // @[Snxn100k.scala 103215:20]
wire inv0 = ~t0; // @[Snxn100k.scala 103216:15]
wire x0 = t0 ^ inv0; // @[Snxn100k.scala 103217:18]
wire invx0 = ~x0; // @[Snxn100k.scala 103218:15]
wire t1 = x0 + invx0; // ... | 6.592475 |
module SnxnLv4Inst210 (
input io_a,
input io_b,
output io_z
);
wire t0 = io_a + io_b; // @[Snxn100k.scala 50727:20]
wire inv0 = ~t0; // @[Snxn100k.scala 50728:15]
wire x0 = t0 ^ inv0; // @[Snxn100k.scala 50729:18]
wire invx0 = ~x0; // @[Snxn100k.scala 50730:15]
wire t1 = x0 + invx0; // @[Sn... | 6.568619 |
module so2par (
input clk,
input ym_so,
input ym_sh1,
input ym_sh2,
input ym_p1,
output reg [15:0] left,
output reg [15:0] right,
output reg [15:0] left_exp,
output reg [15:0] right_exp,
output update_left,
... | 6.571011 |
module SOA #(
parameter M = 11
) (
input wire [16+3-1-M+1:0] tloga, /* M=11, [8:0] */
input wire [16+3-1-M+1:0] tlogb,
output wire [19:0] sumlog
);
/* adder, has 9 bits */
wire cin = tloga[0] & tlogb[0];
wire c14; /* carry of 14 bit */
MCLA_4_c_c4 MCLA_4_c_c4 (
.a (tloga[4:1]),
.b... | 7.061186 |
module Ring_Oscillator_TB ();
reg inp = 1'b1;
wire my_clock;
ring_oscillator #(5, 2) CUT1 (
inp,
my_clock
); //10ns here!
initial begin
#1000 $stop;
end
endmodule
| 6.585354 |
module SOA_11 #(
parameter M = 11
) (
input wire [16+3-1-M+1:0] tloga, /* M=11, [8:0] */
input wire [16+3-1-M+1:0] tlogb,
output wire [19:0] sumlog
);
/* adder, has 9 bits */
wire cin = tloga[0] & tlogb[0];
wire c14; /* carry of 14 bit */
MCLA_4_c_c4 MCLA_4_c_c4 (
.a (tloga[4:1]),
... | 7.176011 |
module SOA_5 #(
parameter M = 5
) (
input wire [16+3-1-M+1:0] tloga, /* M=5 , [14:0] */
input wire [16+3-1-M+1:0] tlogb,
output wire [19:0] sumlog,
output wire cin_EST /* cin of the EST */
);
/* adder, has 15 bits */
wire cin = tloga[0] & tlogb[0];
wire [15:0] A, B, S;
assign A = {2'b00,... | 7.905631 |
module sobelBufferBlock (
clk,
popBufferEn,
reset,
readData,
BufferA,
BufferB,
BufferC,
BufferD
);
parameter STARTADDRESS = 0, ENDADDRESS = 2097151, BEATS = 3, PAUSE = 1, PIXW = 24;
input clk, popBufferEn, reset;
input [63:0] readData;
output [63:0] BufferA;
output [63:0] Buff... | 6.911844 |
module sobelDir (
clk,
startEn,
reset,
sobelX,
sobelY,
dirE
);
parameter STARTADDRESS = 770, ENDADDRESS = 523518,BEATS = 4, PAUSE = 1,COUNTSTEPHOLD = 2, PIXW = 24;//address starts in and down two pixels ends the same. parameter can be imported to accommodate second concurrent pixel
param... | 6.563405 |
module sobelHoldBlock (
clk,
HoldEn,
reset,
ShiftA,
ShiftB,
ShiftC,
HoldOutA,
HoldOutB,
HoldOutC
);
parameter STARTADDRESS = 770, ENDADDRESS = 2097152 ,BEATS = 3, PAUSE = 1,COUNTSTEPHOLD = 2, PIXW = 24;//address starts in and down two pixels ends the same. parameter can be import... | 7.468646 |
module sobelMag (
clk,
startEn,
reset,
sobelX,
sobelY,
normalisedMag
);
parameter STARTADDRESS = 770, ENDADDRESS = 523518,BEATS = 4, PAUSE = 1,COUNTSTEPHOLD = 2, PIXW = 24;//address starts in and down two pixels ends the same. parameter can be imported to accommodate second concurrent pixel... | 6.895943 |
module sobelMultBlock (
clk,
startMultiplierEn,
reset,
sobelHoldOutA,
sobelHoldOutB,
sobelHoldOutC,
sobelX,
sobelY
);
parameter STARTADDRESS = 770, ENDADDRESS = 2097152/2,BEATS = 4, PAUSE = 1,COUNTSTEPHOLD = 2, PICW = 24;//address starts in and down two pixels ends the same. paramete... | 7.078334 |
module sobelTB ();
integer f;
parameter C0 = 3'b000, C1 = 3'b001, C2 = 3'b010, C3 = 3'b011, C4 = 3'b100;
wire [63:0] data1;
wire [63:0] data2;
wire [63:0] data3;
reg clk, we1, reset, startEn;
reg [ 2:0] addressCase;
wire [63:0] q1;
wire [63:0] q2;
wire [63:0] q3;
wire we2, getNext;
wire [ 7:0] ... | 6.962846 |
module sobel_add_nb #(
parameter bitwidth = 8
) (
a,
b,
ans_out,
cout,
subtract
); //parameter here
input [bitwidth-1:0] a;
input [bitwidth-1:0] b;
input subtract;
output cout;
output [bitwidth-1:0] ans_out;
wire [bitwidth-2:0] carry;
wire [bitwidth-1:0] bcomp;
`SR(s26, exoor ... | 6.671204 |
module sobel_edge_detect_tb;
reg clk;
reg pic_ena;
reg vs;
reg hs;
reg [7:0] median_filter_data = 8'b1111_1111;
wire post_vs;
wire post_hs;
wire post_pic_ena;
wire sobel_detect_data_bit;
sobel_edge_detect U_sobel_detect (
.clk(clk),
.rst(1'b0),
.pic_ena(1'b1), //图片使能，表示这个cl... | 7.090042 |
module sobel_filter #(
parameter VESA_STD = "VESA_180X720_60FPS",
parameter X_START = 0,
parameter Y_START = 0,
parameter X_END = 640,
parameter Y_END = 720,
parameter Y_DEPTH = 8,
parameter X_LSB_CNT_WIDTH = 4,
parameter X_MSB_CNT_WIDTH = 6,
parameter Y_LSB_CNT_WIDTH = 4,
param... | 8.441599 |
module sobel_filtering (
input clk,
input [ 7:0] Y_data,
input [10:0] key_value,
input Y_de,
Y_hsync,
Y_vsync,
output wire sobel_hsync,
sobel_vsync,
sobel_de,
output wire sobel_data
);
//sobel --------------------------------... | 7.040271 |
module sobel_func #(
parameter DATA_WIDTH = 8
) (
output wire [DATA_WIDTH-1:0] data_out,
input wire [DATA_WIDTH-1:0] in1,
input wire [DATA_WIDTH-1:0] in2,
input wire [DATA_WIDTH-1:0] in3,
input wire [DATA_WIDTH-1:0] in4,
input wire [DATA_WIDTH-1:0] in5,
input wire [DATA_WIDTH-1:0] ... | 7.294685 |
module sobel_image_rowregs (
// Clock and reset ports
input clk,
input reset,
// System-wide control signals
input go,
// Interface: Sobel Control -> Sobel Image Row Registers
input [`SOBEL_ROW_OP_WIDTH-1:0] sctl2srow_row_op, // command, specifies what to do w... | 7.403636 |
module sobel_shift (
aclr,
clken,
clock,
shiftin,
shiftout,
taps0x,
taps1x,
taps2x
);
input aclr;
input clken;
input clock;
input [0:0] shiftin;
output [0:0] shiftout;
output [0:0] taps0x;
output [0:0] taps1x;
output [0:0] taps2x;
`ifndef ALTERA_RESERVED_QIS
// synopsy... | 6.745861 |
module sobel_shift (
aclr,
clken,
clock,
shiftin,
shiftout,
taps0x,
taps1x,
taps2x
);
input aclr;
input clken;
input clock;
input [0:0] shiftin;
output [0:0] shiftout;
output [0:0] taps0x;
output [0:0] taps1x;
output [0:0] taps2x;
`ifndef ALTERA_RESERVED_QIS
// synopsy... | 6.745861 |
module Sobel (
input iCLK,
input iRST_N,
input [7:0] iTHRESHOLD,
input iDVAL,
input [9:0] iDATA,
output reg oDVAL,
output wire [9:0] oDATA
);
// mask x
parameter X1 = 8'hff, X2 = 8'h00, X3 = 8'h01;
parameter X4 = 8'hfe, X5 = 8'h00... | 7.299654 |
module sobel_test (
input clk,
input rst_n,
input [20:0] threshold,
input ycbcr_vs, //ԤͼЧź
input ycbcr_hs, //ԤͼЧź
input ycbcr_de, //ԤͼʹЧź
input [7:0] ycbcr_y,
output sobel_vs, //ͼЧź
output sobel_hs, //ͼЧź
output sobel_d... | 6.980404 |
module Sobel_Threshold_Adj (
//global clock
input clk, //100MHz
input rst_n, //global reset
//user interface
input key_flag, //key down flag
input [3:0] key_value, //key control data
output reg [3:0] Sobel_Grade, //Sobel Grade output
output reg [7:0] Sobel_Threshold //lcd pwn... | 7.53186 |
module sobel_top (
// sys
input wire vga_clk,
// key
input wire [10:0] iKey_value,
// input
input wire iVGA_de,
iVGA_hs,
iVGA_vs,
input wire [15:0] iRGB_565, // RGB565格式
// output
output wire oVGA_hs,
oVGA_vs,
oVGA_de,
output wire [15:... | 7.441768 |
module Sobol (
input clk,
input rst_n,
input start,
output [12:0] icdf
);
// ========== wire and reg ===================
wire [31:0] res_int32;
// ========== Sequential =====================
// ========== module instantiation ===========
Sobol_to_INT32 sobol_to_int32... | 6.558989 |
module socAhbApbBridge (
input HCLK,
input HRESETn, // active low reset
input [31:0] HADDR, // AHB Address
input [31:0] HWDATA, // write data from AHB Master
input HWRITE, // 1 = write, 0= read
input HSEL, // block select
input ... | 7.735282 |
module SoCBlackIce (
input wire clk,
input wire rx,
output wire tx,
output wire [3:0] status
);
assign status[3] = 0;
wire slowClock;
BlackIcePll pll (
.clock_in(clk),
.clock_out(slowClock),
.locked()
);
SoC #(
.clockRate(`BLACK_ICE_CLOCK_RATE)
) p0 (
.clk(sl... | 6.877513 |
module SoCIceStick (
input wire clk,
input wire rx,
output wire tx,
output wire status
);
SoC #(
.clockRate(`ICE_STICK_CLOCK_RATE)
) p0 (
.clk(clk),
.rx(rx),
.tx(tx),
.status(status)
);
endmodule
| 7.617993 |
module sockit_top (
input OSC_50_B8A,
inout AUD_ADCLRCK,
input AUD_ADCDAT,
inout AUD_DACLRCK,
output AUD_DACDAT,
output AUD_XCK,
inout AUD_BCLK,
output AUD_I2C_SCLK,
inout AUD_I2C_SDAT,
output AUD_MUTE,
input [3:0] KEY,
input [3:0] SW,
output [3:0] LED
);
... | 6.874833 |
module WishboneDevice (
input io_wbSlaveTransmitter_ready,
output io_wbSlaveTransmitter_bits_ack,
output [31:0] io_wbSlaveTransmitter_bits_dat,
output io_wbSlaveTransmitter_bits_err,
output io_wbMasterReceiver_ready,
input io_wbMasterReceiver_valid,
input... | 7.169291 |
module SubRegExt (
input io_we,
input [31:0] io_wd,
input [31:0] io_d,
output io_qe,
output [31:0] io_q,
output [31:0] io_qs
);
assign io_qe = io_we; // @[SubRegExt.scala 25:9]
assign io_q = io_wd; // @[SubRegExt.scala 24:8]
assign io_qs = io_d; // @[SubRegExt.scala 23... | 6.577328 |
module SubRegExt_2 (
input io_we,
input [15:0] io_wd,
input [15:0] io_d,
output io_qe,
output [15:0] io_q,
output [15:0] io_qs
);
assign io_qe = io_we; // @[SubRegExt.scala 25:9]
assign io_q = io_wd; // @[SubRegExt.scala 24:8]
assign io_qs = io_d; // @[SubRegExt.scala ... | 6.705049 |
module WishboneErr (
input clock,
input reset,
output [31:0] io_wbSlaveTransmitter_bits_dat,
output io_wbSlaveTransmitter_bits_err,
input io_wbMasterReceiver_valid,
input io_wbMasterReceiver_bits_cyc,
input io_wbMasterReceiver_bits_stb
);
`ifdef... | 7.966963 |
module InstructionFetch (
input [31:0] io_address,
output [31:0] io_instruction,
input io_coreInstrReq_ready,
output io_coreInstrReq_valid,
output [31:0] io_coreInstrReq_bits_addrRequest,
input io_coreInstrResp_valid,
input [31:0] io_coreInstrResp_bits_dataResponse
)... | 9.064394 |
module HazardUnit (
input io_id_ex_memRead,
input io_ex_mem_memRead,
input io_id_ex_branch,
input [4:0] io_id_ex_rd,
input [4:0] io_ex_mem_rd,
input [4:0] io_id_rs1,
input [4:0] io_id_rs2,
input io_taken,
input [1:0] io_jump,
input io_branc... | 8.02365 |
module BranchUnit (
input io_branch,
input [ 2:0] io_funct3,
input [31:0] io_rd1,
input [31:0] io_rd2,
input io_take_branch,
output io_taken
);
wire _T = 3'h0 == io_funct3; // @[Conditional.scala 37:30]
wire _T_2 = 3'h1 == io_funct3; // @[Conditional.scala 37:30]
... | 7.95714 |
module ALU (
input [31:0] io_input1,
input [31:0] io_input2,
input [ 3:0] io_aluCtl,
output [31:0] io_result
);
wire _T = io_aluCtl == 4'h0; // @[ALU.scala 17:18]
wire [31:0] _T_1 = io_input1 & io_input2; // @[ALU.scala 17:41]
wire _T_2 = io_aluCtl == 4'h1; // @[ALU.scala 18:18]
wire [31:0... | 7.960621 |
module AluControl (
input [1:0] io_aluOp,
input io_f7,
input [2:0] io_f3,
input io_aluSrc,
output [3:0] io_out
);
wire _T_1 = 3'h0 == io_f3; // @[Conditional.scala 37:30]
wire _T_3 = ~io_f7; // @[AluControl.scala 38:34]
wire [1:0] _GEN_0 = ~io_aluSrc | ~io_f7 ? 2'h2 : 2'h3; /... | 8.611802 |
module MemoryFetch(
input clock,
input reset,
input [31:0] io_aluResultIn,
input [31:0] io_writeData,
input io_writeEnable,
input io_readEnable,
output [31:0] io_readData,
output io_stall,
output io_dccmReq_valid,
output [31:0] io_dccmReq_bits_addrRequ... | 7.030255 |
module PC (
input clock,
input reset,
input [31:0] io_in,
input io_halt,
output [31:0] io_out,
output [31:0] io_pc4
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [31:0] pc_reg; // @[PC.scala 12:23]
wire [31:0] _T_2 = $signed(p... | 7.578567 |
module c2soc(input sys_clk_in,
/*****************************/
`include "socsignals.v"
/*****************************/
`ifdef SIMULATION
output FINISH,
`endif
input sys_reset);
wire ... | 7.096001 |
module halt (
input clk,
input rst,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we,
output reg FINISH
);
always @(posedge clk)
if (~rst) FINISH <= 0;
else begin
if (addr_b == 65541) FINISH <= 1;
end
endmodule
| 7.332862 |
module clockcounter (
input clk,
input rst,
input [31:0] data_a,
input [31:0] addr_a,
output reg [31:0] data_b,
output reg strobe_b,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we
);
reg [31:0] counter;
always @(posedge clk)
if (... | 6.814175 |
module clockcounter (
input clk,
input rst,
output [31:0] data_a,
input [31:0] addr_a,
output [31:0] data_b,
output strobe_b,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we
);
reg [31:0] counter;
assign strobe_b = (addr_b == 65542);
assign da... | 6.814175 |
module fpga_gf2m
#(
parameter DIGITAL = 8,
parameter DATA_WIDTH = 163
)(
input clk, // Clock
input rst, // Asynchronous reset active low
input wire start,
input wire [DATA_WIDTH - 1 : 0] a,
input wire [DATA_WIDTH - 1 : 0] g,
input wire [BWIDTH - 1:0] b,
output reg [DATA_WIDTH - 1 : 0] t_i_j,
output reg do... | 7.172496 |
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