code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module snake_cpu_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
);
output [4:0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [4:0] fifo_cnt_inc;
always @(empty or ge2_free or ge3_free or input_tm_cnt) begin
if (empty) fifo_cnt_inc = input_tm_cnt[1 : 0];
else if (ge3_free & (input_tm_cnt == 3)) fifo_cnt_inc = 2;
else if (ge2_free & (input_tm_cnt >= 2)) fifo_cnt_inc = 1;
else if (input_tm_cnt >= 1) fifo_cnt_inc = 0;
else fifo_cnt_inc = {5{1'b1}};
end
endmodule
| 6.6395 |
module snake_cpu_cpu_nios2_oci_pib (
// outputs:
tr_data
);
output [35:0] tr_data;
wire [35:0] tr_data;
assign tr_data = 0;
endmodule
| 6.6395 |
module snake_cpu_cpu_nios2_oci_im (
// inputs:
clk,
jrst_n,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
);
output tracemem_on;
output [35:0] tracemem_trcdata;
output tracemem_tw;
output [6:0] trc_im_addr;
output trc_wrap;
output xbrk_wrap_traceoff;
input clk;
input jrst_n;
input [15:0] trc_ctrl;
input [35:0] tw;
wire tracemem_on;
wire [35:0] tracemem_trcdata;
wire tracemem_tw;
reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [35:0] trc_im_data;
wire trc_on_chip;
reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire tw_valid;
wire xbrk_wrap_traceoff;
assign trc_im_data = tw;
always @(posedge clk or negedge jrst_n) begin
if (jrst_n == 0) begin
trc_im_addr <= 0;
trc_wrap <= 0;
end else begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
end
assign trc_on_chip = ~trc_ctrl[8];
assign tw_valid = |trc_im_data[35 : 32];
assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
assign tracemem_trcdata = 0;
endmodule
| 6.6395 |
module snake_cpu_cpu_nios2_performance_monitors;
endmodule
| 6.6395 |
module snake_cpu_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
);
output [31:0] oci_ienable;
output [31:0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [8:0] address;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [31:0] writedata;
reg [31:0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [31:0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) oci_single_step_mode <= 1'b0;
else if (take_action_ocireg) oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) oci_ienable <= 32'b00000000000000000000001111111111;
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000000000001111111111);
end
endmodule
| 6.6395 |
module snake_cpu_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input [7:0] address;
input [3:0] byteenable;
input clock;
input [31:0] data;
input reset_req;
input wren;
wire clocken;
wire [31:0] q;
wire [31:0] ram_q;
assign q = ram_q;
assign clocken = ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clock),
.clocken0(clocken),
.data_a(data),
.q_a(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.init_file = lpm_file, the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 256, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 8;
endmodule
| 6.6395 |
module for the classic snake game
// re-imagined in hardware.
// --------------------------------------------------------------------------
module snake_device (
input i_Clk,
input i_Rst,
input [3:0] i_Direction,
output wire [6:0] o_ScoreDisplay,
output wire [3:0] o_Red,
output wire [3:0] o_Green,
output wire [3:0] o_Blue,
output wire o_HSync,
output wire o_VSync,
output wire [3:0] o_SegmentSelect
);
parameter CLK_FREQ = 106470000;
parameter REFRESH_RATE = 20;
parameter SCOREBOARD_CLK_FREQ = 4096;
parameter DISPLAY_WIDTH = 1440;
parameter DISPLAY_HEIGHT = 900;
parameter CELLS_WIDTH = 32;
parameter CELLS_HEIGHT = 32;
parameter LFSR_DEPTH = $clog2(CELLS_WIDTH*CELLS_HEIGHT);
parameter LFSR_INIT = 12'hC75;
parameter MAX_7SEG = 16;
wire w_SnakeClk;
wire w_ScoreClk;
wire w_GameOver;
wire [MAX_7SEG-1:0] w_Score;
wire [LFSR_DEPTH-1:0] w_Food;
wire [LFSR_DEPTH-1:0] w_RNG;
wire [(CELLS_WIDTH+1) * (CELLS_HEIGHT+1)-1:0] w_SnakeGrid;
wire [3:0] w_Direction;
localparam TEST_7SEG = { 4'd8, 4'd1, 4'd7, 4'd0 };
clock_divider
#(
.DIV(CLK_FREQ / REFRESH_RATE)
) clk_to_snake (
.i_clk(i_Clk),
.o_clk(w_SnakeClk)
);
clock_divider
#(
.DIV(CLK_FREQ / SCOREBOARD_CLK_FREQ)
) clk_to_scoreboard (
.i_clk(i_Clk),
.o_clk(w_ScoreClk)
);
snake_game
#(
.c_GRID_IDX_SZ(LFSR_DEPTH),
.c_WIDTH(CELLS_WIDTH),
.c_HEIGHT(CELLS_HEIGHT)
) game_logic (
.i_Clk(w_SnakeClk),
.i_Rst(i_Rst),
.i_Direction(w_Direction),
.i_FoodLocation(w_RNG),
.o_Kill(w_GameOver),
.o_SnakeGrid(w_SnakeGrid),
.o_Food(w_Food),
.o_Score(w_Score)
);
lfsr
#(
.DEPTH(LFSR_DEPTH),
.INIT(LFSR_INIT)
) random_cell_generator (
.i_Clk(i_Clk),
.i_Rst(i_Rst),
.o_Data(w_RNG)
);
snake_to_vga
#(
.c_WIDTH(CELLS_WIDTH),
.c_HEIGHT(CELLS_HEIGHT),
.c_GRID_IDX_SZ(LFSR_DEPTH),
.c_SCREEN_WIDTH(DISPLAY_WIDTH),
.c_SCREEN_HEIGHT(DISPLAY_HEIGHT)
) vga_wrapper (
.i_Clk(i_Clk),
.i_Rst(i_Rst),
.i_GameOver(w_GameOver),
.i_SnakeGrid(w_SnakeGrid),
.i_Food(w_Food),
.o_Red(o_Red),
.o_Green(o_Green),
.o_Blue(o_Blue),
.o_HSync(o_HSync),
.o_VSync(o_VSync)
);
snake_scoreboard
#(
.SCORE_WIDTH(MAX_7SEG)
) score_wrapper (
.i_Clk(w_ScoreClk),
.i_Score(TEST_7SEG),
.o_ScoreDisplay(o_ScoreDisplay),
.o_SegmentSelect(o_SegmentSelect)
);
Basys3_button_debouncer
#(
) direction_debouncer (
.i_Clk(i_Clk),
.i_Buttons(i_Direction),
.o_Buttons(w_Direction)
);
endmodule
| 7.733567 |
module snake_game (
i_Clk,
i_Rst,
i_Direction,
i_FoodLocation,
o_Kill,
o_SnakeGrid,
o_Food,
o_Score
);
// Size of indexing for accessing locations on game grid.
parameter c_GRID_IDX_SZ = 10;
// Cell width and height of the snake game.
parameter c_WIDTH = 32;
parameter c_HEIGHT = 32;
parameter SCORE_WIDTH = 14;
// Specified list on inputs and outputs
input [c_GRID_IDX_SZ-1:0] i_FoodLocation;
input i_Clk;
input i_Rst;
input [3:0] i_Direction;
output reg o_Kill;
output reg [(c_WIDTH+1)*(c_HEIGHT+1)-1:0] o_SnakeGrid = 0;
output reg [c_GRID_IDX_SZ-1:0] o_Food = 0;
output reg [SCORE_WIDTH-1:0] o_Score = 0;
localparam [3:0] RIGHT = 4'b0001;
localparam [3:0] LEFT = 4'b0010;
localparam [3:0] UP = 4'b0100;
localparam [3:0] DOWN = 4'b1000;
// Indices to check for snake out of bounds
integer IdxH = 0;
integer IdxV = 0;
// Counter representing the number of nodes to add to the snake.
reg [1:0] r_FoodCount = 0;
// Center starting snake cell
reg [c_GRID_IDX_SZ-1:0] r_Head = (c_WIDTH * c_HEIGHT) / 2 + c_WIDTH / 2;
reg [c_GRID_IDX_SZ-1:0] r_Tail = (c_WIDTH * c_HEIGHT) / 2 + c_WIDTH / 2;
// Update the snake grid by moving the tail
// to the head. Leave the tail if food was recently
// collected.
always @(posedge (i_Clk) or posedge (i_Rst)) begin
if (i_Rst == 1'b1) begin
o_SnakeGrid <= 'b0;
o_Score <= 'b0;
end else begin
case (i_Direction)
RIGHT: begin
o_SnakeGrid[r_Head+1] <= 1'b1; // right
r_Head <= r_Head + 1;
end
LEFT: begin
o_SnakeGrid[r_Head-1] <= 1'b1; // left
r_Head <= r_Head - 1;
end
UP: begin
o_SnakeGrid[r_Head+c_WIDTH] <= 1'b1; // up
r_Head <= r_Head + c_WIDTH;
end
DOWN: begin
o_SnakeGrid[r_Head-c_WIDTH] <= 1'b1; // down
r_Head <= r_Head + -c_WIDTH;
end
default: r_Head <= r_Head; // still
endcase
if (r_FoodCount == 0) begin
o_SnakeGrid[r_Tail] <= 1'b0;
end else begin
o_SnakeGrid[r_Tail] <= 1'b1;
r_FoodCount <= r_FoodCount - 1;
end
// This will not work effectively
// TODO: FIFO of direction changes with counter
// for each entry to remove from FIFO. Represents
// direction to change the tail of the snake.
if (o_SnakeGrid[r_Tail+1] == 1'b1) begin
r_Tail <= r_Tail + 1;
end else if (o_SnakeGrid[r_Tail-1] == 1'b1) begin
r_Tail <= r_Tail - 1;
end else if (o_SnakeGrid[r_Tail+c_WIDTH] == 1'b1) begin
r_Tail <= r_Tail + c_WIDTH;
end else begin
r_Tail <= r_Tail - c_WIDTH;
end
// Check for snake overlapping food
if (o_Food == r_Head) begin
o_Score <= o_Score + 1;
r_FoodCount <= 'd3;
o_Food <= i_FoodLocation;
end
end
end
// Check for snake out of bounds
always @* begin
o_Kill <= 1'b0;
for (IdxH = 0; IdxH < c_WIDTH; IdxH = IdxH + 1) begin
if (o_SnakeGrid[IdxH] == 1'b1) begin
o_Kill <= 1'b1;
end else if (o_SnakeGrid[c_WIDTH*(c_HEIGHT-1)+IdxH] == 1'b1) begin
o_Kill <= 1'b1;
end
end
for (IdxV = 1; IdxV < c_HEIGHT; IdxV = IdxV + 1) begin
if (o_SnakeGrid[c_WIDTH*IdxV] == 1'b1) begin
o_Kill <= 1'b1;
end else if (o_SnakeGrid[(c_WIDTH+1)*IdxV-1] == 1'b1) begin
o_Kill <= 1'b1;
end
end
end
endmodule
| 7.089979 |
module snake_hex2 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [7:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:0] writedata;
wire clk_en;
reg [ 7:0] data_out;
wire [ 7:0] out_port;
wire [ 7:0] read_mux_out;
wire [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8{(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 136;
else if (chipselect && ~write_n && (address == 0)) data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
| 6.597919 |
module snake_master (
input wire sys_clk, //输入工作时钟,频率50MHz
input wire sys_rst_n, //输入复位信号,低电平有效
input wire key1,
input wire key2,
input wire key3,
input wire key4,
output wire ddc_scl,
output wire ddc_sda,
output wire tmds_clk_p,
output wire tmds_clk_n, //HDMI时钟差分信号
output wire [2:0] tmds_data_p,
output wire [2:0] tmds_data_n //HDMI图像差分信号
);
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire vga_clk; //VGA工作时钟,频率25MHz
wire clk_5x;
wire locked; //PLL locked信号
wire rst_n; //VGA模块复位信号
wire [11:0] pix_x; //VGA有效显示区域X轴坐标
wire [11:0] pix_y; //VGA有效显示区域Y轴坐标
wire [15:0] pix_data; //VGA像素点色彩信息
wire hsync; //输出行同步信号
wire vsync; //输出场同步信号
wire [15:0] rgb; //输出像素信息
wire rgb_valid;
wire flag;
wire [ 3:0] direction;
//rst_n:VGA模块复位信号
assign rst_n = (sys_rst_n & locked);
assign ddc_scl = 1'b1;
assign ddc_sda = 1'b1;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- clk_gen_inst -------------
clk_gen clk_gen_inst (
.areset(~sys_rst_n), //输入复位信号,高电平有效,1bit
.inclk0(sys_clk), //输入50MHz晶振时钟,1bit
.c0 (vga_clk), //输出VGA工作时钟,频率25Mhz,1bit
.c1 (clk_5x),
.locked(locked) //输出pll locked信号,1bit
);
//------------- vga_ctrl_inst -------------
vga_ctrl vga_ctrl_inst (
.vga_clk (vga_clk), //输入工作时钟,频率25MHz,1bit
.sys_rst_n(rst_n), //输入复位信号,低电平有效,1bit
.pix_data (pix_data), //输入像素点色彩信息,16bit
.pix_x (pix_x), //输出VGA有效显示区域像素点X轴坐标,10bit
.pix_y (pix_y), //输出VGA有效显示区域像素点Y轴坐标,10bit
.hsync (hsync), //输出行同步信号,1bit
.vsync (vsync), //输出场同步信号,1bit
.rgb_valid(rgb_valid),
.rgb (rgb) //输出像素点色彩信息,16bit
);
//------------- vga_pic_inst -------------
vga_pic vga_pic_inst (
.vga_clk (vga_clk), //输入工作时钟,频率25MHz,1bit
.sys_rst_n(rst_n), //输入复位信号,低电平有效,1bit
.pix_x (pix_x), //输入VGA有效显示区域像素点X轴坐标,10bit
.pix_y (pix_y), //输入VGA有效显示区域像素点Y轴坐标,10bit
.flag (flag),
.direction(direction),
.pix_data(pix_data) //输出像素点色彩信息,16bit
);
//------------- hdmi_ctrl_inst -------------
hdmi_ctrl hdmi_ctrl_inst (
.clk_1x (vga_clk), //输入系统时钟
.clk_5x (clk_5x), //输入5倍系统时钟
.sys_rst_n (rst_n), //复位信号,低有效
.rgb_blue ({rgb[4:0], 3'b0}), //蓝色分量
.rgb_green ({rgb[10:5], 2'b0}), //绿色分量
.rgb_red ({rgb[15:11], 3'b0}), //红色分量
.hsync (hsync), //行同步信号
.vsync (vsync), //场同步信号
.de (rgb_valid), //使能信号
.hdmi_clk_p(tmds_clk_p),
.hdmi_clk_n(tmds_clk_n), //时钟差分信号
.hdmi_r_p (tmds_data_p[2]),
.hdmi_r_n (tmds_data_n[2]), //红色分量差分信号
.hdmi_g_p (tmds_data_p[1]),
.hdmi_g_n (tmds_data_n[1]), //绿色分量差分信号
.hdmi_b_p (tmds_data_p[0]),
.hdmi_b_n (tmds_data_n[0]) //蓝色分量差分信号
);
clk_1 clk_1_inst (
.vga_clk (sys_clk), //输入工作时钟,频率25MHz
.sys_rst_n(rst_n), //输入复位信号,低电平有效
.flag(flag)
);
direction_gen direction_gen_inst (
.clk (sys_clk),
.rst_n(rst_n),
.key1 (key1),
.key2 (key2),
.key3 (key3),
.key4 (key4),
.direction(direction)
);
endmodule
| 8.451556 |
module Snake_pll_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [2:1] CLK_OUT,
// High bits of counters driven by clocks
output [2:1] COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
localparam NUM_C = 2;
genvar count_gen;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
reg [NUM_C:1] rst_sync;
reg [NUM_C:1] rst_sync_int;
reg [NUM_C:1] rst_sync_int1;
reg [NUM_C:1] rst_sync_int2;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk_n;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Instantiation of the clocking network
//--------------------------------------
Snake_pll clknetwork ( // Clock in ports
.CLK_IN1 (CLK_IN1),
// Clock out ports
.CLK_OUT1(clk_int[1]),
.CLK_OUT2(clk_int[2]),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED)
);
genvar clk_out_pins;
generate
for (
clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1
) begin : gen_outclk_oddr
assign clk_n[clk_out_pins] = ~clk[clk_out_pins];
ODDR2 clkout_oddr (
.Q (CLK_OUT[clk_out_pins]),
.C0(clk[clk_out_pins]),
.C1(clk_n[clk_out_pins]),
.CE(1'b1),
.D0(1'b1),
.D1(1'b0),
.R (1'b0),
.S (1'b0)
);
end
endgenerate
// Connect the output clocks to the design
//-----------------------------------------
assign clk[1] = clk_int[1];
assign clk[2] = clk_int[2];
// Reset synchronizer
//-----------------------------------
generate
for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin : counters_1
always @(posedge reset_int or posedge clk[count_gen]) begin
if (reset_int) begin
rst_sync[count_gen] <= 1'b1;
rst_sync_int[count_gen] <= 1'b1;
rst_sync_int1[count_gen] <= 1'b1;
rst_sync_int2[count_gen] <= 1'b1;
end else begin
rst_sync[count_gen] <= 1'b0;
rst_sync_int[count_gen] <= rst_sync[count_gen];
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
end
end
end
endgenerate
// Output clock sampling
//-----------------------------------
generate
for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin : counters
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
if (rst_sync_int2[count_gen]) begin
counter[count_gen] <= #TCQ{C_W{1'b0}};
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
endmodule
| 6.509577 |
module Snake_pll_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.0 * ONE_NS;
localparam time PER1_1 = PER1 / 2;
localparam time PER1_2 = PER1 - PER1 / 2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [ 2:1] COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
wire [ 2:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1 * 6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1 * 6);
COUNTER_RESET = 1;
#(PER1 * 19.5) COUNTER_RESET = 0;
#(PER1 * 1) $display("Timing checks are valid");
test_phase = "counting";
#(PER1 * COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n", $time / PER1);
$finish;
end
always @(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n", $time / PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
Snake_pll_exdes dut ( // Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET(COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED)
);
// Freq Check
endmodule
| 7.130611 |
modules.
// --------------------------------------------------------------------------
module snake_scoreboard
(
i_Clk,
i_Score,
o_ScoreDisplay,
o_SegmentSelect
);
// Four BCD digits
parameter SCORE_WIDTH = 16;
input wire i_Clk;
input wire [SCORE_WIDTH-1:0] i_Score;
output reg [6:0] o_ScoreDisplay;
output reg [3:0] o_SegmentSelect;
localparam c_RESET_SR = 4'b1110;
reg [3:0] r_Selected_Segment = 4'b0000; // Selected digit
reg [1:0] r_SegCounter = 2'b00;
integer r_Score;
localparam SS_0 = 7'b0000001;
localparam SS_1 = 7'b1001111;
localparam SS_2 = 7'b0010010;
localparam SS_3 = 7'b0000110;
localparam SS_4 = 7'b1001100;
localparam SS_5 = 7'b0100100;
localparam SS_6 = 7'b0100000;
localparam SS_7 = 7'b0001111;
localparam SS_8 = 7'b0000000;
localparam SS_9 = 7'b0000100;
always @ (posedge(i_Clk)) begin
r_SegCounter <= r_SegCounter + 1;
end
always @* begin // Select digit to display
case (r_SegCounter)
2'b11 : begin
r_Selected_Segment <= i_Score[15:12];
o_SegmentSelect <= 4'b0111;
end
2'b10 : begin
r_Selected_Segment <= i_Score[11:8];
o_SegmentSelect <= 4'b1011;
end
2'b01 : begin
r_Selected_Segment <= i_Score[7:4];
o_SegmentSelect <= 4'b1101;
end
default : begin
r_Selected_Segment <= i_Score[3:0];
o_SegmentSelect <= 4'b1110;
end
endcase
end
always @* begin // Select 7-Segment pin assertions
case (r_Selected_Segment)
4'd0: o_ScoreDisplay = SS_0;
4'd1: o_ScoreDisplay = SS_1;
4'd2: o_ScoreDisplay = SS_2;
4'd3: o_ScoreDisplay = SS_3;
4'd4: o_ScoreDisplay = SS_4;
4'd5: o_ScoreDisplay = SS_5;
4'd6: o_ScoreDisplay = SS_6;
4'd7: o_ScoreDisplay = SS_7;
4'd8: o_ScoreDisplay = SS_8;
default: o_ScoreDisplay = SS_9;
endcase
end
endmodule
| 6.986352 |
module for snake game.
// --------------------------------------------------------------------------
module snake_scoreboard_tb ();
`timescale 1ns/1ns
time clk_period = 100;
localparam N_TESTS = 5; // Number of test cases for UUT
localparam SCORE_WIDTH = 16; // Number of bits needed for 4-digit decimal
localparam SS_0 = 8'b00000011;
localparam SS_1 = 8'b10011111;
localparam SS_2 = 8'b00100101;
localparam SS_3 = 8'b00001101;
localparam SS_4 = 8'b10011001;
localparam SS_5 = 8'b01001001;
localparam SS_6 = 8'b01000001;
localparam SS_7 = 8'b00011111;
localparam SS_8 = 8'b00000001;
localparam SS_9 = 8'b00011001;
reg [SCORE_WIDTH-1:0] ScoreArray [N_TESTS-1:0];
reg [27:0] ScoreDispArray [N_TESTS-1:0];
reg tb_Clk = 1'b0;
reg [SCORE_WIDTH-1:0] tb_Score = 'b0;
wire [6:0] tb_ScoreDisplay;
wire [3:0] tb_SegmentSelect;
integer test_idx;
integer digit_idx;
initial
begin
// Begin initialize test arrays
ScoreArray[0] = { 4'd1, 4'd2, 4'd3, 4'd4 };
ScoreDispArray[0] = { SS_1, SS_2, SS_3, SS_4 };
ScoreArray[1] = { 4'd9, 4'd8, 4'd7, 4'd6 };
ScoreDispArray[1] = { SS_9, SS_8, SS_7, SS_6 };
ScoreArray[2] = { 4'd0, 4'd5, 4'd5, 4'd0 };
ScoreDispArray[2] = { SS_0, SS_5, SS_5, SS_0 };
ScoreArray[3] = { 4'd2, 4'd3, 4'd3, 4'd03 };
ScoreDispArray[3] = { SS_2, SS_3, SS_3, SS_3 };
ScoreArray[4] = { 4'd9, 4'd8, 4'd9, 4'd8 };
ScoreDispArray[4] = { SS_9, SS_8, SS_9, SS_8 };
// End initialize test arrays
for (test_idx = 0; test_idx < N_TESTS; test_idx = test_idx+1) begin
tb_Score <= ScoreArray[test_idx];
for (digit_idx = 0; digit_idx < 4; digit_idx = digit_idx+1) begin
#clk_period;
case (tb_SegmentSelect) // Determine which segment should be displayed
4'b0001 :
if (tb_ScoreDisplay !== tb_Score[3:0])
$display("Test %d failed : Digit 0 - "
| "Expected %d, Received %d",
| test_idx, tb_Score % 10, tb_ScoreDisplay);
4'b0010 :
if (tb_ScoreDisplay !== tb_Score[7:4])
$display("Test %d failed : Digit 1 - "
| "Expected %d, Received %d",
| test_idx, tb_Score[7:4], tb_ScoreDisplay);
4'b0100 :
if (tb_ScoreDisplay !== tb_Score[11:8])
$display("Test %d failed : Digit 2 - "
| "Expected %d, Received %d",
| test_idx, tb_Score[11:8], tb_ScoreDisplay);
4'b1000 :
if (tb_ScoreDisplay !== tb_Score[15:12])
$display("Test %d failed : Digit 3 - "
| "Expected %d, Received %d",
| test_idx, tb_Score[15:12], tb_ScoreDisplay);
default : $display("Test %d failed : "
| "Unexpected segment select value: %b",
| test_idx+1, tb_SegmentSelect);
endcase
end
end
end
// Generate clock signal
always #(clk_period/2) tb_Clk = ~tb_Clk;
// Instantiate the Unit Under Test : snake_scoreboard
snake_scoreboard #(
.SCORE_WIDTH(SCORE_WIDTH)
) UUT (
.i_Clk(tb_Clk),
.i_Score(tb_Score),
.o_ScoreDisplay(tb_ScoreDisplay),
.o_SegmentSelect(tb_SegmentSelect)
);
endmodule
| 7.611139 |
module snake_seven_seg_display (
input CLOCK,
input [4:0] len,
output [3:0] an,
output [7:0] seg
);
reg SIGNAL = 0;
reg [3:0] anode;
reg [7:0] cath;
wire [7:0] cath_1, cath_2;
snake_output_decimal D (
len,
cath_1,
cath_2
);
always @(posedge CLOCK) begin
case (SIGNAL)
0: begin
anode <= 4'b0001;
cath <= cath_1;
SIGNAL <= SIGNAL + 1;
end
1: begin
anode <= 4'b0010;
cath <= cath_2;
SIGNAL <= SIGNAL + 1;
end
endcase
end
assign seg = cath;
assign an = ~anode;
endmodule
| 6.768718 |
module Snake_top (
input clk,
input rst_n,
input [3:0] cmd_out,
output [1:0] gamestate,
output [1:0] direct,
output [3:0] scorel,
output [3:0] scorem,
output [ 5:0] food_x,
output [ 4:0] food_y,
output [999:0] map,
output [ 5:0] head_x,
output [ 4:0] head_y
);
wire [5:0] foodx;
wire [4:0] foody;
wire [5:0] headx;
wire [4:0] heady;
wire add_body;
wire hit;
// wire [1:0]gamestate;
assign food_x = foodx;
assign food_y = foody;
assign head_x = headx;
assign head_y = heady;
Snake_food U1 (
.clk(clk),
.rst_n(rst_n),
.food_x(foodx),
.food_y(foody),
.add_body(add_body),
.head_x(headx),
.head_y(heady)
);
Game_ctrl U2 (
.clk(clk),
.rst_n(rst_n),
.gamestate(gamestate),
.cmd_out(cmd_out),
.hit(hit)
);
Snake U3 (
.clk(clk),
.rst_n(rst_n),
.cmd_out(cmd_out),
.gamestate(gamestate),
.add_body(add_body),
.hit(hit),
.map(map),
.head_x(headx),
.head_y(heady)
, .direct(direct),
.scorel(scorel),
.scorem(scorem)
);
endmodule
| 7.006251 |
module random_props (
clk,
rand_X,
rand_Y
);
input clk;
output reg [7:0] rand_X;
output reg [6:0] rand_Y;
// set the maximum height and width of the game interface.
// x and y will scan over every pixel.
integer max_height = 100;
integer max_width = 140;
always @(posedge clk) begin
if (rand_X === max_width) rand_X <= 6;
else rand_X <= rand_X + 1;
end
always @(posedge clk) begin
if (rand_X === max_width) begin
if (rand_Y === max_height) rand_Y <= 6;
else rand_Y <= rand_Y + 1;
end
end
endmodule
| 6.88726 |
module delay_counter (
clk,
reset_n,
en_delay,
delayed_clk,
main_difficulty
);
input clk;
input reset_n;
input en_delay;
input [3:0] main_difficulty;
output delayed_clk;
reg [3:0] delay;
// Register for the delay counter
always @(posedge clk) begin
// if (!reset_n)
// delay <= 20'd840000;
if (delay == main_difficulty) delay <= 0;
else if (en_delay) begin
delay <= delay + 1'b1;
end
end
assign delayed_clk = (delay == main_difficulty) ? 1 : 0;
endmodule
| 6.853164 |
module to a VGA signal.
// --------------------------------------------------------------------------
module snake_to_vga
(
i_Clk,
i_Rst,
i_GameOver,
i_SnakeGrid,
i_Food,
o_Red,
o_Green,
o_Blue,
o_HSync,
o_VSync
);
parameter c_WIDTH = 32;
parameter c_HEIGHT = 32;
parameter c_GRID_IDX_SZ = 10;
parameter c_SCREEN_WIDTH = 1440;
parameter c_SCREEN_HEIGHT = 900;
// Eventually change to params to make application more generic.
localparam c_VGA_POLARITY_X = 1'b0;
localparam c_VGA_POLARITY_Y = 1'b1;
localparam c_FRONT_PORCH_END_H = 1520;
localparam c_SYNC_PULSE_END_H = 1672;
localparam c_BACK_PORCH_END_H = 1904;
localparam c_FRONT_PORCH_END_V = 901;
localparam c_SYNC_PULSE_END_V = 904;
localparam c_BACK_PORCH_END_V = 932;
// Max value to VGA DAC = 16, currently set to half for testing
localparam c_COLOR_HIGH = 4'd8;
localparam c_COLOR_LOW = 4'd0;
// Each pixel is x^2 (= 16 pixels) wide
localparam c_SQUARE_PIXEL_SHIFT = 4;
localparam c_GAME_PIXEL_WIDTH = c_WIDTH * (2**c_SQUARE_PIXEL_SHIFT);
localparam c_GAME_PIXEL_HEIGHT = c_HEIGHT * (2**c_SQUARE_PIXEL_SHIFT);
localparam c_PIXEL_TO_CELL_SHIFT = $clog2(c_WIDTH);
localparam c_X_PIXEL_IDX_SZ = $clog2(c_SCREEN_WIDTH)-1;
localparam c_Y_PIXEL_IDX_SZ = $clog2(c_SCREEN_HEIGHT);
// Input / Output list
input i_Clk;
input i_Rst;
input i_GameOver;
input [(c_WIDTH+1)*(c_HEIGHT+1)-1:0] i_SnakeGrid;
input [c_GRID_IDX_SZ-1:0] i_Food;
output reg [3:0] o_Red;
output reg [3:0] o_Green;
output reg [3:0] o_Blue;
output o_HSync;
output o_VSync;
// Current display location for VGA
wire [c_X_PIXEL_IDX_SZ:0] w_Pixel_X = 0;
wire [c_Y_PIXEL_IDX_SZ:0] w_Pixel_Y = 0;
always @(posedge(i_Clk) or posedge(i_Rst)) begin
if (i_Rst == 1'b1) begin
o_Red <= c_COLOR_LOW;
o_Green <= c_COLOR_LOW;
o_Blue <= c_COLOR_HIGH;
end else if (w_Pixel_X > c_GAME_PIXEL_WIDTH ||
w_Pixel_Y > c_GAME_PIXEL_HEIGHT) begin
o_Red <= c_COLOR_LOW;
o_Green <= c_COLOR_LOW;
o_Blue <= c_COLOR_HIGH;
end else if (i_GameOver == 1'b1) begin
o_Red <= c_COLOR_LOW;
o_Green <= c_COLOR_LOW;
o_Blue <= c_COLOR_LOW;
end else if (w_Pixel_X[c_X_PIXEL_IDX_SZ:c_SQUARE_PIXEL_SHIFT] == 'b0 ||
w_Pixel_X[c_X_PIXEL_IDX_SZ:c_SQUARE_PIXEL_SHIFT] == c_WIDTH ||
w_Pixel_Y[c_Y_PIXEL_IDX_SZ:c_SQUARE_PIXEL_SHIFT] == 'b0 ||
w_Pixel_Y[c_Y_PIXEL_IDX_SZ:c_SQUARE_PIXEL_SHIFT] == c_HEIGHT) begin
o_Red <= c_COLOR_HIGH;
o_Green <= c_COLOR_LOW;
o_Blue <= c_COLOR_LOW;
end else if (w_Pixel_X[c_X_PIXEL_IDX_SZ:c_SQUARE_PIXEL_SHIFT] == i_Food) begin
o_Red <= c_COLOR_HIGH;
o_Green <= c_COLOR_LOW;
o_Blue <= c_COLOR_LOW;
end else if ( i_SnakeGrid[ { w_Pixel_Y[c_Y_PIXEL_IDX_SZ:c_SQUARE_PIXEL_SHIFT], c_PIXEL_TO_CELL_SHIFT }
+ w_Pixel_X[c_X_PIXEL_IDX_SZ:c_SQUARE_PIXEL_SHIFT] ] == 1'b1) begin
o_Red <= c_COLOR_LOW;
o_Green <= c_COLOR_HIGH;
o_Blue <= c_COLOR_HIGH;
end else begin
o_Red <= c_COLOR_LOW;
o_Green <= c_COLOR_LOW;
o_Blue <= c_COLOR_LOW;
end
end
signal_generator_coords
#(
.pol_x(c_VGA_POLARITY_X),
.pol_y(c_VGA_POLARITY_Y),
.h_visible_area_end(c_SCREEN_WIDTH),
.h_front_porch_end(c_FRONT_PORCH_END_H),
.h_sync_pulse_end(c_SYNC_PULSE_END_H),
.h_back_porch_end(c_BACK_PORCH_END_H),
.v_visible_area_end(c_SCREEN_HEIGHT),
.v_front_porch_end(c_FRONT_PORCH_END_V),
.v_sync_pulse_end(c_SYNC_PULSE_END_V),
.v_back_porch_end(c_BACK_PORCH_END_V)
) vga_signal (
.i_clk(i_Clk),
.i_rst(i_Rst),
.o_h_sync(o_HSync),
.o_v_sync(o_VSync),
.o_x(w_Pixel_X),
.o_y(w_Pixel_Y)
);
endmodule
| 6.992135 |
module Sna_Request_Transimtter (
clock,
addr,
data,
read,
pov_addr,
is_valid,
is_on_off,
is_allocatable,
araddr,
arvalid,
arready,
awaddr,
awvalid,
awready,
wdata,
wvalid,
wready,
pov_addr_buffer
);
input clock;
input [31:0] addr;
input [31:0] data;
input read;
input [3:0] pov_addr;
input is_valid;
output reg [7:0] is_on_off;
output reg [7:0] is_allocatable;
output reg [31:0] araddr;
output reg arvalid;
input arready;
output reg [31:0] awaddr;
output reg awvalid;
input awready;
output reg [31:0] wdata;
output reg wvalid;
input wready;
output reg [3:0] pov_addr_buffer;
reg [ 2:0] state = 3'b000;
reg [ 3:0] reg_pov_addr;
reg [31:0] reg_addr;
reg [31:0] reg_data;
parameter IDLE = 3'b000;
parameter WREQ1 = 3'b001;
parameter WREQ2 = 3'b010;
parameter WREQ3 = 3'b011;
parameter RREQ1 = 3'b100;
parameter RREQ2 = 3'b101;
always @(clock) begin
if (state == IDLE) begin
arvalid <= 0;
awvalid <= 0;
wvalid <= 0;
is_allocatable <= 8'b00000001;
is_on_off <= 8'b00000001;
repeat (1) begin
@(clock);
end
if (is_valid == 1 && read == 0) begin
is_allocatable <= 8'b00000000;
is_on_off <= 8'b00000000;
reg_pov_addr <= pov_addr;
repeat (1) begin
@(clock);
end
state <= WREQ1;
end
if (is_valid == 1 && read == 1) begin
is_allocatable <= 8'b00000000;
is_on_off <= 8'b00000000;
reg_pov_addr <= pov_addr;
repeat (1) begin
@(clock);
end
state <= RREQ1;
end
end
if (state == WREQ1) begin
is_on_off <= 8'b00000001;
repeat (1) begin
@(clock);
end
if (is_valid == 1) begin
reg_addr <= addr;
is_on_off <= 8'b00000000;
repeat (1) begin
@(clock);
end
state <= WREQ2;
end
end
if (state == WREQ2) begin
is_on_off <= 8'b00000001;
repeat (1) begin
@(clock);
end
if (is_valid == 1) begin
reg_data <= data;
is_on_off <= 8'b00000000;
repeat (1) begin
@(clock);
end
state <= WREQ3;
end
end
if (state == WREQ3) begin
if (awready == 1 && wready == 1) begin
pov_addr_buffer <= reg_pov_addr;
awaddr <= reg_addr;
awvalid <= 1;
wdata <= reg_data;
wvalid <= 1;
repeat (1) begin
@(clock);
end
state <= IDLE;
end
end
if (state == RREQ1) begin
is_on_off <= 8'b00000001;
repeat (1) begin
@(clock);
end
if (is_valid == 1) begin
reg_addr <= addr;
is_on_off <= 8'b00000000;
repeat (1) begin
@(clock);
end
state <= RREQ2;
end
end
if (state == RREQ2) begin
if (arready == 1) begin
pov_addr_buffer <= reg_pov_addr;
araddr <= reg_addr;
arvalid <= 1;
repeat (1) begin
@(clock);
end
state <= IDLE;
end
end
end
endmodule
| 6.866102 |
module snd (
input clk, // system clock
input rst, // system reset
input cs, // chip select
input we, // write enable
input [3:0] addr, // register select
input [7:0] din, // data bus input
output reg [7:0] dout, // data bus output
output snd_l, // left 1-bit DAC output
output snd_r, // right 1-bit DAC output
output snd_nmute // /mute output
);
// write control registers
reg [7:0] f_lo[3:0];
reg [15:0] frq[3:0];
reg [2:0] wave[3:0];
reg [7:0] gain[3:0];
integer i;
always @(posedge clk)
if (rst) begin
for (i = 0; i <= 3; i = i + 1) begin
f_lo[i] <= 8'h00;
frq[i] <= 16'h0000;
end
end else if (cs & we)
case (addr[1:0])
2'h0: f_lo[addr[3:2]] <= din;
2'h1: frq[addr[3:2]] <= {din, f_lo[addr[3:2]]};
2'h2: wave[addr[3:2]] <= din[2:0];
2'h3: gain[addr[3:2]] <= din;
endcase
// read registers
always @(posedge clk)
if (cs & !we)
case (addr[1:0])
2'h0: dout <= frq[addr[3:2]][7:0];
2'h1: dout <= frq[addr[3:2]][15:8];
2'h2: dout <= {5'h00, wave[addr[3:2]]};
2'h3: dout <= gain[addr[3:2]];
default: dout <= 8'h00;
endcase
// sine LUT
reg signed [15:0] sine_lut[255:0];
initial $readmemh("../src/sine.hex", sine_lut, 0);
// NCOs and SD acc
reg [1:0] seq, seq_d1;
reg [23:0] phs[3:0];
reg carry;
reg [19:0] noise[3:0];
reg [16:0] seq_phs;
reg [15:0] sine;
reg [15:0] wv;
reg [7:0] seq_gain;
reg [23:0] wv_scl;
reg [16:0] sd_acc;
always @(posedge clk)
if (rst) begin
seq <= 2'b00;
for (i = 0; i <= 3; i = i + 1) phs[i] <= 24'h000000;
sd_acc <= 17'h00000;
end else begin
// sequential count to index all four voices
seq <= seq + 2'b01;
// 24-bit NCO with carry output
{carry, phs[seq]} <= {1'b0, phs[seq]} + {9'h00, frq[seq]};
// select phase
seq_d1 <= seq;
seq_phs <= phs[seq][23:7];
// sine shaping
sine <= sine_lut[phs[seq][23:16]];
// 16-bit noise generation from 2^20-1 LFSR
if (carry)
noise[seq] <= {
noise[seq][3:0], // top 4 are just shifted
~(noise[seq][19:4] ^ noise[seq][16:1])
};
// wave shaping
seq_gain <= gain[seq_d1];
case (wave[seq_d1])
3'b000: wv <= seq_phs[16:1]; // saw up
3'b001: wv <= seq_phs[16] ? 16'hffff : 16'h0000; // square
3'b010: wv <= seq_phs[16] ? ~seq_phs[15:0] : seq_phs[15:0]; // triangle
3'b011: wv <= sine ^ 16'h8000; // offset-binary sine
3'b100: wv <= noise[seq][19] ? 16'hffff : 16'h0000; // 1-bit noise
3'b101: wv <= noise[seq][15:0]; // 16-bit noise
default: wv <= ~seq_phs[16:1]; // saw down
endcase
// gain scaling
wv_scl <= wv * seq_gain;
// 1st-order sigma-delta
sd_acc <= {1'b0, sd_acc[15:0]} + {1'b0, wv_scl[23:8]};
end
// sigma-delta output is carry output of accum
assign snd_l = sd_acc[16];
assign snd_r = sd_acc[16];
assign snd_nmute = 1'b1;
endmodule
| 7.131703 |
module sndfifo (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrusedw
);
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output [11:0] rdusedw;
output [11:0] wrusedw;
wire [31:0] sub_wire0;
wire sub_wire1;
wire [11:0] sub_wire2;
wire [11:0] sub_wire3;
wire [31:0] q = sub_wire0[31:0];
wire rdempty = sub_wire1;
wire [11:0] rdusedw = sub_wire2[11:0];
wire [11:0] wrusedw = sub_wire3[11:0];
dcfifo dcfifo_component (
.data(data),
.rdclk(rdclk),
.rdreq(rdreq),
.wrclk(wrclk),
.wrreq(wrreq),
.q(sub_wire0),
.rdempty(sub_wire1),
.rdusedw(sub_wire2),
.wrusedw(sub_wire3),
.aclr(),
.eccstatus(),
.rdfull(),
.wrempty(),
.wrfull()
);
defparam dcfifo_component.intended_device_family = "Cyclone IV E",
dcfifo_component.lpm_numwords = 4096, dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = 32,
dcfifo_component.lpm_widthu = 12, dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4, dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON", dcfifo_component.wrsync_delaypipe = 4;
endmodule
| 6.896764 |
module sndfifo (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrusedw
);
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output [11:0] rdusedw;
output [11:0] wrusedw;
endmodule
| 6.896764 |
module snd_buffer (
input CLK,
input BCLK,
input RST_X,
input VIF_SNDRDATAVLD,
input [63:0] VIF_RDATA,
input FIFO_READ_R,
input FIFO_READ_L,
output BUF_WREADY,
output [31:0] FIFO_DOUT_R, //32 bit
output [31:0] FIFO_DOUT_L //32 bit
);
wire rst;
wire fifo_full_r, fifo_full_l;
wire fifo_empty_r, fifo_empty_l;
wire fifo_valid_r, fifo_valid_l;
wire [8:0] fifo_wcount_r, fifo_wcount_l;
// for write
wire fifo_wr_r, fifo_wr_l;
wire [63:0] fifo_din;
// for read
wire fifo_rd_r, fifo_rd_l;
wire [31:0] fifo_dout_r, fifo_dout_l;
assign rst = ~RST_X;
// Xillinx FIFO
// Input and output to FIFO
fifo_64in32out_512depth u_fifo_right (
//in
.din (fifo_din),
.rd_clk (BCLK),
.rd_en (fifo_rd_r),
.rst (rst),
.wr_clk (CLK),
.wr_en (fifo_wr_r),
//out
.dout (fifo_dout_r),
.empty (fifo_empty_r),
.full (fifo_full_r),
.valid (fifo_valid_r),
.wr_data_count(fifo_wcount_r)
);
fifo_64in32out_512depth u_fifo_left (
//in
.din (fifo_din),
.rd_clk(BCLK),
.rd_en (fifo_rd_l),
.rst (rst),
.wr_clk(CLK),
.wr_en (fifo_wr_l),
//out
.dout (fifo_dout_l),
.empty (fifo_empty_l),
.full (fifo_full_l),
.valid (fifo_valid_l),
.wr_data_count(fifo_wcount_l)
);
/* --- fifo in --- */
//fifo_wr
assign fifo_wr_r = VIF_SNDRDATAVLD & !(fifo_full_r);
assign fifo_wr_l = VIF_SNDRDATAVLD & !(fifo_full_l);
//fifo_rd
assign fifo_rd_r = FIFO_READ_R & !(fifo_empty_r); //emptyr
assign fifo_rd_l = FIFO_READ_L & !(fifo_empty_l); //emptyr
//fifo_din
assign fifo_din = VIF_RDATA;
/* --- fifo out --- */
//fifo_wcount
assign BUF_WREADY = (fifo_wcount_r < 9'd256);
//fifo_dout
assign FIFO_DOUT_R[31:0] = fifo_dout_r[31:0];
assign FIFO_DOUT_L[31:0] = fifo_dout_l[31:0];
endmodule
| 6.616602 |
module snd_clkgen (
input CLK,
input RST_X,
output reg SND_LRCLK,
output reg SND_BCLK,
output reg SND_MCLK,
output [6:0] LRCLK_COUNT,
output [6:0] BCLK_COUNT,
output [6:0] MCLK_COUNT
);
reg [6:0] lrclk_count; //0-63 7bit
reg [6:0] bclk_count; //0-34 7bit
reg [6:0] mclk_count; //0-8 7bit
assign LRCLK_COUNT = lrclk_count;
assign BCLK_COUNT = bclk_count;
assign MCLK_COUNT = mclk_count;
// mclk_count
always @(negedge CLK or negedge RST_X) begin
if (!RST_X) mclk_count <= 0;
else if (mclk_count == 8) mclk_count <= 0;
else mclk_count <= mclk_count + 1;
end
// bclk_count
always @(negedge CLK or negedge RST_X) begin
if (!RST_X) bclk_count <= 0;
else if (bclk_count == 34) bclk_count <= 0;
else bclk_count <= bclk_count + 1;
end
// lrclk_count
always @(posedge SND_BCLK or negedge RST_X) begin
if (!RST_X) lrclk_count <= 0;
else if (lrclk_count == 63) lrclk_count <= 0;
else lrclk_count <= lrclk_count + 1;
/*
else if(bclk_count == 17 && lrclk_count == 63)
lrclk_count <= 0;
else if(bclk_count == 17)
lrclk_count <= lrclk_count + 1;
*/
end
// SND_MCLK
always @(posedge CLK or negedge RST_X) begin
if (!RST_X) SND_MCLK <= 1'b1;
else begin
if (mclk_count == 3) SND_MCLK <= 1'b0;
else if (mclk_count == 8) SND_MCLK <= 1'b1;
end
end
// SND_BCLK
always @(posedge CLK or negedge RST_X) begin
if (!RST_X) SND_BCLK <= 1'b1;
else begin
if (bclk_count == 17) SND_BCLK <= 1'b0;
else if (bclk_count == 34) SND_BCLK <= 1'b1;
end
end
// SND_LRCLK
always @(negedge SND_BCLK or negedge RST_X) begin
if (!RST_X) SND_LRCLK <= 1'b0;
else begin
if (lrclk_count == 31) SND_LRCLK <= 1'b1;
else if (lrclk_count == 63) SND_LRCLK <= 1'b0;
end
end
endmodule
| 6.88369 |
module snd_outgen (
input BCLK,
input RST_X,
input SND_LRCLK,
input [6:0] LRCLK_COUNT,
//input [31:0] FIFO_DOUT,
input [15:0] L_SNDDATA,
input [15:0] R_SNDDATA,
input [ 1:0] REG_CMD,
input [31:0] REG_STATUS,
input [31:0] REG_DELAY,
output reg FIFO_READ_R,
output reg FIFO_READ_L,
output reg SND_DOUT //output 1bit one by one
);
wire [6:0] lrclk_count; //0-63 7bit
assign lrclk_count = LRCLK_COUNT;
reg [4:0] half_count; //0-15 5bit
reg [15:0] L_SNDDATA_DE, R_SNDDATA_DE;
wire [15:0] L_SNDDATA_OUT, R_SNDDATA_OUT;
//Right delay data
always @(negedge SND_LRCLK or negedge RST_X) begin
if (!RST_X) R_SNDDATA_DE <= 16'b0;
else R_SNDDATA_DE <= R_SNDDATA;
end
//Left delay data
always @(negedge SND_LRCLK or negedge RST_X) begin
if (!RST_X) L_SNDDATA_DE <= 16'b0;
else L_SNDDATA_DE <= L_SNDDATA;
end
assign L_SNDDATA_OUT = L_SNDDATA;
assign R_SNDDATA_OUT = R_SNDDATA;
// SND_DOUT
always @(negedge BCLK or negedge RST_X) begin
if (!RST_X) SND_DOUT <= 1'b0;
else begin
if (REG_CMD == 2'b01) begin //ԂĐȂΊJn
if (lrclk_count >= 0 && lrclk_count <= 15) begin
//SND_DOUT <= 0;
SND_DOUT <= L_SNDDATA_OUT[15-lrclk_count]; //0 - 15
end else if (lrclk_count >= 32 && lrclk_count <= 47)
//SND_DOUT <= 0;
SND_DOUT <= R_SNDDATA_OUT[47-lrclk_count]; //0 - 15
else SND_DOUT <= 0;
end
end
end
// half_count
always @(posedge BCLK or negedge RST_X) begin
if (!RST_X) half_count <= 1'b0;
else begin
if (half_count == 14) half_count <= 0;
else if (lrclk_count == 62) half_count <= half_count + 1;
end
end
reg [20:0] delay_count; //max1048575
reg DELAY_SIG;
// delay_count
always @(negedge SND_LRCLK or negedge RST_X) begin
if (!RST_X) delay_count <= 20'b0;
else begin
if (delay_count > 1048000) delay_count <= 20'b0;
else delay_count <= delay_count + 20'b1;
end
end
always @(negedge SND_LRCLK or negedge RST_X) begin
if (!RST_X) DELAY_SIG <= 1'b0;
else begin
if (delay_count == REG_DELAY) DELAY_SIG <= 1'b1;
end
end
// FIFO_READ_R
always @(posedge BCLK or negedge RST_X) begin
if (!RST_X) FIFO_READ_R <= 1'b0;
else begin
if (REG_STATUS == 32'h0000_0000 && lrclk_count == 62) //normal
FIFO_READ_R <= 1;
else if (REG_STATUS == 32'h0000_0001 && (lrclk_count == 62 || lrclk_count == 30)) //2x
FIFO_READ_R <= 1;
else if(REG_STATUS == 32'h0000_0002 && lrclk_count == 62) begin //1/2x combine with half_count
if ((half_count % 2) == 0) FIFO_READ_R <= 1;
else FIFO_READ_R <= 0;
end
else if(REG_STATUS == 32'h0000_0003 && (lrclk_count == 62 || lrclk_count == 20 || lrclk_count == 40)) //3{
FIFO_READ_R <= 1;
else FIFO_READ_R <= 0;
end
end
// FIFO_READ_L
always @(posedge BCLK or negedge RST_X) begin
if (!RST_X) FIFO_READ_L <= 1'b0;
else begin
if (DELAY_SIG == 1'b1) begin
if (REG_STATUS == 32'h0000_0000 && lrclk_count == 62) //norma,
FIFO_READ_L <= 1;
else if (REG_STATUS == 32'h0000_0001 && (lrclk_count == 62 || lrclk_count == 30)) //2x
FIFO_READ_L <= 1;
else if(REG_STATUS == 32'h0000_0002 && lrclk_count == 62) begin //1/2x combine with half_count
if ((half_count % 2) == 0) FIFO_READ_L <= 1;
else FIFO_READ_L <= 0;
end
else if(REG_STATUS == 32'h0000_0003 && (lrclk_count == 62 || lrclk_count == 20 || lrclk_count == 40)) //3{
FIFO_READ_L <= 1;
else FIFO_READ_L <= 0;
end
end
end
endmodule
| 7.479288 |
module trans_socket #(
parameter AW = 12, // NOT LESS THAN 10
parameter DW = 8, // 16 FOR SIMULATION ,8 FOR REAL USE
parameter MAX_PACK_LEN = 8100,
parameter PADDING_INFO_LEN = 0 //0...8
) (
input clk,
rst, //cfg if //axi stream to ether if
input [DW-1:0] fifo_dat,
input fifo_wr,
output fifo_full,
//ether udp if
input m_udp_pack_ready,
output reg m_udp_pack_valid = 0,
output reg [15:0] m_udp_tx_len = 0,
output reg [DW-1:0] m_udp_tx_dat = 0,
output reg m_udp_tx_start = 0,
output reg m_udp_tx_end = 0,
input [7:0] inf0,
inf1,
inf2,
inf3,
inf4,
inf5,
inf6,
inf7,
output reg [7:0] st
);
localparam MAX_PACK_LEN_P4 = MAX_PACK_LEN + PADDING_INFO_LEN;
///always @ (posedge clk ) if (s_valid) m_udp_port <= cfg_udp_port ;
wire [DW-1:0] fifo_u8, fwft_dout;
wire [AW:0] fifo_cntr;
wire [DW-1:0] u8;
reg rd_fifo;
wire wr_fifo = fifo_wr & ~full;
sc_fifo_4_socket #(
.AW(AW),
.DW(DW)
) sc_fifo_4_socket (
.clk(clk),
.rst(rst),
.din(fifo_dat),
.wr(wr_fifo),
.full(full),
.dout(fifo_u8),
.rd(rd_fifo),
.empty(empty),
.fwft_dout(fwft_dout),
.fifo_cntr(fifo_cntr)
);
reg [15:0] wait_cntr;
wire wait_cntr_of = wait_cntr >= 512; /// |wait_cntr [15:8];///>= 256 ;
wire fifo_cntr_of = fifo_cntr >= MAX_PACK_LEN;
reg [7:0] inf0r, inf1r, inf2r, inf3r, inf4r, inf5r, inf6r, inf7r;
always @(posedge clk) inf0r <= inf0;
always @(posedge clk) inf1r <= inf1;
always @(posedge clk) inf2r <= inf2;
always @(posedge clk) inf3r <= inf3;
always @(posedge clk) inf4r <= inf4;
always @(posedge clk) inf5r <= inf5;
always @(posedge clk) inf6r <= inf6;
always @(posedge clk) inf7r <= inf7;
always @(posedge clk)
case (st)
32: m_udp_tx_dat <= inf0r;
33: m_udp_tx_dat <= inf1r;
34: m_udp_tx_dat <= inf2r;
35: m_udp_tx_dat <= inf3r;
36: m_udp_tx_dat <= inf4r;
37: m_udp_tx_dat <= inf5r;
38: m_udp_tx_dat <= inf6r;
39: m_udp_tx_dat <= inf7r;
default m_udp_tx_dat <= fifo_u8;
endcase
always @(posedge clk)
if (rst | empty | wr_fifo | m_udp_tx_start) wait_cntr <= 0;
else if (wait_cntr_of == 0) wait_cntr <= wait_cntr + 1;
reg [15:0] fifo_rd_len;
reg [15:0] c;
always @(posedge clk)
case (st)
20: c <= 1 + c;
default c <= 1;
endcase
reg m_udp_tx_start_d1, m_udp_tx_start_d2;
always @(posedge clk)
m_udp_tx_start_d1 <= (st == 20) && (c == 1); //cam accept one as less as one byte
always @(posedge clk) m_udp_tx_start_d2 <= m_udp_tx_start_d1;
always @(posedge clk) m_udp_tx_start <= m_udp_tx_start_d2;
wire [15:0] fifo_cntr_p4 = fifo_cntr + PADDING_INFO_LEN;
always @(posedge clk)
if (st == 11)
m_udp_tx_len <= (fifo_cntr_of) ? (MAX_PACK_LEN_P4) : (fifo_cntr_p4);
always @(posedge clk) if (st == 11) fifo_rd_len <= (fifo_cntr_of) ? (MAX_PACK_LEN) : (fifo_cntr);
always @(posedge clk) m_udp_pack_valid <= st == 11;
always @(posedge clk)
if (rst) st <= 0;
else
case (st)
0: st <= 10;
10: if (wait_cntr_of == 1 || fifo_cntr_of == 1) st <= 11;
11: if (m_udp_pack_ready) st <= 20; //wait ready
20: if (c == fifo_rd_len) st <= 30; //dump bytes
30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42: st <= st + 1; // wait periods
43: st <= 10;
default st <= 0;
endcase
always @(posedge clk) rd_fifo <= st == 20;
assign fifo_full = full;
endmodule
| 7.586291 |
module sc_fifo_4_socket #(
parameter AW = 5,
parameter DW = 64
) (
input clk,
rst,
input [DW-1:0] din,
input wr,
rd,
output full,
empty,
output reg [DW-1:0] dout,
output [DW-1:0] fwft_dout,
output reg [AW:0] fifo_cntr
);
parameter MAX_FIFO_LEN = (1 << AW);
reg [DW-1:0] buff[0:MAX_FIFO_LEN -1];
reg [AW-1:0] wr_ptr, rd_ptr;
assign full = fifo_cntr >= (MAX_FIFO_LEN - 16);
assign empty = fifo_cntr == 0;
wire valid_rd = rd;
wire valid_wr = wr;
always @(posedge clk)
if (rst) wr_ptr <= 0;
else if (valid_wr) wr_ptr <= wr_ptr + 1;
always @(posedge clk)
if (rst) rd_ptr <= 0;
else if (valid_rd) rd_ptr <= rd_ptr + 1;
always @(posedge clk)
casex ({
rst, valid_wr, valid_rd
})
3'b1xx: fifo_cntr <= 0;
3'b010: fifo_cntr <= fifo_cntr + 1;
3'b001: fifo_cntr <= fifo_cntr - 1;
3'b011, 3'b000: fifo_cntr <= fifo_cntr;
endcase
always @(posedge clk) if (valid_wr) buff[wr_ptr] <= din;
always @(posedge clk) if (valid_rd) dout <= buff[rd_ptr];
assign fwft_dout = buff[rd_ptr];
endmodule
| 6.996741 |
module snd_vramctrl (
input CLK,
input RST_X,
input [22:0] REG_VRAMADR,
input BUF_WREADY,
input [ 1:0] REG_CMD,
input REG_LOOP,
input [31:0] REG_MUSIC,
input VIF_SNDACK,
input VIF_SNDRDATAVLD,
input [63:0] VIF_RDATA,
output SND_VRAMREQ,
output [22:0] SND_VRAMADR,
output reg PLAY_NOW
);
reg [22:0] addcount; //read timing
reg endflg; //flag of music end
// state values
reg [2:0] state, nextState;
parameter S_IDLE = 3'b000;
parameter S_PLAY = 3'b001;
parameter S_PAUSE = 3'b010;
parameter S_WAIT = 3'b011;
parameter S_END = 3'b100;
//send a request if state == play
assign SND_VRAMREQ = (state == S_PLAY) && BUF_WREADY;
//REG_VRAMADR + read timing
assign SND_VRAMADR = {REG_VRAMADR + addcount};
/* not used */
// PLAY_NOW ... output singnal if state == play
always @(posedge CLK or negedge RST_X) begin
if (!RST_X) PLAY_NOW <= 1'b0;
else if (state == S_PLAY) PLAY_NOW <= 1'b1;
else PLAY_NOW <= 1'b0;
end
// addcount
always @(posedge CLK or negedge RST_X) begin
if (!RST_X) addcount <= 23'b0;
else if ( /*state == S_PLAY && */ addcount == (REG_MUSIC)) addcount <= 23'b0;
else if ((SND_VRAMREQ == 1) && (VIF_SNDACK == 1)) addcount <= addcount + 23'b1;
end
// endflg
always @(posedge CLK or negedge RST_X) begin
if (!RST_X) endflg <= 1'b0;
else if (state == S_PLAY && (addcount + 1) == REG_MUSIC) // -1 to fix gap
endflg <= 1'b1;
else endflg <= 1'b0;
end
// state FF
always @(posedge CLK, negedge RST_X) begin
if (!RST_X) state <= S_IDLE;
else state <= nextState;
end
// state machine
always @* begin
case (state)
S_IDLE:
if (REG_CMD == 2'b01) nextState <= S_PLAY;
else nextState <= S_IDLE;
S_PLAY: //001
if (REG_CMD == 2'b11) nextState <= S_IDLE; //~
else if (REG_CMD == 2'b10) nextState <= S_PAUSE;
//music end && not loop -> end
else if (endflg == 1'b1 && REG_LOOP == 1'b0) nextState <= S_END;
//music end && loop -> play
//else if( endflg == 1'b1 && REG_LOOP == 1'b1 ) nextState <= S_IDLE;
else if (endflg == 1'b1 && REG_LOOP == 1'b1) nextState <= S_PLAY;
else if (BUF_WREADY == 1'b0) nextState <= S_WAIT;
else nextState <= S_PLAY;
S_PAUSE: //010
if (REG_CMD == 2'b01) nextState <= S_PLAY;
else if (REG_CMD == 2'b11) nextState <= S_IDLE;
else nextState <= S_PAUSE;
S_WAIT: //011
if (BUF_WREADY == 1'b1) nextState <= S_PLAY;
else nextState <= S_WAIT;
S_END: //100
if (REG_CMD != 2'b01) nextState <= S_IDLE;
else nextState <= S_END;
default: nextState <= S_IDLE;
endcase
end
endmodule
| 7.310725 |
module snek (
CLOCK_50,
SW,
LEDR,
KEY,
// TODO: Keyboard inputs
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B
);
input CLOCK_50;
input [9:0] SW; //
input [3:0] KEY;
output [9:0] LEDR;
// TODO: Keyboard inputs
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK_N; // VGA BLANK
output VGA_SYNC_N; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
wire [7:0] x_to_draw;
wire [6:0] y_to_draw;
wire [2:0] colour_to_draw;
wire go;
wire init;
wire play;
draw d (
.board_clock(CLOCK_50),
.go(go),
.in_x(x_to_draw),
.in_y(y_to_draw),
.in_colour(colour_to_draw),
.resetn(SW[0]),
.VGA_CLK(VGA_CLK),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK_N(VGA_BLANK_N),
.VGA_SYNC_N(VGA_SYNC_N)
);
wire [1:0] direction; // bit 1 is axis (x = 0, y = 1), bit 0 is pos/neg.
wire alive;
convert_directions cd (
.up(~KEY[2]),
.down(~KEY[1]),
.left(~KEY[3]),
.right(~KEY[0]),
.resetn(SW[0]),
.clock(CLOCK_50),
.direction(direction)
);
datapath dp (
.clock(CLOCK_50),
.play(play),
.direction(direction),
.resetn(SW[0]),
.in(init),
.alive(alive),
.go(go),
.x_to_draw(x_to_draw),
.y_to_draw(y_to_draw),
.colour_to_draw(colour_to_draw)
);
control c (
.go(SW[1]),
.alive(alive),
.resetn(SW[0]),
.play(play),
.init(init),
.current_s(LEDR[3:2]),
.next_s(LEDR[1:0]),
.clock(CLOCK_50)
);
endmodule
| 7.040318 |
module control (
input go,
input alive,
input resetn,
input clock,
output reg play,
output reg init,
output [1:0] current_s,
output [1:0] next_s
);
localparam S_START = 2'b0, S_INIT = 2'b1, S_PLAY = 2'b10;
reg [1:0] current_state, next_state;
assign current_s = current_state;
assign next_s = next_state;
always @(*) begin : state_table
case (current_state)
S_START: next_state = go ? S_INIT : S_START;
S_INIT: next_state = go ? S_INIT : S_PLAY;
S_PLAY: next_state = alive ? S_PLAY : S_START;
default: next_state = S_START;
endcase
end
always @(*) begin : enable_signals
case (current_state)
S_START: begin
init <= 1'b0;
play <= 1'b0;
end
S_INIT: begin
init <= 1'b1;
play <= 1'b1;
end
S_PLAY: begin
init <= 1'b0;
play <= 1'b1;
end
endcase
end
always @(posedge clock) begin : state_FFs
if (!resetn) begin
current_state <= S_START;
end else begin
current_state <= next_state;
end
end
endmodule
| 7.715617 |
module and the port sync module is that the port
// sync module has read and write enable signals to help realize the bus access. This
// module just observe the address bus for "address switches". Once this module synchronizes
// an address bus "switch" then logic in the 40Mhz domain can safely analyse Address A bus
// accesses. We use this in SNES-Tap to help locate when the processor accesses the reset vector
// and the NMI vector.
module snes_bus_sync (
input clk, // clock (40 MHz and reset)
input rst_n,
input [7:0] PA, // RAW SNES addr bus
output event_latch // Bus change event (detects changes in PA)
);
parameter OUT_OF_SYNC = 1'b1;
parameter IN_SYNC = 1'b0;
reg [7:0] PA_store [0:1];
reg sync_state = IN_SYNC;
reg bus_latch = 0;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
PA_store[0] <= 8'b0; // reset all regs
PA_store[1] <= 8'b0;
bus_latch <= 1'b0;
sync_state <= IN_SYNC;
end
else begin
PA_store[0] <= PA; // These registers are used for both metastability protection
PA_store[1] <= PA_store[0]; // and for address bus "change" detection (3 stages)
if (sync_state == IN_SYNC) begin // IN_SYNC state means the bus has settled and events/outputs have been reported
// The addr bus has been pipelined for 3 stages, move into the OUT_OF_SYNC state once a change in addr is detected
// we also ignore this check if 5 cycles haven't gone by on the previous check
if (((PA != PA_store[0]) || (PA_store[1] != PA_store[0]))) begin
sync_state <= OUT_OF_SYNC; // go to OUT_OF_SYNC
bus_latch <= 0; // initialize
end
end else if (sync_state == OUT_OF_SYNC) begin
bus_latch <= 0;
// The addr bus has under gone a change, detect when it has settled and move back into IN_SYNC
if ((PA == PA_store[0]) && (PA_store[1] == PA_store[0])) begin
bus_latch <= 1;
sync_state <= IN_SYNC;
end
end
end
end
// Report back safe synchronized bus events and data/addr
assign event_latch = bus_latch;
endmodule
| 7.845611 |
module snes_bus_sync_test ();
reg clk = 0;
reg cycle_clk = 0;
reg rst_n = 0;
reg [7:0] PA = 0;
reg [7:0] D = 0;
wire [7:0] PA_sync;
wire [7:0] D_sync;
wire event_latch;
reg PARD_n = 1;
snes_bus_sync bs (
.clk (clk), // clock (40 MHz and reset)
.rst_n (rst_n),
.PA (PA), // RAW SNES addr bus
.event_latch(event_latch) // Bus change event (detects changes in PA)
);
always #14.3 clk = ~clk;
always #139.6 cycle_clk = ~cycle_clk;
initial #1000 rst_n = 1;
always @(posedge cycle_clk) begin
if (PARD_n) PARD_n = $random % 2;
else PARD_n = 1;
D = $random;
#2;
D = $random;
#2;
D = $random;
#2;
D = $random;
#2;
D = $random;
#2;
end
always @(posedge cycle_clk) begin
PA = $random;
#2;
PA = $random;
#2;
PA = $random;
#2;
PA = $random;
#2;
PA = $random;
#2;
end
endmodule
| 6.552602 |
module snes_dejitter (
input MCLK_XTAL_i, //NTSC master clock source: 21.477272MHz from oscillator circuit
input MCLK_EXT_i, //PAL master clock source: 21.28137MHz (3-CHIP) or 17.73MHz (1-CHIP) from external source
input MCLK_SEL_i, //Output clock/csync mode: De-jitter/NTSC (0), Bypass/PAL (1)
input CSYNC_i,
output MCLK_XTAL_o,
output GCLK_o,
output CSYNC_o,
output reg SC_o
);
wire mclk_ntsc = MCLK_XTAL_i;
wire mclk_ntsc_dejitter = mclk_ntsc & gclk_en;
wire mclk_pal = MCLK_EXT_i;
assign GCLK_o = MCLK_SEL_i ? mclk_pal : mclk_ntsc_dejitter;
assign CSYNC_o = MCLK_SEL_i ? CSYNC_i : csync_dejitter;
assign MCLK_XTAL_o = ~MCLK_XTAL_i;
reg [10:0] h_cnt;
reg [2:0] g_cyc;
reg csync_prev;
reg csync_dejitter;
reg gclk_en;
reg [1:0] sc_ctr;
always @(posedge mclk_ntsc) begin
if ((h_cnt >= 1024) && (csync_prev == 1'b1) && (CSYNC_i == 1'b0)) begin
h_cnt <= 0;
if (h_cnt == 340 * 4 - 1) g_cyc <= 4;
else csync_dejitter <= CSYNC_i;
end else begin
h_cnt <= h_cnt + 1'b1;
if (g_cyc > 0) g_cyc <= g_cyc - 1'b1;
if (g_cyc <= 1) csync_dejitter <= CSYNC_i;
end
csync_prev <= CSYNC_i;
end
always @(posedge mclk_ntsc) begin
if (sc_ctr == 2'h2) begin
sc_ctr <= 2'h0;
SC_o <= ~SC_o;
end else begin
sc_ctr <= sc_ctr + 2'h1;
end
end
`ifdef EDGE_SENSITIVE_CLKEN
//Update clock gate enable signal on negative edge
always @(negedge mclk_ntsc) begin
gclk_en <= (g_cyc == 0);
end
`else
//ATF1502AS macrocells support D latch mode,
//enabling level sensitive update of gclk_en during negative phase
always @(*) begin
if (!mclk_ntsc) gclk_en <= (g_cyc == 0);
end
`endif
endmodule
| 6.758675 |
module snes_gamepad
//
// Dependencies: snes_gamepad_ctrl
//
////////////////////////////////////////////////////////////////////////////////
module snes_gamepad_tb;
// INPUTS //////////////////////////////////////////////////////////////////////
reg clk;
reg rst;
reg rd;
reg snes_data;
// OUTPUTS /////////////////////////////////////////////////////////////////////
wire busy;
wire snes_latch;
wire snes_clk;
wire [15:0] buttons;
// CONSTANTS ///////////////////////////////////////////////////////////////////
localparam T_clk = 10; // clock period (ns)
// SIGNAL DECLARATION //////////////////////////////////////////////////////////
reg gamepad [0:15];
integer i;
// MODULES /////////////////////////////////////////////////////////////////////
snes_gamepad uut
(
.clk(clk),
.rst(rst),
.rd(rd),
.busy(busy),
.snes_latch(snes_latch),
.snes_clk(snes_clk),
.snes_data(snes_data),
.buttons(buttons)
);
// CLOCK ///////////////////////////////////////////////////////////////////////
// 100 MHz clock
always
begin
clk = 1;
#(T_clk / 2);
clk = 0;
#(T_clk / 2);
end
// MAIN ////////////////////////////////////////////////////////////////////////
initial
begin
initialize();
// read command
@(posedge clk) rd = 1;
@(posedge clk) rd = 0;
@(negedge busy) $stop; // wait until busy signal clear and stop
end
// GAMEPAD SIMULATION //////////////////////////////////////////////////////////
// button data
initial
begin
gamepad[0] = 0;
gamepad[1] = 1;
gamepad[2] = 1;
gamepad[3] = 1;
gamepad[4] = 1;
gamepad[5] = 1;
gamepad[6] = 1;
gamepad[7] = 1;
gamepad[8] = 0;
gamepad[9] = 1;
gamepad[10] = 1;
gamepad[11] = 1;
gamepad[12] = 1;
gamepad[13] = 1;
gamepad[14] = 1;
gamepad[15] = 0;
end
// SNES gamepad shift register simulation
always
begin
wait(snes_latch); // wait for the latch signal
// first button (B) on the SNES data signal after latch complete
@(negedge snes_latch) snes_data = gamepad[0];
// shift the SNES buttons on each SNES clock posedge
for(i = 1; i < 16; i = i + 1)
@(posedge snes_clk) snes_data = gamepad[i];
// always end with SNES data high
@(posedge snes_clk) snes_data = 1;
end
// TASKS ///////////////////////////////////////////////////////////////////////
// initialize
task initialize;
begin
rst = 0;
rd = 0;
snes_data = 1;
reset_async();
end
endtask
// asynchronous reset
task reset_async;
begin
rst = 1;
#(T_clk / 2) rst = 0;
end
endtask
endmodule
| 6.802858 |
module SNG (
seed,
data,
enable,
reset,
clk
);
input [7:0] seed;
output [7:0] data;
input enable;
input reset;
input clk;
reg [8:1] out_LFSR;
wire feedback;
assign feedback = out_LFSR[8] ^ out_LFSR[6] ^ out_LFSR[5] ^ out_LFSR[4];
always @(posedge clk or posedge reset) begin
if (reset) out_LFSR <= seed;
else if (enable) out_LFSR = {out_LFSR[7:1], feedback};
end
assign data = out_LFSR;
endmodule
| 6.647348 |
module sng_test;
wire [7:0] data;
reg [7:0] seed;
reg enable;
reg reset;
reg clk;
//SNG(seed,data,enable,reset,clk);
SNG U1 (
.data(data),
.seed(seed),
.enable(enable),
.reset(reset),
.clk(clk)
);
initial begin
clk = 0;
reset = 1;
enable = 0;
seed = 8'b0010_0001;
#20;
reset = 0;
enable = 1;
end
always #15 clk = ~clk;
endmodule
| 6.744349 |
module snif #(
parameter ADR_WIDTH = `ADR_WIDTH
) (
input wire clk_i,
input wire rst_i,
input wire [ADR_WIDTH-1:0] adr_i,
input wire we_i,
output wire detect_o
);
reg pulse_reg;
reg pulse_reg_next;
reg detect;
always @(posedge clk_i) begin : seq
if (rst_i) begin
pulse_reg <= 0;
end else begin
pulse_reg <= pulse_reg_next;
end
end
always @* begin : comb
pulse_reg_next = &{adr_i, we_i};
detect = pulse_reg && !pulse_reg_next;
end
assign detect_o = detect;
endmodule
| 7.185337 |
module SNI_RX (
arst_n,
fifo_afull,
fifo_din,
fifo_wren,
// Original FIFO Signal
fifo_EOD_in,
// SNI signal
RXC,
CRS,
RXD
);
// general interface
input wire arst_n; // async reset from user clock domain
// FIFO Interface signal
input wire fifo_afull; // fifo also_full
output wire [7:0] fifo_din;
output wire fifo_wren;
// Original FIFO signal
output wire fifo_EOD_in; // indicates End of Data. Useful to detect frame end.
// SNI (Serial Network Interface) signal
input wire RXC;
input wire CRS;
input wire RXD;
// state
reg [1:0] STATE;
localparam S_IDLE = 2'b00, S_PREAMBLE = 2'b01, S_BODY = 2'b10, S_END = 2'b11;
reg [7:0] seq; // 1Byte
reg [2:0] counter; // 0 -> 7 counter for make a Byte from bits
assign fifo_din = seq;
// store to fifo 1Byte cycle
assign fifo_wren = (counter == 3'h7);
// assign fifo_wren = 1'b1;
assign fifo_EOD_in = ~CRS & (STATE == S_BODY);
always @(posedge RXC or negedge arst_n) begin
if (arst_n == 1'b0) begin
STATE <= S_IDLE;
seq <= 8'b0;
counter <= 3'b0;
end else begin
seq <= {seq[6:0], RXD};
if (STATE == S_IDLE) begin
if (CRS & ~fifo_afull) STATE <= S_PREAMBLE;
end else if (STATE == S_PREAMBLE) begin
if (~CRS) STATE <= S_IDLE;
else if (seq == 8'b1010_1011) // detect SFD
STATE <= S_BODY;
end else if (STATE == S_BODY) begin
counter <= counter + 3'b1;
if (~CRS) begin
STATE <= S_END;
end
// store to fifo 1Byte cycle
end else if (STATE == S_END) begin
counter <= 3'b0;
STATE <= S_IDLE;
end // undefined state, go to S_END
else begin
STATE <= S_END;
end
end
end
endmodule
| 7.496633 |
module SNN #(
parameter c_TOTAL_COLS = 800,
parameter c_TOTAL_ROWS = 525,
parameter c_ACTIVE_COLS = 640,
parameter c_ACTIVE_ROWS = 480
) (
input i_Clk,
input i_HSync,
input i_VSync,
// Button to determine whether Spike is being received
input i_Action_Potential,
// Output Video
output reg o_HSync,
output reg o_VSync,
output [3:0] o_Red_Video,
output [3:0] o_Grn_Video,
output [3:0] o_Blu_Video
);
// Local Constants to Determine Game Play
parameter c_GAME_WIDTH = 640;
parameter c_GAME_HEIGHT = 480;
parameter c_PULSE_BASE = 20;
// State machine enumerations
parameter IDLE = 1'b0;
parameter RUNNING = 1'b1;
reg r_SM_Main = RUNNING;
wire w_HSync, w_VSync;
wire [9:0] w_Col_Count, w_Row_Count;
wire w_Draw_All;
wire w_Draw_Ball;
wire [9:0] w_Ball_X, w_Ball_Y;
// Divided version of the Row/Col Counters
// Allows us to make the board 80x60
wire [9:0] w_Col_Count_Div, w_Row_Count_Div;
Sync_To_Count #(
.TOTAL_COLS(c_TOTAL_COLS),
.TOTAL_ROWS(c_TOTAL_ROWS)
) Sync_To_Count_Inst (
.i_Clk(i_Clk),
.i_HSync(i_HSync),
.i_VSync(i_VSync),
.o_HSync(w_HSync),
.o_VSync(w_VSync),
.o_Col_Count(w_Col_Count),
.o_Row_Count(w_Row_Count)
);
// Register syncs to align with output data
always @(posedge i_Clk) begin
o_HSync <= w_HSync;
o_VSync <= w_VSync;
end
assign w_Col_Count_Div = w_Col_Count;
assign w_Row_Count_Div = w_Row_Count;
Neuron #(
.c_GAME_WIDTH (c_GAME_WIDTH),
.c_GAME_HEIGHT(c_GAME_HEIGHT)
) Neuron_Inst (
.i_Clk(i_Clk),
.i_Action_Potential(i_Action_Potential),
.i_Col_Count_Div(w_Col_Count_Div),
.i_Row_Count_Div(w_Row_Count_Div),
.o_Membrane_Potential(w_Draw_Ball),
.o_Ball_X(w_Ball_X),
.o_Ball_Y(w_Ball_Y)
);
assign w_Game_Active = (r_SM_Main == RUNNING) ? 1'b1 : 1'b0;
assign w_Draw_All = w_Draw_Ball;
assign o_Red_Video = w_Draw_All ? 4'b1111 : 4'b0000;
assign o_Grn_Video = w_Draw_All ? 4'b1111 : 4'b0000;
assign o_Blu_Video = w_Draw_All ? 4'b1111 : 4'b0000;
endmodule
| 9.026486 |
module snn_network #(
parameter NUM_IN = 16,
parameter NUM_HIDDEN = 64,
parameter NUM_OUT = 8
) (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V power
input vssd1, // User area 1 digital ground
`endif
input wire clk,
input wire reset,
input wire [ 15 : 0] in_signal,
output wire [NUM_OUT-1 : 0] out_spk,
output wire [NUM_OUT-1 : 0] io_oeb
);
assign io_oeb = {(NUM_OUT - 1) {1'b0}};
wire [NUM_IN -1:0] inp_spk;
wire [NUM_HIDDEN -1:0] hid_spk;
genvar i;
generate
for (i = 0; i < NUM_IN; i = i + 1) begin
input_neuron #(
.ori_thr(64),
.decay_shift_cur(2),
.decay_shift_mem(2),
.decay_shift_thr(2),
.adp_thr(2)
) in0 (
.clk (clk),
.reset(reset),
.syn (in_signal[i]),
.spk (inp_spk[i])
);
end
for (i = NUM_IN; i < NUM_IN + NUM_HIDDEN; i = i + 1) begin
hidden_neuron #(
.NUM_FAN_IN(NUM_IN),
.NUM_REC_IN(NUM_HIDDEN),
.ori_thr(64),
.decay_shift_cur(2),
.decay_shift_mem(2),
.decay_shift_thr(2),
.adp_thr(2)
) hid0 (
.clk(clk),
.reset(reset),
.fan_in(inp_spk),
.rec_spk(hid_spk),
.spk(hid_spk[i-NUM_IN])
);
end
for (i = NUM_IN + NUM_HIDDEN; i < NUM_IN + NUM_HIDDEN + NUM_OUT; i = i + 1) begin
output_neuron #(
.NUM_FAN_IN(NUM_HIDDEN),
.ori_thr(64),
.decay_shift_cur(2),
.decay_shift_mem(2),
.decay_shift_thr(2),
.adp_thr(2)
) out0 (
.clk(clk),
.reset(reset),
.fan_in(hid_spk),
.spk(out_spk[i-NUM_IN-NUM_HIDDEN])
);
end
endgenerate
// output_neuron #(S
// .NUM_FAN_IN(NUM_HIDDEN),
// .ori_thr(32),
// .decay_shift_cur(2),
// .decay_shift_mem(2),
// .decay_shift_thr(2),
// .adp_thr(2))
// out0 (.clk(clk), .reset(reset), .fan_in(hid_spk), .spk(out_spk[0]));
// output_neuron #(
// .NUM_FAN_IN(NUM_HIDDEN),
// .ori_thr(32),
// .decay_shift_cur(2),
// .decay_shift_mem(2),
// .decay_shift_thr(2),
// .adp_thr(2))
// out1 (.clk(clk), .reset(reset), .fan_in(hid_spk), .spk(out_spk[1]));
endmodule
| 7.114656 |
module snn_tb;
initial begin
$dumpfile("snn.vcd");
$dumpvars(0, snn_tb);
#1;
end
reg clk;
reg RSTB;
reg power1, power2;
reg power3, power4;
wire gpio;
wire [37:0] mprj_io;
// IO Pads
// .state1(io_out[25:18]),
// .io_oeb(io_oeb[25:16])
///// convenience signals that match what the cocotb test modules are looking for
// change to suit your project. Here's how we can make some nicer named signals for inputs & outputs
wire [1:0] spike_out;
wire [7:0] state1;
wire [7:0] in1;
wire reset;
assign spike_out = mprj_io[17:16];
assign state1 = mprj_io[25:18];
assign mprj_io[15:8] = in1;
assign mprj_io[26] = reset;
//////
//////
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire VDD3V3 = power1;
wire VDD1V8 = power2;
wire USER_VDD3V3 = power3;
wire USER_VDD1V8 = power4;
wire VSS = 1'b0;
caravel uut (
.vddio (VDD3V3),
.vddio_2 (VDD3V3),
.vssio (VSS),
.vssio_2 (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
.vdda1 (VDD3V3),
.vdda1_2 (VDD3V3),
.vdda2 (VDD3V3),
.vssa1 (VSS),
.vssa1_2 (VSS),
.vssa2 (VSS),
.vccd1 (VDD1V8),
.vccd2 (VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
.clock (clk), // ?
.gpio (gpio),
.mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
.resetb (RSTB)
);
spiflash #(
.FILENAME("snn.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(), // not used
.io3() // not used
);
endmodule
| 6.51341 |
module SNN_top (
input i_Clk,
// Push Buttons
input i_Switch_1,
// VGA
output o_VGA_HSync,
output o_VGA_VSync,
output o_VGA_Red_0,
output o_VGA_Red_1,
output o_VGA_Red_2,
output o_VGA_Grn_0,
output o_VGA_Grn_1,
output o_VGA_Grn_2,
output o_VGA_Blu_0,
output o_VGA_Blu_1,
output o_VGA_Blu_2
);
// VGA Constants to Set Frame Size
parameter c_VIDEO_WIDTH = 3;
parameter c_TOTAL_COLS = 800;
parameter c_TOTAL_ROWS = 525;
parameter c_ACTIVE_COLS = 640;
parameter c_ACTIVE_ROWS = 480;
// Common VGA Signals
wire [c_VIDEO_WIDTH-1:0] w_Red_Video_Membrane, w_Red_Video_Porch;
wire [c_VIDEO_WIDTH-1:0] w_Grn_Video_Membrane, w_Grn_Video_Porch;
wire [c_VIDEO_WIDTH-1:0] w_Blu_Video_Membrane, w_Blu_Video_Porch;
wire w_Switch_1;
VGA_Sync_Pulses #(
.TOTAL_COLS (c_TOTAL_COLS),
.TOTAL_ROWS (c_TOTAL_ROWS),
.ACTIVE_COLS(c_ACTIVE_COLS),
.ACTIVE_ROWS(c_ACTIVE_ROWS)
) VGA_Sync_Pulses_Inst (
.i_Clk(i_Clk),
.o_HSync(w_HSync_VGA),
.o_VSync(w_VSync_VGA),
.o_Col_Count(),
.o_Row_Count()
);
Debounce_Switch Switch_1 (
.i_Clk(i_Clk),
.i_Switch(i_Switch_1),
.o_Switch(w_Switch_1)
);
SNN #(
.c_TOTAL_COLS (c_TOTAL_COLS),
.c_TOTAL_ROWS (c_TOTAL_ROWS),
.c_ACTIVE_COLS(c_ACTIVE_COLS),
.c_ACTIVE_ROWS(c_ACTIVE_ROWS)
) SNN_Inst (
.i_Clk(i_Clk),
.i_HSync(w_HSync_VGA),
.i_VSync(w_VSync_VGA),
.i_Action_Potential(w_Switch_1),
.o_HSync(w_HSync_SNN),
.o_VSync(w_VSync_SNN),
.o_Red_Video(w_Red_Video_Membrane),
.o_Grn_Video(w_Grn_Video_Membrane),
.o_Blu_Video(w_Blu_Video_Membrane)
);
VGA_Sync_Porch #(
.VIDEO_WIDTH(c_VIDEO_WIDTH),
.TOTAL_COLS (c_TOTAL_COLS),
.TOTAL_ROWS (c_TOTAL_ROWS),
.ACTIVE_COLS(c_ACTIVE_COLS),
.ACTIVE_ROWS(c_ACTIVE_ROWS)
) VGA_Sync_Porch_Inst (
.i_Clk(i_Clk),
.i_HSync(w_HSync_SNN),
.i_VSync(w_VSync_SNN),
.i_Red_Video(w_Red_Video_Membrane),
.i_Grn_Video(w_Grn_Video_Membrane),
.i_Blu_Video(w_Blu_Video_Membrane),
.o_HSync(o_VGA_HSync),
.o_VSync(o_VGA_VSync),
.o_Red_Video(w_Red_Video_Porch),
.o_Grn_Video(w_Grn_Video_Porch),
.o_Blu_Video(w_Blu_Video_Porch)
);
assign o_VGA_Red_0 = w_Red_Video_Porch[0];
assign o_VGA_Red_1 = w_Red_Video_Porch[1];
assign o_VGA_Red_2 = w_Red_Video_Porch[2];
assign o_VGA_Grn_0 = w_Grn_Video_Porch[0];
assign o_VGA_Grn_1 = w_Grn_Video_Porch[1];
assign o_VGA_Grn_2 = w_Grn_Video_Porch[2];
assign o_VGA_Blu_0 = w_Blu_Video_Porch[0];
assign o_VGA_Blu_1 = w_Blu_Video_Porch[1];
assign o_VGA_Blu_2 = w_Blu_Video_Porch[2];
endmodule
| 7.426416 |
module snoop (
input eclk,
input rstb,
input [3:0] stage,
input [3:0] pass_cnt,
input pass_cnt0, //Set during blake2b & collision XOR writing
input bucket_cnt_rst,
input wvalid,
input [`MEM_DATA_WIDTH-1:0] wdata,
output [`MEM_ADDR_WIDTH-1:0] bucket0_base,
output [`MEM_ADDR_WIDTH-1:0] bucket1_base,
output [`MEM_ADDR_WIDTH-1:0] bucket2_base,
output [`MEM_ADDR_WIDTH-1:0] bucket3_base,
output [`MEM_ADDR_WIDTH-1:0] bucket4_base,
output [`MEM_ADDR_WIDTH-1:0] bucket5_base,
output [`MEM_ADDR_WIDTH-1:0] bucket6_base,
output [`MEM_ADDR_WIDTH-1:0] bucket7_base,
output [`MEM_ADDR_WIDTH-1:0] bucket8_base,
output [`MEM_ADDR_WIDTH-1:0] bucket9_base,
output [`MEM_ADDR_WIDTH-1:0] bucketA_base,
output [`MEM_ADDR_WIDTH-1:0] bucketB_base,
output [`MEM_ADDR_WIDTH-1:0] bucketC_base,
output [`MEM_ADDR_WIDTH-1:0] bucketD_base,
output [`MEM_ADDR_WIDTH-1:0] bucketE_base,
output [`MEM_ADDR_WIDTH-1:0] bucketF_base
);
parameter RADIX_BITS = 4; // Comparator size
integer i;
reg wvalidq;
wire [3:0] next_pass_cnt;
reg [`MEM_ADDR_WIDTH-1:0] bucket[15:0];
wire [`MEM_ADDR_WIDTH-1:0] bucket0_base;
wire [`MEM_ADDR_WIDTH-1:0] bucket1_base;
wire [`MEM_ADDR_WIDTH-1:0] bucket2_base;
wire [`MEM_ADDR_WIDTH-1:0] bucket3_base;
wire [`MEM_ADDR_WIDTH-1:0] bucket4_base;
wire [`MEM_ADDR_WIDTH-1:0] bucket5_base;
wire [`MEM_ADDR_WIDTH-1:0] bucket6_base;
wire [`MEM_ADDR_WIDTH-1:0] bucket7_base;
wire [`MEM_ADDR_WIDTH-1:0] bucket8_base;
wire [`MEM_ADDR_WIDTH-1:0] bucket9_base;
wire [`MEM_ADDR_WIDTH-1:0] bucketA_base;
wire [`MEM_ADDR_WIDTH-1:0] bucketB_base;
wire [`MEM_ADDR_WIDTH-1:0] bucketC_base;
wire [`MEM_ADDR_WIDTH-1:0] bucketD_base;
wire [`MEM_ADDR_WIDTH-1:0] bucketE_base;
wire [`MEM_ADDR_WIDTH-1:0] bucketF_base;
wire [`EQUIHASH_c-1:0] data_select;
reg [RADIX_BITS-1:0] bucket_select;
assign next_pass_cnt = (pass_cnt0) ? 4'h0 : pass_cnt + 4'h1;
assign data_select = wdata[`EQUIHASH_c-1:0];
// Bucket Selection
always @(posedge eclk) begin
if (!rstb) begin
bucket_select <= 4'h0;
end
begin
case (next_pass_cnt)
4'h0: bucket_select <= data_select[RADIX_BITS*1-1 : RADIX_BITS*0];
4'h1: bucket_select <= data_select[RADIX_BITS*2-1 : RADIX_BITS*1];
4'h2: bucket_select <= data_select[RADIX_BITS*3-1 : RADIX_BITS*2];
4'h3: bucket_select <= data_select[RADIX_BITS*4-1 : RADIX_BITS*3];
4'h4: bucket_select <= data_select[RADIX_BITS*5-1 : RADIX_BITS*4];
4'h5: bucket_select <= {3'b000, data_select[20]};
default: bucket_select <= data_select[RADIX_BITS*2-1 : RADIX_BITS*1];
endcase
end
end
always @(posedge eclk) begin
if (!rstb) begin
wvalidq <= 1'b0;
for (i = 0; i < 16; i = i + 1) bucket[i] <= `MEM_ADDR_WIDTH'h0;
end else begin
wvalidq <= wvalid;
if (bucket_cnt_rst) begin
for (i = 0; i < 16; i = i + 1) bucket[i] <= `MEM_ADDR_WIDTH'h0;
end else if (wvalidq) begin
// Buckets 0 to 14
for (i = 0; i < 16; i = i + 1) begin
if (i > bucket_select) bucket[i] <= bucket[i] + 32'h1;
else bucket[i] <= bucket[i];
end
end
end
end
//Output buckets
assign bucket0_base = bucket[0];
assign bucket1_base = bucket[1];
assign bucket2_base = bucket[2];
assign bucket3_base = bucket[3];
assign bucket4_base = bucket[4];
assign bucket5_base = bucket[5];
assign bucket6_base = bucket[6];
assign bucket7_base = bucket[7];
assign bucket8_base = bucket[8];
assign bucket9_base = bucket[9];
assign bucketA_base = bucket[10];
assign bucketB_base = bucket[11];
assign bucketC_base = bucket[12];
assign bucketD_base = bucket[13];
assign bucketE_base = bucket[14];
assign bucketF_base = bucket[15];
endmodule
| 6.93785 |
module SnoopP (
input clk,
input reset,
input [25:0] pc,
input [31:0] instr_in,
input stall,
// TESTER PORTS ONLY
input init_start,
output init_done,
input retrieve_start,
output retrieve_done,
// Avalon Profile Master ports
output avm_profileMaster_read,
output avm_profileMaster_write,
output [31:0] avm_profileMaster_address,
output [31:0] avm_profileMaster_writedata,
output [3:0] avm_profileMaster_byteenable,
input [31:0] avm_profileMaster_readdata,
input avm_profileMaster_waitrequest,
input avm_profileMaster_readdatavalid,
output [`CW-1:0] rProfData,
output [`N2-1:0] rProfIndex
);
wire [`N2-1:0] addr_a;
wire [`N2-1:0] count_a;
wire [25:0] addr_lo_data;
wire [25:0] addr_hi_data;
wire [`CW-1:0] count_data;
wire prof_init_start;
wire prof_init_done;
assign rProfData = count_data;
assign rProfIndex = count_a;
// mux avalon signals
wire init_avm_profileMaster_write;
wire [31:0] init_avm_profileMaster_address;
wire [31:0] init_avm_profileMaster_writedata;
wire retrieve_avm_profileMaster_write;
wire [31:0] retrieve_avm_profileMaster_address;
wire [31:0] retrieve_avm_profileMaster_writedata;
assign avm_profileMaster_write = (init_start & !init_done) ? init_avm_profileMaster_write : retrieve_avm_profileMaster_write;
assign avm_profileMaster_address = (init_start & !init_done) ? init_avm_profileMaster_address : retrieve_avm_profileMaster_address;
assign avm_profileMaster_writedata = (init_start & !init_done) ? init_avm_profileMaster_writedata : retrieve_avm_profileMaster_writedata;
Profiler profile (
.clk(clk),
.reset(reset),
.pc(pc),
.stall(stall),
.addr_a (addr_a),
.count_a(count_a),
.addr_lo_data(addr_lo_data),
.addr_hi_data(addr_hi_data),
.count_data (count_data),
.global_init(init_start | retrieve_start),
.init_start (prof_init_start),
.init_done (prof_init_done)
);
sInitializer init (
.clk(clk),
.reset(reset),
.pc(pc),
.init_start(init_start),
.init_done (init_done),
.addr_a(addr_a),
.addr_lo_data(addr_lo_data),
.addr_hi_data(addr_hi_data),
.prof_init_start(prof_init_start),
.prof_init_done (prof_init_done),
//Avalon Bus side signals
.avm_profileMaster_read(avm_profileMaster_read),
.avm_profileMaster_write(init_avm_profileMaster_write),
.avm_profileMaster_address(init_avm_profileMaster_address),
.avm_profileMaster_writedata(init_avm_profileMaster_writedata),
.avm_profileMaster_waitrequest(avm_profileMaster_waitrequest),
.avm_profileMaster_readdata(avm_profileMaster_readdata),
.avm_profileMaster_readdatavalid(avm_profileMaster_readdatavalid)
);
sRetriever retrieve (
.clk(clk),
.reset(reset),
.pc(pc),
.retrieve_start(retrieve_start),
.retrieve_done (retrieve_done),
.count_a(count_a),
.count_data(count_data),
//Avalon Bus side signals
.avm_profileMaster_write(retrieve_avm_profileMaster_write),
.avm_profileMaster_address(retrieve_avm_profileMaster_address),
.avm_profileMaster_writedata(retrieve_avm_profileMaster_writedata),
.avm_profileMaster_waitrequest(avm_profileMaster_waitrequest)
);
endmodule
| 6.93175 |
module sInitializer ( // for sdram
input clk,
input reset,
input [25:0] pc,
input init_start,
output reg init_done,
output reg [`N2-1:0] addr_a,
output reg [25:0] addr_lo_data,
output reg [25:0] addr_hi_data,
output reg prof_init_start,
input prof_init_done,
//Avalon Bus side signals
output reg avm_profileMaster_read,
output reg avm_profileMaster_write,
output reg [31:0] avm_profileMaster_address,
output reg [31:0] avm_profileMaster_writedata,
input avm_profileMaster_waitrequest,
input [31:0] avm_profileMaster_readdata,
input avm_profileMaster_readdatavalid
);
reg [2:0] state;
reg [2:0] next_state;
reg [25:0] sdram_addr;
reg [`N2+1:0] read_count;
wire [`N2-1:0] reg_addr = read_count[`N2:1]; // use to divide by 2 since lo and hi reg's alternate
// Read each value from counter storage's RAM, write to SDRAM
always @(posedge (clk)) begin
if (reset) begin
state <= 3'b000;
avm_profileMaster_write <= 1'b0;
avm_profileMaster_read <= 1'b0;
avm_profileMaster_writedata <= 'b0;
init_done <= 1'b0;
prof_init_start <= 1'b0;
end else begin
if (init_start & !init_done) begin
// State 0: Reset profiler
if (state == 3'b000) begin
// get ready to read ranges from SDRAM
avm_profileMaster_address <= `PROF_ADDR;
sdram_addr <= `PROF_ADDR;
avm_profileMaster_read <= 1'b1;
prof_init_start <= 1'b1;
read_count <= 'b0;
state <= 3'b001;
end else if (state == 3'b001) begin
// Handshaking with profiler module
if (prof_init_start & prof_init_done) prof_init_start <= 1'b0;
//If wait request is low we can give another address to read from
if (!avm_profileMaster_waitrequest) begin
//If we've given address for all the blocks we want, stop reading
if (avm_profileMaster_address == `PROF_ADDR + (2 * 4 * `N))
avm_profileMaster_read <= 1'b0;
else avm_profileMaster_address <= avm_profileMaster_address + 4'h4;
end
//If we have valid data
if (avm_profileMaster_readdatavalid) begin
// if we've read all addr_lo/addr_hi, tell processor to unstall
if (read_count == (2 * `N)) begin
avm_profileMaster_read <= 1'b0;
avm_profileMaster_address <= `STACK_ADDR;
avm_profileMaster_writedata <= 32'hDEADBEEF;
state <= 3'b011;
end else begin
read_count <= read_count + 1'b1;
sdram_addr <= sdram_addr + 4'h4; // this variable is only used for debug output
// store data
if (read_count[0]) begin
//$display("addr_hi[%d] = %h at address %h", reg_addr, avm_profileMaster_readdata, sdram_addr);
addr_hi_data <= avm_profileMaster_readdata; // store to addr_lo registers
addr_a <= reg_addr;
prof_init_start <= 1'b1;
end else begin
//$display("addr_lo[%d] = %h at address %h", reg_addr, avm_profileMaster_readdata, sdram_addr);
addr_lo_data <= avm_profileMaster_readdata; // store to addr_lo registers
end
end
end
// State 3: Tell processor to continue
end else if (state == 3'b011) begin
if (!avm_profileMaster_waitrequest) begin
avm_profileMaster_write <= 1'b1;
state <= 3'b100;
end
// State 4: Wait until write finished
end else if (state == 3'b100) begin
if (!avm_profileMaster_waitrequest) begin
avm_profileMaster_write <= 1'b0;
init_done <= 1'b1;
state <= 3'b000;
end
end
end else if (!init_start & init_done) begin
init_done <= 1'b0; // reset init_done so handshaking can occur again
end
end
end
endmodule
| 6.713009 |
module sRetriever (
input clk,
input reset,
input [25:0] pc,
input retrieve_start,
output reg retrieve_done,
output reg [`N2-1:0] count_a,
input [`CW-1:0] count_data,
//Avalon Bus side signals
output reg avm_profileMaster_write,
output reg [31:0]avm_profileMaster_address,
output reg [31:0]avm_profileMaster_writedata,
input avm_profileMaster_waitrequest
);
reg [2:0] state;
reg [`N2:0] prof_count; // used b/c prof_index can only go up to `N-1, so is always < `N (circular)
// Read each value from counter storage's RAM, write to SDRAM
always @(posedge(clk)) begin
if (reset) begin
retrieve_done <= 1'b0;
state <= 3'b000;
count_a <= 'b0;
avm_profileMaster_write <= 1'b0;
end else begin
if (retrieve_start & !retrieve_done) begin
// State 0: Setup muxes
if (state == 3'b000) begin
count_a <= 'h0;
prof_count <= 'b0;
state <= 3'b001;
end
// State 1: Prepare/write data to sdram
else if (state == 3'b001) begin
if(!avm_profileMaster_waitrequest) begin
if (prof_count < `N) begin
`ifdef CW64
avm_profileMaster_address <= `PROF_ADDR + { count_a, 2'b000 };
`else
avm_profileMaster_address <= `PROF_ADDR + { count_a, 2'b00 };
`endif
avm_profileMaster_write <= 1'b1;
avm_profileMaster_writedata <= count_data;
count_a <= count_a + 1'b1;
prof_count <= prof_count + 1'b1;
$display("prof_data = %4d @ %4d", count_data, count_a);
`ifdef CW64
$display("CW > 32...");
state <= 3'b011;
`endif
end else begin
avm_profileMaster_address <= `STACK_ADDR;
avm_profileMaster_write <= 1'b1;
avm_profileMaster_writedata <= 32'hCADFEED;
state <= 3'b010;
end
end
end
// State 2: Wait until unstall write is finished
else if (state == 3'b010) begin
if(!avm_profileMaster_waitrequest) begin
avm_profileMaster_write <= 0;
state <= 3'b000;
retrieve_done <= 1'b1;
$display("Done");
#1000000 $finish; // uncomment this to have results in modelsim waveform right at end
end
end
// State 3: Write out top 32 bits for a 64-bit counter
`ifdef CW64
else if (`CW>32 & state == 3'b011) begin
if(!avm_profileMaster_waitrequest) begin
avm_profileMaster_address <= `PROF_ADDR + { count_a, 3'b100 };
avm_profileMaster_write <= 1'b1;
avm_profileMaster_writedata <= count_data[63:32];
state <= 3'b001;
//$display("prof_data = %4d @ %4d", prof_data, prof_index);
end
end
`endif
end else if (!retrieve_start & retrieve_done) begin
retrieve_done <= 1'b0; // reset retrieve_done so handshaking can occur again
end
end
end
endmodule
| 8.172321 |
module snoop_adapter (
clk,
reset,
kernel_clk,
kernel_reset,
address,
read,
readdata,
readdatavalid,
write,
writedata,
burstcount,
byteenable,
waitrequest,
burstbegin,
snoop_data,
snoop_valid,
snoop_ready,
export_address,
export_read,
export_readdata,
export_readdatavalid,
export_write,
export_writedata,
export_burstcount,
export_burstbegin,
export_byteenable,
export_waitrequest
);
parameter NUM_BYTES = 4;
parameter BYTE_ADDRESS_WIDTH = 32;
parameter WORD_ADDRESS_WIDTH = 32;
parameter BURSTCOUNT_WIDTH = 1;
localparam DATA_WIDTH = NUM_BYTES * 8;
localparam ADDRESS_SHIFT = BYTE_ADDRESS_WIDTH - WORD_ADDRESS_WIDTH;
localparam DEVICE_BLOCKRAM_MIN_DEPTH = 256; //Stratix IV M9Ks
localparam FIFO_SIZE = DEVICE_BLOCKRAM_MIN_DEPTH;
localparam LOG2_FIFO_SIZE = $clog2(FIFO_SIZE);
input clk;
input reset;
input kernel_clk;
input kernel_reset;
input [WORD_ADDRESS_WIDTH-1:0] address;
input read;
output [DATA_WIDTH-1:0] readdata;
output readdatavalid;
input write;
input [DATA_WIDTH-1:0] writedata;
input [BURSTCOUNT_WIDTH-1:0] burstcount;
input burstbegin;
input [NUM_BYTES-1:0] byteenable;
output waitrequest;
output [1+WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0] snoop_data;
output snoop_valid;
input snoop_ready;
output [BYTE_ADDRESS_WIDTH-1:0] export_address;
output export_read;
input [DATA_WIDTH-1:0] export_readdata;
input export_readdatavalid;
output export_write;
output [DATA_WIDTH-1:0] export_writedata;
output [BURSTCOUNT_WIDTH-1:0] export_burstcount;
output export_burstbegin;
output [NUM_BYTES-1:0] export_byteenable;
input export_waitrequest;
reg snoop_overflow;
// Register snoop data first
reg [WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0] snoop_data_r; //word-address
reg snoop_valid_r;
wire snoop_fifo_empty;
wire overflow;
wire [ LOG2_FIFO_SIZE-1 : 0] rdusedw;
always @(posedge clk) begin
snoop_data_r <= {address, export_burstcount};
snoop_valid_r <= export_write && !export_waitrequest;
end
// 1) Fifo to store snooped accesses from host
dcfifo dcfifo_component (
.wrclk(clk),
.data(snoop_data_r),
.wrreq(snoop_valid_r),
.rdclk(kernel_clk),
.rdreq(snoop_valid & snoop_ready),
.q(snoop_data[WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0]),
.rdempty(snoop_fifo_empty),
.rdfull(overflow),
.aclr(1'b0),
.rdusedw(rdusedw),
.wrempty(),
.wrfull(),
.wrusedw()
);
defparam dcfifo_component.intended_device_family = "Stratix IV", dcfifo_component.lpm_numwords =
FIFO_SIZE, dcfifo_component.lpm_showahead = "ON", dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = WORD_ADDRESS_WIDTH + BURSTCOUNT_WIDTH,
dcfifo_component.lpm_widthu = LOG2_FIFO_SIZE, dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4, dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON", dcfifo_component.wrsync_delaypipe = 4;
assign snoop_valid = ~snoop_fifo_empty;
always @(posedge kernel_clk) snoop_overflow = (rdusedw >= (FIFO_SIZE - 12));
// Overflow piggy backed onto MSB of stream. Since overflow guarantees
// there is something to be read out, we can be sure that this will reach
// the cache.
assign snoop_data[WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH] = snoop_overflow;
assign export_address = address << ADDRESS_SHIFT;
assign export_read = read;
assign readdata = export_readdata;
assign readdatavalid = export_readdatavalid;
assign export_write = write;
assign export_writedata = writedata;
assign export_burstcount = burstcount;
assign export_burstbegin = burstbegin;
assign export_byteenable = byteenable;
assign waitrequest = export_waitrequest;
endmodule
| 7.169538 |
module snowbro2_clock (
input CLK, //48mhz
input CLK96,
input CLK24,
input CLK6,
output CEN675,
output CEN675B,
output CEN2p7,
output CEN2p7B,
output CEN3p375,
output CEN3p375B,
output CEN1p6875,
output CEN1p6875B,
output CEN1350,
output CEN1350B
);
// 13.50mhz / 6.75mhz for GP9001; 3.375 for YM2151 (SNOWBRO2)
// 94.5/7=13.5 // 94.5/14=6.75 // 94.5/28=3.375 // 94.5/56=1.6875
jtframe_frac_cen #(
.W(4)
) u_frac_cen_1350 (
.clk(CLK96),
.n(1),
.m(7),
.cen({CEN1p6875, CEN3p375, CEN675, CEN1350}),
.cenb()
);
// 4mhz for OKI (SNOWBRO2)
// 94.5*(1/35) == 2.7
jtframe_frac_cen u_frac_cen_27 (
.clk(CLK96),
.n(1),
.m(35),
.cen(CEN2p7),
.cenb(CEN2p7B)
);
endmodule
| 7.07318 |
module. This is one of the three queues used in
pingpangpungcontroller.v (refer to that file for details)
*/
module snqueue (
input wire clk,
input wire [1:0] token_from_cpu,
input wire en_from_cpu,
input wire [1:0] token_from_fwd,
input wire en_from_fwd,
input wire deq,
output wire [1:0] head
);
reg [1:0] first = 2'b01, second = 2'b10, third = 2'b11;
wire [1:0] first_n, second_n, third_n;
wire [1:0] incoming;
assign incoming = (en_from_cpu) ? token_from_cpu : ((en_from_fwd) ? token_from_fwd : 0);
assign first_n = second;
assign second_n = (en_from_cpu && en_from_fwd) ? token_from_cpu : third;
assign third_n = (en_from_cpu && en_from_fwd) ? token_from_fwd : incoming;
always @(posedge clk) begin
//This feels like it can be optimized somehow...
if (deq || (first == 0)) begin
first <= first_n;
end
if (deq || (first == 0) || (second == 0)) begin
second <= second_n;
end
if (deq || (first == 0) || (second == 0) || (third == 0)) begin
third <= third_n;
end
end
//Output
assign head = (first == 0) ? ((second == 0) ? third : second) : first;
endmodule
| 6.833535 |
module snurisc (
input reset,
input clk
);
wire [31:0] jump_reg_target;
wire [31:0] brjmp_target;
wire [31:0] data;
wire [31:0] wbdata;
wire [1:0] pc_sel;
wire im_status;
wire dm_status;
wire [11:0] imm12;
wire op1_sel;
wire op2_sel;
wire [3:0] alu_ctrl;
wire br_type;
wire dmem_fcn;
wire dmem_vaild;
wire [1:0] wb_sel;
wire rf_wen;
wire [31:0] inst_pc;
wire [31:0] add_pc;
wire [31:0] mux1out;
wire [31:0] mux2out;
wire [31:0] rs2_data;
wire [31:0] alu_out;
wire [31:0] rdata;
control ctrl (
.clk(clk),
.reset(reset),
.data(data),
.pc(inst_pc),
.jump_reg_target(jump_reg_target),
.status(im_status),
.alu_out(alu_out),
.pc_sel(pc_sel),
.imm12(imm12),
.op1_sel(op1_sel),
.op2_sel(op2_sel),
.alu_ctrl(alu_ctrl),
.br_type(br_type),
.rf_wen(rf_wen),
.dmem_vaild(dmem_vaild),
.dmem_fcn(dmem_fcn),
.wb_sel(wb_sel)
);
pcgen pc_gen (
.clk(clk),
.reset(reset),
.pc_sel(pc_sel),
.jump_reg_target(jump_reg_target),
.brjmp_target(brjmp_target),
.npc(inst_pc),
.add_pc(add_pc)
);
fetch inst_fetch (
.clk(clk),
.reset(reset),
.pc(inst_pc),
.data(data),
.status(im_status)
);
decode inst_decoder (
.clk(clk),
.reset(reset),
.pc(inst_pc),
.data(data),
.wbdata(wbdata),
.rf_wen(rf_wen),
.op1_sel(op1_sel),
.op2_sel(op2_sel),
.imm12(imm12),
.mux1out(mux1out),
.mux2out(mux2out),
.rs2_data(rs2_data)
);
execute inst_execute (
.clk(clk),
.reset(reset),
.pc(inst_pc),
.alu_ctrl(alu_ctrl),
.br_type(br_type),
.mux1out(mux1out),
.mux2out(mux2out),
.rs2_data(rs2_data),
.brjmp_target(brjmp_target),
.alu_out(alu_out)
);
dmem data_memory (
.reset(reset),
.clk(clk),
.rnw(dmem_fcn),
.enable(dmem_vaild),
.status(dm_status),
.addr(alu_out),
.wdata(rs2_data),
.rdata(rdata)
);
assign jump_reg_target = alu_out;
assign wbdata = (wb_sel == 2'b10) ? add_pc : (wb_sel == 2'b01) ? alu_out : rdata;
endmodule
| 6.514048 |
module SnxnLv4Inst4 (
input io_a,
input io_b,
output io_z
);
wire t0 = io_a + io_b; // @[Snxn100k.scala 72281:20]
wire inv0 = ~t0; // @[Snxn100k.scala 72282:15]
wire x0 = t0 ^ inv0; // @[Snxn100k.scala 72283:18]
wire invx0 = ~x0; // @[Snxn100k.scala 72284:15]
wire t1 = x0 + invx0; // @[Snxn100k.scala 72285:18]
wire inv1 = ~t1; // @[Snxn100k.scala 72286:15]
wire x1 = t1 ^ inv1; // @[Snxn100k.scala 72287:18]
assign io_z = ~x1; // @[Snxn100k.scala 72288:15]
endmodule
| 6.93941 |
module SnxnLv4Inst56 (
input io_a,
input io_b,
output io_z
);
wire t0 = io_a + io_b; // @[Snxn100k.scala 63383:20]
wire inv0 = ~t0; // @[Snxn100k.scala 63384:15]
wire x0 = t0 ^ inv0; // @[Snxn100k.scala 63385:18]
wire invx0 = ~x0; // @[Snxn100k.scala 63386:15]
wire t1 = x0 + invx0; // @[Snxn100k.scala 63387:18]
wire inv1 = ~t1; // @[Snxn100k.scala 63388:15]
wire x1 = t1 ^ inv1; // @[Snxn100k.scala 63389:18]
wire invx1 = ~x1; // @[Snxn100k.scala 63390:15]
wire t2 = x1 + invx1; // @[Snxn100k.scala 63391:18]
wire inv2 = ~t2; // @[Snxn100k.scala 63392:15]
wire x2 = t2 ^ inv2; // @[Snxn100k.scala 63393:18]
assign io_z = ~x2; // @[Snxn100k.scala 63394:15]
endmodule
| 6.811338 |
module SnxnLv4Inst63 (
input io_a,
input io_b,
output io_z
);
wire t0 = io_a + io_b; // @[Snxn100k.scala 67495:20]
wire inv0 = ~t0; // @[Snxn100k.scala 67496:15]
wire x0 = t0 ^ inv0; // @[Snxn100k.scala 67497:18]
wire invx0 = ~x0; // @[Snxn100k.scala 67498:15]
wire t1 = x0 + invx0; // @[Snxn100k.scala 67499:18]
wire inv1 = ~t1; // @[Snxn100k.scala 67500:15]
wire x1 = t1 ^ inv1; // @[Snxn100k.scala 67501:18]
wire invx1 = ~x1; // @[Snxn100k.scala 67502:15]
wire t2 = x1 + invx1; // @[Snxn100k.scala 67503:18]
wire inv2 = ~t2; // @[Snxn100k.scala 67504:15]
wire x2 = t2 ^ inv2; // @[Snxn100k.scala 67505:18]
wire invx2 = ~x2; // @[Snxn100k.scala 67506:15]
wire t3 = x2 + invx2; // @[Snxn100k.scala 67507:18]
wire inv3 = ~t3; // @[Snxn100k.scala 67508:15]
wire x3 = t3 ^ inv3; // @[Snxn100k.scala 67509:18]
assign io_z = ~x3; // @[Snxn100k.scala 67510:15]
endmodule
| 6.527747 |
module SnxnLv4Inst140 (
input io_a,
input io_b,
output io_z
);
wire t0 = io_a + io_b; // @[Snxn100k.scala 103215:20]
wire inv0 = ~t0; // @[Snxn100k.scala 103216:15]
wire x0 = t0 ^ inv0; // @[Snxn100k.scala 103217:18]
wire invx0 = ~x0; // @[Snxn100k.scala 103218:15]
wire t1 = x0 + invx0; // @[Snxn100k.scala 103219:18]
wire inv1 = ~t1; // @[Snxn100k.scala 103220:15]
wire x1 = t1 ^ inv1; // @[Snxn100k.scala 103221:18]
wire invx1 = ~x1; // @[Snxn100k.scala 103222:15]
wire t2 = x1 + invx1; // @[Snxn100k.scala 103223:18]
wire inv2 = ~t2; // @[Snxn100k.scala 103224:15]
wire x2 = t2 ^ inv2; // @[Snxn100k.scala 103225:18]
wire invx2 = ~x2; // @[Snxn100k.scala 103226:15]
wire t3 = x2 + invx2; // @[Snxn100k.scala 103227:18]
wire inv3 = ~t3; // @[Snxn100k.scala 103228:15]
wire x3 = t3 ^ inv3; // @[Snxn100k.scala 103229:18]
wire invx3 = ~x3; // @[Snxn100k.scala 103230:15]
wire t4 = x3 + invx3; // @[Snxn100k.scala 103231:18]
wire inv4 = ~t4; // @[Snxn100k.scala 103232:15]
wire x4 = t4 ^ inv4; // @[Snxn100k.scala 103233:18]
wire invx4 = ~x4; // @[Snxn100k.scala 103234:15]
wire t5 = x4 + invx4; // @[Snxn100k.scala 103235:18]
wire inv5 = ~t5; // @[Snxn100k.scala 103236:15]
wire x5 = t5 ^ inv5; // @[Snxn100k.scala 103237:18]
wire invx5 = ~x5; // @[Snxn100k.scala 103238:15]
wire t6 = x5 + invx5; // @[Snxn100k.scala 103239:18]
wire inv6 = ~t6; // @[Snxn100k.scala 103240:15]
wire x6 = t6 ^ inv6; // @[Snxn100k.scala 103241:18]
wire invx6 = ~x6; // @[Snxn100k.scala 103242:15]
wire t7 = x6 + invx6; // @[Snxn100k.scala 103243:18]
wire inv7 = ~t7; // @[Snxn100k.scala 103244:15]
wire x7 = t7 ^ inv7; // @[Snxn100k.scala 103245:18]
assign io_z = ~x7; // @[Snxn100k.scala 103246:15]
endmodule
| 6.592475 |
module SnxnLv4Inst210 (
input io_a,
input io_b,
output io_z
);
wire t0 = io_a + io_b; // @[Snxn100k.scala 50727:20]
wire inv0 = ~t0; // @[Snxn100k.scala 50728:15]
wire x0 = t0 ^ inv0; // @[Snxn100k.scala 50729:18]
wire invx0 = ~x0; // @[Snxn100k.scala 50730:15]
wire t1 = x0 + invx0; // @[Snxn100k.scala 50731:18]
wire inv1 = ~t1; // @[Snxn100k.scala 50732:15]
wire x1 = t1 ^ inv1; // @[Snxn100k.scala 50733:18]
wire invx1 = ~x1; // @[Snxn100k.scala 50734:15]
wire t2 = x1 + invx1; // @[Snxn100k.scala 50735:18]
wire inv2 = ~t2; // @[Snxn100k.scala 50736:15]
wire x2 = t2 ^ inv2; // @[Snxn100k.scala 50737:18]
wire invx2 = ~x2; // @[Snxn100k.scala 50738:15]
wire t3 = x2 + invx2; // @[Snxn100k.scala 50739:18]
wire inv3 = ~t3; // @[Snxn100k.scala 50740:15]
wire x3 = t3 ^ inv3; // @[Snxn100k.scala 50741:18]
wire invx3 = ~x3; // @[Snxn100k.scala 50742:15]
wire t4 = x3 + invx3; // @[Snxn100k.scala 50743:18]
wire inv4 = ~t4; // @[Snxn100k.scala 50744:15]
wire x4 = t4 ^ inv4; // @[Snxn100k.scala 50745:18]
wire invx4 = ~x4; // @[Snxn100k.scala 50746:15]
wire t5 = x4 + invx4; // @[Snxn100k.scala 50747:18]
wire inv5 = ~t5; // @[Snxn100k.scala 50748:15]
wire x5 = t5 ^ inv5; // @[Snxn100k.scala 50749:18]
assign io_z = ~x5; // @[Snxn100k.scala 50750:15]
endmodule
| 6.568619 |
module so2par (
input clk,
input ym_so,
input ym_sh1,
input ym_sh2,
input ym_p1,
output reg [15:0] left,
output reg [15:0] right,
output reg [15:0] left_exp,
output reg [15:0] right_exp,
output update_left,
output update_right
);
reg [12:0] sreg;
reg last_ym_sh1, last_ym_sh2;
reg [15:0] dr, dl;
reg [15:0] left0_pm, right0_pm;
reg [2:0] sr, sl;
reg [15:0] out_r, out_l;
reg update_l, update_r;
always @(posedge ym_p1) begin : sh_edges
last_ym_sh1 <= ym_sh1;
last_ym_sh2 <= ym_sh2;
end
always @(posedge ym_p1) begin : shift_register
// shift register
sreg <= {ym_so, sreg[12:1]};
if (last_ym_sh1 & ~ym_sh1) begin
update_r <= 1'b1;
out_r <= dr;
sr <= sreg[12:10];
dr <= {~sreg[9], sreg[8:0], 6'b000000};
right0_pm <= {3'd0, sreg};
end else begin
update_r <= 1'b0;
if (sr < 7) begin
sr <= sr + 1;
dr[14:0] <= dr[15:1];
end
end
if (last_ym_sh2 & ~ym_sh2) begin
update_l <= 1'b1;
out_l <= dl;
sl <= sreg[12:10];
dl <= {~sreg[9], sreg[8:0], 6'b000000};
left0_pm <= {3'd0, sreg};
end else begin
update_l <= 1'b0;
if (sl < 7) begin
sl <= sl + 1;
dl[14:0] <= dl[15:1];
end
end
end
reg [1:0] aux_upr, aux_upl;
assign update_right = aux_upr[1];
assign update_left = aux_upl[1];
always @(posedge clk) begin : update_sync
aux_upr[0] <= update_r;
aux_upr[1] <= aux_upr[0];
aux_upl[0] <= update_l;
aux_upl[1] <= aux_upl[0];
end
reg [15:0] aux_l, aux_r, left1, right1;
always @(posedge clk) begin : output_sync
if (update_l | update_r) begin
aux_r <= out_r;
right <= aux_r;
aux_l <= out_l;
left <= aux_l;
// salidas en formato exponencial
left1 <= left0_pm;
left_exp <= left1;
right1 <= right0_pm;
right_exp <= right1;
end
end
endmodule
| 6.571011 |
module SOA #(
parameter M = 11
) (
input wire [16+3-1-M+1:0] tloga, /* M=11, [8:0] */
input wire [16+3-1-M+1:0] tlogb,
output wire [19:0] sumlog
);
/* adder, has 9 bits */
wire cin = tloga[0] & tlogb[0];
wire c14; /* carry of 14 bit */
MCLA_4_c_c4 MCLA_4_c_c4 (
.a (tloga[4:1]),
.b (tlogb[4:1]),
.c0(cin),
.s (sumlog[14:11]), /* 4 bits*/
.c4(c14)
);
MCLA_4_c_c0 MCLA_4_c_c0 (
.a (tloga[8:5]),
.b (tlogb[8:5]),
.c0(c14),
.s(sumlog[19:15]) /* 5 bits*/
);
/* set-one, has 11 bits */
assign sumlog[M-1:0] = 11'b111_1111_1111;
endmodule
| 7.061186 |
module Ring_Oscillator_TB ();
reg inp = 1'b1;
wire my_clock;
ring_oscillator #(5, 2) CUT1 (
inp,
my_clock
); //10ns here!
initial begin
#1000 $stop;
end
endmodule
| 6.585354 |
module SOA_11 #(
parameter M = 11
) (
input wire [16+3-1-M+1:0] tloga, /* M=11, [8:0] */
input wire [16+3-1-M+1:0] tlogb,
output wire [19:0] sumlog
);
/* adder, has 9 bits */
wire cin = tloga[0] & tlogb[0];
wire c14; /* carry of 14 bit */
MCLA_4_c_c4 MCLA_4_c_c4 (
.a (tloga[4:1]),
.b (tlogb[4:1]),
.c0(cin),
.s (sumlog[14:11]), /* 4 bits*/
.c4(c14)
);
MCLA_4_c_c0 MCLA_4_c_c0 (
.a (tloga[8:5]),
.b (tlogb[8:5]),
.c0(c14),
.s(sumlog[19:15]) /* 5 bits*/
);
/* set-one, has 11 bits */
assign sumlog[M-1:0] = 11'b111_1111_1111;
endmodule
| 7.176011 |
module SOA_5 #(
parameter M = 5
) (
input wire [16+3-1-M+1:0] tloga, /* M=5 , [14:0] */
input wire [16+3-1-M+1:0] tlogb,
output wire [19:0] sumlog,
output wire cin_EST /* cin of the EST */
);
/* adder, has 15 bits */
wire cin = tloga[0] & tlogb[0];
wire [15:0] A, B, S;
assign A = {2'b00, tloga[14:1]};
assign B = {2'b00, tlogb[14:1]};
MCLA_16_c0_c10 MCLA_16_c0_c10 (
.a (A),
.b (B),
.c0(cin),
.s(S), /* 16 bits */
.c10(cin_EST)
);
assign sumlog[19:M] = S[14:0]; /* 15 bits */
/* set-one, has 5 bits */
assign sumlog[M-1:0] = 5'b1_1111;
endmodule
| 7.905631 |
module sobelBufferBlock (
clk,
popBufferEn,
reset,
readData,
BufferA,
BufferB,
BufferC,
BufferD
);
parameter STARTADDRESS = 0, ENDADDRESS = 2097151, BEATS = 3, PAUSE = 1, PIXW = 24;
input clk, popBufferEn, reset;
input [63:0] readData;
output [63:0] BufferA;
output [63:0] BufferB;
output [63:0] BufferC;
output [63:0] BufferD;
wire clk, popBufferEn, started, process, reset;
wire [63:0] readData;
reg [63:0] BufferA;
reg [63:0] BufferB;
reg [63:0] BufferC;
reg [63:0] BufferD;
wire [23:0] pixelCounter;
reg [63:0] regBufferB;
reg [63:0] regBufferC;
reg [63:0] regBufferD;
reg [63:0] regBufferBH;
reg [63:0] regBufferCH;
wire nclk;
assign nclk = !clk;
beatCounter #(
.MINPIXEL(STARTADDRESS),
.MAXPIXEL(ENDADDRESS),
.BEATS(BEATS),
.PAUSE(PAUSE),
.PIXELCOUNTERWIDTH(PIXW)
) bufferCounterBlock (
clk,
popBufferEn,
reset,
process,
started,
pixelCounter
);
always @(posedge nclk) begin
if (process == 1) begin
regBufferB <= readData;
regBufferC <= regBufferBH;
regBufferD <= regBufferCH;
end
if (process == 0 && started == 1) begin
BufferD <= regBufferD;
BufferC <= regBufferC;
BufferB <= regBufferB;
BufferA <= readData;
end
end
always @(posedge clk) begin
if (process == 1) begin
regBufferBH <= regBufferB;
regBufferCH <= regBufferC;
end
end
always @(posedge clk)
if (reset == 1) begin
regBufferB = 0;
regBufferC = 0;
regBufferD = 0;
BufferA = 0;
BufferB = 0;
BufferC = 0;
BufferD = 0;
end
endmodule
| 6.911844 |
module sobelDir (
clk,
startEn,
reset,
sobelX,
sobelY,
dirE
);
parameter STARTADDRESS = 770, ENDADDRESS = 523518,BEATS = 4, PAUSE = 1,COUNTSTEPHOLD = 2, PIXW = 24;//address starts in and down two pixels ends the same. parameter can be imported to accommodate second concurrent pixel
parameter STHRESHOLD = 5632;
input clk, startEn, reset;
input signed [8:0] sobelX;
input signed [8:0] sobelY;
output [7:0] dirE;
wire clk, startEn, started, process, reset, nclk;
wire [23:0] pixelCounter;
wire signed [8:0] sobelX;
wire signed [8:0] sobelY;
wire signed [17:0] sobelY16;
reg signed [17:0] normalisedDir;
reg [7:0] dirE;
reg signed [8:0] sobMult;
wire normaliseFilter;
reg signed [17:0] oneOSix;
reg signed [17:0] six1Six;
reg signed [17:0] mThreeO5;
//assign sobelY16 = (sobelY >= 0)?{sobelY,8'b00000000}:{sobelY[8:1],9'b011111111};
//assign sobelY16 = (sobelX != 0)? ((sobelY*sobMult)/sobelX):0;
assign sobelY16 = ((sobelY * sobMult) / sobelX);
assign normaliseFilter = ((sobelX ** 2 + sobelY ** 2) > STHRESHOLD);
assign nclk = !clk;
beatCounter #(
.MINPIXEL(STARTADDRESS),
.MAXPIXEL(ENDADDRESS),
.BEATS(BEATS),
.PAUSE(PAUSE),
.COUNTSTEP(COUNTSTEPHOLD),
.PIXELCOUNTERWIDTH(PIXW)
) bufferCounterBlock (
clk,
startEn,
reset,
process,
started,
pixelCounter
);
always @(posedge nclk) begin
if (started == 1 && normaliseFilter == 1) begin
if (sobelX != 0) begin
normalisedDir <= sobelY16; //May be an issue in syntheses
end else begin
normalisedDir <= 0;
end
end
end
always @(posedge clk) begin
if (started == 1 && sobelX != 0) begin
if (normaliseFilter == 1) begin
if ((oneOSix < sobelY16) && (sobelY16 <= six1Six)) begin
dirE <= 255;
end else if ((sobelY16 > six1Six) || (sobelY16 <= mThreeO5)) begin
dirE <= 192;
end else if ((mThreeO5 < sobelY16) && (sobelY16 <= oneOSix)) begin
dirE <= 128;
end else begin
dirE <= 10;
end
end
end else begin
dirE <= 0;
end
end
always @(posedge clk)
if (reset == 1) begin
normalisedDir <= 0;
dirE <= 0;
sobMult = 255;
oneOSix = 106;
six1Six = 616;
mThreeO5 = -305;
end
endmodule
| 6.563405 |
module sobelHoldBlock (
clk,
HoldEn,
reset,
ShiftA,
ShiftB,
ShiftC,
HoldOutA,
HoldOutB,
HoldOutC
);
parameter STARTADDRESS = 770, ENDADDRESS = 2097152 ,BEATS = 3, PAUSE = 1,COUNTSTEPHOLD = 2, PIXW = 24;//address starts in and down two pixels ends the same. parameter can be imported to accommodate second concurrent pixel
input clk, HoldEn, reset;
input [23:0] ShiftA;
input [23:0] ShiftB;
input [23:0] ShiftC;
output [23:0] HoldOutA;
output [23:0] HoldOutB;
output [23:0] HoldOutC;
wire clk, holdEn, started, process, reset;
wire [23:0] ShiftA;
wire [23:0] ShiftB;
wire [23:0] ShiftC;
wire [23:0] pixelCounter;
wire [23:0] HoldOutA;
wire [23:0] HoldOutB;
wire [23:0] HoldOutC;
reg [23:0] HoldBufferA;
reg [23:0] HoldBufferB;
reg [23:0] HoldBufferC;
assign HoldOutA[23:0] = HoldBufferA[23:0];
assign HoldOutB[23:0] = HoldBufferB[23:0];
assign HoldOutC[23:0] = HoldBufferC[23:0];
beatCounter #(
.MINPIXEL(STARTADDRESS),
.MAXPIXEL(ENDADDRESS),
.BEATS(BEATS),
.PAUSE(PAUSE),
.COUNTSTEP(COUNTSTEPHOLD),
.PIXELCOUNTERWIDTH(PIXW)
) bufferCounterBlock (
clk,
HoldEn,
reset,
process,
started,
pixelCounter
);
always @(posedge clk) begin
if (started == 1) begin
HoldBufferA[23:0] <= ShiftA;//Takes gausBuffer + q1 'array' and deposits in the 64 LSB's of the 5 ShiftBuffer Block
HoldBufferB[23:0] <= ShiftB;
HoldBufferC[23:0] <= ShiftC;
end
//Basic form needs conditions for transition from one row to next.....
end
always @(posedge clk)
if (reset == 1) begin
HoldBufferA = 0;
HoldBufferB = 0;
HoldBufferC = 0;
end
endmodule
| 7.468646 |
module sobelMag (
clk,
startEn,
reset,
sobelX,
sobelY,
normalisedMag
);
parameter STARTADDRESS = 770, ENDADDRESS = 523518,BEATS = 4, PAUSE = 1,COUNTSTEPHOLD = 2, PIXW = 24;//address starts in and down two pixels ends the same. parameter can be imported to accommodate second concurrent pixel
parameter STHRESHOLD = 5632;
input clk, startEn, reset;
input signed [8:0] sobelX;
input signed [8:0] sobelY;
output [7:0] normalisedMag;
output normaliseFilter;
wire clk, startEn, started, process, reset;
wire [23:0] pixelCounter;
wire signed [8:0] sobelX;
wire signed [8:0] sobelY;
wire normaliseFilter;
wire signed [17:0] unnormalisedMag;
reg [7:0] normalisedMag;
reg processFlag;
reg signed [9:0] normDevider;
assign normaliseFilter = ((sobelX * sobelX + sobelY * sobelY) > STHRESHOLD);
assign unnormalisedMag = (sobelX * sobelX + sobelY * sobelY);
beatCounter #(
.MINPIXEL(STARTADDRESS),
.MAXPIXEL(ENDADDRESS),
.BEATS(BEATS),
.PAUSE(PAUSE),
.COUNTSTEP(COUNTSTEPHOLD),
.PIXELCOUNTERWIDTH(PIXW)
) bufferCounterBlock (
clk,
startEn,
reset,
process,
started,
pixelCounter
);
always @(posedge clk) begin
if ((started == 1) && (normaliseFilter == 1)) begin
normalisedMag <=unnormalisedMag[16:9];//normDevider;//Truncate last 9 bits, ie divide by 512
processFlag <= 1;
end else if ((started == 1) && (normaliseFilter == 0)) begin
normalisedMag <= 0;
processFlag <= 0;
end
end
always @(posedge clk) begin
if (reset == 1) begin
normalisedMag <= 0;
processFlag <= 0;
normDevider <= 512;
end
end
endmodule
| 6.895943 |
module sobelMultBlock (
clk,
startMultiplierEn,
reset,
sobelHoldOutA,
sobelHoldOutB,
sobelHoldOutC,
sobelX,
sobelY
);
parameter STARTADDRESS = 770, ENDADDRESS = 2097152/2,BEATS = 4, PAUSE = 1,COUNTSTEPHOLD = 2, PICW = 24;//address starts in and down two pixels ends the same. parameter can be imported to accommodate second concurrent pixel
input clk, startMultiplierEn, reset;
input [23:0] sobelHoldOutA;
input [23:0] sobelHoldOutB;
input [23:0] sobelHoldOutC;
output signed [8:0] sobelX;
output signed [8:0] sobelY;
wire clk, startMultiplierEn, started, process, reset;
wire [23:0] pixelCounter;
wire [23:0] sobelHoldOutA;
wire [23:0] sobelHoldOutB;
wire [23:0] sobelHoldOutC;
reg signed [8:0] sobelX;
reg signed [8:0] sobelY;
wire signed [8:0] combSobelX;
wire signed [8:0] combSobelY;
reg signed [8:0] MultA1X;
reg signed [8:0] MultA2X;
reg signed [8:0] MultA3X;
reg signed [8:0] MultB1X;
reg signed [8:0] MultB2X;
reg signed [8:0] MultB3X;
reg signed [8:0] MultC1X;
reg signed [8:0] MultC2X;
reg signed [8:0] MultC3X;
reg signed [8:0] MultA1Y;
reg signed [8:0] MultA2Y;
reg signed [8:0] MultA3Y;
reg signed [8:0] MultB1Y;
reg signed [8:0] MultB2Y;
reg signed [8:0] MultB3Y;
reg signed [8:0] MultC1Y;
reg signed [8:0] MultC2Y;
reg signed [8:0] MultC3Y;
assign combSobelX = (MultA1X+MultA2X+MultA3X+MultB1X+MultB2X+MultB3X+MultC1X+MultC2X+MultC3X);
assign combSobelY = (MultA1Y+MultA2Y+MultA3Y+MultB1Y+MultB2Y+MultB3Y+MultC1Y+MultC2Y+MultC3Y);
beatCounter #(
.MINPIXEL(STARTADDRESS),
.MAXPIXEL(ENDADDRESS),
.BEATS(BEATS),
.PAUSE(PAUSE),
.COUNTSTEP(COUNTSTEPHOLD),
.PIXELCOUNTERWIDTH(PICW)
) bufferCounterBlock (
clk,
startMultiplierEn,
reset,
process,
started,
pixelCounter
);
always @(posedge clk) begin
// $display("X Mult: %d combSobelX: %d",$signed(MultA1X+MultA2X+MultA3X+MultB1X+MultB2X+MultB3X+MultC1X+MultC2X+MultC3X),combSobelX);
// $display("Y Mult: %d combSobelY: %d",$signed(MultA1Y+MultA2Y+MultA3Y+MultB1Y+MultB2Y+MultB3Y+MultC1Y+MultC2Y+MultC3Y),combSobelY);
if (started == 1) begin
//Sobel x Filter multiplication
MultA1X <= (sobelHoldOutA[23:16] * (-1));
MultA2X <= 0;
MultA3X <= (sobelHoldOutA[7:0]);
MultB1X <= (sobelHoldOutB[23:16] * (-2));
MultB2X <= 0;
MultB3X <= (sobelHoldOutB[7:0] * 2);
MultC1X <= (sobelHoldOutC[23:16] * (-1));
MultC2X <= 0;
MultC3X <= (sobelHoldOutC[7:0]);
// Sobel Y Filter Multiplication
MultA1Y <= (sobelHoldOutA[23:16] * (-1));
MultA2Y <= (sobelHoldOutA[15:8] * (-2));
MultA3Y <= (sobelHoldOutA[7:0] * (-1));
MultB1Y <= (0);
MultB2Y <= (0);
MultB3Y <= (0);
MultC1Y <= (sobelHoldOutC[23:16]);
MultC2Y <= (sobelHoldOutC[15:8] * (2));
MultC3Y <= (sobelHoldOutC[7:0]);
sobelX <= combSobelX;
sobelY <= combSobelY;
// sobelX <= {combSobelX[12],combSobelX[7:0]};//Values contraindicated first 'sign' bit + rest of 8 bit values...
// sobelY <= {combSobelY[12],combSobelY[7:0]};
end else begin
MultA1X <= 0;
MultA2X <= 0;
MultA3X <= 0;
MultB1X <= 0;
MultB2X <= 0;
MultB3X <= 0;
MultC1X <= 0;
MultC2X <= 0;
MultC3X <= 0;
MultA1Y <= 0;
MultA2Y <= 0;
MultA3Y <= 0;
MultB1Y <= 0;
MultB2Y <= 0;
MultB3Y <= 0;
MultC1Y <= 0;
MultC2Y <= 0;
MultC3Y <= 0;
sobelX <= 0;
sobelY <= 0;
end
end
always @(posedge clk)
if (reset == 1) begin
MultA1X <= 0;
MultA2X <= 0;
MultA3X <= 0;
MultB1X <= 0;
MultB2X <= 0;
MultB3X <= 0;
MultC1X <= 0;
MultC2X <= 0;
MultC3X <= 0;
MultA1Y <= 0;
MultA2Y <= 0;
MultA3Y <= 0;
MultB1Y <= 0;
MultB2Y <= 0;
MultB3Y <= 0;
MultC1Y <= 0;
MultC2Y <= 0;
MultC3Y <= 0;
sobelX <= 0;
sobelY <= 0;
end
endmodule
| 7.078334 |
module sobelTB ();
integer f;
parameter C0 = 3'b000, C1 = 3'b001, C2 = 3'b010, C3 = 3'b011, C4 = 3'b100;
wire [63:0] data1;
wire [63:0] data2;
wire [63:0] data3;
reg clk, we1, reset, startEn;
reg [ 2:0] addressCase;
wire [63:0] q1;
wire [63:0] q2;
wire [63:0] q3;
wire we2, getNext;
wire [ 7:0] colPos;
reg [19:0] read_addr1;
reg [19:0] read_addr2;
reg [19:0] read_addr3;
reg [19:0] addresSchedule;
wire [19:0] write_addr1;
wire [19:0] write_addr2;
wire [19:0] write_addr3;
//Ram memory blocks (Simulated)
assign colPos[7:0] = addresSchedule[7:0];
simple_ram_dual_clock SRAM1 (
data1,
read_addr1,
write_addr1,
we1,
clk,
clk,
q1
);
simple_ram_dual_clock SRAM2 (
data2,
read_addr2,
write_addr2,
we2,
clk,
clk,
q2
);
simple_ram_dual_clock SRAM3 (
data3,
read_addr3,
write_addr3,
we3,
clk,
clk,
q3
);
sobelFilter sobelFilter1 (
clk,
reset,
startEn,
read_addr1,
q1,
we2,
we3,
write_addr2,
data2,
write_addr3,
data3,
getNext
);
initial begin
$readmemh("C:/hexfiles/outfile2.hex", SRAM1.ram);
f = $fopen("sobTan.csv", "w");
// SRAM1.ram[0] <= 64'hF0E0D0C0B0A09080;
// SRAM1.ram[256] <= 64'hF0E0D0C0B0A09080;
// SRAM1.ram[512] <= 64'hF0E0D0C0B0A09080;
// SRAM1.ram[768] <= 64'hF0E0D0C0B0A09080;
$display("ramValue:", SRAM1.ram[0]);
clk = 0;
reset = 1;
addresSchedule = 768;
#10;
reset = 0;
// #10;
startEn = 1;
#10;
startEn = 0;
#4000000;
// #150000;
#10000;
$writememh("C:/hexfiles/outSRAM4sobel.hex", SRAM2.ram);
$writememh("C:/hexfiles/outSRAM3sobeldir.hex", SRAM3.ram);
$display("ramValue:", SRAM2.ram[0]);
$fclose(f);
$stop;
$finish;
end
always @(posedge clk) begin
case (addressCase)
C0: begin
read_addr1 <= addresSchedule;
addressCase <= C1;
end
C1: begin
read_addr1 <= addresSchedule;
addressCase <= C2;
end
C2: begin
read_addr1 <= addresSchedule - 256;
addressCase <= C3;
end
C3: begin
read_addr1 <= addresSchedule - (256 * 2);
addressCase <= C4;
end
C4: begin
read_addr1 <= addresSchedule - (256 * 3);
if (colPos == 255) begin
addresSchedule <= addresSchedule + 257;
end else begin
addresSchedule <= addresSchedule + 1;
end
addressCase <= C1;
end
endcase
end
// for(addresSchedule = 1280; addresSchedule <= 50000; addresSchedule++ )
// begin
// read_addr1 = addresSchedule;
// #10;
// read_addr1 = addresSchedule-256;
// #10;
// //read_addr1 <= addresSchedule -(256*2);
// #10;
// read_addr1 = addresSchedule -(256*3);
// #10;
// read_addr1 = addresSchedule -(256*4);
// #10;
// end
always @(posedge clk) begin
if (reset == 1) begin
read_addr1 = 0;
addresSchedule = 768;
addressCase = C0;
end
end
always @(posedge clk) begin
if (sobelFilter1.sobelMultBlock1.started != 0) begin
$fwrite(f, "%d,%d\n", sobelFilter1.sobelMultBlock1.sobelY, sobelFilter1.sobelDir1.sobelY,
sobelFilter1.sobelMultBlock1.sobelX);
end
end
always begin
clk = #5 !clk; //100mHz clock
end
initial begin
$dumpfile("sobelSim.fst");
$dumpvars(0, sobelTB);
end
endmodule
| 6.962846 |
module sobel_add_nb #(
parameter bitwidth = 8
) (
a,
b,
ans_out,
cout,
subtract
); //parameter here
input [bitwidth-1:0] a;
input [bitwidth-1:0] b;
input subtract;
output cout;
output [bitwidth-1:0] ans_out;
wire [bitwidth-2:0] carry;
wire [bitwidth-1:0] bcomp;
`SR(s26, exoor X_0 (b[0],subtract,bcomp[0]);, assign bcomp[0] = 'b0;)
`SR(s27, fa fa_0 (a[0],bcomp[0],subtract,ans_out[0],carry[0]);, assign ans_out[0] = 'b0;
assign carry[0] = 'b0;)
genvar i;
generate
for (i = 1; i < bitwidth - 1; i = i + 1) begin : gen_fa
`SR(s28, exoor X_i (b[i],subtract,bcomp[i]);, assign bcomp[i] = 'b0;)
`SR(s29, fa fa_i (a[i],bcomp[i],carry[i-1],ans_out[i],carry[i]);,
assign ans_out[i] = 'b0;
assign carry[i] = 'b0;)
end
endgenerate
`SR(s30, exoor X_bitwidth (b[bitwidth-1],subtract,bcomp[bitwidth-1]);,
assign bcomp[bitwidth-1] = 'b0;)
`SR(s31,
fa fa_bitwidth (a[bitwidth-1],bcomp[bitwidth-1],carry[bitwidth-2],ans_out[bitwidth-1],cout);,
assign ans_out[bitwidth-1] = 'b0;
assign cout = 'b0;)
endmodule
| 6.671204 |
module sobel_edge_detect_tb;
reg clk;
reg pic_ena;
reg vs;
reg hs;
reg [7:0] median_filter_data = 8'b1111_1111;
wire post_vs;
wire post_hs;
wire post_pic_ena;
wire sobel_detect_data_bit;
sobel_edge_detect U_sobel_detect (
.clk(clk),
.rst(1'b0),
.pic_ena(1'b1), //图片使能，表示这个clk在处理图片
.vs(1'b1),
.hs(1'b1),
.threshold(16'd150),
.median_filter_data(median_filter_data),
.sobel_detect_data_bit(sobel_detect_data_bit),
.post_vs(post_vs),
.post_hs(post_hs),
.post_pic_ena(post_pic_ena)
);
integer i;
integer j;
initial begin
#5;
for (j = 0; j <= 2000; j = j + 1) begin
clk = 0;
//median_value = vcount;
#1;
clk = 1;
#1;
/*
for(i = 1; i <= 20; i = i + 1)
begin
clk = ~clk;
median_value = i[7:0] + vcount;
#1;
clk = ~clk;
#5;
end
*/
end
end
endmodule
| 7.090042 |
module sobel_filter #(
parameter VESA_STD = "VESA_180X720_60FPS",
parameter X_START = 0,
parameter Y_START = 0,
parameter X_END = 640,
parameter Y_END = 720,
parameter Y_DEPTH = 8,
parameter X_LSB_CNT_WIDTH = 4,
parameter X_MSB_CNT_WIDTH = 6,
parameter Y_LSB_CNT_WIDTH = 4,
parameter Y_MSB_CNT_WIDTH = 6
) (
input i_arst,
input i_pclk,
input i_vsync,
input i_hsync,
input i_de,
input [Y_DEPTH-1:0] i_y_11_01,
input [Y_DEPTH-1:0] i_y_00_01,
input [Y_DEPTH-1:0] i_y_01_01,
output o_x_en,
output o_vsync,
output o_hsync,
output o_de,
output [Y_DEPTH-1:0] o_y
);
localparam HOR_SYNC_POLARITY = `HOR_SYNC_POLARITY;
localparam VER_SYNC_POLARITY = `VER_SYNC_POLARITY;
wire c_act_vs_por;
wire c_ina_vs_por;
wire c_act_hs_por;
wire c_ina_hs_por;
wire c_act_de_por;
wire c_ina_de_por;
reg r_vsync_1P;
reg r_de_1P;
wire w_x_en_1P;
wire w_hsync_1P;
wire w_x_en_9P;
wire w_vsync_9P;
wire w_hsync_9P;
wire w_de_9P;
wire [Y_DEPTH-1:0] w_y_9P;
generate
if (HOR_SYNC_POLARITY == "NEGATIVE") begin
assign c_act_hs_por = 1'b0;
assign c_ina_hs_por = 1'b1;
end else begin
assign c_act_hs_por = 1'b1;
assign c_ina_hs_por = 1'b0;
end
if (VER_SYNC_POLARITY == "NEGATIVE") begin
assign c_act_vs_por = 1'b0;
assign c_ina_vs_por = 1'b1;
end else begin
assign c_act_vs_por = 1'b1;
assign c_ina_vs_por = 1'b0;
end
endgenerate
assign c_act_de_por = 1'b1;
assign c_ina_de_por = 1'b0;
sobel_feldman
//sobel_scharr
#(
.Y_DEPTH(Y_DEPTH)
) inst_sobel_pixel (
.i_arst(i_arst),
.i_pclk(i_pclk),
.i_pixel_11_01(i_y_11_01),
.i_pixel_00_01(i_y_00_01),
.i_pixel_01_01(i_y_01_01),
.o_pixel(w_y_9P)
);
filter_size #(
.VESA_STD(VESA_STD),
.X_START(0),
.Y_START(0),
.X_END(640),
.Y_END(720),
.X_LSB_CNT_WIDTH(4),
.X_MSB_CNT_WIDTH(6),
.Y_LSB_CNT_WIDTH(4),
.Y_MSB_CNT_WIDTH(6)
) isnt_filter_size (
.i_arst (i_arst),
.i_pclk (i_pclk),
.i_hsync(i_hsync),
.o_hsync(w_hsync_1P),
.o_x_en (w_x_en_1P)
);
shift_reg #(
.D_WIDTH(4),
.TAPE(8)
) inst_shift_reg (
.i_arst(i_arst),
.i_clk (i_pclk),
.i_d({w_x_en_1P, r_vsync_1P, w_hsync_1P, r_de_1P}),
.o_q({w_x_en_9P, w_vsync_9P, w_hsync_9P, w_de_9P})
);
always @(posedge i_arst or posedge i_pclk) begin
if (i_arst) begin
r_vsync_1P <= c_ina_vs_por;
r_de_1P <= c_ina_de_por;
end else begin
r_vsync_1P <= i_vsync;
r_de_1P <= i_de;
end
end
assign o_x_en = w_x_en_9P;
assign o_vsync = w_vsync_9P;
assign o_hsync = w_hsync_9P;
assign o_de = w_de_9P;
assign o_y = w_y_9P;
endmodule
| 8.441599 |
module sobel_filtering (
input clk,
input [ 7:0] Y_data,
input [10:0] key_value,
input Y_de,
Y_hsync,
Y_vsync,
output wire sobel_hsync,
sobel_vsync,
sobel_de,
output wire sobel_data
);
//sobel ---------------------------------------------
reg [9:0] Gx1, Gx3, Gy1, Gy3, Gx, Gy;
reg [10:0] G;
//parameter value = 11'd75;
//--------------------------------------------------- 矩阵顺序
// {matrix_11, matrix_12, matrix_13}
// {matrix_21, matrix_22, matrix_23}
// {matrix_31, matrix_32, matrix_33}
//--------------------------------------------------- 模块例化
wire [ 7:0] matrix_11, matrix_12, matrix_13,matrix_21,matrix_22, matrix_23, matrix_31, matrix_32, matrix_33;
//==========================================================================
//== Sobel处理，耗费3clk
//==========================================================================
//clk1：Gx1、Gx3和Gy1、Gy3
//---------------------------------------------------
always @(posedge clk) begin
Gx1 <= matrix_11 + (matrix_21 << 1) + matrix_31;
Gx3 <= matrix_13 + (matrix_23 << 1) + matrix_33;
Gy1 <= matrix_11 + (matrix_12 << 1) + matrix_13;
Gy3 <= matrix_31 + (matrix_32 << 1) + matrix_33;
end
//clk2：Gx和Gy绝对值
//---------------------------------------------------
always @(posedge clk) begin
Gx <= (Gx1 > Gx3) ? (Gx1 - Gx3) : (Gx3 - Gx1);
Gy <= (Gy1 > Gy3) ? (Gy1 - Gy3) : (Gy3 - Gy1);
end
//clk3：Gx+Gy
//---------------------------------------------------
always @(posedge clk) begin
G <= Gx + Gy;
end
assign sobel_data = ((G > key_value) && Y_de) ? 1'b0 : 1'b1;
// opr 3
opr_3 opr_3_m0 (
.clk (clk),
.din_vld (Y_de),
.din (Y_data),
.matrix_11(matrix_11),
.matrix_12(matrix_12),
.matrix_13(matrix_13),
.matrix_21(matrix_21),
.matrix_22(matrix_22),
.matrix_23(matrix_23),
.matrix_31(matrix_31),
.matrix_32(matrix_32),
.matrix_33(matrix_33)
);
//==========================================================================
//== 信号同步
//==========================================================================
reg [3:0] Y_de_r, Y_hsync_r, Y_vsync_r;
always @(posedge clk) begin
Y_de_r <= {Y_de_r[2:0], Y_de};
Y_hsync_r <= {Y_hsync_r[2:0], Y_hsync};
Y_vsync_r <= {Y_vsync_r[2:0], Y_vsync};
end
assign sobel_de = Y_de_r[3];
assign sobel_hsync = Y_hsync_r[3];
assign sobel_vsync = Y_vsync_r[3];
endmodule
| 7.040271 |
module sobel_func #(
parameter DATA_WIDTH = 8
) (
output wire [DATA_WIDTH-1:0] data_out,
input wire [DATA_WIDTH-1:0] in1,
input wire [DATA_WIDTH-1:0] in2,
input wire [DATA_WIDTH-1:0] in3,
input wire [DATA_WIDTH-1:0] in4,
input wire [DATA_WIDTH-1:0] in5,
input wire [DATA_WIDTH-1:0] in6,
input wire [DATA_WIDTH-1:0] in7,
input wire [DATA_WIDTH-1:0] in8,
input wire [DATA_WIDTH-1:0] in9,
input wire clk,
input wire rst,
input wire enable
);
reg [DATA_WIDTH+1:0] dout;
reg [DATA_WIDTH+1:0] add1;
reg [DATA_WIDTH+1:0] add2;
reg [DATA_WIDTH+1:0] add3;
reg [DATA_WIDTH+1:0] add4;
reg [DATA_WIDTH+1:0] gx;
reg [DATA_WIDTH+1:0] gy;
reg [DATA_WIDTH+1:0] max;
reg [DATA_WIDTH+1:0] min;
reg [DATA_WIDTH+1:0] result;
assign data_out = dout;
always @(posedge clk or posedge rst) begin
if (rst == 1) begin
dout <= 11'b0;
end else if (enable == 1) begin
add1 <= in3 + 2 * in6 + in9;
add2 <= in1 + 2 * in4 + in7;
add3 <= in1 + 2 * in2 + in3;
add4 <= in7 + 2 * in8 + in9;
gy <= (add1 > add2) ? add1 - add2 : add2 - add1;
gx <= (add3 > add4) ? add3 - add4 : add4 - add3;
if (gx >= gy) begin
max <= gx - gx >> 3;
min <= gy >> 1;
result <= max + min;
end else begin
max <= gy - gy >> 3;
min <= gy >> 1;
result <= max + min;
end
if (result >= max) begin
dout <= result;
end else begin
dout <= max;
end
end
end
endmodule
| 7.294685 |
module sobel_image_rowregs (
// Clock and reset ports
input clk,
input reset,
// System-wide control signals
input go,
// Interface: Sobel Control -> Sobel Image Row Registers
input [`SOBEL_ROW_OP_WIDTH-1:0] sctl2srow_row_op, // command, specifies what to do with the incoming data, if anything
// Interface: Memory (input buffer) -> Sobel Image Row Registers
input [`SOBEL_IDATA_WIDTH-1:0] srt2srow_read_data, // memory read data, contains a new block of pixels
// Interface: Sobel Image Row Registers -> Sobel Accelerator Core
output [`SOBEL_IDATA_WIDTH-1:0] srow2sacc_row1_data, // row 1 output data
output [`SOBEL_IDATA_WIDTH-1:0] srow2sacc_row2_data, // row 2 output data
output [`SOBEL_IDATA_WIDTH-1:0] srow2sacc_row3_data // row 3 output data
);
// Internal signals
wire [`SOBEL_IDATA_WIDTH-1:0] row1, row2, row3; // current row data, driven by the row registers
reg [`SOBEL_IDATA_WIDTH-1:0]
row1_next, row2_next, row3_next; // next values for the row data, drives the row registers
// Output generation
assign srow2sacc_row1_data = row1;
assign srow2sacc_row2_data = row2;
assign srow2sacc_row3_data = row3;
// Registers
dffre #(`SOBEL_IDATA_WIDTH) row1_r (
.clk(clk),
.en (go),
.d (row1_next),
.q (row1),
.r (reset)
);
dffre #(`SOBEL_IDATA_WIDTH) row2_r (
.clk(clk),
.en (go),
.d (row2_next),
.q (row2),
.r (reset)
);
dffre #(`SOBEL_IDATA_WIDTH) row3_r (
.clk(clk),
.en (go),
.d (row3_next),
.q (row3),
.r (reset)
);
// Control signal processing and register operations
always @(*) begin
case (sctl2srow_row_op)
`SOBEL_ROW_OP_HOLD: begin
row1_next = row1;
row2_next = row2;
row3_next = row3;
end
`SOBEL_ROW_OP_SHIFT_ROW: begin
row1_next = row2;
row2_next = row3;
row3_next = srt2srow_read_data;
end
default: begin
row1_next = 'h0;
row2_next = 'h0;
row3_next = 'h0;
end
endcase
end
endmodule
| 7.403636 |
module sobel_shift (
aclr,
clken,
clock,
shiftin,
shiftout,
taps0x,
taps1x,
taps2x
);
input aclr;
input clken;
input clock;
input [0:0] shiftin;
output [0:0] shiftout;
output [0:0] taps0x;
output [0:0] taps1x;
output [0:0] taps2x;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 aclr;
tri1 clken;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire0;
wire [2:0] sub_wire1;
wire [0:0] shiftout = sub_wire0[0:0];
wire [2:2] sub_wire5 = sub_wire1[2:2];
wire [1:1] sub_wire4 = sub_wire1[1:1];
wire [1:1] sub_wire3 = sub_wire4[1:1];
wire [0:0] sub_wire2 = sub_wire1[0:0];
wire [0:0] taps0x = sub_wire2[0:0];
wire [0:0] taps1x = sub_wire3[1:1];
wire [0:0] taps2x = sub_wire5[2:2];
altshift_taps ALTSHIFT_TAPS_component (
.aclr(aclr),
.clken(clken),
.clock(clock),
.shiftin(shiftin),
.shiftout(sub_wire0),
.taps(sub_wire1)
// synopsys translate_off
//,
//.sclr ()
// synopsys translate_on
);
defparam ALTSHIFT_TAPS_component.intended_device_family = "Cyclone IV E",
ALTSHIFT_TAPS_component.lpm_hint = "RAM_BLOCK_TYPE=M9K", ALTSHIFT_TAPS_component.lpm_type =
"altshift_taps", ALTSHIFT_TAPS_component.number_of_taps = 3,
ALTSHIFT_TAPS_component.tap_distance = 1280, ALTSHIFT_TAPS_component.width = 1;
endmodule
| 6.745861 |
module sobel_shift (
aclr,
clken,
clock,
shiftin,
shiftout,
taps0x,
taps1x,
taps2x
);
input aclr;
input clken;
input clock;
input [0:0] shiftin;
output [0:0] shiftout;
output [0:0] taps0x;
output [0:0] taps1x;
output [0:0] taps2x;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 aclr;
tri1 clken;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.745861 |
module Sobel (
input iCLK,
input iRST_N,
input [7:0] iTHRESHOLD,
input iDVAL,
input [9:0] iDATA,
output reg oDVAL,
output wire [9:0] oDATA
);
// mask x
parameter X1 = 8'hff, X2 = 8'h00, X3 = 8'h01;
parameter X4 = 8'hfe, X5 = 8'h00, X6 = 8'h02;
parameter X7 = 8'hff, X8 = 8'h00, X9 = 8'h01;
// mask y
parameter Y1 = 8'h01, Y2 = 8'h02, Y3 = 8'h01;
parameter Y4 = 8'h00, Y5 = 8'h00, Y6 = 8'h00;
parameter Y7 = 8'hff, Y8 = 8'hfe, Y9 = 8'hff;
wire [ 7:0] Line0;
wire [ 7:0] Line1;
wire [ 7:0] Line2;
wire [17:0] Mac_x0;
wire [17:0] Mac_x1;
wire [17:0] Mac_x2;
wire [17:0] Mac_y0;
wire [17:0] Mac_y1;
wire [17:0] Mac_y2;
wire [19:0] Pa_x;
wire [19:0] Pa_y;
wire [15:0] Abs_mag;
assign oDATA = iDATA;
// replace the above
endmodule
| 7.299654 |
module sobel_test (
input clk,
input rst_n,
input [20:0] threshold,
input ycbcr_vs, //ԤͼЧź
input ycbcr_hs, //ԤͼЧź
input ycbcr_de, //ԤͼʹЧź
input [7:0] ycbcr_y,
output sobel_vs, //ͼЧź
output sobel_hs, //ͼЧź
output sobel_de, //ͼʹЧź
output [23:0] sobel_data1,
output sobel_data
);
reg [ 9:0] Gx_temp2; //ֵ
reg [ 9:0] Gx_temp1; //һֵ
reg [ 9:0] Gx_data;
reg [ 9:0] Gy_temp1; //һֵ
reg [ 9:0] Gy_temp2; //ֵ
reg [ 9:0] Gy_data;
reg [20:0] Gxy_square;
reg [ 8:0] ycbcr_vs_r;
reg [ 8:0] ycbcr_hs_r;
reg [ 8:0] ycbcr_de_r;
reg sobel_data_r;
wire matrix_vs;
wire matrix_hs;
wire matrix_de;
wire [ 7:0] matrix_p11;
wire [ 7:0] matrix_p12;
wire [ 7:0] matrix_p13;
wire [ 7:0] matrix_p21;
wire [ 7:0] matrix_p22;
wire [ 7:0] matrix_p23;
wire [ 7:0] matrix_p31;
wire [ 7:0] matrix_p32;
wire [ 7:0] matrix_p33;
assign sobel_vs = ycbcr_vs_r[8];
assign sobel_hs = ycbcr_hs_r[8];
assign sobel_de = ycbcr_de_r[8];
assign sobel_data = sobel_hs ? sobel_data_r : 1'b0;
assign sobel_data1 = sobel_data_r ? 24'hffffff : 24'h0;
Matrix_3X3_8 Matrixe_3X3_m0 (
.clk (clk), // input
.matrix_de (matrix_de), // output
.matrix_hs (matrix_hs), // output
.matrix_vs (matrix_vs), // output
.rst_n (rst_n), // input
.ycbcr_de (ycbcr_de), // input
.ycbcr_hs (ycbcr_hs), // input
.ycbcr_vs (ycbcr_vs), // input
.matrix_p11(matrix_p11), // output[7:0]
.matrix_p12(matrix_p12), // output[7:0]
.matrix_p13(matrix_p13), // output[7:0]
.matrix_p21(matrix_p21), // output[7:0]
.matrix_p22(matrix_p22), // output[7:0]
.matrix_p23(matrix_p23), // output[7:0]
.matrix_p31(matrix_p31), // output[7:0]
.matrix_p32(matrix_p32), // output[7:0]
.matrix_p33(matrix_p33), // output[7:0]
.ycbcr_y (ycbcr_y) // input[7:0]
);
//Gx -1 0 +1 Gy +1 +2 +1 P P11 P12 P13
// -2 0 +2 0 0 0 P21 P22 P23
// -1 0 +1 -1 -2 -1 P31 P32 P33
//
//|Gx| = |(P13+2*P23+P33)-(P11+2*P21+P31)|
//|Gy| = |(P11+2*P12+P13)-(P31+2*P32+P33)|
//|G| = |Gx|+ |Gy|
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
Gy_temp1 <= 10'd0;
Gy_temp2 <= 10'd0;
Gy_data <= 10'd0;
end else begin
Gy_temp1 <= matrix_p13 + (matrix_p23 << 1) + matrix_p33;
Gy_temp2 <= matrix_p11 + (matrix_p21 << 1) + matrix_p31;
Gy_data <= (Gy_temp1 >= Gy_temp2) ? Gy_temp1 - Gy_temp2 : (Gy_temp2 - Gy_temp1);
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
Gx_temp1 <= 10'd0;
Gx_temp2 <= 10'd0;
Gx_data <= 10'd0;
end else begin
Gx_temp1 <= matrix_p11 + (matrix_p12 << 1) + matrix_p13;
Gx_temp2 <= matrix_p31 + (matrix_p32 << 1) + matrix_p33;
Gx_data <= (Gx_temp1 >= Gx_temp2) ? Gx_temp1 - Gx_temp2 : (Gx_temp2 - Gx_temp1);
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) Gxy_square <= 21'd0;
else Gxy_square <= Gx_data * Gx_data + Gy_data * Gy_data;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) sobel_data_r <= 1'b0;
else if (Gxy_square >= threshold) sobel_data_r <= 1'b0;
else sobel_data_r <= 1'b1;
end
//ӳ9ͬ
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
ycbcr_vs_r <= 0;
ycbcr_hs_r <= 0;
ycbcr_de_r <= 0;
end else begin
ycbcr_vs_r <= {ycbcr_vs_r[7:0], matrix_vs};
ycbcr_hs_r <= {ycbcr_hs_r[7:0], matrix_hs};
ycbcr_de_r <= {ycbcr_de_r[7:0], matrix_de};
end
end
endmodule
| 6.980404 |
module Sobel_Threshold_Adj (
//global clock
input clk, //100MHz
input rst_n, //global reset
//user interface
input key_flag, //key down flag
input [3:0] key_value, //key control data
output reg [3:0] Sobel_Grade, //Sobel Grade output
output reg [7:0] Sobel_Threshold //lcd pwn signal, l:valid
);
//---------------------------------
//Sobel Threshold adjust with key.
always @(posedge clk or negedge rst_n) begin
if (!rst_n) Sobel_Grade <= 4'd8;
else if (key_flag) begin
case (key_value) //{Sobel_Threshold--, Sobel_Threshold++}
4'b0001: Sobel_Grade <= (Sobel_Grade == 4'd0) ? 4'd0 : Sobel_Grade - 1'b1;
4'b0010: Sobel_Grade <= (Sobel_Grade == 4'd15) ? 4'd15 : Sobel_Grade + 1'b1;
4'b0100: Sobel_Grade <= 4'd8;
4'b1000: Sobel_Grade <= 4'd8;
default: ;
endcase
end else Sobel_Grade <= Sobel_Grade;
end
//---------------------------------
//Sobel Grade Mapping with Sobel Threshold
always @(posedge clk or negedge rst_n) begin
if (!rst_n) Sobel_Threshold <= 35;
else
case (Sobel_Grade)
4'h0: Sobel_Threshold <= 20;
4'h1: Sobel_Threshold <= 25;
4'h2: Sobel_Threshold <= 30;
4'h3: Sobel_Threshold <= 35;
4'h5: Sobel_Threshold <= 40;
4'h6: Sobel_Threshold <= 45;
4'h7: Sobel_Threshold <= 50;
4'h8: Sobel_Threshold <= 100;
4'h9: Sobel_Threshold <= 60;
4'ha: Sobel_Threshold <= 65;
4'hb: Sobel_Threshold <= 70;
4'hc: Sobel_Threshold <= 75;
4'hd: Sobel_Threshold <= 80;
4'he: Sobel_Threshold <= 85;
4'hf: Sobel_Threshold <= 90;
default: ;
endcase
end
endmodule
| 7.53186 |
module sobel_top (
// sys
input wire vga_clk,
// key
input wire [10:0] iKey_value,
// input
input wire iVGA_de,
iVGA_hs,
iVGA_vs,
input wire [15:0] iRGB_565, // RGB565格式
// output
output wire oVGA_hs,
oVGA_vs,
oVGA_de,
output wire [15:0] oVGA_565
);
wire gray_de, gray_hsync, gray_vsync;
wire [7:0] gray_data;
wire sobel_hsync, sobel_vsync, sobel_de;
wire [15:0] sobel_data;
assign oVGA_565 = sobel_data ? 16'h0000 : 16'hffff;
assign oVGA_hs = sobel_hsync;
assign oVGA_vs = sobel_vsync;
assign oVGA_de = sobel_de;
YCbCr u_YCbCr (
// sys
.clk (vga_clk),
// input
.RGB_de (iVGA_de),
.RGB_hsync (iVGA_hs),
.RGB_vsync (iVGA_vs),
.RGB_data (iRGB_565),
// output
.gray_de (gray_de),
.gray_hsync(gray_hsync),
.gray_vsync(gray_vsync),
.gray_data (gray_data[7:0])
);
sobel_filtering u_sobel_filtering (
// sys
.clk (vga_clk),
// param
.key_value (iKey_value[10:0]),
// input
.Y_data (gray_data[7:0]),
.Y_de (gray_de),
.Y_hsync (gray_hsync),
.Y_vsync (gray_vsync),
// output
.sobel_hsync(sobel_hsync),
.sobel_vsync(sobel_vsync),
.sobel_de (sobel_de),
.sobel_data (sobel_data[15:0])
);
endmodule
| 7.441768 |
module Sobol (
input clk,
input rst_n,
input start,
output [12:0] icdf
);
// ========== wire and reg ===================
wire [31:0] res_int32;
// ========== Sequential =====================
// ========== module instantiation ===========
Sobol_to_INT32 sobol_to_int32_0 (
.clk (clk),
.rst_n(rst_n),
.start(start),
.res (res_int32)
);
ICDF_LUT icdf_lut0 (
.clk (clk),
.rst_n(rst_n),
.cdf (res_int32),
.icdf (icdf)
);
endmodule
| 6.558989 |
module socAhbApbBridge (
input HCLK,
input HRESETn, // active low reset
input [31:0] HADDR, // AHB Address
input [31:0] HWDATA, // write data from AHB Master
input HWRITE, // 1 = write, 0= read
input HSEL, // block select
input HREADY, // ready input from other AHB slaves
input [ 1:0] HTRANS, // transfer type
output HREADYOUT, // ready output to AHB Master
output [ 1:0] HRESP, // transfer response to AHB Master
output [31:0] HRDATA, // read data to AHB Master
input PCLK,
input PRESETn, // active low reset
output [31:0] PADDR, // APB Address
output PSEL, // APB Peripheral Select
output PENABLE, // APB Peripheral Enable
output PWRITE, // APB Write Strobe
output [31:0] PWDATA, // APB Write Data bus
input [31:0] PRDATA // APB Read Data bus... Requires a Mux external.
);
assign HRESP = `AHB_RESP_OKAY;
// reg [31:0] HRDATA;
reg HREADYOUT;
reg [31:0] PADDR;
reg [31:0] PWDATA;
reg PSEL;
reg PWRITE;
reg PENABLE;
// HRDATA = PRDATA; Just a pass through to make bridge IP-XACT work.
assign HRDATA = PRDATA;
// APB Bridge state machine:
parameter APB_IDLE = 0;
parameter APB_C1 = 1;
parameter APB_C2 = 2;
reg [1:0] apbState;
reg HSELdly;
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
apbState <= #1 APB_IDLE;
HREADYOUT <= #1 1'b1;
PENABLE <= #1 1'b0;
PADDR <= #1 32'd0;
PWDATA <= #1 32'd0;
PWRITE <= #1 1'b0;
PSEL <= #1 1'b0;
HSELdly <= #1 1'b0;
end else begin
HSELdly <= #1 HSEL;
case (apbState)
APB_IDLE: begin
PENABLE <= #1 1'b0;
HREADYOUT <= #1 1'b1;
if (HSEL & HTRANS[1] & HREADY) begin
HREADYOUT <= #1 1'b0; // assert one wait state
PADDR <= #1 HADDR; // register address & control when selected
PWRITE <= #1 HWRITE;
PSEL <= #1 1'b1;
apbState <= #1 APB_C1;
end
end
APB_C1: begin
HREADYOUT <= #1 1'b1;
PENABLE <= #1 1'b1;
apbState <= #1 APB_C2;
PWDATA <= #1 HWDATA; // register data
end
APB_C2: begin
PENABLE <= #1 1'b0;
PSEL <= #1 1'b0;
// handle case of back-to-back transfers
if (HSEL & HTRANS[1] & HREADY) begin
HREADYOUT <= #1 1'b0; // assert one wait state
PADDR <= #1 HADDR; // register address & control when selected
PWRITE <= #1 HWRITE;
PSEL <= #1 1'b1;
apbState <= #1 APB_C1;
end else apbState <= #1 APB_IDLE;
end
default: apbState <= #1 APB_IDLE;
endcase
end
end
endmodule
| 7.735282 |
module SoCBlackIce (
input wire clk,
input wire rx,
output wire tx,
output wire [3:0] status
);
assign status[3] = 0;
wire slowClock;
BlackIcePll pll (
.clock_in(clk),
.clock_out(slowClock),
.locked()
);
SoC #(
.clockRate(`BLACK_ICE_CLOCK_RATE)
) p0 (
.clk(slowClock),
.rx(rx),
.tx(tx),
.status(status[2:0])
);
endmodule
| 6.877513 |
module SoCIceStick (
input wire clk,
input wire rx,
output wire tx,
output wire status
);
SoC #(
.clockRate(`ICE_STICK_CLOCK_RATE)
) p0 (
.clk(clk),
.rx(rx),
.tx(tx),
.status(status)
);
endmodule
| 7.617993 |
module sockit_top (
input OSC_50_B8A,
inout AUD_ADCLRCK,
input AUD_ADCDAT,
inout AUD_DACLRCK,
output AUD_DACDAT,
output AUD_XCK,
inout AUD_BCLK,
output AUD_I2C_SCLK,
inout AUD_I2C_SDAT,
output AUD_MUTE,
input [3:0] KEY,
input [3:0] SW,
output [3:0] LED
);
wire reset = !KEY[0];
wire main_clk;
wire audio_clk;
wire [1:0] sample_end;
wire [1:0] sample_req;
wire [15:0] audio_output;
wire [15:0] audio_input;
clock_pll pll (
.refclk(OSC_50_B8A),
.rst(reset),
.outclk_0(audio_clk),
.outclk_1(main_clk)
);
i2c_av_config av_config (
.clk(main_clk),
.reset(reset),
.i2c_sclk(AUD_I2C_SCLK),
.i2c_sdat(AUD_I2C_SDAT),
.status(LED)
);
assign AUD_XCK = audio_clk;
assign AUD_MUTE = (SW != 4'b0);
audio_codec ac (
.clk(audio_clk),
.reset(reset),
.sample_end(sample_end),
.sample_req(sample_req),
.audio_output(audio_output),
.audio_input(audio_input),
.channel_sel(2'b10),
.AUD_ADCLRCK(AUD_ADCLRCK),
.AUD_ADCDAT(AUD_ADCDAT),
.AUD_DACLRCK(AUD_DACLRCK),
.AUD_DACDAT(AUD_DACDAT),
.AUD_BCLK(AUD_BCLK)
);
audio_effects ae (
.audio_clk(audio_clk),
.main_clk(main_clk),
.sample_end(sample_end[1]),
.sample_req(sample_req[1]),
.audio_output(audio_output),
.audio_input(audio_input),
.control(SW)
);
endmodule
| 6.874833 |
module WishboneDevice (
input io_wbSlaveTransmitter_ready,
output io_wbSlaveTransmitter_bits_ack,
output [31:0] io_wbSlaveTransmitter_bits_dat,
output io_wbSlaveTransmitter_bits_err,
output io_wbMasterReceiver_ready,
input io_wbMasterReceiver_valid,
input io_wbMasterReceiver_bits_cyc,
input io_wbMasterReceiver_bits_stb,
input io_wbMasterReceiver_bits_we,
input [31:0] io_wbMasterReceiver_bits_adr,
input [31:0] io_wbMasterReceiver_bits_dat,
input [ 3:0] io_wbMasterReceiver_bits_sel,
output io_reqOut_valid,
output [31:0] io_reqOut_bits_addrRequest,
output [31:0] io_reqOut_bits_dataRequest,
output [ 3:0] io_reqOut_bits_activeByteLane,
output io_reqOut_bits_isWrite,
input io_rspIn_valid,
input [31:0] io_rspIn_bits_dataResponse,
input io_rspIn_bits_error
);
wire _T_1 = io_wbMasterReceiver_valid & io_wbMasterReceiver_bits_cyc & io_wbMasterReceiver_bits_stb; // @[WishboneDevice.scala 16:80]
wire _T_4 = io_rspIn_valid & ~io_rspIn_bits_error; // @[WishboneDevice.scala 36:27]
wire _T_5 = io_rspIn_valid & io_rspIn_bits_error; // @[WishboneDevice.scala 42:34]
wire _GEN_5 = io_rspIn_valid & ~io_rspIn_bits_error ? 1'h0 : _T_5; // @[WishboneDevice.scala 36:52 WishboneDevice.scala 40:40]
wire _GEN_18 = ~io_wbMasterReceiver_bits_we ? _T_4 : _T_4; // @[WishboneDevice.scala 26:40]
wire _GEN_19 = ~io_wbMasterReceiver_bits_we ? _GEN_5 : _GEN_5; // @[WishboneDevice.scala 26:40]
assign io_wbSlaveTransmitter_bits_ack = _T_1 & _GEN_18; // @[WishboneDevice.scala 25:16 WishboneDevice.scala 88:9]
assign io_wbSlaveTransmitter_bits_dat = io_rspIn_bits_dataResponse; // @[WishboneDevice.scala 36:52 WishboneDevice.scala 41:40]
assign io_wbSlaveTransmitter_bits_err = _T_1 & _GEN_19; // @[WishboneDevice.scala 25:16 WishboneDevice.scala 89:36]
assign io_wbMasterReceiver_ready = 1'h1; // @[WishboneDevice.scala 19:29]
assign io_reqOut_valid = io_wbMasterReceiver_valid & io_wbMasterReceiver_bits_cyc & io_wbMasterReceiver_bits_stb; // @[WishboneDevice.scala 16:80]
assign io_reqOut_bits_addrRequest = io_wbMasterReceiver_bits_adr; // @[WishboneDevice.scala 26:40 WishboneDevice.scala 32:34 WishboneDevice.scala 56:34]
assign io_reqOut_bits_dataRequest = io_wbMasterReceiver_bits_dat; // @[WishboneDevice.scala 26:40 WishboneDevice.scala 57:34]
assign io_reqOut_bits_activeByteLane = io_wbMasterReceiver_bits_sel; // @[WishboneDevice.scala 26:40 WishboneDevice.scala 34:37 WishboneDevice.scala 58:37]
assign io_reqOut_bits_isWrite = ~io_wbMasterReceiver_bits_we ? 1'h0 : io_wbMasterReceiver_bits_we; // @[WishboneDevice.scala 26:40 WishboneDevice.scala 35:30 WishboneDevice.scala 59:30]
endmodule
| 7.169291 |
module SubRegExt (
input io_we,
input [31:0] io_wd,
input [31:0] io_d,
output io_qe,
output [31:0] io_q,
output [31:0] io_qs
);
assign io_qe = io_we; // @[SubRegExt.scala 25:9]
assign io_q = io_wd; // @[SubRegExt.scala 24:8]
assign io_qs = io_d; // @[SubRegExt.scala 23:9]
endmodule
| 6.577328 |
module SubRegExt_2 (
input io_we,
input [15:0] io_wd,
input [15:0] io_d,
output io_qe,
output [15:0] io_q,
output [15:0] io_qs
);
assign io_qe = io_we; // @[SubRegExt.scala 25:9]
assign io_q = io_wd; // @[SubRegExt.scala 24:8]
assign io_qs = io_d; // @[SubRegExt.scala 23:9]
endmodule
| 6.705049 |
module WishboneErr (
input clock,
input reset,
output [31:0] io_wbSlaveTransmitter_bits_dat,
output io_wbSlaveTransmitter_bits_err,
input io_wbMasterReceiver_valid,
input io_wbMasterReceiver_bits_cyc,
input io_wbMasterReceiver_bits_stb
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
reg [31:0] dataReg; // @[WishboneErr.scala 15:24]
reg errReg; // @[WishboneErr.scala 16:23]
wire _T_1 = io_wbMasterReceiver_valid & io_wbMasterReceiver_bits_cyc & io_wbMasterReceiver_bits_stb; // @[WishboneErr.scala 12:80]
assign io_wbSlaveTransmitter_bits_dat = dataReg; // @[WishboneErr.scala 44:34]
assign io_wbSlaveTransmitter_bits_err = errReg; // @[WishboneErr.scala 45:35]
always @(posedge clock) begin
if (reset) begin // @[WishboneErr.scala 15:24]
dataReg <= 32'h0; // @[WishboneErr.scala 15:24]
end else if (_T_1) begin // @[WishboneErr.scala 21:16]
dataReg <= 32'hffffffff;
end else begin
dataReg <= 32'h0; // @[WishboneErr.scala 37:13]
end
if (reset) begin // @[WishboneErr.scala 16:23]
errReg <= 1'h0; // @[WishboneErr.scala 16:23]
end else begin
errReg <= _T_1;
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
dataReg = _RAND_0[31:0];
_RAND_1 = {1{`RANDOM}};
errReg = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 7.966963 |
module InstructionFetch (
input [31:0] io_address,
output [31:0] io_instruction,
input io_coreInstrReq_ready,
output io_coreInstrReq_valid,
output [31:0] io_coreInstrReq_bits_addrRequest,
input io_coreInstrResp_valid,
input [31:0] io_coreInstrResp_bits_dataResponse
);
assign io_instruction = io_coreInstrResp_valid ? io_coreInstrResp_bits_dataResponse : 32'h0; // @[InstructionFetch.scala 26:24]
assign io_coreInstrReq_valid = io_coreInstrReq_ready; // @[InstructionFetch.scala 24:31]
assign io_coreInstrReq_bits_addrRequest = io_address; // @[InstructionFetch.scala 23:36]
endmodule
| 9.064394 |
module HazardUnit (
input io_id_ex_memRead,
input io_ex_mem_memRead,
input io_id_ex_branch,
input [4:0] io_id_ex_rd,
input [4:0] io_ex_mem_rd,
input [4:0] io_id_rs1,
input [4:0] io_id_rs2,
input io_taken,
input [1:0] io_jump,
input io_branch,
output io_if_reg_write,
output io_pc_write,
output io_ctl_mux,
output io_ifid_flush,
output io_take_branch
);
wire _T_3 = io_id_ex_rd == io_id_rs1 | io_id_ex_rd == io_id_rs2; // @[HazardUnit.scala 35:34]
wire _T_4 = (io_id_ex_memRead | io_branch) & _T_3; // @[HazardUnit.scala 34:37]
wire _T_5 = io_id_ex_rd != 5'h0; // @[HazardUnit.scala 36:21]
wire _T_10 = _T_5 & io_id_rs2 != 5'h0; // @[HazardUnit.scala 37:28]
wire _T_11 = io_id_ex_rd != 5'h0 & io_id_rs1 != 5'h0 | _T_10; // @[HazardUnit.scala 36:51]
wire _T_12 = _T_4 & _T_11; // @[HazardUnit.scala 35:65]
wire _T_13 = ~io_id_ex_branch; // @[HazardUnit.scala 38:7]
wire _T_14 = _T_12 & _T_13; // @[HazardUnit.scala 37:51]
wire _GEN_0 = _T_14 ? 1'h0 : 1'h1; // @[HazardUnit.scala 40:3 HazardUnit.scala 41:16 HazardUnit.scala 26:14]
assign io_if_reg_write = io_ex_mem_memRead & io_branch & (io_ex_mem_rd == io_id_rs1 | io_ex_mem_rd == io_id_rs2) ? 1'h0
: _GEN_0; // @[HazardUnit.scala 47:101 HazardUnit.scala 48:16]
assign io_pc_write = io_ex_mem_memRead & io_branch & (io_ex_mem_rd == io_id_rs1 | io_ex_mem_rd == io_id_rs2) ? 1'h0 :
_GEN_0; // @[HazardUnit.scala 47:101 HazardUnit.scala 48:16]
assign io_ctl_mux = io_ex_mem_memRead & io_branch & (io_ex_mem_rd == io_id_rs1 | io_ex_mem_rd == io_id_rs2) ? 1'h0 :
_GEN_0; // @[HazardUnit.scala 47:101 HazardUnit.scala 48:16]
assign io_ifid_flush = io_taken | io_jump != 2'h0; // @[HazardUnit.scala 55:17]
assign io_take_branch = io_ex_mem_memRead & io_branch & (io_ex_mem_rd == io_id_rs1 | io_ex_mem_rd == io_id_rs2) ? 1'h0
: _GEN_0; // @[HazardUnit.scala 47:101 HazardUnit.scala 48:16]
endmodule
| 8.02365 |
module BranchUnit (
input io_branch,
input [ 2:0] io_funct3,
input [31:0] io_rd1,
input [31:0] io_rd2,
input io_take_branch,
output io_taken
);
wire _T = 3'h0 == io_funct3; // @[Conditional.scala 37:30]
wire _T_2 = 3'h1 == io_funct3; // @[Conditional.scala 37:30]
wire _T_4 = 3'h4 == io_funct3; // @[Conditional.scala 37:30]
wire _T_8 = 3'h5 == io_funct3; // @[Conditional.scala 37:30]
wire _T_12 = 3'h6 == io_funct3; // @[Conditional.scala 37:30]
wire _T_15 = io_rd1 >= io_rd2; // @[BranchUnit.scala 28:32]
wire _GEN_1 = _T_12 ? io_rd1 < io_rd2 : _T_15; // @[Conditional.scala 39:67 BranchUnit.scala 27:21]
wire _GEN_2 = _T_8 ? $signed(
io_rd1
) >= $signed(
io_rd2
) : _GEN_1; // @[Conditional.scala 39:67 BranchUnit.scala 26:21]
wire _GEN_3 = _T_4 ? $signed(
io_rd1
) < $signed(
io_rd2
) : _GEN_2; // @[Conditional.scala 39:67 BranchUnit.scala 25:21]
wire _GEN_4 = _T_2 ? io_rd1 != io_rd2 : _GEN_3; // @[Conditional.scala 39:67 BranchUnit.scala 24:21]
wire check = _T ? io_rd1 == io_rd2 : _GEN_4; // @[Conditional.scala 40:58 BranchUnit.scala 23:21]
assign io_taken = check & io_branch & io_take_branch; // @[BranchUnit.scala 31:33]
endmodule
| 7.95714 |
module ALU (
input [31:0] io_input1,
input [31:0] io_input2,
input [ 3:0] io_aluCtl,
output [31:0] io_result
);
wire _T = io_aluCtl == 4'h0; // @[ALU.scala 17:18]
wire [31:0] _T_1 = io_input1 & io_input2; // @[ALU.scala 17:41]
wire _T_2 = io_aluCtl == 4'h1; // @[ALU.scala 18:18]
wire [31:0] _T_3 = io_input1 | io_input2; // @[ALU.scala 18:41]
wire _T_4 = io_aluCtl == 4'h2; // @[ALU.scala 19:18]
wire [31:0] _T_6 = io_input1 + io_input2; // @[ALU.scala 19:41]
wire _T_7 = io_aluCtl == 4'h3; // @[ALU.scala 20:18]
wire [31:0] _T_9 = io_input1 - io_input2; // @[ALU.scala 20:41]
wire _T_10 = io_aluCtl == 4'h4; // @[ALU.scala 21:18]
wire _T_13 = $signed(io_input1) < $signed(io_input2); // @[ALU.scala 21:48]
wire _T_14 = io_aluCtl == 4'h5; // @[ALU.scala 22:18]
wire _T_15 = io_input1 < io_input2; // @[ALU.scala 22:41]
wire _T_16 = io_aluCtl == 4'h6; // @[ALU.scala 23:18]
wire [62:0] _GEN_0 = {{31'd0}, io_input1}; // @[ALU.scala 23:41]
wire [62:0] _T_18 = _GEN_0 << io_input2[4:0]; // @[ALU.scala 23:41]
wire _T_19 = io_aluCtl == 4'h7; // @[ALU.scala 24:18]
wire [31:0] _T_21 = io_input1 >> io_input2[4:0]; // @[ALU.scala 24:41]
wire _T_22 = io_aluCtl == 4'h8; // @[ALU.scala 25:18]
wire [31:0] _T_26 = $signed(io_input1) >>> io_input2[4:0]; // @[ALU.scala 25:68]
wire _T_27 = io_aluCtl == 4'h9; // @[ALU.scala 26:18]
wire [31:0] _T_28 = io_input1 ^ io_input2; // @[ALU.scala 26:41]
wire [31:0] _T_29 = _T_27 ? _T_28 : 32'h0; // @[Mux.scala 98:16]
wire [31:0] _T_30 = _T_22 ? _T_26 : _T_29; // @[Mux.scala 98:16]
wire [31:0] _T_31 = _T_19 ? _T_21 : _T_30; // @[Mux.scala 98:16]
wire [62:0] _T_32 = _T_16 ? _T_18 : {{31'd0}, _T_31}; // @[Mux.scala 98:16]
wire [62:0] _T_33 = _T_14 ? {{62'd0}, _T_15} : _T_32; // @[Mux.scala 98:16]
wire [62:0] _T_34 = _T_10 ? {{62'd0}, _T_13} : _T_33; // @[Mux.scala 98:16]
wire [62:0] _T_35 = _T_7 ? {{31'd0}, _T_9} : _T_34; // @[Mux.scala 98:16]
wire [62:0] _T_36 = _T_4 ? {{31'd0}, _T_6} : _T_35; // @[Mux.scala 98:16]
wire [62:0] _T_37 = _T_2 ? {{31'd0}, _T_3} : _T_36; // @[Mux.scala 98:16]
wire [62:0] _T_38 = _T ? {{31'd0}, _T_1} : _T_37; // @[Mux.scala 98:16]
assign io_result = _T_38[31:0]; // @[ALU.scala 14:13]
endmodule
| 7.960621 |
module AluControl (
input [1:0] io_aluOp,
input io_f7,
input [2:0] io_f3,
input io_aluSrc,
output [3:0] io_out
);
wire _T_1 = 3'h0 == io_f3; // @[Conditional.scala 37:30]
wire _T_3 = ~io_f7; // @[AluControl.scala 38:34]
wire [1:0] _GEN_0 = ~io_aluSrc | ~io_f7 ? 2'h2 : 2'h3; // @[AluControl.scala 38:43 AluControl.scala 39:18 AluControl.scala 42:20]
wire _T_5 = 3'h1 == io_f3; // @[Conditional.scala 37:30]
wire _T_6 = 3'h2 == io_f3; // @[Conditional.scala 37:30]
wire _T_7 = 3'h3 == io_f3; // @[Conditional.scala 37:30]
wire _T_8 = 3'h5 == io_f3; // @[Conditional.scala 37:30]
wire [3:0] _GEN_1 = _T_3 ? 4'h7 : 4'h8; // @[AluControl.scala 55:29 AluControl.scala 56:18 AluControl.scala 58:18]
wire _T_10 = 3'h7 == io_f3; // @[Conditional.scala 37:30]
wire _T_11 = 3'h6 == io_f3; // @[Conditional.scala 37:30]
wire _T_12 = 3'h4 == io_f3; // @[Conditional.scala 37:30]
wire [3:0] _GEN_2 = _T_12 ? 4'h9 : 4'hf; // @[Conditional.scala 39:67 AluControl.scala 68:16 AluControl.scala 31:10]
wire [3:0] _GEN_3 = _T_11 ? 4'h1 : _GEN_2; // @[Conditional.scala 39:67 AluControl.scala 65:16]
wire [3:0] _GEN_4 = _T_10 ? 4'h0 : _GEN_3; // @[Conditional.scala 39:67 AluControl.scala 62:16]
wire [3:0] _GEN_5 = _T_8 ? _GEN_1 : _GEN_4; // @[Conditional.scala 39:67]
wire [3:0] _GEN_6 = _T_7 ? 4'h5 : _GEN_5; // @[Conditional.scala 39:67 AluControl.scala 52:16]
wire [3:0] _GEN_7 = _T_6 ? 4'h4 : _GEN_6; // @[Conditional.scala 39:67 AluControl.scala 49:16]
wire [3:0] _GEN_8 = _T_5 ? 4'h6 : _GEN_7; // @[Conditional.scala 39:67 AluControl.scala 46:16]
wire [3:0] _GEN_9 = _T_1 ? {{2'd0}, _GEN_0} : _GEN_8; // @[Conditional.scala 40:58]
assign io_out = io_aluOp == 2'h0 ? 4'h2 : _GEN_9; // @[AluControl.scala 33:26 AluControl.scala 34:12]
endmodule
| 8.611802 |
module MemoryFetch(
input clock,
input reset,
input [31:0] io_aluResultIn,
input [31:0] io_writeData,
input io_writeEnable,
input io_readEnable,
output [31:0] io_readData,
output io_stall,
output io_dccmReq_valid,
output [31:0] io_dccmReq_bits_addrRequest,
output [31:0] io_dccmReq_bits_dataRequest,
output io_dccmReq_bits_isWrite,
input io_dccmRsp_valid,
input [31:0] io_dccmRsp_bits_dataResponse
);
wire _T = io_writeEnable | io_readEnable; // @[MemoryFetch.scala 33:42]
wire _T_8 = io_writeEnable & io_aluResultIn[31:28] == 4'h8; // @[MemoryFetch.scala 42:23]
assign io_readData = io_dccmRsp_valid ? io_dccmRsp_bits_dataResponse : 32'h0; // @[MemoryFetch.scala 40:21]
assign io_stall = _T & ~io_dccmRsp_valid; // @[MemoryFetch.scala 35:49]
assign io_dccmReq_valid = io_writeEnable | io_readEnable; // @[MemoryFetch.scala 33:42]
assign io_dccmReq_bits_addrRequest = io_aluResultIn; // @[MemoryFetch.scala 31:31]
assign io_dccmReq_bits_dataRequest = io_writeData; // @[MemoryFetch.scala 30:31]
assign io_dccmReq_bits_isWrite = io_writeEnable; // @[MemoryFetch.scala 32:27]
always @(posedge clock) begin
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_8 & ~reset) begin
$fwrite(32'h80000002,"%x\n",io_writeData); // @[MemoryFetch.scala 43:11]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
| 7.030255 |
module PC (
input clock,
input reset,
input [31:0] io_in,
input io_halt,
output [31:0] io_out,
output [31:0] io_pc4
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [31:0] pc_reg; // @[PC.scala 12:23]
wire [31:0] _T_2 = $signed(pc_reg) + 32'sh4; // @[PC.scala 15:41]
assign io_out = pc_reg; // @[PC.scala 14:10]
assign io_pc4 = io_halt ? $signed(pc_reg) : $signed(_T_2); // @[PC.scala 15:16]
always @(posedge clock) begin
if (reset) begin // @[PC.scala 12:23]
pc_reg <= -32'sh4; // @[PC.scala 12:23]
end else begin
pc_reg <= io_in; // @[PC.scala 13:10]
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
pc_reg = _RAND_0[31:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 7.578567 |
module c2soc(input sys_clk_in,
/*****************************/
`include "socsignals.v"
/*****************************/
`ifdef SIMULATION
output FINISH,
`endif
input sys_reset);
wire clk;
wire rst;
// socmodule.v must define how clk is derived from sys_clk_in
// and how rst depends on sys_reset;
wire [31:0] ram_data_in_a;
wire [31:0] ram_addr_in_a;
wire [31:0] ram_data_in_b;
wire [31:0] ram_addr_in_b;
wire [31:0] ram_data_out_b;
wire ram_we_out;
`include "socmodules.v"
cpu cpu1(.clk(clk),
.rst(rst),
.ram_data_in_a(ram_data_in_a),
.ram_addr_in_a(ram_addr_in_a),
.ram_data_in_b(ram_data_in_b),
.ram_addr_in_b(ram_addr_in_b),
.ram_data_out_b(ram_data_out_b),
.ram_we_out(ram_we_out),
/****************************/
`include "soccpusignalsin.v"
/****************************/
.stall_cpu(0)
);
// Memory-mapped devices:
// Each device is responsible for checking if the address is within its range,
// and asserting the strobe if it owns the output / consumed the input
//
// A single WE signal is passed to all devices, they must only process it if the address is
// within their own range.
//
// Note that port A is connected directly - we do not want to fetch instructions from anything but RAM
wire [31:0] data_bus_in_ram;
wire data_bus_strobe_ram;
socram ram1(.clk(clk),
.rst(rst),
.data_a(ram_data_in_a),
.addr_a(ram_addr_in_a),
.data_b(data_bus_in_ram),
.addr_b(ram_addr_in_b),
.strobe_b(data_bus_strobe_ram),
.data_b_in(ram_data_out_b),
.data_b_we(ram_we_out)
);
`ifdef SIMULATION
debugprinter dbg1 (.clk(clk),
.addr_b(ram_addr_in_b),
.data_b_in(ram_data_out_b),
.data_b_we(ram_we_out));
halt halt11 (.clk(clk),
.rst(rst),
.addr_b(ram_addr_in_b),
.data_b_in(ram_data_out_b),
.data_b_we(ram_we_out),
.FINISH(FINISH));
wire [31:0] data_bus_in_cntr;
wire data_bus_strobe_cntr;
`endif
clockcounter cnt1
(.clk(clk),
.rst(rst),
.data_a(ram_data_in_a),
.addr_a(ram_addr_in_a),
.data_b(data_bus_in_cntr),
.addr_b(ram_addr_in_b),
.strobe_b(data_bus_strobe_cntr),
.data_b_in(ram_data_out_b),
.data_b_we(ram_we_out)
);
// ... and so on - ROMs, VGA, ethernet, whatever - including the hoisted user-defined modules
assign ram_data_in_b =
data_bus_strobe_ram?data_bus_in_ram:
data_bus_strobe_cntr?data_bus_in_cntr:
`include "socdata.v"
0;
endmodule
| 7.096001 |
module halt (
input clk,
input rst,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we,
output reg FINISH
);
always @(posedge clk)
if (~rst) FINISH <= 0;
else begin
if (addr_b == 65541) FINISH <= 1;
end
endmodule
| 7.332862 |
module clockcounter (
input clk,
input rst,
input [31:0] data_a,
input [31:0] addr_a,
output reg [31:0] data_b,
output reg strobe_b,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we
);
reg [31:0] counter;
always @(posedge clk)
if (~rst) begin
counter <= 0;
strobe_b <= 0;
data_b <= 0;
end else begin
counter <= counter + 1;
if (data_b_we & (addr_b == 65542)) $display(">> Clock cycles: %d", counter);
if (addr_b == 65542) begin
strobe_b <= 1;
data_b <= counter;
end else strobe_b <= 0;
end
endmodule
| 6.814175 |
module clockcounter (
input clk,
input rst,
output [31:0] data_a,
input [31:0] addr_a,
output [31:0] data_b,
output strobe_b,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we
);
reg [31:0] counter;
assign strobe_b = (addr_b == 65542);
assign data_b = counter;
always @(posedge clk)
if (~rst) begin
counter <= 0;
end else begin
counter <= counter + 1;
if (data_b_we & (addr_b == 65542)) $display(">> Clock cycles: %d", counter);
end
endmodule
| 6.814175 |
module fpga_gf2m
#(
parameter DIGITAL = 8,
parameter DATA_WIDTH = 163
)(
input clk, // Clock
input rst, // Asynchronous reset active low
input wire start,
input wire [DATA_WIDTH - 1 : 0] a,
input wire [DATA_WIDTH - 1 : 0] g,
input wire [BWIDTH - 1:0] b,
output reg [DATA_WIDTH - 1 : 0] t_i_j,
output reg done
);
parameter ITERATION_NUMBER = DATA_WIDTH / DIGITAL;
parameter BWIDTH = (ITERATION_NUMBER + 1)*DIGITAL;
parameter IDLE = 2'b00;
parameter CAL = 2'b01;
parameter DONE = 2'b10;
reg state;
reg [12:0] counter;
reg [DATA_WIDTH - 1 : 0] reg_a;
reg [DATA_WIDTH - 1 : 0] reg_g;
reg [BWIDTH - 1:0] reg_b;
reg [DIGITAL - 1:0] b_in;
wire [DATA_WIDTH - 1 : 0] out_t_i_j;
wire wire_done;
gf2m fpgainst(
.rst(rst),
.clk(clk),
.start(start),
.a(reg_a),
.g(reg_g),
.b(b_in),
.t_i_j(out_t_i_j),
.done(wire_done)
);
// done
always @(posedge clk or negedge rst) begin : proc_done
if(~rst) begin
done <= 0;
end else begin
case (wire_done)
1'b0: done <= done;
1'b1: done <= 1'b1;
default : done <= done;
endcase
end
end
always @(posedge clk or negedge rst) begin : proc_t_i_j
if(~rst) begin
t_i_j <= 0;
end else begin
case (wire_done)
1'b0: t_i_j <= t_i_j;
1'b1: t_i_j <= out_t_i_j;
default : t_i_j <= t_i_j;
endcase
end
end
// counter
always @(posedge clk or negedge rst) begin : proc_counter
if(~rst) begin
counter <= 0;
end else begin
case (state)
IDLE: begin
counter <= 12'd0;
end
CAL: begin
if(counter < ITERATION_NUMBER)
counter <= counter + 1；
else
counter <= 12'd0;
end
default : counter <= 12'd0;
endcase
end
end
// reg_b_in
assign b_in = reg_b[(ITERATION_NUMBER + 1 - counter)*DIGITAL - 1 : (ITERATION_NUMBER - counter)*DIGITAL];
// reg_a
always @(posedge clk or negedge rst) begin : reg_a
if(~rst) begin
reg_a <= 0;
end else begin
case (state)
IDLE: begin
if(start)
reg_a <= a;
else
reg_a <= 0;
end
default : reg_a <= reg_a;
endcase
end
end
// reg_b
always @(posedge clk or negedge rst) begin : reg_b
if(~rst) begin
reg_b <= 0;
end else begin
case (state)
IDLE: begin
if(start)
reg_b <= b;
else
reg_b <= 0;
end
default : reg_b <= reg_b;
endcase
end
end
// reg_g
always @(posedge clk or negedge rst) begin : proc_reg_g
if(~rst) begin
reg_g <= 0;
end else begin
case (state)
IDLE: begin
if(start)
reg_g <= g;
else
reg_g <= 0;
end
default : reg_g <= reg_g;
endcase
end
end
always @(posedge clk or negedge rst) begin : proc_state_machine
if(~rst) begin
state <= IDLE;
end else begin
case (state)
IDLE: begin
if(start) begin
state <= CAL;
end
else begin
state <= state;
end
end
CAL: begin
if (counter < ITERATION_NUMBER)
state <= CAL
else
state <= DONE
end
DONE: begin
state <= DONE
end
default : state <= IDLE;
endcase
end
end
endmodule
| 7.172496 |
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