code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module termination_fsm (
clk,
rst,
pout,
finished
);
input clk;
input rst;
input [7:0] pout;
output finished;
reg [1:0] state;
localparam STATE_INIT = 2'd0;
localparam STATE_DE_FOUND = 2'd1;
localparam STATE_AD_FOUND = 2'd2;
localparam STATE_00_FOUND = 2'd3;
assign finished = (stat... | 6.955898 |
module axi4_arb_onehot4 (
// Inputs
input clk_i
, input rst_i
, input hold_i
, input [3:0] request_i
// Outputs
, output [3:0] grant_o
);
//-----------------------------------------------------------------
// Registers / Wires
//----------------------------------... | 6.693687 |
modules
//-----------------------------------------------------------------
module axi4retime_fifo2x37
(
// Inputs
input clk_i
,input rst_i
,input [ 36:0] data_in_i
,input push_i
,input pop_i
// Outputs
,output [ 36:0] data_out_o
,output ... | 7.831093 |
module soc (
clk_clk,
export_size_new_signal,
export_start_new_signal,
reset_reset_n,
sdram_clk_clk,
sdram_wire_addr,
sdram_wire_ba,
sdram_wire_cas_n,
sdram_wire_cke,
sdram_wire_cs_n,
sdram_wire_dq,
sdram_wire_dqm,
sdram_wire_ras_n,
sdram_wire_we_n
);
input clk... | 6.848324 |
module soc_bram #(
parameter integer AW = 8,
parameter INIT_FILE = ""
) (
input wire [AW-1:0] addr,
output reg [ 31:0] rdata,
input wire [ 31:0] wdata,
input wire [ 3:0] wmsk,
input wire we,
input wire clk
);
reg [31:0] mem[0:(1<<AW)-1];
initial if (INIT... | 6.785906 |
module soc_config #(
parameter BITS = 32
) (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
input user_clock2,
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
i... | 7.847951 |
module soc_event_arbiter (
clk_i,
rstn_i,
req_i,
grant_o,
grant_ack_i,
anyGrant_o
);
parameter EVNT_NUM = 256;
input wire clk_i;
input wire rstn_i;
input wire [EVNT_NUM - 1:0] req_i;
output wire [EVNT_NUM - 1:0] grant_o;
input wire grant_ack_i;
output wire anyGrant_o;
localparam ... | 6.772068 |
module soc_fpga_ram (
PortAClk,
PortAAddr,
PortADataIn,
PortAWriteEnable,
PortADataOut
);
parameter DATAWIDTH = 2;
parameter ADDRWIDTH = 2;
input PortAClk;
input [(ADDRWIDTH-1):0] PortAAddr;
input [(DATAWIDTH-1):0] PortADataIn;
input PortAWriteEnable;
output [(DATAWIDTH-1):0] PortA... | 7.332224 |
module HelloWorld_Top (
input rstn_i,
input rxd_i,
output txd_o,
inout [7:0] led_o,
output led_ctl_o,
output debug_o
);
GSR GSR_INST (.GSR(rstn_i));
wire sys_clk /*synthesis syn_keep = 1*/;
OSCH #(
.NOM_FREQ("38.00")
) OSCH_inst (
.STDBY(1'b0),
.OSC(sys_clk),
.... | 6.563951 |
module soc_mem_bank_1 (
input [31:0] mem_data_i,
output [31:0] mem_data_o,
input [31:0] mem_addr_i,
input [ 3:0] mem_sel_i,
input mem_we_i,
input mem_cyc_i,
input mem_stb_i,
output mem_ack_o,
output mem_err_o,
output mem_rty_o,
... | 7.232487 |
module soc_mem_bank_2 (
input [31:0] mem_data_i,
output [31:0] mem_data_o,
input [31:0] mem_addr_i,
input [ 3:0] mem_sel_i,
input mem_we_i,
input mem_cyc_i,
input mem_stb_i,
output mem_ack_o,
output mem_err_o,
output mem_rty_o,
... | 7.232487 |
module soc_mem_bank_3 (
input [31:0] mem_data_i,
output [31:0] mem_data_o,
input [31:0] mem_addr_i,
input [ 3:0] mem_sel_i,
input mem_we_i,
input mem_cyc_i,
input mem_stb_i,
output mem_ack_o,
output mem_err_o,
output mem_rty_o,
... | 7.232487 |
module soc_peripherals (
input [31:0] peri_data_i,
output [31:0] peri_data_o,
input [31:0] peri_addr_i,
input [ 3:0] peri_sel_i,
input peri_we_i,
input peri_cyc_i,
input peri_stb_i,
output peri_ack_o,
output peri_err_o,
output peri_... | 6.720925 |
module soc_picorv32_base #(
parameter integer WB_N = 6,
parameter integer WB_DW = 32,
parameter integer WB_AW = 16,
parameter integer SPRAM_AW = 14, /* 14 => 64k, 15 => 128k */
/* auto */
parameter integer WB_MW = WB_DW / 8,
parameter integer WB_RW = WB_DW * WB_N,
parameter integer WB_... | 6.892519 |
module soc_ram (
data,
addr,
we,
clk,
q
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 6;
parameter MEM_INIT = 0;
input [(DATA_WIDTH-1):0] data;
input [(ADDR_WIDTH-1):0] addr;
input we;
input clk;
output [(DATA_WIDTH-1):0] q;
// Declare the RAM variable
reg [DATA_WIDTH-1:... | 7.389656 |
module soc_registers (
input [31:0] reg_data_i,
output [31:0] reg_data_o,
input [31:0] reg_addr_i,
input [ 3:0] reg_sel_i,
input reg_we_i,
input reg_cyc_i,
input reg_stb_i,
output reg_ack_o,
output reg_err_o,
output reg_rty_o,
... | 7.149461 |
module soc_spram #(
parameter integer AW = 14
) (
input wire [AW-1:0] addr,
output wire [ 31:0] rdata,
input wire [ 31:0] wdata,
input wire [ 3:0] wmsk,
input wire we,
input wire clk
);
wire [7:0] msk_nibble = {wmsk[3], wmsk[3], wmsk[2], wmsk[2], wmsk[1], wmsk[1... | 8.106937 |
module soc_system_avalon_st_adapter_data_format_adapter_0 (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [23:0] in_data,
input in_startofpacket,... | 7.482476 |
module soc_system_avalon_st_adapter_timing_adapter_0 (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [23:0] in_data,
input in_startofpacket,
... | 7.482476 |
module soc_system_avalon_st_adapter_timing_adapter_0_fifo (
output reg [3:0] fill_level,
// Interface: clock
input clk,
input reset_n,
// Interface: data_in
output reg in_ready,
input in_valid,
input [25:0] in_data,
// Interface: data_... | 7.482476 |
module soc_system (
avalon_interface_to_smart_meter_fsms_0_interface_to_fsm_data_neg_in,
avalon_interface_to_smart_meter_fsms_0_interface_to_fsm_data_neg_out,
avalon_interface_to_smart_meter_fsms_0_interface_to_fsm_data_pos_in,
avalon_interface_to_smart_meter_fsms_0_interface_to_fsm_data_pos_out,
av... | 6.582601 |
module soc_system_com_mem (
// inputs:
address,
address2,
byteenable,
byteenable2,
chipselect,
chipselect2,
... | 6.744149 |
module soc_system_ddr3_emif_0_p0_acv_ldc (
pll_hr_clk,
pll_dq_clk,
pll_dqs_clk,
dll_phy_delayctrl,
afi_clk,
avl_clk,
adc_clk,
adc_clk_cps,
hr_clk
);
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter ADC_PHASE_SETTING = 0;
parameter ADC_INVERT_PHASE = "false";
parameter IS_HHP_HP... | 6.65294 |
module soc_system_ddr3_emif_0_p0_clock_pair_generator (
datain,
dataout,
dataout_b
) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_o... | 6.65294 |
module soc_system_ddr3_emif_0_p0_generic_ddio (
datain,
halfratebypass,
dataout,
clk_hr,
clk_fr
);
parameter WIDTH = 1;
localparam DATA_IN_WIDTH = 4 * WIDTH;
localparam DATA_OUT_WIDTH = WIDTH;
input [DATA_IN_WIDTH-1:0] datain;
input halfratebypass;
input [WIDTH-1:0] clk_hr;
input [WI... | 6.65294 |
module soc_system_ddr3_emif_0_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe(probe_input),
.source()
// synopsys translate_off
, .clrn(),
.ena(),
.ir_in(),
.ir_... | 6.65294 |
module soc_system_ddr3_emif_0_p0_reset (
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_e... | 6.65294 |
module soc_system_ddr3_emif_0_p0_reset_sync (
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
... | 6.65294 |
module soc_system_dipsw_pio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
);
output irq;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input [3:0] in_port;
input reset_n;
in... | 6.761748 |
module soc_system_low_power_pio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input in_port;
input reset_n;
input write_n;
input [31:... | 6.976668 |
module soc_system_SRAM (
// inputs:
address,
address2,
byteenable,
byteenable2,
chipselect,
chipselect2,
clk,
... | 6.500704 |
module soc_system_tc_mem (
// inputs:
address,
address2,
byteenable,
byteenable2,
chipselect,
chipselect2,
... | 6.810307 |
module RegFile ( // @[:@464.2]
input clock, // @[:@465.4]
input [ 4:0] io_raddr_1, // @[:@467.4]
input [ 4:0] io_raddr_2, // @[:@467.4]
output [31:0] io_rdata_1, // @[:@467.4]
output [31:0] io_rdata_2, // @[:@467.4]
input io_wen, // @[:@467.4]
input [ 4:0] ... | 6.637965 |
module Branch ( // @[:@712.2]
input [31:0] io_in_a, // @[:@715.4]
input [31:0] io_in_b, // @[:@715.4]
input [ 2:0] io_br_type, // @[:@715.4]
output io_br_taken // @[:@715.4]
);
wire [32:0] _T_13; // @[branch.scala 24:33:@717.4]
wire [32:0] _T_14; // @[branch.scala 24:33:@718.4... | 7.283413 |
module DMem_Interface ( // @[:@1967.2]
input clock, // @[:@1968.4]
input reset, // @[:@1969.4]
input [15:0] io_wbs_m2s_addr, // @[:@1970.4]
input [31:0] io_wbs_m2s_data, // @[:@1970.4]
input io_wbs_m2s_we, // @[:@1970.4]
input [ 3:0] io_wbs_... | 6.797058 |
module soc_usb #(
parameter integer DW = 32
) (
// USB
inout wire usb_dp,
inout wire usb_dn,
output wire usb_pu,
// Wishbone slave
input wire [ 11:0] wb_addr,
output wire [DW-1:0] wb_rdata,
input wire [DW-1:0] wb_wdata,
input wire wb_we,
input wire [ 1:0] w... | 6.65512 |
module uart_flip (
input in_txd,
output in_rxd,
output out_txd,
input out_rxd
);
assign out_txd = in_txd;
assign in_rxd = out_rxd;
endmodule
| 9.0395 |
module soc_zedboard_top (
VGA_blue,
VGA_clk,
VGA_de,
VGA_green,
VGA_hsync,
VGA_red,
VGA_vsync
);
output [3:0] VGA_blue;
output VGA_clk;
output VGA_de;
output [3:0] VGA_green;
output VGA_hsync;
output [3:0] VGA_red;
output VGA_vsync;
wire [3:0] VGA_blue;
wire VGA_clk;
wir... | 7.028835 |
module sofa_plus_io (
input SOC_IN, // Input to drive the inpad signal
output SOC_OUT, // Output the outpad signal
output SOC_DIR, // Output the directionality
output FPGA_IN, // Input data to FPGA
input FPGA_OUT, // Output data from FPGA
input FPGA_DIR, // direction control
in... | 6.625884 |
module SOFController (
HCTxPortCntl,
HCTxPortData,
HCTxPortGnt,
HCTxPortRdy,
HCTxPortReq,
HCTxPortWEn,
SOFEnable,
SOFTimerClr,
SOFTimer,
clk,
rst
);
input HCTxPortGnt;
input HCTxPortRdy;
input SOFEnable;
input SOFTimerClr;
input clk;
input rst;
output [7:0] HCTx... | 8.563811 |
module SOFController_simlib (
HCTxPortCntl,
HCTxPortData,
HCTxPortGnt,
HCTxPortRdy,
HCTxPortReq,
HCTxPortWEn,
SOFEnable,
SOFTimerClr,
SOFTimer,
clk,
rst
);
input HCTxPortGnt;
input HCTxPortRdy;
input SOFEnable;
input SOFTimerClr;
input clk;
input rst;
output [7:... | 8.563811 |
module SOFT (
input [11:0] code_address,
output reg [15:0] instruction
);
always @(code_address) begin
case (code_address)
12'b000000000000: instruction <= 16'b1101001000000100;
12'b000000000001: instruction <= 16'b0010001000000011;
12'b000000000010: instruction <= 16'b1100001000000000;
... | 8.260603 |
module softcore_top (
clk_clk,
reset_reset_n,
pio_export
);
input clk_clk;
input reset_reset_n;
output [7:0] pio_export;
endmodule
| 7.00222 |
module softcore_top_jtag_uart_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr... | 7.320375 |
module softcore_top_jtag_uart_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_cl... | 7.320375 |
module softcore_top_jtag_uart_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
re... | 7.320375 |
module softcore_top_jtag_uart_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
... | 7.320375 |
module softcore_top_nios2_gen2_0_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
... | 7.320375 |
module softcore_top_nios2_gen2_0_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
... | 7.320375 |
module softcore_top_nios2_gen2_0_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux... | 7.320375 |
module softcore_top_nios2_gen2_0_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [17:... | 7.320375 |
module softcore_top_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
);
output [1:0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_input_tm_cnt;
wire [2:0] ... | 7.320375 |
module softcore_top_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
);
output [3:0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [3:0] fifo_wrptr_inc;
always @(ge2_free or ge3_fre... | 7.320375 |
module softcore_top_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
);
output [4:0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [4:0] fifo_cnt_inc;
always @(e... | 7.320375 |
module softcore_top_nios2_gen2_0_cpu_nios2_oci_pib (
// outputs:
tr_data
);
output [35:0] tr_data;
wire [35:0] tr_data;
assign tr_data = 0;
endmodule
| 7.320375 |
module softcore_top_nios2_gen2_0_cpu_nios2_oci_im (
// inputs:
clk,
jrst_n,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
);
output tracemem_on;
output [35:0] tracemem_trcdata;
output tracemem_tw;
... | 7.320375 |
module softcore_top_nios2_gen2_0_cpu_nios2_performance_monitors;
endmodule
| 7.320375 |
module softcore_top_nios2_gen2_0_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
... | 7.320375 |
module softcore_top_nios2_gen2_0_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input [7:0] address;
input [3:0] byteenable;
input clock;
input [31:0] data;
in... | 7.320375 |
module softcore_top_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "softcore_top_onchip_memory2_0.hex";
output [31:0] readdata;
input [13:0]... | 7.320375 |
module softcore_top_pio_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [7:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [... | 7.320375 |
module softcore_top_tb ();
wire softcore_top_inst_clk_bfm_clk_clk; // softcore_top_inst_clk_bfm:clk -> [softcore_top_inst:clk_clk, softcore_top_inst_reset_bfm:clk]
wire softcore_top_inst_reset_bfm_reset_reset; // softcore_top_inst_reset_bfm:reset -> softcore_top_inst:reset_reset_n
softcore_top softc... | 7.320375 |
module
module softmax(input clk, input [15:0] data_in [1024], output reg [15:0] data_out [1024]);
// Define the number of DSP slices to use for the softmax operation
parameter num_dsp_slices = 8;
// Define the storage registers for the softmax operation
reg [15:0] softmax_output [1024];
// Define the DSP s... | 7.880853 |
module softmax_invert_tadEe_rom (
addr0,
ce0,
q0,
addr1,
ce1,
q1,
addr2,
ce2,
q2,
addr3,
ce3,
q3,
addr4,
ce4,
q4,
clk
);
parameter DWIDTH = 15;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
output reg ... | 6.759082 |
module softmax_invert_tadEe (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1,
address2,
ce2,
q2,
address3,
ce3,
q3,
address4,
ce4,
q4
);
parameter DataWidth = 32'd15;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input ... | 6.759082 |
module softmax_invert_tafYi_rom (
addr0,
ce0,
q0,
addr1,
ce1,
q1,
addr2,
ce2,
q2,
addr3,
ce3,
q3,
addr4,
ce4,
q4,
clk
);
parameter DWIDTH = 15;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
output reg ... | 6.759082 |
module softmax_invert_tafYi (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1,
address2,
ce2,
q2,
address3,
ce3,
q3,
address4,
ce4,
q4
);
parameter DataWidth = 32'd15;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input ... | 6.759082 |
module softmax_latency_ap_fixed_ap_fixed_softmax_config13_s_exp_bkb_rom (
addr0,
ce0,
q0,
addr1,
ce1,
q1,
addr2,
ce2,
q2,
addr3,
ce3,
q3,
addr4,
ce4,
q4,
clk
);
parameter DWIDTH = 18;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDT... | 7.116033 |
module softmax_latency_ap_fixed_ap_fixed_softmax_config13_s_exp_bkb (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1,
address2,
ce2,
q2,
address3,
ce3,
q3,
address4,
ce4,
q4
);
parameter DataWidth = 32'd18;
parameter AddressRange = 32'd1024;
p... | 7.116033 |
module softmax_latency_ap_fixed_ap_fixed_softmax_config13_s_invecud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 14;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
... | 7.116033 |
module softmax_latency_ap_fixed_ap_fixed_softmax_config13_s_invecud (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd14;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [Da... | 7.116033 |
module softmax_latency_array_array_ap_fixed_5u_softmax_config9_sbkb_rom (
addr0,
ce0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 18;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;... | 7.116033 |
module softmax_latency_array_array_ap_fixed_5u_softmax_config9_sbkb (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd18;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] addr... | 7.116033 |
module softmax_latency_array_array_ap_fixed_5u_softmax_config9_scud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 14;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
... | 7.116033 |
module softmax_latency_array_array_ap_fixed_5u_softmax_config9_scud (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd14;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [Da... | 7.116033 |
module softmax_latency_array_array_softmax_config11_s_exp_table_rom (
addr0,
ce0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 18;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
i... | 7.116033 |
module softmax_latency_array_array_softmax_config11_s_exp_table (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd18;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0... | 7.116033 |
module softmax_latency_array_array_softmax_config11_s_invert_tabbkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 14;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
... | 7.116033 |
module softmax_latency_array_array_softmax_config11_s_invert_tabbkb (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd14;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [Da... | 7.116033 |
module softmax_latency_array_array_softmax_config5_s_exp_table_rom (
addr0,
ce0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 18;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
in... | 7.116033 |
module softmax_latency_array_array_softmax_config5_s_exp_table (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd18;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0;... | 7.116033 |
module softmax_latency_array_array_softmax_config5_s_invert_table3_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 14;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
i... | 7.116033 |
module softmax_latency_array_array_softmax_config5_s_invert_table3 (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd14;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [Dat... | 7.116033 |
module softMC_pcie_app #(
parameter C_PCI_DATA_WIDTH = 9'd32,
DQ_WIDTH = 64
) (
input clk,
input rst,
output CHNL_RX_CLK,
input CHNL_RX,
output reg CHNL_RX_ACK,
input CHNL_RX_LAST,
input [31:0] CHNL_RX_LEN,
input [30:0] CHNL_RX_OFF,
input [C_PCI_DATA_WIDTH-1:0] CHNL_RX_DATA,
... | 8.427519 |
module softrisc_top (
input clk,
input btnC,
input btnU,
input btnD,
input btnR,
input btnL,
input [15:0] sw,
output [6:0] seg,
output dp,
output [3:0] an,
output [15:0] led
);
wire rst;
wire clk_1;
reg [31:0] addr_in, data_in;
reg [1:0] cmd;
wire [7:0] dataA, dataB... | 7.069906 |
module softusb_dpram #(
parameter depth = 11, /* < log2 of the capacity in words */
parameter width = 32,
parameter initfile = ""
) (
input clk,
input clk2,
input [depth-1:0] a,
input we,
input [width-1:0] di,
output reg [width-1:0] do,
input ce2,
input [depth-1:0] a2,
input we2,
input [width-1:0] di2,
... | 7.528927 |
module softusb_filter (
input usb_clk,
input rcv,
input vp,
input vm,
output reg rcv_s,
output reg vp_s,
output reg vm_s
);
reg rcv_s0;
reg vp_s0;
reg vm_s0;
reg rcv_s1;
reg vp_s1;
reg vm_s1;
/* synchronizer */
always @(posedge usb_clk) begin
rcv_s0 <= rcv;
vp_s0 ... | 6.778026 |
module softusb_hostif #(
parameter csr_addr = 4'h0
) (
input sys_clk,
input sys_rst,
input usb_clk,
output reg usb_rst,
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
output irq,
input io_we,
input [5:0] io_a
);
wire csr_selected =... | 7.072219 |
module softusb_phy (
input usb_clk,
input usb_rst,
output usba_spd,
output usba_oe_n,
input usba_rcv,
inout usba_vp,
inout usba_vm,
output usbb_spd,
output usbb_oe_n,
input usbb_rcv,
inout usbb_vp,
inout usbb_vm,
output usba_discon,
output usbb_discon,
... | 7.030247 |
module softusb_ram #(
parameter pmem_width = 11,
parameter dmem_width = 13
) (
input sys_clk,
input sys_rst,
input usb_clk,
input usb_rst,
input [31:0] wb_adr_i,
output [31:0] wb_dat_o,
input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output reg wb_ack_o,
input wb_we_i,
inp... | 7.524306 |
module softusb_sie (
input usb_clk,
input usb_rst,
input io_re,
input io_we,
input [5:0] io_a,
input [7:0] io_di,
output reg [7:0] io_do,
output usba_spd,
output usba_oe_n,
input usba_rcv,
inout usba_vp,
inout usba_vm,
output usbb_spd,
output usbb_oe_n,
... | 7.672188 |
module softusb #(
parameter csr_addr = 4'h0,
parameter pmem_width = 11,
parameter dmem_width = 13
) (
input sys_clk,
input sys_rst,
input usb_clk,
/* CSR interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
output irq,
/* WIS... | 7.827436 |
module softusb_dpram #(
parameter depth = 11, /* < log2 of the capacity in words */
parameter width = 32,
parameter initfile = ""
) (
input clk,
input clk2,
input [depth-1:0] a,
input we,
input [width-1:0] di,
output reg [width-1:0] do,
input ce2,
input [depth-1:0] a2,
input we2,
input [width-1:0] di2,
... | 7.528927 |
module softusb_filter (
input usb_clk,
input rcv,
input vp,
input vm,
output reg rcv_s,
output reg vp_s,
output reg vm_s
);
reg rcv_s0;
reg vp_s0;
reg vm_s0;
/* synchronizer */
always @(posedge usb_clk) begin
rcv_s0 <= rcv;
vp_s0 <= vp;
vm_s0 <= vm;
rcv_s <= ... | 6.778026 |
module softusb_hostif #(
parameter csr_addr = 4'h0,
parameter pmem_width = 12
) (
input sys_clk,
input sys_rst,
input usb_clk,
output reg usb_rst,
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
output irq,
input io_we,
input [5:... | 7.072219 |
module softusb_phy (
input usb_clk,
input usb_rst,
output usba_spd,
output usba_oe_n,
input usba_rcv,
inout usba_vp,
inout usba_vm,
output usbb_spd,
output usbb_oe_n,
input usbb_rcv,
inout usbb_vp,
inout usbb_vm,
output [1:0] line_state_a,
output [1:0] li... | 7.030247 |
module softusb_ram #(
parameter pmem_width = 12,
parameter dmem_width = 13,
parameter initprog = ""
) (
input sys_clk,
input sys_rst,
input usb_clk,
input usb_rst,
input [31:0] wb_adr_i,
output [31:0] wb_dat_o,
input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output reg wb_ac... | 7.524306 |
module softusb_sie (
input usb_clk,
input usb_rst,
input io_re,
input io_we,
input [5:0] io_a,
input [7:0] io_di,
output reg [7:0] io_do,
output usba_spd,
output usba_oe_n,
input usba_rcv,
inout usba_vp,
inout usba_vm,
output usbb_spd,
output usbb_oe_n,
... | 7.672188 |
module software_testbench ();
reg clk, rst;
parameter CPU_CLOCK_PERIOD = 20;
parameter CPU_CLOCK_FREQ = 1_000_000_000 / CPU_CLOCK_PERIOD;
localparam TIMEOUT_CYCLE = 200_000 * 20;
initial clk = 0;
always #(CPU_CLOCK_PERIOD / 2) clk = ~clk;
wire [31:0] csr;
top_axi #(
.AXI_AWIDTH (32),
... | 7.322209 |
module soft_ecc_ram_16bit (
rst,
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b,
err_a,
err_b
);
`include "log2.inc"
// Number of 16 bit data words (stored as 22 bit words internally)
parameter NUM_WORDS = 512;
localparam AD... | 8.952439 |
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