code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module termination_fsm (
clk,
rst,
pout,
finished
);
input clk;
input rst;
input [7:0] pout;
output finished;
reg [1:0] state;
localparam STATE_INIT = 2'd0;
localparam STATE_DE_FOUND = 2'd1;
localparam STATE_AD_FOUND = 2'd2;
localparam STATE_00_FOUND = 2'd3;
assign finished = (state == STATE_00_FOUND);
wire [1:0] state_init_next = (pout == 8'hDE) ? STATE_DE_FOUND : STATE_INIT;
wire [1:0] state_de_next = (pout == 8'hDE) ? STATE_DE_FOUND :
(pout == 8'hAD) ? STATE_AD_FOUND : STATE_INIT;
wire [1:0] state_ad_next = (pout == 8'hAD) ? STATE_AD_FOUND :
(pout == 8'h00) ? STATE_00_FOUND : STATE_INIT;
wire [1:0] state_00_next = STATE_00_FOUND;
always @(posedge clk) begin
if (rst) begin
state <= STATE_INIT;
end else begin
case (state)
STATE_INIT: state <= state_init_next;
STATE_DE_FOUND: state <= state_de_next;
STATE_AD_FOUND: state <= state_ad_next;
STATE_00_FOUND: state <= state_00_next;
default: state <= STATE_INIT;
endcase
end
end
endmodule
| 6.955898 |
module axi4_arb_onehot4 (
// Inputs
input clk_i
, input rst_i
, input hold_i
, input [3:0] request_i
// Outputs
, output [3:0] grant_o
);
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
wire [3:0] req_ffs_masked_w;
wire [3:0] req_ffs_unmasked_w;
wire [3:0] req_ffs_w;
reg [3:0] mask_next_q;
reg [3:0] grant_last_q;
wire [3:0] grant_new_w;
//-----------------------------------------------------------------
// ffs: Find first set
//-----------------------------------------------------------------
function [3:0] ffs;
input [3:0] request;
begin
ffs[0] = request[0];
ffs[1] = ffs[0] | request[1];
ffs[2] = ffs[1] | request[2];
ffs[3] = ffs[2] | request[3];
end
endfunction
assign req_ffs_masked_w = ffs(request_i & mask_next_q);
assign req_ffs_unmasked_w = ffs(request_i);
assign req_ffs_w = (|req_ffs_masked_w) ? req_ffs_masked_w : req_ffs_unmasked_w;
always @(posedge clk_i or posedge rst_i)
if (rst_i == 1'b1) begin
mask_next_q <= {4{1'b1}};
grant_last_q <= 4'b0;
end else begin
if (~hold_i) mask_next_q <= {req_ffs_w[2:0], 1'b0};
grant_last_q <= grant_o;
end
assign grant_new_w = req_ffs_w ^ {req_ffs_w[2:0], 1'b0};
assign grant_o = hold_i ? grant_last_q : grant_new_w;
endmodule
| 6.693687 |
modules
//-----------------------------------------------------------------
module axi4retime_fifo2x37
(
// Inputs
input clk_i
,input rst_i
,input [ 36:0] data_in_i
,input push_i
,input pop_i
// Outputs
,output [ 36:0] data_out_o
,output accept_o
,output valid_o
);
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [36:0] ram_q[1:0];
reg [0:0] rd_ptr_q;
reg [0:0] wr_ptr_q;
reg [1:0] count_q;
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i == 1'b1)
begin
count_q <= 2'b0;
rd_ptr_q <= 1'b0;
wr_ptr_q <= 1'b0;
end
else
begin
// Push
if (push_i & accept_o)
begin
ram_q[wr_ptr_q] <= data_in_i;
wr_ptr_q <= wr_ptr_q + 1'd1;
end
// Pop
if (pop_i & valid_o)
begin
rd_ptr_q <= rd_ptr_q + 1'd1;
end
// Count up
if ((push_i & accept_o) & ~(pop_i & valid_o))
begin
count_q <= count_q + 2'd1;
end
// Count down
else if (~(push_i & accept_o) & (pop_i & valid_o))
begin
count_q <= count_q - 2'd1;
end
end
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
assign valid_o = (count_q != 2'd0);
assign accept_o = (count_q != 2'd2);
assign data_out_o = ram_q[rd_ptr_q];
endmodule
| 7.831093 |
module soc (
clk_clk,
export_size_new_signal,
export_start_new_signal,
reset_reset_n,
sdram_clk_clk,
sdram_wire_addr,
sdram_wire_ba,
sdram_wire_cas_n,
sdram_wire_cke,
sdram_wire_cs_n,
sdram_wire_dq,
sdram_wire_dqm,
sdram_wire_ras_n,
sdram_wire_we_n
);
input clk_clk;
output [31:0] export_size_new_signal;
output [31:0] export_start_new_signal;
input reset_reset_n;
output sdram_clk_clk;
output [12:0] sdram_wire_addr;
output [1:0] sdram_wire_ba;
output sdram_wire_cas_n;
output sdram_wire_cke;
output sdram_wire_cs_n;
inout [31:0] sdram_wire_dq;
output [3:0] sdram_wire_dqm;
output sdram_wire_ras_n;
output sdram_wire_we_n;
endmodule
| 6.848324 |
module soc_bram #(
parameter integer AW = 8,
parameter INIT_FILE = ""
) (
input wire [AW-1:0] addr,
output reg [ 31:0] rdata,
input wire [ 31:0] wdata,
input wire [ 3:0] wmsk,
input wire we,
input wire clk
);
reg [31:0] mem[0:(1<<AW)-1];
initial if (INIT_FILE != "") $readmemh(INIT_FILE, mem);
always @(posedge clk) begin
rdata <= mem[addr];
if (we & ~wmsk[0]) mem[addr][7:0] <= wdata[7:0];
if (we & ~wmsk[1]) mem[addr][15:8] <= wdata[15:8];
if (we & ~wmsk[2]) mem[addr][23:16] <= wdata[23:16];
if (we & ~wmsk[3]) mem[addr][31:24] <= wdata[31:24];
end
endmodule
| 6.785906 |
module soc_config #(
parameter BITS = 32
) (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
input user_clock2,
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oenb,
// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,
output [`MPRJ_IO_PADS-1:0] io_oeb,
// IRQ
output [2:0] irq,
// CPU/MEMORY specific
input rw_from_cpu,
input en_from_cpu,
input [11:0] addr_from_cpu,
input [15:0] data_from_cpu,
output [15:0] data_to_cpu,
input [15:0] data_from_mem0,
input [15:0] data_from_mem1,
input [15:0] data_from_mem2,
input [15:0] data_from_mem3,
output [15:0] data_to_mem,
output [9:0] addr_to_mem,
output [3:0] en_to_memB,
output rw_to_mem,
output en_keyboard,
output en_display,
output soc_rst,
output soc_clk
);
wire [`MPRJ_IO_PADS-1:0] io_in;
wire [`MPRJ_IO_PADS-1:0] io_out;
wire [`MPRJ_IO_PADS-1:0] io_oeb;
wire [15:0] data_from_mem;
wire [3:0] en_to_mems;
wire [1:0] addr_to_decod;
wire en_to_decod;
// IRQ
assign irq = 3'b000; // Unused
// floating unused outputs
assign io_out[21:0] = 22'h000000;
assign io_out[37:30] = 8'h00;
// IO Config
assign io_oeb[37:30] = 8'hFF; // input
assign io_oeb[29:22] = 8'h00; // output
assign io_oeb[21:18] = 4'hF; // input
assign io_oeb[17:0] = 18'hFFFFF; // input but unused
// LA
// if la_data_in[0] is input, then wbclk or usrclk can be used. Else io_in[19] is the clock
assign soc_clk = la_oenb[0] ? (la_data_in[0] ? user_clock2 : wb_clk_i) : io_in[19];
// if la_data_in[1] is input, then wbrst or io_in[18] can be used. Else io_in[18] is the reset
assign soc_rst = la_oenb[1] ? (la_data_in[1] ? io_in[18] : wb_rst_i) : io_in[18];
// Enable display and keyboard by LA or io_in 21/20
assign en_keyboard = la_oenb[2] ? la_data_in[2] : io_in[21];
assign en_display = la_oenb[3] ? la_data_in[3] : io_in[20];
// Provision to read/write ram from LA
assign data_to_mem = la_data_in[127] ? la_data_in[126:111] : data_from_cpu;
assign addr_to_decod = la_data_in[127] ? la_data_in[110:109] : addr_from_cpu[11:10];
assign addr_to_mem = la_data_in[127] ? la_data_in[108:99] : addr_from_cpu[9:0];
assign rw_to_mem = la_data_in[127] ? la_data_in[98] : ~rw_from_cpu; // active low for openram
assign en_to_decod = la_data_in[127] ? la_data_in[97] : en_from_cpu;
assign data_from_mem = addr_to_decod[1] ? ( addr_to_decod [0] ? data_from_mem3 : data_from_mem2 ) : ( addr_to_decod[0] ? data_from_mem1 : data_from_mem0 );
assign data_to_cpu = data_from_mem;
assign la_data_out[96:81] = data_from_mem;
assign en_to_memB = ~en_to_mems; // active low for openram
DECODER2x4 decodHadr (
.d(en_to_mems),
.a(addr_to_decod),
.e(en_to_decod)
);
endmodule
| 7.847951 |
module soc_event_arbiter (
clk_i,
rstn_i,
req_i,
grant_o,
grant_ack_i,
anyGrant_o
);
parameter EVNT_NUM = 256;
input wire clk_i;
input wire rstn_i;
input wire [EVNT_NUM - 1:0] req_i;
output wire [EVNT_NUM - 1:0] grant_o;
input wire grant_ack_i;
output wire anyGrant_o;
localparam S = $clog2(EVNT_NUM);
reg [EVNT_NUM - 1:0] r_priority;
reg [EVNT_NUM - 1:0] g[S:0];
reg [EVNT_NUM - 1:0] p[S - 1:0];
wire anyGnt;
wire [EVNT_NUM - 1:0] gnt;
assign anyGrant_o = anyGnt;
assign grant_o = gnt;
integer i;
integer j;
always @(req_i or r_priority) begin
p[0] = {~req_i[EVNT_NUM-2:0], ~req_i[EVNT_NUM-1]};
g[0] = r_priority;
for (i = 1; i < S; i = i + 1)
for (j = 0; j < EVNT_NUM; j = j + 1)
if ((j - (2 ** (i - 1))) < 0) begin
g[i][j] = g[i-1][j] | (p[i-1][j] & g[i-1][(EVNT_NUM+j)-(2**(i-1))]);
p[i][j] = p[i-1][j] & p[i-1][(EVNT_NUM+j)-(2**(i-1))];
end else begin
g[i][j] = g[i-1][j] | (p[i-1][j] & g[i-1][j-(2**(i-1))]);
p[i][j] = p[i-1][j] & p[i-1][j-(2**(i-1))];
end
for (j = 0; j < EVNT_NUM; j = j + 1)
if ((j - (2 ** (S - 1))) < 0)
g[S][j] = g[S-1][j] | (p[S-1][j] & g[S-1][(EVNT_NUM+j)-(2**(S-1))]);
else g[S][j] = g[S-1][j] | (p[S-1][j] & g[S-1][j-(2**(S-1))]);
end
assign anyGnt = ~(p[S-1][EVNT_NUM-1] & p[S-1][(EVNT_NUM/2)-1]);
assign gnt = req_i & g[S];
always @(posedge clk_i or negedge rstn_i)
if (rstn_i == 1'b0) r_priority <= 1;
else if (anyGnt && grant_ack_i) begin
r_priority[EVNT_NUM-1:1] <= gnt[EVNT_NUM-2:0];
r_priority[0] <= gnt[EVNT_NUM-1];
end
endmodule
| 6.772068 |
module soc_fpga_ram (
PortAClk,
PortAAddr,
PortADataIn,
PortAWriteEnable,
PortADataOut
);
parameter DATAWIDTH = 2;
parameter ADDRWIDTH = 2;
input PortAClk;
input [(ADDRWIDTH-1):0] PortAAddr;
input [(DATAWIDTH-1):0] PortADataIn;
input PortAWriteEnable;
output [(DATAWIDTH-1):0] PortADataOut;
parameter MEMDEPTH = 2 ** (ADDRWIDTH);
reg [(DATAWIDTH-1):0] mem[(MEMDEPTH-1):0];
reg [(DATAWIDTH-1):0] PortADataOut;
always @(posedge PortAClk) begin
if (PortAWriteEnable) begin
mem[PortAAddr] <= PortADataIn;
end else begin
PortADataOut <= mem[PortAAddr];
end
end
endmodule
| 7.332224 |
module HelloWorld_Top (
input rstn_i,
input rxd_i,
output txd_o,
inout [7:0] led_o,
output led_ctl_o,
output debug_o
);
GSR GSR_INST (.GSR(rstn_i));
wire sys_clk /*synthesis syn_keep = 1*/;
OSCH #(
.NOM_FREQ("38.00")
) OSCH_inst (
.STDBY(1'b0),
.OSC(sys_clk),
.SEDSTDBY()
);
SOC_IP HelloWorld_inst (
.clk_i (sys_clk),
.rstn_i (rstn_i),
.rxd_i (rxd_i),
.txd_o (txd_o),
.gpio_io(led_o),
.led_ctl(led_ctl_o),
.debug_o(debug_o)
);
endmodule
| 6.563951 |
module soc_mem_bank_1 (
input [31:0] mem_data_i,
output [31:0] mem_data_o,
input [31:0] mem_addr_i,
input [ 3:0] mem_sel_i,
input mem_we_i,
input mem_cyc_i,
input mem_stb_i,
output mem_ack_o,
output mem_err_o,
output mem_rty_o,
input mem_clk_i,
input mem_rst_i
);
//---------------------------------------------------
// outputs
assign mem_data_o = 32'h1bad_c0de;
assign mem_ack_o = mem_cyc_i & mem_stb_i;
assign mem_err_o = 1'b0;
assign mem_rty_o = 1'b0;
endmodule
| 7.232487 |
module soc_mem_bank_2 (
input [31:0] mem_data_i,
output [31:0] mem_data_o,
input [31:0] mem_addr_i,
input [ 3:0] mem_sel_i,
input mem_we_i,
input mem_cyc_i,
input mem_stb_i,
output mem_ack_o,
output mem_err_o,
output mem_rty_o,
input mem_clk_i,
input mem_rst_i
);
//---------------------------------------------------
// outputs
assign mem_data_o = 32'h1bad_c0de;
assign mem_ack_o = mem_cyc_i & mem_stb_i;
assign mem_err_o = 1'b0;
assign mem_rty_o = 1'b0;
endmodule
| 7.232487 |
module soc_mem_bank_3 (
input [31:0] mem_data_i,
output [31:0] mem_data_o,
input [31:0] mem_addr_i,
input [ 3:0] mem_sel_i,
input mem_we_i,
input mem_cyc_i,
input mem_stb_i,
output mem_ack_o,
output mem_err_o,
output mem_rty_o,
input mem_clk_i,
input mem_rst_i
);
parameter MEM_DEPTH = 14;
//---------------------------------------------------
// ram_byte_0
soc_ram #(
.DATA_WIDTH(8),
.ADDR_WIDTH(MEM_DEPTH),
.MEM_INIT (0)
) i_ram_byte_0 (
.data(mem_data_i[7:0]),
.addr(mem_addr_i[(MEM_DEPTH+1):2]),
.we(mem_we_i & mem_sel_i[0]),
.clk(~mem_clk_i),
.q(mem_data_o[7:0])
);
//---------------------------------------------------
// ram_byte_1
soc_ram #(
.DATA_WIDTH(8),
.ADDR_WIDTH(MEM_DEPTH),
.MEM_INIT (0)
) i_ram_byte_1 (
.data(mem_data_i[15:8]),
.addr(mem_addr_i[(MEM_DEPTH+1):2]),
.we(mem_we_i & mem_sel_i[1]),
.clk(~mem_clk_i),
.q(mem_data_o[15:8])
);
//---------------------------------------------------
// ram_byte_2
soc_ram #(
.DATA_WIDTH(8),
.ADDR_WIDTH(MEM_DEPTH),
.MEM_INIT (0)
) i_ram_byte_2 (
.data(mem_data_i[23:16]),
.addr(mem_addr_i[(MEM_DEPTH+1):2]),
.we(mem_we_i & mem_sel_i[2]),
.clk(~mem_clk_i),
.q(mem_data_o[23:16])
);
//---------------------------------------------------
// ram_byte_3
soc_ram #(
.DATA_WIDTH(8),
.ADDR_WIDTH(MEM_DEPTH),
.MEM_INIT (0)
) i_ram_byte_3 (
.data(mem_data_i[31:24]),
.addr(mem_addr_i[(MEM_DEPTH+1):2]),
.we(mem_we_i & mem_sel_i[3]),
.clk(~mem_clk_i),
.q(mem_data_o[31:24])
);
//---------------------------------------------------
// outputs
assign mem_ack_o = mem_cyc_i & mem_stb_i;
assign mem_err_o = 1'b0;
assign mem_rty_o = 1'b0;
endmodule
| 7.232487 |
module soc_peripherals (
input [31:0] peri_data_i,
output [31:0] peri_data_o,
input [31:0] peri_addr_i,
input [ 3:0] peri_sel_i,
input peri_we_i,
input peri_cyc_i,
input peri_stb_i,
output peri_ack_o,
output peri_err_o,
output peri_rty_o,
output uart_txd_0,
input uart_rxd_0,
input peri_clk_i,
input peri_rst_i
);
//---------------------------------------------------
// uart_0
uart_top i_uart_top (
.wb_clk_i(peri_clk_i),
.wb_rst_i(peri_rst_i),
.wb_adr_i(peri_addr_i[4:0]),
.wb_dat_i(peri_data_i),
.wb_dat_o(peri_data_o),
.wb_we_i (peri_we_i),
.wb_stb_i(peri_stb_i),
.wb_cyc_i(peri_cyc_i),
.wb_ack_o(peri_ack_o),
.wb_sel_i(peri_sel_i),
.int_o(),
.stx_pad_o(uart_txd_0),
.srx_pad_i(uart_rxd_0),
.rts_pad_o(),
.cts_pad_i(1'b0),
.dtr_pad_o(),
.dsr_pad_i(1'b0),
.ri_pad_i (1'b0),
.dcd_pad_i(1'b0)
);
//---------------------------------------------------
// optputs
assign peri_err_o = 1'b0;
assign peri_rty_o = 1'b0;
endmodule
| 6.720925 |
module soc_picorv32_base #(
parameter integer WB_N = 6,
parameter integer WB_DW = 32,
parameter integer WB_AW = 16,
parameter integer SPRAM_AW = 14, /* 14 => 64k, 15 => 128k */
/* auto */
parameter integer WB_MW = WB_DW / 8,
parameter integer WB_RW = WB_DW * WB_N,
parameter integer WB_AI = $clog2(WB_MW)
) (
// Wishbone
output wire [WB_AW-1:0] wb_addr,
input wire [WB_RW-1:0] wb_rdata,
output wire [WB_DW-1:0] wb_wdata,
output wire [WB_MW-1:0] wb_wmsk,
output wire wb_we,
output wire [WB_N -1:0] wb_cyc,
input wire [WB_N -1:0] wb_ack,
// SPI memory
output wire [23:0] spi_addr,
input wire [31:0] spi_rdata,
output wire [31:0] spi_wdata,
input wire spi_ready,
output wire spi_valid,
output wire spi_we,
output wire spi_mem_select,
// Clock / Reset
input wire clk,
input wire rst
);
// Signals
// -------
// Memory bus
wire mem_valid;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_rdata;
wire [31:0] mem_wdata;
wire [ 3:0] mem_wstrb;
// RAM
// BRAM
wire [ 7:0] bram_addr;
wire [31:0] bram_rdata;
wire [31:0] bram_wdata;
wire [ 3:0] bram_wmsk;
wire bram_we;
// SPRAM
wire [14:0] spram_addr;
wire [31:0] spram_rdata;
wire [31:0] spram_wdata;
wire [ 3:0] spram_wmsk;
wire spram_we;
// CPU
// ---
picorv32 #(
.PROGADDR_RESET(32'h0000_0000),
.STACKADDR(32'h0000_0400),
.BARREL_SHIFTER(0),
.COMPRESSED_ISA(0),
.ENABLE_COUNTERS(0),
.ENABLE_COUNTERS64(0),
.ENABLE_MUL(0),
.ENABLE_DIV(0),
.ENABLE_IRQ(0),
.ENABLE_IRQ_QREGS(0),
.CATCH_MISALIGN(0),
.CATCH_ILLINSN(0)
) cpu_I (
.clk (clk),
.resetn (~rst),
.mem_valid(mem_valid),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_addr (mem_addr),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_rdata(mem_rdata)
);
// Bus interface
// -------------
soc_picorv32_bridge #(
.WB_N (WB_N),
.WB_DW(WB_DW),
.WB_AW(WB_AW),
.WB_AI(WB_AI)
) pb_I (
.pb_addr (mem_addr),
.pb_rdata(mem_rdata),
.pb_wdata(mem_wdata),
.pb_wstrb(mem_wstrb),
.pb_valid(mem_valid),
.pb_ready(mem_ready),
.spi_addr(spi_addr),
.spi_rdata(spi_rdata),
.spi_wdata(spi_wdata),
.spi_valid(spi_valid),
.spi_ready(spi_ready),
.spi_we(spi_we),
.spi_mem_select(spi_mem_select),
.bram_addr (bram_addr),
.bram_rdata(bram_rdata),
.bram_wdata(bram_wdata),
.bram_wmsk (bram_wmsk),
.bram_we (bram_we),
.spram_addr (spram_addr),
.spram_rdata(spram_rdata),
.spram_wdata(spram_wdata),
.spram_wmsk (spram_wmsk),
.spram_we (spram_we),
.wb_addr (wb_addr),
.wb_wdata(wb_wdata),
.wb_wmsk (wb_wmsk),
.wb_rdata(wb_rdata),
.wb_cyc (wb_cyc),
.wb_we (wb_we),
.wb_ack (wb_ack),
.clk(clk),
.rst(rst)
);
// Local memory
// ------------
// Boot memory
soc_bram #(
.INIT_FILE("boot.hex")
) bram_I (
.addr (bram_addr),
.rdata(bram_rdata),
.wdata(bram_wdata),
.wmsk (bram_wmsk),
.we (bram_we),
.clk (clk)
);
// Main memory
soc_spram #(
.AW(SPRAM_AW)
) spram_I (
.addr (spram_addr[SPRAM_AW-1:0]),
.rdata(spram_rdata),
.wdata(spram_wdata),
.wmsk (spram_wmsk),
.we (spram_we),
.clk (clk)
);
endmodule
| 6.892519 |
module soc_ram (
data,
addr,
we,
clk,
q
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 6;
parameter MEM_INIT = 0;
input [(DATA_WIDTH-1):0] data;
input [(ADDR_WIDTH-1):0] addr;
input we;
input clk;
output [(DATA_WIDTH-1):0] q;
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] addr_reg;
always @(posedge clk) begin
// Write
if (we) ram[addr] <= data;
addr_reg <= addr;
end
// Read returns NEW data at addr if we == 1'b1. This is the
// natural behavior of TriMatrix memory blocks in Single Port
// mode
assign q = ram[addr_reg];
// generate
// if( MEM_INIT != 0 )
// initial
// $readmemh( MEM_INIT, ram );
// endgenerate
endmodule
| 7.389656 |
module soc_registers (
input [31:0] reg_data_i,
output [31:0] reg_data_o,
input [31:0] reg_addr_i,
input [ 3:0] reg_sel_i,
input reg_we_i,
input reg_cyc_i,
input reg_stb_i,
output reg_ack_o,
output reg_err_o,
output reg_rty_o,
input reg_clk_i,
input reg_rst_i
);
//---------------------------------------------------
// outputs
assign reg_data_o = 32'h1bad_c0de;
assign reg_ack_o = reg_cyc_i & reg_stb_i;
assign reg_err_o = 1'b0;
assign reg_rty_o = 1'b0;
endmodule
| 7.149461 |
module soc_spram #(
parameter integer AW = 14
) (
input wire [AW-1:0] addr,
output wire [ 31:0] rdata,
input wire [ 31:0] wdata,
input wire [ 3:0] wmsk,
input wire we,
input wire clk
);
wire [7:0] msk_nibble = {wmsk[3], wmsk[3], wmsk[2], wmsk[2], wmsk[1], wmsk[1], wmsk[0], wmsk[0]};
ice40_spram_gen #(
.ADDR_WIDTH(AW),
.DATA_WIDTH(32)
) spram_I (
.addr(addr),
.rd_data(rdata),
.rd_ena(1'b1),
.wr_data(wdata),
.wr_mask(msk_nibble),
.wr_ena(we),
.clk(clk)
);
endmodule
| 8.106937 |
module soc_system_avalon_st_adapter_data_format_adapter_0 (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [23:0] in_data,
input in_startofpacket,
input in_endofpacket,
input [ 1:0] in_empty,
// Interface: out
input out_ready,
output reg out_valid,
output reg [23:0] out_data,
output reg out_startofpacket,
output reg out_endofpacket
);
always @* begin
in_ready = out_ready;
out_valid = in_valid;
out_data = in_data;
out_startofpacket = in_startofpacket;
out_endofpacket = in_endofpacket;
end
endmodule
| 7.482476 |
module soc_system_avalon_st_adapter_timing_adapter_0 (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [23:0] in_data,
input in_startofpacket,
input in_endofpacket,
// Interface: out
input out_ready,
output reg out_valid,
output reg [23:0] out_data,
output reg out_startofpacket,
output reg out_endofpacket
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg [25:0] in_payload;
wire [25:0] out_payload;
wire in_ready_wire;
wire out_valid_wire;
wire [ 3:0] fifo_fill;
reg [ 0:0] ready;
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_payload = {in_data, in_startofpacket, in_endofpacket};
{out_data, out_startofpacket, out_endofpacket} = out_payload;
end
// ---------------------------------------------------------------------
//| FIFO
// ---------------------------------------------------------------------
soc_system_avalon_st_adapter_timing_adapter_0_fifo soc_system_avalon_st_adapter_timing_adapter_0_fifo
(
.clk (clk),
.reset_n (reset_n),
.in_ready (),
.in_valid (in_valid),
.in_data (in_payload),
.out_ready (ready[0]),
.out_valid (out_valid_wire),
.out_data (out_payload),
.fill_level(fifo_fill)
);
// ---------------------------------------------------------------------
//| Ready & valid signals.
// ---------------------------------------------------------------------
always @* begin
in_ready = (fifo_fill < 4);
out_valid = out_valid_wire;
ready[0] = out_ready;
end
endmodule
| 7.482476 |
module soc_system_avalon_st_adapter_timing_adapter_0_fifo (
output reg [3:0] fill_level,
// Interface: clock
input clk,
input reset_n,
// Interface: data_in
output reg in_ready,
input in_valid,
input [25:0] in_data,
// Interface: data_out
input out_ready,
output reg out_valid,
output reg [25:0] out_data
);
// ---------------------------------------------------------------------
//| Internal Parameters
// ---------------------------------------------------------------------
parameter DEPTH = 8;
parameter DATA_WIDTH = 26;
parameter ADDR_WIDTH = 3;
// ---------------------------------------------------------------------
//| Signals
// ---------------------------------------------------------------------
reg [ADDR_WIDTH-1:0] wr_addr;
reg [ADDR_WIDTH-1:0] rd_addr;
reg [ADDR_WIDTH-1:0] next_wr_addr;
reg [ADDR_WIDTH-1:0] next_rd_addr;
reg [ADDR_WIDTH-1:0] mem_rd_addr;
reg [DATA_WIDTH-1:0] mem[DEPTH-1:0];
reg empty;
reg full;
reg [0:0] out_ready_vector;
// ---------------------------------------------------------------------
//| FIFO Status
// ---------------------------------------------------------------------
always @* begin
// out_valid = !empty;
out_ready_vector[0] = out_ready;
in_ready = !full;
next_wr_addr = wr_addr + 1'b1;
next_rd_addr = rd_addr + 1'b1;
fill_level[ADDR_WIDTH-1:0] = wr_addr - rd_addr;
fill_level[ADDR_WIDTH] = 0;
if (full) fill_level = DEPTH[ADDR_WIDTH:0];
end
// ---------------------------------------------------------------------
//| Manage Pointers
// ---------------------------------------------------------------------
always @(negedge reset_n, posedge clk) begin
if (!reset_n) begin
wr_addr <= 0;
rd_addr <= 0;
empty <= 1;
rd_addr <= 0;
full <= 0;
out_valid <= 0;
end else begin
out_valid <= !empty;
if (in_ready && in_valid) begin
wr_addr <= next_wr_addr;
empty <= 0;
if (next_wr_addr == rd_addr) full <= 1;
end
if (out_ready_vector[0] && out_valid) begin
rd_addr <= next_rd_addr;
full <= 0;
if (next_rd_addr == wr_addr) begin
empty <= 1;
out_valid <= 0;
end
end
if (out_ready_vector[0] && out_valid && in_ready && in_valid) begin
full <= full;
empty <= empty;
end
end
end // always @ (negedge reset_n, posedge clk)
always @* begin
mem_rd_addr = rd_addr;
if (out_ready && out_valid) begin
mem_rd_addr = next_rd_addr;
end
end
// ---------------------------------------------------------------------
//| Infer Memory
// ---------------------------------------------------------------------
always @(posedge clk) begin
if (in_ready && in_valid) mem[wr_addr] <= in_data;
out_data <= mem[mem_rd_addr];
end
endmodule
| 7.482476 |
module soc_system (
avalon_interface_to_smart_meter_fsms_0_interface_to_fsm_data_neg_in,
avalon_interface_to_smart_meter_fsms_0_interface_to_fsm_data_neg_out,
avalon_interface_to_smart_meter_fsms_0_interface_to_fsm_data_pos_in,
avalon_interface_to_smart_meter_fsms_0_interface_to_fsm_data_pos_out,
avalon_interface_to_smart_meter_fsms_0_interface_to_fsm_data_valid_in,
avalon_interface_to_smart_meter_fsms_0_interface_to_fsm_start_pumps,
avalon_interface_to_smart_meter_fsms_0_interface_to_fsm_start_loads,
avalon_interface_to_smart_meter_fsms_0_interface_to_fsm_battery,
clk_clk,
reset_reset_n
);
input [7:0] avalon_interface_to_smart_meter_fsms_0_interface_to_fsm_data_neg_in;
output [7:0] avalon_interface_to_smart_meter_fsms_0_interface_to_fsm_data_neg_out;
input [7:0] avalon_interface_to_smart_meter_fsms_0_interface_to_fsm_data_pos_in;
output [7:0] avalon_interface_to_smart_meter_fsms_0_interface_to_fsm_data_pos_out;
input avalon_interface_to_smart_meter_fsms_0_interface_to_fsm_data_valid_in;
output avalon_interface_to_smart_meter_fsms_0_interface_to_fsm_start_pumps;
output avalon_interface_to_smart_meter_fsms_0_interface_to_fsm_start_loads;
input [7:0] avalon_interface_to_smart_meter_fsms_0_interface_to_fsm_battery;
input clk_clk;
input reset_reset_n;
endmodule
| 6.582601 |
module soc_system_com_mem (
// inputs:
address,
address2,
byteenable,
byteenable2,
chipselect,
chipselect2,
clk,
clk2,
clken,
clken2,
reset,
reset2,
reset_req,
reset_req2,
write,
write2,
writedata,
writedata2,
// outputs:
readdata,
readdata2
)
;
parameter INIT_FILE = "soc_system_com_mem.hex";
output [ 31: 0] readdata;
output [ 31: 0] readdata2;
input [ 9: 0] address;
input [ 9: 0] address2;
input [ 3: 0] byteenable;
input [ 3: 0] byteenable2;
input chipselect;
input chipselect2;
input clk;
input clk2;
input clken;
input clken2;
input reset;
input reset2;
input reset_req;
input reset_req2;
input write;
input write2;
input [ 31: 0] writedata;
input [ 31: 0] writedata2;
wire clocken0;
wire clocken1;
wire [ 31: 0] readdata;
wire [ 31: 0] readdata2;
wire wren;
wire wren2;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
assign clocken1 = clken2 & ~reset_req2;
assign wren2 = chipselect2 & write2;
altsyncram the_altsyncram
(
.address_a (address),
.address_b (address2),
.byteena_a (byteenable),
.byteena_b (byteenable2),
.clock0 (clk),
.clock1 (clk2),
.clocken0 (clocken0),
.clocken1 (clocken1),
.data_a (writedata),
.data_b (writedata2),
.q_a (readdata),
.q_b (readdata2),
.wren_a (wren),
.wren_b (wren2)
);
defparam the_altsyncram.address_reg_b = "CLOCK1",
the_altsyncram.byte_size = 8,
the_altsyncram.byteena_reg_b = "CLOCK1",
the_altsyncram.indata_reg_b = "CLOCK1",
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 1024,
the_altsyncram.numwords_a = 1024,
the_altsyncram.numwords_b = 1024,
the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.width_byteena_b = 4,
the_altsyncram.widthad_a = 10,
the_altsyncram.widthad_b = 10,
the_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK1";
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
| 6.744149 |
module soc_system_ddr3_emif_0_p0_acv_ldc (
pll_hr_clk,
pll_dq_clk,
pll_dqs_clk,
dll_phy_delayctrl,
afi_clk,
avl_clk,
adc_clk,
adc_clk_cps,
hr_clk
);
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter ADC_PHASE_SETTING = 0;
parameter ADC_INVERT_PHASE = "false";
parameter IS_HHP_HPS = "false";
input pll_hr_clk;
input pll_dq_clk;
input pll_dqs_clk;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
output afi_clk;
output avl_clk;
output adc_clk;
output adc_clk_cps;
output hr_clk;
wire phy_clk_dqs;
wire phy_clk_dq;
wire phy_clk_hr;
wire phy_clk_dqs_2x;
wire phy_clk_addr_cmd;
wire phy_clk_addr_cmd_cps;
generate
if (IS_HHP_HPS == "true") begin
assign phy_clk_hr = pll_hr_clk;
assign phy_clk_dq = pll_dq_clk;
assign phy_clk_dqs = pll_dqs_clk;
assign phy_clk_dqs_2x = 1'b0;
end else begin
cyclonev_phy_clkbuf phy_clkbuf (
.inclk ({pll_hr_clk, pll_dq_clk, pll_dqs_clk, 1'b0}),
.outclk({phy_clk_hr, phy_clk_dq, phy_clk_dqs, phy_clk_dqs_2x})
);
end
endgenerate
wire [3:0] leveled_dqs_clocks;
wire [3:0] leveled_hr_clocks;
wire hr_seq_clock;
cyclonev_leveling_delay_chain leveling_delay_chain_dqs (
.clkin(phy_clk_dqs),
.delayctrlin(dll_phy_delayctrl),
.clkout(leveled_dqs_clocks)
);
defparam leveling_delay_chain_dqs.physical_clock_source = "DQS";
assign afi_clk = leveled_dqs_clocks[0];
cyclonev_leveling_delay_chain leveling_delay_chain_hr (
.clkin(phy_clk_hr),
.delayctrlin(),
.clkout(leveled_hr_clocks)
);
defparam leveling_delay_chain_hr.physical_clock_source = "HR";
assign avl_clk = leveled_hr_clocks[0];
cyclonev_clk_phase_select clk_phase_select_addr_cmd (
.clkin (leveled_dqs_clocks),
.clkout(adc_clk_cps)
);
defparam clk_phase_select_addr_cmd.physical_clock_source = "ADD_CMD";
defparam clk_phase_select_addr_cmd.use_phasectrlin = "false";
defparam clk_phase_select_addr_cmd.phase_setting = ADC_PHASE_SETTING;
defparam clk_phase_select_addr_cmd.invert_phase = ADC_INVERT_PHASE;
cyclonev_clk_phase_select clk_phase_select_hr (
.phasectrlin(),
.phaseinvertctrl(),
.dqsin(),
`ifndef SIMGEN
.clkin(leveled_hr_clocks[0]),
`else
.clkin(leveled_hr_clocks),
`endif
.clkout(hr_seq_clock)
);
defparam clk_phase_select_hr.physical_clock_source = "HR";
defparam clk_phase_select_hr.use_phasectrlin = "false";
defparam clk_phase_select_hr.phase_setting = 0;
assign hr_clk = hr_seq_clock;
generate
if (ADC_INVERT_PHASE == "true") begin
assign adc_clk = ~leveled_dqs_clocks[ADC_PHASE_SETTING];
end else begin
assign adc_clk = leveled_dqs_clocks[ADC_PHASE_SETTING];
end
endgenerate
endmodule
| 6.65294 |
module soc_system_ddr3_emif_0_p0_clock_pair_generator (
datain,
dataout,
dataout_b
) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] wire_pseudo_diffa_oebout;
wire [0:0] wire_pseudo_diffa_oein;
wire [0:0] wire_pseudo_diffa_oeout;
wire [0:0] oe_w;
cyclonev_io_obuf obuf_ba_0 (
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(wire_obuf_ba_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif ,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
, .devoe(1'b1)
// synopsys translate_on
);
defparam obuf_ba_0.bus_hold = "false", obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "cyclonev_io_obuf";
assign wire_obuf_ba_oe = {(~wire_pseudo_diffa_oebout[0])};
cyclonev_io_obuf obufa_0 (
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif ,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
, .devoe(1'b1)
// synopsys translate_on
);
defparam obufa_0.bus_hold = "false", obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
assign wire_obufa_oe = {(~wire_pseudo_diffa_oeout[0])};
cyclonev_pseudo_diff_out pseudo_diffa_0 (
.dtc(),
.dtcbar(),
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]),
.oebout(wire_pseudo_diffa_oebout[0:0]),
.oein(wire_pseudo_diffa_oein[0:0]),
.oeout(wire_pseudo_diffa_oeout[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif ,
.dtcin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
assign wire_pseudo_diffa_oein = {(~oe_w[0])};
assign dataout = wire_obufa_o, dataout_b = wire_obuf_ba_o, oe_w = 1'b1;
endmodule
| 6.65294 |
module soc_system_ddr3_emif_0_p0_generic_ddio (
datain,
halfratebypass,
dataout,
clk_hr,
clk_fr
);
parameter WIDTH = 1;
localparam DATA_IN_WIDTH = 4 * WIDTH;
localparam DATA_OUT_WIDTH = WIDTH;
input [DATA_IN_WIDTH-1:0] datain;
input halfratebypass;
input [WIDTH-1:0] clk_hr;
input [WIDTH-1:0] clk_fr;
output [DATA_OUT_WIDTH-1:0] dataout;
generate
genvar pin;
for (pin = 0; pin < WIDTH; pin = pin + 1) begin : acblock
wire fr_data_hi;
wire fr_data_lo;
cyclonev_ddio_out #(
.half_rate_mode("true"),
.use_new_clocking_model("true"),
.async_mode("none")
) hr_to_fr_hi (
.datainhi(datain[pin*4]),
.datainlo(datain[pin*4+2]),
.dataout(fr_data_hi),
.clkhi(clk_hr[pin]),
.clklo(clk_hr[pin]),
.hrbypass(halfratebypass),
.muxsel(clk_hr[pin])
);
cyclonev_ddio_out #(
.half_rate_mode("true"),
.use_new_clocking_model("true"),
.async_mode("none")
) hr_to_fr_lo (
.datainhi(datain[pin*4+1]),
.datainlo(datain[pin*4+3]),
.dataout(fr_data_lo),
.clkhi(clk_hr[pin]),
.clklo(clk_hr[pin]),
.hrbypass(halfratebypass),
.muxsel(clk_hr[pin])
);
cyclonev_ddio_out #(
.async_mode("none"),
.half_rate_mode("false"),
.sync_mode("none"),
.use_new_clocking_model("true")
) ddio_out (
.datainhi(fr_data_hi),
.datainlo(fr_data_lo),
.dataout(dataout[pin]),
.clkhi(clk_fr[pin]),
.clklo(clk_fr[pin]),
.muxsel(clk_fr[pin])
);
end
endgenerate
endmodule
| 6.65294 |
module soc_system_ddr3_emif_0_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe(probe_input),
.source()
// synopsys translate_off
, .clrn(),
.ena(),
.ir_in(),
.ir_out(),
.jtag_state_cdr(),
.jtag_state_cir(),
.jtag_state_e1dr(),
.jtag_state_sdr(),
.jtag_state_tlr(),
.jtag_state_udr(),
.jtag_state_uir(),
.raw_tck(),
.source_clk(),
.source_ena(),
.tdi(),
.tdo(),
.usr1()
// synopsys translate_on
);
defparam iss_probe_inst.enable_metastability = "NO", iss_probe_inst.instance_id = ID_NAME,
iss_probe_inst.probe_width = WIDTH, iss_probe_inst.sld_auto_instance_index = "YES",
iss_probe_inst.sld_instance_index = 0, iss_probe_inst.source_initial_value = "0",
iss_probe_inst.source_width = 0;
endmodule
| 6.65294 |
module soc_system_ddr3_emif_0_p0_reset (
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
reset_n_afi_clk,
reset_n_addr_cmd_clk,
reset_n_resync_clk,
reset_n_seq_clk,
reset_n_read_capture_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input seq_reset_mem_stable;
input pll_afi_clk;
input pll_addr_cmd_clk;
input pll_dqs_ena_clk;
input seq_clk;
input scc_clk;
input pll_avl_clk;
output reset_n_scc_clk;
output reset_n_avl_clk;
input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input pll_locked;
input global_reset_n;
input soft_reset_n;
output ctl_reset_n;
output ctl_reset_export_n;
output [NUM_AFI_RESET-1:0] reset_n_afi_clk;
output reset_n_addr_cmd_clk;
output reset_n_resync_clk;
output reset_n_seq_clk;
output [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture_clk;
// Apply the synthesis keep attribute on the synchronized reset wires
// so that these names can be constrained using QSF settings to keep
// the resets on local routing.
wire phy_reset_n /* synthesis keep = 1 */;
wire phy_reset_mem_stable_n /* synthesis keep = 1*/;
wire [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture;
assign phy_reset_mem_stable_n = phy_reset_n & seq_reset_mem_stable;
assign reset_n_read_capture_clk = reset_n_read_capture;
assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n;
soc_system_ddr3_emif_0_p0_reset_sync ureset_afi_clk (
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (reset_n_afi_clk)
);
defparam ureset_afi_clk.RESET_SYNC_STAGES = 15;
defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET;
soc_system_ddr3_emif_0_p0_reset_sync ureset_ctl_reset_clk (
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync ({ctl_reset_n, ctl_reset_export_n})
);
defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 15;
defparam ureset_ctl_reset_clk.NUM_RESET_OUTPUT = 2;
soc_system_ddr3_emif_0_p0_reset_sync ureset_addr_cmd_clk (
.reset_n (phy_reset_n),
.clk (pll_addr_cmd_clk),
.reset_n_sync(reset_n_addr_cmd_clk)
);
defparam ureset_addr_cmd_clk.RESET_SYNC_STAGES = 15;
defparam ureset_addr_cmd_clk.NUM_RESET_OUTPUT = 1;
soc_system_ddr3_emif_0_p0_reset_sync ureset_resync_clk (
.reset_n (phy_reset_n),
.clk (pll_dqs_ena_clk),
.reset_n_sync (reset_n_resync_clk)
);
defparam ureset_resync_clk.RESET_SYNC_STAGES = 15;
defparam ureset_resync_clk.NUM_RESET_OUTPUT = 1;
soc_system_ddr3_emif_0_p0_reset_sync ureset_seq_clk (
.reset_n (phy_reset_n),
.clk (seq_clk),
.reset_n_sync (reset_n_seq_clk)
);
defparam ureset_seq_clk.RESET_SYNC_STAGES = 15; defparam ureset_seq_clk.NUM_RESET_OUTPUT = 1;
soc_system_ddr3_emif_0_p0_reset_sync ureset_scc_clk (
.reset_n (phy_reset_n),
.clk (scc_clk),
.reset_n_sync (reset_n_scc_clk)
);
defparam ureset_scc_clk.RESET_SYNC_STAGES = 15; defparam ureset_scc_clk.NUM_RESET_OUTPUT = 1;
soc_system_ddr3_emif_0_p0_reset_sync ureset_avl_clk (
.reset_n (phy_reset_n),
.clk (pll_avl_clk),
.reset_n_sync (reset_n_avl_clk)
);
defparam ureset_avl_clk.RESET_SYNC_STAGES = 2; defparam ureset_avl_clk.NUM_RESET_OUTPUT = 1;
generate
genvar i;
for (i = 0; i < MEM_READ_DQS_WIDTH; i = i + 1) begin : read_capture_reset
soc_system_ddr3_emif_0_p0_reset_sync #(
.RESET_SYNC_STAGES(15),
.NUM_RESET_OUTPUT (1)
) ureset_read_capture_clk (
.reset_n (phy_reset_mem_stable_n),
.clk (read_capture_clk[i]),
.reset_n_sync(reset_n_read_capture[i])
);
end
endgenerate
endmodule
| 6.65294 |
module soc_system_ddr3_emif_0_p0_reset_sync (
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since these resets are localized to the PHY alone, make them routed locally
// to avoid using global networks.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*)
reg [RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;
generate
genvar i;
for (i = 0; i < RESET_SYNC_STAGES + NUM_RESET_OUTPUT - 1; i = i + 1) begin : reset_stage
always @(posedge clk or negedge reset_n) begin
if (~reset_n) reset_reg[i] <= 1'b0;
else begin
if (i == 0) reset_reg[i] <= 1'b1;
else if (i < RESET_SYNC_STAGES) reset_reg[i] <= reset_reg[i-1];
else reset_reg[i] <= reset_reg[RESET_SYNC_STAGES-2];
end
end
end
endgenerate
assign reset_n_sync = reset_reg[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:RESET_SYNC_STAGES-1];
endmodule
| 6.65294 |
module soc_system_dipsw_pio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
);
output irq;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input [3:0] in_port;
input reset_n;
input write_n;
input [31:0] writedata;
wire clk_en;
reg [ 3:0] d1_data_in;
reg [ 3:0] d2_data_in;
wire [ 3:0] data_in;
reg [ 3:0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 3:0] edge_detect;
wire irq;
reg [ 3:0] irq_mask;
wire [ 3:0] read_mux_out;
reg [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
({4 {(address == 2)}} & irq_mask) |
({4 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) readdata <= 0;
else if (clk_en) readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2)) irq_mask <= writedata[3 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[0]) edge_capture[0] <= 0;
else if (edge_detect[0]) edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[1]) edge_capture[1] <= 0;
else if (edge_detect[1]) edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[2]) edge_capture[2] <= 0;
else if (edge_detect[2]) edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[3]) edge_capture[3] <= 0;
else if (edge_detect[3]) edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) begin
d1_data_in <= 0;
d2_data_in <= 0;
end else if (clk_en) begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in ^ d2_data_in;
endmodule
| 6.761748 |
module soc_system_low_power_pio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input in_port;
input reset_n;
input write_n;
input [31:0] writedata;
wire clk_en;
reg d1_data_in;
reg d2_data_in;
wire data_in;
reg edge_capture;
wire edge_capture_wr_strobe;
wire edge_detect;
wire read_mux_out;
reg [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({1{(address == 0)}} & data_in) | ({1{(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) readdata <= 0;
else if (clk_en) readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) edge_capture <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[0]) edge_capture <= 0;
else if (edge_detect) edge_capture <= -1;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) begin
d1_data_in <= 0;
d2_data_in <= 0;
end else if (clk_en) begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in & ~d2_data_in;
endmodule
| 6.976668 |
module soc_system_SRAM (
// inputs:
address,
address2,
byteenable,
byteenable2,
chipselect,
chipselect2,
clk,
clk2,
clken,
clken2,
freeze,
reset,
reset2,
reset_req,
reset_req2,
write,
write2,
writedata,
writedata2,
// outputs:
readdata,
readdata2
)
;
parameter INIT_FILE = "soc_system_SRAM.hex";
output [ 31: 0] readdata;
output [ 31: 0] readdata2;
input [ 13: 0] address;
input [ 13: 0] address2;
input [ 3: 0] byteenable;
input [ 3: 0] byteenable2;
input chipselect;
input chipselect2;
input clk;
input clk2;
input clken;
input clken2;
input freeze;
input reset;
input reset2;
input reset_req;
input reset_req2;
input write;
input write2;
input [ 31: 0] writedata;
input [ 31: 0] writedata2;
wire clocken0;
wire clocken1;
wire [ 31: 0] readdata;
wire [ 31: 0] readdata2;
wire wren;
wire wren2;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
assign clocken1 = clken2 & ~reset_req2;
assign wren2 = chipselect2 & write2;
altsyncram the_altsyncram
(
.address_a (address),
.address_b (address2),
.byteena_a (byteenable),
.byteena_b (byteenable2),
.clock0 (clk),
.clock1 (clk2),
.clocken0 (clocken0),
.clocken1 (clocken1),
.data_a (writedata),
.data_b (writedata2),
.q_a (readdata),
.q_b (readdata2),
.wren_a (wren),
.wren_b (wren2)
);
defparam the_altsyncram.address_reg_b = "CLOCK1",
the_altsyncram.byte_size = 8,
the_altsyncram.byteena_reg_b = "CLOCK1",
the_altsyncram.indata_reg_b = "CLOCK1",
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 16384,
the_altsyncram.numwords_a = 16384,
the_altsyncram.numwords_b = 16384,
the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.width_byteena_b = 4,
the_altsyncram.widthad_a = 14,
the_altsyncram.widthad_b = 14,
the_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK1";
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
| 6.500704 |
module soc_system_tc_mem (
// inputs:
address,
address2,
byteenable,
byteenable2,
chipselect,
chipselect2,
clk,
clk2,
clken,
clken2,
reset,
reset2,
reset_req,
reset_req2,
write,
write2,
writedata,
writedata2,
// outputs:
readdata,
readdata2
)
;
parameter INIT_FILE = "soc_system_tc_mem.hex";
output [ 31: 0] readdata;
output [ 31: 0] readdata2;
input [ 12: 0] address;
input [ 12: 0] address2;
input [ 3: 0] byteenable;
input [ 3: 0] byteenable2;
input chipselect;
input chipselect2;
input clk;
input clk2;
input clken;
input clken2;
input reset;
input reset2;
input reset_req;
input reset_req2;
input write;
input write2;
input [ 31: 0] writedata;
input [ 31: 0] writedata2;
wire clocken0;
wire clocken1;
wire [ 31: 0] readdata;
wire [ 31: 0] readdata2;
wire wren;
wire wren2;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
assign clocken1 = clken2 & ~reset_req2;
assign wren2 = chipselect2 & write2;
altsyncram the_altsyncram
(
.address_a (address),
.address_b (address2),
.byteena_a (byteenable),
.byteena_b (byteenable2),
.clock0 (clk),
.clock1 (clk2),
.clocken0 (clocken0),
.clocken1 (clocken1),
.data_a (writedata),
.data_b (writedata2),
.q_a (readdata),
.q_b (readdata2),
.wren_a (wren),
.wren_b (wren2)
);
defparam the_altsyncram.address_reg_b = "CLOCK1",
the_altsyncram.byte_size = 8,
the_altsyncram.byteena_reg_b = "CLOCK1",
the_altsyncram.indata_reg_b = "CLOCK1",
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 6144,
the_altsyncram.numwords_a = 6144,
the_altsyncram.numwords_b = 6144,
the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.width_byteena_b = 4,
the_altsyncram.widthad_a = 13,
the_altsyncram.widthad_b = 13,
the_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK1";
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
| 6.810307 |
module RegFile ( // @[:@464.2]
input clock, // @[:@465.4]
input [ 4:0] io_raddr_1, // @[:@467.4]
input [ 4:0] io_raddr_2, // @[:@467.4]
output [31:0] io_rdata_1, // @[:@467.4]
output [31:0] io_rdata_2, // @[:@467.4]
input io_wen, // @[:@467.4]
input [ 4:0] io_waddr, // @[:@467.4]
input [31:0] io_wdata // @[:@467.4]
);
reg [31:0] regs[0:31]; // @[reg_file.scala 31:17:@469.4]
reg [31:0] _RAND_0;
wire [31:0] regs__T_23_data; // @[reg_file.scala 31:17:@469.4]
wire [4:0] regs__T_23_addr; // @[reg_file.scala 31:17:@469.4]
wire [31:0] regs__T_28_data; // @[reg_file.scala 31:17:@469.4]
wire [4:0] regs__T_28_addr; // @[reg_file.scala 31:17:@469.4]
wire [31:0] regs__T_34_data; // @[reg_file.scala 31:17:@469.4]
wire [4:0] regs__T_34_addr; // @[reg_file.scala 31:17:@469.4]
wire regs__T_34_mask; // @[reg_file.scala 31:17:@469.4]
wire regs__T_34_en; // @[reg_file.scala 31:17:@469.4]
wire _T_22; // @[reg_file.scala 33:33:@470.4]
wire _T_27; // @[reg_file.scala 34:33:@474.4]
wire _T_32; // @[reg_file.scala 36:26:@478.4]
assign regs__T_23_addr = io_raddr_1;
assign regs__T_23_data = regs[regs__T_23_addr]; // @[reg_file.scala 31:17:@469.4]
assign regs__T_28_addr = io_raddr_2;
assign regs__T_28_data = regs[regs__T_28_addr]; // @[reg_file.scala 31:17:@469.4]
assign regs__T_34_data = io_wdata;
assign regs__T_34_addr = io_waddr;
assign regs__T_34_mask = 1'h1;
assign regs__T_34_en = io_wen & _T_32;
assign _T_22 = io_raddr_1 != 5'h0; // @[reg_file.scala 33:33:@470.4]
assign _T_27 = io_raddr_2 != 5'h0; // @[reg_file.scala 34:33:@474.4]
assign _T_32 = io_waddr != 5'h0; // @[reg_file.scala 36:26:@478.4]
assign io_rdata_1 = _T_22 ? regs__T_23_data : 32'h0; // @[reg_file.scala 33:14:@473.4]
assign io_rdata_2 = _T_27 ? regs__T_28_data : 32'h0; // @[reg_file.scala 34:14:@477.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
#0.002 begin
end
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 32; initvar = initvar + 1) regs[initvar] = _RAND_0[31:0];
`endif // RANDOMIZE_MEM_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (regs__T_34_en & regs__T_34_mask) begin
regs[regs__T_34_addr] <= regs__T_34_data; // @[reg_file.scala 31:17:@469.4]
end
end
endmodule
| 6.637965 |
module Branch ( // @[:@712.2]
input [31:0] io_in_a, // @[:@715.4]
input [31:0] io_in_b, // @[:@715.4]
input [ 2:0] io_br_type, // @[:@715.4]
output io_br_taken // @[:@715.4]
);
wire [32:0] _T_13; // @[branch.scala 24:33:@717.4]
wire [32:0] _T_14; // @[branch.scala 24:33:@718.4]
wire [31:0] difference; // @[branch.scala 24:33:@719.4]
wire not_equal; // @[branch.scala 25:36:@720.4]
wire equal; // @[branch.scala 26:25:@721.4]
wire _T_17; // @[branch.scala 27:32:@722.4]
wire _T_18; // @[branch.scala 27:52:@723.4]
wire is_same_sign; // @[branch.scala 27:41:@724.4]
wire _T_19; // @[branch.scala 28:53:@725.4]
wire less_than; // @[branch.scala 28:28:@727.4]
wire less_than_u; // @[branch.scala 29:28:@730.4]
wire greater_equal; // @[branch.scala 30:25:@731.4]
wire greater_equal_u; // @[branch.scala 31:25:@732.4]
wire _T_25; // @[branch.scala 35:18:@733.4]
wire _T_26; // @[branch.scala 35:30:@734.4]
wire _T_27; // @[branch.scala 36:18:@735.4]
wire _T_28; // @[branch.scala 36:30:@736.4]
wire _T_29; // @[branch.scala 35:40:@737.4]
wire _T_30; // @[branch.scala 37:18:@738.4]
wire _T_31; // @[branch.scala 37:30:@739.4]
wire _T_32; // @[branch.scala 36:44:@740.4]
wire _T_33; // @[branch.scala 38:18:@741.4]
wire _T_34; // @[branch.scala 38:30:@742.4]
wire _T_35; // @[branch.scala 37:44:@743.4]
wire _T_36; // @[branch.scala 39:18:@744.4]
wire _T_37; // @[branch.scala 39:30:@745.4]
wire _T_38; // @[branch.scala 38:48:@746.4]
wire _T_39; // @[branch.scala 40:18:@747.4]
wire _T_40; // @[branch.scala 40:30:@748.4]
assign _T_13 = io_in_a - io_in_b; // @[branch.scala 24:33:@717.4]
assign _T_14 = $unsigned(_T_13); // @[branch.scala 24:33:@718.4]
assign difference = _T_14[31:0]; // @[branch.scala 24:33:@719.4]
assign not_equal = difference != 32'h0; // @[branch.scala 25:36:@720.4]
assign equal = not_equal == 1'h0; // @[branch.scala 26:25:@721.4]
assign _T_17 = io_in_a[31]; // @[branch.scala 27:32:@722.4]
assign _T_18 = io_in_b[31]; // @[branch.scala 27:52:@723.4]
assign is_same_sign = _T_17 == _T_18; // @[branch.scala 27:41:@724.4]
assign _T_19 = difference[31]; // @[branch.scala 28:53:@725.4]
assign less_than = is_same_sign ? _T_19 : _T_17; // @[branch.scala 28:28:@727.4]
assign less_than_u = is_same_sign ? _T_19 : _T_18; // @[branch.scala 29:28:@730.4]
assign greater_equal = less_than == 1'h0; // @[branch.scala 30:25:@731.4]
assign greater_equal_u = less_than_u == 1'h0; // @[branch.scala 31:25:@732.4]
assign _T_25 = io_br_type == 3'h3; // @[branch.scala 35:18:@733.4]
assign _T_26 = _T_25 & equal; // @[branch.scala 35:30:@734.4]
assign _T_27 = io_br_type == 3'h6; // @[branch.scala 36:18:@735.4]
assign _T_28 = _T_27 & not_equal; // @[branch.scala 36:30:@736.4]
assign _T_29 = _T_26 | _T_28; // @[branch.scala 35:40:@737.4]
assign _T_30 = io_br_type == 3'h2; // @[branch.scala 37:18:@738.4]
assign _T_31 = _T_30 & less_than; // @[branch.scala 37:30:@739.4]
assign _T_32 = _T_29 | _T_31; // @[branch.scala 36:44:@740.4]
assign _T_33 = io_br_type == 3'h5; // @[branch.scala 38:18:@741.4]
assign _T_34 = _T_33 & greater_equal; // @[branch.scala 38:30:@742.4]
assign _T_35 = _T_32 | _T_34; // @[branch.scala 37:44:@743.4]
assign _T_36 = io_br_type == 3'h1; // @[branch.scala 39:18:@744.4]
assign _T_37 = _T_36 & less_than_u; // @[branch.scala 39:30:@745.4]
assign _T_38 = _T_35 | _T_37; // @[branch.scala 38:48:@746.4]
assign _T_39 = io_br_type == 3'h4; // @[branch.scala 40:18:@747.4]
assign _T_40 = _T_39 & greater_equal_u; // @[branch.scala 40:30:@748.4]
assign io_br_taken = _T_38 | _T_40; // @[branch.scala 34:15:@750.4]
endmodule
| 7.283413 |
module DMem_Interface ( // @[:@1967.2]
input clock, // @[:@1968.4]
input reset, // @[:@1969.4]
input [15:0] io_wbs_m2s_addr, // @[:@1970.4]
input [31:0] io_wbs_m2s_data, // @[:@1970.4]
input io_wbs_m2s_we, // @[:@1970.4]
input [ 3:0] io_wbs_m2s_sel, // @[:@1970.4]
input io_wbs_m2s_stb, // @[:@1970.4]
output io_wbs_ack_o, // @[:@1970.4]
output [31:0] io_wbs_data_o // @[:@1970.4]
);
wire dmem_clock; // @[dmem_interface.scala 35:20:@1972.4]
wire [10:0] dmem_io_dmem_addr; // @[dmem_interface.scala 35:20:@1972.4]
wire [31:0] dmem_io_dmem_wdata; // @[dmem_interface.scala 35:20:@1972.4]
wire [31:0] dmem_io_dmem_rdata; // @[dmem_interface.scala 35:20:@1972.4]
wire dmem_io_wr_en; // @[dmem_interface.scala 35:20:@1972.4]
wire [3:0] dmem_io_st_type; // @[dmem_interface.scala 35:20:@1972.4]
wire [3:0] _T_35; // @[dmem_interface.scala 37:41:@1975.4]
wire dmem_addr_match; // @[dmem_interface.scala 37:79:@1976.4]
wire dmem_select; // @[dmem_interface.scala 39:41:@1977.4]
wire _T_44; // @[dmem_interface.scala 40:26:@1978.4]
reg ack2; // @[dmem_interface.scala 48:28:@1986.4]
reg [31:0] _RAND_0;
wire dmem_res_en; // @[dmem_interface.scala 49:49:@1988.4]
wire _GEN_0; // @[dmem_interface.scala 51:21:@1989.4]
reg ack; // @[dmem_interface.scala 55:28:@1993.4]
reg [31:0] _RAND_1;
reg rd_resp; // @[dmem_interface.scala 60:24:@1998.4]
reg [31:0] _RAND_2;
DMem dmem ( // @[dmem_interface.scala 35:20:@1972.4]
.clock(dmem_clock),
.io_dmem_addr(dmem_io_dmem_addr),
.io_dmem_wdata(dmem_io_dmem_wdata),
.io_dmem_rdata(dmem_io_dmem_rdata),
.io_wr_en(dmem_io_wr_en),
.io_st_type(dmem_io_st_type)
);
assign _T_35 = io_wbs_m2s_addr[15:12]; // @[dmem_interface.scala 37:41:@1975.4]
assign dmem_addr_match = _T_35 == 4'h1; // @[dmem_interface.scala 37:79:@1976.4]
assign dmem_select = io_wbs_m2s_stb & dmem_addr_match; // @[dmem_interface.scala 39:41:@1977.4]
assign _T_44 = io_wbs_m2s_we == 1'h0; // @[dmem_interface.scala 40:26:@1978.4]
assign dmem_res_en = ack2 ^ io_wbs_m2s_stb; // @[dmem_interface.scala 49:49:@1988.4]
assign _GEN_0 = dmem_res_en ? io_wbs_m2s_stb : ack2; // @[dmem_interface.scala 51:21:@1989.4]
assign io_wbs_ack_o = ack | ack2; // @[dmem_interface.scala 57:18:@1997.4]
assign io_wbs_data_o = rd_resp ? dmem_io_dmem_rdata : 32'h0; // @[dmem_interface.scala 62:18:@2001.4]
assign dmem_clock = clock; // @[:@1973.4]
assign dmem_io_dmem_addr = io_wbs_m2s_addr[10:0]; // @[dmem_interface.scala 42:23:@1981.4]
assign dmem_io_dmem_wdata = io_wbs_m2s_data; // @[dmem_interface.scala 43:23:@1982.4]
assign dmem_io_wr_en = io_wbs_m2s_we & dmem_select; // @[dmem_interface.scala 44:23:@1984.4]
assign dmem_io_st_type = io_wbs_m2s_sel; // @[dmem_interface.scala 45:23:@1985.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
ack2 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
ack = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
rd_resp = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
ack2 <= 1'h0;
end else begin
if (dmem_res_en) begin
ack2 <= io_wbs_m2s_stb;
end
end
if (reset) begin
ack <= 1'h0;
end else begin
ack <= io_wbs_m2s_stb;
end
rd_resp <= _T_44 & dmem_select;
end
endmodule
| 6.797058 |
module soc_usb #(
parameter integer DW = 32
) (
// USB
inout wire usb_dp,
inout wire usb_dn,
output wire usb_pu,
// Wishbone slave
input wire [ 11:0] wb_addr,
output wire [DW-1:0] wb_rdata,
input wire [DW-1:0] wb_wdata,
input wire wb_we,
input wire [ 1:0] wb_cyc,
output wire [ 1:0] wb_ack,
// Misc
output wire usb_sof,
// Clock / Reset
input wire clk_sys,
input wire clk_48m,
input wire rst
);
// Signals
// -------
// Bus OR
wire [DW-1:0] wb_rdata_i [0:1];
// Wishbone in 48 MHz domain
wire [ 11:0] ub_addr;
wire [ 15:0] ub_wdata;
wire [ 15:0] ub_rdata;
wire ub_cyc;
wire ub_we;
wire ub_ack;
// SoF in 48 MHz domain
wire usb_sof_48m;
// EP Buffer
wire [ 8:0] ep_tx_addr_0;
wire [ 31:0] ep_tx_data_0;
wire ep_tx_we_0;
wire [ 8:0] ep_rx_addr_0;
wire [ 31:0] ep_rx_data_1;
wire ep_rx_re_0;
reg ack_ep;
// Cross-clock
// -----------
// Bring control reg wishbone to 48 MHz domain
xclk_wb #(
.DW(16),
.AW(12)
) wb_48m_xclk_I (
.s_addr (wb_addr[11:0]),
.s_wdata(wb_wdata[15:0]),
.s_rdata(wb_rdata_i[0][15:0]),
.s_cyc (wb_cyc[0]),
.s_ack (wb_ack[0]),
.s_we (wb_we),
.s_clk (clk_sys),
.m_addr (ub_addr),
.m_wdata(ub_wdata),
.m_rdata(ub_rdata),
.m_cyc (ub_cyc),
.m_ack (ub_ack),
.m_we (ub_we),
.m_clk (clk_48m),
.rst (rst)
);
if (DW != 16) assign wb_rdata_i[0][DW-1:16] = 0;
xclk_strobe sof_xclk_I (
.in_stb (usb_sof_48m),
.in_clk (clk_48m),
.out_stb(usb_sof),
.out_clk(clk_sys),
.rst (rst)
);
// Core
// ----
usb #(
.EPDW(32)
) usb_I (
.pad_dp (usb_dp),
.pad_dn (usb_dn),
.pad_pu (usb_pu),
.ep_tx_addr_0(ep_tx_addr_0),
.ep_tx_data_0(ep_tx_data_0),
.ep_tx_we_0 (ep_tx_we_0),
.ep_rx_addr_0(ep_rx_addr_0),
.ep_rx_data_1(ep_rx_data_1),
.ep_rx_re_0 (ep_rx_re_0),
.ep_clk (clk_sys),
.wb_addr (ub_addr),
.wb_rdata (ub_rdata),
.wb_wdata (ub_wdata),
.wb_we (ub_we),
.wb_cyc (ub_cyc),
.wb_ack (ub_ack),
.sof (usb_sof_48m),
.clk (clk_48m),
.rst (rst)
);
// EP data
// -------
assign ep_tx_addr_0 = wb_addr[8:0];
assign ep_rx_addr_0 = wb_addr[8:0];
assign ep_tx_data_0 = wb_wdata;
assign wb_rdata_i[1] = ack_ep ? ep_rx_data_1 : 32'h00000000;
assign ep_tx_we_0 = wb_cyc[1] & wb_we & ~ack_ep;
assign ep_rx_re_0 = 1'b1;
assign wb_ack[1] = ack_ep;
always @(posedge clk_sys or posedge rst)
if (rst) ack_ep <= 1'b0;
else ack_ep <= wb_cyc[1] & ~ack_ep;
// Bus read data
// -------------
assign wb_rdata = wb_rdata_i[0] | wb_rdata_i[1];
endmodule
| 6.65512 |
module uart_flip (
input in_txd,
output in_rxd,
output out_txd,
input out_rxd
);
assign out_txd = in_txd;
assign in_rxd = out_rxd;
endmodule
| 9.0395 |
module soc_zedboard_top (
VGA_blue,
VGA_clk,
VGA_de,
VGA_green,
VGA_hsync,
VGA_red,
VGA_vsync
);
output [3:0] VGA_blue;
output VGA_clk;
output VGA_de;
output [3:0] VGA_green;
output VGA_hsync;
output [3:0] VGA_red;
output VGA_vsync;
wire [3:0] VGA_blue;
wire VGA_clk;
wire VGA_de;
wire [3:0] VGA_green;
wire VGA_hsync;
wire [3:0] VGA_red;
wire VGA_vsync;
noop_design noop_design_i (
.VGA_blue(VGA_blue),
.VGA_clk(VGA_clk),
.VGA_de(VGA_de),
.VGA_green(VGA_green),
.VGA_hsync(VGA_hsync),
.VGA_red(VGA_red),
.VGA_vsync(VGA_vsync)
);
endmodule
| 7.028835 |
module sofa_plus_io (
input SOC_IN, // Input to drive the inpad signal
output SOC_OUT, // Output the outpad signal
output SOC_DIR, // Output the directionality
output FPGA_IN, // Input data to FPGA
input FPGA_OUT, // Output data from FPGA
input FPGA_DIR, // direction control
input IO_ISOL_N // Isolation enable signal
);
wire SOC_DIR_N;
// Use drive-strength 4 for a high fan-out from SoC components
sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE (
.B_N(IO_ISOL_N),
.A (FPGA_DIR),
.X (SOC_DIR)
);
// Use drive-strength 4 for a high fan-out from global routing architecture
sky130_fd_sc_hd__inv_1 INV_SOC_DIR (
.A(SOC_DIR),
.Y(SOC_DIR_N)
);
sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE (
.TE_B(SOC_DIR_N),
.A(SOC_IN),
.Z(FPGA_IN)
);
// Use drive-strength 4 for a potential high fan-out from SoC components
sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE (
.TE_B(SOC_DIR),
.A(FPGA_OUT),
.Z(SOC_OUT)
);
endmodule
| 6.625884 |
module SOFController (
HCTxPortCntl,
HCTxPortData,
HCTxPortGnt,
HCTxPortRdy,
HCTxPortReq,
HCTxPortWEn,
SOFEnable,
SOFTimerClr,
SOFTimer,
clk,
rst
);
input HCTxPortGnt;
input HCTxPortRdy;
input SOFEnable;
input SOFTimerClr;
input clk;
input rst;
output [7:0] HCTxPortCntl;
output [7:0] HCTxPortData;
output HCTxPortReq;
output HCTxPortWEn;
output [15:0] SOFTimer;
reg [7:0] HCTxPortCntl, next_HCTxPortCntl;
reg [7:0] HCTxPortData, next_HCTxPortData;
wire HCTxPortGnt;
wire HCTxPortRdy;
reg HCTxPortReq, next_HCTxPortReq;
reg HCTxPortWEn, next_HCTxPortWEn;
wire SOFEnable;
wire SOFTimerClr;
reg [15:0] SOFTimer, next_SOFTimer;
wire clk;
wire rst;
// BINARY ENCODED state machine: sofCntl
// State codes definitions:
`define START_SC 3'b000
`define WAIT_SOF_EN 3'b001
`define WAIT_SEND_RESUME 3'b010
`define INC_TIMER 3'b011
`define SC_WAIT_GNT 3'b100
`define CLR_WEN 3'b101
reg [2:0] CurrState_sofCntl;
reg [2:0] NextState_sofCntl;
//--------------------------------------------------------------------
// Machine: sofCntl
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (SOFTimerClr or SOFTimer or SOFEnable or HCTxPortRdy or HCTxPortGnt or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or CurrState_sofCntl)
begin : sofCntl_NextState
NextState_sofCntl <= CurrState_sofCntl;
// Set default values for outputs and signals
next_HCTxPortReq <= HCTxPortReq;
next_HCTxPortWEn <= HCTxPortWEn;
next_HCTxPortData <= HCTxPortData;
next_HCTxPortCntl <= HCTxPortCntl;
next_SOFTimer <= SOFTimer;
case (CurrState_sofCntl)
`START_SC: NextState_sofCntl <= `WAIT_SOF_EN;
`WAIT_SOF_EN:
if (SOFEnable == 1'b1) begin
NextState_sofCntl <= `SC_WAIT_GNT;
next_HCTxPortReq <= 1'b1;
end
`WAIT_SEND_RESUME:
if (HCTxPortRdy == 1'b1) begin
NextState_sofCntl <= `CLR_WEN;
next_HCTxPortWEn <= 1'b1;
next_HCTxPortData <= 8'h00;
next_HCTxPortCntl <= `TX_RESUME_START;
end
`INC_TIMER: begin
next_HCTxPortReq <= 1'b0;
if (SOFTimerClr == 1'b1) next_SOFTimer <= 16'h0000;
else next_SOFTimer <= SOFTimer + 1'b1;
if (SOFEnable == 1'b0) begin
NextState_sofCntl <= `WAIT_SOF_EN;
next_SOFTimer <= 16'h0000;
end
end
`SC_WAIT_GNT: if (HCTxPortGnt == 1'b1) NextState_sofCntl <= `WAIT_SEND_RESUME;
`CLR_WEN: begin
next_HCTxPortWEn <= 1'b0;
NextState_sofCntl <= `INC_TIMER;
end
endcase
end
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @(posedge clk) begin : sofCntl_CurrentState
if (rst) CurrState_sofCntl <= `START_SC;
else CurrState_sofCntl <= NextState_sofCntl;
end
//----------------------------------
// Registered outputs logic
//----------------------------------
always @(posedge clk) begin : sofCntl_RegOutput
if (rst) begin
SOFTimer <= 16'h0000;
HCTxPortCntl <= 8'h00;
HCTxPortData <= 8'h00;
HCTxPortWEn <= 1'b0;
HCTxPortReq <= 1'b0;
end else begin
SOFTimer <= next_SOFTimer;
HCTxPortCntl <= next_HCTxPortCntl;
HCTxPortData <= next_HCTxPortData;
HCTxPortWEn <= next_HCTxPortWEn;
HCTxPortReq <= next_HCTxPortReq;
end
end
endmodule
| 8.563811 |
module SOFController_simlib (
HCTxPortCntl,
HCTxPortData,
HCTxPortGnt,
HCTxPortRdy,
HCTxPortReq,
HCTxPortWEn,
SOFEnable,
SOFTimerClr,
SOFTimer,
clk,
rst
);
input HCTxPortGnt;
input HCTxPortRdy;
input SOFEnable;
input SOFTimerClr;
input clk;
input rst;
output [7:0] HCTxPortCntl;
output [7:0] HCTxPortData;
output HCTxPortReq;
output HCTxPortWEn;
output [15:0] SOFTimer;
reg [7:0] HCTxPortCntl, next_HCTxPortCntl;
reg [7:0] HCTxPortData, next_HCTxPortData;
wire HCTxPortGnt;
wire HCTxPortRdy;
reg HCTxPortReq, next_HCTxPortReq;
reg HCTxPortWEn, next_HCTxPortWEn;
wire SOFEnable;
wire SOFTimerClr;
reg [15:0] SOFTimer, next_SOFTimer;
wire clk;
wire rst;
// BINARY ENCODED state machine: sofCntl
// State codes definitions:
`define START_SC 3'b000
`define WAIT_SOF_EN 3'b001
`define WAIT_SEND_RESUME 3'b010
`define INC_TIMER 3'b011
`define SC_WAIT_GNT 3'b100
`define CLR_WEN 3'b101
reg [2:0] CurrState_sofCntl;
reg [2:0] NextState_sofCntl;
//--------------------------------------------------------------------
// Machine: sofCntl
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (SOFTimerClr or SOFTimer or SOFEnable or HCTxPortRdy or HCTxPortGnt or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or CurrState_sofCntl)
begin : sofCntl_NextState
NextState_sofCntl <= CurrState_sofCntl;
// Set default values for outputs and signals
next_HCTxPortReq <= HCTxPortReq;
next_HCTxPortWEn <= HCTxPortWEn;
next_HCTxPortData <= HCTxPortData;
next_HCTxPortCntl <= HCTxPortCntl;
next_SOFTimer <= SOFTimer;
case (CurrState_sofCntl)
`START_SC: NextState_sofCntl <= `WAIT_SOF_EN;
`WAIT_SOF_EN:
if (SOFEnable == 1'b1) begin
NextState_sofCntl <= `SC_WAIT_GNT;
next_HCTxPortReq <= 1'b1;
end
`WAIT_SEND_RESUME:
if (HCTxPortRdy == 1'b1) begin
NextState_sofCntl <= `CLR_WEN;
next_HCTxPortWEn <= 1'b1;
next_HCTxPortData <= 8'h00;
next_HCTxPortCntl <= `TX_RESUME_START;
end
`INC_TIMER: begin
next_HCTxPortReq <= 1'b0;
if (SOFTimerClr == 1'b1) next_SOFTimer <= 16'h0000;
else next_SOFTimer <= SOFTimer + 1'b1;
if (SOFEnable == 1'b0) begin
NextState_sofCntl <= `WAIT_SOF_EN;
next_SOFTimer <= 16'h0000;
end
end
`SC_WAIT_GNT: if (HCTxPortGnt == 1'b1) NextState_sofCntl <= `WAIT_SEND_RESUME;
`CLR_WEN: begin
next_HCTxPortWEn <= 1'b0;
NextState_sofCntl <= `INC_TIMER;
end
endcase
end
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @(posedge clk) begin : sofCntl_CurrentState
if (rst) CurrState_sofCntl <= `START_SC;
else CurrState_sofCntl <= NextState_sofCntl;
end
//----------------------------------
// Registered outputs logic
//----------------------------------
always @(posedge clk) begin : sofCntl_RegOutput
if (rst) begin
SOFTimer <= 16'h0000;
HCTxPortCntl <= 8'h00;
HCTxPortData <= 8'h00;
HCTxPortWEn <= 1'b0;
HCTxPortReq <= 1'b0;
end else begin
SOFTimer <= next_SOFTimer;
HCTxPortCntl <= next_HCTxPortCntl;
HCTxPortData <= next_HCTxPortData;
HCTxPortWEn <= next_HCTxPortWEn;
HCTxPortReq <= next_HCTxPortReq;
end
end
endmodule
| 8.563811 |
module SOFT (
input [11:0] code_address,
output reg [15:0] instruction
);
always @(code_address) begin
case (code_address)
12'b000000000000: instruction <= 16'b1101001000000100;
12'b000000000001: instruction <= 16'b0010001000000011;
12'b000000000010: instruction <= 16'b1100001000000000;
12'b000000000011: instruction <= 16'b1111001011111111;
12'b000000000100: instruction <= 16'b1010000000000011;
endcase
end
endmodule
| 8.260603 |
module softcore_top (
clk_clk,
reset_reset_n,
pio_export
);
input clk_clk;
input reset_reset_n;
output [7:0] pio_export;
endmodule
| 7.00222 |
module softcore_top_jtag_uart_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [7:0] r_dat;
wire wfifo_empty;
wire [5:0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk) begin
if (fifo_wr) $write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 7.320375 |
module softcore_top_jtag_uart_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear;
input [7:0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [7:0] r_dat;
wire wfifo_empty;
wire [5:0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
softcore_top_jtag_uart_0_sim_scfifo_w the_softcore_top_jtag_uart_0_sim_scfifo_w (
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty(wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 7.320375 |
module softcore_top_jtag_uart_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [31:0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7:0] fifo_rdata;
wire new_rom;
wire [31:0] num_bytes;
wire [ 6:0] rfifo_entries;
wire rfifo_full;
wire [ 5:0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n) begin
if (rst_n == 0) begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end else begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d) bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom) bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 7.320375 |
module softcore_top_jtag_uart_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [7:0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [7:0] fifo_rdata;
wire rfifo_full;
wire [5:0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
softcore_top_jtag_uart_0_sim_scfifo_r the_softcore_top_jtag_uart_0_sim_scfifo_r (
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata(fifo_rdata),
.rfifo_full(rfifo_full),
.rfifo_used(rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 7.320375 |
module softcore_top_nios2_gen2_0_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire [31:0] q;
wire [31:0] ram_data;
wire [31:0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram (
.address_a(wraddress),
.address_b(rdaddress),
.clock0(clock),
.data_a(ram_data),
.q_b(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0", the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0, the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32, the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32, the_altsyncram.widthad_a = 5, the_altsyncram.widthad_b = 5;
endmodule
| 7.320375 |
module softcore_top_nios2_gen2_0_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire [31:0] q;
wire [31:0] ram_data;
wire [31:0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram (
.address_a(wraddress),
.address_b(rdaddress),
.clock0(clock),
.data_a(ram_data),
.q_b(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0", the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0, the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32, the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32, the_altsyncram.widthad_a = 5, the_altsyncram.widthad_b = 5;
endmodule
| 7.320375 |
module softcore_top_nios2_gen2_0_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
3'b000: begin
td_mode = 4'b0000;
end // 3'b000
3'b001: begin
td_mode = 4'b1000;
end // 3'b001
3'b010: begin
td_mode = 4'b0100;
end // 3'b010
3'b011: begin
td_mode = 4'b1100;
end // 3'b011
3'b100: begin
td_mode = 4'b0010;
end // 3'b100
3'b101: begin
td_mode = 4'b1010;
end // 3'b101
3'b110: begin
td_mode = 4'b0101;
end // 3'b110
3'b111: begin
td_mode = 4'b1111;
end // 3'b111
endcase // ctrl_bits_for_mux
end
endmodule
| 7.320375 |
module softcore_top_nios2_gen2_0_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [17:0] cpu_d_address;
input cpu_d_read;
input [31:0] cpu_d_readdata;
input cpu_d_wait;
input cpu_d_write;
input [31:0] cpu_d_writedata;
input jrst_n;
input [15:0] trc_ctrl;
reg [35:0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [31:0] cpu_d_address_0_padded;
wire [31:0] cpu_d_readdata_0_padded;
wire [31:0] cpu_d_writedata_0_padded;
reg [35:0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dummy_tie_off;
wire record_load_addr;
wire record_load_data;
wire record_store_addr;
wire record_store_data;
wire [ 3:0] td_mode_trc_ctrl;
assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
//softcore_top_nios2_gen2_0_cpu_nios2_oci_trc_ctrl_td_mode, which is an e_instance
softcore_top_nios2_gen2_0_cpu_nios2_oci_td_mode softcore_top_nios2_gen2_0_cpu_nios2_oci_trc_ctrl_td_mode
(
.ctrl (trc_ctrl[8 : 0]),
.td_mode(td_mode_trc_ctrl)
);
assign {record_load_addr, record_store_addr,
record_load_data, record_store_data} = td_mode_trc_ctrl;
always @(posedge clk or negedge jrst_n) begin
if (jrst_n == 0) begin
atm <= 0;
dtm <= 0;
end else begin
atm <= 0;
dtm <= 0;
end
end
assign dummy_tie_off = cpu_d_wait | cpu_d_read | cpu_d_write;
endmodule
| 7.320375 |
module softcore_top_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
);
output [1:0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_input_tm_cnt;
wire [2:0] switch_for_mux;
assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
always @(switch_for_mux) begin
case (switch_for_mux)
3'b000: begin
compute_input_tm_cnt = 0;
end // 3'b000
3'b001: begin
compute_input_tm_cnt = 1;
end // 3'b001
3'b010: begin
compute_input_tm_cnt = 1;
end // 3'b010
3'b011: begin
compute_input_tm_cnt = 2;
end // 3'b011
3'b100: begin
compute_input_tm_cnt = 1;
end // 3'b100
3'b101: begin
compute_input_tm_cnt = 2;
end // 3'b101
3'b110: begin
compute_input_tm_cnt = 2;
end // 3'b110
3'b111: begin
compute_input_tm_cnt = 3;
end // 3'b111
endcase // switch_for_mux
end
endmodule
| 7.320375 |
module softcore_top_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
);
output [3:0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [3:0] fifo_wrptr_inc;
always @(ge2_free or ge3_free or input_tm_cnt) begin
if (ge3_free & (input_tm_cnt == 3)) fifo_wrptr_inc = 3;
else if (ge2_free & (input_tm_cnt >= 2)) fifo_wrptr_inc = 2;
else if (input_tm_cnt >= 1) fifo_wrptr_inc = 1;
else fifo_wrptr_inc = 0;
end
endmodule
| 7.320375 |
module softcore_top_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
);
output [4:0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [4:0] fifo_cnt_inc;
always @(empty or ge2_free or ge3_free or input_tm_cnt) begin
if (empty) fifo_cnt_inc = input_tm_cnt[1 : 0];
else if (ge3_free & (input_tm_cnt == 3)) fifo_cnt_inc = 2;
else if (ge2_free & (input_tm_cnt >= 2)) fifo_cnt_inc = 1;
else if (input_tm_cnt >= 1) fifo_cnt_inc = 0;
else fifo_cnt_inc = {5{1'b1}};
end
endmodule
| 7.320375 |
module softcore_top_nios2_gen2_0_cpu_nios2_oci_pib (
// outputs:
tr_data
);
output [35:0] tr_data;
wire [35:0] tr_data;
assign tr_data = 0;
endmodule
| 7.320375 |
module softcore_top_nios2_gen2_0_cpu_nios2_oci_im (
// inputs:
clk,
jrst_n,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
);
output tracemem_on;
output [35:0] tracemem_trcdata;
output tracemem_tw;
output [6:0] trc_im_addr;
output trc_wrap;
output xbrk_wrap_traceoff;
input clk;
input jrst_n;
input [15:0] trc_ctrl;
input [35:0] tw;
wire tracemem_on;
wire [35:0] tracemem_trcdata;
wire tracemem_tw;
reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [35:0] trc_im_data;
wire trc_on_chip;
reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire tw_valid;
wire xbrk_wrap_traceoff;
assign trc_im_data = tw;
always @(posedge clk or negedge jrst_n) begin
if (jrst_n == 0) begin
trc_im_addr <= 0;
trc_wrap <= 0;
end else begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
end
assign trc_on_chip = ~trc_ctrl[8];
assign tw_valid = |trc_im_data[35 : 32];
assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
assign tracemem_trcdata = 0;
endmodule
| 7.320375 |
module softcore_top_nios2_gen2_0_cpu_nios2_performance_monitors;
endmodule
| 7.320375 |
module softcore_top_nios2_gen2_0_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
);
output [31:0] oci_ienable;
output [31:0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [8:0] address;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [31:0] writedata;
reg [31:0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [31:0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) oci_single_step_mode <= 1'b0;
else if (take_action_ocireg) oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) oci_ienable <= 32'b00000000000000000000000000000011;
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000000000000000000011);
end
endmodule
| 7.320375 |
module softcore_top_nios2_gen2_0_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input [7:0] address;
input [3:0] byteenable;
input clock;
input [31:0] data;
input reset_req;
input wren;
wire clocken;
wire [31:0] q;
wire [31:0] ram_q;
assign q = ram_q;
assign clocken = ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clock),
.clocken0(clocken),
.data_a(data),
.q_a(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.init_file = lpm_file, the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 256, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 8;
endmodule
| 7.320375 |
module softcore_top_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "softcore_top_onchip_memory2_0.hex";
output [31:0] readdata;
input [13:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input freeze;
input reset;
input reset_req;
input write;
input [31:0] writedata;
wire clocken0;
wire [31:0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clk),
.clocken0(clocken0),
.data_a(writedata),
.q_a(readdata),
.wren_a(wren)
);
defparam the_altsyncram.byte_size = 8, the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram", the_altsyncram.maximum_depth = 16384,
the_altsyncram.numwords_a = 16384, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 14;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
| 7.320375 |
module softcore_top_pio_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [7:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:0] writedata;
wire clk_en;
reg [ 7:0] data_out;
wire [ 7:0] out_port;
wire [ 7:0] read_mux_out;
wire [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8{(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else if (chipselect && ~write_n && (address == 0)) data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
| 7.320375 |
module softcore_top_tb ();
wire softcore_top_inst_clk_bfm_clk_clk; // softcore_top_inst_clk_bfm:clk -> [softcore_top_inst:clk_clk, softcore_top_inst_reset_bfm:clk]
wire softcore_top_inst_reset_bfm_reset_reset; // softcore_top_inst_reset_bfm:reset -> softcore_top_inst:reset_reset_n
softcore_top softcore_top_inst (
.clk_clk (softcore_top_inst_clk_bfm_clk_clk), // clk.clk
.pio_export (), // pio.export
.reset_reset_n(softcore_top_inst_reset_bfm_reset_reset) // reset.reset_n
);
altera_avalon_clock_source #(
.CLOCK_RATE(50000000),
.CLOCK_UNIT(1)
) softcore_top_inst_clk_bfm (
.clk(softcore_top_inst_clk_bfm_clk_clk) // clk.clk
);
altera_avalon_reset_source #(
.ASSERT_HIGH_RESET (0),
.INITIAL_RESET_CYCLES(50)
) softcore_top_inst_reset_bfm (
.reset(softcore_top_inst_reset_bfm_reset_reset), // reset.reset_n
.clk (softcore_top_inst_clk_bfm_clk_clk) // clk.clk
);
endmodule
| 7.320375 |
module
module softmax(input clk, input [15:0] data_in [1024], output reg [15:0] data_out [1024]);
// Define the number of DSP slices to use for the softmax operation
parameter num_dsp_slices = 8;
// Define the storage registers for the softmax operation
reg [15:0] softmax_output [1024];
// Define the DSP slices for the softmax operation
reg [15:0] dsp_slice [num_dsp_slices];
// Compute the exponent of each input value
reg [15:0] exp_input [1024];
for (int i = 0; i < 1024; i++) {
exp_input[i] = exp(data_in[i]);
}
// Compute the sum of the exponentiated input values using DSP slices
for (int i = 0; i < num_dsp_slices; i++) {
DSP48E1 #(.INIT_N(0), .INIT_X(0)) dsp_slice(.A(exp_input[i]), .B(exp_input[i+1]), .P(dsp_slice[i])
);
}
// Compute the softmax operation on the input values using DSP slices
for (int i = 0; i < num_dsp_slices; i++) {
DSP48E1 #(.INIT_N(0), .INIT_X(0)) dsp_slice(.A(exp_input[i]), .B(dsp_slice[i]), .P(softmax_output[i])
);
}
// Store the final softmax output in the data_out register
data_out = softmax_output;
endmodule
| 7.880853 |
module softmax_invert_tadEe_rom (
addr0,
ce0,
q0,
addr1,
ce1,
q1,
addr2,
ce2,
q2,
addr3,
ce3,
q3,
addr4,
ce4,
q4,
clk
);
parameter DWIDTH = 15;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input [AWIDTH-1:0] addr2;
input ce2;
output reg [DWIDTH-1:0] q2;
input [AWIDTH-1:0] addr3;
input ce3;
output reg [DWIDTH-1:0] q3;
input [AWIDTH-1:0] addr4;
input ce4;
output reg [DWIDTH-1:0] q4;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram0[0:MEM_SIZE-1];
(* ram_style = "block" *)reg [DWIDTH-1:0] ram1[0:MEM_SIZE-1];
(* ram_style = "block" *)reg [DWIDTH-1:0] ram2[0:MEM_SIZE-1];
initial begin
$readmemh("./softmax_invert_tadEe_rom.dat", ram0);
$readmemh("./softmax_invert_tadEe_rom.dat", ram1);
$readmemh("./softmax_invert_tadEe_rom.dat", ram2);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram0[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram0[addr1];
end
end
always @(posedge clk) begin
if (ce2) begin
q2 <= ram1[addr2];
end
end
always @(posedge clk) begin
if (ce3) begin
q3 <= ram1[addr3];
end
end
always @(posedge clk) begin
if (ce4) begin
q4 <= ram2[addr4];
end
end
endmodule
| 6.759082 |
module softmax_invert_tadEe (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1,
address2,
ce2,
q2,
address3,
ce3,
q3,
address4,
ce4,
q4
);
parameter DataWidth = 32'd15;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
input [AddressWidth - 1:0] address2;
input ce2;
output [DataWidth - 1:0] q2;
input [AddressWidth - 1:0] address3;
input ce3;
output [DataWidth - 1:0] q3;
input [AddressWidth - 1:0] address4;
input ce4;
output [DataWidth - 1:0] q4;
softmax_invert_tadEe_rom softmax_invert_tadEe_rom_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.q1(q1),
.addr2(address2),
.ce2(ce2),
.q2(q2),
.addr3(address3),
.ce3(ce3),
.q3(q3),
.addr4(address4),
.ce4(ce4),
.q4(q4)
);
endmodule
| 6.759082 |
module softmax_invert_tafYi_rom (
addr0,
ce0,
q0,
addr1,
ce1,
q1,
addr2,
ce2,
q2,
addr3,
ce3,
q3,
addr4,
ce4,
q4,
clk
);
parameter DWIDTH = 15;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input [AWIDTH-1:0] addr2;
input ce2;
output reg [DWIDTH-1:0] q2;
input [AWIDTH-1:0] addr3;
input ce3;
output reg [DWIDTH-1:0] q3;
input [AWIDTH-1:0] addr4;
input ce4;
output reg [DWIDTH-1:0] q4;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram0[0:MEM_SIZE-1];
(* ram_style = "block" *)reg [DWIDTH-1:0] ram1[0:MEM_SIZE-1];
(* ram_style = "block" *)reg [DWIDTH-1:0] ram2[0:MEM_SIZE-1];
initial begin
$readmemh("./softmax_invert_tafYi_rom.dat", ram0);
$readmemh("./softmax_invert_tafYi_rom.dat", ram1);
$readmemh("./softmax_invert_tafYi_rom.dat", ram2);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram0[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram0[addr1];
end
end
always @(posedge clk) begin
if (ce2) begin
q2 <= ram1[addr2];
end
end
always @(posedge clk) begin
if (ce3) begin
q3 <= ram1[addr3];
end
end
always @(posedge clk) begin
if (ce4) begin
q4 <= ram2[addr4];
end
end
endmodule
| 6.759082 |
module softmax_invert_tafYi (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1,
address2,
ce2,
q2,
address3,
ce3,
q3,
address4,
ce4,
q4
);
parameter DataWidth = 32'd15;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
input [AddressWidth - 1:0] address2;
input ce2;
output [DataWidth - 1:0] q2;
input [AddressWidth - 1:0] address3;
input ce3;
output [DataWidth - 1:0] q3;
input [AddressWidth - 1:0] address4;
input ce4;
output [DataWidth - 1:0] q4;
softmax_invert_tafYi_rom softmax_invert_tafYi_rom_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.q1(q1),
.addr2(address2),
.ce2(ce2),
.q2(q2),
.addr3(address3),
.ce3(ce3),
.q3(q3),
.addr4(address4),
.ce4(ce4),
.q4(q4)
);
endmodule
| 6.759082 |
module softmax_latency_ap_fixed_ap_fixed_softmax_config13_s_exp_bkb_rom (
addr0,
ce0,
q0,
addr1,
ce1,
q1,
addr2,
ce2,
q2,
addr3,
ce3,
q3,
addr4,
ce4,
q4,
clk
);
parameter DWIDTH = 18;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input [AWIDTH-1:0] addr2;
input ce2;
output reg [DWIDTH-1:0] q2;
input [AWIDTH-1:0] addr3;
input ce3;
output reg [DWIDTH-1:0] q3;
input [AWIDTH-1:0] addr4;
input ce4;
output reg [DWIDTH-1:0] q4;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram0[0:MEM_SIZE-1];
(* ram_style = "block" *)reg [DWIDTH-1:0] ram1[0:MEM_SIZE-1];
(* ram_style = "block" *)reg [DWIDTH-1:0] ram2[0:MEM_SIZE-1];
initial begin
$readmemh("./softmax_latency_ap_fixed_ap_fixed_softmax_config13_s_exp_bkb_rom.dat", ram0);
$readmemh("./softmax_latency_ap_fixed_ap_fixed_softmax_config13_s_exp_bkb_rom.dat", ram1);
$readmemh("./softmax_latency_ap_fixed_ap_fixed_softmax_config13_s_exp_bkb_rom.dat", ram2);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram0[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram0[addr1];
end
end
always @(posedge clk) begin
if (ce2) begin
q2 <= ram1[addr2];
end
end
always @(posedge clk) begin
if (ce3) begin
q3 <= ram1[addr3];
end
end
always @(posedge clk) begin
if (ce4) begin
q4 <= ram2[addr4];
end
end
endmodule
| 7.116033 |
module softmax_latency_ap_fixed_ap_fixed_softmax_config13_s_exp_bkb (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1,
address2,
ce2,
q2,
address3,
ce3,
q3,
address4,
ce4,
q4
);
parameter DataWidth = 32'd18;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
input [AddressWidth - 1:0] address2;
input ce2;
output [DataWidth - 1:0] q2;
input [AddressWidth - 1:0] address3;
input ce3;
output [DataWidth - 1:0] q3;
input [AddressWidth - 1:0] address4;
input ce4;
output [DataWidth - 1:0] q4;
softmax_latency_ap_fixed_ap_fixed_softmax_config13_s_exp_bkb_rom softmax_latency_ap_fixed_ap_fixed_softmax_config13_s_exp_bkb_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.q1(q1),
.addr2(address2),
.ce2(ce2),
.q2(q2),
.addr3(address3),
.ce3(ce3),
.q3(q3),
.addr4(address4),
.ce4(ce4),
.q4(q4)
);
endmodule
| 7.116033 |
module softmax_latency_ap_fixed_ap_fixed_softmax_config13_s_invecud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 14;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./softmax_latency_ap_fixed_ap_fixed_softmax_config13_s_invecud_rom.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 7.116033 |
module softmax_latency_ap_fixed_ap_fixed_softmax_config13_s_invecud (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd14;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
softmax_latency_ap_fixed_ap_fixed_softmax_config13_s_invecud_rom softmax_latency_ap_fixed_ap_fixed_softmax_config13_s_invecud_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 7.116033 |
module softmax_latency_array_array_ap_fixed_5u_softmax_config9_sbkb_rom (
addr0,
ce0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 18;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./softmax_latency_array_array_ap_fixed_5u_softmax_config9_sbkb_rom.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram[addr1];
end
end
endmodule
| 7.116033 |
module softmax_latency_array_array_ap_fixed_5u_softmax_config9_sbkb (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd18;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
softmax_latency_array_array_ap_fixed_5u_softmax_config9_sbkb_rom softmax_latency_array_array_ap_fixed_5u_softmax_config9_sbkb_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.q1(q1)
);
endmodule
| 7.116033 |
module softmax_latency_array_array_ap_fixed_5u_softmax_config9_scud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 14;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./softmax_latency_array_array_ap_fixed_5u_softmax_config9_scud_rom.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 7.116033 |
module softmax_latency_array_array_ap_fixed_5u_softmax_config9_scud (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd14;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
softmax_latency_array_array_ap_fixed_5u_softmax_config9_scud_rom softmax_latency_array_array_ap_fixed_5u_softmax_config9_scud_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 7.116033 |
module softmax_latency_array_array_softmax_config11_s_exp_table_rom (
addr0,
ce0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 18;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./softmax_latency_array_array_softmax_config11_s_exp_table_rom.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram[addr1];
end
end
endmodule
| 7.116033 |
module softmax_latency_array_array_softmax_config11_s_exp_table (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd18;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
softmax_latency_array_array_softmax_config11_s_exp_table_rom softmax_latency_array_array_softmax_config11_s_exp_table_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.q1(q1)
);
endmodule
| 7.116033 |
module softmax_latency_array_array_softmax_config11_s_invert_tabbkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 14;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./softmax_latency_array_array_softmax_config11_s_invert_tabbkb_rom.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 7.116033 |
module softmax_latency_array_array_softmax_config11_s_invert_tabbkb (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd14;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
softmax_latency_array_array_softmax_config11_s_invert_tabbkb_rom softmax_latency_array_array_softmax_config11_s_invert_tabbkb_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 7.116033 |
module softmax_latency_array_array_softmax_config5_s_exp_table_rom (
addr0,
ce0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 18;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./softmax_latency_array_array_softmax_config5_s_exp_table_rom.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram[addr1];
end
end
endmodule
| 7.116033 |
module softmax_latency_array_array_softmax_config5_s_exp_table (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd18;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
softmax_latency_array_array_softmax_config5_s_exp_table_rom softmax_latency_array_array_softmax_config5_s_exp_table_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.q1(q1)
);
endmodule
| 7.116033 |
module softmax_latency_array_array_softmax_config5_s_invert_table3_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 14;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./softmax_latency_array_array_softmax_config5_s_invert_table3_rom.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 7.116033 |
module softmax_latency_array_array_softmax_config5_s_invert_table3 (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd14;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
softmax_latency_array_array_softmax_config5_s_invert_table3_rom softmax_latency_array_array_softmax_config5_s_invert_table3_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 7.116033 |
module softMC_pcie_app #(
parameter C_PCI_DATA_WIDTH = 9'd32,
DQ_WIDTH = 64
) (
input clk,
input rst,
output CHNL_RX_CLK,
input CHNL_RX,
output reg CHNL_RX_ACK,
input CHNL_RX_LAST,
input [31:0] CHNL_RX_LEN,
input [30:0] CHNL_RX_OFF,
input [C_PCI_DATA_WIDTH-1:0] CHNL_RX_DATA,
input CHNL_RX_DATA_VALID,
output CHNL_RX_DATA_REN,
output CHNL_TX_CLK,
output reg CHNL_TX,
input CHNL_TX_ACK,
output CHNL_TX_LAST,
output reg [31:0] CHNL_TX_LEN,
output [30:0] CHNL_TX_OFF,
output [C_PCI_DATA_WIDTH-1:0] CHNL_TX_DATA,
output reg CHNL_TX_DATA_VALID,
input CHNL_TX_DATA_REN,
output app_en,
input app_ack,
output [31:0] app_instr,
//Data read back Interface
input rdback_fifo_empty,
output rdback_fifo_rden,
input [DQ_WIDTH*4 - 1:0] rdback_data
);
assign CHNL_RX_CLK = clk;
assign CHNL_TX_CLK = clk;
assign CHNL_TX_OFF = 0;
assign CHNL_TX_LAST = 1'd1;
reg app_en_r;
reg [C_PCI_DATA_WIDTH-1:0] rx_data_r;
reg old_chnl_rx;
reg pending_ack = 0;
//always acknowledge transaction
always @(posedge clk) begin
old_chnl_rx <= CHNL_RX;
if (~old_chnl_rx & CHNL_RX) pending_ack <= 1'b1;
if (CHNL_RX_ACK) CHNL_RX_ACK <= 1'b0;
else begin
if (pending_ack /*& app_ack*/) begin
CHNL_RX_ACK <= 1'b1;
pending_ack <= 1'b0;
end
end
end
//register incoming data
assign CHNL_RX_DATA_REN = ~app_en_r | app_ack;
always @(posedge clk) begin
if (~app_en_r | app_ack) begin
app_en_r <= CHNL_RX_DATA_VALID;
rx_data_r <= CHNL_RX_DATA;
end
end
//send to the MC
assign app_en = app_en_r;
assign app_instr = rx_data_r;
//SEND DATA TO HOST
localparam RECV_IDLE = 1'b0;
localparam RECV_BUSY = 1'b1;
reg sender_ack;
reg [DQ_WIDTH*4 - 1:0] send_data_r;
reg recv_state = RECV_IDLE;
assign rdback_fifo_rden = (recv_state == RECV_IDLE);
always @(posedge clk) begin
if (rst) begin
recv_state <= RECV_IDLE;
end else begin
case (recv_state)
RECV_IDLE: begin
if (~rdback_fifo_empty) begin
send_data_r <= rdback_data;
recv_state <= RECV_BUSY;
end
end //RECV_IDLE
RECV_BUSY: begin
if (sender_ack) recv_state <= RECV_IDLE;
end //RECV_BUSY
endcase
end
end
reg [2:0] sender_state = 0; //edit this if DQ_WIDTH or C_PCI_DATA_WIDTH changes
reg [2:0] sender_state_ns;
always @* begin
sender_ack = 1'b0;
sender_state_ns = sender_state;
CHNL_TX = sender_state[2];
CHNL_TX_LEN = 16;
if (recv_state == RECV_BUSY) begin
CHNL_TX = 1'b1;
CHNL_TX_DATA_VALID = 1'b1;
if (CHNL_TX_DATA_REN) begin
sender_state_ns = sender_state + 3'd1;
if (sender_state[1:0] == 2'b11) sender_ack = 1'b1;
end
end
end
always @(posedge clk) begin
if (rst) begin
sender_state <= 0;
end else begin
sender_state <= sender_state_ns;
end
end
wire [7:0] offset = {6'd0, sender_state[1:0]} << 6;
assign CHNL_TX_DATA = send_data_r[offset+:64];
endmodule
| 8.427519 |
module softrisc_top (
input clk,
input btnC,
input btnU,
input btnD,
input btnR,
input btnL,
input [15:0] sw,
output [6:0] seg,
output dp,
output [3:0] an,
output [15:0] led
);
wire rst;
wire clk_1;
reg [31:0] addr_in, data_in;
reg [1:0] cmd;
wire [7:0] dataA, dataB;
wire [3:0] bcdn[0:3];
assign dataA = sw[7:0];
assign dataB = sw[15:8];
assign led = sw;
assign rst = ~btnC;
always @(posedge clk) begin
addr_in <= {24'b0, dataA};
data_in <= {26'b0, dataB[5:0]};
cmd <= dataB[7:6];
end
CPU_top CPU_0 (
.clk(clk),
.reset(btnC),
.addr_in(addr_in),
.data_in(data_in),
.cmd(cmd),
.data_out({bcdn[3], bcdn[2], bcdn[1], bcdn[0]})
);
seg_scan(
.clk(clk),
.rst(rst),
.bcd3(bcdn[3]),
.bcd2(bcdn[2]),
.bcd1(bcdn[1]),
.bcd0(bcdn[0]),
.an(an),
.seg(seg),
.dp(dp)
);
endmodule
| 7.069906 |
module softusb_dpram #(
parameter depth = 11, /* < log2 of the capacity in words */
parameter width = 32,
parameter initfile = ""
) (
input clk,
input clk2,
input [depth-1:0] a,
input we,
input [width-1:0] di,
output reg [width-1:0] do,
input ce2,
input [depth-1:0] a2,
input we2,
input [width-1:0] di2,
output reg [width-1:0] do2
);
reg [width-1:0] ram[0:(1 << depth)-1];
// synthesis translate_off
initial if(initfile != "") $readmemh(initfile, ram);
// synthesis translate_on
always @(posedge clk) begin
if(we)
ram[a] <= di;
else
do <= ram[a];
end
always @(posedge clk2) begin
if(ce2) begin
if(we2)
ram[a2] <= di2;
else
do2 <= ram[a2];
end
end
endmodule
| 7.528927 |
module softusb_filter (
input usb_clk,
input rcv,
input vp,
input vm,
output reg rcv_s,
output reg vp_s,
output reg vm_s
);
reg rcv_s0;
reg vp_s0;
reg vm_s0;
reg rcv_s1;
reg vp_s1;
reg vm_s1;
/* synchronizer */
always @(posedge usb_clk) begin
rcv_s0 <= rcv;
vp_s0 <= vp;
vm_s0 <= vm;
rcv_s <= rcv_s0;
vp_s <= vp_s0;
vm_s <= vm_s0;
end
/* glitch filter */
/*reg rcv_s2;
reg vp_s2;
reg vm_s2;
always @(posedge usb_clk) begin
rcv_s2 <= rcv_s1;
vp_s2 <= vp_s1;
vm_s2 <= vm_s1;
if(rcv_s2 == rcv_s1)
rcv_s <= rcv_s2;
if(vp_s2 == vp_s1)
vp_s <= vp_s2;
if(vm_s2 == vm_s1)
vm_s <= vm_s2;
end*/
endmodule
| 6.778026 |
module softusb_hostif #(
parameter csr_addr = 4'h0
) (
input sys_clk,
input sys_rst,
input usb_clk,
output reg usb_rst,
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
output irq,
input io_we,
input [5:0] io_a
);
wire csr_selected = csr_a[13:10] == csr_addr;
reg usb_rst0;
always @(posedge sys_clk) begin
if (sys_rst) begin
usb_rst0 <= 1'b1;
csr_do <= 1'b0;
end else begin
csr_do <= 1'b0;
if (csr_selected) begin
if (csr_we) usb_rst0 <= csr_di[0];
csr_do <= usb_rst0;
end
end
end
/* Synchronize USB Reset to the USB clock domain */
reg usb_rst1;
always @(posedge usb_clk) begin
usb_rst1 <= usb_rst0;
usb_rst <= usb_rst1;
end
/* Generate IRQs */
reg irq_flip;
always @(posedge usb_clk) begin
if (usb_rst) irq_flip <= 1'b0;
else if (io_we && (io_a == 6'h15)) irq_flip <= ~irq_flip;
end
reg irq_flip0;
reg irq_flip1;
reg irq_flip2;
always @(posedge sys_clk) begin
irq_flip0 <= irq_flip;
irq_flip1 <= irq_flip0;
irq_flip2 <= irq_flip1;
end
assign irq = irq_flip1 != irq_flip2;
endmodule
| 7.072219 |
module softusb_phy (
input usb_clk,
input usb_rst,
output usba_spd,
output usba_oe_n,
input usba_rcv,
inout usba_vp,
inout usba_vm,
output usbb_spd,
output usbb_oe_n,
input usbb_rcv,
inout usbb_vp,
inout usbb_vm,
output usba_discon,
output usbb_discon,
output [1:0] line_state_a,
output [1:0] line_state_b,
input port_sel_rx,
input [1:0] port_sel_tx,
input [7:0] tx_data,
input tx_valid,
output tx_ready, /* data acknowledgment */
output tx_busy, /* busy generating EOP, sending data, etc. */
input [1:0] generate_reset,
output [7:0] rx_data,
output rx_valid,
output rx_active,
input tx_low_speed,
input [1:0] low_speed,
input generate_eop
);
/* RX synchronizer */
wire vp_s_a;
wire vm_s_a;
wire rcv_s_a;
softusb_filter filter_a (
.usb_clk(usb_clk),
.rcv(usba_rcv),
.vp (usba_vp),
.vm (usba_vm),
.rcv_s(rcv_s_a),
.vp_s (vp_s_a),
.vm_s (vm_s_a)
);
assign line_state_a = {vm_s_a, vp_s_a};
wire vp_s_b;
wire vm_s_b;
wire rcv_s_b;
softusb_filter filter_b (
.usb_clk(usb_clk),
.rcv(usbb_rcv),
.vp (usbb_vp),
.vm (usbb_vm),
.rcv_s(rcv_s_b),
.vp_s (vp_s_b),
.vm_s (vm_s_b)
);
assign line_state_b = {vm_s_b, vp_s_b};
/* TX section */
wire txp;
wire txm;
wire txoe;
softusb_tx tx (
.usb_clk(usb_clk),
.usb_rst(usb_rst),
.tx_data (tx_data),
.tx_valid(tx_valid),
.tx_ready(tx_ready),
.txp(txp),
.txm(txm),
.txoe(txoe),
.low_speed(tx_low_speed),
.generate_eop(generate_eop)
);
assign tx_busy = txoe;
/* RX section */
reg txoe0;
reg txoe1;
always @(posedge usb_clk) begin
txoe0 <= txoe;
txoe1 <= txoe0;
end
softusb_rx rx (
.usb_clk(usb_clk),
.rxreset(txoe1),
.rx (port_sel_rx ? rcv_s_b : rcv_s_a),
.rxp(port_sel_rx ? vp_s_b : vp_s_a),
.rxm(port_sel_rx ? vm_s_b : vm_s_a),
.rx_data (rx_data),
.rx_valid (rx_valid),
.rx_active(rx_active),
.low_speed(port_sel_rx ? low_speed[1] : low_speed[0])
);
/* Tri-state enables and drivers */
wire txoe_a = (txoe & port_sel_tx[0]) | generate_reset[0];
wire txoe_b = (txoe & port_sel_tx[1]) | generate_reset[1];
assign usba_oe_n = ~txoe_a;
assign usba_vp = txoe_a ? (generate_reset[0] ? 1'b0 : txp) : 1'bz;
assign usba_vm = txoe_a ? (generate_reset[0] ? 1'b0 : txm) : 1'bz;
assign usbb_oe_n = ~txoe_b;
assign usbb_vp = txoe_b ? (generate_reset[1] ? 1'b0 : txp) : 1'bz;
assign usbb_vm = txoe_b ? (generate_reset[1] ? 1'b0 : txm) : 1'bz;
/* Assert USB disconnect if we see SE0 for at least 2.5us */
reg [6:0] usba_discon_cnt;
assign usba_discon = (usba_discon_cnt == 7'd127);
always @(posedge usb_clk) begin
if (usb_rst) usba_discon_cnt <= 7'd0;
else begin
if (line_state_a != 7'd0) usba_discon_cnt <= 7'd0;
else if (~usba_discon) usba_discon_cnt <= usba_discon_cnt + 7'd1;
end
end
reg [6:0] usbb_discon_cnt;
assign usbb_discon = (usbb_discon_cnt == 7'd127);
always @(posedge usb_clk) begin
if (usb_rst) usbb_discon_cnt <= 7'd0;
else begin
if (line_state_b != 2'h0) usbb_discon_cnt <= 7'd0;
else if (~usbb_discon) usbb_discon_cnt <= usbb_discon_cnt + 7'd1;
end
end
assign usba_spd = ~low_speed[0];
assign usbb_spd = ~low_speed[1];
endmodule
| 7.030247 |
module softusb_ram #(
parameter pmem_width = 11,
parameter dmem_width = 13
) (
input sys_clk,
input sys_rst,
input usb_clk,
input usb_rst,
input [31:0] wb_adr_i,
output [31:0] wb_dat_o,
input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output reg wb_ack_o,
input wb_we_i,
input pmem_ce,
input [pmem_width-1:0] pmem_a,
output [15:0] pmem_d,
input dmem_we,
input [dmem_width-1:0] dmem_a,
input [7:0] dmem_di,
output reg [7:0] dmem_do
);
always @(posedge sys_clk) begin
if(sys_rst)
wb_ack_o <= 1'b0;
else begin
if(wb_stb_i & wb_cyc_i & ~wb_ack_o)
wb_ack_o <= 1'b1;
else
wb_ack_o <= 1'b0;
end
end
wire [31:0] wb_dat_o_prog;
softusb_dpram #(
.depth(pmem_width),
.width(16),
.initfile("trx.rom")
) program (
.clk(sys_clk),
.clk2(usb_clk),
.a(wb_adr_i[pmem_width+1:2]),
.we(wb_stb_i & wb_cyc_i & ~wb_adr_i[17] & wb_we_i & ~wb_ack_o),
.di(wb_dat_i[15:0]),
.do(wb_dat_o_prog[15:0]),
.ce2(pmem_ce),
.a2(pmem_a),
.we2(1'b0),
.di2(16'hxxxx),
.do2(pmem_d)
);
assign wb_dat_o_prog[31:16] = 16'd0;
wire [7:0] dmem_do0;
wire [7:0] dmem_do1;
wire [7:0] dmem_do2;
wire [7:0] dmem_do3;
wire [31:0] wb_dat_o_data;
softusb_dpram #(
.depth(dmem_width-2),
.width(8)
) dataram0 (
.clk(sys_clk),
.clk2(usb_clk),
.a(wb_adr_i[dmem_width-1:2]),
.we(wb_stb_i & wb_cyc_i & wb_adr_i[17] & wb_we_i & wb_sel_i[0] & ~wb_ack_o),
.di(wb_dat_i[7:0]),
.do(wb_dat_o_data[7:0]),
.ce2(1'b1),
.a2(dmem_a[dmem_width-1:2]),
.we2(dmem_we & (dmem_a[1:0] == 2'd3)),
.di2(dmem_di),
.do2(dmem_do0)
);
softusb_dpram #(
.depth(dmem_width-2),
.width(8)
) dataram1 (
.clk(sys_clk),
.clk2(usb_clk),
.a(wb_adr_i[dmem_width-1:2]),
.we(wb_stb_i & wb_cyc_i & wb_adr_i[17] & wb_we_i & wb_sel_i[1] & ~wb_ack_o),
.di(wb_dat_i[15:8]),
.do(wb_dat_o_data[15:8]),
.ce2(1'b1),
.a2(dmem_a[dmem_width-1:2]),
.we2(dmem_we & (dmem_a[1:0] == 2'd2)),
.di2(dmem_di),
.do2(dmem_do1)
);
softusb_dpram #(
.depth(dmem_width-2),
.width(8)
) dataram2 (
.clk(sys_clk),
.clk2(usb_clk),
.a(wb_adr_i[dmem_width-1:2]),
.we(wb_stb_i & wb_cyc_i & wb_adr_i[17] & wb_we_i & wb_sel_i[2] & ~wb_ack_o),
.di(wb_dat_i[23:16]),
.do(wb_dat_o_data[23:16]),
.ce2(1'b1),
.a2(dmem_a[dmem_width-1:2]),
.we2(dmem_we & (dmem_a[1:0] == 2'd1)),
.di2(dmem_di),
.do2(dmem_do2)
);
softusb_dpram #(
.depth(dmem_width-2),
.width(8)
) dataram3 (
.clk(sys_clk),
.clk2(usb_clk),
.a(wb_adr_i[dmem_width-1:2]),
.we(wb_stb_i & wb_cyc_i & wb_adr_i[17] & wb_we_i & wb_sel_i[3] & ~wb_ack_o),
.di(wb_dat_i[31:24]),
.do(wb_dat_o_data[31:24]),
.ce2(1'b1),
.a2(dmem_a[dmem_width-1:2]),
.we2(dmem_we & (dmem_a[1:0] == 2'd0)),
.di2(dmem_di),
.do2(dmem_do3)
);
reg [1:0] dmem_a01;
always @(posedge usb_clk) dmem_a01 <= dmem_a[1:0];
always @(*) begin
case(dmem_a01)
2'd0: dmem_do = dmem_do3;
2'd1: dmem_do = dmem_do2;
2'd2: dmem_do = dmem_do1;
2'd3: dmem_do = dmem_do0;
endcase
end
reg datasel;
always @(posedge sys_clk) datasel <= wb_adr_i[17];
assign wb_dat_o = datasel ? wb_dat_o_data : wb_dat_o_prog;
endmodule
| 7.524306 |
module softusb_sie (
input usb_clk,
input usb_rst,
input io_re,
input io_we,
input [5:0] io_a,
input [7:0] io_di,
output reg [7:0] io_do,
output usba_spd,
output usba_oe_n,
input usba_rcv,
inout usba_vp,
inout usba_vm,
output usbb_spd,
output usbb_oe_n,
input usbb_rcv,
inout usbb_vp,
inout usbb_vm
);
wire [1:0] line_state_a;
wire [1:0] line_state_b;
wire discon_a;
wire discon_b;
reg port_sel_rx;
reg [1:0] port_sel_tx;
reg [7:0] tx_data;
reg tx_valid;
wire tx_ready;
reg tx_pending;
reg [1:0] generate_reset;
wire [7:0] rx_data;
wire rx_valid;
wire rx_active;
wire tx_busy;
reg [7:0] data_in;
reg rx_pending;
reg tx_low_speed;
reg [1:0] low_speed;
reg generate_eop;
always @(posedge usb_clk) begin
if (usb_rst) begin
port_sel_rx <= 1'b0;
port_sel_tx <= 2'b00;
tx_valid <= 1'b0;
tx_pending <= 1'b0;
generate_reset <= 2'd0;
rx_pending <= 1'b0;
tx_low_speed <= 1'b0;
low_speed <= 2'b00;
generate_eop <= 1'b0;
io_do <= 8'd0;
end else begin
io_do <= 8'd0;
generate_eop <= 1'b0;
case (io_a)
6'h00: io_do <= line_state_a;
6'h01: io_do <= line_state_b;
6'h02: io_do <= discon_a;
6'h03: io_do <= discon_b;
6'h04: io_do <= port_sel_rx;
6'h05: io_do <= port_sel_tx;
6'h06: io_do <= tx_data;
6'h07: io_do <= tx_pending;
6'h08: io_do <= tx_valid;
6'h09: io_do <= tx_busy;
6'h0a: io_do <= generate_reset;
6'h0b: begin
io_do <= data_in;
if (io_re) rx_pending <= 1'b0;
end
6'h0c: io_do <= rx_pending;
6'h0d: io_do <= rx_active;
6'h0e: io_do <= tx_low_speed;
6'h0f: io_do <= low_speed;
6'h10: io_do <= 8'hxx;
endcase
if (io_we) begin
$display("USB SIE W: a=%x dat=%x", io_a, io_di);
case (io_a)
6'h04: port_sel_rx <= io_di[0];
6'h05: port_sel_tx <= io_di[1:0];
6'h06: begin
tx_valid <= 1'b1;
tx_data <= io_di;
tx_pending <= 1'b1;
end
6'h08: tx_valid <= 1'b0;
6'h0a: generate_reset <= io_di[1:0];
6'h0e: tx_low_speed <= io_di[0];
6'h0f: low_speed <= io_di[1:0];
6'h10: generate_eop <= 1'b1;
endcase
end
if (tx_ready) tx_pending <= 1'b0;
if (rx_valid) begin
data_in <= rx_data;
rx_pending <= 1'b1;
end
if (io_re) // must be at the end because of the delay!
#1 $display("USB SIE R: a=%x dat=%x", io_a, io_do);
end
end
softusb_phy phy (
.usb_clk(usb_clk),
.usb_rst(usb_rst),
.usba_spd (usba_spd),
.usba_oe_n(usba_oe_n),
.usba_rcv (usba_rcv),
.usba_vp (usba_vp),
.usba_vm (usba_vm),
.usbb_spd (usbb_spd),
.usbb_oe_n(usbb_oe_n),
.usbb_rcv (usbb_rcv),
.usbb_vp (usbb_vp),
.usbb_vm (usbb_vm),
.usba_discon(discon_a),
.usbb_discon(discon_b),
.line_state_a(line_state_a),
.line_state_b(line_state_b),
.port_sel_rx(port_sel_rx),
.port_sel_tx(port_sel_tx),
.tx_data (tx_data),
.tx_valid(tx_valid),
.tx_ready(tx_ready),
.tx_busy (tx_busy),
.generate_reset(generate_reset),
.rx_data (rx_data),
.rx_valid (rx_valid),
.rx_active(rx_active),
.tx_low_speed(tx_low_speed),
.low_speed(low_speed),
.generate_eop(generate_eop)
);
endmodule
| 7.672188 |
module softusb #(
parameter csr_addr = 4'h0,
parameter pmem_width = 11,
parameter dmem_width = 13
) (
input sys_clk,
input sys_rst,
input usb_clk,
/* CSR interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
output irq,
/* WISHBONE to access RAM */
input [31:0] wb_adr_i,
output [31:0] wb_dat_o,
input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
input wb_we_i,
/* USB port A */
output usba_spd,
output usba_oe_n,
input usba_rcv,
inout usba_vp,
inout usba_vm,
/* USB port B */
output usbb_spd,
output usbb_oe_n,
input usbb_rcv,
inout usbb_vp,
inout usbb_vm
);
wire usb_rst;
wire io_re;
wire io_we;
wire [5:0] io_a;
wire [7:0] io_dw;
wire [7:0] io_dr_timer, io_dr_sie;
softusb_timer timer (
.usb_clk(usb_clk),
.usb_rst(usb_rst),
.io_we(io_we),
.io_a (io_a),
.io_do(io_dr_timer)
);
softusb_hostif #(
.csr_addr(csr_addr)
) hostif (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.usb_clk(usb_clk),
.usb_rst(usb_rst),
.csr_a (csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.irq(irq),
.io_we(io_we),
.io_a (io_a)
);
softusb_sie sie (
.usb_clk(usb_clk),
.usb_rst(usb_rst),
.io_re(io_re),
.io_we(io_we),
.io_a (io_a),
.io_di(io_dw),
.io_do(io_dr_sie),
.usba_spd (usba_spd),
.usba_oe_n(usba_oe_n),
.usba_rcv (usba_rcv),
.usba_vp (usba_vp),
.usba_vm (usba_vm),
.usbb_spd (usbb_spd),
.usbb_oe_n(usbb_oe_n),
.usbb_rcv (usbb_rcv),
.usbb_vp (usbb_vp),
.usbb_vm (usbb_vm)
);
wire pmem_ce;
wire [pmem_width-1:0] pmem_a;
wire [15:0] pmem_d;
wire dmem_we;
wire [dmem_width-1:0] dmem_a;
wire [7:0] dmem_dr;
wire [7:0] dmem_dw;
softusb_ram #(
.pmem_width(pmem_width),
.dmem_width(dmem_width)
) ram (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.usb_clk(usb_clk),
.usb_rst(usb_rst),
.wb_adr_i(wb_adr_i),
.wb_dat_o(wb_dat_o),
.wb_dat_i(wb_dat_i),
.wb_sel_i(wb_sel_i),
.wb_stb_i(wb_stb_i),
.wb_cyc_i(wb_cyc_i),
.wb_ack_o(wb_ack_o),
.wb_we_i (wb_we_i),
.pmem_ce(pmem_ce),
.pmem_a (pmem_a),
.pmem_d (pmem_d),
.dmem_we(dmem_we),
.dmem_a (dmem_a),
.dmem_di(dmem_dw),
.dmem_do(dmem_dr)
);
softusb_navre #(
.pmem_width(pmem_width),
.dmem_width(dmem_width)
) navre (
.clk(usb_clk),
.rst(usb_rst),
.pmem_ce(pmem_ce),
.pmem_a (pmem_a),
.pmem_d (pmem_d),
.dmem_we(dmem_we),
.dmem_a (dmem_a),
.dmem_di(dmem_dr),
.dmem_do(dmem_dw),
.io_re(io_re),
.io_we(io_we),
.io_a (io_a),
.io_do(io_dw),
.io_di(io_dr_sie | io_dr_timer)
);
endmodule
| 7.827436 |
module softusb_dpram #(
parameter depth = 11, /* < log2 of the capacity in words */
parameter width = 32,
parameter initfile = ""
) (
input clk,
input clk2,
input [depth-1:0] a,
input we,
input [width-1:0] di,
output reg [width-1:0] do,
input ce2,
input [depth-1:0] a2,
input we2,
input [width-1:0] di2,
output reg [width-1:0] do2
);
reg [width-1:0] ram[0:(1 << depth)-1];
// synthesis translate_off
integer i;
initial begin
if(initfile != "")
$readmemh(initfile, ram);
else
for(i=0;i<(1 << depth);i=i+1)
ram[i] = 0;
end
// synthesis translate_on
always @(posedge clk) begin
if(we)
ram[a] <= di;
else
do <= ram[a];
end
always @(posedge clk2) begin
if(ce2) begin
if(we2)
ram[a2] <= di2;
else
do2 <= ram[a2];
end
end
endmodule
| 7.528927 |
module softusb_filter (
input usb_clk,
input rcv,
input vp,
input vm,
output reg rcv_s,
output reg vp_s,
output reg vm_s
);
reg rcv_s0;
reg vp_s0;
reg vm_s0;
/* synchronizer */
always @(posedge usb_clk) begin
rcv_s0 <= rcv;
vp_s0 <= vp;
vm_s0 <= vm;
rcv_s <= rcv_s0;
vp_s <= vp_s0;
vm_s <= vm_s0;
end
endmodule
| 6.778026 |
module softusb_hostif #(
parameter csr_addr = 4'h0,
parameter pmem_width = 12
) (
input sys_clk,
input sys_rst,
input usb_clk,
output reg usb_rst,
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
output irq,
input io_we,
input [5:0] io_a,
input [pmem_width-1:0] dbg_pc
);
wire csr_selected = csr_a[13:10] == csr_addr;
reg usb_rst0;
always @(posedge sys_clk) begin
if (sys_rst) begin
usb_rst0 <= 1'b1;
csr_do <= 1'b0;
end else begin
csr_do <= 1'b0;
if (csr_selected) begin
if (csr_we) usb_rst0 <= csr_di[0];
csr_do <= {dbg_pc, 1'b0};
end
end
end
/* Synchronize USB Reset to the USB clock domain */
reg usb_rst1;
always @(posedge usb_clk) begin
usb_rst1 <= usb_rst0;
usb_rst <= usb_rst1;
end
/* Generate IRQs */
reg irq_flip;
always @(posedge usb_clk) begin
if (usb_rst) irq_flip <= 1'b0;
else if (io_we && (io_a == 6'h15)) irq_flip <= ~irq_flip;
end
reg irq_flip0;
reg irq_flip1;
reg irq_flip2;
always @(posedge sys_clk) begin
irq_flip0 <= irq_flip;
irq_flip1 <= irq_flip0;
irq_flip2 <= irq_flip1;
end
assign irq = irq_flip1 != irq_flip2;
endmodule
| 7.072219 |
module softusb_phy (
input usb_clk,
input usb_rst,
output usba_spd,
output usba_oe_n,
input usba_rcv,
inout usba_vp,
inout usba_vm,
output usbb_spd,
output usbb_oe_n,
input usbb_rcv,
inout usbb_vp,
inout usbb_vm,
output [1:0] line_state_a,
output [1:0] line_state_b,
input port_sel_rx,
input [1:0] port_sel_tx,
input [7:0] tx_data,
input tx_valid,
output tx_ready, /* data acknowledgment */
output reg tx_busy, /* busy generating EOP, sending data, etc. */
input [1:0] generate_reset,
output [7:0] rx_data,
output rx_valid,
output rx_active,
output rx_error,
input tx_low_speed,
input [1:0] low_speed,
input generate_eop
);
/* RX synchronizer */
wire vp_s_a;
wire vm_s_a;
wire rcv_s_a;
softusb_filter filter_a (
.usb_clk(usb_clk),
.rcv(usba_rcv),
.vp (usba_vp),
.vm (usba_vm),
.rcv_s(rcv_s_a),
.vp_s (vp_s_a),
.vm_s (vm_s_a)
);
assign line_state_a = {vm_s_a, vp_s_a};
wire vp_s_b;
wire vm_s_b;
wire rcv_s_b;
softusb_filter filter_b (
.usb_clk(usb_clk),
.rcv(usbb_rcv),
.vp (usbb_vp),
.vm (usbb_vm),
.rcv_s(rcv_s_b),
.vp_s (vp_s_b),
.vm_s (vm_s_b)
);
assign line_state_b = {vm_s_b, vp_s_b};
/* TX section */
wire txp;
wire txm;
wire txoe;
softusb_tx tx (
.usb_clk(usb_clk),
.usb_rst(usb_rst),
.tx_data (tx_data),
.tx_valid(tx_valid),
.tx_ready(tx_ready),
.txp(txp),
.txm(txm),
.txoe(txoe),
.low_speed(tx_low_speed),
.generate_eop(generate_eop)
);
reg txoe_r;
always @(posedge usb_clk) begin
if (usb_rst) begin
txoe_r <= 1'b0;
tx_busy <= 1'b0;
end else begin
txoe_r <= txoe;
if (txoe_r & ~txoe) tx_busy <= 1'b0;
if (generate_eop | tx_valid) tx_busy <= 1'b1;
end
end
/* RX section */
softusb_rx rx (
.usb_clk(usb_clk),
.rxreset(txoe),
.rx (port_sel_rx ? rcv_s_b : rcv_s_a),
.rxp(port_sel_rx ? vp_s_b : vp_s_a),
.rxm(port_sel_rx ? vm_s_b : vm_s_a),
.rx_data (rx_data),
.rx_valid (rx_valid),
.rx_active(rx_active),
.rx_error (rx_error),
.low_speed(port_sel_rx ? low_speed[1] : low_speed[0])
);
/* Tri-state enables and drivers */
wire txoe_a = (txoe & port_sel_tx[0]) | generate_reset[0];
wire txoe_b = (txoe & port_sel_tx[1]) | generate_reset[1];
assign usba_oe_n = ~txoe_a;
assign usba_vp = txoe_a ? (generate_reset[0] ? 1'b0 : txp) : 1'bz;
assign usba_vm = txoe_a ? (generate_reset[0] ? 1'b0 : txm) : 1'bz;
assign usbb_oe_n = ~txoe_b;
assign usbb_vp = txoe_b ? (generate_reset[1] ? 1'b0 : txp) : 1'bz;
assign usbb_vm = txoe_b ? (generate_reset[1] ? 1'b0 : txm) : 1'bz;
assign usba_spd = ~low_speed[0];
assign usbb_spd = ~low_speed[1];
endmodule
| 7.030247 |
module softusb_ram #(
parameter pmem_width = 12,
parameter dmem_width = 13,
parameter initprog = ""
) (
input sys_clk,
input sys_rst,
input usb_clk,
input usb_rst,
input [31:0] wb_adr_i,
output [31:0] wb_dat_o,
input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output reg wb_ack_o,
input wb_we_i,
input pmem_ce,
input [pmem_width-1:0] pmem_a,
output [15:0] pmem_d,
input dmem_we,
input [dmem_width-1:0] dmem_a,
input [7:0] dmem_di,
output reg [7:0] dmem_do
);
always @(posedge sys_clk) begin
if(sys_rst)
wb_ack_o <= 1'b0;
else begin
if(wb_stb_i & wb_cyc_i & ~wb_ack_o)
wb_ack_o <= 1'b1;
else
wb_ack_o <= 1'b0;
end
end
wire [31:0] wb_dat_o_prog;
softusb_dpram #(
.depth(pmem_width),
.width(16),
.initfile(initprog)
) program (
.clk(sys_clk),
.clk2(usb_clk),
.a(wb_adr_i[pmem_width+1:2]),
.we(wb_stb_i & wb_cyc_i & ~wb_adr_i[17] & wb_we_i & ~wb_ack_o),
.di(wb_dat_i[15:0]),
.do(wb_dat_o_prog[15:0]),
.ce2(pmem_ce),
.a2(pmem_a),
.we2(1'b0),
.di2(16'hxxxx),
.do2(pmem_d)
);
assign wb_dat_o_prog[31:16] = 16'd0;
wire [7:0] dmem_do0;
wire [7:0] dmem_do1;
wire [7:0] dmem_do2;
wire [7:0] dmem_do3;
wire [31:0] wb_dat_o_data;
softusb_dpram #(
.depth(dmem_width-2),
.width(8)
) dataram0 (
.clk(sys_clk),
.clk2(usb_clk),
.a(wb_adr_i[dmem_width-1:2]),
.we(wb_stb_i & wb_cyc_i & wb_adr_i[17] & wb_we_i & wb_sel_i[0] & ~wb_ack_o),
.di(wb_dat_i[7:0]),
.do(wb_dat_o_data[7:0]),
.ce2(1'b1),
.a2(dmem_a[dmem_width-1:2]),
.we2(dmem_we & (dmem_a[1:0] == 2'd3)),
.di2(dmem_di),
.do2(dmem_do0)
);
softusb_dpram #(
.depth(dmem_width-2),
.width(8)
) dataram1 (
.clk(sys_clk),
.clk2(usb_clk),
.a(wb_adr_i[dmem_width-1:2]),
.we(wb_stb_i & wb_cyc_i & wb_adr_i[17] & wb_we_i & wb_sel_i[1] & ~wb_ack_o),
.di(wb_dat_i[15:8]),
.do(wb_dat_o_data[15:8]),
.ce2(1'b1),
.a2(dmem_a[dmem_width-1:2]),
.we2(dmem_we & (dmem_a[1:0] == 2'd2)),
.di2(dmem_di),
.do2(dmem_do1)
);
softusb_dpram #(
.depth(dmem_width-2),
.width(8)
) dataram2 (
.clk(sys_clk),
.clk2(usb_clk),
.a(wb_adr_i[dmem_width-1:2]),
.we(wb_stb_i & wb_cyc_i & wb_adr_i[17] & wb_we_i & wb_sel_i[2] & ~wb_ack_o),
.di(wb_dat_i[23:16]),
.do(wb_dat_o_data[23:16]),
.ce2(1'b1),
.a2(dmem_a[dmem_width-1:2]),
.we2(dmem_we & (dmem_a[1:0] == 2'd1)),
.di2(dmem_di),
.do2(dmem_do2)
);
softusb_dpram #(
.depth(dmem_width-2),
.width(8)
) dataram3 (
.clk(sys_clk),
.clk2(usb_clk),
.a(wb_adr_i[dmem_width-1:2]),
.we(wb_stb_i & wb_cyc_i & wb_adr_i[17] & wb_we_i & wb_sel_i[3] & ~wb_ack_o),
.di(wb_dat_i[31:24]),
.do(wb_dat_o_data[31:24]),
.ce2(1'b1),
.a2(dmem_a[dmem_width-1:2]),
.we2(dmem_we & (dmem_a[1:0] == 2'd0)),
.di2(dmem_di),
.do2(dmem_do3)
);
reg [1:0] dmem_a01;
always @(posedge usb_clk) dmem_a01 <= dmem_a[1:0];
always @(*) begin
case(dmem_a01)
2'd0: dmem_do = dmem_do3;
2'd1: dmem_do = dmem_do2;
2'd2: dmem_do = dmem_do1;
2'd3: dmem_do = dmem_do0;
endcase
end
reg datasel;
always @(posedge sys_clk) datasel <= wb_adr_i[17];
assign wb_dat_o = datasel ? wb_dat_o_data : wb_dat_o_prog;
endmodule
| 7.524306 |
module softusb_sie (
input usb_clk,
input usb_rst,
input io_re,
input io_we,
input [5:0] io_a,
input [7:0] io_di,
output reg [7:0] io_do,
output usba_spd,
output usba_oe_n,
input usba_rcv,
inout usba_vp,
inout usba_vm,
output usbb_spd,
output usbb_oe_n,
input usbb_rcv,
inout usbb_vp,
inout usbb_vm
);
wire [1:0] line_state_a;
wire [1:0] line_state_b;
reg port_sel_rx;
reg [1:0] port_sel_tx;
reg [7:0] tx_data;
reg tx_valid;
wire tx_ready;
reg tx_pending;
reg [1:0] generate_reset;
wire [7:0] rx_data;
wire rx_valid;
wire rx_active;
wire rx_error;
reg rx_error_pending;
wire tx_busy;
reg [7:0] data_in;
reg rx_pending;
reg tx_low_speed;
reg [1:0] low_speed;
always @(posedge usb_clk) begin
if (usb_rst) begin
port_sel_rx <= 1'b0;
port_sel_tx <= 2'b00;
tx_valid <= 1'b0;
tx_pending <= 1'b0;
generate_reset <= 2'd0;
rx_error_pending <= 1'b0;
rx_pending <= 1'b0;
tx_low_speed <= 1'b0;
low_speed <= 2'b00;
io_do <= 8'd0;
end else begin
io_do <= 8'd0;
case (io_a)
6'h00: io_do <= line_state_a;
6'h01: io_do <= line_state_b;
6'h02: io_do <= port_sel_rx;
6'h03: io_do <= port_sel_tx;
6'h04: io_do <= tx_data;
6'h05: io_do <= tx_pending;
6'h06: io_do <= tx_valid;
6'h07: io_do <= tx_busy;
6'h08: io_do <= generate_reset;
6'h09: begin
io_do <= data_in;
if (io_re) rx_pending <= 1'b0;
end
6'h0a: io_do <= {rx_pending, rx_active};
6'h0b: io_do <= rx_active;
6'h0c: begin
io_do <= rx_error_pending;
if (io_re) rx_error_pending <= 1'b0;
end
6'h0d: io_do <= tx_low_speed;
6'h0e: io_do <= low_speed;
6'h0f: io_do <= 8'hxx;
endcase
if (io_we) begin
$display("USB SIE W: a=%x dat=%x", io_a, io_di);
case (io_a)
6'h02: port_sel_rx <= io_di[0];
6'h03: port_sel_tx <= io_di[1:0];
6'h04: begin
tx_valid <= 1'b1;
tx_data <= io_di;
tx_pending <= 1'b1;
end
6'h06: tx_valid <= 1'b0;
6'h08: generate_reset <= io_di[1:0];
6'h0d: tx_low_speed <= io_di[0];
6'h0e: low_speed <= io_di[1:0];
// 6'h0f is Generate EOP, handled separately
endcase
end
if (tx_ready) tx_pending <= 1'b0;
if (rx_valid) begin
data_in <= rx_data;
rx_pending <= 1'b1;
end
if (rx_error) rx_error_pending <= 1'b1;
if (io_re) // must be at the end because of the delay!
#1 $display("USB SIE R: a=%x dat=%x", io_a, io_do);
end
end
softusb_phy phy (
.usb_clk(usb_clk),
.usb_rst(usb_rst),
.usba_spd (usba_spd),
.usba_oe_n(usba_oe_n),
.usba_rcv (usba_rcv),
.usba_vp (usba_vp),
.usba_vm (usba_vm),
.usbb_spd (usbb_spd),
.usbb_oe_n(usbb_oe_n),
.usbb_rcv (usbb_rcv),
.usbb_vp (usbb_vp),
.usbb_vm (usbb_vm),
.line_state_a(line_state_a),
.line_state_b(line_state_b),
.port_sel_rx(port_sel_rx),
.port_sel_tx(port_sel_tx),
.tx_data (tx_data),
.tx_valid(tx_valid),
.tx_ready(tx_ready),
.tx_busy (tx_busy),
.generate_reset(generate_reset),
.rx_data (rx_data),
.rx_valid (rx_valid),
.rx_active(rx_active),
.rx_error (rx_error),
.tx_low_speed(tx_low_speed),
.low_speed(low_speed),
.generate_eop(io_we & (io_a == 6'h0f))
);
endmodule
| 7.672188 |
module software_testbench ();
reg clk, rst;
parameter CPU_CLOCK_PERIOD = 20;
parameter CPU_CLOCK_FREQ = 1_000_000_000 / CPU_CLOCK_PERIOD;
localparam TIMEOUT_CYCLE = 200_000 * 20;
initial clk = 0;
always #(CPU_CLOCK_PERIOD / 2) clk = ~clk;
wire [31:0] csr;
top_axi #(
.AXI_AWIDTH (32),
.AXI_DWIDTH (32),
.AXI_MAX_BURST_LEN(256),
.CPU_CLOCK_FREQ (50000000)
) SYSTEM (
.sys_clk (clk),
.rst (rst),
.FPGA_SERIAL_RX(),
.FPGA_SERIAL_TX()
);
assign csr = SYSTEM.csr;
reg [31:0] cycle;
always @(posedge clk) begin
if (rst === 1) cycle <= 0;
else cycle <= cycle + 1;
end
reg [255:0] MIF_FILE;
initial begin
$dumpfile("software_testbench.vcd");
$dumpvars;
if (!$value$plusargs("MIF_FILE=%s", MIF_FILE)) begin
$display("Must supply mif_file!");
$finish();
end
$readmemh(MIF_FILE, SYSTEM.`IMEM_PATH.mem);
$readmemh(MIF_FILE, SYSTEM.`DMEM_PATH.mem);
rst = 1;
// Hold reset for a while
repeat (10) @(posedge clk);
@(negedge clk);
rst = 0;
// Delay for some time
repeat (10) @(posedge clk);
// Wait until csr is updated
wait (csr !== 0);
// if (csr === 32'b1) begin
// $display("[%d sim. cycles] CSR test PASSED!", cycle);
// end else begin
// $display("[%d sim. cycles] CSR test FAILED!", cycle);
// end
$display("[%d sim. cycles] CSR = %d!", cycle, csr);
#100;
$finish();
end
initial begin
repeat (TIMEOUT_CYCLE) @(posedge clk);
$display("Timeout!");
$finish();
end
endmodule
| 7.322209 |
module soft_ecc_ram_16bit (
rst,
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b,
err_a,
err_b
);
`include "log2.inc"
// Number of 16 bit data words (stored as 22 bit words internally)
parameter NUM_WORDS = 512;
localparam ADDR_WIDTH = log2(NUM_WORDS - 1);
// For testing error detection / correction
// a 1 bit indicates inversion of the corresponding code bit
// on the encoded RAM output.
parameter PORT_A_ERROR_INJECT = 22'b0;
parameter PORT_B_ERROR_INJECT = 22'b0;
input rst;
input [ADDR_WIDTH-1:0] address_a;
input [ADDR_WIDTH-1:0] address_b;
input clock_a;
input clock_b;
input [15:0] data_a;
input [15:0] data_b;
input wren_a;
input wren_b;
output [15:0] q_a;
output [15:0] q_b;
output [2:0] err_a;
output [2:0] err_b;
///////////////////////
// port A encoder
///////////////////////
reg [15:0] data_a_reg;
always @(posedge clock_a or posedge rst) begin
if (rst) data_a_reg <= 16'b0;
else data_a_reg <= data_a;
end
wire [21:0] data_a_code;
ecc_encode_16bit enc_a (
.d(data_a_reg),
.c(data_a_code)
);
///////////////////////
// port B encoder
///////////////////////
reg [15:0] data_b_reg;
always @(posedge clock_b or posedge rst) begin
if (rst) data_b_reg <= 16'b0;
else data_b_reg <= data_b;
end
wire [21:0] data_b_code;
ecc_encode_16bit enc_b (
.d(data_b_reg),
.c(data_b_code)
);
///////////////////////
// RAM block (22 bit words)
///////////////////////
wire [21:0] q_a_code;
wire [21:0] q_b_code;
ram_block ram (
.aclr_a(rst),
.aclr_b(rst),
.address_a(address_a),
.address_b(address_b),
.clock_a(clock_a),
.clock_b(clock_b),
.data_a(data_a_code),
.data_b(data_b_code),
.wren_a(wren_a),
.wren_b(wren_b),
.q_a(q_a_code),
.q_b(q_b_code)
);
defparam ram.NUM_WORDS = NUM_WORDS; defparam ram.DAT_WIDTH = 22;
///////////////////////
// port A decoder
///////////////////////
ecc_decode_16bit dec_a (
.clk(clock_a),
.rst(rst),
.c(q_a_code ^ PORT_A_ERROR_INJECT),
.d(q_a),
.no_err(err_a[0]),
.err_corrected(err_a[1]),
.err_fatal(err_a[2])
);
defparam dec_a.OUTPUT_REG = 1; defparam dec_a.MIDDLE_REG = 1;
///////////////////////
// port B decoder
///////////////////////
ecc_decode_16bit dec_b (
.clk(clock_b),
.rst(rst),
.c(q_b_code ^ PORT_B_ERROR_INJECT),
.d(q_b),
.no_err(err_b[0]),
.err_corrected(err_b[1]),
.err_fatal(err_b[2])
);
defparam dec_b.OUTPUT_REG = 1; defparam dec_b.MIDDLE_REG = 1;
endmodule
| 8.952439 |
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