code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module soft_ecc_ram_16bit_tb ();
`include "log2.inc"
parameter NUM_WORDS = 512;
localparam ADDR_WIDTH = log2(NUM_WORDS - 1);
parameter RAM_RD_LATENCY = 4;
parameter DATA_BITS = 16;
localparam DATA_MASK = {DATA_BITS{1'b1}};
reg clk, rst;
reg [ADDR_WIDTH-1:0] address_a;
reg [ADDR_WIDTH-1:0] address_b;
reg [DATA_BITS-1:0] data_a;
reg [DATA_BITS-1:0] data_b;
reg wren_a;
reg wren_b;
wire [DATA_BITS-1:0] q_a;
wire [DATA_BITS-1:0] q_b;
wire [2:0] err_a;
wire [2:0] err_b;
//////////////////////////////////
// ECC RAM under test
//////////////////////////////////
soft_ecc_ram_16bit sr (
.rst(rst),
.address_a(address_a),
.address_b(address_b),
.clock_a(clk),
.clock_b(clk),
.data_a(data_a),
.data_b(data_b),
.wren_a(wren_a),
.wren_b(wren_b),
.q_a(q_a),
.q_b(q_b),
.err_a(err_a),
.err_b(err_b)
);
//////////////////////////////////
// test pattern control
//////////////////////////////////
reg [2:0] state;
parameter STATE_FILL_A = 0, STATE_READ_A = 1, STATE_READ_B = 2,
STATE_FILL_B = 3, STATE_READ_BOTH = 4;
reg [10:0] cntr;
reg [ 2:0] last_state;
always @(posedge clk or posedge rst) begin
if (rst) begin
cntr <= 0;
last_state <= STATE_FILL_A;
end else begin
if (state != last_state) cntr <= 0;
else cntr <= cntr + 1'b1;
last_state <= state;
end
end
initial begin
clk = 0;
rst = 0;
#10 rst = 1;
#10 rst = 0;
end
always begin
#100 clk = ~clk;
end
always @(posedge clk or posedge rst) begin
if (rst) begin
address_a <= 0;
address_b <= 0;
data_a <= 0;
data_b <= 123;
wren_a <= 1'b1;
wren_b <= 1'b0;
state <= STATE_FILL_A;
end else begin
if (state == STATE_FILL_A) begin
if (&address_a) begin
state <= STATE_READ_A;
wren_a <= 1'b0;
end
address_a <= address_a + 1'b1;
data_a <= data_a + 1'b1;
end else if (state == STATE_READ_A) begin
if (&address_a) begin
state <= STATE_READ_B;
end
address_a <= address_a + 1'b1;
if (address_a !== 0 && cntr >= RAM_RD_LATENCY && q_a !== (cntr - RAM_RD_LATENCY)) begin
$display("Mismatch in state read A");
$display(" Expected %x", (cntr - RAM_RD_LATENCY));
$display(" Read %x", q_a);
#100 $stop();
end
end else if (state == STATE_READ_B) begin
if (&address_b) begin
state <= STATE_FILL_B;
wren_b <= 1'b1;
end
address_b <= address_b + 1'b1;
if (address_b !== 0 &&
cntr >= RAM_RD_LATENCY &&
q_b !== ((cntr-RAM_RD_LATENCY) & DATA_MASK)) begin
$display("Mismatch in state read B");
#100 $stop();
end
end else if (state == STATE_FILL_B) begin
if (&address_b) begin
state <= STATE_READ_BOTH;
wren_a <= 1'b0;
wren_b <= 1'b0;
end
address_b <= address_b + 1'b1;
data_b <= data_b + 1'b1;
end else if (state == STATE_READ_BOTH) begin
if (&address_b) begin
state <= STATE_FILL_A;
data_a <= 0;
data_b <= 123;
wren_a <= 1'b1;
// stop after one test cycle
$display("PASS");
$stop();
end
address_a <= address_a + 1'b1;
address_b <= address_b + 1'b1;
if (address_b !== 0 &&
cntr >= RAM_RD_LATENCY &&
q_b !== ((cntr-RAM_RD_LATENCY+123) & DATA_MASK)) begin
$display("Mismatch in state read both");
#100 $stop();
end
end
end
end
endmodule
| 8.952439 |
module soft_ecc_ram_32bit (
rst,
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b,
err_a,
err_b
);
`include "log2.inc"
// Number of 32 bit data words (stored as 39 bit words internally)
parameter NUM_WORDS = 512;
localparam ADDR_WIDTH = log2(NUM_WORDS - 1);
// For testing error detection / correction
// a 1 bit indicates inversion of the corresponding code bit
// on the encoded RAM output.
parameter PORT_A_ERROR_INJECT = 39'b0;
parameter PORT_B_ERROR_INJECT = 39'b0;
input rst;
input [ADDR_WIDTH-1:0] address_a;
input [ADDR_WIDTH-1:0] address_b;
input clock_a;
input clock_b;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
output [2:0] err_a;
output [2:0] err_b;
///////////////////////
// port A encoder
///////////////////////
reg [31:0] data_a_reg;
always @(posedge clock_a or posedge rst) begin
if (rst) data_a_reg <= 32'b0;
else data_a_reg <= data_a;
end
wire [38:0] data_a_code;
ecc_encode_32bit enc_a (
.d(data_a_reg),
.c(data_a_code)
);
///////////////////////
// port B encoder
///////////////////////
reg [31:0] data_b_reg;
always @(posedge clock_b or posedge rst) begin
if (rst) data_b_reg <= 32'b0;
else data_b_reg <= data_b;
end
wire [38:0] data_b_code;
ecc_encode_32bit enc_b (
.d(data_b_reg),
.c(data_b_code)
);
///////////////////////
// RAM block (39 bit words)
///////////////////////
wire [38:0] q_a_code;
wire [38:0] q_b_code;
ram_block ram (
.aclr_a(rst),
.aclr_b(rst),
.address_a(address_a),
.address_b(address_b),
.clock_a(clock_a),
.clock_b(clock_b),
.data_a(data_a_code),
.data_b(data_b_code),
.wren_a(wren_a),
.wren_b(wren_b),
.q_a(q_a_code),
.q_b(q_b_code)
);
defparam ram.NUM_WORDS = NUM_WORDS; defparam ram.DAT_WIDTH = 39;
///////////////////////
// port A decoder
///////////////////////
ecc_decode_32bit dec_a (
.clk(clock_a),
.rst(rst),
.c(q_a_code ^ PORT_A_ERROR_INJECT),
.d(q_a),
.no_err(err_a[0]),
.err_corrected(err_a[1]),
.err_fatal(err_a[2])
);
defparam dec_a.OUTPUT_REG = 1; defparam dec_a.MIDDLE_REG = 1;
///////////////////////
// port B decoder
///////////////////////
ecc_decode_32bit dec_b (
.clk(clock_b),
.rst(rst),
.c(q_b_code ^ PORT_B_ERROR_INJECT),
.d(q_b),
.no_err(err_b[0]),
.err_corrected(err_b[1]),
.err_fatal(err_b[2])
);
defparam dec_b.OUTPUT_REG = 1; defparam dec_b.MIDDLE_REG = 1;
endmodule
| 8.952439 |
module soft_ecc_ram_32bit_tb ();
`include "log2.inc"
parameter NUM_WORDS = 512;
localparam ADDR_WIDTH = log2(NUM_WORDS - 1);
parameter RAM_RD_LATENCY = 4;
parameter DATA_BITS = 32;
localparam DATA_MASK = {DATA_BITS{1'b1}};
reg clk, rst;
reg [ADDR_WIDTH-1:0] address_a;
reg [ADDR_WIDTH-1:0] address_b;
reg [DATA_BITS-1:0] data_a;
reg [DATA_BITS-1:0] data_b;
reg wren_a;
reg wren_b;
wire [DATA_BITS-1:0] q_a;
wire [DATA_BITS-1:0] q_b;
wire [2:0] err_a;
wire [2:0] err_b;
//////////////////////////////////
// ECC RAM under test
//////////////////////////////////
soft_ecc_ram_32bit sr (
.rst(rst),
.address_a(address_a),
.address_b(address_b),
.clock_a(clk),
.clock_b(clk),
.data_a(data_a),
.data_b(data_b),
.wren_a(wren_a),
.wren_b(wren_b),
.q_a(q_a),
.q_b(q_b),
.err_a(err_a),
.err_b(err_b)
);
//////////////////////////////////
// test pattern control
//////////////////////////////////
reg [2:0] state;
parameter STATE_FILL_A = 0, STATE_READ_A = 1, STATE_READ_B = 2,
STATE_FILL_B = 3, STATE_READ_BOTH = 4;
reg [10:0] cntr;
reg [ 2:0] last_state;
always @(posedge clk or posedge rst) begin
if (rst) begin
cntr <= 0;
last_state <= STATE_FILL_A;
end else begin
if (state != last_state) cntr <= 0;
else cntr <= cntr + 1'b1;
last_state <= state;
end
end
initial begin
clk = 0;
rst = 0;
#10 rst = 1;
#10 rst = 0;
end
always begin
#100 clk = ~clk;
end
always @(posedge clk or posedge rst) begin
if (rst) begin
address_a <= 0;
address_b <= 0;
data_a <= 0;
data_b <= 123;
wren_a <= 1'b1;
wren_b <= 1'b0;
state <= STATE_FILL_A;
end else begin
if (state == STATE_FILL_A) begin
if (&address_a) begin
state <= STATE_READ_A;
wren_a <= 1'b0;
end
address_a <= address_a + 1'b1;
data_a <= data_a + 1'b1;
end else if (state == STATE_READ_A) begin
if (&address_a) begin
state <= STATE_READ_B;
end
address_a <= address_a + 1'b1;
if (address_a !== 0 && cntr >= RAM_RD_LATENCY && q_a !== (cntr - RAM_RD_LATENCY)) begin
$display("Mismatch in state read A");
$display(" Expected %x", (cntr - RAM_RD_LATENCY));
$display(" Read %x", q_a);
#100 $stop();
end
end else if (state == STATE_READ_B) begin
if (&address_b) begin
state <= STATE_FILL_B;
wren_b <= 1'b1;
end
address_b <= address_b + 1'b1;
if (address_b !== 0 &&
cntr >= RAM_RD_LATENCY &&
q_b !== ((cntr-RAM_RD_LATENCY) & DATA_MASK)) begin
$display("Mismatch in state read B");
#100 $stop();
end
end else if (state == STATE_FILL_B) begin
if (&address_b) begin
state <= STATE_READ_BOTH;
wren_a <= 1'b0;
wren_b <= 1'b0;
end
address_b <= address_b + 1'b1;
data_b <= data_b + 1'b1;
end else if (state == STATE_READ_BOTH) begin
if (&address_b) begin
state <= STATE_FILL_A;
data_a <= 0;
data_b <= 123;
wren_a <= 1'b1;
// stop after one test cycle
$display("PASS");
$stop();
end
address_a <= address_a + 1'b1;
address_b <= address_b + 1'b1;
if (address_b !== 0 &&
cntr >= RAM_RD_LATENCY &&
q_b !== ((cntr-RAM_RD_LATENCY+123) & DATA_MASK)) begin
$display("Mismatch in state read both");
#100 $stop();
end
end
end
end
endmodule
| 8.952439 |
module soft_ecc_ram_64bit (
rst,
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b,
err_a,
err_b
);
`include "log2.inc"
// Number of 64 bit data words (stored as 72 bit words internally)
parameter NUM_WORDS = 512;
localparam ADDR_WIDTH = log2(NUM_WORDS - 1);
// For testing error detection / correction
// a 1 bit indicates inversion of the corresponding code bit
// on the encoded RAM output.
parameter PORT_A_ERROR_INJECT = 72'b0;
parameter PORT_B_ERROR_INJECT = 72'b0;
input rst;
input [ADDR_WIDTH-1:0] address_a;
input [ADDR_WIDTH-1:0] address_b;
input clock_a;
input clock_b;
input [63:0] data_a;
input [63:0] data_b;
input wren_a;
input wren_b;
output [63:0] q_a;
output [63:0] q_b;
output [2:0] err_a;
output [2:0] err_b;
///////////////////////
// port A encoder
///////////////////////
reg [63:0] data_a_reg;
always @(posedge clock_a or posedge rst) begin
if (rst) data_a_reg <= 64'b0;
else data_a_reg <= data_a;
end
wire [71:0] data_a_code;
ecc_encode_64bit enc_a (
.d(data_a_reg),
.c(data_a_code)
);
///////////////////////
// port B encoder
///////////////////////
reg [63:0] data_b_reg;
always @(posedge clock_b or posedge rst) begin
if (rst) data_b_reg <= 64'b0;
else data_b_reg <= data_b;
end
wire [71:0] data_b_code;
ecc_encode_64bit enc_b (
.d(data_b_reg),
.c(data_b_code)
);
///////////////////////
// RAM block (72 bit words)
///////////////////////
wire [71:0] q_a_code;
wire [71:0] q_b_code;
ram_block ram (
.aclr_a(rst),
.aclr_b(rst),
.address_a(address_a),
.address_b(address_b),
.clock_a(clock_a),
.clock_b(clock_b),
.data_a(data_a_code),
.data_b(data_b_code),
.wren_a(wren_a),
.wren_b(wren_b),
.q_a(q_a_code),
.q_b(q_b_code)
);
defparam ram.NUM_WORDS = NUM_WORDS; defparam ram.DAT_WIDTH = 72;
///////////////////////
// port A decoder
///////////////////////
ecc_decode_64bit dec_a (
.clk(clock_a),
.rst(rst),
.c(q_a_code ^ PORT_A_ERROR_INJECT),
.d(q_a),
.no_err(err_a[0]),
.err_corrected(err_a[1]),
.err_fatal(err_a[2])
);
defparam dec_a.OUTPUT_REG = 1; defparam dec_a.MIDDLE_REG = 1;
///////////////////////
// port B decoder
///////////////////////
ecc_decode_64bit dec_b (
.clk(clock_b),
.rst(rst),
.c(q_b_code ^ PORT_B_ERROR_INJECT),
.d(q_b),
.no_err(err_b[0]),
.err_corrected(err_b[1]),
.err_fatal(err_b[2])
);
defparam dec_b.OUTPUT_REG = 1; defparam dec_b.MIDDLE_REG = 1;
endmodule
| 8.952439 |
module soft_ecc_ram_64bit_tb ();
`include "log2.inc"
parameter NUM_WORDS = 512;
localparam ADDR_WIDTH = log2(NUM_WORDS - 1);
parameter RAM_RD_LATENCY = 4;
parameter DATA_BITS = 64;
localparam DATA_MASK = {DATA_BITS{1'b1}};
reg clk, rst;
reg [ADDR_WIDTH-1:0] address_a;
reg [ADDR_WIDTH-1:0] address_b;
reg [DATA_BITS-1:0] data_a;
reg [DATA_BITS-1:0] data_b;
reg wren_a;
reg wren_b;
wire [DATA_BITS-1:0] q_a;
wire [DATA_BITS-1:0] q_b;
wire [2:0] err_a;
wire [2:0] err_b;
//////////////////////////////////
// ECC RAM under test
//////////////////////////////////
soft_ecc_ram_64bit sr (
.rst(rst),
.address_a(address_a),
.address_b(address_b),
.clock_a(clk),
.clock_b(clk),
.data_a(data_a),
.data_b(data_b),
.wren_a(wren_a),
.wren_b(wren_b),
.q_a(q_a),
.q_b(q_b),
.err_a(err_a),
.err_b(err_b)
);
//////////////////////////////////
// test pattern control
//////////////////////////////////
reg [2:0] state;
parameter STATE_FILL_A = 0, STATE_READ_A = 1, STATE_READ_B = 2,
STATE_FILL_B = 3, STATE_READ_BOTH = 4;
reg [10:0] cntr;
reg [ 2:0] last_state;
always @(posedge clk or posedge rst) begin
if (rst) begin
cntr <= 0;
last_state <= STATE_FILL_A;
end else begin
if (state != last_state) cntr <= 0;
else cntr <= cntr + 1'b1;
last_state <= state;
end
end
initial begin
clk = 0;
rst = 0;
#10 rst = 1;
#10 rst = 0;
end
always begin
#100 clk = ~clk;
end
always @(posedge clk or posedge rst) begin
if (rst) begin
address_a <= 0;
address_b <= 0;
data_a <= 0;
data_b <= 123;
wren_a <= 1'b1;
wren_b <= 1'b0;
state <= STATE_FILL_A;
end else begin
if (state == STATE_FILL_A) begin
if (&address_a) begin
state <= STATE_READ_A;
wren_a <= 1'b0;
end
address_a <= address_a + 1'b1;
data_a <= data_a + 1'b1;
end else if (state == STATE_READ_A) begin
if (&address_a) begin
state <= STATE_READ_B;
end
address_a <= address_a + 1'b1;
if (address_a !== 0 && cntr >= RAM_RD_LATENCY && q_a !== (cntr - RAM_RD_LATENCY)) begin
$display("Mismatch in state read A");
$display(" Expected %x", (cntr - RAM_RD_LATENCY));
$display(" Read %x", q_a);
#100 $stop();
end
end else if (state == STATE_READ_B) begin
if (&address_b) begin
state <= STATE_FILL_B;
wren_b <= 1'b1;
end
address_b <= address_b + 1'b1;
if (address_b !== 0 &&
cntr >= RAM_RD_LATENCY &&
q_b !== ((cntr-RAM_RD_LATENCY) & DATA_MASK)) begin
$display("Mismatch in state read B");
#100 $stop();
end
end else if (state == STATE_FILL_B) begin
if (&address_b) begin
state <= STATE_READ_BOTH;
wren_a <= 1'b0;
wren_b <= 1'b0;
end
address_b <= address_b + 1'b1;
data_b <= data_b + 1'b1;
end else if (state == STATE_READ_BOTH) begin
if (&address_b) begin
state <= STATE_FILL_A;
data_a <= 0;
data_b <= 123;
wren_a <= 1'b1;
// stop after one test cycle
$display("PASS");
$stop();
end
address_a <= address_a + 1'b1;
address_b <= address_b + 1'b1;
if (address_b !== 0 &&
cntr >= RAM_RD_LATENCY &&
q_b !== ((cntr-RAM_RD_LATENCY+123) & DATA_MASK)) begin
$display("Mismatch in state read both");
#100 $stop();
end
end
end
end
endmodule
| 8.952439 |
module soft_ecc_ram_8bit (
rst,
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b,
err_a,
err_b
);
`include "log2.inc"
// Number of 8 bit data words (stored as 13 bit words internally)
parameter NUM_WORDS = 512;
localparam ADDR_WIDTH = log2(NUM_WORDS - 1);
// For testing error detection / correction
// a 1 bit indicates inversion of the corresponding code bit
// on the encoded RAM output.
parameter PORT_A_ERROR_INJECT = 13'b0;
parameter PORT_B_ERROR_INJECT = 13'b0;
input rst;
input [ADDR_WIDTH-1:0] address_a;
input [ADDR_WIDTH-1:0] address_b;
input clock_a;
input clock_b;
input [7:0] data_a;
input [7:0] data_b;
input wren_a;
input wren_b;
output [7:0] q_a;
output [7:0] q_b;
output [2:0] err_a;
output [2:0] err_b;
///////////////////////
// port A encoder
///////////////////////
reg [7:0] data_a_reg;
always @(posedge clock_a or posedge rst) begin
if (rst) data_a_reg <= 8'b0;
else data_a_reg <= data_a;
end
wire [12:0] data_a_code;
ecc_encode_8bit enc_a (
.d(data_a_reg),
.c(data_a_code)
);
///////////////////////
// port B encoder
///////////////////////
reg [7:0] data_b_reg;
always @(posedge clock_b or posedge rst) begin
if (rst) data_b_reg <= 8'b0;
else data_b_reg <= data_b;
end
wire [12:0] data_b_code;
ecc_encode_8bit enc_b (
.d(data_b_reg),
.c(data_b_code)
);
///////////////////////
// RAM block (13 bit words)
///////////////////////
wire [12:0] q_a_code;
wire [12:0] q_b_code;
ram_block ram (
.aclr_a(rst),
.aclr_b(rst),
.address_a(address_a),
.address_b(address_b),
.clock_a(clock_a),
.clock_b(clock_b),
.data_a(data_a_code),
.data_b(data_b_code),
.wren_a(wren_a),
.wren_b(wren_b),
.q_a(q_a_code),
.q_b(q_b_code)
);
defparam ram.NUM_WORDS = NUM_WORDS; defparam ram.DAT_WIDTH = 13;
///////////////////////
// port A decoder
///////////////////////
ecc_decode_8bit dec_a (
.clk(clock_a),
.rst(rst),
.c(q_a_code ^ PORT_A_ERROR_INJECT),
.d(q_a),
.no_err(err_a[0]),
.err_corrected(err_a[1]),
.err_fatal(err_a[2])
);
defparam dec_a.OUTPUT_REG = 1; defparam dec_a.MIDDLE_REG = 1;
///////////////////////
// port B decoder
///////////////////////
ecc_decode_8bit dec_b (
.clk(clock_b),
.rst(rst),
.c(q_b_code ^ PORT_B_ERROR_INJECT),
.d(q_b),
.no_err(err_b[0]),
.err_corrected(err_b[1]),
.err_fatal(err_b[2])
);
defparam dec_b.OUTPUT_REG = 1; defparam dec_b.MIDDLE_REG = 1;
endmodule
| 8.952439 |
module soft_gtv (
input rst,
input clk,
input spd_btn,
input [2:0] mode,
input evnt,
output [7:0] count
);
reg evnt_ff;
reg gtv_tm_flg;
wire gtv_ev_flg;
reg [7:0] gtv_cnt;
reg [7:0] gtv_cnt_ff;
reg [24:0] base_cnt;
reg [24:0] base_cnt_ff;
reg [28:0] spd_ff;
assign count = gtv_cnt_ff;
always @(posedge clk) evnt_ff <= evnt;
assign gtv_ev_flg = evnt & ~evnt_ff;
always @(posedge clk or posedge rst)
if (rst) spd_ff <= 28'b0;
else spd_ff <= spd_ff + spd_btn;
always @* begin
gtv_tm_flg = 1'b0;
base_cnt = base_cnt_ff;
if (base_cnt_ff == (25'd250000 - 25'd1 + spd_ff[28:4])) begin
gtv_tm_flg = 1'b1;
base_cnt = 25'b0;
end else begin
base_cnt = base_cnt_ff + 25'b1;
end
end
always @(posedge clk) begin
base_cnt_ff <= base_cnt;
end
always @* begin
gtv_cnt = gtv_cnt_ff;
case (mode)
0: if (gtv_tm_flg) gtv_cnt = gtv_cnt_ff - 8'b1;
1: if (gtv_tm_flg) gtv_cnt = gtv_cnt_ff + 8'b1;
4: if (gtv_ev_flg) gtv_cnt = gtv_cnt_ff - 8'b1;
5: if (gtv_ev_flg) gtv_cnt = gtv_cnt_ff + 8'b1;
default: gtv_cnt = gtv_cnt_ff;
endcase
end
always @(posedge clk or posedge rst) begin
if (rst) gtv_cnt_ff <= 8'b0;
else gtv_cnt_ff <= gtv_cnt;
end
endmodule
| 7.155872 |
module soft_pcs_8b10b_sequence_tb;
parameter VCD_FILE = "soft_pcs_8b10b_sequence_tb.vcd";
`include "tb_base.v"
// Send a random sequence of characters to the decoder and make sure the
// decoder produces the same character sequence and no disparity or
// not-in-table errors
wire [9:0] raw_data;
reg [7:0] encoder_char = 'h00;
reg encoder_charisk = 1'b0;
wire [7:0] decoder_char;
wire decoder_charisk;
wire decoder_notintable;
wire decoder_disperr;
reg encoder_disparity = 1'b0;
wire encoder_disparity_s;
reg decoder_disparity = 1'b0;
wire decoder_disparity_s;
integer x;
reg inject_enc_disparity_error = 1'b0;
/*
always @(posedge clk) begin
if ({$random} % 256 == 0) begin
inject_enc_disparity_error <= 1'b1;
end else begin
inject_enc_disparity_error <= 1'b0;
end
end
*/
always @(posedge clk) begin
x = {$random} % (256 + 5);
if (x < 256) begin
encoder_char <= x & 8'hff;
encoder_charisk <= 1'b0;
end else begin
case (x - 256)
0: encoder_char <= {3'd0, 5'd28};
1: encoder_char <= {3'd3, 5'd28};
2: encoder_char <= {3'd4, 5'd28};
3: encoder_char <= {3'd5, 5'd28};
4: encoder_char <= {3'd7, 5'd28};
endcase
encoder_charisk <= 1'b1;
end
encoder_disparity <= encoder_disparity_s ^ inject_enc_disparity_error;
decoder_disparity <= decoder_disparity_s;
end
jesd204_8b10b_encoder i_enc (
.in_char(encoder_char),
.in_charisk(encoder_charisk),
.out_char(raw_data),
.in_disparity (encoder_disparity),
.out_disparity(encoder_disparity_s)
);
jesd204_8b10b_decoder i_dec (
.in_char(raw_data),
.out_char(decoder_char),
.out_notintable(decoder_notintable),
.out_disperr(decoder_disperr),
.out_charisk(decoder_charisk),
.in_disparity (decoder_disparity),
.out_disparity(decoder_disparity_s)
);
wire char_mismatch = encoder_char != decoder_char;
wire charisk_mismatch = encoder_charisk != decoder_charisk;
always @(posedge clk) begin
if (char_mismatch == 1'b1 || charisk_mismatch == 1'b1 ||
decoder_notintable == 1'b1 || decoder_disperr == 1'b1) begin
failed <= 1'b1;
end
end
endmodule
| 7.414814 |
module soft_pcs_8b10b_table_tb;
parameter VCD_FILE = "soft_pcs_8b10b_table_tb.vcd";
`include "tb_base.v"
// Build a table of all valid 8b10b words using the encoder and then check
// for every possible 10-bit value that the decoder correctly reports the
// not-in-table flag
reg [1023:0] valid_table = 'h00;
reg [8:0] counter = 10'h00;
reg [7:0] encoder_char = 8'h00;
reg encoder_charisk = 1'b0;
reg encoder_disparity = 1'b0;
wire [9:0] encoder_raw;
wire [7:0] decoder_char;
wire decoder_notintable;
wire decoder_charisk;
reg [9:0] decoder_raw = 10'h00;
reg build_k28 = 1'b0;
reg build_table = 1'b1;
reg decoder_disparity = 1'b0;
wire decoder_disparity_s;
always @(posedge clk) begin
counter <= counter + 1'b1;
if (counter == 'h1ff) begin
build_k28 <= 1'b1;
end else if (counter == 'h9 && build_k28 == 1'b1) begin
build_table <= 1'b0;
end
end
always @(*) begin
encoder_disparity <= counter[0];
if (build_k28 == 1'b0) begin
encoder_char <= counter[8:1];
encoder_charisk <= 1'b0;
end else begin
case (counter[8:1])
0: encoder_char <= {3'd0, 5'd28};
1: encoder_char <= {3'd3, 5'd28};
2: encoder_char <= {3'd4, 5'd28};
3: encoder_char <= {3'd5, 5'd28};
4: encoder_char <= {3'd7, 5'd28};
endcase
encoder_charisk <= 1'b1;
end
end
jesd204_8b10b_encoder i_enc (
.in_char(encoder_char),
.in_charisk(encoder_charisk),
.in_disparity(encoder_disparity),
.out_char(encoder_raw)
);
always @(posedge clk) begin
if (build_table == 1'b1) begin
valid_table[encoder_raw] <= 1'b1;
end
end
always @(posedge clk) begin
if (build_table == 1'b0) begin
decoder_disparity <= ~decoder_disparity;
if (decoder_disparity == 1'b1 && decoder_raw != 'h3ff) begin
decoder_raw <= decoder_raw + 1'b1;
end
end
end
always @(posedge clk) begin
end
jesd204_8b10b_decoder i_dec (
.in_char(build_table ? encoder_raw : decoder_raw),
.out_char(decoder_char),
.out_notintable(decoder_notintable),
.out_charisk(decoder_charisk),
.in_disparity (decoder_disparity),
.out_disparity(decoder_disparity_s)
);
wire decoder_should_be_in_table = valid_table[decoder_raw];
always @(posedge clk) begin
if (build_table == 1'b0) begin
if (decoder_notintable == decoder_should_be_in_table) begin
$display("%b.%b, %d", decoder_raw[9:6], decoder_raw[5:0], decoder_should_be_in_table);
failed <= 1'b1;
end
end
end
endmodule
| 7.414814 |
module soft_pcs_pattern_align_tb;
parameter VCD_FILE = "soft_pcs_pattern_align_tb.vcd";
localparam [9:0] PATTERN_P = 10'b1010000011;
localparam [9:0] PATTERN_N = 10'b0101111100;
`define TIMEOUT 1000000
`include "tb_base.v"
integer counter = 0;
reg [3:0] bitshift = 4'd0;
reg [9:0] comma_unaligned;
reg comma_sync = 1'b0;
wire [9:0] comma_aligned;
reg [9:0] comma = PATTERN_P;
wire comma_match = comma == comma_aligned;
always @(posedge clk) begin
if (counter == 63) begin
if (comma_sync != 1'b1) begin
failed <= 1'b1;
end
comma_sync <= 1'b0;
counter <= 0;
bitshift <= {$random} % 10;
comma <= {$random} % 2 ? PATTERN_P : PATTERN_N;
end else begin
counter <= counter + 1'b1;
// Takes two clock cycles for the new value to propagate
if (counter > 1) begin
// Shouldn't loose sync after it gained it
if (comma_match == 1'b1) begin
comma_sync <= 1'b1;
end else if (comma_sync == 1'b1) begin
failed <= 1'b1;
end
end
end
end
always @(*) begin
case (bitshift)
4'd0: comma_unaligned <= comma[9:0];
4'd1: comma_unaligned <= {comma[0], comma[9:1]};
4'd2: comma_unaligned <= {comma[1:0], comma[9:2]};
4'd3: comma_unaligned <= {comma[2:0], comma[9:3]};
4'd4: comma_unaligned <= {comma[3:0], comma[9:4]};
4'd5: comma_unaligned <= {comma[4:0], comma[9:5]};
4'd6: comma_unaligned <= {comma[5:0], comma[9:6]};
4'd7: comma_unaligned <= {comma[6:0], comma[9:7]};
4'd8: comma_unaligned <= {comma[7:0], comma[9:8]};
default: comma_unaligned <= {comma[8:0], comma[9]};
endcase
end
jesd204_pattern_align #(
.DATA_PATH_WIDTH(1)
) i_pa (
.clk(clk),
.reset(1'b0),
.patternalign_en(1'b1),
.in_data (comma_unaligned),
.out_data(comma_aligned)
);
endmodule
| 7.906764 |
module soft_trig_generator (
ctrl_i,
ctrlclk_i,
trigclk_i,
slow_ce_i,
trig_o
);
input [7:0] ctrl_i;
input ctrlclk_i;
input trigclk_i;
input slow_ce_i;
output trig_o;
wire [3:0] delay_count = ctrl_i[7:4];
wire [2:0] trig_count = ctrl_i[3:1];
wire trig_go = ctrl_i[0];
reg [4:0] delay_counter = {4{1'b0}};
reg [2:0] trig_counter = {3{1'b0}};
wire trig_flag;
SYNCEDGE_R trig_flag_gen (
.I (trig_go),
.O (trig_flag),
.CLK(ctrlclk_i)
);
reg trig_busy = 0;
always @(posedge ctrlclk_i) begin
if ((trig_counter == trig_count) && (delay_counter > delay_count)) trig_busy <= 0;
else if (trig_flag) trig_busy <= 1;
end
// This is naturally a flag, because when delay_counter exceeds delay_count,
// it resets delay_counter (so it can no longer exceed it).
wire trigger = (trig_busy && (delay_counter > delay_count));
reg trig_flag_to_trigclk = 0;
always @(posedge ctrlclk_i) trig_flag_to_trigclk <= trigger;
always @(posedge ctrlclk_i) begin
if (trig_busy) begin
if (delay_counter > delay_count) delay_counter <= {4{1'b0}};
else if (slow_ce_i) delay_counter <= delay_counter + 1;
end else delay_counter <= {4{1'b0}};
end
always @(posedge ctrlclk_i) begin
if (trig_busy) begin
if (trigger) trig_counter <= trig_counter + 1;
end else trig_counter <= {3{1'b0}};
end
flag_sync trig_flag_sync (
.in_clkA(trig_flag_to_trigclk),
.out_clkB(trig_o),
.clkA(ctrlclk_i),
.clkB(trigclk_i)
);
endmodule
| 6.548026 |
module Soft_Vector_Processor
//---------------------------------------------------------------------------------------------------------------------------------------------------
// Customizable parameters at generation
//---------------------------------------------------------------------------------------------------------------------------------------------------
#(
// need to specify in decimal due to a bug in SOPC builder
parameter RESET_ADDRESS = 0,
parameter BREAK_ADDRESS = 0,
parameter EXCEPTION_ADDRESS = 32,
parameter CPU_ID = 3,
// parameter RESET_ADDRESS = 32'h00000000,
// parameter BREAK_ADDRESS = 32'h00000000,
// parameter EXCEPTION_ADDRESS = 32'h00000020,
// parameter CPU_ID = 32'h00000003,
// Vector processor primary parameters
parameter VPU_WIDTH = 32,
parameter NUMLANES = 8,
parameter MEM_WIDTH = 128,
parameter MINDATAWIDTH = 8
)
//---------------------------------------------------------------------------------------------------------------------------------------------------
// Port declaration
//---------------------------------------------------------------------------------------------------------------------------------------------------
(
// Global signals
input csi_clockreset_clk,
input csi_clockreset_reset_n,
// input [31:0] inr_data_master_irq,
input [31:0] inr_receiver_irq,
// Avalon Master 1 : Instruction master
input [31:0] avm_instruction_master_readdata,
input avm_instruction_master_waitrequest,
// Avalon Master 2: Data master
// input [31:0] avm_data_master_irq,
input [MEM_WIDTH-1:0] avm_data_master_readdata, // data from main memory
input avm_data_master_waitrequest,
// Outputs
// Avalon Master 1: Instruction master
output [31:0] avm_instruction_master_address,
output avm_instruction_master_read,
// Avalon Master 2: Data master
output [MEM_WIDTH/8-1:0] avm_data_master_byteenable,
output [ MEM_WIDTH-1:0] avm_data_master_writedata,
output [ 31:0] avm_data_master_address,
output avm_data_master_read,
output avm_data_master_write
);
//---------------------------------------------------------------------------------------------------------------------------------------------------
// Instantiate the processor
//---------------------------------------------------------------------------------------------------------------------------------------------------
VectCPU
// Pass parameters
#(
.RESET_ADDRESS (RESET_ADDRESS),
.BREAK_ADDRESS (BREAK_ADDRESS),
.EXCEPTION_ADDRESS(EXCEPTION_ADDRESS),
.CPU_ID (CPU_ID),
// vector processor primary parameters
.VPU_WIDTH (VPU_WIDTH),
.NUMLANES (NUMLANES),
.MEM_WIDTH (MEM_WIDTH),
.MINDATAWIDTH (MINDATAWIDTH)
) the_VectCPU (
// Global signals
.clk (csi_clockreset_clk),
.reset_n(csi_clockreset_reset_n),
// Avalon Master 1 : Instruction master
.i_readdata (avm_instruction_master_readdata),
.i_waitrequest(avm_instruction_master_waitrequest),
// Avalon Master 2: Data master
.d_irq (inr_receiver_irq),
.d_readdata (avm_data_master_readdata), // data from main memory
.d_waitrequest(avm_data_master_waitrequest),
// Outputs
// Avalon Master 1: Instruction master
.i_address(avm_instruction_master_address),
.i_read (avm_instruction_master_read),
// Avalon Master 2: Data master
.d_byteenable(avm_data_master_byteenable),
.d_writedata (avm_data_master_writedata),
.d_address (avm_data_master_address),
.d_read (avm_data_master_read),
.d_write (avm_data_master_write)
);
endmodule
| 8.047667 |
module divider (
input clk,
input rst_n,
output reg s_counter3_flg
);
//计时0.2S
reg [9:0] s_counter1;
reg [9:0] s_counter2;
reg [9:0] s_counter3;
reg s_counter2_flg;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
s_counter1 <= 6'd0;
end else if (s_counter1 == 6'd49) begin
s_counter1 <= 6'd0;
end else begin
s_counter1 <= s_counter1 + 6'd1;
end
end
//分频后s_counter1为1MHz
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
s_counter2 <= 10'd0;
s_counter2_flg <= 1'd0;
end else if (s_counter1 == 6'd49) begin
if (s_counter2 == 10'd999) begin
s_counter2_flg <= 1'd1;
s_counter2 <= 10'd0;
end else begin
s_counter2_flg <= 1'd0;
s_counter2 <= s_counter2 + 10'd1;
end
end else begin
s_counter2_flg <= 1'd0;
s_counter2 <= s_counter2;
end
end
//分频后s_counter2_flg为1kHz
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
s_counter3 <= 10'd0;
s_counter3_flg <= 1'd0;
end else if (s_counter2_flg == 1'd1) begin
if (s_counter3 == 10'd199) begin
s_counter3_flg <= 1'd1;
s_counter3 <= 10'd0;
end else begin
s_counter3_flg <= 1'd0;
s_counter3 <= s_counter3 + 10'd1;
end
end else begin
s_counter3_flg <= 1'd0;
s_counter3 <= s_counter3;
end
end
//分频后s_counter3_flg为5Hz
endmodule
| 7.389371 |
module people_move (
input clk,
input rst_n,
input BTN_WEST,
input BTN_EAST,
input BTN_SOUTH,
input BTN_NORTH,
input s_counter3_flg,
output reg move_left,
output reg move_right,
output reg move_up,
output reg move_down
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
move_left <= 1'b0;
move_right <= 1'b0;
move_up <= 1'b0;
move_down <= 1'b0;
end else if ((BTN_WEST == 1) && (s_counter3_flg == 1'b1)) begin
move_left <= 1'b1;
end else if ((BTN_EAST == 1) && (s_counter3_flg == 1'b1)) begin
move_right <= 1'b1;
end else if ((BTN_NORTH == 1) && (s_counter3_flg == 1'b1)) begin
move_up <= 1'b1;
end else if ((BTN_SOUTH == 1) && (s_counter3_flg == 1'b1)) begin
move_down <= 1'b1;
end else begin
move_left <= 1'b0;
move_right <= 1'b0;
move_up <= 1'b0;
move_down <= 1'b0;
end
end
endmodule
| 7.254119 |
module enabled_color (
input clk,
input rst_n,
input biankuang,
input zhangai_1,
input zhangai_2,
input xiangzi_biaozhi,
input xiangzi_show,
input xiangzi_show_1,
input xiangzi_show_2,
input win_point,
input win_point_1,
input win_point_2,
input win_point_flg,
input win_point_flg_1,
input win_point_flg_2,
input enable_green,
input enable_blue_2,
input enable_red_1,
input enable_red_2,
input enable_red_3,
output reg vga_red,
output reg vga_green,
output reg vga_blue
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
vga_blue <= 1'b0;
vga_green <= 1'b0;
vga_red <= 1'b0;
end else if (win_point == 1'b1) begin
vga_blue <= 1'b0;
vga_green <= enable_green;
vga_red <= 1'b0;
end else if ((xiangzi_biaozhi == 1'b1) && (win_point == 1'b0)) begin
if (enable_blue_2 == 1'b1) begin
vga_blue <= 1'b1;
vga_green <= 1'b0;
vga_red <= 1'b0;
end else begin
vga_blue <= 1'b1;
vga_green <= 1'b1;
vga_red <= 1'b1;
end
end else if ((xiangzi_show == 1'b1) && (win_point == 1'b0)) begin
vga_blue <= 1'b0;
vga_green <= 1'b1;
vga_red <= 1'b0;
end else if ((xiangzi_show_1 == 1'b1) && (win_point == 1'b0)) begin
vga_blue <= 1'b0;
vga_green <= 1'b1;
vga_red <= 1'b0;
end else if ((xiangzi_show_2 == 1'b1) && (win_point == 1'b0)) begin
vga_blue <= 1'b0;
vga_green <= 1'b1;
vga_red <= 1'b0;
end else if ((win_point_flg == 1'b1) && (win_point == 1'b0)) begin
if (enable_red_1 == 1'b1) begin
vga_blue <= 1'b0;
vga_green <= 1'b0;
vga_red <= 1'b1;
end else begin
vga_blue <= 1'b1;
vga_green <= 1'b1;
vga_red <= 1'b1;
end
end else if ((win_point_flg_1 == 1'b1) && (win_point == 1'b0)) begin
if (enable_red_2 == 1'b1) begin
vga_blue <= 1'b0;
vga_green <= 1'b0;
vga_red <= 1'b1;
end else begin
vga_blue <= 1'b1;
vga_green <= 1'b1;
vga_red <= 1'b1;
end
end else if ((win_point_flg_2 == 1'b1) && (win_point == 1'b0)) begin
if (enable_red_3 == 1'b1) begin
vga_blue <= 1'b0;
vga_green <= 1'b0;
vga_red <= 1'b1;
end else begin
vga_blue <= 1'b1;
vga_green <= 1'b1;
vga_red <= 1'b1;
end
end else if ((zhangai_1 == 1'b1) && (win_point == 1'b0)) begin
vga_blue <= 1'b1;
vga_green <= 1'b1;
vga_red <= 1'b0;
end else if ((zhangai_2 == 1'b1) && (win_point == 1'b0)) begin
vga_blue <= 1'b1;
vga_green <= 1'b1;
vga_red <= 1'b0;
end
else if((xiangzi_biaozhi == 1'b0)&&(xiangzi_show == 1'b0)&&(win_point_flg == 1'b0)&&(biankuang == 1'b1)&&( win_point == 1'b0 )&&
( xiangzi_show_1 == 1'b0 )&&( win_point_flg_1 == 1'b0 )&&( xiangzi_show_2 == 1'b0 )&&( win_point_flg_2 == 1'b0 )&&
(zhangai_1 == 1'b0)&&(zhangai_2 == 1'b0))begin
vga_blue <= 1'b1;
vga_green <= 1'b1;
vga_red <= 1'b1;
end else begin
vga_blue <= 1'b0;
vga_green <= 1'b0;
vga_red <= 1'b0;
end
end
endmodule
| 6.859694 |
module solid_color_screen (
state,
hcnt,
vcnt,
color,
color_out
);
input state, hcnt, vcnt, color;
output color_out;
wire [1:0] state;
wire [9:0] hcnt, vcnt;
wire [2:0] color;
reg [2:0] color_out;
always @(*) begin
if (state == 2'b00) color_out <= color;
else color_out <= 3'bzzz;
end
endmodule
| 6.566949 |
module mux_2x1 (
out,
seli,
a,
b
);
input seli, a, b;
output out;
assign out = seli ? a : b;
endmodule
| 6.925133 |
module mux_8x1 (
out,
sel,
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7
);
input in0, in1, in2, in3, in4, in5, in6, in7;
input [2:0] sel;
output out;
//assign out = sel[2] ? (sel[1] ? (sel[0] ? in7:in6) : (sel[0] ? in5:in4)) : (sel[1] ? (sel[0] ? in7:in6) : (sel[0] ? in7:in6));
assign out=(sel==3'b111)?in7:(sel==3'b110)?in6:(sel==3'b101)?in5:(sel==3'b100)?in4:(sel==3'b011)?in3:(sel==3'b010)?in2:(sel==3'b001)?in1:in0;
endmodule
| 7.358788 |
module counter_3bit (
count,
clear,
clk
);
input clear, clk;
output reg [2:0] count;
always @(posedge clk or negedge clear) begin
if (!clear) begin
count <= 3'b000;
end else begin
count <= count + 1;
end
end
endmodule
| 7.241203 |
module decoder (
out,
en,
count
);
input en;
input [2:0] count;
output reg [7:0] out;
always @(en or count) begin
out = 8'b00000000;
if (en) begin
case (count)
3'b000: out[0] <= 1;
3'b001: out[1] <= 1;
3'b010: out[2] <= 1;
3'b011: out[3] <= 1;
3'b100: out[4] <= 1;
3'b101: out[5] <= 1;
3'b110: out[6] <= 1;
3'b111: out[7] <= 1;
endcase
end
end
endmodule
| 7.018254 |
module top_module (
o,
clear,
clk,
en,
s
);
input en, clk, clear;
input [2:0] s;
output o;
wire [2:0] count;
wire [7:0] c, g, e;
counter_3bit cnt (
count,
clear,
clk
);
decoder d (
c,
en,
count
);
memory m (
g,
s
);
mux_array m1 (
e,
g,
c,
8'b00000000
);
mux_8x1 m2 (
o,
count,
e[0],
e[1],
e[2],
e[3],
e[4],
e[5],
e[6],
e[7]
);
endmodule
| 7.203305 |
module FPGA_SOLOMON (
input MCLK, // 48.0MHz
input RESET,
input [7:0] INP0,
input [7:0] INP1,
input [7:0] INP2,
input [7:0] DSW0,
input [7:0] DSW1,
input [8:0] PH,
input [8:0] PV,
output PCLK,
output [11:0] POUT,
output [15:0] SND,
input ROMCL,
input [19:0] ROMAD,
input [7:0] ROMDT,
input ROMEN
);
// Clock Generator
wire CLK24M, CLK12M, CLK6M, CLK4M, CLK3M, CLK1M5;
SOLOMON_CLKGEN cgen (
MCLK,
CLK24M,
CLK12M,
CLK6M,
CLK4M,
CLK3M,
CLK1M5
);
wire VCLKx8 = MCLK;
wire VCLKx4 = CLK24M;
wire VCLKx2 = CLK12M;
wire VCLK = CLK6M;
wire CPUCL = CLK4M;
wire SCPUCL = CLK3M;
// Main CPU
wire [15:0] CPUAD;
wire [7:0] CPUWD, VIDDT;
wire CPUMW, SNDWR, VIDDV, VBLK;
SOLOMON_MAIN main (
RESET,
CPUCL,
CPUAD,
CPUWD,
CPUMW,
SNDWR,
VIDDT,
VIDDV,
VBLK,
INP0,
INP1,
INP2,
DSW0,
DSW1,
ROMCL,
ROMAD,
ROMDT,
ROMEN
);
// Video
wire SNDT;
SOLOMON_VIDEO video (
VCLKx4,
VCLKx2,
VCLK,
PH,
PV,
PCLK,
POUT,
VBLK,
SNDT,
CPUCL,
CPUAD,
CPUMW,
CPUWD,
VIDDT,
VIDDV,
ROMCL,
ROMAD,
ROMDT,
ROMEN
);
// Sound
wire [7:0] SNDNO = CPUWD;
SOLOMON_SOUND sound (
RESET,
SCPUCL,
CPUCL,
SNDNO,
SNDWR,
SNDT,
CLK1M5,
SND,
ROMCL,
ROMAD,
ROMDT,
ROMEN
);
endmodule
| 6.638126 |
module PROTECT (
input RESET,
input CPUCL,
input [15:0] CPUAD,
input CPUMW,
input [7:0] CPUWD,
output reg [7:0] OUT
);
always @(posedge CPUCL or posedge RESET) begin
if (RESET) OUT <= 0;
else begin
if ((CPUAD == 16'hE803) & CPUMW) OUT <= (CPUWD & 8'h08);
end
end
endmodule
| 6.929555 |
module MAINROM (
input CL,
input [15:0] AD,
output [7:0] DT,
output DV,
input DLCL,
input [19:0] DLAD,
input [7:0] DLDT,
input DLEN
);
/*
34000-37FFF MAINCPU0
38000-3FFFF MAINCPU1 (4000h swaped)
40000-40FFF MAINCPU2
*/
wire [7:0] dt0, dt1, dt2, dt3;
DLROM #(14, 8) r0 (
CL,
AD[13:0],
dt0,
DLCL,
DLAD,
DLDT,
DLEN & (DLAD[19:14] == 6'b0011_01)
);
DLROM #(14, 8) r1 (
CL,
AD[13:0],
dt1,
DLCL,
DLAD,
DLDT,
DLEN & (DLAD[19:14] == 6'b0011_11)
);
DLROM #(14, 8) r2 (
CL,
AD[13:0],
dt2,
DLCL,
DLAD,
DLDT,
DLEN & (DLAD[19:14] == 6'b0011_10)
);
DLROM #(12, 8) r3 (
CL,
AD[11:0],
dt3,
DLCL,
DLAD,
DLDT,
DLEN & (DLAD[19:12] == 8'b0100_0000)
);
wire dv0 = (AD[15:14] == 2'b00);
wire dv4 = (AD[15:14] == 2'b01);
wire dv8 = (AD[15:14] == 2'b10);
wire dvF = (AD[15:12] == 4'b1111);
assign DT = dvF ? dt3 : dv8 ? dt2 : dv4 ? dt1 : dv0 ? dt0 : 8'h0;
assign DV = dvF | dv8 | dv4 | dv0;
endmodule
| 6.632587 |
module BGROM (
input CL,
input [15:0] AD,
output [7:0] DT,
input DLCL,
input [19:0] DLAD,
input [7:0] DLDT,
input DLEN
);
/*
20000-27FFF BGCHIP0
28000-2FFFF BGCHIP1
*/
DLROM #(16, 8) r (
CL,
AD,
DT,
DLCL,
DLAD,
DLDT,
DLEN & (DLAD[19:16] == 4'd2)
);
endmodule
| 6.673735 |
module SNDROM (
input CL,
input [13:0] AD,
output [7:0] DT,
input DLCL,
input [19:0] DLAD,
input [7:0] DLDT,
input DLEN
);
// 30000-33FFF SNDCPU
DLROM #(14, 8) r (
CL,
AD,
DT,
DLCL,
DLAD,
DLDT,
DLEN & (DLAD[19:14] == 6'b0011_00)
);
endmodule
| 6.508443 |
module DLROM #(
parameter AW,
parameter DW
) (
input CL0,
input [(AW-1):0] AD0,
output reg [(DW-1):0] DO0,
input CL1,
input [(AW-1):0] AD1,
input [(DW-1):0] DI1,
input WE1
);
reg [(DW-1):0] core[0:((2**AW)-1)];
always @(posedge CL0) DO0 <= core[AD0];
always @(posedge CL1) if (WE1) core[AD1] <= DI1;
endmodule
| 6.544719 |
module SOLOMON_SOUND (
input RESET,
input CPUCL,
input AXSCL,
input [7:0] SNDNO,
input SNDWR,
input SNDT,
input PSGCL,
output [15:0] SNDO,
input DLCL,
input [19:0] DLAD,
input [7:0] DLDT,
input DLEN
);
wire [15:0] CPUAD;
wire [7:0] CPUID, CPUWD;
wire CPUMR, CPUMW, CPUIW;
wire CPUNMI, CPUIRQ;
wire [7:0] SNDLT, RAMDT, ROMDT;
wire LATDV, RAMDV, ROMDV;
SSADEC adec (
CPUAD,
LATDV,
RAMDV,
ROMDV
);
RAM800 wram (
CPUCL,
CPUAD[10:0],
RAMDV & CPUMW,
CPUWD,
RAMDT
);
SNDROM irom (
CPUCL,
CPUAD[13:0],
ROMDT,
DLCL,
DLAD,
DLDT,
DLEN
);
DSEL3D dsel (
CPUID,
CPUMR,
LATDV,
SNDLT,
RAMDV,
RAMDT,
ROMDV,
ROMDT
);
INTCTR ictr (
RESET,
AXSCL,
SNDNO,
SNDWR,
SNDT,
CPUNMI,
CPUIRQ,
SNDLT
);
Z80IP scpu (
RESET,
CPUCL,
CPUAD,
CPUID,
CPUWD,
CPUMR,
CPUMW,
CPUNMI,
CPUIRQ,
CPUIW
);
PSGx3 psgs (
RESET,
PSGCL,
CPUCL,
CPUAD[7:0],
CPUIW,
CPUWD,
SNDO
);
endmodule
| 6.670566 |
module INTCTR (
input RESET,
input AXSCL,
input [7:0] SNDNO,
input SNDWR,
input SNDT,
output NMI,
output IRQ,
output reg [7:0] SNDLT
);
reg [3:0] NMICN, IRQCN;
reg pSNDW, pIRQQ;
assign NMI = (NMICN != 0);
assign IRQ = (IRQCN != 0);
always @(posedge AXSCL or posedge RESET) begin
if (RESET) begin
SNDLT <= 0;
NMICN <= 0;
IRQCN <= 0;
pSNDW <= 0;
pIRQQ <= 0;
end else begin
pSNDW <= SNDWR;
if ((pSNDW ^ SNDWR) & SNDWR) begin
SNDLT <= SNDNO;
NMICN <= 15;
end else begin
NMICN <= NMI ? (NMICN - 1) : 0;
end
pIRQQ <= SNDT;
if ((pIRQQ ^ SNDT) & SNDT) begin
IRQCN <= 15;
end else begin
IRQCN <= IRQ ? (IRQCN - 1) : 0;
end
end
end
endmodule
| 6.519803 |
module PSGx3 (
input RESET,
input PSGCL,
input CL,
input [7:0] AD,
input WR,
input [7:0] OD,
output [15:0] SNDOUT
);
wire [7:0] A0, B0, C0;
wire [7:0] A1, B1, C1;
wire [7:0] A2, B2, C2;
wire rst = ~RESET;
wire asel = ~AD[0];
wire wd = ~WR;
wire cs_sg1 = ~(AD[7:4] == 4'h1);
wire cs_sg2 = ~(AD[7:4] == 4'h2);
wire cs_sg3 = ~(AD[7:4] == 4'h3);
PSG sg1 (
rst,
CL,
PSGCL,
asel,
cs_sg1,
wd,
OD,
A0,
B0,
C0
);
PSG sg2 (
rst,
CL,
PSGCL,
asel,
cs_sg2,
wd,
OD,
A1,
B1,
C1
);
PSG sg3 (
rst,
CL,
PSGCL,
asel,
cs_sg3,
wd,
OD,
A2,
B2,
C2
);
wire [15:0] o = A0+B0+C0+A1+B1+C1+A2+B2+C2;
wire f = (o[15]|o[14]||o[13]|o[12]);
wire [11:0] p = {12{f}}|o[11:0];
assign SNDOUT = {p, 4'h0};
endmodule
| 6.574222 |
module debounced_counter (
// Inputs
input clk,
input rst_btn,
input inc_btn,
// Outputs
output reg [3:0] led
);
// States
localparam STATE_HIGH = 2'd0;
localparam STATE_LOW = 2'd1;
localparam STATE_WAIT = 2'd2;
localparam STATE_PRESSED = 2'd3;
// Max counts for wait state (40 ms with 12 MHz clock)
localparam MAX_CLK_COUNT = 20'd480000 - 1;
// Internal signals
wire rst;
wire inc;
// Internal storage elements
reg [1:0] state;
reg [19:0] clk_count;
// Invert active-low buttons
assign rst = ~rst_btn;
assign inc = ~inc_btn;
// State transition logic
always @(posedge clk or posedge rst) begin
// On reset, return to idle state and restart counters
if (rst == 1'b1) begin
state <= STATE_HIGH;
led <= 4'd0;
// Define the state transitions
end else begin
case (state)
// Wait for increment signal to go from high to low
STATE_HIGH: begin
if (inc == 1'b0) begin
state <= STATE_LOW;
end
end
// Wait for increment signal to go from low to high
STATE_LOW: begin
if (inc == 1'b1) begin
state <= STATE_WAIT;
end
end
// Wait for count to be done and sample button again
STATE_WAIT: begin
if (clk_count == MAX_CLK_COUNT) begin
if (inc == 1'b1) begin
state <= STATE_PRESSED;
end else begin
state <= STATE_HIGH;
end
end
end
// If button is still pressed, increment LED counter
STATE_PRESSED: begin
led <= led + 1;
state <= STATE_HIGH;
end
// Default case: return to idle state
default: state <= STATE_HIGH;
endcase
end
end
// Run counter if in wait state
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
clk_count <= 20'd0;
end else begin
if (state == STATE_WAIT) begin
clk_count <= clk_count + 1;
end else begin
clk_count <= 20'd0;
end
end
end
endmodule
| 8.528321 |
module is to solve the problem of "read after write"
//In order to solve this problem, I design a module to forward the data of WB to ID.
module Solution_of_RAW(
input [4:0]RsAddr_id,
input [4:0]RtAddr_id,
input [4:0]RegWriteAddr_wb,
input RegWrite_wb,
output reg Rs_selection,
output reg Rt_selection
);
always@(*)
begin
if(RegWrite_wb && (RegWriteAddr_wb != 0) && (RegWriteAddr_wb == RsAddr_id))
Rs_selection <= 1;
else
Rs_selection = 0;
if(RegWrite_wb && (RegWriteAddr_wb != 0) && (RegWriteAddr_wb == RtAddr_id))
Rt_selection <= 1;
else
Rt_selection <= 0;
end
endmodule
| 7.501975 |
module Solver (
Clk,
data_1_80,
data_2_96,
work_2,
output_1_96,
output_2_80
);
input Clk;
input [59:0] data_1_80;
input [77:0] data_2_96;
input [1:0] work_2;
output [77:0] output_1_96;
output [59:0] output_2_80;
wire [77:0] output_1_96_ENC_INTERNAL;
wire [59:0] output_2_80_DEC_INTERNAL;
wire [59:0] output_2_80_PASS_INTERNAL;
reg [77:0] output_1_96;
reg [59:0] output_2_80;
Encrypter ENC (
.Clk(Clk),
.data_to_be_encrpt(data_1_80),
.output_encrypted(output_1_96_ENC_INTERNAL)
);
Decrypter DEC (
Clk,
data_2_96,
output_2_80_DEC_INTERNAL
);
Password_Gen PASSGEN (
.Clk(Clk),
.output_2_80(output_2_80_PASS_INTERNAL)
);
always @(posedge Clk) begin
if (work_2 == 2'b00) output_1_96 = output_1_96_ENC_INTERNAL;
else if (work_2 == 2'b01) output_2_80 = output_2_80_DEC_INTERNAL;
else if (work_2 == 2'b10) output_2_80 = output_2_80_PASS_INTERNAL;
end
endmodule
| 7.170249 |
module solve_color (
input clk,
input vga_clk,
input rst,
input [9:0] col_addr,
input [8:0] row_addr,
// Slope effect
input [10:0] sin_x,
input [10:0] sin_y,
// Player tracing
input [10:0] position_x,
input [10:0] position_y,
// Mode related
input [1:0] map,
input mode,
input [10:0] score_x,
input [10:0] score_y,
input [11:0] score_color,
// Color output
output [11:0] color,
// Coliision checking based on pixel scan
output reg [3:0] collision
);
wire [10:0] real_x;
wire [10:0] real_y;
// transform coords
transform_mapping transform (
.clk(clk),
.sin_x(sin_x),
.sin_y(sin_y),
.x({1'b0, col_addr} + ~11'd80 + 11'd1),
.y({2'b0, row_addr}),
.x_out(real_x),
.y_out(real_y)
);
// draw player
wire [11:0] player_color;
wire in_player;
wire near_player;
draw_player d0 (
.clk(clk),
.rst(rst),
.x(real_x),
.y(real_y),
.position_x(position_x),
.position_y(position_y),
.player_color(player_color),
.in_player(in_player),
.near_player(near_player)
);
// draw score target
wire [11:0] r_score_color;
draw_score s0 (
.clk(clk),
.rst(rst),
.x(real_x),
.y(real_y),
.mode(mode),
.score_x(score_x),
.score_y(score_y),
.score_color(score_color),
.color(r_score_color)
);
// draw map
wire [11:0] map_color;
draw_map m0 (
.clk(clk),
.x(real_x),
.y(real_y),
.map(map),
.color(map_color)
);
// composite
assign color = (in_player==1'b1) ? player_color : ((r_score_color==`NULL) ? map_color : r_score_color);
// process collision
always @(posedge vga_clk) begin
if (near_player) begin
// if accessible
if (map_color == `BLANK || map_color == 12'hfff) begin
collision = 4'b0;
end else begin
if (real_x > position_x + `delta) collision[0] = 1'b1;
if (real_x < position_x + ~`delta + 11'b1) collision[1] = 1'b1;
if (real_y > position_y + `delta) collision[2] = 1'b1;
if (real_y < position_y + ~`delta + 11'b1) collision[3] = 1'b1;
end
end else begin
collision = 4'b0;
end
end
endmodule
| 7.180927 |
module solve_img_top #(
parameter ADDR_WIDTH = 18,
parameter STATE_WIDTH = 5
) (
input wire clk,
output wire rst_n,
//ram port of b
output wire enb,
output wire web,
output wire [ADDR_WIDTH-1:0] addrb,
output wire [7:0] dinb,
input wire [7:0] doutb,
//dmn cell ports
output wire [31:0] width,
output wire [31:0] height,
output wire dmn_en,
input wire dmn_end,
input wire dmn_web,
input wire [7:0] dmn_dinb,
input wire [ADDR_WIDTH-1:0] dmn_addrb,
//axi slave control
input [31:0] slv_reg0,
input [31:0] slv_reg1,
output [31:0] slv_reg2,
output [31:0] slv_reg3
);
wire im_start;
wire im_work;
wire om_start;
wire om_work;
//standard ports
assign rst_n = slv_reg0[4];
assign im_start = slv_reg0[1];
assign im_work = slv_reg0[0];
assign slv_reg3[0] = om_work;
assign slv_reg3[1] = om_start;
assign slv_reg3[31:2] = 1'b0;
solve_img U1_solve (
.clk(clk),
.rst_n(rst_n),
.enb(enb),
.web(web),
.addrb(addrb),
.dinb(dinb),
.doutb(doutb),
//dmn cell
.width(width),
.height(height),
.w1_work(dmn_en),
.w1_work_end(dmn_end),
.web_w1(dmn_web),
.dinb_w1(dmn_dinb),
.addrb_w1(dmn_addrb),
//-------
.im_start(im_start),
.im_work(im_work),
.im_data(slv_reg1),
.om_data(slv_reg2),
.om_start(om_start),
.om_work(om_work)
);
endmodule
| 6.509655 |
module solve_position (
input clk,
input rst,
input [10:0] init_x,
input [10:0] init_y,
// input for checking scoring
input [10:0] score_x,
input [10:0] score_y,
input [10:0] velocity_x,
input [10:0] velocity_y,
// input for immediate react to collision
input [3:0] collision,
output [10:0] position_x,
output [10:0] position_y,
// output for scoring
output reg win
);
reg [15:0] x = 16'd0;
reg [15:0] y = 16'd0;
// v to unsigned v
wire [10:0] u_vx;
wire [10:0] u_vy;
assign u_vx = (velocity_x[10] == 1'b1) ? (~velocity_x + 11'd1) >> 1 : velocity_x >> 1;
assign u_vy = (velocity_y[10] == 1'b1) ? (~velocity_y + 11'd1) >> 1 : velocity_y >> 1;
// position delta
wire [15:0] deltax;
wire [15:0] deltay;
assign deltax = {5'b0, u_vx[10:0]};
assign deltay = {5'b0, u_vy[10:0]};
always @(posedge clk or negedge rst) begin
if (!rst) begin
win <= 1'b0;
x <= {init_x[8:0], 7'b0};
y <= {init_y[8:0], 7'b0};
end // stay win state
else if (win || near_score) begin
win <= 1'b1;
x <= {score_x[8:0], 7'b0};
y <= {score_y[8:0], 7'b0};
end else begin
win <= 1'b0;
case (collision[1:0])
2'b00:
// bouncing
x <= x + {{6{velocity_x[10]}}, velocity_x[9:0]};
2'b10: x <= x + deltax;
2'b01: x <= x + ~deltax + 16'b1;
endcase
case (collision[3:2])
2'b00:
// bouncing
y <= y + {{6{velocity_y[10]}}, velocity_y[9:0]};
2'b10: y <= y + deltay;
2'b01: y <= y + ~deltay + 16'b1;
endcase
end
end
// turn local parameter to global position
wire [10:0] scaled_x;
wire [10:0] scaled_y;
assign scaled_x = {2'b0, x[15:7]};
assign scaled_y = {2'b0, y[15:7]};
// distance to target
wire [10:0] diff_x;
wire [10:0] diff_y;
assign diff_x = (scaled_x>score_x) ? (scaled_x+~score_x+11'b1) : (score_x+~scaled_x+11'b1);
assign diff_y = (scaled_y>score_y) ? (scaled_y+~score_y+11'b1) : (score_y+~scaled_y+11'b1);
// is about to scoring
wire near_score;
assign near_score = diff_x[9:0] <= `DIFF && diff_y[9:0] <= `DIFF;
assign position_x = scaled_x;
assign position_y = scaled_y;
endmodule
| 7.392539 |
module solve_sin (
input clk,
input rst,
input [3:0] slope,
output [10:0] sin_x,
output [10:0] sin_y
);
reg [10:0] y = 11'd0;
reg [10:0] x = 11'd0;
// everytime button pressed,
// sin ++
// Horizontal
always @(posedge clk or negedge rst) begin
if (!rst) begin
x <= 11'd0;
end else begin
case (slope[1:0])
2'b01: begin
x <= (x[10] == 1'b0 && x >= {1'b0, 10'b1111111111}) ? x : x + 11'b1;
end
2'b10: begin
x <= (x[10] == 1'b1 && x[9:0] <= 10'b1) ? x : x + 11'b11111111111;
end
endcase
end
end
// Vertical
always @(posedge clk or negedge rst) begin
if (!rst) begin
y <= 11'd0;
end else begin
case (slope[3:2])
2'b01: begin
y <= (y[10] == 1'b0 && y >= {1'b0, 10'b1111111111}) ? y : y + 11'b1;
end
2'b10: begin
y <= (y[10] == 1'b1 && y[9:0] <= 10'b1) ? y : y + 11'b11111111111;
end
endcase
end
end
assign sin_y = y;
assign sin_x = x;
endmodule
| 6.716191 |
module soma_altpriority_encoder_3e8 (
data,
q,
zero
);
input [1:0] data;
output [0:0] q;
output zero;
assign q = {data[1]}, zero = (~(data[0] | data[1]));
endmodule
| 7.016879 |
module soma_altpriority_encoder_6e8 (
data,
q,
zero
);
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder13_q;
wire wire_altpriority_encoder13_zero;
wire [0:0] wire_altpriority_encoder14_q;
wire wire_altpriority_encoder14_zero;
soma_altpriority_encoder_3e8 altpriority_encoder13 (
.data(data[1:0]),
.q(wire_altpriority_encoder13_q),
.zero(wire_altpriority_encoder13_zero)
);
soma_altpriority_encoder_3e8 altpriority_encoder14 (
.data(data[3:2]),
.q(wire_altpriority_encoder14_q),
.zero(wire_altpriority_encoder14_zero)
);
assign q = {
(~wire_altpriority_encoder14_zero),
((wire_altpriority_encoder14_zero & wire_altpriority_encoder13_q) | ((~ wire_altpriority_encoder14_zero) & wire_altpriority_encoder14_q))
},
zero = (wire_altpriority_encoder13_zero & wire_altpriority_encoder14_zero);
endmodule
| 7.016879 |
module soma_altpriority_encoder_be8 (
data,
q,
zero
);
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder11_q;
wire wire_altpriority_encoder11_zero;
wire [1:0] wire_altpriority_encoder12_q;
wire wire_altpriority_encoder12_zero;
soma_altpriority_encoder_6e8 altpriority_encoder11 (
.data(data[3:0]),
.q(wire_altpriority_encoder11_q),
.zero(wire_altpriority_encoder11_zero)
);
soma_altpriority_encoder_6e8 altpriority_encoder12 (
.data(data[7:4]),
.q(wire_altpriority_encoder12_q),
.zero(wire_altpriority_encoder12_zero)
);
assign q = {
(~wire_altpriority_encoder12_zero),
(({2{wire_altpriority_encoder12_zero}} & wire_altpriority_encoder11_q) | ({2{(~ wire_altpriority_encoder12_zero)}} & wire_altpriority_encoder12_q))
},
zero = (wire_altpriority_encoder11_zero & wire_altpriority_encoder12_zero);
endmodule
| 7.016879 |
module soma_altpriority_encoder_3v7 (
data,
q
);
input [1:0] data;
output [0:0] q;
assign q = {data[1]};
endmodule
| 7.016879 |
module soma_altpriority_encoder_6v7 (
data,
q
);
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder17_q;
wire [0:0] wire_altpriority_encoder18_q;
wire wire_altpriority_encoder18_zero;
soma_altpriority_encoder_3v7 altpriority_encoder17 (
.data(data[1:0]),
.q(wire_altpriority_encoder17_q)
);
soma_altpriority_encoder_3e8 altpriority_encoder18 (
.data(data[3:2]),
.q(wire_altpriority_encoder18_q),
.zero(wire_altpriority_encoder18_zero)
);
assign q = {
(~wire_altpriority_encoder18_zero),
((wire_altpriority_encoder18_zero & wire_altpriority_encoder17_q) | ((~ wire_altpriority_encoder18_zero) & wire_altpriority_encoder18_q))
};
endmodule
| 7.016879 |
module soma_altpriority_encoder_bv7 (
data,
q
);
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder15_q;
wire [1:0] wire_altpriority_encoder16_q;
wire wire_altpriority_encoder16_zero;
soma_altpriority_encoder_6v7 altpriority_encoder15 (
.data(data[3:0]),
.q(wire_altpriority_encoder15_q)
);
soma_altpriority_encoder_6e8 altpriority_encoder16 (
.data(data[7:4]),
.q(wire_altpriority_encoder16_q),
.zero(wire_altpriority_encoder16_zero)
);
assign q = {
(~wire_altpriority_encoder16_zero),
(({2{wire_altpriority_encoder16_zero}} & wire_altpriority_encoder15_q) | ({2{(~ wire_altpriority_encoder16_zero)}} & wire_altpriority_encoder16_q))
};
endmodule
| 7.016879 |
module soma_altpriority_encoder_r08 (
data,
q
);
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder10_q;
wire wire_altpriority_encoder10_zero;
wire [2:0] wire_altpriority_encoder9_q;
soma_altpriority_encoder_be8 altpriority_encoder10 (
.data(data[15:8]),
.q(wire_altpriority_encoder10_q),
.zero(wire_altpriority_encoder10_zero)
);
soma_altpriority_encoder_bv7 altpriority_encoder9 (
.data(data[7:0]),
.q(wire_altpriority_encoder9_q)
);
assign q = {
(~wire_altpriority_encoder10_zero),
(({3{wire_altpriority_encoder10_zero}} & wire_altpriority_encoder9_q) | ({3{(~ wire_altpriority_encoder10_zero)}} & wire_altpriority_encoder10_q))
};
endmodule
| 7.016879 |
module soma_altpriority_encoder_rf8 (
data,
q,
zero
);
input [15:0] data;
output [3:0] q;
output zero;
wire [2:0] wire_altpriority_encoder19_q;
wire wire_altpriority_encoder19_zero;
wire [2:0] wire_altpriority_encoder20_q;
wire wire_altpriority_encoder20_zero;
soma_altpriority_encoder_be8 altpriority_encoder19 (
.data(data[7:0]),
.q(wire_altpriority_encoder19_q),
.zero(wire_altpriority_encoder19_zero)
);
soma_altpriority_encoder_be8 altpriority_encoder20 (
.data(data[15:8]),
.q(wire_altpriority_encoder20_q),
.zero(wire_altpriority_encoder20_zero)
);
assign q = {
(~wire_altpriority_encoder20_zero),
(({3{wire_altpriority_encoder20_zero}} & wire_altpriority_encoder19_q) | ({3{(~ wire_altpriority_encoder20_zero)}} & wire_altpriority_encoder20_q))
},
zero = (wire_altpriority_encoder19_zero & wire_altpriority_encoder20_zero);
endmodule
| 7.016879 |
module soma_altpriority_encoder_qb6 (
data,
q
);
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder7_q;
wire [3:0] wire_altpriority_encoder8_q;
wire wire_altpriority_encoder8_zero;
soma_altpriority_encoder_r08 altpriority_encoder7 (
.data(data[15:0]),
.q(wire_altpriority_encoder7_q)
);
soma_altpriority_encoder_rf8 altpriority_encoder8 (
.data(data[31:16]),
.q(wire_altpriority_encoder8_q),
.zero(wire_altpriority_encoder8_zero)
);
assign q = {
(~wire_altpriority_encoder8_zero),
(({4{wire_altpriority_encoder8_zero}} & wire_altpriority_encoder7_q) | ({4{(~ wire_altpriority_encoder8_zero)}} & wire_altpriority_encoder8_q))
};
endmodule
| 7.016879 |
module soma_altpriority_encoder_nh8 (
data,
q,
zero
);
input [1:0] data;
output [0:0] q;
output zero;
assign q = {(~data[0])}, zero = (~(data[0] | data[1]));
endmodule
| 7.016879 |
module soma_altpriority_encoder_qh8 (
data,
q,
zero
);
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder27_q;
wire wire_altpriority_encoder27_zero;
wire [0:0] wire_altpriority_encoder28_q;
wire wire_altpriority_encoder28_zero;
soma_altpriority_encoder_nh8 altpriority_encoder27 (
.data(data[1:0]),
.q(wire_altpriority_encoder27_q),
.zero(wire_altpriority_encoder27_zero)
);
soma_altpriority_encoder_nh8 altpriority_encoder28 (
.data(data[3:2]),
.q(wire_altpriority_encoder28_q),
.zero(wire_altpriority_encoder28_zero)
);
assign q = {
wire_altpriority_encoder27_zero,
((wire_altpriority_encoder27_zero & wire_altpriority_encoder28_q) | ((~ wire_altpriority_encoder27_zero) & wire_altpriority_encoder27_q))
},
zero = (wire_altpriority_encoder27_zero & wire_altpriority_encoder28_zero);
endmodule
| 7.016879 |
module soma_altpriority_encoder_vh8 (
data,
q,
zero
);
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder25_q;
wire wire_altpriority_encoder25_zero;
wire [1:0] wire_altpriority_encoder26_q;
wire wire_altpriority_encoder26_zero;
soma_altpriority_encoder_qh8 altpriority_encoder25 (
.data(data[3:0]),
.q(wire_altpriority_encoder25_q),
.zero(wire_altpriority_encoder25_zero)
);
soma_altpriority_encoder_qh8 altpriority_encoder26 (
.data(data[7:4]),
.q(wire_altpriority_encoder26_q),
.zero(wire_altpriority_encoder26_zero)
);
assign q = {
wire_altpriority_encoder25_zero,
(({2{wire_altpriority_encoder25_zero}} & wire_altpriority_encoder26_q) | ({2{(~ wire_altpriority_encoder25_zero)}} & wire_altpriority_encoder25_q))
},
zero = (wire_altpriority_encoder25_zero & wire_altpriority_encoder26_zero);
endmodule
| 7.016879 |
module soma_altpriority_encoder_fj8 (
data,
q,
zero
);
input [15:0] data;
output [3:0] q;
output zero;
wire [2:0] wire_altpriority_encoder23_q;
wire wire_altpriority_encoder23_zero;
wire [2:0] wire_altpriority_encoder24_q;
wire wire_altpriority_encoder24_zero;
soma_altpriority_encoder_vh8 altpriority_encoder23 (
.data(data[7:0]),
.q(wire_altpriority_encoder23_q),
.zero(wire_altpriority_encoder23_zero)
);
soma_altpriority_encoder_vh8 altpriority_encoder24 (
.data(data[15:8]),
.q(wire_altpriority_encoder24_q),
.zero(wire_altpriority_encoder24_zero)
);
assign q = {
wire_altpriority_encoder23_zero,
(({3{wire_altpriority_encoder23_zero}} & wire_altpriority_encoder24_q) | ({3{(~ wire_altpriority_encoder23_zero)}} & wire_altpriority_encoder23_q))
},
zero = (wire_altpriority_encoder23_zero & wire_altpriority_encoder24_zero);
endmodule
| 7.016879 |
module soma_altpriority_encoder_n28 (
data,
q
);
input [1:0] data;
output [0:0] q;
assign q = {(~data[0])};
endmodule
| 7.016879 |
module soma_altpriority_encoder_q28 (
data,
q
);
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder33_q;
wire wire_altpriority_encoder33_zero;
wire [0:0] wire_altpriority_encoder34_q;
soma_altpriority_encoder_nh8 altpriority_encoder33 (
.data(data[1:0]),
.q(wire_altpriority_encoder33_q),
.zero(wire_altpriority_encoder33_zero)
);
soma_altpriority_encoder_n28 altpriority_encoder34 (
.data(data[3:2]),
.q(wire_altpriority_encoder34_q)
);
assign q = {
wire_altpriority_encoder33_zero,
((wire_altpriority_encoder33_zero & wire_altpriority_encoder34_q) | ((~ wire_altpriority_encoder33_zero) & wire_altpriority_encoder33_q))
};
endmodule
| 7.016879 |
module soma_altpriority_encoder_v28 (
data,
q
);
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder31_q;
wire wire_altpriority_encoder31_zero;
wire [1:0] wire_altpriority_encoder32_q;
soma_altpriority_encoder_qh8 altpriority_encoder31 (
.data(data[3:0]),
.q(wire_altpriority_encoder31_q),
.zero(wire_altpriority_encoder31_zero)
);
soma_altpriority_encoder_q28 altpriority_encoder32 (
.data(data[7:4]),
.q(wire_altpriority_encoder32_q)
);
assign q = {
wire_altpriority_encoder31_zero,
(({2{wire_altpriority_encoder31_zero}} & wire_altpriority_encoder32_q) | ({2{(~ wire_altpriority_encoder31_zero)}} & wire_altpriority_encoder31_q))
};
endmodule
| 7.016879 |
module soma_altpriority_encoder_f48 (
data,
q
);
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder29_q;
wire wire_altpriority_encoder29_zero;
wire [2:0] wire_altpriority_encoder30_q;
soma_altpriority_encoder_vh8 altpriority_encoder29 (
.data(data[7:0]),
.q(wire_altpriority_encoder29_q),
.zero(wire_altpriority_encoder29_zero)
);
soma_altpriority_encoder_v28 altpriority_encoder30 (
.data(data[15:8]),
.q(wire_altpriority_encoder30_q)
);
assign q = {
wire_altpriority_encoder29_zero,
(({3{wire_altpriority_encoder29_zero}} & wire_altpriority_encoder30_q) | ({3{(~ wire_altpriority_encoder29_zero)}} & wire_altpriority_encoder29_q))
};
endmodule
| 7.016879 |
module soma_altpriority_encoder_e48 (
data,
q
);
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder21_q;
wire wire_altpriority_encoder21_zero;
wire [3:0] wire_altpriority_encoder22_q;
soma_altpriority_encoder_fj8 altpriority_encoder21 (
.data(data[15:0]),
.q(wire_altpriority_encoder21_q),
.zero(wire_altpriority_encoder21_zero)
);
soma_altpriority_encoder_f48 altpriority_encoder22 (
.data(data[31:16]),
.q(wire_altpriority_encoder22_q)
);
assign q = {
wire_altpriority_encoder21_zero,
(({4{wire_altpriority_encoder21_zero}} & wire_altpriority_encoder22_q) | ({4{(~ wire_altpriority_encoder21_zero)}} & wire_altpriority_encoder21_q))
};
endmodule
| 7.016879 |
module soma (
clk_en,
clock,
dataa,
datab,
result
);
input clk_en;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
soma_altfp_add_sub_3ij soma_altfp_add_sub_3ij_component (
.clk_en(clk_en),
.clock (clock),
.dataa (dataa),
.datab (datab),
.result(sub_wire0)
);
endmodule
| 6.646636 |
module somacompleta4bits (
s,
x,
y
);
output [4:0] s;
input [3:0] x, y;
wire c1, c2, c3;
meiasoma HA1 (
s[0],
c1,
x[0],
y[0]
);
somacompleta FA1 (
s[1],
c2,
x[1],
y[1],
c1
);
somacompleta FA2 (
s[2],
c3,
x[2],
y[2],
c2
);
somacompleta FA3 (
s[3],
s[4],
x[3],
y[3],
c3
);
endmodule
| 7.404034 |
module meiasoma (
s0,
s1,
x,
y
);
output s0, s1;
input x, y;
xor XOR1 (s0, x, y);
and AND1 (s1, x, y);
endmodule
| 7.813544 |
module somacompleta (
s0,
s1,
x,
y,
v1
);
output s0, s1;
input x, y, v1;
wire s4, s5, s2;
meiasoma HA1 (
s2,
s4,
x,
y
);
meiasoma HA2 (
s0,
s5,
s2,
v1
);
or OR1 (s1, s5, s4);
endmodule
| 7.045629 |
module test4bits;
reg [3:0] x, y;
wire [4:0] s;
integer a, b;
somacompleta4bits SOM1 (
s,
x,
y
);
initial begin //definindo valores iniciais
x = 0;
y = 0;
end
initial begin //inicio
$display("Guia 05 - Karen Alves Pereira - 407451");
$display("Soma completa de dois valores com 4 bits");
$display("\n A + B = S \n");
$monitor(" %b%b%b%b + %b%b%b%b = %b%b%b%b%b", x[3], x[2], x[1], x[0], y[3], y[2], y[1], y[0],
s[4], s[3], s[2], s[1], s[0]);
for (a = 0; a <= 15; a = a + 1) begin
for (b = 0; b <= 15; b = b + 1) begin
#1 x = a;
y = b;
end
end
end
endmodule
| 6.751233 |
module saida1 (
s1,
x,
y
);
input x, y;
output s1;
wire s1;
and AND1 (s1, x, y);
endmodule
| 6.784364 |
module meiaSoma1 (
s0,
s1,
x,
y
);
input x, y;
output s0, s1;
wire s0, s1;
saida0 S0 (
s0,
x,
y
);
saida1 S1 (
s1,
x,
y
);
endmodule
| 6.754192 |
module somaCompleta (
s3,
s5,
x,
y,
z
);
input x, y, z;
output s1, s0, s3, s4, s5;
wire s1, s0;
meiaSoma1 MEIASOMA1 (
s0,
s1,
x,
y
);
meiaSoma1 MEIASOMA2 (
s3,
s4,
s0,
z
);
or OR1 (s5, s1, s4);
endmodule
| 7.146397 |
module somador3_bits (
s0,
s1,
s2,
s3,
a0,
a1,
a2,
b0,
b1,
b2
);
input a0, a1, a2, b0, b1, b2;
output s0, s1, s2, s3;
wire saida0, saida1;
somaCompleta SOMACOMPLETA1 (
s0,
saida0,
a0,
b0,
0
);
somaCompleta SOMACOMPLETA2 (
s1,
saida1,
saida0,
a1,
b1
);
somaCompleta SOMACOMPLETA3 (
s2,
s3,
saida1,
a2,
b2
);
endmodule
| 6.663999 |
module somador1 (
input [7:0] A,
B,
output [7:0] C
);
assign C = A + B;
endmodule
| 7.583878 |
module somador2 (
proximo_endereco,
imediato_extendido,
saida,
clock
);
// input
input [31:0] proximo_endereco;
input [31:0] imediato_extendido;
input clock;
// output
output [31:0] saida;
assign saida = proximo_endereco + imediato_extendido;
endmodule
| 7.22221 |
module somacompleto (
s0,
s1,
a,
b,
c,
v
);
output s0, s1;
input a, b, c, v;
wire temp0, temp1, temp2, temp3, temp4, temp5, temp6, temp7, temp8, temp9, temp10, temp11, temp12, temp13;
or Or1 (s0, temp0, temp1);
or Or2 (s1, temp2, temp3, temp4, temp5);
xor Xor1 (temp0, a, b);
and And1 (temp1, temp6, temp7);
xor Xor2 (temp6, v, c);
and And2 (temp7, a, b);
and And3 (temp2, temp6, b);
and And4 (temp3, temp8, a, temp6);
not Not1 (temp8, b);
and And5 (temp4, temp0, temp9);
and And6 (temp5, c, temp10);
and And7 (temp11, c, v);
or Or3 (temp12, v, temp13);
and And8 (temp13, b, a, v);
//end module
endmodule
| 7.253117 |
module saida1 (
s1,
a,
b
);
input a, b;
output s1;
wire s1;
and AND1 (s1, a, b);
endmodule
| 6.784364 |
module meiaSoma1 (
s0,
s1,
a,
b
);
input a, b;
output s0, s1;
wire s0, s1;
saida0 S0 (
s0,
a,
b
);
saida1 S1 (
s1,
a,
b
);
endmodule
| 6.754192 |
module somaCompleta (
s3,
s5,
a,
b,
c
);
input a, b, c;
output s1, s0, s3, s4, s5;
wire s1, s0;
meiaSoma1 MEIASOMA1 (
s0,
s1,
a,
b
);
meiaSoma1 MEIASOMA2 (
s3,
s4,
s0,
c
);
or OR1 (s5, s1, s4);
endmodule
| 7.146397 |
module somador_3bits (
s0,
s1,
s2,
s3,
a0,
a1,
a2,
b0,
b1,
b2
);
input a0, a1, a2, b0, b1, b2;
output s0, s1, s2, s3;
wire sSOMAC0, sSOMAC1;
somaCompleta SOMAC1 (
s0,
sSOMAC0,
a0,
b0,
0
);
somaCompleta SOMAC2 (
s1,
sSOMAC1,
a1,
b1,
sSOMAC0
);
somaCompleta SOMAC3 (
s2,
s3,
a2,
b2,
sSOMAC1
);
endmodule
| 6.752206 |
module somador_bcd (
a,
b,
carry_in,
soma,
carry_out
);
input [3:0] a, b;
input carry_in;
output [3:0] soma;
output carry_out;
reg [4:0] soma_aux;
reg [3:0] soma;
reg carry_out;
always @(a, b, carry_in) begin
soma_aux = a + b + carry_in; //adiciona todos os inputs
if (soma_aux > 9) begin
soma_aux = soma_aux + 6; //adiciona 6 se o resultado for maior que 9
carry_out = 1;
soma = soma_aux[3:0];
end else begin
carry_out = 0;
soma = soma_aux[3:0];
end
end
endmodule
| 7.119594 |
module saida1 (
s1,
x,
y
);
input x, y;
output s1;
wire s1;
and AND1 (s1, x, y);
endmodule
| 6.784364 |
module meiaSoma1 (
s0,
s1,
x,
y
);
input x, y;
output s0, s1;
wire s0, s1;
saida0 S0 (
s0,
x,
y
);
saida1 S1 (
s1,
x,
y
);
endmodule
| 6.754192 |
module somaCompleta (
s3,
s5,
x,
y,
z
);
input x, y, z;
output s1, s0, s3, s4, s5;
wire s1, s0;
meiaSoma1 MEIASOMA1 (
s0,
s1,
x,
y
);
meiaSoma1 MEIASOMA2 (
s3,
s4,
s0,
z
);
or OR1 (s5, s1, s4);
endmodule
| 7.146397 |
module somador3_bits (
s0,
s1,
s2,
s3,
a0,
a1,
a2,
b0,
b1,
b2
);
input a0, a1, a2, b0, b1, b2;
output s0, s1, s2, s3;
wire saida0, saida1;
somaCompleta SOMACOMPLETA1 (
s0,
saida0,
a0,
b0,
0
);
somaCompleta SOMACOMPLETA2 (
s1,
saida1,
saida0,
a1,
b1
);
somaCompleta SOMACOMPLETA3 (
s2,
s3,
saida1,
a2,
b2
);
endmodule
| 6.663999 |
module soma_endereco_proc (
id_proc,
ender_in,
ender,
M,
tam_particao
);
input [1:0] id_proc;
input [8:0] ender_in;
output reg [8:0] ender;
input [6:0] M;
input [6:0] tam_particao;
// Soma deslocamento aos endereços
// para cada tipo de processo
always @(*) begin
if (id_proc == 2'b00) ender = ender_in;
else if (id_proc == 2'b01) ender = ender_in + M;
else ender = ender_in + M + tam_particao;
end
endmodule
| 7.014518 |
module someTwoPortVendorMem_128_8_0 (
QA,
CLKA,
CENA,
WENA,
AA,
DA,
OENA,
QB,
CLKB,
CENB,
WENB,
AB,
DB,
OENB
);
output [7:0] QA;
input CLKA;
input CENA;
input WENA;
input [6:0] AA;
input [7:0] DA;
input OENA;
output [7:0] QB;
input CLKB;
input CENB;
input WENB;
input [6:0] AB;
input [7:0] DB;
input OENB;
reg [7:0] mem[127:0];
reg [7:0] QA, QB;
initial begin
$display("%m : someTwoPortVendorMem_128_8_0 instantiated.");
end
always @(posedge CLKA) begin
if ((CENA == 0) && (WENA == 0)) begin
mem[AA] <= DA;
end else if ((CENA == 0) && (WENA == 1)) begin
QA <= mem[AA];
end
end
always @(posedge CLKB) begin
if ((CENB == 0) && (WENB == 0)) begin
mem[AB] <= DB;
end else if ((CENB == 0) && (WENB == 1)) begin
QB <= mem[AB];
end
end
endmodule
| 6.911291 |
module someTwoPortVendorMem_4096_32_0 (
QA,
CLKA,
CENA,
WENA,
AA,
DA,
OENA,
QB,
CLKB,
CENB,
WENB,
AB,
DB,
OENB
);
output [31:0] QA;
input CLKA;
input CENA;
input WENA;
input [11:0] AA;
input [31:0] DA;
input OENA;
output [31:0] QB;
input CLKB;
input CENB;
input WENB;
input [11:0] AB;
input [31:0] DB;
input OENB;
reg [31:0] mem[4096:0];
reg [31:0] QA, QB;
initial begin
$display("%m : someTwoPortVendorMem_4096_32_0 instantiated.");
end
always @(posedge CLKA) begin
if ((CENA == 0) && (WENA == 0)) begin
mem[AA] <= DA;
end else if ((CENA == 0) && (WENA == 1)) begin
QA <= mem[AA];
end
end
always @(posedge CLKB) begin
if ((CENB == 0) && (WENB == 0)) begin
mem[AB] <= DB;
end else if ((CENB == 0) && (WENB == 1)) begin
QB <= mem[AB];
end
end
endmodule
| 6.911291 |
module someTwoPortVendorMem_4096_32_8 (
QA,
CLKA,
CENA,
WENA,
AA,
DA,
OENA,
QB,
CLKB,
CENB,
WENB,
AB,
DB,
OENB
);
output [31:0] QA;
input CLKA;
input CENA;
input WENA;
input [11:0] AA;
input [31:0] DA;
input OENA;
output [31:0] QB;
input CLKB;
input CENB;
input WENB;
input [11:0] AB;
input [31:0] DB;
input OENB;
reg [31:0] mem[4096:0];
reg [31:0] QA, QB;
initial begin
$display("%m : someTwoPortVendorMem_4096_32_8 instantiated.");
end
always @(posedge CLKA) begin
if ((CENA == 0) && (WENA == 0)) begin
mem[AA] <= DA;
end else if ((CENA == 0) && (WENA == 1)) begin
QA <= mem[AA];
end
end
always @(posedge CLKB) begin
if ((CENB == 0) && (WENB == 0)) begin
mem[AB] <= DB;
end else if ((CENB == 0) && (WENB == 1)) begin
QB <= mem[AB];
end
end
endmodule
| 6.911291 |
module pipe_pal
#(parameter W_DATA=32, localparam W_ADDR = 16)
(input a, b,
input [W_DATA-1:0] c, d); /* multi-line
comment */ (* param *) parameter XX = 3;
(* local_param *) localparam [W_DATA-1:0] XY = 4;
input a, b;
input [W_DATA-1:0] c, d;
assign a_wire = (3+4)*2 + 4 - 1;
assign b_wire = a_wire[3] << 2; //expression
assign c_wire = -a[3:0]**2;
assign d_wire = a_wire < b_wire[1][3:0];
assign e_wire = a_wire !== b_wire;
assign f_wire = a || b ? (b ? 1 : 0) : (c ? 0 : 1);
assign g_wire = 8'sb110Z_011x;
assign h_wire = 'h1234_abcd_ef69;
assign i_wire = 3.14 + .5;
assign j_wire = 3.14e10;
assign k_wire = "hello, world!" + "" + "\"";
assign l_wire = {a_wire[2], d_wire[1:0]};
assign m_wire = {3{a_wire[1:0]}};
assign {a, b} = 3;
assign n_wire = afunc(3 +4, a);
reg avar;
reg bvar, cvar[2:0];
integer k;
wire aa;
wire [4:0] awire;
reg [3:0] areg;
always @*
begin
c = a + b;
empty_task;
end
always @(posedge i_clk, negedge resetn)
q_c <= q_c + 1;
function [W_DATA-1:0] afunc(input [W_DATA-1:0] a, b);
reg bff[1:0];
reg arf, dd;
integer k;
bff = a * 3;
endfunction
(* func_decl *)
function bfunc(input [W_DATA-1:0] a, b);
begin
bff = a * 3;
if(c)
afunc = a+b;
else if(a)
afunc = 3;
end
endfunction
task empty_task;
endtask
initial
begin: init
s = 3 + 4;
fork: name
a = 1;
empty_task;
join
disable name;
assign q = 1;
#4 deassign q;
wait(a)
empty_task;;
end
initial
empty_task;
initial
forever #1
clk = ~clk;
initial
begin: loop_blocks
integer i;
repeat (a+1)
empty_task();
while(i<3)
i = i+1;
for(i=0;i<3;i=i+1)
empty_task;
end
always @(*)
begin
case(a)
1:
a = 1;
3:
begin
if(k)
c = 3;
else if(sa)
c = 1;
else begin
c = 2;
end
a = 2;
end
default:
a = 0;
endcase
end
some_submodule u_instance[1:0](a, .b(b), .c(c[3:0]));
initial
-> ev;
genvar i;
generate
begin: gen_blk
some_submodule u_inst(a, .b(b));
if(i)
assign a = b;
else
some_submodule u_inst2(a, .b(b));
end
endgenerate
(* generate_loop *)
generate for(i=0;i<4;i=i+1)
begin: gen_loop
assign a[i] = b;
some_submodule u_inst_gen(a, .b(b));
end
endgenerate
(* attr *)
defparam W_DATA = 16;
task gen_task(input a, output [W_DATA-1:0] b);
(* assign_in_task *) b = a;
endtask
endmodule
| 7.941253 |
module sonar (
input clk,
rst_n, // clk 10MHz
input do_measure,
input sonar_pulse,
output reg [7:0] inches,
output reg sonar_trigger = 0,
output reg READY = 0
);
parameter s_standby = 0, s_startMeasure = 1, s_waitForPulse = 2, s_countPulse = 3;
reg [1:0] state = s_standby, next_state = s_standby;
reg [31:0] timeCount = 0;
reg rst_count = 1;
reg [31:0] timeoutCounter = 0;
always @(negedge rst_n or posedge clk) begin
if (~rst_n) // priority reset
state <= s_standby;
else state <= next_state;
end
always @(state or do_measure or sonar_pulse or timeoutCounter) begin
case (state)
s_standby: begin
sonar_trigger <= 0; // Disable the sonar sensor
READY <= 1; //Signal that we are ready to scan/ not busy
rst_count <= 1;
if (do_measure) next_state <= s_startMeasure;
else next_state <= s_standby;
end
s_startMeasure: begin
sonar_trigger <= 1; // Tell sonar to start ranging
READY <= 0;
if (sonar_pulse) next_state <= s_countPulse;
else next_state <= s_startMeasure;
end
s_countPulse: begin
rst_count = 0;
sonar_trigger <= 0;
if (~sonar_pulse) begin // Pulse from sonar has ended
// calculate the inches from the time
// 147uS / inch
inches <= ((timeCount - 8300) / 1470);
next_state <= s_standby;
end else next_state <= s_countPulse;
end
default: // should never reach this.
next_state <= s_standby;
endcase
end
always @(posedge clk)
if (rst_count) timeCount <= 0;
else timeCount <= timeCount + 1;
always @(posedge clk)
if (state == s_waitForPulse || state == s_countPulse) timeoutCounter <= timeoutCounter + 1;
else timeoutCounter <= 0;
endmodule
| 7.94105 |
module song #(
parameter LENGTH = 170,
parameter WIDTH = 12,
parameter ADDR = $clog2(LENGTH)
) (
input clk,
input [ADDR-1:0] addr,
output [WIDTH-1:0] command
);
reg [WIDTH-1:0] song[LENGTH-1:0];
initial begin
$readmemh("song.txt", song, 0, LENGTH - 1);
end
assign command = song[addr];
endmodule
| 7.448919 |
module song3 (
clk,
ifplay,
SongData
);
input ifplay;
input clk;
output [4:0] SongData;
reg [7:0] state;
initial state = 0;
reg [4:0] YinFu;
assign SongData = YinFu;
always @(posedge clk) begin
state = state + 1'b1;
if (!ifplay) begin
state = 0;
end
if (state > 196) begin
state = 1;
end //ʱʵѭ
case (state)
1, 2, 3, 4, 5, 6: YinFu = 21;
7, 8: YinFu = 12;
9, 10, 11: YinFu = 11;
12: YinFu = 9;
13, 14: YinFu = 9;
15, 16: YinFu = 7;
17, 18, 19: YinFu = 8;
20: YinFu = 7;
21, 22: YinFu = 8;
23, 24: YinFu = 12;
25, 26, 27: YinFu = 11;
28: YinFu = 9;
29, 30: YinFu = 9;
31, 32: YinFu = 11;
33, 34, 35, 36, 37, 38: YinFu = 12;
39, 40: YinFu = 14;
41, 42, 43: YinFu = 11;
44: YinFu = 9;
45, 46: YinFu = 9;
47, 48: YinFu = 7;
49, 50, 51: YinFu = 8;
52: YinFu = 7;
53, 54: YinFu = 8;
55, 56: YinFu = 9;
57, 58, 59: YinFu = 7;
60: YinFu = 5;
61, 62: YinFu = 5;
63, 64: YinFu = 4;
65, 66, 67: YinFu = 7;
68, 69: YinFu = 4;
70, 71, 72, 73, 74, 75: YinFu = 6;
76, 77: YinFu = 9;
78, 79, 80: YinFu = 8;
81: YinFu = 7;
82, 83: YinFu = 8;
84, 85: YinFu = 9;
86, 87, 88: YinFu = 7;
89: YinFu = 7;
90, 91: YinFu = 9;
92, 93: YinFu = 11;
94, 95, 96, 97, 98, 99: YinFu = 12;
100: YinFu = 21;
101, 102: YinFu = 12;
103, 104, 105: YinFu = 11;
106, 107, 108: YinFu = 9;
109, 110: YinFu = 7;
111, 112, 113: YinFu = 8;
114: YinFu = 7;
115, 116: YinFu = 8;
117, 118: YinFu = 9;
119, 120, 121: YinFu = 7;
122, 123, 124: YinFu = 5;
125, 126: YinFu = 4;
127, 128, 129, 130, 131, 132: YinFu = 7;
133, 134: YinFu = 12;
135, 136, 137: YinFu = 11;
138, 139, 140: YinFu = 9;
141, 142: YinFu = 7;
143, 144, 145: YinFu = 8;
146: YinFu = 7;
147, 148: YinFu = 8;
149, 150: YinFu = 12;
151, 152, 153: YinFu = 11;
154, 155, 156: YinFu = 9;
157, 158: YinFu = 11;
159, 160, 161, 162, 163, 164: YinFu = 12;
165, 166: YinFu = 14;
167, 168, 169: YinFu = 11;
170, 171, 172: YinFu = 9;
173, 174: YinFu = 7;
175, 176, 177: YinFu = 8;
178: YinFu = 7;
179, 180: YinFu = 8;
181, 182: YinFu = 9;
183, 184, 185: YinFu = 7;
186, 187, 188: YinFu = 5;
189, 190: YinFu = 4;
191, 192, 193, 194, 195, 196: YinFu = 7;
default: YinFu = 5'b10101;
endcase
end
endmodule
| 6.512848 |
module SongDriver (
input iFpgaClock,
iFpgaReset, //注意这个reset是高有效，我写的, 需要一个手动复位按钮 //输入时钟100MHz，管脚绑定P17
input [5:0] track0,
input [5:0] track1,
input [5:0] track2,
input [5:0] track3,
output speaker //输出至扬声器的信号，本例中为方波.
);
wire clk_6mhz; //用于产生各种音阶频率的基准频率
ClockDivider #(8) u1 (
iFpgaClock,
iFpgaReset,
clk_6mhz //6.25MHz时钟信号
);
wire clk_16hz; //用于控制音长（节拍）的时钟频率
ClockDecelerator #(64) u2 (
iFpgaClock,
iFpgaReset,
clk_16hz //得到16Hz时钟信号
);
//先用4做个测试
//
wire [5:0] current_track;
assign current_track = track0;
one_track_player otp (
clk_6mhz,
clk_16hz,
iFpgaReset,
current_track,
speaker
);
// four_track_player ftp(clk_6mhz,clk_16hz,iFpgaReset,track0,track1,track2,track3,speaker);
endmodule
| 7.184663 |
module SongHz (
input clk,
input rst_n,
output reg clk_5m
);
//clk = 50MHz, div into 5MHz
//1 pause/ 10 clocks
reg [4:0] cnt = 5'h0;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) //ػʱ
cnt <= 5'h0;
else if (cnt == 5'h9) //ʱÿ5M
cnt <= 5'h0;
else cnt <= cnt + 5'h1;
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) clk_5m <= 1'b0;
else if (cnt == 5'h9) clk_5m <= 1'b1;
else clk_5m <= 1'b0;
end
endmodule
| 6.780601 |
module songle_digit_counter (
clk,
rst,
increase,
decrease,
upper_bound,
lower_bound,
up_initial_value,
down_initial_value,
rst_value,
carry,
borrow,
value
);
input clk, rst, increase, decrease;
input [3:0] upper_bound;
input [3:0] lower_bound;
input [3:0] up_initial_value;
input [3:0] down_initial_value;
input [3:0] rst_value;
output carry, borrow;
output [3:0] value;
reg [3:0] value_temp;
reg [3:0] value;
reg carry, borrow;
always @* begin
if (increase == 1'b1) begin
if ((value == upper_bound) && increase) begin
value_temp = up_initial_value;
carry = `enabled;
borrow = `disabled;
end else if ((value != upper_bound) && increase) begin
value_temp = value + 1'b1;
carry = `disabled;
borrow = `disabled;
end else begin
value_temp = value;
carry = `disabled;
borrow = `disabled;
end
end else begin
if (value == lower_bound && decrease) begin
value_temp = down_initial_value;
borrow = `enabled;
carry = `disabled;
end else if (value != lower_bound && decrease) begin
value_temp = value - 1'b1;
borrow = `disabled;
carry = `disabled;
end else begin
value_temp = value;
borrow = `disabled;
carry = `disabled;
end
end
end
always @(posedge clk or negedge rst) begin
if (~rst) value <= rst_value;
else value <= value_temp;
end
endmodule
| 6.779216 |
module songMemory (
clk,
Addr,
DataOut
);
parameter song_len = 12;
parameter encoding_len = 12;
input clk;
input [5:0] Addr;
output [encoding_len-1:0] DataOut;
reg [encoding_len-1:0] mem[song_len-1:0];
initial begin
$readmemb("increasing.dat", mem);
end
assign DataOut = mem[Addr];
endmodule
| 6.732836 |
module testSongMemory;
reg clk;
initial clk = 0;
always #10 clk = ~clk;
reg [5:0] Addr;
initial Addr = 6'b0;
wire [11:0] notes;
songMemory sMem (
clk,
Addr,
notes
);
always #100 Addr = Addr + 1;
endmodule
| 6.759468 |
module songplayer (
audio,
sys_CLK,
button,
song_id
);
output audio;
input sys_CLK;
input button;
input [1:0] song_id;
reg [23:0] counter4Hz, counter6MHz;
reg [13:0] count, origin;
reg audiof;
reg clk_6MHz, clk_4Hz;
reg [4:0] j;
reg [7:0] len;
assign audio = button ? audiof : 1'b0; //ƿ
always @(posedge sys_CLK) //6MHzƵ
begin
if (counter6MHz == 4) begin
counter6MHz = 0;
clk_6MHz = ~clk_6MHz;
end else begin
counter6MHz = counter6MHz + 1;
end
end
always @(posedge sys_CLK) //4HzƵ
begin
if (counter4Hz == 6250000) begin
counter4Hz = 0;
clk_4Hz = ~clk_4Hz;
end else begin
counter4Hz = counter4Hz + 1;
end
end
always @(posedge clk_6MHz) begin
if (count == 16383) begin
count = origin;
audiof = ~audiof;
end else count = count + 1;
end
always @(posedge clk_4Hz) begin
case (j)
'd1: origin = 'd4916; //low
'd2: origin = 'd6168;
'd3: origin = 'd7281;
'd4: origin = 'd7791;
'd5: origin = 'd8730;
'd6: origin = 'd9565;
'd7: origin = 'd10310;
'd8: origin = 'd010647; //middle
'd9: origin = 'd011272;
'd10: origin = 'd011831;
'd11: origin = 'd012087;
'd12: origin = 'd012556;
'd13: origin = 'd012974;
'd14: origin = 'd013346;
'd15: origin = 'd13516; //high
'd16: origin = 'd13829;
'd17: origin = 'd14108;
'd18: origin = 'd11535;
'd19: origin = 'd14470;
'd20: origin = 'd14678;
'd21: origin = 'd14864;
default: origin = 'd016383; // try to modify
endcase
end
always @(posedge clk_4Hz) //
begin
if (song_id == 0) begin
if (len == 63) len = 0;
else len = len + 1;
case (len)
0: j = 19;
1: j = 18;
2: j = 13;
3: j = 13;
4: j = 14;
5: j = 14;
6: j = 18;
7: j = 17;
8: j = 11;
9: j = 11;
10: j = 12;
11: j = 12;
12: j = 16;
13: j = 15;
14: j = 10;
15: j = 10;
16: j = 12;
17: j = 12;
18: j = 15;
19: j = 15;
20: j = 19;
21: j = 18;
22: j = 13;
23: j = 13;
24: j = 14;
25: j = 14;
26: j = 18;
27: j = 17;
28: j = 11;
29: j = 11;
30: j = 12;
31: j = 12;
32: j = 16;
33: j = 15;
34: j = 10;
35: j = 10;
36: j = 12;
37: j = 12;
38: j = 15;
39: j = 15;
40: j = 19;
41: j = 18;
42: j = 13;
43: j = 13;
44: j = 14;
45: j = 14;
46: j = 18;
47: j = 17;
48: j = 11;
49: j = 11;
50: j = 12;
51: j = 12;
52: j = 16;
53: j = 15;
54: j = 10;
55: j = 10;
56: j = 12;
57: j = 12;
58: j = 15;
59: j = 15;
60: j = 0;
61: j = 0;
62: j = 0;
63: j = 0;
default: j = 1;
endcase
end else if (song_id == 1) begin
if (len == 63) len = 0;
else len = len + 1;
case (len)
0: j = 8;
1: j = 8;
2: j = 9;
3: j = 9;
4: j = 10;
5: j = 10;
6: j = 8;
7: j = 8;
8: j = 8;
9: j = 8;
10: j = 9;
11: j = 9;
12: j = 10;
13: j = 10;
14: j = 8;
15: j = 8;
16: j = 10;
17: j = 10;
18: j = 11;
19: j = 11;
20: j = 12;
21: j = 12;
22: j = 12;
23: j = 12;
24: j = 10;
25: j = 10;
26: j = 11;
27: j = 11;
28: j = 12;
29: j = 12;
30: j = 12;
31: j = 12;
32: j = 12;
33: j = 13;
34: j = 12;
35: j = 11;
36: j = 10;
37: j = 10;
38: j = 8;
39: j = 8;
40: j = 12;
41: j = 13;
42: j = 12;
43: j = 11;
44: j = 10;
45: j = 10;
46: j = 8;
47: j = 8;
48: j = 8;
49: j = 8;
50: j = 12;
51: j = 12;
52: j = 8;
53: j = 8;
54: j = 8;
55: j = 8;
56: j = 8;
57: j = 8;
58: j = 12;
59: j = 12;
60: j = 8;
61: j = 8;
62: j = 8;
63: j = 8;
default: j = 1;
endcase
end else if (song_id == 2) begin // updated at 12/26 00:51
if (len == 63) len = 0;
else len = len + 1;
case (len)
0: j = 3;
1: j = 3;
2: j = 1;
3: j = 1;
4: j = 8;
5: j = 8;
6: j = 1;
7: j = 1;
8: j = 5;
9: j = 5;
10: j = 11;
11: j = 11;
12: j = 5;
13: j = 5;
14: j = 1;
15: j = 1;
16: j = 11;
17: j = 11;
18: j = 8;
19: j = 8;
20: j = 1;
21: j = 1;
22: j = 8;
23: j = 8;
24: j = 0;
25: j = 0;
26: j = 3;
27: j = 3;
28: j = 1;
29: j = 1;
30: j = 8;
31: j = 8;
32: j = 1;
33: j = 1;
34: j = 5;
35: j = 5;
36: j = 11;
37: j = 11;
38: j = 5;
39: j = 5;
40: j = 1;
41: j = 1;
42: j = 11;
43: j = 11;
44: j = 8;
45: j = 8;
46: j = 1;
47: j = 1;
48: j = 8;
49: j = 8;
50: j = 0;
51: j = 0;
52: j = 0;
53: j = 0;
54: j = 0;
55: j = 0;
56: j = 0;
57: j = 0;
58: j = 0;
59: j = 0;
60: j = 0;
61: j = 0;
62: j = 0;
63: j = 0;
endcase
end
end
endmodule
| 6.812998 |
module song_amazing_grace (
input clock,
output [7:0] key_code
);
reg [15:0] tmp;
wire [15:0] tmpa;
reg tr;
reg [15:0] step;
wire [15:0] step_r;
reg [15:0] TT;
reg [5:0] st;
reg restart;
reg go_end;
////////Music-processing////////
always @(negedge restart or posedge clock) begin
if (!restart) begin
step = 0;
st = 0;
tr = 0;
restart <= 1'b1;
end else if (step < step_r) begin
case (st)
0: st = st + 1;
1: begin
tr = 0;
st = st + 1;
end
2: begin
tr = 1;
st = st + 1;
end
3: if (go_end) st = st + 1;
4: begin
st = 0;
step = step + 1;
end
endcase
end else restart <= 1'b0;
end
/////////////// pitch //////////////////
wire [7:0] key_code1 = ((TT[3:0] == 1) ? 8'h2b : ( //1
(TT[3:0] == 2) ? 8'h34 : ( //2
(TT[3:0] == 3) ? 8'h33 : ( //3
(TT[3:0] == 4) ? 8'h3b : ( //4
(TT[3:0] == 5) ? 8'h42 : ( //5
(TT[3:0] == 6) ? 8'h4b : ( //6
(TT[3:0] == 7) ? 8'h4c : ( //7
(TT[3:0] == 10) ? 8'h52 : ( //1
(TT[3:0] == 12) ? 8'h1c : ( //-5
(TT[3:0] == 13) ? 8'h1b : ( //-6
(TT[3:0] == 15) ? 8'hf0 : 8'hf0)))))))))));
/////////////// paddle ///////////////////
assign tmpa[15:0]=(
(TT[7:4]==15)?16'h10:(
(TT[7:4]==8)? 16'h20:(
(TT[7:4]==9)? 16'h30:(
(TT[7:4]==1)? 16'h40:(
(TT[7:4]==3)? 16'h60:(
(TT[7:4]==2)? 16'h80:(
(TT[7:4]==4)? 16'h100:0
))))))
);
/////////// note list ///////////
always @(step) begin
case (step)
0: TT = 8'h1f;
1: TT = 8'b00011100;
2: TT = 8'b00100001;
3: TT = 8'b10000011;
4: TT = 8'b10000001;
5: TT = 8'b00100011;
6: TT = 8'b00010010;
7: TT = 8'b00100001;
8: TT = 8'b00011101;
9: TT = 8'b00011100;
10: TT = 8'b00011100;
11: TT = 8'b00100001;
12: TT = 8'b10000011;
13: TT = 8'b10000001;
14: TT = 8'b00100011;
15: TT = 8'b00010010;
16: TT = 8'b01000101;
17: TT = 8'b00010011;
18: TT = 8'b00110101;
19: TT = 8'b10000011;
20: TT = 8'b10000101;
21: TT = 8'b10000011;
22: TT = 8'b00100001;
23: TT = 8'b00011100;
24: TT = 8'b00111101;
25: TT = 8'b10000001;
26: TT = 8'b10000001;
27: TT = 8'b10001101;
28: TT = 8'b00101100;
29: TT = 8'b00011100;
30: TT = 8'b00100001;
31: TT = 8'b10000011;
32: TT = 8'b10000001;
33: TT = 8'b00100011;
34: TT = 8'b00010010;
35: TT = 8'b01000001;
36: TT = 8'h1f;
endcase
end
assign step_r = 36; ///Total note
/////////////KEY release & code-out ////////////////
always @(negedge tr or posedge clock) begin
if (!tr) begin
tmp = 0;
go_end = 0;
end else if (tmp > tmpa) go_end = 1;
else tmp = tmp + 1;
end
assign key_code = (tmp < (tmpa - 1)) ? key_code1 : 8'hf0;
endmodule
| 7.324128 |
module -----------------
//------------- author : Dino --------------------------
module song_control(
input CLK,
input pre,
input nxt,
output reg [2:0] current
);
parameter DELAY_TIME = 10000000;
integer delay = 0;
always @ (negedge CLK) begin
if(delay == DELAY_TIME) begin
if(pre) begin
current <= (current==0) ? 0: current-1;
delay <= 0;
end
else if(nxt) begin
current <= (current==3) ? 3: current+1;
delay <= 0;
end
end
else delay <= delay + 1;
end
endmodule
| 7.025213 |
modulename>song_data_loader_t</modulename>
/// <filedescription>ʼ</filedescription>
/// <version>
/// 0.0.1 (UnnamedOrange) : First commit.
/// </version>
`timescale 1ns / 1ps
module song_data_loader_t #
(
parameter [7:0] static_init_aux_info = 8'b00000100,
parameter restarting_timeout = 10000000
)
(
// CPU
output [7:0] song_init_index,
output [7:0] song_init_aux_info,
output song_restart,
// ⲿϢ
input [7:0] song_selection,
// ơ
input sig_on,
output sig_done,
// λʱӡ
input RESET_L,
input CLK
);
// ״̬塣
localparam state_width = 2;
localparam [state_width - 1 : 0]
s_init = 0, // ȴʹܡ
s_restarting = 1, // ȴ CPU ʼ
s_done = 2, // ɡ
s_unused = 0;
reg [state_width - 1 : 0] state, n_state;
// ʱ
reg [31:0] timer;
always @(posedge CLK) begin
if (!RESET_L) begin
timer <= 0;
end
else begin
if (timer == restarting_timeout - 1)
timer <= 0;
else
timer <= timer + 1;
end
end
// ̡
always @(posedge CLK) begin
if (!RESET_L) begin
state <= s_init;
end
else begin
state <= n_state;
end
end
// ̡
always @(*) begin
case (state)
s_init:
n_state = sig_on ? s_restarting : s_init;
s_restarting:
n_state = timer == restarting_timeout - 1 ? s_done : s_restarting;
s_done:
n_state = s_init;
default:
n_state = s_init;
endcase
end
// ̡
assign song_init_index = song_selection;
assign song_init_aux_info = static_init_aux_info;
assign song_restart = state == s_restarting;
assign sig_done = state == s_done;
endmodule
| 8.658799 |
module song_jesus_christ_is_risen_today (
input clock,
output [7:0] key_code,
input k_tr
);
reg [15:0] tmp;
wire [15:0] tmpa;
reg tr;
reg [15:0] step;
wire [15:0] step_r;
reg [15:0] TT;
reg [5:0] st;
reg go_end;
////////Music-processing////////
always @(negedge k_tr or posedge clock) begin
if (!k_tr) begin
step = 0;
st = 0;
tr = 0;
end else if (step < step_r) begin
case (st)
0: st = st + 1;
1: begin
tr = 0;
st = st + 1;
end
2: begin
tr = 1;
st = st + 1;
end
3: if (go_end) st = st + 1;
4: begin
st = 0;
step = step + 1;
end
endcase
end
end
/////////////// pitch //////////////////
wire [7:0] key_code1 = ((TT[3:0] == 1) ? 8'h2b : ( //1
(TT[3:0] == 2) ? 8'h34 : ( //2
(TT[3:0] == 3) ? 8'h33 : ( //3
(TT[3:0] == 4) ? 8'h3b : ( //4
(TT[3:0] == 5) ? 8'h42 : ( //5
(TT[3:0] == 6) ? 8'h4b : ( //6
(TT[3:0] == 7) ? 8'h4c : ( //7
(TT[3:0] == 10) ? 8'h52 : ( //1
(TT[3:0] == 15) ? 8'hf0 : 8'hf0)))))))));
/////////////// paddle ///////////////////
assign tmpa[15:0]=(
(TT[7:4]==15)?16'h10:(
(TT[7:4]==8)? 16'h20:(
(TT[7:4]==9)? 16'h30:(
(TT[7:4]==1)? 16'h40:(
(TT[7:4]==3)? 16'h60:(
(TT[7:4]==2)? 16'h80:(
(TT[7:4]==4)? 16'h100:0
))))))
);
/////////// note list ///////////
always @(step) begin
case (step)
0: TT = 8'h1f;
1: TT = 8'b00010001;
2: TT = 8'b00010011;
3: TT = 8'b00010101;
4: TT = 8'b00010001;
5: TT = 8'b00010100;
6: TT = 8'b00010110;
7: TT = 8'b00010110;
8: TT = 8'b00010101;
9: TT = 8'b10000011;
10: TT = 8'b10000100;
11: TT = 8'b10000101;
12: TT = 8'b10000001;
13: TT = 8'b00010100;
14: TT = 8'b10000011;
15: TT = 8'b10000100;
16: TT = 8'b00010011;
17: TT = 8'b00010010;
18: TT = 8'b00100001;
19: TT = 8'b00010100;
20: TT = 8'b00010101;
21: TT = 8'b00010110;
22: TT = 8'b00010101;
23: TT = 8'b00010100;
24: TT = 8'b00010011;
25: TT = 8'b00010011;
26: TT = 8'b00010010;
27: TT = 8'b10000011;
28: TT = 8'b10000100;
29: TT = 8'b10000101;
30: TT = 8'b10000001;
31: TT = 8'b00010100;
32: TT = 8'b10000011;
33: TT = 8'b10000100;
34: TT = 8'b00010011;
35: TT = 8'b00010010;
36: TT = 8'b00100001;
37: TT = 8'b00010111;
38: TT = 8'b00011010;
39: TT = 8'b00010010;
40: TT = 8'b00010101;
41: TT = 8'b00010001;
42: TT = 8'b00010010;
43: TT = 8'b00100011;
44: TT = 8'b10000111;
45: TT = 8'b10001010;
46: TT = 8'b10000010;
47: TT = 8'b10000101;
48: TT = 8'b00011010;
49: TT = 8'b10000111;
50: TT = 8'b10001010;
51: TT = 8'b00010111;
52: TT = 8'b00010110;
53: TT = 8'b00100101;
54: TT = 8'b10000101;
55: TT = 8'b10000110;
56: TT = 8'b10000111;
57: TT = 8'b10000101;
58: TT = 8'b00011010;
59: TT = 8'b00010011;
60: TT = 8'b00010100;
61: TT = 8'b00010110;
62: TT = 8'b00010110;
63: TT = 8'b00010101;
64: TT = 8'b10001010;
65: TT = 8'b10000111;
66: TT = 8'b10001010;
67: TT = 8'b10000101;
68: TT = 8'b10000110;
69: TT = 8'b10000111;
70: TT = 8'b10001010;
71: TT = 8'b10000010;
72: TT = 8'b00011010;
73: TT = 8'b00010111;
74: TT = 8'b00101010;
75: TT = 8'h1f;
endcase
end
assign step_r = 75; ///Total note
/////////////KEY release & code-out ////////////////
always @(negedge tr or posedge clock) begin
if (!tr) begin
tmp = 0;
go_end = 0;
end else if (tmp > tmpa) go_end = 1;
else tmp = tmp + 1;
end
assign key_code = (tmp < (tmpa - 1)) ? key_code1 : 8'hf0;
endmodule
| 7.065539 |
module song_loader(song_select, output_red, output_blue, output_yellow, output_total_notes);
input [4:0] song_select;
output [99:0] output_red, output_blue, output_yellow;
output [7:0] output_total_notes;
reg [7:0] total_notes;
assign output_total_notes = total_notes;
// songs available
localparam Take_on_Me = 5'b00011,
Through_The_Fire_and_Flames = 5'b11111,
Vlad_Bit = 5'b01010, // thanks, vlad.
Brian_This_Project_Is_Worth_Full_Marks = 5'b10111;
reg [99:0] red, blue, yellow;
assign output_red = red;
assign output_blue = blue;
assign output_yellow = yellow;
// Songs to switch to
always @(*)
begin
case (song_select[4:0])
Through_The_Fire_and_Flames:
begin
red <= 100'b0000000000101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010;
yellow <= 100'b0000000000010001000100010001000100010001000100010001000100010001000100010001000100010001000100010001;
blue <= 100'b0000000000000100010001000100010001000100010001000100010001000100010001000100010001000100010001000100;
total_notes <= 8'd90;
end
Take_on_Me:
begin
red <= 100'b0000000000000000000001010101010101010000000000000000010101010000000000000000010101010000000000000000;
yellow <= 100'b0000000000111111111100000000000000000101010001010101000000000101000001010101000000000000000000000000;
blue <= 100'b0000000000011111111100000000000000000000000100000000000000000000010100000000000000000000000000000000;
total_notes <= 8'd42;
end
Vlad_Bit:
begin
red <= 100'b0010001001001101110101000101001000000001000001011011010100101000010010100101010010010001001000101111;
yellow <= 100'b0111000001000100101001101101101010100011001001001011101110100100000100011011011011010110110111010011;
blue <= 100'b1001001011110110111111111111111111111111111111111000001111111111111111101001001001110111100010101100;
total_notes <= 8'd94;
end
Brian_This_Project_Is_Worth_Full_Marks:
begin
red <= 100'b1010101010101010101010101110101010101000101010010101011000100101010101010100001101001011010011110001;
yellow <= 100'b0000101010101011111010101010101000010101010101111111000001111010001100100100101010100010100101010100;
blue <= 100'b0110101010110010001010101100001010010100001010101010111111010010010000101001101000100101010101010001;
total_notes <= 8'd82;
default:
begin // Default is no song
red <= 100'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
yellow <= 100'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
blue <= 100'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
total_notes <= 0;
end
endcase
end
endmodule
| 7.479809 |
module. when doing so, load_new_note will go high.
Note:
- This module resets ram before recording.
----------------------------------------------------------------------------- */
module song_player(
input clk, // Standard system clock and reset
input reset, // Standard system clock and reset
input beat,
// inputs for MCU
input play_button, // debounced input for MCU
input next_button, // debounced input for MCU
input prev_button, // debounced input for MCU
input [1:0] master_state,
// inputs to write to ram
input write_enable,
input [6:0] write_address,
input [15:0] write_payload,
input clear_ram_pulse,
output [14:0] note_out,
output load_new_note,
output play,
output [1:0] current_song,
output reset_note_player
);
// ****************************************************************************
// WIRE/REG DECLARATION
// ****************************************************************************
// RAM RESET WIRES
wire address_mux_control = curr_reset_addr == 8'd128; // control MUX reset vs write
wire [7:0] curr_reset_addr; // current address in reset process
reg [6:0] addr_to_write; // controls write address vs reset
reg [15:0] payload_to_write; // controls write payload vs reset
wire song_done; // Output from song Reader alerts mcu to inc
wire clear_ram_pulse; // One cycle pulse when state ==> composer
// ****************************************************************************
// Master Control Unit
// ****************************************************************************
// The reset_player output from the MCU is run only to the song_reader because
// we don't need to reset any state in the note_player.
mcu mcu(
// system inputs
.clk(clk),
.reset(reset),
// state control inputs
.master_state(master_state),
.play_button(play_button),
.next_button(next_button),
.prev_button(prev_button),
.song_done(song_done),
// outputs
.play(play),
.reset_player(reset_note_player),
.song(current_song)
);
// ****************************************************************************
// Song Reader
// ****************************************************************************
song_reader song_reader(
.clk(clk),
.beat(beat),
.reset(reset | reset_note_player),
.play(play),
.song(current_song),
// inputs to write to RAM
.write_enable(write_enable || ~address_mux_control),
.write_address(addr_to_write),
.write_payload(payload_to_write),
// outputs
.note_out(note_out[14:9]),
.duration_out(note_out[8:0]),
.song_done(song_done),
.load_new_note(load_new_note)
);
// ****************************************************************************
// RAM RESET LOGIC
// ****************************************************************************
dffre #(.WIDTH(8)) RAM_RESET (
.clk(clk),
.r(clear_ram_pulse),
.en(~address_mux_control),
.d(curr_reset_addr + 8'd1),
.q(curr_reset_addr)
);
always @(*) begin
case(address_mux_control)
1'b1: begin
addr_to_write = write_address;
payload_to_write = write_payload;
end
1'b0: begin
addr_to_write = curr_reset_addr[6:0];
payload_to_write = 16'b1000000000111100;
end
default: begin
addr_to_write = 7'd0;
payload_to_write = 16'b1000000000111100;
end
endcase
end
endmodule
| 7.207226 |
module song_reader (
clk, //100MHz时钟信号
reset, //复位信号，高电平有效
play, //来自mcu的控制信号，高电平有效
song, //来自mcu的控制信号，当前播放歌曲的序号
note_done, //note_player的应答信号，表示一个音符播放结束并索取新音符
song_done, //给mcu的应答信号，当乐曲播放结束，输出一个时钟周期宽度的脉冲，表示乐曲播放结束
note, //音符标记
duration, //音符的持续时间
new_note //给模块note_player的控制信号，表示新的音符需播放
);
input clk, reset, play, note_done;
input [1:0] song;
output song_done, new_note;
output [5:0] note, duration;
wire [4:0] q; //歌曲音符地址（五位）
wire co; //歌曲结束信号
//控制器
song_reader_ctrl song_reader1 (
.clk(clk),
.reset(reset),
.note_done(note_done),
.play(play),
.new_note(new_note)
);
//地址计数器
counter_n #(
.n(32),
.counter_bits(5)
) song_choose (
.clk(clk),
.en (note_done),
.r (reset),
.q (q),
.co (co)
);
//song_rom
song_rom song1 (
.clk (clk),
.dout({note[5:0], duration[5:0]}),
.addr({song[1:0], q[4:0]})
);
//结束判断
is_over is_over1 (
.clk(clk),
.duration(duration),
.r(co),
.out(song_done)
);
endmodule
| 7.825174 |
module song_reader_ctrl (
clk,
reset,
note_done,
play,
new_note
);
input clk, reset, note_done, play;
output reg new_note;
parameter RESET = 0, NEW_NOTE = 1, WAIT = 2, NEXT_NOTE = 3;
reg [1:0] state, nextstate;
//第一段-时序电路：D寄存器
always @(posedge clk) begin
if (reset) state = RESET;
else state = nextstate;
end
//第二段-组合电路：下一状态和输出电路
always @(*) begin
new_note = 0; //默认为0
case (state)
RESET: begin
if (play) nextstate = NEW_NOTE;
else nextstate = RESET;
end
NEW_NOTE: begin
new_note = 1;
nextstate = WAIT;
end
WAIT: begin
if (!play) nextstate = RESET;
else if (note_done) nextstate = NEXT_NOTE;
else nextstate = WAIT;
end
NEXT_NOTE: begin
nextstate = NEW_NOTE;
end
endcase
end
endmodule
| 6.738957 |
module song_reader_tb_v;
parameter delay = 10;
// Inputs
reg clk;
reg reset;
reg play;
reg [1:0] song;
reg note_done;
// Outputs
wire song_done;
wire [5:0] note;
wire [5:0] duration;
wire new_note;
// Instantiate the Unit Under Test (UUT)
song_reader uut (
.clk(clk),
.reset(reset),
.play(play),
.song(song),
.song_done(song_done),
.note(note),
.duration(duration),
.new_note(new_note),
.note_done(note_done)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
play = 0;
song = 0;
note_done = 0;
//
#(delay * 1.5 + 1) reset = 0;
#(delay * 2) play = 1;
repeat (29) begin
#(delay * 5) note_done = 1;
#(delay) note_done = 0;
end
//
reset = 1;
#(delay) reset = 0;
#(delay * 5) play = 0;
#(delay * 16) $stop;
end
//clock
always #(delay / 2) clk = ~clk;
endmodule
| 6.810514 |
module song_writer (
input clk,
input reset,
input [5:0] root,
input [7:0] switches,
input beat,
input [1:0] state,
input scale_button,
output [47:0] notes,
output finished_recording,
output start_recording,
output write_enable,
output [6:0] write_address,
output [15:0] write_payload
);
/* -----------------------------------------------------------------------------
MODULE INSTANTIATIONS
----------------------------------------------------------------------------- */
switch_to_note SWITCH_TO_NOTE (
// input
.root(root),
.clk(clk),
.reset(reset),
.scale_button(scale_button),
// output
.switches(switches),
.notes(notes)
);
notes_to_ram NOTES_TO_RAM (
// inputs
.clk (clk),
.reset(reset),
.beat (beat),
.notes(notes),
.switches(switches),
.master_state(state),
//outputs
.write_payload(write_payload),
.write_address(write_address),
.finished_recording(finished_recording),
.start_recording(start_recording),
.write_enable(write_enable)
);
endmodule
| 7.179011 |
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