code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module soft_ecc_ram_16bit_tb ();
`include "log2.inc"
parameter NUM_WORDS = 512;
localparam ADDR_WIDTH = log2(NUM_WORDS - 1);
parameter RAM_RD_LATENCY = 4;
parameter DATA_BITS = 16;
localparam DATA_MASK = {DATA_BITS{1'b1}};
reg clk, rst;
reg [ADDR_WIDTH-1:0] address_a;
reg [ADDR_WIDTH-1:0] addres... | 8.952439 |
module soft_ecc_ram_32bit (
rst,
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b,
err_a,
err_b
);
`include "log2.inc"
// Number of 32 bit data words (stored as 39 bit words internally)
parameter NUM_WORDS = 512;
localparam AD... | 8.952439 |
module soft_ecc_ram_32bit_tb ();
`include "log2.inc"
parameter NUM_WORDS = 512;
localparam ADDR_WIDTH = log2(NUM_WORDS - 1);
parameter RAM_RD_LATENCY = 4;
parameter DATA_BITS = 32;
localparam DATA_MASK = {DATA_BITS{1'b1}};
reg clk, rst;
reg [ADDR_WIDTH-1:0] address_a;
reg [ADDR_WIDTH-1:0] addres... | 8.952439 |
module soft_ecc_ram_64bit (
rst,
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b,
err_a,
err_b
);
`include "log2.inc"
// Number of 64 bit data words (stored as 72 bit words internally)
parameter NUM_WORDS = 512;
localparam AD... | 8.952439 |
module soft_ecc_ram_64bit_tb ();
`include "log2.inc"
parameter NUM_WORDS = 512;
localparam ADDR_WIDTH = log2(NUM_WORDS - 1);
parameter RAM_RD_LATENCY = 4;
parameter DATA_BITS = 64;
localparam DATA_MASK = {DATA_BITS{1'b1}};
reg clk, rst;
reg [ADDR_WIDTH-1:0] address_a;
reg [ADDR_WIDTH-1:0] addres... | 8.952439 |
module soft_ecc_ram_8bit (
rst,
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b,
err_a,
err_b
);
`include "log2.inc"
// Number of 8 bit data words (stored as 13 bit words internally)
parameter NUM_WORDS = 512;
localparam ADDR... | 8.952439 |
module soft_gtv (
input rst,
input clk,
input spd_btn,
input [2:0] mode,
input evnt,
output [7:0] count
);
reg evnt_ff;
reg gtv_tm_flg;
wire gtv_ev_flg;
reg [7:0] gtv_cnt;
reg [7:0] gtv_cnt_ff;
reg [24:0] base_cnt;
reg [24:0] base_cnt_ff;
reg [28:0] spd_ff;
assign count = gtv_... | 7.155872 |
module soft_pcs_8b10b_sequence_tb;
parameter VCD_FILE = "soft_pcs_8b10b_sequence_tb.vcd";
`include "tb_base.v"
// Send a random sequence of characters to the decoder and make sure the
// decoder produces the same character sequence and no disparity or
// not-in-table errors
wire [9:0] raw_data;
reg [7... | 7.414814 |
module soft_pcs_8b10b_table_tb;
parameter VCD_FILE = "soft_pcs_8b10b_table_tb.vcd";
`include "tb_base.v"
// Build a table of all valid 8b10b words using the encoder and then check
// for every possible 10-bit value that the decoder correctly reports the
// not-in-table flag
reg [1023:0] valid_table = 'h0... | 7.414814 |
module soft_pcs_pattern_align_tb;
parameter VCD_FILE = "soft_pcs_pattern_align_tb.vcd";
localparam [9:0] PATTERN_P = 10'b1010000011;
localparam [9:0] PATTERN_N = 10'b0101111100;
`define TIMEOUT 1000000
`include "tb_base.v"
integer counter = 0;
reg [3:0] bitshift = 4'd0;
reg [9:0] comma_unaligned;
... | 7.906764 |
module soft_trig_generator (
ctrl_i,
ctrlclk_i,
trigclk_i,
slow_ce_i,
trig_o
);
input [7:0] ctrl_i;
input ctrlclk_i;
input trigclk_i;
input slow_ce_i;
output trig_o;
wire [3:0] delay_count = ctrl_i[7:4];
wire [2:0] trig_count = ctrl_i[3:1];
wire trig_go = ctrl_i[0];
reg [4:0] de... | 6.548026 |
module Soft_Vector_Processor
//---------------------------------------------------------------------------------------------------------------------------------------------------
// Customizable parameters at generation
//-------------------------------------------------------------------------------------------------... | 8.047667 |
module divider (
input clk,
input rst_n,
output reg s_counter3_flg
);
//计时0.2S
reg [9:0] s_counter1;
reg [9:0] s_counter2;
reg [9:0] s_counter3;
reg s_counter2_flg;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
s_counter1 <= 6'd0;
end else if (s_counter1 == 6'd49)... | 7.389371 |
module people_move (
input clk,
input rst_n,
input BTN_WEST,
input BTN_EAST,
input BTN_SOUTH,
input BTN_NORTH,
input s_counter3_flg,
output reg move_left,
output reg move_right,
output reg move_up,
output reg move_down
);
always @(posedge clk or negedge rst_n) begin
if ... | 7.254119 |
module enabled_color (
input clk,
input rst_n,
input biankuang,
input zhangai_1,
input zhangai_2,
input xiangzi_biaozhi,
input xiangzi_show,
input xiangzi_show_1,
input xiangzi_show_2,
input win_point,
input win_point_1,
input win_point_2,
input win_point_flg,
inp... | 6.859694 |
module solid_color_screen (
state,
hcnt,
vcnt,
color,
color_out
);
input state, hcnt, vcnt, color;
output color_out;
wire [1:0] state;
wire [9:0] hcnt, vcnt;
wire [2:0] color;
reg [2:0] color_out;
always @(*) begin
if (state == 2'b00) color_out <= color;
else color_out <= ... | 6.566949 |
module mux_2x1 (
out,
seli,
a,
b
);
input seli, a, b;
output out;
assign out = seli ? a : b;
endmodule
| 6.925133 |
module mux_8x1 (
out,
sel,
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7
);
input in0, in1, in2, in3, in4, in5, in6, in7;
input [2:0] sel;
output out;
//assign out = sel[2] ? (sel[1] ? (sel[0] ? in7:in6) : (sel[0] ? in5:in4)) : (sel[1] ? (sel[0] ? in7:in6) : (sel[0] ? in7:in6))... | 7.358788 |
module counter_3bit (
count,
clear,
clk
);
input clear, clk;
output reg [2:0] count;
always @(posedge clk or negedge clear) begin
if (!clear) begin
count <= 3'b000;
end else begin
count <= count + 1;
end
end
endmodule
| 7.241203 |
module decoder (
out,
en,
count
);
input en;
input [2:0] count;
output reg [7:0] out;
always @(en or count) begin
out = 8'b00000000;
if (en) begin
case (count)
3'b000: out[0] <= 1;
3'b001: out[1] <= 1;
3'b010: out[2] <= 1;
3'b011: out[3] <= 1;
... | 7.018254 |
module top_module (
o,
clear,
clk,
en,
s
);
input en, clk, clear;
input [2:0] s;
output o;
wire [2:0] count;
wire [7:0] c, g, e;
counter_3bit cnt (
count,
clear,
clk
);
decoder d (
c,
en,
count
);
memory m (
g,
s
);
mux_array m... | 7.203305 |
module FPGA_SOLOMON (
input MCLK, // 48.0MHz
input RESET,
input [7:0] INP0,
input [7:0] INP1,
input [7:0] INP2,
input [7:0] DSW0,
input [7:0] DSW1,
input [8:0] PH,
input [8:0] PV,
output PCLK,
output [11:0] POUT,
output [15:0] SND,
input ROMCL,
input [1... | 6.638126 |
module PROTECT (
input RESET,
input CPUCL,
input [15:0] CPUAD,
input CPUMW,
input [7:0] CPUWD,
output reg [7:0] OUT
);
always @(posedge CPUCL or posedge RESET) begin
if (RESET) OUT <= 0;
else begin
if ((CPUAD == 16'hE803) & CPUMW) OUT <= (CPUWD & 8'h08);
end
end... | 6.929555 |
module MAINROM (
input CL,
input [15:0] AD,
output [7:0] DT,
output DV,
input DLCL,
input [19:0] DLAD,
input [7:0] DLDT,
input DLEN
);
/*
34000-37FFF MAINCPU0
38000-3FFFF MAINCPU1 (4000h swaped)
40000-40FFF MAINCPU2
*/
wire [7:0] dt0, dt1, dt2, dt3;
DLROM ... | 6.632587 |
module BGROM (
input CL,
input [15:0] AD,
output [7:0] DT,
input DLCL,
input [19:0] DLAD,
input [7:0] DLDT,
input DLEN
);
/*
20000-27FFF BGCHIP0
28000-2FFFF BGCHIP1
*/
DLROM #(16, 8) r (
CL,
AD,
DT,
DLCL,
DLAD,
DLDT,
DLEN & ... | 6.673735 |
module SNDROM (
input CL,
input [13:0] AD,
output [7:0] DT,
input DLCL,
input [19:0] DLAD,
input [7:0] DLDT,
input DLEN
);
// 30000-33FFF SNDCPU
DLROM #(14, 8) r (
CL,
AD,
DT,
DLCL,
DLAD,
DLDT,
DLEN & (DLAD[19:14] == 6'b0011_00)
... | 6.508443 |
module DLROM #(
parameter AW,
parameter DW
) (
input CL0,
input [(AW-1):0] AD0,
output reg [(DW-1):0] DO0,
input CL1,
input [(AW-1):0] AD1,
input [(DW-1):0] DI1,
input WE1
);
reg [(DW-1):0] core[0:((2**AW)-1)];
always @(posedge CL0) D... | 6.544719 |
module SOLOMON_SOUND (
input RESET,
input CPUCL,
input AXSCL,
input [7:0] SNDNO,
input SNDWR,
input SNDT,
input PSGCL,
output [15:0] SNDO,
input DLCL,
input [19:0] DLAD,
input [7:0] DLDT,
input DLEN
);
wire [15:0] CPUAD;
wire [7:0] CPUID, CPUWD... | 6.670566 |
module INTCTR (
input RESET,
input AXSCL,
input [7:0] SNDNO,
input SNDWR,
input SNDT,
output NMI,
output IRQ,
output reg [7:0] SNDLT
);
reg [3:0] NMICN, IRQCN;
reg pSNDW, pIRQQ;
assign NMI = (NMICN != 0);
assign IRQ = (IRQCN != 0);
always @(pos... | 6.519803 |
module PSGx3 (
input RESET,
input PSGCL,
input CL,
input [7:0] AD,
input WR,
input [7:0] OD,
output [15:0] SNDOUT
);
wire [7:0] A0, B0, C0;
wire [7:0] A1, B1, C1;
wire [7:0] A2, B2, C2;
wire rst = ~RESET;
wire asel = ~AD[0];
wire wd = ~WR;
wire cs_sg1 = ~(AD[7:4] == 4'h1);
... | 6.574222 |
module debounced_counter (
// Inputs
input clk,
input rst_btn,
input inc_btn,
// Outputs
output reg [3:0] led
);
// States
localparam STATE_HIGH = 2'd0;
localparam STATE_LOW = 2'd1;
localparam STATE_WAIT = 2'd2;
localparam STATE_PRESSED = 2'd3;
// Max counts for wait state (40 ms... | 8.528321 |
module is to solve the problem of "read after write"
//In order to solve this problem, I design a module to forward the data of WB to ID.
module Solution_of_RAW(
input [4:0]RsAddr_id,
input [4:0]RtAddr_id,
input [4:0]RegWriteAddr_wb,
input RegWrite_wb,
output reg Rs_selection,
output reg Rt_selection
);
always... | 7.501975 |
module Solver (
Clk,
data_1_80,
data_2_96,
work_2,
output_1_96,
output_2_80
);
input Clk;
input [59:0] data_1_80;
input [77:0] data_2_96;
input [1:0] work_2;
output [77:0] output_1_96;
output [59:0] output_2_80;
wire [77:0] output_1_96_ENC_INTERNAL;
wire [59:0] output_2_80_DEC_IN... | 7.170249 |
module solve_color (
input clk,
input vga_clk,
input rst,
input [9:0] col_addr,
input [8:0] row_addr,
// Slope effect
input [10:0] sin_x,
input [10:0] sin_y,
// Player tracing
input [10:0] position_x,
input [10:0] position_y,
// Mode related
input [1:0] map,
input... | 7.180927 |
module solve_img_top #(
parameter ADDR_WIDTH = 18,
parameter STATE_WIDTH = 5
) (
input wire clk,
output wire rst_n,
//ram port of b
output wire enb,
output wire web,
output wire [ADDR_WIDTH-1:0] addrb,
output wire [7:0] dinb,
input wire [7:0] doutb,
//dmn cell ports
outp... | 6.509655 |
module solve_position (
input clk,
input rst,
input [10:0] init_x,
input [10:0] init_y,
// input for checking scoring
input [10:0] score_x,
input [10:0] score_y,
input [10:0] velocity_x,
input [10:0] velocity_y,
// input for immediate react to collision
input [3:0] collision,... | 7.392539 |
module solve_sin (
input clk,
input rst,
input [3:0] slope,
output [10:0] sin_x,
output [10:0] sin_y
);
reg [10:0] y = 11'd0;
reg [10:0] x = 11'd0;
// everytime button pressed,
// sin ++
// Horizontal
always @(posedge clk or negedge rst) begin
if (!rst) begin
x <= 11'd0;
... | 6.716191 |
module soma_altpriority_encoder_3e8 (
data,
q,
zero
);
input [1:0] data;
output [0:0] q;
output zero;
assign q = {data[1]}, zero = (~(data[0] | data[1]));
endmodule
| 7.016879 |
module soma_altpriority_encoder_6e8 (
data,
q,
zero
);
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder13_q;
wire wire_altpriority_encoder13_zero;
wire [0:0] wire_altpriority_encoder14_q;
wire wire_altpriority_encoder14_zero;
soma_altpriority_encoder_3e8 a... | 7.016879 |
module soma_altpriority_encoder_be8 (
data,
q,
zero
);
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder11_q;
wire wire_altpriority_encoder11_zero;
wire [1:0] wire_altpriority_encoder12_q;
wire wire_altpriority_encoder12_zero;
soma_altpriority_encoder_6e8 a... | 7.016879 |
module soma_altpriority_encoder_3v7 (
data,
q
);
input [1:0] data;
output [0:0] q;
assign q = {data[1]};
endmodule
| 7.016879 |
module soma_altpriority_encoder_6v7 (
data,
q
);
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder17_q;
wire [0:0] wire_altpriority_encoder18_q;
wire wire_altpriority_encoder18_zero;
soma_altpriority_encoder_3v7 altpriority_encoder17 (
.data(data[1:0]),
.q(wire_altp... | 7.016879 |
module soma_altpriority_encoder_bv7 (
data,
q
);
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder15_q;
wire [1:0] wire_altpriority_encoder16_q;
wire wire_altpriority_encoder16_zero;
soma_altpriority_encoder_6v7 altpriority_encoder15 (
.data(data[3:0]),
.q(wire_altp... | 7.016879 |
module soma_altpriority_encoder_r08 (
data,
q
);
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder10_q;
wire wire_altpriority_encoder10_zero;
wire [2:0] wire_altpriority_encoder9_q;
soma_altpriority_encoder_be8 altpriority_encoder10 (
.data(data[15:8]),
.q(wire_alt... | 7.016879 |
module soma_altpriority_encoder_rf8 (
data,
q,
zero
);
input [15:0] data;
output [3:0] q;
output zero;
wire [2:0] wire_altpriority_encoder19_q;
wire wire_altpriority_encoder19_zero;
wire [2:0] wire_altpriority_encoder20_q;
wire wire_altpriority_encoder20_zero;
soma_altpriority_encoder_be8 ... | 7.016879 |
module soma_altpriority_encoder_qb6 (
data,
q
);
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder7_q;
wire [3:0] wire_altpriority_encoder8_q;
wire wire_altpriority_encoder8_zero;
soma_altpriority_encoder_r08 altpriority_encoder7 (
.data(data[15:0]),
.q(wire_altpri... | 7.016879 |
module soma_altpriority_encoder_nh8 (
data,
q,
zero
);
input [1:0] data;
output [0:0] q;
output zero;
assign q = {(~data[0])}, zero = (~(data[0] | data[1]));
endmodule
| 7.016879 |
module soma_altpriority_encoder_qh8 (
data,
q,
zero
);
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder27_q;
wire wire_altpriority_encoder27_zero;
wire [0:0] wire_altpriority_encoder28_q;
wire wire_altpriority_encoder28_zero;
soma_altpriority_encoder_nh8 a... | 7.016879 |
module soma_altpriority_encoder_vh8 (
data,
q,
zero
);
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder25_q;
wire wire_altpriority_encoder25_zero;
wire [1:0] wire_altpriority_encoder26_q;
wire wire_altpriority_encoder26_zero;
soma_altpriority_encoder_qh8 a... | 7.016879 |
module soma_altpriority_encoder_fj8 (
data,
q,
zero
);
input [15:0] data;
output [3:0] q;
output zero;
wire [2:0] wire_altpriority_encoder23_q;
wire wire_altpriority_encoder23_zero;
wire [2:0] wire_altpriority_encoder24_q;
wire wire_altpriority_encoder24_zero;
soma_altpriority_encoder_vh8 ... | 7.016879 |
module soma_altpriority_encoder_n28 (
data,
q
);
input [1:0] data;
output [0:0] q;
assign q = {(~data[0])};
endmodule
| 7.016879 |
module soma_altpriority_encoder_q28 (
data,
q
);
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder33_q;
wire wire_altpriority_encoder33_zero;
wire [0:0] wire_altpriority_encoder34_q;
soma_altpriority_encoder_nh8 altpriority_encoder33 (
.data(data[1:0]),
.q(wire_altp... | 7.016879 |
module soma_altpriority_encoder_v28 (
data,
q
);
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder31_q;
wire wire_altpriority_encoder31_zero;
wire [1:0] wire_altpriority_encoder32_q;
soma_altpriority_encoder_qh8 altpriority_encoder31 (
.data(data[3:0]),
.q(wire_altp... | 7.016879 |
module soma_altpriority_encoder_f48 (
data,
q
);
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder29_q;
wire wire_altpriority_encoder29_zero;
wire [2:0] wire_altpriority_encoder30_q;
soma_altpriority_encoder_vh8 altpriority_encoder29 (
.data(data[7:0]),
.q(wire_alt... | 7.016879 |
module soma_altpriority_encoder_e48 (
data,
q
);
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder21_q;
wire wire_altpriority_encoder21_zero;
wire [3:0] wire_altpriority_encoder22_q;
soma_altpriority_encoder_fj8 altpriority_encoder21 (
.data(data[15:0]),
.q(wire_al... | 7.016879 |
module soma (
clk_en,
clock,
dataa,
datab,
result
);
input clk_en;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
soma_altfp_add_sub_3ij soma_altfp_add_sub_3ij_component (
.clk_en(clk_en... | 6.646636 |
module somacompleta4bits (
s,
x,
y
);
output [4:0] s;
input [3:0] x, y;
wire c1, c2, c3;
meiasoma HA1 (
s[0],
c1,
x[0],
y[0]
);
somacompleta FA1 (
s[1],
c2,
x[1],
y[1],
c1
);
somacompleta FA2 (
s[2],
c3,
x[2],
y... | 7.404034 |
module meiasoma (
s0,
s1,
x,
y
);
output s0, s1;
input x, y;
xor XOR1 (s0, x, y);
and AND1 (s1, x, y);
endmodule
| 7.813544 |
module somacompleta (
s0,
s1,
x,
y,
v1
);
output s0, s1;
input x, y, v1;
wire s4, s5, s2;
meiasoma HA1 (
s2,
s4,
x,
y
);
meiasoma HA2 (
s0,
s5,
s2,
v1
);
or OR1 (s1, s5, s4);
endmodule
| 7.045629 |
module test4bits;
reg [3:0] x, y;
wire [4:0] s;
integer a, b;
somacompleta4bits SOM1 (
s,
x,
y
);
initial begin //definindo valores iniciais
x = 0;
y = 0;
end
initial begin //inicio
$display("Guia 05 - Karen Alves Pereira - 407451");
$display("Soma completa de dois... | 6.751233 |
module saida1 (
s1,
x,
y
);
input x, y;
output s1;
wire s1;
and AND1 (s1, x, y);
endmodule
| 6.784364 |
module meiaSoma1 (
s0,
s1,
x,
y
);
input x, y;
output s0, s1;
wire s0, s1;
saida0 S0 (
s0,
x,
y
);
saida1 S1 (
s1,
x,
y
);
endmodule
| 6.754192 |
module somaCompleta (
s3,
s5,
x,
y,
z
);
input x, y, z;
output s1, s0, s3, s4, s5;
wire s1, s0;
meiaSoma1 MEIASOMA1 (
s0,
s1,
x,
y
);
meiaSoma1 MEIASOMA2 (
s3,
s4,
s0,
z
);
or OR1 (s5, s1, s4);
endmodule
| 7.146397 |
module somador3_bits (
s0,
s1,
s2,
s3,
a0,
a1,
a2,
b0,
b1,
b2
);
input a0, a1, a2, b0, b1, b2;
output s0, s1, s2, s3;
wire saida0, saida1;
somaCompleta SOMACOMPLETA1 (
s0,
saida0,
a0,
b0,
0
);
somaCompleta SOMACOMPLETA2 (
s1,
... | 6.663999 |
module somador1 (
input [7:0] A,
B,
output [7:0] C
);
assign C = A + B;
endmodule
| 7.583878 |
module somador2 (
proximo_endereco,
imediato_extendido,
saida,
clock
);
// input
input [31:0] proximo_endereco;
input [31:0] imediato_extendido;
input clock;
// output
output [31:0] saida;
assign saida = proximo_endereco + imediato_extendido;
endmodule
| 7.22221 |
module somacompleto (
s0,
s1,
a,
b,
c,
v
);
output s0, s1;
input a, b, c, v;
wire temp0, temp1, temp2, temp3, temp4, temp5, temp6, temp7, temp8, temp9, temp10, temp11, temp12, temp13;
or Or1 (s0, temp0, temp1);
or Or2 (s1, temp2, temp3, temp4, temp5);
xor Xor1 (temp0, a, b);
and An... | 7.253117 |
module saida1 (
s1,
a,
b
);
input a, b;
output s1;
wire s1;
and AND1 (s1, a, b);
endmodule
| 6.784364 |
module meiaSoma1 (
s0,
s1,
a,
b
);
input a, b;
output s0, s1;
wire s0, s1;
saida0 S0 (
s0,
a,
b
);
saida1 S1 (
s1,
a,
b
);
endmodule
| 6.754192 |
module somaCompleta (
s3,
s5,
a,
b,
c
);
input a, b, c;
output s1, s0, s3, s4, s5;
wire s1, s0;
meiaSoma1 MEIASOMA1 (
s0,
s1,
a,
b
);
meiaSoma1 MEIASOMA2 (
s3,
s4,
s0,
c
);
or OR1 (s5, s1, s4);
endmodule
| 7.146397 |
module somador_3bits (
s0,
s1,
s2,
s3,
a0,
a1,
a2,
b0,
b1,
b2
);
input a0, a1, a2, b0, b1, b2;
output s0, s1, s2, s3;
wire sSOMAC0, sSOMAC1;
somaCompleta SOMAC1 (
s0,
sSOMAC0,
a0,
b0,
0
);
somaCompleta SOMAC2 (
s1,
sSOMAC1,
... | 6.752206 |
module somador_bcd (
a,
b,
carry_in,
soma,
carry_out
);
input [3:0] a, b;
input carry_in;
output [3:0] soma;
output carry_out;
reg [4:0] soma_aux;
reg [3:0] soma;
reg carry_out;
always @(a, b, carry_in) begin
soma_aux = a + b + carry_in; //adiciona todos os inputs
if (som... | 7.119594 |
module saida1 (
s1,
x,
y
);
input x, y;
output s1;
wire s1;
and AND1 (s1, x, y);
endmodule
| 6.784364 |
module meiaSoma1 (
s0,
s1,
x,
y
);
input x, y;
output s0, s1;
wire s0, s1;
saida0 S0 (
s0,
x,
y
);
saida1 S1 (
s1,
x,
y
);
endmodule
| 6.754192 |
module somaCompleta (
s3,
s5,
x,
y,
z
);
input x, y, z;
output s1, s0, s3, s4, s5;
wire s1, s0;
meiaSoma1 MEIASOMA1 (
s0,
s1,
x,
y
);
meiaSoma1 MEIASOMA2 (
s3,
s4,
s0,
z
);
or OR1 (s5, s1, s4);
endmodule
| 7.146397 |
module somador3_bits (
s0,
s1,
s2,
s3,
a0,
a1,
a2,
b0,
b1,
b2
);
input a0, a1, a2, b0, b1, b2;
output s0, s1, s2, s3;
wire saida0, saida1;
somaCompleta SOMACOMPLETA1 (
s0,
saida0,
a0,
b0,
0
);
somaCompleta SOMACOMPLETA2 (
s1,
... | 6.663999 |
module soma_endereco_proc (
id_proc,
ender_in,
ender,
M,
tam_particao
);
input [1:0] id_proc;
input [8:0] ender_in;
output reg [8:0] ender;
input [6:0] M;
input [6:0] tam_particao;
// Soma deslocamento aos endereços
// para cada tipo de processo
always @(*) begin
if (id_proc =... | 7.014518 |
module someTwoPortVendorMem_128_8_0 (
QA,
CLKA,
CENA,
WENA,
AA,
DA,
OENA,
QB,
CLKB,
CENB,
WENB,
AB,
DB,
OENB
);
output [7:0] QA;
input CLKA;
input CENA;
input WENA;
input [6:0] AA;
input [7:0] DA;
input OENA;
output [7:0] QB;
input CLKB;
input... | 6.911291 |
module someTwoPortVendorMem_4096_32_0 (
QA,
CLKA,
CENA,
WENA,
AA,
DA,
OENA,
QB,
CLKB,
CENB,
WENB,
AB,
DB,
OENB
);
output [31:0] QA;
input CLKA;
input CENA;
input WENA;
input [11:0] AA;
input [31:0] DA;
input OENA;
output [31:0] QB;
input CLKB;
... | 6.911291 |
module someTwoPortVendorMem_4096_32_8 (
QA,
CLKA,
CENA,
WENA,
AA,
DA,
OENA,
QB,
CLKB,
CENB,
WENB,
AB,
DB,
OENB
);
output [31:0] QA;
input CLKA;
input CENA;
input WENA;
input [11:0] AA;
input [31:0] DA;
input OENA;
output [31:0] QB;
input CLKB;
... | 6.911291 |
module pipe_pal
#(parameter W_DATA=32, localparam W_ADDR = 16)
(input a, b,
input [W_DATA-1:0] c, d); /* multi-line
comment */ (* param *) parameter XX = 3;
(* local_param *) localparam [W_DATA-1:0] XY = 4;
input a, b;
input [W_DATA-1:0] c, d;
assign a_wire = (3+4)*2 + 4 - 1;
assign b_wire = a_... | 7.941253 |
module sonar (
input clk,
rst_n, // clk 10MHz
input do_measure,
input sonar_pulse,
output reg [7:0] inches,
output reg sonar_trigger = 0,
output reg READY = 0
);
parameter s_standby = 0, s_startMeasure = 1, s_waitForPulse = 2, s_countPulse = 3;
reg [1:0] state = s_standby, next_state ... | 7.94105 |
module song #(
parameter LENGTH = 170,
parameter WIDTH = 12,
parameter ADDR = $clog2(LENGTH)
) (
input clk,
input [ADDR-1:0] addr,
output [WIDTH-1:0] command
);
reg [WIDTH-1:0] song[LENGTH-1:0];
initial begin
$readmemh("song.txt", song, 0, LENGTH - 1);
end
assign command = song... | 7.448919 |
module song3 (
clk,
ifplay,
SongData
);
input ifplay;
input clk;
output [4:0] SongData;
reg [7:0] state;
initial state = 0;
reg [4:0] YinFu;
assign SongData = YinFu;
always @(posedge clk) begin
state = state + 1'b1;
if (!ifplay) begin
state = 0;
end
if (state > 196) beg... | 6.512848 |
module SongDriver (
input iFpgaClock,
iFpgaReset, //注意这个reset是高有效，我写的, 需要一个手动复位按钮 //输入时钟100MHz，管脚绑定P17
input [5:0] track0,
input [5:0] track1,
input [5:0] track2,
input [5:0] track3,
output speaker //输出至扬声器的信号，本例中为方波.
);
wire clk_6mhz; //用于产生各种音阶频率的基准频率
ClockDivid... | 7.184663 |
module SongHz (
input clk,
input rst_n,
output reg clk_5m
);
//clk = 50MHz, div into 5MHz
//1 pause/ 10 clocks
reg [4:0] cnt = 5'h0;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) //ػʱ
cnt <= 5'h0;
else if (cnt == 5'h9) //ʱÿ5M
cnt <= 5'h0;
else cnt <= cnt + 5'h1;... | 6.780601 |
module songle_digit_counter (
clk,
rst,
increase,
decrease,
upper_bound,
lower_bound,
up_initial_value,
down_initial_value,
rst_value,
carry,
borrow,
value
);
input clk, rst, increase, decrease;
input [3:0] upper_bound;
input [3:0] lower_bound;
input [3:0] up_init... | 6.779216 |
module songMemory (
clk,
Addr,
DataOut
);
parameter song_len = 12;
parameter encoding_len = 12;
input clk;
input [5:0] Addr;
output [encoding_len-1:0] DataOut;
reg [encoding_len-1:0] mem[song_len-1:0];
initial begin
$readmemb("increasing.dat", mem);
end
assign DataOut = mem[Addr];
e... | 6.732836 |
module testSongMemory;
reg clk;
initial clk = 0;
always #10 clk = ~clk;
reg [5:0] Addr;
initial Addr = 6'b0;
wire [11:0] notes;
songMemory sMem (
clk,
Addr,
notes
);
always #100 Addr = Addr + 1;
endmodule
| 6.759468 |
module songplayer (
audio,
sys_CLK,
button,
song_id
);
output audio;
input sys_CLK;
input button;
input [1:0] song_id;
reg [23:0] counter4Hz, counter6MHz;
reg [13:0] count, origin;
reg audiof;
reg clk_6MHz, clk_4Hz;
reg [4:0] j;
reg [7:0] len;
assign audio = button ? audiof :... | 6.812998 |
module song_amazing_grace (
input clock,
output [7:0] key_code
);
reg [15:0] tmp;
wire [15:0] tmpa;
reg tr;
reg [15:0] step;
wire [15:0] step_r;
reg [15:0] TT;
reg [5:0] st;
reg restart;
reg go_end;
////////Music-processing////////
always @(negedge restart or posedge clock) begin
if ... | 7.324128 |
module -----------------
//------------- author : Dino --------------------------
module song_control(
input CLK,
input pre,
input nxt,
output reg [2:0] current
);
parameter DELAY_TIME = 10000000;
integer delay = 0;
always @ (negedge CLK) begin
if(delay == DELAY_TIME) begin
if(pre) begin
current <= (cu... | 7.025213 |
modulename>song_data_loader_t</modulename>
/// <filedescription>ʼ</filedescription>
/// <version>
/// 0.0.1 (UnnamedOrange) : First commit.
/// </version>
`timescale 1ns / 1ps
module song_data_loader_t #
(
parameter [7:0] static_init_aux_info = 8'b00000100,
parameter restarting_timeout = 10000000
)
(
// CPU
outpu... | 8.658799 |
module song_jesus_christ_is_risen_today (
input clock,
output [7:0] key_code,
input k_tr
);
reg [15:0] tmp;
wire [15:0] tmpa;
reg tr;
reg [15:0] step;
wire [15:0] step_r;
reg [15:0] TT;
reg [5:0] st;
reg go_end;
////////Music-processing////////
always @(negedge k_tr or posedge clock) b... | 7.065539 |
module song_loader(song_select, output_red, output_blue, output_yellow, output_total_notes);
input [4:0] song_select;
output [99:0] output_red, output_blue, output_yellow;
output [7:0] output_total_notes;
reg [7:0] total_notes;
assign output_total_notes = total_notes;
// songs available
localparam Take_... | 7.479809 |
module. when doing so, load_new_note will go high.
Note:
- This module resets ram before recording.
----------------------------------------------------------------------------- */
module song_player(
input clk, // Standard system clock and reset
input reset, // Standar... | 7.207226 |
module song_reader (
clk, //100MHz时钟信号
reset, //复位信号，高电平有效
play, //来自mcu的控制信号，高电平有效
song, //来自mcu的控制信号，当前播放歌曲的序号
note_done, //note_player的应答信号，表示一个音符播放结束并索取新音符
song_done, //给mcu的应答信号，当乐曲播放结束，输出一个时钟周期宽度的脉冲，表示乐曲播放结束
note, //音符标记
duration, //音符的持续时间
new_note //给模块note_p... | 7.825174 |
module song_reader_ctrl (
clk,
reset,
note_done,
play,
new_note
);
input clk, reset, note_done, play;
output reg new_note;
parameter RESET = 0, NEW_NOTE = 1, WAIT = 2, NEXT_NOTE = 3;
reg [1:0] state, nextstate;
//第一段-时序电路：D寄存器
always @(posedge clk) begin
if (reset) state = RESET;
... | 6.738957 |
module song_reader_tb_v;
parameter delay = 10;
// Inputs
reg clk;
reg reset;
reg play;
reg [1:0] song;
reg note_done;
// Outputs
wire song_done;
wire [5:0] note;
wire [5:0] duration;
wire new_note;
// Instantiate the Unit Under Test (UUT)
song_reader uut (
.clk(clk),
.reset(res... | 6.810514 |
module song_writer (
input clk,
input reset,
input [5:0] root,
input [7:0] switches,
input beat,
input [1:0] state,
input scale_button,
output [47:0] notes,
output finished_recording,
output start_recording,
output write_enable,
output [6:0] write_address,
output [15... | 7.179011 |
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