code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sonic #(
parameter WIDTH = 30
) (
input clk, // 5MHz
input echo, // Arduino D2
input [WIDTH-1:0] counter,
output reg trig, // Arduino D3
output reg [WIDTH-1:0] data
);
// set measure interval by parameter WIDTH
// reg echowrite;
reg [WIDTH-1:0] pulse_start;
reg echohigh;
alwa... | 6.656231 |
module sonic_detect (
clk_50m,
rst,
Trig,
Echo,
dis
);
input clk_50m, rst, Echo;
output Trig;
output [11:0] dis; // ?????????us
// Vcc--GPIO10
// Gnd--GPIO11
wire clk_1m;
//wire[19:0] d; // ??(??cm),5????,??????
Clk_1M c1 (
.outclk(clk_1m),
.inclk(clk_50m),
.rs... | 6.691201 |
module sonic_distance (
input av_mm_clk,
input av_mm_rst,
input av_mm_read,
input av_mm_cs,
output reg [31:0] av_mm_readdata,
input av_mm_address,
input sonic_echo,
output reg sonic_trigger
);
reg [21:0] co... | 7.493353 |
module sonic_rp_ep_sim_tb_sonic_rp_ep_sim_inst (
input wire reset_0_reset_n, // reset_0.reset_n
output wire [39:0] xcvr_tx_datain_data, // xcvr_tx_datain.data
input wire reset_reset_n, // reset.reset_n
input wire [39:0] xcvr_rx_dataout_data, // xcvr_r... | 6.649769 |
module sonic_test (
input CLOCK_50,
input [1:0] KEY,
input echo,
output trig,
output [3:0] LED,
output [15:0] LED2
);
parameter cycle = 20; // measure interval
wire clock;
wire [31:0] counter_out;
wire [31:0] sonic_out;
wire [7:0] debug;
pll pll (
CLOCK_50,
~KEY[1],
... | 6.847401 |
module simple_counter (
input CLOCK_50,
output reg [31:0] counter_out
);
always @(posedge CLOCK_50) begin
counter_out <= #1 counter_out + 1;
end
endmodule
| 7.044904 |
module Sonic_trig (
input clk,
output trig
);
reg [21:0] cnt_period;
always @(posedge clk) begin
if (cnt_period == 22'd1000000) cnt_period <= 0;
else cnt_period <= cnt_period + 1'b1;
end
assign trig = ((cnt_period >= 22'd100) & (cnt_period <= 22'd1100)) ? 1 : 0;
endmodule
| 7.468305 |
module sonic_vc_timing_adapter (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [127:0] in_data,
input in_error,
input in_st... | 7.130971 |
module sonic_vc_timing_adapter_fifo (
output reg [3:0] fill_level,
// Interface: clock
input clk,
input reset_n,
// Interface: data_in
output reg in_ready,
input in_valid,
input [132:0] in_data,
// Interface: data_out
input ... | 7.130971 |
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
assign out_sop = (c & d) | (~a & ~b & c);
assign out_pos = (c & d) | (~a & ~b & c);
endmodule
| 7.203305 |
module sopc (
input wire clk,
input wire rst
);
// connect with im
wire [`InstAddrBus] inst_addr;
wire [ `InstBus] inst;
wire rom_ce;
wire mem_we_i;
wire [ `RegBus] mem_addr_i;
wire [ `RegBus] mem_data_i;
wire [ `RegBus] mem_data_o;
wire [ ... | 6.595151 |
module sopc3_angle_barre (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [11:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [... | 7.245408 |
module sopc3 (
angle_barre_external_connection_export,
butee_d_external_connection_export,
butee_g_external_connection_export,
clk_clk,
duty_external_connection_export,
freq_external_connection_export,
sens_external_connection_export,
write_data_external_connection_export,
write_n_ex... | 7.047522 |
module sopc3_jtag_uart_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
w... | 6.532205 |
module sopc3_jtag_uart_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear;
... | 6.532205 |
module sopc3_jtag_uart_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [31:... | 6.532205 |
module sopc3_jtag_uart_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input ... | 6.532205 |
module sopc3_nios2_gen2_0_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire... | 6.625656 |
module sopc3_nios2_gen2_0_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire... | 6.625656 |
module sopc3_nios2_gen2_0_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
... | 6.625656 |
module sopc3_nios2_gen2_0_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [23:0] cpu_... | 6.625656 |
module sopc3_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
);
output [1:0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_input_tm_cnt;
wire [2:0] switch_... | 6.625656 |
module sopc3_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
);
output [3:0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [3:0] fifo_wrptr_inc;
always @(ge2_free or ge3_free or in... | 6.625656 |
module sopc3_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
);
output [4:0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [4:0] fifo_cnt_inc;
always @(empty or... | 6.625656 |
module sopc3_nios2_gen2_0_cpu_nios2_oci_pib (
// outputs:
tr_data
);
output [35:0] tr_data;
wire [35:0] tr_data;
assign tr_data = 0;
endmodule
| 6.625656 |
module sopc3_nios2_gen2_0_cpu_nios2_oci_im (
// inputs:
clk,
jrst_n,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
);
output tracemem_on;
output [35:0] tracemem_trcdata;
output tracemem_tw;
output... | 6.625656 |
module sopc3_nios2_gen2_0_cpu_nios2_performance_monitors;
endmodule
| 6.625656 |
module sopc3_nios2_gen2_0_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_a... | 6.625656 |
module sopc3_nios2_gen2_0_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input [7:0] address;
input [3:0] byteenable;
input clock;
input [31:0] data;
input res... | 6.625656 |
module sopc3_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "sopc3_onchip_memory2_0.hex";
output [31:0] readdata;
input [12:0] address;
in... | 6.830472 |
module sopc3_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1633678594 : 7;
endmodule
| 6.714812 |
module sopc_system_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "sopc_system_onchip_memory2_0.hex";
output [31:0] readdata;
input [12:0] address;
in... | 6.548865 |
module sopc_tb ();
reg clock, reset;
sopc sopc0 (
.clk(clock),
.rst(reset)
);
always #1 clock = ~clock;
initial begin
$dumpfile("dump.vcd");
$dumpvars;
$readmemh("rom.txt", sopc0.inst_rom0.inst_mem);
clock = 1'b0;
reset = 1'b1;
#20 reset = 1'b0;
#1000 $finish;
end... | 7.151695 |
module sopc_v3_angle_barre (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [11:0] in_port;
input reset_n;
wire clk_en;
wire [11:0] data_in;
wire [11:0] read_mux_out;
reg [31:0] re... | 7.363723 |
module sopc_v3 (
address_external_connection_export,
angle_barre_external_connection_export,
butee_d_external_connection_export,
butee_g_external_connection_export,
chip_select_external_connection_export,
clk_clk,
raz_external_connection_export,
duty_external_connection_export,
frequ... | 6.539165 |
module sopc_v3_jtag_uart_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
... | 6.585987 |
module sopc_v3_jtag_uart_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear;
... | 6.585987 |
module sopc_v3_jtag_uart_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [3... | 6.585987 |
module sopc_v3_jtag_uart_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
inpu... | 6.585987 |
module sopc_v3_nios2_gen2_0_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wi... | 6.74092 |
module sopc_v3_nios2_gen2_0_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wi... | 6.74092 |
module sopc_v3_nios2_gen2_0_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
... | 6.74092 |
module sopc_v3_nios2_gen2_0_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [17:0] cp... | 6.74092 |
module sopc_v3_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
);
output [1:0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_input_tm_cnt;
wire [2:0] switc... | 6.74092 |
module sopc_v3_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
);
output [3:0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [3:0] fifo_wrptr_inc;
always @(ge2_free or ge3_free or ... | 6.74092 |
module sopc_v3_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
);
output [4:0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [4:0] fifo_cnt_inc;
always @(empty ... | 6.74092 |
module sopc_v3_nios2_gen2_0_cpu_nios2_oci_pib (
// outputs:
tr_data
);
output [35:0] tr_data;
wire [35:0] tr_data;
assign tr_data = 0;
endmodule
| 6.74092 |
module sopc_v3_nios2_gen2_0_cpu_nios2_oci_im (
// inputs:
clk,
jrst_n,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
);
output tracemem_on;
output [35:0] tracemem_trcdata;
output tracemem_tw;
outp... | 6.74092 |
module sopc_v3_nios2_gen2_0_cpu_nios2_performance_monitors;
endmodule
| 6.74092 |
module sopc_v3_nios2_gen2_0_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take... | 6.74092 |
module sopc_v3_nios2_gen2_0_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input [7:0] address;
input [3:0] byteenable;
input clock;
input [31:0] data;
input r... | 6.74092 |
module sopc_v3_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "sopc_v3_onchip_memory2_0.hex";
output [31:0] readdata;
input [12:0] address;
... | 6.956997 |
module sopc_v3_onchip_memory2_1 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "sopc_v3_onchip_memory2_1.hex";
output [31:0] readdata;
input [12:0] address;
... | 6.956997 |
module sopc_v3_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1638528387 : 5639;
endmodul... | 6.93454 |
module SOPimplementationOfXNOR (
A,
B,
C,
f
);
input A, B, C;
output f;
wire notA, notB, notC;
not nota (notA, A);
not notb (notB, B);
not notc (notC, C);
wire Wm0, Wm3, Wm5, Wm6;
and m0 (Wm0, notA, notB, notC);
and m3 (Wm3, notA, B, C);
and m5 (Wm5, A, notB, C);
and m6 (Wm6, A, B,... | 6.984846 |
module SOPimplementationOfXNOR (
A,
B,
C,
f
);
input A, B, C;
output f;
wire notA, notB, notC;
not nota (notA, A);
not notb (notB, B);
not notc (notC, C);
wire Wm0, Wm3, Wm5, Wm6;
and m0 (Wm0, notA, notB, notC);
and m3 (Wm3, notA, B, C);
and m5 (Wm5, A, notB, C);
and m6 (Wm6, A, B,... | 6.984846 |
module sort2in1_tb
#(parameter W =`DATA_WIDTH )
(
);
reg clk;
reg rst_x;
wire synrst;
`include "init_dump.v... | 7.183861 |
module sort3 (
input clk,
input rst_n,
input [7:0] data1,
input [7:0] data2,
input [7:0] data3,
output reg [7:0] max_data,
output reg [7:0] mid_data,
output reg [7:0] min_data
);
//-----------------------------------
//ݽ
always @(posedge clk or negedge rst_n) begin
... | 6.775861 |
module: sort3
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sort3_test;
// Inputs
reg CLK;
reg nRST;
reg [7:0] node1;
reg [7:0] node2;
reg [7:0] node3;
// Outputs
wire [7... | 6.760612 |
module sort4 #(
parameter DATA_WIDTH = 8
) (
input wire reset,
input wire [DATA_WIDTH*4-1:0] data, // 四个无符号整数
output wire [DATA_WIDTH*4-1:0] dataout// 四个无符号整数, 排序完成后输出, 约定默认低字节输出最小值, 高字节输出最大值
);
localparam W = DATA_WIDTH;
wire [W-1:0] a, b, c, d;
wire [W-1:0] m, n;
wire [W*4-1:0] result;
//... | 7.75212 |
module sort4_sequence_test #(
parameter data_width = 3
) (
input wire clk,
output wire [data_width - 1 : 0] outp_inps,
output wire [data_width-1 : 0] outp,
output wire [data_width-1 : 0] max
);
reg subout;
reg [1:0] countin;
integer outfile;
initial begin
outfile = $fopen("output.txt",... | 7.14815 |
module inner_product_tb ();
// note this only runs for 50 cycles with the below settings
// alter TB_TIMEOUT to run longer
localparam TB_TIMEOUT = 100000;
localparam TB_CLK_PERIOD = 2000;
localparam TB_RST_PERIOD = 4000;
initial #(TB_TIMEOUT) $finish();
// clock
reg tb_clk = 1'b0;
always #(TB_CLK_P... | 6.900175 |
module SortElement #(
parameter DSIZE = 18,
parameter OFFSET = 8
) (
input [DSIZE-1:0] a,
input [DSIZE-1:0] b,
output wire [DSIZE-1:0] sort0,
output wire [DSIZE-1:0] sort1
);
assign sort0 = a[OFFSET-1:0] > b[OFFSET-1:0] ? b : a;
assign sort1 = a[OFFSET-1:0] > b[OFFSET-1:0] ? a ... | 6.834422 |
module sorter2 (
max,
min,
_1,
_2
);
// Parameters
parameter DATA_WIDTH = 8;
// Outputs
output wire [DATA_WIDTH - 1 : 0] min, max;
// Inputs
input wire [DATA_WIDTH - 1 : 0] _1, _2;
// Dataflow description on module
assign min = (_1 <= _2) ? _1 : _2;
assign max = (_1 > _2) ? _1 : _2;... | 7.803636 |
module sorter5 (
o1,
o2,
o3,
o4,
o5,
i1,
i2,
i3,
i4,
i5
);
// Parameters
parameter DATA_WIDTH = 8;
// Outputs
output wire [DATA_WIDTH - 1 : 0] o1, o2, o3, o4, o5;
// Inputs
input wire [DATA_WIDTH - 1 : 0] i1, i2, i3, i4, i5;
// Wires
wire [DATA_WIDTH - 1 : 0] _... | 6.536524 |
module sorter7 (
min,
med,
max,
_1,
_2,
_3,
_4,
_5,
_6,
_7
);
// Parameters
parameter DATA_WIDTH = 8;
// Outputs
output wire [DATA_WIDTH - 1 : 0] min, med, max;
// Inputs
input wire [DATA_WIDTH - 1 : 0] _1, _2, _3, _4, _5, _6, _7;
// Wires
wire [DATA_WIDTH - 1 ... | 6.576557 |
module sort4 (
i1,
i2,
i3,
i4,
o1,
o2,
o3,
o4
);
input [7:0] i1, i2, i3, i4;
output [7:0] o1, o2, o3, o4;
wire [7:0] m1, m2, m3, m4, w1, w2, w3, w4;
sorter_2 a41a (
i1,
i2,
m1,
w1
);
sorter_2 ar1a (
i3,
i4,
m2,
w2
);
sorter... | 7.071047 |
module compare_select #(
parameter LEN = 16
) (
input signed [LEN-1:0] a,
input signed [LEN-1:0] b,
output signed [LEN-1:0] out
);
reg signed [LEN-1:0] out_inner;
always @* begin
if (a > b) begin
out_inner = a;
end else begin
out_inner = b;
end
end
assign out = out_i... | 7.097953 |
module that sorts an array of signed numbers into descending order (ie location [0] has largest value)
Delay and Area optimal sorting networks up to length 8 from knuth's sorting and searching volume.
Plans to add up to length 16 delay optimal networks.
One compare/swap operation per pipeline layer.
*/
`include "2dA... | 7.026386 |
module
module s2 #
(
parameter TAG_WIDTH = 32,
parameter BLOCKLENGTH = 2,
parameter DATA_WIDTH = 8
)
(
input clk,
input reset,
input ready_in,
input valid_in,
input [TAG_WIDTH-1:0] tag_in,
input [DATA_WIDTH*BLOCKLENGTH-1:0] unsortedData_flat,
output busy,
output ready_out,
output valid_out,
output [TAG_... | 7.570872 |
module
module s3 #
(
parameter TAG_WIDTH = 32,
parameter BLOCKLENGTH = 3,
parameter DATA_WIDTH = 8
)
(
input clk,
input reset,
input ready_in,
input valid_in,
input [TAG_WIDTH-1:0] tag_in,
input [DATA_WIDTH*BLOCKLENGTH-1:0] unsortedData_flat,
output busy,
output ready_out,
output valid_out,
output [TAG_... | 7.864978 |
module
module s4 #
(
parameter TAG_WIDTH = 32,
parameter BLOCKLENGTH = 4,
parameter DATA_WIDTH = 8
)
(
input clk,
input reset,
input ready_in,
input valid_in,
input [TAG_WIDTH-1:0] tag_in,
input [DATA_WIDTH*BLOCKLENGTH-1:0] unsortedData_flat,
output busy,
output ready_out,
output valid_out,
output [TAG_... | 7.639542 |
module
module s5 #
(
parameter TAG_WIDTH = 32,
parameter BLOCKLENGTH = 5,
parameter DATA_WIDTH = 8
)
(
input clk,
input reset,
input ready_in,
input valid_in,
input [TAG_WIDTH-1:0] tag_in,
input [DATA_WIDTH*BLOCKLENGTH-1:0] unsortedData_flat,
output busy,
output ready_out,
output valid_out,
output [TAG_... | 7.459778 |
module
module s6 #
(
parameter TAG_WIDTH = 32,
parameter BLOCKLENGTH = 6,
parameter DATA_WIDTH = 8
)
(
input clk,
input reset,
input ready_in,
input valid_in,
input [TAG_WIDTH-1:0] tag_in,
input [DATA_WIDTH*BLOCKLENGTH-1:0] unsortedData_flat,
output busy,
output ready_out,
output valid_out,
output [TAG_... | 7.395648 |
module used to instantiate I/O pads and connect them with the block-level design
//----------------------------------------------------------------------
// Pads
//----------------------------------------------------------------------
// EN : If 1, DOUT writes to PAD, if 0, short from PAD to DIN
// DOUT ... | 8.144031 |
module SortX8 #(
parameter DSIZE = 18,
parameter OFFSET = 8
) (
input [DSIZE-1:0] a0,
input [DSIZE-1:0] a1,
input [DSIZE-1:0] a2,
input [DSIZE-1:0] a3,
input [DSIZE-1:0] a4,
input [DSIZE-1:0] a5,
input [DSIZE-1:0] a6,
input [DSIZE-... | 7.145854 |
module sorting_network_core (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
input [31:0] X0;
output [31:0] Y0;
input [31:0] X1;
output [31:0] Y1;
input [31:0] X2;
output [31:0] Y2;
input [31:0] X3;
output [31:0] Y3;
input clk, reset, nex... | 6.527226 |
module shiftRegFIFO (
X,
Y,
clk
);
parameter depth = 1, width = 1;
output [width-1:0] Y;
input [width-1:0] X;
input clk;
reg [width-1:0] mem [depth-1:0];
integer index;
assign Y = mem[depth-1];
always @(posedge clk) begin
for (index = 1; index < depth; index = index... | 7.124291 |
module memArray8_74211 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter d... | 6.541501 |
module memMod (
in,
out,
inAddr,
outAddr,
writeSel,
clk
);
parameter depth = 1024, width = 16, logDepth = 10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is ... | 7.262241 |
module memMod_dist (
in,
out,
inAddr,
outAddr,
writeSel,
clk
);
parameter depth = 1024, width = 16, logDepth = 10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of me... | 7.680291 |
module switch (
ctrl,
x0,
x1,
y0,
y1
);
parameter width = 16;
input [width-1:0] x0, x1;
output [width-1:0] y0, y1;
input ctrl;
assign y0 = (ctrl == 0) ? x0 : x1;
assign y1 = (ctrl == 0) ? x1 : x0;
endmodule
| 6.864438 |
module memArray8_74321 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter d... | 6.550756 |
module memArray16_74557 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter ... | 6.519031 |
module memArray16_74667 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter ... | 6.519031 |
module memArray8_75343 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter d... | 6.511056 |
module codeBlock75453 (
clk,
reset,
next_in,
next_out,
X0_in,
Y0,
X1_in,
Y1,
X2_in,
Y2,
X3_in,
Y3
);
output next_out;
input clk, reset, next_in;
reg next;
input [31:0] X0_in, X1_in, X2_in, X3_in;
reg [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
... | 6.520168 |
module nextReg (
X,
Y,
reset,
clk
);
parameter depth = 2, logDepth = 1;
output Y;
input X;
input clk, reset;
reg [logDepth:0] count;
reg active;
assign Y = (count == depth) ? 1 : 0;
always @(posedge clk) begin
if (reset == 1) begin
count <= 0;
active <= 0... | 6.59955 |
module memArray64_76475 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter ... | 6.57827 |
module memArray32_76585 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter ... | 6.793927 |
module memArray16_76695 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter ... | 6.660044 |
module memArray64_77371 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter ... | 6.583752 |
module memArray32_77481 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter ... | 6.578636 |
module memArray16_77591 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter ... | 6.589425 |
module codeBlock78160 (
clk,
reset,
next_in,
next_out,
X0_in,
Y0,
X1_in,
Y1,
X2_in,
Y2,
X3_in,
Y3
);
output next_out;
input clk, reset, next_in;
reg next;
input [31:0] X0_in, X1_in, X2_in, X3_in;
reg [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
... | 6.514076 |
module codeBlock78270 (
clk,
reset,
next_in,
next_out,
X0_in,
Y0,
X1_in,
Y1,
X2_in,
Y2,
X3_in,
Y3
);
output next_out;
input clk, reset, next_in;
reg next;
input [31:0] X0_in, X1_in, X2_in, X3_in;
reg [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
... | 6.531009 |
module memArray64_78377 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter ... | 6.702107 |
module codeBlock78380 (
clk,
reset,
next_in,
next_out,
X0_in,
Y0,
X1_in,
Y1,
X2_in,
Y2,
X3_in,
Y3
);
output next_out;
input clk, reset, next_in;
reg next;
input [31:0] X0_in, X1_in, X2_in, X3_in;
reg [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
... | 6.651457 |
module memArray16_78597 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter ... | 6.593133 |
module memArray64_79491 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter ... | 6.61286 |
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