code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sonic #(
parameter WIDTH = 30
) (
input clk, // 5MHz
input echo, // Arduino D2
input [WIDTH-1:0] counter,
output reg trig, // Arduino D3
output reg [WIDTH-1:0] data
);
// set measure interval by parameter WIDTH
// reg echowrite;
reg [WIDTH-1:0] pulse_start;
reg echohigh;
always @(posedge clk) begin
if (counter == 1) begin
trig <= 1;
end else if (counter == 50) begin
// echowrite <= 1;
trig <= 0;
end
if (echohigh == 0 && echo == 1) begin
pulse_start <= counter;
echohigh <= 1;
end else if (echohigh == 1 && echo == 0) begin
// echowrite <= 0;
echohigh <= 0;
data <= (counter - pulse_start);
end
end
endmodule
| 6.656231 |
module sonic_detect (
clk_50m,
rst,
Trig,
Echo,
dis
);
input clk_50m, rst, Echo;
output Trig;
output [11:0] dis; // ?????????us
// Vcc--GPIO10
// Gnd--GPIO11
wire clk_1m;
//wire[19:0] d; // ??(??cm),5????,??????
Clk_1M c1 (
.outclk(clk_1m),
.inclk(clk_50m),
.rst(rst)
); // 50??
TrigSignal t1 (
.clk_1m(clk_1m),
.rst(rst),
.trig(Trig)
);
PosCounter p1 (
.clk_1m(clk_1m),
.rst(rst),
.echo(Echo),
.dis_count(dis)
);
//assign Led =((d[19:16] < 1)&(d[15:12] < 1)) ? 1 : 0;
/*
translator u3(.in(d[19:16]), .out(distance[34:28])); // ????
translator u4(.in(d[15:12]), .out(distance[27:21]));
translator u5(.in(d[11:8]), .out(distance[20:14]));
translator u6(.in(d[7:4]), .out(distance[13:7]));
translator u7(.in(d[3:0]), .out(distance[6:0]));
assign d[19:16] = dis/10000; // ??
assign d[15:12] = dis/1000%10; // ??
assign d[11:8] = dis/100%10; // ??
assign d[7:4] = dis/10%10; // 0.1
assign d[3:0] = dis%10; // 0.01
*/
endmodule
| 6.691201 |
module sonic_distance (
input av_mm_clk,
input av_mm_rst,
input av_mm_read,
input av_mm_cs,
output reg [31:0] av_mm_readdata,
input av_mm_address,
input sonic_echo,
output reg sonic_trigger
);
reg [21:0] counter;
reg [21:0] measure_count;
reg [ 2:0] state;
reg [21:0] measure_value;
always @(posedge av_mm_clk or negedge av_mm_rst)
if (~av_mm_rst) counter <= 0;
else if (counter == 22'h3fffff) counter <= 0;
else counter <= counter + 1;
reg reg_echo;
always @(posedge av_mm_clk or negedge av_mm_rst)
if (~av_mm_rst) reg_echo <= 0;
else reg_echo <= sonic_echo;
reg [10:0] trig_count;
wire count_rst = (counter == 22'h3fffff) ? 0 : 1;
always @(posedge av_mm_clk or negedge count_rst)
if (~count_rst) begin
measure_count <= 0;
trig_count <= 0;
state <= 0;
end else begin
case (state)
3'd0: begin
sonic_trigger <= 1;
state <= 1;
end
3'd1: begin
if (trig_count == 2000) begin
sonic_trigger <= 0;
state <= 2;
end else begin
trig_count <= trig_count + 1;
state <= 1;
end
end
3'd2: begin
if (!reg_echo & sonic_echo) state <= 3;
else state <= 2;
end
3'd3: begin
if (reg_echo & !sonic_echo) state <= 4;
else begin
state <= 3;
measure_count <= measure_count + 1;
end
end
3'd4: begin
state <= state;
end
endcase
end
always @(posedge av_mm_clk or negedge av_mm_rst)
if (~av_mm_rst) measure_value <= 0;
else if (state == 3'd4) measure_value <= measure_count;
else measure_value <= measure_value;
always @(posedge av_mm_clk or negedge av_mm_rst)
if (~av_mm_rst) begin
av_mm_readdata <= 0;
end else begin
if (av_mm_cs && av_mm_read && av_mm_address == 0) av_mm_readdata <= {10'b0, measure_value};
end
endmodule
| 7.493353 |
module sonic_rp_ep_sim_tb_sonic_rp_ep_sim_inst (
input wire reset_0_reset_n, // reset_0.reset_n
output wire [39:0] xcvr_tx_datain_data, // xcvr_tx_datain.data
input wire reset_reset_n, // reset.reset_n
input wire [39:0] xcvr_rx_dataout_data, // xcvr_rx_dataout.data
input wire clk_clk, // clk.clk
input wire clk_0_clk // clk_0.clk
);
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> sonic_rp_ep_top_0:rstn
sonic_fast_sim_top sonic_rp_ep_top_0 (
.pld_clk (clk_clk), // pld_clk.clk
.rstn (~rst_controller_reset_out_reset), // rstn.reset_n
.xcvr_rx_clkout (clk_0_clk), // rx_clkout.clk
.xcvr_tx_clkout (clk_0_clk), // tx_clkout.clk
.xcvr_tx_datain (xcvr_tx_datain_data), // tx_datain.data
.xcvr_rx_dataout(xcvr_rx_dataout_data) // rx_dataout.data
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES("deassert"),
.SYNC_DEPTH (2)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10(1'b0), // (terminated)
.reset_in11(1'b0), // (terminated)
.reset_in12(1'b0), // (terminated)
.reset_in13(1'b0), // (terminated)
.reset_in14(1'b0), // (terminated)
.reset_in15(1'b0) // (terminated)
);
endmodule
| 6.649769 |
module sonic_test (
input CLOCK_50,
input [1:0] KEY,
input echo,
output trig,
output [3:0] LED,
output [15:0] LED2
);
parameter cycle = 20; // measure interval
wire clock;
wire [31:0] counter_out;
wire [31:0] sonic_out;
wire [7:0] debug;
pll pll (
CLOCK_50,
~KEY[1],
clock
);
simple_counter counter (
clock,
counter_out
);
sonic #(cycle) sc (
clock,
echo,
counter_out[cycle-1:0],
trig,
sonic_out[cycle-1:0]
);
// assign LED = KEY[0] ? counter_out[26:23] : counter_out[24:21];
// assign LED = debug;
assign LED2 = KEY[0] ? sonic_out[15:0] : sonic_out[31:16];
endmodule
| 6.847401 |
module simple_counter (
input CLOCK_50,
output reg [31:0] counter_out
);
always @(posedge CLOCK_50) begin
counter_out <= #1 counter_out + 1;
end
endmodule
| 7.044904 |
module Sonic_trig (
input clk,
output trig
);
reg [21:0] cnt_period;
always @(posedge clk) begin
if (cnt_period == 22'd1000000) cnt_period <= 0;
else cnt_period <= cnt_period + 1'b1;
end
assign trig = ((cnt_period >= 22'd100) & (cnt_period <= 22'd1100)) ? 1 : 0;
endmodule
| 7.468305 |
module sonic_vc_timing_adapter (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [127:0] in_data,
input in_error,
input in_startofpacket,
input in_endofpacket,
input [ 1:0] in_empty,
// Interface: out
input out_ready,
output reg out_valid,
output reg [127:0] out_data,
output reg out_error,
output reg out_startofpacket,
output reg out_endofpacket,
output reg [ 1:0] out_empty
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg [132:0] in_payload;
wire [132:0] out_payload;
wire in_ready_wire;
wire out_valid_wire;
wire [ 3:0] fifo_fill;
reg [ 0:0] ready;
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_payload = {in_data, in_error, in_startofpacket, in_endofpacket, in_empty};
{out_data, out_error, out_startofpacket, out_endofpacket, out_empty} = out_payload;
end
// ---------------------------------------------------------------------
//| FIFO
// ---------------------------------------------------------------------
sonic_vc_timing_adapter_fifo sonic_vc_timing_adapter_fifo (
.clk (clk),
.reset_n (reset_n),
.in_ready (),
.in_valid (in_valid),
.in_data (in_payload),
.out_ready (ready[0]),
.out_valid (out_valid_wire),
.out_data (out_payload),
.fill_level(fifo_fill)
);
// ---------------------------------------------------------------------
//| Ready & valid signals.
// ---------------------------------------------------------------------
always @* begin
in_ready = (fifo_fill < 4);
out_valid = out_valid_wire;
ready[0] = out_ready;
end
endmodule
| 7.130971 |
module sonic_vc_timing_adapter_fifo (
output reg [3:0] fill_level,
// Interface: clock
input clk,
input reset_n,
// Interface: data_in
output reg in_ready,
input in_valid,
input [132:0] in_data,
// Interface: data_out
input out_ready,
output reg out_valid,
output reg [132:0] out_data
);
// ---------------------------------------------------------------------
//| Internal Parameters
// ---------------------------------------------------------------------
parameter DEPTH = 8;
parameter DATA_WIDTH = 133;
parameter ADDR_WIDTH = 3;
// ---------------------------------------------------------------------
//| Signals
// ---------------------------------------------------------------------
reg [ADDR_WIDTH-1:0] wr_addr;
reg [ADDR_WIDTH-1:0] rd_addr;
reg [ADDR_WIDTH-1:0] next_wr_addr;
reg [ADDR_WIDTH-1:0] next_rd_addr;
reg [ADDR_WIDTH-1:0] mem_rd_addr;
reg [DATA_WIDTH-1:0] mem[DEPTH-1:0];
reg empty;
reg full;
reg [0:0] out_ready_vector;
// ---------------------------------------------------------------------
//| FIFO Status
// ---------------------------------------------------------------------
always @* begin
// out_valid = !empty;
out_ready_vector[0] = out_ready;
in_ready = !full;
next_wr_addr = wr_addr + 1'b1;
next_rd_addr = rd_addr + 1'b1;
fill_level[ADDR_WIDTH-1:0] = wr_addr - rd_addr;
fill_level[ADDR_WIDTH] = 0;
if (full) fill_level = DEPTH[ADDR_WIDTH:0];
end
// ---------------------------------------------------------------------
//| Manage Pointers
// ---------------------------------------------------------------------
always @(negedge reset_n, posedge clk) begin
if (!reset_n) begin
wr_addr <= 0;
rd_addr <= 0;
empty <= 1;
rd_addr <= 0;
full <= 0;
out_valid <= 0;
end else begin
out_valid <= !empty;
if (in_ready && in_valid) begin
wr_addr <= next_wr_addr;
empty <= 0;
if (next_wr_addr == rd_addr) full <= 1;
end
if (out_ready_vector[0] && out_valid) begin
rd_addr <= next_rd_addr;
full <= 0;
if (next_rd_addr == wr_addr) begin
empty <= 1;
out_valid <= 0;
end
end
if (out_ready_vector[0] && out_valid && in_ready && in_valid) begin
full <= full;
empty <= empty;
end
end
end // always @ (negedge reset_n, posedge clk)
always @* begin
mem_rd_addr = rd_addr;
if (out_ready && out_valid) begin
mem_rd_addr = next_rd_addr;
end
end
// ---------------------------------------------------------------------
//| Infer Memory
// ---------------------------------------------------------------------
always @(posedge clk) begin
if (in_ready && in_valid) mem[wr_addr] <= in_data;
out_data <= mem[mem_rd_addr];
end
endmodule
| 7.130971 |
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
assign out_sop = (c & d) | (~a & ~b & c);
assign out_pos = (c & d) | (~a & ~b & c);
endmodule
| 7.203305 |
module sopc (
input wire clk,
input wire rst
);
// connect with im
wire [`InstAddrBus] inst_addr;
wire [ `InstBus] inst;
wire rom_ce;
wire mem_we_i;
wire [ `RegBus] mem_addr_i;
wire [ `RegBus] mem_data_i;
wire [ `RegBus] mem_data_o;
wire [ 3:0] mem_sel_i;
wire mem_ce_i;
wire [ 5:0] interrupt;
wire timer_interrupt;
assign interrupt = {5'b00000, timer_interrupt};
cpu_path cpu_path0 (
.clk(clk),
.rst(rst),
.rom_addr_o(inst_addr),
.rom_data_i(inst),
.rom_ce_o (rom_ce),
.interrupt_i(interrupt),
.ram_we_o (mem_we_i),
.ram_addr_o(mem_addr_i),
.ram_sel_o (mem_sel_i),
.ram_data_o(mem_data_i),
.ram_data_i(mem_data_o),
.ram_ce_o (mem_ce_i),
.timer_interrupt_o(timer_interrupt)
);
inst_rom inst_rom0 (
.ce (rom_ce),
.addr(inst_addr),
.inst(inst)
);
data_ram data_ram0 (
.clk(clk),
.we(mem_we_i),
.addr(mem_addr_i),
.sel(mem_sel_i),
.data_i(mem_data_i),
.data_o(mem_data_o),
.ce(mem_ce_i)
);
endmodule
| 6.595151 |
module sopc3_angle_barre (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [11:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:0] writedata;
wire clk_en;
reg [11:0] data_out;
wire [11:0] out_port;
wire [11:0] read_mux_out;
wire [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {12{(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else if (chipselect && ~write_n && (address == 0)) data_out <= writedata[11 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
| 7.245408 |
module sopc3 (
angle_barre_external_connection_export,
butee_d_external_connection_export,
butee_g_external_connection_export,
clk_clk,
duty_external_connection_export,
freq_external_connection_export,
sens_external_connection_export,
write_data_external_connection_export,
write_n_external_connection_export
);
output [11:0] angle_barre_external_connection_export;
output [11:0] butee_d_external_connection_export;
output [11:0] butee_g_external_connection_export;
input clk_clk;
output [15:0] duty_external_connection_export;
output [15:0] freq_external_connection_export;
output sens_external_connection_export;
input [7:0] write_data_external_connection_export;
input write_n_external_connection_export;
endmodule
| 7.047522 |
module sopc3_jtag_uart_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [7:0] r_dat;
wire wfifo_empty;
wire [5:0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk) begin
if (fifo_wr) $write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 6.532205 |
module sopc3_jtag_uart_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear;
input [7:0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [7:0] r_dat;
wire wfifo_empty;
wire [5:0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
sopc3_jtag_uart_0_sim_scfifo_w the_sopc3_jtag_uart_0_sim_scfifo_w (
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty(wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 6.532205 |
module sopc3_jtag_uart_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [31:0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7:0] fifo_rdata;
wire new_rom;
wire [31:0] num_bytes;
wire [ 6:0] rfifo_entries;
wire rfifo_full;
wire [ 5:0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n) begin
if (rst_n == 0) begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end else begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d) bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom) bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 6.532205 |
module sopc3_jtag_uart_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [7:0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [7:0] fifo_rdata;
wire rfifo_full;
wire [5:0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
sopc3_jtag_uart_0_sim_scfifo_r the_sopc3_jtag_uart_0_sim_scfifo_r (
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata(fifo_rdata),
.rfifo_full(rfifo_full),
.rfifo_used(rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 6.532205 |
module sopc3_nios2_gen2_0_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire [31:0] q;
wire [31:0] ram_data;
wire [31:0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram (
.address_a(wraddress),
.address_b(rdaddress),
.clock0(clock),
.data_a(ram_data),
.q_b(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0", the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0, the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32, the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32, the_altsyncram.widthad_a = 5, the_altsyncram.widthad_b = 5;
endmodule
| 6.625656 |
module sopc3_nios2_gen2_0_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire [31:0] q;
wire [31:0] ram_data;
wire [31:0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram (
.address_a(wraddress),
.address_b(rdaddress),
.clock0(clock),
.data_a(ram_data),
.q_b(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0", the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0, the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32, the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32, the_altsyncram.widthad_a = 5, the_altsyncram.widthad_b = 5;
endmodule
| 6.625656 |
module sopc3_nios2_gen2_0_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
3'b000: begin
td_mode = 4'b0000;
end // 3'b000
3'b001: begin
td_mode = 4'b1000;
end // 3'b001
3'b010: begin
td_mode = 4'b0100;
end // 3'b010
3'b011: begin
td_mode = 4'b1100;
end // 3'b011
3'b100: begin
td_mode = 4'b0010;
end // 3'b100
3'b101: begin
td_mode = 4'b1010;
end // 3'b101
3'b110: begin
td_mode = 4'b0101;
end // 3'b110
3'b111: begin
td_mode = 4'b1111;
end // 3'b111
endcase // ctrl_bits_for_mux
end
endmodule
| 6.625656 |
module sopc3_nios2_gen2_0_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [23:0] cpu_d_address;
input cpu_d_read;
input [31:0] cpu_d_readdata;
input cpu_d_wait;
input cpu_d_write;
input [31:0] cpu_d_writedata;
input jrst_n;
input [15:0] trc_ctrl;
reg [35:0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [31:0] cpu_d_address_0_padded;
wire [31:0] cpu_d_readdata_0_padded;
wire [31:0] cpu_d_writedata_0_padded;
reg [35:0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dummy_tie_off;
wire record_load_addr;
wire record_load_data;
wire record_store_addr;
wire record_store_data;
wire [ 3:0] td_mode_trc_ctrl;
assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
//sopc3_nios2_gen2_0_cpu_nios2_oci_trc_ctrl_td_mode, which is an e_instance
sopc3_nios2_gen2_0_cpu_nios2_oci_td_mode sopc3_nios2_gen2_0_cpu_nios2_oci_trc_ctrl_td_mode (
.ctrl (trc_ctrl[8 : 0]),
.td_mode(td_mode_trc_ctrl)
);
assign {record_load_addr, record_store_addr,
record_load_data, record_store_data} = td_mode_trc_ctrl;
always @(posedge clk or negedge jrst_n) begin
if (jrst_n == 0) begin
atm <= 0;
dtm <= 0;
end else begin
atm <= 0;
dtm <= 0;
end
end
assign dummy_tie_off = cpu_d_wait | cpu_d_read | cpu_d_write;
endmodule
| 6.625656 |
module sopc3_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
);
output [1:0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_input_tm_cnt;
wire [2:0] switch_for_mux;
assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
always @(switch_for_mux) begin
case (switch_for_mux)
3'b000: begin
compute_input_tm_cnt = 0;
end // 3'b000
3'b001: begin
compute_input_tm_cnt = 1;
end // 3'b001
3'b010: begin
compute_input_tm_cnt = 1;
end // 3'b010
3'b011: begin
compute_input_tm_cnt = 2;
end // 3'b011
3'b100: begin
compute_input_tm_cnt = 1;
end // 3'b100
3'b101: begin
compute_input_tm_cnt = 2;
end // 3'b101
3'b110: begin
compute_input_tm_cnt = 2;
end // 3'b110
3'b111: begin
compute_input_tm_cnt = 3;
end // 3'b111
endcase // switch_for_mux
end
endmodule
| 6.625656 |
module sopc3_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
);
output [3:0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [3:0] fifo_wrptr_inc;
always @(ge2_free or ge3_free or input_tm_cnt) begin
if (ge3_free & (input_tm_cnt == 3)) fifo_wrptr_inc = 3;
else if (ge2_free & (input_tm_cnt >= 2)) fifo_wrptr_inc = 2;
else if (input_tm_cnt >= 1) fifo_wrptr_inc = 1;
else fifo_wrptr_inc = 0;
end
endmodule
| 6.625656 |
module sopc3_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
);
output [4:0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [4:0] fifo_cnt_inc;
always @(empty or ge2_free or ge3_free or input_tm_cnt) begin
if (empty) fifo_cnt_inc = input_tm_cnt[1 : 0];
else if (ge3_free & (input_tm_cnt == 3)) fifo_cnt_inc = 2;
else if (ge2_free & (input_tm_cnt >= 2)) fifo_cnt_inc = 1;
else if (input_tm_cnt >= 1) fifo_cnt_inc = 0;
else fifo_cnt_inc = {5{1'b1}};
end
endmodule
| 6.625656 |
module sopc3_nios2_gen2_0_cpu_nios2_oci_pib (
// outputs:
tr_data
);
output [35:0] tr_data;
wire [35:0] tr_data;
assign tr_data = 0;
endmodule
| 6.625656 |
module sopc3_nios2_gen2_0_cpu_nios2_oci_im (
// inputs:
clk,
jrst_n,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
);
output tracemem_on;
output [35:0] tracemem_trcdata;
output tracemem_tw;
output [6:0] trc_im_addr;
output trc_wrap;
output xbrk_wrap_traceoff;
input clk;
input jrst_n;
input [15:0] trc_ctrl;
input [35:0] tw;
wire tracemem_on;
wire [35:0] tracemem_trcdata;
wire tracemem_tw;
reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [35:0] trc_im_data;
wire trc_on_chip;
reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire tw_valid;
wire xbrk_wrap_traceoff;
assign trc_im_data = tw;
always @(posedge clk or negedge jrst_n) begin
if (jrst_n == 0) begin
trc_im_addr <= 0;
trc_wrap <= 0;
end else begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
end
assign trc_on_chip = ~trc_ctrl[8];
assign tw_valid = |trc_im_data[35 : 32];
assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
assign tracemem_trcdata = 0;
endmodule
| 6.625656 |
module sopc3_nios2_gen2_0_cpu_nios2_performance_monitors;
endmodule
| 6.625656 |
module sopc3_nios2_gen2_0_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
);
output [31:0] oci_ienable;
output [31:0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [8:0] address;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [31:0] writedata;
reg [31:0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [31:0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) oci_single_step_mode <= 1'b0;
else if (take_action_ocireg) oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) oci_ienable <= 32'b00000000000000010000000000000000;
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000010000000000000000);
end
endmodule
| 6.625656 |
module sopc3_nios2_gen2_0_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input [7:0] address;
input [3:0] byteenable;
input clock;
input [31:0] data;
input reset_req;
input wren;
wire clocken;
wire [31:0] q;
wire [31:0] ram_q;
assign q = ram_q;
assign clocken = ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clock),
.clocken0(clocken),
.data_a(data),
.q_a(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.init_file = lpm_file, the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 256, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 8;
endmodule
| 6.625656 |
module sopc3_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "sopc3_onchip_memory2_0.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input freeze;
input reset;
input reset_req;
input write;
input [31:0] writedata;
wire clocken0;
wire [31:0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clk),
.clocken0(clocken0),
.data_a(writedata),
.q_a(readdata),
.wren_a(wren)
);
defparam the_altsyncram.byte_size = 8, the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram", the_altsyncram.maximum_depth = 5000,
the_altsyncram.numwords_a = 5000, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 13;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
| 6.830472 |
module sopc3_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1633678594 : 7;
endmodule
| 6.714812 |
module sopc_system_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "sopc_system_onchip_memory2_0.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [31:0] writedata;
wire clocken0;
wire [31:0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clk),
.clocken0(clocken0),
.data_a(writedata),
.q_a(readdata),
.wren_a(wren)
);
defparam the_altsyncram.byte_size = 8, the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram", the_altsyncram.maximum_depth = 8192,
the_altsyncram.numwords_a = 8192, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 13;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
| 6.548865 |
module sopc_tb ();
reg clock, reset;
sopc sopc0 (
.clk(clock),
.rst(reset)
);
always #1 clock = ~clock;
initial begin
$dumpfile("dump.vcd");
$dumpvars;
$readmemh("rom.txt", sopc0.inst_rom0.inst_mem);
clock = 1'b0;
reset = 1'b1;
#20 reset = 1'b0;
#1000 $finish;
end
endmodule
| 7.151695 |
module sopc_v3_angle_barre (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [11:0] in_port;
input reset_n;
wire clk_en;
wire [11:0] data_in;
wire [11:0] read_mux_out;
reg [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {12{(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) readdata <= 0;
else if (clk_en) readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
| 7.363723 |
module sopc_v3 (
address_external_connection_export,
angle_barre_external_connection_export,
butee_d_external_connection_export,
butee_g_external_connection_export,
chip_select_external_connection_export,
clk_clk,
raz_external_connection_export,
duty_external_connection_export,
frequency_external_connection_export,
read_data_external_connection_export,
sens_external_connection_export,
write_data_external_connection_export,
write_n_external_connection_export,
enable_external_connection_export,
fin_butee_external_connection_export
);
input [2:0] address_external_connection_export;
input [11:0] angle_barre_external_connection_export;
output [11:0] butee_d_external_connection_export;
output [11:0] butee_g_external_connection_export;
input chip_select_external_connection_export;
input clk_clk;
output raz_external_connection_export;
output [15:0] duty_external_connection_export;
output [15:0] frequency_external_connection_export;
output [31:0] read_data_external_connection_export;
output sens_external_connection_export;
input [31:0] write_data_external_connection_export;
input write_n_external_connection_export;
output enable_external_connection_export;
output [1:0] fin_butee_external_connection_export;
endmodule
| 6.539165 |
module sopc_v3_jtag_uart_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [7:0] r_dat;
wire wfifo_empty;
wire [5:0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk) begin
if (fifo_wr) $write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 6.585987 |
module sopc_v3_jtag_uart_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear;
input [7:0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [7:0] r_dat;
wire wfifo_empty;
wire [5:0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
sopc_v3_jtag_uart_0_sim_scfifo_w the_sopc_v3_jtag_uart_0_sim_scfifo_w (
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty(wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 6.585987 |
module sopc_v3_jtag_uart_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [31:0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7:0] fifo_rdata;
wire new_rom;
wire [31:0] num_bytes;
wire [ 6:0] rfifo_entries;
wire rfifo_full;
wire [ 5:0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n) begin
if (rst_n == 0) begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end else begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d) bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom) bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 6.585987 |
module sopc_v3_jtag_uart_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [7:0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [7:0] fifo_rdata;
wire rfifo_full;
wire [5:0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
sopc_v3_jtag_uart_0_sim_scfifo_r the_sopc_v3_jtag_uart_0_sim_scfifo_r (
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata(fifo_rdata),
.rfifo_full(rfifo_full),
.rfifo_used(rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 6.585987 |
module sopc_v3_nios2_gen2_0_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire [31:0] q;
wire [31:0] ram_data;
wire [31:0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram (
.address_a(wraddress),
.address_b(rdaddress),
.clock0(clock),
.data_a(ram_data),
.q_b(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0", the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0, the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32, the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32, the_altsyncram.widthad_a = 5, the_altsyncram.widthad_b = 5;
endmodule
| 6.74092 |
module sopc_v3_nios2_gen2_0_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire [31:0] q;
wire [31:0] ram_data;
wire [31:0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram (
.address_a(wraddress),
.address_b(rdaddress),
.clock0(clock),
.data_a(ram_data),
.q_b(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0", the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0, the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32, the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32, the_altsyncram.widthad_a = 5, the_altsyncram.widthad_b = 5;
endmodule
| 6.74092 |
module sopc_v3_nios2_gen2_0_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
3'b000: begin
td_mode = 4'b0000;
end // 3'b000
3'b001: begin
td_mode = 4'b1000;
end // 3'b001
3'b010: begin
td_mode = 4'b0100;
end // 3'b010
3'b011: begin
td_mode = 4'b1100;
end // 3'b011
3'b100: begin
td_mode = 4'b0010;
end // 3'b100
3'b101: begin
td_mode = 4'b1010;
end // 3'b101
3'b110: begin
td_mode = 4'b0101;
end // 3'b110
3'b111: begin
td_mode = 4'b1111;
end // 3'b111
endcase // ctrl_bits_for_mux
end
endmodule
| 6.74092 |
module sopc_v3_nios2_gen2_0_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [17:0] cpu_d_address;
input cpu_d_read;
input [31:0] cpu_d_readdata;
input cpu_d_wait;
input cpu_d_write;
input [31:0] cpu_d_writedata;
input jrst_n;
input [15:0] trc_ctrl;
reg [35:0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [31:0] cpu_d_address_0_padded;
wire [31:0] cpu_d_readdata_0_padded;
wire [31:0] cpu_d_writedata_0_padded;
reg [35:0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dummy_tie_off;
wire record_load_addr;
wire record_load_data;
wire record_store_addr;
wire record_store_data;
wire [ 3:0] td_mode_trc_ctrl;
assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
//sopc_v3_nios2_gen2_0_cpu_nios2_oci_trc_ctrl_td_mode, which is an e_instance
sopc_v3_nios2_gen2_0_cpu_nios2_oci_td_mode sopc_v3_nios2_gen2_0_cpu_nios2_oci_trc_ctrl_td_mode (
.ctrl (trc_ctrl[8 : 0]),
.td_mode(td_mode_trc_ctrl)
);
assign {record_load_addr, record_store_addr,
record_load_data, record_store_data} = td_mode_trc_ctrl;
always @(posedge clk or negedge jrst_n) begin
if (jrst_n == 0) begin
atm <= 0;
dtm <= 0;
end else begin
atm <= 0;
dtm <= 0;
end
end
assign dummy_tie_off = cpu_d_wait | cpu_d_read | cpu_d_write;
endmodule
| 6.74092 |
module sopc_v3_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
);
output [1:0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_input_tm_cnt;
wire [2:0] switch_for_mux;
assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
always @(switch_for_mux) begin
case (switch_for_mux)
3'b000: begin
compute_input_tm_cnt = 0;
end // 3'b000
3'b001: begin
compute_input_tm_cnt = 1;
end // 3'b001
3'b010: begin
compute_input_tm_cnt = 1;
end // 3'b010
3'b011: begin
compute_input_tm_cnt = 2;
end // 3'b011
3'b100: begin
compute_input_tm_cnt = 1;
end // 3'b100
3'b101: begin
compute_input_tm_cnt = 2;
end // 3'b101
3'b110: begin
compute_input_tm_cnt = 2;
end // 3'b110
3'b111: begin
compute_input_tm_cnt = 3;
end // 3'b111
endcase // switch_for_mux
end
endmodule
| 6.74092 |
module sopc_v3_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
);
output [3:0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [3:0] fifo_wrptr_inc;
always @(ge2_free or ge3_free or input_tm_cnt) begin
if (ge3_free & (input_tm_cnt == 3)) fifo_wrptr_inc = 3;
else if (ge2_free & (input_tm_cnt >= 2)) fifo_wrptr_inc = 2;
else if (input_tm_cnt >= 1) fifo_wrptr_inc = 1;
else fifo_wrptr_inc = 0;
end
endmodule
| 6.74092 |
module sopc_v3_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
);
output [4:0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [4:0] fifo_cnt_inc;
always @(empty or ge2_free or ge3_free or input_tm_cnt) begin
if (empty) fifo_cnt_inc = input_tm_cnt[1 : 0];
else if (ge3_free & (input_tm_cnt == 3)) fifo_cnt_inc = 2;
else if (ge2_free & (input_tm_cnt >= 2)) fifo_cnt_inc = 1;
else if (input_tm_cnt >= 1) fifo_cnt_inc = 0;
else fifo_cnt_inc = {5{1'b1}};
end
endmodule
| 6.74092 |
module sopc_v3_nios2_gen2_0_cpu_nios2_oci_pib (
// outputs:
tr_data
);
output [35:0] tr_data;
wire [35:0] tr_data;
assign tr_data = 0;
endmodule
| 6.74092 |
module sopc_v3_nios2_gen2_0_cpu_nios2_oci_im (
// inputs:
clk,
jrst_n,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
);
output tracemem_on;
output [35:0] tracemem_trcdata;
output tracemem_tw;
output [6:0] trc_im_addr;
output trc_wrap;
output xbrk_wrap_traceoff;
input clk;
input jrst_n;
input [15:0] trc_ctrl;
input [35:0] tw;
wire tracemem_on;
wire [35:0] tracemem_trcdata;
wire tracemem_tw;
reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [35:0] trc_im_data;
wire trc_on_chip;
reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire tw_valid;
wire xbrk_wrap_traceoff;
assign trc_im_data = tw;
always @(posedge clk or negedge jrst_n) begin
if (jrst_n == 0) begin
trc_im_addr <= 0;
trc_wrap <= 0;
end else begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
end
assign trc_on_chip = ~trc_ctrl[8];
assign tw_valid = |trc_im_data[35 : 32];
assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
assign tracemem_trcdata = 0;
endmodule
| 6.74092 |
module sopc_v3_nios2_gen2_0_cpu_nios2_performance_monitors;
endmodule
| 6.74092 |
module sopc_v3_nios2_gen2_0_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
);
output [31:0] oci_ienable;
output [31:0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [8:0] address;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [31:0] writedata;
reg [31:0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [31:0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) oci_single_step_mode <= 1'b0;
else if (take_action_ocireg) oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) oci_ienable <= 32'b00000000000000000000000000000001;
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000000000000000000001);
end
endmodule
| 6.74092 |
module sopc_v3_nios2_gen2_0_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input [7:0] address;
input [3:0] byteenable;
input clock;
input [31:0] data;
input reset_req;
input wren;
wire clocken;
wire [31:0] q;
wire [31:0] ram_q;
assign q = ram_q;
assign clocken = ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clock),
.clocken0(clocken),
.data_a(data),
.q_a(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.init_file = lpm_file, the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 256, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 8;
endmodule
| 6.74092 |
module sopc_v3_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "sopc_v3_onchip_memory2_0.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input freeze;
input reset;
input reset_req;
input write;
input [31:0] writedata;
wire clocken0;
wire [31:0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clk),
.clocken0(clocken0),
.data_a(writedata),
.q_a(readdata),
.wren_a(wren)
);
defparam the_altsyncram.byte_size = 8, the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram", the_altsyncram.maximum_depth = 5000,
the_altsyncram.numwords_a = 5000, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 13;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
| 6.956997 |
module sopc_v3_onchip_memory2_1 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "sopc_v3_onchip_memory2_1.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input freeze;
input reset;
input reset_req;
input write;
input [31:0] writedata;
wire clocken0;
wire [31:0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clk),
.clocken0(clocken0),
.data_a(writedata),
.q_a(readdata),
.wren_a(wren)
);
defparam the_altsyncram.byte_size = 8, the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram", the_altsyncram.maximum_depth = 5000,
the_altsyncram.numwords_a = 5000, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 13;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
| 6.956997 |
module sopc_v3_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1638528387 : 5639;
endmodule
| 6.93454 |
module SOPimplementationOfXNOR (
A,
B,
C,
f
);
input A, B, C;
output f;
wire notA, notB, notC;
not nota (notA, A);
not notb (notB, B);
not notc (notC, C);
wire Wm0, Wm3, Wm5, Wm6;
and m0 (Wm0, notA, notB, notC);
and m3 (Wm3, notA, B, C);
and m5 (Wm5, A, notB, C);
and m6 (Wm6, A, B, notC);
or (f, m0, m3, m5, m6);
endmodule
| 6.984846 |
module SOPimplementationOfXNOR (
A,
B,
C,
f
);
input A, B, C;
output f;
wire notA, notB, notC;
not nota (notA, A);
not notb (notB, B);
not notc (notC, C);
wire Wm0, Wm3, Wm5, Wm6;
and m0 (Wm0, notA, notB, notC);
and m3 (Wm3, notA, B, C);
and m5 (Wm5, A, notB, C);
and m6 (Wm6, A, B, notC);
or (f, Wm0, Wm3, Wm5, Wm6);
endmodule
| 6.984846 |
module sort2in1_tb
#(parameter W =`DATA_WIDTH )
(
);
reg clk;
reg rst_x;
wire synrst;
`include "init_dump.v"
system_init system_init();
initial
begin
force clk = system_init.masterclock;
force rst_x = system_init.rst_all ;
end
assign synrst = system_init.syn_rst;
wire [`DATA_WIDTH-1:0] Data_in;
wire clkDiv160;
tb_clock_div #( 2) U_clkDiv160 ( .clk_in(clk),.rst(synrst), .clk_out(clkDiv160) ); // clkDiv160 should be used in read_enable_signal
//read_enable_signal #(`DATA_WIDTH,`DATA_FILE,`DISPLAY_OK) U_data_in(.clk(clk),.enable(rst_x),.signal_out(Data_in));
read_signal #(`DATA_WIDTH,`DATA_FILE,`DISPLAY_OK) U_data_in(.clk(clk),.signal_out(Data_in));
wire DataEn;
wire [W-1:0] DataIn;
wire [W-1:0] DataMax;
wire [W+3:0] DataSumOut;
assign DataEn=1;
assign DataIn=Data_in;
sort2in1 #(.W(12))U_sort2in1
(
.clk (clk ),
.synrst (synrst ),
.DataEn (DataEn ),
.DataIn (DataIn ),
.DataMax (DataMax ),
.DataSumOut (DataSumOut )
);
endmodule
| 7.183861 |
module sort3 (
input clk,
input rst_n,
input [7:0] data1,
input [7:0] data2,
input [7:0] data3,
output reg [7:0] max_data,
output reg [7:0] mid_data,
output reg [7:0] min_data
);
//-----------------------------------
//ݽ
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
max_data <= 0;
mid_data <= 0;
min_data <= 0;
end else begin
//ȡֵ
if (data1 >= data2 && data1 >= data3) max_data <= data1;
else if (data2 >= data1 && data2 >= data3) max_data <= data2;
else //(data3 >= data1 && data3 >= data2)
max_data <= data3;
//ȡֵ
if ((data1 >= data2 && data1 <= data3) || (data1 >= data3 && data1 <= data2))
mid_data <= data1;
else if ((data2 >= data1 && data2 <= data3) || (data2 >= data3 && data2 <= data1))
mid_data <= data2;
else //((data3 >= data1 && data3 <= data2) || (data3 >= data2 && data3 <= data1))
mid_data <= data3;
//ȡСֵ
if (data1 <= data2 && data1 <= data3) min_data <= data1;
else if (data2 <= data1 && data2 <= data3) min_data <= data2;
else //(data3 <= data1 && data3 <= data2)
min_data <= data3;
end
end
endmodule
| 6.775861 |
module: sort3
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sort3_test;
// Inputs
reg CLK;
reg nRST;
reg [7:0] node1;
reg [7:0] node2;
reg [7:0] node3;
// Outputs
wire [7:0] new1;
wire [7:0] new2;
wire [7:0] new3;
// Instantiate the Unit Under Test (UUT)
sort3 uut (
.CLK(CLK),
.nRST(nRST),
.node1(node1),
.node2(node2),
.node3(node3),
.new1(new1),
.new2(new2),
.new3(new3)
);
initial begin
// Initialize Inputs
CLK = 0;
nRST = 0;
node1 = 8'b0010_1010;
node2 = 8'b0011_1011;
node3 = 8'b0001_1100;
// Wait 100 ns for global reset to finish
#100;
nRST = 1;
// Add stimulus here
end
parameter DALAY = 3;
always
# DALAY CLK = ~ CLK;
endmodule
| 6.760612 |
module sort4 #(
parameter DATA_WIDTH = 8
) (
input wire reset,
input wire [DATA_WIDTH*4-1:0] data, // 四个无符号整数
output wire [DATA_WIDTH*4-1:0] dataout// 四个无符号整数, 排序完成后输出, 约定默认低字节输出最小值, 高字节输出最大值
);
localparam W = DATA_WIDTH;
wire [W-1:0] a, b, c, d;
wire [W-1:0] m, n;
wire [W*4-1:0] result;
// stage1: 输出分组排序结果, 其中 a>b, c>d
sort2 #(
.DATA_WIDTH(W)
) stage1_sort_a_b (
.data(data[W*4-1:W*2]),
.dataout({a, b})
);
sort2 #(
.DATA_WIDTH(W)
) stage1_sort_c_d (
.data(data[W*2-1:0]),
.dataout({c, d})
);
// stage2: 输出最大值=maxof(a,c) 最小值=minof(b,d) 排第二或三位的中间值m,n
sort2 #(
.DATA_WIDTH(W)
) stage2_maxof (
.data({a, c}),
.dataout({result[W*4-1:W*3], m})
);
sort2 #(
.DATA_WIDTH(W)
) stage2_minof (
.data({b, d}),
.dataout({n, result[W-1:0]})
);
// stage3: 比较中间值m,n
// 输出第二大=maxof(m,n) 和倒数第二小=minof(m,n)
sort2 #(
.DATA_WIDTH(W)
) stage3_middle (
.data({m, n}),
.dataout(result[W*3-1:W])
);
// 输出排序结果
localparam ALL_ZEROS = {(W * 4) {1'b0}};
assign dataout = (reset) ? (ALL_ZEROS) : (result);
endmodule
| 7.75212 |
module sort4_sequence_test #(
parameter data_width = 3
) (
input wire clk,
output wire [data_width - 1 : 0] outp_inps,
output wire [data_width-1 : 0] outp,
output wire [data_width-1 : 0] max
);
reg subout;
reg [1:0] countin;
integer outfile;
initial begin
outfile = $fopen("output.txt", "w");
if (0 == outfile) begin
$display("ERROR: could not open output.txt");
$finish();
end
end
initial countin = 2'b0;
initial subout = 0;
// timing: when to set subout
always @(posedge clk) begin
if (countin == 2'b11) begin
countin <= 2'b0;
subout <= 1'b1;
end else begin
countin <= count + 1'b1;
subout <= 1'b0;
end
end //end of block
//counter
reg [data_width - 1 : 0] count;
initial begin
count = 180;
end
always @(posedge clk) begin
count <= count - 1;
end
assign outp_inps = count;
// instantiate
sequence_input_compare #(
.DW(data_width)
) my_inner_product (
.clk (clk),
.inp (count),
.max (max),
.outp(outp)
);
endmodule
| 7.14815 |
module inner_product_tb ();
// note this only runs for 50 cycles with the below settings
// alter TB_TIMEOUT to run longer
localparam TB_TIMEOUT = 100000;
localparam TB_CLK_PERIOD = 2000;
localparam TB_RST_PERIOD = 4000;
initial #(TB_TIMEOUT) $finish();
// clock
reg tb_clk = 1'b0;
always #(TB_CLK_PERIOD / 2) tb_clk = ~tb_clk;
// DUT
wire [ (`NUM_ELEMS * `DATA_WIDTH)-1 : 0] outp;
wire [(`NUM_ELEMS * `DATA_WIDTH) - 1 : 0] inps;
pipe_sort5number_test #(
.data_width(`DATA_WIDTH)
) my_inner_product_test (
.clk(tb_clk),
.outp(outp),
.outp_inps(inps) // the count
);
// display inputs and output on each clock cycle
always @(posedge tb_clk) begin
$display("inps = ", inps, " => outp = ", outp);
end
endmodule
| 6.900175 |
module SortElement #(
parameter DSIZE = 18,
parameter OFFSET = 8
) (
input [DSIZE-1:0] a,
input [DSIZE-1:0] b,
output wire [DSIZE-1:0] sort0,
output wire [DSIZE-1:0] sort1
);
assign sort0 = a[OFFSET-1:0] > b[OFFSET-1:0] ? b : a;
assign sort1 = a[OFFSET-1:0] > b[OFFSET-1:0] ? a : b;
endmodule
| 6.834422 |
module sorter2 (
max,
min,
_1,
_2
);
// Parameters
parameter DATA_WIDTH = 8;
// Outputs
output wire [DATA_WIDTH - 1 : 0] min, max;
// Inputs
input wire [DATA_WIDTH - 1 : 0] _1, _2;
// Dataflow description on module
assign min = (_1 <= _2) ? _1 : _2;
assign max = (_1 > _2) ? _1 : _2;
endmodule
| 7.803636 |
module sorter5 (
o1,
o2,
o3,
o4,
o5,
i1,
i2,
i3,
i4,
i5
);
// Parameters
parameter DATA_WIDTH = 8;
// Outputs
output wire [DATA_WIDTH - 1 : 0] o1, o2, o3, o4, o5;
// Inputs
input wire [DATA_WIDTH - 1 : 0] i1, i2, i3, i4, i5;
// Wires
wire [DATA_WIDTH - 1 : 0] _11, _12, _13, _14, _15, _16, _17;
wire [DATA_WIDTH - 1 : 0] _21, _22, _23, _24, _25, _26, _27;
wire [DATA_WIDTH - 1 : 0] _31, _32, _33, _34, _35, _36, _37;
wire [DATA_WIDTH - 1 : 0] _41, _42, _43, _44, _45, _46, _47;
// Dataflow of signals
assign _21 = _11;
assign _41 = _31;
assign _15 = i5;
assign _35 = _25;
assign o5 = _45;
// Instantiation of modules
sorter2 #(.DATA_WIDTH(8))
sb11 (
_11,
_12,
i1,
i2
),
sb12 (
_13,
_14,
i3,
i4
),
sb21 (
_22,
_23,
_12,
_13
),
sb22 (
_24,
_25,
_14,
_15
),
sb31 (
_31,
_32,
_21,
_22
),
sb32 (
_33,
_34,
_23,
_24
),
sb41 (
_42,
_43,
_32,
_33
),
sb42 (
_44,
_45,
_34,
_35
),
sb51 (
o1,
o2,
_41,
_42
),
sb52 (
o3,
o4,
_43,
_44
);
endmodule
| 6.536524 |
module sorter7 (
min,
med,
max,
_1,
_2,
_3,
_4,
_5,
_6,
_7
);
// Parameters
parameter DATA_WIDTH = 8;
// Outputs
output wire [DATA_WIDTH - 1 : 0] min, med, max;
// Inputs
input wire [DATA_WIDTH - 1 : 0] _1, _2, _3, _4, _5, _6, _7;
// Wires
wire [DATA_WIDTH - 1 : 0] _11, _12, _13, _14, _15, _16, _17;
wire [DATA_WIDTH - 1 : 0] _21, _22, _23, _24, _25, _26, _27;
wire [DATA_WIDTH - 1 : 0] _31, _32, _33, _34, _35, _36, _37;
wire [DATA_WIDTH - 1 : 0] _41, _42, _43, _44, _45, _46, _47;
wire [DATA_WIDTH - 1 : 0] _51, _52, _53, _54, _55, _56, _57;
wire [DATA_WIDTH - 1 : 0] _61, _62, _63, _64, _65, _66, _67;
wire [DATA_WIDTH - 1 : 0] _71, _72, _73, _74, _75, _76, _77;
// Dataflow of signals
assign _21 = _11;
assign _41 = _31;
assign _61 = _51;
assign _17 = _7;
assign _37 = _27;
assign _57 = _47;
assign min = _67;
// Instantiation of modules
sorter2 #(.DATA_WIDTH(8))
sb11 (
_11,
_12,
_1,
_2
),
sb12 (
_13,
_14,
_3,
_4
),
sb13 (
_15,
_16,
_5,
_6
),
sb21 (
_22,
_23,
_12,
_13
),
sb22 (
_24,
_25,
_14,
_15
),
sb23 (
_26,
_27,
_16,
_17
),
sb31 (
_31,
_32,
_21,
_22
),
sb32 (
_33,
_34,
_23,
_24
),
sb33 (
_35,
_36,
_25,
_26
),
sb41 (
_42,
_43,
_32,
_33
),
sb42 (
_44,
_45,
_34,
_35
),
sb43 (
_46,
_47,
_36,
_37
),
sb51 (
_51,
_52,
_41,
_42
),
sb52 (
_53,
_54,
_43,
_44
),
sb53 (
_55,
_56,
_45,
_46
),
sb61 (
_62,
_63,
_52,
_53
),
sb62 (
_64,
_65,
_54,
_55
),
sb63 (
_66,
_67,
_56,
_57
),
sb71 (
max
,,
_61,
_62
),
sb72 (
,
med,
_63,
_64
);
endmodule
| 6.576557 |
module sort4 (
i1,
i2,
i3,
i4,
o1,
o2,
o3,
o4
);
input [7:0] i1, i2, i3, i4;
output [7:0] o1, o2, o3, o4;
wire [7:0] m1, m2, m3, m4, w1, w2, w3, w4;
sorter_2 a41a (
i1,
i2,
m1,
w1
);
sorter_2 ar1a (
i3,
i4,
m2,
w2
);
sorter_2 a2f1a (
m1,
m2,
o1,
w3
);
sorter_2 a3d1a (
w1,
w2,
m4,
o4
);
sorter_2 a3d1na (
w3,
m4,
o2,
o3
);
endmodule
| 7.071047 |
module compare_select #(
parameter LEN = 16
) (
input signed [LEN-1:0] a,
input signed [LEN-1:0] b,
output signed [LEN-1:0] out
);
reg signed [LEN-1:0] out_inner;
always @* begin
if (a > b) begin
out_inner = a;
end else begin
out_inner = b;
end
end
assign out = out_inner;
endmodule
| 7.097953 |
module that sorts an array of signed numbers into descending order (ie location [0] has largest value)
Delay and Area optimal sorting networks up to length 8 from knuth's sorting and searching volume.
Plans to add up to length 16 delay optimal networks.
One compare/swap operation per pipeline layer.
*/
`include "2dArrayMacros.v"
`include "PipelineTrain.v"
module SortNetwork # //wrapper for the various circuits
(
parameter TAG_WIDTH = 32,
//The number of numbers to be sorted
parameter BLOCKLENGTH = 16,
//The number of bits given for the signed integers
parameter DATA_WIDTH = 8
)
(
input clk,
input reset,
input ready_in,
input valid_in,
input [TAG_WIDTH-1:0] tag_in,
input [DATA_WIDTH*BLOCKLENGTH-1:0] unsortedData,
output busy,
output ready_out,
output valid_out,
output [TAG_WIDTH-1:0] tag_out,
output [DATA_WIDTH*BLOCKLENGTH-1:0] sortedData
);
generate
if (1 == BLOCKLENGTH) begin
s1 #( .TAG_WIDTH(TAG_WIDTH),
.BLOCKLENGTH(BLOCKLENGTH),
.DATA_WIDTH(DATA_WIDTH)) sorter( clk, reset, ready_in, valid_in, tag_in, unsortedData,
busy, ready_out, valid_out, tag_out, sortedData);
end else if(2 == BLOCKLENGTH) begin
s2 #( .TAG_WIDTH(TAG_WIDTH),
.BLOCKLENGTH(BLOCKLENGTH),
.DATA_WIDTH(DATA_WIDTH)) sorter( clk, reset, ready_in, valid_in, tag_in, unsortedData,
busy, ready_out, valid_out, tag_out, sortedData);
end else if(3 == BLOCKLENGTH) begin
s3 #( .TAG_WIDTH(TAG_WIDTH),
.BLOCKLENGTH(BLOCKLENGTH),
.DATA_WIDTH(DATA_WIDTH)) sorter( clk, reset, ready_in, valid_in, tag_in, unsortedData,
busy, ready_out, valid_out, tag_out, sortedData);
end else if(4 == BLOCKLENGTH) begin
s4 #( .TAG_WIDTH(TAG_WIDTH),
.BLOCKLENGTH(BLOCKLENGTH),
.DATA_WIDTH(DATA_WIDTH)) sorter( clk, reset, ready_in, valid_in, tag_in, unsortedData,
busy, ready_out, valid_out, tag_out, sortedData);
end else if(5 == BLOCKLENGTH) begin
s5 #( .TAG_WIDTH(TAG_WIDTH),
.BLOCKLENGTH(BLOCKLENGTH),
.DATA_WIDTH(DATA_WIDTH)) sorter( clk, reset, ready_in, valid_in, tag_in, unsortedData,
busy, ready_out, valid_out, tag_out, sortedData);
end else if(6 == BLOCKLENGTH) begin
s6 #( .TAG_WIDTH(TAG_WIDTH),
.BLOCKLENGTH(BLOCKLENGTH),
.DATA_WIDTH(DATA_WIDTH)) sorter( clk, reset, ready_in, valid_in, tag_in, unsortedData,
busy, ready_out, valid_out, tag_out, sortedData);
end else if(7 == BLOCKLENGTH) begin
s7 #( .TAG_WIDTH(TAG_WIDTH),
.BLOCKLENGTH(BLOCKLENGTH),
.DATA_WIDTH(DATA_WIDTH)) sorter( clk, reset, ready_in, valid_in, tag_in, unsortedData,
busy, ready_out, valid_out, tag_out, sortedData);
end else if(8 == BLOCKLENGTH) begin
s8 #( .TAG_WIDTH(TAG_WIDTH),
.BLOCKLENGTH(BLOCKLENGTH),
.DATA_WIDTH(DATA_WIDTH)) sorter( clk, reset, ready_in, valid_in, tag_in, unsortedData,
busy, ready_out, valid_out, tag_out, sortedData);
end else if(14 == BLOCKLENGTH) begin
s14 #( .TAG_WIDTH(TAG_WIDTH),
.BLOCKLENGTH(BLOCKLENGTH),
.DATA_WIDTH(DATA_WIDTH)) sorter( clk, reset, ready_in, valid_in, tag_in, unsortedData,
busy, ready_out, valid_out, tag_out, sortedData);
end else if(15 == BLOCKLENGTH) begin
s15 #( .TAG_WIDTH(TAG_WIDTH),
.BLOCKLENGTH(BLOCKLENGTH),
.DATA_WIDTH(DATA_WIDTH)) sorter( clk, reset, ready_in, valid_in, tag_in, unsortedData,
busy, ready_out, valid_out, tag_out, sortedData);
end else if(16 == BLOCKLENGTH) begin
s16 #( .TAG_WIDTH(TAG_WIDTH),
.BLOCKLENGTH(BLOCKLENGTH),
.DATA_WIDTH(DATA_WIDTH)) sorter( clk, reset, ready_in, valid_in, tag_in, unsortedData,
busy, ready_out, valid_out, tag_out, sortedData);
end
endgenerate
endmodule
| 7.026386 |
module
module s2 #
(
parameter TAG_WIDTH = 32,
parameter BLOCKLENGTH = 2,
parameter DATA_WIDTH = 8
)
(
input clk,
input reset,
input ready_in,
input valid_in,
input [TAG_WIDTH-1:0] tag_in,
input [DATA_WIDTH*BLOCKLENGTH-1:0] unsortedData_flat,
output busy,
output ready_out,
output valid_out,
output [TAG_WIDTH-1:0] tag_out,
output [DATA_WIDTH*BLOCKLENGTH-1:0] sortedData_flat
);
localparam NUM_REGISTERS = 2;
wire enable;
//pipeline train takes care of all pipeline logic.
PipelineTrain #( .TAG_WIDTH(TAG_WIDTH),
.NUM_REGISTERS(NUM_REGISTERS)) chooChoo( clk, reset, valid_in, ready_in, tag_in,
valid_out, ready_out, busy, enable, tag_out);
wire signed [DATA_WIDTH-1:0] unsorted [0:BLOCKLENGTH-1];
`UNPACK_ARRAY(DATA_WIDTH,BLOCKLENGTH,unsorted,unsortedData_flat)
//I don't think I can 3D array in verilog
reg signed [DATA_WIDTH-1:0] reg0 [0:BLOCKLENGTH-1];
reg signed [DATA_WIDTH-1:0] reg1 [0:BLOCKLENGTH-1];
//NON-ACTIVE SORTING PROPOGATIONS
integer i;
always @(posedge clk, posedge reset) begin
for(i = 0; i<BLOCKLENGTH; i=i+1 ) begin
if (1'b1 == reset) begin
reg0[i] <= 0;
end else if (1'b1 == enable) begin
reg0[i] <= unsorted[i];
end
end
end
//REGISTER 1 - sorting logic for first layer
wire swapIndicator;
assign swapIndicator = reg0[0] < reg0[1];
always @(posedge clk, posedge reset) begin
if (1'b1 == reset) begin
reg1[0] <= 0;
reg1[1] <= 0;
end else if (1'b1 == enable) begin
reg1[0] <= swapIndicator ? reg0[1] : reg0[0];
reg1[1] <= swapIndicator ? reg0[0] : reg0[1];
end
end
//output reg1
`PACK_ARRAY(DATA_WIDTH,BLOCKLENGTH,reg1,sortedData_flat)
endmodule
| 7.570872 |
module
module s3 #
(
parameter TAG_WIDTH = 32,
parameter BLOCKLENGTH = 3,
parameter DATA_WIDTH = 8
)
(
input clk,
input reset,
input ready_in,
input valid_in,
input [TAG_WIDTH-1:0] tag_in,
input [DATA_WIDTH*BLOCKLENGTH-1:0] unsortedData_flat,
output busy,
output ready_out,
output valid_out,
output [TAG_WIDTH-1:0] tag_out,
output [DATA_WIDTH*BLOCKLENGTH-1:0] sortedData_flat
);
localparam NUM_REGISTERS = 4;
wire enable;
//pipeline train takes care of all pipeline logic.
PipelineTrain #( .TAG_WIDTH(TAG_WIDTH),
.NUM_REGISTERS(NUM_REGISTERS)) chooChoo( clk, reset, valid_in, ready_in, tag_in,
valid_out, ready_out, busy, enable, tag_out);
wire signed [DATA_WIDTH-1:0] unsorted [0:BLOCKLENGTH-1];
`UNPACK_ARRAY(DATA_WIDTH,BLOCKLENGTH,unsorted,unsortedData_flat)
//I don't think I can 3D array in verilog
reg signed [DATA_WIDTH-1:0] reg0 [0:BLOCKLENGTH-1];
reg signed [DATA_WIDTH-1:0] reg1 [0:BLOCKLENGTH-1];
reg signed [DATA_WIDTH-1:0] reg2 [0:BLOCKLENGTH-1];
reg signed [DATA_WIDTH-1:0] reg3 [0:BLOCKLENGTH-1];
//NON-ACTIVE SORTING PROPAGATIONS
integer i;
always @(posedge clk, posedge reset) begin
for(i = 0; i<BLOCKLENGTH; i=i+1 ) begin
if (1'b1 == reset) begin
reg0[i] <= 0;
end else if (1'b1 == enable) begin
reg0[i] <= unsorted[i];
end
end
end
//ACTIVE SORTING PROPAGATIONS
wire swapIndicator1;
assign swapIndicator1 = reg0[0] < reg0[1];
wire swapIndicator2;
assign swapIndicator2 = reg1[0] < reg1[2];
wire swapIndicator3;
assign swapIndicator3 = reg2[1] < reg2[2];
always @(posedge clk, posedge reset) begin
if (1'b1 == reset) begin
for(i = 0; i<BLOCKLENGTH; i=i+1 ) begin
reg1[i] <= 0;
reg2[i] <= 0;
reg3[i] <= 0;
end
end else if (1'b1 == enable) begin
//first sort layer
reg1[0] <= swapIndicator1 ? reg0[1] : reg0[0];
reg1[1] <= swapIndicator1 ? reg0[0] : reg0[1];
reg1[2] <= reg0[2];
//second sort layer
reg2[0] <= swapIndicator2 ? reg1[2] : reg1[0];
reg2[2] <= swapIndicator2 ? reg1[0] : reg1[2];
reg2[1] <= reg1[1];
//third sort layer
reg3[1] <= swapIndicator3 ? reg2[2] : reg2[1];
reg3[2] <= swapIndicator3 ? reg2[1] : reg2[2];
reg3[0] <= reg2[0];
end
end
//output reg3
`PACK_ARRAY(DATA_WIDTH,BLOCKLENGTH,reg3,sortedData_flat)
endmodule
| 7.864978 |
module
module s4 #
(
parameter TAG_WIDTH = 32,
parameter BLOCKLENGTH = 4,
parameter DATA_WIDTH = 8
)
(
input clk,
input reset,
input ready_in,
input valid_in,
input [TAG_WIDTH-1:0] tag_in,
input [DATA_WIDTH*BLOCKLENGTH-1:0] unsortedData_flat,
output busy,
output ready_out,
output valid_out,
output [TAG_WIDTH-1:0] tag_out,
output [DATA_WIDTH*BLOCKLENGTH-1:0] sortedData_flat
);
localparam NUM_REGISTERS = 4;
wire enable;
//pipeline train takes care of all pipeline logic.
PipelineTrain #( .TAG_WIDTH(TAG_WIDTH),
.NUM_REGISTERS(NUM_REGISTERS)) chooChoo( clk, reset, valid_in, ready_in, tag_in,
valid_out, ready_out, busy, enable, tag_out);
wire signed [DATA_WIDTH-1:0] unsorted [0:BLOCKLENGTH-1];
`UNPACK_ARRAY(DATA_WIDTH,BLOCKLENGTH,unsorted,unsortedData_flat)
//I don't think I can 3D array in verilog
reg signed [DATA_WIDTH-1:0] reg0 [0:BLOCKLENGTH-1];
reg signed [DATA_WIDTH-1:0] reg1 [0:BLOCKLENGTH-1];
reg signed [DATA_WIDTH-1:0] reg2 [0:BLOCKLENGTH-1];
reg signed [DATA_WIDTH-1:0] reg3 [0:BLOCKLENGTH-1];
//NON-ACTIVE SORTING PROPAGATIONS
integer i;
always @(posedge clk, posedge reset) begin
for(i = 0; i<BLOCKLENGTH; i=i+1 ) begin
if (1'b1 == reset) begin
reg0[i] <= 0;
end else if (1'b1 == enable) begin
reg0[i] <= unsorted[i];
end
end
end
//ACTIVE SORTING PROPAGATIONS
wire [0:1] swapIndicator1;
assign swapIndicator1[0] = reg0[0] < reg0[1];
assign swapIndicator1[1] = reg0[2] < reg0[3];
wire [0:1] swapIndicator2;
assign swapIndicator2[0] = reg1[0] < reg1[2];
assign swapIndicator2[1] = reg1[1] < reg1[3];
wire swapIndicator3;
assign swapIndicator3 = reg2[1] < reg2[2];
always @(posedge clk, posedge reset) begin
if (1'b1 == reset) begin
for(i = 0; i<BLOCKLENGTH; i=i+1 ) begin
reg1[i] <= 0;
reg2[i] <= 0;
reg3[i] <= 0;
end
end else if (1'b1 == enable) begin
//first sort layer
reg1[0] <= swapIndicator1[0] ? reg0[1] : reg0[0];
reg1[1] <= swapIndicator1[0] ? reg0[0] : reg0[1];
reg1[2] <= swapIndicator1[1] ? reg0[3] : reg0[2];
reg1[3] <= swapIndicator1[1] ? reg0[2] : reg0[3];
//second sort layer
reg2[0] <= swapIndicator2[0] ? reg1[2] : reg1[0];
reg2[2] <= swapIndicator2[0] ? reg1[0] : reg1[2];
reg2[1] <= swapIndicator2[1] ? reg1[3] : reg1[1];
reg2[3] <= swapIndicator2[1] ? reg1[1] : reg1[3];
//third sort layer
reg3[1] <= swapIndicator3 ? reg2[2] : reg2[1];
reg3[2] <= swapIndicator3 ? reg2[1] : reg2[2];
reg3[0] <= reg2[0];
reg3[3] <= reg2[3];
end
end
//output reg3
`PACK_ARRAY(DATA_WIDTH,BLOCKLENGTH,reg3,sortedData_flat)
endmodule
| 7.639542 |
module
module s5 #
(
parameter TAG_WIDTH = 32,
parameter BLOCKLENGTH = 5,
parameter DATA_WIDTH = 8
)
(
input clk,
input reset,
input ready_in,
input valid_in,
input [TAG_WIDTH-1:0] tag_in,
input [DATA_WIDTH*BLOCKLENGTH-1:0] unsortedData_flat,
output busy,
output ready_out,
output valid_out,
output [TAG_WIDTH-1:0] tag_out,
output [DATA_WIDTH*BLOCKLENGTH-1:0] sortedData_flat
);
localparam NUM_REGISTERS = 6;
wire enable;
//pipeline train takes care of all pipeline logic.
PipelineTrain #( .TAG_WIDTH(TAG_WIDTH),
.NUM_REGISTERS(NUM_REGISTERS)) chooChoo( clk, reset, valid_in, ready_in, tag_in,
valid_out, ready_out, busy, enable, tag_out);
wire signed [DATA_WIDTH-1:0] unsorted [0:BLOCKLENGTH-1];
`UNPACK_ARRAY(DATA_WIDTH,BLOCKLENGTH,unsorted,unsortedData_flat)
//I don't think I can 3D array in verilog
reg signed [DATA_WIDTH-1:0] reg0 [0:BLOCKLENGTH-1];
reg signed [DATA_WIDTH-1:0] reg1 [0:BLOCKLENGTH-1];
reg signed [DATA_WIDTH-1:0] reg2 [0:BLOCKLENGTH-1];
reg signed [DATA_WIDTH-1:0] reg3 [0:BLOCKLENGTH-1];
reg signed [DATA_WIDTH-1:0] reg4 [0:BLOCKLENGTH-1];
reg signed [DATA_WIDTH-1:0] reg5 [0:BLOCKLENGTH-1];
//NON-ACTIVE SORTING PROPAGATIONS
integer i;
always @(posedge clk, posedge reset) begin
for(i = 0; i<BLOCKLENGTH; i=i+1 ) begin
if (1'b1 == reset) begin
reg0[i] <= 0;
end else if (1'b1 == enable) begin
reg0[i] <= unsorted[i];
end
end
end
//ACTIVE SORTING PROPAGATIONS
wire swapIndicator1 [0:1];
assign swapIndicator1[0] = reg0[0] < reg0[1];
assign swapIndicator1[1] = reg0[2] < reg0[3];
wire swapIndicator2 [0:1];
assign swapIndicator2[0] = reg1[0] < reg1[2];
assign swapIndicator2[1] = reg1[1] < reg1[4];
wire swapIndicator3 [0:1];
assign swapIndicator3[0] = reg2[0] < reg2[1];
assign swapIndicator3[1] = reg2[2] < reg2[3];
wire swapIndicator4 [0:1];
assign swapIndicator4[0] = reg3[1] < reg3[2];
assign swapIndicator4[1] = reg3[3] < reg3[4];
wire swapIndicator5;
assign swapIndicator5 = reg4[2] < reg4[3];
always @(posedge clk, posedge reset) begin
if (1'b1 == reset) begin
for(i = 0; i<BLOCKLENGTH; i=i+1 ) begin
reg1[i] <= 0;
reg2[i] <= 0;
reg3[i] <= 0;
reg4[i] <= 0;
reg5[i] <= 0;
end
end else if (1'b1 == enable) begin
//first sort layer
reg1[0] <= swapIndicator1[0] ? reg0[1] : reg0[0];
reg1[1] <= swapIndicator1[0] ? reg0[0] : reg0[1];
reg1[2] <= swapIndicator1[1] ? reg0[3] : reg0[2];
reg1[3] <= swapIndicator1[1] ? reg0[2] : reg0[3];
reg1[4] <= reg0[4];
//second sort layer
reg2[0] <= swapIndicator2[0] ? reg1[2] : reg1[0];
reg2[2] <= swapIndicator2[0] ? reg1[0] : reg1[2];
reg2[1] <= swapIndicator2[1] ? reg1[4] : reg1[1];
reg2[4] <= swapIndicator2[1] ? reg1[1] : reg1[4];
reg2[3] <= reg1[3];
//third sort layer
reg3[0] <= swapIndicator3[0] ? reg2[1] : reg2[0];
reg3[1] <= swapIndicator3[0] ? reg2[0] : reg2[1];
reg3[2] <= swapIndicator3[1] ? reg2[3] : reg2[2];
reg3[3] <= swapIndicator3[1] ? reg2[2] : reg2[3];
reg3[4] <= reg2[4];
//fourth sort layer
reg4[1] <= swapIndicator4[0] ? reg3[2] : reg3[1];
reg4[2] <= swapIndicator4[0] ? reg3[1] : reg3[2];
reg4[3] <= swapIndicator4[1] ? reg3[4] : reg3[3];
reg4[4] <= swapIndicator4[1] ? reg3[3] : reg3[4];
reg4[0] <= reg3[0];
//fifth sort layer
reg5[2] <= swapIndicator5 ? reg4[3] : reg4[2];
reg5[3] <= swapIndicator5 ? reg4[2] : reg4[3];
reg5[0] <= reg4[0];
reg5[1] <= reg4[1];
reg5[4] <= reg4[4];
end
end
//output reg5
`PACK_ARRAY(DATA_WIDTH,BLOCKLENGTH,reg5,sortedData_flat)
endmodule
| 7.459778 |
module
module s6 #
(
parameter TAG_WIDTH = 32,
parameter BLOCKLENGTH = 6,
parameter DATA_WIDTH = 8
)
(
input clk,
input reset,
input ready_in,
input valid_in,
input [TAG_WIDTH-1:0] tag_in,
input [DATA_WIDTH*BLOCKLENGTH-1:0] unsortedData_flat,
output busy,
output ready_out,
output valid_out,
output [TAG_WIDTH-1:0] tag_out,
output [DATA_WIDTH*BLOCKLENGTH-1:0] sortedData_flat
);
localparam NUM_REGISTERS = 6;
wire enable;
//pipeline train takes care of all pipeline logic.
PipelineTrain #( .TAG_WIDTH(TAG_WIDTH),
.NUM_REGISTERS(NUM_REGISTERS)) chooChoo( clk, reset, valid_in, ready_in, tag_in,
valid_out, ready_out, busy, enable, tag_out);
wire signed [DATA_WIDTH-1:0] unsorted [0:BLOCKLENGTH-1];
`UNPACK_ARRAY(DATA_WIDTH,BLOCKLENGTH,unsorted,unsortedData_flat)
//I don't think I can 3D array in verilog
reg signed [DATA_WIDTH-1:0] reg0 [0:BLOCKLENGTH-1];
reg signed [DATA_WIDTH-1:0] reg1 [0:BLOCKLENGTH-1];
reg signed [DATA_WIDTH-1:0] reg2 [0:BLOCKLENGTH-1];
reg signed [DATA_WIDTH-1:0] reg3 [0:BLOCKLENGTH-1];
reg signed [DATA_WIDTH-1:0] reg4 [0:BLOCKLENGTH-1];
reg signed [DATA_WIDTH-1:0] reg5 [0:BLOCKLENGTH-1];
//NON-ACTIVE SORTING PROPAGATIONS
integer i;
always @(posedge clk, posedge reset) begin
for(i = 0; i<BLOCKLENGTH; i=i+1 ) begin
if (1'b1 == reset) begin
reg0[i] <= 0;
end else if (1'b1 == enable) begin
reg0[i] <= unsorted[i];
end
end
end
//ACTIVE SORTING PROPAGATIONS
wire swapIndicator1 [0:2];
assign swapIndicator1[0] = reg0[0] < reg0[1];
assign swapIndicator1[1] = reg0[2] < reg0[3];
assign swapIndicator1[2] = reg0[4] < reg0[5];
wire swapIndicator2 [0:2];
assign swapIndicator2[0] = reg1[0] < reg1[2];
assign swapIndicator2[1] = reg1[3] < reg1[5];
assign swapIndicator2[2] = reg1[1] < reg1[4];
wire swapIndicator3 [0:2];
assign swapIndicator3[0] = reg2[0] < reg2[1];
assign swapIndicator3[1] = reg2[2] < reg2[3];
assign swapIndicator3[2] = reg2[4] < reg2[5];
wire swapIndicator4 [0:1];
assign swapIndicator4[0] = reg3[1] < reg3[2];
assign swapIndicator4[1] = reg3[3] < reg3[4];
wire swapIndicator5;
assign swapIndicator5 = reg4[2] < reg4[3];
always @(posedge clk, posedge reset) begin
if (1'b1 == reset) begin
for(i = 0; i<BLOCKLENGTH; i=i+1 ) begin
reg1[i] <= 0;
reg2[i] <= 0;
reg3[i] <= 0;
reg4[i] <= 0;
reg5[i] <= 0;
end
end else if (1'b1 == enable) begin
//first sort layer
reg1[0] <= swapIndicator1[0] ? reg0[1] : reg0[0];
reg1[1] <= swapIndicator1[0] ? reg0[0] : reg0[1];
reg1[2] <= swapIndicator1[1] ? reg0[3] : reg0[2];
reg1[3] <= swapIndicator1[1] ? reg0[2] : reg0[3];
reg1[4] <= swapIndicator1[2] ? reg0[5] : reg0[4];
reg1[5] <= swapIndicator1[2] ? reg0[4] : reg0[5];
//second sort layer
reg2[0] <= swapIndicator2[0] ? reg1[2] : reg1[0];
reg2[2] <= swapIndicator2[0] ? reg1[0] : reg1[2];
reg2[3] <= swapIndicator2[1] ? reg1[5] : reg1[3];
reg2[5] <= swapIndicator2[1] ? reg1[3] : reg1[5];
reg2[1] <= swapIndicator2[2] ? reg1[4] : reg1[1];
reg2[4] <= swapIndicator2[2] ? reg1[1] : reg1[4];
//third sort layer
reg3[0] <= swapIndicator3[0] ? reg2[1] : reg2[0];
reg3[1] <= swapIndicator3[0] ? reg2[0] : reg2[1];
reg3[2] <= swapIndicator3[1] ? reg2[3] : reg2[2];
reg3[3] <= swapIndicator3[1] ? reg2[2] : reg2[3];
reg3[4] <= swapIndicator3[2] ? reg2[5] : reg2[4];
reg3[5] <= swapIndicator3[2] ? reg2[4] : reg2[5];
//fourth sort layer
reg4[1] <= swapIndicator4[0] ? reg3[2] : reg3[1];
reg4[2] <= swapIndicator4[0] ? reg3[1] : reg3[2];
reg4[3] <= swapIndicator4[1] ? reg3[4] : reg3[3];
reg4[4] <= swapIndicator4[1] ? reg3[3] : reg3[4];
reg4[0] <= reg3[0];
reg4[5] <= reg3[5];
//fifth sort layer
reg5[2] <= swapIndicator5 ? reg4[3] : reg4[2];
reg5[3] <= swapIndicator5 ? reg4[2] : reg4[3];
reg5[0] <= reg4[0];
reg5[1] <= reg4[1];
reg5[4] <= reg4[4];
reg5[5] <= reg4[5];
end
end
//output reg5
`PACK_ARRAY(DATA_WIDTH,BLOCKLENGTH,reg5,sortedData_flat)
endmodule
| 7.395648 |
module used to instantiate I/O pads and connect them with the block-level design
//----------------------------------------------------------------------
// Pads
//----------------------------------------------------------------------
// EN : If 1, DOUT writes to PAD, if 0, short from PAD to DIN
// DOUT : Output of the chip, to the iocell, on the chip side
// DIN : Input to the chip from the iocell, on the chip side
// PAD : Signal pin on the pad side, (to the outside world)
//
// _______________________________________
// |
// ______________ EN |
// | |----------|
// PAD---| Iocell Pad | DIN | Chip Core Area
// | |----------|
// | | DOUT |
// |______________|----------|
// |
// ______________ |
// | | |
`define OUTPUT_PAD(name, pad, signal) \
BidirectionalIOPad name \
( \
.EN (1'b1 ), \
.DOUT(signal), \
.DIN ( ), \
.PAD (pad ) \
);
`define INPUT_PAD(name, pad, signal) \
BidirectionalIOPad name \
( \
.EN (1'b0 ), \
.DOUT( ), \
.DIN (signal), \
.PAD (pad ) \
);
//----------------------------------------------------------------------
// Design
//----------------------------------------------------------------------
module SortUnitStructRTL__chip_top
(
input wire clk ,
input wire cs ,
output wire miso ,
input wire mosi ,
input wire reset ,
input wire sclk
);
// From iocell to core area
logic clk_core;
logic cs_core;
logic miso_core;
logic mosi_core;
logic reset_core;
logic sclk_core;
//name pad signal
`INPUT_PAD( clk_pad, clk, clk_core )
`INPUT_PAD( cs_pad, cs, cs_core )
`OUTPUT_PAD( miso_pad, miso, miso_core )
`INPUT_PAD( mosi_pad, mosi, mosi_core )
`INPUT_PAD( reset_pad, reset, reset_core )
`INPUT_PAD( sclk_pad, sclk, sclk_core )
SPI_SortUnitStructRTL__nbits_8__num_entries_5 SortUnitBlock
(
.clk(clk_core),
.cs(cs_core),
.miso(miso_core),
.mosi(mosi_core),
.reset(reset_core),
.sclk(sclk_core)
);
endmodule
| 8.144031 |
module SortX8 #(
parameter DSIZE = 18,
parameter OFFSET = 8
) (
input [DSIZE-1:0] a0,
input [DSIZE-1:0] a1,
input [DSIZE-1:0] a2,
input [DSIZE-1:0] a3,
input [DSIZE-1:0] a4,
input [DSIZE-1:0] a5,
input [DSIZE-1:0] a6,
input [DSIZE-1:0] a7,
output wire [DSIZE-1:0] sort0,
output wire [DSIZE-1:0] sort1,
output wire [DSIZE-1:0] sort2,
output wire [DSIZE-1:0] sort3,
output wire [DSIZE-1:0] sort4,
output wire [DSIZE-1:0] sort5,
output wire [DSIZE-1:0] sort6,
output wire [DSIZE-1:0] sort7
);
wire [DSIZE-1:0] sortx4_0_0;
wire [DSIZE-1:0] sortx4_0_1;
wire [DSIZE-1:0] sortx4_0_2;
wire [DSIZE-1:0] sortx4_0_3;
wire [DSIZE-1:0] sortx4_1_0;
wire [DSIZE-1:0] sortx4_1_1;
wire [DSIZE-1:0] sortx4_1_2;
wire [DSIZE-1:0] sortx4_1_3;
wire [DSIZE-1:0] sort0_0;
wire [DSIZE-1:0] sort0_1;
wire [DSIZE-1:0] sort1_0;
wire [DSIZE-1:0] sort1_1;
wire [DSIZE-1:0] sort2_0;
wire [DSIZE-1:0] sort2_1;
wire [DSIZE-1:0] sort3_0;
wire [DSIZE-1:0] sort3_1;
// divide sort
SortX4 #(
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sortx4_inst0 (
.a0 (a0),
.a1 (a1),
.a2 (a2),
.a3 (a3),
.sort0(sortx4_0_0),
.sort1(sortx4_0_1),
.sort2(sortx4_0_2),
.sort3(sortx4_0_3)
);
SortX4 #(
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sortx4_inst1 (
.a0 (a4),
.a1 (a5),
.a2 (a6),
.a3 (a7),
.sort0(sortx4_1_0),
.sort1(sortx4_1_1),
.sort2(sortx4_1_2),
.sort3(sortx4_1_3)
);
// merge
SortElement #(
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst0 (
.a(sortx4_0_0),
.b(sortx4_1_3),
.sort0(sort0_0),
.sort1(sort0_1)
);
SortElement #(
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst1 (
.a(sortx4_0_1),
.b(sortx4_1_2),
.sort0(sort1_0),
.sort1(sort1_1)
);
SortElement #(
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst2 (
.a(sortx4_0_2),
.b(sortx4_1_1),
.sort0(sort2_0),
.sort1(sort2_1)
);
SortElement #(
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst3 (
.a(sortx4_0_3),
.b(sortx4_1_0),
.sort0(sort3_0),
.sort1(sort3_1)
);
// bitonic
BitonicSortX4 #(
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) bitonicsortx4_inst0 (
.a0 (sort0_0),
.a1 (sort1_0),
.a2 (sort2_0),
.a3 (sort3_0),
.sort0(sort0),
.sort1(sort1),
.sort2(sort2),
.sort3(sort3)
);
BitonicSortX4 #(
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) bitonicsortx4_inst1 (
.a0 (sort3_1),
.a1 (sort2_1),
.a2 (sort1_1),
.a3 (sort0_1),
.sort0(sort4),
.sort1(sort5),
.sort2(sort6),
.sort3(sort7)
);
endmodule
| 7.145854 |
module sorting_network_core (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
input [31:0] X0;
output [31:0] Y0;
input [31:0] X1;
output [31:0] Y1;
input [31:0] X2;
output [31:0] Y2;
input [31:0] X3;
output [31:0] Y3;
input clk, reset, next;
output next_out;
statementList80057 instList80058 (
.clk(clk),
.reset(reset),
.next(next),
.next_out(next_out),
.X0(X0),
.Y0(Y0),
.X1(X1),
.Y1(Y1),
.X2(X2),
.Y2(Y2),
.X3(X3),
.Y3(Y3)
);
endmodule
| 6.527226 |
module shiftRegFIFO (
X,
Y,
clk
);
parameter depth = 1, width = 1;
output [width-1:0] Y;
input [width-1:0] X;
input clk;
reg [width-1:0] mem [depth-1:0];
integer index;
assign Y = mem[depth-1];
always @(posedge clk) begin
for (index = 1; index < depth; index = index + 1) begin
mem[index] <= mem[index-1];
end
mem[0] <= X;
end
endmodule
| 7.124291 |
module memArray8_74211 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter depth = 2;
parameter logDepth = 1;
parameter width = 32;
input clk, next, reset;
input inFlip, outFlip;
wire next0;
input [width-1:0] x0;
output [width-1:0] y0;
input [logDepth-1:0] inAddr0, outAddr0;
input [width-1:0] x1;
output [width-1:0] y1;
input [logDepth-1:0] inAddr1, outAddr1;
input [width-1:0] x2;
output [width-1:0] y2;
input [logDepth-1:0] inAddr2, outAddr2;
input [width-1:0] x3;
output [width-1:0] y3;
input [logDepth-1:0] inAddr3, outAddr3;
shiftRegFIFO #(2, 1) shiftFIFO_80124 (
.X (next),
.Y (next0),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod0 (
.in(x0),
.out(y0),
.inAddr({inFlip, inAddr0}),
.outAddr({outFlip, outAddr0}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod1 (
.in(x1),
.out(y1),
.inAddr({inFlip, inAddr1}),
.outAddr({outFlip, outAddr1}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod2 (
.in(x2),
.out(y2),
.inAddr({inFlip, inAddr2}),
.outAddr({outFlip, outAddr2}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod3 (
.in(x3),
.out(y3),
.inAddr({inFlip, inAddr3}),
.outAddr({outFlip, outAddr3}),
.writeSel(1'b1),
.clk(clk)
);
endmodule
| 6.541501 |
module memMod (
in,
out,
inAddr,
outAddr,
writeSel,
clk
);
parameter depth = 1024, width = 16, logDepth = 10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is block
reg [width-1:0] mem [depth-1:0];
always @(posedge clk) begin
out <= mem[outAddr];
if (writeSel) mem[inAddr] <= in;
end
endmodule
| 7.262241 |
module memMod_dist (
in,
out,
inAddr,
outAddr,
writeSel,
clk
);
parameter depth = 1024, width = 16, logDepth = 10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is distributed
reg [width-1:0] mem [depth-1:0];
always @(posedge clk) begin
out <= mem[outAddr];
if (writeSel) mem[inAddr] <= in;
end
endmodule
| 7.680291 |
module switch (
ctrl,
x0,
x1,
y0,
y1
);
parameter width = 16;
input [width-1:0] x0, x1;
output [width-1:0] y0, y1;
input ctrl;
assign y0 = (ctrl == 0) ? x0 : x1;
assign y1 = (ctrl == 0) ? x1 : x0;
endmodule
| 6.864438 |
module memArray8_74321 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter depth = 2;
parameter logDepth = 1;
parameter width = 32;
input clk, next, reset;
input inFlip, outFlip;
wire next0;
input [width-1:0] x0;
output [width-1:0] y0;
input [logDepth-1:0] inAddr0, outAddr0;
input [width-1:0] x1;
output [width-1:0] y1;
input [logDepth-1:0] inAddr1, outAddr1;
input [width-1:0] x2;
output [width-1:0] y2;
input [logDepth-1:0] inAddr2, outAddr2;
input [width-1:0] x3;
output [width-1:0] y3;
input [logDepth-1:0] inAddr3, outAddr3;
shiftRegFIFO #(2, 1) shiftFIFO_80136 (
.X (next),
.Y (next0),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod0 (
.in(x0),
.out(y0),
.inAddr({inFlip, inAddr0}),
.outAddr({outFlip, outAddr0}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod1 (
.in(x1),
.out(y1),
.inAddr({inFlip, inAddr1}),
.outAddr({outFlip, outAddr1}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod2 (
.in(x2),
.out(y2),
.inAddr({inFlip, inAddr2}),
.outAddr({outFlip, outAddr2}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod3 (
.in(x3),
.out(y3),
.inAddr({inFlip, inAddr3}),
.outAddr({outFlip, outAddr3}),
.writeSel(1'b1),
.clk(clk)
);
endmodule
| 6.550756 |
module memArray16_74557 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter depth = 4;
parameter logDepth = 2;
parameter width = 32;
input clk, next, reset;
input inFlip, outFlip;
wire next0;
input [width-1:0] x0;
output [width-1:0] y0;
input [logDepth-1:0] inAddr0, outAddr0;
input [width-1:0] x1;
output [width-1:0] y1;
input [logDepth-1:0] inAddr1, outAddr1;
input [width-1:0] x2;
output [width-1:0] y2;
input [logDepth-1:0] inAddr2, outAddr2;
input [width-1:0] x3;
output [width-1:0] y3;
input [logDepth-1:0] inAddr3, outAddr3;
shiftRegFIFO #(4, 1) shiftFIFO_80153 (
.X (next),
.Y (next0),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod0 (
.in(x0),
.out(y0),
.inAddr({inFlip, inAddr0}),
.outAddr({outFlip, outAddr0}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod1 (
.in(x1),
.out(y1),
.inAddr({inFlip, inAddr1}),
.outAddr({outFlip, outAddr1}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod2 (
.in(x2),
.out(y2),
.inAddr({inFlip, inAddr2}),
.outAddr({outFlip, outAddr2}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod3 (
.in(x3),
.out(y3),
.inAddr({inFlip, inAddr3}),
.outAddr({outFlip, outAddr3}),
.writeSel(1'b1),
.clk(clk)
);
endmodule
| 6.519031 |
module memArray16_74667 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter depth = 4;
parameter logDepth = 2;
parameter width = 32;
input clk, next, reset;
input inFlip, outFlip;
wire next0;
input [width-1:0] x0;
output [width-1:0] y0;
input [logDepth-1:0] inAddr0, outAddr0;
input [width-1:0] x1;
output [width-1:0] y1;
input [logDepth-1:0] inAddr1, outAddr1;
input [width-1:0] x2;
output [width-1:0] y2;
input [logDepth-1:0] inAddr2, outAddr2;
input [width-1:0] x3;
output [width-1:0] y3;
input [logDepth-1:0] inAddr3, outAddr3;
shiftRegFIFO #(4, 1) shiftFIFO_80165 (
.X (next),
.Y (next0),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod0 (
.in(x0),
.out(y0),
.inAddr({inFlip, inAddr0}),
.outAddr({outFlip, outAddr0}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod1 (
.in(x1),
.out(y1),
.inAddr({inFlip, inAddr1}),
.outAddr({outFlip, outAddr1}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod2 (
.in(x2),
.out(y2),
.inAddr({inFlip, inAddr2}),
.outAddr({outFlip, outAddr2}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod3 (
.in(x3),
.out(y3),
.inAddr({inFlip, inAddr3}),
.outAddr({outFlip, outAddr3}),
.writeSel(1'b1),
.clk(clk)
);
endmodule
| 6.519031 |
module memArray8_75343 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter depth = 2;
parameter logDepth = 1;
parameter width = 32;
input clk, next, reset;
input inFlip, outFlip;
wire next0;
input [width-1:0] x0;
output [width-1:0] y0;
input [logDepth-1:0] inAddr0, outAddr0;
input [width-1:0] x1;
output [width-1:0] y1;
input [logDepth-1:0] inAddr1, outAddr1;
input [width-1:0] x2;
output [width-1:0] y2;
input [logDepth-1:0] inAddr2, outAddr2;
input [width-1:0] x3;
output [width-1:0] y3;
input [logDepth-1:0] inAddr3, outAddr3;
shiftRegFIFO #(2, 1) shiftFIFO_80230 (
.X (next),
.Y (next0),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod0 (
.in(x0),
.out(y0),
.inAddr({inFlip, inAddr0}),
.outAddr({outFlip, outAddr0}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod1 (
.in(x1),
.out(y1),
.inAddr({inFlip, inAddr1}),
.outAddr({outFlip, outAddr1}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod2 (
.in(x2),
.out(y2),
.inAddr({inFlip, inAddr2}),
.outAddr({outFlip, outAddr2}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod3 (
.in(x3),
.out(y3),
.inAddr({inFlip, inAddr3}),
.outAddr({outFlip, outAddr3}),
.writeSel(1'b1),
.clk(clk)
);
endmodule
| 6.511056 |
module codeBlock75453 (
clk,
reset,
next_in,
next_out,
X0_in,
Y0,
X1_in,
Y1,
X2_in,
Y2,
X3_in,
Y3
);
output next_out;
input clk, reset, next_in;
reg next;
input [31:0] X0_in, X1_in, X2_in, X3_in;
reg [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
assign next_out = next;
wire signed [31:0] Y0;
wire signed [31:0] Y1;
wire signed [31:0] Y2;
wire signed [31:0] Y3;
assign Y0 = X0;
assign Y1 = X2;
assign Y2 = X1;
assign Y3 = X3;
always @(posedge clk) begin
if (reset == 1) begin
end else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
| 6.520168 |
module nextReg (
X,
Y,
reset,
clk
);
parameter depth = 2, logDepth = 1;
output Y;
input X;
input clk, reset;
reg [logDepth:0] count;
reg active;
assign Y = (count == depth) ? 1 : 0;
always @(posedge clk) begin
if (reset == 1) begin
count <= 0;
active <= 0;
end else if (X == 1) begin
active <= 1;
count <= 1;
end else if (count == depth) begin
count <= 0;
active <= 0;
end else if (active) count <= count + 1;
end
endmodule
| 6.59955 |
module memArray64_76475 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter depth = 16;
parameter logDepth = 4;
parameter width = 32;
input clk, next, reset;
input inFlip, outFlip;
wire next0;
input [width-1:0] x0;
output [width-1:0] y0;
input [logDepth-1:0] inAddr0, outAddr0;
input [width-1:0] x1;
output [width-1:0] y1;
input [logDepth-1:0] inAddr1, outAddr1;
input [width-1:0] x2;
output [width-1:0] y2;
input [logDepth-1:0] inAddr2, outAddr2;
input [width-1:0] x3;
output [width-1:0] y3;
input [logDepth-1:0] inAddr3, outAddr3;
nextReg #(16, 4) nextReg_80372 (
.X(next),
.Y(next0),
.reset(reset),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod0 (
.in(x0),
.out(y0),
.inAddr({inFlip, inAddr0}),
.outAddr({outFlip, outAddr0}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod1 (
.in(x1),
.out(y1),
.inAddr({inFlip, inAddr1}),
.outAddr({outFlip, outAddr1}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod2 (
.in(x2),
.out(y2),
.inAddr({inFlip, inAddr2}),
.outAddr({outFlip, outAddr2}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod3 (
.in(x3),
.out(y3),
.inAddr({inFlip, inAddr3}),
.outAddr({outFlip, outAddr3}),
.writeSel(1'b1),
.clk(clk)
);
endmodule
| 6.57827 |
module memArray32_76585 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter depth = 8;
parameter logDepth = 3;
parameter width = 32;
input clk, next, reset;
input inFlip, outFlip;
wire next0;
input [width-1:0] x0;
output [width-1:0] y0;
input [logDepth-1:0] inAddr0, outAddr0;
input [width-1:0] x1;
output [width-1:0] y1;
input [logDepth-1:0] inAddr1, outAddr1;
input [width-1:0] x2;
output [width-1:0] y2;
input [logDepth-1:0] inAddr2, outAddr2;
input [width-1:0] x3;
output [width-1:0] y3;
input [logDepth-1:0] inAddr3, outAddr3;
shiftRegFIFO #(8, 1) shiftFIFO_80388 (
.X (next),
.Y (next0),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod0 (
.in(x0),
.out(y0),
.inAddr({inFlip, inAddr0}),
.outAddr({outFlip, outAddr0}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod1 (
.in(x1),
.out(y1),
.inAddr({inFlip, inAddr1}),
.outAddr({outFlip, outAddr1}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod2 (
.in(x2),
.out(y2),
.inAddr({inFlip, inAddr2}),
.outAddr({outFlip, outAddr2}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod3 (
.in(x3),
.out(y3),
.inAddr({inFlip, inAddr3}),
.outAddr({outFlip, outAddr3}),
.writeSel(1'b1),
.clk(clk)
);
endmodule
| 6.793927 |
module memArray16_76695 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter depth = 4;
parameter logDepth = 2;
parameter width = 32;
input clk, next, reset;
input inFlip, outFlip;
wire next0;
input [width-1:0] x0;
output [width-1:0] y0;
input [logDepth-1:0] inAddr0, outAddr0;
input [width-1:0] x1;
output [width-1:0] y1;
input [logDepth-1:0] inAddr1, outAddr1;
input [width-1:0] x2;
output [width-1:0] y2;
input [logDepth-1:0] inAddr2, outAddr2;
input [width-1:0] x3;
output [width-1:0] y3;
input [logDepth-1:0] inAddr3, outAddr3;
shiftRegFIFO #(4, 1) shiftFIFO_80400 (
.X (next),
.Y (next0),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod0 (
.in(x0),
.out(y0),
.inAddr({inFlip, inAddr0}),
.outAddr({outFlip, outAddr0}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod1 (
.in(x1),
.out(y1),
.inAddr({inFlip, inAddr1}),
.outAddr({outFlip, outAddr1}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod2 (
.in(x2),
.out(y2),
.inAddr({inFlip, inAddr2}),
.outAddr({outFlip, outAddr2}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod3 (
.in(x3),
.out(y3),
.inAddr({inFlip, inAddr3}),
.outAddr({outFlip, outAddr3}),
.writeSel(1'b1),
.clk(clk)
);
endmodule
| 6.660044 |
module memArray64_77371 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter depth = 16;
parameter logDepth = 4;
parameter width = 32;
input clk, next, reset;
input inFlip, outFlip;
wire next0;
input [width-1:0] x0;
output [width-1:0] y0;
input [logDepth-1:0] inAddr0, outAddr0;
input [width-1:0] x1;
output [width-1:0] y1;
input [logDepth-1:0] inAddr1, outAddr1;
input [width-1:0] x2;
output [width-1:0] y2;
input [logDepth-1:0] inAddr2, outAddr2;
input [width-1:0] x3;
output [width-1:0] y3;
input [logDepth-1:0] inAddr3, outAddr3;
nextReg #(16, 4) nextReg_80493 (
.X(next),
.Y(next0),
.reset(reset),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod0 (
.in(x0),
.out(y0),
.inAddr({inFlip, inAddr0}),
.outAddr({outFlip, outAddr0}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod1 (
.in(x1),
.out(y1),
.inAddr({inFlip, inAddr1}),
.outAddr({outFlip, outAddr1}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod2 (
.in(x2),
.out(y2),
.inAddr({inFlip, inAddr2}),
.outAddr({outFlip, outAddr2}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod3 (
.in(x3),
.out(y3),
.inAddr({inFlip, inAddr3}),
.outAddr({outFlip, outAddr3}),
.writeSel(1'b1),
.clk(clk)
);
endmodule
| 6.583752 |
module memArray32_77481 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter depth = 8;
parameter logDepth = 3;
parameter width = 32;
input clk, next, reset;
input inFlip, outFlip;
wire next0;
input [width-1:0] x0;
output [width-1:0] y0;
input [logDepth-1:0] inAddr0, outAddr0;
input [width-1:0] x1;
output [width-1:0] y1;
input [logDepth-1:0] inAddr1, outAddr1;
input [width-1:0] x2;
output [width-1:0] y2;
input [logDepth-1:0] inAddr2, outAddr2;
input [width-1:0] x3;
output [width-1:0] y3;
input [logDepth-1:0] inAddr3, outAddr3;
shiftRegFIFO #(8, 1) shiftFIFO_80509 (
.X (next),
.Y (next0),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod0 (
.in(x0),
.out(y0),
.inAddr({inFlip, inAddr0}),
.outAddr({outFlip, outAddr0}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod1 (
.in(x1),
.out(y1),
.inAddr({inFlip, inAddr1}),
.outAddr({outFlip, outAddr1}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod2 (
.in(x2),
.out(y2),
.inAddr({inFlip, inAddr2}),
.outAddr({outFlip, outAddr2}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod3 (
.in(x3),
.out(y3),
.inAddr({inFlip, inAddr3}),
.outAddr({outFlip, outAddr3}),
.writeSel(1'b1),
.clk(clk)
);
endmodule
| 6.578636 |
module memArray16_77591 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter depth = 4;
parameter logDepth = 2;
parameter width = 32;
input clk, next, reset;
input inFlip, outFlip;
wire next0;
input [width-1:0] x0;
output [width-1:0] y0;
input [logDepth-1:0] inAddr0, outAddr0;
input [width-1:0] x1;
output [width-1:0] y1;
input [logDepth-1:0] inAddr1, outAddr1;
input [width-1:0] x2;
output [width-1:0] y2;
input [logDepth-1:0] inAddr2, outAddr2;
input [width-1:0] x3;
output [width-1:0] y3;
input [logDepth-1:0] inAddr3, outAddr3;
shiftRegFIFO #(4, 1) shiftFIFO_80521 (
.X (next),
.Y (next0),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod0 (
.in(x0),
.out(y0),
.inAddr({inFlip, inAddr0}),
.outAddr({outFlip, outAddr0}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod1 (
.in(x1),
.out(y1),
.inAddr({inFlip, inAddr1}),
.outAddr({outFlip, outAddr1}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod2 (
.in(x2),
.out(y2),
.inAddr({inFlip, inAddr2}),
.outAddr({outFlip, outAddr2}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod3 (
.in(x3),
.out(y3),
.inAddr({inFlip, inAddr3}),
.outAddr({outFlip, outAddr3}),
.writeSel(1'b1),
.clk(clk)
);
endmodule
| 6.589425 |
module codeBlock78160 (
clk,
reset,
next_in,
next_out,
X0_in,
Y0,
X1_in,
Y1,
X2_in,
Y2,
X3_in,
Y3
);
output next_out;
input clk, reset, next_in;
reg next;
input [31:0] X0_in, X1_in, X2_in, X3_in;
reg [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
shiftRegFIFO #(1, 1) shiftFIFO_80601 (
.X (next),
.Y (next_out),
.clk(clk)
);
wire signed [31:0] a5158;
wire signed [31:0] a5159;
wire [0:0] a5156;
wire signed [31:0] a5164;
wire signed [31:0] a5165;
wire [0:0] a5157;
reg signed [31:0] t2430;
reg signed [31:0] t2431;
wire signed [31:0] Y0;
wire signed [31:0] Y1;
reg signed [31:0] t2432;
reg signed [31:0] t2433;
wire signed [31:0] Y2;
wire signed [31:0] Y3;
assign a5158 = X0;
assign a5159 = X1;
assign a5156 = (a5158 <= a5159) ? 1 : 0;
assign a5164 = X2;
assign a5165 = X3;
assign a5157 = (a5164 <= a5165) ? 1 : 0;
assign Y0 = t2430;
assign Y1 = t2431;
assign Y2 = t2432;
assign Y3 = t2433;
always @(posedge clk) begin
if (reset == 1) begin
end else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
t2430 <= (a5156 == 1) ? a5158 : a5159;
t2431 <= (a5156 == 1) ? a5159 : a5158;
t2432 <= (a5157 == 1) ? a5164 : a5165;
t2433 <= (a5157 == 1) ? a5165 : a5164;
end
end
endmodule
| 6.514076 |
module codeBlock78270 (
clk,
reset,
next_in,
next_out,
X0_in,
Y0,
X1_in,
Y1,
X2_in,
Y2,
X3_in,
Y3
);
output next_out;
input clk, reset, next_in;
reg next;
input [31:0] X0_in, X1_in, X2_in, X3_in;
reg [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
shiftRegFIFO #(1, 1) shiftFIFO_80621 (
.X (next),
.Y (next_out),
.clk(clk)
);
wire signed [31:0] a5124;
wire signed [31:0] a5125;
wire [0:0] a5122;
wire signed [31:0] a5130;
wire signed [31:0] a5131;
wire [0:0] a5123;
reg signed [31:0] t2414;
reg signed [31:0] t2415;
wire signed [31:0] Y0;
wire signed [31:0] Y1;
reg signed [31:0] t2416;
reg signed [31:0] t2417;
wire signed [31:0] Y2;
wire signed [31:0] Y3;
assign a5124 = X0;
assign a5125 = X1;
assign a5122 = (a5124 <= a5125) ? 1 : 0;
assign a5130 = X2;
assign a5131 = X3;
assign a5123 = (a5130 <= a5131) ? 1 : 0;
assign Y0 = t2414;
assign Y1 = t2415;
assign Y2 = t2416;
assign Y3 = t2417;
always @(posedge clk) begin
if (reset == 1) begin
end else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
t2414 <= (a5122 == 1) ? a5124 : a5125;
t2415 <= (a5122 == 1) ? a5125 : a5124;
t2416 <= (a5123 == 1) ? a5130 : a5131;
t2417 <= (a5123 == 1) ? a5131 : a5130;
end
end
endmodule
| 6.531009 |
module memArray64_78377 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter depth = 16;
parameter logDepth = 4;
parameter width = 32;
input clk, next, reset;
input inFlip, outFlip;
wire next0;
input [width-1:0] x0;
output [width-1:0] y0;
input [logDepth-1:0] inAddr0, outAddr0;
input [width-1:0] x1;
output [width-1:0] y1;
input [logDepth-1:0] inAddr1, outAddr1;
input [width-1:0] x2;
output [width-1:0] y2;
input [logDepth-1:0] inAddr2, outAddr2;
input [width-1:0] x3;
output [width-1:0] y3;
input [logDepth-1:0] inAddr3, outAddr3;
nextReg #(16, 4) nextReg_80634 (
.X(next),
.Y(next0),
.reset(reset),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod0 (
.in(x0),
.out(y0),
.inAddr({inFlip, inAddr0}),
.outAddr({outFlip, outAddr0}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod1 (
.in(x1),
.out(y1),
.inAddr({inFlip, inAddr1}),
.outAddr({outFlip, outAddr1}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod2 (
.in(x2),
.out(y2),
.inAddr({inFlip, inAddr2}),
.outAddr({outFlip, outAddr2}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod3 (
.in(x3),
.out(y3),
.inAddr({inFlip, inAddr3}),
.outAddr({outFlip, outAddr3}),
.writeSel(1'b1),
.clk(clk)
);
endmodule
| 6.702107 |
module codeBlock78380 (
clk,
reset,
next_in,
next_out,
X0_in,
Y0,
X1_in,
Y1,
X2_in,
Y2,
X3_in,
Y3
);
output next_out;
input clk, reset, next_in;
reg next;
input [31:0] X0_in, X1_in, X2_in, X3_in;
reg [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
shiftRegFIFO #(1, 1) shiftFIFO_80641 (
.X (next),
.Y (next_out),
.clk(clk)
);
wire signed [31:0] a5090;
wire signed [31:0] a5091;
wire [0:0] a5088;
wire signed [31:0] a5096;
wire signed [31:0] a5097;
wire [0:0] a5089;
reg signed [31:0] t2398;
reg signed [31:0] t2399;
wire signed [31:0] Y0;
wire signed [31:0] Y1;
reg signed [31:0] t2400;
reg signed [31:0] t2401;
wire signed [31:0] Y2;
wire signed [31:0] Y3;
assign a5090 = X0;
assign a5091 = X1;
assign a5088 = (a5090 <= a5091) ? 1 : 0;
assign a5096 = X2;
assign a5097 = X3;
assign a5089 = (a5096 <= a5097) ? 1 : 0;
assign Y0 = t2398;
assign Y1 = t2399;
assign Y2 = t2400;
assign Y3 = t2401;
always @(posedge clk) begin
if (reset == 1) begin
end else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
t2398 <= (a5088 == 1) ? a5090 : a5091;
t2399 <= (a5088 == 1) ? a5091 : a5090;
t2400 <= (a5089 == 1) ? a5096 : a5097;
t2401 <= (a5089 == 1) ? a5097 : a5096;
end
end
endmodule
| 6.651457 |
module memArray16_78597 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter depth = 4;
parameter logDepth = 2;
parameter width = 32;
input clk, next, reset;
input inFlip, outFlip;
wire next0;
input [width-1:0] x0;
output [width-1:0] y0;
input [logDepth-1:0] inAddr0, outAddr0;
input [width-1:0] x1;
output [width-1:0] y1;
input [logDepth-1:0] inAddr1, outAddr1;
input [width-1:0] x2;
output [width-1:0] y2;
input [logDepth-1:0] inAddr2, outAddr2;
input [width-1:0] x3;
output [width-1:0] y3;
input [logDepth-1:0] inAddr3, outAddr3;
shiftRegFIFO #(4, 1) shiftFIFO_80662 (
.X (next),
.Y (next0),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod0 (
.in(x0),
.out(y0),
.inAddr({inFlip, inAddr0}),
.outAddr({outFlip, outAddr0}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod1 (
.in(x1),
.out(y1),
.inAddr({inFlip, inAddr1}),
.outAddr({outFlip, outAddr1}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod2 (
.in(x2),
.out(y2),
.inAddr({inFlip, inAddr2}),
.outAddr({outFlip, outAddr2}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod3 (
.in(x3),
.out(y3),
.inAddr({inFlip, inAddr3}),
.outAddr({outFlip, outAddr3}),
.writeSel(1'b1),
.clk(clk)
);
endmodule
| 6.593133 |
module memArray64_79491 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
x2,
y2,
inAddr2,
outAddr2,
x3,
y3,
inAddr3,
outAddr3,
clk,
inFlip,
outFlip
);
parameter numBanks = 4;
parameter logBanks = 2;
parameter depth = 16;
parameter logDepth = 4;
parameter width = 32;
input clk, next, reset;
input inFlip, outFlip;
wire next0;
input [width-1:0] x0;
output [width-1:0] y0;
input [logDepth-1:0] inAddr0, outAddr0;
input [width-1:0] x1;
output [width-1:0] y1;
input [logDepth-1:0] inAddr1, outAddr1;
input [width-1:0] x2;
output [width-1:0] y2;
input [logDepth-1:0] inAddr2, outAddr2;
input [width-1:0] x3;
output [width-1:0] y3;
input [logDepth-1:0] inAddr3, outAddr3;
nextReg #(16, 4) nextReg_80795 (
.X(next),
.Y(next0),
.reset(reset),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod0 (
.in(x0),
.out(y0),
.inAddr({inFlip, inAddr0}),
.outAddr({outFlip, outAddr0}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod1 (
.in(x1),
.out(y1),
.inAddr({inFlip, inAddr1}),
.outAddr({outFlip, outAddr1}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod2 (
.in(x2),
.out(y2),
.inAddr({inFlip, inAddr2}),
.outAddr({outFlip, outAddr2}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod3 (
.in(x3),
.out(y3),
.inAddr({inFlip, inAddr3}),
.outAddr({outFlip, outAddr3}),
.writeSel(1'b1),
.clk(clk)
);
endmodule
| 6.61286 |
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