code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sort_cell #(
parameter SORT_WIDTH = 32,
parameter SHIFT_INPUT_WIDTH = 8,
parameter PRI_POS_START = 0,
parameter PRI_POS_END = 32
) (
input clk,
input reset,
//Forward shift path
input [SORT_WIDTH-1:0] prev_data,
output [SORT_WIDTH-1:0] data_out,
input [SORT_WIDTH-1:0] datain,
input place_en,
input wren,
input order,
input left_is_lower,
output i_am_lower //if (datain>= data_out), ly is set otherwise reset
);
reg [SORT_WIDTH-1:0] datain_stored;
reg [SORT_WIDTH-1:0] current;
assign data_out = current;
reg is_lower, is_lower_next;
wire aleb;
wire [31:0] current_priority;
wire [31:0] datain_priority;
assign current_priority = current[PRI_POS_END-1:PRI_POS_START];
assign datain_priority = datain[PRI_POS_END-1:PRI_POS_START];
assign i_am_lower = is_lower;
//data in is [key, val, delta, pri, ptr]
//look at pri field for comparison
//assign i_am_bigger = (current[PRI_POS_END-1:PRI_POS_START]>datain[PRI_POS_END-1:PRI_POS_START])?1'b1:1'b0;
/*A comparator for floating point comparisons*/
float_cmp fcomp (
.clk_en (place_en), //when the place_en is high, the floating_cmp compares the data and produces aleb - This result will be used 1 cycle later when wren is asserted
.clock(clk),
.dataa(current_priority),
.datab(datain_priority),
.aleb(aleb)
);
always @(posedge clk) begin
if (reset) begin
current <= 0;
is_lower <= 0;
datain_stored <= 0;
end else begin
if (wren) begin
current <= current;
is_lower <= (aleb) ? 1'b1 : 1'b0; //(current_priority<=datain_priority)?1'b1:1'b0;
end
else if(order) begin //this logic will make the logic shift right (if the cell's value is lower than the incoming data value)
is_lower <= is_lower;
case ({
left_is_lower, i_am_lower
})
2'b01: current <= datain_stored;
2'b11: current <= prev_data;
default: current <= current;
endcase
end else begin
current <= current;
is_lower <= is_lower;
end
datain_stored <= datain;
end
end
endmodule
| 6.993922 |
module SORT_counter (
input clk,
rst,
input [3:0] opcode,
output reg counter
);
always @(posedge clk, posedge rst) begin
if (rst) counter <= 0;
else begin
if (opcode == 4'b0011) begin
counter <= ~counter;
end else counter <= 0;
end
end
endmodule
| 6.705264 |
module sort_frequent (
CLK,
nRST,
FREQUENT_IN,
FREQUENT_OUT
);
input CLK;
input nRST;
input [15:0] FREQUENT_IN;
output [31:0] FREQUENT_OUT;
wire [7:0] weight_A;
wire [7:0] weight_B;
wire [7:0] weight_C;
wire [7:0] weight_D;
assign weight_A[7:0] = {FREQUENT_IN[3:0], 4'b1010};
assign weight_B[7:0] = {FREQUENT_IN[7:4], 4'b1011};
assign weight_C[7:0] = {FREQUENT_IN[11:8], 4'b1100};
assign weight_D[7:0] = {FREQUENT_IN[15:12], 4'b1101};
bubble_sort sort (
.CLK(CLK),
.nRST(nRST),
.weight_A(weight_A),
.weight_B(weight_B),
.weight_C(weight_C),
.weight_D(weight_D),
.SORT_RESULT(FREQUENT_OUT[31:0])
);
endmodule
| 6.681097 |
module: sort_frequent
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sort_frequent_test;
// Inputs
reg CLK;
reg nRST;
reg [15:0] FREQUENT_IN;
// Outputs
wire [31:0] FREQUENT_OUT;
// Instantiate the Unit Under Test (UUT)
sort_frequent uut (
.CLK(CLK),
.nRST(nRST),
.FREQUENT_IN(FREQUENT_IN),
.FREQUENT_OUT(FREQUENT_OUT)
);
initial begin
// Initialize Inputs
CLK = 0;
nRST = 0;
FREQUENT_IN = 16'b0011_0001_0010_0001;
// Wait 100 ns for global reset to finish
#100;
nRST = 1;
// Add stimulus here
end
parameter DELAY = 1;
always
#DELAY CLK = ~CLK;
endmodule
| 6.98429 |
module sort_index (
input clk,
input rst_n,
input en_sort,
input [14*(32+3)-1:0] index_to_q_unit_in,
output reg [14*(32+3)-1:0] index_to_q_unit
);
reg [5:0] count_sort;
always @(posedge clk or negedge rst_n)
if (!rst_n) count_sort <= 0;
else if (en_sort) count_sort <= count_sort + 1'b1;
else count_sort <= 0;
always @(posedge clk or negedge rst_n)
if (!rst_n) index_to_q_unit <= 0;
else if (en_sort) begin
if (index_to_q_unit_in[count_sort*14+:14] == 0) index_to_q_unit <= index_to_q_unit;
else
index_to_q_unit <= {index_to_q_unit_in[count_sort*14+:14], index_to_q_unit[14*(32+3)-1:14]};
end
endmodule
| 6.511812 |
module sort_istack (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd100;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
output [DataWidth - 1:0] q1;
sort_istack_ram sort_istack_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.d1(d1),
.we1(we1),
.q1(q1)
);
endmodule
| 6.757775 |
module N must be a power of two.
//
// Sorts N input signals of DATAWIDTH bits wide
// using only combinatorial logic
// reference Fen Logic Ltd
//********************************************************************//
module sort_N#(
parameter DATAWIDTH = 8, // Data width
parameter N = 16 // Number of entries: power of two
)
(
input CLK,
input RSTn,
output [DATAWIDTH-1:0] max,
output [DATAWIDTH-1:0] min
//also can input data
);
wire [DATAWIDTH-1:0] w [0:N*(N+1)-1];
reg [DATAWIDTH-1:0] RAM1 [0:N-1]; //input data memory
wire [DATAWIDTH-1:0] RAM2 [0:N-1]; //output data memory
//*******************initialization RAM*******************//
integer k;
always @(posedge CLK or negedge RSTn)
begin
if (!RSTn)
begin
for (k = 0;k < N;k = k + 1)
RAM1[k] <= 0;
end
else
begin
for (k = 0;k < N;k = k + 1)
RAM1[k] <= $random();//you can input data
//use some random data
end
end
//*******************compare generate**********************//
genvar c,r,a;
generate
for (c = 0;c < N;c = c + 1) //compare N times
begin
if (c[0] == 1'b0)
begin // even
for (r = 0;r < N;r = r + 2)
begin
sort2 sort2_i ( .a (w[c*N + r ]),
.b (w[c*N + r + 1 ]),
.big(w[c*N + r + N ]),
.sme(w[c*N + r + N + 1 ]));
end
end
else
begin // odd
assign w[c*N + N]=w[c*N];
for (r = 1;r < N - 2;r = r + 2)
begin
sort2 sort2_i ( .a (w[c*N + r ]),
.b (w[c*N + r + 1 ]),
.big(w[c*N + r + N ]),
.sme(w[c*N + r+ N + 1 ]));
end
assign w[c*N + N + N - 1]=w[c*N + N - 1];
end
end
for (r = 0;r < N;r = r + 1)
begin
assign w[r] = RAM1[r];
assign RAM2[r] = w[N*N + r];
end
assign max = w[N*N];
assign min = w[N*N+N-1];
endgenerate
endmodule
| 7.269022 |
module sort_three (
//global clk
input clk,
input rst_n,
//input data
input [7:0] data_in1,
input [7:0] data_in2,
input [7:0] data_in3,
//sort interface
output reg [7:0] max_data,
output reg [7:0] mid_data,
output reg [7:0] min_data
);
//--------------------------------
////Funtion : define
wire [ 7:0] shiftout;
wire [255:0] taps;
//---------------------------------
////Funtion : find the max data
always @(posedge clk or negedge rst_n) begin
if (!rst_n) max_data <= 1'd0;
else if (data_in1 >= data_in2 && data_in1 >= data_in3) max_data <= data_in1;
else if (data_in2 >= data_in1 && data_in2 >= data_in3) max_data <= data_in2;
else if (data_in3 >= data_in1 && data_in3 >= data_in2) max_data <= data_in3;
end
//--------------------------------
////Funtion : find the median data
always @(posedge clk or negedge rst_n) begin
if (!rst_n) mid_data <= 1'd0;
else if((data_in1 <= data_in2 && data_in1 >= data_in3) || (data_in1 >= data_in2 && data_in1 <= data_in3))
mid_data <= data_in1;
else if((data_in2 <= data_in1 && data_in2 >= data_in3) || (data_in2 >= data_in1 && data_in2 <= data_in3))
mid_data <= data_in2;
else if((data_in3 <= data_in2 && data_in3 >= data_in1) || (data_in3 >= data_in2 && data_in3 <= data_in1))
mid_data <= data_in3;
end
//--------------------------------
////Funtion : find the min data
always @(posedge clk or negedge rst_n) begin
if (!rst_n) min_data <= 1'd0;
else if (data_in1 <= data_in2 && data_in1 <= data_in3) min_data <= data_in1;
else if (data_in2 <= data_in1 && data_in2 <= data_in3) min_data <= data_in2;
else if (data_in3 <= data_in2 && data_in3 <= data_in1) min_data <= data_in3;
end
endmodule
| 7.744624 |
module sottrattore (
x,
y,
d,
b_in,
b_out
);
parameter N = 8;
input [N-1:0] x, y;
input b_in;
output [N-1:0] d;
output b_out;
assign #1{b_out, d} = x - y - b_in;
endmodule
| 6.687635 |
module sound (
input wire clk,
f0,
reset,
input wire [7:0] din,
input wire beeper_wr,
input wire covox_wr,
input wire beeper_mux, // output either tape_out or beeper
output wire sound_bit
);
reg sound_bit_SD;
reg sound_bit_PWM;
reg [7:0] val;
//================BEGIN===========================================
assign sound_bit = sound_bit_SD;
// port writes
always @(posedge clk)
if (reset) val <= 8'h00;
else if (covox_wr) val <= din;
else if (beeper_wr) val <= (beeper_mux ? din[3] : din[4]) ? 8'hFF : 8'h00;
//`ifdef SDM
// SD modulator ================ sigma-delta SD ===================================
reg [7:0] ctr_SD;
wire gte = val >= ctr_SD;
always @(posedge clk) begin
sound_bit_SD <= gte;
ctr_SD <= {8{gte}} - val + ctr_SD;
end
//`else
// PWM generator ============================ PWM =================================
reg [8:0] ctr_PWM;
wire phase = ctr_PWM[8];
wire [7:0] saw = ctr_PWM[7:0];
always @(posedge clk) // 28 MHz strobes, Fpwm = 54.7 kHz (two semi-periods)
begin
sound_bit_PWM <= ((phase ? saw : ~saw) < val);
ctr_PWM <= ctr_PWM + 9'b1;
end
//`endif ===========================================================================
endmodule
| 7.264396 |
module soundA (
input clk,
input rst,
input lightA,
output reg speakerA
);
reg [31:0] counter;
reg [14:0] keepON;
// FSM to Regulate Sound with Switch
reg [ 1:0] S;
reg [ 1:0] NS;
parameter START = 2'b00, PLAY = 2'b01, WAIT = 2'b10, WAIT2 = 2'b11;
reg [31:0] clkdivider;
always @(*) begin
case (S)
START:
if (lightA == 1) NS = WAIT2;
else NS = START;
WAIT2:
if (keepON == 2) NS = WAIT2;
else NS = PLAY;
PLAY:
if (lightA == 0) NS = WAIT;
else NS = PLAY;
WAIT:
if (keepON == 2) NS = START;
else NS = WAIT;
default NS = START;
endcase
end
always @(posedge clk or negedge rst) begin
if (rst == 1'b0) begin
counter <= 32'd0;
keepON <= 0;
end else
case (S)
START: begin
keepON <= 4'd0;
speakerA <= 0;
clkdivider <= 50000000 / 110 / 2;
end
WAIT2: keepON <= keepON + 4'd1;
PLAY: begin
keepON <= 4'd0;
if (counter == 0) begin
counter <= clkdivider - 1;
speakerA <= ~speakerA;
end else counter <= counter - 32'd1;
end
WAIT: keepON <= keepON + 4'd1;
endcase
end
/* FSM init and NS always */
always @(posedge clk or negedge rst) begin
if (rst == 1'b0) begin
S <= START;
end else begin
S <= NS;
end
end
endmodule
| 6.599725 |
module SoundBlaster (
input wire clk,
input wire reset_n,
input wire [11:0] port,
input wire [7:0] iodin,
output reg [7:0] iodout,
input wire iowrin,
output reg iowrout,
input wire iordin,
output reg iordout,
input wire [7:0] dma_din,
input wire dma_rdin,
output reg dma_rdout,
input wire [7:0] adlib_in,
output reg [7:0] output_left,
output reg pwm_left
);
reg data;
reg [7:0] index;
reg [7:0] div;
reg [7:0] timeconst;
reg [5:0] div50;
reg [9:0] pwm;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
data <= 1'b0;
output_left <= 8'd0;
end else begin
pwm <= pwm + 1'd1;
pwm_left <= (output_left + {adlib_in, 1'b0}) < pwm;
iordout <= iordin;
iowrout <= iowrin;
iodout <= port == 12'h22C ? 8'h00 : 8'hAA;
data <=
(port == 12'h22C) && (iordin ^ iordout) ? 1'd0 :
(port == 12'h22C) && (iowrin ^ iowrout) ? ~data :
data;
index <= (port == 12'h22C) && (iowrin ^ iowrout) && (~data) ? iodin[7:0] : index;
timeconst <=
(port == 12'h22C) && (iowrin ^ iowrout) && data && (index == 8'h40) ? iodin[7:0] :
timeconst;
div <= div50 == 6'd49 ? (&div ? timeconst : div + 8'd1) : div;
dma_rdout <= (&div) && (div50 == 6'd49) && (dma_rdin ^ dma_rdout) ? ~dma_rdout : dma_rdout;
output_left <= (&div) && (div50 == 6'd49) && (dma_rdin ^ dma_rdout) ? dma_din : output_left;
div50 <= div50 == 6'd49 ? 6'd22 : div50 + 6'd1;
end
end
endmodule
| 7.436088 |
module soundC (
input clk,
input rst,
input lightC,
output reg speakerC
);
reg [31:0] counter;
reg [ 3:0] keepON;
// FSM to Regulate Sound with Switch
reg [ 1:0] S;
reg [ 1:0] NS;
parameter START = 2'b00, PLAY = 2'b01, WAIT = 2'b10, WAIT2 = 2'b11;
reg [31:0] clkdivider;
always @(*) begin
case (S)
START:
if (lightC == 1) NS = WAIT2;
else NS = START;
WAIT2:
if (keepON == 2) NS = WAIT2;
else NS = PLAY;
PLAY:
if (lightC == 0) NS = WAIT;
else NS = PLAY;
WAIT:
if (keepON == 2) NS = START;
else NS = WAIT;
default NS = START;
endcase
end
always @(posedge clk or negedge rst) begin
if (rst == 1'b0) begin
counter <= 32'd0;
keepON <= 0;
end else
case (S)
START: begin
keepON <= 4'd0;
speakerC <= 0;
clkdivider <= 50000000 / 130.81 / 2;
end
WAIT2: keepON <= keepON + 4'd1;
PLAY: begin
keepON <= 4'd0;
if (counter == 0) begin
counter <= clkdivider - 1;
speakerC <= ~speakerC;
end else counter <= counter - 32'd1;
end
WAIT: keepON <= keepON + 4'd1;
endcase
end
/* FSM init and NS always */
always @(posedge clk or negedge rst) begin
if (rst == 1'b0) begin
S <= START;
end else begin
S <= NS;
end
end
endmodule
| 6.688412 |
module soundCard (
input wire snd_clk, // Sound clock.
input wire [1:0] channel, // Channels of sound.
input wire [1:0] sound, // Type of sound.
output wire right_o, // Channel right.
output wire left_o // Channel left.
);
// Type sounds.
localparam ping = 2'd1;
localparam pong = 2'd2;
localparam goal = 2'd3;
// Channels of sound.
localparam none = 2'd0;
localparam right = 2'd1;
localparam left = 2'd2;
localparam both = 2'd3;
// Counter.
reg [19:0] divcounter;
// Wave sound.
reg tick_sound;
// Balance channels.
assign right_o = ((channel == right) || (channel == both)) ? tick_sound : 1'b0;
assign left_o = ((channel == left) || (channel == both)) ? tick_sound : 1'b0;
// Generate and assign output tones.
always @(posedge snd_clk) begin
// New tick sound.
divcounter <= divcounter + 1;
// Check type of sound.
case (sound)
ping: tick_sound <= divcounter[15];
pong: tick_sound <= divcounter[17];
goal: tick_sound <= divcounter[18];
endcase
end
endmodule
| 6.821635 |
module soundcodec(clk24,
pulses,
ay_soundA,ay_soundB,ay_soundC,
rs_soundA,rs_soundB,rs_soundC,
covox,
tapein, reset_n,
o_adc_clk, o_adc_cs_n, i_adc_data_in,
o_pwm);
input clk24;
input [3:0] pulses;
input [7:0] ay_soundA;
input [7:0] ay_soundB;
input [7:0] ay_soundC;
input [7:0] rs_soundA;
input [7:0] rs_soundB;
input [7:0] rs_soundC;
input [7:0] covox;
output reg tapein;
input reset_n;
output o_adc_clk;
output o_adc_cs_n;
input i_adc_data_in;
output reg o_pwm;
parameter HYST = 4;
parameter PWM_WIDTH = 9;
// o +5V (from USB)
// |
// | /
// o|| 8 Ohm PC
// o|| Speaker
// | \
// |/
// o----[ R27 ] -- | 2N3904
// |\,
// |
// |
// ---
// -
//
// at 2:0 2N3904 runs quite hot when playing music through 8-ohm PC speaker, but its loud and nice
// 3:0 it gets some time to chill, but the quality/loudness is worse
reg [2:0] divctr;
always @(posedge clk24)
divctr <= divctr + 1'b1;
wire delta_sigma_ce = divctr == 0;
wire [2:0] beepsum = {pulses[0] + pulses[1] + pulses[2] + {2{pulses[3]}}};
wire [9:0] aysum = ay_soundA + ay_soundB + ay_soundC;
wire [9:0] rssum = rs_soundA + rs_soundB + rs_soundC;
wire [15:0] mixed = {beepsum, 13'b0} +
`ifdef WITH_RSOUND
{aysum, 4'b0} + {rssum, 4'b0}
`else
{aysum, 5'b0}
`endif
+ {covox, 4'b0};
wire [7:0] line8in;
tlc549c adc(.clk24(clk24), .adc_data_in(i_adc_data_in), .adc_data(line8in), .adc_clk(o_adc_clk), .adc_cs_n(o_adc_cs_n));
always @(posedge clk24) begin
if (line8in < 128+HYST) tapein <= 1'b0;
if (line8in > 128-HYST) tapein <= 1'b1;
end
reg [PWM_WIDTH:0] delta_sigma_accu;
always @(posedge clk24)
if (delta_sigma_ce)
delta_sigma_accu <= delta_sigma_accu[PWM_WIDTH - 1:0] + mixed[15:15 - (PWM_WIDTH - 1)];
always
o_pwm <= delta_sigma_accu[PWM_WIDTH];
endmodule
| 7.985964 |
module, channel 2. Squate waves with variable timmer, configurable frequency and envelope functions.
////////////////////////////////////////////////////////////////////////////////////
module SoundCtrlChannel2 //parameters
(
input wire iClock, //CPU CLOCK, 4194304Hz
input wire iReset,
input wire iOsc64, //OSC1 clock 64Hz
input wire iOsc256, //OSC1 clock 256Hz
input wire iOsc262k, //OSC2 clock 131072Hz
input wire [7:0] iNR21,
input wire [7:0] iNR22,
input wire [7:0] iNR23,
input wire [7:0] iNR24,
output reg [4:0] oOut,
output wire oOnFlag
);
reg [5:0] rLength;
reg [19:0] rLengthCounter;
reg [1:0] rDutyCycle;
reg rTimedMode;
reg rLengthComplete; // Channe disable.
reg rTone;
reg [10:0] rSoundFrequency;
reg [10:0] rSoundFrequencyCounter;
reg [3:0] rStep;
reg [18:0] rStepTime;
reg [18:0] rStepCounter;
reg [3:0] rInitialValue;
reg rEvelopeMode;
wire [4:0] up_value, down_value;
// register load
always @(posedge iClock) begin
if (iReset || iNR24[7]) begin // Register reload and counters restart.
rLength <= iNR21[5:0];
rLengthCounter <= 64-iNR21[5:0]; // Decrements to zero then load rLength.
rLengthComplete <= 0; // Disables channel when is asserted.
rDutyCycle <= iNR21[7:6];
rTimedMode <= iNR24[6];
rStepTime <= iNR22[2:0];
rStepCounter <= iNR22[2:0]; // Decrements to zero then load rStepTime.
rEvelopeMode <= iNR22[3];
rInitialValue <= iNR22[7:4];
rStep <= iNR22[7:4];
rTone <= 0;
rSoundFrequency[7:0] <= iNR23[7:0];
rSoundFrequency[10:8] <= iNR24[2:0];
rSoundFrequencyCounter <= 2048-{iNR24[2:0],iNR23[7:0]};
end
end
// step gen: generates the output amplitud value.
always @(posedge iOsc64) begin
if (rStepTime != 0) begin // Check if channel is enabled.
if (rStepCounter ==1 ) begin
rStepCounter <= rStepTime; // Reset counter.
if(rEvelopeMode) begin // Envelope mode.
rStep <= ((rStep == 4'hF) ? rStep : rStep+1); //INCREASES ONLY IF STEP IF LOWER THAN TOP VALUE
end
else begin
rStep <= ((rStep == 4'h0) ? rStep : rStep-1); //DECREASES ONLY IF STEP IF LOWER THAN BOTTOM VALUE
end
end
else begin
rStepCounter <= rStepCounter-1;
end
end
end
// tone gen: generates the frecuency of the output.
always @(posedge iOsc262k) begin
if (rSoundFrequencyCounter ==0) begin
rSoundFrequencyCounter <= 2048-rSoundFrequency;
rTone <= ~rTone;
end
else begin
rSoundFrequencyCounter <= rSoundFrequencyCounter-1;
end
end
// timmer: enable or disable channel output.
always @(posedge iOsc256) begin
if (rLengthCounter == 0) begin
rLengthCounter <= 64-rLength;
rLengthComplete <= rTimedMode; // Disable channel only if timmer is enabled.
end
else begin
rLengthCounter <= rLengthCounter-1;
end
end
//re-map mux
assign up_value = 5'd15 + rStep;
assign down_value = 5'd15 - rStep;
always @(posedge iClock) begin
if (rLengthComplete) begin
oOut[4:0] <= 5'd15;
end
else begin
if (rTone) begin
oOut[4:0] <= up_value[4:0];
end
else begin
oOut[4:0] <= down_value[4:0];
end
end
end
assign oOnFlag = rLengthComplete;
endmodule
| 8.02213 |
module, channel 2. Squate waves with variable timmer, configurable frequency and envelope functions.
////////////////////////////////////////////////////////////////////////////////////
module SoundCtrlMX //parameters
(
input wire iClock, //CPU CLOCK, 4194304Hz
input wire iReset,
input wire iOsc262k, //OSC2 clock 131072Hz
input wire [4:0] iOut1, // Channel 1.
input wire [4:0] iOut2, // Channel 2.
input wire [4:0] iOut3, // Channel 3.
input wire [4:0] iOut4, // Channel 4.
input wire [7:0] iNR50, // Left/Right enable + Left/Right volume.
input wire [7:0] iNR51, // Enable channel 1/2/3/4 in Left/Right.
output reg [4:0] oSO1, // Left channel.
output reg [4:0] oSO2, // Right channel.
output wire [1:0] oChSel,
output wire oChClk
);
reg [7:0] rNR50, rNR51;
reg [4:0] rSO1_PRE, rSO2_PRE;
reg rSer_clk; // 8kHz clock, used for serializer.
reg [1:0] rSer_sel; // Indicates which channel data were sent.
//Registers load
always @ (posedge iClock) begin
if (iReset) begin
rNR50 <= iNR50;
rNR51 <= iNR51;
rSer_sel <= 2'b0;
rSer_clk <= 1'b0;
rSO1_PRE <= 5'd15;
rSO2_PRE <= 5'd15;
end
end
//Serializer
always @ (posedge iOsc262k) begin
rSer_clk <= ~rSer_clk;
rSer_sel <= (~rSer_clk) ? rSer_sel + 1 : rSer_sel;
end
//Volume control
always @ (*) begin
case (rSer_sel)
2'd0: begin
rSO1_PRE = (rNR51[0]) ? iOut1 : 5'd15;
rSO2_PRE = (rNR51[4]) ? iOut1 : 5'd15;
end
2'd1: begin
rSO1_PRE = (rNR51[1]) ? iOut2 : 5'd15;
rSO2_PRE = (rNR51[5]) ? iOut2 : 5'd15;
end
2'd2: begin
rSO1_PRE = (rNR51[2]) ? iOut3 : 5'd15;
rSO2_PRE = (rNR51[6]) ? iOut3 : 5'd15;
end
2'd3: begin
rSO1_PRE = (rNR51[3]) ? iOut4 : 5'd15;
rSO2_PRE = (rNR51[7]) ? iOut4 : 5'd15;
end
default: begin
rSO1_PRE = 5'dX;
rSO2_PRE = 5'dX;
end
endcase
oSO1 = rSO1_PRE >> (3'd7-rNR50[2:0]);
oSO2 = rSO1_PRE >> (3'd7-rNR50[6:4]);
end
assign oChSel = rSer_sel;
assign oChClk = rSer_clk;
endmodule
| 8.02213 |
module soundctl (
input clk,
input rst,
output sound_clr_full,
input [15:0] sound_clr_sample,
input [15:0] sound_clr_rate,
input sound_clr_req,
output reg pwm_out
);
wire [15:0] fifo_out;
wire fifo_empty;
reg fifo_rd;
smallfifo16x fifo1 (
.rst(rst),
.clk_in(clk),
.fifo_in(sound_clr_sample),
.fifo_en(sound_clr_req),
.fifo_full(sound_clr_full),
.clk_out(clk),
.fifo_out(fifo_out),
.fifo_empty(fifo_empty),
.fifo_rd(fifo_rd)
);
reg [15:0] counter;
reg [ 8:0] sample;
always @(posedge clk)
if (~rst) begin
fifo_rd <= 0;
counter <= 0;
pwm_out <= 0;
sample <= 1024; // 50% duty cycle default level
end else begin
pwm_out <= (counter < sample) ? 1 : 0;
if (fifo_rd) begin
sample <= fifo_out;
fifo_rd <= 0;
end else if (counter >= sound_clr_rate) begin
counter <= 0;
if (~fifo_empty) fifo_rd <= 1;
else begin
fifo_rd <= 0;
sample <= 1024;
end
end else begin
fifo_rd <= 0;
counter <= counter + 1;
end
end
endmodule
| 6.787148 |
module soundD (
input clk,
input rst,
input lightD,
output reg speakerD
);
reg [31:0] counter;
reg [ 3:0] keepON;
// FSM to Regulate Sound with Switch
reg [ 1:0] S;
reg [ 1:0] NS;
parameter START = 2'b00, PLAY = 2'b01, WAIT = 2'b10, WAIT2 = 2'b11;
reg [31:0] clkdivider;
always @(*) begin
case (S)
START:
if (lightD == 1) NS = WAIT2;
else NS = START;
WAIT2:
if (keepON == 2) NS = WAIT2;
else NS = PLAY;
PLAY:
if (lightD == 0) NS = WAIT;
else NS = PLAY;
WAIT:
if (keepON == 2) NS = START;
else NS = WAIT;
default NS = START;
endcase
end
always @(posedge clk or negedge rst) begin
if (rst == 1'b0) begin
counter <= 32'd0;
keepON <= 0;
end else
case (S)
START: begin
keepON <= 4'd0;
speakerD <= 0;
clkdivider <= 50000000 / 146.83 / 2;
end
WAIT2: keepON <= keepON + 4'd1;
PLAY: begin
keepON <= 4'd0;
if (counter == 0) begin
counter <= clkdivider - 1;
speakerD <= ~speakerD;
end else counter <= counter - 32'd1;
end
WAIT: keepON <= keepON + 4'd1;
endcase
end
/* FSM init and NS always */
always @(posedge clk or negedge rst) begin
if (rst == 1'b0) begin
S <= START;
end else begin
S <= NS;
end
end
endmodule
| 7.012868 |
module soundE (
input clk,
input rst,
input lightE,
output reg speakerE
);
reg [31:0] counter;
reg [ 3:0] keepON;
// FSM to Regulate Sound with Switch
reg [ 1:0] S;
reg [ 1:0] NS;
parameter START = 2'b00, PLAY = 2'b01, WAIT = 2'b10, WAIT2 = 2'b11;
reg [31:0] clkdivider;
always @(*) begin
case (S)
START:
if (lightE == 1) NS = WAIT2;
else NS = START;
WAIT2:
if (keepON == 2) NS = WAIT2;
else NS = PLAY;
PLAY:
if (lightE == 0) NS = WAIT;
else NS = PLAY;
WAIT:
if (keepON == 2) NS = START;
else NS = WAIT;
default NS = START;
endcase
end
always @(posedge clk or negedge rst) begin
if (rst == 1'b0) begin
counter <= 32'd0;
keepON <= 0;
end else
case (S)
START: begin
keepON <= 4'd0;
speakerE <= 0;
clkdivider <= 50000000 / 164.81 / 2;
end
WAIT2: keepON <= keepON + 4'd1;
PLAY: begin
keepON <= 4'd0;
if (counter == 0) begin
counter <= clkdivider - 1;
speakerE <= ~speakerE;
end else counter <= counter - 32'd1;
end
WAIT: keepON <= keepON + 4'd1;
endcase
end
/* FSM init and NS always */
always @(posedge clk or negedge rst) begin
if (rst == 1'b0) begin
S <= START;
end else begin
S <= NS;
end
end
endmodule
| 7.228901 |
module soundF (
input clk,
input rst,
input lightF,
output reg speakerF
);
reg [31:0] counter;
reg [ 3:0] keepON;
// FSM to Regulate Sound with Switch
reg [ 1:0] S;
reg [ 1:0] NS;
parameter START = 2'b00, PLAY = 2'b01, WAIT = 2'b10, WAIT2 = 2'b11;
reg [31:0] clkdivider;
always @(*) begin
case (S)
START:
if (lightF == 1) NS = WAIT2;
else NS = START;
WAIT2:
if (keepON == 2) NS = WAIT2;
else NS = PLAY;
PLAY:
if (lightF == 0) NS = WAIT;
else NS = PLAY;
WAIT:
if (keepON == 2) NS = START;
else NS = WAIT;
default NS = START;
endcase
end
always @(posedge clk or negedge rst) begin
if (rst == 1'b0) begin
counter <= 32'd0;
keepON <= 0;
end else
case (S)
START: begin
keepON <= 4'd0;
speakerF <= 0;
clkdivider <= 50000000 / 174.61 / 2;
end
WAIT2: keepON <= keepON + 4'd1;
PLAY: begin
keepON <= 4'd0;
if (counter == 0) begin
counter <= clkdivider - 1;
speakerF <= ~speakerF;
end else counter <= counter - 32'd1;
end
WAIT: keepON <= keepON + 4'd1;
endcase
end
/* FSM init and NS always */
always @(posedge clk or negedge rst) begin
if (rst == 1'b0) begin
S <= START;
end else begin
S <= NS;
end
end
endmodule
| 6.663165 |
module soundG (
input clk,
input rst,
input lightG,
output reg speakerG
);
reg [31:0] counter;
reg [ 3:0] keepON;
// FSM to Regulate Sound with Switch
reg [ 1:0] S;
reg [ 1:0] NS;
parameter START = 2'b00, PLAY = 2'b01, WAIT = 2'b10, WAIT2 = 2'b11;
reg [31:0] clkdivider;
always @(*) begin
case (S)
START:
if (lightG == 1) NS = WAIT2;
else NS = START;
WAIT2:
if (keepON == 2) NS = WAIT2;
else NS = PLAY;
PLAY:
if (lightG == 0) NS = WAIT;
else NS = PLAY;
WAIT:
if (keepON == 2) NS = START;
else NS = WAIT;
default NS = START;
endcase
end
always @(posedge clk or negedge rst) begin
if (rst == 1'b0) begin
counter <= 32'd0;
keepON <= 0;
end else
case (S)
START: begin
keepON <= 4'd0;
speakerG <= 0;
clkdivider <= 50000000 / 196 / 2;
end
WAIT2: keepON <= keepON + 4'd1;
PLAY: begin
keepON <= 4'd0;
if (counter == 0) begin
counter <= clkdivider - 1;
speakerG <= ~speakerG;
end else counter <= counter - 32'd1;
end
WAIT: keepON <= keepON + 4'd1;
endcase
end
/* FSM init and NS always */
always @(posedge clk or negedge rst) begin
if (rst == 1'b0) begin
S <= START;
end else begin
S <= NS;
end
end
endmodule
| 6.965651 |
module SoundMixer (
//////////// Audio //////////
input AUD_ADCDAT,
inout AUD_ADCLRCK,
inout AUD_BCLK,
output AUD_DACDAT,
inout AUD_DACLRCK,
output AUD_XCK,
//////////// CLOCK //////////
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
//////////// I2C for Audio and Video-In //////////
output FPGA_I2C_SCLK,
inout FPGA_I2C_SDAT,
//////////// SEG7 //////////
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
//////////// KEY //////////
input [3:0] KEY,
//////////// LED //////////
output [9:0] LEDR,
//////////// SW //////////
input [9:0] SW
);
//=======================================================
// REG/WIRE declarations
//=======================================================
//=======================================================
// Structural coding
//=======================================================
assign HEX5 = 7'b1111111;
assign HEX4 = 7'b1111111;
assign HEX3 = 7'b1111111;
assign HEX2 = 7'b1111111;
assign HEX1 = 7'b1111111;
mixer m (
.audio_config_extern_SDAT (FPGA_I2C_SDAT),
.audio_config_extern_SCLK (FPGA_I2C_SCLK),
.audio_external_ADCDAT (AUD_ADCDAT),
.audio_external_ADCLRCK (AUD_ADCLRCK),
.audio_external_BCLK (AUD_BCLK),
.audio_external_DACDAT (AUD_DACDAT),
.audio_external_DACLRCK (AUD_DACLRCK),
.audio_pll_clk_clk (AUD_XCK),
.clk_clk (CLOCK_50),
.hex_amplif_hex_signal (HEX0),
.key_amplif_key_signal (KEY[1:0]),
.led_amplif_led_signal (LEDR),
.reset_reset_n (~SW[9]),
.switch_avg_switch_signal (SW[0]),
.switch_delay_switch_signal(SW[1]),
.switch_noise_switch_signal(SW[2])
);
endmodule
| 7.652105 |
module: sound_player
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module soundtb;
// Inputs
reg [3:0] noteAction;
reg [3:0] noteSuccessState;
reg clk;
reg rst;
// Outputs
wire buzzer_sound;
// Instantiate the Unit Under Test (UUT)
sound_player uut (
.noteAction(noteAction),
.noteSuccessState(noteSuccessState),
.clk(clk),
.rst(rst),
.buzzer_sound(buzzer_sound)
);
initial begin
// Initialize Inputs
noteAction = 0;
noteSuccessState = 0;
clk = 0;
rst = 1;
#5;
rst = 0;
// Wait 100 ns for global reset to finish
#100;
noteAction = 4'b1000;
noteSuccessState = 4'b1000;
#5;
noteAction = 4'b0000;
#1215752;
noteAction = 4'b0001;
noteSuccessState = 4'b0001;
#5;
noteAction = 4'b0000;
// Add stimulus here
end
always #5 clk = ~clk;
endmodule
| 7.421987 |
module soundwave (
input CLK,
input CLK44100x256,
input [7:0] data,
input we,
output reg AUDIO
);
reg [15:0] wdata;
reg [2:0] write = 3'b000;
reg [15:0] sample;
reg [15:0] buffer;
reg [31:0] lval = 0;
wire lsign = lval[31:16] < sample;
always @(posedge CLK44100x256) begin
if (|write) begin
sample <= buffer;
buffer <= wdata;
end
lval <= lval - lval[31:7] + (lsign << 25);
AUDIO <= lsign;
end
always @(posedge CLK) begin
if (we) begin
write <= 3'b110;
wdata <= {1'b0, data[7:0], 7'b0000000};
end else write <= write - |write;
end
endmodule
| 7.074226 |
module draw_graph (
clk,
audio_clock,
enable,
reset,
soundwave,
enable_draw,
X_Vga,
Y_Vga
);
input clk, audio_clock, enable, reset;
input [23:0] soundwave;
output enable_draw;
output [7:0] X_Vga;
output [6:0] Y_Vga;
// Rate divider: every 4 clock cycles
wire [15:0] load = 16'd1000;
wire [15:0] count;
countdown ct (
clk,
audio_clock,
enable,
load,
reset,
count
);
// Enable draw
wire enable_draw;
assign enable_draw = (count == 0) ? 1 : 0;
// Handle reset and enable
reg [7:0] x;
always @(posedge clk) begin
if (reset) x <= 8'd0;
else if (enable_draw && audio_clock) begin
if (x < 8'b11111110) x <= x + 8'd1;
end
end
// Set parameters to draw
wire [2:0] colour;
wire [7:0] x_in;
assign x_in = x;
simple_draw d1 (
soundwave,
x_in,
X_Vga,
Y_Vga,
colour
);
endmodule
| 7.4209 |
module hex_decoder (
hex_digit,
segments
);
input [3:0] hex_digit;
output reg [6:0] segments;
always @(*)
case (hex_digit)
4'h0: segments = 7'b100_0000;
4'h1: segments = 7'b111_1001;
4'h2: segments = 7'b010_0100;
4'h3: segments = 7'b011_0000;
4'h4: segments = 7'b001_1001;
4'h5: segments = 7'b001_0010;
4'h6: segments = 7'b000_0010;
4'h7: segments = 7'b111_1000;
4'h8: segments = 7'b000_0000;
4'h9: segments = 7'b001_1000;
4'hA: segments = 7'b000_1000;
4'hB: segments = 7'b000_0011;
4'hC: segments = 7'b100_0110;
4'hD: segments = 7'b010_0001;
4'hE: segments = 7'b000_0110;
4'hF: segments = 7'b000_1110;
default: segments = 7'h7f;
endcase
endmodule
| 7.584821 |
module Sound_control (
inout v2, //ͨ·
input clk_100MHz, //ϵͳʱ
input rst_sound, //λźţӵĸλźͬ
output v2_show_en //ʾ
);
//ԴƵ¼ʱ
reg clk_1MHz; //ÿ1us
reg [7:0] cnt;
parameter N = 100;
initial begin
cnt <= 8'b0;
clk_1MHz <= 1'b0;
end
always @(posedge clk_100MHz, negedge rst_sound) begin
if (!rst_sound) begin
cnt <= 8'b0;
clk_1MHz <= 1'b0;
end else if (cnt == N / 2 - 1) begin
cnt <= 8'b0;
clk_1MHz <= ~clk_1MHz;
end else cnt <= cnt + 1'b1;
end
reg [1:0] state_sound;
reg [31:0] us_count;
reg temp_reg = 0;
parameter S0 = 0, S1 = 1, S2 = 2;
always @(posedge clk_1MHz, negedge rst_sound) begin
if (!rst_sound) begin
state_sound <= S0;
us_count <= 0;
temp_reg <= 0;
end else begin
case (state_sound)
S0: begin
if (v2 == 1) begin
if(us_count >= 50_0000) //0.5s
begin
state_sound <= S1;
temp_reg <= 1;
us_count <= 0;
end else begin
temp_reg <= 0;
us_count <= us_count + 1;
end
end else begin
state_sound <= S0;
temp_reg <= 0;
end
end
S1: begin
if(us_count >= 2000_0000) //СҪʣܴ
begin
state_sound <= S2;
us_count <= 0;
temp_reg <= 0;
end else begin
us_count <= us_count + 1;
state_sound <= S1;
temp_reg <= 1;
end
end
S2: begin
if (v2 == 1) state_sound <= S1;
else state_sound <= S0;
end
default: begin
state_sound <= S0;
us_count <= 0;
end
endcase
end
end
assign v2_show_en = rst_sound ? temp_reg : 1; //Чʱʼմ1
endmodule
| 6.788332 |
module sound_controller (
clk,
on,
pitch,
out
);
input clk, on;
input [3:0] pitch;
output reg out;
reg [31:0] counter;
reg [31:0] maxCounter;
initial begin
counter = 32'd0;
maxCounter = 32'd113636;
out = 0;
end
always @(pitch) begin
case (pitch)
4'b0000: maxCounter <= 32'd113636; // A 3
4'b0001: maxCounter <= 32'd101215; // B
4'b0010: maxCounter <= 32'd90253; // C#
4'b0011: maxCounter <= 32'd85034; // D
4'b0100: maxCounter <= 32'd75758; // E
4'b0101: maxCounter <= 32'd67568; // F#
4'b0110: maxCounter <= 32'd60241; // G#
4'b0111: maxCounter <= 32'd56818; // A 4
4'b1000: maxCounter <= 32'd50607; // B
4'b1001: maxCounter <= 32'd45126; // C#
4'b1010: maxCounter <= 32'd42589; // D
4'b1011: maxCounter <= 32'd37936; // E
4'b1100: maxCounter <= 32'd33784; // F#
4'b1101: maxCounter <= 32'd30084; // G#
4'b1110: maxCounter <= 32'd28409; // A 5
4'b1111: maxCounter <= 32'd28409; // A 5
endcase
end
always @(posedge clk) begin
if (counter >= maxCounter) begin
if (on) out <= ~out;
else out <= 0;
counter <= 32'd0;
end else counter <= counter + 32'd1;
end
endmodule
| 7.041631 |
module Sound_control_tb ();
wire v2;
reg clk_100MHz;
reg rst_sound;
wire v2_show_en;
initial begin
clk_100MHz = 0;
rst_sound = 1;
end
always #1 clk_100MHz = ~clk_100MHz;
initial begin
force v2 = 1;
#50;
release v2;
#50 force v2 = 1;
#600;
release v2;
#50;
rst_sound = 0;
#50 force v2 = 1;
#50 release v2;
end
Sound_control uut (
.v2(v2),
.clk_100MHz(clk_100MHz),
.rst_sound(rst_sound),
.v2_show_en(v2_show_en)
);
endmodule
| 6.788332 |
module Sound_Counter (
WAVE,
RESET,
RESULT
);
input WAVE;
input RESET;
output reg [`SOUND_COUNTER_WIDTH-1:0] RESULT;
always @(posedge WAVE or posedge RESET) begin
if (RESET) begin
RESULT <= 0;
end else begin
RESULT <= RESULT + 1;
end
end
endmodule
| 6.526267 |
module generates strobe signal for data sender - load, indicating when it loaded new portion of data,
// and allowing sender to begin preparing new data. dac_leftright is also to be used by sender (by locking it
// when load is 1).
//
// dac_clock is symmetrical clock at 1/10 of input clock (2.4 MHz)
// load is positive 1 clock cycle pulse informing that new data has just loaded
module sound_dac(
clock, // input clock (24 MHz)
dac_clock, // clock to DAC
dac_leftright, // left-right signal to DAC (0 - left, 1 - right)
dac_data, // data to DAC
load, // output indicating cycle when new data loaded from datain bus
datain // input 16-bit bus
);
input clock;
output dac_clock;
output dac_leftright;
output dac_data;
output reg load;
input [15:0] datain;
reg [16:0] data; // internal shift register
reg [2:0] fifth; // divide by 5
reg [6:0] sync; // sync[0] - dac_clock
// sync[6] - dac_leftright
wire load_int;
// for simulation purposes
initial
begin
fifth <= 0;
sync <= 0;
data <= 0;
load <= 0;
end
// divide input clock by 5
always @(posedge clock)
begin
if( fifth[2] )
fifth <= 3'b000;
else
fifth <= fifth + 3'd1;
end
// divide further to get dac_clock and dac_leftright
always @(posedge clock)
begin
if( fifth[2] ) sync <= sync + 7'd1;
end
// load signal generation
assign load_int = fifth[2] & (&sync[5:0]);
always @(posedge clock)
begin
load <= load_int;
end
// loading and shifting data
always @(posedge clock)
begin
if( fifth[2] && sync[0] )
begin
if( load_int )
data[15:0] <= datain;
else
data[15:0] <= { data[14:0], 1'b0 }; // MSB first
data[16] <= data[15];
end
end
assign dac_leftright = sync[6];
assign dac_clock = sync[0];
assign dac_data = data[16];
endmodule
| 7.590906 |
module generates strobe signal for data sender - load, indicating when it loaded new portion of data,
// and allowing sender to begin preparing new data. dac_leftright is also to be used by sender (by locking it
// when load is 1).
//
// dac_clock is symmetrical clock at 1/10 of input clock (2.4 MHz)
// load is positive 1 clock cycle pulse informing that new data has just loaded
module sound_dac(
clock, // input clock (24 MHz)
dac_clock, // clock to DAC
dac_leftright, // left-right signal to DAC (0 - left, 1 - right)
dac_data, // data to DAC
load, // output indicating cycle when new data loaded from datain bus
datain // input 16-bit bus
);
input clock;
output dac_clock;
output dac_leftright;
output dac_data;
output reg load;
input [15:0] datain;
reg [16:0] data; // internal shift register
reg [2:0] fifth; // divide by 5
reg [6:0] sync; // sync[0] - dac_clock
// sync[6] - dac_leftright
wire load_int;
// for simulation purposes
initial
begin
fifth <= 0;
sync <= 0;
data <= 0;
load <= 0;
end
// divide input clock by 5
always @(posedge clock)
begin
if( fifth[2] )
fifth <= 3'b000;
else
fifth <= fifth + 3'd1;
end
// divide further to get dac_clock and dac_leftright
always @(posedge clock)
begin
if( fifth[2] ) sync <= sync + 7'd1;
end
// load signal generation
assign load_int = fifth[2] & (&sync[5:0]);
always @(posedge clock)
begin
load <= load_int;
end
// loading and shifting data
always @(posedge clock)
begin
if( fifth[2] && sync[0] )
begin
if( load_int )
data[15:0] <= datain;
else
data[15:0] <= { data[14:0], 1'b0 }; // MSB first
data[16] <= data[15];
end
end
assign dac_leftright = sync[6];
assign dac_clock = sync[0];
assign dac_data = data[16];
endmodule
| 7.590906 |
module Sound_Encoder (
CLK,
WAVE,
LEVEL
);
input CLK; //100Hz
input WAVE;
output reg [`SOUND_LEVEL_ENCODE_LENGTH-1:0] LEVEL;
/*
该模块作用是将声音传感器收集到的声音频率信号抽象为6个等级
每0.02s采样一次，采样时间为为0.01s,统计期间声波上升沿的个数
由上升沿个数的多寡决定最终分级
*/
reg counter_reset;
wire [`SOUND_COUNTER_WIDTH-1:0] wave_counter;
Sound_Counter sound_counter (
WAVE,
counter_reset,
wave_counter
);
parameter RESET = 1'b0;
parameter UPDATE = 1'b1;
reg current_state = RESET;
reg next_state;
always @(posedge CLK) begin
current_state <= next_state;
end
always @(current_state) begin
case (current_state)
RESET: begin
next_state = UPDATE;
end
UPDATE: begin
next_state = RESET;
end
endcase
end
always @(posedge CLK) begin
case (next_state)
RESET: begin
counter_reset <= 1;
end
UPDATE: begin
counter_reset <= 0;
end
endcase
end
always @(negedge CLK) begin
case (current_state)
RESET: begin
LEVEL <= LEVEL;
end
UPDATE: begin
if (wave_counter < `LEVEL_BOUNDARY_0) begin
LEVEL <= `NO_SOUND;
end else if (wave_counter >= `LEVEL_BOUNDARY_0 && wave_counter < `LEVEL_BOUNDARY_1) begin
LEVEL <= `LEVEL_1;
end else if (wave_counter >= `LEVEL_BOUNDARY_1 && wave_counter < `LEVEL_BOUNDARY_2) begin
LEVEL <= `LEVEL_2;
end else if (wave_counter >= `LEVEL_BOUNDARY_2 && wave_counter < `LEVEL_BOUNDARY_3) begin
LEVEL <= `LEVEL_3;
end else if (wave_counter >= `LEVEL_BOUNDARY_3 && wave_counter < `LEVEL_BOUNDARY_4) begin
LEVEL <= `LEVEL_4;
end else begin
LEVEL <= `LEVEL_5;
end
end
endcase
end
endmodule
| 6.800788 |
module sound # (
parameter wav_length= 16'd38174;
parameter init_file= ""
)
(
input clk,
input trigger,
input RESET_n,
output signed [15:0] sound_out
);
reg sndclk = 1'b0;
always @(posedge clk) begin
sndclk <= ~sndclk;
end
reg wav_playing = 1'b0;
wire wav_play;
reg [WAV_COUNTER_SIZE-1:0] wav_counter;
localparam WAV_COUNTER_SIZE = 10;//10
localparam WAV_COUNTER_MAX = 100;//1000
reg signed [7:0] wav_signed;
// Wave player
reg [15:0] wave_rom_addr;
wire [7:0] wave_rom_data_out;
reg [15:0] wave_rom_length = wav_length;
spram #(16,8,init_file) wave_rom
(
.clk(clk),
.address(wave_rom_addr),
.wren(1'b0),
.data(),
.q(wave_rom_data_out)
);
clock trig1(
.clk(sndclk),
.rst_n(),
.Phi2(trigger),
.cpu_clken(wav_play)
);
// States
localparam STOP = 0, START = 1, PLAY = 2;
reg [1:0] state = STOP;
always @(posedge clk)
begin
case (state)
STOP : begin
wav_signed <= 8'b0;
wave_rom_addr <= 16'b0; //reset the rom address
wav_counter <= WAV_COUNTER_MAX; // put the wav counter to the maximum
if(wav_play)
begin//wav_play is trigger to play it
state <= START;
//wav_play <= 1'b0;
end
end
START : begin
wav_signed <= 8'b0;
wave_rom_addr <= 16'b0; //reset the rom address
wav_counter <= WAV_COUNTER_MAX; // put the wav counter to the maximum
wav_playing <= 1'b1; //make wav_playing 1
state <= PLAY;
end
PLAY : begin
wav_counter <= wav_counter - 1'b1; //reduce the wav counter by one bit.
if(wav_play)
begin//wav_play is trigger to play it
state <= START;
//wav_play <= 1'b0;
end
if(wav_counter == {WAV_COUNTER_SIZE{1'b0}})// if wav counter is zero.
begin
if(wave_rom_addr < wave_rom_length) // if wave rom address is below wave rom length (38174)
begin
wav_signed <= wave_rom_data_out; //wav signed is wave rom data out
wave_rom_addr <= wave_rom_addr + 16'b1; //wave rom address is incremented by 1 bit
wav_counter <= {WAV_COUNTER_SIZE{1'b1}}; //wav counter is? check this!
end
else //if wave rom address in NOT below wave rom length
begin
state <= STOP;
end
end
end
endcase
end
wire signed [15:0] wav_amplified = { wav_signed[7], {1{wav_signed[7]}}, wav_signed[6:0], {7{wav_signed[7]}} }; //create 16 bit from 8 bit wav
assign sound_out = wav_amplified;
endmodule
| 7.716383 |
module sound_mem (
clk,
addr,
rdata
);
parameter ROM_DATA_FILE = "Sound.mem";
input clk;
input [17:0] addr;
output reg [3:0] rdata;
reg [3:0] MY_ROM[0:2**18-1];
initial $readmemb(ROM_DATA_FILE, MY_ROM);
always @(posedge clk) rdata <= MY_ROM[addr];
endmodule
| 6.905564 |
module sound_memory (
input [6:0] address,
input en,
output [6:0] data
);
reg [6:0] sound_file[127:0];
initial $readmemh("./resources/sound.txt", sound_file);
assign data = en ? sound_file[address] : 0;
endmodule
| 7.01527 |
module sound_mulacc (
clock, // input clock (24 MHz)
vol_in, // input volume (6 bit unsigned)
dat_in, // input sound data (8 bit signed with sign bit inverted)
mode_inv7b, // whether to invert 7th bit of dat_in
load, // load pulse input
clr_sum, // clear sum input
ready, // ready output
sum_out // 16-bit sum output
);
input clock;
input [5:0] vol_in;
input [7:0] dat_in;
input mode_inv7b;
input load;
input clr_sum;
output reg ready;
output reg [15:0] sum_out;
wire [5:0] add_data;
wire [6:0] sum_unreg;
reg [6:0] sum_reg;
reg [7:0] shifter;
reg [5:0] adder;
wire mul_out;
reg [3:0] counter;
reg clr_sum_reg;
wire [1:0] temp_sum;
wire carry_in;
wire old_data_in;
reg old_carry;
// control section
//
always @(posedge clock) begin
if (load) ready <= 1'b0;
if (counter[3:0] == 4'd15) ready <= 1'b1;
if (load) counter <= 4'd0;
else counter <= counter + 4'd1;
end
// serial multiplier section
//
assign add_data = (shifter[0]) ? adder : 6'd0; // data to be added controlled by LSB of shifter
assign sum_unreg[6:0] = sum_reg[6:1] + add_data[5:0]; // sum of two values
assign mul_out = sum_unreg[0];
always @(posedge clock) begin
if( !load ) // normal addition
begin
sum_reg[6:0] <= sum_unreg[6:0];
shifter[6:0] <= shifter[7:1];
end else // load==1
begin
sum_reg[6:0] <= 7'd0;
shifter[7] <= ~(mode_inv7b^dat_in[7]); // convert to signed data (we need signed result), invert 7th bit if needed
shifter[6:0] <= dat_in[6:0];
adder <= vol_in;
end
end
// serial adder section
//
always @(posedge clock) begin
if (load) clr_sum_reg <= clr_sum;
end
assign carry_in = (counter == 4'd0) ? 1'b0 : old_carry;
assign old_data_in = (clr_sum_reg) ? 1'b0 : sum_out[0];
assign temp_sum[1:0] = carry_in + mul_out + old_data_in;
always @(posedge clock) begin
if (!ready) begin
sum_out[15:0] <= {temp_sum[0], sum_out[15:1]};
old_carry <= temp_sum[1];
end
end
endmodule
| 6.512135 |
module sound_noise (
input rst, // Async reset
input clk, // CPU Clock
input clk_length_ctr, // Length control clock
input clk_vol_env, // Volume Envelope clock
input [5:0] length, // Length = (64-t1)*(1/256) second, used iff single is set
input [3:0] initial_volume, // Initial volume of envelope 0 = no sound
input envelope_increasing, // 0 = decrease, 1 = increase
input [2:0] num_envelope_sweeps, // number of envelope sweep 0 = stop
input [3:0] shift_clock_freq, // shift clock prescaler (s)
input counter_width, // 0 = 15 bits, 1 = 7 bits
input [2:0] freq_dividing_ratio, // shift clock divider 0 -> 1MHz, 1 -> 512kHz (r)
input start, // Restart sound
input single, // If set, output would stop upon reaching the length specified
output [3:0] level,
output enable
);
// Dividing ratio from 4MHz is (r * 8), for the divier to work, the comparator shoud
// compare with (dividing_factor / 2 - 1), so it becomes (r * 4 - 1)
reg [4:0] adjusted_freq_dividing_ratio;
reg [3:0] latched_shift_clock_freq;
wire [3:0] target_vol;
reg clk_div = 0;
wire clk_shift;
reg [4:0] clk_divider = 5'b0; // First stage
always @(posedge clk) begin
if (clk_divider == adjusted_freq_dividing_ratio) begin
clk_div <= ~clk_div;
clk_divider <= 0;
end else clk_divider <= clk_divider + 1'b1;
end
reg [13:0] clk_shifter = 14'b0; // Second stage
always @(posedge clk_div) begin
clk_shifter <= clk_shifter + 1'b1;
end
assign clk_shift = clk_shifter[latched_shift_clock_freq];
reg [14:0] lfsr = {15{1'b1}};
wire target_freq_out = ~lfsr[0];
wire [14:0] lfsr_next =
(counter_width == 0) ? ({(lfsr[0] ^ lfsr[1]), lfsr[14:1]}) :
({8'b0, (lfsr[0] ^ lfsr[1]), lfsr[6:1]});
always @(posedge start) begin
adjusted_freq_dividing_ratio <=
(freq_dividing_ratio == 3'b0) ? (5'd1) : ((freq_dividing_ratio * 4) - 1);
latched_shift_clock_freq <= shift_clock_freq;
end
always @(posedge clk_shift, posedge start) begin
if (start) begin
lfsr <= {15{1'b1}};
end else begin
lfsr <= lfsr_next;
end
end
sound_vol_env sound_vol_env (
.clk_vol_env(clk_vol_env),
.start(start),
.initial_volume(initial_volume),
.envelope_increasing(envelope_increasing),
.num_envelope_sweeps(num_envelope_sweeps),
.target_vol(target_vol)
);
sound_length_ctr #(6) sound_length_ctr (
.rst(rst),
.clk_length_ctr(clk_length_ctr),
.start(start),
.single(single),
.length(length),
.enable(enable)
);
sound_channel_mix sound_channel_mix (
.enable(enable),
.modulate(target_freq_out),
.target_vol(target_vol),
.level(level)
);
endmodule
| 7.820615 |
module sound_player (
input [7:0] noteAction,
input [7:0] noteSuccessState,
input clk,
input rst,
output buzzer_sound
);
reg [7:0] sound;
buzzer_driver buzzer_driver (
.clk(clk),
.rst(rst),
.sound(sound),
.buzzer(buzzer_sound)
);
always @(posedge clk) begin
if (rst) begin
sound <= 0;
end else if (noteAction !== 8'b0) sound <= noteSuccessState;
else sound <= 0;
end
endmodule
| 7.356737 |
module sound_sample (
//////////// CLOCK //////////
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
//////////// KEY //////////
input [3:0] KEY,
//////////// SW //////////
input [9:0] SW,
//////////// LED //////////
output [9:0] LEDR,
//////////// Seg7 //////////
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
//////////// Audio //////////
input AUD_ADCDAT,
inout AUD_ADCLRCK,
inout AUD_BCLK,
output AUD_DACDAT,
inout AUD_DACLRCK,
output AUD_XCK,
//////////// PS2 //////////
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
//////////// I2C for Audio and Video-In //////////
output FPGA_I2C_SCLK,
inout FPGA_I2C_SDAT
);
//=======================================================
// REG/WIRE declarations
//=======================================================
wire clk_i2c;
wire reset;
wire [15:0] audiodata;
//mypart
wire [15:0] frequency;
reg [6:0] vol = 7'b1111001;
//=======================================================
// Structural coding
//=======================================================
always @(negedge KEY[3]) begin
vol <= vol + 4;
end
assign reset = ~KEY[0];
audio_clk u1 (
CLOCK_50,
reset,
AUD_XCK,
LEDR[9]
);
//mypart
keyboard k (
CLOCK_50,
SW[1],
PS2_DAT,
PS2_CLK,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
frequency
);
//I2C part
clkgen #(10000) my_i2c_clk (
CLOCK_50,
reset,
1'b1,
clk_i2c
); //10k I2C clock
I2C_Audio_Config myconfig (
vol,
clk_i2c,
KEY[0],
FPGA_I2C_SCLK,
FPGA_I2C_SDAT,
LEDR[2:0]
);
I2S_Audio myaudio (
AUD_XCK,
KEY[0],
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
audiodata
);
//mypart
Sin_Generator sin_wave (
AUD_DACLRCK,
KEY[0],
frequency,
audiodata
); //
endmodule
| 6.897427 |
module sound_square (
input rst, // Async reset
input clk, // CPU Clock
input clk_length_ctr, // Length control clock
input clk_vol_env, // Volume Envelope clock
input clk_sweep, // Sweep clock
input clk_freq_div, // Base frequency for divider (should be 16x131072=2097152Hz)
input [2:0] sweep_time, // From 0 to 7/128Hz
input sweep_decreasing, // 0: Addition (Freq+) 1: Subtraction (Freq-)
input [2:0] num_sweep_shifts, // Number of sweep shift (n=0-7)
input [1:0] wave_duty, // 00: 87.5% HIGH 01: 75% HIGH 10: 50% HIGH 11: 25% HIGH
input [5:0] length, // Length = (64-t1)*(1/256) second, used iff single is set
input [3:0] initial_volume, // Initial volume of envelope 0 = no sound
input envelope_increasing, // 0 = decrease, 1 = increase
input [2:0] num_envelope_sweeps, // number of envelope sweep 0 = stop
input start, // Restart sound
input single, // If set, output would stop upon reaching the length specified
input [10:0] frequency, // Output frequency = 131072/(2048-x) Hz
output [3:0] level, // Sound output
output enable // Internal enable flag
);
//Sweep: X(t) = X(t-1) +/- X(t-1)/2^n
reg [10:0] divider = 11'b0;
reg [10:0] target_freq;
reg octo_freq_out = 0; // 8 x target frequency with arbitrary duty cycle
wire target_freq_out; // Traget frequency with specified duty cycle
wire [3:0] target_vol;
reg [2:0] sweep_left; // Number of sweeps need to be done
always @(posedge clk_freq_div, posedge start) begin
if (start) begin
divider <= target_freq;
end else begin
if (divider == 11'd2047) begin
octo_freq_out <= ~octo_freq_out;
divider <= target_freq;
end else begin
divider <= divider + 1'b1;
end
end
end
reg [2:0] duty_counter = 3'b0;
always @(posedge octo_freq_out) begin
duty_counter <= duty_counter + 1'b1;
end
assign target_freq_out =
(wave_duty == 2'b00) ? ((duty_counter != 3'b111) ? 1'b1 : 1'b0) : ( // 87.5% HIGH
(wave_duty == 2'b01) ? ((duty_counter[2:1] != 2'b11) ? 1'b1 : 1'b0) : ( // 75% HIGH
(wave_duty == 2'b10) ? ((duty_counter[2]) ? 1'b1 : 1'b0) : ( // 50% HIGH
((duty_counter[2:1] == 2'b00) ? 1'b1 : 1'b0)))); // 25% HIGH
// Frequency Sweep
reg overflow;
always @(posedge clk_sweep, posedge start) begin
if (start) begin
target_freq <= frequency;
sweep_left <= sweep_time;
overflow <= 0;
end else begin
if (sweep_left != 3'b0) begin
sweep_left <= sweep_left - 1'b1;
if (sweep_decreasing) target_freq <= target_freq - (target_freq << num_sweep_shifts);
else
{overflow, target_freq} <= {1'b0, target_freq} + ({1'b0, target_freq} << num_sweep_shifts);
end else begin
target_freq <= frequency;
end
end
end
/*always@(posedge start)
begin
target_freq <= frequency;
end*/
sound_vol_env sound_vol_env (
.clk_vol_env(clk_vol_env),
.start(start),
.initial_volume(initial_volume),
.envelope_increasing(envelope_increasing),
.num_envelope_sweeps(num_envelope_sweeps),
.target_vol(target_vol)
);
wire enable_length;
sound_length_ctr #(6) sound_length_ctr (
.rst(rst),
.clk_length_ctr(clk_length_ctr),
.start(start),
.single(single),
.length(length),
.enable(enable_length)
);
assign enable = enable_length & ~overflow;
sound_channel_mix sound_channel_mix (
.enable(enable),
.modulate(target_freq_out),
.target_vol(target_vol),
.level(level)
);
endmodule
| 6.919254 |
module sound_tb;
reg rst = 1;
reg clk = 0;
always #500 clk = !clk;
wire dac_en;
wire [7:0] dac_value;
sound dut (
.rst(rst),
.clk_4e(clk),
.diagnostic(1'b1),
.pb(6'b000000),
.hand(1'b0),
.dac_en(dac_en),
.dac_value(dac_value)
);
initial begin
$dumpfile("sound_tb.vcd");
$dumpvars(0, dut);
end
initial begin
#5000 rst <= 0;
end
endmodule
| 6.909182 |
module sound_test (
GPIO,
LEDR,
SW
);
input [0:0] GPIO;
input [17:0] SW;
output [17:0] LEDR;
Sound_Module sound (
.sound(GPIO[0]),
.out(LEDR[0]),
.enable(SW[1])
);
endmodule
| 7.05487 |
module Sound_Top (
input clk,
reset,
inout SDIN,
output SCLK,
USB_clk,
BCLK,
output reg DAC_LR_CLK,
output DAC_DATA,
output [2:0] ACK_LEDR
);
reg [3:0] counter; //selecting register address and its corresponding data
reg counting_state, ignition;
reg read_enable;
reg [15:0] MUX_input;
reg [17:0] read_counter;
reg [3:0] ROM_output_mux_counter;
reg [4:0] DAC_LR_CLK_counter;
wire [15:0] ROM_out;
wire finish_flag;
assign DAC_DATA = ROM_out[15-ROM_output_mux_counter];
//============================================
//Instantiation section
I2C_Protocol I2C (
.clk(clk),
.reset(reset),
.ignition(ignition),
.MUX_input(MUX_input),
.ACK(ACK_LEDR),
.SDIN(SDIN),
.finish_flag(finish_flag),
.SCLK(SCLK)
);
USB_Clock_PLL USB_Clock_PLL_inst (
.inclk0(clk),
.c0(USB_clk),
.c1(BCLK)
);
music_rom contra_ROM_inst (
.address(read_counter),
.clock(clk),
.q(ROM_out)
);
//============================================
// address for ROM
always @(posedge DAC_LR_CLK) begin
if (read_enable) begin
read_counter <= read_counter + 1;
if (read_counter == 96377) read_counter <= 0;
end
end
//============================================
// ROM output mux
always @(posedge BCLK) begin
if (read_enable) begin
ROM_output_mux_counter <= ROM_output_mux_counter + 1;
if (DAC_LR_CLK_counter == 31) DAC_LR_CLK <= 1;
else DAC_LR_CLK <= 0;
end
end
always @(posedge BCLK) begin
if (read_enable) begin
DAC_LR_CLK_counter <= DAC_LR_CLK_counter + 1;
end
end
//============================================
// generate 6 configuration pulses
always @(posedge clk) begin
if (!reset) begin
counting_state <= 0;
read_enable <= 0;
end else begin
case (counting_state)
0: begin
ignition <= 1;
read_enable <= 0;
if (counter == 8) counting_state <= 1; //was 8
end
1: begin
read_enable <= 1;
ignition <= 0;
end
endcase
end
end
//============================================
// this counter is used to switch between registers
always @(posedge SCLK) begin
case (counter) //MUX_input[15:9] register address, MUX_input[8:0] register data
0: MUX_input <= 16'h1201; // activate interface
1: MUX_input <= 16'h0460; // left headphone out
2: MUX_input <= 16'h0C00; // power down control
3: MUX_input <= 16'h0812; // analog audio path control
4: MUX_input <= 16'h0A00; // digital audio path control
5: MUX_input <= 16'h102F; // sampling control
6: MUX_input <= 16'h0E23; // digital audio interface format
7: MUX_input <= 16'h0660; // right headphone out
8: MUX_input <= 16'h1E00; // reset device
endcase
end
always @(posedge finish_flag) begin
counter <= counter + 1;
end
endmodule
| 6.898608 |
module SOUND_TO_MTL2 (
input [15:0] WAVE,
input AUDIO_MCLK,
input SAMPLE_TR,
input RESET_n,
input DRAW_DOT,
input MTL_CLK,
output [7:0] MTL2_R,
output [7:0] MTL2_G,
output [7:0] MTL2_B,
output MTL2_HSD,
output MTL2_VSD,
output MTL2_DCLK,
input [2:0] SCAL,
input START_STOP
);
//---VGA CONTROLLER ---
VGA_Controller vc ( // Host Side
.iRed (MTL_D_R),
.iGreen (MTL_D_G),
.iBlue (MTL_D_B),
.oRequest (),
// VGA Side
.oVGA_R (MTL2_R),
.oVGA_G (MTL2_G),
.oVGA_B (MTL2_B),
.oVGA_H_SYNC(MTL2_HSD),
.oVGA_V_SYNC(MTL2_VSD),
.oVGA_CLOCK (MTL2_DCLK),
// Control Signal
.iCLK (MTL_CLK),
.iRST_N (RESET_n),
.H_Cont (H_CNT),
.V_Cont (V_CNT)
);
wire [11:0] H_CNT, V_CNT;
//--WAVE BUFFFER ---
reg [11:0] SW_ADDR;
wire [11:0] VR_ADDR;
reg PW_CH;
wire [15:0] VRDAT_1;
wire [15:0] VRDAT_2;
//----PIXEL TRIGGER DRAWN LINE PROCESS ----
wire [7:0] MTL_D_R, MTL_D_G, MTL_D_B;
assign { MTL_D_R , MTL_D_G , MTL_D_B } = (
(
( ( DRAW_DOT==0 ) &&
( ( X1 > X2) && ( V_CNT[8:0] < X1 ) && ( V_CNT[8:0] >= X2 ) ) ||
( ( X1 < X2) && ( V_CNT[8:0] >= X1 ) && ( V_CNT[8:0] < X2 ) )||
( ( X1 == X2) &&( V_CNT[8:0] == X2 ) )
) ||
( ( DRAW_DOT==1 ) && ( V_CNT[8:0] == X1 ) )
) ? 24'hFFFF00 :
( 255 == V_CNT[8:0] ) ? ( (START_STOP)? 24'h6F6F6F : 24'hFF0000) : 0
);
//----POLIAR TRANSFORM ----
wire [8:0] X1; //currentPIXEL
wire [8:0] X2; //nextPIXEL
assign X1 = PW_CH ? {~VDT2_1[15], VDT2_1[14:7]} : {~VDT1_1[15], VDT1_1[14:7]};
assign X2 = PW_CH ? {~VDT2_2[15], VDT2_2[14:7]} : {~VDT1_2[15], VDT1_2[14:7]};
//-- BUFFER CONTROLLER -----
//re
reg [15:0] VDT1_1, VDT1_2;
reg [15:0] VDT2_1, VDT2_2;
reg rMTL2_VSD;
reg [7:0] CNT;
always @(posedge SAMPLE_TR) begin
rMTL2_VSD <= MTL2_VSD;
if (CNT >= SCAL) CNT <= 0;
else CNT <= CNT + 1;
if ((!rMTL2_VSD && MTL2_VSD) && (SW_ADDR > 1000)) begin
SW_ADDR <= (START_STOP) ? 0 : SW_ADDR;
PW_CH <= (START_STOP) ? ~PW_CH : PW_CH;
end else begin
if (MTL2_VSD) begin
if (SW_ADDR > 1000) begin
SW_ADDR <= SW_ADDR;
end else if (CNT == 0) begin
SW_ADDR <= SW_ADDR + 1;
end
end
end
end
always @(posedge MTL2_DCLK) begin
{VDT1_1, VDT1_2} <= {VDT1_2, VRDAT_1};
{VDT2_1, VDT2_2} <= {VDT2_2, VRDAT_2};
end
//--3200word 16bit DPORT-RAM1--//
PIPO P1 (
.rdaddress(H_CNT),
.rdclock (MTL_CLK),
.q (VRDAT_1),
.data (WAVE),
.wraddress(SW_ADDR),
.wrclock (SAMPLE_TR),
.wren (PW_CH)
);
//--3200word 16bit DPORT-RAM2--//
PIPO P2 (
.rdaddress(H_CNT),
.rdclock (MTL_CLK),
.q (VRDAT_2),
.data (WAVE),
.wraddress(SW_ADDR),
.wrclock (SAMPLE_TR),
.wren (~PW_CH)
);
endmodule
| 6.632043 |
module sound_wave (
input rst, // Async reset
input clk, // Main CPU clock
input clk_length_ctr, // Length control clock
input [7:0] length, // Length = (256-t1)*(1/256) second, used iff single is set
input [1:0] volume,
input on,
input single,
input start,
input [10:0] frequency,
output [3:0] wave_a,
input [7:0] wave_d,
output [3:0] level,
output enable
);
// Freq = 64kHz / (2048 - frequency)
// Why????????
wire [3:0] current_sample;
reg [4:0] current_pointer = 5'b0;
assign wave_a[3:0] = current_pointer[4:1];
assign current_sample[3:0] = (current_pointer[0]) ? (wave_d[3:0]) : (wave_d[7:4]);
wire clk_wave_base = clk; // base clock
/*clk_div #(.WIDTH(6), .DIV(32)) freq_div(
.i(clk),
.o(clk_wave_base)
);*/
reg clk_pointer_inc = 1'b0; // Clock for pointer to increment
reg [10:0] divider = 11'b0;
always @(posedge clk_wave_base, posedge start) begin
if (start) begin
divider <= frequency;
end else begin
if (divider == 11'd2047) begin
clk_pointer_inc <= ~clk_pointer_inc;
divider <= frequency;
end else begin
divider <= divider + 1'b1;
end
end
end
always @(posedge clk_pointer_inc, posedge start) begin
if (start) begin
current_pointer <= 5'b0;
end else begin
if (on) current_pointer <= current_pointer + 1'b1;
end
end
sound_length_ctr #(8) sound_length_ctr (
.rst(rst),
.clk_length_ctr(clk_length_ctr),
.start(start),
.single(single),
.length(length),
.enable(enable)
);
assign level = (on) ? (
(volume == 2'b00) ? (4'b0000) : (
(volume == 2'b01) ? (current_sample[3:0]) : (
(volume == 2'b10) ? ({1'b0, current_sample[3:1]}) : (
({2'b0, current_sample[3:2]}))))) : 4'b0000;
endmodule
| 7.559463 |
module serial_source (
en_w,
ip_traffic,
clk,
reset,
serial_out,
busy,
pir
);
//parameter DEST_ID=`NUM_NODES-1;
parameter NODE_ID = 0;
input clk, reset, busy, en_w;
input [7:0] pir;
input [`NUM_NODES-1:0] ip_traffic;
output serial_out;
wire [`ADDR_SZ-1:0] data;
source #(
.NODE_ID(NODE_ID)
) s1 (
en_w,
ip_traffic,
clk,
reset,
data,
req,
tx_busy,
pir
);
tx tx1 (
clk,
reset,
req,
tx_busy,
busy,
data,
serial_out
);
endmodule
| 6.947006 |
module serial_source (
clk,
reset,
serial_out,
busy,
pir
);
parameter DEST_ID = `NUM_NODES - 1;
parameter NODE_ID = 0;
input clk, reset, busy;
input [7:0] pir;
output serial_out;
wire [`ADDR_SZ-1:0] data;
source #(
.DEST_ID(DEST_ID),
.NODE_ID(NODE_ID)
) s1 (
clk,
reset,
data,
req,
tx_busy,
pir
);
tx tx1 (
clk,
reset,
req,
tx_busy,
busy,
data,
serial_out
);
endmodule
| 6.947006 |
module sourcemux (
muxin0,
muxin1,
select,
muxout
);
parameter k = 1;
input [15:0] muxin0, muxin1;
input select;
output reg [15:0] muxout;
always @(*) begin
case (select)
1'b0: muxout = muxin0;
1'b1: muxout = muxin1;
default: muxout = {k{1'bx}};
endcase
end
endmodule
| 6.56294 |
module serial_source_from_memory (
clk,
reset,
serial_out,
busy,
send
);
parameter id = -1;
parameter dests = 1;
parameter pir = 16;
parameter traffic_file = "";
input clk, reset, busy, send;
output serial_out;
wire tx_active;
wire [`HDR_SZ + `PL_SZ + `ADDR_SZ-1:0] data;
source_from_memory #(id, dests, pir, traffic_file) s1 (
clk,
reset,
data,
req,
tx_busy,
send
);
tx tx1 (
clk,
reset,
req,
tx_busy,
busy,
data,
serial_out,
tx_active
);
endmodule
| 6.947006 |
module serial_source_from_memory (
clk,
reset,
serial_out,
busy
);
parameter id = -1;
parameter flits = 16;
parameter traffic_file = "";
input clk, reset, busy;
output serial_out;
wire tx_active;
wire [`SIZE-1:0] data;
source_from_memory #(id, flits, traffic_file) s1 (
clk,
reset,
data,
req,
tx_busy
);
tx tx1 (
clk,
reset,
req,
tx_busy,
busy,
data,
serial_out,
tx_active
);
endmodule
| 6.947006 |
module serial_source_from_memory (
clk,
reset,
serial_out,
busy,
send
);
parameter id = -1;
parameter dests = 1;
parameter pir = 16;
parameter traffic_file = "";
input clk, reset, busy, send;
output serial_out;
wire tx_active;
wire [`HDR_SZ + `PL_SZ + `ADDR_SZ-1:0] data;
source_from_memory #(id, dests, pir, traffic_file) s1 (
clk,
reset,
data,
req,
tx_busy,
send
);
tx tx1 (
clk,
reset,
req,
tx_busy,
busy,
data,
serial_out,
tx_active
);
endmodule
| 6.947006 |
module source_v3 #(
parameter WIDTH = 8,
parameter DEPTH = 256
) (
clk,
s_rst,
vaild_in,
ready,
vaild,
data_out
);
localparam wt = $clog2(DEPTH);
input clk;
input s_rst;
input vaild_in;
input ready;
output reg [WIDTH-1:0] data_out;
output vaild;
reg [WIDTH-1:0] mem [DEPTH-1:0];
reg [ wt:0] rd_addr;
//=================== 初始化 ==================
integer i;
always @(posedge clk)
if (s_rst == 1'b1)
for (i = 0; i < DEPTH; i = i + 1) begin
mem[i] <= i + 1;
end
//================== end ===================
//==================vaild ==================
// always@(posedge clk)begin
// if(s_rst == 1'b1)
// vaild <= 1'b0;
// else if(rd_addr == (DEPTH))//To prevent livelocks
// vaild <= 1'b0;
// else if(vaild_in == 1'b0 && vaild == 1'b1 && ready == 1'b0)
// vaild <= 1'b1;
// else if(vaild_in == 1'b1)//To prevent deadlocks
// vaild <= 1'b1;
// else
// vaild <= 1'b0;
// end
assign vaild = vaild_in;
//==================end===============
//===================payload_out=====================
always @(posedge clk) begin
if (s_rst == 1'b1) //first data
data_out <= mem[0];
else if (ready == 1'b1 && vaild == 1'b1) data_out <= mem[rd_addr];
else data_out <= data_out;
end
always @(posedge clk) begin
if (s_rst == 1'b1) rd_addr <= 'd1;
else if (rd_addr == (DEPTH) && ready == 1'b1 && vaild == 1'b1) rd_addr <= rd_addr;
else if (ready == 1'b1 && vaild == 1'b1) //handshake is complete,next begin
rd_addr <= rd_addr + 1'b1;
end
//===================end ====================================================
endmodule
| 6.983352 |
module Sout_16bit (
input clk,
input rst,
input ld,
input [15:0] in,
output reg Dout
);
reg [15:0] out;
always @(posedge clk)
if (!rst) Dout <= 0;
else Dout <= out[15];
always @(posedge clk)
if (!rst) out <= 0;
else if (ld) out <= in;
else out <= {out[14:0], 1'b0};
endmodule
| 7.362124 |
module so_pdm #(
parameter INPUT_WIDTH = 8
) (
input wire i_clk,
input wire i_res,
input wire i_ce,
input wire [INPUT_WIDTH-1:0] i_func,
output wire o_DAC
);
reg this_bit;
reg [(INPUT_WIDTH):0] DAC_acc_1st;
reg [(INPUT_WIDTH):0] DAC_acc_2nd;
reg [(INPUT_WIDTH):0] i_func_extended;
assign o_DAC = this_bit;
always @(*) i_func_extended = {i_func[INPUT_WIDTH-1], i_func};
always @(posedge i_clk) begin
if (i_ce == 1'b1) begin
if (this_bit == 1'b1) begin
DAC_acc_1st = DAC_acc_1st + i_func_extended - (2 ** (INPUT_WIDTH - 1));
DAC_acc_2nd = DAC_acc_2nd + DAC_acc_1st - (2 ** (INPUT_WIDTH - 1));
end else begin
DAC_acc_1st = DAC_acc_1st + i_func_extended + (2 ** (INPUT_WIDTH - 1));
DAC_acc_2nd = DAC_acc_2nd + DAC_acc_1st + (2 ** (INPUT_WIDTH - 1));
end
// When the high bit is set (a negative value) we need to output a 0 and when it is clear we need to output a 1.
this_bit = ~DAC_acc_2nd[INPUT_WIDTH];
end
if (i_res == 1'b1) begin
DAC_acc_1st <= {INPUT_WIDTH{1'b0}};
DAC_acc_2nd <= {INPUT_WIDTH{1'b0}};
this_bit = 1'b0;
end
end
endmodule
| 6.95409 |
module so_pdm_tb ();
reg clk;
reg rst;
wire dac_out;
reg pulse_48k;
reg pulse_24M;
reg pulse_sine;
wire [7:0] sine_signal;
reg [7:0] sine_signal_r = 0;
initial begin
$dumpfile("test.vcd");
$dumpvars(0, so_pdm_tb);
end
// Clock generator
always begin
clk = 0;
#10.416 clk = 1;
#10.416 clk = 0;
end
initial begin
rst = 1;
#50;
rst = 0;
end
real x;
integer f, i;
// 24MHz pulse train
always begin
pulse_24M = 0;
#20.832 pulse_24M = 1;
#20.832 pulse_24M = 0;
end
// 48KHz pulse train
always begin
pulse_48k = 0;
#20811.168 pulse_48k = 1;
#20.832 pulse_48k = 0;
end
// sine pulse train
always begin
pulse_sine = 0;
#20.832 pulse_sine = 0;
#20.832 pulse_sine = 0;
#20.832 pulse_sine = 1;
#20.832 pulse_sine = 0;
end
initial begin
for (i = 0; i < 4096; i = i + 1) begin
@(posedge pulse_48k);
end
end
initial begin
f = $fopen("output.txt", "w");
@(negedge rst); //Wait for reset to be released
while (i < 4096) begin
@(posedge clk); //Wait for first clock out of reset
$fwrite(f, "%d\n", sine_signal_r);
//$fwrite(f,"%d\n",{8{dac_out}});
end
$fclose(f);
$finish();
end
rom_wavegen i_sinegen (
.clk(clk),
.reset(rst),
.enable_pulse(pulse_sine),
.step(12'b1),
.wave_out(sine_signal)
);
always @(posedge clk) begin
sine_signal_r <= 8'h00;
if (pulse_24M) begin
sine_signal_r <= sine_signal;
end
end
second_order_dac i_so_pdm (
.i_clk (clk),
.i_res (~rst),
.i_ce (1'b1),
.i_func({sine_signal_r, 8'h00}),
.o_DAC (dac_out)
);
endmodule
| 7.261106 |
module SP256K (
input wire [13:0] AD,
input wire [15:0] DI,
input wire [3:0] MASKWE,
input wire WE,
input wire CS,
input wire CK,
input wire STDBY,
input wire SLEEP,
input wire PWROFF_N,
output wire [15:0] DO
);
wire [13 : 0] addr;
wire [15 : 0] din;
wire [ 1 : 0] write_en;
wire clk;
reg [15 : 0] dout;
assign clk = CK;
assign DO = dout;
assign addr = AD;
assign din = DI;
assign write_en = {WE & MASKWE[2], WE & MASKWE[0]};
reg [15 : 0] mem[(1<<14)-1:0];
genvar i;
generate
for (i = 0; i < 2; i = i + 1) begin : gen_proc
always @(posedge clk) begin
if (write_en[i]) begin
mem[(addr)][8*(i+1)-1 : 8*i] <= din[8*(i+1)-1 : 8*i];
end
end
end
endgenerate
always @(posedge clk) begin
dout <= mem[addr];
end
endmodule
| 6.962635 |
module xilinx_single_port_ram_write_first #(
parameter RAM_WIDTH = 32, // Specify RAM data width
parameter RAM_DEPTH = 1024, // Specify RAM depth (number of entries)
parameter INIT_FILE = "" // Specify name/location of RAM initialization file if using one (leave blank if not)
) (
input [clogb2(RAM_DEPTH-1)-1:0] addra, // Address bus, width determined from RAM_DEPTH
input [RAM_WIDTH-1:0] dina, // RAM input data
input clka, // Clock
input wea, // Write enable
input ena, // RAM Enable, for additional power savings, disable port when not in use
output [RAM_WIDTH-1:0] douta // RAM output data
);
reg [RAM_WIDTH-1:0] BRAM[RAM_DEPTH-1:0];
reg [RAM_WIDTH-1:0] ram_data = {RAM_WIDTH{1'b0}};
// The following code either initializes the memory values to a specified file or to all zeros to match hardware
generate
if (INIT_FILE != "") begin : use_init_file
initial $readmemh(INIT_FILE, BRAM, 0, RAM_DEPTH - 1);
end else begin : init_bram_to_zero
integer ram_index;
initial
for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1)
BRAM[ram_index] = {RAM_WIDTH{1'b0}};
end
endgenerate
always @(posedge clka)
if (!ena)
if (!wea) begin
BRAM[addra] <= dina;
ram_data <= dina;
end else ram_data <= BRAM[addra];
assign douta = ram_data;
// The following function calculates the address width based on specified RAM depth
function integer clogb2;
input integer depth;
for (clogb2 = 0; depth > 0; clogb2 = clogb2 + 1) depth = depth >> 1;
endfunction
endmodule
| 10.742794 |
module SP32B1024 (
output [31:0] Q,
input CLK,
input CEN,
input WEN,
input [9:0] A,
input [31:0] D
);
xilinx_single_port_ram_write_first #(
.RAM_WIDTH(32), // Specify RAM data width
.RAM_DEPTH(1024), // Specify RAM depth (number of entries)
.INIT_FILE("") // Specify name/location of RAM initialization file if using one (leave blank if not)
) your_instance_name (
.addra(A), // Address bus, width determined from RAM_DEPTH
.dina (D), // RAM input data, width determined from RAM_WIDTH
.clka (CLK), // Clock
.wea (WEN), // Write enable
.ena (CEN), // RAM Enable, for additional power savings, disable port when not in use
.douta(Q) // RAM output data, width determined from RAM_WIDTH
);
endmodule
| 6.523259 |
module Testbench ();
wire [9:0][23:0] strip;
reg [3:0] op_code;
reg clk;
reg [4:0] i;
wire [2:0] brightness;
BreadBoard BB (
.clk(clk),
.op_code(op_code),
.strip(strip),
.brightness(brightness)
);
initial begin
forever begin
clk = 0;
#5;
clk = 1;
#5;
end
end
initial begin
op_code = 4'b0001; //Turn On System
#100;
op_code = 4'b0000; // back to no_op
op_code = 4'b0010; //To Flashing Color
#100;
op_code = 4'b0000; // back to no_op
op_code = 4'b0010; // To rainbow
#100;
op_code = 4'b0000; // back to no_op
op_code = 4'b0010; //Test mode Overflow
#100;
op_code = 4'b0000; // back to no_op
op_code = 4'b0010; //Test mode Overflow
#100;
op_code = 4'b0000; // back to no_op
/*
op_code = 4'b0100; //Next color
#100;
op_code = 4'b0000; // back to no_op
op_code = 4'b0100; //Next color
#100;
op_code = 4'b0000; // back to no_op
op_code = 4'b0100; //Next color
#100;
op_code = 4'b0000; // back to no_op
op_code = 4'b0100; //Next color
#100;
op_code = 4'b0000; // back to no_op
op_code = 4'b0101; //Prev color
#100;
op_code = 4'b0000; // back to no_op
op_code = 4'b0101; //Prev color, will have same result as last one because we only memerize one last color.
#100;
op_code = 4'b0000; // back to no_op
op_code = 4'b0110; //Bri up
#100;
op_code = 4'b0000; // back to no_op
op_code = 4'b0110; //Bri up
#100;
op_code = 4'b0000; // back to no_op
op_code = 4'b0111; //Bri down
#100;
op_code = 4'b0000; // back to no_op
op_code = 4'b0111; //Bri down
#100;
op_code = 4'b0000; // back to no_op
op_code = 4'b0111; //Bri down
#100;
op_code = 4'b0000; // back to no_op
*/
op_code = 4'b1111; //set to color 8
#100;
op_code = 4'b0000; // back to no_op
op_code = 4'b1101; //set to color 6
#100;
op_code = 4'b0000; // back to no_op
op_code = 4'b1100; //set to color 5
#100;
op_code = 4'b0000; // back to no_op
$finish;
end
endmodule
| 6.722871 |
module BreadBoard (
clk,
op_code,
strip,
brightness
);
output [9:0][23:0] strip;
output [2:0] brightness;
input [3:0] op_code;
input clk;
wire [1:0] mode;
wire [2:0] color_code;
reg [4:0] i;
wire [2:0] brightness_mux_out;
wire [1:0] mode_mux_out;
wire [2:0] color_mux_out;
wire [9:0][23:0] strip_out;
Brightness_mux Mux1 (
op_code,
brightness_mux_out
);
Mode_mux Mux2 (
op_code,
mode_mux_out
);
Color_mux Mux3 (
op_code,
color_mux_out
);
Strip_mux Mux4 (
op_code,
mode,
color_code,
clk,
strip_out
);
assign brightness = brightness_mux_out;
assign mode = mode_mux_out;
assign color_code = color_mux_out;
assign strip = strip_out;
always @(op_code) begin
#10;
$display("OP_CODE:%d, Mode:%d, Color Set:%d, Brightness:%d.", op_code, mode, color_code,
brightness);
for (i = 0; i < 5; i++) begin
#10;
$display("Iteration %2d", i + 1);
$display("[%d, %d, %d]", strip[0][23:16], strip[0][15:8], strip[0][7:0]);
$display("[%d, %d, %d]", strip[1][23:16], strip[1][15:8], strip[1][7:0]);
$display("[%d, %d, %d]", strip[2][23:16], strip[2][15:8], strip[2][7:0]);
$display("[%d, %d, %d]", strip[3][23:16], strip[3][15:8], strip[3][7:0]);
$display("[%d, %d, %d]", strip[4][23:16], strip[4][15:8], strip[4][7:0]);
$display("[%d, %d, %d]", strip[5][23:16], strip[5][15:8], strip[5][7:0]);
$display("[%d, %d, %d]", strip[6][23:16], strip[6][15:8], strip[6][7:0]);
$display("[%d, %d, %d]", strip[7][23:16], strip[7][15:8], strip[7][7:0]);
$display("[%d, %d, %d]", strip[8][23:16], strip[8][15:8], strip[8][7:0]);
$display("[%d, %d, %d]", strip[9][23:16], strip[9][15:8], strip[9][7:0]);
end
$display("\n");
end
endmodule
| 6.725321 |
module DFF (
clk
);
input clk;
always @(posedge clk) $display("clk tking.");
endmodule
| 8.191977 |
module get_solid_color (
color_code,
solid_color
);
wire [7:0][23:0] channels; //8 solid color
input [2:0] color_code;
output reg [23:0] solid_color;
assign channels[0] = 24'b11111111_00000000_00000000; //red
assign channels[1] = 24'b00000000_11111111_00000000; //green
assign channels[2] = 24'b00000000_00000000_11111111; //blue
assign channels[3] = 24'b11111111_11111111_00000000; //yellow
assign channels[4] = 24'b11111111_01100100_00000000; //orange
assign channels[5] = 24'b11111111_00000000_11111111; //pink
assign channels[6] = 24'b01100100_00000000_11111111; //purple
assign channels[7] = 24'b11111111_11111111_11111111; //white
always @(*) begin
solid_color = channels[color_code];
end
endmodule
| 7.164143 |
module Testbench ();
parameter command = -1;
wire [9:0][23:0] strip;
reg [3:0] op_code;
reg clk;
reg [4:0] i;
wire [2:0] brightness;
reg [3:0] in;
integer inFile;
integer outFile;
BreadBoard BB (
.clk(clk),
.op_code(op_code),
.strip(strip),
.brightness(brightness)
);
initial begin
forever begin
clk = 0;
#5;
clk = 1;
#5;
end
end
initial begin
outFile = $fopen("command_history.txt", "a");
$fdisplay(outFile, "%b", command); //write as binary
$fclose(outFile);
inFile = $fopen("command_history.txt", "r");
op_code = 4'b0001; //Turn On System
#100;
op_code = 4'b0000; // back to no_op
#10;
while (!$feof(
inFile
) && $fscanf(
inFile, "%b\n", in
)) begin
op_code = in;
#100;
op_code = 4'b0000;
#10;
end
$fclose(inFile);
$finish;
end
endmodule
| 6.722871 |
module BreadBoard (
clk,
op_code,
strip,
brightness
);
output [9:0][23:0] strip;
output [2:0] brightness;
input [3:0] op_code;
input clk;
wire [1:0] mode;
wire [2:0] color_code;
reg [4:0] i;
wire [2:0] brightness_mux_out;
wire [1:0] mode_mux_out;
wire [2:0] color_mux_out;
wire [9:0][23:0] strip_out;
integer outColors;
Brightness_mux Mux1 (
op_code,
brightness_mux_out
);
Mode_mux Mux2 (
op_code,
mode_mux_out
);
Color_mux Mux3 (
op_code,
color_mux_out
);
Strip_mux Mux4 (
op_code,
mode,
color_code,
clk,
strip_out
);
assign brightness = brightness_mux_out;
assign mode = mode_mux_out;
assign color_code = color_mux_out;
assign strip = strip_out;
always @(op_code) begin
$display("OP_CODE:%d, Mode:%d, Color Set:%d, Brightness:%d.", op_code, mode, color_code,
brightness);
outColors = $fopen("./LED_COLORS.txt", "w");
$fdisplay(outColors, "%d %d %d %d", op_code, mode, color_code, brightness);
for (i = 0; i < 10; i++) begin
#10;
/*
$display("Iteration %2d", i+1);
$display ("[%h, %h, %h]", strip[0][23:16], strip[0][15:8], strip[0][7:0]);
$display ("[%h, %h, %h]", strip[1][23:16], strip[1][15:8], strip[1][7:0]);
$display ("[%h, %h, %h]", strip[2][23:16], strip[2][15:8], strip[2][7:0]);
$display ("[%h, %h, %h]", strip[3][23:16], strip[3][15:8], strip[3][7:0]);
$display ("[%h, %h, %h]", strip[4][23:16], strip[4][15:8], strip[4][7:0]);
$display ("[%h, %h, %h]", strip[5][23:16], strip[5][15:8], strip[5][7:0]);
$display ("[%h, %h, %h]", strip[6][23:16], strip[6][15:8], strip[6][7:0]);
$display ("[%h, %h, %h]", strip[7][23:16], strip[7][15:8], strip[7][7:0]);
$display ("[%h, %h, %h]", strip[8][23:16], strip[8][15:8], strip[8][7:0]);
$display ("[%h, %h, %h]", strip[9][23:16], strip[9][15:8], strip[9][7:0]);
*/
$fdisplay(outColors, "Iteration %2d", i + 1);
$fdisplay(outColors, "%h", strip[0]);
$fdisplay(outColors, "%h", strip[1]);
$fdisplay(outColors, "%h", strip[2]);
$fdisplay(outColors, "%h", strip[3]);
$fdisplay(outColors, "%h", strip[4]);
$fdisplay(outColors, "%h", strip[5]);
$fdisplay(outColors, "%h", strip[6]);
$fdisplay(outColors, "%h", strip[7]);
$fdisplay(outColors, "%h", strip[8]);
$fdisplay(outColors, "%h", strip[9]);
/*
$display ("Iteration %2d", i+1);
$display ( "%h", strip[0]);
$display ( "%h", strip[1]);
$display ( "%h", strip[2]);
$display ( "%h", strip[3]);
$display ( "%h", strip[4]);
$display ( "%h", strip[5]);
$display ( "%h", strip[6]);
$display ( "%h", strip[7]);
$display ( "%h", strip[8]);
$display ( "%h", strip[9]);
*/
end
$fclose(outColors);
$display("\n");
end
endmodule
| 6.725321 |
module DFF (
clk
);
input clk;
always @(posedge clk) $display("clk tking.");
endmodule
| 8.191977 |
module get_solid_color (
color_code,
solid_color
);
wire [7:0][23:0] channels; //8 solid color
input [2:0] color_code;
output reg [23:0] solid_color;
assign channels[0] = 24'b11111111_00000000_00000000; //red
assign channels[1] = 24'b00000000_11111111_00000000; //green
assign channels[2] = 24'b00000000_00000000_11111111; //blue
assign channels[3] = 24'b11111111_11111111_00000000; //yellow
assign channels[4] = 24'b11111111_01100100_00000000; //orange
assign channels[5] = 24'b11111111_00000000_11111111; //pink
assign channels[6] = 24'b01100100_00000000_11111111; //purple
assign channels[7] = 24'b11111111_11111111_11111111; //white
always @(*) begin
solid_color = channels[color_code];
end
endmodule
| 7.164143 |
module space (
input [9:0] tlx,
input [9:0] tly,
input [9:0] brx,
input [9:0] bry,
input rst,
input change,
input [9:0] x,
input [9:0] y,
input [1:0] nextmode,
output [9:0] lx,
output [9:0] ly,
output xyin,
output [1:0] mode
);
reg [1:0] state; //00 -> empty, 01 -> x, 10 -> o, 11 -> invalid
always @(posedge change, negedge rst) begin
if (~rst) begin
state <= 2'b00;
end else if (change) begin
state <= nextmode;
end
end
assign mode = state;
assign xyin = (x > tlx && x < brx && y > tly && y < bry) ? 1'b1 : 1'b0;
assign lx = x - tlx;
assign ly = y - tly;
endmodule
| 6.743672 |
module spaced_2lvl_penc #(
parameter INPUT_WIDTH = 8192,
parameter PENC1_SIZE = 32,
parameter PENC2_SIZE = 32,
parameter BIN_COUNT = 8,
parameter LARGE_BLOCK = BIN_COUNT*PENC1_SIZE*PENC2_SIZE,
parameter OUTPUT_WIDTH = $clog2(LARGE_BLOCK)
) (
input wire clk,
input wire rst,
input wire [INPUT_WIDTH-1:0] one_hot,
output reg [BIN_COUNT*OUTPUT_WIDTH-1:0] index,
output reg [ BIN_COUNT-1:0] valid,
output reg [ BIN_COUNT-1:0] error
);
initial begin
if (LARGE_BLOCK < INPUT_WIDTH) begin
$error("Error: BIN_COUNT is not large enough.");
$finish;
end
end
localparam JUMP = BIN_COUNT * PENC2_SIZE;
localparam PENC1_WIDTH = $clog2(PENC1_SIZE);
localparam PENC2_WIDTH = $clog2(PENC2_SIZE);
localparam BIN_WIDTH = $clog2(BIN_COUNT);
wire [LARGE_BLOCK-1:0] adjusted_input = {{(LARGE_BLOCK - INPUT_WIDTH) {1'b0}}, one_hot};
// Stage 1
reg [PENC1_WIDTH-1:0] lvl1_index[0:JUMP-1];
reg [JUMP-1:0] lvl1_valid;
reg [JUMP-1:0] lvl1_error;
genvar i, j;
generate
for (i = 0; i < JUMP; i = i + 1) begin : lvl1
wire [PENC1_SIZE-1:0] penc1_input;
for (j = 0; j < PENC1_SIZE; j = j + 1) begin : lvl1_reorder
assign penc1_input[j] = adjusted_input[j*JUMP+i];
end
reg [PENC1_WIDTH-1:0] penc1_output;
reg [PENC1_WIDTH-1:0] ones1;
integer k;
always @(*) begin : lvl1_penc
penc1_output = {PENC1_WIDTH{1'b0}};
ones1 = {PENC1_WIDTH{1'b0}};
for (k = PENC1_SIZE - 1; k >= 0; k = k - 1)
if (penc1_input[k]) begin
penc1_output = k;
ones1 = ones1 + 1;
end
end
always @(posedge clk) begin : lvl1_reg
lvl1_index[i] <= penc1_output;
if (rst) begin
lvl1_valid[i] <= 1'b0;
lvl1_error[i] <= 1'b0;
end else begin
lvl1_valid[i] <= |penc1_input;
lvl1_error[i] <= (ones1 > 1);
end
end
end // lvl1 for loop
endgenerate
// Stage 2
reg [PENC2_WIDTH-1:0] second_index [0:BIN_COUNT-1];
reg [ BIN_COUNT-1:0] second_valid;
genvar p, q;
generate
for (p = 0; p < BIN_COUNT; p = p + 1) begin : lvl2
wire [PENC2_SIZE-1:0] penc2_input;
for (q = 0; q < PENC2_SIZE; q = q + 1) begin : lvl2_reorder
assign penc2_input[q] = lvl1_valid[q*BIN_COUNT+p];
end
reg [PENC2_WIDTH-1:0] penc2_output;
reg [PENC2_WIDTH-1:0] ones2;
reg [PENC1_WIDTH-1:0] lvl1_selected_index;
reg lvl1_selected_error;
integer r;
always @(*) begin : lvl2_penc
penc2_output = {PENC2_WIDTH{1'b0}};
ones2 = {PENC2_WIDTH{1'b0}};
lvl1_selected_index = lvl1_index[p];
lvl1_selected_error = lvl1_error[p];
for (r = PENC2_SIZE - 1; r >= 0; r = r - 1)
if (penc2_input[r]) begin
penc2_output = r;
ones2 = ones2 + 1;
lvl1_selected_index = lvl1_index[r*BIN_COUNT+p];
lvl1_selected_error = lvl1_error[r*BIN_COUNT+p];
end
end
always @(posedge clk) begin : lvl1_reg
index[p*OUTPUT_WIDTH+:BIN_WIDTH] <= p;
index[p*OUTPUT_WIDTH+BIN_WIDTH+:PENC2_WIDTH] <= penc2_output;
index[p*OUTPUT_WIDTH+BIN_WIDTH+PENC2_WIDTH+:PENC1_WIDTH] <= lvl1_selected_index;
if (rst) begin
valid[p] <= 1'b0;
error[p] <= 1'b0;
end else begin
valid[p] <= |penc2_input;
error[p] <= (ones2 > 1) | lvl1_selected_error;
end
end
end // lvl2 for loop
endgenerate
endmodule
| 8.176834 |
module SpaceInvaders (
input clk,
input reset,
input btnLeftInput,
input btnRightInput,
input fire,
output [7:0] rgb,
output hSync,
output vSync,
output victory,
output defeat
);
// Parameters :
parameter NB_LIN = 3;
parameter NB_COL = 5;
parameter NB_ALIENS = NB_LIN * NB_COL;
// WIRES
wire [9:0] hPos;
wire [9:0] vPos;
wire [2:0] colorSpaceship;
wire [2:0] colorLaser;
wire [2:0] colorAlien;
wire [2:0] colorOutput;
reg [2:0] colorSum;
wire btnLeftWire;
wire btnRightWire;
wire killingAlien;
wire [9:0] gunPosition;
wire [9:0] xLaser;
wire [9:0] yLaser;
wire enableVga;
wire enableZigZag;
wire enableLaser;
wire [1:0] motion;
wire canLeft;
wire canRight;
wire signed [10:0] xAlien;
wire [9:0] yAlien;
wire [NB_ALIENS-1:0] alive;
TimeUnitEnable #(
.FREQ_WANTED(25000000)
) timeUnitVga (
.clk (clk),
.reset(reset),
.pulse(enableVga)
);
TimeUnitEnable #(
.FREQ_WANTED(100)
) timeUnitZigZag (
.clk (clk),
.reset(reset),
.pulse(enableZigZag)
);
TimeUnitEnable #(
.FREQ_WANTED(300)
) timeUnitLaser (
.clk (clk),
.reset(reset),
.pulse(enableLaser)
);
// MODULES
Button btnLeftModule (
.clk(clk),
.reset(reset),
.pressed(btnLeftInput),
.pulse(btnLeftWire)
);
Button btnRightModule (
.clk(clk),
.reset(reset),
.pressed(btnRightInput),
.pulse(btnRightWire)
);
SpaceShip spaceship (
.clk(clk),
.reset(reset),
.left(btnLeftWire),
.right(btnRightWire),
.hPos(hPos),
.vPos(vPos),
.gunPosition(gunPosition),
.color(colorSpaceship)
);
Laser laser (
.clk(clk),
.reset(reset),
.enable(enableLaser),
.fire(fire),
.killingAlien(killingAlien),
.gunPosition(gunPosition),
.hPos(hPos),
.vPos(vPos),
.xLaser(xLaser),
.yLaser(yLaser),
.colorLaser(colorLaser)
);
ZigZagAlien zigZagAlien (
.clk(clk),
.reset(reset),
.enable(enableZigZag),
.canLeft(canLeft),
.canRight(canRight),
.Motion(motion)
);
AliensMotion #(
.NB_LIN(NB_LIN),
.NB_COL(NB_COL)
) aliensMotion (
.clk(clk),
.reset(reset),
.xLaser(xLaser),
.yLaser(yLaser),
.motion(motion),
.hPos(hPos),
.vPos(vPos),
.killingAlien(killingAlien),
.canLeft(canLeft),
.canRight(canRight),
.victory(victory),
.defeat(defeat),
.xAlien(xAlien),
.yAlien(yAlien),
.alive(alive)
);
ColorAlien #(
.NB_LIN(NB_LIN),
.NB_COL(NB_COL)
) colorAlienUnit (
.hPos(hPos),
.vPos(vPos),
.xAlien(xAlien),
.yAlien(yAlien),
.alive(alive),
.colorAlien(colorAlien)
);
Vga_module vga (
.clk(clk),
.enable(enableVga),
.reset(reset),
.hPos(hPos),
.vPos(vPos),
.hSync(hSync),
.vSync(vSync)
);
FinalColor finalcolor (
.colorInput(colorSum),
.hPos(hPos),
.vPos(vPos),
.color(colorOutput)
);
Rgb rgbUnit (
.color(colorOutput),
.rgb (rgb)
);
always @(posedge clk) begin
colorSum = colorAlien + colorLaser + colorSpaceship;
end
endmodule
| 7.417106 |
module SpaceShip(
input clk,
input reset,
input left,
input right,
input [9:0] hPos,
input [9:0] vPos,
output reg [9:0] gunPosition,
output reg [2:0] color
);
parameter SCREEN_WIDTH = 640 ;
parameter SCREEN_HEIGHT = 480 ;
parameter RADIUS = 30;
parameter SHIP_WIDTH = 60 ; // Width of the ship
parameter SHIP_HEIGHT = 75 ; // Height of the ship
parameter COCKPIT_WIDTH = 10;
parameter COCKPIT_LENGTH = 40;
parameter STEP = 20 ; // Nb pixel for moving the ship
parameter BACKGROUND = 0 ;
parameter SPACESHIP = 1 ;
parameter ALIENS0 = 2 ;
parameter ALIENS1 = 3 ;
parameter ALIENS2 = 4 ;
parameter ALIENS3 = 5 ;
parameter LASER = 6 ;
parameter NONE = 7 ;
parameter RECT_PERCENT = 15 ; // Percentage of the WIDTH
localparam RECT_WIDTH = SHIP_WIDTH*RECT_PERCENT/100;
parameter V_OFFSET = 10 ; // Number of pixels between bottom of the screen and ship
parameter H_OFFSET = 10 ; // Horizontal margin (we don't touch the side of the screen)
localparam NB_PIXELS_DOWN = SCREEN_HEIGHT - SHIP_HEIGHT - H_OFFSET;
always @(posedge clk) begin
// We init our position in the middle of the screen (could be random?)
if (reset) begin
gunPosition <= SCREEN_WIDTH/2;
end
// If we are not already full right :
if (right && gunPosition + SHIP_WIDTH/2 < SCREEN_WIDTH - H_OFFSET) begin
// If we have enough space to take a full step :
if (SCREEN_WIDTH - H_OFFSET - gunPosition + SHIP_WIDTH/2 > STEP) begin
gunPosition <= gunPosition + STEP ;
end
// Otherwise, we stick to the side - offset :
else gunPosition <= SCREEN_WIDTH - H_OFFSET - SHIP_WIDTH/2 ;
end
// Same on the left
if (left && gunPosition - SHIP_WIDTH/2 > H_OFFSET) begin
if (gunPosition - SHIP_WIDTH/2 - H_OFFSET > STEP) begin
gunPosition <= gunPosition - STEP ;
end
else gunPosition <= H_OFFSET + SHIP_WIDTH/2 ;
end
// We now need to manage the color, meaning we have to compute our ship's shape
// First, we check if vPos and hPos are where our ship is
if ((gunPosition - hPos)*(gunPosition - hPos) + (SCREEN_HEIGHT - SHIP_HEIGHT/2 - vPos)*(SCREEN_HEIGHT - SHIP_HEIGHT/2 - vPos) < RADIUS) begin
color <= SPACESHIP;
end
else if (hPos >= gunPosition + RADIUS - COCKPIT_WIDTH && hPos <= gunPosition + RADIUS && vPos >= SCREEN_HEIGHT - V_OFFSET - RADIUS && vPos <= SHIP_HEIGHT) begin
color <= SPACESHIP;
end
else if ((hPos <= gunPosition - 5 && hPos >= gunPosition - RADIUS) || (hPos >= gunPosition + 5 && hPos <= gunPosition + RADIUS) ) begin
if (vPos <= SCREEN_HEIGHT - SHIP_HEIGHT/2 && vPos >= SCREEN_HEIGHT - SHIP_HEIGHT) begin
if (hPos > (gunPosition - (vPos-NB_PIXELS_DOWN)) || hPos < gunPosition + (vPos-NB_PIXELS_DOWN)) ) begin
color <= SPACESHIP;
end
end
end
else color <= BACKGROUND;
end
endmodule
| 7.157699 |
module planet_status (
clock,
planet_hit,
game_state,
status,
War
);
/***************************************************************
DEFINING INPUTS AND OUTPUTS
***************************************************************/
input clock;
//50MHz clock for registers
input planet_hit;
//1 if the planet was just hit
input [1:0] game_state;
//current game state
input War;
// war gamemode
output reg [1:0] status;
//the status of the planet
reg [5:0] war_counter;
//counter for war mod health
/***************************************************************
PARAMETERS
***************************************************************/
parameter[1:0] MENU= 2'b00, PLAY = 2'b01, GAMEOVER_VICTORY_RIGHT = 2'b10 , GAMEOVER_VICTORY_LEFT = 2'b11 ;
//game states
parameter [1:0] SHIELD = 2'b00, NO_SHIELD = 2'b01, DAMAGED = 2'b10, DEAD = 2'b11;
//planet state
/***************************************************************
PLANET STATUS LOGIC
***************************************************************/
always @(posedge clock) begin
if (game_state != PLAY) begin
status <= SHIELD;
war_counter <= 6'd20;
//reset the status
end else if (status != DEAD && planet_hit) begin
if (War) begin
if (war_counter > 6'd0) war_counter <= war_counter - 6'd1;
if ((war_counter > 6'd10)) status <= SHIELD;
else if ((war_counter > 6'd5)) status <= NO_SHIELD;
else if ((war_counter > 6'd0)) status <= DAMAGED;
else begin
status <= DEAD;
end
end else begin
status <= status + 1'b1;
//increase the damage by one
end
end
/*else begin // commented code starts here (original code)
if (planet_hit && status != DEAD) begin
status <= status + 1'b1;
//increase the damage by one
end
end*/
end
endmodule
| 6.524642 |
module gamestate_fsm (
clock_50M,
left_planet_status,
right_planet_status,
st1,
st2,
game_state,
score_resetn,
earth_score_counter,
mars_score_counter,
earth_defense
);
/***************************************************************
DEFINING INPUTS AND OUTPUTS
***************************************************************/
input clock_50M; //50MHz clock
input [1:0] left_planet_status, right_planet_status; //status of the left and right planets
input st1, st2; //user input on the 'start' buttons
input score_resetn; //resets the score counters
input earth_defense;
output [1:0] game_state;
//current game state
output reg [7:0] earth_score_counter = 8'b0;
output reg [7:0] mars_score_counter = 8'b0;
//score counters
/***************************************************************
DEFINING LOCAL SIGNALS
***************************************************************/
parameter[1:0] MENU= 2'b00, PLAY = 2'b01, GAMEOVER_VICTORY_RIGHT = 2'b10 , GAMEOVER_VICTORY_LEFT = 2'b11 ;
//game states
parameter [1:0] SHIELD = 2'b00, NO_SHIELD = 2'b01, DAMAGED = 2'b10, DEAD = 2'b11;
//planet state
parameter [7:0] MAX_SCORE_COUNT = 8'd99;
//maximum possible score
reg [1:0] y_curr = MENU;
reg [1:0] Y_next = MENU;
//current and next states
/***************************************************************
STATE TABLE
***************************************************************/
always @(*) begin
case (y_curr)
MENU: begin //if both players press start, play. Else, stay in current state
if (st2 || st1) Y_next = PLAY;
else Y_next = MENU;
end
PLAY: begin
if (left_planet_status == DEAD) Y_next = GAMEOVER_VICTORY_RIGHT;
//the left planet is dead, so the right player won
else if (right_planet_status == DEAD) Y_next = GAMEOVER_VICTORY_LEFT;
//the right planet is dead, so the left player won
else
Y_next = PLAY;
//no winner yet, so keep playing
end
GAMEOVER_VICTORY_LEFT: begin //if both players press start, play. Else, stay in current state
if (st2 || st1) Y_next = PLAY;
else Y_next = GAMEOVER_VICTORY_LEFT;
end
GAMEOVER_VICTORY_RIGHT: begin //if both players press start, play. Else, stay in current state
if (st2 || st1) Y_next = PLAY;
else Y_next = GAMEOVER_VICTORY_RIGHT;
end
endcase
end
/***************************************************************
STATE REGISTERS
***************************************************************/
always @(posedge clock_50M) begin
y_curr <= Y_next;
end
/***************************************************************
ASSIGN OUTPUTS
***************************************************************/
assign game_state = y_curr;
/***************************************************************
SCORE COUNTER
***************************************************************/
always @(posedge clock_50M) begin
if (~score_resetn || earth_defense) begin // if game mode changes also reset, when we get there
earth_score_counter <= 8'b0;
mars_score_counter <= 8'b0;
end
if ((Y_next == GAMEOVER_VICTORY_LEFT) && (y_curr == PLAY)) begin
if (mars_score_counter < MAX_SCORE_COUNT) mars_score_counter <= mars_score_counter + 1'b1;
end
if ((Y_next == GAMEOVER_VICTORY_RIGHT) && (y_curr == PLAY)) begin
if (earth_score_counter < MAX_SCORE_COUNT) earth_score_counter <= earth_score_counter + 1'b1;
end
end
endmodule
| 7.338756 |
module get60HzClock (
clock50MHz,
clock60Hz
);
input clock50MHz;
output reg clock60Hz;
parameter [19:0] TICKS = 20'd833333;
reg [19:0] cnt = 20'b0;
always @(posedge clock50MHz) begin
if (cnt == TICKS) begin
clock60Hz <= 1'b1;
cnt <= 20'b0;
end else begin
clock60Hz <= 1'b0;
cnt <= cnt + 1;
end
end
endmodule
| 7.011083 |
module nes_fsm (
clock,
clock60hz,
clock6us,
latch,
pulse,
data,
a,
b,
sel,
st,
up,
down,
left,
right
);
input clock, clock60hz, clock6us;
output latch, pulse;
input data;
output a, b, sel, st, up, down, left, right;
parameter[2:0] WAIT=3'b000, LATCH=3'b001, LATCH2=3'b010, READ=3'b011, INCR=3'b100, PULSE_LOW=3'b101, PULSE_HIGH=3'b110;
reg [2:0] y_curr = 3'b0;
reg [2:0] Y_next = 3'b0;
wire counter_is_done;
always @(*) begin
case (y_curr)
WAIT: begin
if (clock60hz) Y_next = LATCH;
else Y_next = WAIT;
end
LATCH: begin
if (clock6us) Y_next = LATCH2;
else Y_next = LATCH;
end
LATCH2: begin
if (clock6us) Y_next = READ;
else Y_next = LATCH2;
end
READ: begin
Y_next = INCR;
end
INCR: begin
Y_next = PULSE_LOW;
end
PULSE_LOW: begin
if (counter_is_done) Y_next = WAIT;
else if (clock6us) Y_next = PULSE_HIGH;
else Y_next = PULSE_LOW;
end
PULSE_HIGH: begin
if (clock6us) Y_next = READ;
else Y_next = PULSE_HIGH;
end
default: Y_next = WAIT;
endcase
end
//state regs
always @(posedge clock) begin
y_curr <= Y_next;
end
nes_datapath nes_dp (
y_curr,
latch,
pulse,
data,
counter_is_done,
clock,
a,
b,
sel,
st,
up,
down,
left,
right
);
endmodule
| 6.539374 |
module hex_decoder (
hex_out,
val
);
input [3:0] val;
output [7:0] hex_out;
mux16to1 u0 (
1'b0,
1,
0,
0,
1,
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
0,
val[0],
val[1],
val[2],
val[3],
hex_out[0]
);
mux16to1 u1 (
1'b0,
0,
0,
0,
0,
1,
1,
0,
0,
0,
0,
1,
1,
0,
1,
1,
val[0],
val[1],
val[2],
val[3],
hex_out[1]
);
mux16to1 u2 (
1'b0,
0,
1,
0,
0,
0,
0,
0,
0,
0,
0,
0,
1,
0,
1,
1,
val[0],
val[1],
val[2],
val[3],
hex_out[2]
);
mux16to1 u3 (
1'b0,
1,
0,
0,
1,
0,
0,
1,
0,
1,
1,
0,
0,
0,
0,
1,
val[0],
val[1],
val[2],
val[3],
hex_out[3]
);
mux16to1 u4 (
1'b0,
1,
0,
1,
1,
1,
0,
1,
0,
1,
0,
0,
0,
0,
0,
0,
val[0],
val[1],
val[2],
val[3],
hex_out[4]
);
mux16to1 u5 (
1'b0,
1,
1,
1,
0,
0,
0,
1,
0,
0,
0,
0,
0,
1,
0,
0,
val[0],
val[1],
val[2],
val[3],
hex_out[5]
);
mux16to1 u6 (
1'b1,
1,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
1,
0,
0,
0,
val[0],
val[1],
val[2],
val[3],
hex_out[6]
);
endmodule
| 7.584821 |
module mux16to1 (
x1,
x2,
x3,
x4,
x5,
x6,
x7,
x8,
x9,
x10,
x11,
x12,
x13,
x14,
x15,
x16,
s1,
s2,
s3,
s4,
out
);
input x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, s1, s2, s3, s4;
output out;
wire connect1, connect2;
mux8to1 u0 (
.x1 (x1),
.x2 (x2),
.x3 (x3),
.x4 (x4),
.x5 (x5),
.x6 (x6),
.x7 (x7),
.x8 (x8),
.s1 (s1),
.s2 (s2),
.s3 (s3),
.out(connect1)
);
mux8to1 u1 (
.x1 (x9),
.x2 (x10),
.x3 (x11),
.x4 (x12),
.x5 (x13),
.x6 (x14),
.x7 (x15),
.x8 (x16),
.s1 (s1),
.s2 (s2),
.s3 (s3),
.out(connect2)
);
mux2to1 u2 (
.x(connect1),
.y(connect2),
.s(s4),
.m(out)
);
endmodule
| 7.318793 |
module mux8to1 (
x1,
x2,
x3,
x4,
x5,
x6,
x7,
x8,
s1,
s2,
s3,
out
);
input x1, x2, x3, x4, x5, x6, x7, x8, s1, s2, s3;
output out;
wire connect1, connect2;
mux4to1 u0 (
.x1 (x1),
.x2 (x2),
.x3 (x3),
.x4 (x4),
.s1 (s1),
.s2 (s2),
.out(connect1)
);
mux4to1 u1 (
.x1 (x5),
.x2 (x6),
.x3 (x7),
.x4 (x8),
.s1 (s1),
.s2 (s2),
.out(connect2)
);
mux2to1 u2 (
.x(connect1),
.y(connect2),
.s(s3),
.m(out)
);
endmodule
| 7.465042 |
module mux4to1 (
x1,
x2,
x3,
x4,
s1,
s2,
out
);
input x1, x2, x3, x4, s1, s2;
output out;
wire connect1, connect2;
mux2to1 u0 (
.x(x1),
.y(x2),
.s(s1),
.m(connect1)
);
mux2to1 u1 (
.x(x3),
.y(x4),
.s(s1),
.m(connect2)
);
mux2to1 u2 (
.x(connect1),
.y(connect2),
.s(s2),
.m(out)
);
endmodule
| 7.010477 |
module mux2to1 (
x,
y,
s,
m
);
input x; //select 0
input y; //select 1
input s; //select signal
output m; //output
//assign m = s & y | ~s & x;
// OR
assign m = s ? y : x;
endmodule
| 7.107199 |
module spaceinvaders (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
LEDR,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B // VGA Blue[9:0]
);
input CLOCK_50; // 50 MHz
input [9:0] SW;
input [3:0] KEY;
output [9:0] LEDR;
output reg [6:0] HEX5, HEX4, HEX3, HEX2, HEX1, HEX0;
// Declare your inputs and outputs here
// Do not change the following outputs
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK_N; // VGA BLANK
output VGA_SYNC_N; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
wire resetn;
assign resetn = ~KEY[0];
// Create the colour, x, y and writeEn wires that are inputs to the controller.
wire [2:0] colour;
wire [7:0] x;
wire [7:0] y;
wire writeEn;
wire rd_out;
wire fire;
wire [7:0] alienX;
wire [7:0] alienY;
wire [7:0] cannonX;
wire [7:0] cannonY;
wire [7:0] shotX;
wire [7:0] shotY;
wire [14:0] alive;
reg [14:0] sum;
// assign sum = (~alive[0] + ~alive[1] + ~alive[2] + ~alive[3] + ~alive[4] + ~alive[5] + ~alive[6] + ~alive[7] + ~alive[8] + ~alive[9] + ~alive[10] + ~alive[11] + ~alive[12] + ~alive[13] + ~alive[14]);
wire reset_shot;
wire player_alive;
always @(*) begin
if (~player_alive) begin
// LEDR[8:0] <= 10'b1111111111;
HEX0[6:0] <= 7'b0000110;
HEX1[6:0] <= 7'b0010010;
HEX2[6:0] <= 7'b1000000;
HEX3[6:0] <= 7'b1000111;
HEX4[6:0] <= 7'b1111111;
HEX5[6:0] <= 7'b1000001;
end else begin
// LEDR[8:0] <= 0;
HEX0[6:0] <= 7'b1111111;
HEX1[6:0] <= 7'b1111111;
HEX2[6:0] <= 7'b1111111;
HEX3[6:0] <= 7'b1111111;
HEX4[6:0] <= 7'b1111111;
HEX5[6:0] <= 7'b1111111;
end
end
// Create an Instance of a VGA controller - there can be only one!
// Define the number of colours as well as the initial background
// image file (.MIF) for the controller.
vga_adapter VGA (
.resetn(~resetn),
.clock(CLOCK_50),
.colour(colour),
.x(x),
.y(y),
.plot(writeEn),
/* Signals for the DAC to drive the monitor. */
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK)
);
defparam VGA.RESOLUTION = "160x120"; defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1; defparam VGA.BACKGROUND_IMAGE = "black.mif";
cannon cann (
CLOCK_50,
~resetn,
~KEY[2],
~KEY[1],
~KEY[3],
player_alive,
cannonX,
cannonY,
fire
);
aliens als (
CLOCK_50,
~resetn,
player_alive,
alienX,
alienY
);
shot_handler sh (
CLOCK_50,
~resetn,
~reset_shot,
cannonX,
cannonY,
fire,
shotX,
shotY,
LEDR[9]
);
collision coll (
CLOCK_50,
~resetn,
alienX,
alienY,
shotX,
shotY,
cannonX,
cannonY,
alive,
player_alive,
reset_shot
);
render renderAll (
CLOCK_50,
rd_out,
~resetn,
shotX,
shotY,
cannonX,
cannonY,
alienX,
alienY,
alive,
sum,
~player_alive,
x,
y,
writeEn,
colour
);
counterDraw cd1 (
CLOCK_50,
~resetn,
rd_out
);
always @(posedge CLOCK_50) begin
if (resetn) begin
sum <= 0;
end else if (reset_shot) begin
sum <= sum + 125;
end
end
endmodule
| 7.385663 |
module counterDraw (
input clock,
input reset,
output reg q
);
reg [21:0] count;
always @(posedge clock) begin
if (!reset) begin
count <= 22'd0;
q <= 1'd0;
end else begin
if (count < 24'b111101000010010000000) begin
// if(count < 20'd10000) begin
count <= count + 1'd1;
q <= 1'd0;
end else begin
count <= 22'd0;
q <= 1'd1;
end
end
end
endmodule
| 6.950832 |
module space_start (
input clk,
input rst,
input ext,
input [7:0] keycode,
input make,
output reg startGame
);
parameter SPACE = 8'h29;
initial startGame <= 0;
always @(posedge clk)
if (rst) startGame <= 0;
else
case (keycode)
SPACE: startGame <= 1;
default: startGame <= 0; //continues in previously selected direction
endcase
endmodule
| 7.096019 |
module space_vector_modulator #(
parameter current_bits = 4,
parameter microstep_bits = 8,
parameter phase_ct_bits = 8,
parameter center_aligned = 1,
parameter phases = 2,
parameter microsteps = 64
) (
input clk,
input resetn,
input pwm_clk,
output [phases-1:0] vref_pwm,
//output [phases*(current_bits+microstep_bits)-1:0] vref_val,
input [current_bits-1:0] current, // also called Phase Vector amplitude
input [phase_ct_bits-1:0] phase_ct // Represents 0 -> 2pi integer range
);
// center aligned delay only possible with phases > 1
localparam can_delay = center_aligned && phases > 1;
// microsteps commonly means quarter-wave resolution
// however we store a half wave to get a true zero PWM crossing
localparam integer phase_table_end = microsteps * 2 - 1;
// Table of phase agnles (BRAM on FPGA)
reg [microstep_bits-1:0] phase_table[0:phase_table_end];
// Initialize sine table into BRAM
localparam real pi = 3.1415926535897;
integer i;
initial begin
for (i = 0; i <= phase_table_end; i = i + 1) begin
phase_table[i] <= $sin(pi * i / (phase_table_end + 1)) * (2.0 ** microstep_bits - 1);
end
end
// sine value based on phase location (retrieved from BRAM)
reg [microstep_bits-1:0] phase[phases-1:0];
// sine value scaled by the current
wire [microstep_bits+current_bits-1:0] pwm[phases-1:0];
genvar ig;
generate
for (ig = 0; ig < phases; ig = ig + 1) begin
assign pwm[ig] = phase[ig] * current;
end
endgenerate
//assign vref_val = {pwm[0], pwm[1]};
// PWM Types:
//
// Center Aligned
// A: ___|-------|____
// B: ______|-|_______
//
// Normal
// A: ___|-------|____
// B: ___|-|__________
wire [microstep_bits+current_bits-2:0] pwm_delay[phases-1:0];
if (can_delay) begin
// Determine delay for center aligned PWM
// Center Aligned
// A: |-------|____
// B: ___|-|_______
// C: _|-----|_____
// For the above:
// Delay A: 0
// Delay B: (A-B)/2
// Delay C: (A-C)/2
// Where A == Max(A,B,C)
if (phases == 2) begin
assign pwm_delay[0] = (pwm[0] >= pwm[1]) ? 0 : (pwm[1] - pwm[0]) >> 1;
assign pwm_delay[1] = (pwm[1] >= pwm[0]) ? 0 : (pwm[0] - pwm[1]) >> 1;
end
if (phases == 3) begin
// TODO
assign pwm_delay[0] = (pwm[0] >= pwm[1]) ? 0 : (pwm[1] - pwm[0]) >> 1;
assign pwm_delay[1] = (pwm[1] >= pwm[0]) ? 0 : (pwm[0] - pwm[1]) >> 1;
end
end
// Microstep*current -> vector angle voltage reference
// Center aligned for better response characteristics if available/selected
for (ig = 0; ig < phases; ig = ig + 1) begin
pwm #(
.bits(microstep_bits + current_bits),
.delayed(can_delay)
) mb (
.clk(pwm_clk),
.resetn(resetn),
.val(pwm[ig]),
.delay(pwm_delay[ig]),
.pwm(vref_pwm[ig])
);
end
localparam idx_end = phase_ct_bits - 2; //
wire [idx_end:0] phase_idx = phase_ct[idx_end:0];
always @(posedge clk) begin
if (resetn) begin
// Load sine/cosine from RAM
if (phases == 1) begin
phase[1] <= phase_table[phase_idx];
end
if (phases == 2) begin
phase[0] <= phase_table[phase_idx];
phase[1] <= phase_table[phase_idx+microsteps];
end
if (phases == 3) begin
phase[0] <= phase_table[phase_idx+microsteps/3];
phase[1] <= phase_table[phase_idx+microsteps*2/3];
phase[3] <= phase_table[phase_idx];
end
end
end
endmodule
| 7.24844 |
modules
//------------------------------------------------------------------------------
module space_wire_sync_one_pulse
(
input wire i_clk,
input wire i_async_clk,
input wire i_reset_n,
input wire i_async_in,
output wire o_sync_out
);
//------------------------------------------------------------------------------
reg latched_async;
reg sync_reg;
reg sync_clear;
reg sync_out;
//------------------------------------------------------------------------------
//---
//---
//---
//------------------------------------------------------------------------------
// Synchronize the asynchronous One Shot Pulse to Clock.
//------------------------------------------------------------------------------
assign o_sync_out = sync_out;
//------------------------------------------------------------------------------
//---
//---
//---
//==============================================================================
// latch the rising edge of the input signal.
//==============================================================================
always @(posedge i_async_in or negedge i_reset_n or posedge sync_clear)
begin : s_latched_async
if ( !i_reset_n | sync_clear )
begin
latched_async <= 1'b0;
end
else
begin
latched_async <= 1'b1;
end
end
//------------------------------------------------------------------------------
//---
//---
//---
//==============================================================================
// Synchronize a latch signal to Clock.
//==============================================================================
always @(posedge i_clk or negedge i_reset_n or posedge sync_clear)
begin : s_sync_reg
if ( !i_reset_n | sync_clear )
begin
sync_reg <= 1'b0;
end
else
begin
if ( latched_async )
begin
sync_reg <= 1'b1;
end
end
end
//------------------------------------------------------------------------------
//---
//---
//---
//==============================================================================
// Output Clock synchronized One_Shot_Pulse and clear signal.
//==============================================================================
always @(posedge i_clk or negedge i_reset_n)
begin : s_sync_clear_and_out
if ( !i_reset_n )
begin
sync_out <= 1'b0;
sync_clear <= 1'b0;
end
else
begin
if ( sync_reg & !sync_clear )
begin
sync_out <= 1'b1;
sync_clear <= 1'b1;
end
else if ( sync_reg )
begin
sync_out <= 1'b0;
sync_clear <= 1'b0;
end
else
begin
sync_out <= 1'b0;
sync_clear <= 1'b0;
end
end
end
//------------------------------------------------------------------------------
//---
//---
//---
endmodule
| 7.831093 |
modules
//------------------------------------------------------------------------------
module space_wire_time_code_control
(
input wire i_clk,
input wire i_reset_n,
input wire i_rx_clk,
input wire i_got_time_code,
input wire [7:0] i_rx_time_code,
output wire [5:0] o_time_out,
output wire [1:0] o_control_flags_out, // reserved for future use
output wire o_tick_out
);
//------------------------------------------------------------------------------
reg [7:0] rx_time_code_reg;
reg [1:0] control_flags;
reg [5:0] rx_time_code;
reg [5:0] rx_time_code_plus1;
reg tick_out;
wire got_time_code_sync;
//------------------------------------------------------------------------------
assign o_time_out = rx_time_code;
assign o_control_flags_out = control_flags;
assign o_tick_out = tick_out;
//------------------------------------------------------------------------------
//---
//---
//---
//==============================================================================
// ECSS-E-ST-50-12C 8.12 System time distribution (normative)
// ECSS-E-ST-50-12C 7.3 Control characters and control codes
// The new time should be one more than the time-counter's previous
// time-value.
//==============================================================================
always @(posedge i_clk or negedge i_reset_n)
begin : s_tick_out
if ( !i_reset_n )
begin
rx_time_code <= {6{1'b0}};
rx_time_code_plus1 <= 6'b000001;
tick_out <= 1'b0;
control_flags <= 2'b00;
rx_time_code_reg <= {8{1'b0}};
end
else
begin
if ( got_time_code_sync )
begin
control_flags <= rx_time_code_reg[7:6];
rx_time_code <= rx_time_code_reg[5:0];
rx_time_code_plus1 <= rx_time_code_reg[5:0] + 1;
if ( rx_time_code_plus1 == rx_time_code_reg[5:0] )
begin
tick_out <= 1'b1;
end
end
else
begin
tick_out <= 1'b0;
end
rx_time_code_reg <= i_rx_time_code;
end
end
//------------------------------------------------------------------------------
//---
//---
//---
//------------------------------------------------------------------------------
space_wire_sync_one_pulse inst0_time_code_pulse
(
.i_clk ( i_clk ),
.i_async_clk ( i_rx_clk ),
.i_reset_n ( i_reset_n ),
.i_async_in ( i_got_time_code ),
.o_sync_out ( got_time_code_sync )
);
//------------------------------------------------------------------------------
//---
//---
//---
endmodule
| 7.831093 |
module SPad #(
parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH = 9
) (
input clk,
input reset,
input read_req,
input write_en,
input [ADDR_BITWIDTH-1 : 0] r_addr,
input [ADDR_BITWIDTH-1 : 0] w_addr,
input [DATA_BITWIDTH-1 : 0] w_data,
output [DATA_BITWIDTH-1 : 0] r_data
);
reg [DATA_BITWIDTH-1 : 0] mem [0 : (1 << ADDR_BITWIDTH) - 1];
// default - 512(2^9) 16-bit memory. Total size = 1kB
reg [DATA_BITWIDTH-1 : 0] data;
always @(posedge clk) begin : READ
if (reset) data <= 0;
else begin
if (read_req) begin
data <= mem[r_addr];
// $display("Read Address to SPad:%d",r_addr);
end else begin
data <= 10101;
end
end
end
assign r_data = data;
always @(posedge clk) begin : WRITE
/*$display("\t\t\t\t\t Current Status:\n \
\t mem[0]:%d", mem[0],
" | mem[1]:%d", mem[1],
" | mem[2]:%d", mem[2],
" | mem[3]:%d", mem[3],
" | mem[4]:%d", mem[4],
" | mem[5]:%d", mem[5],
" | mem[8]:%d", mem[8],
" | mem[24]:%d\n", mem[24],
" \t\t\t\t\t mem[100]:%d", mem[100],
" | mem[101]:%d", mem[101],
" | mem[102]:%d", mem[102],
" | mem[103]:%d", mem[103],
" | mem[104]:%d", mem[104],
" | mem[105]:%d\n", mem[105],
" | mem[124]:%d\n", mem[124],
" | mem[148]:%d\n", mem[148],
" \t\t\t\t\t psum:%d", mem[500],
" | psum:%d", mem[501],
" | psum:%d", mem[502],
" | psum:%d", mem[503],
" | psum:%d", mem[504]
); */
if (write_en && !reset) begin
mem[w_addr] <= w_data;
end
end
endmodule
| 7.909722 |
module getSpan_equal (
input clk_en,
input clk_base,
input clk_test_1,
input clk_test_2,
output reg [31:0] count_1,
output reg [31:0] count_2,
output reg isCount = 0,
output reg pin_r
);
reg [31:0] count_1_hide;
reg [31:0] count_2_hide;
//门控
always @(posedge clk_test_1) begin
if (clk_en) isCount <= 1;
else begin
isCount <= 0;
end
end
//计数1 clk_1与clk_2相同
always @(posedge clk_base) begin
if (isCount) begin
if (clk_test_2 == clk_test_1) count_1_hide <= count_1_hide + 1;
end else begin
count_1_hide <= 0;
end
end
//计数2 clk_1与clk_2不同
always @(posedge clk_base) begin
if (isCount) begin
if (clk_test_2 != clk_test_1) count_2_hide <= count_2_hide + 1;
end else begin
count_2_hide <= 0;
end
end
//保存数据
always @(negedge isCount) begin
count_1 <= count_1_hide;
count_2 <= count_2_hide;
end
//测量超前
always @(posedge clk_test_1) begin
if (clk_test_2) pin_r = 1;
else pin_r = 0;
end
endmodule
| 7.811042 |
module sparc_exu_rml_inc3 ( /*AUTOARG*/
// Outputs
dout,
// Inputs
din,
inc
);
input [2:0] din;
input inc;
output [2:0] dout;
assign dout[2] = ((~din[2] & ~din[1] & ~din[0] & ~inc) |
(~din[2] & din[1] & din[0] & inc) |
(din[2] & din[1] & ~din[0]) |
(din[2] & ~din[1] & inc) |
(din[2] & din[0] & ~inc));
assign dout[1] = ((~din[1] & ~din[0] & ~inc) |
(din[1] & ~din[0] & inc) |
(~din[1] & din[0] & inc) |
(din[1] & din[0] & ~inc));
assign dout[0] = ~din[0];
endmodule
| 6.786149 |
module sparc_ffu_part_add32 ( /*AUTOARG*/
// Outputs
z,
// Inputs
a,
b,
cin,
add32
);
input [31:0] a;
input [31:0] b;
input cin;
input add32;
output [31:0] z;
wire cout15; // carry out from lower 16 bit add
wire cin16; // carry in to the upper 16 bit add
assign cin16 = (add32) ? cout15 : cin;
assign {cout15, z[15:0]} = a[15:0] + b[15:0] + {15'b0, cin};
assign z[31:16] = a[31:16] + b[31:16] + {15'b0, cin16};
endmodule
| 6.841442 |
module sparc_ifu_sscan (
ctu_sscan_snap,
ctu_sscan_se,
ctu_tck,
lsu_sscan_test_data,
tlu_sscan_test_data,
swl_sscan_thrstate,
ifq_sscan_test_data,
sparc_sscan_so,
rclk,
si,
so,
se
);
input ctu_sscan_snap;
input ctu_sscan_se;
input ctu_tck;
input si;
input se;
input [10:0] swl_sscan_thrstate;
input [3:0] ifq_sscan_test_data;
input [15:0] lsu_sscan_test_data;
input [62:0] tlu_sscan_test_data;
input rclk;
output sparc_sscan_so;
output so;
//////////////////////////////////////////////////////////////////
wire snap_f;
wire [93:0] snap_data, snap_data_f, snap_data_ff;
`ifdef CONNECT_SHADOW_SCAN
wire [92:0] sscan_shift_data;
`endif
////////
dff_s #(1) snap_inst0 (
.q (snap_f),
.din(ctu_sscan_snap),
.clk(rclk),
.se (se),
.si (),
.so ()
);
assign snap_data = {
ifq_sscan_test_data, tlu_sscan_test_data, lsu_sscan_test_data, swl_sscan_thrstate
};
dffe_s #(94) snap_inst1 (
.q (snap_data_f),
.din(snap_data),
.clk(rclk),
.en (snap_f),
.se (se),
.si (),
.so ()
);
`ifdef CONNECT_SHADOW_SCAN
dff_sscan #(94) snap_inst2 (
.q (snap_data_ff),
.din(snap_data_f),
.clk(ctu_tck),
.se (ctu_sscan_se),
.si ({sscan_shift_data, 1'b0}),
.so ({sparc_sscan_so, sscan_shift_data})
);
`else
dff_s #(94) snap_inst2 (
.q (snap_data_ff),
.din(snap_data_f),
.clk(ctu_tck),
.se (ctu_sscan_se),
.si (),
.so ()
);
assign sparc_sscan_so = 1'b0;
`endif
sink #(94) s0 (.in(snap_data_ff));
endmodule
| 6.596396 |
module sparc_tlu_penc64 ( /*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [63:0] in;
output [5:0] out;
reg [5:0] out;
integer i;
always @(in) begin
//
// code modified for verplex to avoid inferred latches
// if (in == 64'b0) // don't want a latch
out = 6'b0;
// else
for (i = 0; i < 64; i = i + 1) begin
if (in[i]) out[5:0] = i[5:0];
end
end
endmodule
| 6.582247 |
module spare_logic_block (
`ifdef USE_POWER_PINS
inout VDD,
inout VSS,
`endif
output [30:0] spare_xz, // Constant 0 outputs (and block inputs)
output [3:0] spare_xi, // Inverter outputs
output spare_xib, // Big inverter output
output [1:0] spare_xna, // NAND outputs
output [1:0] spare_xno, // NOR outputs
output [1:0] spare_xmx, // Mux outputs
output [1:0] spare_xfq // Flop noninverted output
);
wire [ 3:0] spare_logic_nc;
wire [ 3:0] spare_xi;
wire spare_xib;
wire [ 1:0] spare_xna;
wire [ 1:0] spare_xno;
wire [ 1:0] spare_xmx;
wire [ 1:0] spare_xfq;
wire [26:0] spare_logic0;
wire [ 3:0] spare_logic1;
wire [30:0] spare_xz;
// Rename the logic0 outputs at the block pins.
assign spare_xz = {spare_logic1, spare_logic0};
gf180mcu_fd_sc_mcu7t5v0__tiel spare_logic_const_zero[26:0] (
`ifdef USE_POWER_PINS
.VDD(VDD),
.VSS(VSS),
`endif
.ZN (spare_logic0)
);
gf180mcu_fd_sc_mcu7t5v0__tieh spare_logic_const_one[3:0] (
`ifdef USE_POWER_PINS
.VDD(VDD),
.VSS(VSS),
`endif
.Z (spare_logic1)
);
gf180mcu_fd_sc_mcu7t5v0__inv_2 spare_logic_inv[3:0] (
`ifdef USE_POWER_PINS
.VDD(VDD),
.VSS(VSS),
`endif
.ZN (spare_xi),
.I (spare_logic0[3:0])
);
gf180mcu_fd_sc_mcu7t5v0__inv_12 spare_logic_biginv (
`ifdef USE_POWER_PINS
.VDD(VDD),
.VSS(VSS),
`endif
.ZN (spare_xib),
.I (spare_logic0[4])
);
gf180mcu_fd_sc_mcu7t5v0__nand2_2 spare_logic_nand[1:0] (
`ifdef USE_POWER_PINS
.VDD(VDD),
.VSS(VSS),
`endif
.ZN (spare_xna),
.A1 (spare_logic0[6:5]),
.A2 (spare_logic0[8:7])
);
gf180mcu_fd_sc_mcu7t5v0__nor2_2 spare_logic_nor[1:0] (
`ifdef USE_POWER_PINS
.VDD(VDD),
.VSS(VSS),
`endif
.ZN (spare_xno),
.A1 (spare_logic0[10:9]),
.A2 (spare_logic0[12:11])
);
gf180mcu_fd_sc_mcu7t5v0__mux2_2 spare_logic_mux[1:0] (
`ifdef USE_POWER_PINS
.VDD(VDD),
.VSS(VSS),
`endif
.Z (spare_xmx),
.I0 (spare_logic0[14:13]),
.I1 (spare_logic0[16:15]),
.S (spare_logic0[18:17])
);
gf180mcu_fd_sc_mcu7t5v0__dffrsnq_2 spare_logic_flop[1:0] (
`ifdef USE_POWER_PINS
.VDD(VDD),
.VSS(VSS),
`endif
.Q(spare_xfq),
.D(spare_logic0[20:19]),
.CLK(spare_logic0[22:21]),
.SETN(spare_logic0[24:23]),
.RN(spare_logic0[26:25])
);
gf180mcu_fd_sc_mcu7t5v0__antenna spare_logic_diode[3:0] (
`ifdef USE_POWER_PINS
.VDD(VDD),
.VSS(VSS),
`endif
.I (spare_logic_nc)
);
endmodule
| 7.245444 |
module SparseCNN #(
parameter input_size = 28,
parameter kernel_size = 5,
parameter word_length = 8, // used for data
parameter col_length = 8,
parameter double_word_length = 16, // used for utils number,
parameter output_size = 24,
parameter PE_output_size = 16,
parameter PE_weight_row_size = 28
) (
clk,
tclk,
rst,
feature_in_valid,
in_feature,
pe_input_weight_value,
pe_input_weight_rows,
pe_input_weight_cols,
weight_valid_num,
out_valid,
out_feature
);
input clk;
input tclk;
input rst;
input feature_in_valid;
input [word_length-1:0] in_feature;
input [224-1:0] pe_input_weight_value;
input [224-1 : 0] pe_input_weight_rows;
input [224-1 : 0] pe_input_weight_cols;
input [double_word_length-1:0] weight_valid_num;
output out_valid;
output [output_size*output_size*double_word_length-1:0] out_feature;
wire [double_word_length-1:0] channel;
assign channel = 1;
wire csr_feature_done;
wire [double_word_length-1:0] csr_feature_valid_num;
wire [input_size*input_size*word_length -1:0] csr_feature_value_output;
wire [input_size*input_size*col_length -1:0] csr_feature_col_output, csr_feature_row_output;
wire signed [double_word_length*PE_output_size -1:0] pe_data_out;
wire signed [col_length*PE_output_size -1:0] pe_data_out_cols;
wire signed [col_length*PE_output_size -1:0] pe_data_out_rows;
wire pe_out_valid;
// PEAdder output
wire [output_size*output_size*double_word_length-1:0] peadder_data_out_wire;
wire peadder_out_valid_wire;
// Output
reg [output_size*output_size*double_word_length-1:0] data_out_r, next_data_out_r;
reg out_valid_r, next_out_valid_r;
assign out_valid = out_valid_r;
assign out_feature = data_out_r;
CSR #(
.image_size(input_size),
.col_length(col_length),
.word_length(word_length),
.double_word_length(double_word_length)
) feature_csr (
.clk(clk),
.rst(rst),
.in_valid(feature_in_valid),
.data_in(in_feature),
.out_valid(csr_feature_done),
.valid_num_out(csr_feature_valid_num),
.data_out(csr_feature_value_output),
.data_out_cols(csr_feature_col_output),
.data_out_rows(csr_feature_row_output)
);
PE #(
.col_length(col_length),
.word_length(word_length),
.double_word_length(double_word_length),
.kernel_size(kernel_size),
.image_size(input_size)
) pe (
.clk(clk),
.rst(rst),
.in_channel(channel),
.in_valid(csr_feature_done),
.feature_valid_num(csr_feature_valid_num),
.feature_value(csr_feature_value_output),
.feature_cols(csr_feature_col_output),
.feature_rows(csr_feature_row_output),
.weight_valid_num(weight_valid_num),
.weight_value(pe_input_weight_value),
.weight_cols(pe_input_weight_rows),
.weight_rows(pe_input_weight_cols),
.out_valid(pe_out_valid),
.data_out(pe_data_out),
.data_out_cols(pe_data_out_cols),
.data_out_rows(pe_data_out_rows),
.out_channel(channel)
);
PEADDER #(
.col_length(col_length),
.word_length(word_length),
.double_word_length(double_word_length),
.PE_output_size(PE_output_size),
.output_col_size(output_size),
.output_size(output_size * output_size)
) peadder (
.clk(clk),
.tclk(tclk),
.rst(rst),
.in_valid(pe_out_valid),
.data_in(pe_data_out),
.data_in_cols(pe_data_out_cols),
.data_in_rows(pe_data_out_rows),
.out_valid(peadder_out_valid_wire),
.data_out (peadder_data_out_wire)
);
always @(negedge peadder_out_valid_wire) begin
if (csr_feature_done) next_out_valid_r = 1;
else next_out_valid_r = out_valid_r;
end
always @(*) begin
if (peadder_out_valid_wire) next_data_out_r = peadder_data_out_wire;
else next_data_out_r = data_out_r;
end
always @(posedge clk or posedge rst) begin
if (rst) begin
out_valid_r <= 0;
data_out_r <= 0;
end else begin
out_valid_r <= next_out_valid_r;
data_out_r <= next_data_out_r;
end
end
endmodule
| 8.904559 |
modules together and
// performs the intreactions between the serial input (rx) and output (tx) as well as the
// databus and signals from the driver. It connects the bus interface, tx, rx, and baud generator
// together
//////////////////////////////////////////////////////////////////////////////////////////////
module spart(
input clk,
input rst,
input iocs,
input iorw,
output rda,
output tbr,
input [1:0] ioaddr,
inout [7:0] databus,
output txd,
input rxd
);
///////////////////////////////////
// Interconnects between modules //
///////////////////////////////////
wire [7:0] databus_out, bus_interface_out, rx_data_out;
wire sel, wrt_db_low, wrt_db_high, wrt_tx, tx_rx_en, rd_rx;
// Tri-state buffer used to receive and send data via the databuse
// Sel high = output, Sel low = input
assign databus = sel ? databus_out : 8'bzz;
// Bus Interface Module
bus_interface bus0( .iocs(iocs),
.iorw(iorw),
.ioaddr(ioaddr),
.rda(rda),
.tbr(tbr),
.databus_in(databus),
.databus_out(databus_out),
.data_in(rx_data_out),
.data_out(bus_interface_out),
.wrt_db_low(wrt_db_low),
.wrt_db_high(wrt_db_high),
.wrt_tx(wrt_tx),
.rd_rx(rd_rx),
.databus_sel(sel)
);
// Baud Rate Generator Module
baud_rate_gen baud0( .clk(clk),
.rst(rst),
.en(tx_rx_en),
.data(bus_interface_out),
.sel_low(wrt_db_low),
.sel_high(wrt_db_high)
);
// TX Module (Sends data out)
tx tx0( .clk(clk),
.rst(rst),
.data(bus_interface_out),
.en(tx_rx_en),
.en_tx(wrt_tx),
.tbr(tbr),
.TxD(txd)
);
// RX Module (Recieves data in)
rx rx0( .clk(clk),
.rst(rst),
.RxD(rxd),
.Baud(tx_rx_en),
.RxD_data(rx_data_out),
.RDA(rda),
.rd_rx(rd_rx)
);
endmodule
| 8.250554 |
module Spartan3StarterKit (
// Clock Sources
CLK50MHZ,
SOCKET,
// Fast, Asynchronous SRAM
SRAM_A,
SRAM_WE_X,
SRAM_OE_X,
SRAM_IO_A,
SRAM_CE_A_X,
SRAM_LB_A_X,
SRAM_UB_A_X,
SRAM_IO_B,
SRAM_CE_B_X,
SRAM_LB_B_X,
SRAM_UB_B_X,
// Four-Digit, Saven-Segment LED Display
LED_AN,
LED_A,
LED_B,
LED_C,
LED_D,
LED_E,
LED_F,
LED_G,
LED_DP,
// Switch
SW,
// Button
BTN,
// LED
LD,
// VGA Port
VGA_R,
VGA_G,
VGA_B,
VGA_HS,
VGA_VS,
// PS2
PS2C,
PS2D,
// RS-232 Serial Port
RXD,
TXD,
RXDA,
TXDA,
// Platform Flash (XCF02S Serial PROM)
DIN,
INIT_B,
RCLK
);
input CLK50MHZ;
input SOCKET;
output [17:0] SRAM_A;
output SRAM_WE_X;
output SRAM_OE_X;
inout [15:0] SRAM_IO_A;
output SRAM_CE_A_X;
output SRAM_LB_A_X;
output SRAM_UB_A_X;
inout [15:0] SRAM_IO_B;
output SRAM_CE_B_X;
output SRAM_LB_B_X;
output SRAM_UB_B_X;
output [3:0] LED_AN;
output LED_A;
output LED_B;
output LED_C;
output LED_D;
output LED_E;
output LED_F;
output LED_G;
output LED_DP;
input [7:0] SW;
input [3:0] BTN;
output [7:0] LD;
output VGA_R;
output VGA_G;
output VGA_B;
output VGA_HS;
output VGA_VS;
input PS2C;
input PS2D;
input RXD;
output TXD;
input RXDA;
output TXDA;
input DIN;
output INIT_B;
output RCLK;
assign SRAM_A = 18'h00000;
assign SRAM_WE_X = 1'b0;
assign SRAM_OE_X = 1'b1;
assign SRAM_IO_A = 16'hffff;
assign SRAM_CE_A_X = 1'b1;
assign SRAM_LB_A_X = 1'b1;
assign SRAM_UB_A_X = 1'b1;
assign SRAM_IO_B = 16'hffff;
assign SRAM_CE_B_X = 1'b1;
assign SRAM_LB_B_X = 1'b1;
assign SRAM_UB_B_X = 1'b1;
assign LED_AN = 4'b1111;
assign LED_A = 1'b1;
assign LED_B = 1'b1;
assign LED_C = 1'b1;
assign LED_D = 1'b1;
assign LED_E = 1'b1;
assign LED_F = 1'b1;
assign LED_G = 1'b1;
assign LED_DP = 1'b1;
assign LD = SW | {1'b0, BTN, PS2D, PS2C, SOCKET};
assign VGA_R = 1'b0;
assign VGA_G = 1'b0;
assign VGA_B = 1'b0;
assign VGA_HS = 1'b1;
assign VGA_VS = 1'b1;
assign TXD = RXD;
assign TXDA = RXDA;
assign INIT_B = DIN;
assign RCLK = DIN;
endmodule
| 7.180055 |
module DCM (
CLK0,
CLK180,
CLK270,
CLK2X,
CLK2X180,
CLK90,
CLKDV,
CLKFX,
CLKFX180,
LOCKED,
PSDONE,
STATUS,
CLKFB,
CLKIN,
DSSEN,
PSCLK,
PSEN,
PSINCDEC,
RST
); // synthesis syn_black_box
parameter CLK_FEEDBACK = "1X";
parameter CLKDV_DIVIDE = 2.0;
parameter CLKFX_DIVIDE = 1;
parameter CLKFX_MULTIPLY = 4;
parameter CLKIN_DIVIDE_BY_2 = "FALSE";
parameter CLKIN_PERIOD = 0.0; // non-simulatable
parameter CLKOUT_PHASE_SHIFT = "NONE";
parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; // non-simulatable
parameter DFS_FREQUENCY_MODE = "LOW";
parameter DLL_FREQUENCY_MODE = "LOW";
parameter DSS_MODE = "NONE"; // non-simulatable
parameter DUTY_CYCLE_CORRECTION = "TRUE";
parameter FACTORY_JF = 16'hC080; // non-simulatable
parameter MAXPERCLKIN = 1000000;
parameter MAXPERPSCLK = 100000000;
parameter PHASE_SHIFT = 0;
parameter STARTUP_WAIT = "FALSE"; // non-simulatable
input CLKFB, CLKIN, DSSEN;
input PSCLK, PSEN, PSINCDEC, RST;
output CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90;
output CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE;
output [7:0] STATUS;
endmodule
| 6.58978 |
module IBUFGDS_LVPECL_33 (
O,
I,
IB
); // synthesis syn_black_box
output O;
input I;
input IB;
endmodule
| 6.584593 |
module IBUFG_AGP (
O,
I
); // synthesis syn_black_box
output O;
input I;
endmodule
| 6.520006 |
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