code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sort_cell #(
parameter SORT_WIDTH = 32,
parameter SHIFT_INPUT_WIDTH = 8,
parameter PRI_POS_START = 0,
parameter PRI_POS_END = 32
) (
input clk,
input reset,
//Forward shift path
input [SORT_WIDTH-1:0] prev_data,
output [SORT_WIDTH-1:0] data_out,
input [SORT_WIDTH-1:0] d... | 6.993922 |
module SORT_counter (
input clk,
rst,
input [3:0] opcode,
output reg counter
);
always @(posedge clk, posedge rst) begin
if (rst) counter <= 0;
else begin
if (opcode == 4'b0011) begin
counter <= ~counter;
end else counter <= 0;
end
end
endmodule
| 6.705264 |
module sort_frequent (
CLK,
nRST,
FREQUENT_IN,
FREQUENT_OUT
);
input CLK;
input nRST;
input [15:0] FREQUENT_IN;
output [31:0] FREQUENT_OUT;
wire [7:0] weight_A;
wire [7:0] weight_B;
wire [7:0] weight_C;
wire [7:0] weight_D;
assign weight_A[7:0] = {FREQUENT_IN[3:0], 4'b1010};
assign... | 6.681097 |
module: sort_frequent
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sort_frequent_test;
// Inputs
reg CLK;
reg nRST;
reg [15:0] FREQUENT_IN;
// Outputs
wire [31:0] FREQUENT... | 6.98429 |
module sort_index (
input clk,
input rst_n,
input en_sort,
input [14*(32+3)-1:0] index_to_q_unit_in,
output reg [14*(32+3)-1:0] index_to_q_unit
);
reg [5:0] count_sort;
always @(posedge clk or negedge rst_n)
if (!rst_n) count_sort <= 0;
else if (en_sort) count_sort <= count_sort + 1'b1;... | 6.511812 |
module sort_istack (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd100;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0... | 6.757775 |
module N must be a power of two.
//
// Sorts N input signals of DATAWIDTH bits wide
// using only combinatorial logic
// reference Fen Logic Ltd
//********************************************************************//
module sort_N#(
parameter DATAWIDTH = 8, // Data width
parameter N = 16 // Number of entri... | 7.269022 |
module sort_three (
//global clk
input clk,
input rst_n,
//input data
input [7:0] data_in1,
input [7:0] data_in2,
input [7:0] data_in3,
//sort interface
output reg [7:0] max_data,
output reg [7:0] mid_data,
output reg [7:0] min_data
);
//-------------------------------... | 7.744624 |
module sottrattore (
x,
y,
d,
b_in,
b_out
);
parameter N = 8;
input [N-1:0] x, y;
input b_in;
output [N-1:0] d;
output b_out;
assign #1{b_out, d} = x - y - b_in;
endmodule
| 6.687635 |
module sound (
input wire clk,
f0,
reset,
input wire [7:0] din,
input wire beeper_wr,
input wire covox_wr,
input wire beeper_mux, // output either tape_out or beeper
output wire sound_bit
);
reg sound_bit_SD;
reg sound_bit_PWM;
reg [7:0] val;
//================BEGIN=============... | 7.264396 |
module soundA (
input clk,
input rst,
input lightA,
output reg speakerA
);
reg [31:0] counter;
reg [14:0] keepON;
// FSM to Regulate Sound with Switch
reg [ 1:0] S;
reg [ 1:0] NS;
parameter START = 2'b00, PLAY = 2'b01, WAIT = 2'b10, WAIT2 = 2'b11;
reg [31:0] clkdivider;
always @(*)... | 6.599725 |
module SoundBlaster (
input wire clk,
input wire reset_n,
input wire [11:0] port,
input wire [7:0] iodin,
output reg [7:0] iodout,
input wire iowrin,
output reg iowrout,
input wire iordin,
output reg iordout,
input wire [7:0] dma_din,
input wire dma_rdin,
output reg dma... | 7.436088 |
module soundC (
input clk,
input rst,
input lightC,
output reg speakerC
);
reg [31:0] counter;
reg [ 3:0] keepON;
// FSM to Regulate Sound with Switch
reg [ 1:0] S;
reg [ 1:0] NS;
parameter START = 2'b00, PLAY = 2'b01, WAIT = 2'b10, WAIT2 = 2'b11;
reg [31:0] clkdivider;
always @(*)... | 6.688412 |
module soundCard (
input wire snd_clk, // Sound clock.
input wire [1:0] channel, // Channels of sound.
input wire [1:0] sound, // Type of sound.
output wire right_o, // Channel right.
output wire left_o // Channel left.
);
// Type sounds.
localparam ping = 2'd1;
... | 6.821635 |
module soundcodec(clk24,
pulses,
ay_soundA,ay_soundB,ay_soundC,
rs_soundA,rs_soundB,rs_soundC,
covox,
tapein, reset_n,
o_adc_clk, o_adc_cs_n, i_adc_data_in,
o_pwm);
input clk24;
input [3:0] pulses;
input [7:0] ay_soundA;
input [7:0] ay_soundB;
input [7:0... | 7.985964 |
module, channel 2. Squate waves with variable timmer, configurable frequency and envelope functions.
////////////////////////////////////////////////////////////////////////////////////
module SoundCtrlChannel2 //parameters
(
input wire iClock, //CPU CLOCK, 4194304Hz
input wire iReset,
input wire i... | 8.02213 |
module, channel 2. Squate waves with variable timmer, configurable frequency and envelope functions.
////////////////////////////////////////////////////////////////////////////////////
module SoundCtrlMX //parameters
(
input wire iClock, //CPU CLOCK, 4194304Hz
input wire iReset,
input wire iOsc262k... | 8.02213 |
module soundctl (
input clk,
input rst,
output sound_clr_full,
input [15:0] sound_clr_sample,
input [15:0] sound_clr_rate,
input sound_clr_req,
output reg pwm_out
);
wire [15:0] fifo_out;
wire fifo_empty;
reg fifo_rd;
smallfi... | 6.787148 |
module soundD (
input clk,
input rst,
input lightD,
output reg speakerD
);
reg [31:0] counter;
reg [ 3:0] keepON;
// FSM to Regulate Sound with Switch
reg [ 1:0] S;
reg [ 1:0] NS;
parameter START = 2'b00, PLAY = 2'b01, WAIT = 2'b10, WAIT2 = 2'b11;
reg [31:0] clkdivider;
always @(*)... | 7.012868 |
module soundE (
input clk,
input rst,
input lightE,
output reg speakerE
);
reg [31:0] counter;
reg [ 3:0] keepON;
// FSM to Regulate Sound with Switch
reg [ 1:0] S;
reg [ 1:0] NS;
parameter START = 2'b00, PLAY = 2'b01, WAIT = 2'b10, WAIT2 = 2'b11;
reg [31:0] clkdivider;
always @(*)... | 7.228901 |
module soundF (
input clk,
input rst,
input lightF,
output reg speakerF
);
reg [31:0] counter;
reg [ 3:0] keepON;
// FSM to Regulate Sound with Switch
reg [ 1:0] S;
reg [ 1:0] NS;
parameter START = 2'b00, PLAY = 2'b01, WAIT = 2'b10, WAIT2 = 2'b11;
reg [31:0] clkdivider;
always @(*)... | 6.663165 |
module soundG (
input clk,
input rst,
input lightG,
output reg speakerG
);
reg [31:0] counter;
reg [ 3:0] keepON;
// FSM to Regulate Sound with Switch
reg [ 1:0] S;
reg [ 1:0] NS;
parameter START = 2'b00, PLAY = 2'b01, WAIT = 2'b10, WAIT2 = 2'b11;
reg [31:0] clkdivider;
always @(*)... | 6.965651 |
module SoundMixer (
//////////// Audio //////////
input AUD_ADCDAT,
inout AUD_ADCLRCK,
inout AUD_BCLK,
output AUD_DACDAT,
inout AUD_DACLRCK,
output AUD_XCK,
//////////// CLOCK //////////
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
////////... | 7.652105 |
module: sound_player
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module soundtb;
// Inputs
reg [3:0] noteAction;
reg [3:0] noteSuccessState;
reg clk;
reg rst;
// Outputs
wire... | 7.421987 |
module soundwave (
input CLK,
input CLK44100x256,
input [7:0] data,
input we,
output reg AUDIO
);
reg [15:0] wdata;
reg [2:0] write = 3'b000;
reg [15:0] sample;
reg [15:0] buffer;
reg [31:0] lval = 0;
wire lsign = lval[31:16] < sample;
always @(posedge CLK44100x256) begin
if (|wr... | 7.074226 |
module draw_graph (
clk,
audio_clock,
enable,
reset,
soundwave,
enable_draw,
X_Vga,
Y_Vga
);
input clk, audio_clock, enable, reset;
input [23:0] soundwave;
output enable_draw;
output [7:0] X_Vga;
output [6:0] Y_Vga;
// Rate divider: every 4 clock cycles
wire [15:0] load = ... | 7.4209 |
module hex_decoder (
hex_digit,
segments
);
input [3:0] hex_digit;
output reg [6:0] segments;
always @(*)
case (hex_digit)
4'h0: segments = 7'b100_0000;
4'h1: segments = 7'b111_1001;
4'h2: segments = 7'b010_0100;
4'h3: segments = 7'b011_0000;
4'h4: segments = 7'b001_1001... | 7.584821 |
module Sound_control (
inout v2, //ͨ·
input clk_100MHz, //ϵͳʱ
input rst_sound, //λźţӵĸλźͬ
output v2_show_en //ʾ
);
//ԴƵ¼ʱ
reg clk_1MHz; //ÿ1us
reg [7:0] cnt;
parameter N = 100;
initial begin
cnt <= 8'b0;
clk_1MHz <= 1'b0;
end
always @(posedge clk_100MHz, negedge ... | 6.788332 |
module sound_controller (
clk,
on,
pitch,
out
);
input clk, on;
input [3:0] pitch;
output reg out;
reg [31:0] counter;
reg [31:0] maxCounter;
initial begin
counter = 32'd0;
maxCounter = 32'd113636;
out = 0;
end
always @(pitch) begin
case (pitch)
4'b0000: maxCoun... | 7.041631 |
module Sound_control_tb ();
wire v2;
reg clk_100MHz;
reg rst_sound;
wire v2_show_en;
initial begin
clk_100MHz = 0;
rst_sound = 1;
end
always #1 clk_100MHz = ~clk_100MHz;
initial begin
force v2 = 1;
#50;
release v2;
#50 force v2 = 1;
#600;
release v2;
#50;
rs... | 6.788332 |
module Sound_Counter (
WAVE,
RESET,
RESULT
);
input WAVE;
input RESET;
output reg [`SOUND_COUNTER_WIDTH-1:0] RESULT;
always @(posedge WAVE or posedge RESET) begin
if (RESET) begin
RESULT <= 0;
end else begin
RESULT <= RESULT + 1;
end
end
endmodule
| 6.526267 |
module generates strobe signal for data sender - load, indicating when it loaded new portion of data,
// and allowing sender to begin preparing new data. dac_leftright is also to be used by sender (by locking it
// when load is 1).
//
// dac_clock is symmetrical clock at 1/10 of input clock (2.4 MHz)
// load is positiv... | 7.590906 |
module generates strobe signal for data sender - load, indicating when it loaded new portion of data,
// and allowing sender to begin preparing new data. dac_leftright is also to be used by sender (by locking it
// when load is 1).
//
// dac_clock is symmetrical clock at 1/10 of input clock (2.4 MHz)
// load is positiv... | 7.590906 |
module Sound_Encoder (
CLK,
WAVE,
LEVEL
);
input CLK; //100Hz
input WAVE;
output reg [`SOUND_LEVEL_ENCODE_LENGTH-1:0] LEVEL;
/*
该模块作用是将声音传感器收集到的声音频率信号抽象为6个等级
每0.02s采样一次，采样时间为为0.01s,统计期间声波上升沿的个数
由上升沿个数的多寡决定最终分级
*/
reg counter_reset;
wire [`SOUND_COUNTER_WIDTH-1:0] wave_counter;
Sound_Cou... | 6.800788 |
module sound # (
parameter wav_length= 16'd38174;
parameter init_file= ""
)
(
input clk,
input trigger,
input RESET_n,
output signed [15:0] sound_out
);
reg sndclk = 1'b0;
always @(posedge clk) begin
sndclk <= ~sndclk;
end
reg wav_playing = 1'b0;
wire wav_play;
reg [WAV_COUNTER_SIZE-1:0] wav_counter;
loc... | 7.716383 |
module sound_mem (
clk,
addr,
rdata
);
parameter ROM_DATA_FILE = "Sound.mem";
input clk;
input [17:0] addr;
output reg [3:0] rdata;
reg [3:0] MY_ROM[0:2**18-1];
initial $readmemb(ROM_DATA_FILE, MY_ROM);
always @(posedge clk) rdata <= MY_ROM[addr];
endmodule
| 6.905564 |
module sound_memory (
input [6:0] address,
input en,
output [6:0] data
);
reg [6:0] sound_file[127:0];
initial $readmemh("./resources/sound.txt", sound_file);
assign data = en ? sound_file[address] : 0;
endmodule
| 7.01527 |
module sound_mulacc (
clock, // input clock (24 MHz)
vol_in, // input volume (6 bit unsigned)
dat_in, // input sound data (8 bit signed with sign bit inverted)
mode_inv7b, // whether to invert 7th bit of dat_in
load, // load pulse input
clr_sum, // clear sum input
ready, // ready... | 6.512135 |
module sound_noise (
input rst, // Async reset
input clk, // CPU Clock
input clk_length_ctr, // Length control clock
input clk_vol_env, // Volume Envelope clock
input [5:0] length, // Length = (64-t1)*(1/256) second, used iff single is set
input [3:0] initial_volume, // Initial volume of e... | 7.820615 |
module sound_player (
input [7:0] noteAction,
input [7:0] noteSuccessState,
input clk,
input rst,
output buzzer_sound
);
reg [7:0] sound;
buzzer_driver buzzer_driver (
.clk(clk),
.rst(rst),
.sound(sound),
.buzzer(buzzer_sound)
);
always @(posedge clk) begin
if ... | 7.356737 |
module sound_sample (
//////////// CLOCK //////////
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
//////////// KEY //////////
input [3:0] KEY,
//////////// SW //////////
input [9:0] SW,
//////////// LED //////////
output [9:0] LEDR,
//////////// ... | 6.897427 |
module sound_square (
input rst, // Async reset
input clk, // CPU Clock
input clk_length_ctr, // Length control clock
input clk_vol_env, // Volume Envelope clock
input clk_sweep, // Sweep clock
input clk_freq_div, // Base frequency for divider (should be 16x131072=2097152Hz)
input [2:0... | 6.919254 |
module sound_tb;
reg rst = 1;
reg clk = 0;
always #500 clk = !clk;
wire dac_en;
wire [7:0] dac_value;
sound dut (
.rst(rst),
.clk_4e(clk),
.diagnostic(1'b1),
.pb(6'b000000),
.hand(1'b0),
.dac_en(dac_en),
.dac_value(dac_value)
);
initial begin
$dum... | 6.909182 |
module sound_test (
GPIO,
LEDR,
SW
);
input [0:0] GPIO;
input [17:0] SW;
output [17:0] LEDR;
Sound_Module sound (
.sound(GPIO[0]),
.out(LEDR[0]),
.enable(SW[1])
);
endmodule
| 7.05487 |
module Sound_Top (
input clk,
reset,
inout SDIN,
output SCLK,
USB_clk,
BCLK,
output reg DAC_LR_CLK,
output DAC_DATA,
output [2:0] ACK_LEDR
);
reg [3:0] counter; //selecting register address and its corresponding data
reg counting_state, ignition;
reg read_enable;
reg [15:0] ... | 6.898608 |
module SOUND_TO_MTL2 (
input [15:0] WAVE,
input AUDIO_MCLK,
input SAMPLE_TR,
input RESET_n,
input DRAW_DOT,
input MTL_CLK,
output [7:0] MTL2_R,
output [7:0] MTL2_G,
output [7:0] MTL2_B,
output MTL2_HSD,
output MTL2_VSD,
output MTL... | 6.632043 |
module sound_wave (
input rst, // Async reset
input clk, // Main CPU clock
input clk_length_ctr, // Length control clock
input [7:0] length, // Length = (256-t1)*(1/256) second, used iff single is set
input [1:0] volume,
input on,
input single,
input start,
input [10:0] frequenc... | 7.559463 |
module serial_source (
en_w,
ip_traffic,
clk,
reset,
serial_out,
busy,
pir
);
//parameter DEST_ID=`NUM_NODES-1;
parameter NODE_ID = 0;
input clk, reset, busy, en_w;
input [7:0] pir;
input [`NUM_NODES-1:0] ip_traffic;
output serial_out;
wire [`ADDR_SZ-1:0] data;
source #(
... | 6.947006 |
module serial_source (
clk,
reset,
serial_out,
busy,
pir
);
parameter DEST_ID = `NUM_NODES - 1;
parameter NODE_ID = 0;
input clk, reset, busy;
input [7:0] pir;
output serial_out;
wire [`ADDR_SZ-1:0] data;
source #(
.DEST_ID(DEST_ID),
.NODE_ID(NODE_ID)
) s1 (
clk,
... | 6.947006 |
module sourcemux (
muxin0,
muxin1,
select,
muxout
);
parameter k = 1;
input [15:0] muxin0, muxin1;
input select;
output reg [15:0] muxout;
always @(*) begin
case (select)
1'b0: muxout = muxin0;
1'b1: muxout = muxin1;
default: muxout = {k{1'bx}};
endcase
end
endmod... | 6.56294 |
module serial_source_from_memory (
clk,
reset,
serial_out,
busy,
send
);
parameter id = -1;
parameter dests = 1;
parameter pir = 16;
parameter traffic_file = "";
input clk, reset, busy, send;
output serial_out;
wire tx_active;
wire [`HDR_SZ + `PL_SZ + `ADDR_SZ-1:0] data;
so... | 6.947006 |
module serial_source_from_memory (
clk,
reset,
serial_out,
busy
);
parameter id = -1;
parameter flits = 16;
parameter traffic_file = "";
input clk, reset, busy;
output serial_out;
wire tx_active;
wire [`SIZE-1:0] data;
source_from_memory #(id, flits, traffic_file) s1 (
clk,
... | 6.947006 |
module serial_source_from_memory (
clk,
reset,
serial_out,
busy,
send
);
parameter id = -1;
parameter dests = 1;
parameter pir = 16;
parameter traffic_file = "";
input clk, reset, busy, send;
output serial_out;
wire tx_active;
wire [`HDR_SZ + `PL_SZ + `ADDR_SZ-1:0] data;
so... | 6.947006 |
module source_v3 #(
parameter WIDTH = 8,
parameter DEPTH = 256
) (
clk,
s_rst,
vaild_in,
ready,
vaild,
data_out
);
localparam wt = $clog2(DEPTH);
input clk;
input s_rst;
input vaild_in;
input ready;
output reg [WIDTH-1:0] data_out;
output vaild;
reg [WIDTH-1:0]... | 6.983352 |
module Sout_16bit (
input clk,
input rst,
input ld,
input [15:0] in,
output reg Dout
);
reg [15:0] out;
always @(posedge clk)
if (!rst) Dout <= 0;
else Dout <= out[15];
always @(posedge clk)
if (!rst) out <= 0;
else if (ld) out <= in;
else out <= {out[14:0], 1'b0};
endm... | 7.362124 |
module so_pdm #(
parameter INPUT_WIDTH = 8
) (
input wire i_clk,
input wire i_res,
input wire i_ce,
input wire [INPUT_WIDTH-1:0] i_func,
output wire o_DAC
);
reg this_bit;
reg [(INPUT_WIDTH):0] DAC_acc_1st;
reg [(INPUT_WIDTH):0] DAC_acc_2nd;
reg [(INPUT_WIDTH):0] i_func_extended;
as... | 6.95409 |
module so_pdm_tb ();
reg clk;
reg rst;
wire dac_out;
reg pulse_48k;
reg pulse_24M;
reg pulse_sine;
wire [7:0] sine_signal;
reg [7:0] sine_signal_r = 0;
initial begin
$dumpfile("test.vcd");
$dumpvars(0, so_pdm_tb);
end
// Clock generator
always begin
clk = 0;
#10.416 clk = 1;
... | 7.261106 |
module SP256K (
input wire [13:0] AD,
input wire [15:0] DI,
input wire [3:0] MASKWE,
input wire WE,
input wire CS,
input wire CK,
input wire STDBY,
input wire SLEEP,
input wire PWROFF_N,
output wire [15:0] DO
);
wire [13 : 0] addr;
wire [15 : 0] din;
wire [ 1 : 0] write_... | 6.962635 |
module xilinx_single_port_ram_write_first #(
parameter RAM_WIDTH = 32, // Specify RAM data width
parameter RAM_DEPTH = 1024, // Specify RAM depth (number of entries)
parameter INIT_FILE = "" // Specify name/location of RAM initialization file if using one (leave blank if not)
) (
... | 10.742794 |
module SP32B1024 (
output [31:0] Q,
input CLK,
input CEN,
input WEN,
input [9:0] A,
input [31:0] D
);
xilinx_single_port_ram_write_first #(
.RAM_WIDTH(32), // Specify RAM data width
.RAM_DEPTH(1024), // Specify RAM depth (number of entries)
.INIT_FILE("") ... | 6.523259 |
module Testbench ();
wire [9:0][23:0] strip;
reg [3:0] op_code;
reg clk;
reg [4:0] i;
wire [2:0] brightness;
BreadBoard BB (
.clk(clk),
.op_code(op_code),
.strip(strip),
.brightness(brightness)
);
initial begin
forever begin
clk = 0;
#5;
clk = 1;
#5;... | 6.722871 |
module BreadBoard (
clk,
op_code,
strip,
brightness
);
output [9:0][23:0] strip;
output [2:0] brightness;
input [3:0] op_code;
input clk;
wire [1:0] mode;
wire [2:0] color_code;
reg [4:0] i;
wire [2:0] brightness_mux_out;
wire [1:0] mode_mux_out;
wire [2:0] color_mux_out;
wire [... | 6.725321 |
module DFF (
clk
);
input clk;
always @(posedge clk) $display("clk tking.");
endmodule
| 8.191977 |
module get_solid_color (
color_code,
solid_color
);
wire [7:0][23:0] channels; //8 solid color
input [2:0] color_code;
output reg [23:0] solid_color;
assign channels[0] = 24'b11111111_00000000_00000000; //red
assign channels[1] = 24'b00000000_11111111_00000000; //green
assign channels[2] = 24'b0... | 7.164143 |
module Testbench ();
parameter command = -1;
wire [9:0][23:0] strip;
reg [3:0] op_code;
reg clk;
reg [4:0] i;
wire [2:0] brightness;
reg [3:0] in;
integer inFile;
integer outFile;
BreadBoard BB (
.clk(clk),
.op_code(op_code),
.strip(strip),
.brightness(brightness)
);
... | 6.722871 |
module BreadBoard (
clk,
op_code,
strip,
brightness
);
output [9:0][23:0] strip;
output [2:0] brightness;
input [3:0] op_code;
input clk;
wire [1:0] mode;
wire [2:0] color_code;
reg [4:0] i;
wire [2:0] brightness_mux_out;
wire [1:0] mode_mux_out;
wire [2:0] color_mux_out;
wire ... | 6.725321 |
module DFF (
clk
);
input clk;
always @(posedge clk) $display("clk tking.");
endmodule
| 8.191977 |
module get_solid_color (
color_code,
solid_color
);
wire [7:0][23:0] channels; //8 solid color
input [2:0] color_code;
output reg [23:0] solid_color;
assign channels[0] = 24'b11111111_00000000_00000000; //red
assign channels[1] = 24'b00000000_11111111_00000000; //green
assign channels[2] = 24'b0... | 7.164143 |
module space (
input [9:0] tlx,
input [9:0] tly,
input [9:0] brx,
input [9:0] bry,
input rst,
input change,
input [9:0] x,
input [9:0] y,
input [1:0] nextmode,
output [9:0] lx,
output [9:0] ly,
output xyin,
output [1:0] mode
);
reg [1:0] state; //00 -> empty, 01 ... | 6.743672 |
module spaced_2lvl_penc #(
parameter INPUT_WIDTH = 8192,
parameter PENC1_SIZE = 32,
parameter PENC2_SIZE = 32,
parameter BIN_COUNT = 8,
parameter LARGE_BLOCK = BIN_COUNT*PENC1_SIZE*PENC2_SIZE,
parameter OUTPUT_WIDTH = $clog2(LARGE_BLOCK)
) (
input wire clk,
input wire rst,
... | 8.176834 |
module SpaceInvaders (
input clk,
input reset,
input btnLeftInput,
input btnRightInput,
input fire,
output [7:0] rgb,
output hSync,
output vSync,
output victory,
output defeat
);
// Parameters :
parameter NB_LIN = 3;
parameter NB_COL = 5;
parameter NB_ALIENS = NB_LIN ... | 7.417106 |
module SpaceShip(
input clk,
input reset,
input left,
input right,
input [9:0] hPos,
input [9:0] vPos,
output reg [9:0] gunPosition,
output reg [2:0] color
);
parameter SCREEN_WIDTH = 640 ;
parameter SCREEN_HEIGHT = 480 ;
parameter RADIUS = 30;
parameter SHIP_WIDTH = 60 ; // Width o... | 7.157699 |
module planet_status (
clock,
planet_hit,
game_state,
status,
War
);
/***************************************************************
DEFINING INPUTS AND OUTPUTS
***************************************************************/
input clock;
//50MHz clock for registers
input planet_hi... | 6.524642 |
module gamestate_fsm (
clock_50M,
left_planet_status,
right_planet_status,
st1,
st2,
game_state,
score_resetn,
earth_score_counter,
mars_score_counter,
earth_defense
);
/***************************************************************
DEFINING INPUTS AND OUTPUTS
********... | 7.338756 |
module get60HzClock (
clock50MHz,
clock60Hz
);
input clock50MHz;
output reg clock60Hz;
parameter [19:0] TICKS = 20'd833333;
reg [19:0] cnt = 20'b0;
always @(posedge clock50MHz) begin
if (cnt == TICKS) begin
clock60Hz <= 1'b1;
cnt <= 20'b0;
end else begin
clock60Hz <= 1'b0;
... | 7.011083 |
module nes_fsm (
clock,
clock60hz,
clock6us,
latch,
pulse,
data,
a,
b,
sel,
st,
up,
down,
left,
right
);
input clock, clock60hz, clock6us;
output latch, pulse;
input data;
output a, b, sel, st, up, down, left, right;
parameter[2:0] WAIT=3'b000, LATCH=... | 6.539374 |
module hex_decoder (
hex_out,
val
);
input [3:0] val;
output [7:0] hex_out;
mux16to1 u0 (
1'b0,
1,
0,
0,
1,
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
0,
val[0],
val[1],
val[2],
val[3],
hex_ou... | 7.584821 |
module mux16to1 (
x1,
x2,
x3,
x4,
x5,
x6,
x7,
x8,
x9,
x10,
x11,
x12,
x13,
x14,
x15,
x16,
s1,
s2,
s3,
s4,
out
);
input x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16, s1, s2, s3, s4;
output out;
wire connect1... | 7.318793 |
module mux8to1 (
x1,
x2,
x3,
x4,
x5,
x6,
x7,
x8,
s1,
s2,
s3,
out
);
input x1, x2, x3, x4, x5, x6, x7, x8, s1, s2, s3;
output out;
wire connect1, connect2;
mux4to1 u0 (
.x1 (x1),
.x2 (x2),
.x3 (x3),
.x4 (x4),
.s1 (s1),
.s2 (s2),... | 7.465042 |
module mux4to1 (
x1,
x2,
x3,
x4,
s1,
s2,
out
);
input x1, x2, x3, x4, s1, s2;
output out;
wire connect1, connect2;
mux2to1 u0 (
.x(x1),
.y(x2),
.s(s1),
.m(connect1)
);
mux2to1 u1 (
.x(x3),
.y(x4),
.s(s1),
.m(connect2)
);
mux2to... | 7.010477 |
module mux2to1 (
x,
y,
s,
m
);
input x; //select 0
input y; //select 1
input s; //select signal
output m; //output
//assign m = s & y | ~s & x;
// OR
assign m = s ? y : x;
endmodule
| 7.107199 |
module spaceinvaders (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
LEDR,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_S... | 7.385663 |
module counterDraw (
input clock,
input reset,
output reg q
);
reg [21:0] count;
always @(posedge clock) begin
if (!reset) begin
count <= 22'd0;
q <= 1'd0;
end else begin
if (count < 24'b111101000010010000000) begin
// if(count < 20'd10000) begin
count <= co... | 6.950832 |
module space_start (
input clk,
input rst,
input ext,
input [7:0] keycode,
input make,
output reg startGame
);
parameter SPACE = 8'h29;
initial startGame <= 0;
always @(posedge clk)
if (rst) startGame <= 0;
else
case ... | 7.096019 |
module space_vector_modulator #(
parameter current_bits = 4,
parameter microstep_bits = 8,
parameter phase_ct_bits = 8,
parameter center_aligned = 1,
parameter phases = 2,
parameter microsteps = 64
) (
input clk,
input resetn,
input pwm_clk,
output [phases-1:0] vref_pwm,
//ou... | 7.24844 |
modules
//------------------------------------------------------------------------------
module space_wire_sync_one_pulse
(
input wire i_clk,
input wire i_async_clk,
input wire i_reset_n,
input wire i_async_in,
output wire o_sync_out
);
//----------------------... | 7.831093 |
modules
//------------------------------------------------------------------------------
module space_wire_time_code_control
(
input wire i_clk,
input wire i_reset_n,
input wire i_rx_clk,
input wire i_got_time_code,
input wire [... | 7.831093 |
module SPad #(
parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH = 9
) (
input clk,
input reset,
input read_req,
input write_en,
input [ADDR_BITWIDTH-1 : 0] r_addr,
input [ADDR_BITWIDTH-1 : 0] w_addr,
input [DATA_BITWIDTH-1 : 0] w_data,
output [DATA_BITWIDTH-1 : 0] r_data
);
... | 7.909722 |
module getSpan_equal (
input clk_en,
input clk_base,
input clk_test_1,
input clk_test_2,
output reg [31:0] count_1,
output reg [31:0] count_2,
output reg isCount = 0,
output reg pin_r
);
reg [31:0] count_1_hide;
reg [31:0] count_2_hide;
//门控
always @(posedge clk_test_1) begin
... | 7.811042 |
module sparc_exu_rml_inc3 ( /*AUTOARG*/
// Outputs
dout,
// Inputs
din,
inc
);
input [2:0] din;
input inc;
output [2:0] dout;
assign dout[2] = ((~din[2] & ~din[1] & ~din[0] & ~inc) |
(~din[2] & din[1] & din[0] & inc) |
(din[2] & d... | 6.786149 |
module sparc_ffu_part_add32 ( /*AUTOARG*/
// Outputs
z,
// Inputs
a,
b,
cin,
add32
);
input [31:0] a;
input [31:0] b;
input cin;
input add32;
output [31:0] z;
wire cout15; // carry out from lower 16 bit add
wire cin16; // carry in to the upper 16 bit add
assign cin16 ... | 6.841442 |
module sparc_ifu_sscan (
ctu_sscan_snap,
ctu_sscan_se,
ctu_tck,
lsu_sscan_test_data,
tlu_sscan_test_data,
swl_sscan_thrstate,
ifq_sscan_test_data,
sparc_sscan_so,
rclk,
si,
so,
se
);
input ctu_sscan_snap;
input ctu_sscan_se;
input ctu_tck;
input si;
input se;
... | 6.596396 |
module sparc_tlu_penc64 ( /*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [63:0] in;
output [5:0] out;
reg [5:0] out;
integer i;
always @(in) begin
//
// code modified for verplex to avoid inferred latches
// if (in == 64'b0) // don't want a latch
out = 6'b0;
/... | 6.582247 |
module spare_logic_block (
`ifdef USE_POWER_PINS
inout VDD,
inout VSS,
`endif
output [30:0] spare_xz, // Constant 0 outputs (and block inputs)
output [3:0] spare_xi, // Inverter outputs
output spare_xib, // Big inverter output
output [1:0] spare_xna, // NAND outputs
output [1:0] spare_x... | 7.245444 |
module SparseCNN #(
parameter input_size = 28,
parameter kernel_size = 5,
parameter word_length = 8, // used for data
parameter col_length = 8,
parameter double_word_length = 16, // used for utils number,
parameter output_size = 24,
parameter PE_output_size = 16,
parameter PE_weight_ro... | 8.904559 |
modules together and
// performs the intreactions between the serial input (rx) and output (tx) as well as the
// databus and signals from the driver. It connects the bus interface, tx, rx, and baud generator
// together
//////////////////////////////////////////////////////////////////////////////////////////////
mo... | 8.250554 |
module Spartan3StarterKit (
// Clock Sources
CLK50MHZ,
SOCKET,
// Fast, Asynchronous SRAM
SRAM_A,
SRAM_WE_X,
SRAM_OE_X,
SRAM_IO_A,
SRAM_CE_A_X,
SRAM_LB_A_X,
SRAM_UB_A_X,
SRAM_IO_B,
SRAM_CE_B_X,
SRAM_LB_B_X,
SRAM_UB_B_X,
// Four-Digit, Saven-Segment LED Dis... | 7.180055 |
module DCM (
CLK0,
CLK180,
CLK270,
CLK2X,
CLK2X180,
CLK90,
CLKDV,
CLKFX,
CLKFX180,
LOCKED,
PSDONE,
STATUS,
CLKFB,
CLKIN,
DSSEN,
PSCLK,
PSEN,
PSINCDEC,
RST
); // synthesis syn_black_box
parameter CLK_FEEDBACK = "1X";
parameter CLKDV_DIVIDE ... | 6.58978 |
module IBUFGDS_LVPECL_33 (
O,
I,
IB
); // synthesis syn_black_box
output O;
input I;
input IB;
endmodule
| 6.584593 |
module IBUFG_AGP (
O,
I
); // synthesis syn_black_box
output O;
input I;
endmodule
| 6.520006 |
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