code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module IBUFG_LVCMOS15 (
O,
I
); // synthesis syn_black_box
output O;
input I;
endmodule
| 6.645095 |
module IBUFG_LVCMOS18 (
O,
I
); // synthesis syn_black_box
output O;
input I;
endmodule
| 6.645095 |
module IBUFG_LVCMOS2 (
O,
I
); // synthesis syn_black_box
output O;
input I;
endmodule
| 6.862655 |
module IBUFG_LVCMOS25 (
O,
I
); // synthesis syn_black_box
output O;
input I;
endmodule
| 6.862655 |
module IBUFG_LVCMOS33 (
O,
I
); // synthesis syn_black_box
output O;
input I;
endmodule
| 6.84274 |
module IBUFG_LVTTL (
O,
I
); // synthesis syn_black_box
output O;
input I;
endmodule
| 6.785299 |
module LUT2_D (
LO,
O,
I0,
I1
); // synthesis xc_map=lut syn_black_box
output O;
output LO;
input I0;
input I1;
parameter INIT = 4'b0;
LUT2 d (
O,
I0,
I1
);
defparam d.INIT = INIT;
assign LO = O;
endmodule
| 6.610296 |
module MUXCY_D (
LO,
O,
CI,
DI,
S
); // synthesis syn_black_box
output O;
output LO;
input CI;
input DI;
input S;
endmodule
| 6.747696 |
module RAM16X1D (
DPO,
SPO,
A0,
A1,
A2,
A3,
D,
DPRA0,
DPRA1,
DPRA2,
DPRA3,
WCLK,
WE
); // synthesis syn_black_box
parameter INIT = 16'h0000;
output DPO;
output SPO;
input A0;
input A1;
input A2;
input A3;
input D;
input DPRA0;
input DPRA1;
input DPRA2;
input DPRA3;
input WCLK;
input WE;
endmodule
| 7.214201 |
module RAM16X2S (
O0,
O1,
A0,
A1,
A2,
A3,
D0,
D1,
WCLK,
WE
); // synthesis syn_black_box
parameter INIT_00 = 16'h0000;
parameter INIT_01 = 16'h0000;
output O0;
output O1;
input A0;
input A1;
input A2;
input A3;
input D0;
input D1;
input WCLK;
input WE;
endmodule
| 6.79591 |
module RAM16X4S (
O0,
O1,
O2,
O3,
A0,
A1,
A2,
A3,
D0,
D1,
D2,
D3,
WCLK,
WE
); //synthesis syn_black_box
parameter INIT_00 = 16'h0000;
parameter INIT_01 = 16'h0000;
parameter INIT_02 = 16'h0000;
parameter INIT_03 = 16'h0000;
output O0;
output O1;
output O2;
output O3;
input A0;
input A1;
input A2;
input A3;
input D0;
input D1;
input D2;
input D3;
input WCLK;
input WE;
endmodule
| 7.228089 |
module RAM64X1S (
O,
A0,
A1,
A2,
A3,
A4,
A5,
D,
WCLK,
WE
); // synthesis syn_black_box
parameter INIT = 64'h0000000000000000;
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input D;
input WCLK;
input WE;
endmodule
| 6.70696 |
module ROM16X1 (
O,
A0,
A1,
A2,
A3
); // synthesis syn_black_box
parameter INIT = 16'h0000;
output O;
input A0;
input A1;
input A2;
input A3;
endmodule
| 6.912224 |
module ROM32X1 (
O,
A0,
A1,
A2,
A3,
A4
); // synthesis syn_black_box
parameter INIT = 32'h00000000;
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
endmodule
| 6.860443 |
module ROM64X1 (
O,
A0,
A1,
A2,
A3,
A4,
A5
); // synthesis syn_black_box
parameter INIT = 64'h0000000000000000;
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
endmodule
| 7.252243 |
module ROM128X1 (
O,
A0,
A1,
A2,
A3,
A4,
A5,
A6
); // synthesis syn_black_box
parameter INIT = 128'h00000000000000000000000000000000;
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input A6;
endmodule
| 6.888303 |
module ROM256X1 (
O,
A0,
A1,
A2,
A3,
A4,
A5,
A6,
A7
); // synthesis syn_black_box
parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input A6;
input A7;
endmodule
| 7.225115 |
module SRLC16 (
Q,
Q15,
A0,
A1,
A2,
A3,
CLK,
D
); // synthesis syn_black_box
output Q;
output Q15;
input A0;
input A1;
input A2;
input A3;
input CLK;
input D;
endmodule
| 6.770168 |
module SRLC16E (
Q,
Q15,
A0,
A1,
A2,
A3,
CE,
CLK,
D
); // synthesis syn_black_box
output Q;
output Q15;
input A0;
input A1;
input A2;
input A3;
input CE;
input CLK;
input D;
endmodule
| 6.802804 |
module SRLC16E_1 (
Q,
Q15,
A0,
A1,
A2,
A3,
CE,
CLK,
D
); // synthesis syn_black_box
output Q;
output Q15;
input A0;
input A1;
input A2;
input A3;
input CE;
input CLK;
input D;
endmodule
| 6.554028 |
module SRLC16_1 (
Q,
Q15,
A0,
A1,
A2,
A3,
CLK,
D
); // synthesis syn_black_box
output Q;
output Q15;
input A0;
input A1;
input A2;
input A3;
input CLK;
input D;
endmodule
| 6.699982 |
module XORCY (
O,
CI,
LI
); // synthesis syn_black_box
output O;
input CI;
input LI;
endmodule
| 6.992694 |
module IBUFGDS_LVPECL_25 (
O,
I,
IB
); // synthesis syn_black_box
output O;
input I, IB;
endmodule
| 6.584593 |
module spartan6_clocks (
input rst,
input sysclk_p,
input sysclk_n,
output clk_eth,
output clk_1x_90,
output clk_2x_0,
output pll_lock
);
parameter clkin_period = 5;
parameter dcm_mult = 5;
parameter dcm_div = 8;
parameter plladv_mult = 5;
parameter plladv_div0 = 16;
parameter plladv_div1 = 8;
wire xclk125_buf, clk_int_buf, clk_int;
wire sysclk_buf;
wire pll_clkfb;
`ifdef SIMULATE
assign clk_2x_0 = sysclk_p;
reg clk_r = 0;
always @(negedge clk_2x_0) clk_r <= #1.25 ~clk_r;
assign clk_1x_90 = clk_r;
assign clk_eth = clk_r;
`else
IBUFGDS #(
.DIFF_TERM("FALSE"),
.IBUF_DELAY_VALUE("0"),
.IOSTANDARD("LVDS_25")
) inibufgds (
.O (sysclk_buf),
.I (sysclk_p),
.IB(sysclk_n)
);
//---------- 125 MHz TX clock ----------
DCM_SP #(
.CLKDV_DIVIDE(4.0),
.CLKFX_DIVIDE(dcm_div), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(dcm_mult), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(clkin_period), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
.DLL_FREQUENCY_MODE("HIGH"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_SP_clk125tx (
.CLKFX (xclk125_buf), // DCM CLK synthesis out (M/D)
.CLKFB (clk_eth), // DCM clock feedback
.CLKIN (clk_int), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK (1'b0), // Dynamic phase adjust clock input
.PSEN (1'b0), // Dynamic phase adjust enable input
.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement
.RST (rst) // DCM asynchronous reset input
);
BUFG bufg125_tx (
.I(xclk125_buf),
.O(clk_eth)
);
PLL_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKIN1_PERIOD(clkin_period),
.CLKFBOUT_MULT(plladv_mult), // 200x5=1000
.DIVCLK_DIVIDE(1),
.CLKFBOUT_PHASE(0.0),
.CLKOUT0_DIVIDE(plladv_div0),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(90.0), // 62.5 MHz
.CLKOUT1_DIVIDE(plladv_div1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0.0), // 125 MHz
.CLKOUT2_DIVIDE(plladv_mult),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0.0), // 200 MHz
.REF_JITTER(0.005),
.COMPENSATION("SYSTEM_SYNCHRONOUS")
) PLL_ADV_inst (
.CLKINSEL(1'b1),
.CLKIN1 (sysclk_buf),
.CLKOUT0 (clk_1x_buf), // 62.5 MHz, 90 degree
.CLKOUT1 (clk_2x_buf), // 125 MHz, 0 degree
.CLKOUT2 (clk_int_buf), // 200 MHz, 0 degree
.CLKFBOUT(pll_clkfb),
.LOCKED (pll_lock),
.DADDR (5'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.REL (1'b0),
.RST (rst),
.CLKFBIN (pll_clkfb)
);
BUFG clk_1x_bufg (
.I(clk_1x_buf),
.O(clk_1x_90)
);
BUFG clk_2x_bufg (
.I(clk_2x_buf),
.O(clk_2x_0)
);
BUFG clk_200_bufg (
.I(clk_int_buf),
.O(clk_int)
);
`endif // `define SIMULATE
endmodule
| 6.640304 |
module spartan6_dcm (
// Inputs
input clkref_i
// Outputs
, output clkout0_o
);
wire clkref_buffered_w;
wire clkfb;
wire clk0;
wire clkfx;
// Input buffering
IBUFG IBUFG_IN (
.I(clkref_i),
.O(clkref_buffered_w)
);
// Clocking primitive
DCM_SP #(
.CLKDV_DIVIDE(2.000),
.CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(8),
.CLKIN_PERIOD(166.666666667),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("1X"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT(0)
) dcm_sp_inst (
.CLKIN(clkref_buffered_w),
.CLKFB(clkfb),
// Output clocks
.CLK0(clk0), // 48MHz
.CLK90(),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLKFX(clkfx),
.CLKFX180(),
.CLKDV(),
// Ports for dynamic phase shift
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PSDONE(),
// Other control and status signals,
.LOCKED(),
.STATUS(),
.RST(1'b0),
// Unused pin, tie low
.DSSEN(1'b0)
);
BUFG clkfb_buf (
.I(clk0),
.O(clkfb)
);
//-----------------------------------------------------------------
// CLK_OUT0
//-----------------------------------------------------------------
BUFG clkout0_buf (
.I(clkfx),
.O(clkout0_o)
);
endmodule
| 7.448689 |
module spartan6_pll (
// Inputs
input clkref_i
// Outputs
, output clkout0_o
);
wire clkref_buffered_w;
wire clkfbout_w;
wire pll_clkout0_w;
wire pll_clkout0_buffered_w;
// Input buffering
assign clkref_buffered_w = clkref_i;
// Clocking primitive
PLL_BASE #(
.BANDWIDTH ("OPTIMIZED"),
.CLK_FEEDBACK ("CLKFBOUT"),
.COMPENSATION ("INTERNAL"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (13), // VCO=624MHz
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (2), // CLK0=312MHz
.CLKOUT0_PHASE (0.0),
.CLKOUT0_DUTY_CYCLE(0.500),
.CLKIN_PERIOD (20.8333333333),
.REF_JITTER (0.010)
) pll_base_inst (
.CLKFBOUT(clkfbout_w),
.CLKOUT0(pll_clkout0_w),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.RST(1'b0),
.CLKFBIN(clkfbout_w),
.CLKIN(clkref_buffered_w)
);
//-----------------------------------------------------------------
// CLK_OUT0
//-----------------------------------------------------------------
BUFG clkout0_buf (
.I(pll_clkout0_w),
.O(pll_clkout0_buffered_w)
);
assign clkout0_o = pll_clkout0_buffered_w;
endmodule
| 6.599485 |
module spart_rx_old (
input clk,
input rst,
input enable,
input rxd,
output reg [7:0] data,
output [7:0] rx_capture,
output rda
);
reg [8:0] rx_buf;
reg [3:0] bit_cnt;
reg [4:0] en_cnt;
reg start_detected;
reg old;
reg [4:0] old_en_cnt;
wire count;
wire sample;
// Single cycle signals used as enables to flops
assign count = en_cnt == 5'd16 & old_en_cnt == 5'd15;
assign zero = en_cnt == 5'd1 & old_en_cnt == 5'd16;
assign sample = en_cnt == 5'd8 & old_en_cnt == 5'd7;
always @(posedge clk, posedge rst)
if (rst) old = 1;
else if (enable) old = rxd;
// Falling edge detector for detecting start bit
always @(posedge clk, posedge rst)
if (rst) start_detected = 0;
else if (bit_cnt == 0 && ~rxd && old) start_detected = 1;
else if (bit_cnt == 4'd0 && zero) start_detected = 0;
always @(posedge clk, posedge rst)
if (rst) old_en_cnt = 5'h00;
else old_en_cnt = en_cnt;
always @(posedge clk, posedge rst)
if (rst) rx_buf = 9'b111111111;
else if (start_detected && sample) rx_buf = {rxd, rx_buf[8:1]};
wire [4:0] in;
// Counter keeping track of the number of enable signals received
assign in = start_detected ?
~enable ? en_cnt :
enable ? (en_cnt == 5'd16) ? 5'h01 : ( en_cnt + 1 ) : 5'h01 : 5'h00;
always @(posedge clk, posedge rst)
if (rst) en_cnt = 5'h00;
else en_cnt = in;
// Counts from zero to ten keeping track of how many bits have been received
always @(posedge clk, posedge rst)
if (rst) begin
bit_cnt = 4'd0;
end else if (bit_cnt == 4'd10 && count) begin
bit_cnt = 4'd0;
end else if (rx_buf[8] == 0 && bit_cnt == 0 && count) bit_cnt = 4'd1;
else if (count && bit_cnt > 0) begin
bit_cnt = bit_cnt + 1;
end
always @(posedge clk, posedge rst)
if (rst) data = 8'hFF;
else if (bit_cnt == 4'd10 && sample) data = rx_buf[7:0];
// Test signal
assign rx_capture = data;
assign rda = bit_cnt == 4'd10 && count ? 1 : 0;
endmodule
| 6.778364 |
module spart_tb ();
reg stm_clk, stm_rst, stm_iocs, stm_iorw, stm_databus_oe, stm_wrt_tx, stm_rd_rx;
reg [1:0] stm_ioaddr;
reg [7:0] stm_databus_in, stm_tx_data;
wire rda_mon, tbr_mon, txd_mon, rx_in, tx_en, tb_rda_mon;
wire [7:0] databus_inout, final_data_mon;
assign databus_inout = (stm_databus_oe) ? stm_databus_in : 8'hzz;
spart spart0 (
.clk(stm_clk),
.rst(stm_rst),
.iocs(stm_iocs),
.iorw(stm_iorw),
.rda(rda_mon),
.tbr(tbr_mon),
.ioaddr(stm_ioaddr),
.databus(databus_inout),
.txd(txd_mon),
.rxd(rx_in),
.tx_rx_en_out(tx_en)
);
tx tx_tb_1 (
.clk(stm_clk),
.rst(stm_rst),
.data(stm_tx_data),
.en(tx_en),
.en_tx(stm_wrt_tx),
.tbr(tbr_mon),
.TxD(rx_in)
);
rx rx_tb_1 (
.clk(stm_clk),
.rst(stm_rst),
.RxD(txd_mon),
.Baud(tx_en),
.RxD_data(final_data_mon),
.RDA(tb_rda_mon),
.rd_rx(stm_rd_rx)
);
always #5 stm_clk <= ~stm_clk;
initial begin
stm_clk = 0;
stm_rst = 1;
stm_iocs = 0;
stm_iorw = 0;
stm_databus_oe = 0;
stm_ioaddr = 2'b00;
// TX Init
stm_tx_data = 8'hA5;
stm_wrt_tx = 0;
// RX Init
stm_rd_rx = 0;
// Load Low Buffer
@(posedge stm_clk);
stm_rst = 0;
stm_iocs = 1;
stm_ioaddr = 2'b10;
stm_databus_oe = 1;
stm_databus_in = 8'h80;
// Load High Buffer
@(posedge stm_clk);
stm_ioaddr = 2'b11;
stm_databus_oe = 1;
stm_databus_in = 8'h25;
// Send Data (Ready to Receive)
@(posedge stm_clk);
// Trun off bus, get ready for read
stm_iocs = 0;
stm_ioaddr = 2'b00;
stm_iorw = 1;
stm_databus_oe = 0;
// Start sending spart data
stm_wrt_tx = 1;
@(posedge stm_clk);
stm_wrt_tx = 0;
@(posedge rda_mon) stm_iocs = 1;
repeat (10) @(posedge stm_clk);
$display("Spart received: %h", databus_inout);
repeat (10) @(posedge stm_clk);
stm_ioaddr = 2'b00;
stm_iorw = 0;
stm_databus_oe = 1;
stm_databus_in = 8'hAC;
@(posedge stm_clk);
stm_iocs = 0;
stm_databus_oe = 0;
@(posedge tb_rda_mon);
repeat (100) @(posedge stm_clk);
$stop();
end
endmodule
| 6.631748 |
module spart_tx_old (
input clk,
input rst,
input enable,
input [7:0] data,
input [1:0] ioaddr,
input iorw,
output txd,
output tbr,
output reg [7:0] tx_capture
);
reg load, transmitting;
wire [3:0] bit_cnt;
reg [4:0] en_cnt, old_en_cnt;
localparam IDLE = 1'b0;
localparam TRMT = 1'b1;
wire trmt;
assign trmt = (ioaddr == 2'b00 && ~iorw);
wire shift;
assign shift = en_cnt == 5'd16 && old_en_cnt == 5'd15;
always @(posedge clk, posedge rst)
if (rst) old_en_cnt = 5'h00;
else old_en_cnt = en_cnt;
reg state, nxt_state, set_done, clr_done;
cnt_4bit bit_counter (
.en({load, shift}),
.clk(clk),
.rst(rst),
.bit_cnt(bit_cnt)
);
tx_shift_reg shift_register (
.en({load, shift}),
.clk(clk),
.rst(rst),
.tx_data(data),
.TX(txd)
);
tx_sr_ff tx_done_flop (
.q (tbr),
.s (set_done),
.r (clr_done),
.rst(rst),
.clk(clk)
);
wire [4:0] in;
// Counts the number of enable signals
assign in = transmitting ?
~enable ? en_cnt :
enable ? (en_cnt == 5'd16) ? 5'h01 : ( en_cnt + 1 ) : 5'h01 : 5'h00;
always @(posedge clk, posedge rst)
if (rst) en_cnt = 5'h00;
else en_cnt = in;
// Test signal - Captures data in buffer
always @(posedge clk, posedge rst)
if (rst) tx_capture <= 8'hFF;
else if (load) tx_capture <= data;
always @(posedge clk, posedge rst) begin
if (rst) state <= IDLE;
else state <= nxt_state;
end
always @(*) begin
nxt_state = IDLE;
load = 0;
transmitting = 0;
set_done = 0;
clr_done = 0;
case (state)
IDLE: begin
if (trmt) begin
nxt_state = TRMT;
clr_done = 1;
load = 1;
transmitting = 1;
end
end
TRMT: begin
if (bit_cnt == 4'd10 && shift) begin
nxt_state = IDLE;
set_done = 1;
clr_done = 0;
end else begin
nxt_state = TRMT;
clr_done = 0;
transmitting = 1;
end
end
default: nxt_state = IDLE;
endcase
end
endmodule
| 6.626413 |
module cnt_4bit (
en,
clk,
rst,
bit_cnt
);
input clk, rst;
input [1:0] en; // {load, shift}
output reg [3:0] bit_cnt;
wire [3:0] in;
reg old;
wire shift;
assign in = ~|en ? bit_cnt : ~en[1] ? (bit_cnt == 4'd10) ? 4'h0 : (bit_cnt + 1) : 4'h0;
// Edge detector to hold the shift enable high for a single clock cycle
always @(posedge clk, posedge rst)
if (rst) old = 0;
else old = en[0];
assign shift = en[0] && ~old;
always @(posedge clk, posedge rst)
if (rst) bit_cnt <= 4'h0;
else if (shift) bit_cnt <= in;
endmodule
| 7.453869 |
module tx_shift_reg (
en,
clk,
rst,
tx_data,
TX
);
input clk, rst;
input [1:0] en; // {load, shift}
input [7:0] tx_data;
output TX;
wire [9:0] in;
reg [9:0] tx_shft_reg;
reg old;
wire shift;
// Edge detector to hold the shift enable high for a single clock cycle
always @(posedge clk, posedge rst)
if (rst) old = 0;
else old = en[0];
assign shift = en[0] && ~old;
assign in = ~|en ? tx_shft_reg : ~en[1] ? {1'b1, tx_shft_reg[9:1]} : {1'b1, tx_data, 1'b0};
assign TX = tx_shft_reg[0];
always @(posedge clk, posedge rst)
if (rst) tx_shft_reg <= 10'h3FF;
else if (en[1] || shift) tx_shft_reg <= in;
endmodule
| 7.005889 |
module spawner (
clk,
reset,
enable,
frequency,
spawn,
out
);
input clk, reset, enable;
// input clk should be CLOCK_50
input [1:0] frequency;
// frequency at which the pseudo_random numbers cycle. Also determines how long the spawn signal will be held for.
// 00 for making it enable signal, 01 for 1hz, 10 for 2hz, 11 for 3hz
output spawn;
output [9:0] out;
// 10 digit output, can handle up to height of 1023 pixels
// might have to put an if statement in the drawing module if the height has to be i.e. between 0 and 800, to check if out value is in the range
wire hertzclk;
wire spawnenable;
wire onesecond;
// the modules were written with activehigh reset so it is negated in the modules below
slowclk c0 (
clk,
~reset,
enable,
frequency,
hertzclk
);
slowclk c1 (
clk,
~reset,
enable,
2'b01,
onesecond
);
LFSR lfsr0 (
hertzclk,
~reset,
spawnenable,
spawn,
out
);
spawncountdown sp0 (
onesecond,
~reset,
enable,
spawn,
3'b011,
spawnenable
);
// wait for minimum 3 seconds between spawns
endmodule
| 7.87409 |
module slowclk (
clk,
reset,
enable,
frequency,
out
);
input clk, reset, enable;
// should make input clk be CLOCK_50
input [1:0] frequency;
output reg out;
// this is the slower 'clock', will output 0 or 1
wire [27:0] w1hz, w2hz, w3hz;
ratedivider r1hz (
enable,
{2'b00, 26'd49999999},
clk,
reset,
w1hz
);
ratedivider r2hz (
enable,
{3'b000, 25'd24999999},
clk,
reset,
w2hz
);
ratedivider r3hz (
enable,
{4'b0000, 24'd16666666},
clk,
reset,
w3hz
);
// faster dividers for testing. Uncomment top and comment below for actual.
// ratedivider r1hz(enable, {26'd0, 2'b11}, clk, reset, w1hz);
// ratedivider r2hz(enable, {26'd0, 2'b10}, clk, reset, w2hz);
// ratedivider r3hz(enable, {26'd0, 2'b01}, clk, reset, w3hz);
always @(*) begin
case (frequency)
2'b00: out <= enable;
2'b01: out <= (w1hz == 28'd0) ? 1'b1 : 1'b0;
2'b10: out <= (w2hz == 28'd0) ? 1'b1 : 1'b0;
2'b11: out <= (w3hz == 28'd0) ? 1'b1 : 1'b0;
endcase
end
endmodule
| 7.153401 |
module LFSR (
clk,
reset,
enable,
spawn,
out
);
input clk, reset, enable;
// ToDo: make a counter hooked to enable so that there is a gap between each spawn. Make spawn reset the counter.
output reg [9:0] out;
// ToDo: set bits of out to match y-value of screen resolution - height of objects
output reg spawn;
reg [9:0] value;
wire linear_feedback;
assign linear_feedback = (value[1] ^ value[0]);
initial out = 10'b0;
initial spawn = 0;
initial value = 10'b0010010100;
always @(posedge clk, posedge reset) begin
if (reset) begin
// seed
value <= 10'b0010010100;
// ToDo: adjust out bits if necessary
out <= 10'b0;
spawn <= 0;
end else if (enable) begin
value <= {
linear_feedback,
value[9],
value[8],
value[7],
value[6],
value[5],
value[4],
value[3],
value[2],
value[1]
};
out <= value[9:0];
spawn <= linear_feedback;
end else begin
out <= 10'b0;
spawn <= 0;
end
end
endmodule
| 6.729795 |
module ratedivider (
enable,
load,
clk,
reset,
q
);
input enable, clk, reset;
input [27:0] load;
output reg [27:0] q;
initial q = load;
always @(posedge clk) begin
if (reset) q <= load;
else if (enable) begin
if (q == 28'd0) q <= load;
else q <= q - 1'b1;
end
end
endmodule
| 8.084012 |
module SPC ( /*AUTOARG*/
// Outputs
spco,
spcptr,
// Inputs
clk,
reset,
state_fetch,
spcw,
spcnt,
spush,
srp,
swp
);
input clk;
input reset;
input state_fetch;
input [18:0] spcw;
input spcnt;
input spush;
input srp;
input swp;
output [18:0] spco;
output [4:0] spcptr;
////////////////////////////////////////////////////////////////////////////////
localparam ADDR_WIDTH = 5;
localparam DATA_WIDTH = 19;
localparam MEM_DEPTH = 32;
reg [4:0] spcptr;
wire [4:0] spcadr;
////////////////////////////////////////////////////////////////////////////////
wire [4:0] spcptr_p1;
assign spcptr_p1 = spcptr + 5'b00001;
assign spcadr = (spcnt && spush) ? spcptr_p1 : spcptr;
`ifndef ISE
reg [18:0] ram[0:31];
reg [18:0] out_a;
reg [18:0] out_b;
reg swp_cond;
always @(posedge clk) begin
swp_cond <= (swp && spcadr == spcptr);
out_b <= spcw;
end
assign spco = (swp_cond) ? out_a : out_b;
always @(posedge clk) begin
if (swp) begin
ram[spcadr] <= spcw;
end
end
always @(posedge clk) begin
if (srp) begin
out_a <= ram[spcptr];
end
end
/*
always @(posedge clk)
if (1'b0) begin
ram[spcptr] <= 19'b0;
end else if (swp) begin
ram[spcadr] <= spcw;
end
always @(posedge clk)
if (reset)
out_a <= 0;
else if (srp && ~swp) begin
/ * WE NEED 'READ NEW DATA' ON SIMULTANEOUS WRITE/READ TO SAME ADDR * /
if (swp && spcadr == spcptr) begin
out_a <= spcw;
end else begin
out_a <= ram[spcptr];
end
end
*/
`else
wire ena_a = srp && ~swp | 1'b0;
wire ena_b = 1'b0 | swp;
ise_SPC inst (
.clka (clk),
.ena (ena_a),
.wea (1'b0),
.addra(spcptr),
.dina (19'b0),
.douta(spco),
.clkb (clk),
.enb (ena_b),
.web (swp),
.addrb(spcadr),
.dinb (spcw),
.doutb()
/*AUTOINST*/);
`endif
always @(posedge clk)
if (reset) spcptr <= 0;
else if (state_fetch) begin
if (spcnt) begin
if (spush) spcptr <= spcptr + 5'd1;
else spcptr <= spcptr - 5'd1;
end
end
endmodule
| 6.546698 |
module spcm_core_nexys3 (
input wire clk, // main clock
input wire rst, // synchronous reset
input wire cs, // chip select
input wire [ADDR_BITS-1:2] addr, // address
input wire burst, // burst mode flag
output reg [31:0] dout, // data read in
output reg busy, // busy flag
output reg ack, // acknowledge
// Serial PCM interfaces
output wire spcm_cs_n,
output wire spcm_sck,
output wire spcm_mosi,
input wire spcm_miso
);
parameter ADDR_BITS = 24; // address length for serial PCM
reg spi_en;
reg [31:0] spi_din;
wire [31:0] spi_dout;
wire spi_ack;
wire spi_busy;
spi_core_fast #(
.SPI_CPHA (0),
.SPI_CPOL (0),
.SPI_LSBFE(0),
.DATA_BITS(32)
) SPCM_SPI (
.clk (clk),
.rst (rst),
.en (spi_en),
.din (spi_din),
.dout(spi_dout),
.ack (spi_ack),
.busy(spi_busy),
.sck (spcm_sck),
.miso(spcm_miso),
.mosi(spcm_mosi)
);
assign spcm_cs_n = ~spi_busy;
localparam S_IDLE = 0, // idle
S_SEND = 1, // send command
S_RECV = 2, // receive data
S_DONE = 3; // wait until SPI core is not busy
reg [1:0] state = 0;
reg [1:0] next_state;
always @(*) begin
next_state = 0;
case (state)
S_IDLE: begin
if (cs) next_state = S_SEND;
else next_state = S_IDLE;
end
S_SEND: begin
if (spi_ack) next_state = S_RECV;
else next_state = S_SEND;
end
S_RECV: begin
if (spi_ack && ~burst) next_state = S_DONE;
else next_state = S_RECV;
end
S_DONE: begin
if (~spi_busy) next_state = S_IDLE;
else next_state = S_DONE;
end
endcase
end
always @(posedge clk) begin
if (rst) state <= 0;
else state <= next_state;
end
always @(*) begin
spi_en = 0;
spi_din = 0;
dout = 0;
busy = 0;
ack = 0;
case (state)
S_SEND: begin
busy = 1;
spi_en = 1;
spi_din = {8'h3, addr, 2'b0};
end
S_RECV: begin
spi_en = 1;
busy = 1;
dout = spi_dout;
ack = spi_ack;
end
endcase
end
endmodule
| 9.179782 |
module SPController (
input entry_sensor,
exit_sensor,
clk,
resetn,
input [7:0] entered_pass,
output reg entry,
NoSpace,
exit
);
reg [1:0] cur_s, nex_s;
parameter sensor = 2'b00, password = 2'b01, entrance = 2'b10, space = 2'b11;
parameter passkey = 8'hA4;
reg mem[0:49];
reg [5:0] j_reg, j_nex;
reg entr, ext;
integer i;
always @(posedge clk) begin
if (~resetn) begin
cur_s <= sensor;
j_reg <= 0;
for (i = 0; i < 50; i = i + 1) begin
mem[i] = 0;
end
//entr <= entry_sensor;
//exr <= exit_sensor;
end else begin
cur_s <= nex_s;
j_reg <= j_nex;
//entr <= entn;
//exr <= exn;
end
end
always @(*) begin
if (entry_sensor) begin
entr <= 1;
ext <= 0;
end else if (exit_sensor) begin
entr <= 0;
ext <= 1;
end
end
always @(*) begin
nex_s = cur_s;
entry = 0;
exit = 0;
NoSpace = 0;
j_nex = j_reg;
case (cur_s)
sensor: begin
if (entr) begin
nex_s = password;
end else if (ext) begin
nex_s = space;
exit = 1;
end
end
password: begin
if (entered_pass == passkey) nex_s = entrance;
else nex_s = cur_s;
end
entrance: begin
entry = 1;
nex_s = space;
end
space: begin
if (j_reg < 50) begin
if (mem[j_reg] == 0 && entr) begin
mem[j_reg] = 1;
nex_s = sensor;
j_nex = j_reg + 1;
end else if (ext) begin
mem[j_reg] = 0;
j_nex = j_reg + 1;
nex_s = sensor;
end else begin
nex_s = space;
end
end else begin
j_nex = 0;
nex_s = sensor;
if (entr) NoSpace = 1;
else if (ext) NoSpace = 0;
end
end
endcase
end
endmodule
| 7.072054 |
module spc_pcx_buf ( /*AUTOARG*/
// Outputs
spc_pcx_data_pa,
spc_pcx_atom_pq,
spc_pcx_req_pq,
pcx_spc_grant_px_buf,
// Inputs
spc_pcx_data_pa_buf,
spc_pcx_atom_pq_buf,
spc_pcx_req_pq_buf,
pcx_spc_grant_px
);
input [`PCX_WIDTH-1:0] spc_pcx_data_pa_buf;
input spc_pcx_atom_pq_buf;
input [4:0] spc_pcx_req_pq_buf;
input [4:0] pcx_spc_grant_px;
output [`PCX_WIDTH-1:0] spc_pcx_data_pa;
output spc_pcx_atom_pq;
output [4:0] spc_pcx_req_pq;
output [4:0] pcx_spc_grant_px_buf;
assign spc_pcx_req_pq = spc_pcx_req_pq_buf;
assign spc_pcx_atom_pq = spc_pcx_atom_pq_buf;
assign spc_pcx_data_pa = spc_pcx_data_pa_buf;
assign pcx_spc_grant_px_buf = pcx_spc_grant_px;
endmodule
| 6.901589 |
module SPDIFdecoder (
input SPDIFin,
output [1:0] BMCdec,
input clk,
output reg edgeclk = 0,
output reg clkout = 0,
output reg [27:0] Dout = 0,
output reg [1:0] synccode = 0, //B=1,M=2,W=3,ERROR=0
output reg parityOK=0,//パリティチェック結果が正しければ1,誤りで0(paritycheck:OK=1,NG=0)
output [23:0] AudioL,
output [23:0] AudioR,
output reg Audioclk = 0
);
reg [23:0] AudioL1 = 0;
reg [23:0] AudioR1 = 0;
reg SPDIF1 = 0;
reg SPDIF2 = 0;
reg [11:0] freqcounter = 0;
reg [5:0] timecounter = 1;
reg [3:0] timereg = 0;
reg [1:0] BMC0 = 0;
reg [1:0] BMC1 = 0;
reg [1:0] BMC2 = 0;
reg [1:0] BMC3 = 0;
reg [1:0] BMC4 = 0;
reg [6:0] countbits = 0;
reg [1:0] syncreg = 0;
reg [27:0] bufdat = 0;
wire [1:0] synccodew;
wire [1:0] freqselw;
reg [1:0] freqselmax = 0;
reg [1:0] freqsel = 0;
reg [23:0] AudioLbuf = 0;
reg [23:0] AudioRbuf = 0;
reg [23:0] timeoutdt = 0;
reg noneSIGNAL = 0;
assign AudioL = noneSIGNAL ? 0 : AudioL1;
assign AudioR = noneSIGNAL ? 0 : AudioR1;
/////////////////パルス時間検出部//////////////////////////////////
always @(posedge clk) begin //パルス時間検出部(pulse time detection)
SPDIF1 <= SPDIFin; //メタステ対策
SPDIF2 <= SPDIF1;
if((SPDIF1!=SPDIF2)&&(timecounter>3))begin//変化エッジ検出(changing edge detection )
noneSIGNAL = 0;
edgeclk = 0; //変化ごとのクロック(changing edge clock )
timereg <= (timecounter < 6'h3f) ? (timecounter >> 2) : 0;
timecounter <= 1;
end else if (timecounter < 6'h3f) timecounter <= timecounter + 1;
else noneSIGNAL = 1;
if (timecounter == 2) edgeclk = 1;
end
////////////////自動周波数検出(auto frequency detection)//////////////////////////////////
assign freqselw = timereg[3] ? 3 : (timereg[2] ? 2 : (timereg[1] ? 1 : 0));
always @(posedge clk) begin //frequency detector
if (freqcounter < 12'hfff) freqcounter = freqcounter + 1;
if ((freqselw >= freqselmax) || freqcounter == 12'hfff) begin
freqselmax <= freqselw;
freqcounter = 0;
end
if ((freqselw == freqselmax) /*&&(freqselmax!=0)*/) freqsel <= freqselmax;
//freqsel<=1;//192kHz固定
end
/////////////////時間幅信号をBMCパルス共通信号に変換(convert time width signal to pulse signal)//////////////////////////////////////
assign BMCdec = (freqsel == 0) ? 0 : (timereg >> (freqsel - 1));
/////////////////サブフレーム切り出し・出力(output subframe)////////////////////////////////////////////////
assign synccodew=(BMC3==3)?(BMC2==3?2:(BMC0==3?1:((BMC0==2&&BMC1==1&&BMC2==2)?3:0))):0;//1:B,2:M,3:W,0:Error
always @(posedge edgeclk) begin //サブフレーム取り出し
BMC0 <= BMCdec;
BMC1 <= BMC0;
BMC2 <= BMC1;
BMC3 <= BMC2;
BMC4 <= BMC3;
if (synccodew != 0) begin
countbits <= 3;
syncreg <= synccodew;
end else begin
countbits <= countbits + BMC3;
end
if (countbits > 8 && countbits[0] == 0) begin
bufdat = bufdat >> 1;
bufdat[27] = BMC4[0];
end
if (countbits == 7'h40) begin //サブフレーム１つ分受信したら出力する。
parityOK <= ~^bufdat;
Dout <= bufdat;
synccode <= syncreg;
clkout <= 0;
if (parityOK) timeoutdt <= 0;
else timeoutdt <= timeoutdt + 1;
if (timeoutdt < 192000) begin
if ((synccode == 1) || (synccode == 2)) begin //フレームごとにL／R同時に更新
AudioL1 <= AudioLbuf;
AudioR1 <= AudioRbuf;
if (parityOK) AudioLbuf <= Dout & 24'hffffff;
Audioclk <= 0;
end
if (synccode == 3) begin
Audioclk <= 1;
if (parityOK) AudioRbuf <= Dout & 24'hffffff; //Rのサブフレーム検出
end
end else begin
AudioL1 <= 0;
AudioR1 <= 0;
AudioLbuf <= 0;
AudioRbuf <= 0;
end
end
if (countbits == 7'h20) clkout <= 1;
end
endmodule
| 6.875902 |
module spdif_audio_encoder #(
parameter audio_width = 16
) (
input wire reset,
input wire clk,
input wire clk256,
input wire i_valid,
output wire i_ready,
input wire [audio_width-1:0] i_audio,
input wire i_is_left,
output wire spdif
);
reg clk128;
always @(posedge clk256 or posedge reset) clk128 <= (reset) ? 1'b0 : ~clk128;
wire o_ready;
wire o_valid;
wire o_is_left;
wire o_is_error;
wire [audio_width-1:0] o_audio;
dual_clock_buffer #(
.width(audio_width + 1)
) dbuffer_ (
.reset (reset),
.i_clk (clk),
.i_valid(i_valid),
.i_ready(i_ready),
.i_data ({i_is_left, i_audio}),
.o_clk (clk128),
.o_valid(o_valid),
.o_ready(o_ready),
.o_data ({o_is_left, o_audio})
);
spdif_frame_encoder #(
.audio_width(audio_width)
) encoder_ (
.clk128(clk128),
.reset(reset),
.next_sub_frame_number(),
.i_valid(o_valid),
.i_ready(o_ready),
.i_is_left(o_is_left),
.i_audio(o_audio),
.i_user(1'b0),
.i_control(1'b0),
.spdif(spdif)
);
endmodule
| 6.753542 |
module spdif_bmc_encoder #(
parameter width = 4
) (
input wire clk128,
input wire reset,
input wire i_valid,
output wire i_ready,
input wire [width-1:0] i_data,
output reg is_underrun,
output reg q
);
reg is_valid_shift;
reg [width-2:0] shift_data;
reg [$clog2(width-1)-1:0] shift_count;
reg is_loaded;
assign i_ready = !is_valid_shift;
always @(posedge clk128 or posedge reset) begin
if (reset) begin
q <= 1'b0;
shift_count <= 0;
is_valid_shift <= 1'b0;
shift_data <= 0;
is_underrun <= 1'b0;
is_loaded <= 1'b0;
end else begin
if (is_valid_shift) begin
shift_count <= shift_count - 1'b1;
shift_data <= shift_data << 1;
q <= q ^ shift_data[width-2];
is_valid_shift <= shift_count != 0;
is_underrun <= 1'b0;
is_loaded <= 1'b1;
end else begin
if (i_valid) begin
shift_data <= i_data[width-2:0];
shift_count <= width - 2;
q <= q ^ i_data[width-1];
is_valid_shift <= 1'b1;
is_underrun <= 1'b0;
is_loaded <= 1'b1;
end else begin
is_valid_shift <= 1'b0;
if (is_loaded) is_underrun <= 1'b1;
is_loaded <= 1'b0;
end
end
end
end
endmodule
| 6.545627 |
module spdif_bmc_encoder_tb ();
parameter STEP = 1000000000 / (44100 * 128);
initial begin
$dumpfile("spdif_bmc_encoder_tb.vcd");
$dumpvars(0, bmc_encoder_);
end
reg mclk;
initial begin
mclk = 1'b0;
forever #(STEP / 2) mclk = ~mclk;
end
reg reset;
reg i_valid;
wire i_ready;
wire is_underrun;
reg [3:0] data;
wire spdif;
spdif_bmc_encoder bmc_encoder_ (
.clk128(mclk),
.reset(reset),
.i_valid(i_valid),
.i_ready(i_ready),
.i_data(data),
.is_underrun(is_underrun),
.q(spdif)
);
spdif_decoder_tb decoder_tb_ (
.clk128(mclk),
.reset (reset),
.spdif (spdif)
);
task output_with_wait(input reg [3:0] w_data);
begin
i_valid <= 1'b1;
data <= w_data;
wait (i_ready) @(posedge mclk); // transfer
i_valid <= 1'b0;
@(posedge mclk);
end
endtask
task output_with_wait_multi(input [3:0] data1, input [3:0] data2);
begin
i_valid <= 1'b1;
data <= data1;
wait (i_ready) @(posedge mclk); // transfer
@(posedge mclk);
data <= data2;
wait (i_ready) @(posedge mclk); // transfer (burst)
i_valid <= 1'b0;
@(posedge mclk);
end
endtask
initial begin
// reset
reset = 1'b0;
i_valid = 1'b0;
repeat (2) @(posedge mclk) reset = 1'b1;
@(posedge mclk) reset <= 1'b0;
repeat (4) @(posedge mclk);
output_with_wait_multi(4'h9, 4'hC);
// output_with_wait(4'hC);
output_with_wait(4'hA);
output_with_wait(4'hA);
output_with_wait(4'hA);
output_with_wait(4'hA);
output_with_wait(4'hE);
output_with_wait(4'hA);
output_with_wait(4'hE);
output_with_wait(4'hB);
output_with_wait(4'hE);
output_with_wait(4'hB);
output_with_wait(4'hA);
output_with_wait(4'hB);
output_with_wait(4'hA);
output_with_wait(4'hA);
repeat (64) @(posedge mclk);
$finish;
end
endmodule
| 6.545627 |
module spdif_tx_tb;
// Signals
// -------
reg [15:0] audio_val = 16'h0000;
wire audio_ack;
wire spdif;
reg rst = 1'b1;
reg clk = 1'b0;
// DUT
// ---
// Encoder
spdif_tx #(
// Approximate 6.144 MHz clock from 25.125 MHz
// (we get 6.137 which is 0.1% off)
//.ACC_STEP (131),
.ACC_STEP(132),
.ACC_FRAC(5)
) spdif_I (
.spdif (spdif),
.spdif_tick(),
.audio_l ({2'b00, audio_val, 6'b000000}),
.audio_r ({2'b00, audio_val, 6'b000000}),
.ack (audio_ack),
.valid (1'b1),
.clk (clk),
.rst (rst)
);
// Data source
// -----------
// Triangle wave generator (750 Hz at 48 ksps)
always @(posedge clk) if (audio_ack) audio_val <= audio_val + 16'd1024;
// Test bench
// ----------
// Setup recording
initial begin
$dumpfile("spdif_tx_tb.vcd");
$dumpvars(0, spdif_tx_tb);
end
// Reset pulse
initial begin
#200 rst = 0;
#10000000 $finish;
end
// Clocks
always #19.9 clk = !clk; // 25.125 MHz
endmodule
| 8.26142 |
module
*
* Copyright (C) 2021 Sylvain Munaut <tnt@246tNt.com>
* SPDX-License-Identifier: CERN-OHL-P-2.0
*/
`default_nettype none
module spdif_word_code (
// 27-bit word input
input wire [ 1:0] word_preamble, // 00=B, 10=M, 11=W
input wire [26:0] word_payload,
output wire word_ack,
// Encoded bi-phase bit output
output reg bit_val,
input wire bit_ack,
// Clock / Reset
input wire clk,
input wire rst
);
// Signals
// -------
// Word
reg [ 7:0] word_preamble_bits;
wire [34:0] word_val;
wire pol;
// Shift register
reg [34:0] shift_data;
reg [ 3:0] shift_cnt1; // Preamble counter
reg [ 6:0] shift_cnt2; // Total counter
wire shift_last;
(* keep *)
wire shift_ce;
// Bi-Phase code
wire bp_in;
wire bp_cycle;
// Next-Word value
// ---------------
always @(*)
case (word_preamble)
2'b00: word_preamble_bits = 8'b00010111; // B
2'b10: word_preamble_bits = 8'b01000111; // M
2'b11: word_preamble_bits = 8'b00100111; // W
default: word_preamble_bits = 8'bxxxxxxxx;
endcase
assign word_val[34: 8] = word_payload;
assign word_val[ 7: 0] = word_preamble_bits ^ { 8{pol} };
assign pol = bit_val ^ bp_in;
// Shift regiter
// -------------
// Counters
always @(posedge clk or posedge rst)
if (rst) begin
shift_cnt1 <= 0;
shift_cnt2 <= 0;
end else if (bit_ack) begin
shift_cnt1 <= shift_last ? 4'd8 : (shift_cnt1 + {3'b000, shift_cnt1[3]});
shift_cnt2 <= shift_last ? 7'd1 : (shift_cnt2 + 1);
end
assign shift_last = shift_cnt2[6];
// Data
always @(posedge clk or posedge rst)
if (rst)
shift_data <= 0;
else if (shift_ce)
shift_data <= shift_last ? word_val : { ^shift_data[34:8], shift_data[34:1] };
assign shift_ce = bit_ack & (shift_cnt1[3] | ~shift_cnt2[0]);
assign word_ack = bit_ack & shift_last;
// Bi-Phase coding
// ---------------
assign bp_in = shift_data[0];
assign bp_cycle = shift_cnt2[0];
always @(posedge clk or posedge rst)
if (rst)
bit_val <= 1'b0;
else if (bit_ack)
bit_val <= shift_cnt1[3] ? bp_in : (bit_val ^ (bp_in || bp_cycle));
endmodule
| 7.306032 |
module SpeakerControl (
input wire clk,
input wire [4:0] note,
output reg audio
);
reg [18:0] count;
reg [18:0] value;
always @(posedge clk)
if (count > 0) count = count - 1;
else begin
count <= value;
audio <= ~audio;
end
always @(posedge clk)
case (note)
// These values are wave lengths of notes with respect to time (10 nano sec)
// value = 100,000,000 / (frequency of notes / 2)
5'b00000: value = 1000; //es
5'b00001: value = 254817; //G 3
5'b00010: value = 240790; //G#3
5'b00011: value = 227273; //A 3
5'b00100: value = 214519; //A#3
5'b00101: value = 202478; //B 3
5'b00110: value = 191113; //C 4
5'b00111: value = 180388; //C#4
5'b01000: value = 170262; //D 4
5'b01001: value = 160705; //D#4
5'b01010: value = 151685; //E 4
5'b01011: value = 143172; //F 4
5'b01100: value = 135139; //F#4
5'b01101: value = 127553; //G 4
5'b01110: value = 120395; //G#4
5'b01111: value = 113636; //A 4
5'b10000: value = 107259; //A#4
5'b10001: value = 101238; //B 4
5'b10010: value = 95557; //C 5
5'b10011: value = 90194; //C#5
5'b10100: value = 85131; //D 5
5'b10101: value = 80353; //D#5
5'b10110: value = 75843; //E 5
5'b10111: value = 71587; //F 5
5'b11000: value = 67569; //F#5
5'b11001: value = 63776; //G 5
5'b11010: value = 60197; //G#5
5'b11011: value = 56818; //A 5
5'b11100: value = 53629; //A#5
5'b11101: value = 50619; //B 5
5'b11110: value = 286344; //f 3
5'b11111: value = 270278; //f#3
default: value = 191113; //C 4
endcase
endmodule
| 6.797029 |
module speaker_control (
clk, // clock from the crystal
rst, // active high reset
audio_in_left, // left channel audio data input
audio_in_right, // right channel audio data input
audio_mclk, // master clock
audio_lrck, // left-right clock, Word Select clock, or sample rate clock
audio_sck, // serial clock
audio_sdin // serial audio data input
);
// I/O declaration
input clk; // clock from the crystal
input rst; // active high reset
input [15:0] audio_in_left; // left channel audio data input
input [15:0] audio_in_right; // right channel audio data input
output audio_mclk; // master clock
output audio_lrck; // left-right clock
output audio_sck; // serial clock
output audio_sdin; // serial audio data input
reg audio_sdin;
// Declare internal signal nodes
wire [8:0] clk_cnt_next;
reg [8:0] clk_cnt;
reg [15:0] audio_left, audio_right;
// Counter for the clock divider
assign clk_cnt_next = clk_cnt + 1'b1;
always @(posedge clk or posedge rst)
if (rst == 1'b1) clk_cnt <= 9'd0;
else clk_cnt <= clk_cnt_next;
// Assign divided clock output
assign audio_mclk = clk_cnt[1];
assign audio_lrck = clk_cnt[8];
assign audio_sck = 1'b1; // use internal serial clock mode
// audio input data buffer
always @(posedge clk_cnt[8] or posedge rst)
if (rst == 1'b1) begin
audio_left <= 16'd0;
audio_right <= 16'd0;
end else begin
audio_left <= audio_in_left;
audio_right <= audio_in_right;
end
always @*
case (clk_cnt[8:4])
5'b00000: audio_sdin = audio_right[0];
5'b00001: audio_sdin = audio_left[15];
5'b00010: audio_sdin = audio_left[14];
5'b00011: audio_sdin = audio_left[13];
5'b00100: audio_sdin = audio_left[12];
5'b00101: audio_sdin = audio_left[11];
5'b00110: audio_sdin = audio_left[10];
5'b00111: audio_sdin = audio_left[9];
5'b01000: audio_sdin = audio_left[8];
5'b01001: audio_sdin = audio_left[7];
5'b01010: audio_sdin = audio_left[6];
5'b01011: audio_sdin = audio_left[5];
5'b01100: audio_sdin = audio_left[4];
5'b01101: audio_sdin = audio_left[3];
5'b01110: audio_sdin = audio_left[2];
5'b01111: audio_sdin = audio_left[1];
5'b10000: audio_sdin = audio_left[0];
5'b10001: audio_sdin = audio_right[15];
5'b10010: audio_sdin = audio_right[14];
5'b10011: audio_sdin = audio_right[13];
5'b10100: audio_sdin = audio_right[12];
5'b10101: audio_sdin = audio_right[11];
5'b10110: audio_sdin = audio_right[10];
5'b10111: audio_sdin = audio_right[9];
5'b11000: audio_sdin = audio_right[8];
5'b11001: audio_sdin = audio_right[7];
5'b11010: audio_sdin = audio_right[6];
5'b11011: audio_sdin = audio_right[5];
5'b11100: audio_sdin = audio_right[4];
5'b11101: audio_sdin = audio_right[3];
5'b11110: audio_sdin = audio_right[2];
5'b11111: audio_sdin = audio_right[1];
default: audio_sdin = 1'b0;
endcase
endmodule
| 6.944398 |
module foo (
a,
b,
x
);
input a, b;
output x;
specify
if (a) (a *> x) = 10;
if (!a) (a *> x) = 21;
(b *> x) = 12;
endspecify
assign x = a ^ b;
endmodule
| 6.935051 |
module foo #(.p1(10), .p2(21)) (a,b,x,y);
input a,b;
output x,y;
specify
if (a) (a *> x) = p1;
if (!a) (a *> x) = p2;
(b *> x) = 12;
(a, b *> y) = 17;
endspecify
assign {x,y} = a + b;
endmodule
| 6.690934 |
module specdrum (
input wire clk,
input wire rst_n,
input wire [7:0] a,
input wire iorq_n,
input wire wr_n,
input wire [7:0] d,
output reg [7:0] specdrum_out
);
initial specdrum_out = 8'h00;
always @(posedge clk) begin
if (rst_n == 1'b0) specdrum_out <= 8'h00;
else if (iorq_n == 1'b0 && a == 8'hDF && wr_n == 1'b0) specdrum_out <= d;
end
endmodule
| 7.215447 |
module special (
a,
b,
special,
specialsign,
zero,
aisnan,
bisnan,
infinity,
invalid,
specialcase,
specialsigncase
);
// external signals
input [`WIDTH-1:0] a, b; // floating-point inputs
output [`WIDTH-2:0] special; // special case output, exp + sig
output specialsign; // the special-case sign
input zero; // is there a zero?
input aisnan; // NaN detected in A
input bisnan; // NaN detected in B
input infinity; // infinity detected
output invalid; // invalid operation
output specialcase; // this is a special case
output specialsigncase; // Use the special sign
// internal signals
wire infandzero; // infinity and zero detected
wire [`WIDTH-2:0] highernan; // holds inputed NaN, the higher if two are input,
// and dont care if neither a nor b are NaNs
wire aishighernan; // a is the higher NaN
assign infandzero = (infinity & zero);
//#######SPECIAL ASSIGNMENT######
// #######return higher NaN##########
// Use this block if you want to return the higher of two NaNs
assign aishighernan = (aisnan & ((a[`WSIG-1:0] >= b[`WSIG-1:0]) | ~bisnan));
assign highernan[`WIDTH-2:0] = aishighernan ? a[`WIDTH-2:0] : b[`WIDTH-2:0];
assign special[`WIDTH-2:0] = (aisnan | bisnan) ? (highernan[`WIDTH-2:0]) :
(zero ?
(infinity ? (`CONSTNAN) : (`CONSTZERO)) : (`CONSTINFINITY));
// #######return first NaN##########
// Use this block to return the first NaN encountered
// assign special = aisnan ? (a[`WIDTH-2:0]) :
// (bisnan ? (b[`WIDTH-2:0]) :
// (zero ?
// (infinity ? (`CONSTNAN) : (`CONSTZERO)) : (`CONSTINFINITY)));
//######END SPECIAL ASSIGNMENT#######
assign specialcase = zero | aisnan | bisnan | infinity;
assign invalid = infandzero; //*** need to include something about signaling NaNs here
// dont need to check if b is NaN, if it defaults to that point, and b isnt NAN
// then it wont be used anyway
assign specialsign = infandzero ? (1'b1) : (aishighernan ? a[`WIDTH-1] : b[`WIDTH-1]);
assign specialsigncase = infandzero | aisnan | bisnan;
endmodule
| 8.673693 |
module SpecialAdd (
input [31:0] cin_Special,
input [31:0] zin_Special,
input reset,
input clock,
output reg idle_Special = 1'b0,
output reg [7:0] difference_Special,
output reg [35:0] cout_Special,
output reg [35:0] zout_Special,
output reg [31:0] sout_Special
);
wire z_sign;
wire [7:0] z_exponent;
wire [26:0] z_mantissa;
wire c_sign;
wire [7:0] c_exponent;
wire [26:0] c_mantissa;
assign c_sign = cin_Special[31];
assign c_exponent = {cin_Special[30:23] - 127};
assign c_mantissa = {cin_Special[22:0], 3'd0};
assign z_sign = {zin_Special[31]};
assign z_exponent = {zin_Special[30:23] - 127};
assign z_mantissa = {zin_Special[22:0], 3'd0};
parameter no_idle = 1'b0, put_idle = 1'b1;
always @(posedge clock) begin
if (reset == 1'b1) begin
idle_Special <= 1'b0;
end else begin
if ($signed(z_exponent) > $signed(c_exponent)) begin
difference_Special <= z_exponent - c_exponent;
end else if ($signed(z_exponent) <= $signed(c_exponent)) begin
difference_Special <= c_exponent - z_exponent;
end
// Most of the special cases will never occur except the case where one input is zero.
// The HCORDIC module will not receive NaN and inf at input stage.
//if c is NaN or z is NaN return NaN
if ((c_exponent == 128 && c_mantissa != 0) || (z_exponent == 128 && z_mantissa != 0)) begin
sout_Special[31] <= 1;
sout_Special[30:23] <= 255;
sout_Special[22] <= 1;
sout_Special[21:0] <= 0;
zout_Special <= zin_Special;
cout_Special <= cin_Special;
idle_Special <= put_idle;
//if c is inf return inf
end else if (c_exponent == 128) begin
sout_Special[31] <= c_sign;
sout_Special[30:23] <= 255;
sout_Special[22:0] <= 0;
zout_Special <= zin_Special;
cout_Special <= cin_Special;
idle_Special <= put_idle;
//if z is inf return inf
end else if (z_exponent == 128) begin
sout_Special[31] <= z_sign;
sout_Special[30:23] <= 255;
sout_Special[22:0] <= 0;
zout_Special <= zin_Special;
cout_Special <= cin_Special;
idle_Special <= put_idle;
//if c is zero return z
end else if ((($signed(
c_exponent
) == -127) && (c_mantissa == 0)) && (($signed(
z_exponent
) == -127) && (z_mantissa == 0))) begin
sout_Special[31] <= c_sign & z_sign;
sout_Special[30:23] <= z_exponent[7:0] + 127;
sout_Special[22:0] <= z_mantissa[26:3];
zout_Special <= zin_Special;
cout_Special <= cin_Special;
idle_Special <= put_idle;
//if c is zero return z
end else if (($signed(c_exponent) == -127) && (c_mantissa == 0)) begin
sout_Special[31] <= z_sign;
sout_Special[30:23] <= z_exponent[7:0] + 127;
sout_Special[22:0] <= z_mantissa[26:3];
zout_Special <= zin_Special;
cout_Special <= cin_Special;
idle_Special <= put_idle;
//if z is zero return c
end else if (($signed(z_exponent) == -127) && (z_mantissa == 0)) begin
sout_Special[31] <= c_sign;
sout_Special[30:23] <= c_exponent[7:0] + 127;
sout_Special[22:0] <= c_mantissa[26:3];
zout_Special <= zin_Special;
cout_Special <= cin_Special;
idle_Special <= put_idle;
end else begin
sout_Special <= 0;
//Denormalised Number
if ($signed(c_exponent) == -127) begin
cout_Special[34:27] <= -126;
cout_Special[35] <= c_sign;
cout_Special[26:0] <= c_mantissa;
end else begin
cout_Special[34:27] <= c_exponent + 127;
cout_Special[35] <= c_sign;
cout_Special[26] <= 1;
cout_Special[25:0] <= c_mantissa[25:0];
idle_Special <= no_idle;
end
//Denormalised Number
if ($signed(z_exponent) == -127) begin
zout_Special[35] <= z_sign;
zout_Special[34:27] <= -126;
zout_Special[26:0] <= z_mantissa;
end else begin
zout_Special[35] <= z_sign;
zout_Special[34:27] <= z_exponent + 127;
zout_Special[25:0] <= z_mantissa[25:0];
zout_Special[26] <= 1;
idle_Special <= no_idle;
end
end
end
end
endmodule
| 7.497565 |
module SpecialCasesHandler (
isInputStable,
isFloat,
sign,
exponent,
mantissa,
out,
isInputNormalized
);
parameter SIZE = 8'd64, EXPONENT_SIZE = 4'd11, MANTISSA_SIZE = 6'd52;
input isFloat, isInputStable;
input sign;
input [EXPONENT_SIZE - 1:0] exponent;
input [MANTISSA_SIZE - 1:0] mantissa;
output [SIZE -1:0] out;
reg [SIZE -1:0] out;
output isInputNormalized;
reg isInputNormalized;
always @(*) begin
if (isInputStable) begin
isInputNormalized = 0;
if (isFloat) begin
// if a is NaN or negative return NaN
if (sign == 1 || (exponent[7:0] == 255 && mantissa[22:0] != 0)) begin
out[31] = sign;
out[30:23] = 255;
out[22] = 1;
out[21:0] = 0;
// state = put_z;
end // if a is inf return inf
else if (exponent[7:0] == 255) begin
out[31] = sign;
out[30:23] = 255;
out[22:0] = 0;
// state = put_z;
// if a is zero return zero
end else if ((exponent[7:0] == 0) && (mantissa[22:0] == 0)) begin
out[31] = sign;
out[30:23] = 0;
out[22:0] = 0;
// state = put_z;
end else begin
// Denormalised Number
if (exponent[7:0] < 255) begin
isInputNormalized = 1;
out = {sign, exponent, mantissa};
end else begin
isInputNormalized = 0;
out[31] = sign;
out[30:23] = 255;
out[22] = 1;
out[21:0] = 0;
end
end
end else begin
// if a is NaN or negative return NaN
if (sign == 1 || (exponent[10:0] == 2047 && mantissa[51:0] != 0)) begin
out[63] = sign;
out[62:52] = 2047;
out[51] = 1;
out[50:0] = 0;
// state = put_z;
end // if a is inf return inf
else if (exponent[10:0] == 2047) begin
out[63] = sign;
out[62:52] = 2047;
out[51:0] = 0;
// state = put_z;
// if a is zero return zero
end else if ((($signed(exponent[10:0]) == 0) && (mantissa[51:0] == 0))) begin
out[63] = sign;
out[62:52] = 0;
out[51:0] = 0;
// state = put_z;
end else begin
// Denormalised Number
if (exponent < 2047) begin
isInputNormalized = 1;
out = {sign, exponent, mantissa};
end else begin
isInputNormalized = 0;
out[63] = sign;
out[62:52] = 2047;
out[51] = 1;
out[50:0] = 0;
end
end
end
end else begin
isInputNormalized = 0;
out = 0;
end
end
endmodule
| 7.431494 |
module specialJudge (
input [30:0] a,
input [30:0] b,
input [30:0] in,
output [30:0] out,
output err_INF
);
reg err;
reg [30:0] tmp;
initial begin
err = 1'b0;
end
always @* begin
tmp = in;
if (a == 31'b1111111_10000000_00000000_00000000 || b == 31'b1111111_10000000_00000000_00000000)
tmp = 31'b1111111_10000000_00000000_00000000;
if (a == 31'b0000000_00000000_00000000_00000000 || b == 31'b0000000_00000000_00000000_00000000)
tmp = 31'b0000000_00000000_00000000_00000000;
if (a == 31'b0000000_00000000_00000000_00000000 && b == 31'b1111111_10000000_00000000_00000000)
tmp = 31'b1111111_11111111_11111111_11111111;
if (a == 31'b1111111_10000000_00000000_00000000 && b == 31'b0000000_00000000_00000000_00000000)
tmp = 31'b1111111_11111111_11111111_11111111;
if (a == 31'b1111111_11111111_11111111_11111111 || b == 31'b1111111_11111111_11111111_11111111)
tmp = 31'b1111111_11111111_11111111_11111111;
if (tmp == 31'b1111111_11111111_11111111_11111111) err = 1'b1;
else err = 1'b0;
end
assign out = tmp;
assign err_INF = err;
endmodule
| 6.800833 |
module specialkeys (
clk,
cpu_ce,
reset_n,
key_blksbr,
key_osd,
osd_command,
o_disable_rom,
o_blksbr_reset,
o_osd
);
input clk;
input cpu_ce;
input reset_n;
input key_blksbr;
input key_osd;
input [7:0] osd_command; // {F11,F12,HOLD}
output reg o_disable_rom;
output o_blksbr_reset;
output reg o_osd;
// BLK+SBR
reg rst0toggle = 0;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
o_disable_rom <= 0;
rst0toggle <= 0;
end else begin
if (key_blksbr) begin
o_disable_rom <= 1;
rst0toggle <= 1;
end else rst0toggle <= 0;
end
end
oneshot blksbr (
clk,
cpu_ce,
rst0toggle,
o_blksbr_reset
);
// ScrollLock
reg key_osd_x = 0;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
o_osd <= 0;
key_osd_x <= 0;
end else begin
key_osd_x <= key_osd;
if (key_osd & ~key_osd_x) o_osd <= ~o_osd;
end
end
endmodule
| 7.416959 |
module emulates the special operation performing part of the processor
* When it receives the en signal, it saves the PC and starts doing special ops
* (eg convolution). After it is done, it restores the PC to its value before
* special ops began
*
* Top module has to have a mux to decide when to select out_pc as the pc while
*
* NOTE: THIS MODULE IS TO BE USED ONLY IF RUNNING SPECIAL OPERATIONS ARE BEING
* PERFORMED ON THE PROCESSOR ITSELF
*/
module SpecialPcUnit #(parameter ADDRESS_BITS = 20,
DATA_WIDTH = 32)(
input wire clk, // clock
input wire rst, // reset
input wire en, // start special module
input wire [ADDRESS_BITS-1:0] curr_pc, // current pc
output wire done, // special computation done
output reg [ADDRESS_BITS-1:0] out_pc // pc for current instruction of special operation
);
// number of special instructions to run
localparam IDLE = 0;
localparam RUNNING = 1;
localparam LOG2_NUM_SPECIAL_INST = 2;
localparam NUM_SPECIAL_INST = 2**LOG2_NUM_SPECIAL_INST;
// the special instructions to run when en is asserted
reg [ADDRESS_BITS-1:0] special_instr_pcs[0:NUM_SPECIAL_INST-1];
reg [LOG2_NUM_SPECIAL_INST:0] instr_idx; // keep bitwidth one more than LOG2_NUM_SPECIAL_INST else it will overflow to zero
// value of pc to restore after done
reg [ADDRESS_BITS-1:0] saved_pc;
// current state of special ops pc unit
reg state;
// fill dummy values for debug
initial
begin
special_instr_pcs[0] <= 20'hB;
special_instr_pcs[1] <= 20'hE;
special_instr_pcs[2] <= 20'hE;
special_instr_pcs[3] <= 20'hF;
end
assign done = (state==RUNNING) && (instr_idx==NUM_SPECIAL_INST);
always @(posedge clk)
begin
if (rst)
begin
state <= IDLE;
instr_idx <= 0;
out_pc <= 0;
end
else
begin
case (state)
IDLE:
begin
if (en == 1'b1)
begin
saved_pc <= curr_pc + 4; // save pc of next instruction
state <= RUNNING;
end
else
begin
instr_idx <= 0;
state <= IDLE;
end
end
RUNNING:
begin
if (instr_idx < NUM_SPECIAL_INST) // continue running special ops
begin
out_pc = special_instr_pcs[instr_idx];
instr_idx <= instr_idx + 1;
end
else // done with special ops
begin
state <= IDLE;
instr_idx <= 0;
out_pc <= saved_pc; // restore pc
end
end
endcase
end
end
endmodule
| 7.334367 |
module special_register_file (
// Reset and clock
input rst_n,
input clk,
// Register read/write signals
input [ 3:0] reg_select,
input read_enable,
output [31:0] read_value,
input write_enable,
input [31:0] write_value,
// Increment the instruction count register
input inc_icount,
// Save or restore state due to an exception
input save_state,
input restore_state,
output [7:0] interrupt_mask,
input [3:0] exception_status,
input [7:0] interrupt_status,
output interrupts_enabled,
output kernel_mode,
output [19:0] user_base,
output [19:0] protection_table
);
// Get the register name definitions
`include "wramp.vh"
reg [31:0] register[0:15];
assign read_value = read_enable ? register[reg_select] : 32'hzzzzzzzz;
// Output misc signals
assign interrupt_mask = register[ICTRL_REGNO][11:4];
assign interrupts_enabled = register[ICTRL_REGNO][1];
assign kernel_mode = register[ICTRL_REGNO][3];
assign user_base = register[USERBASE_REGNO][19:0];
assign protection_table = register[WPTABLE_REGNO][19:0];
//not all special registers are defined, but they all need to exist
always @(posedge clk) begin
if (!rst_n) begin
register[0] = 32'hXXXXXXXX;
register[1] = 32'hXXXXXXXX;
register[2] = 32'hXXXXXXXX;
register[3] = 32'hXXXXXXXX;
register[ICTRL_REGNO] = 32'h00000008; // Kernel mode, no interrupts
register[ISTAT_REGNO] = 32'b0;
register[ICOUNT_REGNO] = 32'b0;
register[CCOUNT_REGNO] = 32'b0;
register[IVEC_REGNO] = 32'b0;
register[IAR_REGNO] = 32'b0;
register[ESP_REGNO] = 32'b0; //was supposed to be an exception stack pointer
//was never implimented/not needed (exc can use normal stack)
register[ERS_REGNO] = 32'b0;
register[WPTABLE_REGNO] = 32'b0;
register[USERBASE_REGNO] = 32'b0;
register[14] = 32'hXXXXXXXX;
register[15] = 32'hXXXXXXXX;
end
// Enable writing to registers
if (write_enable) begin
if (reg_select != ISTAT_REGNO) begin
register[reg_select] = write_value;
end
end
// Increment the cycle count register
register[CCOUNT_REGNO] = register[CCOUNT_REGNO] + 1;
// Increment the instruction count register
if (inc_icount) begin
register[ICOUNT_REGNO] = register[ICOUNT_REGNO] + 1;
end
// If we are taking an exception
if (save_state) begin
// Capture the cause of the exception
// A comment was left in the original VHDL source about fixing this
// to support software exceptions. Pretty sure they're supported.
register[ISTAT_REGNO] = {
16'h0000, exception_status, (interrupt_status & interrupt_mask), 4'b0000
};
// Maintain the kernel/user mode and interrupt enable bits
// Set kernel mode and disable interrupts for exception handler
register[ICTRL_REGNO] = {
register[ICTRL_REGNO][31:4], 1'b1, register[ICTRL_REGNO][3], 1'b0, register[ICTRL_REGNO][1]
};
end
// If we are returning from an exception
if (restore_state) begin
// Maintain the kernel/user mode and interrupt enable bits
register[ICTRL_REGNO] = {
register[ICTRL_REGNO][31:4], {2{register[ICTRL_REGNO][2]}}, {2{register[ICTRL_REGNO][0]}}
};
end
end
endmodule
| 7.832977 |
module mydff (
output reg q,
input d,
input c
);
always @(posedge c) q <= d;
specify
(posedge c => (q +: d)) = (3, 2);
endspecify
endmodule
| 6.92993 |
module dff_rtl (
q,
d,
cp,
cdn
);
output q;
input d;
input cp;
input cdn;
reg qi;
always @(posedge cp or negedge cdn) begin
if (~cdn) qi <= 1'b0;
else qi <= d;
end
buf (q, qi);
specify
specparam tpd_cp_q_lh = 6;
specparam tpd_cp_q_hl = 7;
specparam tpd_cdn_q_lh = 0;
specparam tpd_cdn_q_hl = 3;
if (cdn) (posedge cp => (q +: d)) = (tpd_cp_q_lh, tpd_cp_q_hl);
(negedge cdn => (q +: 1'b0)) = (tpd_cdn_q_lh, tpd_cdn_q_hl);
endspecify
endmodule
| 7.027196 |
module dff (
clk,
d,
q
);
input d, clk;
output q;
reg q_out;
wire q;
specify
specparam tR_clk_q = 100, tF_clk_q = 150;
(clk, d => q) = (tR_clk_q, tF_clk_q);
endspecify
always @(posedge clk) q_out <= d;
buf u_buf (q, q_out);
endmodule
| 6.824043 |
module Spectolizer #(
////////////////////////////////////////////////////
// Parameters
parameter bw_fftp = 11,
parameter bw_dpram = 12,
parameter bw_fftdata = 16,
parameter bw_data = 16
) (
////////////////////////////////////////////////////
// Ports
input Clock,
Reset,
//For Cacher
input [ bw_data-1:0] RAM_Q,
output [bw_dpram-1:0] DPRAMAddr,
//For VRAMControl
input SWClockEn,
input StartLoader,
output [14:0] Color,
output Screen,
output [8:0] X,
output [6:0] Y
);
////////////////////////////////////////////////////
// Instantiations
//波形読み込み
FFTSeq_Loader #(
.bw_dpram(bw_dpram),
.bw_data (bw_data)
) loader (
.Clock(Clock),
.Reset(Reset),
.Start(StartLoader),
.DPRAMAddr(DPRAMAddr),
.ibstart(ibstart),
.ibend(ibend),
.rfib(rfib)
);
//シーケンサ
FFTSequenser #(
.bw_fftp(bw_fftp)
) seq (
.Clock(Clock),
.Reset(Reset),
.obstart(obstart),
.outvalid(outvalid),
.Busy_SW(Busy_SW),
.Busy_SL(Busy_SL),
.CGate(Gate),
.Start_SL(Start_SL),
.Start_SW(Start_SW)
);
//Clock Gate
ClockGate cgate (
.InClock(Clock),
.Gate(Gate),
.OutClock(GatedClock)
);
wire [bw_data-1:0] dire = RAM_Q;
//FFTComiler
`ifdef N64
FFTC64 fftc (
.clk(GatedClock), // system clock
.rstn(~Reset), // system reset
.ibstart(ibstart), // input block start indicator
.dire(dire), // real part of input data
.diim(0), // imaginary part of input data
.except(except), // exception signal
.rfib(rfib), // ready for input block
.ibend(ibend), // input block end
.obstart(obstart), // output block start
.outvalid(outvalid), // output outvalid
.dore(dore), // real part of output data
.doim(doim) // imaginary part of output data
);
`else
FFTC2048_16 fftc (
.clk(GatedClock), // system clock
.rstn(~Reset), // system reset
.ibstart(ibstart), // input block start indicator
.dire(dire), // real part of input data
.diim(0), // imaginary part of input data
.except(except), // exception signal
.rfib(rfib), // ready for input block
.ibend(ibend), // input block end
.obstart(obstart), // output block start
.outvalid(outvalid), // output outvalid
.dore(dore), // real part of output data
.doim(doim) // imaginary part of output data
);
`endif
wire [bw_fftdata-1:0] dore, doim;
//スペクトル化
FFTSpectolizer #(
.bw_data(bw_fftdata)
) fft_spec (
.Clock(Clock),
.Reset(Reset),
.Start(Start_SL),
.Re(dore),
.Im(doim),
.Spectol(Spectol),
.Busy(Busy_SL)
);
wire [6:0] Spectol;
//スペクトル描画
wire LRChange = obstart;
FFT_SpectolWriter sw (
.Clock(Clock),
.ClockEn(SWClockEn),
.Reset(Reset),
.End(End_SW),
.Busy(Busy_SW),
.Start(Start_SW),
.LRChange(LRChange), //LRChange = obstart
.Bar(Spectol),
.Screen(Screen),
.X(X),
.Y(Y),
.Color(Color)
);
endmodule
| 6.518935 |
module StreamBuffer (
input clock,
input reset,
input auto_out_out_ready,
output auto_out_out_valid,
output [7:0] auto_out_out_bits_data,
output auto_out_out_bits_last,
output auto_in_in_ready,
input auto_in_in_valid,
input [7:0] auto_in_in_bits_data,
input auto_in_in_bits_last
);
wire Queue_clock; // @[Decoupled.scala 296:21]
wire Queue_reset; // @[Decoupled.scala 296:21]
wire Queue_io_enq_ready; // @[Decoupled.scala 296:21]
wire Queue_io_enq_valid; // @[Decoupled.scala 296:21]
wire [7:0] Queue_io_enq_bits_data; // @[Decoupled.scala 296:21]
wire Queue_io_enq_bits_last; // @[Decoupled.scala 296:21]
wire Queue_io_deq_ready; // @[Decoupled.scala 296:21]
wire Queue_io_deq_valid; // @[Decoupled.scala 296:21]
wire [7:0] Queue_io_deq_bits_data; // @[Decoupled.scala 296:21]
wire Queue_io_deq_bits_last; // @[Decoupled.scala 296:21]
Queue_1 Queue ( // @[Decoupled.scala 296:21]
.clock(Queue_clock),
.reset(Queue_reset),
.io_enq_ready(Queue_io_enq_ready),
.io_enq_valid(Queue_io_enq_valid),
.io_enq_bits_data(Queue_io_enq_bits_data),
.io_enq_bits_last(Queue_io_enq_bits_last),
.io_deq_ready(Queue_io_deq_ready),
.io_deq_valid(Queue_io_deq_valid),
.io_deq_bits_data(Queue_io_deq_bits_data),
.io_deq_bits_last(Queue_io_deq_bits_last)
);
assign auto_out_out_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:49]
assign auto_out_out_bits_data = Queue_io_deq_bits_data; // @[LazyModule.scala 173:49]
assign auto_out_out_bits_last = Queue_io_deq_bits_last; // @[LazyModule.scala 173:49]
assign auto_in_in_ready = Queue_io_enq_ready; // @[LazyModule.scala 173:31]
assign Queue_clock = clock;
assign Queue_reset = reset;
assign Queue_io_enq_valid = auto_in_in_valid; // @[Decoupled.scala 297:22]
assign Queue_io_enq_bits_data = auto_in_in_bits_data; // @[Decoupled.scala 298:21]
assign Queue_io_enq_bits_last = auto_in_in_bits_last; // @[Decoupled.scala 298:21]
assign Queue_io_deq_ready = auto_out_out_ready; // @[Decoupled.scala 320:15]
endmodule
| 6.986803 |
module NCOTable (
input [ 8:0] io_phase,
output [15:0] io_sinOut,
output [15:0] io_cosOut
);
wire [ 8:0] tableNCO_io_phase; // @[NCOTable.scala 475:13]
wire [15:0] tableNCO_io_sinOut; // @[NCOTable.scala 475:13]
wire [15:0] tableNCO_io_cosOut; // @[NCOTable.scala 475:13]
NCOTableStandardMode tableNCO ( // @[NCOTable.scala 475:13]
.io_phase (tableNCO_io_phase),
.io_sinOut(tableNCO_io_sinOut),
.io_cosOut(tableNCO_io_cosOut)
);
assign io_sinOut = tableNCO_io_sinOut; // @[NCOTable.scala 480:13]
assign io_cosOut = tableNCO_io_cosOut; // @[NCOTable.scala 481:13]
assign tableNCO_io_phase = io_phase; // @[NCOTable.scala 479:21]
endmodule
| 6.814188 |
module StreamBuffer_1 (
input clock,
input reset,
input auto_out_out_ready,
output auto_out_out_valid,
output [31:0] auto_out_out_bits_data,
output auto_out_out_bits_last,
output auto_in_in_ready,
input auto_in_in_valid,
input [31:0] auto_in_in_bits_data,
input auto_in_in_bits_last
);
wire Queue_clock; // @[Decoupled.scala 296:21]
wire Queue_reset; // @[Decoupled.scala 296:21]
wire Queue_io_enq_ready; // @[Decoupled.scala 296:21]
wire Queue_io_enq_valid; // @[Decoupled.scala 296:21]
wire [31:0] Queue_io_enq_bits_data; // @[Decoupled.scala 296:21]
wire Queue_io_enq_bits_last; // @[Decoupled.scala 296:21]
wire Queue_io_deq_ready; // @[Decoupled.scala 296:21]
wire Queue_io_deq_valid; // @[Decoupled.scala 296:21]
wire [31:0] Queue_io_deq_bits_data; // @[Decoupled.scala 296:21]
wire Queue_io_deq_bits_last; // @[Decoupled.scala 296:21]
Queue_37 Queue ( // @[Decoupled.scala 296:21]
.clock(Queue_clock),
.reset(Queue_reset),
.io_enq_ready(Queue_io_enq_ready),
.io_enq_valid(Queue_io_enq_valid),
.io_enq_bits_data(Queue_io_enq_bits_data),
.io_enq_bits_last(Queue_io_enq_bits_last),
.io_deq_ready(Queue_io_deq_ready),
.io_deq_valid(Queue_io_deq_valid),
.io_deq_bits_data(Queue_io_deq_bits_data),
.io_deq_bits_last(Queue_io_deq_bits_last)
);
assign auto_out_out_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:49]
assign auto_out_out_bits_data = Queue_io_deq_bits_data; // @[LazyModule.scala 173:49]
assign auto_out_out_bits_last = Queue_io_deq_bits_last; // @[LazyModule.scala 173:49]
assign auto_in_in_ready = Queue_io_enq_ready; // @[LazyModule.scala 173:31]
assign Queue_clock = clock;
assign Queue_reset = reset;
assign Queue_io_enq_valid = auto_in_in_valid; // @[Decoupled.scala 297:22]
assign Queue_io_enq_bits_data = auto_in_in_bits_data; // @[Decoupled.scala 298:21]
assign Queue_io_enq_bits_last = auto_in_in_bits_last; // @[Decoupled.scala 298:21]
assign Queue_io_deq_ready = auto_out_out_ready; // @[Decoupled.scala 320:15]
endmodule
| 6.662474 |
module StreamBuffer_2 (
input clock,
input reset,
input auto_out_out_ready,
output auto_out_out_valid,
output [31:0] auto_out_out_bits_data,
output auto_out_out_bits_last,
output auto_in_in_ready,
input auto_in_in_valid,
input [31:0] auto_in_in_bits_data,
input auto_in_in_bits_last
);
wire Queue_clock; // @[Decoupled.scala 296:21]
wire Queue_reset; // @[Decoupled.scala 296:21]
wire Queue_io_enq_ready; // @[Decoupled.scala 296:21]
wire Queue_io_enq_valid; // @[Decoupled.scala 296:21]
wire [31:0] Queue_io_enq_bits_data; // @[Decoupled.scala 296:21]
wire Queue_io_enq_bits_last; // @[Decoupled.scala 296:21]
wire Queue_io_deq_ready; // @[Decoupled.scala 296:21]
wire Queue_io_deq_valid; // @[Decoupled.scala 296:21]
wire [31:0] Queue_io_deq_bits_data; // @[Decoupled.scala 296:21]
wire Queue_io_deq_bits_last; // @[Decoupled.scala 296:21]
Queue_39 Queue ( // @[Decoupled.scala 296:21]
.clock(Queue_clock),
.reset(Queue_reset),
.io_enq_ready(Queue_io_enq_ready),
.io_enq_valid(Queue_io_enq_valid),
.io_enq_bits_data(Queue_io_enq_bits_data),
.io_enq_bits_last(Queue_io_enq_bits_last),
.io_deq_ready(Queue_io_deq_ready),
.io_deq_valid(Queue_io_deq_valid),
.io_deq_bits_data(Queue_io_deq_bits_data),
.io_deq_bits_last(Queue_io_deq_bits_last)
);
assign auto_out_out_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:49]
assign auto_out_out_bits_data = Queue_io_deq_bits_data; // @[LazyModule.scala 173:49]
assign auto_out_out_bits_last = Queue_io_deq_bits_last; // @[LazyModule.scala 173:49]
assign auto_in_in_ready = Queue_io_enq_ready; // @[LazyModule.scala 173:31]
assign Queue_clock = clock;
assign Queue_reset = reset;
assign Queue_io_enq_valid = auto_in_in_valid; // @[Decoupled.scala 297:22]
assign Queue_io_enq_bits_data = auto_in_in_bits_data; // @[Decoupled.scala 298:21]
assign Queue_io_enq_bits_last = auto_in_in_bits_last; // @[Decoupled.scala 298:21]
assign Queue_io_deq_ready = auto_out_out_ready; // @[Decoupled.scala 320:15]
endmodule
| 6.662474 |
module StreamBuffer_3 (
input clock,
input reset,
input auto_out_out_ready,
output auto_out_out_valid,
output [31:0] auto_out_out_bits_data,
output auto_out_out_bits_last,
output auto_in_in_ready,
input auto_in_in_valid,
input [31:0] auto_in_in_bits_data,
input auto_in_in_bits_last
);
wire Queue_clock; // @[Decoupled.scala 296:21]
wire Queue_reset; // @[Decoupled.scala 296:21]
wire Queue_io_enq_ready; // @[Decoupled.scala 296:21]
wire Queue_io_enq_valid; // @[Decoupled.scala 296:21]
wire [31:0] Queue_io_enq_bits_data; // @[Decoupled.scala 296:21]
wire Queue_io_enq_bits_last; // @[Decoupled.scala 296:21]
wire Queue_io_deq_ready; // @[Decoupled.scala 296:21]
wire Queue_io_deq_valid; // @[Decoupled.scala 296:21]
wire [31:0] Queue_io_deq_bits_data; // @[Decoupled.scala 296:21]
wire Queue_io_deq_bits_last; // @[Decoupled.scala 296:21]
Queue_40 Queue ( // @[Decoupled.scala 296:21]
.clock(Queue_clock),
.reset(Queue_reset),
.io_enq_ready(Queue_io_enq_ready),
.io_enq_valid(Queue_io_enq_valid),
.io_enq_bits_data(Queue_io_enq_bits_data),
.io_enq_bits_last(Queue_io_enq_bits_last),
.io_deq_ready(Queue_io_deq_ready),
.io_deq_valid(Queue_io_deq_valid),
.io_deq_bits_data(Queue_io_deq_bits_data),
.io_deq_bits_last(Queue_io_deq_bits_last)
);
assign auto_out_out_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:49]
assign auto_out_out_bits_data = Queue_io_deq_bits_data; // @[LazyModule.scala 173:49]
assign auto_out_out_bits_last = Queue_io_deq_bits_last; // @[LazyModule.scala 173:49]
assign auto_in_in_ready = Queue_io_enq_ready; // @[LazyModule.scala 173:31]
assign Queue_clock = clock;
assign Queue_reset = reset;
assign Queue_io_enq_valid = auto_in_in_valid; // @[Decoupled.scala 297:22]
assign Queue_io_enq_bits_data = auto_in_in_bits_data; // @[Decoupled.scala 298:21]
assign Queue_io_enq_bits_last = auto_in_in_bits_last; // @[Decoupled.scala 298:21]
assign Queue_io_deq_ready = auto_out_out_ready; // @[Decoupled.scala 320:15]
endmodule
| 6.662474 |
module IntToBundleBridge (
input auto_in_0,
output auto_out_0
);
assign auto_out_0 = auto_in_0; // @[LazyModule.scala 173:49]
endmodule
| 6.772464 |
module BundleBridgeToAXI4 (
output auto_in_aw_ready,
input auto_in_aw_valid,
input auto_in_aw_bits_id,
input [31:0] auto_in_aw_bits_addr,
input [ 2:0] auto_in_aw_bits_size,
output auto_in_w_ready,
input auto_in_w_valid,
input [31:0] auto_in_w_bits_data,
input [ 3:0] auto_in_w_bits_strb,
input auto_in_w_bits_last,
input auto_in_b_ready,
output auto_in_b_valid,
output [ 1:0] auto_in_b_bits_resp,
output auto_in_ar_ready,
input auto_in_ar_valid,
input auto_in_ar_bits_id,
input [31:0] auto_in_ar_bits_addr,
input [ 2:0] auto_in_ar_bits_size,
input auto_in_r_ready,
output auto_in_r_valid,
output [31:0] auto_in_r_bits_data,
output [ 1:0] auto_in_r_bits_resp,
output auto_in_r_bits_last,
input auto_out_aw_ready,
output auto_out_aw_valid,
output auto_out_aw_bits_id,
output [29:0] auto_out_aw_bits_addr,
output [ 2:0] auto_out_aw_bits_size,
input auto_out_w_ready,
output auto_out_w_valid,
output [31:0] auto_out_w_bits_data,
output [ 3:0] auto_out_w_bits_strb,
output auto_out_w_bits_last,
output auto_out_b_ready,
input auto_out_b_valid,
input [ 1:0] auto_out_b_bits_resp,
input auto_out_ar_ready,
output auto_out_ar_valid,
output auto_out_ar_bits_id,
output [29:0] auto_out_ar_bits_addr,
output [ 2:0] auto_out_ar_bits_size,
output auto_out_r_ready,
input auto_out_r_valid,
input [31:0] auto_out_r_bits_data,
input [ 1:0] auto_out_r_bits_resp,
input auto_out_r_bits_last
);
assign auto_in_aw_ready = auto_out_aw_ready; // @[LazyModule.scala 173:31]
assign auto_in_w_ready = auto_out_w_ready; // @[LazyModule.scala 173:31]
assign auto_in_b_valid = auto_out_b_valid; // @[LazyModule.scala 173:31]
assign auto_in_b_bits_resp = auto_out_b_bits_resp; // @[LazyModule.scala 173:31]
assign auto_in_ar_ready = auto_out_ar_ready; // @[LazyModule.scala 173:31]
assign auto_in_r_valid = auto_out_r_valid; // @[LazyModule.scala 173:31]
assign auto_in_r_bits_data = auto_out_r_bits_data; // @[LazyModule.scala 173:31]
assign auto_in_r_bits_resp = auto_out_r_bits_resp; // @[LazyModule.scala 173:31]
assign auto_in_r_bits_last = auto_out_r_bits_last; // @[LazyModule.scala 173:31]
assign auto_out_aw_valid = auto_in_aw_valid; // @[LazyModule.scala 173:49]
assign auto_out_aw_bits_id = auto_in_aw_bits_id; // @[LazyModule.scala 173:49]
assign auto_out_aw_bits_addr = auto_in_aw_bits_addr[29:0]; // @[LazyModule.scala 173:49]
assign auto_out_aw_bits_size = auto_in_aw_bits_size; // @[LazyModule.scala 173:49]
assign auto_out_w_valid = auto_in_w_valid; // @[LazyModule.scala 173:49]
assign auto_out_w_bits_data = auto_in_w_bits_data; // @[LazyModule.scala 173:49]
assign auto_out_w_bits_strb = auto_in_w_bits_strb; // @[LazyModule.scala 173:49]
assign auto_out_w_bits_last = auto_in_w_bits_last; // @[LazyModule.scala 173:49]
assign auto_out_b_ready = auto_in_b_ready; // @[LazyModule.scala 173:49]
assign auto_out_ar_valid = auto_in_ar_valid; // @[LazyModule.scala 173:49]
assign auto_out_ar_bits_id = auto_in_ar_bits_id; // @[LazyModule.scala 173:49]
assign auto_out_ar_bits_addr = auto_in_ar_bits_addr[29:0]; // @[LazyModule.scala 173:49]
assign auto_out_ar_bits_size = auto_in_ar_bits_size; // @[LazyModule.scala 173:49]
assign auto_out_r_ready = auto_in_r_ready; // @[LazyModule.scala 173:49]
endmodule
| 6.583104 |
module AXI4StreamToBundleBridge (
output auto_in_ready,
input auto_in_valid,
input [7:0] auto_in_bits_data,
input auto_in_bits_last,
input auto_out_ready,
output auto_out_valid,
output [7:0] auto_out_bits_data,
output auto_out_bits_last
);
assign auto_in_ready = auto_out_ready; // @[LazyModule.scala 173:31]
assign auto_out_valid = auto_in_valid; // @[LazyModule.scala 173:49]
assign auto_out_bits_data = auto_in_bits_data; // @[LazyModule.scala 173:49]
assign auto_out_bits_last = auto_in_bits_last; // @[LazyModule.scala 173:49]
endmodule
| 6.737467 |
module XOR20 (
input A,
input B,
output Q
);
xor (Q, B, A);
specify
(A => Q) = (1, 1);
(B => Q) = (1, 1);
endspecify
endmodule
| 7.125193 |
module speed (
rst,
speedKey,
unitsDisplay,
tensDisplay,
speedValue
);
// input declarations
input wire rst, speedKey;
// output declarations
output wire [6:0] unitsDisplay;
output wire [6:0] tensDisplay;
output reg [3:0] speedValue;
// internal registers
reg countDirection; //1 - up ; 0 - down
// internal parameters
parameter up = 1'b1, zero = 4'b0000, speed10 = 4'b0001, speed60 = 4'b0110;
always @(negedge speedKey or negedge rst) begin
if (~rst) begin // restart. reset enable at 0
speedValue = speed10; // initial speed = 10
countDirection = ~up; // initial direction = down
end else begin
if (speedValue == speed10 || speedValue == speed60)
countDirection = ~countDirection; //change direction
if (countDirection == up) speedValue <= speedValue + 1; // increase speed by 1
else speedValue <= speedValue - 1; // decrease speed by 1
end
end
//output logic
sevenSegment unitsConvert (
.in (zero),
.out(unitsDisplay)
); // output to display
sevenSegment tensConvert (
.in (speedValue),
.out(tensDisplay)
); // output to display
endmodule
| 7.342801 |
module lab5Part2 (
input [2:0] SW,
input CLOCK_50,
output [9:0] LEDR,
output [6:0] HEX0
);
assign LEDR[9:0] = 10'b0000000000; // all LEDs remain off
wire [4:0] disp_Count;
speedController S1 (
.f_Select(SW[1:0]),
.clock(CLOCK_50),
.reset(SW[2]),
.countState(disp_Count)
);
BCD_to_HEX_Decoder D1 (
.C (disp_Count[3:0]),
.HEX(HEX0)
);
endmodule
| 7.63386 |
module speedController (
input [1:0] f_Select,
input clock,
reset,
output [4:0] countState
);
wire [25:0] m_Cycles; // to connect max cycles.
wire dwnClk_Enable; // downclocked, synchronous enable for counter
speedSelect S1 (
.sel(f_Select),
.maxCycles(m_Cycles)
);
rateDivider R1 (
.maxCycles(m_Cycles),
.clock(clock),
.reset(reset),
.downClock(dwnClk_Enable)
);
fourBit_Counter C1 (
.clock(clock),
.reset(reset),
.enable(dwnClk_Enable),
.Q(countState)
);
endmodule
| 6.715175 |
module speedSelect (
input [1:0] sel,
output reg [25:0] maxCycles
);
always @(*) begin
case (sel)
2'b00: maxCycles = 26'd1; // 50MHz
2'b01: maxCycles = 26'd12; //500000; // 4Hz
2'b10: maxCycles = 26'd25; //000000; // 2Hz
2'b11: maxCycles = 26'd50; //000000; // 1Hz
default: maxCycles = 26'd50000000; // dwef
endcase
end
endmodule
| 8.319183 |
module fourBit_Counter (
input clock,
reset,
enable,
output reg [4:0] Q
);
always @(posedge clock) // triggered on rising edge of clock
begin
if (reset == 1'd0) // synch reset active-low
Q <= 5'd0;
else if (Q == 5'd16) // max vvalll
Q <= 5'd0;
else if (enable == 1'd1) // increment on enable
Q <= Q + 1;
else Q <= Q;
end
endmodule
| 6.963069 |
module speedCtrlMux (
directCtrlRate,
directCtrlPol,
sendPacketRate,
sendPacketPol,
sendPacketSel,
fullSpeedRate,
fullSpeedPol
);
input directCtrlRate;
input directCtrlPol;
input sendPacketRate;
input sendPacketPol;
input sendPacketSel;
output fullSpeedRate;
output fullSpeedPol;
wire directCtrlRate;
wire directCtrlPol;
wire sendPacketRate;
wire sendPacketPol;
wire sendPacketSel;
reg fullSpeedRate;
reg fullSpeedPol;
always @(directCtrlRate or directCtrlPol or sendPacketRate or sendPacketPol or sendPacketSel)
begin
if (sendPacketSel == 1'b1) begin
fullSpeedRate <= sendPacketRate;
fullSpeedPol <= sendPacketPol;
end else begin
fullSpeedRate <= directCtrlRate;
fullSpeedPol <= directCtrlPol;
end
end
endmodule
| 7.430587 |
module speedCtrlMux_simlib (
directCtrlRate,
directCtrlPol,
sendPacketRate,
sendPacketPol,
sendPacketSel,
fullSpeedRate,
fullSpeedPol
);
input directCtrlRate;
input directCtrlPol;
input sendPacketRate;
input sendPacketPol;
input sendPacketSel;
output fullSpeedRate;
output fullSpeedPol;
wire directCtrlRate;
wire directCtrlPol;
wire sendPacketRate;
wire sendPacketPol;
wire sendPacketSel;
reg fullSpeedRate;
reg fullSpeedPol;
always @(directCtrlRate or directCtrlPol or sendPacketRate or sendPacketPol or sendPacketSel)
begin
if (sendPacketSel == 1'b1) begin
fullSpeedRate <= sendPacketRate;
fullSpeedPol <= sendPacketPol;
end else begin
fullSpeedRate <= directCtrlRate;
fullSpeedPol <= directCtrlPol;
end
end
endmodule
| 7.640258 |
module speed_calculation #(
parameter MAX_VALUE = 49_999_999
) (
clk,
rst,
hall_sensor,
revolution
);
input clk;
input rst;
input hall_sensor;
output [7:0] revolution;
//wire enable;
//assign enable = (HA & ~LA & ~HB & LB & ~LC);
reg [25:0] count;
wire max_count = (count == MAX_VALUE); //max_count = 49,999,999
always @(posedge clk)
if (rst) count <= 26'h0;
else if (max_count) count <= 26'h0;
else count <= count + 26'h1;
//counter mechanical cycles
reg [7:0] mec_cycles = 8'h0;
wire min_count = (count == 26'h0);
always @(posedge hall_sensor, posedge min_count)
if (min_count) mec_cycles <= 8'h0;
else mec_cycles <= mec_cycles + 8'h1;
reg [7:0] D;
always @(posedge clk)
if (rst) D <= 8'h0;
else if (max_count) D <= mec_cycles;
assign revolution = D;
endmodule
| 7.256677 |
module speed_calculation_wrapper (
clock,
reset,
hall_f_a,
hall_f_b,
hall_f_c,
rpm
);
input clock;
input reset;
input hall_f_a;
input hall_f_b;
input hall_f_c;
output [9:0] rpm;
wire [7:0] rev_a;
wire [7:0] rev_b;
wire [7:0] rev_c;
wire [9:0] rpm_a;
wire [9:0] rpm_b;
wire [9:0] rpm_c;
wire [10:0] sum1, sum0, div1;
//hall a speed calculation
speed_calculation HA (
.clk(clock),
.rst(reset),
.hall_sensor(hall_f_a),
.revolution(rev_a)
);
//hall b speed calculation
speed_calculation HB (
.clk(clock),
.rst(reset),
.hall_sensor(hall_f_b),
.revolution(rev_b)
);
//hall c speed calculation
speed_calculation HC (
.clk(clock),
.rst(reset),
.hall_sensor(hall_f_c),
.revolution(rev_c)
);
rpm_lut HA_l (
.datain (rev_a),
.dataout(rpm_a)
);
rpm_lut HB_l (
.datain (rev_b),
.dataout(rpm_b)
);
rpm_lut HC_1 (
.datain (rev_c),
.dataout(rpm_c)
);
assign sum0 = rpm_a + rpm_b;
assign sum1 = div1 + rpm_c;
divider_2 S0 (
.clock (clock),
.reset (reset),
.datain (sum0),
.dataout(div1)
);
divider_2 S1 (
.clock (clock),
.reset (reset),
.datain (sum1),
.dataout(rpm)
);
endmodule
| 7.256677 |
module speed_clk ( // sync input
sys_clk,
sys_rst_l,
// data input
speed,
accelerate,
change_readyH,
// pulse output
pulse_clk
);
parameter XTAL_CLK = 20000000;
parameter CLK_DIV = 5000000;
input sys_rst_l; // async reset
input sys_clk; // main clock
input [7:0] init_speed;
input [7:0] accelerate;
input change_readyH;
output pulse_clk;
reg div;
reg cnt;
reg r_pulse_clk;
assign pulse_clk = r_pulse_clk;
always @(posedge sys_clk) begin
if (!sys_rst_l) begin
cnt <= 0;
r_pulse_clk = 0;
end else begin
if (cnt == CLK_DIV) begin
cnt <= 0;
r_pulse_clk <= ~r_pulse_clk;
end else begin
cnt <= cnt + 1;
end
end
end
endmodule
| 6.688223 |
module speed_cnt (
input clkin,
input rst,
input clken,
input [9:0] clk_freq,
output reg clkout
);
wire [31:0] limit;
assign limit = (25000000 / clk_freq);
reg [31:0] clkcount;
always @(posedge clkin) begin
if (rst) begin
clkcount = 0;
clkout = 1'b0;
end else begin
if (clken) begin
clkcount = clkcount + 1;
if (clkcount >= limit) begin
clkcount = 32'd0;
clkout = ~clkout;
end else clkout = clkout;
end else begin
clkcount = clkcount;
clkout = clkout;
end
end
end
endmodule
| 7.029104 |
module speed_computation (
clk_sys,
Hall_sensor,
rst,
RPM_out
);
parameter n = 13; //13 bits is enough to represent counter up to 5000 RPM
parameter m = 26;
parameter k = 7; //7 bits is enough to represent counter up to 5000/60 radian per second
input clk_sys; //this clock using 50MHz of FPGA clock system
input Hall_sensor; //this Hall sensor acted as clock;
input rst;
output [n-1:0] RPM_out;
reg [k-1:0] RPS_out = 7'b0;
wire rst_to_zero;
wire [k-1:0] rotation_per_second;
wire [m-1:0] sys_count;
wire en_mechanical_cycle;
//instantiate electrical_cycle_counter_upto_16 module
electrical_cycle_counter_upto_16 U0 (
.clk(Hall_sensor), /* .rst(rst), */
.en_mechanical_cycle(en_mechanical_cycle)
);
//instantiate mechanical_cycle_counter module
mechanical_cycle_counter U1 (
.clk(Hall_sensor),
.rst_to_zero(rst_to_zero),
.enable(en_mechanical_cycle),
.mec_cycle_count(rotation_per_second)
);
//instantiate general_counter module
general_counter U2 (
.clk_sys(clk_sys),
.rst(rst),
.sys_counter_up(sys_count)
);
assign rst_to_zero = (sys_count == 26'h2faf080) ? 1'b1 : 1'b0;
always @(posedge clk_sys) begin
if (sys_count == 26'h2faf07f) RPS_out <= rotation_per_second;
else RPS_out <= RPS_out;
end
//assign RPS_out = (sys_count < 26'h2faf080) ? RPS_out : rotation_per_second;
assign RPM_out = RPS_out * 6'h3c; //RPM_out = RPS times 60
endmodule
| 7.550645 |
module electrical_cycle_counter_upto_16 (
clk, /* rst, */
en_mechanical_cycle
);
input clk; //consider HallA/HallB/HallC as clock for this module
/* input rst; */
output wire en_mechanical_cycle;
reg [4:0] counter_up = 0;
always @(posedge clk) begin
// if(rst)
// counter_up <= 5'b00000;
// else
if (counter_up == 5'b10000) counter_up <= 5'b00000;
else counter_up <= counter_up + 5'b00001;
end
assign en_mechanical_cycle = (counter_up == 5'b10000) ? 1'b1 : 1'b0;
endmodule
| 6.892382 |
module mechanical_cycle_counter (
clk,
rst_to_zero,
enable,
mec_cycle_count
);
parameter n = 7;
input clk; // this is using HallA/HallB/HallC as clock
input rst_to_zero, enable;
output reg [n-1:0] mec_cycle_count = 0;
always @(posedge clk or posedge rst_to_zero) begin
if (rst_to_zero) mec_cycle_count <= 7'b0;
else if (enable) mec_cycle_count <= mec_cycle_count + {{(n - 1) {1'b0}}, 1'b1};
else mec_cycle_count <= mec_cycle_count;
end
endmodule
| 6.557139 |
module general_counter (
clk_sys,
rst,
sys_counter_up
);
parameter n = 26;
input clk_sys; //this clock using hall effect
input rst;
output reg [n-1:0] sys_counter_up;
reg [n-1:0] counter_ref;
always @(posedge clk_sys) begin
if (rst) sys_counter_up <= 26'b0;
else if (sys_counter_up == 26'h2faf080) sys_counter_up <= 2'b0;
else sys_counter_up <= sys_counter_up + {{(n - 1) {1'b0}}, 1'b1};
end
endmodule
| 6.636282 |
module speed_config (
input clk,
input rst_n,
input bps_start,
output clk_bps
);
`define CLK_PERIOD 10 //10ns,100MHz
`define BPS_SET 1152 //"115200/100"=1152表示波特率
`define BPS_PARA (10_000_000/`CLK_PERIOD/`BPS_SET) //波特率时钟周期
`define BPS_PARA_2 (`BPS_PARA/2)
reg [12:0] cnt; //分频计数器
reg clk_bps_r; //波特率时钟的寄存器
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt <= 13'd0; //计数器复位
end else if ((cnt == `BPS_PARA) || !bps_start) begin
cnt <= 13'd0; //计数器清零
end else begin
cnt <= cnt + 1'b1;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
clk_bps_r <= 1'b0;
end else if (cnt == `BPS_PARA_2) begin
clk_bps_r <= 1'b1; //接收数据位的中间采样点
end else begin
clk_bps_r <= 1'b0;
end
end
assign clk_bps = clk_bps_r;
endmodule
| 6.992478 |
module speed_controller (
input wire clk,
input wire reset,
input wire en,
input wire [7:0] actual_speed,
input wire [7:0] desired_speed,
input wire [7:0] init_pwm,
output wire [7:0] pwm_value
);
/*
**********************
* Signals
**********************
*/
wire speed_too_slow;
wire speed_too_fast;
wire slowing;
wire speeding_up;
reg [7:0] previous_speed;
wire up = speed_too_slow & ~speeding_up;
wire down = speed_too_fast & ~slowing;
reg [7:0] init_pwm_reg;
reg load;
/*
**********************
* Instantiations
**********************
*/
// Compare actual speed to desired speed
comparator comp_inst1 (
.clk(clk),
.reset(reset),
.en(en),
.in1(actual_speed), // [7:0]
.in2(desired_speed), // [7:0]
.less_than (speed_too_slow), // in1 < in2
//.equal(), // in1 = in2
.greater_than(speed_too_fast) // in1 > in2
);
// Check if we are accel or decel
comparator comp_inst2 (
.clk(clk),
.reset(reset),
.en(en),
.in1(actual_speed), // [7:0]
.in2(previous_speed), // [7:0]
.less_than (slowing), // in1 < in2
//.equal(), // in1 = in2
.greater_than(speeding_up) // in1 > in2
);
up_down_counter up_down_counter_inst (
.clk(clk),
.reset(reset),
.en(en),
.load(load),
.init_value(init_pwm_reg), // [7:0]
.up(up),
.down(down),
.out_value(pwm_value) // [7:0]
);
/*
**********************
* Main
**********************
*/
// Remember previous speed
always @(posedge clk) begin
if (reset) begin
previous_speed <= 0;
end else begin
if (en) begin
previous_speed <= actual_speed;
end
end
end
// Generate load for init_pwm
always @(posedge clk) begin
if (reset) begin
init_pwm_reg <= 0;
load <= 0;
end else begin
init_pwm_reg <= init_pwm;
load <= 0;
if (init_pwm_reg != init_pwm) begin
// new init_pwm value, so load it
load <= 1;
end
end
end
endmodule
| 7.063206 |
module speed_convertor (
clk,
rst,
speed_value,
SW3_half_step,
key1_quarterTurn,
SW2_AUTO,
out_flag
);
input wire clk, rst, SW3_half_step, key1_quarterTurn, SW2_AUTO;
input wire [3:0] speed_value;
output wire out_flag;
wire countMaxOut;
wire quarterTrunOut;
wire [23:0] max_count;
MaxCount maxCount (
.clk(clk),
.rst(rst),
.speed_value(speed_value),
.SW3_half_step(SW3_half_step),
.max_count(max_count)
);
CountToMax CountToMax (
.clk(clk),
.rst(rst),
.max_count(max_count),
.flag(countMaxOut)
);
quarterTurn quarterTurn (
.clk(clk),
.rst(rst),
.enable((~key1_quarterTurn) & (~SW2_AUTO)),
.in(countMaxOut),
.SW3_half_step(SW3_half_step),
.out_flag(quarterTrunOut)
);
assign out_flag = (~SW2_AUTO) ? quarterTrunOut : countMaxOut;
endmodule
| 6.883507 |
module speed_ctrl (
input wire rst,
input wire clk,
input wire avail,
input wire [7:0] data,
input wire signed [31:0] mX_maxSpd,
output reg signed [31:0] mX_tgtSpd,
input wire signed [31:0] mY_maxSpd,
output reg signed [31:0] mY_tgtSpd,
input wire signed [31:0] mZ_maxSpd,
output reg signed [31:0] mZ_tgtSpd,
input wire signed [31:0] mA_maxSpd,
output reg signed [31:0] mA_tgtSpd,
input wire signed [31:0] mB_maxSpd,
output reg signed [31:0] mB_tgtSpd,
input wire signed [31:0] mC_maxSpd,
output reg signed [31:0] mC_tgtSpd,
output wire [15:0] gpOut,
output reg [63:0] latchedData
);
wire hexValid;
wire [3:0] hexValue;
assign hexValid = ((data >= "0") && (data <= "9")) || ((data >= "a") && (data <= "f"));
assign hexValue = (data >= "a") ? (data - "a" + 10) : (data - "0");
reg [1:0] state;
reg [3:0] nibble;
reg [63:0] rxData;
reg latchedReady;
wire signed [7:0] mX = latchedData[63:56];
wire signed [7:0] mY = latchedData[55:48];
wire signed [7:0] mZ = latchedData[47:40];
wire signed [7:0] mA = latchedData[39:32];
wire signed [7:0] mB = latchedData[31:24];
wire signed [7:0] mC = latchedData[23:16];
assign gpOut = latchedData[15:0];
reg signed [7:0] mX_mult, mY_mult, mZ_mult, mA_mult, mB_mult, mC_mult;
wire signed [39:0] mX_result = mX_maxSpd * mX_mult;
wire signed [39:0] mY_result = mY_maxSpd * mY_mult;
wire signed [39:0] mZ_result = mZ_maxSpd * mZ_mult;
wire signed [39:0] mA_result = mA_maxSpd * mA_mult;
wire signed [39:0] mB_result = mB_maxSpd * mB_mult;
wire signed [39:0] mC_result = mC_maxSpd * mC_mult;
always @(posedge clk) begin
if (rst) begin
mX_tgtSpd <= 0;
mY_tgtSpd <= 0;
mZ_tgtSpd <= 0;
mA_tgtSpd <= 0;
mB_tgtSpd <= 0;
mC_tgtSpd <= 0;
state <= 0;
nibble <= 0;
rxData <= 0;
latchedReady <= 0;
latchedData <= 0;
mX_mult <= 0;
mY_mult <= 0;
mZ_mult <= 0;
mA_mult <= 0;
mB_mult <= 0;
mC_mult <= 0;
end else begin
// defaults
latchedReady <= 0;
if (avail) begin
case (state)
0: begin
if (data == "[") begin
nibble <= 0;
state <= 1;
end
end
1: begin
if (data == "[") begin
nibble <= 0;
state <= 1;
end else if (hexValid) begin
rxData <= {rxData[59:0], hexValue};
nibble <= nibble + 1;
if (nibble == 15) begin
state <= 2;
end
end else begin
nibble <= 0;
state <= 0;
end
end
2: begin
if (data == "[") begin
nibble <= 0;
state <= 1;
end else if (data == "]") begin
nibble <= 0;
state <= 0;
latchedReady <= 1;
latchedData <= rxData;
end else begin
nibble <= 0;
state <= 0;
end
end
default: begin
nibble <= 0;
state <= 0;
end
endcase
end
if (latchedReady) begin
if (mX < -4) mX_mult <= mX + 4;
else if (mX > +4) mX_mult <= mX - 4;
else mX_mult <= 0;
if (mY < -4) mY_mult <= mY + 4;
else if (mY > +4) mY_mult <= mY - 4;
else mY_mult <= 0;
if (mZ < -4) mZ_mult <= mZ + 4;
else if (mZ > +4) mZ_mult <= mZ - 4;
else mZ_mult <= 0;
if (mA < -4) mA_mult <= mA + 4;
else if (mA > +4) mA_mult <= mA - 4;
else mA_mult <= 0;
if (mB < -4) mB_mult <= mB + 4;
else if (mB > +4) mB_mult <= mB - 4;
else mB_mult <= 0;
if (mC < -4) mC_mult <= mC + 4;
else if (mC > +4) mC_mult <= mC - 4;
else mC_mult <= 0;
end
mX_tgtSpd <= mX_result[38:7];
mY_tgtSpd <= mY_result[38:7];
mZ_tgtSpd <= mZ_result[38:7];
mA_tgtSpd <= mA_result[38:7];
mB_tgtSpd <= mB_result[38:7];
mC_tgtSpd <= mC_result[38:7];
end
end
endmodule
| 7.277032 |
module speed_ctrl_04 (
input wire clk,
input wire rst_n,
output reg [5:0] cnt
);
parameter T_250ms = 36_650_000;
reg [25:0] count;
wire flag_250ms;
always @(posedge clk, negedge rst_n) begin
if (rst_n == 1'b0) count <= 26'd0;
else if (count < T_250ms - 1'b1) count <= count + 1'b1;
else count <= 26'd0;
end
assign flag_250ms = (count == T_250ms - 1'b1) ? 1'b1 : 1'b0;
always @(posedge clk, negedge rst_n) begin
if (rst_n == 1'b0) cnt <= 6'd0;
else if (flag_250ms == 1'b1) cnt <= cnt + 1'b1;
else cnt <= cnt;
end
endmodule
| 6.837333 |
module speed_display (
input wire [2:0] speed,
output [6:0] tens,
output [6:0] ones
);
bcd_7seg seg_tens (
.num(speed),
.seg_num(tens)
);
assign ones = 7'b1000000;
endmodule
| 8.127114 |
module bcd_7seg (
input wire [3:0] num,
output reg [6:0] seg_num
);
always @(num) begin
case (num)
4'b0: seg_num = 7'b1000000;
4'b1: seg_num = 7'b1111001;
4'b10: seg_num = 7'b0100100;
4'b11: seg_num = 7'b0110000;
4'b100: seg_num = 7'b0011001;
4'b101: seg_num = 7'b0010010;
4'b110: seg_num = 7'b0000010;
4'b111: seg_num = 7'b1011000;
4'b1000: seg_num = 7'b0000000;
4'b1001: seg_num = 7'b0011000;
4'b1010: seg_num = 7'b0001000;
4'b1011: seg_num = 7'b0000011;
4'b1100: seg_num = 7'b0100110;
4'b1101: seg_num = 7'b0010001;
4'b1110: seg_num = 7'b0000110;
4'b1111: seg_num = 7'b0001110;
default: seg_num = 7'b1000000;
endcase
end
endmodule
| 6.710996 |
module speed_generator (
input wire [ 3:0] speed,
output reg [25:0] bpm_ticks
);
parameter FREQ = 24000000;
// MHz / bpm * (60 seconds in minute) / 2 clocks per decrement
always @(*) begin
case (speed)
4'd0: bpm_ticks = FREQ / 40 * 60;
4'd1: bpm_ticks = FREQ / 60 * 60;
4'd2: bpm_ticks = FREQ / 72 * 60;
4'd3: bpm_ticks = FREQ / 80 * 60;
4'd4: bpm_ticks = FREQ / 88 * 60;
4'd5: bpm_ticks = FREQ / 96 * 60;
4'd6: bpm_ticks = FREQ / 104 * 60;
4'd7: bpm_ticks = FREQ / 112 * 60;
4'd8: bpm_ticks = FREQ / 120 * 60;
4'd9: bpm_ticks = FREQ / 132 * 60;
4'd10: bpm_ticks = FREQ / 144 * 60;
4'd11: bpm_ticks = FREQ / 152 * 60;
4'd12: bpm_ticks = FREQ / 160 * 60;
4'd13: bpm_ticks = FREQ / 176 * 60;
4'd14: bpm_ticks = FREQ / 192 * 60;
4'd15: bpm_ticks = FREQ / 208 * 60;
endcase
end
endmodule
| 7.749685 |
module speed_measurement (
clock,
reset,
hall_effect,
mac_out
);
input clock;
input reset;
input [2:0] hall_effect;
output reg mac_out;
parameter A = 3'b101, B = 3'b100, C = 3'b110, D = 3'b010, E = 3'b011, F = 3'b001;
reg [2:0] Tstep_Q, Tstep_D;
//Define the next state and output combinational circuits
always @(Tstep_Q, hall_effect) begin
mac_out = 1'b0;
case (Tstep_Q)
A:
if (hall_effect != 3'b101) begin
Tstep_D = hall_effect;
mac_out = 1'b1;
end else begin
Tstep_D = A;
mac_out = 1'b0;
end
B:
if (hall_effect != 3'b100) begin
Tstep_D = hall_effect;
mac_out = 1'b1;
end else begin
Tstep_D = B;
mac_out = 1'b0;
end
C:
if (hall_effect != 3'b110) begin
Tstep_D = hall_effect;
mac_out = 1'b1;
end else begin
Tstep_D = C;
mac_out = 1'b0;
end
D:
if (hall_effect != 3'b010) begin
Tstep_D = hall_effect;
mac_out = 1'b1;
end else begin
Tstep_D = D;
mac_out = 1'b0;
end
E:
if (hall_effect != 3'b011) begin
Tstep_D = hall_effect;
mac_out = 1'b1;
end else begin
Tstep_D = E;
mac_out = 1'b0;
end
F:
if (hall_effect != 3'b001) begin
Tstep_D = hall_effect;
mac_out = 1'b1;
end else begin
Tstep_D = F;
mac_out = 1'b0;
end
default: begin
Tstep_D = 3'bx;
mac_out = 1'bx;
end
endcase
end
//Define the sequential block
always @(posedge clock)
if (reset) Tstep_Q <= A;
else Tstep_Q <= Tstep_D;
endmodule
| 7.720324 |
module to slow down the 50MHz clock
// Written by Mathun
module speed_module(CLOCK_50, LEDG);
input CLOCK_50;
output [0:0] LEDG;
/* registers */
reg [25:0] counter;
reg state;
/* assign */
assign LEDG[0] = state;
/* state change */
always @ (posedge CLOCK_50) begin
counter <= counter + 1;
state <= counter[25]; // refresh every 1 second as default.
end
endmodule
| 6.596066 |
module speed_select (
input wire clk,
input wire rst_n,
input wire bps_start,
output wire clk_bps
);
/*
parameter bps9600 = 5207, //Taxa de transmissao de 9600bps
bps19200 = 2603, //Taxa de transmissao de 19200bps
bps38400 = 1301, //Taxa de transmissao de 38400bps
bps57600 = 867, //Taxa de transmissao de 57600bps
bps115200 = 433; //Taxa de transmissao de 115200bps
parameter bps9600_2 = 2603,
bps19200_2 = 1301,
bps38400_2 = 650,
bps57600_2 = 433,
bps115200_2 = 216;
*/
// Valores de cntagem de divisao de frequencia de taxa de transmissao
// podem ser alterados de acordo com os valores acima
//
`define BPS_PARA 5207
`define BPS_PARA_2 2603
// Declaracao de variaveis e sinais
reg [12:0] cnt;
reg clk_bps_r;
// Registro de selecao da taxa de transmissao
reg [2:0] uart_ctrl;
// Bloco always executado nas bordas de subida de clk ou bordas de descida de rst
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt <= 13'd0;
end else if ((cnt == `BPS_PARA) || !bps_start) begin
cnt <= 13'd0;
end else begin
cnt <= cnt + 1'b1;
end
end
// Bloco always executado nas bordas de subida de clk ou bordas de descida de rst
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
clk_bps_r <= 1'b0;
end else if ((cnt == `BPS_PARA_2) && bps_start) begin
clk_bps_r <= 1'b1;
end else begin
clk_bps_r <= 1'b0;
end
end
// --> Atribuir a 'clk_bps' o valor de 'clk_bps_r'
assign clk_bps = clk_bps_r;
endmodule
| 8.221921 |
module speed_select_rx (
input clk,
rst_n,
bps_start,
output clk_bps
);
// `define BPS_PARA 5207;//9600ʷƵֵ
// `define BPS_PARA_2 2603;//һʱ
reg [13:0] cnt; //Ƶ
reg clk_bps_r; //ʱӼĴ
reg [2:0] uart_ctrl; //ѡĴ
always @(posedge clk or negedge rst_n)
if (!rst_n) cnt <= 14'd0;
else if ((cnt == 5207) || !bps_start) //жϼǷﵽ1
cnt <= 14'd0;
else cnt <= cnt + 1'b1; //ʱ
always @(posedge clk or negedge rst_n) begin
if (!rst_n) clk_bps_r <= 1'b0;
else if (cnt == 2603) //ʼһʱ,в洢
clk_bps_r <= 1'b1;
else clk_bps_r <= 1'b0;
end
assign clk_bps = clk_bps_r; //uart_rxģ
endmodule
| 6.670943 |
module speed_setting #(
parameter BPS_SET = 1152, //波特率
parameter CLK_PERIORD = 40 //时钟周期40ns(25MHz)
) (
input clk, //25MHz主时钟
input rst_n, //低电平复位信号
input bps_start, //接收到数据后，波特率时钟启动信号置位
output clk_bps //clk_bps的高电平为接收或者发送数据位的中间采样点
);
`define BPS_PARA (10_000_000/CLK_PERIORD/BPS_SET) //10_000_000/`CLK_PERIORD/96;
`define BPS_PARA_2 (`BPS_PARA/2) //BPS_PARA/2;
reg [12:0] cnt; //分频计数
reg clk_bps_r; //波特率时钟寄存器
reg [ 2:0] uart_ctrl; //uart波特率选择寄存器
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt <= 13'd0;
else if ((cnt == `BPS_PARA) || !bps_start) cnt <= 13'd0; //波特率计数清零
else cnt <= cnt + 1'b1; //波特率时钟计数启动
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) clk_bps_r <= 1'b0;
else if (cnt == `BPS_PARA_2)
clk_bps_r <= 1'b1; //clk_bps_r高电平为接收数据位的中间采样点,同时也作为发送数据的数据改变点
else clk_bps_r <= 1'b0;
end
assign clk_bps = clk_bps_r;
endmodule
| 7.50403 |
module speed_test (
input clk,
input nomangle, // software settable
// client interface with RTEFI, see doc/clients.eps
input [10:0] len_c,
input [7:0] idata,
input raw_l,
input raw_s,
output [7:0] odata
);
parameter n_lat = 2; // minimum value is 1
// len_c counts down to 9, but we need something that counts up from 0
reg [7:0] count = 0;
reg [7:0] processed = 0;
always @(posedge clk) begin
count <= raw_s ? count + 1 : 0;
processed <= idata ^ (count & {8{~nomangle}});
end
// 13 bits input, 8 bits output, choose to pipeline output
reg_delay #(
.len(n_lat - 1),
.dw (8)
) align (
.clk (clk),
.gate (1'b1),
.reset(1'b0),
.din (processed),
.dout (odata)
);
endmodule
| 6.993034 |
module speed_test_tb;
parameter n_lat = 12;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("speed_test.vcd");
$dumpvars(5, speed_test_tb);
end
end
// Gateway to UDP, client interface test generator
wire [10:0] len_c;
wire [7:0] idata, odata;
wire clk, raw_l, raw_s;
client_sub #(
.n_lat(n_lat)
) net (
.clk(clk),
.len_c(len_c),
.idata(idata),
.raw_l(raw_l),
.raw_s(raw_s),
.odata(odata),
.thinking(1'b0)
);
// DUT
speed_test #(
.n_lat(n_lat)
) dut (
.clk(clk),
.nomangle(1'b0),
.len_c(len_c),
.idata(idata),
.raw_l(raw_l),
.raw_s(raw_s),
.odata(odata)
);
endmodule
| 6.724921 |
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