code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module IBUFG_LVCMOS15 (
O,
I
); // synthesis syn_black_box
output O;
input I;
endmodule
| 6.645095 |
module IBUFG_LVCMOS18 (
O,
I
); // synthesis syn_black_box
output O;
input I;
endmodule
| 6.645095 |
module IBUFG_LVCMOS2 (
O,
I
); // synthesis syn_black_box
output O;
input I;
endmodule
| 6.862655 |
module IBUFG_LVCMOS25 (
O,
I
); // synthesis syn_black_box
output O;
input I;
endmodule
| 6.862655 |
module IBUFG_LVCMOS33 (
O,
I
); // synthesis syn_black_box
output O;
input I;
endmodule
| 6.84274 |
module IBUFG_LVTTL (
O,
I
); // synthesis syn_black_box
output O;
input I;
endmodule
| 6.785299 |
module LUT2_D (
LO,
O,
I0,
I1
); // synthesis xc_map=lut syn_black_box
output O;
output LO;
input I0;
input I1;
parameter INIT = 4'b0;
LUT2 d (
O,
I0,
I1
);
defparam d.INIT = INIT;
assign LO = O;
endmodule
| 6.610296 |
module MUXCY_D (
LO,
O,
CI,
DI,
S
); // synthesis syn_black_box
output O;
output LO;
input CI;
input DI;
input S;
endmodule
| 6.747696 |
module RAM16X1D (
DPO,
SPO,
A0,
A1,
A2,
A3,
D,
DPRA0,
DPRA1,
DPRA2,
DPRA3,
WCLK,
WE
); // synthesis syn_black_box
parameter INIT = 16'h0000;
output DPO;
output SPO;
input A0;
input A1;
input A2;
input A3;
input D;
input DPRA0;
input DPRA1;
input... | 7.214201 |
module RAM16X2S (
O0,
O1,
A0,
A1,
A2,
A3,
D0,
D1,
WCLK,
WE
); // synthesis syn_black_box
parameter INIT_00 = 16'h0000;
parameter INIT_01 = 16'h0000;
output O0;
output O1;
input A0;
input A1;
input A2;
input A3;
input D0;
input D1;
input WCLK;
input WE;
en... | 6.79591 |
module RAM16X4S (
O0,
O1,
O2,
O3,
A0,
A1,
A2,
A3,
D0,
D1,
D2,
D3,
WCLK,
WE
); //synthesis syn_black_box
parameter INIT_00 = 16'h0000;
parameter INIT_01 = 16'h0000;
parameter INIT_02 = 16'h0000;
parameter INIT_03 = 16'h0000;
output O0;
output O1;
out... | 7.228089 |
module RAM64X1S (
O,
A0,
A1,
A2,
A3,
A4,
A5,
D,
WCLK,
WE
); // synthesis syn_black_box
parameter INIT = 64'h0000000000000000;
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input D;
input WCLK;
input WE;
endmodule
| 6.70696 |
module ROM16X1 (
O,
A0,
A1,
A2,
A3
); // synthesis syn_black_box
parameter INIT = 16'h0000;
output O;
input A0;
input A1;
input A2;
input A3;
endmodule
| 6.912224 |
module ROM32X1 (
O,
A0,
A1,
A2,
A3,
A4
); // synthesis syn_black_box
parameter INIT = 32'h00000000;
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
endmodule
| 6.860443 |
module ROM64X1 (
O,
A0,
A1,
A2,
A3,
A4,
A5
); // synthesis syn_black_box
parameter INIT = 64'h0000000000000000;
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
endmodule
| 7.252243 |
module ROM128X1 (
O,
A0,
A1,
A2,
A3,
A4,
A5,
A6
); // synthesis syn_black_box
parameter INIT = 128'h00000000000000000000000000000000;
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input A6;
endmodule
| 6.888303 |
module ROM256X1 (
O,
A0,
A1,
A2,
A3,
A4,
A5,
A6,
A7
); // synthesis syn_black_box
parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
input A5;
input A6;
input A7;
end... | 7.225115 |
module SRLC16 (
Q,
Q15,
A0,
A1,
A2,
A3,
CLK,
D
); // synthesis syn_black_box
output Q;
output Q15;
input A0;
input A1;
input A2;
input A3;
input CLK;
input D;
endmodule
| 6.770168 |
module SRLC16E (
Q,
Q15,
A0,
A1,
A2,
A3,
CE,
CLK,
D
); // synthesis syn_black_box
output Q;
output Q15;
input A0;
input A1;
input A2;
input A3;
input CE;
input CLK;
input D;
endmodule
| 6.802804 |
module SRLC16E_1 (
Q,
Q15,
A0,
A1,
A2,
A3,
CE,
CLK,
D
); // synthesis syn_black_box
output Q;
output Q15;
input A0;
input A1;
input A2;
input A3;
input CE;
input CLK;
input D;
endmodule
| 6.554028 |
module SRLC16_1 (
Q,
Q15,
A0,
A1,
A2,
A3,
CLK,
D
); // synthesis syn_black_box
output Q;
output Q15;
input A0;
input A1;
input A2;
input A3;
input CLK;
input D;
endmodule
| 6.699982 |
module XORCY (
O,
CI,
LI
); // synthesis syn_black_box
output O;
input CI;
input LI;
endmodule
| 6.992694 |
module IBUFGDS_LVPECL_25 (
O,
I,
IB
); // synthesis syn_black_box
output O;
input I, IB;
endmodule
| 6.584593 |
module spartan6_clocks (
input rst,
input sysclk_p,
input sysclk_n,
output clk_eth,
output clk_1x_90,
output clk_2x_0,
output pll_lock
);
parameter clkin_period = 5;
parameter dcm_mult = 5;
parameter dcm_div = 8;
parameter plladv_mult = 5;
parameter plladv_div0 = 16;
parameter... | 6.640304 |
module spartan6_dcm (
// Inputs
input clkref_i
// Outputs
, output clkout0_o
);
wire clkref_buffered_w;
wire clkfb;
wire clk0;
wire clkfx;
// Input buffering
IBUFG IBUFG_IN (
.I(clkref_i),
.O(clkref_buffered_w)
);
// Clocking primitive
DCM_SP #(
.CLKDV_DIVIDE(... | 7.448689 |
module spartan6_pll (
// Inputs
input clkref_i
// Outputs
, output clkout0_o
);
wire clkref_buffered_w;
wire clkfbout_w;
wire pll_clkout0_w;
wire pll_clkout0_buffered_w;
// Input buffering
assign clkref_buffered_w = clkref_i;
// Clocking primitive
PLL_BASE #(
.BANDWIDTH ... | 6.599485 |
module spart_rx_old (
input clk,
input rst,
input enable,
input rxd,
output reg [7:0] data,
output [7:0] rx_capture,
output rda
);
reg [8:0] rx_buf;
reg [3:0] bit_cnt;
reg [4:0] en_cnt;
reg start_detected;
reg old;
reg [4:0] old_en_cnt;
wire count;
wire sample;
// Single... | 6.778364 |
module spart_tb ();
reg stm_clk, stm_rst, stm_iocs, stm_iorw, stm_databus_oe, stm_wrt_tx, stm_rd_rx;
reg [1:0] stm_ioaddr;
reg [7:0] stm_databus_in, stm_tx_data;
wire rda_mon, tbr_mon, txd_mon, rx_in, tx_en, tb_rda_mon;
wire [7:0] databus_inout, final_data_mon;
assign databus_inout = (stm_databus_oe) ? s... | 6.631748 |
module spart_tx_old (
input clk,
input rst,
input enable,
input [7:0] data,
input [1:0] ioaddr,
input iorw,
output txd,
output tbr,
output reg [7:0] tx_capture
);
reg load, transmitting;
wire [3:0] bit_cnt;
reg [4:0] en_cnt, old_en_cnt;
localparam IDLE = 1'b0;
localparam ... | 6.626413 |
module cnt_4bit (
en,
clk,
rst,
bit_cnt
);
input clk, rst;
input [1:0] en; // {load, shift}
output reg [3:0] bit_cnt;
wire [3:0] in;
reg old;
wire shift;
assign in = ~|en ? bit_cnt : ~en[1] ? (bit_cnt == 4'd10) ? 4'h0 : (bit_cnt + 1) : 4'h0;
// Edge detector to hold the shift enable... | 7.453869 |
module tx_shift_reg (
en,
clk,
rst,
tx_data,
TX
);
input clk, rst;
input [1:0] en; // {load, shift}
input [7:0] tx_data;
output TX;
wire [9:0] in;
reg [9:0] tx_shft_reg;
reg old;
wire shift;
// Edge detector to hold the shift enable high for a single clock cycle
always @(po... | 7.005889 |
module spawner (
clk,
reset,
enable,
frequency,
spawn,
out
);
input clk, reset, enable;
// input clk should be CLOCK_50
input [1:0] frequency;
// frequency at which the pseudo_random numbers cycle. Also determines how long the spawn signal will be held for.
// 00 for making it enable s... | 7.87409 |
module slowclk (
clk,
reset,
enable,
frequency,
out
);
input clk, reset, enable;
// should make input clk be CLOCK_50
input [1:0] frequency;
output reg out;
// this is the slower 'clock', will output 0 or 1
wire [27:0] w1hz, w2hz, w3hz;
ratedivider r1hz (
enable,
{2'b00, ... | 7.153401 |
module LFSR (
clk,
reset,
enable,
spawn,
out
);
input clk, reset, enable;
// ToDo: make a counter hooked to enable so that there is a gap between each spawn. Make spawn reset the counter.
output reg [9:0] out;
// ToDo: set bits of out to match y-value of screen resolution - height of object... | 6.729795 |
module ratedivider (
enable,
load,
clk,
reset,
q
);
input enable, clk, reset;
input [27:0] load;
output reg [27:0] q;
initial q = load;
always @(posedge clk) begin
if (reset) q <= load;
else if (enable) begin
if (q == 28'd0) q <= load;
else q <= q - 1'b1;
end
en... | 8.084012 |
module SPC ( /*AUTOARG*/
// Outputs
spco,
spcptr,
// Inputs
clk,
reset,
state_fetch,
spcw,
spcnt,
spush,
srp,
swp
);
input clk;
input reset;
input state_fetch;
input [18:0] spcw;
input spcnt;
input spush;
input srp;
input swp;
output [18:0] spco;
o... | 6.546698 |
module spcm_core_nexys3 (
input wire clk, // main clock
input wire rst, // synchronous reset
input wire cs, // chip select
input wire [ADDR_BITS-1:2] addr, // address
input wire burst, // burst mode flag
output reg [31:0] dout, // data read in
output reg busy, // busy flag
output ... | 9.179782 |
module SPController (
input entry_sensor,
exit_sensor,
clk,
resetn,
input [7:0] entered_pass,
output reg entry,
NoSpace,
exit
);
reg [1:0] cur_s, nex_s;
parameter sensor = 2'b00, password = 2'b01, entrance = 2'b10, space = 2'b11;
parameter passkey = 8'hA4;
reg mem[0:49];
reg [... | 7.072054 |
module spc_pcx_buf ( /*AUTOARG*/
// Outputs
spc_pcx_data_pa,
spc_pcx_atom_pq,
spc_pcx_req_pq,
pcx_spc_grant_px_buf,
// Inputs
spc_pcx_data_pa_buf,
spc_pcx_atom_pq_buf,
spc_pcx_req_pq_buf,
pcx_spc_grant_px
);
input [`PCX_WIDTH-1:0] spc_pcx_data_pa_buf;
input spc_pcx_atom_pq... | 6.901589 |
module SPDIFdecoder (
input SPDIFin,
output [1:0] BMCdec,
input clk,
output reg edgeclk = 0,
output reg clkout = 0,
output reg [27:0] Dout = 0,
output reg [1:0] synccode = 0, //B=1,M=2,W=3,ERROR=0
output reg parityOK=0,//パリティチェック結果が正しければ1,誤りで0(paritycheck:OK=1,NG=0)
output [23:0] Au... | 6.875902 |
module spdif_audio_encoder #(
parameter audio_width = 16
) (
input wire reset,
input wire clk,
input wire clk256,
input wire i_valid,
output wire i_ready,
input wire [audio_width-1:0] i_audio,
input wire i_is_left,
output wire spdif
);
reg clk128;
always @(posedge clk256 or pose... | 6.753542 |
module spdif_bmc_encoder #(
parameter width = 4
) (
input wire clk128,
input wire reset,
input wire i_valid,
output wire i_ready,
input wire [width-1:0] i_data,
output reg is_underrun,
output reg q
);
reg is_valid_shift;
reg [width-2:0] shift_data;
reg [$clog2(width-1)-1:0] shift_... | 6.545627 |
module spdif_bmc_encoder_tb ();
parameter STEP = 1000000000 / (44100 * 128);
initial begin
$dumpfile("spdif_bmc_encoder_tb.vcd");
$dumpvars(0, bmc_encoder_);
end
reg mclk;
initial begin
mclk = 1'b0;
forever #(STEP / 2) mclk = ~mclk;
end
reg reset;
reg i_valid;
wire i_ready;
wire ... | 6.545627 |
module spdif_tx_tb;
// Signals
// -------
reg [15:0] audio_val = 16'h0000;
wire audio_ack;
wire spdif;
reg rst = 1'b1;
reg clk = 1'b0;
// DUT
// ---
// Encoder
spdif_tx #(
// Approximate 6.144 MHz clock from 25.125 MHz
// (we get 6.137 which is 0.1%... | 8.26142 |
module
*
* Copyright (C) 2021 Sylvain Munaut <tnt@246tNt.com>
* SPDX-License-Identifier: CERN-OHL-P-2.0
*/
`default_nettype none
module spdif_word_code (
// 27-bit word input
input wire [ 1:0] word_preamble, // 00=B, 10=M, 11=W
input wire [26:0] word_payload,
output wire word_ack,
// Encoded bi-ph... | 7.306032 |
module SpeakerControl (
input wire clk,
input wire [4:0] note,
output reg audio
);
reg [18:0] count;
reg [18:0] value;
always @(posedge clk)
if (count > 0) count = count - 1;
else begin
count <= value;
audio <= ~audio;
end
always @(posedge clk)
case (note)
// The... | 6.797029 |
module speaker_control (
clk, // clock from the crystal
rst, // active high reset
audio_in_left, // left channel audio data input
audio_in_right, // right channel audio data input
audio_mclk, // master clock
audio_lrck, // left-right clock, Word Select clock, or sample rate clock
audio... | 6.944398 |
module foo (
a,
b,
x
);
input a, b;
output x;
specify
if (a) (a *> x) = 10;
if (!a) (a *> x) = 21;
(b *> x) = 12;
endspecify
assign x = a ^ b;
endmodule
| 6.935051 |
module foo #(.p1(10), .p2(21)) (a,b,x,y);
input a,b;
output x,y;
specify
if (a) (a *> x) = p1;
if (!a) (a *> x) = p2;
(b *> x) = 12;
(a, b *> y) = 17;
endspecify
assign {x,y} = a + b;
endmodule
| 6.690934 |
module specdrum (
input wire clk,
input wire rst_n,
input wire [7:0] a,
input wire iorq_n,
input wire wr_n,
input wire [7:0] d,
output reg [7:0] specdrum_out
);
initial specdrum_out = 8'h00;
always @(posedge clk) begin
if (rst_n == 1'b0) specdrum_out <= 8'h00;
else if (iorq_n ==... | 7.215447 |
module special (
a,
b,
special,
specialsign,
zero,
aisnan,
bisnan,
infinity,
invalid,
specialcase,
specialsigncase
);
// external signals
input [`WIDTH-1:0] a, b; // floating-point inputs
output [`WIDTH-2:0] special; // special case output, exp + sig
output spec... | 8.673693 |
module SpecialAdd (
input [31:0] cin_Special,
input [31:0] zin_Special,
input reset,
input clock,
output reg idle_Special = 1'b0,
output reg [7:0] difference_Special,
output reg [35:0] cout_Special,
output reg [35:0] zout_Special,
output reg [31:0] sout_Special
);
wire z_sign;
w... | 7.497565 |
module SpecialCasesHandler (
isInputStable,
isFloat,
sign,
exponent,
mantissa,
out,
isInputNormalized
);
parameter SIZE = 8'd64, EXPONENT_SIZE = 4'd11, MANTISSA_SIZE = 6'd52;
input isFloat, isInputStable;
input sign;
input [EXPONENT_SIZE - 1:0] exponent;
input [MANTISSA_SIZE - ... | 7.431494 |
module specialJudge (
input [30:0] a,
input [30:0] b,
input [30:0] in,
output [30:0] out,
output err_INF
);
reg err;
reg [30:0] tmp;
initial begin
err = 1'b0;
end
always @* begin
tmp = in;
if (a == 31'b1111111_10000000_00000000_00000000 || b == 31'b1111111_10000000_00000000_0... | 6.800833 |
module specialkeys (
clk,
cpu_ce,
reset_n,
key_blksbr,
key_osd,
osd_command,
o_disable_rom,
o_blksbr_reset,
o_osd
);
input clk;
input cpu_ce;
input reset_n;
input key_blksbr;
input key_osd;
input [7:0] osd_command; // {F11,F12,HOLD}
output reg o_disable_rom;
output o... | 7.416959 |
module emulates the special operation performing part of the processor
* When it receives the en signal, it saves the PC and starts doing special ops
* (eg convolution). After it is done, it restores the PC to its value before
* special ops began
*
* Top module has to have a mux to decide when to select out_pc as... | 7.334367 |
module special_register_file (
// Reset and clock
input rst_n,
input clk,
// Register read/write signals
input [ 3:0] reg_select,
input read_enable,
output [31:0] read_value,
input write_enable,
input [31:0] write_value,
// Increment the instruction count regi... | 7.832977 |
module mydff (
output reg q,
input d,
input c
);
always @(posedge c) q <= d;
specify
(posedge c => (q +: d)) = (3, 2);
endspecify
endmodule
| 6.92993 |
module dff_rtl (
q,
d,
cp,
cdn
);
output q;
input d;
input cp;
input cdn;
reg qi;
always @(posedge cp or negedge cdn) begin
if (~cdn) qi <= 1'b0;
else qi <= d;
end
buf (q, qi);
specify
specparam tpd_cp_q_lh = 6;
specparam tpd_cp_q_hl = 7;
specparam tpd_cdn_q_lh =... | 7.027196 |
module dff (
clk,
d,
q
);
input d, clk;
output q;
reg q_out;
wire q;
specify
specparam tR_clk_q = 100, tF_clk_q = 150;
(clk, d => q) = (tR_clk_q, tF_clk_q);
endspecify
always @(posedge clk) q_out <= d;
buf u_buf (q, q_out);
endmodule
| 6.824043 |
module Spectolizer #(
////////////////////////////////////////////////////
// Parameters
parameter bw_fftp = 11,
parameter bw_dpram = 12,
parameter bw_fftdata = 16,
parameter bw_data = 16
) (
////////////////////////////////////////////////////
// Ports
input Clock,
Reset,
/... | 6.518935 |
module StreamBuffer (
input clock,
input reset,
input auto_out_out_ready,
output auto_out_out_valid,
output [7:0] auto_out_out_bits_data,
output auto_out_out_bits_last,
output auto_in_in_ready,
input auto_in_in_valid,
input [7:0] auto_in... | 6.986803 |
module NCOTable (
input [ 8:0] io_phase,
output [15:0] io_sinOut,
output [15:0] io_cosOut
);
wire [ 8:0] tableNCO_io_phase; // @[NCOTable.scala 475:13]
wire [15:0] tableNCO_io_sinOut; // @[NCOTable.scala 475:13]
wire [15:0] tableNCO_io_cosOut; // @[NCOTable.scala 475:13]
NCOTableStandardMode tab... | 6.814188 |
module StreamBuffer_1 (
input clock,
input reset,
input auto_out_out_ready,
output auto_out_out_valid,
output [31:0] auto_out_out_bits_data,
output auto_out_out_bits_last,
output auto_in_in_ready,
input auto_in_in_valid,
input [31... | 6.662474 |
module StreamBuffer_2 (
input clock,
input reset,
input auto_out_out_ready,
output auto_out_out_valid,
output [31:0] auto_out_out_bits_data,
output auto_out_out_bits_last,
output auto_in_in_ready,
input auto_in_in_valid,
input [31... | 6.662474 |
module StreamBuffer_3 (
input clock,
input reset,
input auto_out_out_ready,
output auto_out_out_valid,
output [31:0] auto_out_out_bits_data,
output auto_out_out_bits_last,
output auto_in_in_ready,
input auto_in_in_valid,
input [31... | 6.662474 |
module IntToBundleBridge (
input auto_in_0,
output auto_out_0
);
assign auto_out_0 = auto_in_0; // @[LazyModule.scala 173:49]
endmodule
| 6.772464 |
module BundleBridgeToAXI4 (
output auto_in_aw_ready,
input auto_in_aw_valid,
input auto_in_aw_bits_id,
input [31:0] auto_in_aw_bits_addr,
input [ 2:0] auto_in_aw_bits_size,
output auto_in_w_ready,
input auto_in_w_valid,
input [31:0] auto_in_w_bits... | 6.583104 |
module AXI4StreamToBundleBridge (
output auto_in_ready,
input auto_in_valid,
input [7:0] auto_in_bits_data,
input auto_in_bits_last,
input auto_out_ready,
output auto_out_valid,
output [7:0] auto_out_bits_data,
output auto_out_bits_last
);
assign... | 6.737467 |
module XOR20 (
input A,
input B,
output Q
);
xor (Q, B, A);
specify
(A => Q) = (1, 1);
(B => Q) = (1, 1);
endspecify
endmodule
| 7.125193 |
module speed (
rst,
speedKey,
unitsDisplay,
tensDisplay,
speedValue
);
// input declarations
input wire rst, speedKey;
// output declarations
output wire [6:0] unitsDisplay;
output wire [6:0] tensDisplay;
output reg [3:0] speedValue;
// internal registers
reg countDirection; //1 ... | 7.342801 |
module lab5Part2 (
input [2:0] SW,
input CLOCK_50,
output [9:0] LEDR,
output [6:0] HEX0
);
assign LEDR[9:0] = 10'b0000000000; // all LEDs remain off
wire [4:0] disp_Count;
speedController S1 (
.f_Select(SW[1:0]),
.clock(CLOCK_50),
.reset(SW[2]),
.countState(disp_Count)
... | 7.63386 |
module speedController (
input [1:0] f_Select,
input clock,
reset,
output [4:0] countState
);
wire [25:0] m_Cycles; // to connect max cycles.
wire dwnClk_Enable; // downclocked, synchronous enable for counter
speedSelect S1 (
.sel(f_Select),
.maxCycles(m_Cycles)
);
rateDivider ... | 6.715175 |
module speedSelect (
input [1:0] sel,
output reg [25:0] maxCycles
);
always @(*) begin
case (sel)
2'b00: maxCycles = 26'd1; // 50MHz
2'b01: maxCycles = 26'd12; //500000; // 4Hz
2'b10: maxCycles = 26'd25; //000000; // 2Hz
2'b11: maxCycles = 26'd50; //000000; // 1Hz
... | 8.319183 |
module fourBit_Counter (
input clock,
reset,
enable,
output reg [4:0] Q
);
always @(posedge clock) // triggered on rising edge of clock
begin
if (reset == 1'd0) // synch reset active-low
Q <= 5'd0;
else if (Q == 5'd16) // max vvalll
Q <= 5'd0;
else if (enable == 1'd1) ... | 6.963069 |
module speedCtrlMux (
directCtrlRate,
directCtrlPol,
sendPacketRate,
sendPacketPol,
sendPacketSel,
fullSpeedRate,
fullSpeedPol
);
input directCtrlRate;
input directCtrlPol;
input sendPacketRate;
input sendPacketPol;
input sendPacketSel;
output fullSpeedRate;
output fullSpeedPol... | 7.430587 |
module speedCtrlMux_simlib (
directCtrlRate,
directCtrlPol,
sendPacketRate,
sendPacketPol,
sendPacketSel,
fullSpeedRate,
fullSpeedPol
);
input directCtrlRate;
input directCtrlPol;
input sendPacketRate;
input sendPacketPol;
input sendPacketSel;
output fullSpeedRate;
output fullS... | 7.640258 |
module speed_calculation #(
parameter MAX_VALUE = 49_999_999
) (
clk,
rst,
hall_sensor,
revolution
);
input clk;
input rst;
input hall_sensor;
output [7:0] revolution;
//wire enable;
//assign enable = (HA & ~LA & ~HB & LB & ~LC);
reg [25:0] count;
wire max_count = (count == MAX_... | 7.256677 |
module speed_calculation_wrapper (
clock,
reset,
hall_f_a,
hall_f_b,
hall_f_c,
rpm
);
input clock;
input reset;
input hall_f_a;
input hall_f_b;
input hall_f_c;
output [9:0] rpm;
wire [7:0] rev_a;
wire [7:0] rev_b;
wire [7:0] rev_c;
wire [9:0] rpm_a;
wire [9:0] rpm_b;
w... | 7.256677 |
module speed_clk ( // sync input
sys_clk,
sys_rst_l,
// data input
speed,
accelerate,
change_readyH,
// pulse output
pulse_clk
);
parameter XTAL_CLK = 20000000;
parameter CLK_DIV = 5000000;
input sys_rst_l; // async reset
input sys_clk; // main clock
input [7:0] init_... | 6.688223 |
module speed_cnt (
input clkin,
input rst,
input clken,
input [9:0] clk_freq,
output reg clkout
);
wire [31:0] limit;
assign limit = (25000000 / clk_freq);
reg [31:0] clkcount;
always @(posedge clkin) begin
if (rst) begin
clkcount = 0;
clkout = 1'b0;
end else begin
... | 7.029104 |
module speed_computation (
clk_sys,
Hall_sensor,
rst,
RPM_out
);
parameter n = 13; //13 bits is enough to represent counter up to 5000 RPM
parameter m = 26;
parameter k = 7; //7 bits is enough to represent counter up to 5000/60 radian per second
input clk_sys; //this clock using 50MHz of FPGA... | 7.550645 |
module electrical_cycle_counter_upto_16 (
clk, /* rst, */
en_mechanical_cycle
);
input clk; //consider HallA/HallB/HallC as clock for this module
/* input rst; */
output wire en_mechanical_cycle;
reg [4:0] counter_up = 0;
always @(posedge clk) begin
// if(rst)
// counter_up <= 5'b00000;
... | 6.892382 |
module mechanical_cycle_counter (
clk,
rst_to_zero,
enable,
mec_cycle_count
);
parameter n = 7;
input clk; // this is using HallA/HallB/HallC as clock
input rst_to_zero, enable;
output reg [n-1:0] mec_cycle_count = 0;
always @(posedge clk or posedge rst_to_zero) begin
if (rst_to_zero) m... | 6.557139 |
module general_counter (
clk_sys,
rst,
sys_counter_up
);
parameter n = 26;
input clk_sys; //this clock using hall effect
input rst;
output reg [n-1:0] sys_counter_up;
reg [n-1:0] counter_ref;
always @(posedge clk_sys) begin
if (rst) sys_counter_up <= 26'b0;
else if (sys_counter_up == ... | 6.636282 |
module speed_config (
input clk,
input rst_n,
input bps_start,
output clk_bps
);
`define CLK_PERIOD 10 //10ns,100MHz
`define BPS_SET 1152 //"115200/100"=1152表示波特率
`define BPS_PARA (10_000_000/`CLK_PERIOD/`BPS_SET) //波特率时钟周期
`define BPS_PARA_2 (`BPS_PARA/2)
reg [12:0] cnt; //分频计数器
reg c... | 6.992478 |
module speed_controller (
input wire clk,
input wire reset,
input wire en,
input wire [7:0] actual_speed,
input wire [7:0] desired_speed,
input wire [7:0] init_pwm,
output wire [7:0] pwm_value
);
/*
**********************
* Signals
**********************
*/
wire speed_too_slow;
w... | 7.063206 |
module speed_convertor (
clk,
rst,
speed_value,
SW3_half_step,
key1_quarterTurn,
SW2_AUTO,
out_flag
);
input wire clk, rst, SW3_half_step, key1_quarterTurn, SW2_AUTO;
input wire [3:0] speed_value;
output wire out_flag;
wire countMaxOut;
wire quarterTrunOut;
wire [23:0] max_c... | 6.883507 |
module speed_ctrl (
input wire rst,
input wire clk,
input wire avail,
input wire [7:0] data,
input wire signed [31:0] mX_maxSpd,
output reg signed [31:0] mX_tgtSpd,
input wire signed [31:0] mY_maxSpd,
output reg signed [31:0] mY_tgtSpd,
input wire signed [31:0] mZ_maxSpd,
... | 7.277032 |
module speed_ctrl_04 (
input wire clk,
input wire rst_n,
output reg [5:0] cnt
);
parameter T_250ms = 36_650_000;
reg [25:0] count;
wire flag_250ms;
always @(posedge clk, negedge rst_n) begin
if (rst_n == 1'b0) count <= 26'd0;
else if (count < T_250ms - 1'b1) count <= count + 1'b... | 6.837333 |
module speed_display (
input wire [2:0] speed,
output [6:0] tens,
output [6:0] ones
);
bcd_7seg seg_tens (
.num(speed),
.seg_num(tens)
);
assign ones = 7'b1000000;
endmodule
| 8.127114 |
module bcd_7seg (
input wire [3:0] num,
output reg [6:0] seg_num
);
always @(num) begin
case (num)
4'b0: seg_num = 7'b1000000;
4'b1: seg_num = 7'b1111001;
4'b10: seg_num = 7'b0100100;
4'b11: seg_num = 7'b0110000;
4'b100: seg_num = 7'b0011001;
4'b101: seg_num = 7'b0010... | 6.710996 |
module speed_generator (
input wire [ 3:0] speed,
output reg [25:0] bpm_ticks
);
parameter FREQ = 24000000;
// MHz / bpm * (60 seconds in minute) / 2 clocks per decrement
always @(*) begin
case (speed)
4'd0: bpm_ticks = FREQ / 40 * 60;
4'd1: bpm_ticks = FREQ / 60 * 60;
4'd2: bp... | 7.749685 |
module speed_measurement (
clock,
reset,
hall_effect,
mac_out
);
input clock;
input reset;
input [2:0] hall_effect;
output reg mac_out;
parameter A = 3'b101, B = 3'b100, C = 3'b110, D = 3'b010, E = 3'b011, F = 3'b001;
reg [2:0] Tstep_Q, Tstep_D;
//Define the next state and output combi... | 7.720324 |
module to slow down the 50MHz clock
// Written by Mathun
module speed_module(CLOCK_50, LEDG);
input CLOCK_50;
output [0:0] LEDG;
/* registers */
reg [25:0] counter;
reg state;
/* assign */
assign LEDG[0] = state;
/* state change */
always @ (posedge CLOCK_50) begin
c... | 6.596066 |
module speed_select (
input wire clk,
input wire rst_n,
input wire bps_start,
output wire clk_bps
);
/*
parameter bps9600 = 5207, //Taxa de transmissao de 9600bps
bps19200 = 2603, //Taxa de transmissao de 19200bps
bps38400 = 1301, //Taxa de transmissao de 38400bps
bps5760... | 8.221921 |
module speed_select_rx (
input clk,
rst_n,
bps_start,
output clk_bps
);
// `define BPS_PARA 5207;//9600ʷƵֵ
// `define BPS_PARA_2 2603;//һʱ
reg [13:0] cnt; //Ƶ
reg clk_bps_r; //ʱӼĴ
reg [2:0] uart_ctrl; //ѡĴ
always @(posedge clk or negedge rst_n)
if (!rst_n) cnt <= 14'd0;
else if... | 6.670943 |
module speed_setting #(
parameter BPS_SET = 1152, //波特率
parameter CLK_PERIORD = 40 //时钟周期40ns(25MHz)
) (
input clk, //25MHz主时钟
input rst_n, //低电平复位信号
input bps_start, //接收到数据后，波特率时钟启动信号置位
output clk_bps //clk_bps的高电平为接收或者发送数据位的中间采样点
);
`define BPS_PARA (10_000_000/CLK_PERIORD/BPS... | 7.50403 |
module speed_test (
input clk,
input nomangle, // software settable
// client interface with RTEFI, see doc/clients.eps
input [10:0] len_c,
input [7:0] idata,
input raw_l,
input raw_s,
output [7:0] odata
);
parameter n_lat = 2; // minimum value is 1
// len_c counts down to 9, but... | 6.993034 |
module speed_test_tb;
parameter n_lat = 12;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("speed_test.vcd");
$dumpvars(5, speed_test_tb);
end
end
// Gateway to UDP, client interface test generator
wire [10:0] len_c;
wire [7:0] idata, odata;
wire clk, raw_l, raw_s;
clien... | 6.724921 |
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