code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module spi (
input clk,
input miso,
output mosi,
output sck,
input rst,
input start,
input cpol,
input cpha,
input [4:0] bits_per_word,
input [5:0] div,
input [MAX_DATA_WIDTH-1:0] data_in,
output [MAX_DATA_WIDTH-1:0] data_out,
output busy,
output new_data
);
parameter MAX_DATA_WIDTH = 32;
localparam IDLE = 3'd0;
localparam START = 3'd1;
localparam TRANSFER_STAGE_1 = 3'd2;
localparam TRANSFER_STAGE_2 = 3'd3;
reg [1:0] state;
reg [1:0] next_state;
reg [4:0] ctrl;
reg [4:0] next_ctrl;
reg clk_div;
reg [15:0] counter;
reg new_data;
reg sck;
reg mosi;
assign busy = state != IDLE;
always @(posedge clk or posedge rst) begin
if (rst) begin
counter <= 0;
clk_div <= 1'b0;
end else begin
if (counter == div) begin
clk_div <= 1'b1;
counter <= 0;
end else begin
clk_div <= 1'b0;
counter <= counter + 1'b1;
end
end
end
always @(posedge clk or posedge rst) begin
if (rst) begin
next_state <= IDLE;
next_ctrl <= 5'b00000;
new_data <= 1'b0;
end else begin
if (clk_div) begin
case (state)
IDLE: begin
sck <= cpol;
mosi <= 1'b0;
next_ctrl = 5'b00000;
if (start == 1'b1) begin
next_state = START;
new_data <= 1'b0;
end
end
START: begin
if (start == 1'b0) begin
if (cpha == 1'b0) begin
next_state = TRANSFER_STAGE_1;
end else begin
next_state = TRANSFER_STAGE_2;
end
end
end
TRANSFER_STAGE_1: begin
next_state = TRANSFER_STAGE_2;
sck <= cpol;
if (cpha == 1'b0) begin
mosi <= data_in[bits_per_word-ctrl];
end else begin
data_out[bits_per_word-ctrl] <= miso;
next_ctrl = ctrl + 1'b1;
end
if (ctrl == bits_per_word && cpha == 1'b1) begin
next_state = IDLE;
new_data <= 1'b1;
end
end
TRANSFER_STAGE_2: begin
next_state = TRANSFER_STAGE_1;
sck <= !cpol;
if (cpha == 1'b0) begin
data_out[bits_per_word-ctrl] <= miso;
next_ctrl = ctrl + 1'b1;
end else begin
mosi <= data_in[bits_per_word-ctrl];
end
if (ctrl == bits_per_word && cpha == 1'b0) begin
next_state = IDLE;
new_data <= 1'b1;
end
end
endcase
end
end
end
always @(posedge clk or posedge rst) begin
if (rst) begin
state <= IDLE;
ctrl <= 5'b00000;
end else begin
ctrl <= next_ctrl;
state <= next_state;
end
end
endmodule
| 7.760909 |
module spi_slave #(
parameter MAX_BITS_PER_WORD = 8,
parameter USE_TX = "TRUE",
parameter USE_RX = "TRUE"
) (
input rst_i,
input clk_i,
input en_i,
input [3:0] bit_per_word_i,
input lsb_first_i,
input ss_i,
input scl_i,
output miso_o,
input mosi_i,
input [MAX_BITS_PER_WORD - 1:0] bus_i,
output reg rdy_o,
input rdy_ack_i,
output reg [MAX_BITS_PER_WORD - 1:0] bus_o,
output first_byte_o,
output last_byte_o,
input last_byte_ack_i
);
reg [MAX_BITS_PER_WORD - 1:0] rx_shift_reg;
reg [MAX_BITS_PER_WORD - 1:0] tx_shift_reg;
reg [3:0] bit_cnt;
reg first_byte_1;
reg first_byte_2;
reg rdy_p;
reg rdy_n;
reg last_byte_p;
reg last_byte_n;
reg cs_p;
reg cs_start_p;
reg [3:0] bit_per_word_int;
always @(posedge rst_i or posedge clk_i or negedge en_i) begin
if (rst_i | ~en_i) begin
rdy_n <= 'h0;
end else if (rdy_ack_i) begin
rdy_n <= rdy_p;
end
end
always @(posedge rst_i or posedge clk_i or negedge en_i) begin
if (rst_i | ~en_i) begin
last_byte_n <= 1'b0;
end else if (last_byte_ack_i) begin
last_byte_n <= last_byte_p;
end
end
always @(posedge rst_i or posedge clk_i or negedge en_i) begin
if (rst_i | ~en_i) begin
last_byte_p <= 1'b0;
cs_p <= 1'b1;
end else begin
if (last_byte_p == last_byte_n && {cs_p, ss_i} == 2'b01) begin
last_byte_p <= ~last_byte_p;
end
cs_p <= ss_i;
end
end
//rx
always @(posedge rst_i or posedge scl_i or posedge ss_i or negedge en_i) begin
if (rst_i | ~en_i) begin
rx_shift_reg <= 'hFFF;
bit_cnt <= 4'h0;
first_byte_1 <= 1'b0;
first_byte_2 <= 1'b0;
rdy_p <= 1'b0;
bit_per_word_int <= bit_per_word_i - 4'd1;
bus_o <= 8'h00;
end else begin
if (ss_i) begin
rx_shift_reg <= 'hFFF;
bit_cnt <= 4'h0;
first_byte_1 <= 1'b0;
first_byte_2 <= 1'b0;
bit_per_word_int <= bit_per_word_i - 4'd1;
end else begin
bit_cnt <= bit_cnt + 4'd1;
if (bit_cnt == bit_per_word_int) begin
first_byte_2 <= first_byte_1;
first_byte_1 <= 1'b1;
if (rdy_p == rdy_n) begin
rdy_p <= ~rdy_p;
end
if (USE_RX == "TRUE") begin
if (lsb_first_i == 1'b0) begin
bus_o <= {rx_shift_reg[MAX_BITS_PER_WORD-2:0], mosi_i};
end else begin
bus_o <= rx_shift_reg[MAX_BITS_PER_WORD-1:0];
bus_o[bit_cnt] <= mosi_i;
end
end
bit_cnt <= 4'h0;
end
if (USE_RX == "TRUE") begin
if (lsb_first_i == 1'b0) begin
rx_shift_reg <= {rx_shift_reg[MAX_BITS_PER_WORD-2:0], mosi_i};
end else begin
rx_shift_reg[bit_cnt] <= mosi_i;
end
end
end
end
end
//tx
always @(posedge rst_i or negedge scl_i or posedge ss_i or negedge en_i) begin
if (USE_TX == "TRUE") begin
if (rst_i | ~en_i) begin
tx_shift_reg <= 'h0;
end else begin
if (bit_cnt == 4'h0 || ss_i) begin
tx_shift_reg <= bus_i;
end else begin
if (lsb_first_i == 1'b0) begin
tx_shift_reg <= {tx_shift_reg[MAX_BITS_PER_WORD-2:0], 1'b0};
end else begin
tx_shift_reg <= {1'b0, tx_shift_reg[MAX_BITS_PER_WORD-1:1]};
end
end
end
end
end
always @(posedge clk_i) begin
if (rst_i) begin
rdy_o <= 1'b0;
end else begin
rdy_o <= rdy_p ^ rdy_n;
end
end
assign miso_o = (ss_i | ~en_i) ? 1'bz : (lsb_first_i == 1'b0 ? tx_shift_reg[bit_per_word_int] : tx_shift_reg[0]);
assign first_byte_o = first_byte_1 & ~first_byte_2;
assign last_byte_o = last_byte_n ^ last_byte_p;
endmodule
| 6.875224 |
module spi (
input wire clk, // 7MHz
input wire enviar_dato, // a 1 para indicar que queremos enviar un dato por SPI
input wire recibir_dato, // a 1 para indicar que queremos recibir un dato
input wire [7:0] din, // del bus de datos de salida de la CPU
output reg [7:0] dout, // al bus de datos de entrada de la CPU
output reg oe_n, // el dato en dout es vlido
output reg wait_n,
output wire spi_clk, // Interface SPI
output wire spi_di, //
input wire spi_do //
);
// Modulo SPI.
reg ciclo_lectura = 1'b0; // ciclo de lectura en curso
reg ciclo_escritura = 1'b0; // ciclo de escritura en curso
reg [4:0] contador = 5'b00000; // contador del FSM (ciclos)
reg [7:0] data_to_spi; // dato a enviar a la spi por DI
reg [7:0] data_from_spi; // dato a recibir desde la spi
reg [7:0] data_to_cpu; // ultimo dato recibido correctamente
assign spi_clk = contador[0]; // spi_CLK es la mitad que el reloj del mdulo
assign spi_di = data_to_spi[7]; // la transmisin es del bit 7 al 0
initial wait_n = 1'b1;
always @(posedge clk) begin
if (enviar_dato && !ciclo_escritura) begin // si ha sido sealizado, iniciar ciclo de escritura
ciclo_escritura <= 1'b1;
ciclo_lectura <= 1'b0;
contador <= 5'b00000;
data_to_spi <= din;
wait_n <= 1'b0;
end
else if (recibir_dato && !ciclo_lectura) begin // si no, si mirar si hay que iniciar ciclo de lectura
ciclo_lectura <= 1'b1;
ciclo_escritura <= 1'b0;
contador <= 5'b00000;
data_to_cpu <= data_from_spi;
data_from_spi <= 8'h00;
data_to_spi <= 8'hFF; // mientras leemos, MOSI debe estar a nivel alto!
wait_n <= 1'b0;
end // FSM para enviar un dato a la spi
else if (ciclo_escritura == 1'b1) begin
if (contador != 5'b10000) begin
if (contador == 5'b01000) wait_n <= 1'b1;
if (spi_clk == 1'b1) begin
data_to_spi <= {data_to_spi[6:0], 1'b0};
data_from_spi <= {data_from_spi[6:0], spi_do};
end
contador <= contador + 1;
end else begin
if (!enviar_dato) ciclo_escritura <= 1'b0;
end
end // FSM para leer un dato de la spi
else if (ciclo_lectura == 1'b1) begin
if (contador != 5'b10000) begin
if (contador == 5'b01000) wait_n <= 1'b1;
if (spi_clk == 1'b1) data_from_spi <= {data_from_spi[6:0], spi_do};
contador <= contador + 1;
end else begin
if (!recibir_dato) ciclo_lectura <= 1'b0;
end
end
end
always @* begin
if (recibir_dato) begin
dout = data_to_cpu;
oe_n = 1'b0;
end else begin
dout = 8'hZZ;
oe_n = 1'b1;
end
end
endmodule
| 7.760909 |
module implement a 16-bit shift register and control logic to send
// 16-bit words serially, MSB first, to a low-speed DAC. The bit rate is
// 1/4 of the input clock rate. The serial clock (sclk) positive edge occurs
// 1/4 cycle after sync becomes active. Data changes 1/4 cycle after the
// falling edge of sclk.
//
// 15 slices used. Maximum clock rate is 243 MHz.
//
// History:
// 12-8-10 eliminated truncation warning for Spartan-6 (dec. by 1)
//
module spi16o(
input iocs, // select this port
input iowr, // write data
input [15:0] din, // parallel data input
input clk, // common clock and reset
input rst,
output sck, // serial clock
output sdo, // serial data output
output sync // active low enable
);
// internal signals
wire ce,se,we; // count enable, shift enable, write enable
reg [15:0] d; // transmit shift register
reg [5:0] c; // counter
// address decode
assign we = iocs & iowr;
// data storage
always @ (posedge clk)
begin
if (rst) c <= 0; // count from 63 to 0 then stop after preset
else if (we) c <= 63;
else if (ce) c <= c - 6'b000001;
if (we) d <= din; // load when WE true, else shift left
else if (se) d <= {d[14:0],1'b0};
end
assign ce = |c; // enable count down as long as counter is non-zero
assign se = ~|c[1:0]; // enable shifting on every 4th clock
// connect outputs
assign sdo = d[15]; // data sent MSB first
assign sck = c[1]; // clock out is 1/4 clock in
assign sync = ~(we|ce); // sync signal is active low
endmodule
| 8.672374 |
module spi2dac (
clk,
data_in,
load,
dac_sdi,
dac_cs,
dac_sck,
dac_ld
);
input clk; // 50MHz system clock of DE0
input [9:0] data_in; // input data to DAC
input load; // Pulse to load data to dac
output dac_sdi; // SPI serial data out
output dac_cs; // chip select - low when sending data to dac
output dac_sck; // SPI clock, 16 cycles at half clk freq
output dac_ld;
//-------------Input Ports-----------------------------
// All the input ports should be wires
wire clk, load;
wire [9:0] data_in;
//-------------Output Ports-----------------------------
// Output port can be a storage element (reg) or a wire
reg dac_cs, dac_ld;
wire dac_sck, dac_sdi;
parameter BUF = 1'b1; // 0:no buffer, 1:Vref buffered
parameter GA_N = 1'b1; // 0:gain = 2x, 1:gain = 1x
parameter SHDN_N = 1'b1; // 0:power down, 1:dac active
wire [3:0] cmd = {1'b0, BUF, GA_N, SHDN_N}; // wire to VDD or GND
// --- Submodule: Generate internal clock at 1 MHz -----
reg clk_1MHz; // 1Mhz clock derived from 50MHz
reg [4:0] ctr; // internal counter
parameter TIME_CONSTANT = 5'd24; // change this for diff clk freq
initial begin
clk_1MHz = 0; // don't need to reset - don't care if it is 1 or 0 to start
ctr = 5'b0; // ... Initialise when FPGA is configured
end
always @(posedge clk) //
if (ctr == 0) begin
ctr <= TIME_CONSTANT;
clk_1MHz <= ~clk_1MHz; // toggle the output clock for squarewave
end else ctr <= ctr - 1'b1;
// ---- end internal clock generator ----------
// ---- Detect posedge of load with a small state machine
// .... FF set on posedge of load
// .... reset when dac_cs goes high at the end of DAC output cycle
reg [1:0] sr_state;
parameter IDLE = 2'b00, WAIT_CSB_FALL = 2'b01, WAIT_CSB_HIGH = 2'b10;
reg dac_start; // set if a DAC write is detected
initial begin
sr_state = IDLE;
dac_start = 1'b0; // set while sending data to DAC
end
always @(posedge clk)
case (sr_state)
IDLE:
if (load == 1'b0) sr_state <= IDLE;
else begin
sr_state <= WAIT_CSB_FALL;
dac_start <= 1'b1;
end
WAIT_CSB_FALL:
if (dac_cs == 1'b1) sr_state <= WAIT_CSB_FALL;
else sr_state <= WAIT_CSB_HIGH;
WAIT_CSB_HIGH:
if (dac_cs == 1'b0) sr_state <= WAIT_CSB_HIGH;
else begin
sr_state <= IDLE;
dac_start <= 1'b0;
end
default: sr_state <= IDLE;
endcase
//------- End circuit to detect start and end of conversion
//------- spi controller designed as a state machine
// .... with 17 states (idle, and S1-S16
// .... for the 16 cycles each sending 1-bit to dac)
reg [4:0] state;
initial begin
state = 5'b0;
dac_ld = 1'b0;
dac_cs = 1'b1;
end
always @(posedge clk_1MHz) begin
// default outputs and state transition
dac_cs <= 1'b0;
dac_ld <= 1'b1;
state <= state + 1'b1; // move to next state by default
case (state)
5'd0:
if (dac_start == 1'b0) begin
state <= 5'd0; // still waiting
dac_cs <= 1'b1;
end
5'd16: begin
dac_cs <= 1'b1;
dac_ld <= 1'b0;
state <= 5'd0; // go back to idle state
end
default: begin // all other states
dac_cs <= 1'b0;
dac_ld <= 1'b1;
state <= state + 1'b1; // default state transition
end
endcase
end // ... always
// shift register for output data
reg [15:0] shift_reg;
initial begin
shift_reg = 16'b0;
end
always @(posedge clk_1MHz)
if ((dac_start == 1'b1) && (dac_cs == 1'b1)) // parallel load data to shift reg
shift_reg <= {cmd, data_in, 2'b00};
else // .. else start shifting
shift_reg <= {shift_reg[14:0], 1'b0};
// Assign outputs to drive SPI interface to DAC
assign dac_sck = !clk_1MHz & !dac_cs;
assign dac_sdi = shift_reg[15];
endmodule
| 7.828507 |
module spiarbiter (
i_clk,
i_cs_a_n,
i_ck_a,
i_mosi_a,
i_cs_b_n,
i_ck_b,
i_mosi_b,
o_cs_a_n,
o_cs_b_n,
o_ck,
o_mosi,
o_grant
);
input i_clk;
input i_cs_a_n, i_ck_a, i_mosi_a;
// output wire o_grant_a;
input i_cs_b_n, i_ck_b, i_mosi_b;
// output wire o_grant_b;
output wire o_cs_a_n, o_cs_b_n, o_ck, o_mosi;
//
output wire o_grant; // == o_grant_a = ~o_grant_b
reg a_owner;
initial a_owner = 1'b1;
always @(posedge i_clk)
if ((i_cs_a_n) && (i_cs_b_n)) a_owner <= 1'b1; // Keep control
else if ((i_cs_a_n) && (~i_cs_b_n)) a_owner <= 1'b0; // Give up control
else if ((~i_cs_a_n) && (i_cs_b_n)) a_owner <= 1'b1; // Take control
// assign o_grant_a = a_owner;
// assign o_grant_b = (~a_owner);
assign o_cs_a_n = (~a_owner) || (i_cs_a_n);
assign o_cs_b_n = (a_owner) || (i_cs_b_n);
assign o_ck = (a_owner) ? i_ck_a : i_ck_b;
assign o_mosi = (a_owner) ? i_mosi_a : i_mosi_b;
assign o_grant = ~a_owner;
endmodule
| 7.77286 |
module SPIbs (
input clock,
input reset,
// input byte valid
input wire ib_v,
// input byte value
input wire [7:0] ib_in,
output wire [7:0] rb_o,
output wire byte_ready,
output wire sclk,
output wire mosi,
input wire miso
);
assign sclk = divclk & ib_v;
assign byte_ready = (sc == 4'd7) & divcnt[3] & ~(|divcnt[2:0]);
reg [7:0] wb;
reg [6:0] divcnt;
reg [3:0] sc;
reg [7:0] rb;
reg tr;
wire divclk;
assign divclk = divcnt[3];
assign mosi = wb[0];
assign rb_o = {rb[6:0], tr};
always @(posedge clock or posedge reset) begin
if (reset) begin
divcnt <= 0;
end
divcnt <= divcnt + 1;
end
always @(posedge divclk) begin
tr <= miso;
end
always @(negedge divclk or posedge reset) begin
rb <= (reset | ((sc == 4'd7) & ib_v)) ? 8'd0 : {rb[6:0], tr};
wb <= (reset | ((sc == 4'd7) & ib_v)) ? ib_in : {1'b0, wb[7:1]};
sc <= (reset | ((sc == 4'd7) & ib_v)) ? 4'd0 : sc + 1;
end
endmodule
| 6.664835 |
modules. The spi_master
// selects the data to be transmitted and stores all data received
// from the PmodACL. The data is then made available to the rest of
// the design on the xAxis, yAxis, and zAxis outputs.
//
//
// Inputs:
// CLK 100MHz onboard system clock
// RST Main Reset Controller
// START Signal to initialize a data transfer
// SDI Serial Data In
//
// Outputs:
// SDO Serial Data Out
// SCLK Serial Clock
// SS Slave Select
// xAxis x-axis data received from PmodACL
// yAxis y-axis data received from PmodACL
// zAxis z-axis data received from PmodACL
//
// Revision History:
// Revision 0.01 - File Created (Andrew Skreen)
// Revision 1.00 - Added comments and modified code (Josh Sackos)
////////////////////////////////////////////////////////////////////////////////////
// ===================================================================================
// Define Module, Inputs and Outputs
// ===================================================================================
module SPIcomponent(
CLK,
RST,
START,
SDI,
SDO,
SCLK,
SS,
xAxis,
yAxis,
zAxis
);
// ====================================================================================
// Port Declarations
// ====================================================================================
input CLK;
input RST;
input START;
input SDI;
output SDO;
output SCLK;
output SS;
output [9:0] xAxis;
output [9:0] yAxis;
output [9:0] zAxis;
// ====================================================================================
// Parameters, Register, and Wires
// ====================================================================================
wire [9:0] xAxis;
wire [9:0] yAxis;
wire [9:0] zAxis;
wire [15:0] TxBuffer;
wire [7:0] RxBuffer;
wire doneConfigure;
wire done;
wire transmit;
// ===================================================================================
// Implementation
// ===================================================================================
//-------------------------------------------------------------------------
// Controls SPI Interface, Stores Received Data, and Controls Data to Send
//-------------------------------------------------------------------------
SPImaster C0(
.rst(RST),
.start(START),
.clk(CLK),
.transmit(transmit),
.txdata(TxBuffer),
.rxdata(RxBuffer),
.done(done),
.x_axis_data(xAxis),
.y_axis_data(yAxis),
.z_axis_data(zAxis)
);
//-------------------------------------------------------------------------
// Produces Timing Signal, Reads ACL Data, and Writes Data to ACL
//-------------------------------------------------------------------------
SPIinterface C1(
.sdi(SDI),
.sdo(SDO),
.rst(RST),
.clk(CLK),
.sclk(SCLK),
.txbuffer(TxBuffer),
.rxbuffer(RxBuffer),
.done_out(done),
.transmit(transmit)
);
//-------------------------------------------------------------------------
// Enables/Disables PmodACL Communication
//-------------------------------------------------------------------------
slaveSelect C2(
.clk(CLK),
.ss(SS),
.done(done),
.transmit(transmit),
.rst(RST)
);
endmodule
| 8.292332 |
module spiControl (
input clock, //On-board Zynq clock (100 MHz)
input reset,
input [7:0] data_in,
input load_data, //Signal indicates new data for transmission
output reg done_send, //Signal indicates data has been sent over spi interface
output spi_clock, //10MHz max
output reg spi_data
);
reg [2:0] counter = 0;
reg [2:0] dataCount;
reg [7:0] shiftReg;
reg [1:0] state;
reg clock_10;
reg CE;
assign spi_clock = (CE == 1) ? clock_10 : 1'b1;
always @(posedge clock) begin
if (counter != 4) counter <= counter + 1;
else counter <= 0;
end
initial clock_10 <= 0;
always @(posedge clock) begin
if (counter == 4) clock_10 <= ~clock_10;
end
localparam IDLE = 'd0, SEND = 'd1, DONE = 'd2;
always @(negedge clock_10) begin
if (reset) begin
state <= IDLE;
dataCount <= 0;
done_send <= 1'b0;
CE <= 0;
spi_data <= 1'b1;
end else begin
case (state)
IDLE: begin
if (load_data) begin
shiftReg <= data_in;
state <= SEND;
dataCount <= 0;
end
end
SEND: begin
spi_data <= shiftReg[7];
shiftReg <= {shiftReg[6:0], 1'b0};
CE <= 1;
if (dataCount != 7) dataCount <= dataCount + 1;
else begin
state <= DONE;
end
end
DONE: begin
CE <= 0;
done_send <= 1'b1;
if (!load_data) begin
done_send <= 1'b0;
state <= IDLE;
end
end
endcase
end
end
endmodule
| 6.726953 |
module spidlg (
input Clk,
input Dclk,
input Din,
input Dlatch,
output [6:0] Dout,
output [5:0] Addr,
output CLR,
output WR
);
reg clear;
reg write_latch;
reg [3:0] address;
reg [8:0] sr;
reg [2:0] state;
// Commands
parameter CLEAR = 0, LOAD = 1, LOAD_ADV = 2, GOTO_POS = 3;
// States
parameter S_IDLE=0, S_CLEAR=1, S_LOAD=2, S_WR=3, S_LOAD_ADV=4, S_ADV_WR=5, S_GOTO_POS=6;
// Shift Register
always @(posedge Dclk) begin
sr[8:1] <= sr[7:0];
sr[0] <= Din;
end
// State machine
always @(posedge Clk or posedge Dlatch) begin
if (Dlatch)
case (sr[8:7])
CLEAR: state = S_CLEAR;
LOAD: state = S_LOAD;
LOAD_ADV: state = S_LOAD_ADV;
GOTO_POS: state = S_GOTO_POS;
default: state = S_IDLE;
endcase
else
case (state)
S_IDLE: begin
address <= address;
state = S_IDLE;
end
S_CLEAR: begin
address <= 0;
state = S_IDLE;
end
S_GOTO_POS: begin
address <= sr[3:0];
state = S_IDLE;
end
S_LOAD: begin
address <= address;
state = S_WR;
end
S_WR: begin
address <= address;
state = S_IDLE;
end
S_LOAD_ADV: begin
address <= address;
state = S_ADV_WR;
end
S_ADV_WR: begin
address <= address + 1;
state = S_IDLE;
end
endcase
end
// Latch and Clear control
always @(state) begin
case (state)
default: begin
clear <= 0;
write_latch <= 0;
end
S_GOTO_POS: begin
clear <= 0;
write_latch <= 0;
end
S_LOAD_ADV: begin
clear <= 0;
write_latch <= 0;
end
S_CLEAR: begin
clear <= 1;
write_latch <= 0;
end
S_WR: begin
clear <= 0;
write_latch <= 1;
end
S_ADV_WR: begin
clear <= 0;
write_latch <= 1;
end
endcase
end
assign Dout = sr[6:0];
assign CLR = ~clear;
assign WR = ~write_latch;
assign Addr[5] = ~address[3];
assign Addr[4] = ~address[2];
assign Addr[3] = address[3];
assign Addr[2] = address[2];
assign Addr[1] = ~address[1];
assign Addr[0] = ~address[0];
endmodule
| 7.313117 |
module SPIDriver_tb;
reg master_clock = 1'b1;
reg [ 2:0] image_number = 3'b000;
reg [ 2:0] access_type = 3'b000;
reg [11:0] absolute_position = 12'd1018;
wire [14:0] write_addr;
wire write_data;
wire write_clock;
wire nCS;
wire MOSI;
wire MISO;
wire CLK;
wire nWP;
wire nHOLD;
SPILoader Main (
.MCLK(master_clock),
.IMGNUM(image_number),
.ACCTYPE(access_type),
.ABSPOS(absolute_position),
.OUTBUFWADDR (write_addr),
.OUTBUFWDATA (write_data),
.nOUTBUFWCLKEN(write_clock),
.nCS (nCS),
.MOSI (MOSI),
.MISO (MISO),
.CLK (CLK),
.nWP (nWP),
.nHOLD(nHOLD)
);
W25Q32JVxxIM Module0 (
.CSn(nCS),
.CLK(CLK),
.DO(MISO),
.DIO(MOSI),
.WPn(nWP),
.HOLDn(nHOLD),
.RESETn(nHOLD)
);
always #1 master_clock = ~master_clock;
initial begin
#10000 access_type = 3'b110;
#60000 access_type = 3'b000;
#100 access_type = 3'b001;
#100 access_type = 3'b111;
#20000 access_type = 3'b000;
end
endmodule
| 6.719993 |
module spigpio (
clk,
cs,
sr_in,
gpioin,
gpioout,
sr_out
);
input clk, cs;
input sr_in;
input [9:0] gpioin;
output sr_out;
output [9:0] gpioout;
reg [9:0] gpioout;
reg sr_out;
reg [7:0] ram;
wire [6:0] addr;
wire [7:0] data;
wire rw;
reg [15:0] sr;
assign rw = sr[15];
assign addr = sr[14:8];
assign data = sr[7:0];
always @(posedge clk or posedge cs) begin
if (cs == 1'b0) begin
sr_out <= sr[15];
sr[15:1] <= sr[14:0];
sr[0] <= sr_in;
end
if (cs == 1'b1) begin
if (rw == 1'b0) begin
case (addr)
`P0_OP: gpioout[0] <= data[0];
`P1_OP: gpioout[1] <= data[0];
`P2_OP: gpioout[2] <= data[0];
`P3_OP: gpioout[3] <= data[0];
`P4_OP: gpioout[4] <= data[0];
`P5_OP: gpioout[5] <= data[0];
`P6_OP: gpioout[6] <= data[0];
`P7_OP: gpioout[7] <= data[0];
`P8_OP: gpioout[8] <= data[0];
`P9_OP: gpioout[9] <= data[0];
`P0_P9_OP:
gpioout[9:0] <= {
data[0], data[0], data[0], data[0], data[0], data[0], data[0], data[0], data[0], data[0]
};
`P0_P3_OP: gpioout[3:0] <= {data[0], data[0], data[0], data[0]};
`P4_P7_OP: gpioout[7:4] <= {data[0], data[0], data[0], data[0]};
`P8_P9_OP: gpioout[9:8] <= {data[0], data[0]};
`RAM: ram[7:0] <= data[7:0];
endcase
end
if (rw == 1'b1) // READ THE PORT LEVEL
begin
case (addr)
`P0_OP: sr[7:0] <= {7'b0, gpioout[0]};
`P1_OP: sr[7:0] <= {7'b0, gpioout[1]};
`P2_OP: sr[7:0] <= {7'b0, gpioout[2]};
`P3_OP: sr[7:0] <= {7'b0, gpioout[3]};
`P4_OP: sr[7:0] <= {7'b0, gpioout[4]};
`P5_OP: sr[7:0] <= {7'b0, gpioout[5]};
`P6_OP: sr[7:0] <= {7'b0, gpioout[6]};
`P7_OP: sr[7:0] <= {7'b0, gpioout[7]};
`P8_OP: sr[7:0] <= {7'b0, gpioout[8]};
`P9_OP: sr[7:0] <= {7'b0, gpioout[9]};
`P0_P9_OP: sr[7:0] <= {7'b0, gpioout[0]};
`P0_P3_OP: sr[7:0] <= {7'b0, gpioout[0]};
`P4_P7_OP: sr[7:0] <= {7'b0, gpioout[4]};
`P8_P9_OP: sr[7:0] <= {7'b0, gpioout[8]};
`PO_P7_IP: sr[7:0] <= gpioin[7:0];
`P8_P9_IP: sr[7:0] <= gpioin[9:8];
`RAM: sr[7:0] <= ram[7:0];
endcase
end
end
end
endmodule
| 6.590193 |
module SPIHandler (
CLK,
ARST_L,
DIN,
DOUT,
SEND,
DONE,
MOSI,
MISO,
SCLK_A,
SS,
XDATA_MISO,
YDATA_MISO
);
input CLK, ARST_L;
input [23:0] DIN;
output [23:0] DOUT;
input SEND;
output DONE;
input MISO;
output MOSI;
output SS, SCLK_A;
output [7:0] XDATA_MISO;
output [7:0] YDATA_MISO;
reg [7:0] XDATA_MISO;
reg [7:0] YDATA_MISO;
wire READNWRITE;
reg [23:0] SPIReg;
wire roll_i;
reg [4:0] count_i;
reg DONE;
reg SS;
reg SCLK_A;
reg [2:0] HandlerReg;
reg [2:0] HandlerNext;
//State machine state names as parameters
parameter [2:0] IDLE_HANDLER = 3'b000;
parameter [2:0] SSLOW = 3'b001;
parameter [2:0] SCLK_AHIGH = 3'b010;
parameter [2:0] SCLK_ALOW = 3'b011;
parameter [2:0] SSHIGH = 3'b100;
parameter [2:0] DONESTROBE = 3'b101;
assign MOSI = SPIReg[23]; //shifting data OUT MSB first
assign READNWRITE = (DIN[7:0] == 8'b00000000) ? 1'b1 : 1'b0;
//READING == 1 when DIN == 0
//SPIReg Shift Register
always @(posedge CLK or negedge ARST_L) begin
if (~ARST_L) SPIReg <= 24'h000000;
else if (HandlerReg == SSLOW) SPIReg <= DIN; //LOAD SPI REG
else if ((READNWRITE == 1'b0) && (HandlerReg == SCLK_ALOW))
SPIReg <= {SPIReg[22:0], 1'b0}; //SHIFT SPI REG
else if ((READNWRITE == 1'b1) && (HandlerReg == SCLK_ALOW))
SPIReg <= {SPIReg[22:0], MISO}; //LOAD SPI REG..Maybe shifts?
// else if (READNWRITE == 1'b0)
//// SPIReg <= {SPIReg [22:0], 0};
else;
end
//MISO!!!
always @(posedge CLK or negedge ARST_L)
if (~ARST_L) begin
XDATA_MISO <= 8'b00000000;
YDATA_MISO <= 8'b00000000;
end else if ((READNWRITE == 1'b1) && (HandlerReg == SSHIGH) && (DONE == 1'b1)) begin
XDATA_MISO <= SPIReg[7:0];
YDATA_MISO <= SPIReg[7:0];
end else;
//State Memory
always @(posedge CLK or negedge ARST_L)
if (~ARST_L) HandlerReg <= IDLE_HANDLER;
else HandlerReg <= HandlerNext;
//Next State Logic
always @(SEND or roll_i or HandlerReg) begin
case (HandlerReg)
IDLE_HANDLER:
if (SEND == 1'b1) HandlerNext <= SSLOW;
else HandlerNext <= IDLE_HANDLER;
SSLOW: HandlerNext <= SCLK_AHIGH;
SCLK_AHIGH: HandlerNext <= SCLK_ALOW;
SCLK_ALOW:
if (roll_i == 1'b1) HandlerNext <= SSHIGH;
else HandlerNext <= SCLK_AHIGH;
SSHIGH: HandlerNext <= DONESTROBE;
DONESTROBE: HandlerNext <= IDLE_HANDLER;
endcase
end
//SS and SCLK_A and DONE
always @(posedge CLK or negedge ARST_L) begin
if (~ARST_L) begin
DONE <= 1'b0;
SS <= 1'b1;
SCLK_A <= 1'b0;
end else if (HandlerReg == SSLOW) SS <= 1'b0;
else if (HandlerReg == SCLK_AHIGH) SCLK_A <= 1'b1;
else if (HandlerReg == SCLK_ALOW) SCLK_A <= 1'b0;
else if (HandlerReg == SSHIGH) SS <= 1'b1;
else if (HandlerReg == DONESTROBE) DONE <= 1'b1;
else begin
DONE <= 1'b0;
SS <= 1'b1;
SCLK_A <= 1'b0;
end
end
//24 count counter!
always @(posedge CLK or negedge ARST_L)
if (~ARST_L) count_i <= 5'b00000;
else if (roll_i == 1'b1) count_i <= 5'b00000;
else if (HandlerReg == SCLK_AHIGH) count_i <= count_i + 1;
else;
assign roll_i = (count_i == 24) ? 1'b1 : 1'b0;
endmodule
| 7.310697 |
module spihub (
input wire fclk,
input wire rst_n,
// pins to SDcard
output reg sdcs_n,
output wire sdclk,
output wire sddo,
input wire sddi,
// zports SDcard iface
input wire zx_sdcs_n_val,
input wire zx_sdcs_n_stb,
input wire zx_sd_start,
input wire [7:0] zx_sd_datain,
output wire [7:0] zx_sd_dataout,
// slavespi SDcard iface
input wire avr_lock_in,
output reg avr_lock_out,
input wire avr_sdcs_n,
input wire avr_sd_start,
input wire [7:0] avr_sd_datain,
output wire [7:0] avr_sd_dataout
);
// spi2 module control
wire [7:0] sd_datain;
wire [7:0] sd_dataout;
wire sd_start;
// single dataout to all ifaces
assign zx_sd_dataout = sd_dataout;
assign avr_sd_dataout = sd_dataout;
// spi2 module itself
spi2 spi2 (
.clock(fclk),
.sck(sdclk),
.sdo(sddo),
.sdi(sddi),
.start(sd_start),
.din (sd_datain),
.dout (sd_dataout),
.speed(2'b00)
);
// control locking/arbitrating between ifaces
always @(posedge fclk, negedge rst_n)
if (!rst_n) avr_lock_out <= 1'b0;
else // posedge fclk
begin
if (sdcs_n) avr_lock_out <= avr_lock_in;
end
// control cs_n to SDcard
always @(posedge fclk, negedge rst_n)
if (!rst_n) sdcs_n <= 1'b1;
else // posedge fclk
begin
if (avr_lock_out) sdcs_n <= avr_sdcs_n;
else // !avr_lock_out
if (zx_sdcs_n_stb) sdcs_n <= zx_sdcs_n_val;
end
// control start and outgoing data to spi2
assign sd_start = avr_lock_out ? avr_sd_start : zx_sd_start;
//
assign sd_datain = avr_lock_out ? avr_sd_datain : zx_sd_datain;
endmodule
| 6.936413 |
module spi (
clk,
rstb,
sclk,
Nss0,
mosi,
miso,
start,
busy,
clk_end,
wr_data,
rd_data,
rd_data_en,
rd_1byte
);
input clk;
input rstb;
//SPI
output sclk;
output Nss0;
output mosi;
input miso;
//interface
input start; //通信開始
output busy; //通信中
input [5:0] clk_end; //通信クロック数
input [63:0] wr_data; //書き込みデータ
output [63:0] rd_data; //読み出しデータ
output rd_data_en; //読み出しデータイネーブル
output reg [7:0] rd_1byte;
reg sclk;
reg mosi;
reg start_d1;
wire start_sig;
reg [ 5:0] clk_end_cnt;
reg busy;
reg [63:0] mosi_data;
reg [63:0] miso_data;
reg [63:0] rd_data;
reg [11:0] cnt_1clk;
reg [ 5:0] clk_cnt;
reg [15:0] state_cnt;
reg rd_data_en;
parameter p_1bit_cnt = 12'd10;
parameter p_mosi_chg = 12'd1;
parameter p_miso_trg = p_1bit_cnt - 12'd1;
// wr,rd 1clk delay
always @(posedge clk or negedge rstb)
if (rstb == 1'b0) begin
start_d1 <= 1'b0;
end else begin
start_d1 <= start;
end
// strat signal
assign start_sig = ((start == 1'b1) && (start_d1 == 1'b0)) ? 1'b1 : 1'b0;
//end_cnt hold
always @(posedge clk or negedge rstb)
if (rstb == 1'b0) clk_end_cnt <= 6'd0;
else if (start_sig == 1'b1) clk_end_cnt <= clk_end - 6'd1;
else clk_end_cnt <= clk_end_cnt;
//busy signel
always @(posedge clk or negedge rstb)
if (rstb == 1'b0) busy <= 1'b0;
else if (start_sig == 1'b1) busy <= 1'b1;
else if ((cnt_1clk == p_1bit_cnt) && (clk_cnt == clk_end_cnt)) busy <= 1'b0;
else busy <= busy;
//SCLK generator
always @(posedge clk or negedge rstb)
if (rstb == 1'b0) begin
cnt_1clk <= 12'd0;
clk_cnt <= 5'd0;
end else if (busy == 1'b0) begin
cnt_1clk <= 12'd0;
clk_cnt <= 5'd0;
end else if (cnt_1clk == p_1bit_cnt) begin
cnt_1clk <= 12'd0;
if (clk_cnt == clk_end_cnt) clk_cnt <= 6'd0;
else clk_cnt <= clk_cnt + 6'd1;
end else begin
cnt_1clk <= cnt_1clk + 12'd1;
clk_cnt <= clk_cnt;
end
always @(posedge clk or negedge rstb)
if (rstb == 1'b0) sclk <= 1'b0;
else if (busy == 1'b0) sclk <= 1'b0;
else if (cnt_1clk == p_1bit_cnt) sclk <= 1'b0;
else if (cnt_1clk == {1'b0, p_1bit_cnt[11:1]}) sclk <= 1'b1;
else sclk <= sclk;
//ss
assign Nss0 = ~busy;
always @(posedge clk or negedge rstb)
if (rstb == 1'b0) mosi_data <= 64'b0;
else if (start_sig == 1'b1) mosi_data <= wr_data;
else if (cnt_1clk == p_mosi_chg) mosi_data <= {mosi_data[62:0], 1'b0};
else mosi_data <= mosi_data;
always @(posedge clk or negedge rstb)
if (rstb == 1'b0) mosi <= 1'b0;
else if (busy == 1'b1)
if (cnt_1clk == p_mosi_chg) mosi <= mosi_data[63];
else mosi <= mosi;
else mosi <= 1'b0;
always @(posedge clk or negedge rstb)
if (rstb == 1'b0) miso_data <= 64'd0;
else if (cnt_1clk == p_miso_trg) miso_data <= {miso_data[62:0], miso};
else miso_data <= miso_data;
always @(posedge clk or negedge rstb)
if (rstb == 1'b0) rd_data <= 64'd0;
else if ((cnt_1clk == p_1bit_cnt) && (clk_cnt == clk_end_cnt)) rd_data <= miso_data;
else rd_data <= rd_data;
always @(posedge clk or negedge rstb)
if (rstb == 1'b0) rd_data_en <= 1'b0;
else if ((cnt_1clk == p_1bit_cnt) && (clk_cnt == clk_end_cnt)) begin
rd_1byte <= miso_data[7:0];
rd_data_en <= 1'b1;
end else rd_data_en <= 1'b0;
endmodule
| 7.53911 |
module spikecnt_async (
spike,
int_cnt_out,
fast_clk,
slow_clk,
reset,
clear_out,
cnt,
sig1,
sig2,
read
);
input spike, slow_clk, fast_clk, reset;
output reg [31:0] int_cnt_out, cnt;
reg [31:0] acc_cnt_d1, acc_cnt_d0;
output clear_out;
output read;
output reg sig1, sig2;
reg t1, t2;
wire t = t1 ^ t2;
reg [31:0] status_counter;
always @(posedge reset or posedge slow_clk) begin
if (reset) t1 <= 0;
else t1 <= ~t2;
end
wire [31:0] temp_cnt = (acc_cnt_d0 - acc_cnt_d1);
always @(posedge reset or posedge t) begin
if (reset) begin
t2 <= 0;
acc_cnt_d0 <= 32'd0;
acc_cnt_d1 <= 32'd0;
int_cnt_out <= 32'd0;
end else begin
//int_cnt_out <= temp_cnt > 32'd128 ? int_cnt_out : temp_cnt;
int_cnt_out <= temp_cnt;
acc_cnt_d1 <= acc_cnt_d0;
acc_cnt_d0 <= cnt;
t2 <= t1;
end
end
always @(posedge reset or posedge spike) begin
if (reset) begin
cnt <= 32'd0;
end else begin
cnt <= t ? cnt : cnt + 32'd1;
//cnt <= cnt + 32'd1;
end
end
assign clear_out = t;
endmodule
| 7.55137 |
module spikecnt_async_old (
spike,
int_cnt_out,
fast_clk,
slow_clk,
reset,
clear_out,
cnt,
sig1,
sig2,
read
);
input spike, slow_clk, fast_clk, reset;
output reg [31:0] int_cnt_out, cnt;
output clear_out;
output read;
output reg sig1, sig2;
reg [31:0] status_counter;
always @(posedge reset or posedge fast_clk) begin
if (reset) begin
//t1 <= t2;
status_counter <= 0;
end else begin
if (slow_clk) begin
status_counter <= status_counter + 32'd1;
end else begin
status_counter <= 32'd0;
end
end
end
always @(posedge spike or posedge sig2) // for cleaning
begin
if (sig2) begin // cnt being read, lock the register
cnt <= 32'd0;
end else begin
if (~sig1) begin
cnt <= cnt + 32'd1;
end
// case ({sig1, sig2})
// 2'b10 : cnt <= cnt; // sig1 = being read, lock the data
// 2'b01 : cnt <= 32'd0; // sig2 = cnt ready for cleaning
// 2'b00 : cnt <= cnt + 32'd1; // ~sig1 && ~sig2 = normal spike counting
// default : cnt <= cnt; // ERROR, stop counting
// endcase
end
end
always @(posedge fast_clk or posedge reset) begin
if (reset) begin
sig1 <= 1'b0;
sig2 <= 1'b0;
end else begin
sig1 <= {(status_counter == 32'd1) || (status_counter == 32'd2)};
sig2 <= {(status_counter == 32'd3) || (status_counter == 32'd4)};
end
end
always @(posedge sig1 or posedge reset) begin
if (reset) begin
int_cnt_out <= 32'd0;
end else begin
int_cnt_out <= cnt;
end
end
endmodule
| 7.55137 |
module spikeout_gen (
input i_clk,
input i_rst_n,
input [1:0] i_spike_in,
input [3:0] i_spike,
output [3:0] o_spike
);
parameter p_delay = 4;
reg [$clog2(p_delay):0] r_counter;
reg r_event_on;
wire w_event_on;
wire w_reset_n;
wire w_en_spike;
assign w_event_on = i_spike_in[0] | i_spike_in[1];
assign w_en_spike = (r_counter >= 1) ? 1'b1 : 1'b0;
assign w_reset_n = (r_counter == p_delay || !i_rst_n) ? 1'b0 : 1'b1;
always @(posedge w_event_on or negedge w_reset_n) begin
if (!w_reset_n) r_event_on <= 1'b0;
else r_event_on <= 1'b1;
end
always @(posedge i_clk or negedge i_rst_n) begin
if (!i_rst_n) r_counter <= 0;
else if (r_counter < p_delay && r_event_on) r_counter <= r_counter + 1;
else r_counter <= 0;
end
spike_generator u1 (
.i_event(i_spike[0]),
.i_clk (i_clk),
.i_rst_n(w_en_spike),
.o_spike(o_spike[0])
);
spike_generator u2 (
.i_event(i_spike[1]),
.i_clk (i_clk),
.i_rst_n(w_en_spike),
.o_spike(o_spike[1])
);
spike_generator u3 (
.i_event(i_spike[2]),
.i_clk (i_clk),
.i_rst_n(w_en_spike),
.o_spike(o_spike[2])
);
spike_generator u4 (
.i_event(i_spike[3]),
.i_clk (i_clk),
.i_rst_n(w_en_spike),
.o_spike(o_spike[3])
);
endmodule
| 7.704602 |
module spike_generator (
input i_event,
input i_clk,
input i_rst_n,
output o_spike
);
wire w_q2, w_q1;
assign o_spike = w_q2;
flipflop u1 (
.i_d (1'b1),
.i_clk(i_event),
.i_clr(w_q2 | ~i_rst_n),
.o_q (w_q1),
.o_qb ()
);
flipflop u2 (
.i_d (w_q1),
.i_clk(i_clk),
.i_clr(~i_rst_n),
.o_q (w_q2),
.o_qb ()
);
endmodule
| 8.025153 |
module spill_register_497C2_3F032 (
clk_i,
rst_ni,
valid_i,
ready_o,
data_i,
valid_o,
ready_i,
data_o
);
parameter [31:0] T_SelectWidth = 0;
parameter [0:0] Bypass = 1'b0;
input wire clk_i;
input wire rst_ni;
input wire valid_i;
output wire ready_o;
input wire [T_SelectWidth - 1:0] data_i;
output wire valid_o;
input wire ready_i;
output wire [T_SelectWidth - 1:0] data_o;
spill_register_flushable_ECCE9_D4EC8 #(
.T_T_SelectWidth(T_SelectWidth),
.Bypass(Bypass)
) spill_register_flushable_i (
.clk_i (clk_i),
.rst_ni (rst_ni),
.valid_i(valid_i),
.flush_i(1'b0),
.ready_o(ready_o),
.data_i (data_i),
.valid_o(valid_o),
.ready_i(ready_i),
.data_o (data_o)
);
endmodule
| 7.215474 |
module spill_register_F2424 (
clk_i,
rst_ni,
valid_i,
ready_o,
data_i,
valid_o,
ready_i,
data_o
);
parameter [0:0] Bypass = 1'b0;
input wire clk_i;
input wire rst_ni;
input wire valid_i;
output wire ready_o;
input wire data_i;
output wire valid_o;
input wire ready_i;
output wire data_o;
spill_register_flushable_C4179 #(
.Bypass(Bypass)
) spill_register_flushable_i (
.clk_i (clk_i),
.rst_ni (rst_ni),
.valid_i(valid_i),
.flush_i(1'b0),
.ready_o(ready_o),
.data_i (data_i),
.valid_o(valid_o),
.ready_i(ready_i),
.data_o (data_o)
);
endmodule
| 7.215474 |
module spill_register_flushable_C4179 (
clk_i,
rst_ni,
valid_i,
flush_i,
ready_o,
data_i,
valid_o,
ready_i,
data_o
);
parameter [0:0] Bypass = 1'b0;
input wire clk_i;
input wire rst_ni;
input wire valid_i;
input wire flush_i;
output wire ready_o;
input wire data_i;
output wire valid_o;
input wire ready_i;
output wire data_o;
generate
if (Bypass) begin : gen_bypass
assign valid_o = valid_i;
assign ready_o = ready_i;
assign data_o = data_i;
end else begin : gen_spill_reg
reg a_data_q;
reg a_full_q;
wire a_fill;
wire a_drain;
always @(posedge clk_i or negedge rst_ni) begin : ps_a_data
if (!rst_ni) a_data_q <= 1'sb0;
else if (a_fill) a_data_q <= data_i;
end
always @(posedge clk_i or negedge rst_ni) begin : ps_a_full
if (!rst_ni) a_full_q <= 0;
else if (a_fill || a_drain) a_full_q <= a_fill;
end
reg b_data_q;
reg b_full_q;
wire b_fill;
wire b_drain;
always @(posedge clk_i or negedge rst_ni) begin : ps_b_data
if (!rst_ni) b_data_q <= 1'sb0;
else if (b_fill) b_data_q <= a_data_q;
end
always @(posedge clk_i or negedge rst_ni) begin : ps_b_full
if (!rst_ni) b_full_q <= 0;
else if (b_fill || b_drain) b_full_q <= b_fill;
end
assign a_fill = (valid_i && ready_o) && !flush_i;
assign a_drain = (a_full_q && !b_full_q) || flush_i;
assign b_fill = (a_drain && !ready_i) && !flush_i;
assign b_drain = (b_full_q && ready_i) || flush_i;
assign ready_o = !a_full_q || !b_full_q;
assign valid_o = a_full_q | b_full_q;
assign data_o = (b_full_q ? b_data_q : a_data_q);
end
endgenerate
endmodule
| 7.215474 |
module spill_register_flushable_ECCE9_D4EC8 (
clk_i,
rst_ni,
valid_i,
flush_i,
ready_o,
data_i,
valid_o,
ready_i,
data_o
);
parameter [31:0] T_T_SelectWidth = 0;
parameter [0:0] Bypass = 1'b0;
input wire clk_i;
input wire rst_ni;
input wire valid_i;
input wire flush_i;
output wire ready_o;
input wire [T_T_SelectWidth - 1:0] data_i;
output wire valid_o;
input wire ready_i;
output wire [T_T_SelectWidth - 1:0] data_o;
generate
if (Bypass) begin : gen_bypass
assign valid_o = valid_i;
assign ready_o = ready_i;
assign data_o = data_i;
end else begin : gen_spill_reg
reg [T_T_SelectWidth - 1:0] a_data_q;
reg a_full_q;
wire a_fill;
wire a_drain;
always @(posedge clk_i or negedge rst_ni) begin : ps_a_data
if (!rst_ni) a_data_q <= 1'sb0;
else if (a_fill) a_data_q <= data_i;
end
always @(posedge clk_i or negedge rst_ni) begin : ps_a_full
if (!rst_ni) a_full_q <= 0;
else if (a_fill || a_drain) a_full_q <= a_fill;
end
reg [T_T_SelectWidth - 1:0] b_data_q;
reg b_full_q;
wire b_fill;
wire b_drain;
always @(posedge clk_i or negedge rst_ni) begin : ps_b_data
if (!rst_ni) b_data_q <= 1'sb0;
else if (b_fill) b_data_q <= a_data_q;
end
always @(posedge clk_i or negedge rst_ni) begin : ps_b_full
if (!rst_ni) b_full_q <= 0;
else if (b_fill || b_drain) b_full_q <= b_fill;
end
assign a_fill = (valid_i && ready_o) && !flush_i;
assign a_drain = (a_full_q && !b_full_q) || flush_i;
assign b_fill = (a_drain && !ready_i) && !flush_i;
assign b_drain = (b_full_q && ready_i) || flush_i;
assign ready_o = !a_full_q || !b_full_q;
assign valid_o = a_full_q | b_full_q;
assign data_o = (b_full_q ? b_data_q : a_data_q);
end
endgenerate
endmodule
| 7.215474 |
module consisting of SPIMinionAdapterComposite and Loopback modules.
For use with testing SPI communication
Author : Kyle Infantino
Date : Oct 31, 2022
*/
`ifndef SPI_V3_COMPONENTS_LOOPBACKCOMPOSITE_V
`define SPI_V3_COMPONENTS_LOOPBACKCOMPOSITE_V
`include "SPI_v3/components/LoopBackVRTL.v"
`include "SPI_v3/components/SPIMinionAdapterCompositeVRTL.v"
module SPI_v3_components_SPILoopBackCompositeVRTL
#(
parameter nbits = 32
)(
input logic clk,
input logic reset,
input logic cs,
input logic sclk,
input logic mosi,
output logic miso,
output logic minion_parity,
output logic adapter_parity
);
logic spi_send_val;
logic spi_send_rdy;
logic [nbits-3:0] spi_send_msg;
logic spi_recv_val;
logic spi_recv_rdy;
logic [nbits-3:0] spi_recv_msg;
SPI_v3_components_SPIMinionAdapterCompositeVRTL #(nbits, 1) spi (
.clk(clk),
.cs(cs),
.miso(miso),
.mosi(mosi),
.reset(reset),
.sclk(sclk),
.recv_msg(spi_send_msg),
.recv_rdy(spi_send_rdy),
.recv_val(spi_send_val),
.send_msg(spi_recv_msg),
.send_rdy(spi_recv_rdy),
.send_val(spi_recv_val),
.minion_parity(minion_parity),
.adapter_parity(adapter_parity)
);
SPI_v3_components_LoopBackVRTL #(nbits) loopback (
.clk(clk),
.reset(reset),
.recv_val(spi_recv_val),
.recv_rdy(spi_recv_rdy),
.recv_msg(spi_recv_msg),
.send_val(spi_send_val),
.send_rdy(spi_send_rdy),
.send_msg(spi_send_msg)
);
endmodule
| 8.294413 |
module spils (
input iocs, // select this module for I/O
input [2:0] ioaddr, // address (this module uses 4)
input [15:0] din, // parallel data input
input iowr, // input valid
output [15:0] dout, // parallel data output
input sdi, // serial data input
output sdo, // serial data output
output sck, // serial clock
output ss0n,
ss1n, // slave selects (active low)
input clk, // master clock
input rst // master reset
);
// internal signals
wire wrc, wra, wrd; // register select
reg a; // address
reg [7:0] t; // counter
reg clock; // serial clock
reg shift; // shift data
wire nz; // counter not zero
reg [7:0] rsr, tsr; // data I/O shift registers
reg ss; // slave select
wire data; // data input
reg [7:0] omux; // output multiplexer
// decode address
assign wrd = iocs & iowr & (ioaddr[1:0] == 2'b00); // write data
assign wra = iocs & iowr & (ioaddr[1:0] == 2'b01); // write address
assign wrc = iocs & iowr & (ioaddr[1] == 1'b1); // control chip select
// configuration registers
always @(posedge clk) begin
if (rst) a <= 0; // address register
else if (wra) a <= din[0];
end
// count down 255-0 and generate shift enable and clock signals
// the shift enable signal is valid every 32nd CLK period
// during this time 8 SCK cycles are generated
always @(posedge clk) begin
if (rst) t <= 0; // reset to 0
else if (wrd) t <= 8'd255; // set to all ones when data arrives and
else if (nz) t <= t - 1'b1; // decrement until 8 bits shifted in and out
shift <= (t[4:0] == 5'b00001); // shift when 5 LSBs low
clock <= nz & ~t[4]; // generate serial clock when bit 4 is 0
end
assign nz = |t; // counter not zero
// transmit shift register - shift on SCK negative-going edge
always @(posedge clk) begin
if (wrd) tsr <= din[7:0]; // load from port 0
else if (shift) tsr <= {tsr[6:0], 1'b0}; // shift out continuously
if (rst) ss <= 0; // reset SS when port 2, set SS when port 3
else if (wrc) ss <= ioaddr[0];
end
// receive shift register - shift on SCK negative-going edge
always @(posedge clk) begin
if (rst) rsr <= 0; // shift 8 bits in
else if (shift) rsr <= {rsr[6:0], data};
end
// connect to SPI bus
OBUF bufcs0n (
.I(~(ss & ~a)),
.O(ss0n)
); // active low slave select 0
OBUF bufcs1n (
.I(~(ss & a)),
.O(ss1n)
); // active low slave select 1
OBUF bufclk (
.I(clock),
.O(sck)
); // clock active in 2nd half bit cell
OBUF bufsdo (
.I(tsr[7]),
.O(sdo)
); // data output
IBUF bufsdi (
.I(sdi),
.O(data)
); // data input
// connect input port
assign dout = {nz | shift, 7'b0000000, rsr}; // zero upper byte to allow ORing into words
endmodule
| 7.435714 |
module sm_fifoRTL (
wrClk,
rdClk,
rstSyncToWrClk,
rstSyncToRdClk,
dataIn,
dataOut,
fifoWEn,
fifoREn,
fifoFull,
fifoEmpty,
forceEmptySyncToWrClk,
forceEmptySyncToRdClk,
numElementsInFifo
);
//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
parameter FIFO_WIDTH = 8;
parameter FIFO_DEPTH = 64;
parameter ADDR_WIDTH = 6;
// Two clock domains within this module
// These ports are within 'wrClk' domain
input wrClk;
input rstSyncToWrClk;
input [FIFO_WIDTH-1:0] dataIn;
input fifoWEn;
input forceEmptySyncToWrClk;
output fifoFull;
// These ports are within 'rdClk' domain
input rdClk;
input rstSyncToRdClk;
output [FIFO_WIDTH-1:0] dataOut;
input fifoREn;
input forceEmptySyncToRdClk;
output fifoEmpty;
output [15:0] numElementsInFifo; //note that this implies a max fifo depth of 65536
wire wrClk;
wire rdClk;
wire rstSyncToWrClk;
wire rstSyncToRdClk;
wire [FIFO_WIDTH-1:0] dataIn;
reg [FIFO_WIDTH-1:0] dataOut;
wire fifoWEn;
wire fifoREn;
reg fifoFull;
reg fifoEmpty;
wire forceEmpty;
reg [15:0] numElementsInFifo;
// local registers
reg [ADDR_WIDTH:0] bufferInIndex;
reg [ADDR_WIDTH:0] bufferInIndexSyncToRdClk;
reg [ADDR_WIDTH:0] bufferOutIndex;
reg [ADDR_WIDTH:0] bufferOutIndexSyncToWrClk;
reg [ADDR_WIDTH-1:0] bufferInIndexToMem;
reg [ADDR_WIDTH-1:0] bufferOutIndexToMem;
reg [ADDR_WIDTH:0] bufferCnt;
reg fifoREnDelayed;
wire [FIFO_WIDTH-1:0] dataFromMem;
always @(posedge wrClk) begin
bufferOutIndexSyncToWrClk <= bufferOutIndex;
if (rstSyncToWrClk == 1'b1 || forceEmptySyncToWrClk == 1'b1) begin
fifoFull <= 1'b0;
bufferInIndex <= 0;
end else begin
if (fifoWEn == 1'b1) begin
bufferInIndex <= bufferInIndex + 1'b1;
end
if ((bufferOutIndexSyncToWrClk[ADDR_WIDTH-1:0] == bufferInIndex[ADDR_WIDTH-1:0]) &&
(bufferOutIndexSyncToWrClk[ADDR_WIDTH] != bufferInIndex[ADDR_WIDTH]) )
fifoFull <= 1'b1;
else fifoFull <= 1'b0;
end
end
always @(bufferInIndexSyncToRdClk or bufferOutIndex)
bufferCnt <= bufferInIndexSyncToRdClk - bufferOutIndex;
always @(posedge rdClk) begin
numElementsInFifo <= {
{16 - ADDR_WIDTH - 1{1'b0}}, bufferCnt
}; //pad bufferCnt with leading zeroes
bufferInIndexSyncToRdClk <= bufferInIndex;
if (rstSyncToRdClk == 1'b1 || forceEmptySyncToRdClk == 1'b1) begin
fifoEmpty <= 1'b1;
bufferOutIndex <= 0;
fifoREnDelayed <= 1'b0;
end else begin
fifoREnDelayed <= fifoREn;
if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
dataOut <= dataFromMem;
bufferOutIndex <= bufferOutIndex + 1'b1;
end
if (bufferInIndexSyncToRdClk == bufferOutIndex) fifoEmpty <= 1'b1;
else fifoEmpty <= 1'b0;
end
end
always @(bufferInIndex or bufferOutIndex) begin
bufferInIndexToMem <= bufferInIndex[ADDR_WIDTH-1:0];
bufferOutIndexToMem <= bufferOutIndex[ADDR_WIDTH-1:0];
end
sm_dpMem_dc #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_sm_dpMem_dc (
.addrIn (bufferInIndexToMem),
.addrOut(bufferOutIndexToMem),
.wrClk (wrClk),
.rdClk (rdClk),
.dataIn (dataIn),
.writeEn(fifoWEn),
.readEn (fifoREn),
.dataOut(dataFromMem)
);
endmodule
| 7.980621 |
module sm_RxFifo (
busClk,
spiSysClk,
rstSyncToBusClk,
rstSyncToSpiClk,
fifoWEn,
fifoFull,
busAddress,
busWriteEn,
busStrobe_i,
busFifoSelect,
busDataIn,
busDataOut,
fifoDataIn
);
//FIFO_DEPTH = 2^ADDR_WIDTH
parameter FIFO_DEPTH = 64;
parameter ADDR_WIDTH = 6;
input busClk;
input spiSysClk;
input rstSyncToBusClk;
input rstSyncToSpiClk;
input fifoWEn;
output fifoFull;
input [2:0] busAddress;
input busWriteEn;
input busStrobe_i;
input busFifoSelect;
input [7:0] busDataIn;
output [7:0] busDataOut;
input [7:0] fifoDataIn;
wire busClk;
wire spiSysClk;
wire rstSyncToBusClk;
wire rstSyncToSpiClk;
wire fifoWEn;
wire fifoFull;
wire [2:0] busAddress;
wire busWriteEn;
wire busStrobe_i;
wire busFifoSelect;
wire [7:0] busDataIn;
wire [7:0] busDataOut;
wire [7:0] fifoDataIn;
//internal wires and regs
wire [7:0] dataFromFifoToBus;
wire fifoREn;
wire forceEmptySyncToBusClk;
wire forceEmptySyncToSpiClk;
wire [15:0] numElementsInFifo;
wire fifoEmpty; //not used
sm_fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_sm_fifo (
.wrClk(spiSysClk),
.rdClk(busClk),
.rstSyncToWrClk(rstSyncToSpiClk),
.rstSyncToRdClk(rstSyncToBusClk),
.dataIn(fifoDataIn),
.dataOut(dataFromFifoToBus),
.fifoWEn(fifoWEn),
.fifoREn(fifoREn),
.fifoFull(fifoFull),
.fifoEmpty(fifoEmpty),
.forceEmptySyncToWrClk(forceEmptySyncToSpiClk),
.forceEmptySyncToRdClk(forceEmptySyncToBusClk),
.numElementsInFifo(numElementsInFifo)
);
sm_RxfifoBI u_sm_RxfifoBI (
.address(busAddress),
.writeEn(busWriteEn),
.strobe_i(busStrobe_i),
.busClk(busClk),
.spiSysClk(spiSysClk),
.rstSyncToBusClk(rstSyncToBusClk),
.fifoSelect(busFifoSelect),
.fifoDataIn(dataFromFifoToBus),
.busDataIn(busDataIn),
.busDataOut(busDataOut),
.fifoREn(fifoREn),
.forceEmptySyncToBusClk(forceEmptySyncToBusClk),
.forceEmptySyncToSpiClk(forceEmptySyncToSpiClk),
.numElementsInFifo(numElementsInFifo)
);
endmodule
| 7.12044 |
module sm_TxFifo (
busClk,
spiSysClk,
rstSyncToBusClk,
rstSyncToSpiClk,
fifoREn,
fifoEmpty,
busAddress,
busWriteEn,
busStrobe_i,
busFifoSelect,
busDataIn,
busDataOut,
fifoDataOut
);
//FIFO_DEPTH = 2^ADDR_WIDTH
parameter FIFO_DEPTH = 64;
parameter ADDR_WIDTH = 6;
input busClk;
input spiSysClk;
input rstSyncToBusClk;
input rstSyncToSpiClk;
input fifoREn;
output fifoEmpty;
input [2:0] busAddress;
input busWriteEn;
input busStrobe_i;
input busFifoSelect;
input [7:0] busDataIn;
output [7:0] busDataOut;
output [7:0] fifoDataOut;
wire busClk;
wire spiSysClk;
wire rstSyncToBusClk;
wire rstSyncToSpiClk;
wire fifoREn;
wire fifoEmpty;
wire [2:0] busAddress;
wire busWriteEn;
wire busStrobe_i;
wire busFifoSelect;
wire [7:0] busDataIn;
wire [7:0] busDataOut;
wire [7:0] fifoDataOut;
//internal wires and regs
wire fifoWEn;
wire forceEmptySyncToSpiClk;
wire forceEmptySyncToBusClk;
wire [15:0] numElementsInFifo;
wire fifoFull;
sm_fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_sm_fifo (
.wrClk(busClk),
.rdClk(spiSysClk),
.rstSyncToWrClk(rstSyncToBusClk),
.rstSyncToRdClk(rstSyncToSpiClk),
.dataIn(busDataIn),
.dataOut(fifoDataOut),
.fifoWEn(fifoWEn),
.fifoREn(fifoREn),
.fifoFull(fifoFull),
.fifoEmpty(fifoEmpty),
.forceEmptySyncToWrClk(forceEmptySyncToBusClk),
.forceEmptySyncToRdClk(forceEmptySyncToSpiClk),
.numElementsInFifo(numElementsInFifo)
);
sm_TxfifoBI u_sm_TxfifoBI (
.address(busAddress),
.writeEn(busWriteEn),
.strobe_i(busStrobe_i),
.busClk(busClk),
.spiSysClk(spiSysClk),
.rstSyncToBusClk(rstSyncToBusClk),
.fifoSelect(busFifoSelect),
.busDataIn(busDataIn),
.busDataOut(busDataOut),
.fifoWEn(fifoWEn),
.forceEmptySyncToBusClk(forceEmptySyncToBusClk),
.forceEmptySyncToSpiClk(forceEmptySyncToSpiClk),
.numElementsInFifo(numElementsInFifo)
);
endmodule
| 7.082185 |
module spimemio_pack #(
parameter BASE_ADDR = 8'h00
) (
input clk,
resetn,
output flash_csb,
output flash_clk,
// Tristate Data IO pins
inout [3:0] flash_dz,
// PicoRV32 packed MEM Bus interface
input [68:0] mem_packed_fwd, //DEC > GPO
output [32:0] mem_packed_ret //DEC < GPO
);
localparam SPIMEM_CFG_REG = 24'hFFFFFC;
// --------------------------------------------------------------
// Unpack the MEM bus
// --------------------------------------------------------------
wire [31:0] mem_wdata;
wire [ 3:0] mem_wstrb;
wire mem_valid;
wire [31:0] mem_addr;
wire mem_ready_mem;
reg [31:0] mem_rdata = 0;
wire [31:0] mem_rdata_cfg;
wire [31:0] mem_rdata_mem;
reg mem_ready = 0;
reg mem_ready_ = 0;
wire ready_sum = mem_ready || mem_ready_;
munpack mu (
.clk (clk),
.mem_packed_fwd(mem_packed_fwd),
.mem_packed_ret(mem_packed_ret),
.mem_wdata (mem_wdata),
.mem_wstrb (mem_wstrb),
.mem_valid (mem_valid),
.mem_addr (mem_addr),
.mem_ready (mem_ready),
.mem_rdata (mem_rdata)
);
// split apart the address word
wire [7 : 0] mem_base_addr = mem_addr[31:24]; // Which peripheral (BASE_ADDR)
wire [ 23:0] mem_flash_addr = mem_addr[23:0]; // Which address on the flash chip
// Decode address bus and see when SPI memory or the config words get addressed
wire isFlashSelect = mem_valid && !ready_sum && mem_base_addr == BASE_ADDR;
wire isAddrCfg = mem_flash_addr == SPIMEM_CFG_REG;
wire [ 3:0] flash_di;
wire [ 3:0] flash_do;
wire [ 3:0] flash_doe;
spimemio mio (
.clk (clk),
.resetn (resetn),
.flash_csb (flash_csb),
.flash_clk (flash_clk),
.flash_io0_oe(flash_doe[0]),
.flash_io1_oe(flash_doe[1]),
.flash_io2_oe(flash_doe[2]),
.flash_io3_oe(flash_doe[3]),
.flash_io0_do(flash_do[0]),
.flash_io1_do(flash_do[1]),
.flash_io2_do(flash_do[2]),
.flash_io3_do(flash_do[3]),
.flash_io0_di(flash_di[0]),
.flash_io1_di(flash_di[1]),
.flash_io2_di(flash_di[2]),
.flash_io3_di(flash_di[3]),
.valid(isFlashSelect && !isAddrCfg),
.ready(mem_ready_mem),
.addr (mem_flash_addr),
.rdata(mem_rdata_mem),
.cfgreg_we((isFlashSelect && isAddrCfg) ? mem_wstrb : 4'h0),
.cfgreg_di(mem_wdata),
.cfgreg_do(mem_rdata_cfg)
);
// Wire it up to the flash_dz pins
generate
genvar i;
for (i = 0; i <= 3; i = i + 1) begin
assign flash_dz[i] = flash_doe[i] ? flash_do[i] : 1'bz;
end
endgenerate
assign flash_di = flash_dz;
always @(posedge clk) begin
mem_ready <= 0;
mem_rdata <= 0;
if (isFlashSelect) begin
if (isAddrCfg) begin
mem_rdata <= mem_rdata_cfg;
mem_ready <= 1;
end else begin
if (mem_ready_mem) begin
mem_rdata <= mem_rdata_mem;
mem_ready <= 1;
end
end
end
mem_ready_ <= mem_ready;
end
endmodule
| 7.178614 |
module spiMemory
(
input clk, // FPGA clock
input sclk_pin, // SPI clock
input cs_pin, // SPI chip select
output miso_pin, // SPI master in slave out
input mosi_pin, // SPI master out slave in
input fault_pin, // For fault injection testing
output [3:0] leds // LEDs for debugging
)
endmodule
| 6.624118 |
module combining the SPIMinion and SPIMinionAdapter
// Author : Kyle Infantino
// Date : Dec 7, 2021
`ifndef SPI_V3_COMPONENTS_MINION_ADAPTER_COMPOSITE_V
`define SPI_V3_COMPONENTS_MINION_ADAPTER_COMPOSITE_V
`include "SPI_v3/components/SPIMinionVRTL.v"
`include "SPI_v3/components/SPIMinionAdapterVRTL.v"
module SPI_v3_components_SPIMinionAdapterCompositeVRTL
#(
parameter nbits = 8,
parameter num_entries = 1
)
(
input logic clk,
input logic cs,
output logic miso,
input logic mosi,
input logic reset,
input logic sclk,
input logic [nbits-3:0] recv_msg,
output logic recv_rdy,
input logic recv_val,
output logic [nbits-3:0] send_msg,
input logic send_rdy,
output logic send_val,
output logic minion_parity,
output logic adapter_parity
);
logic pull_en;
logic pull_msg_val;
logic pull_msg_spc;
logic [nbits-3:0] pull_msg_data;
logic push_en;
logic push_msg_val_wrt;
logic push_msg_val_rd;
logic [nbits-3:0] push_msg_data;
logic [nbits-1:0] pull_msg;
logic [nbits-1:0] push_msg;
SPI_v3_components_SPIMinionAdapterVRTL #(nbits,num_entries) adapter
(
.clk( clk ),
.reset( reset ),
.pull_en( pull_en ),
.pull_msg_val( pull_msg_val ),
.pull_msg_spc(pull_msg_spc),
.pull_msg_data(pull_msg_data),
.push_en( push_en ),
.push_msg_val_wrt( push_msg_val_wrt ),
.push_msg_val_rd( push_msg_val_rd ),
.push_msg_data( push_msg_data ),
.recv_msg( recv_msg ),
.recv_rdy( recv_rdy ),
.recv_val( recv_val ),
.send_msg( send_msg ),
.send_rdy( send_rdy ),
.send_val( send_val ),
.parity( adapter_parity )
);
SPI_v3_components_SPIMinionVRTL #(nbits) minion
(
.clk( clk ),
.cs( cs ),
.miso( miso ),
.mosi( mosi ),
.reset( reset ),
.sclk( sclk ),
.pull_en( pull_en ),
.pull_msg( pull_msg ),
.push_en( push_en ),
.push_msg( push_msg ),
.parity( minion_parity )
);
assign pull_msg[nbits-1] = pull_msg_val;
assign pull_msg[nbits-2] = pull_msg_spc;
assign pull_msg[nbits-3:0] = pull_msg_data;
assign push_msg_val_wrt = push_msg[nbits-1];
assign push_msg_val_rd = push_msg[nbits-2];
assign push_msg_data = push_msg[nbits-3:0];
endmodule
| 9.386012 |
module SPI_v3_components_SPIMinionAdapterVRTL #(
parameter nbits = 8,
parameter num_entries = 1
) (
input logic clk,
input logic reset,
input logic pull_en,
output logic pull_msg_val,
output logic pull_msg_spc,
output logic [nbits-3:0] pull_msg_data,
input logic push_en,
input logic push_msg_val_wrt,
input logic push_msg_val_rd,
input logic [nbits-3:0] push_msg_data,
input logic [nbits-3:0] recv_msg,
output logic recv_rdy,
input logic recv_val,
output logic [nbits-3:0] send_msg,
input logic send_rdy,
output logic send_val,
output logic parity
);
logic open_entries;
logic [nbits-3:0] cm_q_send_msg;
logic cm_q_send_rdy;
logic cm_q_send_val;
vc_Queue #(4'b0, nbits - 2, num_entries) cm_q (
.clk(clk),
.num_free_entries(),
.reset(reset),
.recv_msg(recv_msg),
.recv_rdy(recv_rdy),
.recv_val(recv_val),
.send_msg(cm_q_send_msg),
.send_rdy(cm_q_send_rdy),
.send_val(cm_q_send_val)
);
logic [$clog2(num_entries):0] mc_q_num_free;
logic mc_q_recv_rdy;
logic mc_q_recv_val;
vc_Queue #(4'b0, nbits - 2, num_entries) mc_q (
.clk(clk),
.num_free_entries(mc_q_num_free),
.reset(reset),
.recv_msg(push_msg_data),
.recv_rdy(mc_q_recv_rdy),
.recv_val(mc_q_recv_val),
.send_msg(send_msg),
.send_rdy(send_rdy),
.send_val(send_val)
);
assign parity = (^send_msg) & send_val;
always_comb begin : comb_block
open_entries = mc_q_num_free > 1;
mc_q_recv_val = push_msg_val_wrt & push_en;
pull_msg_spc = mc_q_recv_rdy & ((~mc_q_recv_val) | open_entries);
cm_q_send_rdy = push_msg_val_rd & pull_en;
pull_msg_val = cm_q_send_rdy & cm_q_send_val;
pull_msg_data = cm_q_send_msg & {(nbits - 2) {pull_msg_val}};
end
endmodule
| 7.522988 |
module top (
input clk,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5,
output RS232_Tx,
input RS232_Rx
);
reg [15:0] count = 0;
reg [ 7:0] ctimer = 0;
reg [ 3:0] laresetct = 0;
wire lareset;
assign lareset = (laresetct == 4'b0000 || laresetct == 4'b1111);
// logic analyzer
// Since the state machine can only change when count==0, using the clock qualifer
// lets us skip so many repeating values
top_of_verifla verifla (
.clk(clk),
.cqual(1'b1),
.rst_l(lareset),
.sys_run(1'b0),
.data_in({ctimer, 6'b0, state}),
.uart_XMIT_dataH(RS232_Tx),
.uart_REC_dataH(RS232_Rx)
);
// generate POR reset for logic analyzer
always @(posedge clk) if (laresetct != 4'b1111) laresetct <= laresetct + 4'b0001;
/*
Simple state machine
CW - n=n+1, led-on ctimer=250, >CWAIT
CWAIT - wait for timer, if n==3 >CCW else >CW
CCW - n=n-1, led-on ctimer=250, CCWAIT
CCWAIT - wait for timer, if n==0 >CW else CCW
*/
// dense encoding
localparam CW = 2'b00;
localparam CWAIT = 2'b01;
localparam CCW = 2'b10;
localparam CCWAIT = 2'b11;
reg [1:0] state = CW;
reg [3:0] leds = 1;
reg blink = 0;
assign LED1 = leds[0];
assign LED2 = leds[1];
assign LED3 = leds[2];
assign LED4 = leds[3];
assign LED5 = blink;
always @(posedge clk) begin
count <= count + 1;
if (ctimer != 0 && count == 0) ctimer <= ctimer - 1;
case (state)
CW: begin
leds = {leds[2:0], 1'b0};
ctimer <= 250;
blink <= ~blink;
state <= CWAIT;
end
CWAIT: begin
if (ctimer == 0) begin
state <= leds[3] ? CCW : CW;
end
end
CCW: begin
leds = {1'b0, leds[3:1]};
blink <= ~blink;
ctimer <= 250;
state = CCWAIT;
end
CCWAIT: begin
if (ctimer == 0) begin
state <= leds[0] ? CW : CCW;
end
end
default: begin
state <= CW; // never gets here we hope
end
endcase // case (state)
end
endmodule
| 7.233807 |
module spindle_bag1 (
gamma_dyn,
lce,
clk,
reset,
out0,
out1,
out2,
out3
);
input [31:0] gamma_dyn;
input [31:0] lce;
input clk;
input reset;
output wire [31:0] out0;
output wire [31:0] out1;
output wire [31:0] out2;
output wire [31:0] out3;
// *** Declarations
reg [31:0] Ia_fiber;
wire [31:0] IEEE_100000;
assign IEEE_100000 = 32'h47C3_5000;
//model derivatives
wire [31:0] dx_0;
wire [31:0] dx_1;
wire [31:0] dx_2;
wire [31:0] x_0_F0;
wire [31:0] x_1_F0;
wire [31:0] x_2_F0;
//State variables
reg [31:0] x_0;
reg [31:0] x_1;
reg [31:0] x_2;
// *** Output layouts
assign out0 = x_0;
assign out1 = x_1;
assign out2 = x_2;
assign out3 = Ia_fiber;
// *** BEGIN COMBINATIONAL LOGICS
//Ia fiber pps calculation
wire [31:0] LSR0_0;
assign LSR0_0 = 32'h3D23D70A;
wire [31:0] GI_0;
assign GI_0 = 32'h469C4000;
wire [31:0] Ia_fiber_RR2, Ia_fiber_R1, Ia_fiber_F0;
add Ia_fiber_a1 (
.x (x_1_F0),
.y (LSR0_0),
.out(Ia_fiber_RR2)
);
sub Ia_fiber_s1 (
.x (lce),
.y (Ia_fiber_RR2),
.out(Ia_fiber_R1)
);
mult Ia_fiber_m1 (
.x (GI_0),
.y (Ia_fiber_R1),
.out(Ia_fiber_F0)
);
//
//assign Ia_fiber = Ia_fiber_F0;
wire [31:0] Ia_max_flag;
sub Ia_fiber_max (
.x (IEEE_100000),
.y (Ia_fiber_F0),
.out(Ia_max_flag)
);
//loeb spindle bag1 derivatives
spindle_bag1_derivatives dev_for_bag1 (
.gamma_dyn(gamma_dyn),
.lce(lce),
.x_0(x_0),
.x_1(x_1),
.x_2(x_2),
.dx_0(dx_0),
.dx_1(dx_1),
.dx_2(dx_2)
);
//integrate state variables (euler integration)
integrator x_0_integrator (
.x(dx_0),
.int_x(x_0),
.out(x_0_F0)
);
integrator x_1_integrator (
.x(dx_1),
.int_x(x_1),
.out(x_1_F0)
);
integrator x_2_integrator (
.x(dx_2),
.int_x(x_2),
.out(x_2_F0)
);
//BEGIN SEQUENTIAL LOGICS
always @(posedge clk or posedge reset) begin
if (reset) begin
Ia_fiber <= 32'h0000_0000;
x_0 <= 32'h0000_0000;
x_1 <= 32'h3F75_38EF; //0.9579
x_2 <= 32'h0000_0000;
end else begin
x_0 <= x_0_F0;
x_1 <= x_1_F0;
x_2 <= x_2_F0;
if (Ia_fiber_F0[31]) begin // if Ia_fr < 0 pps
Ia_fiber <= 32'h0000_0000;
//Ia_fiber <= x_0_F0;
end else begin // if Ia_fr > 0
if (Ia_max_flag[31]) begin // if Ia_fr > 10000 pps
Ia_fiber <= IEEE_100000;
//Ia_fiber <= x_0_F0;
end else begin // Ia_fr fine
Ia_fiber <= Ia_fiber_F0;
//Ia_fiber <= x_0_F0;
end
end
end
end
endmodule
| 7.230676 |
module spindle_bag2_derivatives (
input [31:0] gamma_dyn,
input [31:0] lce,
input [31:0] x_0,
input [31:0] x_1,
input [31:0] x_2,
output [31:0] dx_0,
output [31:0] dx_1,
output [31:0] dx_2
);
//Min Gamma Dynamic Calculation
//
//From spindle.py
// mingd = gammaDyn**2/(gammaDyn**2+60**2)
//
wire [31:0] mingd;
wire [31:0] gamma_dyn_sqr;
wire [31:0] gamma_dyn_R1;
wire [31:0] IEEE_3600, IEEE_0_01;
assign IEEE_3600 = 32'h4561_0000;
assign IEEE_0_01 = 32'h3C23D70A;
mult min_gamma_dyn_m1 (
.x (gamma_dyn),
.y (gamma_dyn),
.out(gamma_dyn_sqr)
);
add min_gamma_dyn_a1 (
.x (gamma_dyn_sqr),
.y (IEEE_3600),
.out(gamma_dyn_R1)
);
div min_gamma_dyn_d1 (
.x (gamma_dyn_sqr),
.y (gamma_dyn_R1),
.out(mingd)
);
//assign mingd = 32'h3F23_D70A;
//dx_0 calculation
//
//From spindle.py
// dx_0 = (mingd-x_0)/0.149
//
wire [31:0] dx_0_R1, IEEE_ZERO_POINT_ONE_FOUR_NINE, IEEE_ZERO_POINT_TWO_ZERO_FIVE;
assign IEEE_ZERO_POINT_ONE_FOUR_NINE = 32'h3E18_9375;
assign IEEE_ZERO_POINT_TWO_ZERO_FIVE = 32'h3E51_EB85;
sub dx_0_s1 (
.x (mingd),
.y (x_0),
.out(dx_0_R1)
);
div dx_0_d1 (
.x (dx_0_R1),
.y (IEEE_ZERO_POINT_TWO_ZERO_FIVE),
.out(dx_0)
);
//dx_1 calculation
//
//From spindle.py
// dx_1 = x_2
//
assign dx_1 = x_2;
//CSS calculation
//
//From spindle.py
//if (-1000.0*x_2 > 100.0):
// CSS = -1.0
//elif (-1000.0*x_2 < -100.0):
// CSS = 1.0
//else:
// CSS = (2.0 / (1.0 + exp(-1000.0*x_2) ) ) - 1.0
//
//approximating this to copysign(1.0, x_2)
wire [31:0] CSS;
assign CSS[30:0] = 31'h3F80_0000;
assign CSS[31] = x_2[31];
//dx_2 calculation
//
//From spindle.py
//dx_2 = (1/MASS) * (KSR*lce - (KSR+KPR)*x_1 - CSS*(BDAMP*x_0)*(abs(x_2)**0.25) - 0.4)
//
wire [31:0] C_REV_M, C_KSR, C_KSR_P_KPR, C_KPR_M_LSR0, C_KSR_M_LSR0;
wire [31:0] abs_x2_pow_25, abs_x2_pow_25_unchk;
wire [31:0] BDAMP;
wire [31:0] dx_2_RRRRR5, dx_2_RRRRLR6, dx_2_RRRRL5, dx_2_RRRR4;
wire [31:0] dx_2_RRRLRR6, dx_2_RRRLRLR7, dx_2_RRRLRL6, dx_2_RRRLR5;
wire [31:0] dx_2_RRRL4, dx_2_RRR3, dx_2_RRL3, dx_2_RR2, dx_2_RL2;
wire [31:0] dx_2_R1, dx_2_F0;
wire [31:0] IEEE_ZERO_POINT_FOUR;
wire [31:0] dx_2_RRLL4;
assign IEEE_ZERO_POINT_FOUR = 32'h3ECCCCCC; // 0.4
//assign BDAMP = 32'h3E71_4120;//BDAMP = 0.2356
assign BDAMP = 32'h3D14_4674; //BDAMP = 0.0362
assign C_REV_M = 32'h459C4000; //1/M[j] = 1 / 0.0002 = 5000
assign C_KSR = 32'h4127703B; //KSR=10.4649
assign C_KSR_P_KPR = 32'h412A0903; //KSR[j]+KPR[j] = 10.4649 + 0.1623 = 10.6272
assign C_KSR_M_LSR0 = 32'h3ED652BD; //KSR[j]*LSR0[j] = 10.4649*0.04 = 0.4186
assign C_KPR_M_LSR0 = 32'h3DAF6944; //KPR[j]*LPR0[j] = 0.1127*0.76= 0.08565
wire [31:0] flag_abs_x2_pow_25;
pow_25 dx_2_p1 (
.x ({1'b0, x_2[30:0]}),
.out(abs_x2_pow_25)
);
wire [31:0] css_bdamp;
assign css_bdamp = {x_2[31], BDAMP[30:0]};
mult dx_2_RRRLRL6_mult (
.x (css_bdamp),
.y (x_0),
.out(dx_2_RRRLRL6)
);
mult dx_2_RRRLR5_mult (
.x (dx_2_RRRLRL6),
.y (abs_x2_pow_25),
.out(dx_2_RRRL4)
);
add dx_2_RRR3_add (
.x (dx_2_RRRL4),
.y (IEEE_ZERO_POINT_FOUR),
.out(dx_2_RRR3)
);
mult dx_2_RRL3_mult (
.x (C_KSR_P_KPR),
.y (x_1),
.out(dx_2_RRL3)
);
// - dx_2_RRL3 @@@@ dx_2_RRR3 => dx_2_RR2
add dx_2_RR2_add (
.x (dx_2_RRL3),
.y (dx_2_RRR3),
.out(dx_2_RR2)
);
// * KSR_0 @@@@ LCE_0 => dx_2_RL2
mult dx_2_RL2_mult (
.x (C_KSR),
.y (lce),
.out(dx_2_RL2)
);
// - dx_2_RL2 @@@@ dx_2_RR2 => dx_2_R1
sub dx_2_R1_sub (
.x (dx_2_RL2),
.y (dx_2_RR2),
.out(dx_2_R1)
);
// * C_REV_M @@@@ dx_2_R1 => dx_2
mult dx_2_F0_mult (
.x (C_REV_M),
.y (dx_2_R1),
.out(dx_2)
);
endmodule
| 6.860421 |
module spindle_neuron (
input [31:0] pps,
input clk,
input reset,
output reg spike
);
reg [10:0] isi_count; //Inter spike interval count
reg [10:0] spike_count; //spike count over 1 second
reg [1023:0] spike_history;
wire [31:0] floored_pps;
wire [10:0] int_pps;
wire [10:0] isi; //inter spike interval based on pps firing rate
wire [10:0] isi_final; //inter spike interval taking into account fractional isi
wire generate_spike; //command to spike on this clock cycle
floor floor1 (
.in (pps),
.out(floored_pps)
);
assign int_pps = floored_pps[10:0];
pps_to_isi pi_convertor (
.pps(int_pps),
.isi(isi)
);
assign isi_final = (spike_count > int_pps) ? (isi+1) : (isi); //if over-firing, delay spike 1 cycle
assign generate_spike = (isi_count >= isi_final) ? 1'b1 : 1'b0;
always @(posedge clk) begin
// this section if generate_spike == 0
isi_count <= isi_count + 1;
spike <= generate_spike;
spike_history <= {spike_history[1022:0], generate_spike};
spike_count <= spike_count - spike_history[1023] + generate_spike;
if (reset) begin
//this section on reset
isi_count <= 1;
spike_history <= 1023'd0;
spike <= 0;
spike_count <= 0;
end else if (generate_spike) begin
//this section if generate_spike == 1
isi_count <= 1;
spike_history <= {spike_history[1022:0], generate_spike};
spike <= generate_spike;
spike_count <= spike_count - spike_history[1023] + generate_spike;
end
end
endmodule
| 7.183239 |
module spinet6 (
input clk,
input rst,
input [37:0] io_in,
output [37:0] io_out
);
spinet #(
.N(6)
) SPINET (
.clk (clk),
.rst (rst),
.MOSI ({io_in[0], io_in[8], io_in[14], io_in[20], io_in[26], io_in[32]}),
.SCLK ({io_in[1], io_in[9], io_in[15], io_in[21], io_in[27], io_in[33]}),
.SS ({io_in[2], io_in[10], io_in[16], io_in[22], io_in[28], io_in[34]}),
.MISO ({io_out[3], io_out[11], io_out[17], io_out[23], io_out[29], io_out[35]}),
.txready({io_out[4], io_out[12], io_out[18], io_out[24], io_out[30], io_out[36]}),
.rxready({io_out[7], io_out[13], io_out[19], io_out[25], io_out[31], io_out[37]})
);
endmodule
| 7.475178 |
module spinet5 (
input clk,
input rst,
input [37:0] io_in,
output [37:0] io_out
);
spinet #(
.N(5)
) SPINET (
.clk (clk),
.rst (rst),
.MOSI ({io_in[8], io_in[14], io_in[20], io_in[26], io_in[32]}),
.SCLK ({io_in[9], io_in[15], io_in[21], io_in[27], io_in[33]}),
.SS ({io_in[10], io_in[16], io_in[22], io_in[28], io_in[34]}),
.MISO ({io_out[11], io_out[17], io_out[23], io_out[29], io_out[35]}),
.txready({io_out[12], io_out[18], io_out[24], io_out[30], io_out[36]}),
.rxready({io_out[13], io_out[19], io_out[25], io_out[31], io_out[37]})
);
endmodule
| 7.299742 |
module spinet #(
parameter N = 8,
WIDTH = 16,
ABITS = 3
) (
input clk,
input rst,
output [N-1:0] txready,
output [N-1:0] rxready,
input [N-1:0] MOSI,
SCLK,
SS,
output [N-1:0] MISO
);
wire [WIDTH-1:0] r[N-1:0];
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin
spinode #(
.WIDTH (WIDTH),
.ABITS (ABITS),
.ADDRESS(i)
) NODE (
.clk(clk),
.rst(rst),
.fromring(r[(i+N-1)%N]),
.toring(r[i]),
.txready(txready[i]),
.rxready(rxready[i]),
.MOSI(MOSI[i]),
.SCLK(SCLK[i]),
.SS(SS[i]),
.MISO(MISO[i])
);
end
endgenerate
endmodule
| 8.061406 |
module spinode #(
parameter WIDTH = 16,
ABITS = 3,
ADDRESS = 0
) (
input clk,
input rst,
input [WIDTH-1:0] fromring,
output [WIDTH-1:0] toring,
output txready,
rxready,
input SCLK,
SS,
MOSI,
output MISO
);
wire [WIDTH-1:0] txdata, rxdata;
wire mosivalid, mosiack, misovalid, misoack;
ringnode #(
.WIDTH (WIDTH),
.ABITS (ABITS),
.ADDRESS(ADDRESS)
) NODE (
.clk(clk),
.rst(rst),
.fromring(fromring),
.toring(toring),
.fromclient(rxdata),
.toclient(txdata),
.txready(txready),
.rxready(rxready),
.misovalid(misovalid),
.misoack(misoack),
.mosivalid(mosivalid),
.mosiack(mosiack)
);
ringspi #(
.WIDTH(WIDTH)
) SPI (
.rst(rst),
.txdata(txdata),
.rxdata(rxdata),
.misovalid(misovalid),
.misoack(misoack),
.mosivalid(mosivalid),
.mosiack(mosiack),
.MOSI(MOSI),
.SCLK(SCLK),
.SS(SS),
.MISO(MISO)
);
endmodule
| 7.786073 |
module ringnode #(
parameter WIDTH = 16,
ABITS = 3,
ADDRESS = 0
) (
input clk,
input rst,
input [WIDTH-1:0] fromring,
output [WIDTH-1:0] toring,
input [WIDTH-1:0] fromclient,
output [WIDTH-1:0] toclient,
output txready,
rxready,
input mosivalid,
misoack,
output reg mosiack,
misovalid
);
wire [ABITS-1:0] address = ADDRESS;
reg [1:0] mosivalid_sync, misoack_sync;
always @(posedge clk or posedge rst)
if (rst) begin
mosivalid_sync <= 0;
misoack_sync <= 0;
end else begin
mosivalid_sync <= {mosivalid_sync[0], mosivalid};
misoack_sync <= {misoack_sync[0], misoack};
end
localparam
FULL = WIDTH-1, ACK = WIDTH-2,
DST = (WIDTH-2) - ABITS, SRC = (WIDTH-2) - 2*ABITS;
reg [WIDTH-1:0] rxbuf, txbuf, ringbuf;
reg busy;
assign toring = ringbuf;
assign toclient = rxbuf;
assign rxready = rxbuf[FULL];
assign txready = ~txbuf[FULL];
reg xmit, recv, seize;
reg [WIDTH-1:0] outpkt;
always @(*) begin
outpkt = fromring;
xmit = 0;
recv = 0;
seize = 0;
case (fromring[FULL:ACK])
2'b00: // free slot - transmit if ready
if (txbuf[FULL] & ~busy) begin
outpkt = txbuf;
outpkt[SRC+:ABITS] = address;
outpkt[FULL] = 1;
seize = 1;
end
2'b10, 2'b11: // payload - return ack to sender
if (fromring[DST+:ABITS] == address && !rxbuf[FULL]) begin
outpkt[FULL:ACK] = 2'b01;
recv = 1;
end
2'b01: // ack
if (fromring[SRC+:ABITS] == address) begin
outpkt[ACK] = 0;
xmit = 1;
end
endcase
end
always @(posedge clk or posedge rst)
if (rst) begin
ringbuf <= 0;
rxbuf <= 0;
txbuf <= 0;
busy <= 0;
mosiack <= 0;
misovalid <= 0;
end else begin
ringbuf <= outpkt;
if (recv) begin
rxbuf <= fromring;
misovalid <= ~misovalid;
end else if (misoack_sync[1] == misovalid) rxbuf[FULL] <= 0;
if (mosivalid_sync[1] != mosiack) begin
txbuf <= fromclient;
mosiack <= ~mosiack;
end else if (xmit) txbuf[FULL] <= 0;
if (seize) busy <= 1;
else if (xmit) busy <= 0;
end
endmodule
| 7.618976 |
module ringspi #(
parameter WIDTH = 16
) (
input rst,
input SCLK,
SS,
MOSI,
output MISO,
input misovalid,
output reg misoack,
output reg mosivalid,
input mosiack,
output [WIDTH-1:0] rxdata,
input [WIDTH-1:0] txdata
);
localparam LOGWIDTH = $clog2(WIDTH);
reg [WIDTH:0] shiftreg;
assign MISO = shiftreg[WIDTH];
reg [LOGWIDTH-1:0] bitcount;
reg [WIDTH-1:0] inbuf;
assign rxdata = inbuf;
// capture incoming data on falling clock edge
always @(negedge SCLK or posedge SS)
if (SS) begin
bitcount <= 0;
shiftreg[0] <= 0;
end else begin
if (bitcount != WIDTH - 1) begin
bitcount <= bitcount + 1;
shiftreg[0] <= MOSI;
end else begin
bitcount <= 0;
if (mosiack == mosivalid) begin
inbuf <= {shiftreg[WIDTH-1:1], MOSI};
end
end
end
// set up next outgoing data on rising clock edge
always @(posedge SCLK or posedge SS)
if (SS) begin
shiftreg[WIDTH:1] <= 0;
end else begin
if (bitcount == 0) begin
if (misovalid != misoack) begin
shiftreg[WIDTH:1] <= txdata;
end else shiftreg[WIDTH:1] <= 0;
end else shiftreg[WIDTH:1] <= shiftreg[WIDTH-1:0];
end
// handshake with node
always @(negedge SCLK or posedge rst)
if (rst) begin
mosivalid <= 0;
end else begin
if (bitcount == WIDTH - 1 && mosiack == mosivalid) mosivalid <= ~mosivalid;
end
always @(posedge SCLK or posedge rst)
if (rst) begin
misoack <= 0;
end else begin
if (bitcount == 0 && misovalid != misoack) misoack <= ~misoack;
end
endmodule
| 8.302773 |
module spinnaker_fpgas_sync #(
parameter SIZE = 1
) (
input CLK_IN,
input [SIZE - 1:0] IN,
output reg [SIZE - 1:0] OUT
);
//---------------------------------------------------------------
// internal signals
//---------------------------------------------------------------
reg [SIZE - 1:0] sync;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//--------------------------- datapath --------------------------
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// flops
always @(posedge CLK_IN) begin
sync <= IN;
OUT <= sync;
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 7.944417 |
module spinner (
input wire sync_rot_a,
input wire sync_rot_b,
input wire clk,
output reg event_rot_l,
output reg event_rot_r
);
reg rotary_q1;
reg rotary_q2;
reg rotary_q1_dly;
reg rotary_q2_dly;
always @(posedge clk) begin : filter
case ({
sync_rot_b, sync_rot_a
})
0: rotary_q1 <= 1'b0;
1: rotary_q2 <= 1'b0;
2: rotary_q2 <= 1'b1;
3: rotary_q1 <= 1'b1;
endcase
rotary_q1_dly <= rotary_q1;
rotary_q2_dly <= rotary_q2;
event_rot_l <= rotary_q2_dly && !rotary_q1_dly && rotary_q1;
event_rot_r <= !rotary_q2_dly && !rotary_q1_dly && rotary_q1;
end
endmodule
| 6.771272 |
module spinner (
clock,
spin,
amount,
din,
dout
);
input clock;
input spin;
input [4:0] amount;
input [31:0] din;
output [31:0] dout;
reg [31:0] dout;
reg [31:0] inr;
reg spl;
wire [31:0] tmp0;
wire [31:0] tmp1;
wire [31:0] tmp2;
wire [31:0] tmp3;
wire [31:0] tmp4;
wire [31:0] tmp5;
initial begin
dout = 0;
inr = 0;
spl = 0;
end
assign tmp0 = inr;
assign tmp1[30:0] = amount[0] ? tmp0[31:1] : tmp0[30:0];
assign tmp1[31] = amount[0] ? tmp0[0] : tmp0[31];
assign tmp2[29:0] = amount[1] ? tmp1[31:2] : tmp1[29:0];
assign tmp2[31:30] = amount[1] ? tmp1[1:0] : tmp1[31:30];
assign tmp3[27:0] = amount[2] ? tmp2[31:4] : tmp2[27:0];
assign tmp3[31:28] = amount[2] ? tmp2[3:0] : tmp2[31:28];
assign tmp4[23:0] = amount[3] ? tmp3[31:8] : tmp3[23:0];
assign tmp4[31:24] = amount[3] ? tmp3[7:0] : tmp3[31:24];
assign tmp5[15:0] = amount[4] ? tmp4[31:16] : tmp4[15:0];
assign tmp5[31:16] = amount[4] ? tmp4[15:0] : tmp4[31:16];
always @(posedge clock) begin
if (spl) inr <= dout;
else inr <= din;
dout <= tmp5;
spl <= spin;
end // always @ (posedge clock)
//invariant: # FAIL:
//!(dout[31:0]=b10101010101010101010101010101010);
assert property (dout != 32'b10101010101010101010101010101010);
endmodule
| 6.771272 |
module spin_timer (
CLOCK,
reset,
start,
value,
pause,
active,
done
);
input CLOCK, reset, start, pause;
output active, done;
output [3:0] value; // provides the value1 (max 4 bits) of the
// current time on the timer – you’ll pass this on to a BCD decoder,
// and then to a 7-segment display if you want to see the timer count
reg active, done1;
reg [3:0] value1;
reg enabled;
integer clockedvalue1;
parameter defaultvalue1 = 7; // number of time units (seconds) this timer
// will run
parameter clockHZ = 50000000; // we assume you’ll use the 50MHz clock feed
// if not, you’ll adjust this accordingly
tri_state_buffer(
done1, done, active
); tri_state_bus_buffer(
value1, value, active
);
initial begin
value1 = defaultvalue1;
enabled = 0;
clockedvalue1 = 0;
done1 = 0;
active = 0;
end
always @(negedge CLOCK) begin
active = enabled & ~pause;
if (reset) begin
value1 = defaultvalue1;
enabled = 0;
clockedvalue1 = 0;
done1 = 0;
active = 0;
end
if (enabled & ~pause) clockedvalue1 = clockedvalue1 + 1;
if (clockedvalue1 > clockHZ) begin
value1 = value1 - 1;
clockedvalue1 = 0;
end
if (value1 == 0) begin
enabled = 0;
done1 = 1;
end
if (start & ~enabled & ~done1) begin
done1 = 0;
enabled = 1;
value1 = defaultvalue1;
end
end
endmodule
| 8.279232 |
module spio (
i_clk,
i_wb_cyc,
i_wb_stb,
i_wb_we,
i_wb_data,
i_wb_sel,
o_wb_ack,
o_wb_stall,
o_wb_data,
i_btn,
o_led,
o_int
);
parameter NLEDS = 8, NBTN = 8;
input wire i_clk;
input wire i_wb_cyc, i_wb_stb, i_wb_we;
input wire [31:0] i_wb_data;
input wire [3:0] i_wb_sel;
output reg o_wb_ack;
output wire o_wb_stall;
output wire [31:0] o_wb_data;
input wire [(NBTN-1):0] i_btn;
output reg [(NLEDS-1):0] o_led;
output reg o_int;
reg led_demo;
reg [(8-1):0] r_led;
initial r_led = 0;
initial led_demo = 1'b1;
always @(posedge i_clk) begin
if ((i_wb_stb) && (i_wb_we) && (i_wb_sel[0])) begin
if (!i_wb_sel[1]) r_led[NLEDS-1:0] <= i_wb_data[(NLEDS-1):0];
else
r_led[NLEDS-1:0] <= (r_led[NLEDS-1:0]&(~i_wb_data[(8+NLEDS-1):8]))
|(i_wb_data[(NLEDS-1):0]&i_wb_data[(8+NLEDS-1):8]);
end
end
wire [(8-1):0] o_btn;
generate
if (NBTN > 0)
debouncer #(NBTN) thedebouncer (
i_clk,
i_btn,
o_btn[(NBTN-1):0]
);
endgenerate
generate
if (NBTN < 8) assign o_btn[7:NBTN] = 0;
endgenerate
// 2FF synchronizer for our switches
reg [(8-1):0] r_sw;
always @(*) r_sw = 0;
always @(posedge i_clk) if ((i_wb_stb) && (i_wb_we) && (i_wb_sel[3])) led_demo <= i_wb_data[24];
assign o_wb_data = {7'h0, led_demo, r_sw, o_btn, r_led};
reg [(NBTN-1):0] last_btn;
always @(posedge i_clk) last_btn <= o_btn[(NBTN-1):0];
always @(posedge i_clk) o_int <= (|((o_btn[(NBTN-1):0]) & (~last_btn)));
always @(posedge i_clk) o_led <= r_led[NLEDS-1:0];
assign o_wb_stall = 1'b0;
always @(posedge i_clk) o_wb_ack <= (i_wb_stb);
// Make Verilator happy
// verilator lint_on UNUSED
wire [33:0] unused;
assign unused = {i_wb_cyc, i_wb_data, i_wb_sel[2]};
// verilator lint_off UNUSED
endmodule
| 6.985462 |
module
//
// -------------------------------------------------------------------------
// AUTHOR
// lap - luis.plana@manchester.ac.uk
// Based on work by J Pepper (Date 07/08/2012)
//
// -------------------------------------------------------------------------
// DETAILS
// Created on : 28 Nov 2012
// Version : $Revision: 2098 $
// Last modified on : $Date: 2013-01-19 11:38:48 +0000 (Sat, 19 Jan 2013) $
// Last modified by : $Author: plana $
// $HeadURL: https://solem.cs.man.ac.uk/svn/spiNNlink/testing/src/crc_gen.v $
//
// -------------------------------------------------------------------------
// COPYRIGHT
// Copyright (c) The University of Manchester, 2012-2016.
// SpiNNaker Project
// Advanced Processor Technologies Group
// School of Computer Science
// -------------------------------------------------------------------------
// TODO
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
// include spiNNlink global constants and parameters
//
`include "spio_hss_multiplexer_common.h"
// -------------------------------------------------------------------------
`timescale 1ns / 1ps
module spio_hss_multiplexer_crc_gen
(
input wire clk,
input wire rst,
// CRC data interface
input wire crc_go,
input wire crc_last,
input wire [31:0] crc_in,
output reg [31:0] crc_out
);
//---------------------------------------------------------------
// constants
//---------------------------------------------------------------
// NOTE: standard practice is to reset checksum to all 1s
localparam CHKSUM_RST = {16 {1'b1}};
//---------------------------------------------------------------
// internal variables
//---------------------------------------------------------------
reg [15:0] new_chksum;
reg [15:0] chksum;
//---------------------------------------------------------------
// functions
//---------------------------------------------------------------
`include "CRC16_D32.v" // function nextCRC16_D32 (Data, crc)
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//--------------------------- datapath --------------------------
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//---------------------------------------------------------------
// new checksum (combinatorial)
//---------------------------------------------------------------
always @(*)
//# new_chksum = nextCRC16_D32 (.Data (crc_in), .crc (chksum));
new_chksum = nextCRC16_D32 (crc_in, chksum);
//---------------------------------------------------------------
//---------------------------------------------------------------
// crc output (combinatorial)
//---------------------------------------------------------------
always @(*)
if (crc_last && crc_go)
// substitute crc in last flit of every frame
crc_out = {crc_in[31:16], new_chksum};
else
crc_out = crc_in;
//---------------------------------------------------------------
//---------------------------------------------------------------
// keep new checksum for next clock cycle
//---------------------------------------------------------------
always @(posedge clk or posedge rst)
if (rst)
chksum <= CHKSUM_RST;
else
if (crc_go)
if (crc_last)
chksum <= CHKSUM_RST;
else
chksum <= new_chksum;
//---------------------------------------------------------------
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 7.80459 |
module spio_hss_multiplexer_lfsr_tb;
// constants
// ----------------------------------
// internal signals
// ----------------------------------
// clock signals
reg tb_clk; // tb
reg uut_clk; // unit under test
// reset signals
reg tb_rst; // tb
reg uut_rst; // unit under test
// signals to drive the uut
reg uut_next;
wire [15:0] uut_data;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//---------------------- unit under test ------------------------
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
spio_hss_multiplexer_lfsr uut (
.clk(uut_clk),
.rst(uut_rst),
.next (uut_next),
.data_out(uut_data)
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//----------------------- drive the uut -------------------------
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge tb_clk or posedge tb_rst)
if (tb_rst) uut_next = 1'b0;
else uut_next = 1'b1;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//----------------- clocks, resets and counters -----------------
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//---------------------------------------------------------------
// generate clocks
//---------------------------------------------------------------
initial begin
tb_clk = 1'b0;
forever #6.66666667 tb_clk = ~tb_clk;
end
initial begin
uut_clk = 1'b0;
forever #6.66666667 uut_clk = ~uut_clk;
end
//---------------------------------------------------------------
//---------------------------------------------------------------
// generate resets
//---------------------------------------------------------------
initial begin
tb_rst = 1'b1;
#50 tb_rst = 1'b0;
end
initial begin
uut_rst = 1'b1;
#50 uut_rst = 1'b0;
end
//---------------------------------------------------------------
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 7.043246 |
module spio_link_speed_doubler_tb;
localparam PKT_BITS = 16;
genvar i;
reg sclk_i;
reg fclk_i;
reg reset_i;
// Input stream
reg [PKT_BITS-1:0] in_data_i;
reg in_vld_i;
wire in_rdy_i;
// Output stream
wire [PKT_BITS-1:0] out_data_i;
wire out_vld_i;
reg out_rdy_i;
////////////////////////////////////////////////////////////////////////////////
// Device under test
////////////////////////////////////////////////////////////////////////////////
spio_link_speed_doubler #(
.PKT_BITS(PKT_BITS)
) spio_link_speed_doubler_i (
.RESET_IN(reset_i)
, .SCLK_IN (sclk_i)
, .FCLK_IN (fclk_i)
, .DATA_IN (in_data_i)
, .VLD_IN (in_vld_i)
, .RDY_OUT (in_rdy_i)
, .DATA_OUT(out_data_i)
, .VLD_OUT (out_vld_i)
, .RDY_IN (out_rdy_i)
);
////////////////////////////////////////////////////////////////////////////////
// Input Stimulus
////////////////////////////////////////////////////////////////////////////////
initial begin
in_vld_i <= 1'b1;
out_rdy_i <= 1'b1;
@(negedge reset_i) @(posedge sclk_i) $display("Ensure full-throughput");
in_vld_i <= 1'b1;
out_rdy_i <= 1'b1;
#200 @(posedge sclk_i) $display("Ensure things stop cleanly");
in_vld_i <= 1'b0;
out_rdy_i <= 1'b1;
#200 @(posedge sclk_i) $display("Ensure things start-up cleanly again");
in_vld_i <= 1'b1;
out_rdy_i <= 1'b1;
#200 @(posedge sclk_i) $display("Ensure we can block the link");
in_vld_i <= 1'b1;
out_rdy_i <= 1'b0;
#200 @(posedge sclk_i) $display("...and resume");
in_vld_i <= 1'b1;
out_rdy_i <= 1'b1;
#200 @(posedge sclk_i) $display("Ensure we can block the link at the same time as the stream.");
@(posedge sclk_i) in_vld_i <= 1'b0;
out_rdy_i <= 1'b0;
#200 @(posedge sclk_i) $display("...and resume to a blocked link");
in_vld_i <= 1'b1;
out_rdy_i <= 1'b0;
#200 @(posedge sclk_i) $display("...and then recover when unblocked mid-sclk");
@(posedge fclk_i) in_vld_i <= 1'b1;
out_rdy_i <= 1'b1;
#200
@(posedge sclk_i)
// Job done!
$finish;
end
// Send packets with ascending values
reg [PKT_BITS-1:0] packets_sent_i;
always @(posedge sclk_i, posedge reset_i)
if (reset_i) begin
in_data_i <= 0;
packets_sent_i <= 1;
end else begin
if (in_vld_i && in_rdy_i) begin
in_data_i <= packets_sent_i;
packets_sent_i <= packets_sent_i + 1;
end
end
reg [PKT_BITS-1:0] next_arrival_i;
initial begin
next_arrival_i = 0;
end
// Print arriving output data
always @(posedge fclk_i)
if (out_vld_i && out_rdy_i) begin
$display("Time=%8d; %018x", $time, out_data_i);
if (out_data_i != next_arrival_i) $display("Time=%8d; %018x Missing!", $time, next_arrival_i);
next_arrival_i = out_data_i + 1;
end else $display("Time=%8d; Output Idle.", $time);
////////////////////////////////////////////////////////////////////////////////
// Testbench signals
////////////////////////////////////////////////////////////////////////////////
// Clock generation
initial begin
sclk_i = 1'b1;
forever #10 sclk_i = ~sclk_i;
end
initial begin
fclk_i = 1'b1;
forever #5 fclk_i = ~fclk_i;
end
// Reset generation
initial begin
reset_i <= 1'b1;
#100 reset_i <= 1'b0;
end
endmodule
| 7.052187 |
module spio_link_speed_halver_tb;
localparam PKT_BITS = 16;
genvar i;
reg sclk_i;
reg fclk_i;
reg reset_i;
// Input stream
reg [PKT_BITS-1:0] in_data_i;
reg in_vld_i;
wire in_rdy_i;
// Output stream
wire [PKT_BITS-1:0] out_data_i;
wire out_vld_i;
reg out_rdy_i;
////////////////////////////////////////////////////////////////////////////////
// Device under test
////////////////////////////////////////////////////////////////////////////////
spio_link_speed_halver #(
.PKT_BITS(PKT_BITS)
) spio_link_speed_halver_i (
.RESET_IN(reset_i)
, .SCLK_IN (sclk_i)
, .FCLK_IN (fclk_i)
, .DATA_IN (in_data_i)
, .VLD_IN (in_vld_i)
, .RDY_OUT (in_rdy_i)
, .DATA_OUT(out_data_i)
, .VLD_OUT (out_vld_i)
, .RDY_IN (out_rdy_i)
);
////////////////////////////////////////////////////////////////////////////////
// Input Stimulus
////////////////////////////////////////////////////////////////////////////////
initial begin
in_vld_i <= 1'b1;
out_rdy_i <= 1'b1;
@(negedge reset_i) @(posedge sclk_i) $display("Ensure full-throughput");
in_vld_i <= 1'b1;
out_rdy_i <= 1'b1;
#200 @(posedge sclk_i) $display("Ensure things stop cleanly");
in_vld_i <= 1'b0;
out_rdy_i <= 1'b1;
#200 @(posedge sclk_i) $display("Ensure things start-up cleanly again");
in_vld_i <= 1'b1;
out_rdy_i <= 1'b1;
#200 @(posedge sclk_i) $display("Ensure we can block the link");
in_vld_i <= 1'b1;
out_rdy_i <= 1'b0;
#200 @(posedge sclk_i) $display("...and resume");
in_vld_i <= 1'b1;
out_rdy_i <= 1'b1;
#200 @(posedge sclk_i) $display("Ensure we can block the link at the same time as the stream.");
@(posedge sclk_i) in_vld_i <= 1'b0;
out_rdy_i <= 1'b0;
#200 @(posedge sclk_i) $display("...and resume to a blocked link");
in_vld_i <= 1'b1;
out_rdy_i <= 1'b0;
#200 @(posedge sclk_i) $display("...and then recover when unblocked mid-sclk");
@(posedge sclk_i) in_vld_i <= 1'b1;
out_rdy_i <= 1'b1;
#200
@(posedge sclk_i)
// Job done!
$finish;
end
// Send packets with ascending values
reg [PKT_BITS-1:0] packets_sent_i;
always @(posedge fclk_i, posedge reset_i)
if (reset_i) begin
in_data_i <= 0;
packets_sent_i <= 1;
end else begin
if (in_vld_i && in_rdy_i) begin
in_data_i <= packets_sent_i;
packets_sent_i <= packets_sent_i + 1;
end
end
reg [PKT_BITS-1:0] next_arrival_i;
initial begin
next_arrival_i = 0;
end
// Print arriving output data
always @(posedge sclk_i)
if (out_vld_i && out_rdy_i) begin
$display("Time=%8d; %018x", $time, out_data_i);
if (out_data_i != next_arrival_i) $display("Time=%8d; %018x Missing!", $time, next_arrival_i);
next_arrival_i = out_data_i + 1;
end else $display("Time=%8d; Output Idle.", $time);
////////////////////////////////////////////////////////////////////////////////
// Testbench signals
////////////////////////////////////////////////////////////////////////////////
// Clock generation
initial begin
sclk_i = 1'b1;
forever #10 sclk_i = ~sclk_i;
end
initial begin
fclk_i = 1'b1;
forever #5 fclk_i = ~fclk_i;
end
// Reset generation
initial begin
reset_i <= 1'b1;
#100 reset_i <= 1'b0;
end
endmodule
| 7.052187 |
module
//
// -------------------------------------------------------------------------
// AUTHOR
// lap - luis.plana@manchester.ac.uk
//
// -------------------------------------------------------------------------
// DETAILS
// Created on : 28 Mar 2013
// Version : $Revision: 2517 $
// Last modified on : $Date: 2013-08-19 10:33:30 +0100 (Mon, 19 Aug 2013) $
// Last modified by : $Author: plana $
// $HeadURL: https://solem.cs.man.ac.uk/svn/spiNNlink/testing/src/pkt_ctr.v $
//
// -------------------------------------------------------------------------
// COPYRIGHT
// Copyright (c) The University of Manchester, 2012-2016.
// SpiNNaker Project
// Advanced Processor Technologies Group
// School of Computer Science
// -------------------------------------------------------------------------
// TODO
// -------------------------------------------------------------------------
// ----------------------------------------------------------------
// include spiNNlink global constants and parameters
//
`include "spio_packet_counter.h"
// ----------------------------------------------------------------
`timescale 1ns / 1ps
module spio_packet_counter
(
input wire CLK_IN,
input wire RESET_IN,
// packet interface
input wire [15:0] pkt_vld,
input wire [15:0] pkt_rdy,
// error interface
input wire [15:0] tp0_err,
input wire [15:0] tp1_err,
input wire [15:0] tp2_err,
// register access interface
input wire [`CTRA_BITS - 1:0] ctr_addr,
output reg [`CTRD_BITS - 1:0] ctr_data
);
//---------------------------------------------------------------
// internal signals
//---------------------------------------------------------------
reg [`CTRD_BITS - 1:0] pkt_ctr [15:0];
reg [`CTRD_BITS - 1:0] tp0_ctr [15:0];
reg [`CTRD_BITS - 1:0] tp1_ctr [15:0];
reg [`CTRD_BITS - 1:0] tp2_ctr [15:0];
//---------------------------------------------------------------
// packet and error counters
//---------------------------------------------------------------
genvar i;
generate for (i = 0; i < 16; i = i + 1)
begin : counters
always @ (posedge CLK_IN or posedge RESET_IN)
if (RESET_IN)
pkt_ctr[i] <= 1'b0;
else
if (pkt_vld[i] && pkt_rdy[i])
pkt_ctr[i] <= pkt_ctr[i] + 1;
always @ (posedge CLK_IN or posedge RESET_IN)
if (RESET_IN)
tp0_ctr[i] <= 1'b0;
else
if (tp0_err[i])
tp0_ctr[i] <= tp0_ctr[i] + 1;
always @ (posedge CLK_IN or posedge RESET_IN)
if (RESET_IN)
tp1_ctr[i] <= 1'b0;
else
if (tp1_err[i])
tp1_ctr[i] <= tp1_ctr[i] + 1;
always @ (posedge CLK_IN or posedge RESET_IN)
if (RESET_IN)
tp2_ctr[i] <= 1'b0;
else
if (tp2_err[i])
tp2_ctr[i] <= tp2_ctr[i] + 1;
end
endgenerate
//---------------------------------------------------------------
//---------------------------------------------------------------
// register output selection
//---------------------------------------------------------------
always @ (*)
case (ctr_addr[5:4])
`PKT_CNT_BITS: ctr_data = pkt_ctr[ctr_addr[3:0]];
`TP0_ERR_BITS: ctr_data = tp0_ctr[ctr_addr[3:0]];
`TP1_ERR_BITS: ctr_data = tp1_ctr[ctr_addr[3:0]];
`TP2_ERR_BITS: ctr_data = tp2_ctr[ctr_addr[3:0]];
default: ctr_data = {`CTRD_BITS {1'b1}};
endcase
//---------------------------------------------------------------
endmodule
| 7.80459 |
modules/spinnaker_link/spio_spinnaker_link.h"
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
`timescale 1ns / 1ps
module spio_spinn2aer_mapper
(
input wire rst,
input wire clk,
// SpiNNaker packet interface
input wire [`PKT_BITS - 1:0] opkt_data,
input wire opkt_vld,
output reg opkt_rdy,
// output AER device interface
output reg [15:0] oaer_data,
output reg oaer_req,
input wire oaer_ack
);
//---------------------------------------------------------------
// constants
//---------------------------------------------------------------
localparam OSTATE_BITS = 2;
localparam IDLE_OST = 0;
localparam HS11_OST = IDLE_OST + 1;
localparam HS10_OST = HS11_OST + 1;
//---------------------------------------------------------------
// internal signals
//---------------------------------------------------------------
reg [OSTATE_BITS - 1:0] ostate;
//---------------------------------------------------------------
// generate opkt_rdy signal
//---------------------------------------------------------------
always @(posedge clk or posedge rst)
if (rst)
opkt_rdy <= 1'b1;
else
case (ostate)
IDLE_OST:
if (opkt_vld)
opkt_rdy <= 1'b0;
else
opkt_rdy <= 1'b1; // no change!
HS10_OST:
if (oaer_ack) // oaer_ack is active LOW!
opkt_rdy <= 1'b1;
else
opkt_rdy <= 1'b0; // no change!
default:
opkt_rdy <= opkt_rdy; // no change!
endcase
//---------------------------------------------------------------
//---------------------------------------------------------------
// extract event data from packet and send out
//---------------------------------------------------------------
always @(posedge clk or posedge rst)
if (rst)
oaer_data <= 16'd0; // not really necessary!
else
case (ostate)
IDLE_OST:
if (opkt_vld)
oaer_data <= opkt_data[23:8];
else
oaer_data <= oaer_data; // no change!
default:
oaer_data <= oaer_data; // no change!
endcase
always @(posedge clk or posedge rst)
if (rst)
oaer_req <= 1'b1; // oaer_req is active LOW!
else
case (ostate)
IDLE_OST:
if (opkt_vld)
oaer_req <= 1'b0;
else
oaer_req <= 1'b1; // no change!
HS11_OST:
if (!oaer_ack) // oaer_ack is active LOW!
oaer_req <= 1'b1;
else
oaer_req <= 1'b0; // no change!
default:
oaer_req <= oaer_req; // no change!
endcase
//---------------------------------------------------------------
//---------------------------------------------------------------
// out_mapper state machine
//---------------------------------------------------------------
always @(posedge clk or posedge rst)
if (rst)
ostate <= IDLE_OST;
else
case (ostate)
IDLE_OST:
if (opkt_vld)
ostate <= HS11_OST;
else
ostate <= IDLE_OST; // no change!
HS11_OST:
if (!oaer_ack) // oaer_ack is active LOW!
ostate <= HS10_OST;
else
ostate <= HS11_OST; // no change!
HS10_OST:
if (oaer_ack)
ostate <= IDLE_OST;
else
ostate <= HS10_OST; // no change!
default:
ostate <= ostate; // no change!
endcase
endmodule
| 9.49495 |
module spio_spinnaker_link_packet_gen (
clk,
reset,
data_2of7,
ack
// gen_data
);
input reset;
input clk;
output [6:0] data_2of7;
input ack;
//input [31:0] gen_data;
///////////////////////////////////////////////////////////////////
// 2 of 7 packet generator
// Packet generator state machine //
reg [ 8:0] gen_state;
reg [ 6:0] data_2of7;
reg [ 4:0] quibble;
reg [39:0] packet;
reg old_ack;
reg [15:0] cnt;
initial gen_state = 0;
initial data_2of7 = 0;
//#parameter gen_data = 'h76543210;
parameter gen_data = 32'hFFFE0000;
parameter gen_header = 8'h00;
always @(posedge clk or posedge reset) begin
if (reset == 1) begin
gen_state <= 0;
data_2of7 <= 0;
cnt <= 0;
end else
case (gen_state)
0: begin
//# packet <= {gen_data, 8'h0}; //create spinnaker packet
packet <= {(gen_data | cnt), gen_header}; //create spinnaker packet
gen_state <= gen_state + 1;
end
1: begin
quibble <= {1'b0, packet[3:1], ~(^packet[39:1])};
gen_state <= gen_state + 1;
end
2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22: begin
data_2of7 <= code_2of7_lut(quibble, data_2of7); //transmit 2of7 code to spinnaker
packet <= packet >> 4; //shift the next packet nibble down
old_ack <= ack;
gen_state <= gen_state + 1;
end
3, 5, 7, 9, 11, 13, 15, 17, 19 // set the nibble
: begin
quibble[3:0] <= packet[3:0];
if (ack != old_ack) gen_state <= gen_state + 1; //wait for ack from spinnaker
end
21: begin // set eop
quibble[4] <= 1;
if (ack != old_ack) gen_state <= gen_state + 1;
end
23:
if (ack != old_ack) begin
gen_state <= 0;
cnt <= cnt + 1;
end
default: ;
endcase
;
end
// Define functions
function [6:0] code_2of7_lut;
input [4:0] din;
input [6:0] code_2of7;
casez (din)
5'b00000: code_2of7_lut = code_2of7 ^ 7'b0010001; // 0
5'b00001: code_2of7_lut = code_2of7 ^ 7'b0010010; // 1
5'b00010: code_2of7_lut = code_2of7 ^ 7'b0010100; // 2
5'b00011: code_2of7_lut = code_2of7 ^ 7'b0011000; // 3
5'b00100: code_2of7_lut = code_2of7 ^ 7'b0100001; // 4
5'b00101: code_2of7_lut = code_2of7 ^ 7'b0100010; // 5
5'b00110: code_2of7_lut = code_2of7 ^ 7'b0100100; // 6
5'b00111: code_2of7_lut = code_2of7 ^ 7'b0101000; // 7
5'b01000: code_2of7_lut = code_2of7 ^ 7'b1000001; // 8
5'b01001: code_2of7_lut = code_2of7 ^ 7'b1000010; // 9
5'b01010: code_2of7_lut = code_2of7 ^ 7'b1000100; // 10
5'b01011: code_2of7_lut = code_2of7 ^ 7'b1001000; // 11
5'b01100: code_2of7_lut = code_2of7 ^ 7'b0000011; // 12
5'b01101: code_2of7_lut = code_2of7 ^ 7'b0000110; // 13
5'b01110: code_2of7_lut = code_2of7 ^ 7'b0001100; // 14
5'b01111: code_2of7_lut = code_2of7 ^ 7'b0001001; // 15
5'b1????: code_2of7_lut = code_2of7 ^ 7'b1100000; // EOP
default: code_2of7_lut = 7'bxxxxxxx;
endcase
;
endfunction
;
endmodule
| 7.752712 |
module spio_spinnaker_link_sync #(
parameter SIZE = 1
) (
input CLK_IN,
input [SIZE - 1:0] IN,
output reg [SIZE - 1:0] OUT
);
//---------------------------------------------------------------
// internal signals
//---------------------------------------------------------------
(* IOB = "TRUE" *)
reg [SIZE - 1:0] sync;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//--------------------------- datapath --------------------------
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// flops
always @(posedge CLK_IN) begin
sync <= IN;
OUT <= sync;
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 7.752712 |
module spio_spinnaker_link_sync2 #(
parameter SIZE = 1
) (
input CLK0_IN,
input CLK1_IN,
input [SIZE - 1:0] IN,
output reg [SIZE - 1:0] OUT
);
//---------------------------------------------------------------
// internal signals
//---------------------------------------------------------------
reg [SIZE - 1:0] sync;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//--------------------------- datapath --------------------------
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// flops
always @(posedge CLK0_IN) sync <= IN;
always @(posedge CLK1_IN) OUT <= sync;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 7.752712 |
module
//
// -------------------------------------------------------------------------
// AUTHOR
// lap - luis.plana@manchester.ac.uk
// Based on work by J Pepper (Date 08/08/2012)
//
// -------------------------------------------------------------------------
// Taken from:
// https://solem.cs.man.ac.uk/svn/spiNNlink/testing/src/packet_receiver.v
// Revision 2517 (Last-modified date: Date: 2013-08-19 10:33:30 +0100)
//
// -------------------------------------------------------------------------
// COPYRIGHT
// Copyright (c) The University of Manchester, 2012-2016.
// SpiNNaker Project
// Advanced Processor Technologies Group
// School of Computer Science
// -------------------------------------------------------------------------
// TODO
// -------------------------------------------------------------------------
// ----------------------------------------------------------------
// include spiNNlink global constants and parameters
//
`include "spio_spinnaker_link.h"
// ----------------------------------------------------------------
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
`timescale 1ns / 1ps
module spio_spinnaker_link_synchronous_receiver
(
input CLK_IN,
input RESET_IN,
// link error reporting
output wire FLT_ERR_OUT,
output wire FRM_ERR_OUT,
output wire GCH_ERR_OUT,
// SpiNNaker link interface
input [6:0] SL_DATA_2OF7_IN,
output wire SL_ACK_OUT,
// spiNNlink interface
output wire [`PKT_BITS - 1:0] PKT_DATA_OUT,
output wire PKT_VLD_OUT,
input PKT_RDY_IN
);
//-------------------------------------------------------------
// internal signals
//-------------------------------------------------------------
wire [6:0] synced_sl_data_2of7; // synchronized 2of7-encoded data input
// these signals do not use rdy/vld handshake!
// cts must be 1 before starting to send flits
// dat/bad/eop are a 1-hot indication of a new flit
wire [6:0] flt_data_bad; // bad data flit
wire [3:0] flt_data_bin; // binary data
wire flt_dat; // flit is correct data
wire flt_bad; // flit contains incorrect data
wire flt_eop; // flit contains and end-of-packet
wire flt_cts; // flit interface is clear-to-send
spio_spinnaker_link_sync #(.SIZE(7)) sync
( .CLK_IN (CLK_IN),
.IN (SL_DATA_2OF7_IN),
.OUT (synced_sl_data_2of7)
);
flit_input_if fi
(
.CLK_IN (CLK_IN),
.RESET_IN (RESET_IN),
.GCH_ERR_OUT (GCH_ERR_OUT),
.SL_DATA_2OF7_IN (synced_sl_data_2of7),
.SL_ACK_OUT (SL_ACK_OUT),
.flt_data_bad (flt_data_bad),
.flt_data_bin (flt_data_bin),
.flt_dat (flt_dat),
.flt_bad (flt_bad),
.flt_eop (flt_eop),
.flt_cts (flt_cts)
);
pkt_deserializer pd
(
.CLK_IN (CLK_IN),
.RESET_IN (RESET_IN),
.FLT_ERR_OUT (FLT_ERR_OUT),
.FRM_ERR_OUT (FRM_ERR_OUT),
.flt_data_bad (flt_data_bad),
.flt_data_bin (flt_data_bin),
.flt_dat (flt_dat),
.flt_bad (flt_bad),
.flt_eop (flt_eop),
.flt_cts (flt_cts),
.PKT_DATA_OUT (PKT_DATA_OUT),
.PKT_VLD_OUT (PKT_VLD_OUT),
.PKT_RDY_IN (PKT_RDY_IN)
);
endmodule
| 7.80459 |
module
//
// -------------------------------------------------------------------------
// AUTHOR
// lap - luis.plana@manchester.ac.uk
// Based on work by J Pepper (Date 08/08/2012)
//
// -------------------------------------------------------------------------
// Taken from:
// https://solem.cs.man.ac.uk/svn/spiNNlink/testing/src/packet_sender.v
// Revision 2517 (Last-modified date: 2013-08-19 10:33:30 +0100)
//
// -------------------------------------------------------------------------
// COPYRIGHT
// Copyright (c) The University of Manchester, 2012-2016.
// SpiNNaker Project
// Advanced Processor Technologies Group
// School of Computer Science
// -------------------------------------------------------------------------
// TODO
// -------------------------------------------------------------------------
// ----------------------------------------------------------------
// include spiNNlink global constants and parameters
//
`include "spio_spinnaker_link.h"
// ----------------------------------------------------------------
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
`timescale 1ns / 1ps
module spio_spinnaker_link_synchronous_sender
(
input CLK_IN,
input RESET_IN,
// link error reporting
output wire ACK_ERR_OUT,
output wire TMO_ERR_OUT,
// synchronous packet interface
input [`PKT_BITS - 1:0] PKT_DATA_IN,
input PKT_VLD_IN,
output PKT_RDY_OUT,
// SpiNNaker link asynchronous interface
output [6:0] SL_DATA_2OF7_OUT,
input SL_ACK_IN
);
//-------------------------------------------------------------
// internal signals
//-------------------------------------------------------------
wire synced_sl_ack; // synchronized acknowledge input
wire [6:0] flt_data;
wire flt_vld;
wire flt_rdy;
pkt_serializer ps
(
.CLK_IN (CLK_IN),
.RESET_IN (RESET_IN),
.PKT_DATA_IN (PKT_DATA_IN),
.PKT_VLD_IN (PKT_VLD_IN),
.PKT_RDY_OUT (PKT_RDY_OUT),
.flt_data (flt_data),
.flt_vld (flt_vld),
.flt_rdy (flt_rdy)
);
flit_output_if fo
(
.CLK_IN (CLK_IN),
.RESET_IN (RESET_IN),
.ACK_ERR_OUT (ACK_ERR_OUT),
.TMO_ERR_OUT (TMO_ERR_OUT),
.flt_data (flt_data),
.flt_vld (flt_vld),
.flt_rdy (flt_rdy),
.SL_DATA_2OF7_OUT (SL_DATA_2OF7_OUT),
.SL_ACK_IN (synced_sl_ack)
);
spio_spinnaker_link_sync #(.SIZE(1)) sync
( .CLK_IN (CLK_IN),
.IN (SL_ACK_IN),
.OUT (synced_sl_ack)
);
endmodule
| 7.80459 |
module spio_uart_baud_gen #( // The number of ticks before the timer expires.
parameter PERIOD = 100
// The number of bits to use for the internal timer
// (must be enough to represent PERIOD-1)
, parameter NUM_BITS = 7
) ( // Input clock source
input wire CLK_IN
// Asynchronous active-high reset
, input wire RESET_IN
// A single-cycle pulse every PERIOD clock ticks
, output wire BAUD_PULSE_OUT
// A single-cycle pulse (approximately) every
// PERIOD/8 clock ticks, for sub-sampling an
// incoming signal.
, output wire SUBSAMPLE_PULSE_OUT
);
// The baud pulse counter
reg [NUM_BITS-1:0] counter_i;
always @(posedge CLK_IN, posedge RESET_IN)
if (RESET_IN) counter_i <= PERIOD - 1;
else if (counter_i == 0) counter_i <= PERIOD - 1;
else counter_i <= counter_i - 1;
assign BAUD_PULSE_OUT = counter_i == {NUM_BITS{1'b0}};
// The subsampling pulse counter
reg [NUM_BITS-3-1:0] counter8_i;
always @(posedge CLK_IN, posedge RESET_IN)
if (RESET_IN) counter8_i <= (PERIOD >> 3) - 1;
else if (counter8_i == 0) counter8_i <= (PERIOD >> 3) - 1;
else counter8_i <= counter8_i - 1;
assign SUBSAMPLE_PULSE_OUT = counter8_i == {(NUM_BITS - 3) {1'b0}};
endmodule
| 7.147371 |
module spio_uart_fifo #( // The number of bits required to address the specified
// buffer size (i.e. the buffer will have size
// (1<<BUFFER_ADDR_BITS)-1).
parameter BUFFER_ADDR_BITS = 4
// The number of bits in a word in the buffer.
, parameter WORD_SIZE = 8
) ( // Common clock for synchronous signals
input wire CLK_IN
// Asynchronous active-high reset
, input wire RESET_IN
// The number of words in the FIFO.
, output wire [BUFFER_ADDR_BITS-1:0] OCCUPANCY_OUT
// Input (rdy/vld protocol)
, input wire [ WORD_SIZE-1:0] IN_DATA_IN
, input wire IN_VLD_IN
, output wire IN_RDY_OUT
// Output (rdy/vld protocol)
, output wire [ WORD_SIZE-1:0] OUT_DATA_OUT
, output wire OUT_VLD_OUT
, input wire OUT_RDY_IN
);
// A circular buffer where head_i points to the next empty slot and tail_i
// points to the last value in the buffer.
reg [ WORD_SIZE-1:0] buffer_i[(1<<BUFFER_ADDR_BITS)-1:0];
reg [BUFFER_ADDR_BITS-1:0] head_i;
reg [BUFFER_ADDR_BITS-1:0] tail_i;
// If the FIFO is empty, head_i and tail_i are equal.
assign OUT_VLD_OUT = head_i != tail_i;
// If the FIFO is full, head_i == tail_i-1.
assign IN_RDY_OUT = head_i != (tail_i - 1);
// The output data is just the current tail
assign OUT_DATA_OUT = (head_i != tail_i) ? buffer_i[tail_i] : {WORD_SIZE{1'bX}};
// The difference between the pointers positive-modulo the length of the buffer
// yields the number of words in the FIFO.
assign OCCUPANCY_OUT = head_i - tail_i;
// Advance (and fill) the head of the FIFO whenever valid data arrives
always @(posedge CLK_IN, posedge RESET_IN)
if (RESET_IN) head_i <= {BUFFER_ADDR_BITS{1'b0}};
else if (IN_RDY_OUT && IN_VLD_IN) begin
head_i <= head_i + 1;
buffer_i[head_i] <= IN_DATA_IN;
end
// Advance the tail whenever a value is output
always @(posedge CLK_IN, posedge RESET_IN)
if (RESET_IN) tail_i <= {BUFFER_ADDR_BITS{1'b0}};
else if (OUT_RDY_IN && OUT_VLD_OUT) tail_i <= tail_i + 1;
endmodule
| 8.439757 |
module spio_uart_sync #( // The number of bits to synchronise
parameter NUM_BITS = 1
// The number of synchroniser flops to go through (must
// be at least 1)
, parameter NUM_STAGES = 2
// The value to initialise internal flops to (and thus
// the value during reset)
, parameter INITIAL_VALUE = 0
) ( // Clock to sync to
input wire CLK_IN
// Asynchronous active-high reset
, input wire RESET_IN
// Signal to synchronise
, input wire [NUM_BITS-1:0] DATA_IN
// Synchronised signal
, output wire [NUM_BITS-1:0] DATA_OUT
);
genvar i;
// Data trickles from flop 0 up to flop NUM_STAGES-1.
reg [NUM_BITS-1:0] sync_flops_i[NUM_STAGES-1:0];
always @(posedge CLK_IN, posedge RESET_IN)
if (RESET_IN) sync_flops_i[0] <= INITIAL_VALUE;
else sync_flops_i[0] <= DATA_IN;
generate
for (i = 1; i < NUM_STAGES; i = i + 1) begin : sync_stages
always @(posedge CLK_IN, posedge RESET_IN)
if (RESET_IN) sync_flops_i[i] <= INITIAL_VALUE;
else sync_flops_i[i] <= sync_flops_i[i-1];
end
endgenerate
assign DATA_OUT = sync_flops_i[0];
endmodule
| 7.925194 |
module spi_phy_internal_altera_avalon_st_idle_remover (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7:0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7:0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & in_ready) begin
if (escape_char & ~received_esc) begin
received_esc <= 1;
end else if (out_valid) begin
received_esc <= 0;
end
end
end
end
always @* begin
in_ready = out_ready;
//out valid when in_valid. Except when we get idle or escape
//however, if we have received an escape character, then we are valid
out_valid = in_valid & ~idle_char & (received_esc | ~escape_char);
out_data = received_esc ? (in_data ^ 8'h20) : in_data;
end
endmodule
| 6.954639 |
module spi_phy_internal_altera_avalon_st_idle_inserter (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7:0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7:0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & out_ready) begin
if ((idle_char | escape_char) & ~received_esc & out_ready) begin
received_esc <= 1;
end else begin
received_esc <= 0;
end
end
end
end
always @* begin
//we are always valid
out_valid = 1'b1;
in_ready = out_ready & (~in_valid | ((~idle_char & ~escape_char) | received_esc));
out_data = (~in_valid) ? 8'h4a : //if input is not valid, insert idle
(received_esc) ? in_data ^ 8'h20 : //escaped once, send data XOR'd
(idle_char | escape_char) ? 8'h4d : //input needs escaping, send escape_char
in_data; //send data
end
endmodule
| 6.954639 |
module single_output_pipeline_stage (
in_valid, /*input valid signal*/
in_ready, /*input ready signal*/
in_data, /*input data signal*/
out_valid, /*output valid signal*/
out_ready, /*output ready signal*/
out_data, /*output data signal*/
clk, /*clock signal*/
reset_n /*reset signal*/
);
/*parameter declaration*/
parameter DATAWIDTH = 8;
/*input, output declaration*/
input clk;
input reset_n;
input in_valid;
output in_ready;
input [DATAWIDTH-1:0] in_data;
output out_valid;
input out_ready;
output [DATAWIDTH-1:0] out_data;
reg out_valid;
reg [DATAWIDTH-1:0] out_data;
/*internal wires*/
wire internal_out_ready;
/*comb logic*/
assign internal_out_ready = out_ready || (!out_valid);
assign in_ready = out_ready; /*ready signal is pass through*/
/*always block for output valid signal and data signal*/
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
out_valid <= 0;
end else begin
if (internal_out_ready) begin
out_valid <= in_valid;
end
end
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
out_data <= {DATAWIDTH{1'b0}};
end else begin
if (internal_out_ready) begin
out_data <= in_data;
end
end
end
endmodule
| 7.235132 |
module shiftRegFIFO (
X,
Y,
clk
);
parameter depth = 1, width = 1;
output [width-1:0] Y;
input [width-1:0] X;
input clk;
reg [width-1:0] mem [depth-1:0];
integer index;
assign Y = mem[depth-1];
always @(posedge clk) begin
for (index = 1; index < depth; index = index + 1) begin
mem[index] <= mem[index-1];
end
mem[0] <= X;
end
endmodule
| 7.124291 |
module rc87481 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
wire [63:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[63:32];
assign Y1 = s0[31:0];
assign Y2 = s1[63:32];
assign Y3 = s1[31:0];
perm87479 instPerm110003 (
.x0(t0),
.y0(s0),
.x1(t1),
.y1(s1),
.clk(clk),
.next(next),
.next_out(next_out),
.reset(reset)
);
endmodule
| 7.197592 |
module nextReg (
X,
Y,
reset,
clk
);
parameter depth = 2, logDepth = 1;
output Y;
input X;
input clk, reset;
reg [logDepth:0] count;
reg active;
assign Y = (count == depth) ? 1 : 0;
always @(posedge clk) begin
if (reset == 1) begin
count <= 0;
active <= 0;
end else if (X == 1) begin
active <= 1;
count <= 1;
end else if (count == depth) begin
count <= 0;
active <= 0;
end else if (active) count <= count + 1;
end
endmodule
| 6.59955 |
module memMod (
in,
out,
inAddr,
outAddr,
writeSel,
clk
);
parameter depth = 1024, width = 16, logDepth = 10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is block
reg [width-1:0] mem [depth-1:0];
always @(posedge clk) begin
out <= mem[outAddr];
if (writeSel) mem[inAddr] <= in;
end
endmodule
| 7.262241 |
module memMod_dist (
in,
out,
inAddr,
outAddr,
writeSel,
clk
);
parameter depth = 1024, width = 16, logDepth = 10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is distributed
reg [width-1:0] mem [depth-1:0];
always @(posedge clk) begin
out <= mem[outAddr];
if (writeSel) mem[inAddr] <= in;
end
endmodule
| 7.680291 |
module switch (
ctrl,
x0,
x1,
y0,
y1
);
parameter width = 16;
input [width-1:0] x0, x1;
output [width-1:0] y0, y1;
input ctrl;
assign y0 = (ctrl == 0) ? x0 : x1;
assign y1 = (ctrl == 0) ? x1 : x0;
endmodule
| 6.864438 |
module shiftRegFIFO (
X,
Y,
clk
);
parameter depth = 1, width = 1;
output [width-1:0] Y;
input [width-1:0] X;
input clk;
reg [width-1:0] mem [depth-1:0];
integer index;
assign Y = mem[depth-1];
always @(posedge clk) begin
for (index = 1; index < depth; index = index + 1) begin
mem[index] <= mem[index-1];
end
mem[0] <= X;
end
endmodule
| 7.124291 |
module rc87564 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
wire [63:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[63:32];
assign Y1 = s0[31:0];
assign Y2 = s1[63:32];
assign Y3 = s1[31:0];
perm87562 instPerm110024 (
.x0(t0),
.y0(s0),
.x1(t1),
.y1(s1),
.clk(clk),
.next(next),
.next_out(next_out),
.reset(reset)
);
endmodule
| 7.106502 |
module memArray4_87562 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
clk,
inFlip,
outFlip
);
parameter numBanks = 2;
parameter logBanks = 1;
parameter depth = 2;
parameter logDepth = 1;
parameter width = 64;
input clk, next, reset;
input inFlip, outFlip;
wire next0;
input [width-1:0] x0;
output [width-1:0] y0;
input [logDepth-1:0] inAddr0, outAddr0;
input [width-1:0] x1;
output [width-1:0] y1;
input [logDepth-1:0] inAddr1, outAddr1;
shiftRegFIFO #(2, 1) shiftFIFO_110033 (
.X (next),
.Y (next0),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod0 (
.in(x0),
.out(y0),
.inAddr({inFlip, inAddr0}),
.outAddr({outFlip, outAddr0}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod1 (
.in(x1),
.out(y1),
.inAddr({inFlip, inAddr1}),
.outAddr({outFlip, outAddr1}),
.writeSel(1'b1),
.clk(clk)
);
endmodule
| 6.637434 |
module D42_87735 (
addr,
out,
clk
);
input clk;
output [31:0] out;
reg [31:0] out, out2, out3;
input [0:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 32'h3f800000;
1: out3 <= 32'h0;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "distributed"
endmodule
| 6.656545 |
module D44_87743 (
addr,
out,
clk
);
input clk;
output [31:0] out;
reg [31:0] out, out2, out3;
input [0:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 32'h0;
1: out3 <= 32'hbf800000;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "distributed"
endmodule
| 7.140299 |
module rc87829 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
wire [63:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[63:32];
assign Y1 = s0[31:0];
assign Y2 = s1[63:32];
assign Y3 = s1[31:0];
perm87827 instPerm110041 (
.x0(t0),
.y0(s0),
.x1(t1),
.y1(s1),
.clk(clk),
.next(next),
.next_out(next_out),
.reset(reset)
);
endmodule
| 6.504066 |
module D38_87998 (
addr,
out,
clk
);
input clk;
output [31:0] out;
reg [31:0] out, out2, out3;
input [1:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 32'h3f800000;
1: out3 <= 32'h3f3504f3;
2: out3 <= 32'h0;
3: out3 <= 32'hbf3504f3;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "distributed"
endmodule
| 6.934489 |
module D40_88016 (
addr,
out,
clk
);
input clk;
output [31:0] out;
reg [31:0] out, out2, out3;
input [1:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 32'h0;
1: out3 <= 32'hbf3504f3;
2: out3 <= 32'hbf800000;
3: out3 <= 32'hbf3504f3;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "distributed"
endmodule
| 6.783452 |
module rc88102 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
wire [63:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[63:32];
assign Y1 = s0[31:0];
assign Y2 = s1[63:32];
assign Y3 = s1[31:0];
perm88100 instPerm110058 (
.x0(t0),
.y0(s0),
.x1(t1),
.y1(s1),
.clk(clk),
.next(next),
.next_out(next_out),
.reset(reset)
);
endmodule
| 6.795712 |
module memArray16_88100 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
clk,
inFlip,
outFlip
);
parameter numBanks = 2;
parameter logBanks = 1;
parameter depth = 8;
parameter logDepth = 3;
parameter width = 64;
input clk, next, reset;
input inFlip, outFlip;
wire next0;
input [width-1:0] x0;
output [width-1:0] y0;
input [logDepth-1:0] inAddr0, outAddr0;
input [width-1:0] x1;
output [width-1:0] y1;
input [logDepth-1:0] inAddr1, outAddr1;
shiftRegFIFO #(8, 1) shiftFIFO_110067 (
.X (next),
.Y (next0),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod0 (
.in(x0),
.out(y0),
.inAddr({inFlip, inAddr0}),
.outAddr({outFlip, outAddr0}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod1 (
.in(x1),
.out(y1),
.inAddr({inFlip, inAddr1}),
.outAddr({outFlip, outAddr1}),
.writeSel(1'b1),
.clk(clk)
);
endmodule
| 6.685218 |
module D34_88295 (
addr,
out,
clk
);
input clk;
output [31:0] out;
reg [31:0] out, out2, out3;
input [2:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 32'h3f800000;
1: out3 <= 32'h3f6c835e;
2: out3 <= 32'h3f3504f3;
3: out3 <= 32'h3ec3ef15;
4: out3 <= 32'h0;
5: out3 <= 32'hbec3ef15;
6: out3 <= 32'hbf3504f3;
7: out3 <= 32'hbf6c835e;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "distributed"
endmodule
| 6.713127 |
module rc88391 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
wire [63:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[63:32];
assign Y1 = s0[31:0];
assign Y2 = s1[63:32];
assign Y3 = s1[31:0];
perm88389 instPerm110075 (
.x0(t0),
.y0(s0),
.x1(t1),
.y1(s1),
.clk(clk),
.next(next),
.next_out(next_out),
.reset(reset)
);
endmodule
| 6.746835 |
module D32_88572 (
addr,
out,
clk
);
input clk;
output [31:0] out;
reg [31:0] out, out2, out3;
input [3:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 32'h0;
1: out3 <= 32'hbe47c5c2;
2: out3 <= 32'hbec3ef15;
3: out3 <= 32'hbf0e39da;
4: out3 <= 32'hbf3504f3;
5: out3 <= 32'hbf54db31;
6: out3 <= 32'hbf6c835e;
7: out3 <= 32'hbf7b14be;
8: out3 <= 32'hbf800000;
9: out3 <= 32'hbf7b14be;
10: out3 <= 32'hbf6c835e;
11: out3 <= 32'hbf54db31;
12: out3 <= 32'hbf3504f3;
13: out3 <= 32'hbf0e39da;
14: out3 <= 32'hbec3ef15;
15: out3 <= 32'hbe47c5c2;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "distributed"
endmodule
| 6.55555 |
module D30_88608 (
addr,
out,
clk
);
input clk;
output [31:0] out;
reg [31:0] out, out2, out3;
input [3:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 32'h3f800000;
1: out3 <= 32'h3f7b14be;
2: out3 <= 32'h3f6c835e;
3: out3 <= 32'h3f54db31;
4: out3 <= 32'h3f3504f3;
5: out3 <= 32'h3f0e39da;
6: out3 <= 32'h3ec3ef15;
7: out3 <= 32'h3e47c5c2;
8: out3 <= 32'h0;
9: out3 <= 32'hbe47c5c2;
10: out3 <= 32'hbec3ef15;
11: out3 <= 32'hbf0e39da;
12: out3 <= 32'hbf3504f3;
13: out3 <= 32'hbf54db31;
14: out3 <= 32'hbf6c835e;
15: out3 <= 32'hbf7b14be;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "distributed"
endmodule
| 6.820919 |
module rc88712 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
wire [63:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[63:32];
assign Y1 = s0[31:0];
assign Y2 = s1[63:32];
assign Y3 = s1[31:0];
perm88710 instPerm110100 (
.x0(t0),
.y0(s0),
.x1(t1),
.y1(s1),
.clk(clk),
.next(next),
.next_out(next_out),
.reset(reset)
);
endmodule
| 6.740419 |
module memArray64_88710 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
clk,
inFlip,
outFlip
);
parameter numBanks = 2;
parameter logBanks = 1;
parameter depth = 32;
parameter logDepth = 5;
parameter width = 64;
input clk, next, reset;
input inFlip, outFlip;
wire next0;
input [width-1:0] x0;
output [width-1:0] y0;
input [logDepth-1:0] inAddr0, outAddr0;
input [width-1:0] x1;
output [width-1:0] y1;
input [logDepth-1:0] inAddr1, outAddr1;
nextReg #(32, 5) nextReg_110113 (
.X(next),
.Y(next0),
.reset(reset),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod0 (
.in(x0),
.out(y0),
.inAddr({inFlip, inAddr0}),
.outAddr({outFlip, outAddr0}),
.writeSel(1'b1),
.clk(clk)
);
memMod_dist #(depth * 2, width, logDepth + 1) memMod1 (
.in(x1),
.out(y1),
.inAddr({inFlip, inAddr1}),
.outAddr({outFlip, outAddr1}),
.writeSel(1'b1),
.clk(clk)
);
endmodule
| 6.956129 |
module rc89097 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
wire [63:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[63:32];
assign Y1 = s0[31:0];
assign Y2 = s1[63:32];
assign Y3 = s1[31:0];
perm89095 instPerm110125 (
.x0(t0),
.y0(s0),
.x1(t1),
.y1(s1),
.clk(clk),
.next(next),
.next_out(next_out),
.reset(reset)
);
endmodule
| 6.614422 |
module rc89610 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
wire [63:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[63:32];
assign Y1 = s0[31:0];
assign Y2 = s1[63:32];
assign Y3 = s1[31:0];
perm89608 instPerm110150 (
.x0(t0),
.y0(s0),
.x1(t1),
.y1(s1),
.clk(clk),
.next(next),
.next_out(next_out),
.reset(reset)
);
endmodule
| 6.937146 |
module rc90379 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
wire [63:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[63:32];
assign Y1 = s0[31:0];
assign Y2 = s1[63:32];
assign Y3 = s1[31:0];
perm90377 instPerm110175 (
.x0(t0),
.y0(s0),
.x1(t1),
.y1(s1),
.clk(clk),
.next(next),
.next_out(next_out),
.reset(reset)
);
endmodule
| 6.598659 |
module rc91660 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
wire [63:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[63:32];
assign Y1 = s0[31:0];
assign Y2 = s1[63:32];
assign Y3 = s1[31:0];
perm91658 instPerm110200 (
.x0(t0),
.y0(s0),
.x1(t1),
.y1(s1),
.clk(clk),
.next(next),
.next_out(next_out),
.reset(reset)
);
endmodule
| 6.607253 |
module rc93965 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
wire [63:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[63:32];
assign Y1 = s0[31:0];
assign Y2 = s1[63:32];
assign Y3 = s1[31:0];
perm93963 instPerm110225 (
.x0(t0),
.y0(s0),
.x1(t1),
.y1(s1),
.clk(clk),
.next(next),
.next_out(next_out),
.reset(reset)
);
endmodule
| 6.79302 |
module rc106766 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
wire [63:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[63:32];
assign Y1 = s0[31:0];
assign Y2 = s1[63:32];
assign Y3 = s1[31:0];
perm106764 instPerm110275 (
.x0(t0),
.y0(s0),
.x1(t1),
.y1(s1),
.clk(clk),
.next(next),
.next_out(next_out),
.reset(reset)
);
endmodule
| 6.895769 |
module multfp32fp32 (
clk,
enable,
rst,
a,
b,
out
);
input [31:0] a, b;
output [31:0] out;
input clk, enable, rst;
wire signA, signB;
wire [7:0] expA, expB;
wire [23:0] sigA, sigB;
assign signA = b[31];
assign expA = b[30:23];
assign sigA = {1'b1, b[22:0]};
assign signB = a[31];
assign expB = a[30:23];
assign sigB = {1'b1, a[22:0]};
reg signP_m0;
reg [8:0] expP_m0;
wire [47:0] mult_res0;
multfxp24fxp24 mult (
clk,
enable,
rst,
sigA,
sigB,
mult_res0
);
reg isNaN_a0, isNaN_b0, isZero_a0, isZero_b0, isInf_a0, isInf_b0;
wire sigAZero, sigBZero;
assign sigAZero = (sigA[22:0] == 0);
assign sigBZero = (sigB[22:0] == 0);
// stage 1 mult stage 1
always @(posedge clk)
if (enable) begin
isNaN_a0 <= (expA == 8'hff) && !sigAZero;
isNaN_b0 <= (expB == 8'hff) && !sigBZero;
isZero_a0 <= (expA == 8'h00);
isZero_b0 <= (expB == 8'h00);
isInf_a0 <= (expA == 8'hff) && sigAZero;
isInf_b0 <= (expB == 8'hff) && sigBZero;
signP_m0 <= signA != signB;
expP_m0 <= expA + expB;
end
reg signP_m1, zero_m1, inf_m1, nan_m1, under_m1;
reg [8:0] expP_m1;
// stage 2 mult stage 2
always @(posedge clk)
if (enable) begin
zero_m1 <= isZero_a0 || isZero_b0;
inf_m1 <= isInf_a0 || isInf_b0;
nan_m1 <= isNaN_a0 || isNaN_b0;
under_m1 <= (expP_m0 < 128);
signP_m1 <= signP_m0;
expP_m1 <= expP_m0 - 127;
end
reg signP_m2, zero_m2, inf_m2, nan_m2;
reg [8:0] expP_m2;
// stage 3 mult stage 3
always @(posedge clk)
if (enable) begin
zero_m2 <= zero_m1 || under_m1;
inf_m2 <= (inf_m1 || (expP_m1[8] && ~under_m1));
nan_m2 <= nan_m1 || (zero_m1 && inf_m1); // 0 * infty = NaN
signP_m2 <= signP_m1;
expP_m2 <= expP_m1;
end
reg signP_m3, zero_m3, inf_m3, nan_m3;
reg [8:0] expP_m3;
// stage 4 mult stage 4
always @(posedge clk)
if (enable) begin
zero_m3 <= zero_m2;
inf_m3 <= (inf_m2 || (expP_m2 == 9'h0ff));
nan_m3 <= nan_m2;
signP_m3 <= signP_m2;
expP_m3 <= expP_m2;
end
reg signP_m4, zero_m4, inf_m4, nan_m4;
reg [8:0] expP_m4;
// stage 5 mult stage 5
always @(posedge clk)
if (enable) begin
zero_m4 <= zero_m3;
inf_m4 <= inf_m3;
nan_m4 <= nan_m3;
signP_m4 <= signP_m3;
expP_m4 <= expP_m3;
end
reg signP_m5, zero_m5, inf_m5, nan_m5;
reg [8:0] expP_m5;
// stage 6 mult stage 6
always @(posedge clk)
if (enable) begin
zero_m5 <= zero_m4;
inf_m5 <= inf_m4;
nan_m5 <= nan_m4;
signP_m5 <= signP_m4;
expP_m5 <= expP_m4;
end
reg signP_m6, zero_m6, inf_m6, nan_m6;
reg [ 8:0] expP_m6;
reg [23:0] sig_m6;
// stage 7 -- mult output here!
// normalize product
always @(posedge clk)
if (enable) begin
zero_m6 <= (zero_m5 || (mult_res0[47:23] == 0));
nan_m6 <= nan_m5;
signP_m6 <= signP_m5;
if (mult_res0[47] == 1'b1) begin
expP_m6 <= expP_m5 + 1;
sig_m6 <= mult_res0[47:24];
inf_m6 <= (inf_m5 || (expP_m5 == 9'h0ff));
end else begin
expP_m6 <= expP_m5;
sig_m6 <= mult_res0[46:23];
inf_m6 <= inf_m5;
end
end
reg signP_m7;
reg [7:0] expP_m7;
reg [22:0] sig_m7;
// stage 8: cleanup
always @(posedge clk)
if (enable) begin
signP_m7 <= signP_m6;
if (inf_m6 || nan_m6) expP_m7 <= 8'hff;
else if (zero_m6) expP_m7 <= 8'h00;
else expP_m7 <= expP_m6;
if (nan_m6) sig_m7 <= 1;
else if (zero_m6 || inf_m6) sig_m7 <= 0;
else sig_m7 <= sig_m6[22:0];
end
assign out = {signP_m7, expP_m7, sig_m7};
endmodule
| 6.885293 |
module multfxp24fxp24 (
clk,
enable,
rst,
a,
b,
out
);
parameter WIDTH = 24, CYCLES = 6;
input [WIDTH-1:0] a, b;
output [2*WIDTH-1:0] out;
input clk, rst, enable;
reg [2*WIDTH-1:0] q [CYCLES-1:0];
integer i;
assign out = q[CYCLES-1];
always @(posedge clk) begin
q[0] <= a * b;
for (i = 1; i < CYCLES; i = i + 1) begin
q[i] <= q[i-1];
end
end
endmodule
| 6.576922 |
module addfxp (
a,
b,
q,
clk
);
parameter width = 16, cycles = 1;
input signed [width-1:0] a, b;
input clk;
output signed [width-1:0] q;
reg signed [width-1:0] res[cycles-1:0];
assign q = res[cycles-1];
integer i;
always @(posedge clk) begin
res[0] <= a + b;
for (i = 1; i < cycles; i = i + 1) res[i] <= res[i-1];
end
endmodule
| 6.519538 |
module shiftRegFIFO (
X,
Y,
clk
);
parameter depth = 1, width = 1;
output [width-1:0] Y;
input [width-1:0] X;
input clk;
reg [width-1:0] mem [depth-1:0];
integer index;
assign Y = mem[depth-1];
always @(posedge clk) begin
for (index = 1; index < depth; index = index + 1) begin
mem[index] <= mem[index-1];
end
mem[0] <= X;
end
endmodule
| 7.124291 |
module multfp32fp32 (
clk,
enable,
rst,
a,
b,
out
);
input [31:0] a, b;
output [31:0] out;
input clk, enable, rst;
wire signA, signB;
wire [7:0] expA, expB;
wire [23:0] sigA, sigB;
assign signA = b[31];
assign expA = b[30:23];
assign sigA = {1'b1, b[22:0]};
assign signB = a[31];
assign expB = a[30:23];
assign sigB = {1'b1, a[22:0]};
reg signP_m0;
reg [8:0] expP_m0;
wire [47:0] mult_res0;
multfxp24fxp24 mult (
clk,
enable,
rst,
sigA,
sigB,
mult_res0
);
reg isNaN_a0, isNaN_b0, isZero_a0, isZero_b0, isInf_a0, isInf_b0;
wire sigAZero, sigBZero;
assign sigAZero = (sigA[22:0] == 0);
assign sigBZero = (sigB[22:0] == 0);
// stage 1 mult stage 1
always @(posedge clk)
if (enable) begin
isNaN_a0 <= (expA == 8'hff) && !sigAZero;
isNaN_b0 <= (expB == 8'hff) && !sigBZero;
isZero_a0 <= (expA == 8'h00);
isZero_b0 <= (expB == 8'h00);
isInf_a0 <= (expA == 8'hff) && sigAZero;
isInf_b0 <= (expB == 8'hff) && sigBZero;
signP_m0 <= signA != signB;
expP_m0 <= expA + expB;
end
reg signP_m1, zero_m1, inf_m1, nan_m1, under_m1;
reg [8:0] expP_m1;
// stage 2 mult stage 2
always @(posedge clk)
if (enable) begin
zero_m1 <= isZero_a0 || isZero_b0;
inf_m1 <= isInf_a0 || isInf_b0;
nan_m1 <= isNaN_a0 || isNaN_b0;
under_m1 <= (expP_m0 < 128);
signP_m1 <= signP_m0;
expP_m1 <= expP_m0 - 127;
end
reg signP_m2, zero_m2, inf_m2, nan_m2;
reg [8:0] expP_m2;
// stage 3 mult stage 3
always @(posedge clk)
if (enable) begin
zero_m2 <= zero_m1 || under_m1;
inf_m2 <= (inf_m1 || (expP_m1[8] && ~under_m1));
nan_m2 <= nan_m1 || (zero_m1 && inf_m1); // 0 * infty = NaN
signP_m2 <= signP_m1;
expP_m2 <= expP_m1;
end
reg signP_m3, zero_m3, inf_m3, nan_m3;
reg [8:0] expP_m3;
// stage 4 mult stage 4
always @(posedge clk)
if (enable) begin
zero_m3 <= zero_m2;
inf_m3 <= (inf_m2 || (expP_m2 == 9'h0ff));
nan_m3 <= nan_m2;
signP_m3 <= signP_m2;
expP_m3 <= expP_m2;
end
reg signP_m4, zero_m4, inf_m4, nan_m4;
reg [8:0] expP_m4;
// stage 5 mult stage 5
always @(posedge clk)
if (enable) begin
zero_m4 <= zero_m3;
inf_m4 <= inf_m3;
nan_m4 <= nan_m3;
signP_m4 <= signP_m3;
expP_m4 <= expP_m3;
end
reg signP_m5, zero_m5, inf_m5, nan_m5;
reg [8:0] expP_m5;
// stage 6 mult stage 6
always @(posedge clk)
if (enable) begin
zero_m5 <= zero_m4;
inf_m5 <= inf_m4;
nan_m5 <= nan_m4;
signP_m5 <= signP_m4;
expP_m5 <= expP_m4;
end
reg signP_m6, zero_m6, inf_m6, nan_m6;
reg [ 8:0] expP_m6;
reg [23:0] sig_m6;
// stage 7 -- mult output here!
// normalize product
always @(posedge clk)
if (enable) begin
zero_m6 <= (zero_m5 || (mult_res0[47:23] == 0));
nan_m6 <= nan_m5;
signP_m6 <= signP_m5;
if (mult_res0[47] == 1'b1) begin
expP_m6 <= expP_m5 + 1;
sig_m6 <= mult_res0[47:24];
inf_m6 <= (inf_m5 || (expP_m5 == 9'h0ff));
end else begin
expP_m6 <= expP_m5;
sig_m6 <= mult_res0[46:23];
inf_m6 <= inf_m5;
end
end
reg signP_m7;
reg [7:0] expP_m7;
reg [22:0] sig_m7;
// stage 8: cleanup
always @(posedge clk)
if (enable) begin
signP_m7 <= signP_m6;
if (inf_m6 || nan_m6) expP_m7 <= 8'hff;
else if (zero_m6) expP_m7 <= 8'h00;
else expP_m7 <= expP_m6;
if (nan_m6) sig_m7 <= 1;
else if (zero_m6 || inf_m6) sig_m7 <= 0;
else sig_m7 <= sig_m6[22:0];
end
assign out = {signP_m7, expP_m7, sig_m7};
endmodule
| 6.885293 |
module multfxp24fxp24 (
clk,
enable,
rst,
a,
b,
out
);
parameter WIDTH = 24, CYCLES = 6;
input [WIDTH-1:0] a, b;
output [2*WIDTH-1:0] out;
input clk, rst, enable;
reg [2*WIDTH-1:0] q [CYCLES-1:0];
integer i;
assign out = q[CYCLES-1];
always @(posedge clk) begin
q[0] <= a * b;
for (i = 1; i < CYCLES; i = i + 1) begin
q[i] <= q[i-1];
end
end
endmodule
| 6.576922 |
module addfxp (
a,
b,
q,
clk
);
parameter width = 16, cycles = 1;
input signed [width-1:0] a, b;
input clk;
output signed [width-1:0] q;
reg signed [width-1:0] res[cycles-1:0];
assign q = res[cycles-1];
integer i;
always @(posedge clk) begin
res[0] <= a + b;
for (i = 1; i < cycles; i = i + 1) res[i] <= res[i-1];
end
endmodule
| 6.519538 |
module spiral_0 (
i_data,
o_data_36,
o_data_83
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input signed [19:0] i_data;
output signed [19+7:0] o_data_36;
output signed [19+7:0] o_data_83;
// ********************************************
//
// WIRE DECLARATION
//
// ********************************************
wire signed [26:0] w1, w8, w9, w64, w65, w18, w83, w36;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign w1 = i_data;
assign w8 = w1 << 3;
assign w9 = w1 + w8;
assign w64 = w1 << 6;
assign w65 = w1 + w64;
assign w18 = w9 << 1;
assign w83 = w65 + w18;
assign w36 = w9 << 2;
assign o_data_36 = w36;
assign o_data_83 = w83;
endmodule
| 7.01186 |
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