code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module spi (
input clk,
input miso,
output mosi,
output sck,
input rst,
input start,
input cpol,
input cpha,
input [4:0] bits_per_word,
input [5:0] div,
input [MAX_DATA_WIDTH-1:0] data_in,
output [MAX_DATA_WIDTH-1:0] data_out,
output busy... | 7.760909 |
module spi_slave #(
parameter MAX_BITS_PER_WORD = 8,
parameter USE_TX = "TRUE",
parameter USE_RX = "TRUE"
) (
input rst_i,
input clk_i,
input en_i,
input [3:0] bit_per_word_i,
input lsb_first_i,
input ss_i,
input scl_i,
output miso_o,
input mosi_i,
input [MAX_BITS_PER... | 6.875224 |
module spi (
input wire clk, // 7MHz
input wire enviar_dato, // a 1 para indicar que queremos enviar un dato por SPI
input wire recibir_dato, // a 1 para indicar que queremos recibir un dato
input wire [7:0] din, // del bus de datos de salida de la CPU
ou... | 7.760909 |
module implement a 16-bit shift register and control logic to send
// 16-bit words serially, MSB first, to a low-speed DAC. The bit rate is
// 1/4 of the input clock rate. The serial clock (sclk) positive edge occurs
// 1/4 cycle after sync becomes active. Data changes 1/4 cycle after the
// falling edge of sclk.
//
//... | 8.672374 |
module spi2dac (
clk,
data_in,
load,
dac_sdi,
dac_cs,
dac_sck,
dac_ld
);
input clk; // 50MHz system clock of DE0
input [9:0] data_in; // input data to DAC
input load; // Pulse to load data to dac
output dac_sdi; // SPI serial data out
output dac_cs; // chip select - low when ... | 7.828507 |
module spiarbiter (
i_clk,
i_cs_a_n,
i_ck_a,
i_mosi_a,
i_cs_b_n,
i_ck_b,
i_mosi_b,
o_cs_a_n,
o_cs_b_n,
o_ck,
o_mosi,
o_grant
);
input i_clk;
input i_cs_a_n, i_ck_a, i_mosi_a;
// output wire o_grant_a;
input i_cs_b_n, i_ck_b, i_mosi_b;
// output wire o_grant_b;
... | 7.77286 |
module SPIbs (
input clock,
input reset,
// input byte valid
input wire ib_v,
// input byte value
input wire [7:0] ib_in,
output wire [7:0] rb_o,
output wire byte_ready,
output wire sclk,
output wire mosi,
input wire miso
);
assign sclk = divclk & ib_v;
assign byt... | 6.664835 |
modules. The spi_master
// selects the data to be transmitted and stores all data received
// from the PmodACL. The data is then made available to the rest of
// the design on the xAxis, yAxis, and zAxis outputs.
//
//
// Inputs:
// CLK 100MHz onboard system clock
// RST Main Reset Controller
/... | 8.292332 |
module spiControl (
input clock, //On-board Zynq clock (100 MHz)
input reset,
input [7:0] data_in,
input load_data, //Signal indicates new data for transmission
output reg done_send, //Signal indicates data has been sent over spi interface
outpu... | 6.726953 |
module spidlg (
input Clk,
input Dclk,
input Din,
input Dlatch,
output [6:0] Dout,
output [5:0] Addr,
output CLR,
output WR
);
reg clear;
reg write_latch;
reg [3:0] address;
reg [8:0] sr;
reg [2:0] state;
// Commands
parameter CLEAR = 0, LOAD = 1, LOAD_ADV = 2, GOTO_POS ... | 7.313117 |
module SPIDriver_tb;
reg master_clock = 1'b1;
reg [ 2:0] image_number = 3'b000;
reg [ 2:0] access_type = 3'b000;
reg [11:0] absolute_position = 12'd1018;
wire [14:0] write_addr;
wire write_data;
wire write_clock;
wire nCS;
wire MOSI;
wire MISO;
wi... | 6.719993 |
module spigpio (
clk,
cs,
sr_in,
gpioin,
gpioout,
sr_out
);
input clk, cs;
input sr_in;
input [9:0] gpioin;
output sr_out;
output [9:0] gpioout;
reg [9:0] gpioout;
reg sr_out;
reg [7:0] ram;
wire [6:0] addr;
wire [7:0] data;
wire rw;
reg [15:0] sr;
assign rw = sr... | 6.590193 |
module SPIHandler (
CLK,
ARST_L,
DIN,
DOUT,
SEND,
DONE,
MOSI,
MISO,
SCLK_A,
SS,
XDATA_MISO,
YDATA_MISO
);
input CLK, ARST_L;
input [23:0] DIN;
output [23:0] DOUT;
input SEND;
output DONE;
input MISO;
output MOSI;
output SS, SCLK_A;
output [7:0] XDATA_MIS... | 7.310697 |
module spihub (
input wire fclk,
input wire rst_n,
// pins to SDcard
output reg sdcs_n,
output wire sdclk,
output wire sddo,
input wire sddi,
// zports SDcard iface
input wire zx_sdcs_n_val,
input wire zx_sdcs_n_stb,
input wire zx_sd_start,
input... | 6.936413 |
module spi (
clk,
rstb,
sclk,
Nss0,
mosi,
miso,
start,
busy,
clk_end,
wr_data,
rd_data,
rd_data_en,
rd_1byte
);
input clk;
input rstb;
//SPI
output sclk;
output Nss0;
output mosi;
input miso;
//interface
input start; //通信開始
output busy; //通信中
i... | 7.53911 |
module spikecnt_async (
spike,
int_cnt_out,
fast_clk,
slow_clk,
reset,
clear_out,
cnt,
sig1,
sig2,
read
);
input spike, slow_clk, fast_clk, reset;
output reg [31:0] int_cnt_out, cnt;
reg [31:0] acc_cnt_d1, acc_cnt_d0;
output clear_out;
output read;
output reg sig1, ... | 7.55137 |
module spikecnt_async_old (
spike,
int_cnt_out,
fast_clk,
slow_clk,
reset,
clear_out,
cnt,
sig1,
sig2,
read
);
input spike, slow_clk, fast_clk, reset;
output reg [31:0] int_cnt_out, cnt;
output clear_out;
output read;
output reg sig1, sig2;
reg [31:0] status_counte... | 7.55137 |
module spikeout_gen (
input i_clk,
input i_rst_n,
input [1:0] i_spike_in,
input [3:0] i_spike,
output [3:0] o_spike
);
parameter p_delay = 4;
reg [$clog2(p_delay):0] r_counter;
reg r_event_on;
wire w_event_on;
wire w_reset_n;
... | 7.704602 |
module spike_generator (
input i_event,
input i_clk,
input i_rst_n,
output o_spike
);
wire w_q2, w_q1;
assign o_spike = w_q2;
flipflop u1 (
.i_d (1'b1),
.i_clk(i_event),
.i_clr(w_q2 | ~i_rst_n),
.o_q (w_q1),
.o_qb ()
);
flipflop u2 (
.i_d (w_q1),
... | 8.025153 |
module spill_register_497C2_3F032 (
clk_i,
rst_ni,
valid_i,
ready_o,
data_i,
valid_o,
ready_i,
data_o
);
parameter [31:0] T_SelectWidth = 0;
parameter [0:0] Bypass = 1'b0;
input wire clk_i;
input wire rst_ni;
input wire valid_i;
output wire ready_o;
input wire [T_SelectWidt... | 7.215474 |
module spill_register_F2424 (
clk_i,
rst_ni,
valid_i,
ready_o,
data_i,
valid_o,
ready_i,
data_o
);
parameter [0:0] Bypass = 1'b0;
input wire clk_i;
input wire rst_ni;
input wire valid_i;
output wire ready_o;
input wire data_i;
output wire valid_o;
input wire ready_i;
ou... | 7.215474 |
module spill_register_flushable_C4179 (
clk_i,
rst_ni,
valid_i,
flush_i,
ready_o,
data_i,
valid_o,
ready_i,
data_o
);
parameter [0:0] Bypass = 1'b0;
input wire clk_i;
input wire rst_ni;
input wire valid_i;
input wire flush_i;
output wire ready_o;
input wire data_i;
ou... | 7.215474 |
module spill_register_flushable_ECCE9_D4EC8 (
clk_i,
rst_ni,
valid_i,
flush_i,
ready_o,
data_i,
valid_o,
ready_i,
data_o
);
parameter [31:0] T_T_SelectWidth = 0;
parameter [0:0] Bypass = 1'b0;
input wire clk_i;
input wire rst_ni;
input wire valid_i;
input wire flush_i;
... | 7.215474 |
module consisting of SPIMinionAdapterComposite and Loopback modules.
For use with testing SPI communication
Author : Kyle Infantino
Date : Oct 31, 2022
*/
`ifndef SPI_V3_COMPONENTS_LOOPBACKCOMPOSITE_V
`define SPI_V3_COMPONENTS_LOOPBACKCOMPOSITE_V
`include "SPI_v3/components/LoopBackVRTL.v"
`include "SPI_v3/compone... | 8.294413 |
module spils (
input iocs, // select this module for I/O
input [2:0] ioaddr, // address (this module uses 4)
input [15:0] din, // parallel data input
input iowr, // input valid
output [15:0] dout, // parallel data output
input sdi, // serial data input
output sdo, // serial data outpu... | 7.435714 |
module sm_fifoRTL (
wrClk,
rdClk,
rstSyncToWrClk,
rstSyncToRdClk,
dataIn,
dataOut,
fifoWEn,
fifoREn,
fifoFull,
fifoEmpty,
forceEmptySyncToWrClk,
forceEmptySyncToRdClk,
numElementsInFifo
);
//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
parameter FIFO_WIDTH = 8;... | 7.980621 |
module sm_RxFifo (
busClk,
spiSysClk,
rstSyncToBusClk,
rstSyncToSpiClk,
fifoWEn,
fifoFull,
busAddress,
busWriteEn,
busStrobe_i,
busFifoSelect,
busDataIn,
busDataOut,
fifoDataIn
);
//FIFO_DEPTH = 2^ADDR_WIDTH
parameter FIFO_DEPTH = 64;
parameter ADDR_WIDTH = 6;
... | 7.12044 |
module sm_TxFifo (
busClk,
spiSysClk,
rstSyncToBusClk,
rstSyncToSpiClk,
fifoREn,
fifoEmpty,
busAddress,
busWriteEn,
busStrobe_i,
busFifoSelect,
busDataIn,
busDataOut,
fifoDataOut
);
//FIFO_DEPTH = 2^ADDR_WIDTH
parameter FIFO_DEPTH = 64;
parameter ADDR_WIDTH = 6;... | 7.082185 |
module spimemio_pack #(
parameter BASE_ADDR = 8'h00
) (
input clk,
resetn,
output flash_csb,
output flash_clk,
// Tristate Data IO pins
inout [3:0] flash_dz,
// PicoRV32 packed MEM Bus interface
input [68:0] mem_packed_fwd, //DEC > GPO
output [32:0] mem_packed_ret //DEC < ... | 7.178614 |
module spiMemory
(
input clk, // FPGA clock
input sclk_pin, // SPI clock
input cs_pin, // SPI chip select
output miso_pin, // SPI master in slave out
input mosi_pin, // SPI master out slave in
input fault_pin, // For fa... | 6.624118 |
module combining the SPIMinion and SPIMinionAdapter
// Author : Kyle Infantino
// Date : Dec 7, 2021
`ifndef SPI_V3_COMPONENTS_MINION_ADAPTER_COMPOSITE_V
`define SPI_V3_COMPONENTS_MINION_ADAPTER_COMPOSITE_V
`include "SPI_v3/components/SPIMinionVRTL.v"
`include "SPI_v3/components/SPIMinionAdapterVRTL.v"
module SP... | 9.386012 |
module SPI_v3_components_SPIMinionAdapterVRTL #(
parameter nbits = 8,
parameter num_entries = 1
) (
input logic clk,
input logic reset,
input logic pull_en,
output logic pull_msg_val,
output logic pull_msg_spc,
output logic [... | 7.522988 |
module top (
input clk,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5,
output RS232_Tx,
input RS232_Rx
);
reg [15:0] count = 0;
reg [ 7:0] ctimer = 0;
reg [ 3:0] laresetct = 0;
wire lareset;
assign lareset = (laresetct == 4'b0000 || laresetct ... | 7.233807 |
module spindle_bag1 (
gamma_dyn,
lce,
clk,
reset,
out0,
out1,
out2,
out3
);
input [31:0] gamma_dyn;
input [31:0] lce;
input clk;
input reset;
output wire [31:0] out0;
output wire [31:0] out1;
output wire [31:0] out2;
output wire [31:0] out3;
// *** Declarations
reg ... | 7.230676 |
module spindle_bag2_derivatives (
input [31:0] gamma_dyn,
input [31:0] lce,
input [31:0] x_0,
input [31:0] x_1,
input [31:0] x_2,
output [31:0] dx_0,
output [31:0] dx_1,
output [31:0] dx_2
);
//Min Gamma Dynamic Calculation
//
//From spindle.py
// mingd = gammaDyn**2/(gamma... | 6.860421 |
module spindle_neuron (
input [31:0] pps,
input clk,
input reset,
output reg spike
);
reg [10:0] isi_count; //Inter spike interval count
reg [10:0] spike_count; //spike count over 1 second
reg [1023:0] spike_history;
wire [31:0] floored_pps;
wire [10:0] int_pps;
wire [10:0] isi; //inter ... | 7.183239 |
module spinet6 (
input clk,
input rst,
input [37:0] io_in,
output [37:0] io_out
);
spinet #(
.N(6)
) SPINET (
.clk (clk),
.rst (rst),
.MOSI ({io_in[0], io_in[8], io_in[14], io_in[20], io_in[26], io_in[32]}),
.SCLK ({io_in[1], io_in[9], io_in[15], io_in[21], io... | 7.475178 |
module spinet5 (
input clk,
input rst,
input [37:0] io_in,
output [37:0] io_out
);
spinet #(
.N(5)
) SPINET (
.clk (clk),
.rst (rst),
.MOSI ({io_in[8], io_in[14], io_in[20], io_in[26], io_in[32]}),
.SCLK ({io_in[9], io_in[15], io_in[21], io_in[27], io_in[33]})... | 7.299742 |
module spinet #(
parameter N = 8,
WIDTH = 16,
ABITS = 3
) (
input clk,
input rst,
output [N-1:0] txready,
output [N-1:0] rxready,
input [N-1:0] MOSI,
SCLK,
SS,
output [N-1:0] MISO
);
wire [WIDTH-1:0] r[N-1:0];
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin
... | 8.061406 |
module spinode #(
parameter WIDTH = 16,
ABITS = 3,
ADDRESS = 0
) (
input clk,
input rst,
input [WIDTH-1:0] fromring,
output [WIDTH-1:0] toring,
output txready,
rxready,
input SCLK,
SS,
MOSI,
output MISO
);
wire [WIDTH-1:0] txdata, rxdata;
wire mosivalid, mosiack,... | 7.786073 |
module ringnode #(
parameter WIDTH = 16,
ABITS = 3,
ADDRESS = 0
) (
input clk,
input rst,
input [WIDTH-1:0] fromring,
output [WIDTH-1:0] toring,
input [WIDTH-1:0] fromclient,
output [WIDTH-1:0] toclient,
output txready,
rxready,
input mosivalid,
misoack,
output re... | 7.618976 |
module ringspi #(
parameter WIDTH = 16
) (
input rst,
input SCLK,
SS,
MOSI,
output MISO,
input misovalid,
output reg misoack,
output reg mosivalid,
input mosiack,
output [WIDTH-1:0] rxdata,
input [WIDTH-1:0] txdata
);
localparam LOGWIDTH = $clog2(WIDTH);
reg [WIDTH:0... | 8.302773 |
module spinnaker_fpgas_sync #(
parameter SIZE = 1
) (
input CLK_IN,
input [SIZE - 1:0] IN,
output reg [SIZE - 1:0] OUT
);
//---------------------------------------------------------------
// internal signals
//---------------------------------------------------------------
... | 7.944417 |
module spinner (
input wire sync_rot_a,
input wire sync_rot_b,
input wire clk,
output reg event_rot_l,
output reg event_rot_r
);
reg rotary_q1;
reg rotary_q2;
reg rotary_q1_dly;
reg rotary_q2_dly;
always @(posedge clk) begin : filter
case ({
sync_rot_b, sync_rot_a
})
... | 6.771272 |
module spinner (
clock,
spin,
amount,
din,
dout
);
input clock;
input spin;
input [4:0] amount;
input [31:0] din;
output [31:0] dout;
reg [31:0] dout;
reg [31:0] inr;
reg spl;
wire [31:0] tmp0;
wire [31:0] tmp1;
wire [31:0] tmp2;
wire [31:0] tmp3;
wire [31:0] tm... | 6.771272 |
module spin_timer (
CLOCK,
reset,
start,
value,
pause,
active,
done
);
input CLOCK, reset, start, pause;
output active, done;
output [3:0] value; // provides the value1 (max 4 bits) of the
// current time on the timer – you’ll pass this on to a BCD decoder,
// and then to a 7-seg... | 8.279232 |
module spio (
i_clk,
i_wb_cyc,
i_wb_stb,
i_wb_we,
i_wb_data,
i_wb_sel,
o_wb_ack,
o_wb_stall,
o_wb_data,
i_btn,
o_led,
o_int
);
parameter NLEDS = 8, NBTN = 8;
input wire i_clk;
input wire i_wb_cyc, i_wb_stb, i_wb_we;
input wire [31:0] i_wb_data;
input wire [3:0] ... | 6.985462 |
module
//
// -------------------------------------------------------------------------
// AUTHOR
// lap - luis.plana@manchester.ac.uk
// Based on work by J Pepper (Date 07/08/2012)
//
// -------------------------------------------------------------------------
// DETAILS
// Created on : 28 Nov 2012
// Version... | 7.80459 |
module spio_hss_multiplexer_lfsr_tb;
// constants
// ----------------------------------
// internal signals
// ----------------------------------
// clock signals
reg tb_clk; // tb
reg uut_clk; // unit under test
// reset signals
reg tb_rst; // tb
reg uut_rst; ... | 7.043246 |
module spio_link_speed_doubler_tb;
localparam PKT_BITS = 16;
genvar i;
reg sclk_i;
reg fclk_i;
reg reset_i;
// Input stream
reg [PKT_BITS-1:0] in_data_i;
reg in_vld_i;
wire in_rdy_i;
// Output stream
wire [PKT_BIT... | 7.052187 |
module spio_link_speed_halver_tb;
localparam PKT_BITS = 16;
genvar i;
reg sclk_i;
reg fclk_i;
reg reset_i;
// Input stream
reg [PKT_BITS-1:0] in_data_i;
reg in_vld_i;
wire in_rdy_i;
// Output stream
wire [PKT_BITS... | 7.052187 |
module
//
// -------------------------------------------------------------------------
// AUTHOR
// lap - luis.plana@manchester.ac.uk
//
// -------------------------------------------------------------------------
// DETAILS
// Created on : 28 Mar 2013
// Version : $Revision: 2517 $
// Last modified ... | 7.80459 |
modules/spinnaker_link/spio_spinnaker_link.h"
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
`timescale 1ns / 1ps
module spio_spinn2aer_mapper
(
input wire rst,
input wire clk,
// SpiNNaker packet interface
input wire [`PKT_BITS - 1:0] opkt_data,
inp... | 9.49495 |
module spio_spinnaker_link_packet_gen (
clk,
reset,
data_2of7,
ack
// gen_data
);
input reset;
input clk;
output [6:0] data_2of7;
input ack;
//input [31:0] gen_data;
///////////////////////////////////////////////////////////////////
// 2 of 7 packet generator
// Packet gene... | 7.752712 |
module spio_spinnaker_link_sync #(
parameter SIZE = 1
) (
input CLK_IN,
input [SIZE - 1:0] IN,
output reg [SIZE - 1:0] OUT
);
//---------------------------------------------------------------
// internal signals
//------------------------------------------------------------... | 7.752712 |
module spio_spinnaker_link_sync2 #(
parameter SIZE = 1
) (
input CLK0_IN,
input CLK1_IN,
input [SIZE - 1:0] IN,
output reg [SIZE - 1:0] OUT
);
//---------------------------------------------------------------
// internal signals
//---------------------... | 7.752712 |
module
//
// -------------------------------------------------------------------------
// AUTHOR
// lap - luis.plana@manchester.ac.uk
// Based on work by J Pepper (Date 08/08/2012)
//
// -------------------------------------------------------------------------
// Taken from:
// https://solem.cs.man.ac.uk/svn/spiNNlin... | 7.80459 |
module
//
// -------------------------------------------------------------------------
// AUTHOR
// lap - luis.plana@manchester.ac.uk
// Based on work by J Pepper (Date 08/08/2012)
//
// -------------------------------------------------------------------------
// Taken from:
// https://solem.cs.man.ac.uk/svn/spiNNlin... | 7.80459 |
module spio_uart_baud_gen #( // The number of ticks before the timer expires.
parameter PERIOD = 100
// The number of bits to use for the internal timer
// (must be enough to represent PERIOD-1)
, parameter NUM_BITS = 7
) ( // Input clock source
input wire CLK_IN
// Asynchronous active-... | 7.147371 |
module spio_uart_fifo #( // The number of bits required to address the specified
// buffer size (i.e. the buffer will have size
// (1<<BUFFER_ADDR_BITS)-1).
parameter BUFFER_ADDR_BITS = 4
// The number of bits in a word in the buffer.
, parameter WORD_SIZ... | 8.439757 |
module spio_uart_sync #( // The number of bits to synchronise
parameter NUM_BITS = 1
// The number of synchroniser flops to go through (must
// be at least 1)
, parameter NUM_STAGES = 2
// The value to initialise internal flops to (and thus
// the value during reset)
, parameter INITIAL_VAL... | 7.925194 |
module spi_phy_internal_altera_avalon_st_idle_remover (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7:0] in_data,
// Interface: ST out
input out_ready,
output... | 6.954639 |
module spi_phy_internal_altera_avalon_st_idle_inserter (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7:0] in_data,
// Interface: ST out
input out_ready,
outpu... | 6.954639 |
module single_output_pipeline_stage (
in_valid, /*input valid signal*/
in_ready, /*input ready signal*/
in_data, /*input data signal*/
out_valid, /*output valid signal*/
out_ready, /*output ready signal*/
out_data, /*output data signal*/
clk, /*clock signal*/
reset_n /*reset sig... | 7.235132 |
module shiftRegFIFO (
X,
Y,
clk
);
parameter depth = 1, width = 1;
output [width-1:0] Y;
input [width-1:0] X;
input clk;
reg [width-1:0] mem [depth-1:0];
integer index;
assign Y = mem[depth-1];
always @(posedge clk) begin
for (index = 1; index < depth; index = index... | 7.124291 |
module rc87481 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
w... | 7.197592 |
module nextReg (
X,
Y,
reset,
clk
);
parameter depth = 2, logDepth = 1;
output Y;
input X;
input clk, reset;
reg [logDepth:0] count;
reg active;
assign Y = (count == depth) ? 1 : 0;
always @(posedge clk) begin
if (reset == 1) begin
count <= 0;
active <= 0... | 6.59955 |
module memMod (
in,
out,
inAddr,
outAddr,
writeSel,
clk
);
parameter depth = 1024, width = 16, logDepth = 10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is ... | 7.262241 |
module memMod_dist (
in,
out,
inAddr,
outAddr,
writeSel,
clk
);
parameter depth = 1024, width = 16, logDepth = 10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of me... | 7.680291 |
module switch (
ctrl,
x0,
x1,
y0,
y1
);
parameter width = 16;
input [width-1:0] x0, x1;
output [width-1:0] y0, y1;
input ctrl;
assign y0 = (ctrl == 0) ? x0 : x1;
assign y1 = (ctrl == 0) ? x1 : x0;
endmodule
| 6.864438 |
module shiftRegFIFO (
X,
Y,
clk
);
parameter depth = 1, width = 1;
output [width-1:0] Y;
input [width-1:0] X;
input clk;
reg [width-1:0] mem [depth-1:0];
integer index;
assign Y = mem[depth-1];
always @(posedge clk) begin
for (index = 1; index < depth; index = index... | 7.124291 |
module rc87564 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
w... | 7.106502 |
module memArray4_87562 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
clk,
inFlip,
outFlip
);
parameter numBanks = 2;
parameter logBanks = 1;
parameter depth = 2;
parameter logDepth = 1;
parameter width = 64;
input clk, next, reset;... | 6.637434 |
module D42_87735 (
addr,
out,
clk
);
input clk;
output [31:0] out;
reg [31:0] out, out2, out3;
input [0:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 32'h3f800000;
1: out3 <= 32'h0;
default: out3 <= 0;
endcase
end
// ... | 6.656545 |
module D44_87743 (
addr,
out,
clk
);
input clk;
output [31:0] out;
reg [31:0] out, out2, out3;
input [0:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 32'h0;
1: out3 <= 32'hbf800000;
default: out3 <= 0;
endcase
end
// ... | 7.140299 |
module rc87829 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
w... | 6.504066 |
module D38_87998 (
addr,
out,
clk
);
input clk;
output [31:0] out;
reg [31:0] out, out2, out3;
input [1:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 32'h3f800000;
1: out3 <= 32'h3f3504f3;
2: out3 <= 32'h0;
3: out3 <= 3... | 6.934489 |
module D40_88016 (
addr,
out,
clk
);
input clk;
output [31:0] out;
reg [31:0] out, out2, out3;
input [1:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 32'h0;
1: out3 <= 32'hbf3504f3;
2: out3 <= 32'hbf800000;
3: out3 <= 3... | 6.783452 |
module rc88102 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
w... | 6.795712 |
module memArray16_88100 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
clk,
inFlip,
outFlip
);
parameter numBanks = 2;
parameter logBanks = 1;
parameter depth = 8;
parameter logDepth = 3;
parameter width = 64;
input clk, next, reset... | 6.685218 |
module D34_88295 (
addr,
out,
clk
);
input clk;
output [31:0] out;
reg [31:0] out, out2, out3;
input [2:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 32'h3f800000;
1: out3 <= 32'h3f6c835e;
2: out3 <= 32'h3f3504f3;
3: ou... | 6.713127 |
module rc88391 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
w... | 6.746835 |
module D32_88572 (
addr,
out,
clk
);
input clk;
output [31:0] out;
reg [31:0] out, out2, out3;
input [3:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 32'h0;
1: out3 <= 32'hbe47c5c2;
2: out3 <= 32'hbec3ef15;
3: out3 <= 3... | 6.55555 |
module D30_88608 (
addr,
out,
clk
);
input clk;
output [31:0] out;
reg [31:0] out, out2, out3;
input [3:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 32'h3f800000;
1: out3 <= 32'h3f7b14be;
2: out3 <= 32'h3f6c835e;
3: ou... | 6.820919 |
module rc88712 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
w... | 6.740419 |
module memArray64_88710 (
next,
reset,
x0,
y0,
inAddr0,
outAddr0,
x1,
y1,
inAddr1,
outAddr1,
clk,
inFlip,
outFlip
);
parameter numBanks = 2;
parameter logBanks = 1;
parameter depth = 32;
parameter logDepth = 5;
parameter width = 64;
input clk, next, rese... | 6.956129 |
module rc89097 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
w... | 6.614422 |
module rc89610 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
w... | 6.937146 |
module rc90379 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
w... | 6.598659 |
module rc91660 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
w... | 6.607253 |
module rc93965 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
w... | 6.79302 |
module rc106766 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [31:0] X0, X1, X2, X3;
output [31:0] Y0, Y1, Y2, Y3;
wire [63:0] t0;
wire [63:0] s0;
assign t0 = {X0, X1};
wire [63:0] t1;
... | 6.895769 |
module multfp32fp32 (
clk,
enable,
rst,
a,
b,
out
);
input [31:0] a, b;
output [31:0] out;
input clk, enable, rst;
wire signA, signB;
wire [7:0] expA, expB;
wire [23:0] sigA, sigB;
assign signA = b[31];
assign expA = b[30:23];
assign sigA = {1'b1, b[22:0]};
assign signB ... | 6.885293 |
module multfxp24fxp24 (
clk,
enable,
rst,
a,
b,
out
);
parameter WIDTH = 24, CYCLES = 6;
input [WIDTH-1:0] a, b;
output [2*WIDTH-1:0] out;
input clk, rst, enable;
reg [2*WIDTH-1:0] q [CYCLES-1:0];
integer i;
assign out = q[CYCLES-1];
always @(posedge clk) begi... | 6.576922 |
module addfxp (
a,
b,
q,
clk
);
parameter width = 16, cycles = 1;
input signed [width-1:0] a, b;
input clk;
output signed [width-1:0] q;
reg signed [width-1:0] res[cycles-1:0];
assign q = res[cycles-1];
integer i;
always @(posedge clk) begin
res[0] <= a + b;
for (i = 1; i < ... | 6.519538 |
module shiftRegFIFO (
X,
Y,
clk
);
parameter depth = 1, width = 1;
output [width-1:0] Y;
input [width-1:0] X;
input clk;
reg [width-1:0] mem [depth-1:0];
integer index;
assign Y = mem[depth-1];
always @(posedge clk) begin
for (index = 1; index < depth; index = index... | 7.124291 |
module multfp32fp32 (
clk,
enable,
rst,
a,
b,
out
);
input [31:0] a, b;
output [31:0] out;
input clk, enable, rst;
wire signA, signB;
wire [7:0] expA, expB;
wire [23:0] sigA, sigB;
assign signA = b[31];
assign expA = b[30:23];
assign sigA = {1'b1, b[22:0]};
assign signB ... | 6.885293 |
module multfxp24fxp24 (
clk,
enable,
rst,
a,
b,
out
);
parameter WIDTH = 24, CYCLES = 6;
input [WIDTH-1:0] a, b;
output [2*WIDTH-1:0] out;
input clk, rst, enable;
reg [2*WIDTH-1:0] q [CYCLES-1:0];
integer i;
assign out = q[CYCLES-1];
always @(posedge clk) begi... | 6.576922 |
module addfxp (
a,
b,
q,
clk
);
parameter width = 16, cycles = 1;
input signed [width-1:0] a, b;
input clk;
output signed [width-1:0] q;
reg signed [width-1:0] res[cycles-1:0];
assign q = res[cycles-1];
integer i;
always @(posedge clk) begin
res[0] <= a + b;
for (i = 1; i < ... | 6.519538 |
module spiral_0 (
i_data,
o_data_36,
o_data_83
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
// ... | 7.01186 |
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