code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module spiral_4 (
i_data,
o_data_18,
o_data_50,
o_data_75,
o_data_89
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
// ... | 6.755767 |
module spiral_8 (
i_data,
o_data_9,
o_data_25,
o_data_43,
o_data_57,
o_data_70,
o_data_80,
o_data_87,
o_data_90
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION ... | 6.75681 |
module spiral_move (
clk,
rst,
done_spin,
enable,
output_speed,
motion_command
);
parameter done_time = 32'd200; //Original=20000
parameter STOP = 2'b00;
parameter STRAIGHT = 2'b01;
parameter TURN = 2'b10;
parameter COUNT_UP = 2'b11; //used for counting straight states
parameter TU... | 8.204679 |
module spiral_move_tb;
reg clk, rst;
reg enable;
reg done_spin;
wire [2:0] output_speed;
wire [9:0] motion_command;
spiral_move SP (
.clk(clk),
.rst(rst),
.enable(enable),
.done_spin(done_spin),
.output_speed(output_speed),
.motion_command(motion_command)
);
ini... | 6.797452 |
module spiRead (
spiClock,
start,
bitIn,
finish,
byteOut,
waitForBitIn
);
parameter outByteSize = 1;
// 'public' variables
input spiClock;
input start;
input bitIn;
output [(outByteSize * 8) - 1:0] byteOut;
output reg finish;
input waitForBitIn;
// 'private' variables
wire... | 7.412213 |
module spireceiver (
input wire clk,
input wire rst_n,
input wire sclk,
input wire sdc,
input wire sdin
);
// internal states
parameter [2:0]
S_READ_BIT7 = 3'd0,
S_READ_BIT6 = 3'd1,
S_READ_BIT5 = 3'd2,
S_READ_BIT4 = 3'd3,
S_READ_BIT3 = 3'd4,
S_READ_BIT2 = 3'd5,
S_REA... | 7.224868 |
module spireg_tb ();
reg clk, nrst;
reg [63:0] txd, rxd;
reg sclk, nss;
wire mosi;
wire miso;
integer mosi_bsel;
integer ntest;
assign mosi = txd[mosi_bsel];
spireg_example #(
.ADDR_W(6),
.REG_W (16)
) spireg_example_inst (
.clk (clk),
.nrst(nrst),
.mosi(mosi),
... | 7.211135 |
module spirom_axi_fifo2
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 2,
parameter ADDR_W = 1
)
//-----------------------------------------------------------------... | 7.178559 |
module spirom_sbm_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//-----------------------------------------------------------------
... | 7.137436 |
module takes the SPI signals CPHA and CPOL
and producces a signal RS
that will control on what edge of the clock the SPI registers run.
If RS is 1; the register should toggle on the posedge
If RS is 0; the register should toggle on the negedge
As such:
If CPHA = 0 and CPOL = 0; RS = 0
If CPHA = 0 and CPOL = 1; RS ... | 8.02415 |
module of main.v. Send 48-bit cmd command `CMD`. Output is in `bitout`.
// Sending process will start on `start` HIGH (synchronous with negedge)
// Process finish is notified by `finish` HIGH (synchronous with negedge)
// Dependencies: main.v
// Revision: 1.00
// Revision 1.00 - Finished Read Operation
// Revision 0.01... | 8.048585 |
module spisequencer (
input wire clk,
/* Memory buffer signals. */
input wire [addr_bits - 1:0] buf_addr,
input wire [7:0] buf_wr_val,
output wire [7:0] buf_rd_val,
input wire buf_wr_en,
/* SPI transfer control signals. */
input wire [8:0] divider,
input wire xfer_star... | 8.489578 |
module spigpio (
clk,
cs,
sr_in,
gpioout,
sr_out
);
input clk, cs;
input sr_in;
output sr_out;
output [7:0] gpioout;
reg [7:0] gpioout;
reg sr_out;
wire rw;
reg [7:0] sr;
assign rw = sr[7];
always @(posedge clk) begin
if (cs == 1'b0) begin
sr_out <= sr[7];
s... | 6.590193 |
module SPISlaveInterface (
clk_in,
spi_sclk,
spi_mosi,
spi_miso,
spi_n_ss,
tx_buffer,
rx_buffer,
rx_ready,
rx_ready_ack,
nss_risen_stable_out
);
input clk_in;
input spi_sclk;
input spi_mosi;
output reg spi_miso;
input spi_n_ss;
input [7:0] tx_buffer;
reg [7:0] tx_... | 7.551734 |
module altera_avalon_packets_to_master_inst_for_spichain_out_stream_arbitrator (
// inputs:
altera_avalon_packets_to_master_inst_for_spichain_out_stream_data,
altera_avalon_packets_to_master_inst_for_spichain_out_stream_endofpacket,
altera_avalon_packets_to_master_inst_for_spichain_out_stream_startofpac... | 7.767945 |
module altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_arbitrator (
// inputs:
altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_ready,
clk,
reset_n,
spislave_inst_for_spichain_avalon_streaming_source_data,
spislave_inst_for_spichain_avalon_streaming_source_... | 7.767945 |
module altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_arbitrator (
// inputs:
altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_channel,
altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_data,
altera_avalon_st_bytes_to_packets_inst_for_sp... | 7.767945 |
module altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_arbitrator (
// inputs:
altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_data,
altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_valid,
clk,
reset_n,
spislave_inst_for_spichain_aval... | 7.767945 |
module spislave_inst_for_spichain_avalon_streaming_sink_arbitrator (
// inputs:
altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_data,
altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_valid,
clk,
reset_n,
spislave_inst_for_spichain_avalon_streaming_sink_re... | 7.769557 |
module spislave_inst_for_spichain_avalon_streaming_source_arbitrator (
// inputs:
altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_ready_from_sa,
clk,
reset_n,
spislave_inst_for_spichain_avalon_streaming_source_data,
spislave_inst_for_spichain_avalon_streaming_source_valid,
... | 7.769557 |
module SPISlaveToAvalonMasterBridge_reset_clk_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGIST... | 7.403143 |
module test_bench
//;
// wire [ 31: 0] address_from_the_altera_avalon_packets_to_master_inst_for_spichain;
// wire [ 3: 0] byteenable_from_the_altera_avalon_packets_to_master_inst_for_spichain;
// reg clk;
// wire miso_to_and_from_the_spislave_inst_for_spichain;
// wire ... | 7.171211 |
module spislave_inst_for_spichain (
// inputs:
mosi,
nreset,
nss,
sclk,
stsinkdata,
stsinkvalid,
stsourceready,
sysclk,
// outputs:
miso,
stsinkready,
stsourcedata,
stsourcevalid
);
parameter SYNC_DEPTH = 2; /* Number of synchronizer stages for clock crossing... | 7.769557 |
module SPIslave_InternalComponent #(
// parametr to define the width of the address bus and the data bus
parameter WIDTH = 8
) (
// input internal bus from shift register
input wire [WIDTH-1:0] Data_sh,
// input internal control signal from FSM indicates address is valid to be captured
input w... | 7.618396 |
module SPIslave_SHregister #(
// parametr to define the width of the address bus and the data bus
parameter WIDTH = 8
) (
// input bus to the system from REG file as read data
input wire [WIDTH-1:0] Rd_Data,
// input signal to the system from the master (master output salve input)
input wire M... | 8.255097 |
module SPIslave_Top #(
// parametr to define the width of the address bus and the data bus
parameter WIDTH = 8
) (
// input bus to the system from REG file as read data
input wire [WIDTH-1:0] Rd_Data,
// input signal to the system from the master (master output salve input)
input wire MOSI,
... | 9.140751 |
module combining the SPI Minion, SPI Minion Adapter, and Loopthrough
// This is the standard SPI stack used in the efabless tapeout in 2022.
// Author : Jack Brzozowski
// Date : May 7th, 2022
`ifndef SPI_V3_COMPONENTS_SPI_STACK_V
`define SPI_V3_COMPONENTS_SPI_STACK_V
`include "SPI_v3/components/LoopThroughVRTL.v... | 9.386012 |
module spitest_avr (
output wire spick,
output reg spics_n,
output wire spido,
input wire spidi
);
reg aclk;
reg spistart;
wire spirdy;
reg [7:0] spidin;
wire [7:0] spidout;
// clock gen
initial begin
aclk = 1'b0;
forever #`AVR_HALF_PERIOD aclk = ~aclk;
end
// s... | 6.599071 |
module spitest_rom (
input wire [18:0] in_addr,
output reg [7:0] out_word
);
integer fd;
reg [7:0] mem[0:524287];
initial begin
// init rom
integer i;
for (i = 0; i < 524288; i = i + 1) mem[i] = 8'hFF;
// load file
fd = $fopen("spitest.bin", "rb");
if (37 != $fread(mem, fd... | 6.619457 |
module spitoi2c (
input start,
input [7:0] data,
input clk,
input reset,
output i2c_sda,
output i2c_scl
);
//wire mosi;
wire ss;
wire din;
wire done;
wire siso;
wire [7:0] in;
wire i2cmreset;
spi_fsm spi_fsm1 (
.clk(clk),
.reset(reset),
.data(data),
.sta... | 6.506946 |
module: spitoi2c
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module spitoi2ct;
// Inputs
reg start;
reg [7:0] data;
reg clk;
reg reset;
// Outputs
wire i2c_sda;
wire i2c_scl;
... | 6.515775 |
module xip_regs (
input wire clk,
input wire rst_n,
// APB Port
input wire apbs_psel,
input wire apbs_penable,
input wire apbs_pwrite,
input wire [15:0] apbs_paddr,
input wire [31:0] apbs_pwdata,
output wire [31:0] apbs_prdata,
output wire apbs_pready,
output wire apbs_pslve... | 8.425532 |
module SPI_16bit (
input wire clk_in,
input wire rst,
input wire SPI_MOSI,
input wire SPI_CS,
input wire SPI_SCLK,
input wire [15:0] tx_data,
output reg SPI_MISO,
output reg [15:0] rx_data,
output reg rx_flag
);
reg [15:0] rx_buf;
reg [15:0] tx_buf;
reg [2:0] state = 0;
... | 6.743084 |
module spi_16i_16o (
sclk,
pdi,
pdo,
send,
data_valid,
cs,
sdi,
sdo
);
input wire sclk;
input wire [15:0] pdi;
input wire send;
input wire sdi;
output reg cs;
output wire sdo;
output reg [15:0] pdo;
output reg data_valid;
reg last_send; // for edge detection of send
... | 6.733825 |
module SPI_3_to_2_tb;
parameter Reand_Delay = 1;
parameter SPI_Command_Len = 16;
parameter SPI_Sys_Clock_Half_Div = 27;
reg SPI_SYNC ;
wire Control_Test ;
reg nReset ;
reg Clock_108M ;
reg SPI_SI_Fr_M ;
wire Control_Clock_Delay ;
wire SPI_SO_To_M ;
wire Slave... | 6.976381 |
module spi_7seg_controller (
MAX10_CLK1_50,
GPIO,
KEY,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5
);
input MAX10_CLK1_50;
input [35:0] GPIO;
input [1:0] KEY;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
wire sys_clk = MAX10_CLK1_50;
wire sys_rst_n = KEY[1];
w... | 8.176312 |
module SPI_AD (
input SPI_CLK,
input New_Word,
input [12:0] Addr,
input [ 7:0] Data,
output reg [ 7:0] q,
input RW, //1 Write; 0 :read
output reg SPI_CS,
inout reg SPI_Data,
output reg Over
);
reg [15:0] CM... | 6.754558 |
module spi_ad9268 #(
parameter tsckw = 5
) (
// Local bus interface
input clk, // local clock
input strobe, // bus strobe
input ce, // clock enable / module select
input rd, // read/write
output reg ack, // ack from the mod... | 7.15698 |
module SPI_ADC (
input clk,
input miso,
input measure_start,
output reg sck = 1,
output reg cs = 1,
output reg [15:0] data_out = 0,
output reg enable = 0
);
reg [15:0] count = 0;
reg [5:0] countsck = 0;
reg [5:0] countdatai = 0;
reg [5:0] i = 0;
reg [15:0] datain = 0;
reg flag_d... | 6.573293 |
module spi_addressing (
input clk,
input rst,
// SPI Signals
output spi_miso,
input spi_mosi,
input spi_sck,
input spi_ss,
// Register interface signals
output [5:0] reg_addr,
output write,
output new_req,
output [7:0] write_value,
input [7:0] read_value,
out... | 7.159558 |
module tf_Test_SPI;
// Inputs
reg st;
reg clk;
reg [11:0] MTX_DAT;
reg RESET;
reg [11:0] STX_DAT;
// Outputs
wire LOAD;
wire SCLK;
wire MOSI;
wire [11:0] MRX_DAT;
wire [11:0] sr_MTX;
wire [11:0] sr_MRX;
wire [7:0] cb_bit;
wire ce_tact;
wire MISO;
wire [11:0] sr_STX;
wire [11:0] sr_... | 6.66783 |
module spi_avalon_pio (
clk_clk,
pio_data_export,
reset_reset_n,
spi_bridge_mosi_to_the_spislave_inst_for_spichain,
spi_bridge_nss_to_the_spislave_inst_for_spichain,
spi_bridge_miso_to_and_from_the_spislave_inst_for_spichain,
spi_bridge_sclk_to_the_spislave_inst_for_spichain
);
input clk_... | 7.467778 |
module spi_axi_slave_tb ();
// HELPER
function integer clogb2;
input integer value;
integer i;
begin
clogb2 = 0;
for (i = 0; 2 ** i < value; i = i + 1) clogb2 = i + 1;
end
endfunction
localparam tries = 512;
localparam sword = 32;
localparam impl = 0;
localparam syncing = 0;... | 7.287623 |
module spi_bidir_clgen (
clk_in,
rst,
go,
enable,
last_clk,
divider,
clk_out,
pos_edge,
neg_edge
);
parameter Tp = 1;
input clk_in; // input clock (system clock)
input rst; // reset
input enable; // clock enable
input go; // start transfer
input last_clk; // last c... | 6.931618 |
module BIST (
input wire clk,
input wire reset,
input wire master_writeread,
input wire [7:0] MOSI_user_input,
input wire [7:0] MISO_user_input,
input wire select,
output wire CS,
output wire S_clk,
output wire [3:0] counter,
output wire MOSI_res,
output wire MISO_res,
ou... | 8.224113 |
module Cmp (
input wire clk,
input wire select,
input wire [4:0] count,
input wire [7:0] MOSI_in_data,
input wire [7:0] MOSI_out_data,
input wire [7:0] MISO_in_data,
input wire [7:0] MISO_out_data,
output wire MOSI_result,
output wire MISO_result
);
reg MOSI_res;
reg MISO_res;
... | 7.700968 |
module BIST_tb;
reg clk;
reg reset;
reg master_writeread;
reg [7:0] MOSI_user_input;
reg [7:0] MISO_user_input;
reg select;
wire CS;
wire S_clk;
wire [3:0] counter;
wire MOSI_res;
wire MISO_res;
wire [7:0] BIST_output;
BIST dut (
.clk(clk),
.reset(reset),
.master_writeread... | 6.526458 |
module spi_block (
clk,
out_bit,
in_bit,
data_out,
chip_select,
data_clk,
data_ready,
finished_reading,
reset
);
input clk;
input reset;
input finished_reading;
output out_bit;
output [7:0] data_out;
output data_ready;
//input wire in_bit;
wire shift_out_clk;
wire ... | 6.784186 |
module and the Zynq PS SPI interface.
//
// History:
// 02/23/19: Created
//
// License: BSD 3-Clause
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above c... | 7.982139 |
module spi_buttons (
// pins
input spi_mosi,
output spi_miso,
input spi_cs_n,
input spi_clk,
output irq_n,
input clk,
input resetq,
// outputs
output joystick_down,
output joystick_up,
output joystick_left,
output joystick_right,
output joystick_press,
ou... | 9.468796 |
module spi_byte (
input wire sysClk, // FPGA system clock (must be several times faster as SCLK, e.g. 66MHz)
input wire usrReset, // FPGA user reset button
input wire SCLK, // SPI clock (e.g. 4 MHz)
input wire MOSI, // SPI master out, slave in
output wire MISO, // SPI slave in... | 6.828003 |
module spi_byte_if (
input wire sysClk,
input wire usrReset,
input wire SCLK, // SPI clock
input wire MOSI, // SPI master out, slave in
output wire MISO, // SPI slave in, master out
input wire SS, // SPI slave select
output wire ... | 9.48502 |
module spi_chunk (
input CLK,
input RST,
inout SDIO,
output reg SCLK,
output reg CSB,
input [7:0] data_i,
input read_i,
input start_i,
output reg [7:0] data_o,
output busy_o,
output finish_o
);
reg [1:0] state;
parame... | 7.111754 |
module spi_clgen (
clk_in,
rst,
go,
enable,
last_clk,
divider,
clk_out,
pos_edge,
neg_edge
);
parameter Tp = 1;
parameter SPI_DIVIDER_LEN = 8;
input clk_in; // input clock (system clock)
input rst; // reset
input enable; // clock enable
input go; // start transfer
... | 6.677874 |
module spi_clkgen (
input clk_in, // input clock (system clock)
input rst, // reset
input enable, // clock enable
input go, // start transfer
input last_clk, // last clock
input [31:0] divider, // clock divid... | 6.539467 |
module spi_clk_gen #(
parameter SPI_RATIO_GRADE = 3
) ( /*AUTOARG*/
// Outputs
spi_clk_o,
// Inputs
clk_i,
arst_n_i,
en_i,
ratio_i
);
/* ports */
input clk_i;
input arst_n_i;
input en_i;
input [SPI_RATIO_GRADE-1:0] ratio_i;
output spi_clk_o;
/* ratio-driven clock generat... | 6.897232 |
module spi_clock_gen #(
parameter Nc=6, //Разрядность количества импульсов, которые надо сгенерировать
THalfSpiClk = 10, //Полупериод SPI Clock в тактах clk
TCS=20 //Время между приходом строба start и первым импульсом spi_clk
) (
input rst, //Асинхронный сброс
input clk... | 7.887818 |
module spi_clock_generator (
//CLK
// i_clk is the system clock (10-200MHz)
input i_clk,
//RST
// i_reset is the system reset. This is a active high signal.
// '1' : reset is active
input i_reset,
//Controll inputs from registers
input i_spr0,
input i_spr1,
input i_cpol... | 7.887818 |
module spi_cmd_sm (
output wire SPI_CMD_reading,
input wire SPI_done,
input wire clk,
input wire reset
);
// state bits
parameter IDLE = 1'b0, // SPI_CMD_reading=0
READING = 1'b1; // SPI_CMD_reading=1
reg state;
reg nextstate;
// comb always block
always @* begin
// Warning I... | 8.36777 |
module spi_masterf (
input clk,
rst,
miso, // flag = 0 means data from slave to master and vice versa
input [1:0] slave,
dtf,
output reg sclk,
mosi,
ssb1,
ssb2
);
reg [7:0] stor_reg1, stor_reg2;
reg [2:0] k, p;
always @(clk) begin
if (rst) begin
stor_reg1 = 8'b0111... | 7.746324 |
module spi_slave1f (
input sclk,
mosi,
ssb,
input [1:0] dtf, // flag = 0 means data from slave to master and vice versa
output reg miso
);
reg [7:0] stor_reg1, stor_reg2;
reg [2:0] i, j;
initial begin
stor_reg2 = 8'b01010010;
i = 0;
j = 0;
end
always @(posedge sclk) begin
... | 7.116147 |
module spi_slave2f (
input sclk,
mosi,
ssb,
input [1:0] dtf, // flag = 0 means data from slave to master and vice versa
output reg miso
);
reg [7:0] stor_reg1, stor_reg2;
reg [2:0] i, j;
initial begin
stor_reg2 = 8'b01010010;
i = 0;
j = 0;
end
always @(posedge sclk) begin
... | 7.141492 |
module spi_topf (
clk,
rst,
miso,
mosi,
dtf,
sclk,
ssb1,
ssb2,
slave
);
input clk, rst;
inout miso, mosi;
inout sclk, ssb1, ssb2;
input [1:0] slave, dtf;
wire miso1, miso2;
assign miso = ((slave == 2'b01) ? miso1 : miso2) && ((dtf == 2'b01) || (dtf == 2'b11));
spi_maste... | 7.052945 |
module spi_config #(
parameter SPI_MAX_WIDTH_LOG = 4
) (
input clk,
rst_n, // Asynchronous reset active low
/*
test
*/
input config_req,
input [SPI_MAX_WIDTH_LOG + 1:0] config_data,
output reg cpol,
output reg cpha,
output reg [SPI_MAX_WIDTH_LOG - 1:0] spi_width
);
always @(pos... | 7.074612 |
module spi_control #(
parameter CFG_FRAME_SIZE = 4
) (
input aresetn,
input sresetn,
input psel,
input penable,
input pwrite,
input [ 6:0] paddr,
input [CFG_FRAME_SIZE-1... | 7.409405 |
module spi_core (
input wire i_clk,
input wire i_reset_n,
// SPI bus
input wire i_spi_cs_n,
input wire i_spi_sck,
input wire i_spi_si,
output wire o_spi_so,
//
input wire [7:0] i_wr_data,
output wire [7:0] o_rd_data,
output wire o_last_bit
);
reg r_spi_cs_n, r_spi_sck, r_s... | 7.598117 |
module adc (
sdo,
spi_clk,
clk,
rst,
conv
);
parameter WIDTH = 14; //multiple of two
parameter PATTERN = {WIDTH / 2{2'b10}};
parameter COUNTMAX = 34;
input rst, conv, spi_clk, clk;
output sdo;
reg [WIDTH-1:0] mem;
reg sdo;
reg flag;
reg [6:0] count;
integer N;
initial beg... | 7.467564 |
module amp (
spi_clk,
reset,
cs,
din,
dout,
gain_state
);
parameter Tp = 1;
input spi_clk, reset, cs, din;
output dout;
output [7:0] gain_state;
reg [0:7] data;
reg [7:0] gain_state;
reg temp, dout;
always @(cs or reset) begin
if (reset) gain_state <= 'bz;
else gain_... | 6.993726 |
module dac (
spi_clk,
reset,
cs,
din,
dout,
command,
dacN,
dacDATA
);
parameter Tp = 1;
input spi_clk, reset, cs, din;
output [3:0] command;
output [3:0] dacN;
output [11:0] dacDATA;
output dout;
reg [0:31] data;
reg dout;
reg temp;
assign command = data[0:3];
a... | 7.762087 |
module spi_clgen (
clk_in,
rst,
go,
enable,
last_clk,
divider,
clk_out,
pos_edge,
neg_edge
);
parameter Tp = 1;
input clk_in; // input clock (system clock)
input rst; // reset
input enable; // clock enable
input go; // start transfer
input last_clk; // last clock
... | 6.677874 |
module spi_shift_in (
clk,
rst,
go,
pos_edge,
neg_edge,
rx_negedge,
tip,
last,
p_out,
s_clk,
s_in
);
parameter Tp = 1;
input clk; // system clock
input rst; // reset
// input [`SPI_ADC_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
input go; /... | 7.4541 |
module spi_shift_out (
clk,
rst,
len,
lsb,
go,
pos_edge,
neg_edge,
tx_negedge,
capture,
tip,
last,
p_in,
s_out
);
parameter Tp = 1;
input clk; // system clock
input rst; // reset
input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
input ... | 7.503529 |
module spi_core_fast (
input wire clk, // main clock
input wire rst, // synchronous reset
input wire en, // enable signal, flag to start transmitting
input wire [DATA_BITS-1:0] din, // data to sent out
output reg [DATA_BITS-1:0] dout, // data received in
output reg ack, // data sent/receiv... | 7.879942 |
module spi_crc16 (
rst,
clk,
gen_en,
out_en,
din,
dout,
load_start_tkn,
load_multi_blk_wr_tkn,
crc_reg
);
input rst;
input clk;
input gen_en;
input out_en;
input din;
output dout;
input load_start_tkn;
input load_multi_blk_wr_tkn;
output [15:0] crc_reg;
wire rst... | 7.633748 |
module takes the first two spi transfers
// and uses the values taken from them to simulate
// a chip select and select a pin to use for slave out.
//
// After the start condition is pulsed the following values are decoded:
// first 8 bits = Pin to use for chip select or 0xFF for invalid
// second 8 bits = Byte cycles ... | 8.342096 |
module spi_ctrl (
fpga_0_RS232_RX_pin,
fpga_0_RS232_TX_pin,
fpga_0_clk_1_sys_clk_pin,
fpga_0_rst_1_sys_rst_pin,
Generic_SPI_MISO_I_pin,
Generic_SPI_MOSI_O_pin,
Generic_SPI_SCK_O_pin,
Generic_SPI_SS_O_pin,
Generic_GPIO_GPIO_IO_O_pin
);
input fpga_0_RS232_RX_pin;
output fpga_0_RS23... | 6.929849 |
module spi_ctrl_reduced (
clk,
rst_n,
sck,
mosi,
miso,
cs_n,
spi_tx_en,
spi_rx_en,
mode_select,
receive_status
);
parameter DATA_LENGTH = 64;
input clk, rst_n, miso;
input mode_select;
output sck, mosi, cs_n;
output receive_status;
input spi_tx_en;
input spi_rx_... | 8.088552 |
module spi_ctrl_stub (
fpga_0_RS232_RX_pin,
fpga_0_RS232_TX_pin,
fpga_0_clk_1_sys_clk_pin,
fpga_0_rst_1_sys_rst_pin,
Generic_SPI_MISO_I_pin,
Generic_SPI_MOSI_O_pin,
Generic_SPI_SCK_O_pin,
Generic_SPI_SS_O_pin,
Generic_GPIO_GPIO_IO_O_pin
);
input fpga_0_RS232_RX_pin;
output fpga_0... | 7.114411 |
module spi_ctrl (
fpga_0_RS232_RX_pin,
fpga_0_RS232_TX_pin,
fpga_0_clk_1_sys_clk_pin,
fpga_0_rst_1_sys_rst_pin,
Generic_SPI_MISO_I_pin,
Generic_SPI_MOSI_O_pin,
Generic_SPI_SCK_O_pin,
Generic_SPI_SS_O_pin,
Generic_GPIO_GPIO_IO_O_pin
);
input fpga_0_RS232_RX_pin;
output fpga_0_RS23... | 6.929849 |
module SPI_DAC8512 (
output wire SDAT, // .
input st,
output wire SCLK, // .
input clk,
output reg NCS = 1, // .
input [11:0] DI,
output reg NLD = 1, // .
output wire ce, //
output reg [3:0] cb_bit = 0
); // .
parameter Tsclk = 80; //Tsclk=Tcl+Tch=40+40 ns
reg [11:0] sr_d... | 6.577009 |
module spi_dac_out (
clk,
reset,
spi_sck,
spi_sdo,
spi_dac_cs,
ena_out,
deltaS_out,
data_in,
cycles
);
input clk;
input reset;
output spi_sck;
output spi_sdo;
output spi_dac_cs;
output ena_out;
output deltaS_out;
input [11:0] data_in;
input [11:0] cycles; // total ... | 7.524932 |
module spi_datapath_master #(
parameter SPI_MAX_WIDTH_LOG = 4
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
//config
input cpha,
//control flow
input sck_first_edge,
sck_second_edge,
input spi_start,
//spi
input miso,
output mosi,
//data... | 7.269792 |
module spi_datapath_slave #(
parameter SPI_MAX_WIDTH_LOG = 4
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
//config
input cpha,
//control flow
input sck_first_edge,
sck_second_edge,
input spi_start,
//spi
output miso,
input mosi,
//data
... | 7.269792 |
module SPI_DCS_if #(
parameter width_addr = 8,
parameter width_data = 16
) (
input wire clk,
input wire rst_n,
input wire spi_scl,
input wire spi_sdi,
output reg spi_sdo,
input wire spi_cs_addr,
input wire spi_cs_data,
input wire [width_data-1:0] Din,
output reg [wid... | 8.562424 |
module spi_debug_ifc (
input spi_clk,
input spi_cs_i,
input spi_data_i,
output spi_data_o,
input sys_clk,
output sys_wr_o,
output [15:0] sys_waddr_o,
output [15:0] sys_wdata_o
);
reg [15:0] spi_shift = 16'd0;
reg [16:0] spi_data = 17'd0;
reg [3:0] spi_count = 4'd0;
reg spi_signa... | 7.025411 |
module spi_decoder #(
parameter DATA_SIZE = 8 // The size of the parallel output data.
) (
//
// ------- Inputs -------
//
input I_sclk, // Serial data clock
input I_enable, // Enable for the decoder
input I_sdi, ... | 7.538646 |
module SPI_Demo_tb;
reg Clock;
reg Reset;
wire ready;
reg send;
wire arrived;
reg [7:0] data;
wire [7:0] dataO;
wire arrivedS;
reg [7:0] dataS;
wire [7:0] dataSO;
wire SCLK;
wire MISO;
wire MOSI;
wire CS;
SPI_Demo mdl (
Clock,
Reset,
ready,
send,
arrived,
... | 6.945999 |
module spi_detector #(
parameter FREQ = 12'hfff
) (
input wire CLK,
input wire RST,
input wire SCLK,
output wire DETECT
);
reg [11:0] r_timer;
reg [ 7:0] r_counter;
reg [ 7:0] r_capture0;
reg [ 7:0] r_capture1;
//============================================================
// spi cl... | 7.385287 |
module spi_dev_arb #(
parameter integer N = 1,
// auto
parameter integer NL = N - 1,
parameter integer DL = (8 * N) - 1
) (
// Upstream
output wire us_req,
input wire us_gnt,
output reg [7:0] us_rdata,
output reg us_rstb,
// Downstream
input wire [NL:0] ds_req,
... | 6.943197 |
module spi_dev_core_tb;
// Signals
reg rst = 1'b1;
reg clk_slow = 1'b0;
reg clk_fast = 1'b0;
wire spi_mosi;
wire spi_miso;
wire spi_cs_n;
wire spi_clk;
wire [7:0] usr_mosi_data;
wire usr_mosi_stb;
reg [7:0] usr_miso_data;
wire usr_mis... | 7.107739 |
module spi_dev_ezwb #(
parameter integer WB_N = 3,
// auto
parameter integer DL = (32 * WB_N) - 1,
parameter integer CL = WB_N - 1
) (
// SPI interface
output wire spi_miso,
input wire spi_mosi,
input wire spi_clk,
input wire spi_cs_n,
// Wishbone
output reg [31:0] wb_w... | 8.755922 |
module spi_dev_lcdpalwr #(
// LSB must be 0 and it uses
// CMD_BYTE and CMD_BYTE+1
parameter [7:0] CMD_BYTE = 8'he4
) (
// LCD PHY drive
output wire [7:0] phy_data,
output wire phy_rs,
output reg phy_valid,
input wire phy_ready,
// SPI protocol wrapper interface
... | 7.652795 |
module spi_dev_lcdwr #(
// LSB must be 0 and it uses
// CMD_BYTE and CMD_BYTE+1
parameter [7:0] CMD_BYTE = 8'hf2
) (
// LCD PHY drive
output reg [7:0] phy_data,
output reg phy_rs,
output reg phy_valid,
input wire phy_ready,
// SPI protocol wrapper interface
... | 9.783844 |
module spi_dev_memwr #(
parameter [7:0] CMD_BYTE = 8'he0,
parameter integer DATA_WIDTH = 16,
parameter integer ADDR_WIDTH = 23, // Word-address
parameter integer BURST_LEN = 64, // In words
// auto-set
parameter integer DL = DATA_WIDTH - 1,
parameter integer AL = ADDR_WIDTH - 1
) (
//... | 7.967197 |
module spi_dev_scmd #(
parameter [7:0] CMD_BYTE = 8'h00,
parameter integer CMD_LEN = 4,
parameter integer CMD_REPEAT = 0,
// auto
parameter integer DL = (8 * CMD_LEN) - 1
) (
// Protocol wrapper interface
input wire [7:0] pw_wdata,
input wire pw_wcmd,
input wire pw_wstb,... | 7.884751 |
module spi_dev_to_wb_tb;
// Signals
reg rst = 1'b1;
reg clk = 1'b0;
reg [ 7:0] pw_wdata;
reg pw_wcmd;
reg pw_wstb;
reg pw_end;
wire [31:0] wb_wdata;
wire [95:0] wb_rdata;
wire [23:0] wb_addr;
wire wb_we;
wire [ 2:0] wb_cyc;
reg [ 2:0] wb_ack;... | 6.963367 |
module spi_encoder #(
parameter DATA_SIZE = 8 // The size of the parallel input data.
) (
//
// ------- Inputs -------
//
input I_sclk, // Serial data clock
input I_enable, // Enable for the decoder
input I_latch, // Latch for... | 7.663643 |
module spi_fast (
// SPI pads
input wire spi_mosi,
output wire spi_miso,
input wire spi_cs_n,
input wire spi_clk,
// Interface
output reg [7:0] addr,
output reg [7:0] data,
output wire first,
output wire last,
output reg strobe,
input wire [7:0] out,
// Clock / ... | 7.545359 |
module spi_fast_core_tb;
// Signals
reg rst = 1'b1;
reg clk = 1'b0;
wire spi_mosi;
wire spi_miso;
wire spi_cs_n;
wire spi_clk;
wire [7:0] user_out;
wire user_out_stb;
wire [7:0] user_in;
wire user_in_ack;
wire csn_state;
wire csn_rise;
wire csn_fall;
// Setup recording
initial begi... | 7.177189 |
module spi_file (
// pins
input spi_mosi,
output spi_miso,
input spi_cs_n,
input spi_clk,
output irq_n,
input clk,
input resetq,
// input request
output file_request_ready,
input file_request_valid,
inpu... | 8.509388 |
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