code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module spiral_4 (
i_data,
o_data_18,
o_data_50,
o_data_75,
o_data_89
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input signed [18:0] i_data;
output signed [18+7:0] o_data_18;
output signed [18+7:0] o_data_50;
output signed [18+7:0] o_data_75;
output signed [18+7:0] o_data_89;
// ********************************************
//
// WIRE DECLARATION
//
// ********************************************
wire signed [25:0] w1, w8, w9, w16, w25, w4, w5, w80, w75, w89, w18, w50;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign w1 = i_data;
assign w8 = w1 << 3;
assign w9 = w1 + w8;
assign w16 = w1 << 4;
assign w25 = w9 + w16;
assign w4 = w1 << 2;
assign w5 = w1 + w4;
assign w80 = w5 << 4;
assign w75 = w80 - w5;
assign w89 = w9 + w80;
assign w18 = w9 << 1;
assign w50 = w25 << 1;
assign o_data_18 = w18;
assign o_data_50 = w50;
assign o_data_75 = w75;
assign o_data_89 = w89;
endmodule
| 6.755767 |
module spiral_8 (
i_data,
o_data_9,
o_data_25,
o_data_43,
o_data_57,
o_data_70,
o_data_80,
o_data_87,
o_data_90
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input signed [17:0] i_data;
output signed [17+7:0] o_data_9;
output signed [17+7:0] o_data_25;
output signed [17+7:0] o_data_43;
output signed [17+7:0] o_data_57;
output signed [17+7:0] o_data_70;
output signed [17+7:0] o_data_80;
output signed [17+7:0] o_data_87;
output signed [17+7:0] o_data_90;
// ********************************************
//
// WIRE DECLARATION
//
// ********************************************
wire signed [24:0] w1,
w4,
w5,
w8,
w9,
w16,
w25,
w36,
w35,
w40,
w45,
w3,
w43,
w48,
w57,
w96,
w87,
w70,
w80,
w90;
assign w1 = i_data;
assign w4 = w1 << 2;
assign w5 = w1 + w4;
assign w8 = w1 << 3;
assign w9 = w1 + w8;
assign w16 = w1 << 4;
assign w25 = w9 + w16;
assign w36 = w9 << 2;
assign w35 = w36 - w1;
assign w40 = w5 << 3;
assign w45 = w5 + w40;
assign w3 = w4 - w1;
assign w43 = w3 + w40;
assign w48 = w3 << 4;
assign w57 = w9 + w48;
assign w96 = w3 << 5;
assign w87 = w96 - w9;
assign w70 = w35 << 1;
assign w80 = w5 << 4;
assign w90 = w45 << 1;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign o_data_9 = w9;
assign o_data_25 = w25;
assign o_data_43 = w43;
assign o_data_57 = w57;
assign o_data_70 = w70;
assign o_data_80 = w80;
assign o_data_87 = w87;
assign o_data_90 = w90;
endmodule
| 6.75681 |
module spiral_move (
clk,
rst,
done_spin,
enable,
output_speed,
motion_command
);
parameter done_time = 32'd200; //Original=20000
parameter STOP = 2'b00;
parameter STRAIGHT = 2'b01;
parameter TURN = 2'b10;
parameter COUNT_UP = 2'b11; //used for counting straight states
parameter TURN_45 = 10'b01_0010_1101;
parameter GO_STRAIGHT = 10'b00_0000_0000;
input clk, rst;
input enable;
input done_spin;
output [2:0] output_speed;
output [9:0] motion_command;
reg [2:0] output_speed;
reg [2:0] next_speed;
reg [9:0] motion_command;
reg [9:0] next_command;
reg [1:0] state;
reg [1:0] next_state;
reg [7:0] straight_count; //how many times it's gone straight per spiral. Resets at the end of every spiral
reg [31:0] k; //the constant we will multiply done_times by.
reg [31:0] straight_length; //done_time*k
reg [31:0] straight_time; //how long it's been going straight
always @(posedge clk) begin
if (rst) begin //gloabl reset
state <= STOP;
motion_command <= GO_STRAIGHT;
output_speed <= 3'b000;
straight_time <= 32'b0;
k <= 32'b1;
straight_count <= 8'b0;
end else begin
state <= next_state;
output_speed <= next_speed;
motion_command <= next_command;
if (state == STRAIGHT) begin //if going straight increment straight time
straight_time <= straight_time + 1;
end else begin //if turning or stopped reset straight time to 0
straight_time <= 32'b0;
if (state == COUNT_UP) begin //COUNT_UP only lasts one clk tick
if (straight_count == 6) begin //if between the 7th and 8th leg increment k, reset straight_count
straight_count <= 8'b0;
k <= k + 1'b1;
end//if
else begin //increment straight_count
straight_count <= straight_count + 8'b1;
end //else
end else if (state == STOP) begin //reset k and straight_count on STOP
straight_count <= 8'b0;
k <= 32'b1;
end //else if
end //else
end //else
end //always
always @(state or straight_time or rst or enable or k or done_spin) begin
straight_length <= done_time * k; //recalculate straight_length
case (state)
STOP: begin
if (enable) begin //start going straight on enable
next_state <= STRAIGHT;
next_speed <= 3'b011;
next_command <= GO_STRAIGHT;
end//if
else begin //stay stopped without enable
next_state <= STOP;
next_speed <= 3'b000;
next_command <= GO_STRAIGHT;
end //else
end //end STOP state
STRAIGHT: begin
if (enable) begin
if (straight_time < straight_length) begin //keep going straight
next_state <= STRAIGHT;
next_speed <= 3'b011;
next_command <= GO_STRAIGHT;
end else begin // if it's done going straight count up straight_count or k
next_state <= COUNT_UP;
next_speed <= 3'b000;
next_command <= GO_STRAIGHT;
end
end //if
else begin //if enable is low go back to STOP state
next_state <= STOP;
next_speed <= 3'b000;
next_command <= GO_STRAIGHT;
end //else
end // STRAIGHT state
COUNT_UP: begin //lasts only 1 clk tick. Used for incrementing k and straight_count appropriately
if (enable) begin
next_state <= TURN;
next_speed <= 3'b011;
next_command <= TURN_45;
end//if
else begin //go back to stop if not enabled
next_state <= STOP;
next_speed <= 3'b000;
next_command <= GO_STRAIGHT;
end //else
end //COUNT_UP state
TURN: begin
if (enable) begin
if (done_spin) begin //if done spinning go straight
next_state <= STRAIGHT;
next_speed <= 3'b011;
next_command <= GO_STRAIGHT;
end//if
else //keep spinning
next_state <= TURN;
next_speed <= 3'b011;
next_command <= TURN_45;
end//else
else begin //if enable is low go back to STOP state
next_state <= STOP;
next_speed <= 3'b000;
next_command <= GO_STRAIGHT;
end //else
end // TURN state
endcase
end //always
endmodule
| 8.204679 |
module spiral_move_tb;
reg clk, rst;
reg enable;
reg done_spin;
wire [2:0] output_speed;
wire [9:0] motion_command;
spiral_move SP (
.clk(clk),
.rst(rst),
.enable(enable),
.done_spin(done_spin),
.output_speed(output_speed),
.motion_command(motion_command)
);
initial begin
$stop;
clk = 1'b0;
rst = 1'b0;
enable = 1'b0;
done_spin = 1'b0;
#500 $stop;
end
initial begin
$dumpfile("Spiral Move.vcd");
$dumpvars;
end
always begin
#25 clk = !clk;
end
initial begin
#50 rst = 1'b1;
#50 rst = 1'b0;
#500 enable = 1'b0;
#2000 enable = 1'b1;
#2000 done_spin = 1'b1;
#2000 done_spin = 1'b0;
#2000 $stop;
end
endmodule
| 6.797452 |
module spiRead (
spiClock,
start,
bitIn,
finish,
byteOut,
waitForBitIn
);
parameter outByteSize = 1;
// 'public' variables
input spiClock;
input start;
input bitIn;
output [(outByteSize * 8) - 1:0] byteOut;
output reg finish;
input waitForBitIn;
// 'private' variables
wire _start;
assign _start = start;
reg _running = 0, _waiting = 0;
reg [(outByteSize * 8) - 1:0] inputBuffer = 0;
reg [outByteSize + 3:0] _i;
assign byteOut = _running ? 'bZ : inputBuffer;
reg _error = 0;
// main //
always @(posedge spiClock) begin
if (_start && ~_running && ~_waiting) begin
// initial
if (~waitForBitIn || ~bitIn) begin
inputBuffer <= {{(outByteSize * 8 - 1) {1'b0}}, bitIn};
finish <= 0;
_running <= 1;
_i <= (outByteSize * 8) - 1; // Read the last 7 bits, first bit is always 0;
end
end else if (_start && _running && ~_waiting) begin
// looping
_i = _i - 1;
inputBuffer <= {inputBuffer[(outByteSize*8)-2:0], bitIn};
if (_i == 0) begin
// end
finish <= 1;
_running <= 0;
_waiting <= 1;
end
end else if (_start && _waiting) begin
//do nothing while waiting
end else if (~_start) begin
finish <= 0;
_waiting <= 0;
end else begin
_error = 1;
end
end
endmodule
| 7.412213 |
module spireceiver (
input wire clk,
input wire rst_n,
input wire sclk,
input wire sdc,
input wire sdin
);
// internal states
parameter [2:0]
S_READ_BIT7 = 3'd0,
S_READ_BIT6 = 3'd1,
S_READ_BIT5 = 3'd2,
S_READ_BIT4 = 3'd3,
S_READ_BIT3 = 3'd4,
S_READ_BIT2 = 3'd5,
S_READ_BIT1 = 3'd6,
S_READ_BIT0 = 3'd7;
reg [2:0] r_state;
reg r_sdc, r_print;
reg [7:0] r_word;
// print the current word
task print_word();
begin
if (r_sdc) $display("received data: %08b (%02x)", r_word, r_word);
else $display("received command: %08b (%02x)", r_word, r_word);
end
endtask
always @(negedge clk) begin
if (rst_n) begin
r_state <= S_READ_BIT7;
if (r_print) begin
r_print <= 1'b0;
print_word();
end
end else r_print <= 1'b0;
end
// sample inputs on sclk (negative edge, SPI clock is "active low")
always @(negedge sclk) begin
if (rst_n == 1'b1) begin
r_sdc <= sdc;
r_word <= r_word << 1;
r_word[0] <= sdin;
case (r_state)
S_READ_BIT7: r_state <= S_READ_BIT6;
S_READ_BIT6: r_state <= S_READ_BIT5;
S_READ_BIT5: r_state <= S_READ_BIT4;
S_READ_BIT4: r_state <= S_READ_BIT3;
S_READ_BIT3: r_state <= S_READ_BIT2;
S_READ_BIT2: r_state <= S_READ_BIT1;
S_READ_BIT1: r_state <= S_READ_BIT0;
S_READ_BIT0: r_state <= S_READ_BIT7;
endcase
r_print <= r_state == S_READ_BIT0;
end
end
endmodule
| 7.224868 |
module spireg_tb ();
reg clk, nrst;
reg [63:0] txd, rxd;
reg sclk, nss;
wire mosi;
wire miso;
integer mosi_bsel;
integer ntest;
assign mosi = txd[mosi_bsel];
spireg_example #(
.ADDR_W(6),
.REG_W (16)
) spireg_example_inst (
.clk (clk),
.nrst(nrst),
.mosi(mosi),
.miso(miso),
.sclk(sclk),
.nss (nss)
);
task run_clks(input integer n);
integer i;
for (i = 0; i < n; i = i + 1) begin
#1 clk = 1;
#1 clk = 0;
end
endtask
task run_spi(input integer bits, input integer dly);
integer i;
begin
sclk = 0;
nss = 0;
mosi_bsel = bits - 1;
run_clks(dly);
for (i = 0; i < bits; i = i + 1) begin
//sample input
rxd = {rxd[62:0], miso};
//send rising edge
sclk = 1;
run_clks(dly);
//change output
txd = {txd[62:0], 1'b0};
//send falling edge
sclk = 0;
run_clks(dly);
end
nss = 1;
run_clks(dly);
end
endtask
task dump_rxd(input integer bits);
integer i;
if (bits > 8) begin
$write("status: %b, bytes: ", rxd[(bits-8)+:8]);
for (i = bits / 8 - 2; i >= 0; i = i - 1) begin
$write("%h", rxd[(i*8)+:8]);
end
$write("\n");
end else if (bits == 8) begin
$display("status: %b", rxd[7:0]);
end
endtask
initial begin
clk = 0;
nrst = 0;
sclk = 0;
nss = 0;
txd = 0;
rxd = 0;
mosi_bsel = 0;
ntest = 0;
run_clks(4);
nrst = 1;
run_clks(32);
nss = 1;
run_clks(32);
//run test - read reg
ntest = 1;
rxd = 0;
txd = 24'h00_ffff; //read reg[0]
run_spi(24, 8);
dump_rxd(24); //status: 00000000, bytes: 0000
//run test - fastcmd
ntest = 2;
rxd = 0;
txd = 8'hc1;
run_spi(8, 8);
//run test - read reg
ntest = 3;
rxd = 0;
txd = 24'h00_ffff; //read reg[0]
run_spi(24, 8);
dump_rxd(24); //status: 00000001, bytes: 0100
//run test - fastcmd2
ntest = 4;
rxd = 0;
txd = 8'hc0;
ntest = 2;
run_spi(8, 8);
//run test - write reg
ntest = 5;
rxd = 0;
txd = 24'h8a_1010; //write reg[10]
run_spi(24, 8);
ntest = 6;
rxd = 0;
txd = 8'hbf; //write reg[63] and drop
run_spi(8, 8);
ntest = 7;
rxd = 0;
txd = 40'h82_0202_0303; //write reg[2,3]
run_spi(40, 8);
ntest = 8;
rxd = 0;
txd = 40'hbf_3f3f_dddd; //write reg[63,0]
run_spi(40, 8);
//run test - read reg
ntest = 9;
rxd = 0;
txd = 24'h00_ffff; //read reg[0]
run_spi(24, 8);
dump_rxd(24); //status: 11011101, bytes: dddd
ntest = 10;
rxd = 0;
txd = 40'h02_ffff_ffff; //read reg[2,3]
run_spi(40, 8);
dump_rxd(40); //status: 11011101, bytes: 02020303
ntest = 11;
rxd = 0;
txd = 40'h3f_0000_0000; //read reg[63,0]
run_spi(40, 8);
dump_rxd(40); //status: 11011101, bytes: 3f3fdddd
$stop;
end
endmodule
| 7.211135 |
module spirom_axi_fifo2
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 2,
parameter ADDR_W = 1
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
, input rst_i
, input [WIDTH-1:0] data_in_i
, input push_i
, input pop_i
// Outputs
, output [WIDTH-1:0] data_out_o
, output accept_o
, output valid_o
);
//-----------------------------------------------------------------
// Local Params
//-----------------------------------------------------------------
localparam COUNT_W = ADDR_W + 1;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [ WIDTH-1:0] ram [DEPTH-1:0];
reg [ ADDR_W-1:0] rd_ptr;
reg [ ADDR_W-1:0] wr_ptr;
reg [COUNT_W-1:0] count;
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @(posedge clk_i or posedge rst_i)
if (rst_i) begin
count <= {(COUNT_W) {1'b0}};
rd_ptr <= {(ADDR_W) {1'b0}};
wr_ptr <= {(ADDR_W) {1'b0}};
end else begin
// Push
if (push_i & accept_o) begin
ram[wr_ptr] <= data_in_i;
wr_ptr <= wr_ptr + 1;
end
// Pop
if (pop_i & valid_o) rd_ptr <= rd_ptr + 1;
// Count up
if ((push_i & accept_o) & ~(pop_i & valid_o)) count <= count + 1;
// Count down
else if (~(push_i & accept_o) & (pop_i & valid_o)) count <= count - 1;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
/* verilator lint_off WIDTH */
assign accept_o = (count != DEPTH);
assign valid_o = (count != 0);
/* verilator lint_on WIDTH */
assign data_out_o = ram[rd_ptr];
endmodule
| 7.178559 |
module spirom_sbm_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
, input rst_i
, input [WIDTH-1:0] data_in_i
, input push_i
, input pop_i
// Outputs
, output [WIDTH-1:0] data_out_o
, output accept_o
, output valid_o
);
//-----------------------------------------------------------------
// Local Params
//-----------------------------------------------------------------
localparam COUNT_W = ADDR_W + 1;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [ WIDTH-1:0] ram [DEPTH-1:0];
reg [ ADDR_W-1:0] rd_ptr;
reg [ ADDR_W-1:0] wr_ptr;
reg [COUNT_W-1:0] count;
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @(posedge clk_i or posedge rst_i)
if (rst_i) begin
count <= {(COUNT_W) {1'b0}};
rd_ptr <= {(ADDR_W) {1'b0}};
wr_ptr <= {(ADDR_W) {1'b0}};
end else begin
// Push
if (push_i & accept_o) begin
ram[wr_ptr] <= data_in_i;
wr_ptr <= wr_ptr + 1;
end
// Pop
if (pop_i & valid_o) rd_ptr <= rd_ptr + 1;
// Count up
if ((push_i & accept_o) & ~(pop_i & valid_o)) count <= count + 1;
// Count down
else if (~(push_i & accept_o) & (pop_i & valid_o)) count <= count - 1;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
/* verilator lint_off WIDTH */
assign accept_o = (count != DEPTH);
assign valid_o = (count != 0);
/* verilator lint_on WIDTH */
assign data_out_o = ram[rd_ptr];
endmodule
| 7.137436 |
module takes the SPI signals CPHA and CPOL
and producces a signal RS
that will control on what edge of the clock the SPI registers run.
If RS is 1; the register should toggle on the posedge
If RS is 0; the register should toggle on the negedge
As such:
If CPHA = 0 and CPOL = 0; RS = 0
If CPHA = 0 and CPOL = 1; RS = 1
If CPHA = 1 and CPOL = 0; RS = 1
If CPHA = 1 and CPOL = 1; RS = 0
Reference: http://www.byteparadigm.com/applications/introduction-to-i2c-and-spi-protocols/?/article/AA-00255/22/Introduction-to-SPI-and-IC-protocols.html
*/
module SPIRSMaker (CPHA, CPOL, RS);
//Define the Inputs and Outputs
input CPHA;
input CPOL;
output RS;
assign RS = CPHA ^ CPOL;
endmodule
| 8.02415 |
module of main.v. Send 48-bit cmd command `CMD`. Output is in `bitout`.
// Sending process will start on `start` HIGH (synchronous with negedge)
// Process finish is notified by `finish` HIGH (synchronous with negedge)
// Dependencies: main.v
// Revision: 1.00
// Revision 1.00 - Finished Read Operation
// Revision 0.01 - File Created
// Additional Comments: SET ON NEGEDGE!!!!
//////////////////////////////////////////////////////////////////////////////////
module spiSend(
spiClock,
start,
cmd,
bitout,
finish
);
parameter byteSize = 6;
// 'public' variables
input spiClock;
input start;
input [(byteSize * 8) - 1:0] cmd;
output bitout;
output reg finish;
// 'private' variables
wire _start;
assign _start = start;
reg _running = 0, _waiting = 0;
reg [(byteSize * 8) - 1:0] _cmdBuffer;
reg [byteSize - 1:0] _i;
assign bitout = _running ? _cmdBuffer[47] : 1'b1; /// active low
reg _error = 0;
// main //
always @ (negedge spiClock) begin
if (_start && ~_running && ~_waiting) begin
// initial
finish <= 0;
_cmdBuffer <= cmd; // cmd always start with 0
_running <= 1;
_i <= 47; // this loop sends a `0`
end else if (_start && _running && ~_waiting) begin
// looping
_i = _i - 1;
_cmdBuffer = _cmdBuffer << 1;
if (_i == 0) begin
// end
_running <= 0;
_waiting <= 1;
end
end else if (_start && _waiting) begin
finish <= 1;
end else if (~_start) begin
finish <= 0;
_waiting <= 0;
end else begin
_error = 1;
end
end
endmodule
| 8.048585 |
module spisequencer (
input wire clk,
/* Memory buffer signals. */
input wire [addr_bits - 1:0] buf_addr,
input wire [7:0] buf_wr_val,
output wire [7:0] buf_rd_val,
input wire buf_wr_en,
/* SPI transfer control signals. */
input wire [8:0] divider,
input wire xfer_start,
input wire [addr_bits - 1:0] xfer_length,
output reg xfer_complete,
/* SPI bus signals. */
input wire miso,
output wire mosi,
output wire sclk
);
localparam num_bytes = 8192;
localparam addr_bits = $clog2(num_bytes);
localparam STATE_IDLE = 4'b0001;
localparam STATE_XFER = 4'b0010;
localparam STATE_NEXT_BYTE = 4'b0100;
localparam STATE_COMPLETE = 4'b1000;
reg [3:0] state = STATE_IDLE;
reg [3:0] next_state = STATE_IDLE;
wire [7:0] seq_wr_val;
wire [7:0] seq_rd_val;
reg seq_wr_en = 1'b0;
reg seq_xfer_start = 1'b0;
wire seq_xfer_complete;
reg [addr_bits - 1:0] bytes_xferred = {addr_bits{1'b0}};
spibuf #(
.num_bytes(num_bytes)
) xfer_buf (
.clk(clk),
/* Host side buffer signals. */
.a_addr(buf_addr),
.a_wr_val(buf_wr_val),
.a_rd_val(buf_rd_val),
.a_wr_en(buf_wr_en),
/* Sequencer side buffer signals. */
.b_addr(bytes_xferred),
.b_wr_val(seq_wr_val),
.b_rd_val(seq_rd_val),
.b_wr_en(seq_wr_en)
);
spimaster master (
.clk(clk),
/* Control signals. */
.divider(divider),
.xfer_start(seq_xfer_start),
.xfer_complete(seq_xfer_complete),
.tx_data(seq_rd_val),
.rx_data(seq_wr_val),
/* SPI signals. */
.miso(miso),
.mosi(mosi),
.sclk(sclk)
);
initial xfer_complete = 1'b0;
always @(*) begin
case (state)
STATE_IDLE: begin
next_state = xfer_start ? STATE_XFER : STATE_IDLE;
end
STATE_XFER: begin
if (seq_xfer_complete) next_state = STATE_NEXT_BYTE;
else next_state = STATE_XFER;
end
STATE_NEXT_BYTE: begin
if (bytes_xferred == xfer_length) next_state = STATE_COMPLETE;
else next_state = STATE_XFER;
end
STATE_COMPLETE: next_state = STATE_IDLE;
default: ;
endcase
end
always @(*) begin
seq_wr_en = 1'b0;
if (state == STATE_XFER && seq_xfer_complete) seq_wr_en = 1'b1;
end
always @(*) xfer_complete = (state == STATE_COMPLETE);
always @(*) seq_xfer_start = (state == STATE_XFER) & ~seq_xfer_complete;
always @(posedge clk)
if (state == STATE_IDLE) bytes_xferred <= {addr_bits{1'b0}};
else if (state == STATE_XFER && seq_xfer_complete) bytes_xferred <= bytes_xferred + 1'b1;
always @(posedge clk) state <= next_state;
endmodule
| 8.489578 |
module spigpio (
clk,
cs,
sr_in,
gpioout,
sr_out
);
input clk, cs;
input sr_in;
output sr_out;
output [7:0] gpioout;
reg [7:0] gpioout;
reg sr_out;
wire rw;
reg [7:0] sr;
assign rw = sr[7];
always @(posedge clk) begin
if (cs == 1'b0) begin
sr_out <= sr[7];
sr[7:1] <= sr[6:0];
sr[0] <= sr_in;
end
if (cs == 1'b1) begin
if (rw == 1'b1) begin
case (sr)
`P0_P9_OP: gpioout[7:0] <= {sr[0], sr[1], sr[2], sr[3], sr[4], sr[5], sr[6], sr[7]};
`P0_P3_OP: gpioout[3:0] <= {sr[0], sr[1], sr[2], sr[3]};
`P4_P7_OP: gpioout[7:4] <= {sr[4], sr[5], sr[6], sr[7]};
default: gpioout[0] <= sr[0];
endcase
end
end
end
endmodule
| 6.590193 |
module SPISlaveInterface (
clk_in,
spi_sclk,
spi_mosi,
spi_miso,
spi_n_ss,
tx_buffer,
rx_buffer,
rx_ready,
rx_ready_ack,
nss_risen_stable_out
);
input clk_in;
input spi_sclk;
input spi_mosi;
output reg spi_miso;
input spi_n_ss;
input [7:0] tx_buffer;
reg [7:0] tx_latch;
output reg [7:0] rx_buffer;
output reg rx_ready;
input rx_ready_ack;
reg [2:0] bit_nbr;
reg between_bytes;
// generate short rising/falling pulses
reg [2:0] SCKr;
always @(posedge clk_in) SCKr <= {SCKr[1:0], spi_sclk};
wire sclk_risingedge = (SCKr[2:1] == 2'b01);
wire sclk_fallingedge = (SCKr[2:1] == 2'b10);
// generate short rising/falling pulses when nSS falls or rises
// and remains stable at least one clock
reg [3:0] NSSr;
always @(posedge clk_in) NSSr <= {NSSr[2:0], spi_n_ss};
wire nss_risen_stable = (NSSr[3:1] == 3'b011);
output nss_risen_stable_out;
assign nss_risen_stable_out = nss_risen_stable;
initial begin
bit_nbr <= 3'b000;
rx_buffer <= 8'b00000000;
rx_ready <= 1'b0;
spi_miso <= 1'b0;
between_bytes <= 1'b0;
end
always @(negedge clk_in) begin
// keep spi_miso ready while we're between bytes
if (between_bytes) spi_miso <= tx_latch[7];
if (sclk_fallingedge) begin
if (bit_nbr == 3'd0) begin
between_bytes <= 1'b1;
end else begin
between_bytes <= 1'b0;
end
// set up data for MISO on negative clock edges
if (spi_n_ss == 1'b0) begin
spi_miso <= tx_latch[7-bit_nbr];
end else begin
spi_miso <= 1'bZ;
end
end
end
always @(posedge clk_in) begin
if (bit_nbr == 3'd0 || bit_nbr == 3'd7) tx_latch <= tx_buffer;
if (rx_ready == 1'b1 && rx_ready_ack == 1'b1) begin
// lower our ready signal once the controller acknowledges it was received
rx_ready <= 1'b0;
end
if (spi_n_ss == 1'b0) begin
// read MOSI on positive clock edges
if (sclk_risingedge) begin
// spi_n_ss is low, the master is talking to us
rx_buffer[7-bit_nbr] <= spi_mosi;
bit_nbr <= bit_nbr + 1'b1;
if (bit_nbr == 3'd7) begin
// we have an entire byte in the buffer, signal our controller
rx_ready <= 1'b1;
bit_nbr <= 3'd0;
end
end
end
// only reset things if nSS has risen and is now stable, to avoid glitches causing resets
if (nss_risen_stable) begin
// spi_n_ss is high, the master is talking to someone else, reset our state
bit_nbr <= 1'b0;
end
end
endmodule
| 7.551734 |
module altera_avalon_packets_to_master_inst_for_spichain_out_stream_arbitrator (
// inputs:
altera_avalon_packets_to_master_inst_for_spichain_out_stream_data,
altera_avalon_packets_to_master_inst_for_spichain_out_stream_endofpacket,
altera_avalon_packets_to_master_inst_for_spichain_out_stream_startofpacket,
altera_avalon_packets_to_master_inst_for_spichain_out_stream_valid,
channel_adapter_ptob_for_spichain_in_ready_from_sa,
clk,
reset_n,
// outputs:
altera_avalon_packets_to_master_inst_for_spichain_out_stream_ready,
altera_avalon_packets_to_master_inst_for_spichain_out_stream_reset_n
);
output altera_avalon_packets_to_master_inst_for_spichain_out_stream_ready;
output altera_avalon_packets_to_master_inst_for_spichain_out_stream_reset_n;
input [7:0] altera_avalon_packets_to_master_inst_for_spichain_out_stream_data;
input altera_avalon_packets_to_master_inst_for_spichain_out_stream_endofpacket;
input altera_avalon_packets_to_master_inst_for_spichain_out_stream_startofpacket;
input altera_avalon_packets_to_master_inst_for_spichain_out_stream_valid;
input channel_adapter_ptob_for_spichain_in_ready_from_sa;
input clk;
input reset_n;
wire altera_avalon_packets_to_master_inst_for_spichain_out_stream_ready;
wire altera_avalon_packets_to_master_inst_for_spichain_out_stream_reset_n;
//altera_avalon_packets_to_master_inst_for_spichain_out_stream_reset_n assignment, which is an e_assign
assign altera_avalon_packets_to_master_inst_for_spichain_out_stream_reset_n = reset_n;
//mux altera_avalon_packets_to_master_inst_for_spichain_out_stream_ready, which is an e_mux
assign altera_avalon_packets_to_master_inst_for_spichain_out_stream_ready = channel_adapter_ptob_for_spichain_in_ready_from_sa;
endmodule
| 7.767945 |
module altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_arbitrator (
// inputs:
altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_ready,
clk,
reset_n,
spislave_inst_for_spichain_avalon_streaming_source_data,
spislave_inst_for_spichain_avalon_streaming_source_valid,
// outputs:
altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_data,
altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_ready_from_sa,
altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_valid
);
output [7:0] altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_data;
output altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_ready_from_sa;
output altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_valid;
input altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_ready;
input clk;
input reset_n;
input [7:0] spislave_inst_for_spichain_avalon_streaming_source_data;
input spislave_inst_for_spichain_avalon_streaming_source_valid;
wire [7:0] altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_data;
wire altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_ready_from_sa;
wire altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_valid;
//mux altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_data, which is an e_mux
assign altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_data = spislave_inst_for_spichain_avalon_streaming_source_data;
//assign altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_ready_from_sa = altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_ready so that symbol knows where to group signals which may go to master only, which is an e_assign
assign altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_ready_from_sa = altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_ready;
//mux altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_valid, which is an e_mux
assign altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_valid = spislave_inst_for_spichain_avalon_streaming_source_valid;
endmodule
| 7.767945 |
module altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_arbitrator (
// inputs:
altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_channel,
altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_data,
altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_endofpacket,
altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_startofpacket,
altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_valid,
channel_adapter_btop_for_spichain_in_ready_from_sa,
clk,
reset_n,
// outputs:
altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_ready,
altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_reset_n
);
output altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_ready;
output altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_reset_n;
input [7:0] altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_channel;
input [7:0] altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_data;
input altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_endofpacket;
input altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_startofpacket;
input altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_valid;
input channel_adapter_btop_for_spichain_in_ready_from_sa;
input clk;
input reset_n;
wire altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_ready;
wire altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_reset_n;
//altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_reset_n assignment, which is an e_assign
assign altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_reset_n = reset_n;
//mux altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_ready, which is an e_mux
assign altera_avalon_st_bytes_to_packets_inst_for_spichain_out_packets_stream_ready = channel_adapter_btop_for_spichain_in_ready_from_sa;
endmodule
| 7.767945 |
module altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_arbitrator (
// inputs:
altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_data,
altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_valid,
clk,
reset_n,
spislave_inst_for_spichain_avalon_streaming_sink_ready_from_sa,
// outputs:
altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_ready
);
output altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_ready;
input [7:0] altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_data;
input altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_valid;
input clk;
input reset_n;
input spislave_inst_for_spichain_avalon_streaming_sink_ready_from_sa;
wire altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_ready;
//mux altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_ready, which is an e_mux
assign altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_ready = spislave_inst_for_spichain_avalon_streaming_sink_ready_from_sa;
endmodule
| 7.767945 |
module spislave_inst_for_spichain_avalon_streaming_sink_arbitrator (
// inputs:
altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_data,
altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_valid,
clk,
reset_n,
spislave_inst_for_spichain_avalon_streaming_sink_ready,
// outputs:
spislave_inst_for_spichain_avalon_streaming_sink_data,
spislave_inst_for_spichain_avalon_streaming_sink_ready_from_sa,
spislave_inst_for_spichain_avalon_streaming_sink_valid
);
output [7:0] spislave_inst_for_spichain_avalon_streaming_sink_data;
output spislave_inst_for_spichain_avalon_streaming_sink_ready_from_sa;
output spislave_inst_for_spichain_avalon_streaming_sink_valid;
input [7:0] altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_data;
input altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_valid;
input clk;
input reset_n;
input spislave_inst_for_spichain_avalon_streaming_sink_ready;
wire [7:0] spislave_inst_for_spichain_avalon_streaming_sink_data;
wire spislave_inst_for_spichain_avalon_streaming_sink_ready_from_sa;
wire spislave_inst_for_spichain_avalon_streaming_sink_valid;
//mux spislave_inst_for_spichain_avalon_streaming_sink_data, which is an e_mux
assign spislave_inst_for_spichain_avalon_streaming_sink_data = altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_data;
//assign spislave_inst_for_spichain_avalon_streaming_sink_ready_from_sa = spislave_inst_for_spichain_avalon_streaming_sink_ready so that symbol knows where to group signals which may go to master only, which is an e_assign
assign spislave_inst_for_spichain_avalon_streaming_sink_ready_from_sa = spislave_inst_for_spichain_avalon_streaming_sink_ready;
//mux spislave_inst_for_spichain_avalon_streaming_sink_valid, which is an e_mux
assign spislave_inst_for_spichain_avalon_streaming_sink_valid = altera_avalon_st_packets_to_bytes_inst_for_spichain_out_bytes_stream_valid;
endmodule
| 7.769557 |
module spislave_inst_for_spichain_avalon_streaming_source_arbitrator (
// inputs:
altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_ready_from_sa,
clk,
reset_n,
spislave_inst_for_spichain_avalon_streaming_source_data,
spislave_inst_for_spichain_avalon_streaming_source_valid,
// outputs:
spislave_inst_for_spichain_avalon_streaming_source_ready,
spislave_inst_for_spichain_avalon_streaming_source_reset_n
);
output spislave_inst_for_spichain_avalon_streaming_source_ready;
output spislave_inst_for_spichain_avalon_streaming_source_reset_n;
input altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_ready_from_sa;
input clk;
input reset_n;
input [7:0] spislave_inst_for_spichain_avalon_streaming_source_data;
input spislave_inst_for_spichain_avalon_streaming_source_valid;
wire spislave_inst_for_spichain_avalon_streaming_source_ready;
wire spislave_inst_for_spichain_avalon_streaming_source_reset_n;
//spislave_inst_for_spichain_avalon_streaming_source_reset_n assignment, which is an e_assign
assign spislave_inst_for_spichain_avalon_streaming_source_reset_n = reset_n;
//mux spislave_inst_for_spichain_avalon_streaming_source_ready, which is an e_mux
assign spislave_inst_for_spichain_avalon_streaming_source_ready = altera_avalon_st_bytes_to_packets_inst_for_spichain_in_bytes_stream_ready_from_sa;
endmodule
| 7.769557 |
module SPISlaveToAvalonMasterBridge_reset_clk_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <= 0;
else if (1) data_in_d1 <= data_in;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else if (1) data_out <= data_in_d1;
end
endmodule
| 7.403143 |
module test_bench
//;
// wire [ 31: 0] address_from_the_altera_avalon_packets_to_master_inst_for_spichain;
// wire [ 3: 0] byteenable_from_the_altera_avalon_packets_to_master_inst_for_spichain;
// reg clk;
// wire miso_to_and_from_the_spislave_inst_for_spichain;
// wire mosi_to_the_spislave_inst_for_spichain;
// wire nss_to_the_spislave_inst_for_spichain;
// wire read_from_the_altera_avalon_packets_to_master_inst_for_spichain;
// wire [ 31: 0] readdata_to_the_altera_avalon_packets_to_master_inst_for_spichain;
// wire readdatavalid_to_the_altera_avalon_packets_to_master_inst_for_spichain;
// reg reset_n;
// wire sclk_to_the_spislave_inst_for_spichain;
// wire waitrequest_to_the_altera_avalon_packets_to_master_inst_for_spichain;
// wire write_from_the_altera_avalon_packets_to_master_inst_for_spichain;
// wire [ 31: 0] writedata_from_the_altera_avalon_packets_to_master_inst_for_spichain;
// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
// add your signals and additional architecture here
// AND HERE WILL BE PRESERVED </ALTERA_NOTE>
//Set us up the Dut
// SPISlaveToAvalonMasterBridge DUT
// (
// .address_from_the_altera_avalon_packets_to_master_inst_for_spichain (address_from_the_altera_avalon_packets_to_master_inst_for_spichain),
// .byteenable_from_the_altera_avalon_packets_to_master_inst_for_spichain (byteenable_from_the_altera_avalon_packets_to_master_inst_for_spichain),
// .clk (clk),
// .miso_to_and_from_the_spislave_inst_for_spichain (miso_to_and_from_the_spislave_inst_for_spichain),
// .mosi_to_the_spislave_inst_for_spichain (mosi_to_the_spislave_inst_for_spichain),
// .nss_to_the_spislave_inst_for_spichain (nss_to_the_spislave_inst_for_spichain),
// .read_from_the_altera_avalon_packets_to_master_inst_for_spichain (read_from_the_altera_avalon_packets_to_master_inst_for_spichain),
// .readdata_to_the_altera_avalon_packets_to_master_inst_for_spichain (readdata_to_the_altera_avalon_packets_to_master_inst_for_spichain),
// .readdatavalid_to_the_altera_avalon_packets_to_master_inst_for_spichain (readdatavalid_to_the_altera_avalon_packets_to_master_inst_for_spichain),
// .reset_n (reset_n),
// .sclk_to_the_spislave_inst_for_spichain (sclk_to_the_spislave_inst_for_spichain),
// .waitrequest_to_the_altera_avalon_packets_to_master_inst_for_spichain (waitrequest_to_the_altera_avalon_packets_to_master_inst_for_spichain),
// .write_from_the_altera_avalon_packets_to_master_inst_for_spichain (write_from_the_altera_avalon_packets_to_master_inst_for_spichain),
// .writedata_from_the_altera_avalon_packets_to_master_inst_for_spichain (writedata_from_the_altera_avalon_packets_to_master_inst_for_spichain)
// );
// initial
// clk = 1'b0;
// always
// #10 clk <= ~clk;
// initial
// begin
// reset_n <= 0;
// #200 reset_n <= 1;
// end
//endmodule
| 7.171211 |
module spislave_inst_for_spichain (
// inputs:
mosi,
nreset,
nss,
sclk,
stsinkdata,
stsinkvalid,
stsourceready,
sysclk,
// outputs:
miso,
stsinkready,
stsourcedata,
stsourcevalid
);
parameter SYNC_DEPTH = 2; /* Number of synchronizer stages for clock crossing */
inout miso;
output stsinkready;
output [7:0] stsourcedata;
output stsourcevalid;
input mosi;
input nreset;
input nss;
input sclk;
input [7:0] stsinkdata;
input stsinkvalid;
input stsourceready;
input sysclk;
wire miso;
wire stsinkready;
wire [7:0] stsourcedata;
wire stsourcevalid;
SPIPhy the_SPIPhy (
.miso (miso),
.mosi (mosi),
.nreset (nreset),
.nss (nss),
.sclk (sclk),
.stsinkdata (stsinkdata),
.stsinkready (stsinkready),
.stsinkvalid (stsinkvalid),
.stsourcedata (stsourcedata),
.stsourceready(stsourceready),
.stsourcevalid(stsourcevalid),
.sysclk (sysclk)
);
defparam the_SPIPhy.SYNC_DEPTH = SYNC_DEPTH;
//defparam the_SPIPhy.CPOL = 0;
endmodule
| 7.769557 |
module SPIslave_InternalComponent #(
// parametr to define the width of the address bus and the data bus
parameter WIDTH = 8
) (
// input internal bus from shift register
input wire [WIDTH-1:0] Data_sh,
// input internal control signal from FSM indicates address is valid to be captured
input wire Address_en,
// input internal control signal from FSM indicates write data is valid to be captured
input wire Wr_Data_en,
// input internal control signal from FSM is used to activate the incrementer to increment the current address to the next one
input wire incr_sel,
// input clock to the system
input wire SCLK,
// input slave select from SPI slave master
input wire SS,
// input the system as active low reset
input wire RST,
// output internal control singal indicates that the counter overflow
output reg coutner_tick,
// output signal from the system to REG file to write enable
output reg Wr_EN,
// output bus from the system to REG file as address bus to write in or read from
output reg [WIDTH-1:0] Address,
// output bus from the system to REG file as data to write into
output reg [WIDTH-1:0] Wr_Data
);
// local parameter to define the width of the counter
parameter COUNTER_WIDTH = $clog2(WIDTH);
// defining the counter to count number of bits entered to the system
reg [COUNTER_WIDTH:0] counter;
//////////////////////////////////////////////////////////////////////////////////////////
// sequential always to reset the system and assign the outputs form SPI slave to REG file
//////////////////////////////////////////////////////////////////////////////////////////
always @(posedge SCLK or negedge RST) begin
if (!RST) begin
// reset all registers
Address <= {WIDTH{1'b0}};
Wr_Data <= {WIDTH{1'b0}};
Wr_EN <= 1'b0;
end else begin
if (!SS) begin
if (Wr_Data_en) begin
// assign the data of write data bus to shift register
Wr_Data <= Data_sh;
// assign the write enable signal to one to enable REG file to write the data
Wr_EN <= 1'b1;
end else begin
// write data bus still the same and deactivate the enable signal
Wr_EN <= 1'b0;
end
if (incr_sel)
// increment the address bus to the next address to enable multi mode
Address <= Address + 1;
else if (Address_en)
// assign the address bus to data from the shift register
Address <= Data_sh;
else begin
// address bus still the same
end
end
end
end
///////////////////////////////////////////////////////////////////////////
// sequential always to reset the counter and handle the counter operations
///////////////////////////////////////////////////////////////////////////
always @(posedge SCLK or posedge SS) begin
if (SS) begin
// reset the conter and the conter tick register
counter <= {COUNTER_WIDTH{1'b0}};
coutner_tick <= 1'b0;
end else begin
if (counter == WIDTH - 1) begin
// reset the counter when overflow happen
counter <= {COUNTER_WIDTH{1'b0}};
// conter tick with overflow of the counter
coutner_tick <= 1'b1;
end else begin
// increment the counter withe each clock cycle
counter <= counter + 1;
coutner_tick <= 1'b0;
end
end
end
endmodule
| 7.618396 |
module SPIslave_SHregister #(
// parametr to define the width of the address bus and the data bus
parameter WIDTH = 8
) (
// input bus to the system from REG file as read data
input wire [WIDTH-1:0] Rd_Data,
// input signal to the system from the master (master output salve input)
input wire MOSI,
// input internal control signal from FSM is used to select the source of the data will be written into the shift register
input wire DataSel,
// input clock to the shift register
input wire CLK,
// input active low reset
input wire RST,
// output signal from the system to the master (master input slave output)
output wire MISO,
// output internal control signal indicates that the operation mode is write
output wire OP_Wr,
// output internal control signal indicates that the operation mode is read
output wire OP_Rd,
// ouput internal bus holds the value of the shift register
output wire [WIDTH-1:0] Data_sh
);
// shift register is working with postive edge of clk signal
reg [WIDTH-1:0] Data_in;
// shift register is working wigh negative edge of clk signal
reg [WIDTH-1:0] Data_out;
// integer to be used in the for loop
integer i;
// internal signal holds the inverted version of clock
wire CLK_inv;
// assign the clk_inv to the clock invert
assign CLK_inv = ~CLK;
// assign the MISO signal to the MSB of Data_out
assign MISO = Data_out[WIDTH-1];
// assign the Data_sh bus to the Data_in register
assign Data_sh = Data_in;
// assign the op_wr signal to 1 if the operation code is 0x2 and 0 otherwise
assign OP_Wr = (Data_in == 8'h02) ? 1'b1 : 1'b0;
// assign the op_wr signal to 1 if the operation code is 0x3 and 0 otherwise
assign OP_Rd = (Data_in == 8'h03) ? 1'b1 : 1'b0;
//////////////////////////////////////////////////////////////////////////
// sequential always to reset the system and assign Data_in shift register
//////////////////////////////////////////////////////////////////////////
always @(posedge CLK or posedge RST) begin
if (RST) begin
// reset the shift register
Data_in <= {WIDTH{1'b0}};
end else begin
// perform shift operation
Data_in[0] <= MOSI;
for (i = 1; i < WIDTH; i = i + 1) begin
Data_in[i] <= Data_in[i-1];
end
end
end
//////////////////////////////////////////////////////////////////////////
// sequential always to reset the system and assign Data_out shift register
//////////////////////////////////////////////////////////////////////////
always @(posedge CLK_inv or posedge RST) begin
if (RST) begin
// reset the shift registerData_out <= WIDTH {1'b0};
Data_out <= {WIDTH{1'b0}};
end else begin
if (DataSel) begin
// perform shift operation
Data_out[0] <= MOSI;
for (i = 1; i < WIDTH; i = i + 1) begin
Data_out[i] <= Data_out[i-1];
end
end else begin
// insert the value of read data from REG file to Data_out shift register
Data_out <= Rd_Data;
end
end
end
endmodule
| 8.255097 |
module SPIslave_Top #(
// parametr to define the width of the address bus and the data bus
parameter WIDTH = 8
) (
// input bus to the system from REG file as read data
input wire [WIDTH-1:0] Rd_Data,
// input signal to the system from the master (master output salve input)
input wire MOSI,
//input clock to the system
input wire SCLK,
// input slave select from SPI slave master
input wire SS,
// input active low reset
input wire RST,
// output signal from the system to the master (master input slave output)
output wire MISO,
// output signal from the system to REG file to write enable
output wire Wr_EN,
//output form the system to REG file as read enable signal
output wire Rd_EN,
// output bus from the system to REG file as address bus to write in or read from
output wire [WIDTH-1:0] Address,
// output bus from the system to REG file as data to write into
output wire [WIDTH-1:0] Wr_Data
);
// internal signals to connect between different blocks
wire counter_tick, OP_Wr, OP_Rd, DataSel, Address_en, Wr_Data_en, incr_sel;
// internal bus holds the value of shift register
wire [WIDTH-1:0] Data_sh;
SPIsalve_FSMController FSM_1 (
.coutner_tick(counter_tick),
.OP_Wr(OP_Wr),
.OP_Rd(OP_Rd),
.SCLK(SCLK),
.SS(SS),
.DataSel(DataSel),
.Address_en(Address_en),
.Wr_Data_en(Wr_Data_en),
.incr_sel(incr_sel),
.Rd_EN(Rd_EN)
);
SPIslave_SHregister #(
.WIDTH(WIDTH)
) SH_Register_1 (
.Rd_Data(Rd_Data),
.MOSI(MOSI),
.DataSel(DataSel),
.CLK(SCLK),
.RST(SS),
.MISO(MISO),
.OP_Wr(OP_Wr),
.OP_Rd(OP_Rd),
.Data_sh(Data_sh)
);
SPIslave_InternalComponent #(
.WIDTH(WIDTH)
) SPI_1 (
.Data_sh(Data_sh),
.Address_en(Address_en),
.Wr_Data_en(Wr_Data_en),
.incr_sel(incr_sel),
.SCLK(SCLK),
.SS(SS),
.RST(RST),
.coutner_tick(counter_tick),
.Wr_EN(Wr_EN),
.Address(Address),
.Wr_Data(Wr_Data)
);
endmodule
| 9.140751 |
module combining the SPI Minion, SPI Minion Adapter, and Loopthrough
// This is the standard SPI stack used in the efabless tapeout in 2022.
// Author : Jack Brzozowski
// Date : May 7th, 2022
`ifndef SPI_V3_COMPONENTS_SPI_STACK_V
`define SPI_V3_COMPONENTS_SPI_STACK_V
`include "SPI_v3/components/LoopThroughVRTL.v"
`include "SPI_v3/components/SPIMinionAdapterCompositeVRTL.v"
`include "SPI_v3/components/Synchronizer.v"
module SPI_v3_components_SPIStackVRTL
#(
parameter nbits = 34, // the size of the val/rdy msg for the SPI minion
parameter num_entries = 1
)(
input logic clk,
input logic reset,
input logic loopthrough_sel,
output logic minion_parity,
output logic adapter_parity,
// SPI Minion Ifc
input logic sclk,
input logic cs,
input logic mosi,
output logic miso,
// Send/Recv Ifc
output logic send_val,
output logic [(nbits-2)-1:0] send_msg,
input logic send_rdy,
input logic recv_val,
input logic [(nbits-2)-1:0] recv_msg,
output logic recv_rdy
);
logic minion_out_val;
logic [nbits-3:0] minion_out_msg;
logic minion_out_rdy;
logic minion_in_val;
logic [nbits-3:0] minion_in_msg;
logic minion_in_rdy;
SPI_v3_components_SPIMinionAdapterCompositeVRTL #(nbits, num_entries) minion
(
.clk( clk ),
.reset( reset ),
.cs( cs ),
.miso( miso ),
.mosi( mosi ),
.sclk( sclk ),
.minion_parity( minion_parity ),
.adapter_parity( adapter_parity ),
.recv_val( minion_in_val ),
.recv_msg( minion_in_msg ),
.recv_rdy( minion_in_rdy ),
.send_val( minion_out_val ),
.send_msg( minion_out_msg ),
.send_rdy( minion_out_rdy )
);
logic loopthrough_sel_sync_out;
SPI_v3_components_Synchronizer #(1'b0) lt_sel_sync
(
.clk( clk ),
.in_( loopthrough_sel ),
.negedge_(),
.out( loopthrough_sel_sync_out ),
.posedge_(),
.reset( reset )
);
SPI_v3_components_LoopThroughVRTL #(nbits-2) loopthrough
(
.clk( clk ),
.reset( reset ),
.sel( loopthrough_sel_sync_out ),
.upstream_req_val( minion_out_val ),
.upstream_req_msg( minion_out_msg ),
.upstream_req_rdy( minion_out_rdy ),
.upstream_resp_val( minion_in_val ),
.upstream_resp_msg( minion_in_msg ),
.upstream_resp_rdy( minion_in_rdy ),
.downstream_req_val( send_val ),
.downstream_req_msg( send_msg ),
.downstream_req_rdy( send_rdy ),
.downstream_resp_val( recv_val ),
.downstream_resp_msg( recv_msg ),
.downstream_resp_rdy( recv_rdy )
);
endmodule
| 9.386012 |
module spitest_avr (
output wire spick,
output reg spics_n,
output wire spido,
input wire spidi
);
reg aclk;
reg spistart;
wire spirdy;
reg [7:0] spidin;
wire [7:0] spidout;
// clock gen
initial begin
aclk = 1'b0;
forever #`AVR_HALF_PERIOD aclk = ~aclk;
end
// signals init
initial begin
spics_n = 1'b1;
spistart = 1'b0;
end
// use standard spi2 module to send and receive over SPI.
// reverse bytes since spi2 sends and receives MSB first,
// while slavespi LSB first
spi2 spi2 (
.clock(aclk),
.sck(spick),
.sdo(spido),
.sdi(spidi),
.bsync(),
.start(spistart),
.rdy (spirdy),
.speed(2'b00),
.din({
spidin[0], spidin[1], spidin[2], spidin[3], spidin[4], spidin[5], spidin[6], spidin[7]
}),
.dout({
spidout[0],
spidout[1],
spidout[2],
spidout[3],
spidout[4],
spidout[5],
spidout[6],
spidout[7]
})
);
// test loop
initial begin
repeat (2211) @(posedge aclk);
forever begin
get_access();
send_msg();
release_access();
repeat (1234) @(posedge aclk);
end
end
task get_access();
reg [7:0] tmp;
reg_io(8'h61, 8'h81, tmp);
while (!tmp[7]) reg_io(8'h61, 8'h81, tmp);
endtask
task send_msg();
reg [7:0] tmp;
reg [71:0] msg = "AVR SEND\n";
integer i;
reg_io(8'h61, 8'h80, tmp);
for (i = 8; i >= 0; i = i - 1) begin
reg_io(8'h60, msg[i*8+:8], tmp);
end
reg_io(8'h61, 8'h81, tmp);
endtask
task release_access();
reg [7:0] tmp;
reg_io(8'h61, 8'h81, tmp);
reg_io(8'h61, 8'h01, tmp);
endtask
task reg_io(input [7:0] addr, input [7:0] wrdata, output [7:0] rddata);
reg [7:0] trash;
spics_n <= 1'b1;
@(posedge aclk);
spi_io(addr, trash);
spics_n <= 1'b0;
@(posedge aclk);
spi_io(wrdata, rddata);
spics_n <= 1'b1;
@(posedge aclk);
endtask
task spi_io(input [7:0] wrdata, output [7:0] rddata);
spidin <= wrdata;
spistart <= 1'b1;
@(posedge aclk);
spistart <= 1'b0;
@(posedge aclk);
wait (spirdy == 1'b1);
@(posedge aclk);
rddata = spidout;
endtask
endmodule
| 6.599071 |
module spitest_rom (
input wire [18:0] in_addr,
output reg [7:0] out_word
);
integer fd;
reg [7:0] mem[0:524287];
initial begin
// init rom
integer i;
for (i = 0; i < 524288; i = i + 1) mem[i] = 8'hFF;
// load file
fd = $fopen("spitest.bin", "rb");
if (37 != $fread(mem, fd, 524288 - 16384)) begin
$display("Couldn't load spitest.bin!\n");
$stop;
end
$fclose(fd);
end
always @* out_word = mem[in_addr];
endmodule
| 6.619457 |
module spitoi2c (
input start,
input [7:0] data,
input clk,
input reset,
output i2c_sda,
output i2c_scl
);
//wire mosi;
wire ss;
wire din;
wire done;
wire siso;
wire [7:0] in;
wire i2cmreset;
spi_fsm spi_fsm1 (
.clk(clk),
.reset(reset),
.data(data),
.start(start),
.mosi(din),
.ss(ss),
.done(i2cmreset),
.miso(siso)
);
sipo sipo1 (
.din (din),
.clk (clk),
.ss (ss),
.dout(in),
.siso(siso)
//.ndone(i2cmreset)
);
i2cmaster i2cmaster1 (
.clk(clk),
.reset(i2cmreset),
.in(in),
.i2c_sda(i2c_sda),
.i2c_scl(i2c_scl)
);
//bridge bridge1(
//.mosi(mosi),
//.ss(ss),
//.clk(clk),
//.miso(siso),
//.i2c_sda(i2c_sda),
//.i2c_scl(i2c_scl)
//);
//i2cslave i2cslave1(
//.i2c_sda(i2c_sda),
//.i2c_scl(i2c_scl)
//);
endmodule
| 6.506946 |
module: spitoi2c
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module spitoi2ct;
// Inputs
reg start;
reg [7:0] data;
reg clk;
reg reset;
// Outputs
wire i2c_sda;
wire i2c_scl;
// Instantiate the Unit Under Test (UUT)
spitoi2c uut (
.start(start),
.data(data),
.clk(clk),
.reset(reset),
.i2c_sda(i2c_sda),
.i2c_scl(i2c_scl)
);
initial begin
// Initialize Inputs
start = 0;
data = 8'b10101010;
clk = 0;
reset = 1;
forever #10 clk=~clk;
end
// Add stimulus here
initial begin
#90
data = 8'b10101010;
reset=0;
start=1;
end
endmodule
| 6.515775 |
module xip_regs (
input wire clk,
input wire rst_n,
// APB Port
input wire apbs_psel,
input wire apbs_penable,
input wire apbs_pwrite,
input wire [15:0] apbs_paddr,
input wire [31:0] apbs_pwdata,
output wire [31:0] apbs_prdata,
output wire apbs_pready,
output wire apbs_pslverr,
// Register interfaces
output reg csr_direct_o,
input wire csr_busy_i,
output reg [7:0] txdata_o,
output reg txdata_wen,
input wire [7:0] rxdata_i,
output reg rxdata_ren
);
// APB adapter
wire [31:0] wdata = apbs_pwdata;
reg [31:0] rdata;
wire wen = apbs_psel && apbs_penable && apbs_pwrite;
wire ren = apbs_psel && apbs_penable && !apbs_pwrite;
wire [15:0] addr = apbs_paddr & 16'hc;
assign apbs_prdata = rdata;
assign apbs_pready = 1'b1;
assign apbs_pslverr = 1'b0;
localparam ADDR_CSR = 0;
localparam ADDR_TXDATA = 4;
localparam ADDR_RXDATA = 8;
wire __csr_wen = wen && addr == ADDR_CSR;
wire __csr_ren = ren && addr == ADDR_CSR;
wire __txdata_wen = wen && addr == ADDR_TXDATA;
wire __txdata_ren = ren && addr == ADDR_TXDATA;
wire __rxdata_wen = wen && addr == ADDR_RXDATA;
wire __rxdata_ren = ren && addr == ADDR_RXDATA;
wire csr_direct_wdata = wdata[0];
wire csr_direct_rdata;
wire csr_busy_wdata = wdata[1];
wire csr_busy_rdata;
wire [31:0] __csr_rdata = {30'h0, csr_busy_rdata, csr_direct_rdata};
assign csr_direct_rdata = csr_direct_o;
assign csr_busy_rdata = csr_busy_i;
wire [ 7:0] txdata_wdata = wdata[7:0];
wire [ 7:0] txdata_rdata;
wire [31:0] __txdata_rdata = {24'h0, txdata_rdata};
assign txdata_rdata = 8'h0;
wire [ 7:0] rxdata_wdata = wdata[7:0];
wire [ 7:0] rxdata_rdata;
wire [31:0] __rxdata_rdata = {24'h0, rxdata_rdata};
assign rxdata_rdata = rxdata_i;
always @(*) begin
case (addr)
ADDR_CSR: rdata = __csr_rdata;
ADDR_TXDATA: rdata = __txdata_rdata;
ADDR_RXDATA: rdata = __rxdata_rdata;
default: rdata = 32'h0;
endcase
txdata_wen = __txdata_wen;
txdata_o = txdata_wdata;
rxdata_ren = __rxdata_ren;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
csr_direct_o <= 1'h0;
end else begin
if (__csr_wen) csr_direct_o <= csr_direct_wdata;
end
end
endmodule
| 8.425532 |
module SPI_16bit (
input wire clk_in,
input wire rst,
input wire SPI_MOSI,
input wire SPI_CS,
input wire SPI_SCLK,
input wire [15:0] tx_data,
output reg SPI_MISO,
output reg [15:0] rx_data,
output reg rx_flag
);
reg [15:0] rx_buf;
reg [15:0] tx_buf;
reg [2:0] state = 0;
reg SPI_SCLK_neg = 0;
reg SPI_SCLK_pos = 0;
reg [2:0] SPI_SCLK_r = 0;
reg SPI_cs_neg = 0;
reg SPI_cs_pos = 0;
reg [2:0] SPI_cs_r = 0;
reg [4:0] cnt_neg = 0;
always@(posedge clk_in) // 打两拍捕获cs上升下降沿
begin
SPI_cs_r <= {SPI_cs_r[1:0], SPI_CS};
SPI_cs_neg <= SPI_cs_r[2] & (~SPI_cs_r[1]);
SPI_cs_pos <= (~SPI_cs_r[2]) & SPI_cs_r[1];
end
always@(posedge clk_in) // 打两拍捕获clk上升下降沿
begin
SPI_SCLK_r <= {SPI_SCLK_r[1:0], SPI_SCLK};
SPI_SCLK_neg <= SPI_SCLK_r[2] & (~SPI_SCLK_r[1]);
SPI_SCLK_pos <= (~SPI_SCLK_r[2]) & SPI_SCLK_r[1];
end
always@(posedge clk_in) // 模式3，下降沿采样
begin
if (SPI_cs_neg) // 开始通信
begin
state = 1; // 状态1开始通信
cnt_neg = 0;
tx_buf <= tx_data;
// tx_buf<=rx_data; // 回环测试
rx_buf <= 0; // 清空缓冲区
rx_flag <= 0;
end
if (state == 1) begin
if (SPI_SCLK_neg) // 采样主站发送的数据,MSB first
begin
rx_buf <= SPI_MOSI + rx_buf;
tx_buf <= tx_buf << 1;
cnt_neg = cnt_neg + 1;
end
if (SPI_SCLK_pos) // 下降沿采样，上升沿准备send数据
begin
SPI_MISO <= tx_buf[15]; // 先发送最高位
if (cnt_neg != 0) // 准备接收下一个bit
begin
rx_buf <= rx_buf << 1;
end
end
end
// if (cnt_neg == 8) // 8个下降沿，数据接收完成，立刻进行数据处理
// begin
// rx_flag <= 1;
// end
if (SPI_cs_pos) // cs拉高，数据接收完成
begin
cnt_neg = 0; // 清空计数器
rx_data <= rx_buf;
state = 0; // 进入空闲状态
if(rx_buf[15] != 1) // 最高位为1时 主站只接收数据，不发送数据，所以不置位rx_flag从而不发送曼码
begin
rx_flag <= 1; // cs拉高时接收完成
tx_buf <= 0; // 发送缓冲区清0
end
end
end
endmodule
| 6.743084 |
module spi_16i_16o (
sclk,
pdi,
pdo,
send,
data_valid,
cs,
sdi,
sdo
);
input wire sclk;
input wire [15:0] pdi;
input wire send;
input wire sdi;
output reg cs;
output wire sdo;
output reg [15:0] pdo;
output reg data_valid;
reg last_send; // for edge detection of send
reg [4:0] sent_bit; // count of last bit sent_bit
reg [15:0] shift_out; // register for shifting out
assign sdo = shift_out[15];
initial begin
last_send <= 1'b0;
sent_bit <= 5'b0;
cs <= 1'b1;
shift_out <= 16'b0;
data_valid <= 1'b0;
end
always @(posedge sclk) begin
last_send <= send;
// start serial transmission on rising edge of send
if (~last_send & send) begin
cs <= 1'b0;
shift_out <= pdi;
sent_bit <= 5'd15; // starting with msb
data_valid <= 1'b0; // set data not-valid
pdo <= 1'b0; // zero internal storage register
end
// continuing transmission
if (cs == 1'b0) begin
pdo <= {pdo[14:0], sdi}; // shifting data into storage
shift_out <= {shift_out[14:0], 1'b0}; // shifting data out
sent_bit <= sent_bit - 1'b1;
end
// ending transmission
if (sent_bit == 1'b0) begin
cs <= 1'b1;
data_valid <= 1'b1;
end
end
endmodule
| 6.733825 |
module SPI_3_to_2_tb;
parameter Reand_Delay = 1;
parameter SPI_Command_Len = 16;
parameter SPI_Sys_Clock_Half_Div = 27;
reg SPI_SYNC ;
wire Control_Test ;
reg nReset ;
reg Clock_108M ;
reg SPI_SI_Fr_M ;
wire Control_Clock_Delay ;
wire SPI_SO_To_M ;
wire Slave_CLOCK_Delay_Control ;
reg Slave_IN_OUT_In ;
wire Slave_CLOCK ;
wire Control_Command ;
wire Slave_OUT_Test ;
wire Control_1 ;
wire [23:0] write_data ;
reg SPI_CLK ;
wire [23:0] read_data ;
wire Base_CLOCK ;
wire Command_Test ;
wire Slave_IN_OUT_Out ;
SPI_3_to_2 #(Reand_Delay, SPI_Command_Len, SPI_Sys_Clock_Half_Div) DUT (
.SPI_SYNC(SPI_SYNC),
.Control_Test(Control_Test),
.nReset(nReset),
.Clock_108M(Clock_108M),
.SPI_SI_Fr_M(SPI_SI_Fr_M),
.Control_Clock_Delay(Control_Clock_Delay),
.SPI_SO_To_M(SPI_SO_To_M),
.Slave_CLOCK_Delay_Control(Slave_CLOCK_Delay_Control),
.Slave_IN_OUT_In(Slave_IN_OUT_In),
.Slave_CLOCK(Slave_CLOCK),
.Control_Command(Control_Command),
.Slave_OUT_Test(Slave_OUT_Test),
.Control_1(Control_1),
.write_data(write_data),
.SPI_CLK(SPI_CLK),
.read_data(read_data),
.Base_CLOCK(Base_CLOCK),
.Command_Test(Command_Test),
.Slave_IN_OUT_Out(Slave_IN_OUT_Out)
);
initial begin
Clock_108M = 1'b0;
forever #5 Clock_108M = !Clock_108M;
end
reg [7:0] data_number;
reg [7:0] index;
reg [SPI_Command_Len+7:0] data_write[2:0];
reg [SPI_Command_Len+7:0] data_temp;
always @(negedge SPI_CLK or negedge SPI_SYNC) begin
if (!SPI_SYNC) begin
SPI_SI_Fr_M = 1;
data_number = 0;
index = index + 1;
end else begin
if (index >= 3) index = 0;
if (data_number < SPI_Command_Len + 8) begin
data_temp = data_write[index];
SPI_SI_Fr_M = data_temp[data_number];
data_number = data_number + 1'h1;
end
end
end
initial //clock, uint: 10ns==100MHz
begin
// $readmenb("SPICOMD.dat",data_write);
data_write[0] = 24'h013;
data_write[1] = 24'h036;
data_write[2] = 24'h055;
nReset = 1;
data_number = 0;
index = 0;
SPI_CLK = 1;
SPI_SYNC = 0;
SPI_SI_Fr_M = 1;
fork
#5 nReset = 0;
#20 nReset = 1;
join
#500 SPI_SYNC = 1;
#5000 SPI_CLK = 0;
#500 SPI_CLK = 1;
#500 SPI_CLK = 0;
#500 SPI_CLK = 1;
#500 SPI_CLK = 0;
#500 SPI_CLK = 1;
#500 SPI_CLK = 0;
#500 SPI_CLK = 1;
#500 SPI_CLK = 0;
#500 SPI_CLK = 1;
#500 SPI_CLK = 0;
#500 SPI_CLK = 1;
#500 SPI_CLK = 0;
#500 SPI_CLK = 1;
#500 SPI_CLK = 0;
#500 SPI_CLK = 1; //8???
#5000 SPI_CLK = 0;
#500 SPI_CLK = 1;
#500 SPI_CLK = 0;
#500 SPI_CLK = 1;
#500 SPI_CLK = 0;
#500 SPI_CLK = 1;
#500 SPI_CLK = 0;
#500 SPI_CLK = 1;
#500 SPI_CLK = 0;
#500 SPI_CLK = 1;
#500 SPI_CLK = 0;
#500 SPI_CLK = 1;
#500 SPI_CLK = 0;
#500 SPI_CLK = 1;
#500 SPI_CLK = 0;
#500 SPI_CLK = 1; //?8???
#5000 SPI_CLK = 0;
#500 SPI_CLK = 1;
#500 SPI_CLK = 0;
#500 SPI_CLK = 1;
#500 SPI_CLK = 0;
#500 SPI_CLK = 1;
#500 SPI_CLK = 0;
#500 SPI_CLK = 1;
#500 SPI_CLK = 0;
#500 SPI_CLK = 1;
#500 SPI_CLK = 0;
#500 SPI_CLK = 1;
#500 SPI_CLK = 0;
#500 SPI_CLK = 1;
#500 SPI_CLK = 0;
#500 SPI_CLK = 1; //?8???
#5000 SPI_SYNC = 0;
end
endmodule
| 6.976381 |
module spi_7seg_controller (
MAX10_CLK1_50,
GPIO,
KEY,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5
);
input MAX10_CLK1_50;
input [35:0] GPIO;
input [1:0] KEY;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
wire sys_clk = MAX10_CLK1_50;
wire sys_rst_n = KEY[1];
wire spi_sck = GPIO[0];
wire spi_cs = GPIO[1];
wire spi_mosi = GPIO[2];
wire sck_rs_edg;
wire tr_cmplt;
reg [7:0] spi_dat_ff;
reg [2:0] sck_sync_ff;
reg [2:0] cs_sync_ff;
reg [1:0] mosi_sync_ff;
reg ctrl_or_data_ff; // 0 -> waiting ctrl word (address, etc)
// 1 -> waiting data word
reg spi_recv_byte_ff;
reg [2:0] cnt_ff;
reg [2:0] addr_ff;
reg [6:0] digits [5:0];
assign HEX0 = digits[0];
assign HEX1 = digits[1];
assign HEX2 = digits[2];
assign HEX3 = digits[3];
assign HEX4 = digits[4];
assign HEX5 = digits[5];
/******************************************************************************
* SPI old part *
******************************************************************************/
assign sck_rs_edg = ~sck_sync_ff[2] & sck_sync_ff[1];
assign tr_cmplt = ~cs_sync_ff[2] & cs_sync_ff[1];
always @(posedge sys_clk, negedge sys_rst_n) begin
if (~sys_rst_n) sck_sync_ff <= 3'b000;
else sck_sync_ff <= {sck_sync_ff[1:0], spi_sck};
end
always @(posedge sys_clk, negedge sys_rst_n) begin
if (~sys_rst_n) cs_sync_ff <= 3'b111;
else cs_sync_ff <= {cs_sync_ff[1:0], spi_cs};
end
always @(posedge sys_clk) mosi_sync_ff <= {mosi_sync_ff[0], spi_mosi};
always @(posedge sys_clk) begin
if (sck_rs_edg) spi_dat_ff <= {spi_dat_ff[6:0], mosi_sync_ff[1]};
end
/******************************************************************************
* SPI new part *
******************************************************************************/
always @(posedge sys_clk, negedge sys_rst_n) begin
if (~sys_rst_n) cnt_ff <= 3'd0;
else if (cs_sync_ff[2]) cnt_ff <= 3'd0;
else if (sck_rs_edg) cnt_ff <= cnt_ff + 1'b1;
end
always @(posedge sys_clk, negedge sys_rst_n) begin
if (~sys_rst_n) spi_recv_byte_ff <= 1'b0;
else if (sck_rs_edg & (3'd7 == cnt_ff)) spi_recv_byte_ff <= 1'b1;
else spi_recv_byte_ff <= 1'b0;
end
always @(posedge sys_clk, negedge sys_rst_n) begin
if (~sys_rst_n) ctrl_or_data_ff <= 1'b0;
else if (cs_sync_ff[2]) ctrl_or_data_ff <= 1'b0;
else if (spi_recv_byte_ff & ~ctrl_or_data_ff) ctrl_or_data_ff <= 1'b1;
end
always @(posedge sys_clk, negedge sys_rst_n) begin
if (~sys_rst_n) addr_ff <= 3'd0;
else if (cs_sync_ff[2]) addr_ff <= 3'd0;
else if (spi_recv_byte_ff & ~ctrl_or_data_ff) addr_ff <= spi_dat_ff[2:0];
else if (spi_recv_byte_ff) addr_ff <= addr_ff + 1'b1;
end
always @(posedge sys_clk) begin
if (spi_recv_byte_ff & ctrl_or_data_ff) digits[addr_ff] <= spi_dat_ff[6:0];
end
endmodule
| 8.176312 |
module SPI_AD (
input SPI_CLK,
input New_Word,
input [12:0] Addr,
input [ 7:0] Data,
output reg [ 7:0] q,
input RW, //1 Write; 0 :read
output reg SPI_CS,
inout reg SPI_Data,
output reg Over
);
reg [15:0] CMD;
reg [ 7:0] Wr_Data;
reg [ 7:0] SPI_Counter;
always @(negedge SPI_CLK or posedge New_Word) begin
if (New_Word) begin
CMD <= {RW, 1'b0, 1'b0, Addr[12:0]};
Wr_Data <= Data;
SPI_Counter <= 8'd0;
Over <= 1'b0;
SPI_CS <= 1'b1;
SPI_Data <= 1'bz;
end else begin
if (SPI_Counter < 8'd16) begin // first CMD
SPI_Counter <= SPI_Counter + 1'b1;
SPI_Data <= CMD[15];
CMD <= CMD << 1;
SPI_CS <= 1'b0;
q <= 8'd00;
end else if (SPI_Counter < 8'd24) begin //Data
SPI_Counter <= SPI_Counter + 1'b1;
if (RW) begin
q <= {q[6:0], SPI_Data};
SPI_Data <= 1'bz;
end else begin
SPI_Data <= Wr_Data[7];
Wr_Data <= Wr_Data << 1;
end
SPI_CS <= 1'b0;
end else if (SPI_Counter < 8'd25) begin //Data
SPI_Counter <= SPI_Counter + 1'b1;
if (RW) begin
q <= {q[6:0], SPI_Data};
SPI_Data <= 1'bz;
end
SPI_CS <= 1'b1;
end else if (SPI_Counter < 8'd32) begin // interval
SPI_Counter <= SPI_Counter + 1'b1;
SPI_CS <= 1'b1;
SPI_Data <= 1'bz;
Over <= 1'b1;
end else begin
SPI_Data <= 1'bz;
SPI_CS <= 1'b1;
Over <= 1'b1;
end
end
end
endmodule
| 6.754558 |
module spi_ad9268 #(
parameter tsckw = 5
) (
// Local bus interface
input clk, // local clock
input strobe, // bus strobe
input ce, // clock enable / module select
input rd, // read/write
output reg ack, // ack from the module
input [8:0] addr, // 9 bit register address
input [7:0] din, // from the bus
output reg [7:0] read_r,
// control lines
(* IOB = "FALSE" *)
output reg sclk, // serial clock
(* IOB = "FALSE" *)
inout sdio, // serial data
(* IOB = "FALSE" *)
output reg csb, // load
output [7:0] spi_state
);
// Registers
reg [23:0] sft_reg;
reg [tsckw-1:0] tckcnt = 0;
parameter IDLE = 6'h3f;
parameter START = 6'h00;
parameter END_SPI = 6'h30;
parameter END = 6'h31;
reg [5:0] state = IDLE;
reg sdo_r;
//assign spi_state={{(8-tsckw){1'b0}},tckcnt};
initial begin
ack <= 1'b0;
sclk <= 1'b0;
sdo_r <= 1'b0;
csb <= 1'b1;
tckcnt <= 0;
end
// sclk is two times slower than clk, should be <25 MHz
reg rwb;
wire clk_div = tckcnt[tsckw-1];
always @(posedge clk) begin
tckcnt <= tckcnt + 1;
end
wire strobe_div;
flag_xdomain flag_xdomain (
.clk1(clk),
.flagin_clk1(strobe),
.clk2(clk_div),
.flagout_clk2(strobe_div)
);
always @(posedge clk_div) begin
if (strobe_div & ce & ~ack & (state == IDLE) & csb) begin
rwb <= rd;
// R/W, W[1:0], A[12:7], A[6:0], D[7:0]
//sft_reg <= {rd, 2'b0, 6'b0, addr, 8'b0};
sft_reg <= {rd, 2'b0, 4'b0, addr, din[7:0]};
state <= START;
csb <= 1'b0;
end
if (ack) begin
ack <= 1'b0;
end
//if ((state != IDLE)&&(&tckcnt)) begin
if ((state != IDLE)) begin
if (state == END_SPI) begin
state <= state + 6'b1;
sclk <= 1'b0;
csb <= 1'b1;
end else if (state == END) begin
state <= IDLE;
ack <= 1'b1;
end else begin
state <= state + 6'b1;
if (~state[0]) begin
sdo_r <= sft_reg[23];
sft_reg <= {sft_reg[22:0], 1'b0};
sclk <= 1'b0;
end else begin
sclk <= 1'b1;
if (rwb & state[5]) begin
read_r <= {read_r[6:0], sdio};
end
end
end
end
end
// output assignment
assign sdio = ((~csb) & rwb & state[5]) ? 1'bz : sdo_r;
endmodule
| 7.15698 |
module SPI_ADC (
input clk,
input miso,
input measure_start,
output reg sck = 1,
output reg cs = 1,
output reg [15:0] data_out = 0,
output reg enable = 0
);
reg [15:0] count = 0;
reg [5:0] countsck = 0;
reg [5:0] countdatai = 0;
reg [5:0] i = 0;
reg [15:0] datain = 0;
reg flag_d = 0;
reg flagsck = 0;
reg flag = 1;
initial flag = 1;
always @(posedge clk) begin
if (measure_start == 1) begin
flag = 1; /*enable = 0;*/
end
if (flag == 1) begin
count = count + 1;
if (count == 100) begin
cs = 0;
sck = 1;
enable = 0;
end
if (cs == 0) begin
if ((countsck == 4) && (flag_d == 0)) begin
flag_d = 1;
countsck = 0;
sck = 0;
i = i + 1;
end
if ((countsck == 4) && (flag_d == 1)) begin
if (sck == 0) begin
sck = 1;
flagsck = 1;
end else begin
if (i < 16) sck = 0;
i = i + 1;
end
countsck = 0;
end
if ((sck == 0) && (flagsck == 1) && (i > 4) && (i < 17) && (countsck == 1)) begin
datain[11-countdatai] = miso;
countdatai = countdatai + 1;
flagsck = 0;
end
countsck = countsck + 1;
if (i == 17) begin
cs = 1;
count = 0;
sck = 1;
flagsck = 0;
countsck = 0;
countdatai = 0;
flag_d = 0;
data_out[15:0] <= datain[15:0];
enable = 1;
datain = 0;
i = 0;
flag = 0;
end
end
end
end
endmodule
| 6.573293 |
module spi_addressing (
input clk,
input rst,
// SPI Signals
output spi_miso,
input spi_mosi,
input spi_sck,
input spi_ss,
// Register interface signals
output [5:0] reg_addr,
output write,
output new_req,
output [7:0] write_value,
input [7:0] read_value,
output in_transaction
);
wire spi_done;
wire [7:0] spi_dout;
wire frame_start, frame_end;
wire spi_miso_m;
spi_slave spi_slave (
.clk(clk),
.rst(n_rdy),
.ss(spi_ss),
.mosi(spi_mosi),
.miso(spi_miso_m),
.sck(spi_sck),
.done(spi_done),
.din(read_value),
.dout(spi_dout),
.frame_start(frame_start),
.frame_end(frame_end)
);
localparam STATE_SIZE = 2;
localparam IDLE = 0, ADDR = 1, WRITE = 2, READ = 3;
reg [STATE_SIZE-1:0] state_d, state_q;
reg [7:0] write_value_d, write_value_q;
reg write_d, write_q;
reg auto_inc_d, auto_inc_q;
reg [5:0] reg_addr_d, reg_addr_q;
reg new_req_d, new_req_q;
reg first_write_d, first_write_q;
assign reg_addr = reg_addr_q;
assign write = write_q;
assign new_req = new_req_q;
assign write_value = write_value_q;
assign spi_miso = !spi_ss ? spi_miso_m : 1'bZ;
assign in_transaction = !spi_ss;
always @(*) begin
write_value_d = write_value_q;
write_d = write_q;
auto_inc_d = auto_inc_q;
reg_addr_d = reg_addr_q;
new_req_d = 1'b0;
state_d = state_q;
first_write_d = first_write_q;
case (state_q)
IDLE: begin
if (frame_start) state_d = ADDR;
end
ADDR: begin
if (spi_done) begin
first_write_d = 1'b1;
{write_d, auto_inc_d, reg_addr_d} = spi_dout;
if (spi_dout[7]) begin
state_d = WRITE;
end else begin
state_d = READ;
new_req_d = 1'b1;
end
end
end
WRITE: begin
if (spi_done) begin
first_write_d = 1'b0;
if (auto_inc_q && !first_write_q) reg_addr_d = reg_addr_q + 1'b1;
new_req_d = 1'b1;
write_value_d = spi_dout;
end
end
READ: begin
if (spi_done) begin
if (auto_inc_q) reg_addr_d = reg_addr_q + 1'b1;
new_req_d = 1'b1;
end
end
default: state_d = IDLE;
endcase
if (frame_end) state_d = IDLE;
end
always @(posedge clk) begin
if (rst) begin
state_q <= IDLE;
end else begin
state_q <= state_d;
end
write_value_q <= write_value_d;
write_q <= write_d;
auto_inc_q <= auto_inc_d;
reg_addr_q <= reg_addr_d;
new_req_q <= new_req_d;
first_write_q <= first_write_d;
end
endmodule
| 7.159558 |
module tf_Test_SPI;
// Inputs
reg st;
reg clk;
reg [11:0] MTX_DAT;
reg RESET;
reg [11:0] STX_DAT;
// Outputs
wire LOAD;
wire SCLK;
wire MOSI;
wire [11:0] MRX_DAT;
wire [11:0] sr_MTX;
wire [11:0] sr_MRX;
wire [7:0] cb_bit;
wire ce_tact;
wire MISO;
wire [11:0] sr_STX;
wire [11:0] sr_SRX;
wire [11:0] SRX_DAT;
// Instantiate the Unit Under Test (UUT)
Sch_test_SLAVE uut (
.st(st),
.LOAD(LOAD),
.clk(clk),
.SCLK(SCLK),
.MTX_DAT(MTX_DAT),
.MOSI(MOSI),
.RESET(RESET),
.MRX_DAT(MRX_DAT),
.sr_MTX(sr_MTX),
.sr_MRX(sr_MRX),
.cb_bit(cb_bit),
.ce_tact(ce_tact),
.STX_DAT(STX_DAT),
.MISO(MISO),
.sr_STX(sr_STX),
.sr_SRX(sr_SRX),
.SRX_DAT(SRX_DAT)
);
always begin
clk = 0;
#10;
clk = 1;
#10;
end
initial begin
// Initialize Inputs
st = 0;
MTX_DAT = 12'b011100000010;
RESET = 0;
STX_DAT = 12'b111001101100;
#1000;
st = 1;
#20;
st = 0;
#20000;
RESET = 1;
#20;
RESET = 0;
end
endmodule
| 6.66783 |
module spi_avalon_pio (
clk_clk,
pio_data_export,
reset_reset_n,
spi_bridge_mosi_to_the_spislave_inst_for_spichain,
spi_bridge_nss_to_the_spislave_inst_for_spichain,
spi_bridge_miso_to_and_from_the_spislave_inst_for_spichain,
spi_bridge_sclk_to_the_spislave_inst_for_spichain
);
input clk_clk;
output [31:0] pio_data_export;
input reset_reset_n;
input spi_bridge_mosi_to_the_spislave_inst_for_spichain;
input spi_bridge_nss_to_the_spislave_inst_for_spichain;
inout spi_bridge_miso_to_and_from_the_spislave_inst_for_spichain;
input spi_bridge_sclk_to_the_spislave_inst_for_spichain;
endmodule
| 7.467778 |
module spi_axi_slave_tb ();
// HELPER
function integer clogb2;
input integer value;
integer i;
begin
clogb2 = 0;
for (i = 0; 2 ** i < value; i = i + 1) clogb2 = i + 1;
end
endfunction
localparam tries = 512;
localparam sword = 32;
localparam impl = 0;
localparam syncing = 0;
// Autogen localparams
reg CLK = 1'b0;
reg RST;
// AXI4-lite master memory interfaces
reg axi_awvalid;
wire axi_awready;
reg [sword-1:0] axi_awaddr;
reg [ 3-1:0] axi_awprot;
reg axi_wvalid;
wire axi_wready;
reg [sword-1:0] axi_wdata;
reg [ 4-1:0] axi_wstrb;
wire axi_bvalid;
reg axi_bready;
reg axi_arvalid;
wire axi_arready;
reg [sword-1:0] axi_araddr;
reg [ 3-1:0] axi_arprot;
wire axi_rvalid;
reg axi_rready;
wire [sword-1:0] axi_rdata;
// SPI interface
wire SCLK;
wire CEB;
wire DATA;
// Data per capturing
reg [sword-1:0] cap;
integer fd1, tmp1, ifstop;
integer PERIOD = 20;
integer i, j, error, l;
spi_axi_slave inst_spi_axi_slave (
.CLK(CLK),
.RST(RST),
.SCLK(SCLK),
.CEB(CEB),
.DATA(DATA),
.axi_awvalid(axi_awvalid),
.axi_awready(axi_awready),
.axi_awaddr(axi_awaddr),
.axi_awprot(axi_awprot),
.axi_wvalid(axi_wvalid),
.axi_wready(axi_wready),
.axi_wdata(axi_wdata),
.axi_wstrb(axi_wstrb),
.axi_bvalid(axi_bvalid),
.axi_bready(axi_bready),
.axi_arvalid(axi_arvalid),
.axi_arready(axi_arready),
.axi_araddr(axi_araddr),
.axi_arprot(axi_arprot),
.axi_rvalid(axi_rvalid),
.axi_rready(axi_rready),
.axi_rdata(axi_rdata)
);
always begin
#(PERIOD / 2) CLK = ~CLK;
end
task aexpect;
input [sword-1:0] av, e;
begin
if (av == e)
$display("TIME=%t.", $time, " Actual value of trans=%b, expected is %b. MATCH!", av, e);
else begin
$display("TIME=%t.", $time, " Actual value of trans=%b, expected is %b. ERROR!", av, e);
error = error + 1;
end
end
endtask
reg [63:0] xorshift64_state = 64'd88172645463325252;
task xorshift64_next;
begin
// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
end
endtask
initial begin
$sdf_annotate("spi_axi_slave.sdf", inst_spi_axi_slave);
CLK = 1'b0;
RST = 1'b0;
cap = {sword{1'b0}};
error = 0;
axi_awvalid = 1'b0;
axi_wvalid = 1'b0;
axi_bready = 1'b0;
axi_arvalid = 1'b0;
axi_rready = 1'b0;
axi_awaddr = {sword{1'b0}};
axi_awprot = {3{1'b0}};
axi_wdata = {sword{1'b0}};
axi_wstrb = 4'b1111;
axi_araddr = {sword{1'b0}};
axi_arprot = {3{1'b0}};
#101;
RST = 1'b1;
// WRITTING AND READING TEST
// BASICALLY, WHAT I READ, IS WHAT I WRITE
for (i = 0; i < tries; i = i + 1) begin
#(PERIOD * 8);
// WRITTING TEST
axi_awvalid = 1'b1;
#PERIOD;
while (!axi_awready) begin
#PERIOD;
end
axi_wvalid = 1'b1;
axi_wdata = xorshift64_state[sword-1:0];
while (!axi_wready) begin
#PERIOD;
end
while (!axi_bvalid) begin
#PERIOD;
end
axi_bready = 1'b1;
#PERIOD;
axi_awvalid = 1'b0;
axi_wvalid = 1'b0;
axi_bready = 1'b0;
// Waiting the SPI for finishing
while (!CEB) begin
#PERIOD;
end
aexpect(cap, xorshift64_state[sword-1:0]);
xorshift64_next;
end
$timeformat(-9, 0, "ns", 7);
#(PERIOD * 8)
if (error == 0) $display("All match");
else $display("Mismatches = %d", error);
$finish;
end
always @(posedge SCLK) begin
if (CEB == 1'b0) begin
cap = {cap[sword-2:0], DATA};
end
end
endmodule
| 7.287623 |
module spi_bidir_clgen (
clk_in,
rst,
go,
enable,
last_clk,
divider,
clk_out,
pos_edge,
neg_edge
);
parameter Tp = 1;
input clk_in; // input clock (system clock)
input rst; // reset
input enable; // clock enable
input go; // start transfer
input last_clk; // last clock
input [`SPI_DIVIDER_LEN-1:0] divider; // clock divider (output clock is divided by this value)
output clk_out; // output clock
output pos_edge; // pulse marking positive edge of clk_out
output neg_edge; // pulse marking negative edge of clk_out
reg clk_out;
reg pos_edge;
reg neg_edge;
reg [`SPI_DIVIDER_LEN-1:0] cnt; // clock counter
wire cnt_zero; // conter is equal to zero
wire cnt_one; // conter is equal to one
assign cnt_zero = cnt == {`SPI_DIVIDER_LEN{1'b0}};
assign cnt_one = cnt == {{`SPI_DIVIDER_LEN - 1{1'b0}}, 1'b1};
// Counter counts half period
always @(posedge clk_in or posedge rst) begin
if (rst) cnt <= #Tp{`SPI_DIVIDER_LEN{1'b1}};
else begin
if (!enable || cnt_zero) cnt <= #Tp divider;
else cnt <= #Tp cnt - {{`SPI_DIVIDER_LEN - 1{1'b0}}, 1'b1};
end
end
// clk_out is asserted every other half period
always @(posedge clk_in or posedge rst) begin
if (rst) clk_out <= #Tp 1'b0;
else clk_out <= #Tp(enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
end
// Pos and neg edge signals
always @(posedge clk_in or posedge rst) begin
if (rst) begin
pos_edge <= #Tp 1'b0;
neg_edge <= #Tp 1'b0;
end else begin
pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
neg_edge <= #Tp(enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
end
end
endmodule
| 6.931618 |
module BIST (
input wire clk,
input wire reset,
input wire master_writeread,
input wire [7:0] MOSI_user_input,
input wire [7:0] MISO_user_input,
input wire select,
output wire CS,
output wire S_clk,
output wire [3:0] counter,
output wire MOSI_res,
output wire MISO_res,
output wire [7:0] BIST_output
);
wire MOSI_data_out;
wire MISO_data_out;
wire [7:0] MOSI_data;
wire [7:0] MISO_data;
wire [7:0] BIST_mode_mux_out;
wire [4:0] count;
wire [7:0] MOSI_out; ///MUX input MOSI side
wire [7:0] MISO_out; //MUX input MISO side
wire [7:0] LFSR_out;
BIST_MUX M1 (
MOSI_user_input,
LFSR_out,
select,
MOSI_out
);
BIST_MUX M2 (
MISO_user_input,
LFSR_out,
select,
MISO_out
);
LFSR V0 (
clk,
reset,
LFSR_out,
count
);
spi_master V1 (
MOSI_out,
MISO_data_out,
reset,
clk,
master_writeread,
CS,
S_clk,
MOSI_data_out,
counter,
MISO_data
);
spi_slave V2 (
clk,
reset,
MOSI_data_out,
master_writeread,
MISO_out,
MISO_data_out,
MOSI_data
);
Cmp V3 (
clk,
select,
count,
LFSR_out,
MOSI_data,
LFSR_out,
MISO_data,
MOSI_res,
MISO_res
);
assign BIST_output = LFSR_out;
endmodule
| 8.224113 |
module Cmp (
input wire clk,
input wire select,
input wire [4:0] count,
input wire [7:0] MOSI_in_data,
input wire [7:0] MOSI_out_data,
input wire [7:0] MISO_in_data,
input wire [7:0] MISO_out_data,
output wire MOSI_result,
output wire MISO_result
);
reg MOSI_res;
reg MISO_res;
reg [7:0] MOSI_in_data_reg;
reg [7:0] MOSI_out_data_reg;
reg [7:0] MISO_in_data_reg;
reg [7:0] MISO_out_data_reg;
always @(posedge clk) begin
if (select == 1) begin
if (count == 0) begin
MOSI_in_data_reg = MOSI_in_data;
MISO_in_data_reg = MISO_in_data;
end
if (count == 9) begin
MOSI_out_data_reg = MOSI_out_data;
MISO_out_data_reg = MISO_out_data;
end
if (MOSI_in_data_reg == MOSI_out_data_reg) MOSI_res = 1'd1;
else MOSI_res = 1'd0;
if (MISO_in_data_reg == MISO_out_data_reg) MISO_res = 1'd1;
else MISO_res = 1'd0;
end
end
assign MISO_result = MISO_res;
assign MOSI_result = MOSI_res;
endmodule
| 7.700968 |
module BIST_tb;
reg clk;
reg reset;
reg master_writeread;
reg [7:0] MOSI_user_input;
reg [7:0] MISO_user_input;
reg select;
wire CS;
wire S_clk;
wire [3:0] counter;
wire MOSI_res;
wire MISO_res;
wire [7:0] BIST_output;
BIST dut (
.clk(clk),
.reset(reset),
.master_writeread(master_writeread),
.MOSI_user_input(MOSI_user_input),
.MISO_user_input(MISO_user_input),
.select(select),
.CS(CS),
.S_clk(S_clk),
.counter(counter),
.MOSI_res(MOSI_res),
.MISO_res(MISO_res),
.BIST_output(BIST_output)
);
initial begin
clk = 0;
reset = 1;
master_writeread = 1;
select = 1;
MOSI_user_input = 8'hf0;
MISO_user_input = 8'hf0;
end
always #10 clk = ~clk;
initial begin
$dumpfile("output2.vcd");
$dumpvars;
end
initial begin
#20 reset = 1'b0;
end
initial begin
#1000 $finish;
end
endmodule
| 6.526458 |
module spi_block (
clk,
out_bit,
in_bit,
data_out,
chip_select,
data_clk,
data_ready,
finished_reading,
reset
);
input clk;
input reset;
input finished_reading;
output out_bit;
output [7:0] data_out;
output data_ready;
//input wire in_bit;
wire shift_out_clk;
wire shift_in_clk;
output wire data_clk;
input wire in_bit;
reg load_shift_register;
wire shifting_finished;
wire read_shifting_finished;
wire out_bit;
wire [7:0] shift_out_wire;
(*KEEP = "FALSE"*) reg [2:0] state = 0;
reg init_counter = 0;
output reg chip_select = 1;
wire vcc_wire;
wire gnd_wire;
wire floating_wire;
reg [7:0] shifted_data;
reg [31:0] in_data = 32'h0300_0000;
(*KEEP = "FALSE"*) reg [4:0] remaining_send;
(*KEEP = "FALSE"*) reg [2:0] remaining_receive;
//reg [7:0] out_data;
assign data_ready = (state >= 3) & (remaining_receive == 0);
//assign data_out = out_data;//shifted_data;
assign data_out = shift_out_wire; //shifted_data;
assign vcc_wire = 1;
assign gnd_wire = 0;
//NB!!!
//assign shift_out_clk = chip_select ? 0 : ~data_clk;
assign shift_in_clk = (state == 3) ? data_clk : 1;
assign data_clk = chip_select ? 0 : clk;
always @(posedge clk)
if (!reset)
case (state)
0: state <= 1;
1: state <= 2; // status 2 = start shifting;
2: state <= (remaining_send == 0) ? 3 : 2;
//3: state <= 4;
3: state <= (remaining_receive == 0) ? 4 : 3;
4: state <= 4;
// 4: state <= ;
default: state <= state;
endcase
// always @(negedge clk)
// data_clock_enabled <= ~chip_select;
//assign data_clock = data_clock_enabled ? clk : 0;
always @(negedge clk) chip_select <= (state > 0 & !finished_reading) ? 0 : 1;
always @*
if (state == 1) begin
init_counter <= 1;
//in_data <= 32'h9000_0001;
end else init_counter <= 0;
always @(posedge clk)
if (state == 1) remaining_send <= 31;
else remaining_send <= remaining_send - 1;
always @(posedge clk)
if (state == 1) remaining_receive <= 7;
else if (state >= 3) remaining_receive <= remaining_receive - 1;
else remaining_receive <= remaining_receive;
//always @(negedge clk)
// if ((state >= 3) & (remaining_receive == 0))
//out_data <= shift_out_wire;
//always @(posedge clk)
// init_counter <= (state == 1) ? 1 : 0;
shift_out_reg send_reg (
clk,
in_data,
init_counter,
out_bit
);
//always @(posedge read_shifting_finished)
// shifted_data <= {shift_out_wire[7:0]};
shift_in_reg recive_reg (
clk, //??????????
in_bit,
shift_out_wire // out data??????
);
endmodule
| 6.784186 |
module and the Zynq PS SPI interface.
//
// History:
// 02/23/19: Created
//
// License: BSD 3-Clause
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module spi_bridge(
// SPI Slave Interface
input M_SPI_SCLK_O,
input M_SPI_SCLK_TN,
output M_SPI_SCLK_I,
input M_SPI_MOSI_O,
input M_SPI_MOSI_TN,
output M_SPI_MOSI_I,
output M_SPI_MISO_I,
input M_SPI_MISO_TN,
input M_SPI_MISO_O,
input M_SPI_SS_TN,
input M_SPI_SS_O,
input M_SPI_SS1_O,
input M_SPI_SS2_O,
output M_SPI_SS_I,
// LSM9DS1 Interface
inout SCK_AGM,
inout MOSI_AGM,
input MISO_AG,
input MISO_M,
inout SS_AG,
inout SS_M
);
// Tri-state logic for SPI CLK
assign SCK_AGM = (M_SPI_SCLK_TN == 1'b0) ? M_SPI_SCLK_O : 1'bZ;
assign M_SPI_SCLK_I = 1'b0;
// Tri-state Logic for SPI MOSI
assign MOSI_AGM = (M_SPI_MOSI_TN == 1'b0) ? M_SPI_MOSI_O : 1'bZ;
assign M_SPI_MOSI_I = 1'b0;
// Mux Logic for MISO, MISO_TN/MISO_O - nc
assign M_SPI_MISO_I = (M_SPI_SS_O == 1'b0 && M_SPI_SS_TN == 1'b0) ? MISO_AG :
((M_SPI_SS1_O == 1'b0 && M_SPI_SS_TN == 1'b0) ? MISO_M : 1'b1);
// Tri-state for SS
// SS0 - SS_AG
// SS1 - SS_M
// SS2 - nc
assign SS_AG = (M_SPI_SS_TN == 1'b0) ? M_SPI_SS_O : 1'bZ;
assign SS_M = (M_SPI_SS_TN == 1'b0) ? M_SPI_SS1_O : 1'bZ;
// M_SPI_SS_I must be tied high in the PL stream to ensure that the PS-PL level
// shifters are enabled. See UG585 Zynq TRM Chapter 17.
assign M_SPI_SS_I = 1'b1;
endmodule
| 7.982139 |
module spi_buttons (
// pins
input spi_mosi,
output spi_miso,
input spi_cs_n,
input spi_clk,
output irq_n,
input clk,
input resetq,
// outputs
output joystick_down,
output joystick_up,
output joystick_left,
output joystick_right,
output joystick_press,
output home,
output menu,
output select,
output start,
output accept,
output back
);
// -----------------------------------------------
// SPI interface
// -----------------------------------------------
wire [7:0] usr_miso_data, usr_mosi_data;
wire usr_mosi_stb, usr_miso_ack;
wire csn_state, csn_rise, csn_fall;
spi_dev_core _communication (
.clk(clk),
.rst(resetq),
.usr_mosi_data(usr_mosi_data),
.usr_mosi_stb (usr_mosi_stb),
.usr_miso_data(usr_miso_data),
.usr_miso_ack (usr_miso_ack),
.csn_state(csn_state),
.csn_rise (csn_rise),
.csn_fall (csn_fall),
// Interface to SPI wires
.spi_miso(spi_miso),
.spi_mosi(spi_mosi),
.spi_clk (spi_clk),
.spi_cs_n(spi_cs_n)
);
wire [7:0] pw_wdata;
wire pw_wcmd, pw_wstb, pw_end;
spi_dev_proto #(
.NO_RESP(1)
) _protocol (
.clk(clk),
.rst(resetq),
// Connection to the actual SPI module:
.usr_mosi_data(usr_mosi_data),
.usr_mosi_stb (usr_mosi_stb),
.usr_miso_data(usr_miso_data),
.usr_miso_ack (usr_miso_ack),
.csn_state(csn_state),
.csn_rise (csn_rise),
.csn_fall (csn_fall),
// These wires deliver received data:
.pw_wdata(pw_wdata),
.pw_wcmd (pw_wcmd),
.pw_wstb (pw_wstb),
.pw_end (pw_end),
);
reg [ 7:0] command;
reg [31:0] incoming_data;
reg [31:0] buttonstate;
always @(posedge clk) begin
if (pw_wstb & pw_wcmd) command <= pw_wdata;
if (pw_wstb) incoming_data <= incoming_data << 8 | pw_wdata;
if (pw_end & (command == 8'hF4)) buttonstate <= incoming_data;
end
assign joystick_down = buttonstate[16];
assign joystick_up = buttonstate[17];
assign joystick_left = buttonstate[18];
assign joystick_right = buttonstate[19];
assign joystick_press = buttonstate[20];
assign home = buttonstate[21];
assign menu = buttonstate[22];
assign select = buttonstate[23];
assign start = buttonstate[24];
assign accept = buttonstate[25];
assign back = buttonstate[26];
/*
Bits are mapped to the following keys:
0 - joystick down
1 - joystick up
2 - joystick left
3 - joystick right
4 - joystick press
5 - home
6 - menu
7 - select
8 - start
9 - accept
10 - back
*/
endmodule
| 9.468796 |
module spi_byte (
input wire sysClk, // FPGA system clock (must be several times faster as SCLK, e.g. 66MHz)
input wire usrReset, // FPGA user reset button
input wire SCLK, // SPI clock (e.g. 4 MHz)
input wire MOSI, // SPI master out, slave in
output wire MISO, // SPI slave in, master out
input wire SS, // SPI slave select
output reg LED1
); // output bit
wire rxValid;
wire [7:0] rx, tx;
// bits <> bytes
spi_byte_if byte_if (
.sysClk (sysClk),
.usrReset(usrReset),
.SCLK (SCLK),
.MOSI (MOSI),
.MISO (MISO),
.SS (SS),
.rxValid (rxValid),
.rx (rx),
.tx (8'h55)
);
// byte received controls an LED
always @(posedge sysClk) if (rxValid) LED1 <= (rx == 8'hAA);
endmodule
| 6.828003 |
module spi_byte_if (
input wire sysClk,
input wire usrReset,
input wire SCLK, // SPI clock
input wire MOSI, // SPI master out, slave in
output wire MISO, // SPI slave in, master out
input wire SS, // SPI slave select
output wire rxValid, // BYTE received is valid
output reg [7:0] rx, // BYTE received
input wire [7:0] tx
); // BYTE to transmit
// synchronize SCLK to FPGA domain clock using a two-stage shift-register
// (bit [0] takes the hit of timing errors)
reg [2:0] SCLKr;
always @(posedge sysClk) SCLKr <= {SCLKr[1:0], SCLK};
reg [1:0] SSr;
always @(posedge sysClk) SSr <= {SSr[0], SS};
reg [1:0] MOSIr;
always @(posedge sysClk) MOSIr <= {MOSIr[0], MOSI};
wire SCLK_rising = ( SCLKr[2:1] == 2'b01 );
wire SCLK_falling = ( SCLKr[2:1] == 2'b10 );
wire SS_active = ~SSr[1]; // synchronous version of ~SS input
wire MOSI_s = MOSIr[1]; // synchronous version of MOSI input
// next state logic
reg [2:0] state; // state corresponds to bit count
localparam [2:0] STATE_WAIT4BIT7 = 3'd0,
STATE_WAIT4BIT6 = 3'd1,
STATE_WAIT4BIT5 = 3'd2,
STATE_WAIT4BIT4 = 3'd3,
STATE_WAIT4BIT3 = 3'd4,
STATE_WAIT4BIT2 = 3'd5,
STATE_WAIT4BIT1 = 3'd6,
STATE_WAIT4BIT0 = 3'd7;
reg [2:0] nState;
// control path, next state logic
always @(*)
if (SS_active)
if (SCLK_rising) nState = state + 3'd1;
else nState = state;
else nState = STATE_WAIT4BIT7;
// control path, current state logic
always @(posedge sysClk or posedge usrReset)
if (usrReset) state <= STATE_WAIT4BIT7;
else state <= nState;
// data path
reg [7:0] data = 8'hxx, nData;
reg rxAvail = 1'b0, nRxAvail;
reg [7:0] nRx;
reg MISOr = 1'bx, nMISOr;
// data path, next state logic
wire [7:0] rx_next = {data[6:0], MOSI_s};
always @(*) begin
nData = data; // assume all stays the same unless noted
nRx = rx;
nRxAvail = rxAvail;
nMISOr = MISOr;
if (SS_active)
if ( SCLK_rising ) // input on rising PCI clock edge
begin
nData = rx_next;
if (state == STATE_WAIT4BIT0) begin
nRx = rx_next; // grab data received
nRxAvail = 1'b1;
end else nRxAvail = 1'b0;
end
else if ( SCLK_falling) // output on falling PCI clock edge
begin
if (state == STATE_WAIT4BIT7) begin
nData = tx; // get data to transmit
nMISOr = tx[7];
end else nMISOr = data[7];
end
end
// data path, current state logic
always @(posedge sysClk or posedge usrReset)
if (usrReset) begin
rx <= 8'hxx;
rxAvail <= 1'b0;
data <= 8'hxx;
MISOr <= 1'bx;
end else begin
rx <= nRx;
rxAvail <= nRxAvail;
data <= nData;
MISOr <= nMISOr;
end
// data path, output logic
assign MISO = SS_active ? MISOr : 1'bz; // send MSB first
reg rxAvailFall; // make rxAvail change on the falling edge
reg rxAvailFall_dly; // make it 1 cycle wide
always @(negedge sysClk) rxAvailFall <= rxAvail;
always @(negedge sysClk) rxAvailFall_dly <= rxAvailFall;
assign rxValid = rxAvailFall & ~rxAvailFall_dly;
endmodule
| 9.48502 |
module spi_chunk (
input CLK,
input RST,
inout SDIO,
output reg SCLK,
output reg CSB,
input [7:0] data_i,
input read_i,
input start_i,
output reg [7:0] data_o,
output busy_o,
output finish_o
);
reg [1:0] state;
parameter s_idle = 2'b00;
parameter s_waitcsb = 2'b01;
parameter s_sending = 2'b10;
reg [3:0] bitcounter;
wire sdio_reg;
wire sdio_en;
reg [7:0] data;
reg read;
assign SDIO = sdio_en ? sdio_reg : 1'bz;
assign sdio_en = (!read && state == s_sending);
assign sdio_reg = data[7];
assign busy_o = state != s_idle || start_i;
assign finish_o = state == s_sending && bitcounter == 4'h7 && SCLK;
always @(posedge CLK or negedge RST)
if (!RST) begin
state <= s_idle;
end else begin
case (state)
s_idle: if (start_i) state <= s_waitcsb;
s_waitcsb: state <= s_sending;
s_sending: if (bitcounter == 4'd7 && SCLK) state <= s_idle;
default: ;
endcase
end
always @(posedge CLK or negedge RST)
if (!RST) begin
bitcounter <= 4'd0;
end else begin
case (state)
s_sending: if (SCLK) bitcounter <= bitcounter + 4'd1;
default: bitcounter <= 4'd0;
endcase
end
always @(posedge CLK or negedge RST)
if (!RST) begin
SCLK <= 1'b0;
end else begin
case (state)
s_idle: SCLK <= 1'b0;
s_sending: SCLK <= ~SCLK;
endcase
end
always @(posedge CLK or negedge RST)
if (!RST) begin
CSB <= 1'b1;
end else begin
case (state)
s_idle:
if (start_i) CSB <= 1'b0;
else CSB <= 1'b1;
default: ;
endcase
end
always @(posedge CLK or negedge RST)
if (!RST) begin
data <= 8'h0;
end else begin
case (state)
s_idle: if (start_i) data <= data_i;
s_sending: if (SCLK) data <= {data[6:0], 1'b0};
endcase
end
always @(posedge CLK or negedge RST)
if (!RST) begin
read <= 1'b0;
end else begin
if (start_i) begin
read <= read_i;
end
end
always @(posedge CLK or negedge RST)
if (!RST) begin
data_o <= 8'h0;
end else begin
case (state)
s_sending: if (!SCLK) data_o <= {data_o[6:0], SDIO};
default: ;
endcase
end
endmodule
| 7.111754 |
module spi_clgen (
clk_in,
rst,
go,
enable,
last_clk,
divider,
clk_out,
pos_edge,
neg_edge
);
parameter Tp = 1;
parameter SPI_DIVIDER_LEN = 8;
input clk_in; // input clock (system clock)
input rst; // reset
input enable; // clock enable
input go; // start transfer
input last_clk; // last clock
input [SPI_DIVIDER_LEN-1:0] divider; // clock divider (output clock is divided by this value)
output clk_out; // output clock
output pos_edge; // pulse marking positive edge of clk_out
output neg_edge; // pulse marking negative edge of clk_out
reg clk_out = 1'b0;
reg pos_edge;
reg neg_edge;
reg [SPI_DIVIDER_LEN-1:0] cnt; // clock counter
wire cnt_zero; // conter is equal to zero
wire cnt_one; // conter is equal to one
assign cnt_zero = cnt == {SPI_DIVIDER_LEN{1'b0}};
assign cnt_one = cnt == {{SPI_DIVIDER_LEN - 1{1'b0}}, 1'b1};
// Counter counts half period
always @(posedge clk_in or posedge rst) begin
if (rst) cnt <= #Tp{SPI_DIVIDER_LEN{1'b1}};
else begin
if (!enable || cnt_zero) cnt <= #Tp divider;
else cnt <= #Tp cnt - {{SPI_DIVIDER_LEN - 1{1'b0}}, 1'b1};
end
end
// clk_out is asserted every other half period
always @(posedge clk_in or posedge rst) begin
if (rst) clk_out <= #Tp 1'b0;
else clk_out <= #Tp(enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
end
// Pos and neg edge signals
always @(posedge clk_in or posedge rst) begin
if (rst) begin
pos_edge <= #Tp 1'b0;
neg_edge <= #Tp 1'b0;
end else begin
pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
neg_edge <= #Tp(enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
end
end
endmodule
| 6.677874 |
module spi_clkgen (
input clk_in, // input clock (system clock)
input rst, // reset
input enable, // clock enable
input go, // start transfer
input last_clk, // last clock
input [31:0] divider, // clock divider (output clock is divided by this value)
output reg clk_out, // output clock
output reg pos_edge, // pulse marking positive edge of clk_out
output reg neg_edge // pulse marking negative edge of clk_out
);
//Local Parameters
//Registers/Wires
reg [311:0] cnt; // clock counter
wire cnt_zero; // conter is equal to zero
wire cnt_one; // conter is equal to one
//Submodules
//Asynchronous Logic
assign cnt_zero = (cnt == 32'h0);
assign cnt_one = (cnt == 32'h00000001);
//Synchronous Logic
// Counter counts half period
always @(posedge clk_in or posedge rst) begin
if (rst) begin
cnt <= 32'h00000001;
end else begin
if (!enable || cnt_zero) begin
cnt <= divider;
end else begin
cnt <= cnt - 32'h00000001;
end
end
end
// clk_out is asserted every other half period
always @(posedge clk_in or posedge rst) begin
if (rst) begin
clk_out <= 1'b0;
end else begin
clk_out <= (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
end
end
// Pos and neg edge signals
always @(posedge clk_in or posedge rst) begin
if (rst) begin
pos_edge <= 1'b0;
neg_edge <= 1'b0;
end else begin
pos_edge <= (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
neg_edge <= (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
end
end
endmodule
| 6.539467 |
module spi_clk_gen #(
parameter SPI_RATIO_GRADE = 3
) ( /*AUTOARG*/
// Outputs
spi_clk_o,
// Inputs
clk_i,
arst_n_i,
en_i,
ratio_i
);
/* ports */
input clk_i;
input arst_n_i;
input en_i;
input [SPI_RATIO_GRADE-1:0] ratio_i;
output spi_clk_o;
/* ratio-driven clock generator */
ratio_clk #(
.RATIO_GRADE(SPI_RATIO_GRADE)
) ratio_clk_inst (
.clk_i (clk_i),
.arst_n_i (arst_n_i),
.en_i (en_i),
.ratio_i (ratio_i),
.ratio_clk_o(spi_clk_o)
);
endmodule
| 6.897232 |
module spi_clock_gen #(
parameter Nc=6, //Разрядность количества импульсов, которые надо сгенерировать
THalfSpiClk = 10, //Полупериод SPI Clock в тактах clk
TCS=20 //Время между приходом строба start и первым импульсом spi_clk
) (
input rst, //Асинхронный сброс
input clk, //Тактовый генератор
input start, //Старт генерации clk_count импульсов
input [Nc-1:0] clk_count, //Количество циклов, передачи данных
output neg_edge_st, //Строб отрицательного фронта
output pos_edge_st, //Строб положительного фронта
output reg spi_clk, //Текущее состояние на выходе тактового генератора
output reg [Nc-1:0]clk_num, //Номер текущего генерируемого импульса
output reg [Nc-1:0]last_clk_num, //Номер последнего импульса (включая тот, что передается при CS=1)
output reg busy //Индикатор того, что модуль занят
);
function integer log2; //Функция выисления логорифма по основанию 2
input integer value;
begin
for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1;
end
endfunction
parameter Nt = (TCS > THalfSpiClk) ? log2(
TCS
) : log2(
THalfSpiClk
); //Количество бит, необходимое для хранения текущего состояния таймера
reg [Nt-1:0] t_cnt; //Таймер обратного отсчета времени цикла
always @(posedge clk, posedge rst)
if (rst) begin
t_cnt <= 0;
spi_clk <= 0;
end else if (!busy) begin
if (start) //Если пришел строб старта
t_cnt <= TCS; //то ждем TCS и далее начинаем формировать импульсы
spi_clk <= 0; //В режиме ожидания держим spi_clk в 0
end else begin
if(t_cnt == 0) //Если ожидание в полпериода закончилось
begin
spi_clk <= ~spi_clk; //Меняем состояние spi_clk
t_cnt <= THalfSpiClk; //Ждем очередные пол периода
end else
t_cnt <= t_cnt - 1; //В моменты ожидания обновляем значения таймера
end
always @(posedge clk, posedge rst)
if (rst) begin
busy <= 0;
clk_num <= 0;
last_clk_num <= 0;
end
else if(!busy) //Если модуль свободен
begin
if(start) //И приходит строб на старт
begin
clk_num <=0; //то выставляем busy, вычисляем номер последнего цикла
last_clk_num <= clk_count; //и обнуляем счетчик импульсов
busy <= 1;
end
end else
if(neg_edge_st) //Если на выход был выдан отрицательный строб
begin
if(clk_num == last_clk_num) //Если только что передали последний цикл
begin
busy <= 0; //Снимаем busy и переходим к ожиданию нового строба start
clk_num <= 0;
end else begin
clk_num <= clk_num + 1; //Иначе увеличиваем номер формируемого импульса
end
end
reg prev_spi_clk; //Предыдущее значение spi_clk для определения фронтов
always @(posedge clk, posedge rst)
if (rst) prev_spi_clk <= 0;
else prev_spi_clk <= spi_clk;
//Формирование стробов фронтов
assign pos_edge_st = (!prev_spi_clk) & spi_clk;
assign neg_edge_st = prev_spi_clk & (!spi_clk);
endmodule
| 7.887818 |
module spi_clock_generator (
//CLK
// i_clk is the system clock (10-200MHz)
input i_clk,
//RST
// i_reset is the system reset. This is a active high signal.
// '1' : reset is active
input i_reset,
//Controll inputs from registers
input i_spr0,
input i_spr1,
input i_cpol,
input i_cpha,
input i_mstr,
// Controll output to other logic
// o_sclk: This is the SPI clock. The polarity based on the i_cpol
// The frequency is derived by i_spr0 and i_spr1
output o_sclk,
// o_sclk_rising_edge: is active one sys clk long at the rising edge of
// the sclk.
output o_sclk_rising_edge,
// o_sclk_falling_edge: is active one sys clk long at the falling edge of
// the sclk.
output o_sclk_falling_edge,
// o_sample_spi_data: is active one sys clk long at an edge of the spi slck
// i_cpha and i_cpol describe if it is the rising or the falling edge.
output o_sample_spi_data,
// o_setup_spi_data: is active one sys clk long at an edge of the spi slck
// i_cpha and i_cpol describe if it is the rising or the falling edge.
// Note that this is the alter edge than o_sample_spi_data
output o_setup_spi_data
);
// The spi clock counter. The max value is depends on the frequency which
// derived by i_spr0 and i_spr1
reg [6:0] q_spi_sclk_cntr;
wire w_sclk_internal;
wire [1:0]w_clk_select;
reg q_sclk_internal_d1; //alwaysbe reg, d1->eggyel kesleltetett
wire w_sclk_rising_edge_internal;
wire w_sclk_falling_edge_internal;
wire w_sample_spi_data_internal;
wire w_setup_spi_data;
wire [1:0] w_sample_setup_select;
always @(posedge i_clk) begin : SCLK_CNTR
if (i_reset) begin
q_spi_sclk_cntr <= 7'b0;
end else begin
q_spi_sclk_cntr <= q_spi_sclk_cntr + 1;
end
end
assign w_clk_select = {i_spr0, i_spr1};
assign w_sclk_internal = (w_clk_select==0) ? q_spi_sclk_cntr[1] :
(w_clk_select==1) ? q_spi_sclk_cntr[3] :
(w_clk_select==2) ? q_spi_sclk_cntr[5] :
(w_clk_select==3) ? q_spi_sclk_cntr[6] :
0; // soha nem jut ide
assign o_sclk = w_sclk_internal;
always @(posedge i_clk) begin : SCLK_EDGE_DETECT
if (i_reset) begin
q_sclk_internal_d1 <= 0;
end else begin
q_sclk_internal_d1 <= w_sclk_internal;
end
end
//felfuto el
assign w_sclk_rising_edge_internal = (w_sclk_internal > q_sclk_internal_d1) ? 1:
0; //ha nagyobb az aktualis, mint az elozo ->felfuto
assign o_sclk_rising_edge = w_sclk_rising_edge_internal;
//lefuto el
assign w_sclk_falling_edge_internal = (w_sclk_internal < q_sclk_internal_d1) ? 1:
0; //ha kisebb ->lefuto
assign o_sclk_falling_edge = w_sclk_falling_edge_internal;
assign w_sample_setup_select = {i_cpol, i_cpha};
//o_sample_spi_data
assign w_sample_spi_data_internal = (w_sample_setup_select==0) ? w_sclk_rising_edge_internal:
(w_sample_setup_select==1) ? w_sclk_falling_edge_internal:
(w_sample_setup_select==2) ? w_sclk_falling_edge_internal:
(w_sample_setup_select==3) ? w_sclk_rising_edge_internal:
0;
assign o_sample_spi_data = w_sample_spi_data_internal;
//o_setup_spi_data
assign w_setup_spi_data = (w_sample_setup_select==0) ? w_sclk_falling_edge_internal:
(w_sample_setup_select==1) ? w_sclk_rising_edge_internal:
(w_sample_setup_select==2) ? w_sclk_rising_edge_internal:
(w_sample_setup_select==3) ? w_sclk_falling_edge_internal:
0;
assign o_setup_spi_data = w_setup_spi_data;
// -- TODO --
endmodule
| 7.887818 |
module spi_cmd_sm (
output wire SPI_CMD_reading,
input wire SPI_done,
input wire clk,
input wire reset
);
// state bits
parameter IDLE = 1'b0, // SPI_CMD_reading=0
READING = 1'b1; // SPI_CMD_reading=1
reg state;
reg nextstate;
// comb always block
always @* begin
// Warning I2: Neither implied_loopback nor default_state_is_x attribute is set on state machine - defaulting to implied_loopback to avoid latches being inferred
nextstate = state; // default to hold value because implied_loopback is set
case (state)
IDLE: begin
if (SPI_done == 1) begin
nextstate = READING;
end
end
READING: begin
if (SPI_done == 1) begin
nextstate = IDLE;
end
end
endcase
end
// Assign reg'd outputs to state bits
assign SPI_CMD_reading = state;
// sequential always block
always @(posedge clk or posedge reset) begin
if (reset) state <= IDLE;
else state <= nextstate;
end
// This code allows you to see state names in simulation
`ifndef SYNTHESIS
reg [55:0] statename;
always @* begin
case (state)
IDLE :
statename = "IDLE";
READING:
statename = "READING";
default:
statename = "XXXXXXX";
endcase
end
`endif
endmodule
| 8.36777 |
module spi_masterf (
input clk,
rst,
miso, // flag = 0 means data from slave to master and vice versa
input [1:0] slave,
dtf,
output reg sclk,
mosi,
ssb1,
ssb2
);
reg [7:0] stor_reg1, stor_reg2;
reg [2:0] k, p;
always @(clk) begin
if (rst) begin
stor_reg1 = 8'b01110101;
//stor_reg2 = 8'b01010010;
k = 0;
p = 0;
sclk = 0;
mosi = 0;
ssb1 = 0; // ssb is active low version of ss, ss = !ssb
ssb2 = 0;
end else if (dtf == 2'b01 || dtf == 2'b10 || dtf == 2'b11) begin
sclk = clk;
if (clk) begin
if (slave == 2'b01) begin
ssb1 = 1;
ssb2 = 0;
end else if (slave == 2'b10) begin
ssb2 = 1;
ssb1 = 0;
end else begin
ssb1 = 0;
ssb2 = 0;
end
end
if (dtf == 2'b10 & clk) begin
mosi = stor_reg1[k];
k = k + 1;
end else if (dtf == 2'b01 & clk) begin
stor_reg2[p] = miso;
p = p + 1;
end else if (dtf == 2'b11 & clk) begin
mosi = stor_reg1[k];
k = k + 1;
stor_reg2[p] = miso;
p = p + 1;
end
end
end
endmodule
| 7.746324 |
module spi_slave1f (
input sclk,
mosi,
ssb,
input [1:0] dtf, // flag = 0 means data from slave to master and vice versa
output reg miso
);
reg [7:0] stor_reg1, stor_reg2;
reg [2:0] i, j;
initial begin
stor_reg2 = 8'b01010010;
i = 0;
j = 0;
end
always @(posedge sclk) begin
if (((dtf == 2'b10) || (dtf == 2'b11)) && ssb) begin
stor_reg1[i] = mosi;
i = i + 1;
end
if (((dtf == 2'b01) || (dtf == 2'b11)) && ssb) begin
miso = stor_reg2[j];
j = j + 1;
end
end
endmodule
| 7.116147 |
module spi_slave2f (
input sclk,
mosi,
ssb,
input [1:0] dtf, // flag = 0 means data from slave to master and vice versa
output reg miso
);
reg [7:0] stor_reg1, stor_reg2;
reg [2:0] i, j;
initial begin
stor_reg2 = 8'b01010010;
i = 0;
j = 0;
end
always @(posedge sclk) begin
if (((dtf == 2'b10) || (dtf == 2'b11)) && ssb) begin
stor_reg1[i] = mosi;
i = i + 1;
end
if (((dtf == 2'b01) || (dtf == 2'b11)) && ssb) begin
miso = stor_reg2[j];
j = j + 1;
end
end
endmodule
| 7.141492 |
module spi_topf (
clk,
rst,
miso,
mosi,
dtf,
sclk,
ssb1,
ssb2,
slave
);
input clk, rst;
inout miso, mosi;
inout sclk, ssb1, ssb2;
input [1:0] slave, dtf;
wire miso1, miso2;
assign miso = ((slave == 2'b01) ? miso1 : miso2) && ((dtf == 2'b01) || (dtf == 2'b11));
spi_masterf p1 (
clk,
rst,
miso,
slave,
dtf,
sclk,
mosi,
ssb1,
ssb2
);
spi_slave1f p2 (
sclk,
mosi,
ssb1,
dtf,
miso1
);
spi_slave2f p3 (
sclk,
mosi,
ssb2,
dtf,
miso2
);
endmodule
| 7.052945 |
module spi_config #(
parameter SPI_MAX_WIDTH_LOG = 4
) (
input clk,
rst_n, // Asynchronous reset active low
/*
test
*/
input config_req,
input [SPI_MAX_WIDTH_LOG + 1:0] config_data,
output reg cpol,
output reg cpha,
output reg [SPI_MAX_WIDTH_LOG - 1:0] spi_width
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
{cpol, cpha, spi_width} <= 'b0;
end else if (config_req) begin
{cpol, cpha, spi_width} <= config_data;
end else begin
{cpol, cpha, spi_width} <= {cpol, cpha, spi_width};
end
end
endmodule
| 7.074612 |
module spi_control #(
parameter CFG_FRAME_SIZE = 4
) (
input aresetn,
input sresetn,
input psel,
input penable,
input pwrite,
input [ 6:0] paddr,
input [CFG_FRAME_SIZE-1:0] wr_data_in,
input cfg_master,
input rx_fifo_empty,
input tx_fifo_empty,
output [CFG_FRAME_SIZE-1:0] tx_fifo_data,
output tx_fifo_write,
output tx_fifo_last,
output rx_fifo_read
);
//######################################################################################################
reg tx_fifo_write_sig;
reg rx_fifo_read_sig;
reg tx_last_frame_sig;
// Output assignments.
assign tx_fifo_last = tx_last_frame_sig;
assign tx_fifo_data = wr_data_in;
assign tx_fifo_write = tx_fifo_write_sig;
assign rx_fifo_read = rx_fifo_read_sig;
// Note combinational generation of FIFO read and write signals
always @(*) begin
//defaults
rx_fifo_read_sig = 1'b0; //default no read on rx fifo
tx_fifo_write_sig = 1'b0; //default no write on tx fifo
tx_last_frame_sig = 1'b0; //default not last frame
if (penable && psel) begin
case (paddr) //synthesis parallel_case
6'h0C: //write to transmit fifo
begin
if (pwrite) begin
tx_fifo_write_sig = 1'b1; //write to the fifo
end
end
6'h08: //read from receive fifo
begin
if (~pwrite) begin
rx_fifo_read_sig = 1'b1;
end
end
6'h28: // aliased transmit data, sets last frame bit
begin
if (pwrite) begin
tx_fifo_write_sig = 1'b1; //write to the fifo
tx_last_frame_sig = 1'b1; //last frame
end
end
default: begin
end
endcase
end
end
endmodule
| 7.409405 |
module spi_core (
input wire i_clk,
input wire i_reset_n,
// SPI bus
input wire i_spi_cs_n,
input wire i_spi_sck,
input wire i_spi_si,
output wire o_spi_so,
//
input wire [7:0] i_wr_data,
output wire [7:0] o_rd_data,
output wire o_last_bit
);
reg r_spi_cs_n, r_spi_sck, r_spi_si;
always @(posedge i_clk) begin
r_spi_cs_n <= i_spi_cs_n;
r_spi_sck <= i_spi_sck;
r_spi_si <= i_spi_si;
end
reg r_spi_sck_prev;
always @(posedge i_clk) r_spi_sck_prev <= r_spi_sck;
wire w_sck_rise = r_spi_sck & (!r_spi_sck_prev);
wire w_sck_fall = (!r_spi_sck) & r_spi_sck_prev;
reg [2:0] r_bit_cnt;
reg [7:0] r_dr_in, r_dr_out;
wire w_reset = (i_reset_n == 1'b0) || (r_spi_cs_n == 1'b1);
wire w_last_bit = (r_bit_cnt == 3'b111) & w_sck_fall;
always @(posedge i_clk) begin
if (w_reset) begin
r_bit_cnt <= 3'b000;
end else if (w_sck_rise == 1'b1) begin
//r_dr_in <= { r_spi_si, r_dr_in[7:1] };
r_dr_in <= {r_dr_in[6:0], r_spi_si};
end else if (w_sck_fall == 1'b1) begin
r_bit_cnt <= r_bit_cnt + 1'b1;
if (w_last_bit) begin
r_dr_out <= i_wr_data;
end else begin
//r_dr_out <= { 1'b0, r_dr_out[7:1] };
r_dr_out <= {r_dr_out[6:0], 1'b0};
end
end
end
//assign o_spi_so = r_dr_out[0];
assign o_spi_so = r_dr_out[7];
assign o_rd_data = r_dr_in;
assign o_last_bit = w_last_bit;
endmodule
| 7.598117 |
module adc (
sdo,
spi_clk,
clk,
rst,
conv
);
parameter WIDTH = 14; //multiple of two
parameter PATTERN = {WIDTH / 2{2'b10}};
parameter COUNTMAX = 34;
input rst, conv, spi_clk, clk;
output sdo;
reg [WIDTH-1:0] mem;
reg sdo;
reg flag;
reg [6:0] count;
integer N;
initial begin
mem = PATTERN;
end
/* always@ (posedge conv or posedge rst)
begin
if(rst)
flag <= 0;
else
flag <= 1;
end*/
always @(posedge clk or posedge rst) begin
if (rst) flag <= 0;
else if (conv) flag <= 1;
else if (count == COUNTMAX) begin
count <= 'b0;
flag <= 0;
mem = ~mem;
end
end
always @(negedge spi_clk or posedge rst) begin
if (rst) count <= 0;
else if (flag & !rst)
if (count == COUNTMAX) count <= 'b0;
else count <= count + 1;
end
always @(count) begin
case (count)
0: sdo <= 'bZ;
1: sdo <= 'bZ;
2: sdo <= 'bZ;
3: sdo <= mem[13];
4: sdo <= mem[12];
5: sdo <= mem[11];
6: sdo <= mem[10];
7: sdo <= mem[9];
8: sdo <= mem[8];
9: sdo <= mem[7];
10: sdo <= mem[6];
11: sdo <= mem[5];
12: sdo <= mem[4];
13: sdo <= mem[3];
14: sdo <= mem[2];
15: sdo <= mem[1];
16: sdo <= mem[0];
17: sdo <= 'bZ;
18: sdo <= 'bZ;
19: sdo <= mem[13];
20: sdo <= mem[12];
21: sdo <= mem[11];
22: sdo <= mem[10];
23: sdo <= mem[9];
24: sdo <= mem[8];
25: sdo <= mem[7];
26: sdo <= mem[6];
27: sdo <= mem[5];
28: sdo <= mem[4];
29: sdo <= mem[3];
30: sdo <= mem[2];
31: sdo <= mem[1];
32: sdo <= mem[0];
33: sdo <= 'bZ;
34: sdo <= 'bZ;
default: sdo <= 'bZ;
endcase
end
endmodule
| 7.467564 |
module amp (
spi_clk,
reset,
cs,
din,
dout,
gain_state
);
parameter Tp = 1;
input spi_clk, reset, cs, din;
output dout;
output [7:0] gain_state;
reg [0:7] data;
reg [7:0] gain_state;
reg temp, dout;
always @(cs or reset) begin
if (reset) gain_state <= 'bz;
else gain_state <= #Tp data;
end
always @(posedge spi_clk or posedge reset) begin
if (reset) begin
temp <= 1'b0;
data <= 'b0;
end else if (!cs) begin
data <= #Tp{din, data[0:6]};
temp <= #Tp data[7];
end
end
always @(negedge spi_clk) dout <= #Tp data[7];
endmodule
| 6.993726 |
module dac (
spi_clk,
reset,
cs,
din,
dout,
command,
dacN,
dacDATA
);
parameter Tp = 1;
input spi_clk, reset, cs, din;
output [3:0] command;
output [3:0] dacN;
output [11:0] dacDATA;
output dout;
reg [0:31] data;
reg dout;
reg temp;
assign command = data[0:3];
assign dacN = data[4:7];
assign dacDATA = data[8:19];
always @(posedge spi_clk or posedge reset) begin
if (reset) begin
temp <= 1'b0;
data <= 'b0;
end else if (!cs) begin
data <= #Tp{din, data[0:30]};
temp <= #Tp data[31];
end
end
always @(negedge spi_clk) dout <= #Tp data[31];
endmodule
| 7.762087 |
module spi_clgen (
clk_in,
rst,
go,
enable,
last_clk,
divider,
clk_out,
pos_edge,
neg_edge
);
parameter Tp = 1;
input clk_in; // input clock (system clock)
input rst; // reset
input enable; // clock enable
input go; // start transfer
input last_clk; // last clock
input [`SPI_DIVIDER_LEN-1:0] divider; // clock divider (output clock is divided by this value)
output clk_out; // output clock
output pos_edge; // pulse marking positive edge of clk_out
output neg_edge; // pulse marking negative edge of clk_out
reg clk_out;
reg pos_edge;
reg neg_edge;
reg [`SPI_DIVIDER_LEN-1:0] cnt; // clock counter
wire cnt_zero; // conter is equal to zero
wire cnt_one; // conter is equal to one
assign cnt_zero = cnt == {`SPI_DIVIDER_LEN{1'b0}};
assign cnt_one = cnt == {{`SPI_DIVIDER_LEN - 1{1'b0}}, 1'b1};
// Counter counts half period
always @(posedge clk_in or posedge rst) begin
if (rst) cnt <= #Tp{`SPI_DIVIDER_LEN{1'b1}};
else begin
if (!enable || cnt_zero) cnt <= #Tp divider;
else cnt <= #Tp cnt - {{`SPI_DIVIDER_LEN - 1{1'b0}}, 1'b1};
end
end
// clk_out is asserted every other half period
always @(posedge clk_in or posedge rst) begin
if (rst) clk_out <= #Tp 1'b0;
else clk_out <= #Tp(enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
end
// Pos and neg edge signals
always @(posedge clk_in or posedge rst) begin
if (rst) begin
pos_edge <= #Tp 1'b0;
neg_edge <= #Tp 1'b0;
end else begin
pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
neg_edge <= #Tp(enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
end
end
endmodule
| 6.677874 |
module spi_shift_in (
clk,
rst,
go,
pos_edge,
neg_edge,
rx_negedge,
tip,
last,
p_out,
s_clk,
s_in
);
parameter Tp = 1;
input clk; // system clock
input rst; // reset
// input [`SPI_ADC_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
input go; // start stansfer
input pos_edge; // recognize posedge of sclk
input neg_edge; // recognize negedge of sclk
input rx_negedge; // s_in is sampled on negative edge
output tip; // transfer in progress
output last; // last bit
output [`SPI_ADC_CHAR-1:0] p_out; // parallel out
input s_clk; // serial clk
input s_in; // serial in
reg tip;
reg [ `SPI_ADC_CHAR_LEN_BITS:0] cnt; // data bit count
reg [ `SPI_ADC_CHAR-1:0] data; // shift register
wire [ `SPI_ADC_CHAR_LEN_BITS:0] rx_bit_pos; // next bit position
wire rx_clk; // rx clock enable
wire [`SPI_ADC_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
assign len = 'h20; //Fix LEN since that won't be changing, unless you only want to sample one channel
assign p_out = data;
//LSB last
assign rx_bit_pos = (rx_negedge ? cnt : cnt - {{`SPI_ADC_CHAR_LEN_BITS{1'b0}}, 1'b1});
assign last = !(|cnt);
assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
// Character bit counter
always @(posedge clk or posedge rst) begin
if (rst) cnt <= #Tp{`SPI_ADC_CHAR_LEN_BITS + 1{1'b0}};
else begin
if (tip) cnt <= #Tp pos_edge ? (cnt - {{`SPI_ADC_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
else cnt <= #Tp !(|len) ? {1'b1, {`SPI_ADC_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
end
end
// Transfer in progress
always @(posedge clk or posedge rst) begin
if (rst) tip <= #Tp 1'b0;
else if (go && ~tip) tip <= #Tp 1'b1;
else if (tip && last && pos_edge) tip <= #Tp 1'b0;
end
// Receiving bits from the line
always @(posedge clk or posedge rst) begin
if (rst) data <= #Tp{`SPI_ADC_CHAR{1'b0}};
else if (tip)
data[rx_bit_pos[`SPI_ADC_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_ADC_CHAR_LEN_BITS-1:0]];
end
endmodule
| 7.4541 |
module spi_shift_out (
clk,
rst,
len,
lsb,
go,
pos_edge,
neg_edge,
tx_negedge,
capture,
tip,
last,
p_in,
s_out
);
parameter Tp = 1;
input clk; // system clock
input rst; // reset
input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
input lsb; // lbs first on the line
input go; // start stansfer
input capture; //
input pos_edge; // recognize posedge of sclk
input neg_edge; // recognize negedge of sclk
input tx_negedge; // s_out is driven on negative edge
output tip; // transfer in progress
output last; // last bit
input [23:0] p_in; // parallel in
output s_out; // serial out
reg s_out;
reg tip;
reg [`SPI_CHAR_LEN_BITS:0] cnt; // data bit count
reg [ `SPI_MAX_CHAR-1:0] data; // shift register
wire [`SPI_CHAR_LEN_BITS:0] tx_bit_pos; // next bit position
wire tx_clk; // tx clock enable
assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1};
assign last = !(|cnt);
assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
// Character bit counter
always @(posedge clk or posedge rst) begin
if (rst) cnt <= #Tp{`SPI_CHAR_LEN_BITS + 1{1'b0}};
else begin
if (tip) cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
else cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
end
end
// Transfer in progress
always @(posedge clk or posedge rst) begin
if (rst) tip <= #Tp 1'b0;
else if (go && ~tip) tip <= #Tp 1'b1;
else if (tip && last && pos_edge) tip <= #Tp 1'b0;
end
// Sending bits to the line
always @(posedge clk or posedge rst) begin
if (rst) s_out <= #Tp 1'b0;
else s_out <= #Tp(tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
end
// Capture data from p_in to the
always @(posedge clk or posedge rst) begin
if (rst) data <= #Tp{24{1'b0}};
else if (!tip && capture) data <= #Tp p_in;
end
endmodule
| 7.503529 |
module spi_core_fast (
input wire clk, // main clock
input wire rst, // synchronous reset
input wire en, // enable signal, flag to start transmitting
input wire [DATA_BITS-1:0] din, // data to sent out
output reg [DATA_BITS-1:0] dout, // data received in
output reg ack, // data sent/received acknowledge
output reg busy, // busy flag
// SPI interfaces
output wire sck,
input wire miso,
output reg mosi
);
`include "function.vh"
parameter SPI_CPHA = 0, // clock phase
SPI_CPOL = 0, // clock polarity
SPI_LSBFE = 0, // LSB first enable
DATA_BITS = 8; // data length for transmit
localparam DATA_BITS_WIDTH = GET_WIDTH(DATA_BITS);
reg [DATA_BITS-1:0] data_buf;
ODDR2 #(
.DDR_ALIGNMENT("NONE"),
.INIT(SPI_CPOL ? 1'b1 : 1'b0),
.SRTYPE("SYNC")
) RAM_CLK (
.Q (sck),
.C0(clk),
.C1(~clk),
.CE(busy),
.D0(1'b1),
.D1(1'b0),
.R (1'b0),
.S (1'b0)
);
localparam S_IDLE = 0, // idle
S_LOAD = 1, // load data, prepare for sending
S_TRANS = 2, // send and receive data simultaneously
S_ACK = 3; // acknowledge
reg [1:0] state = 0;
reg [1:0] next_state;
reg [DATA_BITS_WIDTH-1:0] count = 0;
reg [DATA_BITS_WIDTH-1:0] next_count;
always @(*) begin
next_state = 0;
next_count = 0;
case (state)
S_IDLE: begin
if (en) next_state = S_LOAD;
else next_state = S_IDLE;
end
S_LOAD: begin
next_state = S_TRANS;
end
S_TRANS: begin
next_count = count + 1'h1;
if (count == DATA_BITS - 1) next_state = S_ACK;
else next_state = S_TRANS;
end
S_ACK: begin
next_state = S_IDLE;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state <= 0;
count <= 0;
end else begin
state <= next_state;
count <= next_count;
end
end
generate
begin : SPI_GEN
if (SPI_CPHA ^ SPI_CPOL) begin
always @(negedge clk) begin
dout <= 0;
ack <= 0;
if (~rst)
case (next_state)
S_TRANS: begin
dout <= SPI_LSBFE ? {miso, dout[DATA_BITS-1:1]} : {dout[DATA_BITS-2:0], miso};
end
S_ACK: begin
dout <= dout;
ack <= 1;
end
endcase
end
always @(posedge clk) begin
data_buf <= 0;
mosi <= 1;
if (~rst)
case (next_state)
S_LOAD: begin
data_buf <= din;
end
S_TRANS: begin
mosi <= SPI_LSBFE ? data_buf[0] : data_buf[DATA_BITS-1];
data_buf <= SPI_LSBFE ? {1'b0, data_buf[DATA_BITS-1:1]} : {data_buf[DATA_BITS-2:0], 1'b0};
end
endcase
end
end else begin
always @(posedge clk) begin
dout <= 0;
ack <= 0;
if (~rst)
case (next_state)
S_TRANS: begin
dout <= SPI_LSBFE ? {miso, dout[DATA_BITS-1:1]} : {dout[DATA_BITS-2:0], miso};
end
S_ACK: begin
dout <= dout;
ack <= 1;
end
endcase
end
always @(negedge clk) begin
data_buf <= 0;
mosi <= 1;
if (~rst)
case (next_state)
S_LOAD: begin
data_buf <= din;
end
S_TRANS: begin
mosi <= SPI_LSBFE ? data_buf[0] : data_buf[DATA_BITS-1];
data_buf <= SPI_LSBFE ? {1'b0, data_buf[DATA_BITS-1:1]} : {data_buf[DATA_BITS-2:0], 1'b0};
end
endcase
end
end
if (SPI_CPOL) begin
always @(posedge clk) begin
busy <= 0;
if (~rst)
case (next_state)
S_TRANS: busy <= 1;
endcase
end
end else begin
always @(negedge clk) begin
busy <= 0;
if (~rst)
case (next_state)
S_TRANS: busy <= 1;
endcase
end
end
end
endgenerate
endmodule
| 7.879942 |
module spi_crc16 (
rst,
clk,
gen_en,
out_en,
din,
dout,
load_start_tkn,
load_multi_blk_wr_tkn,
crc_reg
);
input rst;
input clk;
input gen_en;
input out_en;
input din;
output dout;
input load_start_tkn;
input load_multi_blk_wr_tkn;
output [15:0] crc_reg;
wire rst;
wire clk;
wire gen_en;
wire out_en;
wire din;
wire dout;
reg [15:0] crc_reg;
assign dout = crc_reg[15];
always @(posedge rst or posedge clk) begin
if (rst) begin
crc_reg <= 16'h0;
end else begin
if (load_start_tkn) crc_reg <= 16'h0ED1;
else if (load_multi_blk_wr_tkn) crc_reg <= 16'h2E93;
else if (gen_en) begin
crc_reg[15:13] <= crc_reg[14:12];
crc_reg[12] <= din ^ crc_reg[15] ^ crc_reg[11];
crc_reg[11:6] <= crc_reg[10:5];
crc_reg[5] <= din ^ crc_reg[15] ^ crc_reg[4];
crc_reg[4:1] <= crc_reg[3:0];
crc_reg[0] <= din ^ crc_reg[15];
end else if (out_en) begin
crc_reg[15:1] <= crc_reg[14:0];
crc_reg[0] <= 1'b0;
end
end
end
endmodule
| 7.633748 |
module takes the first two spi transfers
// and uses the values taken from them to simulate
// a chip select and select a pin to use for slave out.
//
// After the start condition is pulsed the following values are decoded:
// first 8 bits = Pin to use for chip select or 0xFF for invalid
// second 8 bits = Byte cycles to assert chip select for
//
// This is intended for use with the spi_sequence_detector which
// detects the start of a session.
//
// Note - this is expecting SPI phase and polarity to be 0
//
// Requirements
// -The "start" parameter must be asserted when sclk is low
//
// Guarantees
// -Chip select asserted on same cycle as the falling edge of the
// slave clock after select and cycles have been read
// -Chip select deasserted on falling edge of the slave clock
// after the requested number of cycles have passed
module spi_cs_decoder #(
parameter SELECT_SIZE = 8,
parameter CYCLES_SIZE = 8
)
(
input wire clk,
input wire rst,
input wire start,
input wire sin,
input wire sclk,
output wire scs,
output reg [SELECT_SIZE - 1:0] sindex
);
reg [CYCLES_SIZE + 3 - 1:0] scycles;
reg [SELECT_SIZE + CYCLES_SIZE - 1 - 1:0] bitstream;
reg sclk_prev;
reg started;
reg [7:0] cycles_until_start;
reg scs_start_on_falling, scs_stop_on_falling;
wire running;
wire [SELECT_SIZE - 1:0] index;
wire [CYCLES_SIZE - 1:0] cycles;
wire posedge_sclk, negedge_sclk;
assign index = bitstream[CYCLES_SIZE - 1 +:SELECT_SIZE];
assign cycles = {bitstream[0 +:CYCLES_SIZE - 1], sin}; // Lookahead
assign scs = (started && (!scs_start_on_falling || !sclk)) || (scs_stop_on_falling && sclk);
assign posedge_sclk = (sclk == 1) && (sclk_prev == 0);
assign negedge_sclk = (sclk == 0) && (sclk_prev == 1);
assign running = start || started;
always @(posedge clk) begin
if (rst || start) begin
sindex <= ~0;
scycles <= 0;
bitstream <= 0;
sclk_prev <= 0;
started <= 0;
cycles_until_start <= rst ? 0 : SELECT_SIZE + CYCLES_SIZE;
scs_start_on_falling <= 0;
scs_stop_on_falling <= 0;
end else begin
sclk_prev <= sclk;
if (posedge_sclk) begin
bitstream <= (bitstream << 1) | sin;
if (cycles_until_start > 0) begin
cycles_until_start <= cycles_until_start - 1;
end
if (cycles_until_start == 1) begin
sindex <= index;
scycles <= cycles << 3;
scs_start_on_falling <= 1;
started <= 1;
end
if (started) begin
scycles <= scycles - 1;
if (scycles == 1) begin
scs_stop_on_falling <= 1;
started <= 0;
end
end
end
if (negedge_sclk) begin
scs_start_on_falling <= 0;
scs_stop_on_falling <= 0;
end
end
end
endmodule
| 8.342096 |
module spi_ctrl (
fpga_0_RS232_RX_pin,
fpga_0_RS232_TX_pin,
fpga_0_clk_1_sys_clk_pin,
fpga_0_rst_1_sys_rst_pin,
Generic_SPI_MISO_I_pin,
Generic_SPI_MOSI_O_pin,
Generic_SPI_SCK_O_pin,
Generic_SPI_SS_O_pin,
Generic_GPIO_GPIO_IO_O_pin
);
input fpga_0_RS232_RX_pin;
output fpga_0_RS232_TX_pin;
input fpga_0_clk_1_sys_clk_pin;
input fpga_0_rst_1_sys_rst_pin;
input Generic_SPI_MISO_I_pin;
output Generic_SPI_MOSI_O_pin;
output Generic_SPI_SCK_O_pin;
output Generic_SPI_SS_O_pin;
output [0:1] Generic_GPIO_GPIO_IO_O_pin;
endmodule
| 6.929849 |
module spi_ctrl_reduced (
clk,
rst_n,
sck,
mosi,
miso,
cs_n,
spi_tx_en,
spi_rx_en,
mode_select,
receive_status
);
parameter DATA_LENGTH = 64;
input clk, rst_n, miso;
input mode_select;
output sck, mosi, cs_n;
output receive_status;
input spi_tx_en;
input spi_rx_en;
wire spi_over;
wire receive_status;
reg spi_clk;
reg [7:0] clk_count;
reg [7:0] rst_count;
reg rst_flag;
assign cs_n = 1'b0;
/*
spi baud rate is calculated by clk / 100 / 3
as we count 3 sck change to be a full period
*/
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
clk_count <= 8'h0;
spi_clk <= 1'b0;
end else begin
if (clk_count < 8'd100) clk_count <= clk_count + 1'b1;
else begin
clk_count <= 8'h0;
spi_clk <= ~spi_clk;
end
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
rst_flag <= 1'b0;
rst_count <= 'h0;
end else begin
if (rst_count < 8'd20) rst_count <= rst_count + 1'b1;
else rst_flag <= 1'b1;
end
end
spi_master_reduced #(
.DATA_LENGTH(DATA_LENGTH)
) spi_master_reduced_instance (
.clk(spi_clk),
.rst_n(rst_flag),
.spi_miso(miso),
.spi_mosi(mosi),
.spi_clk(sck),
.spi_tx_en(spi_tx_en),
.spi_rx_en(spi_rx_en),
.mode_select(mode_select),
.receive_status(receive_status)
);
endmodule
| 8.088552 |
module spi_ctrl_stub (
fpga_0_RS232_RX_pin,
fpga_0_RS232_TX_pin,
fpga_0_clk_1_sys_clk_pin,
fpga_0_rst_1_sys_rst_pin,
Generic_SPI_MISO_I_pin,
Generic_SPI_MOSI_O_pin,
Generic_SPI_SCK_O_pin,
Generic_SPI_SS_O_pin,
Generic_GPIO_GPIO_IO_O_pin
);
input fpga_0_RS232_RX_pin;
output fpga_0_RS232_TX_pin;
input fpga_0_clk_1_sys_clk_pin;
input fpga_0_rst_1_sys_rst_pin;
input Generic_SPI_MISO_I_pin;
output Generic_SPI_MOSI_O_pin;
output Generic_SPI_SCK_O_pin;
output Generic_SPI_SS_O_pin;
output [0:1] Generic_GPIO_GPIO_IO_O_pin;
(* BOX_TYPE = "user_black_box" *)
spi_ctrl spi_ctrl_i (
.fpga_0_RS232_RX_pin(fpga_0_RS232_RX_pin),
.fpga_0_RS232_TX_pin(fpga_0_RS232_TX_pin),
.fpga_0_clk_1_sys_clk_pin(fpga_0_clk_1_sys_clk_pin),
.fpga_0_rst_1_sys_rst_pin(fpga_0_rst_1_sys_rst_pin),
.Generic_SPI_MISO_I_pin(Generic_SPI_MISO_I_pin),
.Generic_SPI_MOSI_O_pin(Generic_SPI_MOSI_O_pin),
.Generic_SPI_SCK_O_pin(Generic_SPI_SCK_O_pin),
.Generic_SPI_SS_O_pin(Generic_SPI_SS_O_pin),
.Generic_GPIO_GPIO_IO_O_pin(Generic_GPIO_GPIO_IO_O_pin)
);
endmodule
| 7.114411 |
module spi_ctrl (
fpga_0_RS232_RX_pin,
fpga_0_RS232_TX_pin,
fpga_0_clk_1_sys_clk_pin,
fpga_0_rst_1_sys_rst_pin,
Generic_SPI_MISO_I_pin,
Generic_SPI_MOSI_O_pin,
Generic_SPI_SCK_O_pin,
Generic_SPI_SS_O_pin,
Generic_GPIO_GPIO_IO_O_pin
);
input fpga_0_RS232_RX_pin;
output fpga_0_RS232_TX_pin;
input fpga_0_clk_1_sys_clk_pin;
input fpga_0_rst_1_sys_rst_pin;
input Generic_SPI_MISO_I_pin;
output Generic_SPI_MOSI_O_pin;
output Generic_SPI_SCK_O_pin;
output Generic_SPI_SS_O_pin;
output [0:1] Generic_GPIO_GPIO_IO_O_pin;
endmodule
| 6.929849 |
module SPI_DAC8512 (
output wire SDAT, // .
input st,
output wire SCLK, // .
input clk,
output reg NCS = 1, // .
input [11:0] DI,
output reg NLD = 1, // .
output wire ce, //
output reg [3:0] cb_bit = 0
); // .
parameter Tsclk = 80; //Tsclk=Tcl+Tch=40+40 ns
reg [11:0] sr_dat = 0; //
reg [ 1:0] cb_ce = 0; //
assign ce = (cb_ce == (Tsclk / `Tclk) - 1); // (cb_ce==80/20-1=3)
assign SCLK = cb_ce[1] | NCS; // . 40ns
assign SDAT = sr_dat[11]; //
always @(posedge clk) begin
cb_ce <= (st | ce) ? 0 : cb_ce + 1;
NCS <= st ? 0 : ((cb_bit == 11) & ce) ? 1 : NCS; // Chip Select 1
cb_bit <= st ? 0 : (!NCS & ce) ? cb_bit + 1 : cb_bit;
sr_dat <= st ? DI : (ce & !NCS) ? sr_dat << 1 : sr_dat; //
NLD <= st ? 1 : ce ? !(cb_bit == 11) : NLD; // LD 0
end
endmodule
| 6.577009 |
module spi_dac_out (
clk,
reset,
spi_sck,
spi_sdo,
spi_dac_cs,
ena_out,
deltaS_out,
data_in,
cycles
);
input clk;
input reset;
output spi_sck;
output spi_sdo;
output spi_dac_cs;
output ena_out;
output deltaS_out;
input [11:0] data_in;
input [11:0] cycles; // total number of clocks between each DAC ena
wire [ 3:0] cmd = 4'b0011; // write & update
wire [ 3:0] add = 4'b0000; // DAC A
wire [11:0] cycles;
// SPI_sck = 0 Clock is Low (required)
// SPI_dac_cs = 1 Deselect D/A
dac delta_sigma (
.DACout(deltaS_out),
.DACin(data_in),
.Clk(clk),
.Reset(reset)
);
// SPI clock is system clock/2
reg half_clk;
always @(posedge clk)
if (reset) half_clk <= 1'b0;
else half_clk <= ~half_clk;
// synchronous counter sequences the spi bits
reg [11:0] state, next_state; // extended to allow longer delay
always @(posedge clk)
if (reset) state <= 12'd0;
else if (half_clk) state <= next_state;
reg ck_ena = 1'b1;
reg sdo;
reg dac_cs = 1'b0;
// compute next state and spi outputs
always @ ( state or cycles ) // 'or cycles' added by SRG. Eliminates an XST warning and does not change the functionality
begin
next_state <= state + 1;
case (state)
12'd0: // 1st cycle: CS high
begin
ck_ena <= 1'b0;
dac_cs <= 1'b1;
end
12'd1: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd2: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd3: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd4: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd5: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd6: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd7: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd8: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd9: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd10: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd11: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd12: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd13: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd14: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd15: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd16: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd17: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd18: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd19: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd20: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd21: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd22: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd23: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd24: begin
ck_ena <= 1'b1;
dac_cs <= 1'b0;
end
12'd25: begin
ck_ena <= 1'b0;
dac_cs <= 1'b1;
end
default: begin
if (state == cycles) next_state <= 12'd0;
end
endcase
end
// Data register
reg [23:0] ser_reg;
always @(posedge clk)
if (ck_ena) begin
if (half_clk == 1'b1) ser_reg <= {ser_reg[22:0], 1'b0};
end else begin
ser_reg <= {cmd, add, data_in, 4'h0};
end
// Output registers
reg spi_sck, spi_sdo, spi_dac_cs, ena_out;
always @(posedge clk) begin
spi_sck <= half_clk & ck_ena;
spi_sdo <= ser_reg[23];
spi_dac_cs <= dac_cs;
end
reg ck_ena_old = 1'b0;
always @(posedge clk) begin
ck_ena_old <= ck_ena;
if ((ck_ena_old ^ ck_ena) == 1'b1 && ck_ena == 1'b0) ena_out <= 1'b1;
else ena_out <= 1'b0;
end
endmodule
| 7.524932 |
module spi_datapath_master #(
parameter SPI_MAX_WIDTH_LOG = 4
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
//config
input cpha,
//control flow
input sck_first_edge,
sck_second_edge,
input spi_start,
//spi
input miso,
output mosi,
//data
input [2 ** SPI_MAX_WIDTH_LOG - 1:0] din,
output reg [2 ** SPI_MAX_WIDTH_LOG - 1:0] dout
);
reg spi_read, spi_write;
always @(*) begin
if (cpha) begin
spi_read = sck_second_edge;
spi_write = sck_first_edge;
end else begin
spi_read = sck_first_edge;
spi_write = sck_second_edge;
end
end
reg [2 ** SPI_MAX_WIDTH_LOG - 1:0] din_lock;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
{din_lock, dout} <= 'b0;
end else if (spi_start) begin
din_lock <= din;
dout <= 'b0;
end else if (spi_read) begin
dout <= {miso, dout[2**SPI_MAX_WIDTH_LOG-1:1]};
end else if (spi_write) begin
din_lock <= din_lock >> 1;
end
end
assign mosi = din_lock[0];
endmodule
| 7.269792 |
module spi_datapath_slave #(
parameter SPI_MAX_WIDTH_LOG = 4
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
//config
input cpha,
//control flow
input sck_first_edge,
sck_second_edge,
input spi_start,
//spi
output miso,
input mosi,
//data
input [2 ** SPI_MAX_WIDTH_LOG - 1:0] din,
output reg [2 ** SPI_MAX_WIDTH_LOG - 1:0] dout
);
reg spi_read, spi_write;
always @(*) begin
if (cpha) begin
spi_read = sck_second_edge;
spi_write = sck_first_edge;
end else begin
spi_read = sck_first_edge;
spi_write = sck_second_edge;
end
end
reg [2 ** SPI_MAX_WIDTH_LOG - 1:0] din_lock;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
{din_lock, dout} <= 'b0;
end else if (spi_start) begin
din_lock <= din;
dout <= 'b0;
end else if (spi_read) begin
dout <= {mosi, dout[2**SPI_MAX_WIDTH_LOG-1:1]};
end else if (spi_write) begin
din_lock <= din_lock >> 1;
end
end
assign miso = din_lock[0];
endmodule
| 7.269792 |
module SPI_DCS_if #(
parameter width_addr = 8,
parameter width_data = 16
) (
input wire clk,
input wire rst_n,
input wire spi_scl,
input wire spi_sdi,
output reg spi_sdo,
input wire spi_cs_addr,
input wire spi_cs_data,
input wire [width_data-1:0] Din,
output reg [width_addr-1:0] Addr,
output reg [width_data-1:0] Dout,
output reg Data_begin,
output reg Data_end
);
reg [width_data-1:0] r_Din;
reg [ 1:0] r_spi_scl;
wire pos_spi_scl;
wire neg_spi_scl;
reg [ 1:0] r_spi_cs_addr;
wire pos_spi_cs_addr;
wire neg_spi_cs_addr;
wire en_spi_cs_addr;
reg [ 1:0] r_spi_cs_data;
wire pos_spi_cs_data;
wire neg_spi_cs_data;
wire en_spi_cs_data;
// edge detect
always @(posedge clk, negedge rst_n) begin
if (!rst_n) r_spi_scl <= 2'b00;
else r_spi_scl <= {r_spi_scl[0], spi_scl};
end
assign pos_spi_scl = (!r_spi_scl[1]) & (r_spi_scl[0]);
assign neg_spi_scl = (r_spi_scl[1]) & (!r_spi_scl[0]);
always @(posedge clk, negedge rst_n) begin
if (!rst_n) r_spi_cs_addr <= 2'b11;
else r_spi_cs_addr <= {r_spi_cs_addr[0], spi_cs_addr};
end
assign pos_spi_cs_addr = (!r_spi_cs_addr[1]) & (r_spi_cs_addr[0]);
assign neg_spi_cs_addr = (r_spi_cs_addr[1]) & (!r_spi_cs_addr[0]);
assign en_spi_cs_addr = (!r_spi_cs_addr[1]) & (!r_spi_cs_addr[0]);
always @(posedge clk, negedge rst_n) begin
if (!rst_n) r_spi_cs_data <= 2'b11;
else r_spi_cs_data <= {r_spi_cs_data[0], spi_cs_data};
end
assign pos_spi_cs_data = (!r_spi_cs_data[1]) & (r_spi_cs_data[0]);
assign neg_spi_cs_data = (r_spi_cs_data[1]) & (!r_spi_cs_data[0]);
assign en_spi_cs_data = (!r_spi_cs_data[1]) & (!r_spi_cs_data[0]);
always @(*) begin
Data_begin = neg_spi_cs_data;
Data_end = pos_spi_cs_data;
end
// receive part
always @(posedge clk, negedge rst_n) begin
if (!rst_n) Addr <= {width_addr{1'b0}};
else if (neg_spi_cs_addr) Addr <= {width_addr{1'b0}};
else if (en_spi_cs_addr)
if (pos_spi_scl) Addr[width_addr-1:0] <= {Addr[width_addr-2:0], spi_sdi};
else Addr <= Addr;
else Addr <= Addr;
end
always @(posedge clk, negedge rst_n) begin
if (!rst_n) Dout <= {width_data{1'b0}};
else if (neg_spi_cs_data) Dout <= {width_data{1'b0}};
else if (en_spi_cs_data)
if (pos_spi_scl) Dout[width_data-1:0] <= {Dout[width_data-2:0], spi_sdi};
else Dout <= Dout;
else Dout <= Dout;
end
// transmit part
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
spi_sdo <= 1'b0;
r_Din <= {width_data{1'b0}};
end else if (neg_spi_cs_data) begin
spi_sdo <= Din[width_data-1];
r_Din[width_data-1:0] <= {Din[width_data-2:0], 1'b0};
end else if (en_spi_cs_data)
if (neg_spi_scl) begin
spi_sdo <= r_Din[width_data-1];
r_Din[width_data-1:0] <= {r_Din[width_data-2:0], 1'b0};
end else begin
spi_sdo <= spi_sdo;
r_Din <= r_Din;
end
else begin
spi_sdo <= 1'b0;
r_Din <= {width_data{1'b0}};
end
end
// make verilator happy
wire unused;
assign unused = pos_spi_cs_addr;
endmodule
| 8.562424 |
module spi_debug_ifc (
input spi_clk,
input spi_cs_i,
input spi_data_i,
output spi_data_o,
input sys_clk,
output sys_wr_o,
output [15:0] sys_waddr_o,
output [15:0] sys_wdata_o
);
reg [15:0] spi_shift = 16'd0;
reg [16:0] spi_data = 17'd0;
reg [3:0] spi_count = 4'd0;
reg spi_signal = 1'd0;
reg spi_flag = 1'd0;
assign spi_data_o = 1'b0;
wire [15:0] spi_next = {spi_data_i, spi_shift[15:1]};
reg [15:0] spi_shift_next;
reg [16:0] spi_data_next;
reg [3:0] spi_count_next;
reg spi_signal_next;
reg spi_flag_next;
always @(*) begin
spi_shift_next = spi_shift;
spi_data_next = spi_data;
spi_count_next = spi_count;
spi_signal_next = spi_signal;
spi_flag_next = spi_flag;
if (spi_cs_i) begin
spi_count_next = 4'd0;
spi_flag_next = 1'b1;
end else begin
spi_shift_next = spi_next;
spi_count_next = spi_count + 4'd1;
if (spi_count == 4'd15) begin
spi_data_next = {spi_flag, spi_next};
spi_signal_next = ~spi_signal;
spi_flag_next = 1'b0;
end
end
end
always @(posedge spi_clk) begin
spi_shift <= spi_shift_next;
spi_data <= spi_data_next;
spi_count <= spi_count_next;
spi_signal <= spi_signal_next;
spi_flag <= spi_flag_next;
end
wire sys_signal;
sync_oneway sync_spi_sys (
.txclk(spi_clk),
.txdat(spi_signal),
.rxclk(sys_clk),
.rxdat(sys_signal)
);
reg sys_signal_ack = 1'b0;
reg enabled = 1'b0;
reg [15:0] addr;
reg [15:0] data;
reg wr = 1'b0;
reg [15:0] addr_next;
reg [15:0] data_next;
reg enabled_next;
reg sys_signal_ack_next;
reg wr_next;
reg [15:0] delay = 16'd0;
reg [15:0] delay_next;
always @(*) begin
delay_next = delay;
addr_next = addr;
data_next = data;
sys_signal_ack_next = sys_signal_ack;
wr_next = wr;
// ensure we're up and running before accepting writes
// there's got to be a nicer way to do this
if (delay != 16'hFFFF) begin
delay_next = delay + 1'd1;
enabled_next = 1'b0;
end else begin
enabled_next = 1'b1;
end
if (sys_signal ^ sys_signal_ack) begin
sys_signal_ack_next = ~sys_signal_ack;
if (spi_data[16]) begin
addr_next = spi_data[15:0];
end else begin
data_next = spi_data[15:0];
wr_next = 1'b1;
end
end else begin
if (wr) begin
wr_next = 1'b0;
addr_next = addr + 16'd1;
end
end
end
always @(posedge sys_clk) begin
delay <= delay_next;
addr <= addr_next;
data <= data_next;
enabled <= enabled_next;
sys_signal_ack <= sys_signal_ack_next;
wr <= wr_next;
end
assign sys_wr_o = wr & enabled;
assign sys_waddr_o = addr;
assign sys_wdata_o = data;
endmodule
| 7.025411 |
module spi_decoder #(
parameter DATA_SIZE = 8 // The size of the parallel output data.
) (
//
// ------- Inputs -------
//
input I_sclk, // Serial data clock
input I_enable, // Enable for the decoder
input I_sdi, // Serial data input
//
// ------- Outputs -------
//
output reg [DATA_SIZE - 1:0] O_data // Parallel output data
);
// Shift up data and insert SDI on rising clock edge.
always @(posedge I_sclk) if (I_enable) O_data <= {O_data[DATA_SIZE-2:0], I_sdi};
endmodule
| 7.538646 |
module SPI_Demo_tb;
reg Clock;
reg Reset;
wire ready;
reg send;
wire arrived;
reg [7:0] data;
wire [7:0] dataO;
wire arrivedS;
reg [7:0] dataS;
wire [7:0] dataSO;
wire SCLK;
wire MISO;
wire MOSI;
wire CS;
SPI_Demo mdl (
Clock,
Reset,
ready,
send,
arrived,
data,
dataO,
arrivedS,
dataS,
dataSO,
SCLK,
MISO,
MOSI,
CS
);
initial begin
Reset = 1'b0;
#2 Reset = 1'b1;
end
initial begin
Clock = 1'b1;
forever #2 Clock = ~Clock;
end
initial begin
send = 1'b0;
data = 8'bx;
dataS = 8'bx;
end
task automatic exchangeData(input [7:0] d, input [7:0] q);
begin
@(posedge Clock) while (~ready) @(posedge Clock);
send = 1'b1;
data = d;
dataS = q;
@(posedge Clock) send = 1'b0;
fork
begin
@(posedge Clock) while (~arrived) @(posedge Clock);
$display("MISO: %b -> %b (%b)", q, dataO, q == dataO);
end
begin
@(posedge Clock) while (~arrivedS) @(posedge Clock);
$display("MOSI: %b -> %b (%b)", d, dataSO, d == dataSO);
end
join
end
endtask
initial begin
exchangeData(8'b01000010, 8'b00101011);
exchangeData(8'b10101010, 8'b01010110);
exchangeData(8'b01000101, 8'b11100011);
exchangeData(8'b01110010, 8'b10001111);
exchangeData(8'b11110011, 8'b11001101);
exchangeData(8'b01010010, 8'b00101001);
exchangeData(8'b11001110, 8'b10001110);
exchangeData(8'b01110111, 8'b10111001);
exchangeData(8'b00001010, 8'b01101001);
exchangeData(8'b10010010, 8'b01101101);
exchangeData(8'b01101011, 8'b00101011);
$finish;
end
endmodule
| 6.945999 |
module spi_detector #(
parameter FREQ = 12'hfff
) (
input wire CLK,
input wire RST,
input wire SCLK,
output wire DETECT
);
reg [11:0] r_timer;
reg [ 7:0] r_counter;
reg [ 7:0] r_capture0;
reg [ 7:0] r_capture1;
//============================================================
// spi clock freerun counter
//============================================================
always @(posedge SCLK or posedge RST) begin
if (RST) r_counter <= 8'b0;
else r_counter <= r_counter + 8'b1;
end
//============================================================
//
//============================================================
always @(posedge CLK or posedge RST) begin
if (RST) r_timer <= 12'b0;
else if (r_timer == FREQ) r_timer <= 12'b0;
else r_timer <= r_timer + 12'b1;
end
//============================================================
//
//============================================================
always @(posedge CLK or posedge RST) begin
if (RST) begin
r_capture0 <= 8'b0;
r_capture1 <= 8'b0;
end else if (r_timer == FREQ) begin
r_capture0 <= r_counter; // TODO : this bus signal must be synchronized by CLK !!!
r_capture1 <= r_capture0;
end
end
assign DETECT = (r_capture0 != r_capture1);
endmodule
| 7.385287 |
module spi_dev_arb #(
parameter integer N = 1,
// auto
parameter integer NL = N - 1,
parameter integer DL = (8 * N) - 1
) (
// Upstream
output wire us_req,
input wire us_gnt,
output reg [7:0] us_rdata,
output reg us_rstb,
// Downstream
input wire [NL:0] ds_req,
output wire [NL:0] ds_gnt,
input wire [DL:0] ds_rdata,
input wire [NL:0] ds_rstb,
// Clock / Reset
input wire clk,
input wire rst
);
// Signals
// -------
localparam WL = $clog2(N) - 1;
reg [WL:0] sel_nxt;
reg [WL:0] sel;
reg [NL:0] sel_mask_nxt;
reg [NL:0] sel_mask;
reg sel_valid;
wire sel_done;
reg sel_inhibit;
// Control
// -------
// Continuous selection of potential next
always @(*) begin : sel_loop
integer i;
sel_nxt = 0;
sel_mask_nxt = 0;
for (i = N - 1; i >= 0; i = i - 1)
if (ds_req[i]) begin
sel_nxt = i;
sel_mask_nxt = 0;
sel_mask_nxt[i] = 1'b1;
end
end
// Latch selection
always @(posedge clk or posedge rst)
if (rst) begin
sel_valid <= 1'b0;
sel_mask <= 0;
sel <= 0;
end else begin
if (sel_valid) begin
// Just track we're still active
if (sel_done) begin
sel_valid <= 1'b0;
sel_mask <= 0;
sel <= 0;
end
end else begin
sel_valid <= |ds_req;
sel_mask <= sel_mask_nxt;
sel <= sel_nxt;
end
end
// Detect end
assign sel_done = sel_valid & ~ds_req[sel];
always @(posedge clk) sel_inhibit <= sel_done;
// Pass on request DS -> US
assign us_req = sel_valid | (|ds_req & ~sel_inhibit);
// Pass on grants US -> DS
assign ds_gnt = (us_gnt & sel_valid) ? sel_mask : 0;
// Data mux
always @(posedge clk) begin
us_rdata <= ds_rdata[8*sel+:8];
us_rstb <= ds_rstb[sel];
end
endmodule
| 6.943197 |
module spi_dev_core_tb;
// Signals
reg rst = 1'b1;
reg clk_slow = 1'b0;
reg clk_fast = 1'b0;
wire spi_mosi;
wire spi_miso;
wire spi_cs_n;
wire spi_clk;
wire [7:0] usr_mosi_data;
wire usr_mosi_stb;
reg [7:0] usr_miso_data;
wire usr_miso_ack;
wire csn_state;
wire csn_rise;
wire csn_fall;
// Setup recording
initial begin
$dumpfile("spi_dev_core_tb.vcd");
$dumpvars(0, spi_dev_core_tb);
end
// Reset pulse
initial begin
#200 rst = 0;
#1000000 $finish;
end
// Clocks
always #16.66 clk_slow = !clk_slow; // ~ 30 MHz (sys_clk)
always #3.125 clk_fast = !clk_fast; // ~ 160 MHz (2*spi_clk)
// DUT
spi_dev_core spi_I (
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
.spi_cs_n (spi_cs_n),
.spi_clk (spi_clk),
.usr_mosi_data(usr_mosi_data),
.usr_mosi_stb (usr_mosi_stb),
.usr_miso_data(usr_miso_data),
.usr_miso_ack (usr_miso_ack),
.csn_state (csn_state),
.csn_rise (csn_rise),
.csn_fall (csn_fall),
.clk (clk_slow),
.rst (rst)
);
// Dummy TX
always @(posedge clk_slow)
if (csn_state) usr_miso_data <= 8'hA5;
else if (usr_miso_ack) usr_miso_data <= usr_miso_data + 1;
// SPI data generation
reg [71:0] spi_csn_data = 72'b111100000000000000000000000000000000000000000000000000000001111111111111;
reg [71:0] spi_clk_data = 72'b000000101010101010101010101010101010101010101010101010000000000000000000;
reg [71:0] spi_dat_data = 72'b000001100110000110011111100000000001111110000000011000000000000000000000;
always @(posedge clk_fast) begin
if (~rst) begin
spi_csn_data <= {spi_csn_data[70:0], spi_csn_data[71]};
spi_clk_data <= {spi_clk_data[70:0], spi_clk_data[71]};
spi_dat_data <= {spi_dat_data[70:0], spi_dat_data[71]};
end
end
assign spi_mosi = spi_dat_data[70];
assign spi_cs_n = spi_csn_data[70];
assign spi_clk = spi_clk_data[70];
// Print and validate output
reg [ 1:0] out_cnt;
reg [23:0] out_val = 24'hc2c1a5;
always @(posedge clk_slow) begin
if (csn_fall) begin
$write("\nRX:");
out_cnt = 0;
end
if (usr_mosi_stb) begin
$write(" %02x", usr_mosi_data);
if (usr_mosi_data != out_val[out_cnt*8+:8]) $error("\nInvalid data\n");
out_cnt = out_cnt + 1;
end
if (out_cnt == 4) $error("\nToo many data\n");
end
endmodule
| 7.107739 |
module spi_dev_ezwb #(
parameter integer WB_N = 3,
// auto
parameter integer DL = (32 * WB_N) - 1,
parameter integer CL = WB_N - 1
) (
// SPI interface
output wire spi_miso,
input wire spi_mosi,
input wire spi_clk,
input wire spi_cs_n,
// Wishbone
output reg [31:0] wb_wdata,
input wire [DL:0] wb_rdata,
output reg [23:0] wb_addr,
output wire wb_we,
output reg [CL:0] wb_cyc,
input wire [CL:0] wb_ack,
// Clock / Reset
input wire clk,
input wire rst
);
// Signals
// -------
// Raw core IF
wire [7:0] usr_mosi_data;
wire usr_mosi_stb;
wire [7:0] usr_miso_data;
wire usr_miso_ack;
wire csn_state;
wire csn_rise;
wire csn_fall;
// Protocol IF
wire [7:0] pw_wdata;
wire pw_wcmd;
wire pw_wstb;
wire pw_end;
wire pw_req;
wire pw_gnt;
wire [7:0] pw_rdata;
wire pw_rstb;
// Cores
// -----
// Device Core
spi_dev_core core_I (
.spi_miso (spi_miso),
.spi_mosi (spi_mosi),
.spi_clk (spi_clk),
.spi_cs_n (spi_cs_n),
.usr_mosi_data(usr_mosi_data),
.usr_mosi_stb (usr_mosi_stb),
.usr_miso_data(usr_miso_data),
.usr_miso_ack (usr_miso_ack),
.csn_state (csn_state),
.csn_rise (csn_rise),
.csn_fall (csn_fall),
.clk (clk),
.rst (rst)
);
// Protocol wrapper
spi_dev_proto proto_I (
.usr_mosi_data(usr_mosi_data),
.usr_mosi_stb (usr_mosi_stb),
.usr_miso_data(usr_miso_data),
.usr_miso_ack (usr_miso_ack),
.csn_state (csn_state),
.csn_rise (csn_rise),
.csn_fall (csn_fall),
.pw_wdata (pw_wdata),
.pw_wcmd (pw_wcmd),
.pw_wstb (pw_wstb),
.pw_end (pw_end),
.pw_req (pw_req),
.pw_gnt (pw_gnt),
.pw_rdata (pw_rdata),
.pw_rstb (pw_rstb),
.pw_irq (4'h0),
.irq (),
.clk (clk),
.rst (rst)
);
// Wishbone bridge
spi_dev_to_wb #(
.WB_N(WB_N)
) wb_I (
.pw_wdata(pw_wdata),
.pw_wcmd (pw_wcmd),
.pw_wstb (pw_wstb),
.pw_end (pw_end),
.pw_req (pw_req),
.pw_gnt (pw_gnt),
.pw_rdata(pw_rdata),
.pw_rstb (pw_rstb),
.wb_wdata(wb_wdata),
.wb_rdata(wb_rdata),
.wb_addr (wb_addr),
.wb_we (wb_we),
.wb_cyc (wb_cyc),
.wb_ack (wb_ack),
.clk (clk),
.rst (rst)
);
endmodule
| 8.755922 |
module spi_dev_lcdpalwr #(
// LSB must be 0 and it uses
// CMD_BYTE and CMD_BYTE+1
parameter [7:0] CMD_BYTE = 8'he4
) (
// LCD PHY drive
output wire [7:0] phy_data,
output wire phy_rs,
output reg phy_valid,
input wire phy_ready,
// SPI protocol wrapper interface
input wire [7:0] pw_wdata,
input wire pw_wcmd,
input wire pw_wstb,
input wire pw_end,
// Clock /Reset
input wire clk,
input wire rst
);
// Signals
// -------
// SPI state
(* keep *)wire [ 1:0] match;
(* keep *)wire start;
reg active_wr;
reg active_pal;
// Palette RAM
reg [ 8:0] pal_waddr;
wire [ 7:0] pal_wdata;
wire pal_wen;
wire [ 7:0] pal_raddr;
wire [15:0] pal_rdata;
wire pal_ren;
// Read control
reg [ 1:0] rd_valid;
reg rd_bsel;
// SPI
// ---
// Matching
assign match[0] = (pw_wdata[7:4] == CMD_BYTE[7:4]);
assign match[1] = (pw_wdata[3:1] == CMD_BYTE[3:1]);
assign start = match[0] & match[1] & pw_wcmd & pw_wstb;
// SPI Command tracking
always @(posedge clk)
if (rst) begin
active_wr <= 1'b0;
active_pal <= 1'b0;
end else begin
active_wr <= (active_wr | (start & ~pw_wdata[0])) & ~pw_end;
active_pal <= (active_pal | (start & pw_wdata[0])) & ~pw_end;
end
// Palette RAM
// -----------
// Instance
ice40_ebr #(
.READ_MODE (0), // x16
.WRITE_MODE(1) // x8
) pal_ram_I (
.wr_addr(pal_waddr),
.wr_data(pal_wdata),
.wr_ena (pal_wen),
.wr_mask(8'h00),
.wr_clk (clk),
.rd_addr(pal_raddr),
.rd_data(pal_rdata),
.rd_ena (pal_ren),
.rd_clk (clk)
);
// Write from SPI
always @(posedge clk) if (pw_wstb) pal_waddr <= (pal_waddr + 1) & {9{~pw_wcmd}};
assign pal_wdata = pw_wdata;
assign pal_wen = pw_wstb & active_pal;
// Read from SPI to LCD
assign pal_raddr = pw_wdata;
assign pal_ren = pw_wstb;
always @(posedge clk) begin
if (pw_wstb) begin
rd_valid <= {2{active_wr}};
rd_bsel <= 1'b0;
end else begin
rd_valid <= phy_ready ? {1'b0, rd_valid[1]} : rd_valid;
rd_bsel <= rd_bsel ^ phy_ready;
end
end
assign phy_valid = rd_valid[0];
assign phy_data = rd_bsel ? pal_rdata[7:0] : pal_rdata[15:8];
assign phy_rs = 1'b1;
endmodule
| 7.652795 |
module spi_dev_lcdwr #(
// LSB must be 0 and it uses
// CMD_BYTE and CMD_BYTE+1
parameter [7:0] CMD_BYTE = 8'hf2
) (
// LCD PHY drive
output reg [7:0] phy_data,
output reg phy_rs,
output reg phy_valid,
input wire phy_ready,
// SPI protocol wrapper interface
input wire [7:0] pw_wdata,
input wire pw_wcmd,
input wire pw_wstb,
input wire pw_end,
// Clock /Reset
input wire clk,
input wire rst
);
// Signals
// -------
// FSM
localparam [1:0] ST_LEN = 2'b00, ST_CMD = 2'b10, ST_DATA = 2'b11;
wire [1:0] match;
wire start;
reg active;
reg [1:0] state;
reg [1:0] state_nxt;
// Data length tracker
reg [8:0] data_len;
reg data_inf;
wire data_last;
// FSM
// ---
// Matching
assign match[0] = (pw_wdata[7:4] == CMD_BYTE[7:4]);
assign match[1] = (pw_wdata[3:1] == CMD_BYTE[3:1]);
assign start = match[0] & match[1] & pw_wcmd & pw_wstb;
// SPI Command tracking
always @(posedge clk)
if (rst) active <= 1'b0;
else active <= (active | start) & ~pw_end;
// State tracking
always @(posedge clk or posedge rst)
if (rst) state <= ST_LEN;
else if (pw_wstb) state <= state_nxt;
always @(*) begin
// Default sequence
case (state)
ST_LEN: state_nxt = ST_CMD;
ST_CMD: state_nxt = data_last ? ST_LEN : ST_DATA;
ST_DATA: state_nxt = data_last ? ST_LEN : ST_DATA;
default: state_nxt = state;
endcase
// Reset
if (pw_wcmd)
// Only need to consider the LSB since if the rest doesn't match it
// doesn't matter what state we are since `active` will stay low
state_nxt = pw_wdata[0] ? ST_DATA : ST_LEN;
end
// Data length tracking
always @(posedge clk or posedge rst) begin
if (rst) begin
data_len <= 0;
data_inf <= 1'b0;
end else if (pw_wstb) begin
data_len <= ((state == ST_LEN) ? {1'b0, pw_wdata} : data_len) - 1;
data_inf <= ((state == ST_LEN) ? &pw_wdata : data_inf) | pw_wcmd;
end
end
assign data_last = data_len[8] & ~data_inf;
// Register data
always @(posedge clk)
if (pw_wstb) begin
phy_data <= pw_wdata;
phy_rs <= state == ST_DATA;
end
always @(posedge clk)
phy_valid <=
(phy_valid & ~phy_ready) |
(pw_wstb & active & (
(state == ST_CMD) |
(state == ST_DATA)
));
endmodule
| 9.783844 |
module spi_dev_memwr #(
parameter [7:0] CMD_BYTE = 8'he0,
parameter integer DATA_WIDTH = 16,
parameter integer ADDR_WIDTH = 23, // Word-address
parameter integer BURST_LEN = 64, // In words
// auto-set
parameter integer DL = DATA_WIDTH - 1,
parameter integer AL = ADDR_WIDTH - 1
) (
// Protocol wrapper interface
input wire [7:0] pw_wdata,
input wire pw_wcmd,
input wire pw_wstb,
input wire pw_end,
// Memory interface
output wire [AL:0] mi_addr,
output wire [ 6:0] mi_len,
output wire mi_rw,
output wire mi_valid,
input wire mi_ready,
output wire [DL:0] mi_wdata,
input wire mi_wack,
input wire mi_wlast,
input wire [DL:0] mi_rdata, // Not used
input wire mi_rstb, // Not used
input wire mi_rlast, // Not used
// Wishbone interface
input wire [31:0] wb_wdata,
output wire [31:0] wb_rdata,
input wire [ 1:0] wb_addr,
input wire wb_we,
input wire wb_cyc,
output reg wb_ack,
// Clock / Reset
input wire clk,
input wire rst
);
// Signals
// -------
// Bus
wire bus_clr;
reg bus_we_csr;
reg bus_we_base;
// FIFO
wire [DL:0] fw_data;
wire fw_ena;
wire fw_full;
wire [DL:0] fr_data;
wire fr_ena;
wire fr_empty;
(* keep *)
wire [ 8:0] fifo_level_inc;
reg [ 8:0] fifo_level;
// DMA
reg dma_run;
localparam [1:0] DS_IDLE = 2'b00, DS_CMD = 2'b01, DS_WAIT = 2'b10;
reg [ 1:0] dma_state;
reg [ 1:0] dma_state_nxt;
reg [AL:0] dma_addr;
// Wishbone interface
// ------------------
// Ack
always @(posedge clk) wb_ack <= wb_cyc & ~wb_ack;
// Clear
assign bus_clr = ~wb_cyc | wb_ack;
// Write strobes
always @(posedge clk)
if (bus_clr) begin
bus_we_csr <= 1'b0;
bus_we_base <= 1'b0;
end else begin
bus_we_csr <= wb_we & (wb_addr == 2'b00);
bus_we_base <= wb_we & (wb_addr == 2'b01);
end
// No read support
assign wb_rdata = 32'h00000000;
// SPI-to-FIFO
// -----------
// Command decode (with repeat)
spi_dev_scmd #(
.CMD_BYTE(CMD_BYTE),
.CMD_LEN(DATA_WIDTH / 8),
.CMD_REPEAT(1)
) cmd_I (
.pw_wdata(pw_wdata),
.pw_wcmd (pw_wcmd),
.pw_wstb (pw_wstb),
.pw_end (pw_end),
.cmd_data(fw_data),
.cmd_stb (fw_ena),
.clk (clk),
.rst (rst)
);
// FIFO instance
fifo_sync_ram #(
.DEPTH(256),
.WIDTH(DATA_WIDTH)
) fifo_I (
.wr_data (fw_data),
.wr_ena (fw_ena & ~fw_full),
.wr_full (fw_full),
.rd_data (fr_data),
.rd_ena (fr_ena & ~fr_empty),
.rd_empty(fr_empty),
.clk (clk),
.rst (rst)
);
// Fill level counter
assign fifo_level_inc[8:2] = {7{fifo_level_inc[1]}};
assign fifo_level_inc[1] = fr_ena & ~fw_ena;
assign fifo_level_inc[0] = fr_ena ^ fw_ena;
always @(posedge clk)
if (rst) fifo_level <= 0;
else fifo_level <= fifo_level + fifo_level_inc;
// DMA
// ---
// Register Write
always @(posedge clk or posedge rst)
if (rst) dma_run <= 1'b0;
else if (bus_we_csr) dma_run <= wb_wdata[0];
// Address
always @(posedge clk)
if (rst) dma_addr <= 0;
else if (bus_we_base) dma_addr <= wb_wdata[AL:0];
else if (mi_valid & mi_ready) dma_addr <= dma_addr + BURST_LEN;
// Control
always @(posedge clk)
if (rst) dma_state <= DS_IDLE;
else dma_state <= dma_state_nxt;
always @(*) begin
// Default is no change
dma_state_nxt = dma_state;
// Transitions
case (dma_state)
DS_IDLE: if (|fifo_level[8:6] & dma_run) dma_state_nxt = DS_CMD;
DS_CMD: if (mi_ready) dma_state_nxt = DS_WAIT;
DS_WAIT: if (mi_wack & mi_wlast) dma_state_nxt = DS_IDLE;
endcase
end
// MemIF commands
assign mi_addr = dma_addr;
assign mi_len = (BURST_LEN - 1);
assign mi_rw = 1'b0;
assign mi_valid = (dma_state == DS_CMD);
// MemIF data from FIFO
assign mi_wdata = fr_data;
assign fr_ena = mi_wack;
endmodule
| 7.967197 |
module spi_dev_scmd #(
parameter [7:0] CMD_BYTE = 8'h00,
parameter integer CMD_LEN = 4,
parameter integer CMD_REPEAT = 0,
// auto
parameter integer DL = (8 * CMD_LEN) - 1
) (
// Protocol wrapper interface
input wire [7:0] pw_wdata,
input wire pw_wcmd,
input wire pw_wstb,
input wire pw_end,
// Command output
output wire [DL:0] cmd_data,
output reg cmd_stb,
// Clock / Reset
input wire clk,
input wire rst
);
// Signals
// -------
// Write Shift
reg [DL:0] ws_data;
reg [CMD_LEN-1:0] ws_stb_shift;
// Command match
(* keep *)
wire [1:0] cmd_match;
// Command decoder
// ---------------
// Data shift register
always @(posedge clk) if (pw_wstb) ws_data <= {ws_data[DL-8:0], pw_wdata};
assign cmd_data = ws_data;
// Command match
assign cmd_match[0] = CMD_BYTE[7:4] == pw_wdata[7:4];
assign cmd_match[1] = CMD_BYTE[3:0] == pw_wdata[3:0];
always @(posedge clk or posedge rst)
if (rst) ws_stb_shift <= 0;
else if (pw_wstb)
ws_stb_shift <= pw_wcmd ?
{ { (CMD_LEN-1){1'b0} }, &cmd_match } :
{ ws_stb_shift[CMD_LEN-2:0], CMD_REPEAT ? ws_stb_shift[CMD_LEN-1] : 1'b0 };
always @(posedge clk) cmd_stb <= pw_wstb & ~pw_wcmd & ws_stb_shift[CMD_LEN-1];
endmodule
| 7.884751 |
module spi_dev_to_wb_tb;
// Signals
reg rst = 1'b1;
reg clk = 1'b0;
reg [ 7:0] pw_wdata;
reg pw_wcmd;
reg pw_wstb;
reg pw_end;
wire [31:0] wb_wdata;
wire [95:0] wb_rdata;
wire [23:0] wb_addr;
wire wb_we;
wire [ 2:0] wb_cyc;
reg [ 2:0] wb_ack;
// Setup recording
initial begin
$dumpfile("spi_dev_to_wb_tb.vcd");
$dumpvars(0, spi_dev_to_wb_tb);
end
// Reset pulse
initial begin
#200 rst = 0;
#1000000 $finish;
end
// Clocks
always #10 clk = !clk;
// DUT
spi_dev_to_wb #(
.WB_N(3)
) dut_I (
.pw_wdata(pw_wdata),
.pw_wcmd (pw_wcmd),
.pw_wstb (pw_wstb),
.pw_end (pw_end),
.wb_wdata(wb_wdata),
.wb_rdata(wb_rdata),
.wb_addr (wb_addr),
.wb_we (wb_we),
.wb_cyc (wb_cyc),
.wb_ack (wb_ack),
.clk (clk),
.rst (rst)
);
// Fake WB responder
always @(posedge clk) wb_ack <= wb_cyc & ~wb_ack;
assign wb_rdata[31:0] = (~wb_we & wb_ack[0]) ? 32'h600dbabe : 32'h00000000;
assign wb_rdata[63:32] = (~wb_we & wb_ack[1]) ? 32'hbaadbabe : 32'h00000000;
assign wb_rdata[95:64] = (~wb_we & wb_ack[2]) ? 32'hcafebabe : 32'h00000000;
// Stimulus
task pw_write;
input cmd;
input [7:0] data;
begin
pw_wdata <= data;
pw_wcmd <= cmd;
pw_wstb <= 1'b1;
@(posedge clk);
pw_wdata <= 8'hxx;
pw_wcmd <= 1'bx;
pw_wstb <= 1'b0;
@(posedge clk);
@(posedge clk);
end
endtask
initial begin
// Default
pw_wdata <= 8'hxx;
pw_wcmd <= 1'bx;
pw_wstb <= 1'b0;
pw_end <= 1'b0;
// Wait for reset
@(negedge rst);
@(posedge clk);
// Issue command
pw_write(1, 8'hf0);
pw_write(1, 8'ha1); // Mode W, Auto-increment, Device 1
pw_write(1, 8'h12);
pw_write(1, 8'h34);
pw_write(1, 8'h56);
pw_write(1, 8'hb0);
pw_write(1, 8'h0b);
pw_write(1, 8'h1e);
pw_write(1, 8'h50);
pw_write(1, 8'hca);
pw_write(1, 8'hfe);
pw_write(1, 8'hba);
pw_write(1, 8'hbe);
@(posedge clk);
pw_end <= 1'b1;
@(posedge clk);
pw_end <= 1'b0;
// Issue command
pw_write(1, 8'hf0);
pw_write(0, 8'h82); // Mode W, No-increment, Device 2
pw_write(0, 8'h12);
pw_write(0, 8'h34);
pw_write(0, 8'h56);
pw_write(0, 8'hb0);
pw_write(0, 8'h0b);
pw_write(0, 8'h1e);
pw_write(0, 8'h50);
pw_write(0, 8'hca);
pw_write(0, 8'hfe);
pw_write(0, 8'hba);
pw_write(0, 8'hbe);
@(posedge clk);
pw_end <= 1'b1;
@(posedge clk);
pw_end <= 1'b0;
// Issue command
pw_write(1, 8'hf0);
pw_write(0, 8'hc2); // Mode W, Re-address, Device 2
pw_write(0, 8'h22);
pw_write(0, 8'h22);
pw_write(0, 8'h22);
pw_write(0, 8'hb0);
pw_write(0, 8'h0b);
pw_write(0, 8'h1e);
pw_write(0, 8'h50);
pw_write(0, 8'hc0); // Mode W, Re-address, Device 0
pw_write(0, 8'h11);
pw_write(0, 8'h11);
pw_write(0, 8'h11);
pw_write(0, 8'hca);
pw_write(0, 8'hfe);
pw_write(0, 8'hba);
pw_write(0, 8'hbe);
pw_write(0, 8'h40); // Mode R, Re-address, Device 0
pw_write(0, 8'h11);
pw_write(0, 8'h11);
pw_write(0, 8'h11);
pw_write(0, 8'hca);
pw_write(0, 8'hfe);
pw_write(0, 8'hba);
pw_write(0, 8'hbe);
@(posedge clk);
pw_end <= 1'b1;
@(posedge clk);
pw_end <= 1'b0;
end
endmodule
| 6.963367 |
module spi_encoder #(
parameter DATA_SIZE = 8 // The size of the parallel input data.
) (
//
// ------- Inputs -------
//
input I_sclk, // Serial data clock
input I_enable, // Enable for the decoder
input I_latch, // Latch for reading data into shift register
input [DATA_SIZE - 1:0] I_data, // Parallel input data
//
// ------- Outputs -------
//
output O_sdo // Serial data output
);
reg [DATA_SIZE - 1:0] shift_data; // Shift register data
reg sdo_enable; // SDO enable
// Assign SDO, assuming MSB-first transfers.
assign O_sdo = sdo_enable ? shift_data[DATA_SIZE-1] : 1'b0;
// Latch shift register, then shift data to MSB.
// ** This always block uses the negedge of the I_sclk because serial data out
// needs to be ready before the next I_sclk after a valid address has been received.
always @(negedge I_sclk)
if (I_enable) begin
if (I_latch) shift_data <= I_data;
else shift_data <= {shift_data[DATA_SIZE-2:0], 1'b0};
end else shift_data <= 0;
// Synchronize enable for SDO with the negative edge of the clock.
always @(negedge I_sclk) sdo_enable <= I_enable;
endmodule
| 7.663643 |
module spi_fast (
// SPI pads
input wire spi_mosi,
output wire spi_miso,
input wire spi_cs_n,
input wire spi_clk,
// Interface
output reg [7:0] addr,
output reg [7:0] data,
output wire first,
output wire last,
output reg strobe,
input wire [7:0] out,
// Clock / Reset
input wire clk,
input wire rst
);
// Signals
// -------
// Core IF
wire [7:0] core_out_data;
wire core_out_stb;
wire core_out_prestb;
wire [7:0] core_in_data;
wire core_in_ack;
wire csn_state;
wire csn_rise;
wire csn_fall;
// "Simple Bus"
reg rx_first;
reg rx_second;
reg rx_third;
reg tx_first;
wire addr_ce;
reg first_i;
reg last_i;
// Core
// ----
spi_fast_core core_I (
.spi_miso(spi_miso),
.spi_mosi(spi_mosi),
.spi_clk(spi_clk),
.spi_cs_n(spi_cs_n),
.user_out(core_out_data),
.user_out_stb(core_out_stb),
.user_out_prestb(core_out_prestb),
.user_in(core_in_data),
.user_in_ack(core_in_ack),
.csn_state(csn_state),
.csn_rise(csn_rise),
.csn_fall(csn_fall),
.clk(clk),
.rst(rst)
);
// Interface to "Simple Bus"
// -------------------------
// Track state
always @(posedge clk) tx_first <= (tx_first | csn_state) & ~core_in_ack;
always @(posedge clk) begin
rx_first <= (rx_first | csn_state) & ~core_out_stb;
rx_second <= (rx_second & ~core_out_stb & ~csn_state) | (rx_first & core_out_stb);
rx_third <= (rx_third & ~core_out_stb & ~csn_state) | (rx_second & core_out_stb);
end
// Status sent as first word
assign core_in_data = tx_first ? out : 8'h00;
// Address register
always @(posedge clk) if (addr_ce) addr <= core_out_data;
assign addr_ce = core_out_stb & rx_first;
// Data register
// (this is needed because we need to be able to hold the data until
// we know if it's the last or not ...)
always @(posedge clk) if (core_out_prestb | csn_rise) data <= core_out_data;
// External strobes
always @(posedge clk) begin
first_i <= (first_i & ~core_out_stb & ~csn_rise) | rx_third;
last_i <= (last_i & ~core_out_stb) | csn_rise;
strobe <= csn_rise | (core_out_stb & ~rx_first & ~rx_second);
end
assign first = first_i;
assign last = last_i;
endmodule
| 7.545359 |
module spi_fast_core_tb;
// Signals
reg rst = 1'b1;
reg clk = 1'b0;
wire spi_mosi;
wire spi_miso;
wire spi_cs_n;
wire spi_clk;
wire [7:0] user_out;
wire user_out_stb;
wire [7:0] user_in;
wire user_in_ack;
wire csn_state;
wire csn_rise;
wire csn_fall;
// Setup recording
initial begin
$dumpfile("spi_fast_core_tb.vcd");
$dumpvars(0, spi_fast_core_tb);
end
// Reset pulse
initial begin
#200 rst = 0;
#1000000 $finish;
end
// Clocks
always #10 clk = !clk;
// DUT
spi_fast_core spi_I (
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
.spi_cs_n(spi_cs_n),
.spi_clk(spi_clk),
.user_out(user_out),
.user_out_stb(user_out_stb),
.user_in(user_in),
.user_in_ack(user_in_ack),
.csn_state(csn_state),
.csn_rise(csn_rise),
.csn_fall(csn_fall),
.clk(clk),
.rst(rst)
);
// Dummy TX
assign user_in = 8'hBA;
// SPI data generation
reg [71:0] spi_csn_data = 72'b11110000000000000000000000000000000000000000000000000001111;
reg [71:0] spi_clk_data = 72'b00000010101010101010101010101010101010101010101010101000000;
reg [71:0] spi_dat_data = 72'b00000110011000011001111110000000000111111000000001100000000;
reg [ 4:0] div;
always @(posedge clk)
if (rst) div <= 0;
else div <= div + 1;
always @(posedge clk)
if (1 || div == 4'hf) begin
spi_csn_data <= {spi_csn_data[70:0], spi_csn_data[71]};
spi_clk_data <= {spi_clk_data[70:0], spi_clk_data[71]};
spi_dat_data <= {spi_dat_data[70:0], spi_dat_data[71]};
end
assign spi_mosi = spi_dat_data[70];
assign spi_cs_n = spi_csn_data[70];
assign spi_clk = spi_clk_data[70];
endmodule
| 7.177189 |
module spi_file (
// pins
input spi_mosi,
output spi_miso,
input spi_cs_n,
input spi_clk,
output irq_n,
input clk,
input resetq,
// input request
output file_request_ready,
input file_request_valid,
input [31:0] file_request_offset,
// received data
output [ 7:0] file_data,
output file_data_avail
);
/***************************************************************************/
// SPI interface.
/***************************************************************************/
wire [7:0] usr_miso_data, usr_mosi_data;
wire usr_mosi_stb, usr_miso_ack;
wire csn_state, csn_rise, csn_fall;
spi_dev_core _communication (
.clk(clk),
.rst(resetq),
.usr_mosi_data(usr_mosi_data),
.usr_mosi_stb (usr_mosi_stb),
.usr_miso_data(usr_miso_data),
.usr_miso_ack (usr_miso_ack),
.csn_state(csn_state),
.csn_rise (csn_rise),
.csn_fall (csn_fall),
// Interface to SPI wires
.spi_miso(spi_miso),
.spi_mosi(spi_mosi),
.spi_clk (spi_clk),
.spi_cs_n(spi_cs_n)
);
wire [7:0] pw_wdata;
wire pw_wcmd, pw_wstb, pw_end;
wire [7:0] pw_rdata;
wire pw_req, pw_rstb, pw_gnt;
wire [3:0] pw_irq;
wire irq;
spi_dev_proto _protocol (
.clk(clk),
.rst(resetq),
// Connection to the actual SPI module:
.usr_mosi_data(usr_mosi_data),
.usr_mosi_stb (usr_mosi_stb),
.usr_miso_data(usr_miso_data),
.usr_miso_ack (usr_miso_ack),
.csn_state(csn_state),
.csn_rise (csn_rise),
.csn_fall (csn_fall),
// These wires deliver received data:
.pw_wdata(pw_wdata),
.pw_wcmd (pw_wcmd),
.pw_wstb (pw_wstb),
.pw_end (pw_end),
// Replies and requests
.pw_req (pw_req),
.pw_gnt (pw_gnt),
.pw_rdata(pw_rdata),
.pw_rstb (pw_rstb),
.pw_irq(pw_irq),
.irq (irq)
);
assign pw_irq[3:1] = 3'b000;
assign irq_n = irq ? 1'b0 : 1'bz;
/***************************************************************************/
// File request interface over SPI.
/***************************************************************************/
spi_dev_fread #(
.INTERFACE("STREAM")
) _fread (
.clk(clk),
.rst(resetq),
// SPI interface
.pw_wdata(pw_wdata),
.pw_wcmd (pw_wcmd),
.pw_wstb (pw_wstb),
.pw_end (pw_end),
.pw_req (pw_req),
.pw_gnt (pw_gnt),
.pw_rdata(pw_rdata),
.pw_rstb (pw_rstb),
.pw_irq (pw_irq[0]),
// Read request interface
.req_file_id(32'hBFBFBFBF),
.req_offset (file_request_offset),
.req_len (10'd1023), // One less than the actual requested length!
.req_valid(file_request_valid),
.req_ready(file_request_ready),
// Stream reply interface
.resp_data (file_data),
.resp_valid(file_data_avail)
);
endmodule
| 8.509388 |
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