code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module spi_final_tb ();
parameter n = 7; //Defining the parameter n=7 for 8-bits.
reg clk, ss0, ss1, ss2, load, rst; //Declaring the inputs as reg.
reg [0:7] data_inp; //Declaring the data input.
wire [0:7] master_data1; //Declaring the outputs as wire.
wire mosi;
wire [0:7] slave_data1, slave_data2, sl... | 7.205388 |
module spi_flash_be (
input wire sys_clk, //系统时钟，频率50MHz
input wire sys_rst_n, //复位信号,低电平有效
input wire pi_key, //按键输入信号
output wire cs_n, //片选信号
output wire sck, //串行时钟
output wire mosi //主输出从输入数据
);
//********************************************************************//
//**... | 9.582677 |
module spi_flash_clgen (
clk_in,
rst,
go,
enable,
last_clk,
clk_out,
pos_edge,
neg_edge
);
parameter divider_len = 2;
parameter divider = 1;
parameter Tp = 1;
input clk_in; // input clock (system clock)
input rst; // reset
input enable; // clock enable
input go; // s... | 6.559539 |
module spi_flash_pp (
input wire sys_clk, //系统时钟，频率50MHz
input wire sys_rst_n, //复位信号,低电平有效
input wire pi_key, //按键输入信号
output wire cs_n, //片选信号
output wire sck, //串行时钟
output wire mosi //主输出从输入数据
);
//********************************************************************//
//**... | 9.13151 |
module spi_flash_read (
input wire sys_clk, //系统时钟，频率50MHz
input wire sys_rst_n, //复位信号,低电平有效
input wire pi_key, //按键输入信号
input wire miso, //读出flash数据
output wire cs_n, //片选信号
output wire sck, //串行时钟
output wire mosi, //主输出从输入数据
output wire tx
);
//***************... | 7.669238 |
module spi_flash_reader_tb;
// Signals
reg rst = 1'b1;
reg clk = 1'b0;
wire spi_mosi;
wire spi_miso;
wire spi_cs_n;
wire spi_clk;
wire [23:0] addr;
wire [15:0] len;
wire go;
wire rdy;
wire [7:0] data;
wire valid;
reg flip;
reg [23:0] cnt;
// Setup recording
initial begin
$dum... | 7.669238 |
module spi_flash_se (
input wire sys_clk, //系统时钟，频率50MHz
input wire sys_rst_n, //复位信号,低电平有效
input wire pi_key, //按键输入信号
output wire cs_n, //片选信号
output wire sck, //串行时钟
output wire mosi //主输出从输入数据
);
//********************************************************************//
//**... | 9.396052 |
module spi_flash_seq_wr (
input wire sys_clk, //系统时钟，频率50MHz
input wire sys_rst_n, //复位信号,低电平有效
input wire rx, //串口接收数据
output wire cs_n, //片选信号
output wire sck, //串行时钟
output wire mosi, //主输出从输入数据
output wire tx //串口发送数据
);
//***************************************... | 8.371752 |
module spi_flash_shift (
clk,
rst,
latch,
byte_sel,
len,
go,
pos_edge,
neg_edge,
lsb,
rx_negedge,
tx_negedge,
tip,
last,
p_in,
p_out,
s_clk,
s_in,
s_out
);
parameter Tp = 1;
input clk; // system clock
input rst; // reset
input latch; /... | 7.481809 |
module SPI_FPGA_SLAVE_CPHA_EQ_0_CPOL_EQ_0 //старший бит вперед
#(
parameter PACK_LENGTH = 8,
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH)
) (
input [PACK_LENGTH-1:0] IN_TRANSMIT_DATA,
input MOSI,
input CS,
input ... | 6.69837 |
module SPI_FPGA_SLAVE_CPHA_EQ_0_CPOL_EQ_1 //старший бит вперед
#(
parameter PACK_LENGTH = 8,
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH)
) (
input [PACK_LENGTH-1:0] IN_TRANSMIT_DATA,
input MOSI,
input CS,
input ... | 6.69837 |
module SPI_FPGA_SLAVE_CPHA_EQ_1_CPOL_EQ_0 //старший бит вперед
#(
parameter PACK_LENGTH = 8,
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH)
) (
input [PACK_LENGTH-1:0] IN_TRANSMIT_DATA,
input MOSI,
input CS,
input ... | 6.69837 |
module SPI_FPGA_SLAVE_CPHA_EQ_1_CPOL_EQ_1 //старший бит вперед
#(
parameter PACK_LENGTH = 8,
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH)
) (
input [PACK_LENGTH-1:0] IN_TRANSMIT_DATA,
input MOSI,
input CS,
input ... | 6.69837 |
module SPI_FPGA_TB1_CPOL_EQ_0_CPHA_EQ_0_M_TO_S_EQ_0_S_TO_M_EQ_0 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
... | 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_0_CPHA_EQ_0_M_TO_S_EQ_0_S_TO_M_EQ_1 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
... | 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_0_CPHA_EQ_0_M_TO_S_EQ_1_S_TO_M_EQ_0 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
... | 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_0_CPHA_EQ_0_M_TO_S_EQ_0_S_TO_M_EQ_1 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
... | 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_1_CPHA_EQ_0_M_TO_S_EQ_0_S_TO_M_EQ_0 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b1,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
... | 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_1_CPHA_EQ_0_M_TO_S_EQ_0_S_TO_M_EQ_1 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b1,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
... | 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_1_CPHA_EQ_0_M_TO_S_EQ_1_S_TO_M_EQ_0 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b1,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
... | 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_1_CPHA_EQ_0_M_TO_S_EQ_1_S_TO_M_EQ_1 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b1,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
... | 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_0_CPHA_EQ_1_M_TO_S_EQ_0_S_TO_M_EQ_0 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b1,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
... | 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_0_CPHA_EQ_1_M_TO_S_EQ_0_S_TO_M_EQ_1 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b1,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
... | 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_0_CPHA_EQ_1_M_TO_S_EQ_1_S_TO_M_EQ_0 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b1,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
... | 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_0_CPHA_EQ_1_M_TO_S_EQ_1_S_TO_M_EQ_1 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b1,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
... | 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_1_CPHA_EQ_1_M_TO_S_EQ_0_S_TO_M_EQ_0 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b1,
parameter CPHA = 1'b1,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
... | 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_1_CPHA_EQ_1_M_TO_S_EQ_0_S_TO_M_EQ_1 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b1,
parameter CPHA = 1'b1,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
... | 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_1_CPHA_EQ_1_M_TO_S_EQ_1_S_TO_M_EQ_0 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b1,
parameter CPHA = 1'b1,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
... | 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_1_CPHA_EQ_1_M_TO_S_EQ_1_S_TO_M_EQ_1 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b1,
parameter CPHA = 1'b1,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
... | 7.661703 |
module SPI_FPGA_TB1 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_... | 7.280926 |
module SPI_FPGA_TB2 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_... | 6.907803 |
module SPI_FPGA_TB3 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_... | 7.397924 |
module SPI_FPGA_TB4_CPOL_1_CPHA_1_M_TO_S_1_S_TO_M_0 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b1,
parameter CPHA = 1'b1,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter ... | 7.566786 |
module SPI_FPGA_TB4 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_... | 7.694781 |
module SPI_FPGA_TB5 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_... | 7.631141 |
module spi_fsm #(
parameter DEPTH = 8, // number of chunks
parameter WIDTH = 8, // bits per chunk
parameter WRCMD = 8'h01,
parameter RDCMD = 8'h02
) (
input clk,
input rst,
output reg spi_we, // spi_slave wr
input spi_dv, // spi_slave rx_dv
input spi_halt,
input [WIDTH-1:0] ... | 8.302968 |
module acts as the translator from
// SPI slave to an 8-bit address, 8-bit data local bus.
// That super-stripped down SPI concept could be revisited if we can verify
// a suitable portable (STM32 and LPC) API on the microcontroller side.
module spi_gate(
// pins
input SCLK,
input CSB,
input MOSI,
output MISO,
//... | 7.829874 |
module bin2gray (
bin,
gray
);
parameter SIZE = 8;
input [SIZE-1:0] bin;
output [SIZE-1:0] gray;
assign gray = (bin >> 1) ^ bin;
endmodule
| 6.587586 |
module gray_counter (clk_i, rst_n_i, en_i, period_i, clock_o);
parameter SIZE = 8;
input clk_i;
input rst_n_i;
input en_i;
input [SIZE-1:0] period_i;
output clock_o;
reg [SIZE-1:0] gray_code;
reg [SIZE-1:0] tog;
reg clock;
wire [SIZE-1:0] gray_code_comp;... | 6.858216 |
module spi_if (
clk,
reset_n,
// towards ctrl i/f
sck_pe,
sck_int,
cs_int_n,
byte_in,
load_byte,
byte_out,
shift_out,
shift_in,
cfg_tgt_sel,
sck,
so,
si,
cs_n
);
input clk, reset_n;
input sck_pe;
input sck_int, cs_int_n;
input load_byte;
inp... | 6.662688 |
module spi_interf (
input wire clk,
input wire sclk,
input wire cs_n,
input wire load,
input wire [26:0] data_in,
output wire serial_out
);
reg [26:0] data;
reg [1:0] sclk_r;
reg [1:0] cs_n_r;
wire sclk_ne = (sclk_r == 2'b10);
always @(posedge clk) begin
sclk_r <= {sclk_r[0], sc... | 7.045277 |
module SPI_Interface (
input iCLK,
input iCLK_50,
input Reset,
output SD_CLK,
output SD_MOSI,
input SD_MISO,
output SD_CS,
// Barramento de dados
input wReadEnable,
wWriteEnable,
input [ 3:0] wByteEnable,
input... | 6.535791 |
module spi_interface_master #(
parameter SPI_MAX_WIDTH_LOG = 4,
parameter SPI_SCAIL_LOG = 8
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input spi_start,
output spi_finish,
output sck,
output cs,
output mosi,
input miso,
input config_req,
i... | 7.730375 |
module spi_interface_slave #(
parameter SPI_MAX_WIDTH_LOG = 4
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
output spi_start,
output spi_finish,
input sck,
input cs,
input mosi,
output miso,
input config_req,
input [SPI_MAX_WIDTH_LOG + 1:0] con... | 7.730375 |
module spi_io (
clk,
start,
ctrl_reg,
din,
dout,
status_reg,
sclk,
miso,
mosi
);
input wire clk;
input wire start;
input wire [31:0] ctrl_reg; //interface for data width and speed
input wire [31:0] din; //input data, left justified
input wire miso;
output reg [31:0] d... | 7.353623 |
module: spi_io
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module spi_io_tb;
// Inputs
reg clk;
reg start;
reg [31:0] ctrl_reg;
reg [31:0] din;
reg miso;
// Outputs
wire [31:0... | 6.575778 |
module CKHS_INVX1 (
z,
a
);
input a;
output z;
SEH_INV_S_1 u (
.A(a),
.X(z)
);
endmodule
| 7.359776 |
module CKHS_MUX2X2 (
z,
d1,
d0,
sd
);
input d1, d0, sd;
output z;
SEH_MUX2_S_2 u (
.D0(d0),
.D1(d1),
.S (sd),
.X (z)
);
endmodule
| 6.598457 |
module CKHS_BUFX4_0 (
z,
a
);
input a;
output z;
SEH_BUF_S_4 u (
.A(a),
.X(z)
);
endmodule
| 7.290982 |
module CKHS_MUX4X2 (
z,
d3,
d2,
d1,
d0,
sd2,
sd1
);
input d3, d2, d1, d0, sd2, sd1;
output z;
SEH_MUX4_DG_2 u (
.D0(d0),
.D1(d1),
.D2(d2),
.D3(d3),
.S0(sd1),
.S1(sd2),
.X (z)
);
endmodule
| 6.53252 |
module CKHS_BUFX4_1 (
z,
a
);
input a;
output z;
SEH_BUF_S_4 u (
.A(a),
.X(z)
);
endmodule
| 7.25101 |
module SPI_LCD (
input wire clk,
input wire [3:0] rows,
input wire MISO,
clear,
output wire MOSI,
SCLK,
SS,
output wire [3:0] cols
);
wire clk_500KHz, clk_250KHz, clk_1KHz;
wire key_data_ready, data_ready_synced, lcd_send;
wire [6:0] encoder_out, lcd_data_out;
wire clear_inv, sp... | 6.856694 |
module that integrating keypad and SPI display
module SPI_LCD_top(
(*chip_pin = "E17"*)output MOSI,
(*chip_pin = "G17"*)input MISO,
(*chip_pin = "D17"*)output SS,
(*chip_pin = "H18"*)output SCLK,
(*chip_pin = "M18"*)inout VCC,
(*chip_pin = "K18"*)inout GND,
(*chip_pin = "J6"*) input clkin,
(*chip_pin="D... | 7.875918 |
module spi_lite_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//-----------------------------------------------------------------
// ... | 6.714668 |
module spi_loader_wrap #(
parameter MEM_TYPE = "DUAL_SPRAM",
ST_ADDR = 24'h020000
) (
input resetn, //
input clk, // Clock (= RISC-V clock)
input i_init,
// FIFO interface
input i_fill,
output o_fifo_empty,
output o_fifo_low,
input i_fifo_rd,
... | 6.822725 |
module SPI_loopback #(
parameter CLK_FREQUENCE = 50_000_000, //system clk frequence
SPI_FREQUENCE = 5_000_000, //spi clk frequence
DATA_WIDTH = 8, //serial word length
CPOL = 0, //SPI mode selection (mode 0 default)
CPHA ... | 8.799181 |
module SPI_loopback_tb ();
parameter CLK_FREQUENCE = 50_000_000 ,
SPI_FREQUENCE = 5_000_000 ,
DATA_WIDTH = 8 ,
CPOL = 0 ,
CPHA = 0 ;
reg clk;
reg rst_n;
reg [DATA_WIDTH-1:0] data_m_in;
reg [DATA_WIDTH-1:0] data_s_in;
reg ... | 7.741791 |
module spi_master0_37 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
lo... | 8.133749 |
module spi_master10_47 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
l... | 7.785648 |
module spi_master11_48 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
l... | 7.851033 |
module spi_master12_49 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
l... | 7.888647 |
module spi_master13_50 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
l... | 7.898857 |
module spi_master14_51 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
l... | 7.865188 |
module spi_master15_52 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
l... | 8.028121 |
module spi_master16_53 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
l... | 7.944648 |
module spi_master17_54 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
l... | 8.158599 |
module spi_master18_55 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
l... | 8.184709 |
module spi_master19_56 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
l... | 8.294831 |
module spi_master1_38 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
lo... | 8.041383 |
module spi_master20_57 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
l... | 8.175769 |
module spi_master21_58 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
l... | 7.813494 |
module spi_master22_59 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
l... | 7.99538 |
module spi_master23_60 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
l... | 8.128513 |
module spi_master24_61 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
l... | 7.827576 |
module spi_master25_62 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
l... | 8.037488 |
module spi_master26_63 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
l... | 7.941921 |
module spi_master27_64 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
l... | 7.954921 |
module spi_master28_65 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
l... | 7.940503 |
module spi_master29_66 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
l... | 8.056942 |
module spi_master2_39 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
lo... | 8.127403 |
module spi_master30_67 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
l... | 8.157523 |
module spi_master31_68 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
l... | 7.94063 |
module spi_master32_69 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
l... | 8.081446 |
module spi_master3_40 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
lo... | 8.128919 |
module spi_master4_41 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
lo... | 7.85054 |
module spi_master5_42 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
lo... | 8.105354 |
module spi_master6_43 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
lo... | 8.019294 |
module spi_master7_44 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
lo... | 8.157203 |
module spi_master8_45 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
lo... | 8.150674 |
module spi_master9_46 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
lo... | 7.846677 |
module spi_master_3 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 4'h8;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
loca... | 8.187428 |
module spi_master (
rstb,
clk,
mlb,
start,
tdat,
cdiv,
din,
ss,
sck,
dout,
done_r,
rdata
);
parameter state_idle = 4'd0;
parameter state_send = 4'd1;
parameter state_finish = 4'd2;
input rstb, clk, mlb, start;
input [31:0] tdat; //transmit data
input [1:0]... | 8.21649 |
module spi_master_7 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h5;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
loca... | 8.048569 |
module spi_master_clkgen (
clk,
rstn,
en,
clk_div,
clk_div_valid,
spi_clk,
spi_fall,
spi_rise
);
input wire clk;
input wire rstn;
input wire en;
input wire [7:0] clk_div;
input wire clk_div_valid;
output reg spi_clk;
output reg spi_fall;
output reg spi_rise;
reg [7:0] c... | 7.372709 |
module spi_master_ctrl (
input clk,
input reset,
input wr,
input rd,
input [7:0] addr,
input [7:0] cpu_di,
output reg [7:0] cpu_do,
input [7:0] rxData,
input rxDataRdySet,
output reg [7:0] txData,
output reg txDataFull,
input txDataFullClr,
input txDataEmpty,
o... | 6.679552 |
module spi_master_driver (
input clk_i,
input rst_i,
// system interface
input start_i, // signal to start transaction
input [7:0] data_in_bi, // data that master will write to slave
output reg busy_o, // transaction is being processed
output reg [7:0] data_o... | 7.596245 |
module spi_master_fifo #(
parameter DATA_WIDTH = 32,
parameter BUFFER_DEPTH = 2,
parameter LOG_BUFFER_DEPTH = `log2(BUFFER_DEPTH)
) (
clk_i,
rst_ni,
clr_i,
elements_o,
data_o,
valid_o,
ready_i,
valid_i,
data_i,
ready_o
);
//parameter DATA_WIDTH = 32;
//parameter B... | 6.959157 |
module spi_master_model (
clk,
rst,
adr,
din,
dout,
wr,
rd
);
parameter dwidth = 8;
parameter awidth = 4;
input clk, rst;
output [awidth -1:0] adr;
input [dwidth -1:0] din;
output [dwidth -1:0] dout;
output wr, rd;
///////////////////////////////////////////////////... | 7.276598 |
module must be run for a clock cycle count
// of at least (DATABITSZ * (1 << (SCLKDIVLIMIT-1))) with "stb_i" low.
module spi_master_phy (
clk_i
,sclk_o ,mosi_o ,miso_i ,cs_o
,stb_i ,rdy_o ,rcvd_o ,sclkdiv_i
,data_o ,data_i
);
`include "lib/clog2.v"
parameter DATABITSZ = 2;
parameter SCLKDIVLIMIT = 1;
loc... | 6.817562 |
module spi_master_reduced (
clk,
rst_n,
spi_miso,
spi_mosi,
spi_clk,
spi_tx_en,
spi_rx_en,
mode_select,
receive_status
);
parameter DATA_LENGTH = 64;
input clk;
input rst_n;
input spi_miso;
output spi_mosi;
output spi_clk;
input spi_tx_en;
output receive_s... | 7.240007 |
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