code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module spi_final_tb ();
parameter n = 7; //Defining the parameter n=7 for 8-bits.
reg clk, ss0, ss1, ss2, load, rst; //Declaring the inputs as reg.
reg [0:7] data_inp; //Declaring the data input.
wire [0:7] master_data1; //Declaring the outputs as wire.
wire mosi;
wire [0:7] slave_data1, slave_data2, slave_data3;
//Instantiating the module!
top_spi_final uut (
data_inp,
load,
clk,
rst,
ss0,
ss1,
ss2,
mosi,
master_data1,
slave_data1,
slave_data2,
slave_data3
);
initial begin
forever #2 clk = ~clk; //Setting the clock time period.
end
//Giving the test cases.
initial begin
clk = 1;
rst = 1;
load = 0;
ss0 = 0;
ss1 = 0;
ss2 = 0;
data_inp = 8'b11111111;
#4;
rst = 0;
load = 1;
#4;
load = 0;
ss0 = 1;
ss1 = 0;
ss2 = 0;
#32;
ss0 = 0;
ss1 = 0;
ss2 = 1;
#32;
$finish;
end
endmodule
| 7.205388 |
module spi_flash_be (
input wire sys_clk, //系统时钟，频率50MHz
input wire sys_rst_n, //复位信号,低电平有效
input wire pi_key, //按键输入信号
output wire cs_n, //片选信号
output wire sck, //串行时钟
output wire mosi //主输出从输入数据
);
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//parameter define
parameter CNT_MAX = 20'd999_999; //计数器计数最大值
//wire define
wire po_key;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- key_filter_inst -------------
key_filter #(
.CNT_MAX(CNT_MAX) //计数器计数最大值
) key_filter_inst (
.sys_clk (sys_clk), //系统时钟，频率50MHz
.sys_rst_n(sys_rst_n), //复位信号,低电平有效
.key_in (pi_key), //按键输入信号
.key_flag(po_key) //消抖后信号
);
//------------- flash_be_ctrl_inst -------------
flash_be_ctrl flash_be_ctrl_inst (
.sys_clk (sys_clk), //系统时钟，频率50MHz
.sys_rst_n(sys_rst_n), //复位信号,低电平有效
.key (po_key), //按键输入信号
.sck (sck), //片选信号
.cs_n(cs_n), //串行时钟
.mosi(mosi) //主输出从输入数据
);
endmodule
| 9.582677 |
module spi_flash_clgen (
clk_in,
rst,
go,
enable,
last_clk,
clk_out,
pos_edge,
neg_edge
);
parameter divider_len = 2;
parameter divider = 1;
parameter Tp = 1;
input clk_in; // input clock (system clock)
input rst; // reset
input enable; // clock enable
input go; // start transfer
input last_clk; // last clock
//input [spi_divider_len-1:0] divider; // clock divider (output clock is divided by this value)
output clk_out; // output clock
output pos_edge; // pulse marking positive edge of clk_out
output neg_edge; // pulse marking negative edge of clk_out
reg clk_out;
reg pos_edge;
reg neg_edge;
reg [divider_len-1:0] cnt; // clock counter
wire cnt_zero; // conter is equal to zero
wire cnt_one; // conter is equal to one
assign cnt_zero = cnt == {divider_len{1'b0}};
assign cnt_one = cnt == {{divider_len - 1{1'b0}}, 1'b1};
// Counter counts half period
always @(posedge clk_in or posedge rst) begin
if (rst) cnt <= #Tp{divider_len{1'b1}};
else begin
if (!enable || cnt_zero) cnt <= #Tp divider;
else cnt <= #Tp cnt - {{divider_len - 1{1'b0}}, 1'b1};
end
end
// clk_out is asserted every other half period
always @(posedge clk_in or posedge rst) begin
if (rst) clk_out <= #Tp 1'b0;
else clk_out <= #Tp(enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
end
// Pos and neg edge signals
always @(posedge clk_in or posedge rst) begin
if (rst) begin
pos_edge <= #Tp 1'b0;
neg_edge <= #Tp 1'b0;
end else begin
pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
neg_edge <= #Tp(enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
end
end
endmodule
| 6.559539 |
module spi_flash_pp (
input wire sys_clk, //系统时钟，频率50MHz
input wire sys_rst_n, //复位信号,低电平有效
input wire pi_key, //按键输入信号
output wire cs_n, //片选信号
output wire sck, //串行时钟
output wire mosi //主输出从输入数据
);
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//parameter define
parameter CNT_MAX = 20'd999_999; //计数器计数最大值
//wire define
wire po_key;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- key_filter_inst -------------
key_filter #(
.CNT_MAX(CNT_MAX) //计数器计数最大值
) key_filter_inst (
.sys_clk (sys_clk), //系统时钟，频率50MHz
.sys_rst_n(sys_rst_n), //复位信号,低电平有效
.key_in (pi_key), //按键输入信号
.key_flag(po_key) //消抖后信号
);
//------------- flash_pp_ctrl_inst -------------
flash_pp_ctrl flash_pp_ctrl_inst (
.sys_clk (sys_clk), //系统时钟，频率50MHz
.sys_rst_n(sys_rst_n), //复位信号,低电平有效
.key (po_key), //按键输入信号
.sck (sck), //片选信号
.cs_n(cs_n), //串行时钟
.mosi(mosi) //主输出从输入数据
);
endmodule
| 9.13151 |
module spi_flash_read (
input wire sys_clk, //系统时钟，频率50MHz
input wire sys_rst_n, //复位信号,低电平有效
input wire pi_key, //按键输入信号
input wire miso, //读出flash数据
output wire cs_n, //片选信号
output wire sck, //串行时钟
output wire mosi, //主输出从输入数据
output wire tx
);
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//parameter define
parameter CNT_MAX = 20'd999_999; //计数器计数最大值
parameter UART_BPS = 14'd9600, //比特率
CLK_FREQ = 26'd50_000_000; //时钟频率
//wire define
wire po_key; //消抖处理后的按键信号
wire tx_flag; //输入串口发送模块数据标志信号
wire [7:0] tx_data; //输入串口发送模块数据
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- key_filter_inst -------------
key_filter #(
.CNT_MAX(CNT_MAX) //计数器计数最大值
) key_filter_inst (
.sys_clk (sys_clk), //系统时钟，频率50MHz
.sys_rst_n(sys_rst_n), //复位信号,低电平有效
.key_in (pi_key), //按键输入信号
.key_flag(po_key) //消抖后信号
);
//-------------flash_read_ctrl_inst-------------
flash_read_ctrl flash_read_ctrl_inst (
.sys_clk (sys_clk), //系统时钟，频率50MHz
.sys_rst_n(sys_rst_n), //复位信号,低电平有效
.key (po_key), //按键输入信号
.miso (miso), //读出flash数据
.sck (sck), //片选信号
.cs_n (cs_n), //串行时钟
.mosi (mosi), //主输出从输入数据
.tx_flag(tx_flag), //输出数据标志信号
.tx_data(tx_data) //输出数据
);
//-------------uart_tx_inst-------------
uart_tx #(
.UART_BPS(UART_BPS), //串口波特率
.CLK_FREQ(CLK_FREQ) //时钟频率
) uart_tx_inst (
.sys_clk (sys_clk), //系统时钟50Mhz
.sys_rst_n(sys_rst_n), //全局复位
.pi_data (tx_data), //并行数据
.pi_flag (tx_flag), //并行数据有效标志信号
.tx(tx) //串口发送数据
);
endmodule
| 7.669238 |
module spi_flash_reader_tb;
// Signals
reg rst = 1'b1;
reg clk = 1'b0;
wire spi_mosi;
wire spi_miso;
wire spi_cs_n;
wire spi_clk;
wire [23:0] addr;
wire [15:0] len;
wire go;
wire rdy;
wire [7:0] data;
wire valid;
reg flip;
reg [23:0] cnt;
// Setup recording
initial begin
$dumpfile("spi_flash_reader_tb.vcd");
$dumpvars(0, spi_flash_reader_tb);
end
// Reset pulse
initial begin
#200 rst = 0;
#1000000 $finish;
end
// Clocks
always #33 clk = !clk; // ~ 30 MHz
// DUT
spi_flash_reader dut_I (
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
.spi_cs_n(spi_cs_n),
.spi_clk(spi_clk),
.addr(addr),
.len(len),
.go(go),
.rdy(rdy),
.data(data),
.valid(valid),
.clk(clk),
.rst(rst)
);
// No real RAM
assign spi_miso = spi_cs_n ? 1'bz : flip;
always @(posedge rst, negedge spi_clk)
if (rst) flip <= 1'b0;
else flip <= ~flip;
// Read commands
assign addr = cnt;
assign len = 16'h0000;
assign go = rdy & ~rst & ~valid;
always @(posedge clk)
if (rst) cnt <= 24'h00BABE;
else if (valid) cnt <= cnt + 1;
endmodule
| 7.669238 |
module spi_flash_se (
input wire sys_clk, //系统时钟，频率50MHz
input wire sys_rst_n, //复位信号,低电平有效
input wire pi_key, //按键输入信号
output wire cs_n, //片选信号
output wire sck, //串行时钟
output wire mosi //主输出从输入数据
);
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//parameter define
parameter CNT_MAX = 20'd999_999; //计数器计数最大值
//wire define
wire po_key;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- key_filter_inst -------------
key_filter #(
.CNT_MAX(CNT_MAX) //计数器计数最大值
) key_filter_inst (
.sys_clk (sys_clk), //系统时钟，频率50MHz
.sys_rst_n(sys_rst_n), //复位信号,低电平有效
.key_in (pi_key), //按键输入信号
.key_flag(po_key) //消抖后信号
);
//------------- flash_se_ctrl_inst -------------
flash_se_ctrl flash_se_ctrl_inst (
.sys_clk (sys_clk), //系统时钟，频率50MHz
.sys_rst_n(sys_rst_n), //复位信号,低电平有效
.key (po_key), //按键输入信号
.sck (sck), //片选信号
.cs_n(cs_n), //串行时钟
.mosi(mosi) //主输出从输入数据
);
endmodule
| 9.396052 |
module spi_flash_seq_wr (
input wire sys_clk, //系统时钟，频率50MHz
input wire sys_rst_n, //复位信号,低电平有效
input wire rx, //串口接收数据
output wire cs_n, //片选信号
output wire sck, //串行时钟
output wire mosi, //主输出从输入数据
output wire tx //串口发送数据
);
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//parameter define
parameter UART_BPS = 14'd9600, //比特率
CLK_FREQ = 26'd50_000_000; //时钟频率
//wire define
wire po_flag;
wire [7:0] po_data;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//-------------uart_rx_inst-------------
uart_rx #(
.UART_BPS(UART_BPS), //串口波特率
.CLK_FREQ(CLK_FREQ) //时钟频率
) uart_rx_inst (
.sys_clk (sys_clk), //系统时钟50Mhz
.sys_rst_n(sys_rst_n), //全局复位
.rx (rx), //串口接收数据
.po_data(po_data), //串转并后的数据
.po_flag(po_flag) //串转并后的数据有效标志信号
);
//-------------flash_seq_wr_ctrl_inst-------------
flash_seq_wr_ctrl flash_seq_wr_ctrl_inst (
.sys_clk (sys_clk), //系统时钟，频率50MHz
.sys_rst_n(sys_rst_n), //复位信号,低电平有效
.pi_flag (po_flag), //数据标志信号
.pi_data (po_data), //写入数据
.sck (sck), //片选信号
.cs_n(cs_n), //串行时钟
.mosi(mosi) //主输出从输入数据
);
//-------------uart_tx_inst-------------
uart_tx #(
.UART_BPS(UART_BPS), //串口波特率
.CLK_FREQ(CLK_FREQ) //时钟频率
) uart_tx_inst (
.sys_clk (sys_clk), //系统时钟50Mhz
.sys_rst_n(sys_rst_n), //全局复位
.pi_data (po_data), //并行数据
.pi_flag (po_flag), //并行数据有效标志信号
.tx(tx) //串口发送数据
);
endmodule
| 8.371752 |
module spi_flash_shift (
clk,
rst,
latch,
byte_sel,
len,
go,
pos_edge,
neg_edge,
lsb,
rx_negedge,
tx_negedge,
tip,
last,
p_in,
p_out,
s_clk,
s_in,
s_out
);
parameter Tp = 1;
input clk; // system clock
input rst; // reset
input latch; // latch signal for storing the data in shift register
input [3:0] byte_sel; // byte select signals for storing the data in shift register
input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
input lsb; // lbs first on the line
input tx_negedge;
input rx_negedge;
input go; // start stansfer
input pos_edge; // recognize posedge of sclk
input neg_edge; // recognize negedge of sclk
output tip; // transfer in progress
output last; // last bit
input [31:0] p_in; // parallel in
output [`SPI_MAX_CHAR-1:0] p_out; // parallel out
input s_clk; // serial clock
input s_in; // serial in
output s_out; // serial out
reg s_out;
reg tip;
reg [`SPI_CHAR_LEN_BITS:0] cnt; // data bit count
reg [ `SPI_MAX_CHAR-1:0] data; // shift register
wire [`SPI_CHAR_LEN_BITS:0] tx_bit_pos; // next bit position
wire [`SPI_CHAR_LEN_BITS:0] rx_bit_pos; // next bit position
wire rx_clk; // rx clock enable
wire tx_clk; // tx clock enable
assign p_out = data;
assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1};
assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) : (rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1});
assign last = !(|cnt);
assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
// Character bit counter
always @(posedge clk or posedge rst) begin
if (rst) cnt <= #Tp{`SPI_CHAR_LEN_BITS + 1{1'b0}};
else begin
if (tip) cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
else cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
end
end
// Transfer in progress
always @(posedge clk or posedge rst) begin
if (rst) tip <= #Tp 1'b0;
else if (go && ~tip) tip <= #Tp 1'b1;
else if (tip && last && pos_edge) tip <= #Tp 1'b0;
end
// Sending bits to the line
always @(posedge clk or posedge rst) begin
if (rst) s_out <= #Tp 1'b0;
else s_out <= #Tp(tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
end
// Receiving bits from the line
always @(posedge clk or posedge rst)
if (rst) data <= #Tp `SPI_CHAR_RST;
else if (latch & !tip) begin
if (byte_sel[0]) data[7:0] <= #Tp p_in[7:0];
if (byte_sel[1]) data[15:8] <= #Tp p_in[15:8];
if (byte_sel[2]) data[23:16] <= #Tp p_in[23:16];
if (byte_sel[3]) data[31:24] <= #Tp p_in[31:24];
end else
data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
endmodule
| 7.481809 |
module SPI_FPGA_SLAVE_CPHA_EQ_0_CPOL_EQ_0 //старший бит вперед
#(
parameter PACK_LENGTH = 8,
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH)
) (
input [PACK_LENGTH-1:0] IN_TRANSMIT_DATA,
input MOSI,
input CS,
input SCLK,
input IN_RESET,
output MISO,
output reg [PACK_LENGTH-1:0] OUT_RECEIVE_DATA
);
reg [PACK_LENGTH-1:0] REG_TRANSMIT_DATA;
reg [PACK_LENGTH_LOG_2:0] REG_BIT_INDEX;
initial begin
REG_TRANSMIT_DATA = 0;
REG_BIT_INDEX = PACK_LENGTH;
OUT_RECEIVE_DATA = 0;
end
assign MISO=!CS ? (REG_TRANSMIT_DATA[REG_BIT_INDEX-1]&(REG_BIT_INDEX>0)|REG_TRANSMIT_DATA[0]&(REG_BIT_INDEX==0)) : 1'bZ;
always @(negedge CS) REG_TRANSMIT_DATA <= IN_TRANSMIT_DATA;
always @(negedge SCLK or posedge CS or posedge IN_RESET) begin
if (IN_RESET) REG_BIT_INDEX = PACK_LENGTH;
else if (CS) REG_BIT_INDEX = PACK_LENGTH;
else REG_BIT_INDEX = REG_BIT_INDEX - 1;
end
always @(posedge SCLK or posedge IN_RESET) begin
if (IN_RESET) OUT_RECEIVE_DATA = 0;
else if (!CS) OUT_RECEIVE_DATA[REG_BIT_INDEX-1] = MOSI;
end
endmodule
| 6.69837 |
module SPI_FPGA_SLAVE_CPHA_EQ_0_CPOL_EQ_1 //старший бит вперед
#(
parameter PACK_LENGTH = 8,
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH)
) (
input [PACK_LENGTH-1:0] IN_TRANSMIT_DATA,
input MOSI,
input CS,
input SCLK,
input IN_RESET,
output MISO,
output reg [PACK_LENGTH-1:0] OUT_RECEIVE_DATA
);
reg [PACK_LENGTH-1:0] REG_TRANSMIT_DATA;
reg [PACK_LENGTH_LOG_2:0] REG_BIT_INDEX;
initial begin
REG_TRANSMIT_DATA = 0;
REG_BIT_INDEX = PACK_LENGTH;
OUT_RECEIVE_DATA = 0;
end
assign MISO=!CS ? (REG_TRANSMIT_DATA[REG_BIT_INDEX-1]&(REG_BIT_INDEX>0)|REG_TRANSMIT_DATA[0]&(REG_BIT_INDEX==0)) : 1'bZ;
always @(negedge CS) REG_TRANSMIT_DATA <= IN_TRANSMIT_DATA;
always @(posedge SCLK or posedge CS or posedge IN_RESET) begin
if (IN_RESET) REG_BIT_INDEX = PACK_LENGTH;
else if (CS) REG_BIT_INDEX = PACK_LENGTH;
else REG_BIT_INDEX = REG_BIT_INDEX - 1;
end
always @(negedge SCLK or posedge IN_RESET) begin
if (IN_RESET) OUT_RECEIVE_DATA = 0;
else if (!CS) OUT_RECEIVE_DATA[REG_BIT_INDEX-1] = MOSI;
end
endmodule
| 6.69837 |
module SPI_FPGA_SLAVE_CPHA_EQ_1_CPOL_EQ_0 //старший бит вперед
#(
parameter PACK_LENGTH = 8,
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH)
) (
input [PACK_LENGTH-1:0] IN_TRANSMIT_DATA,
input MOSI,
input CS,
input SCLK,
input IN_RESET,
output MISO,
output reg [PACK_LENGTH-1:0] OUT_RECEIVE_DATA
);
reg [ PACK_LENGTH-1:0] REG_TRANSMIT_DATA;
reg [PACK_LENGTH_LOG_2:0] REG_BIT_INDEX;
initial begin
REG_TRANSMIT_DATA = 0;
REG_BIT_INDEX = PACK_LENGTH;
OUT_RECEIVE_DATA = 0;
end
assign MISO=!CS ? (REG_TRANSMIT_DATA[REG_BIT_INDEX]&(REG_BIT_INDEX<PACK_LENGTH)|REG_TRANSMIT_DATA[PACK_LENGTH-1]&(REG_BIT_INDEX==PACK_LENGTH)) : 1'bZ;
always @(negedge CS) REG_TRANSMIT_DATA <= IN_TRANSMIT_DATA;
always @(posedge SCLK or posedge CS or posedge IN_RESET) begin
if (IN_RESET) REG_BIT_INDEX = PACK_LENGTH;
else if (CS) REG_BIT_INDEX = PACK_LENGTH;
else REG_BIT_INDEX = REG_BIT_INDEX - 1;
end
always @(negedge SCLK or posedge IN_RESET) begin
if (IN_RESET) OUT_RECEIVE_DATA = 0;
else if (!CS) OUT_RECEIVE_DATA[REG_BIT_INDEX] = MOSI;
end
endmodule
| 6.69837 |
module SPI_FPGA_SLAVE_CPHA_EQ_1_CPOL_EQ_1 //старший бит вперед
#(
parameter PACK_LENGTH = 8,
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH)
) (
input [PACK_LENGTH-1:0] IN_TRANSMIT_DATA,
input MOSI,
input CS,
input SCLK,
input IN_RESET,
output MISO,
output reg [PACK_LENGTH-1:0] OUT_RECEIVE_DATA
);
reg [ PACK_LENGTH-1:0] REG_TRANSMIT_DATA;
reg [PACK_LENGTH_LOG_2:0] REG_BIT_INDEX;
initial begin
REG_TRANSMIT_DATA = 0;
REG_BIT_INDEX = PACK_LENGTH;
OUT_RECEIVE_DATA = 0;
end
assign MISO=!CS ? (REG_TRANSMIT_DATA[REG_BIT_INDEX]&(REG_BIT_INDEX<PACK_LENGTH)|REG_TRANSMIT_DATA[PACK_LENGTH-1]&(REG_BIT_INDEX==PACK_LENGTH)) : 1'bZ;
always @(negedge CS) REG_TRANSMIT_DATA <= IN_TRANSMIT_DATA;
always @(negedge SCLK or posedge CS or posedge IN_RESET) begin
if (IN_RESET) REG_BIT_INDEX = PACK_LENGTH;
else if (CS) REG_BIT_INDEX = PACK_LENGTH;
else REG_BIT_INDEX = REG_BIT_INDEX - 1;
end
always @(posedge SCLK or posedge IN_RESET) begin
if (IN_RESET) OUT_RECEIVE_DATA = 0;
else if (!CS) OUT_RECEIVE_DATA[REG_BIT_INDEX] = MOSI;
end
endmodule
| 6.69837 |
module SPI_FPGA_TB1_CPOL_EQ_0_CPHA_EQ_0_M_TO_S_EQ_0_S_TO_M_EQ_0 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH),
parameter MASTER_PACK_BIT_SEQUENCE_TRANSMIT = 0, //1-major bit forward;0-junior bit forward;
parameter MASTER_PACK_BIT_SEQUENCE_RECEIVE = 0, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_TRANSMIT = 0, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_RECEIVE = 0 //1-major bit forward;0-junior bit forward;
);
localparam PERIOD_IN_CLOCK_NS = 1000000000 / CLOCK_FREQUENCY;
wire CS, MISO, MOSI, SCLK;
reg [PACK_LENGTH-1:0] IN_MASTER_DATA;
wire [PACK_LENGTH-1:0] OUT_MASTER_RECEIVE_DATA;
reg IN_CLOCK, IN_LAUNCH;
SPI_FPGA_MASTER #(
.BIT_PER_SECOND(BIT_PER_SECOND),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PACK_LENGTH(PACK_LENGTH),
.CPOL(CPOL),
.CPHA(CPHA),
.PACK_BIT_SEQUENCE_TRANSMIT(MASTER_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(MASTER_PACK_BIT_SEQUENCE_RECEIVE)
) MASTER (
IN_CLOCK,
IN_LAUNCH,
IN_MASTER_DATA,
MISO,
MOSI,
CS,
SCLK,
OUT_MASTER_RECEIVE_DATA,
OUT_MASTER_ACTION_DONE
);
reg [PACK_LENGTH-1:0] IN_SLAVE_TRANSMIT_DATA;
wire [PACK_LENGTH-1:0] OUT_SLAVE_RECEIVE_DATA;
reg IN_SLAVE_RESET;
SPI_FPGA_SLAVE #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(SLAVE_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(SLAVE_PACK_BIT_SEQUENCE_RECEIVE)
) SLAVE (
IN_SLAVE_TRANSMIT_DATA,
MOSI,
CS,
SCLK,
IN_SLAVE_RESET,
MISO,
OUT_SLAVE_RECEIVE_DATA
);
initial begin
//initial master
IN_CLOCK = 0;
IN_MASTER_DATA = 0;
IN_LAUNCH = 0;
//initial slave
IN_SLAVE_TRANSMIT_DATA = 0;
IN_SLAVE_RESET = 0;
end
always begin
#(PERIOD_IN_CLOCK_NS / 2);
IN_CLOCK = !IN_CLOCK;
end
event start;
initial begin
#(PERIOD_IN_CLOCK_NS * 10);
IN_SLAVE_RESET = 1;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_RESET = 0;
#(PERIOD_IN_CLOCK_NS * 5);
->start;
end
initial begin
@(start) IN_MASTER_DATA = 8'b11101010;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_TRANSMIT_DATA = 8'b01010011;
#(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH = 1;
@(negedge CS) #(PERIOD_IN_CLOCK_NS * 5);
IN_LAUNCH = 0;
end
endmodule
| 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_0_CPHA_EQ_0_M_TO_S_EQ_0_S_TO_M_EQ_1 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH),
parameter MASTER_PACK_BIT_SEQUENCE_TRANSMIT = 0, //1-major bit forward;0-junior bit forward;
parameter MASTER_PACK_BIT_SEQUENCE_RECEIVE = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_RECEIVE = 0 //1-major bit forward;0-junior bit forward;
);
localparam PERIOD_IN_CLOCK_NS = 1000000000 / CLOCK_FREQUENCY;
wire CS, MISO, MOSI, SCLK;
reg [PACK_LENGTH-1:0] IN_MASTER_DATA;
wire [PACK_LENGTH-1:0] OUT_MASTER_RECEIVE_DATA;
reg IN_CLOCK, IN_LAUNCH;
SPI_FPGA_MASTER #(
.BIT_PER_SECOND(BIT_PER_SECOND),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PACK_LENGTH(PACK_LENGTH),
.CPOL(CPOL),
.CPHA(CPHA),
.PACK_BIT_SEQUENCE_TRANSMIT(MASTER_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(MASTER_PACK_BIT_SEQUENCE_RECEIVE)
) MASTER (
IN_CLOCK,
IN_LAUNCH,
IN_MASTER_DATA,
MISO,
MOSI,
CS,
SCLK,
OUT_MASTER_RECEIVE_DATA,
OUT_MASTER_ACTION_DONE
);
reg [PACK_LENGTH-1:0] IN_SLAVE_TRANSMIT_DATA;
wire [PACK_LENGTH-1:0] OUT_SLAVE_RECEIVE_DATA;
reg IN_SLAVE_RESET;
SPI_FPGA_SLAVE #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(SLAVE_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(SLAVE_PACK_BIT_SEQUENCE_RECEIVE)
) SLAVE (
IN_SLAVE_TRANSMIT_DATA,
MOSI,
CS,
SCLK,
IN_SLAVE_RESET,
MISO,
OUT_SLAVE_RECEIVE_DATA
);
initial begin
//initial master
IN_CLOCK = 0;
IN_MASTER_DATA = 0;
IN_LAUNCH = 0;
//initial slave
IN_SLAVE_TRANSMIT_DATA = 0;
IN_SLAVE_RESET = 0;
end
always begin
#(PERIOD_IN_CLOCK_NS / 2);
IN_CLOCK = !IN_CLOCK;
end
event start;
initial begin
#(PERIOD_IN_CLOCK_NS * 10);
IN_SLAVE_RESET = 1;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_RESET = 0;
#(PERIOD_IN_CLOCK_NS * 5);
->start;
end
initial begin
@(start) IN_MASTER_DATA = 8'b11101010;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_TRANSMIT_DATA = 8'b01010011;
#(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH = 1;
@(negedge CS) #(PERIOD_IN_CLOCK_NS * 5);
IN_LAUNCH = 0;
end
endmodule
| 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_0_CPHA_EQ_0_M_TO_S_EQ_1_S_TO_M_EQ_0 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH),
parameter MASTER_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter MASTER_PACK_BIT_SEQUENCE_RECEIVE = 0, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_TRANSMIT = 0, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_RECEIVE = 1 //1-major bit forward;0-junior bit forward;
);
localparam PERIOD_IN_CLOCK_NS = 1000000000 / CLOCK_FREQUENCY;
wire CS, MISO, MOSI, SCLK;
reg [PACK_LENGTH-1:0] IN_MASTER_DATA;
wire [PACK_LENGTH-1:0] OUT_MASTER_RECEIVE_DATA;
reg IN_CLOCK, IN_LAUNCH;
SPI_FPGA_MASTER #(
.BIT_PER_SECOND(BIT_PER_SECOND),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PACK_LENGTH(PACK_LENGTH),
.CPOL(CPOL),
.CPHA(CPHA),
.PACK_BIT_SEQUENCE_TRANSMIT(MASTER_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(MASTER_PACK_BIT_SEQUENCE_RECEIVE)
) MASTER (
IN_CLOCK,
IN_LAUNCH,
IN_MASTER_DATA,
MISO,
MOSI,
CS,
SCLK,
OUT_MASTER_RECEIVE_DATA,
OUT_MASTER_ACTION_DONE
);
reg [PACK_LENGTH-1:0] IN_SLAVE_TRANSMIT_DATA;
wire [PACK_LENGTH-1:0] OUT_SLAVE_RECEIVE_DATA;
reg IN_SLAVE_RESET;
SPI_FPGA_SLAVE #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(SLAVE_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(SLAVE_PACK_BIT_SEQUENCE_RECEIVE)
) SLAVE (
IN_SLAVE_TRANSMIT_DATA,
MOSI,
CS,
SCLK,
IN_SLAVE_RESET,
MISO,
OUT_SLAVE_RECEIVE_DATA
);
initial begin
//initial master
IN_CLOCK = 0;
IN_MASTER_DATA = 0;
IN_LAUNCH = 0;
//initial slave
IN_SLAVE_TRANSMIT_DATA = 0;
IN_SLAVE_RESET = 0;
end
always begin
#(PERIOD_IN_CLOCK_NS / 2);
IN_CLOCK = !IN_CLOCK;
end
event start;
initial begin
#(PERIOD_IN_CLOCK_NS * 10);
IN_SLAVE_RESET = 1;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_RESET = 0;
#(PERIOD_IN_CLOCK_NS * 5);
->start;
end
initial begin
@(start) IN_MASTER_DATA = 8'b11101010;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_TRANSMIT_DATA = 8'b01010011;
#(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH = 1;
@(negedge CS) #(PERIOD_IN_CLOCK_NS * 5);
IN_LAUNCH = 0;
end
endmodule
| 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_0_CPHA_EQ_0_M_TO_S_EQ_0_S_TO_M_EQ_1 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH),
parameter MASTER_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter MASTER_PACK_BIT_SEQUENCE_RECEIVE = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_RECEIVE = 1 //1-major bit forward;0-junior bit forward;
);
localparam PERIOD_IN_CLOCK_NS = 1000000000 / CLOCK_FREQUENCY;
wire CS, MISO, MOSI, SCLK;
reg [PACK_LENGTH-1:0] IN_MASTER_DATA;
wire [PACK_LENGTH-1:0] OUT_MASTER_RECEIVE_DATA;
reg IN_CLOCK, IN_LAUNCH;
SPI_FPGA_MASTER #(
.BIT_PER_SECOND(BIT_PER_SECOND),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PACK_LENGTH(PACK_LENGTH),
.CPOL(CPOL),
.CPHA(CPHA),
.PACK_BIT_SEQUENCE_TRANSMIT(MASTER_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(MASTER_PACK_BIT_SEQUENCE_RECEIVE)
) MASTER (
IN_CLOCK,
IN_LAUNCH,
IN_MASTER_DATA,
MISO,
MOSI,
CS,
SCLK,
OUT_MASTER_RECEIVE_DATA,
OUT_MASTER_ACTION_DONE
);
reg [PACK_LENGTH-1:0] IN_SLAVE_TRANSMIT_DATA;
wire [PACK_LENGTH-1:0] OUT_SLAVE_RECEIVE_DATA;
reg IN_SLAVE_RESET;
SPI_FPGA_SLAVE #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(SLAVE_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(SLAVE_PACK_BIT_SEQUENCE_RECEIVE)
) SLAVE (
IN_SLAVE_TRANSMIT_DATA,
MOSI,
CS,
SCLK,
IN_SLAVE_RESET,
MISO,
OUT_SLAVE_RECEIVE_DATA
);
initial begin
//initial master
IN_CLOCK = 0;
IN_MASTER_DATA = 0;
IN_LAUNCH = 0;
//initial slave
IN_SLAVE_TRANSMIT_DATA = 0;
IN_SLAVE_RESET = 0;
end
always begin
#(PERIOD_IN_CLOCK_NS / 2);
IN_CLOCK = !IN_CLOCK;
end
event start;
initial begin
#(PERIOD_IN_CLOCK_NS * 10);
IN_SLAVE_RESET = 1;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_RESET = 0;
#(PERIOD_IN_CLOCK_NS * 5);
->start;
end
initial begin
@(start) IN_MASTER_DATA = 8'b11101010;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_TRANSMIT_DATA = 8'b01010011;
#(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH = 1;
@(negedge CS) #(PERIOD_IN_CLOCK_NS * 5);
IN_LAUNCH = 0;
end
endmodule
| 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_1_CPHA_EQ_0_M_TO_S_EQ_0_S_TO_M_EQ_0 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b1,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH),
parameter MASTER_PACK_BIT_SEQUENCE_TRANSMIT = 0, //1-major bit forward;0-junior bit forward;
parameter MASTER_PACK_BIT_SEQUENCE_RECEIVE = 0, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_TRANSMIT = 0, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_RECEIVE = 0 //1-major bit forward;0-junior bit forward;
);
localparam PERIOD_IN_CLOCK_NS = 1000000000 / CLOCK_FREQUENCY;
wire CS, MISO, MOSI, SCLK;
reg [PACK_LENGTH-1:0] IN_MASTER_DATA;
wire [PACK_LENGTH-1:0] OUT_MASTER_RECEIVE_DATA;
reg IN_CLOCK, IN_LAUNCH;
SPI_FPGA_MASTER #(
.BIT_PER_SECOND(BIT_PER_SECOND),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PACK_LENGTH(PACK_LENGTH),
.CPOL(CPOL),
.CPHA(CPHA),
.PACK_BIT_SEQUENCE_TRANSMIT(MASTER_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(MASTER_PACK_BIT_SEQUENCE_RECEIVE)
) MASTER (
IN_CLOCK,
IN_LAUNCH,
IN_MASTER_DATA,
MISO,
MOSI,
CS,
SCLK,
OUT_MASTER_RECEIVE_DATA,
OUT_MASTER_ACTION_DONE
);
reg [PACK_LENGTH-1:0] IN_SLAVE_TRANSMIT_DATA;
wire [PACK_LENGTH-1:0] OUT_SLAVE_RECEIVE_DATA;
reg IN_SLAVE_RESET;
SPI_FPGA_SLAVE #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(SLAVE_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(SLAVE_PACK_BIT_SEQUENCE_RECEIVE)
) SLAVE (
IN_SLAVE_TRANSMIT_DATA,
MOSI,
CS,
SCLK,
IN_SLAVE_RESET,
MISO,
OUT_SLAVE_RECEIVE_DATA
);
initial begin
//initial master
IN_CLOCK = 0;
IN_MASTER_DATA = 0;
IN_LAUNCH = 0;
//initial slave
IN_SLAVE_TRANSMIT_DATA = 0;
IN_SLAVE_RESET = 0;
end
always begin
#(PERIOD_IN_CLOCK_NS / 2);
IN_CLOCK = !IN_CLOCK;
end
event start;
initial begin
#(PERIOD_IN_CLOCK_NS * 10);
IN_SLAVE_RESET = 1;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_RESET = 0;
#(PERIOD_IN_CLOCK_NS * 5);
->start;
end
initial begin
@(start) IN_MASTER_DATA = 8'b11101010;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_TRANSMIT_DATA = 8'b01010011;
#(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH = 1;
@(negedge CS) #(PERIOD_IN_CLOCK_NS * 5);
IN_LAUNCH = 0;
end
endmodule
| 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_1_CPHA_EQ_0_M_TO_S_EQ_0_S_TO_M_EQ_1 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b1,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH),
parameter MASTER_PACK_BIT_SEQUENCE_TRANSMIT = 0, //1-major bit forward;0-junior bit forward;
parameter MASTER_PACK_BIT_SEQUENCE_RECEIVE = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_RECEIVE = 0 //1-major bit forward;0-junior bit forward;
);
localparam PERIOD_IN_CLOCK_NS = 1000000000 / CLOCK_FREQUENCY;
wire CS, MISO, MOSI, SCLK;
reg [PACK_LENGTH-1:0] IN_MASTER_DATA;
wire [PACK_LENGTH-1:0] OUT_MASTER_RECEIVE_DATA;
reg IN_CLOCK, IN_LAUNCH;
SPI_FPGA_MASTER #(
.BIT_PER_SECOND(BIT_PER_SECOND),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PACK_LENGTH(PACK_LENGTH),
.CPOL(CPOL),
.CPHA(CPHA),
.PACK_BIT_SEQUENCE_TRANSMIT(MASTER_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(MASTER_PACK_BIT_SEQUENCE_RECEIVE)
) MASTER (
IN_CLOCK,
IN_LAUNCH,
IN_MASTER_DATA,
MISO,
MOSI,
CS,
SCLK,
OUT_MASTER_RECEIVE_DATA,
OUT_MASTER_ACTION_DONE
);
reg [PACK_LENGTH-1:0] IN_SLAVE_TRANSMIT_DATA;
wire [PACK_LENGTH-1:0] OUT_SLAVE_RECEIVE_DATA;
reg IN_SLAVE_RESET;
SPI_FPGA_SLAVE #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(SLAVE_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(SLAVE_PACK_BIT_SEQUENCE_RECEIVE)
) SLAVE (
IN_SLAVE_TRANSMIT_DATA,
MOSI,
CS,
SCLK,
IN_SLAVE_RESET,
MISO,
OUT_SLAVE_RECEIVE_DATA
);
initial begin
//initial master
IN_CLOCK = 0;
IN_MASTER_DATA = 0;
IN_LAUNCH = 0;
//initial slave
IN_SLAVE_TRANSMIT_DATA = 0;
IN_SLAVE_RESET = 0;
end
always begin
#(PERIOD_IN_CLOCK_NS / 2);
IN_CLOCK = !IN_CLOCK;
end
event start;
initial begin
#(PERIOD_IN_CLOCK_NS * 10);
IN_SLAVE_RESET = 1;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_RESET = 0;
#(PERIOD_IN_CLOCK_NS * 5);
->start;
end
initial begin
@(start) IN_MASTER_DATA = 8'b11101010;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_TRANSMIT_DATA = 8'b01010011;
#(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH = 1;
@(negedge CS) #(PERIOD_IN_CLOCK_NS * 5);
IN_LAUNCH = 0;
end
endmodule
| 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_1_CPHA_EQ_0_M_TO_S_EQ_1_S_TO_M_EQ_0 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b1,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH),
parameter MASTER_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter MASTER_PACK_BIT_SEQUENCE_RECEIVE = 0, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_TRANSMIT = 0, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_RECEIVE = 1 //1-major bit forward;0-junior bit forward;
);
localparam PERIOD_IN_CLOCK_NS = 1000000000 / CLOCK_FREQUENCY;
wire CS, MISO, MOSI, SCLK;
reg [PACK_LENGTH-1:0] IN_MASTER_DATA;
wire [PACK_LENGTH-1:0] OUT_MASTER_RECEIVE_DATA;
reg IN_CLOCK, IN_LAUNCH;
SPI_FPGA_MASTER #(
.BIT_PER_SECOND(BIT_PER_SECOND),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PACK_LENGTH(PACK_LENGTH),
.CPOL(CPOL),
.CPHA(CPHA),
.PACK_BIT_SEQUENCE_TRANSMIT(MASTER_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(MASTER_PACK_BIT_SEQUENCE_RECEIVE)
) MASTER (
IN_CLOCK,
IN_LAUNCH,
IN_MASTER_DATA,
MISO,
MOSI,
CS,
SCLK,
OUT_MASTER_RECEIVE_DATA,
OUT_MASTER_ACTION_DONE
);
reg [PACK_LENGTH-1:0] IN_SLAVE_TRANSMIT_DATA;
wire [PACK_LENGTH-1:0] OUT_SLAVE_RECEIVE_DATA;
reg IN_SLAVE_RESET;
SPI_FPGA_SLAVE #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(SLAVE_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(SLAVE_PACK_BIT_SEQUENCE_RECEIVE)
) SLAVE (
IN_SLAVE_TRANSMIT_DATA,
MOSI,
CS,
SCLK,
IN_SLAVE_RESET,
MISO,
OUT_SLAVE_RECEIVE_DATA
);
initial begin
//initial master
IN_CLOCK = 0;
IN_MASTER_DATA = 0;
IN_LAUNCH = 0;
//initial slave
IN_SLAVE_TRANSMIT_DATA = 0;
IN_SLAVE_RESET = 0;
end
always begin
#(PERIOD_IN_CLOCK_NS / 2);
IN_CLOCK = !IN_CLOCK;
end
event start;
initial begin
#(PERIOD_IN_CLOCK_NS * 10);
IN_SLAVE_RESET = 1;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_RESET = 0;
#(PERIOD_IN_CLOCK_NS * 5);
->start;
end
initial begin
@(start) IN_MASTER_DATA = 8'b11101010;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_TRANSMIT_DATA = 8'b01010011;
#(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH = 1;
@(negedge CS) #(PERIOD_IN_CLOCK_NS * 5);
IN_LAUNCH = 0;
end
endmodule
| 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_1_CPHA_EQ_0_M_TO_S_EQ_1_S_TO_M_EQ_1 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b1,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH),
parameter MASTER_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter MASTER_PACK_BIT_SEQUENCE_RECEIVE = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_RECEIVE = 1 //1-major bit forward;0-junior bit forward;
);
localparam PERIOD_IN_CLOCK_NS = 1000000000 / CLOCK_FREQUENCY;
wire CS, MISO, MOSI, SCLK;
reg [PACK_LENGTH-1:0] IN_MASTER_DATA;
wire [PACK_LENGTH-1:0] OUT_MASTER_RECEIVE_DATA;
reg IN_CLOCK, IN_LAUNCH;
SPI_FPGA_MASTER #(
.BIT_PER_SECOND(BIT_PER_SECOND),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PACK_LENGTH(PACK_LENGTH),
.CPOL(CPOL),
.CPHA(CPHA),
.PACK_BIT_SEQUENCE_TRANSMIT(MASTER_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(MASTER_PACK_BIT_SEQUENCE_RECEIVE)
) MASTER (
IN_CLOCK,
IN_LAUNCH,
IN_MASTER_DATA,
MISO,
MOSI,
CS,
SCLK,
OUT_MASTER_RECEIVE_DATA,
OUT_MASTER_ACTION_DONE
);
reg [PACK_LENGTH-1:0] IN_SLAVE_TRANSMIT_DATA;
wire [PACK_LENGTH-1:0] OUT_SLAVE_RECEIVE_DATA;
reg IN_SLAVE_RESET;
SPI_FPGA_SLAVE #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(SLAVE_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(SLAVE_PACK_BIT_SEQUENCE_RECEIVE)
) SLAVE (
IN_SLAVE_TRANSMIT_DATA,
MOSI,
CS,
SCLK,
IN_SLAVE_RESET,
MISO,
OUT_SLAVE_RECEIVE_DATA
);
initial begin
//initial master
IN_CLOCK = 0;
IN_MASTER_DATA = 0;
IN_LAUNCH = 0;
//initial slave
IN_SLAVE_TRANSMIT_DATA = 0;
IN_SLAVE_RESET = 0;
end
always begin
#(PERIOD_IN_CLOCK_NS / 2);
IN_CLOCK = !IN_CLOCK;
end
event start;
initial begin
#(PERIOD_IN_CLOCK_NS * 10);
IN_SLAVE_RESET = 1;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_RESET = 0;
#(PERIOD_IN_CLOCK_NS * 5);
->start;
end
initial begin
@(start) IN_MASTER_DATA = 8'b11101010;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_TRANSMIT_DATA = 8'b01010011;
#(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH = 1;
@(negedge CS) #(PERIOD_IN_CLOCK_NS * 5);
IN_LAUNCH = 0;
end
endmodule
| 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_0_CPHA_EQ_1_M_TO_S_EQ_0_S_TO_M_EQ_0 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b1,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH),
parameter MASTER_PACK_BIT_SEQUENCE_TRANSMIT = 0, //1-major bit forward;0-junior bit forward;
parameter MASTER_PACK_BIT_SEQUENCE_RECEIVE = 0, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_TRANSMIT = 0, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_RECEIVE = 0 //1-major bit forward;0-junior bit forward;
);
localparam PERIOD_IN_CLOCK_NS = 1000000000 / CLOCK_FREQUENCY;
wire CS, MISO, MOSI, SCLK;
reg [PACK_LENGTH-1:0] IN_MASTER_DATA;
wire [PACK_LENGTH-1:0] OUT_MASTER_RECEIVE_DATA;
reg IN_CLOCK, IN_LAUNCH;
SPI_FPGA_MASTER #(
.BIT_PER_SECOND(BIT_PER_SECOND),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PACK_LENGTH(PACK_LENGTH),
.CPOL(CPOL),
.CPHA(CPHA),
.PACK_BIT_SEQUENCE_TRANSMIT(MASTER_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(MASTER_PACK_BIT_SEQUENCE_RECEIVE)
) MASTER (
IN_CLOCK,
IN_LAUNCH,
IN_MASTER_DATA,
MISO,
MOSI,
CS,
SCLK,
OUT_MASTER_RECEIVE_DATA,
OUT_MASTER_ACTION_DONE
);
reg [PACK_LENGTH-1:0] IN_SLAVE_TRANSMIT_DATA;
wire [PACK_LENGTH-1:0] OUT_SLAVE_RECEIVE_DATA;
reg IN_SLAVE_RESET;
SPI_FPGA_SLAVE #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(SLAVE_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(SLAVE_PACK_BIT_SEQUENCE_RECEIVE)
) SLAVE (
IN_SLAVE_TRANSMIT_DATA,
MOSI,
CS,
SCLK,
IN_SLAVE_RESET,
MISO,
OUT_SLAVE_RECEIVE_DATA
);
initial begin
//initial master
IN_CLOCK = 0;
IN_MASTER_DATA = 0;
IN_LAUNCH = 0;
//initial slave
IN_SLAVE_TRANSMIT_DATA = 0;
IN_SLAVE_RESET = 0;
end
always begin
#(PERIOD_IN_CLOCK_NS / 2);
IN_CLOCK = !IN_CLOCK;
end
event start;
initial begin
#(PERIOD_IN_CLOCK_NS * 10);
IN_SLAVE_RESET = 1;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_RESET = 0;
#(PERIOD_IN_CLOCK_NS * 5);
->start;
end
initial begin
@(start) IN_MASTER_DATA = 8'b11101010;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_TRANSMIT_DATA = 8'b01010011;
#(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH = 1;
@(negedge CS) #(PERIOD_IN_CLOCK_NS * 5);
IN_LAUNCH = 0;
end
endmodule
| 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_0_CPHA_EQ_1_M_TO_S_EQ_0_S_TO_M_EQ_1 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b1,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH),
parameter MASTER_PACK_BIT_SEQUENCE_TRANSMIT = 0, //1-major bit forward;0-junior bit forward;
parameter MASTER_PACK_BIT_SEQUENCE_RECEIVE = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_RECEIVE = 0 //1-major bit forward;0-junior bit forward;
);
localparam PERIOD_IN_CLOCK_NS = 1000000000 / CLOCK_FREQUENCY;
wire CS, MISO, MOSI, SCLK;
reg [PACK_LENGTH-1:0] IN_MASTER_DATA;
wire [PACK_LENGTH-1:0] OUT_MASTER_RECEIVE_DATA;
reg IN_CLOCK, IN_LAUNCH;
SPI_FPGA_MASTER #(
.BIT_PER_SECOND(BIT_PER_SECOND),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PACK_LENGTH(PACK_LENGTH),
.CPOL(CPOL),
.CPHA(CPHA),
.PACK_BIT_SEQUENCE_TRANSMIT(MASTER_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(MASTER_PACK_BIT_SEQUENCE_RECEIVE)
) MASTER (
IN_CLOCK,
IN_LAUNCH,
IN_MASTER_DATA,
MISO,
MOSI,
CS,
SCLK,
OUT_MASTER_RECEIVE_DATA,
OUT_MASTER_ACTION_DONE
);
reg [PACK_LENGTH-1:0] IN_SLAVE_TRANSMIT_DATA;
wire [PACK_LENGTH-1:0] OUT_SLAVE_RECEIVE_DATA;
reg IN_SLAVE_RESET;
SPI_FPGA_SLAVE #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(SLAVE_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(SLAVE_PACK_BIT_SEQUENCE_RECEIVE)
) SLAVE (
IN_SLAVE_TRANSMIT_DATA,
MOSI,
CS,
SCLK,
IN_SLAVE_RESET,
MISO,
OUT_SLAVE_RECEIVE_DATA
);
initial begin
//initial master
IN_CLOCK = 0;
IN_MASTER_DATA = 0;
IN_LAUNCH = 0;
//initial slave
IN_SLAVE_TRANSMIT_DATA = 0;
IN_SLAVE_RESET = 0;
end
always begin
#(PERIOD_IN_CLOCK_NS / 2);
IN_CLOCK = !IN_CLOCK;
end
event start;
initial begin
#(PERIOD_IN_CLOCK_NS * 10);
IN_SLAVE_RESET = 1;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_RESET = 0;
#(PERIOD_IN_CLOCK_NS * 5);
->start;
end
initial begin
@(start) IN_MASTER_DATA = 8'b11101010;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_TRANSMIT_DATA = 8'b01010011;
#(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH = 1;
@(negedge CS) #(PERIOD_IN_CLOCK_NS * 5);
IN_LAUNCH = 0;
end
endmodule
| 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_0_CPHA_EQ_1_M_TO_S_EQ_1_S_TO_M_EQ_0 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b1,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH),
parameter MASTER_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter MASTER_PACK_BIT_SEQUENCE_RECEIVE = 0, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_TRANSMIT = 0, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_RECEIVE = 1 //1-major bit forward;0-junior bit forward;
);
localparam PERIOD_IN_CLOCK_NS = 1000000000 / CLOCK_FREQUENCY;
wire CS, MISO, MOSI, SCLK;
reg [PACK_LENGTH-1:0] IN_MASTER_DATA;
wire [PACK_LENGTH-1:0] OUT_MASTER_RECEIVE_DATA;
reg IN_CLOCK, IN_LAUNCH;
SPI_FPGA_MASTER #(
.BIT_PER_SECOND(BIT_PER_SECOND),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PACK_LENGTH(PACK_LENGTH),
.CPOL(CPOL),
.CPHA(CPHA),
.PACK_BIT_SEQUENCE_TRANSMIT(MASTER_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(MASTER_PACK_BIT_SEQUENCE_RECEIVE)
) MASTER (
IN_CLOCK,
IN_LAUNCH,
IN_MASTER_DATA,
MISO,
MOSI,
CS,
SCLK,
OUT_MASTER_RECEIVE_DATA,
OUT_MASTER_ACTION_DONE
);
reg [PACK_LENGTH-1:0] IN_SLAVE_TRANSMIT_DATA;
wire [PACK_LENGTH-1:0] OUT_SLAVE_RECEIVE_DATA;
reg IN_SLAVE_RESET;
SPI_FPGA_SLAVE #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(SLAVE_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(SLAVE_PACK_BIT_SEQUENCE_RECEIVE)
) SLAVE (
IN_SLAVE_TRANSMIT_DATA,
MOSI,
CS,
SCLK,
IN_SLAVE_RESET,
MISO,
OUT_SLAVE_RECEIVE_DATA
);
initial begin
//initial master
IN_CLOCK = 0;
IN_MASTER_DATA = 0;
IN_LAUNCH = 0;
//initial slave
IN_SLAVE_TRANSMIT_DATA = 0;
IN_SLAVE_RESET = 0;
end
always begin
#(PERIOD_IN_CLOCK_NS / 2);
IN_CLOCK = !IN_CLOCK;
end
event start;
initial begin
#(PERIOD_IN_CLOCK_NS * 10);
IN_SLAVE_RESET = 1;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_RESET = 0;
#(PERIOD_IN_CLOCK_NS * 5);
->start;
end
initial begin
@(start) IN_MASTER_DATA = 8'b11101010;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_TRANSMIT_DATA = 8'b01010011;
#(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH = 1;
@(negedge CS) #(PERIOD_IN_CLOCK_NS * 5);
IN_LAUNCH = 0;
end
endmodule
| 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_0_CPHA_EQ_1_M_TO_S_EQ_1_S_TO_M_EQ_1 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b1,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH),
parameter MASTER_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter MASTER_PACK_BIT_SEQUENCE_RECEIVE = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_RECEIVE = 1 //1-major bit forward;0-junior bit forward;
);
localparam PERIOD_IN_CLOCK_NS = 1000000000 / CLOCK_FREQUENCY;
wire CS, MISO, MOSI, SCLK;
reg [PACK_LENGTH-1:0] IN_MASTER_DATA;
wire [PACK_LENGTH-1:0] OUT_MASTER_RECEIVE_DATA;
reg IN_CLOCK, IN_LAUNCH;
SPI_FPGA_MASTER #(
.BIT_PER_SECOND(BIT_PER_SECOND),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PACK_LENGTH(PACK_LENGTH),
.CPOL(CPOL),
.CPHA(CPHA),
.PACK_BIT_SEQUENCE_TRANSMIT(MASTER_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(MASTER_PACK_BIT_SEQUENCE_RECEIVE)
) MASTER (
IN_CLOCK,
IN_LAUNCH,
IN_MASTER_DATA,
MISO,
MOSI,
CS,
SCLK,
OUT_MASTER_RECEIVE_DATA,
OUT_MASTER_ACTION_DONE
);
reg [PACK_LENGTH-1:0] IN_SLAVE_TRANSMIT_DATA;
wire [PACK_LENGTH-1:0] OUT_SLAVE_RECEIVE_DATA;
reg IN_SLAVE_RESET;
SPI_FPGA_SLAVE #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(SLAVE_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(SLAVE_PACK_BIT_SEQUENCE_RECEIVE)
) SLAVE (
IN_SLAVE_TRANSMIT_DATA,
MOSI,
CS,
SCLK,
IN_SLAVE_RESET,
MISO,
OUT_SLAVE_RECEIVE_DATA
);
initial begin
//initial master
IN_CLOCK = 0;
IN_MASTER_DATA = 0;
IN_LAUNCH = 0;
//initial slave
IN_SLAVE_TRANSMIT_DATA = 0;
IN_SLAVE_RESET = 0;
end
always begin
#(PERIOD_IN_CLOCK_NS / 2);
IN_CLOCK = !IN_CLOCK;
end
event start;
initial begin
#(PERIOD_IN_CLOCK_NS * 10);
IN_SLAVE_RESET = 1;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_RESET = 0;
#(PERIOD_IN_CLOCK_NS * 5);
->start;
end
initial begin
@(start) IN_MASTER_DATA = 8'b11101010;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_TRANSMIT_DATA = 8'b01010011;
#(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH = 1;
@(negedge CS) #(PERIOD_IN_CLOCK_NS * 5);
IN_LAUNCH = 0;
end
endmodule
| 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_1_CPHA_EQ_1_M_TO_S_EQ_0_S_TO_M_EQ_0 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b1,
parameter CPHA = 1'b1,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH),
parameter MASTER_PACK_BIT_SEQUENCE_TRANSMIT = 0, //1-major bit forward;0-junior bit forward;
parameter MASTER_PACK_BIT_SEQUENCE_RECEIVE = 0, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_TRANSMIT = 0, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_RECEIVE = 0 //1-major bit forward;0-junior bit forward;
);
localparam PERIOD_IN_CLOCK_NS = 1000000000 / CLOCK_FREQUENCY;
wire CS, MISO, MOSI, SCLK;
reg [PACK_LENGTH-1:0] IN_MASTER_DATA;
wire [PACK_LENGTH-1:0] OUT_MASTER_RECEIVE_DATA;
reg IN_CLOCK, IN_LAUNCH;
SPI_FPGA_MASTER #(
.BIT_PER_SECOND(BIT_PER_SECOND),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PACK_LENGTH(PACK_LENGTH),
.CPOL(CPOL),
.CPHA(CPHA),
.PACK_BIT_SEQUENCE_TRANSMIT(MASTER_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(MASTER_PACK_BIT_SEQUENCE_RECEIVE)
) MASTER (
IN_CLOCK,
IN_LAUNCH,
IN_MASTER_DATA,
MISO,
MOSI,
CS,
SCLK,
OUT_MASTER_RECEIVE_DATA,
OUT_MASTER_ACTION_DONE
);
reg [PACK_LENGTH-1:0] IN_SLAVE_TRANSMIT_DATA;
wire [PACK_LENGTH-1:0] OUT_SLAVE_RECEIVE_DATA;
reg IN_SLAVE_RESET;
SPI_FPGA_SLAVE #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(SLAVE_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(SLAVE_PACK_BIT_SEQUENCE_RECEIVE)
) SLAVE (
IN_SLAVE_TRANSMIT_DATA,
MOSI,
CS,
SCLK,
IN_SLAVE_RESET,
MISO,
OUT_SLAVE_RECEIVE_DATA
);
initial begin
//initial master
IN_CLOCK = 0;
IN_MASTER_DATA = 0;
IN_LAUNCH = 0;
//initial slave
IN_SLAVE_TRANSMIT_DATA = 0;
IN_SLAVE_RESET = 0;
end
always begin
#(PERIOD_IN_CLOCK_NS / 2);
IN_CLOCK = !IN_CLOCK;
end
event start;
initial begin
#(PERIOD_IN_CLOCK_NS * 10);
IN_SLAVE_RESET = 1;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_RESET = 0;
#(PERIOD_IN_CLOCK_NS * 5);
->start;
end
initial begin
@(start) IN_MASTER_DATA = 8'b11101010;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_TRANSMIT_DATA = 8'b01010011;
#(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH = 1;
@(negedge CS) #(PERIOD_IN_CLOCK_NS * 5);
IN_LAUNCH = 0;
end
endmodule
| 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_1_CPHA_EQ_1_M_TO_S_EQ_0_S_TO_M_EQ_1 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b1,
parameter CPHA = 1'b1,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH),
parameter MASTER_PACK_BIT_SEQUENCE_TRANSMIT = 0, //1-major bit forward;0-junior bit forward;
parameter MASTER_PACK_BIT_SEQUENCE_RECEIVE = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_RECEIVE = 0 //1-major bit forward;0-junior bit forward;
);
localparam PERIOD_IN_CLOCK_NS = 1000000000 / CLOCK_FREQUENCY;
wire CS, MISO, MOSI, SCLK;
reg [PACK_LENGTH-1:0] IN_MASTER_DATA;
wire [PACK_LENGTH-1:0] OUT_MASTER_RECEIVE_DATA;
reg IN_CLOCK, IN_LAUNCH;
SPI_FPGA_MASTER #(
.BIT_PER_SECOND(BIT_PER_SECOND),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PACK_LENGTH(PACK_LENGTH),
.CPOL(CPOL),
.CPHA(CPHA),
.PACK_BIT_SEQUENCE_TRANSMIT(MASTER_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(MASTER_PACK_BIT_SEQUENCE_RECEIVE)
) MASTER (
IN_CLOCK,
IN_LAUNCH,
IN_MASTER_DATA,
MISO,
MOSI,
CS,
SCLK,
OUT_MASTER_RECEIVE_DATA,
OUT_MASTER_ACTION_DONE
);
reg [PACK_LENGTH-1:0] IN_SLAVE_TRANSMIT_DATA;
wire [PACK_LENGTH-1:0] OUT_SLAVE_RECEIVE_DATA;
reg IN_SLAVE_RESET;
SPI_FPGA_SLAVE #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(SLAVE_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(SLAVE_PACK_BIT_SEQUENCE_RECEIVE)
) SLAVE (
IN_SLAVE_TRANSMIT_DATA,
MOSI,
CS,
SCLK,
IN_SLAVE_RESET,
MISO,
OUT_SLAVE_RECEIVE_DATA
);
initial begin
//initial master
IN_CLOCK = 0;
IN_MASTER_DATA = 0;
IN_LAUNCH = 0;
//initial slave
IN_SLAVE_TRANSMIT_DATA = 0;
IN_SLAVE_RESET = 0;
end
always begin
#(PERIOD_IN_CLOCK_NS / 2);
IN_CLOCK = !IN_CLOCK;
end
event start;
initial begin
#(PERIOD_IN_CLOCK_NS * 10);
IN_SLAVE_RESET = 1;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_RESET = 0;
#(PERIOD_IN_CLOCK_NS * 5);
->start;
end
initial begin
@(start) IN_MASTER_DATA = 8'b11101010;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_TRANSMIT_DATA = 8'b01010011;
#(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH = 1;
@(negedge CS) #(PERIOD_IN_CLOCK_NS * 5);
IN_LAUNCH = 0;
end
endmodule
| 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_1_CPHA_EQ_1_M_TO_S_EQ_1_S_TO_M_EQ_0 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b1,
parameter CPHA = 1'b1,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH),
parameter MASTER_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter MASTER_PACK_BIT_SEQUENCE_RECEIVE = 0, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_TRANSMIT = 0, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_RECEIVE = 1 //1-major bit forward;0-junior bit forward;
);
localparam PERIOD_IN_CLOCK_NS = 1000000000 / CLOCK_FREQUENCY;
wire CS, MISO, MOSI, SCLK;
reg [PACK_LENGTH-1:0] IN_MASTER_DATA;
wire [PACK_LENGTH-1:0] OUT_MASTER_RECEIVE_DATA;
reg IN_CLOCK, IN_LAUNCH;
SPI_FPGA_MASTER #(
.BIT_PER_SECOND(BIT_PER_SECOND),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PACK_LENGTH(PACK_LENGTH),
.CPOL(CPOL),
.CPHA(CPHA),
.PACK_BIT_SEQUENCE_TRANSMIT(MASTER_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(MASTER_PACK_BIT_SEQUENCE_RECEIVE)
) MASTER (
IN_CLOCK,
IN_LAUNCH,
IN_MASTER_DATA,
MISO,
MOSI,
CS,
SCLK,
OUT_MASTER_RECEIVE_DATA,
OUT_MASTER_ACTION_DONE
);
reg [PACK_LENGTH-1:0] IN_SLAVE_TRANSMIT_DATA;
wire [PACK_LENGTH-1:0] OUT_SLAVE_RECEIVE_DATA;
reg IN_SLAVE_RESET;
SPI_FPGA_SLAVE #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(SLAVE_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(SLAVE_PACK_BIT_SEQUENCE_RECEIVE)
) SLAVE (
IN_SLAVE_TRANSMIT_DATA,
MOSI,
CS,
SCLK,
IN_SLAVE_RESET,
MISO,
OUT_SLAVE_RECEIVE_DATA
);
initial begin
//initial master
IN_CLOCK = 0;
IN_MASTER_DATA = 0;
IN_LAUNCH = 0;
//initial slave
IN_SLAVE_TRANSMIT_DATA = 0;
IN_SLAVE_RESET = 0;
end
always begin
#(PERIOD_IN_CLOCK_NS / 2);
IN_CLOCK = !IN_CLOCK;
end
event start;
initial begin
#(PERIOD_IN_CLOCK_NS * 10);
IN_SLAVE_RESET = 1;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_RESET = 0;
#(PERIOD_IN_CLOCK_NS * 5);
->start;
end
initial begin
@(start) IN_MASTER_DATA = 8'b11101010;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_TRANSMIT_DATA = 8'b01010011;
#(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH = 1;
@(negedge CS) #(PERIOD_IN_CLOCK_NS * 5);
IN_LAUNCH = 0;
end
endmodule
| 7.661703 |
module SPI_FPGA_TB1_CPOL_EQ_1_CPHA_EQ_1_M_TO_S_EQ_1_S_TO_M_EQ_1 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b1,
parameter CPHA = 1'b1,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH),
parameter MASTER_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter MASTER_PACK_BIT_SEQUENCE_RECEIVE = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_RECEIVE = 1 //1-major bit forward;0-junior bit forward;
);
localparam PERIOD_IN_CLOCK_NS = 1000000000 / CLOCK_FREQUENCY;
wire CS, MISO, MOSI, SCLK;
reg [PACK_LENGTH-1:0] IN_MASTER_DATA;
wire [PACK_LENGTH-1:0] OUT_MASTER_RECEIVE_DATA;
reg IN_CLOCK, IN_LAUNCH;
SPI_FPGA_MASTER #(
.BIT_PER_SECOND(BIT_PER_SECOND),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PACK_LENGTH(PACK_LENGTH),
.CPOL(CPOL),
.CPHA(CPHA),
.PACK_BIT_SEQUENCE_TRANSMIT(MASTER_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(MASTER_PACK_BIT_SEQUENCE_RECEIVE)
) MASTER (
IN_CLOCK,
IN_LAUNCH,
IN_MASTER_DATA,
MISO,
MOSI,
CS,
SCLK,
OUT_MASTER_RECEIVE_DATA,
OUT_MASTER_ACTION_DONE
);
reg [PACK_LENGTH-1:0] IN_SLAVE_TRANSMIT_DATA;
wire [PACK_LENGTH-1:0] OUT_SLAVE_RECEIVE_DATA;
reg IN_SLAVE_RESET;
SPI_FPGA_SLAVE #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(SLAVE_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(SLAVE_PACK_BIT_SEQUENCE_RECEIVE)
) SLAVE (
IN_SLAVE_TRANSMIT_DATA,
MOSI,
CS,
SCLK,
IN_SLAVE_RESET,
MISO,
OUT_SLAVE_RECEIVE_DATA
);
initial begin
//initial master
IN_CLOCK = 0;
IN_MASTER_DATA = 0;
IN_LAUNCH = 0;
//initial slave
IN_SLAVE_TRANSMIT_DATA = 0;
IN_SLAVE_RESET = 0;
end
always begin
#(PERIOD_IN_CLOCK_NS / 2);
IN_CLOCK = !IN_CLOCK;
end
event start;
initial begin
#(PERIOD_IN_CLOCK_NS * 10);
IN_SLAVE_RESET = 1;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_RESET = 0;
#(PERIOD_IN_CLOCK_NS * 5);
->start;
end
initial begin
@(start) IN_MASTER_DATA = 8'b11101010;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_TRANSMIT_DATA = 8'b01010011;
#(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH = 1;
@(negedge CS) #(PERIOD_IN_CLOCK_NS * 5);
IN_LAUNCH = 0;
end
endmodule
| 7.661703 |
module SPI_FPGA_TB1 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH),
parameter MASTER_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter MASTER_PACK_BIT_SEQUENCE_RECEIVE = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_RECEIVE = 1 //1-major bit forward;0-junior bit forward;
);
localparam PERIOD_IN_CLOCK_NS = 1000000000 / CLOCK_FREQUENCY;
wire CS, MISO, MOSI, SCLK;
reg [PACK_LENGTH-1:0] IN_MASTER_DATA;
wire [PACK_LENGTH-1:0] OUT_MASTER_RECEIVE_DATA;
reg IN_CLOCK, IN_LAUNCH;
SPI_FPGA_MASTER #(
.BIT_PER_SECOND(BIT_PER_SECOND),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PACK_LENGTH(PACK_LENGTH),
.CPOL(CPOL),
.CPHA(CPHA),
.PACK_BIT_SEQUENCE_TRANSMIT(MASTER_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(MASTER_PACK_BIT_SEQUENCE_RECEIVE)
) MASTER (
IN_CLOCK,
IN_LAUNCH,
IN_MASTER_DATA,
MISO,
MOSI,
CS,
SCLK,
OUT_MASTER_RECEIVE_DATA,
OUT_MASTER_ACTION_DONE
);
reg [PACK_LENGTH-1:0] IN_SLAVE_TRANSMIT_DATA;
wire [PACK_LENGTH-1:0] OUT_SLAVE_RECEIVE_DATA;
reg IN_SLAVE_RESET;
SPI_FPGA_SLAVE #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(SLAVE_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(SLAVE_PACK_BIT_SEQUENCE_RECEIVE)
) SLAVE (
IN_SLAVE_TRANSMIT_DATA,
MOSI,
CS,
SCLK,
IN_SLAVE_RESET,
MISO,
OUT_SLAVE_RECEIVE_DATA
);
initial begin
//initial master
IN_CLOCK = 0;
IN_MASTER_DATA = 0;
IN_LAUNCH = 0;
//initial slave
IN_SLAVE_TRANSMIT_DATA = 0;
IN_SLAVE_RESET = 0;
end
always begin
#(PERIOD_IN_CLOCK_NS / 2);
IN_CLOCK = !IN_CLOCK;
end
initial begin
#(PERIOD_IN_CLOCK_NS * 10);
IN_MASTER_DATA = 8'b11101010;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_TRANSMIT_DATA = 8'b01010011;
#(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH = 1;
#(PERIOD_IN_CLOCK_NS * 5);
IN_LAUNCH = 0;
end
endmodule
| 7.280926 |
module SPI_FPGA_TB2 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH),
parameter MASTER_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter MASTER_PACK_BIT_SEQUENCE_RECEIVE = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_RECEIVE = 1 //1-major bit forward;0-junior bit forward;
);
localparam PERIOD_IN_CLOCK_NS = 1000000000 / CLOCK_FREQUENCY;
wire CS, MISO, MOSI, SCLK;
reg [PACK_LENGTH-1:0] IN_MASTER_DATA;
wire [PACK_LENGTH-1:0] OUT_MASTER_RECEIVE_DATA;
reg IN_CLOCK, IN_LAUNCH;
SPI_FPGA_MASTER #(
.BIT_PER_SECOND(BIT_PER_SECOND),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PACK_LENGTH(PACK_LENGTH),
.CPOL(CPOL),
.CPHA(CPHA),
.PACK_BIT_SEQUENCE_TRANSMIT(MASTER_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(MASTER_PACK_BIT_SEQUENCE_RECEIVE)
) MASTER (
IN_CLOCK,
IN_LAUNCH,
IN_MASTER_DATA,
MISO,
MOSI,
CS,
SCLK,
OUT_MASTER_RECEIVE_DATA,
OUT_MASTER_ACTION_DONE
);
initial begin
//initial master
IN_CLOCK = 0;
IN_MASTER_DATA = 0;
IN_LAUNCH = 0;
end
always begin
#(PERIOD_IN_CLOCK_NS / 2);
IN_CLOCK = !IN_CLOCK;
end
initial begin
#(PERIOD_IN_CLOCK_NS * 10);
IN_MASTER_DATA = 8'b11101010;
#(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH = 1;
#(PERIOD_IN_CLOCK_NS * 5);
IN_LAUNCH = 0;
end
endmodule
| 6.907803 |
module SPI_FPGA_TB3 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH),
parameter MASTER_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter MASTER_PACK_BIT_SEQUENCE_RECEIVE = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_RECEIVE = 1 //1-major bit forward;0-junior bit forward;
);
localparam PERIOD_IN_CLOCK_NS = 1000000000 / CLOCK_FREQUENCY;
wire CS, MISO, MOSI, SCLK;
reg [PACK_LENGTH-1:0] IN_MASTER_DATA;
reg IN_CLOCK_MASTER, IN_LAUNCH_MASTER;
wire [PACK_LENGTH-1:0] OUT_MASTER_RECEIVE_DATA;
SPI_FPGA_MASTER #(
.BIT_PER_SECOND(BIT_PER_SECOND),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PACK_LENGTH(PACK_LENGTH),
.CPOL(CPOL),
.CPHA(CPHA),
.PACK_BIT_SEQUENCE_TRANSMIT(MASTER_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(MASTER_PACK_BIT_SEQUENCE_RECEIVE)
) MASTER (
IN_CLOCK_MASTER,
IN_LAUNCH_MASTER,
IN_MASTER_DATA,
MISO,
MOSI,
CS,
SCLK,
OUT_MASTER_RECEIVE_DATA,
OUT_MASTER_ACTION_DONE
);
reg IN_CLOCK_PWM, IN_RESET_PWM;
SPI_SLAVE_PWM #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(SLAVE_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(SLAVE_PACK_BIT_SEQUENCE_RECEIVE),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY)
) SLAVE_PWM (
IN_CLOCK_PWM,
MOSI,
CS,
SCLK,
IN_RESET_PWM,
OUT_PWM_SIGNAL
);
initial begin
//initial master
IN_CLOCK_MASTER = 1;
IN_MASTER_DATA = 0;
IN_LAUNCH_MASTER = 0;
//initial PWM slave
IN_RESET_PWM = 0;
IN_CLOCK_PWM = 0;
end
always begin
#(PERIOD_IN_CLOCK_NS / 2);
IN_CLOCK_MASTER = !IN_CLOCK_MASTER;
IN_CLOCK_PWM = !IN_CLOCK_PWM;
end
reg start;
initial begin
start = 0;
#(PERIOD_IN_CLOCK_NS * 10);
IN_RESET_PWM = 1;
#(PERIOD_IN_CLOCK_NS * 2);
IN_RESET_PWM = 0;
#(PERIOD_IN_CLOCK_NS * 6);
start = 1;
end
integer i = 0;
integer step = 25;
initial begin
@(posedge start)
forever begin
#(PERIOD_IN_CLOCK_NS * 10);
IN_MASTER_DATA = i;
#(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH_MASTER = 1;
@(negedge CS) #(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH_MASTER = 0;
@(posedge CS) #(PERIOD_IN_CLOCK_NS * 64);
i = i + step;
if (i > 255) begin
#(PERIOD_IN_CLOCK_NS * 500);
i = 0;
end
end
end
endmodule
| 7.397924 |
module SPI_FPGA_TB4_CPOL_1_CPHA_1_M_TO_S_1_S_TO_M_0 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b1,
parameter CPHA = 1'b1,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH),
parameter MASTER_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter MASTER_PACK_BIT_SEQUENCE_RECEIVE = 0, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_TRANSMIT = 0, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_RECEIVE = 1, //1-major bit forward;0-junior bit forward;
parameter FREQUENCY_DIV = 32,
parameter PWM_FREQUENCY = CLOCK_FREQUENCY / FREQUENCY_DIV
);
localparam PERIOD_IN_CLOCK_NS = 1000000000 / CLOCK_FREQUENCY;
wire CS, MISO, MOSI, SCLK;
reg [PACK_LENGTH-1:0] IN_MASTER_DATA;
reg IN_CLOCK_MASTER, IN_LAUNCH_MASTER;
wire [PACK_LENGTH-1:0] OUT_MASTER_RECEIVE_DATA;
SPI_FPGA_MASTER #(
.BIT_PER_SECOND(BIT_PER_SECOND),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PACK_LENGTH(PACK_LENGTH),
.CPOL(CPOL),
.CPHA(CPHA),
.PACK_BIT_SEQUENCE_TRANSMIT(MASTER_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(MASTER_PACK_BIT_SEQUENCE_RECEIVE)
) MASTER (
IN_CLOCK_MASTER,
IN_LAUNCH_MASTER,
IN_MASTER_DATA,
MISO,
MOSI,
CS,
SCLK,
OUT_MASTER_RECEIVE_DATA,
OUT_MASTER_ACTION_DONE
);
reg IN_CLOCK_PWM, IN_RESET_PWM;
SPI_SLAVE_PWM #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(SLAVE_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(SLAVE_PACK_BIT_SEQUENCE_RECEIVE),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PWM_FREQUENCY(PWM_FREQUENCY)
) SLAVE_PWM (
IN_CLOCK_PWM,
MOSI,
CS,
SCLK,
IN_RESET_PWM,
OUT_PWM_SIGNAL
);
initial begin
//initial master
IN_CLOCK_MASTER = 1;
IN_MASTER_DATA = 0;
IN_LAUNCH_MASTER = 0;
//initial PWM slave
IN_RESET_PWM = 0;
IN_CLOCK_PWM = 0;
end
always begin
#(PERIOD_IN_CLOCK_NS / 2);
IN_CLOCK_MASTER = !IN_CLOCK_MASTER;
IN_CLOCK_PWM = !IN_CLOCK_PWM;
end
reg start;
initial begin
start = 0;
#(PERIOD_IN_CLOCK_NS * 10);
IN_RESET_PWM = 1;
#(PERIOD_IN_CLOCK_NS * 2);
IN_RESET_PWM = 0;
#(PERIOD_IN_CLOCK_NS * 6);
start = 1;
end
integer i = 0;
integer step = 15;
initial begin
@(posedge start)
forever begin
#(PERIOD_IN_CLOCK_NS * 10);
IN_MASTER_DATA = i;
#(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH_MASTER = 1;
@(negedge CS) #(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH_MASTER = 0;
@(posedge CS) #(PERIOD_IN_CLOCK_NS * FREQUENCY_DIV * 4);
i = i + step;
if (i > 255) begin
#(PERIOD_IN_CLOCK_NS * 1000);
i = 0;
end
end
end
endmodule
| 7.566786 |
module SPI_FPGA_TB4 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH),
parameter MASTER_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter MASTER_PACK_BIT_SEQUENCE_RECEIVE = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_RECEIVE = 1, //1-major bit forward;0-junior bit forward;
parameter FREQUENCY_DIV = 32,
parameter PWM_FREQUENCY = CLOCK_FREQUENCY / FREQUENCY_DIV
);
localparam PERIOD_IN_CLOCK_NS = 1000000000 / CLOCK_FREQUENCY;
wire CS, MISO, MOSI, SCLK;
reg [PACK_LENGTH-1:0] IN_MASTER_DATA;
reg IN_CLOCK_MASTER, IN_LAUNCH_MASTER;
wire [PACK_LENGTH-1:0] OUT_MASTER_RECEIVE_DATA;
SPI_FPGA_MASTER #(
.BIT_PER_SECOND(BIT_PER_SECOND),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PACK_LENGTH(PACK_LENGTH),
.CPOL(CPOL),
.CPHA(CPHA),
.PACK_BIT_SEQUENCE_TRANSMIT(MASTER_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(MASTER_PACK_BIT_SEQUENCE_RECEIVE)
) MASTER (
IN_CLOCK_MASTER,
IN_LAUNCH_MASTER,
IN_MASTER_DATA,
MISO,
MOSI,
CS,
SCLK,
OUT_MASTER_RECEIVE_DATA,
OUT_MASTER_ACTION_DONE
);
reg IN_CLOCK_PWM, IN_RESET_PWM;
SPI_SLAVE_PWM #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(SLAVE_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(SLAVE_PACK_BIT_SEQUENCE_RECEIVE),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PWM_FREQUENCY(PWM_FREQUENCY)
) SLAVE_PWM (
IN_CLOCK_PWM,
MOSI,
CS,
SCLK,
IN_RESET_PWM,
OUT_PWM_SIGNAL
);
initial begin
//initial master
IN_CLOCK_MASTER = 1;
IN_MASTER_DATA = 0;
IN_LAUNCH_MASTER = 0;
//initial PWM slave
IN_RESET_PWM = 0;
IN_CLOCK_PWM = 0;
end
always begin
#(PERIOD_IN_CLOCK_NS / 2);
IN_CLOCK_MASTER = !IN_CLOCK_MASTER;
IN_CLOCK_PWM = !IN_CLOCK_PWM;
end
reg start;
initial begin
start = 0;
#(PERIOD_IN_CLOCK_NS * 10);
IN_RESET_PWM = 1;
#(PERIOD_IN_CLOCK_NS * 2);
IN_RESET_PWM = 0;
#(PERIOD_IN_CLOCK_NS * 6);
start = 1;
end
integer i = 0;
integer step = 15;
initial begin
@(posedge start)
forever begin
#(PERIOD_IN_CLOCK_NS * 10);
IN_MASTER_DATA = i;
#(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH_MASTER = 1;
@(negedge CS) #(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH_MASTER = 0;
@(posedge CS) #(PERIOD_IN_CLOCK_NS * FREQUENCY_DIV * 4);
i = i + step;
if (i > 255) begin
#(PERIOD_IN_CLOCK_NS * 1000);
i = 0;
end
end
end
endmodule
| 7.694781 |
module SPI_FPGA_TB5 #(
parameter BIT_PER_SECOND = 12500000,
parameter CLOCK_FREQUENCY = 50000000,
parameter PACK_LENGTH = 8,
parameter CPOL = 1'b0,
parameter CPHA = 1'b0,
parameter CLKS_PER_BIT_LOG_2 = $clog2(CLOCK_FREQUENCY / (BIT_PER_SECOND * 2)),
parameter PACK_LENGTH_LOG_2 = $clog2(PACK_LENGTH),
parameter MASTER_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter MASTER_PACK_BIT_SEQUENCE_RECEIVE = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter SLAVE_PACK_BIT_SEQUENCE_RECEIVE = 1 //1-major bit forward;0-junior bit forward;
);
localparam PERIOD_IN_CLOCK_NS = 1000000000 / CLOCK_FREQUENCY;
wire CS, MISO, MOSI, SCLK;
reg [PACK_LENGTH-1:0] IN_MASTER_DATA;
wire [PACK_LENGTH-1:0] OUT_MASTER_RECEIVE_DATA;
reg IN_CLOCK, IN_LAUNCH;
SPI_FPGA_MASTER #(
.BIT_PER_SECOND(BIT_PER_SECOND),
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PACK_LENGTH(PACK_LENGTH),
.CPOL(CPOL),
.CPHA(CPHA),
.PACK_BIT_SEQUENCE_TRANSMIT(MASTER_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(MASTER_PACK_BIT_SEQUENCE_RECEIVE)
) MASTER (
IN_CLOCK,
IN_LAUNCH,
IN_MASTER_DATA,
MISO,
MOSI,
CS,
SCLK,
OUT_MASTER_RECEIVE_DATA,
OUT_MASTER_ACTION_DONE
);
reg [PACK_LENGTH-1:0] IN_SLAVE_1_TRANSMIT_DATA;
wire [PACK_LENGTH-1:0] OUT_SLAVE_1_RECEIVE_DATA;
reg IN_SLAVE_1_RESET;
SPI_FPGA_SLAVE #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(SLAVE_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(SLAVE_PACK_BIT_SEQUENCE_RECEIVE)
) SLAVE1 (
IN_SLAVE_1_TRANSMIT_DATA,
MOSI,
CS_1,
SCLK,
IN_SLAVE_1_RESET,
MISO,
OUT_SLAVE_1_RECEIVE_DATA
);
reg [PACK_LENGTH-1:0] IN_SLAVE_2_TRANSMIT_DATA;
wire [PACK_LENGTH-1:0] OUT_SLAVE_2_RECEIVE_DATA;
reg IN_SLAVE_2_RESET;
SPI_FPGA_SLAVE #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(SLAVE_PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(SLAVE_PACK_BIT_SEQUENCE_RECEIVE)
) SLAVE2 (
IN_SLAVE_2_TRANSMIT_DATA,
MOSI,
CS_2,
SCLK,
IN_SLAVE_2_RESET,
MISO,
OUT_SLAVE_2_RECEIVE_DATA
);
integer SLAVE_INDEX;
assign CS_1 = (SLAVE_INDEX == 1) ? CS : 1;
assign CS_2 = (SLAVE_INDEX == 2) ? CS : 1;
initial begin
SLAVE_INDEX = 0;
//initial master
IN_CLOCK = 0;
IN_MASTER_DATA = 0;
IN_LAUNCH = 0;
//initial slave1
IN_SLAVE_1_TRANSMIT_DATA = 0;
IN_SLAVE_1_RESET = 0;
//initial slave1
IN_SLAVE_2_TRANSMIT_DATA = 0;
IN_SLAVE_2_RESET = 0;
end
always begin
#(PERIOD_IN_CLOCK_NS / 2);
IN_CLOCK = !IN_CLOCK;
end
event start;
initial begin
#(PERIOD_IN_CLOCK_NS * 5);
IN_SLAVE_1_RESET = 1;
IN_SLAVE_2_RESET = 1;
#(PERIOD_IN_CLOCK_NS * 5);
IN_SLAVE_1_RESET = 0;
IN_SLAVE_2_RESET = 0;
->start;
end
initial begin
@(start) SLAVE_INDEX = 1;
#(PERIOD_IN_CLOCK_NS * 10);
IN_MASTER_DATA = 8'b11101010;
#(PERIOD_IN_CLOCK_NS * 3);
IN_SLAVE_1_TRANSMIT_DATA = 8'b01010011;
#(PERIOD_IN_CLOCK_NS * 3);
IN_LAUNCH = 1;
@(negedge CS) #(PERIOD_IN_CLOCK_NS * 2);
IN_LAUNCH = 0;
@(posedge CS) #(PERIOD_IN_CLOCK_NS * 2);
IN_SLAVE_2_TRANSMIT_DATA = 8'b10101010;
#(PERIOD_IN_CLOCK_NS * 5);
SLAVE_INDEX = 2;
IN_MASTER_DATA = 8'b11100011;
#(PERIOD_IN_CLOCK_NS * 5);
IN_LAUNCH = 1;
@(negedge CS) #(PERIOD_IN_CLOCK_NS * 2);
IN_LAUNCH = 0;
//передача в никуда
@(posedge CS) #(PERIOD_IN_CLOCK_NS * 2);
SLAVE_INDEX = 3;
IN_MASTER_DATA = 8'b11001100;
#(PERIOD_IN_CLOCK_NS * 5);
IN_LAUNCH = 1;
@(negedge CS) #(PERIOD_IN_CLOCK_NS * 2);
IN_LAUNCH = 0;
end
endmodule
| 7.631141 |
module spi_fsm #(
parameter DEPTH = 8, // number of chunks
parameter WIDTH = 8, // bits per chunk
parameter WRCMD = 8'h01,
parameter RDCMD = 8'h02
) (
input clk,
input rst,
output reg spi_we, // spi_slave wr
input spi_dv, // spi_slave rx_dv
input spi_halt,
input [WIDTH-1:0] i_data, // chunks from spi slave
output reg [WIDTH-1:0] o_data, // chunks to spi slave
output reg buf_dv, // fsm buffer data valid
input [(DEPTH*WIDTH)-1:0] i_buffer,
output reg [(DEPTH*WIDTH)-1:0] o_buffer
);
parameter [2:0] S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100, S5 = 3'b101;
integer count;
reg [2:0] current_state, next_state;
// state register
always @(posedge clk) begin
if (rst) begin
current_state <= S0;
end else begin
current_state <= next_state;
end
end
// transition logic
always @(*) begin
case (current_state)
S0: begin
if (spi_dv && (i_data == WRCMD)) begin
next_state = S1;
end else if (spi_dv && (i_data == RDCMD)) begin
next_state = S3;
end else begin
next_state = S0;
end
end
S1: begin
if (count != 0) begin
next_state = S1;
end else begin
next_state = S2;
end
end
S2: begin
next_state = S0;
end
S3: begin
next_state = S4;
end
S4: begin
if (count != 0) begin
next_state = S5;
end else begin
next_state = S0;
end
end
S5: begin
next_state <= S4;
end
endcase
end
// output logic
always @(posedge clk) begin
spi_we <= spi_we;
o_data <= o_data;
buf_dv <= buf_dv;
o_buffer <= o_buffer;
count <= count;
if (rst) begin
spi_we <= 0;
o_data <= 0;
buf_dv <= 0;
o_buffer <= 0;
count <= DEPTH;
end else begin
case (current_state)
S0: begin
spi_we <= 0;
buf_dv <= 0;
count <= DEPTH;
end
S1: begin
if (spi_dv) begin
o_buffer <= {o_buffer[(WIDTH*(DEPTH-1))-1:0], i_data};
count <= count - 1;
end
end
S2: begin
buf_dv <= 1;
end
S3: begin
o_buffer <= i_buffer;
end
S4: begin
if (~spi_halt) begin
spi_we <= 1;
o_data <= o_buffer[(WIDTH*DEPTH)-1:(WIDTH*(DEPTH-1))];
o_buffer <= {o_buffer[(WIDTH*(DEPTH-1))-1:0], {WIDTH{1'b0}}};
count <= count - 1;
end else begin
spi_we <= 0;
end
end
S5: begin
count <= count; // wait for SPI to assert halt
end
endcase
end
end
endmodule
| 8.302968 |
module acts as the translator from
// SPI slave to an 8-bit address, 8-bit data local bus.
// That super-stripped down SPI concept could be revisited if we can verify
// a suitable portable (STM32 and LPC) API on the microcontroller side.
module spi_gate(
// pins
input SCLK,
input CSB,
input MOSI,
output MISO,
//
input config_clk, // drives the only clock domain here
output config_w,
output config_r,
output [7:0] config_a,
output [7:0] config_d,
input [7:0] tx_data,
//
output [3:0] spi_pins_debug // latched in config_clk domain
);
reg [15:0] sr=0; // shift register accumulating {a,d} from SPI master
reg din=0, csb_d1=0, csb_d2=0, sclk_d1=0, sclk_d2=0;
reg config_w_r=0, config_r_r=0, halfway=0;
reg config_r_r1=0, config_r_r2=0;
reg [4:0] bit_cnt=0;
reg [7:0] sr_tx=0; // could merge with sr?
wire active_edge = ~csb_d1 & ~sclk_d1 & sclk_d2; // falling edge
reg active_edge1=0, active_edge2=0;
always @(posedge config_clk) begin
// sync/IOB the three inputs. Latency is not an issue.
din <= MOSI;
csb_d1 <= CSB;
sclk_d1 <= SCLK;
// need history to look for edges
csb_d2 <= csb_d1;
sclk_d2 <= sclk_d1;
// update the shift register on active edge of SCLK
if (active_edge) begin
sr <= {sr[14:0], din};
bit_cnt <= bit_cnt + 1;
halfway <= |bit_cnt[4:3];
end
active_edge1 <= active_edge;
active_edge2 <= active_edge1;
if (active_edge2) sr_tx <= {sr_tx[6:0], 1'b0};
// cycle the output on rising edge of CSB
config_w_r <= csb_d1 & ~csb_d2;
// WIP: flag the halfway point
config_r_r <= active_edge & (bit_cnt==7);
config_r_r1 <= config_r_r;
if (config_r_r1) sr_tx <= tx_data;
if (csb_d2 & ~csb_d1) bit_cnt <= 0;
end
assign config_w = config_w_r;
assign config_r = config_r_r;
assign config_a = halfway ? sr[15:8] : sr[7:0];
assign config_d = sr[7:0];
assign MISO = sr_tx[7];
// MISO transitions three cycles (24 ns) after falling edge of SCLK
// (as latched in the IOB as sclk_d1)
assign spi_pins_debug = {MISO, din, sclk_d1, csb_d1};
// watch MISO like a hawk, make sure it lands in an IOB
endmodule
| 7.829874 |
module bin2gray (
bin,
gray
);
parameter SIZE = 8;
input [SIZE-1:0] bin;
output [SIZE-1:0] gray;
assign gray = (bin >> 1) ^ bin;
endmodule
| 6.587586 |
module gray_counter (clk_i, rst_n_i, en_i, period_i, clock_o);
parameter SIZE = 8;
input clk_i;
input rst_n_i;
input en_i;
input [SIZE-1:0] period_i;
output clock_o;
reg [SIZE-1:0] gray_code;
reg [SIZE-1:0] tog;
reg clock;
wire [SIZE-1:0] gray_code_comp;
integer i,j,k;
bin2gray #SIZE B2G(period_i, gray_code_comp);
assign clock_o = clock;
always @(posedge clk_i or negedge rst_n_i)
if (rst_n_i==1'b0) begin
gray_code <= 0;
clock <= 1'b0;
end
else begin //sequential update
if (en_i==1'b1)
if (gray_code_comp==gray_code) begin
gray_code <= 0;
clock <= 1'b1;
end
else begin //enabled
clock <= 1'b0;
tog = 0;
for (i=0; i<=SIZE-1; i=i+1) begin //i loop
//
// Toggle bit if number of bits set in [SIZE-1:i] is even
// XNOR current bit up to MSB bit
//
for (j=i; j<=SIZE-1; j=j+1) tog[i] = tog[i] ^ gray_code[j];
tog[i] = !tog[i];
//
// Disable tog[i] if a lower bit is toggling
//
for (k=0; k<=i-1; k=k+1) tog[i] = tog[i] && !tog[k];
end //i loop
//
//Toggle MSB if no lower bits set (covers code wrap case)
//
if (tog[SIZE-2:0]==0) tog[SIZE-1] = 1;
//
//Apply the toggle mask
//
gray_code <= gray_code ^ tog;
end //enabled
end //sequential update
endmodule
| 6.858216 |
module spi_if (
clk,
reset_n,
// towards ctrl i/f
sck_pe,
sck_int,
cs_int_n,
byte_in,
load_byte,
byte_out,
shift_out,
shift_in,
cfg_tgt_sel,
sck,
so,
si,
cs_n
);
input clk, reset_n;
input sck_pe;
input sck_int, cs_int_n;
input load_byte;
input [1:0] cfg_tgt_sel;
input [7:0] byte_out;
input shift_out, shift_in;
output [7:0] byte_in;
output sck, so;
output [3:0] cs_n;
input si;
reg [7:0] so_reg;
reg [7:0] si_reg;
wire [7:0] byte_out;
wire sck;
reg so;
wire [3:0] cs_n;
//Output Shift Register
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
so_reg <= 8'h00;
so <= 1'b0;
end else begin
if (load_byte) begin
so_reg <= byte_out;
if (shift_out) begin
// Handling backto back case :
// Last Transfer bit + New Trasfer Load
so <= so_reg[7];
end
end // if (load_byte)
else begin
if (shift_out) begin
so <= so_reg[7];
so_reg <= {so_reg[6:0], 1'b0};
end // if (shift_out)
end // else: !if(load_byte)
end // else: !if(!reset_n)
end // always @ (posedge clk or negedge reset_n)
// Input shift register
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
si_reg <= 8'h0;
end else begin
if (sck_pe & shift_in) begin
si_reg[7:0] <= {si_reg[6:0], si};
end // if (sck_pe & shift_in)
end // else: !if(!reset_n)
end // always @ (posedge clk or negedge reset_n)
assign byte_in[7:0] = si_reg[7:0];
assign cs_n[0] = (cfg_tgt_sel[1:0] == 2'b00) ? cs_int_n : 1'b1;
assign cs_n[1] = (cfg_tgt_sel[1:0] == 2'b01) ? cs_int_n : 1'b1;
assign cs_n[2] = (cfg_tgt_sel[1:0] == 2'b10) ? cs_int_n : 1'b1;
assign cs_n[3] = (cfg_tgt_sel[1:0] == 2'b11) ? cs_int_n : 1'b1;
assign sck = sck_int;
endmodule
| 6.662688 |
module spi_interf (
input wire clk,
input wire sclk,
input wire cs_n,
input wire load,
input wire [26:0] data_in,
output wire serial_out
);
reg [26:0] data;
reg [1:0] sclk_r;
reg [1:0] cs_n_r;
wire sclk_ne = (sclk_r == 2'b10);
always @(posedge clk) begin
sclk_r <= {sclk_r[0], sclk};
end
always @(posedge clk) begin
if (!cs_n) begin
if (sclk_ne) begin
data <= {data[25:0], data[26]};
end
end else begin
if (load) begin
data <= data_in;
end
end
end
assign serial_out = data[26];
endmodule
| 7.045277 |
module SPI_Interface (
input iCLK,
input iCLK_50,
input Reset,
output SD_CLK,
output SD_MOSI,
input SD_MISO,
output SD_CS,
// Barramento de dados
input wReadEnable,
wWriteEnable,
input [ 3:0] wByteEnable,
input [31:0] wAddress,
wWriteData,
output [31:0] wReadData
);
sd_controller sd1 (
.cs (SD_CS),
.mosi(SD_MOSI),
.miso(SD_MISO),
.sclk(SD_CLK),
.rd (SDReadEnable),
.wr (1'b0),
.dm_in (1'b1), // data mode, 0 = write continuously, 1 = write single block
.reset (Reset),
.din (8'hFF),
.dout (SDData),
.address(SDAddress),
.iCLK (iCLK_50),
.idleSD (SDCtrl)
);
reg [31:0] SDAddress;
wire [ 7:0] SDData;
wire [ 3:0] SDCtrl; // [SDCtrl ? BUSY : READY]
reg SDReadEnable;
always @(posedge iCLK) begin
if (wWriteEnable) begin
if (wAddress == SD_INTERFACE_ADDR) SDAddress <= wWriteData;
end
end
always @(posedge iCLK) begin
if (SDCtrl == 4'h8 || SDCtrl == 4'h9 || SDCtrl == 4'hA || SDCtrl == 4'hB) SDReadEnable = 1'b0;
else if (wAddress == SD_INTERFACE_ADDR && SDCtrl == 4'h0) SDReadEnable = 1'b1;
end
always @(*) begin
if (wReadEnable) begin
if (wAddress == SD_INTERFACE_DATA || wAddress == SD_INTERFACE_CTRL)
wReadData = {16'b0, SDData, 4'b0, SDCtrl};
else wReadData = 32'hzzzzzzzz;
end else wReadData = 32'hzzzzzzzz;
end
endmodule
| 6.535791 |
module spi_interface_master #(
parameter SPI_MAX_WIDTH_LOG = 4,
parameter SPI_SCAIL_LOG = 8
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input spi_start,
output spi_finish,
output sck,
output cs,
output mosi,
input miso,
input config_req,
input [SPI_MAX_WIDTH_LOG + 1:0] config_data,
input [2 ** SPI_MAX_WIDTH_LOG - 1:0] din,
output [2 ** SPI_MAX_WIDTH_LOG - 1:0] dout
);
wire cpol, cpha;
wire [SPI_MAX_WIDTH_LOG - 1:0] spi_width;
spi_config #(
.SPI_MAX_WIDTH_LOG(SPI_MAX_WIDTH_LOG)
) u_spi_config (
.clk (clk), // Clock
.rst_n(rst_n), // Asynchronous reset active low
.config_req (config_req),
.config_data(config_data),
.cpol(cpol),
.cpha(cpha),
.spi_width(spi_width)
);
wire sck_first_edge;
wire sck_second_edge;
sck_gen #(
.SPI_MAX_WIDTH_LOG(SPI_MAX_WIDTH_LOG),
.SPI_SCAIL_LOG(SPI_SCAIL_LOG)
) u_sck_gen (
.clk (clk), // Clock
.rst_n(rst_n), // Asynchronous reset active low
.spi_start(spi_start),
.cpol(cpol),
.cpha(cpha),
.spi_width(spi_width),
.sck_first_edge (sck_first_edge),
.sck_second_edge(sck_second_edge),
.sck(sck),
.cs (cs),
.spi_finish(spi_finish)
);
spi_datapath_master #(
.SPI_MAX_WIDTH_LOG(SPI_MAX_WIDTH_LOG)
) u_spi_datapath_master (
.clk (clk), // Clock
.rst_n(rst_n), // Asynchronous reset active low
//config
.cpha(cpha),
//control flow
.sck_first_edge(sck_first_edge),
.sck_second_edge(sck_second_edge),
.spi_start(spi_start),
//spi
.miso(miso),
.mosi(mosi),
//data
.din (din),
.dout(dout)
);
endmodule
| 7.730375 |
module spi_interface_slave #(
parameter SPI_MAX_WIDTH_LOG = 4
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
output spi_start,
output spi_finish,
input sck,
input cs,
input mosi,
output miso,
input config_req,
input [SPI_MAX_WIDTH_LOG + 1:0] config_data,
input [2 ** SPI_MAX_WIDTH_LOG - 1:0] din,
output [2 ** SPI_MAX_WIDTH_LOG - 1:0] dout
);
wire cpol, cpha;
wire [SPI_MAX_WIDTH_LOG - 1:0] spi_width;
spi_config #(
.SPI_MAX_WIDTH_LOG(SPI_MAX_WIDTH_LOG)
) u_spi_config (
.clk (clk), // Clock
.rst_n(rst_n), // Asynchronous reset active low
.config_req (config_req),
.config_data(config_data),
.cpol(cpol),
.cpha(cpha),
.spi_width(spi_width)
);
wire sck_first_edge;
wire sck_second_edge;
sck_detect u_sck_detect (
.clk (clk), // Clock
.rst_n(rst_n), // Asynchronous reset active low
.cpol(cpol),
.cpha(cpha),
.spi_width(spi_width),
.sck_first_edge (sck_first_edge),
.sck_second_edge(sck_second_edge),
.sck(sck),
.cs (cs),
.spi_start (spi_start),
.spi_finish(spi_finish)
);
spi_datapath_slave #(
.SPI_MAX_WIDTH_LOG(SPI_MAX_WIDTH_LOG)
) u_spi_datapath_slave (
.clk (clk), // Clock
.rst_n(rst_n), // Asynchronous reset active low
//config
.cpha(cpha),
//control flow
.sck_first_edge(sck_first_edge),
.sck_second_edge(sck_second_edge),
.spi_start(spi_start),
//spi
.miso(miso),
.mosi(mosi),
//data
.din (din),
.dout(dout)
);
endmodule
| 7.730375 |
module spi_io (
clk,
start,
ctrl_reg,
din,
dout,
status_reg,
sclk,
miso,
mosi
);
input wire clk;
input wire start;
input wire [31:0] ctrl_reg; //interface for data width and speed
input wire [31:0] din; //input data, left justified
input wire miso;
output reg [31:0] dout = 0; //output data
output reg [31:0] status_reg = 0; //done status
output reg sclk = 0;
output reg mosi = 0;
//ctrl_reg[7:0]
reg [4:0] data_width; //sets number of bits to send
//ctrl_reg[15:8]
reg [7:0] clk_div; //sets SPI frequency
//ctrl_reg[16]
reg spi_polarity; //sets spi clk polarity, not implimented
//ctrl_reg[17]
reg spi_phase; //sets spi clk phase, not implimented
reg [3:0] FSM_state = 0;
reg [7:0] clk_counter = 0;
reg [4:0] data_index = 0;
always @(*) begin
//protect aganst stupid settings
data_width <= (ctrl_reg[4:0] == 0) ? 1 : ctrl_reg[4:0];
clk_div <= (ctrl_reg[15:8] == 0) ? 1 : ctrl_reg[15:8];
spi_phase <= 0;
spi_polarity <= 0;
end
always @(posedge clk) begin
case (FSM_state)
0: begin //idle state
FSM_state <= start ? 1 : 0;
end
1: begin //setup
FSM_state <= 2;
status_reg <= 0; //spi is in progress
data_index <= data_width - 1; //set data_index
dout <= 0; //clear old dout
clk_counter <= 0; //clear old clk_counter
end
2: begin //start send
sclk <= 0;
FSM_state <= (clk_counter >= clk_div) ? 3 : 2;
dout[data_index] <= miso;
mosi <= din[data_index];
//incriment data index on transistion
clk_counter <= (clk_counter >= clk_div) ? 0 : clk_counter + 1;
end
3: begin //clk phase#2
sclk <= 1;
clk_counter <= (clk_counter >= clk_div) ? 0 : clk_counter + 1; //timer countdown
if (data_index == 0) begin
FSM_state <= (clk_counter >= clk_div) ? 4 : 3; //exit loop
end else begin
FSM_state <= (clk_counter >= clk_div) ? 2 : 3;
data_index <= (clk_counter >= clk_div) ? data_index - 1 : data_index;
end
end
4: begin //clean up
FSM_state <= 0;
sclk <= 0;
status_reg <= 1; //spi is done!
mosi <= 0;
end
endcase
end
endmodule
| 7.353623 |
module: spi_io
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module spi_io_tb;
// Inputs
reg clk;
reg start;
reg [31:0] ctrl_reg;
reg [31:0] din;
reg miso;
// Outputs
wire [31:0] dout;
wire [31:0] status_reg;
wire sclk;
wire mosi;
// Instantiate the Unit Under Test (UUT)
spi_io uut (
.clk(clk),
.start(start),
.ctrl_reg(ctrl_reg),
.din(din),
.dout(dout),
.status_reg(status_reg),
.sclk(sclk),
.miso(miso),
.mosi(mosi)
);
always #5 clk=~clk;
always #1 miso = mosi;
initial begin
// Initialize Inputs
clk = 0;
start = 0;
ctrl_reg = 0;
din = 0;
//miso = 0;
// Wait 100 ns for global reset to finish
#100;
ctrl_reg = 32'h00_00_02_0c;
din = 32'hFF_00_FF_AA;
start = 1;
#10;
start = 0;
// Add stimulus here
end
endmodule
| 6.575778 |
module CKHS_INVX1 (
z,
a
);
input a;
output z;
SEH_INV_S_1 u (
.A(a),
.X(z)
);
endmodule
| 7.359776 |
module CKHS_MUX2X2 (
z,
d1,
d0,
sd
);
input d1, d0, sd;
output z;
SEH_MUX2_S_2 u (
.D0(d0),
.D1(d1),
.S (sd),
.X (z)
);
endmodule
| 6.598457 |
module CKHS_BUFX4_0 (
z,
a
);
input a;
output z;
SEH_BUF_S_4 u (
.A(a),
.X(z)
);
endmodule
| 7.290982 |
module CKHS_MUX4X2 (
z,
d3,
d2,
d1,
d0,
sd2,
sd1
);
input d3, d2, d1, d0, sd2, sd1;
output z;
SEH_MUX4_DG_2 u (
.D0(d0),
.D1(d1),
.D2(d2),
.D3(d3),
.S0(sd1),
.S1(sd2),
.X (z)
);
endmodule
| 6.53252 |
module CKHS_BUFX4_1 (
z,
a
);
input a;
output z;
SEH_BUF_S_4 u (
.A(a),
.X(z)
);
endmodule
| 7.25101 |
module SPI_LCD (
input wire clk,
input wire [3:0] rows,
input wire MISO,
clear,
output wire MOSI,
SCLK,
SS,
output wire [3:0] cols
);
wire clk_500KHz, clk_250KHz, clk_1KHz;
wire key_data_ready, data_ready_synced, lcd_send;
wire [6:0] encoder_out, lcd_data_out;
wire clear_inv, spi_done;
// Clear button is active low
assign clear_inv = ~clear;
// Divide the 8MHz clock to 500KHz
CLK_DIV16 clock_divider (
.CLKIN(clk),
.CLKDV(clk_500KHz)
);
// Divide 500KHz to 125KHz and 1KHz
clk_div clk_div (
.clk(clk_500KHz),
.clk_div_250khz(clk_250KHz),
.clk_div_1khz(clk_1KHz)
);
keypad key (
.clk(clk_1KHz),
.rows(rows),
.data_ready(key_data_ready),
.cols(cols),
.encoder_out(encoder_out)
);
synchronizer sync (
.fast_clk(clk_250KHz),
.rst(1'b0),
.flag(key_data_ready),
.flag_out(data_ready_synced)
);
lcd_ctrl lcd (
.clk(clk_250KHz),
.rst(1'b0),
.clear(clear_inv),
.spi_done(spi_done),
.key_data_out(encoder_out),
.key_send(data_ready_synced),
.data_out(lcd_data_out),
.send(lcd_send)
);
spi_master spi (
.clk(clk_250KHz),
.rst(1'b0),
.data_in(lcd_data_out),
.MISO(MISO),
.send(lcd_send),
.MOSI(MOSI),
.SCLK(SCLK),
.SS(SS),
.done(spi_done)
);
endmodule
| 6.856694 |
module that integrating keypad and SPI display
module SPI_LCD_top(
(*chip_pin = "E17"*)output MOSI,
(*chip_pin = "G17"*)input MISO,
(*chip_pin = "D17"*)output SS,
(*chip_pin = "H18"*)output SCLK,
(*chip_pin = "M18"*)inout VCC,
(*chip_pin = "K18"*)inout GND,
(*chip_pin = "J6"*) input clkin,
(*chip_pin="D4,C2,D1,B4"*)input [4:1] keyrow,
(*chip_pin="J3,G4,F4,E4"*)output [3:0] keycolumn
);
wire w_clk_1K;
wire w_press;
wire[7:0] w_data;
wire w_data_ready;
wire w_send;
wire [5:0] key;
reg [6:0] address;
assign {VCC,GND} = 2'b10;
SPI spi(
.MISO(MISO),
.MOSI(MOSI),
.SS(SS),
.SCLK(SCLK),
.clk(w_clk_1K),
.data_ready(w_send),
.send_data(w_data),
.INT(w_data_ready));
Controller control(
.clk(w_clk_1K),
.dataRdy(w_send),
.transEna(w_data_ready),
.data(w_data),
.key_press(w_press),
.address_key(address)
);
keypad Keyboard(
.clk(w_clk_1K),
.keyrow(keyrow),
.keycolumn(keycolumn),
.Dout(key),
.Data_ena(w_press)
);
ClockDivider divy(
.CLK(clkin),
.CLK_1K(w_clk_1K));
always @ (posedge w_press)
begin
case(key)
6'b000111:begin address =38; end//1
6'b001011:begin address =40; end//2
6'b001101:begin address =42; end//3
6'b001110:begin address =65; end//up
6'b010111:begin address =44; end//4
6'b011011:begin address =46; end//5
6'b011101:begin address =48; end//6
6'b011110:begin address =68; end//down
6'b100111:begin address =50; end//7
6'b101011:begin address =52; end//8
6'b101101:begin address =54; end//9
6'b101110:begin address =61; end//2nd
6'b110111:begin address =0; end//clear
6'b111011:begin address =36; end//0
6'b111101:begin address =56; end//help
6'b111110:begin address =73; end//enter
default:begin address = 56; end
endcase
end
endmodule
| 7.875918 |
module spi_lite_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
, input rst_i
, input [WIDTH-1:0] data_in_i
, input push_i
, input pop_i
, input flush_i
// Outputs
, output [WIDTH-1:0] data_out_o
, output accept_o
, output valid_o
);
//-----------------------------------------------------------------
// Local Params
//-----------------------------------------------------------------
localparam COUNT_W = ADDR_W + 1;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [WIDTH-1:0] ram_q[DEPTH-1:0];
reg [ADDR_W-1:0] rd_ptr_q;
reg [ADDR_W-1:0] wr_ptr_q;
reg [COUNT_W-1:0] count_q;
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @(posedge clk_i)
if (rst_i) begin
count_q <= {(COUNT_W) {1'b0}};
rd_ptr_q <= {(ADDR_W) {1'b0}};
wr_ptr_q <= {(ADDR_W) {1'b0}};
end else if (flush_i) begin
count_q <= {(COUNT_W) {1'b0}};
rd_ptr_q <= {(ADDR_W) {1'b0}};
wr_ptr_q <= {(ADDR_W) {1'b0}};
end else begin
// Push
if (push_i & accept_o) begin
ram_q[wr_ptr_q] <= data_in_i;
wr_ptr_q <= wr_ptr_q + 1;
end
// Pop
if (pop_i & valid_o) rd_ptr_q <= rd_ptr_q + 1;
// Count up
if ((push_i & accept_o) & ~(pop_i & valid_o)) count_q <= count_q + 1;
// Count down
else if (~(push_i & accept_o) & (pop_i & valid_o)) count_q <= count_q - 1;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
/* verilator lint_off WIDTH */
assign valid_o = (count_q != 0);
assign accept_o = (count_q != DEPTH);
/* verilator lint_on WIDTH */
assign data_out_o = ram_q[rd_ptr_q];
endmodule
| 6.714668 |
module spi_loader_wrap #(
parameter MEM_TYPE = "DUAL_SPRAM",
ST_ADDR = 24'h020000
) (
input resetn, //
input clk, // Clock (= RISC-V clock)
input i_init,
// FIFO interface
input i_fill,
output o_fifo_empty,
output o_fifo_low,
input i_fifo_rd,
output [31:0] o_fifo_dout,
output SPI_CSS, // SPI I/F for flash access
output SPI_CLK, //
input SPI_MISO, //
output SPI_MOSI, //
output o_load_done
);
generate
if (MEM_TYPE == "EBRAM") begin : g_on_code_ebram
spi_loader_ebram #(
.ST_ADDR(ST_ADDR)
) u_spi_loader (
.clk (clk),
.resetn(resetn),
.o_load_done(o_load_done),
.i_fill (i_fill),
.i_init (i_init),
.o_fifo_empty(o_fifo_empty),
.o_fifo_low (o_fifo_low),
.i_fifo_rd (i_fifo_rd),
.o_fifo_dout (o_fifo_dout),
.SPI_CLK (SPI_CLK),
.SPI_CSS (SPI_CSS),
.SPI_MISO(SPI_MISO),
.SPI_MOSI(SPI_MOSI)
);
end else if (MEM_TYPE == "SINGLE_SPRAM") begin : g_on_code_single_spram
spi_loader_single_spram #(
.ST_ADDR(ST_ADDR)
) u_spi_loader (
.clk (clk),
.resetn(resetn),
.o_load_done(o_load_done),
.i_fill (i_fill),
.i_init (i_init),
.o_fifo_empty(o_fifo_empty),
.o_fifo_low (o_fifo_low),
.i_fifo_rd (i_fifo_rd),
.o_fifo_dout (o_fifo_dout),
.SPI_CLK (SPI_CLK),
.SPI_CSS (SPI_CSS),
.SPI_MISO(SPI_MISO),
.SPI_MOSI(SPI_MOSI)
);
end else if (MEM_TYPE == "TRI_SPRAM") begin : g_on_code_tri_spram
spi_loader_tri_spram #(
.ST_ADDR(ST_ADDR)
) u_spi_loader (
.clk (clk),
.resetn(resetn),
.o_load_done(o_load_done),
.i_fill (i_fill),
.i_init (i_init),
.o_fifo_empty(o_fifo_empty),
.o_fifo_low (o_fifo_low),
.i_fifo_rd (i_fifo_rd),
.o_fifo_dout (o_fifo_dout),
.SPI_CLK (SPI_CLK),
.SPI_CSS (SPI_CSS),
.SPI_MISO(SPI_MISO),
.SPI_MOSI(SPI_MOSI)
);
end else if (MEM_TYPE == "QUAD_SPRAM") begin : g_on_code_quad_spram
spi_loader_spram #(
.QUAD_SPRAM(1'b1),
.ST_ADDR(ST_ADDR)
) u_spi_loader (
.clk (clk),
.resetn(resetn),
.o_load_done(o_load_done),
.i_fill (i_fill),
.i_init (i_init),
.o_fifo_empty(o_fifo_empty),
.o_fifo_low (o_fifo_low),
.i_fifo_rd (i_fifo_rd),
.o_fifo_dout (o_fifo_dout),
.SPI_CLK (SPI_CLK),
.SPI_CSS (SPI_CSS),
.SPI_MISO(SPI_MISO),
.SPI_MOSI(SPI_MOSI)
);
end else // DUAL_SPRAM
begin : g_on_code_dual_spram
spi_loader_spram #(
.QUAD_SPRAM(1'b0),
.ST_ADDR(ST_ADDR)
) u_spi_loader (
.clk (clk),
.resetn(resetn),
.o_load_done(o_load_done),
.i_fill (i_fill),
.i_init (i_init),
.o_fifo_empty(o_fifo_empty),
.o_fifo_low (o_fifo_low),
.i_fifo_rd (i_fifo_rd),
.o_fifo_dout (o_fifo_dout),
.SPI_CLK (SPI_CLK),
.SPI_CSS (SPI_CSS),
.SPI_MISO(SPI_MISO),
.SPI_MOSI(SPI_MOSI)
);
end
endgenerate
endmodule
| 6.822725 |
module SPI_loopback #(
parameter CLK_FREQUENCE = 50_000_000, //system clk frequence
SPI_FREQUENCE = 5_000_000, //spi clk frequence
DATA_WIDTH = 8, //serial word length
CPOL = 0, //SPI mode selection (mode 0 default)
CPHA = 0 //CPOL = clock polarity, CPHA = clock phase
) (
input clk,
input rst_n,
input [DATA_WIDTH-1:0] data_m_in,
input [DATA_WIDTH-1:0] data_s_in,
input start_m,
output finish_m,
output [DATA_WIDTH-1:0] data_m_out,
output [DATA_WIDTH-1:0] data_s_out,
output data_valid_s
);
wire miso;
wire mosi;
wire cs_n;
wire sclk;
spi_master #(
.CLK_FREQUENCE(CLK_FREQUENCE),
.SPI_FREQUENCE(SPI_FREQUENCE),
.DATA_WIDTH (DATA_WIDTH),
.CPOL (CPOL),
.CPHA (CPHA)
) u_spi_master (
.clk (clk),
.rst_n (rst_n),
.data_in (data_m_in),
.start (start_m),
.miso (miso),
.sclk (sclk),
.cs_n (cs_n),
.mosi (mosi),
.finish (finish_m),
.data_out(data_m_out)
);
SPI_Slave #(
.CLK_FREQUENCE(CLK_FREQUENCE),
.SPI_FREQUENCE(SPI_FREQUENCE),
.DATA_WIDTH (DATA_WIDTH),
.CPOL (CPOL),
.CPHA (CPHA)
) u_SPI_Slave (
.clk (clk),
.rst_n (rst_n),
.data_in (data_s_in),
.sclk (sclk),
.cs_n (cs_n),
.mosi (mosi),
.miso (miso),
.data_valid(data_valid_s),
.data_out (data_s_out)
);
endmodule
| 8.799181 |
module SPI_loopback_tb ();
parameter CLK_FREQUENCE = 50_000_000 ,
SPI_FREQUENCE = 5_000_000 ,
DATA_WIDTH = 8 ,
CPOL = 0 ,
CPHA = 0 ;
reg clk;
reg rst_n;
reg [DATA_WIDTH-1:0] data_m_in;
reg [DATA_WIDTH-1:0] data_s_in;
reg start_m;
wire finish_m;
wire [DATA_WIDTH-1:0] data_m_out;
wire [DATA_WIDTH-1:0] data_s_out;
wire data_valid_s;
//the clk generation
initial begin
clk = 1;
forever #10 clk = ~clk;
end
//the rst_n generation
initial begin
rst_n = 1'b0;
#22 rst_n = 1'b1;
end
//the main block
initial
fork
data_m_in_generate;
data_s_in_generate;
start_change;
join
//to generate data_m_in
task data_m_in_generate;
begin
data_m_in = 'd0;
@(posedge rst_n) data_m_in <= 8'b10100101;
@(posedge finish_m) data_m_in <= 8'b10011010;
end
endtask
//to generate data_s_in
task data_s_in_generate;
begin
data_s_in = 'd0;
@(posedge rst_n) data_s_in <= $random;
@(posedge finish_m) data_s_in <= $random;
@(negedge data_valid_s);
@(negedge data_valid_s) #20 $finish;
end
endtask
//to generate the start signal
task start_change;
begin
start_m = 1'b0;
@(posedge rst_n) #20 start_m <= 1'b1;
#20 start_m = 1'b0;
@(negedge finish_m) #20 start_m = 1'b1;
#20 start_m = 1'b0;
end
endtask
//to generate uart_frame_tx_tb.vcd
initial begin
$dumpfile("SPI_loopback_tb.vcd");
$dumpvars();
end
//Debug information
reg data_valid_1;
reg data_valid_2;
always @(posedge clk or negedge rst_n) begin
data_valid_1 <= data_valid_s;
data_valid_2 <= data_valid_1;
end
assign data_valid_pos = ~data_valid_2 & data_valid_1;
always @(posedge clk) begin
if (data_valid_pos)
if (data_s_out == data_m_in)
$display("PASS! data_s_out = %h, data_m_in = %h", data_s_out, data_m_in);
else $display("FAIL! data_s_out = %h, data_m_in = %h", data_s_out, data_m_in);
end
always @(posedge clk) begin
if (data_valid_pos)
if (data_m_out == data_s_in)
$display("PASS! data_m_out = %h, data_s_in = %h", data_m_out, data_s_in);
else $display("FAIL! data_m_out = %h, data_s_in = %h", data_m_out, data_s_in);
end
//DUT
SPI_loopback #(
.CLK_FREQUENCE(CLK_FREQUENCE),
.SPI_FREQUENCE(SPI_FREQUENCE),
.DATA_WIDTH (DATA_WIDTH),
.CPOL (CPOL),
.CPHA (CPHA)
) u_SPI_loopback (
.clk (clk),
.rst_n (rst_n),
.data_m_in (data_m_in),
.data_s_in (data_s_in),
.start_m (start_m),
.finish_m (finish_m),
.data_m_out (data_m_out),
.data_s_out (data_s_out),
.data_valid_s(data_valid_s)
);
endmodule
| 7.741791 |
module spi_master0_37 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 8.133749 |
module spi_master10_47 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 7.785648 |
module spi_master11_48 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 7.851033 |
module spi_master12_49 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
end
endmodule
| 7.888647 |
module spi_master13_50 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 7.898857 |
module spi_master14_51 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 7.865188 |
module spi_master15_52 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 8.028121 |
module spi_master16_53 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
end
endmodule
| 7.944648 |
module spi_master17_54 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 8.158599 |
module spi_master18_55 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 8.184709 |
module spi_master19_56 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 8.294831 |
module spi_master1_38 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 8.041383 |
module spi_master20_57 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 8.175769 |
module spi_master21_58 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 7.813494 |
module spi_master22_59 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 7.99538 |
module spi_master23_60 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 8.128513 |
module spi_master24_61 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 7.827576 |
module spi_master25_62 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 8.037488 |
module spi_master26_63 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 7.941921 |
module spi_master27_64 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 7.954921 |
module spi_master28_65 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 7.940503 |
module spi_master29_66 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 8.056942 |
module spi_master2_39 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 8.127403 |
module spi_master30_67 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 8.157523 |
module spi_master31_68 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 7.94063 |
module spi_master32_69 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 8.081446 |
module spi_master3_40 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 8.128919 |
module spi_master4_41 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 7.85054 |
module spi_master5_42 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 8.105354 |
module spi_master6_43 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 8.019294 |
module spi_master7_44 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
end
endmodule
| 8.157203 |
module spi_master8_45 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 8.150674 |
module spi_master9_46 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h4;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [3:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[3+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 3'h7) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 4'hf) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
M_ctr_d = 1'h0;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 7.846677 |
module spi_master_3 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 4'h8;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [7:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[7+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 7'h7f) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 8'hff) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 8.187428 |
module spi_master (
rstb,
clk,
mlb,
start,
tdat,
cdiv,
din,
ss,
sck,
dout,
done_r,
rdata
);
parameter state_idle = 4'd0;
parameter state_send = 4'd1;
parameter state_finish = 4'd2;
input rstb, clk, mlb, start;
input [31:0] tdat; //transmit data
input [1:0] cdiv; //clock divider
input din;
output reg ss;
output reg sck;
output reg dout;
output reg done_r;
output reg [31:0] rdata; //received data
wire [4:0] mid;
reg [3:0] current_state, next_state;
reg [31:0] treg, rreg;
reg [31:0] rdata_next;
reg [31:0] nbit;
reg [ 4:0] cnt;
reg shift, clr;
reg done;
assign mid = 1;
//state transistion
always @(negedge clk or negedge rstb) begin
if (rstb == 0) done_r <= 1'b0;
else if (current_state == state_finish) done_r <= 1'b1;
else done_r <= 1'b0;
end
//state transistion
always @(negedge clk or negedge rstb) begin
if (rstb == 0) begin
current_state <= state_finish;
rdata <= 0;
end else begin
current_state <= next_state;
rdata <= rdata_next;
end
end
//FSM i/o
always @(start or current_state or nbit or cdiv or rreg or rdata) begin
clr = 0;
shift = 0;
ss = 1;
// done = 0;
rdata_next = rdata;
next_state = current_state;
/* case (cdiv) // clk divider for spi sck
2'b00: mid = 2;
2'b01: mid = 4;
2'b10: mid = 8;
2'b11: mid = 131;
endcase*/
case (current_state)
state_idle: begin // 2'b00 = 0
#1 // to avoid infinite simulation loop
if (start == 1) begin
shift = 1;
next_state = state_send;
end
end
state_send: begin // 2'b10 = 2
ss = 0;
if (nbit != 32) begin
shift = 1;
end else begin
rdata_next = rreg;
// done = 1'b1;
// next_state = state_wait_1;
next_state = state_finish;
end
end
state_finish: begin // 2'b11 = 3
shift = 0;
ss = 1;
clr = 1;
// done = 1'b1;
next_state = state_idle;
end
default: next_state = state_finish;
endcase
end
//setup falling edge (shift dout) sample rising edge (read din)
always @(negedge clk or posedge clr) begin
if (clr == 1) begin
cnt = 5'd0;
sck = 0;
end else begin
if (shift == 1) begin
cnt = cnt + 5'd1;
if (cnt == mid) begin
sck = ~sck;
cnt = 5'd0;
end
end
end
end
//sample @ rising edge (read din)
always @(negedge sck or posedge clr) begin // or negedge rstb
if (clr == 1) begin
nbit = 7'd0;
rreg = 32'hFFFF_FFFF;
end else begin
if (mlb == 0) begin //LSB first, din @ msb -> right shift
rreg = {din, rreg[31:1]};
end else begin //MSB first, din @ lsb -> left shift
rreg = {rreg[30:0], din};
end
nbit = nbit + 7'd1;
end
end
// shift dout @ falling edge (write dout)
always @(posedge sck or posedge clr) begin
if (clr == 1) begin
treg = 32'h0;
dout = 0;
end else begin
if (nbit == 0) begin //load data into TREG
treg = tdat;
dout = mlb ? treg[31] : treg[0];
end //nbit_if
else begin
if (mlb == 0) begin //LSB first, shift right
treg = {1'b1, treg[31:1]};
dout = treg[0];
end else begin //MSB first shift LEFT
treg = {treg[30:0], 1'b1};
dout = treg[31];
end
end
end
end
endmodule
| 8.21649 |
module spi_master_7 (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 3'h5;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
localparam IDLE_state = 1'd0;
localparam TRANSFER_state = 1'd1;
reg M_state_d, M_state_q = IDLE_state;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg [4:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg [2:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_mosi_reg_d = M_mosi_reg_q;
M_sck_reg_d = M_sck_reg_q;
M_data_d = M_data_q;
M_ctr_d = M_ctr_q;
new_data = 1'h0;
busy = M_state_q != IDLE_state;
data_out = M_data_q;
sck = ((1'h0 ^ M_sck_reg_q[4+0-:1]) & (M_state_q == TRANSFER_state)) ^ 1'h0;
mosi = M_mosi_reg_q;
case (M_state_q)
IDLE_state: begin
M_sck_reg_d = 1'h0;
M_ctr_d = 1'h0;
if (start) begin
M_data_d = data_in;
M_state_d = TRANSFER_state;
end
end
TRANSFER_state: begin
M_sck_reg_d = M_sck_reg_q + 1'h1;
if (M_sck_reg_q == 1'h0) begin
M_mosi_reg_d = M_data_q[7+0-:1];
end else begin
if (M_sck_reg_q == 4'hf) begin
M_data_d = {M_data_q[0+6-:7], miso};
end else begin
if (M_sck_reg_q == 5'h1f) begin
M_ctr_d = M_ctr_q + 1'h1;
if (M_ctr_q == 3'h7) begin
M_state_d = IDLE_state;
new_data = 1'h1;
end
end
end
end
end
endcase
end
always @(posedge clk) begin
M_data_q <= M_data_d;
M_sck_reg_q <= M_sck_reg_d;
M_mosi_reg_q <= M_mosi_reg_d;
M_ctr_q <= M_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 8.048569 |
module spi_master_clkgen (
clk,
rstn,
en,
clk_div,
clk_div_valid,
spi_clk,
spi_fall,
spi_rise
);
input wire clk;
input wire rstn;
input wire en;
input wire [7:0] clk_div;
input wire clk_div_valid;
output reg spi_clk;
output reg spi_fall;
output reg spi_rise;
reg [7:0] counter_trgt;
reg [7:0] counter_trgt_next;
reg [7:0] counter;
reg [7:0] counter_next;
reg spi_clk_next;
reg running;
always @(*) begin
spi_rise = 1'b0;
spi_fall = 1'b0;
if (clk_div_valid) counter_trgt_next = clk_div;
else counter_trgt_next = counter_trgt;
if (counter == counter_trgt) begin
counter_next = 0;
spi_clk_next = ~spi_clk;
if (spi_clk == 1'b0) spi_rise = running;
else spi_fall = running;
end else begin
counter_next = counter + 1;
spi_clk_next = spi_clk;
end
end
always @(posedge clk or negedge rstn)
if (rstn == 1'b0) begin
counter_trgt <= 'h0;
counter <= 'h0;
spi_clk <= 1'b0;
running <= 1'b0;
end else begin
counter_trgt <= counter_trgt_next;
if (!((spi_clk == 1'b0) && ~en)) begin
running <= 1'b1;
spi_clk <= spi_clk_next;
counter <= counter_next;
end else running <= 1'b0;
end
endmodule
| 7.372709 |
module spi_master_ctrl (
input clk,
input reset,
input wr,
input rd,
input [7:0] addr,
input [7:0] cpu_di,
output reg [7:0] cpu_do,
input [7:0] rxData,
input rxDataRdySet,
output reg [7:0] txData,
output reg txDataFull,
input txDataFullClr,
input txDataEmpty,
output reg spiSS0,
output reg spiSS1,
output reg spiSS2,
output reg spiSS3,
output reg [7:0] clkDelay
);
reg rxDataRdy;
reg spiSS;
reg [1:0] spiDevNum;
always @(posedge clk) begin
spiSS0 <= 0;
spiSS1 <= 0;
spiSS2 <= 0;
spiSS3 <= 0;
if (spiSS)
case (spiDevNum)
0: spiSS0 <= 1;
1: spiSS1 <= 1;
2: spiSS2 <= 1;
3: spiSS3 <= 1;
endcase
end
always @(posedge clk) begin
if (reset) begin
cpu_do <= 0;
rxDataRdy <= 0;
txDataFull <= 0;
spiSS <= 0;
spiDevNum <= 0;
clkDelay <= 8'h30;
end else begin
cpu_do <= 0;
if (rxDataRdySet) rxDataRdy <= 1;
if (txDataFullClr) txDataFull <= 0;
case (addr[1:0])
0: begin
if (rd) begin
cpu_do <= rxData;
rxDataRdy <= 0;
end
if (wr) begin
txData <= cpu_di;
txDataFull <= 1;
end
end
1: begin
if (rd) begin
cpu_do[0] <= spiSS;
cpu_do[1] <= rxDataRdy;
cpu_do[2] <= txDataFull;
cpu_do[3] <= txDataEmpty;
cpu_do[5:4] <= spiDevNum;
end
if (wr) begin
spiSS <= cpu_di[0];
spiDevNum <= cpu_di[5:4];
end
end
2: begin
if (rd) begin
cpu_do <= clkDelay;
end
if (wr) begin
clkDelay <= cpu_di;
end
end
endcase
end
end
endmodule
| 6.679552 |
module spi_master_driver (
input clk_i,
input rst_i,
// system interface
input start_i, // signal to start transaction
input [7:0] data_in_bi, // data that master will write to slave
output reg busy_o, // transaction is being processed
output reg [7:0] data_out_bo, // data recevied from slave in last transaction
// SPI interface
input spi_cs_i,
input spi_miso_i,
output reg spi_mosi_o,
output reg spi_sclk_o
);
localparam CLK_NOPS = 1;
reg in_progress;
reg [2:0] counter;
reg [7:0] clk_div;
reg clk_div_pulse;
reg [7:0] shiftreg;
reg bit_buffer;
localparam STATE_IDLE = 0; // wait for transaction begin
localparam STATE_WAIT_SCLK_1 = 1; // wait for SCLK to become 1
localparam STATE_WAIT_SCLK_0 = 2; // wait for SCLK to become 0
localparam STATE_WAIT_IDLE = 3; // wait one SCLK and swith to idle
reg [2:0] state;
always @(posedge clk_i) begin
if (rst_i) begin
counter <= 0;
shiftreg <= 0;
bit_buffer <= 0;
in_progress <= 0;
clk_div <= 0;
clk_div_pulse <= 0;
state <= STATE_IDLE;
end else begin
case (state)
STATE_IDLE: begin
if (start_i) begin
in_progress = 1;
shiftreg <= data_in_bi;
state <= STATE_WAIT_SCLK_1;
clk_div <= 0;
end else begin
in_progress = 0;
end
end
STATE_WAIT_SCLK_1: begin
if (clk_div == CLK_NOPS) begin
bit_buffer <= spi_miso_i;
state <= STATE_WAIT_SCLK_0;
clk_div <= 0;
clk_div_pulse <= ~clk_div_pulse;
end else begin
clk_div <= clk_div + 1;
end
end
STATE_WAIT_SCLK_0: begin
if (clk_div == CLK_NOPS) begin
shiftreg <= {bit_buffer, shiftreg[7:1]};
if (counter == 7) begin
in_progress <= 0;
state <= STATE_WAIT_IDLE;
counter <= 0;
end else begin
state <= STATE_WAIT_SCLK_1;
counter <= counter + 1;
end
clk_div <= 0;
clk_div_pulse <= ~clk_div_pulse;
end else begin
clk_div <= clk_div + 1;
end
end
STATE_WAIT_IDLE: begin
if (clk_div == CLK_NOPS) begin
state <= STATE_IDLE;
clk_div <= 0;
clk_div_pulse <= 0;
end else begin
clk_div <= clk_div + 1;
end
end
default: begin
state <= STATE_IDLE;
end
endcase
end
end
always @* begin
busy_o = (state != STATE_IDLE);
data_out_bo = shiftreg;
spi_sclk_o = clk_div_pulse && !spi_cs_i;
if (in_progress) spi_mosi_o = shiftreg[0] && !spi_cs_i;
else spi_mosi_o = 0;
end
endmodule
| 7.596245 |
module spi_master_fifo #(
parameter DATA_WIDTH = 32,
parameter BUFFER_DEPTH = 2,
parameter LOG_BUFFER_DEPTH = `log2(BUFFER_DEPTH)
) (
clk_i,
rst_ni,
clr_i,
elements_o,
data_o,
valid_o,
ready_i,
valid_i,
data_i,
ready_o
);
//parameter DATA_WIDTH = 32;
//parameter BUFFER_DEPTH = 2;
//parameter LOG_BUFFER_DEPTH = (BUFFER_DEPTH < 1 ? 0 : (BUFFER_DEPTH < 2 ? 1 : (BUFFER_DEPTH < 4 ? 2 : (BUFFER_DEPTH < 8 ? 3 : (BUFFER_DEPTH < 16 ? 4 : (BUFFER_DEPTH < 32 ? 5 : (BUFFER_DEPTH < 64 ? 6 : (BUFFER_DEPTH < 128 ? 7 : (BUFFER_DEPTH < 256 ? 8 : (BUFFER_DEPTH < 512 ? 9 : (BUFFER_DEPTH < 1024 ? 10 : (BUFFER_DEPTH < 2048 ? 11 : (BUFFER_DEPTH < 4096 ? 12 : (BUFFER_DEPTH < 8192 ? 13 : (BUFFER_DEPTH < 16384 ? 14 : (BUFFER_DEPTH < 32768 ? 15 : (BUFFER_DEPTH < 65536 ? 16 : (BUFFER_DEPTH < 131072 ? 17 : (BUFFER_DEPTH < 262144 ? 18 : (BUFFER_DEPTH < 524288 ? 19 : (BUFFER_DEPTH < 1048576 ? 20 : (BUFFER_DEPTH < 2097152 ? 21 : (BUFFER_DEPTH < 4194304 ? 22 : (BUFFER_DEPTH < 8388608 ? 23 : (BUFFER_DEPTH < 16777216 ? 24 : 25)))))))))))))))))))))))));
input wire clk_i;
input wire rst_ni;
input wire clr_i;
output wire [LOG_BUFFER_DEPTH:0] elements_o;
output wire [DATA_WIDTH - 1:0] data_o;
output wire valid_o;
input wire ready_i;
input wire valid_i;
input wire [DATA_WIDTH - 1:0] data_i;
output wire ready_o;
reg [LOG_BUFFER_DEPTH - 1:0] pointer_in;
reg [LOG_BUFFER_DEPTH - 1:0] pointer_out;
reg [LOG_BUFFER_DEPTH:0] elements;
reg [DATA_WIDTH - 1:0] buffer[BUFFER_DEPTH - 1:0];
wire full;
integer loop1;
assign full = elements == BUFFER_DEPTH;
assign elements_o = elements;
always @(posedge clk_i or negedge rst_ni) begin : elements_sequential
if (rst_ni == 1'b0) elements <= 0;
else if (clr_i) elements <= 0;
else if ((ready_i && valid_o) && (!valid_i || full)) elements <= elements - 1;
else if (((!valid_o || !ready_i) && valid_i) && !full) elements <= elements + 1;
end
always @(posedge clk_i or negedge rst_ni) begin : buffers_sequential
if (rst_ni == 1'b0) begin
for (loop1 = 0; loop1 < BUFFER_DEPTH; loop1 = loop1 + 1) buffer[loop1] <= 0;
end else if (valid_i && !full) buffer[pointer_in] <= data_i;
end
always @(posedge clk_i or negedge rst_ni) begin : sequential
if (rst_ni == 1'b0) begin
pointer_out <= 0;
pointer_in <= 0;
end else if (clr_i) begin
pointer_out <= 0;
pointer_in <= 0;
end else begin
if (valid_i && !full)
if (pointer_in == $unsigned(BUFFER_DEPTH - 1)) pointer_in <= 0;
else pointer_in <= pointer_in + 1;
if (ready_i && valid_o)
if (pointer_out == $unsigned(BUFFER_DEPTH - 1)) pointer_out <= 0;
else pointer_out <= pointer_out + 1;
end
end
assign data_o = buffer[pointer_out];
assign valid_o = elements != 0;
assign ready_o = ~full;
endmodule
| 6.959157 |
module spi_master_model (
clk,
rst,
adr,
din,
dout,
wr,
rd
);
parameter dwidth = 8;
parameter awidth = 4;
input clk, rst;
output [awidth -1:0] adr;
input [dwidth -1:0] din;
output [dwidth -1:0] dout;
output wr, rd;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [awidth -1:0] adr;
reg [dwidth -1:0] dout;
reg wr, rd;
reg [dwidth -1:0] q;
always @(negedge rst) begin
if (!rst) begin
adr = {awidth{1'bz}};
dout = {dwidth{1'bz}};
wr = 1'b0;
rd = 1'b0;
end
end
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
/*
initial
begin
//adr = 32'hxxxx_xxxx;
//adr = 0;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
wr = 1'b0;
rd = 1'b0;
#1;
$display("\nINFO: SPI MASTER MODEL INSTANTIATED (%m)\n");
end
*/
////////////////////////////////////////////////////////////////////
//
// Wishbone write cycle
//
task wb_write;
input delay;
//integer delay;
input [awidth -1:0] a;
input [dwidth -1:0] d;
begin
// wait initial delay
repeat (delay) @(negedge clk);
adr = a;
dout = d;
wr = 1'b1;
rd = 1'b0;
@(negedge clk);
// negate wishbone signals
#1;
wr = 1'b0;
rd = 1'b0;
end
endtask
////////////////////////////////////////////////////////////////////
//
// Wishbone read cycle
//
task wb_read;
input delay;
//integer delay;
input [awidth -1:0] a;
output [dwidth -1:0] d;
begin
// wait initial delay
repeat (delay) @(negedge clk);
adr = a;
dout = {dwidth{1'bx}};
wr = 1'b0;
rd = 1'b1;
@(negedge clk);
// negate wishbone signals
#1;
wr = 1'b0;
rd = 1'b0;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
d = din;
end
endtask
endmodule
| 7.276598 |
module must be run for a clock cycle count
// of at least (DATABITSZ * (1 << (SCLKDIVLIMIT-1))) with "stb_i" low.
module spi_master_phy (
clk_i
,sclk_o ,mosi_o ,miso_i ,cs_o
,stb_i ,rdy_o ,rcvd_o ,sclkdiv_i
,data_o ,data_i
);
`include "lib/clog2.v"
parameter DATABITSZ = 2;
parameter SCLKDIVLIMIT = 1;
localparam CLOG2DATABITSZ = clog2(DATABITSZ);
localparam CLOG2SCLKDIVLIMIT = clog2(SCLKDIVLIMIT);
input wire clk_i;
output wire sclk_o;
output wire mosi_o;
input wire miso_i;
output reg cs_o = 1'b1;
input wire stb_i;
output wire rdy_o;
output wire rcvd_o;
input wire [CLOG2SCLKDIVLIMIT -1 : 0] sclkdiv_i;
output reg [DATABITSZ -1 : 0] data_o;
input wire [DATABITSZ -1 : 0] data_i;
// Register holding bits used to set the output "mosi_o".
reg [DATABITSZ -1 : 0] mosibits = {DATABITSZ{1'b1}};
// Register used to keep track of the number of clock cycles.
reg [SCLKDIVLIMIT : 0] cntr = 0;
// Register which is used to keep track
// of the number of bits left to transmit.
reg [CLOG2DATABITSZ -1 : 0] bitcnt = 0;
assign rdy_o = !bitcnt;
wire [CLOG2SCLKDIVLIMIT -1 : 0] sclkdiv_w;
wire [CLOG2SCLKDIVLIMIT -1 : 0] sclkdiv_w_minus_one = (sclkdiv_w-1);
assign sclkdiv_w = ((sclkdiv_i < 1) ? 1 : sclkdiv_i);
assign sclk_o = cntr[sclkdiv_w_minus_one];
assign mosi_o = mosibits[DATABITSZ -1];
// Register used to detect a falling edge on "rdy_o".
reg rdy_o_sampled = 1;
// This logic set the net rdy_o_negedge to 1
// when the falling edge of "rdy_o" occurs.
wire rdy_o_negedge = (rdy_o < rdy_o_sampled);
// Register used to detect a falling/rising edge on "cs_o".
reg cs_o_sampled = 1;
wire cs_o_negedge = (cs_o < cs_o_sampled);
wire cs_o_posedge = (cs_o > cs_o_sampled);
// Data has been received when either of the following condition occurs:
// - A falling edge on "rdy_o";
// in this condition, data has been received only if there was no
// falling edge on "cs_o", otherwise it means that the transmission
// just started and data still has yet to be received.
// - A rising edge on "cs_o".
//
// "rcvd_o" is high only for a single clock cycle since
// rdy_o_sampled and cs_o_sampled are updated every clock cycles.
assign rcvd_o = ((rdy_o_negedge && !cs_o_negedge) || cs_o_posedge);
always @ (posedge clk_i) begin
if (!cs_o && (cntr == (({{SCLKDIVLIMIT{1'b0}}, 1'b1} << sclkdiv_w_minus_one) -1)))
data_o <= {data_o[DATABITSZ -2 : 0], miso_i};
// When the output "cs_o" is low, this block executes only
// after every clock cycle count of ((1 << sclkdiv_w) -1);
// when the output "cs_o" is high, this block executes every clock cycle.
// ">=" is used so that the register "cntr" gets correctly wrapped
// around when "sclkdiv_w" is suddently set to a value that makes
// the register "cntr" greater than or equal to ((1 << sclkdiv_w) -1).
if (cs_o || (cntr >= (({{SCLKDIVLIMIT{1'b0}}, 1'b1} << sclkdiv_w) -1))) begin
if (bitcnt)
mosibits <= (mosibits << 1);
else
mosibits <= data_i;
if (bitcnt)
bitcnt <= bitcnt - 1'b1;
else if (stb_i)
bitcnt <= (DATABITSZ -1);
cs_o <= !(bitcnt || stb_i);
cntr <= 0;
end else
cntr <= cntr + 1'b1;
rdy_o_sampled <= rdy_o;
cs_o_sampled <= cs_o;
end
endmodule
| 6.817562 |
module spi_master_reduced (
clk,
rst_n,
spi_miso,
spi_mosi,
spi_clk,
spi_tx_en,
spi_rx_en,
mode_select,
receive_status
);
parameter DATA_LENGTH = 64;
input clk;
input rst_n;
input spi_miso;
output spi_mosi;
output spi_clk;
input spi_tx_en;
output receive_status;
input spi_rx_en;
input mode_select;
reg [8:0] data_count;
reg [7:0] recv_detect;
reg [7:0] spi_tx_db;
reg [4:0] cnt8;
reg spi_clkr;
reg spi_mosir;
reg spi_mosir1;
reg receive_status;
reg [7:0] spi_rx_dbr;
reg [7:0] spi_rx_dbr1;
wire [7:0] spi_rx_db;
wire [4:0] mode_reg;
wire [4:0] start_reg;
/***********************************************************************
*detect spi mode
***********************************************************************/
assign mode_reg = mode_select ? 5'd18 : 5'd17;
assign start_reg = mode_select ? 5'd1 : 5'd0;
/***********************************************************************
*control the spi timimg
***********************************************************************/
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt8 <= 5'd0;
data_count <= 9'h0;
spi_tx_db <= 8'h0;
recv_detect <= 8'h0;
end else if ((spi_tx_en || spi_rx_en) && ((data_count < DATA_LENGTH))) begin
if (cnt8 < mode_reg) cnt8 <= cnt8 + 1'b1;
else begin
if (spi_tx_en && spi_rx_en) begin
cnt8 <= 5'd0;
data_count <= data_count + 1'b1;
spi_tx_db <= spi_tx_db + 1'b1;
recv_detect <= (spi_rx_db == data_count) ? (recv_detect + 1'b1) : recv_detect;
end else begin
if (spi_tx_en) begin
cnt8 <= 5'd0;
data_count <= data_count + 1'b1;
spi_tx_db <= spi_tx_db + 1'b1;
end else begin
cnt8 <= 5'd0;
data_count <= data_count + 1'b1;
recv_detect <= (spi_rx_db == data_count) ? (recv_detect + 1'b1) : recv_detect;
end
end
end
end else begin
cnt8 <= 5'd0;
data_count <= data_count;
end
end
/***********************************************************************
*generate spi clk
***********************************************************************/
always @(posedge clk or negedge rst_n) begin
if (!rst_n) spi_clkr <= mode_select ? 1'b1 : 1'b0;
else if (cnt8 > start_reg && cnt8 < mode_reg) spi_clkr <= ~spi_clkr;
else spi_clkr <= spi_clkr;
end
assign spi_clk = spi_clkr;
/***********************************************************************
*spi master output data
***********************************************************************/
always @(posedge clk or negedge rst_n) begin
if (!rst_n) spi_mosir <= 1'b1;
else if (spi_tx_en) begin
case (cnt8[4:1])
4'd0: spi_mosir <= spi_tx_db[7];
4'd1: spi_mosir <= spi_tx_db[6];
4'd2: spi_mosir <= spi_tx_db[5];
4'd3: spi_mosir <= spi_tx_db[4];
4'd4: spi_mosir <= spi_tx_db[3];
4'd5: spi_mosir <= spi_tx_db[2];
4'd6: spi_mosir <= spi_tx_db[1];
4'd7: spi_mosir <= spi_tx_db[0];
default: spi_mosir <= 1'b1;
endcase
end else spi_mosir <= 1'b1;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) spi_mosir1 <= 1'b1;
else if (spi_tx_en) begin
case (cnt8[4:1])
4'd1: spi_mosir1 <= spi_tx_db[7];
4'd2: spi_mosir1 <= spi_tx_db[6];
4'd3: spi_mosir1 <= spi_tx_db[5];
4'd4: spi_mosir1 <= spi_tx_db[4];
4'd5: spi_mosir1 <= spi_tx_db[3];
4'd6: spi_mosir1 <= spi_tx_db[2];
4'd7: spi_mosir1 <= spi_tx_db[1];
4'd8: spi_mosir1 <= spi_tx_db[0];
default: spi_mosir1 <= 1'b1;
endcase
end else spi_mosir1 <= 1'b1;
end
assign spi_mosi = mode_select ? spi_mosir1 : spi_mosir;
endmodule
| 7.240007 |
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