code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module spi_master_sim //SPI0
(
output wire sclk,
output wire ss_n,
output wire mosi,
input wire miso,
input wire din_en,
input wire [31:0] din,
output wire dout_en,
output wire [15:0] dout
);
localparam PERIOD = 10;
clk_gen #(
.PERIOD (PERIOD * 30),
... | 8.842287 |
module
*
*********1*********2*********3*********4*********5*********6*********7*********/
module spi_master_top(
Clk
,Rst_n
,Wr
,Rd
,Addr
,DataIn
,DataOut
,SCLK
,MOSI
,MISO
,SS
,Int
,spi_cpol_debug
,spi_cpha_debug
);
parameter SIZE = 8;
input Clk; // Clock
input ... | 6.861976 |
module spi_model #(
parameter DW = 32,
parameter CPOL = 0,
parameter integer ID = 0
) (
input [DW-1:0] ROM,
input cs,
input sck,
input copi,
output cipo
);
reg [DW-1:0] shift = 0;
/* verilator lint_save */
/* verilator lint_off MULTIDRIVEN */
reg [5:0] cnt = 0;
/* verilator lin... | 6.782942 |
module spi_mon_tb;
localparam SIM_TIME = 500000; // ns
reg clk = 0;
integer fd, ix, rc;
reg en = 0;
reg [8:0] maddr = 0;
reg [7:0] mdat;
reg mwe = 0;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("spi_mon.vcd");
$dumpvars(5, spi_mon_tb);
end
fd = $fopen("spi_mon.... | 6.984381 |
module spi_msg #(
parameter nrRWregs = 4,
parameter nrROregs = 12
) // nrRWregs + nrROregs should be <= 16
(
input wire sysClk, // FPGA system clock (must be several times faster as SCLK, e.g. 66MHz)
input wire usrReset, // FPGA user reset button
input wire SCLK, // SPI clock (e.g. 4 MHz)
in... | 7.05648 |
module spi_msg_wb #(
parameter [7:0] CMD_BYTE = 8'h10
) (
// Wishbone interface
input wire [31:0] wb_wdata,
output reg [31:0] wb_rdata,
input wire [ 1:0] wb_addr,
input wire wb_we,
input wire wb_cyc,
output reg wb_ack,
// SPI protocol wrapper interface
... | 8.428155 |
module SPI_mstr (
clk,
rst_n,
SS_n,
SCLK,
command,
MISO,
wrt_cmd,
done,
resp,
MOSI
);
input clk, rst_n;
input wrt_cmd; //Input to Master to initiate SPI transaction
// input RDY; // Input fro slave saying response to previous command is ready
... | 8.236484 |
module SPI_TestBench ();
reg [7:0] data_in;
wire [7:0] data_out;
initial data_in = 0;
reg clock;
initial clock = 0;
always #(1) clock <= ~clock;
wire rst;
wire SCK, MO, CS;
reg data_in_valid, MI;
initial data_in_valid = 0;
initial MI = 0;
wire data_out_valid;
SPI_slave spi_s (
.SCK(S... | 7.278138 |
module spi_oled #(
parameter integer CLOCK_FREQ_HZ = 0,
parameter integer CS_LENGTH = 32
) (
input clk,
input resetn,
input ctrl_wr,
input ctrl_rd,
input [7:0] ctrl_addr,
input [31:0] ctrl_wdat,
output reg [31:0] ctrl_rdat,
output reg ctrl_done,
inout mosi,
sclk,
cs... | 7.090459 |
module spi_osd #(
parameter [7:0] c_addr_enable = 8'hFE, // high addr byte of enable byte
parameter [7:0] c_addr_display = 8'hFD, // high addr byte of display data, +0x10000 for inverted
parameter c_start_x = 64, // x1 pixel window h-position
parameter c_start_y = 48, // x1 pixel window v-position... | 8.360593 |
module spi_pack #(
parameter BASE_ADDR = 8'h00,
parameter BASE2_ADDR = 8'h00 // Takes 1 BASE2 slot at BASE2_ADDR
) (
input clk,
input rst,
// Hardware interface
output spi_cs, // active low chip select
output spi_sck, // serial clock
outp... | 8.56925 |
module spi_passthrough (
input wire iCLK,
input wire RSTin,
input wire ID_in,
input wire IRQ_in,
input wire address_strobe,
input wire [6:0] currentSPIAddr,
input wire [6:0] setSPIAddr,
input wire SCLKin,
input wire SCSNin,
input wire MOSIin,
output wire MISOout,
out... | 7.988149 |
module.
// These SPI parameters are used in this module:
// CPOL = 0 (spi_clk idles low)
// CPHA = 0 (data clocked in on rising edge when CPOL is 1)
//
// Note: addr/wdat are synchronous to the SPI clock. we & re are synchronized
//
// A SPI transfer consists of 40 bits, MSB first.
// The first bit is read/write_n... | 8.233778 |
module spi_pg #(
parameter DW = 64,
parameter AS = 32,
parameter IDW = 8
) (
input spi_aclk,
input spi_aresetn,
input [IDW-1:0] spi_awid,
input [ AS-1:0] spi_awaddr,
input [ 1:0] spi_awlen,
input [ 2:0] spi_awsize,
input [ 1:0] spi_awburst,
input s... | 7.914416 |
module spi_phy (
input wire spi_cs,
input wire spi_clk,
input wire spi_mosi,
output reg spi_miso,
output reg spi_byte_o_en,
output reg [7:0] spi_byte_o,
input wire spi_byte_i_en,
input wire [7:0] spi_byte_i
);
// serial transfer index counter
reg [2:0] spi_bit_c... | 6.946697 |
module SPI_PINGPONG_top (
input clk,
input sck,
input ssel,
input rst_n,
input mosi,
output wire miso,
output wire DRDY
);
// SPI
wire byteReceived; // 在第八个sck_risingEdge置为1
wire [7:0] receivedData; // shift register
// wire dataNeeded; // MOSI ready信号
// // wire [7:0] dataToSe... | 7.532732 |
module SPI_PINGPONG_top_tb;
reg clk;
wire sck;
reg sck_ori;
reg rst_n;
wire mosi;
wire miso;
reg ssel;
wire ssel_active = ~ssel;
// wire readya1;
// wire byteReceived; // received a bit
wire DRDY;
parameter LOOPTIME = 256;
parameter PERIOD = 10; // must be even
parameter SCKPERIOD = ... | 7.532732 |
module implements a SPI port for use with ADI HSC SPI protocol.
// This version supports only 16-bit instruction phase, MSB transfers.
//
// Dependencies: spi_control.v, spi_decoder.v, spi_encoder.v
//
// Revision: 1.00
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////... | 6.904081 |
module spi_process (
input rst_n, //reset ,low active
input clk,
//spi_slave
input mosi,
input csb,
input sck,
output miso,
//internal_bus
input [15:0] reg_dout,
output reg spi_req,
input ... | 8.100182 |
module spi (
input wire clk, //
input wire clken, //
input wire enviar_dato, // a 1 para indicar que queremos enviar un dato por SPI
input wire recibir_dato, // a 1 para indicar que queremos recibir un dato
input wire [7:0] din, // del bus de datos de salida de la CPU
output reg [7:0] dout... | 7.760909 |
module spi_ram_btn #(
parameter [7:0] c_addr_btn = 8'hFB, // high addr byte of BTNs
parameter [7:0] c_addr_irq = 8'hF1, // high addr byte of IRQ flag
parameter c_debounce_bits = 20, // more -> slower BTNs
parameter c_addr_bits = 32, // don't touch
parameter c_sclk_capable_pin = 0 //, // 0-sclk ... | 6.997779 |
module uses 24x iCE40 block-RAMs internally. In the iCE40, block-RAMs
* have two independently clocked ports, with one read-only port and one
* write-only port. Therefore, the read-port is clocked by the pixel clock,
* while the read-port
*/
module spi_ram_slave(clk, sck, cs, mosi, ram_addr, ram_data, ram_wr);
loca... | 6.919368 |
module spi_rcv(CLK, SCK, MOSI, MISO, SSEL, LED);
input wire CLK, SCK, SSEL, MOSI;
output wire MISO, LED;
wire [7:0] MSG;
spi_slave spi1(.CLK(CLK),
.SCK(SCK),
.MOSI(MOSI),
.MISO(MISO),
.SSEL(SSEL),
.MSG(MSG));
assign LED = (MSG==8'b11111111);*/
module spi_rcv(... | 6.612991 |
module spi_receiver (
clock,
sclk,
extReset,
mosi,
cs,
transmitting,
// outputs...
op,
data,
execute
);
input clock;
input sclk;
input extReset;
input mosi;
input cs;
input transmitting;
output [7:0] op;
output [31:0] data;
output execute;
parameter READOPCO... | 7.263457 |
module spi_reg #(
parameter ADDR = 8'h00,
parameter integer BYTES = 1
) (
// Bus interface
input wire [7:0] addr,
input wire [7:0] data,
input wire first,
input wire strobe,
// Reset
input wire [(8*BYTES)-1:0] rst_val,
// Output
output wire [(8*BYTES)-1:0] out_val,
outp... | 7.046065 |
module SPI_ri (
input wire clk,
input wire reset,
input wire [1:0] a,
input wire ce,
input wire wren,
output wire spi_int,
output reg [7:0] to_cpu,
input wire [7:0] from_cpu,
output wire mosi,
input wire miso,
output wire sclk,
output wire [7:0] ncs
);
// Registers:
... | 6.775711 |
module SPI_rsvr (
//General Usage
input wire CLK,
input wire RST,
//Pmod Interface
input wire SDATA,
output reg SCLK,
output reg nCS,
//User Interface Signals
output reg [15:0] DATA,
input wire START,
output reg DONE
);
//--current_state : exectly current state of ... | 7.080609 |
module spi_rx_test ();
reg clk, reset_n, ss_n;
wire [7:0] data, adrs;
wire valid, sdi;
reg [15:0] shift_reg;
assign sdi = shift_reg[15];
initial begin
clk <= 0;
reset_n <= 0;
ss_n <= 0;
shift_reg <= 16'h51AB;
#21 reset_n <= 1;
end
parameter CLOCK_INT = 10;
always #(CLOCK_INT ... | 6.802184 |
module spi_s (
input i_clk,
input i_reset,
input i_spi_mosi,
input i_spi_cs_n,
input i_spi_clk,
output [7:0] o_rx_data,
output o_rx_dataValid
);
// Registers
reg r_spi_mosi;
reg r_spi_cs_n;
reg r_spi_clk;
reg r_prev_spi_clk;
reg r_prev_spi_nss;
reg [7:0] ... | 7.625664 |
module spi_sd (
input wire clk,
input wire spi_in,
output wire spi_out,
output wire cs,
output wire sck,
output wire led
);
zrb_sd_core #(8) spi_core (
clk,
8'b0,
1'b0,
spi_in,
1'b0
,,
led,
spi_out,
cs,
sck
);
endmodule
| 6.811218 |
module SPI_send (
input clk_50M, //50M
input rst_n,
input ENABLE,
input [15:0] DATA,
output reg CSB,
output SCLK,
output SDIN,
output DONE
);
reg [12:0] Divide_Cnt;
reg [3:0] Sel_Cnt;
reg clk_10K;
assign SCLK = (ENABLE) ? clk_10K : 0;
assign SDIN = (ENABLE) ? DATA[~Sel_Cnt] :... | 6.998533 |
module spi_sender (
input clk,
input sclk_posedge,
input sclk_negedge,
input reset,
input en,
input [DATA_BITS-1:0] data,
output reg out,
output ... | 7.210176 |
module spi_sequence_detector #(
parameter KEY = 64'h929d9a9b2935a265,
parameter KEY_SIZE = 64
) (
input wire clk,
input wire rst,
input wire sin,
input wire sclk,
output wire match
);
reg [KEY_SIZE - 1 - 1:0] bitstream;
reg sclk_prev;
reg match_reg;
wire [KEY_SIZE - 1:0] key;
... | 8.533479 |
module spi_serdes (
// Host side signals
input reset_n,
input spi_clk,
input spi_clk_out,
input [15:0] data_tx,
input start,
output done,
output reg [ 7:0] data_rx,
// SPI side signals
output SPI_SDI,
... | 7.584351 |
module spi_shift_in (
clk,
rst,
go,
pos_edge,
neg_edge,
rx_negedge,
tip,
last,
p_out,
s_clk,
s_in
);
parameter Tp = 1;
input clk; // system clock
input rst; // reset
// input [`SPI_ADC_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
input go; /... | 7.4541 |
module spi_shift_out (
clk,
rst,
len,
lsb,
go,
pos_edge,
neg_edge,
tx_negedge,
capture,
tip,
last,
p_in,
s_out
);
parameter Tp = 1;
input clk; // system clock
input rst; // reset
input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
input ... | 7.503529 |
module spi_simple (
// SPI pads
input wire spi_mosi,
output wire spi_miso,
input wire spi_cs_n,
input wire spi_clk,
// Interface
output wire [7:0] addr,
output wire [7:0] data,
output reg first,
output reg last,
output wire strobe,
input wire [7:0] out,
// Clock... | 7.87219 |
module spi_simple_io_in (
input wire pad,
output wire val,
output reg rise,
output reg fall,
input wire clk,
input wire rst
);
// Signals
wire iob_out;
reg val_i;
// IOB
SB_IO #(
.PIN_TYPE(6'b000000),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0),
.IO_STANDARD("SB_LV... | 6.608719 |
module spi_simple_io_out (
output wire pad,
input wire val,
input wire oe,
input wire clk,
input wire rst
);
SB_IO #(
.PIN_TYPE(6'b101001),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0),
.IO_STANDARD("SB_LVCMOS")
) miso_iob_I (
.PACKAGE_PIN(pad),
.CLOCK_ENABLE(1'b1),... | 6.608719 |
module SPI_Slave (
clk,
SCK,
SSEL,
MOSI,
MISO //SPI communication pin
);
input clk;
input SCK, SSEL, MOSI;
output MISO;
reg [7:0] mem;
assign MISO = MOSI;
always @(posedge SCK) begin
if (SSEL) begin
if (mem == 255) begin
mem <= 0;
end else begin
mem <... | 6.615248 |
module spi_slave_88 (
input clk,
input rst,
input ss,
input mosi,
output reg miso,
input sck,
output reg done,
input [7:0] data_in,
output reg [7:0] data_out
);
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
reg [2:0] M_bit_ct_d, M_bit_ct_q = 1'h0;
reg [7:0] M_data_d, M_d... | 6.539713 |
module will get 64 bytes and then return the count 64 at next clks
*******************************************************************************/
module spi_slave_b2b_reduced(
clk,sck,mosi,miso,ssel,rst_n,recived_status
);
input clk;
input rst_n;
input sck,mosi,ssel;
output miso;
output recived_status;
reg recived_... | 7.500858 |
module will get 64 bytes and then return the count 64 at next clks
*******************************************************************************/
module spi_slave_b2b_reduced(
clk,sck,mosi,miso,ssel,rst_n,recived_status
);
input clk;
input rst_n;
input sck,mosi,ssel;
output miso;
output recived_status;
reg recived_... | 7.500858 |
module spi_slave (
spi1_miso_io,
spi1_mosi_io,
spi1_sck_io,
spi1_scs_n_i,
spi1_mcs_n_o,
rst_i,
ipload_i,
ipdone_o,
sb_clk_i,
sb_wr_i,
sb_stb_i,
sb_adr_i,
sb_dat_i,
sb_dat_o,
sb_ack_o,
spi_pirq_o,
spi_pwkup_o
) /* synthesis syn_black_box syn_declare_bl... | 7.335456 |
module SPI_SLAVE_BOT_1_LATE_DATA_REFLECTOR #(
parameter CPHA =1, //clock phase
parameter CPOL =1, //clock polarity
parameter PACK_LENGTH =8, //number of bits in package
parameter PACK_BIT_SEQUENCE_TRANSMIT=1,//1-major bit forward;0-junior bit forward;
parameter PACK_BIT_SEQUENCE_RECEIVE=1//1... | 7.117769 |
module spi_slave_buffer (
input wire reset,
input wire clk,
input wire mosi,
output reg miso,
input wire sel,
output reg [7:0] buffer
);
always @(posedge clk or posedge reset) begin
if (reset) begin
buffer <= 8'h00;
miso <= 1'b0;
end else if (sel) begin
buffer ... | 6.811609 |
module spi_slave_cpha0 (
clk,
sck,
mosi,
miso,
ssel,
rst_n
);
input clk;
input rst_n;
input sck, mosi, ssel;
output miso;
reg recived_status;
reg [2:0] sckr;
reg [2:0] sselr;
reg [1:0] mosir;
reg [2:0] bitcnt;
reg [7:0] bytecnt;
reg byte_received; // high when a byte has... | 7.373032 |
module spi_slave_dc_fifo #(
parameter DATA_WIDTH = 32,
parameter BUFFER_DEPTH = 8
) (
clk_a,
rstn_a,
data_a,
valid_a,
ready_a,
clk_b,
rstn_b,
data_b,
valid_b,
ready_b
);
//parameter DATA_WIDTH = 32;
//parameter BUFFER_DEPTH = 8;
input wire clk_a;
input wire rstn... | 8.005999 |
module spi (
input wire iCLK,
input wire RST,
input wire SCLK,
input wire SCSN,
input wire MOSI,
output reg start_of_transfer,
output reg end_of_transfer,
output reg [7:0] mosi_data_out,
output reg mosi_data_ready,
output reg MISO,
output reg mi... | 7.760909 |
module spi_slave (
input wire reset,
input wire en,
input wire DATA_IN0,
input wire DATA_IN1,
input wire SCK,
input wire SSEL,
input wire clk,
// input [31:0] data32, //added feb03
//output MISO,
output wire [31:0] rx_out0,
output wire [31:0] rx_out1,
output wire rdy
)... | 7.335456 |
module spi_slave_model (
input wire csn;
input wire sck
input wire di;
output wire do
);
//
// Variable declaration
//
wire debug = 1'b1;
wire cpol = 1'b0;
wire cpha = 1'b0;
reg [7:0] mem [7:0]; // initiate memory
reg [2:0] mem_adr; // memory address
reg [7:0] mem_do; // memory data output
re... | 7.009262 |
module SPI_SLAVE_PWM #(
parameter CPHA = 1, //clock phase
parameter CPOL = 1, //clock polarity
parameter PACK_LENGTH = 8, //number of bits in package
parameter PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter PACK_BIT_SEQUENCE_RECEIVE = 1, //1-major bit for... | 7.872544 |
module spi_slave_r (
input rst,
input clk,
//fifo
input fifo_full,
output [7:0] fifo_d,
output fifo_w_en,
//spi slave
input sclk,
input sdin
);
//sck edge check
reg [1:0] sclk_edge = 2'b00;
always @(posedge clk) begin
if (!rst) begin
sclk_edge <= 2'b00;
end el... | 7.320152 |
module spi_slave_regs #(
parameter REG_SIZE = 8
) (
sclk,
rstn,
wr_data,
wr_addr,
wr_data_valid,
rd_data,
rd_addr,
dummy_cycles,
en_qpi,
wrap_length
);
//parameter REG_SIZE = 8;
input wire sclk;
input wire rstn;
input wire [REG_SIZE - 1:0] wr_data;
input wire [1:0] ... | 7.107196 |
module spi_slave_syncro #(
parameter AXI_ADDR_WIDTH = 32
) (
sys_clk,
rstn,
cs,
address,
address_valid,
rd_wr,
cs_sync,
address_sync,
address_valid_sync,
rd_wr_sync
);
//parameter AXI_ADDR_WIDTH = 32;
input wire sys_clk;
input wire rstn;
input wire cs;
input wire [A... | 7.177815 |
module spi_slave_tb ();
parameter N = 8;
integer i;
reg [N-1:0] din;
wire [N-1:0] dout;
reg [N-1:0] gotback;
reg [N-1:0] tosend;
wire miso;
reg mosi, sclk, ssbar;
task send;
input [N-1:0] dataout;
output [N-1:0] gotdata;
reg [N-1:0] temp;
begin
#10;
ssbar = 0;
fo... | 7.301482 |
module to test api slaves
//
// This allows SPI data to be sent and received
// from tests
module spi_slave_tester(
input wire clk,
input wire rst,
input wire sout,
output wire sin,
output wire sclk
);
integer period;
reg phase;
reg polarity;
task send;
... | 7.078078 |
module SPI_SM (
output reg latch_cmd,
output reg rd_select,
output reg wr_select,
input wire clk,
input wire [3:0] cmd,
input wire done,
input wire rst
);
// state bits
parameter IDLE = 3'b000, LATCH = 3'b001, READ = 3'b010, WRITE = 3'b011, WRITE_WAIT = 3'b100;
reg [2:0] state;
reg... | 7.946031 |
module spi_tb (
output reg SCK,
output reg CS,
output reg MOSI,
output reg FLAG,
output reg [7:0] readed,
input MISO
);
localparam PERIOD = 3.2; //312.5 MHz SoC
localparam PERIOD_SPI = 50; //20 MHz SPI SCK
//****** SEQUENCE OF STIMULUS ***********
initial begin
//**INITIAL VA... | 7.608779 |
module spi_sub (
input wire i_clk,
input wire i_reset_n,
// SPI bus
input wire i_spi_cs_n,
input wire i_spi_sck,
input wire i_spi_si,
output wire o_spi_so,
// shared
output wire [4:0] o_slave_addr,
output wire o_wr_req,
output wire [7:0] o_data_wr,
// slaves connections
... | 7.473618 |
module name:spi_switch
//file name: spi_switch.v
//version: 1.0
//author: zxc
//date: 2008.09.08
//function: spi switch control
///////////////////////////////////////////////////
//revision history
`timescale 1ns/1ns
module spi_switch (
rstb_i, //reset
... | 8.275824 |
module spi_synchronizer (
input clk,
input sck,
sdi,
cs,
output sck_out,
sdi_out,
cs_out
);
parameter integer SYNC_STAGES = 2;
parameter integer SYNC_MSB = SYNC_STAGES - 1;
reg [SYNC_MSB:0] sck_sync;
reg [SYNC_MSB:0] sdi_sync;
reg [SYNC_MSB:0] cs_sync;
assign sck_out = sck_s... | 6.67042 |
module SPI_TestBench();
wire [7:0] data_in;
reg [7:0] data_out;
initial data_out = 0;
reg [7:0]testdata;
initial testdata = 8'h1275;
reg clock;
initial clock = 0;
always #(1) clock <= ~clock;
wire rst;
reg SCK,MO,CS;
wire MI;
initial SCK = 1;
initial MO = 0;
i... | 7.278138 |
module spi_t (
input clk,
input rst,
input miso,
output mosi,
output sck,
input start,
input [7:0] data_in,
output [7:0] data_out,
output busy,
output new_data
);
localparam CLK_DIV = 2;
localparam STATE_SIZE = 2;
localparam IDLE = 2'd0, WAIT_HALF = 2'd1, TRANSFER = 2'd2;
... | 8.335937 |
module combining the SPI stack (SPI Minion, SPI Minion Adapter, and Loopthrough)
// that connects to the individual project group's block module. This was used for the
// efabless tapeout in Spring 2022.
//
// Author : Jack Brzozowski
// Date : May 9th, 2022
`include "SPI_v3/components/SPIstackVRTL.v"
`include "tap... | 9.386012 |
module SPI_v3_components_LoopThroughVRTL (
clk,
reset,
sel,
upstream_req_val,
upstream_req_msg,
upstream_req_rdy,
upstream_resp_val,
upstream_resp_msg,
upstream_resp_rdy,
downstream_req_val,
downstream_req_msg,
downstream_req_rdy,
downstream_resp_val,
downstream_r... | 7.522988 |
module ShiftReg (
clk,
in_,
load_data,
load_en,
out,
reset,
shift_en
);
parameter nbits = 8;
input wire clk;
input wire in_;
input wire [nbits - 1:0] load_data;
input wire load_en;
output reg [nbits - 1:0] out;
input wire reset;
input wire shift_en;
always @(posedge clk)
... | 8.65434 |
module SPI_v3_components_SPIMinionVRTL (
clk,
cs,
miso,
mosi,
reset,
sclk,
pull_en,
pull_msg,
push_en,
push_msg,
parity
);
parameter nbits = 8;
input wire clk;
input wire cs;
output wire miso;
input wire mosi;
input wire reset;
input wire sclk;
output wire pul... | 7.522988 |
module vc_Reg (
clk,
q,
d
);
parameter p_nbits = 1;
input wire clk;
output reg [p_nbits - 1:0] q;
input wire [p_nbits - 1:0] d;
always @(posedge clk) q <= d;
endmodule
| 7.27876 |
module vc_ResetReg (
clk,
reset,
q,
d
);
parameter p_nbits = 1;
parameter p_reset_value = 0;
input wire clk;
input wire reset;
output reg [p_nbits - 1:0] q;
input wire [p_nbits - 1:0] d;
always @(posedge clk) q <= (reset ? p_reset_value : d);
endmodule
| 6.831298 |
module vc_EnReg (
clk,
reset,
q,
d,
en
);
parameter p_nbits = 1;
input wire clk;
input wire reset;
output reg [p_nbits - 1:0] q;
input wire [p_nbits - 1:0] d;
input wire en;
always @(posedge clk) if (en) q <= d;
endmodule
| 7.427182 |
module vc_EnResetReg (
clk,
reset,
q,
d,
en
);
parameter p_nbits = 1;
parameter p_reset_value = 0;
input wire clk;
input wire reset;
output reg [p_nbits - 1:0] q;
input wire [p_nbits - 1:0] d;
input wire en;
always @(posedge clk) if (reset || en) q <= (reset ? p_reset_value : d);
end... | 7.207198 |
module vc_Mux2 (
in0,
in1,
sel,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
input wire sel;
output reg [p_nbits - 1:0] out;
always @(*)
case (sel)
1'd0: out = in0;
1'd1: out = in1;
default: out = {p_nbits{1'bx}};
end... | 7.493918 |
module vc_Mux3 (
in0,
in1,
in2,
sel,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
input wire [p_nbits - 1:0] in2;
input wire [1:0] sel;
output reg [p_nbits - 1:0] out;
always @(*)
case (sel)
2'd0: out = in0;
2'd1: out = i... | 7.892776 |
module vc_Mux4 (
in0,
in1,
in2,
in3,
sel,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
input wire [p_nbits - 1:0] in2;
input wire [p_nbits - 1:0] in3;
input wire [1:0] sel;
output reg [p_nbits - 1:0] out;
always @(*)
case (sel)... | 7.741558 |
module vc_Mux5 (
in0,
in1,
in2,
in3,
in4,
sel,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
input wire [p_nbits - 1:0] in2;
input wire [p_nbits - 1:0] in3;
input wire [p_nbits - 1:0] in4;
input wire [2:0] sel;
output reg [p_nbi... | 7.614878 |
module vc_Mux6 (
in0,
in1,
in2,
in3,
in4,
in5,
sel,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
input wire [p_nbits - 1:0] in2;
input wire [p_nbits - 1:0] in3;
input wire [p_nbits - 1:0] in4;
input wire [p_nbits - 1:0] in5;
... | 7.692722 |
module vc_Mux7 (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
input wire [p_nbits - 1:0] in2;
input wire [p_nbits - 1:0] in3;
input wire [p_nbits - 1:0] in4;
input wire [p_nbits - 1... | 7.845565 |
module vc_Mux8 (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
input wire [p_nbits - 1:0] in2;
input wire [p_nbits - 1:0] in3;
input wire [p_nbits - 1:0] in4;
input wire [p_... | 7.77376 |
module vc_MuxN (
in,
sel,
out
);
parameter p_nbits = 1;
parameter p_ninputs = 2;
input wire [(p_ninputs * p_nbits) - 1:0] in;
input wire [$clog2(p_ninputs) - 1:0] sel;
output wire [p_nbits - 1:0] out;
assign out = in[sel*p_nbits+:p_nbits];
endmodule
| 7.320871 |
module vc_Regfile_1r1w (
clk,
reset,
read_addr,
read_data,
write_en,
write_addr,
write_data
);
parameter p_data_nbits = 1;
parameter p_num_entries = 2;
parameter c_addr_nbits = $clog2(p_num_entries);
input wire clk;
input wire reset;
input wire [c_addr_nbits - 1:0] read_addr;
o... | 7.208433 |
module vc_ResetRegfile_1r1w (
clk,
reset,
read_addr,
read_data,
write_en,
write_addr,
write_data
);
parameter p_data_nbits = 1;
parameter p_num_entries = 2;
parameter p_reset_value = 0;
parameter c_addr_nbits = $clog2(p_num_entries);
input wire clk;
input wire reset;
input wire... | 6.956174 |
module vc_Regfile_2r1w (
clk,
reset,
read_addr0,
read_data0,
read_addr1,
read_data1,
write_en,
write_addr,
write_data
);
parameter p_data_nbits = 1;
parameter p_num_entries = 2;
parameter c_addr_nbits = $clog2(p_num_entries);
input wire clk;
input wire reset;
input wire [... | 6.740536 |
module vc_Regfile_2r2w (
clk,
reset,
read_addr0,
read_data0,
read_addr1,
read_data1,
write_en0,
write_addr0,
write_data0,
write_en1,
write_addr1,
write_data1
);
parameter p_data_nbits = 1;
parameter p_num_entries = 2;
parameter c_addr_nbits = $clog2(p_num_entries);
... | 6.740536 |
module vc_Regfile_2r1w_zero (
clk,
reset,
rd_addr0,
rd_data0,
rd_addr1,
rd_data1,
wr_en,
wr_addr,
wr_data
);
input wire clk;
input wire reset;
input wire [4:0] rd_addr0;
output wire [31:0] rd_data0;
input wire [4:0] rd_addr1;
output wire [31:0] rd_data1;
input wire wr_e... | 6.740536 |
module vc_QueueCtrl1 (
clk,
reset,
recv_val,
recv_rdy,
send_val,
send_rdy,
write_en,
bypass_mux_sel,
num_free_entries
);
parameter p_type = 4'b0000;
input wire clk;
input wire reset;
input wire recv_val;
output wire recv_rdy;
output wire send_val;
input wire send_rdy;
... | 7.312115 |
module vc_QueueCtrl (
clk,
reset,
recv_val,
recv_rdy,
send_val,
send_rdy,
write_en,
write_addr,
read_addr,
bypass_mux_sel,
num_free_entries
);
parameter p_type = 4'b0000;
parameter p_num_msgs = 2;
parameter c_addr_nbits = $clog2(p_num_msgs);
input wire clk;
input wi... | 6.52014 |
module vc_Queue (
clk,
reset,
recv_val,
recv_rdy,
recv_msg,
send_val,
send_rdy,
send_msg,
num_free_entries
);
parameter p_type = 4'b0000;
parameter p_msg_nbits = 1;
parameter p_num_msgs = 2;
parameter c_addr_nbits = $clog2(p_num_msgs);
input wire clk;
input wire reset;
... | 7.520267 |
module SPI_v3_components_SPIMinionAdapterVRTL (
clk,
reset,
pull_en,
pull_msg_val,
pull_msg_spc,
pull_msg_data,
push_en,
push_msg_val_wrt,
push_msg_val_rd,
push_msg_data,
recv_msg,
recv_rdy,
recv_val,
send_msg,
send_rdy,
send_val,
parity
);
parameter... | 7.522988 |
module SPI_v3_components_SPIMinionAdapterCompositeVRTL (
clk,
cs,
miso,
mosi,
reset,
sclk,
recv_msg,
recv_rdy,
recv_val,
send_msg,
send_rdy,
send_val,
minion_parity,
adapter_parity
);
parameter nbits = 8;
parameter num_entries = 1;
input wire clk;
input wi... | 7.522988 |
module SPI_v3_components_SPIstackVRTL (
clk,
reset,
loopthrough_sel,
minion_parity,
adapter_parity,
sclk,
cs,
mosi,
miso,
send_val,
send_msg,
send_rdy,
recv_val,
recv_msg,
recv_rdy
);
parameter nbits = 34;
parameter num_entries = 1;
input wire clk;
inp... | 7.522988 |
module tapeout_BlockPlaceholderVRTL (
send_val,
send_msg,
send_rdy,
recv_val,
recv_msg,
recv_rdy
);
parameter nbits = 32;
output wire send_val;
output wire [nbits - 1:0] send_msg;
input wire send_rdy;
input wire recv_val;
input wire [nbits - 1:0] recv_msg;
output wire recv_rdy;
a... | 7.853688 |
module vc_Adder (
in0,
in1,
cin,
out,
cout
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
input wire cin;
output wire [p_nbits - 1:0] out;
output wire cout;
assign {cout, out} = (in0 + in1) + {{p_nbits - 1{1'b0}}, cin};
endmodule
| 8.30696 |
module vc_SimpleAdder (
in0,
in1,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
output wire [p_nbits - 1:0] out;
assign out = in0 + in1;
endmodule
| 8.112602 |
module vc_Subtractor (
in0,
in1,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
output wire [p_nbits - 1:0] out;
assign out = in0 - in1;
endmodule
| 7.776575 |
module vc_Incrementer (
in,
out
);
parameter p_nbits = 1;
parameter p_inc_value = 1;
input wire [p_nbits - 1:0] in;
output wire [p_nbits - 1:0] out;
assign out = in + p_inc_value;
endmodule
| 8.657353 |
module vc_ZeroExtender (
in,
out
);
parameter p_in_nbits = 1;
parameter p_out_nbits = 8;
input wire [p_in_nbits - 1:0] in;
output wire [p_out_nbits - 1:0] out;
assign out = {{p_out_nbits - p_in_nbits{1'b0}}, in};
endmodule
| 8.062945 |
module vc_SignExtender (
in,
out
);
parameter p_in_nbits = 1;
parameter p_out_nbits = 8;
input wire [p_in_nbits - 1:0] in;
output wire [p_out_nbits - 1:0] out;
assign out = {{p_out_nbits - p_in_nbits{in[p_in_nbits-1]}}, in};
endmodule
| 8.543095 |
module vc_ZeroComparator (
in,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in;
output wire out;
assign out = in == {p_nbits{1'b0}};
endmodule
| 8.972309 |
module vc_EqComparator (
in0,
in1,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
output wire out;
assign out = in0 == in1;
endmodule
| 8.385225 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.