code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module spi_master_sim //SPI0
(
output wire sclk,
output wire ss_n,
output wire mosi,
input wire miso,
input wire din_en,
input wire [31:0] din,
output wire dout_en,
output wire [15:0] dout
);
localparam PERIOD = 10;
clk_gen #(
.PERIOD (PERIOD * 30),
.REST_VALUE(1'b0)
) sclk_gen (
.clk (sclk),
.rstn()
);
localparam IDLE = 2'd0;
localparam SEND = 2'd1;
localparam FINISH = 2'd3;
reg [ 1:0] state = IDLE;
reg ss_n_tmp = 1;
reg [31:0] din_lock;
reg [ 6:0] data_cnt = 6'd0;
reg mosi_tmp = 0;
reg [15:0] data_shift;
reg data_shift_en;
reg rd;
always @(negedge sclk)
case (state)
IDLE: begin
ss_n_tmp <= 1;
data_cnt <= 0;
data_shift <= 0;
data_shift_en <= 0;
if (din_en) begin
ss_n_tmp <= 0;
state <= SEND;
din_lock <= din;
rd <= din[31];
end
end
SEND: begin
data_cnt <= data_cnt + 1;
// mosi_tmp <= din_lock[31];
din_lock <= din_lock << 1;
if (data_cnt > 15) data_shift <= {data_shift[14:0], miso};
if (data_cnt == 6'd31) ss_n_tmp <= 1;
if (data_cnt == 6'd31) begin
state <= FINISH;
data_shift_en <= 1;
end
end
FINISH: begin
data_shift_en <= 0;
state <= IDLE;
end
default: ;
endcase
assign ss_n = ss_n_tmp;
assign mosi = din_lock[31];
assign dout_en = data_shift_en;
assign dout = data_shift;
endmodule
| 8.842287 |
module
*
*********1*********2*********3*********4*********5*********6*********7*********/
module spi_master_top(
Clk
,Rst_n
,Wr
,Rd
,Addr
,DataIn
,DataOut
,SCLK
,MOSI
,MISO
,SS
,Int
,spi_cpol_debug
,spi_cpha_debug
);
parameter SIZE = 8;
input Clk; // Clock
input Rst_n; // Reset. Asynchronous. Active low
// Internal Data Bus
input Wr; // Write enable. Active high
input Rd; // Read enable. Active high
input [SIZE-1:0] Addr; // Registers Address
input [SIZE-1:0] DataIn; // Data input
output [SIZE-1:0] DataOut; // Data output
// SPI port
output SCLK; // SPI serial clock pad output
output MOSI; // Master Out Slave Out pad output
input MISO; // Master In Slave In
output [SIZE-1:0] SS; // Slave Selector
// Others
output Int; // SPI interrupt
output spi_cpol_debug; // SPI Clock Polarity debug
output spi_cpha_debug; // SPI Clock Phase debug
wire cPol; // SPI Clock Polarity
wire cPha; // SPI Clock Phase
wire spr1,spr0; // SPI Clock Rate Selector
wire [SIZE-1:0] cPre; // SPI Prescaled Clock Value
wire busy; // SPI tranceiver is busy
wire [SIZE-1:0] spiSRRx; // Data from SPI Shift Register Rx
wire [SIZE-1:0] spiBuf; // SPI Buffer Register
wire wrBuf; // Write Enable for SpiSR Data
wire spie; // Enable interrupt
wire spse; // Enable system
wire loadMaster; // Load data form SpiBuf to SpiSRTx
assign spi_cpol_debug = cPol;
assign spi_cpha_debug = cPha;
spi_master_registers SPI_REG(
.Clk (Clk)
,.Rst_n (Rst_n)
,.Wr (Wr)
,.Rd (Rd)
,.Addr (Addr)
,.DataIn (DataIn)
,.DataOut (DataOut)
,.CPol (cPol)
,.CPha (cPha)
,.Spr1 (spr1)
,.Spr0 (spr0)
,.CPre (cPre)
,.SS (SS)
,.Busy (busy)
,.SpiSRRx (spiSRRx)
,.SpiBuf (spiBuf)
,.WrBuf (wrBuf)
,.Spie (spie)
,.Spse (spse)
,.LoadMaster (loadMaster)
);
spi_master_controller MSTR_CTRL(
.Clk (Clk)
,.Rst_n (Rst_n)
,.MI (MISO)
,.MO (MOSI)
,.SCLK (SCLK)
,.CPre (cPre)
,.CPol (cPol)
,.CPha (cPha)
,.Spr1 (spr1)
,.Spr0 (spr0)
,.Spie (spie)
,.Spse (spse)
,.LoadMaster (loadMaster)
,.SpiBuf (spiBuf)
,.Busy (busy)
,.WrBuf (wrBuf)
,.Int (Int)
,.SpiSRRx (spiSRRx)
);
endmodule
| 6.861976 |
module spi_model #(
parameter DW = 32,
parameter CPOL = 0,
parameter integer ID = 0
) (
input [DW-1:0] ROM,
input cs,
input sck,
input copi,
output cipo
);
reg [DW-1:0] shift = 0;
/* verilator lint_save */
/* verilator lint_off MULTIDRIVEN */
reg [5:0] cnt = 0;
/* verilator lint_restore */
reg [DW-1:0] rom = 0;
wire sck_edge = CPOL ? ~sck : sck; // convert to CPOL=0
always @(negedge cs) cnt <= 0;
// CIPO changes on SCK rising edge
always @(posedge sck_edge)
if (~cs) begin
cnt <= (cnt == DW) ? 0 : cnt + 1'b1;
if (cnt == 0) rom <= ROM;
else rom <= {rom[DW-2:0], rom[DW-1]};
end
// Sample COPI on SCK falling edge
reg read = 0;
always @(negedge sck_edge)
if (~cs) begin
if (cnt == 1) read <= copi; // only response to 'read' cmd
shift <= {shift[DW-2:0], copi};
if (cnt == DW) begin
// $display("Time: %g ns, spi_model_%1d got: 0x%x, '%c'", $time, ID, shift, shift);
read <= 0;
end
end
// TODO why?
// assign cipo = read ? rom[DW-1] : 0;
assign cipo = rom[DW-1];
endmodule
| 6.782942 |
module spi_mon_tb;
localparam SIM_TIME = 500000; // ns
reg clk = 0;
integer fd, ix, rc;
reg en = 0;
reg [8:0] maddr = 0;
reg [7:0] mdat;
reg mwe = 0;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("spi_mon.vcd");
$dumpvars(5, spi_mon_tb);
end
fd = $fopen("spi_mon.dat", "r");
for (ix = 0; ix < 512; ix = ix + 1) begin
@(posedge clk);
#1;
mwe = 1;
maddr = ix;
rc = $fscanf(fd, "%x\n", mdat);
if (rc != 1) begin
$display("FAIL: parse error, aborting");
$stop(0);
end
end
mwe = 0;
en = 1;
while ($time < SIM_TIME) @(posedge clk);
$display("WARNING: Not a self-checking testbench. Will always pass.");
$display("PASS");
$finish(0);
end
always #5 clk = ~clk;
localparam AW = 8;
localparam DW = 24;
wire [ 3:0] spi_hw_sel;
wire spi_start;
wire spi_busy;
wire [AW-1:0] spi_addr;
wire [DW-1:0] spi_data;
wire spi_rnw;
wire spi_rvalid;
wire [DW-1:0] spi_rdata;
reg [ 6:0] rd_addr = 0;
wire [ 31:0] rd_data;
wire cs, sck;
reg sdo = 0;
wire sdi;
// Exercise enable functionality
initial begin
#(SIM_TIME / 4);
en = 0;
#(1000) @(posedge clk);
en = 1;
#(SIM_TIME / 4);
en = 0;
#(1000) @(posedge clk);
en = 1;
end
// Silly toggling to get non-zero stimulus
always @(posedge cs) sdo <= ~sdo;
// Continuously read-out spi_mon dpram
always @(posedge clk) rd_addr <= rd_addr + 1;
// Hack to make simulations more understandable;
// also note the width change from DW to 32.
wire [31:0] spi_rdata_x = en ? spi_rdata : {DW{1'bx}};
spi_mon #(
.SLEEP_SHIFT(4),
.IMEM_WI(9),
.DMEM_WI(7)
) i_dut (
.clk (clk),
.en (en),
.sleep (8'd20),
.wr_dwell (8'd10),
.imem_we (mwe),
.imem_waddr (maddr),
.imem_wdat (mdat),
.spi_hw_sel (spi_hw_sel),
.spi_start (spi_start),
.spi_busy (spi_busy),
.spi_data_addr({spi_data, spi_addr}),
.spi_rnw (spi_rnw),
.spi_rvalid (spi_rvalid),
.spi_rdata (spi_rdata_x),
.rd_addr (rd_addr),
.rd_data (rd_data)
);
spi_master #(
.TSCKHALF(4),
.ADDR_WIDTH(AW),
.DATA_WIDTH(DW),
.SCK_RISING_SHIFT(0)
) i_spi_master (
.clk (clk),
.spi_start(spi_start),
.spi_busy (spi_busy),
.spi_read (spi_rnw),
.spi_addr (spi_addr),
.spi_data (spi_data),
.cs (cs),
.sck (sck),
.sdo (sdo),
.sdi (sdi),
.sdo_addr (),
.spi_ready(spi_rvalid),
.spi_rdbk (spi_rdata)
);
endmodule
| 6.984381 |
module spi_msg #(
parameter nrRWregs = 4,
parameter nrROregs = 12
) // nrRWregs + nrROregs should be <= 16
(
input wire sysClk, // FPGA system clock (must be several times faster as SCLK, e.g. 66MHz)
input wire usrReset, // FPGA user reset button
input wire SCLK, // SPI clock (e.g. 4 MHz)
input wire MOSI, // SPI master out, slave in
output wire MISO, // SPI slave in, master out
input wire SS, // SPI slave select
output wire [1:0] LED
); // debug
wire rxValid;
wire [7:0] rx, tx;
wire [nrRWregs*32-1:0] rwRegs1D;
wire [nrROregs*32-1:0] roRegs1D;
// bits <> bytes
spi_byte_if byte_if (
.sysClk (sysClk),
.usrReset(usrReset),
.SCLK (SCLK),
.MOSI (MOSI),
.MISO (MISO),
.SS (SS),
.rxValid (rxValid),
.rx (rx),
.tx (tx)
);
// bytes <> messages
spi_msg_if #(nrRWregs, nrROregs) msg_if (
.sysClk (sysClk),
.usrReset(usrReset),
.rxValid (rxValid),
.rx (rx),
.tx (tx),
.rwRegs1D(rwRegs1D),
.roRegs1D(roRegs1D)
);
// inflate the 1D arrays (rwRegs1D, roRegs1D)
// into a 2D registers array (registers)
wire [31:0] registers[0:nrRWregs+nrROregs-1];
genvar nn;
for (nn = 0; nn < nrRWregs; nn = nn + 1) begin : nnRW
assign registers[nn] = rwRegs1D[32*nn+31:32*nn];
end
for (nn = 0; nn < nrROregs; nn = nn + 1) begin : nnRO
assign roRegs1D[32*nn+31:32*nn] = registers[nn+nrRWregs];
end
// connect the input and outputs
assign registers[4] = 32'hDEADBEEF;
for (nn = 1; nn < nrROregs; nn = nn + 1) begin : nnRegs
assign registers[nn+nrRWregs] = 32'h00000000;
end
// turn LEDs on when expected value has been written to register
assign LED[0] = (registers[0] == 32'h76543210);
assign LED[1] = (registers[1] == 32'h01234567);
endmodule
| 7.05648 |
module spi_msg_wb #(
parameter [7:0] CMD_BYTE = 8'h10
) (
// Wishbone interface
input wire [31:0] wb_wdata,
output reg [31:0] wb_rdata,
input wire [ 1:0] wb_addr,
input wire wb_we,
input wire wb_cyc,
output reg wb_ack,
// SPI protocol wrapper interface
input wire [7:0] pw_wdata,
input wire pw_wcmd,
input wire pw_wstb,
input wire pw_end,
output reg pw_req,
input wire pw_gnt,
output wire [7:0] pw_rdata,
output wire pw_rstb,
// Clock / Reset
input wire clk,
input wire rst
);
// Signals
// -------
// Bus
wire bus_clr;
reg bus_we_csr;
reg bus_we_data;
reg bus_re_data;
wire [31:0] bus_rd_csr;
wire [31:0] bus_rd_data;
// SPI -> CPU FIFO
wire [ 7:0] scf_wdata;
wire scf_wen;
wire scf_full;
wire [ 7:0] scf_rdata;
wire scf_ren;
wire scf_empty;
// SPI
reg spi_active;
reg spi_cmd_pending;
// Bus interface
// -------------
// Ack
always @(posedge clk) wb_ack <= wb_cyc & ~wb_ack;
// Clear
assign bus_clr = ~wb_cyc | wb_ack;
// Read Mux
always @(posedge clk)
if (bus_clr) wb_rdata <= 32'h00000000;
else wb_rdata <= wb_addr[0] ? bus_rd_data : bus_rd_csr;
// Strobes
always @(posedge clk)
if (bus_clr) begin
bus_we_csr <= 1'b0;
bus_we_data <= 1'b0;
bus_re_data <= 1'b0;
end else begin
bus_we_csr <= wb_we & ~wb_addr[0];
bus_we_data <= wb_we & wb_addr[0];
bus_re_data <= ~wb_we & wb_addr[0];
end
// CSR
assign bus_rd_csr = {24'h000000, 2'b00, pw_gnt, spi_cmd_pending};
// FIFO reads
assign bus_rd_data = {scf_empty, 23'h000000, scf_rdata};
assign scf_ren = bus_re_data & ~wb_rdata[31];
// FIFO
// ----
// Instance
fifo_sync_ram #(
.DEPTH(512),
.WIDTH(8)
) fifo_I (
.wr_data (scf_wdata),
.wr_ena (scf_wen),
.wr_full (scf_full),
.rd_data (scf_rdata),
.rd_ena (scf_ren),
.rd_empty(scf_empty),
.clk (clk),
.rst (rst)
);
// SPI pass-through
// ----------------
// SPI Command tracking
always @(posedge clk)
if (rst) spi_active <= 1'b0;
else spi_active <= (spi_active | (pw_wstb & pw_wcmd & (pw_wdata == CMD_BYTE))) & ~pw_end;
// Write to FIFO
assign scf_wdata = pw_wdata;
assign scf_wen = pw_wstb & spi_active & ~scf_full;
// Command Pending flag
always @(posedge clk)
if (rst) spi_cmd_pending <= 1'b0;
else spi_cmd_pending <= (spi_cmd_pending & ~(bus_we_csr & wb_wdata[0])) | scf_wen;
// Response writes from CPU
always @(posedge clk)
if (rst) pw_req <= 1'b0;
else pw_req <= (pw_req & ~(bus_we_csr & wb_wdata[3])) | (bus_we_csr & wb_wdata[2]);
assign pw_rdata = wb_wdata[7:0];
assign pw_rstb = bus_we_data;
endmodule
| 8.428155 |
module SPI_mstr (
clk,
rst_n,
SS_n,
SCLK,
command,
MISO,
wrt_cmd,
done,
resp,
MOSI
);
input clk, rst_n;
input wrt_cmd; //Input to Master to initiate SPI transaction
// input RDY; // Input fro slave saying response to previous command is ready
input MISO; // Input bit stream of data written from slave to master
input [15:0] command; // 16 bit command provided from user
output SS_n, SCLK, done, MOSI; // MOSI - Serial data of Master which is resp[0]
output [15:0] resp; // parallel data of MISO
reg [15:0] cmd_buf; // Command buffer to capture 16 bit command to be sent to MOSI
reg [1:0] state, nxt_state;
reg [9:0] pause_cntr;
reg [4:0] bit_cntr;
reg [15:0] resp;
reg done;
reg SS_n;
reg rst_cnt, en_cnt, shft, ld;
localparam IDLE = 2'b00;
localparam BITS = 2'b01;
localparam TRAIL = 2'b10;
///////////////////////////////
// Implement state register //
/////////////////////////////
always @(posedge clk, negedge rst_n)
if (!rst_n) state <= IDLE;
else state <= nxt_state;
////////////////////////////
// Implement bit counter //
//////////////////////////
always @(posedge clk)
if (rst_cnt) bit_cntr <= 5'b00000;
else if (en_cnt) bit_cntr <= bit_cntr + 1;
//////////////////////////////
// Implement pause counter //
////////////////////////////
always @(posedge clk)
if (rst_cnt) pause_cntr <= 10'h1EE;
else pause_cntr <= pause_cntr + 1;
assign SCLK = pause_cntr[9];
//////////////////////////////////////
// resp is shifted on fall of SCLK //
////////////////////////////////////
always @(posedge clk) if (shft) resp <= {resp[14:0], MISO};
//////////////////////////////////////
// command is given serially to MOSI//
/////////////////////////////////////
always @(posedge clk)
if (ld) cmd_buf <= command;
else if (shft) cmd_buf <= {cmd_buf[14:0], 1'b0};
assign MOSI = (SS_n) ? 1'bx : cmd_buf[15];
////////////////////////////////////////
// Implement SM that controls output //
//////////////////////////////////////
always @(state, wrt_cmd, pause_cntr) begin
//////////////////////
// Default outputs //
////////////////////
rst_cnt = 1'b0;
SS_n = 1'b1;
en_cnt = 1'b0;
shft = 1'b0;
done = 1'b0;
ld = 1'b0;
case (state)
IDLE: begin
rst_cnt = 1'b1;
ld = 1'b1;
if (wrt_cmd) begin
SS_n = 1'b0;
nxt_state = BITS;
end else nxt_state = IDLE;
end
BITS: begin
////////////////////////////////////
// For the 16 bits of the packet //
//////////////////////////////////
SS_n = 1'b0;
en_cnt = &pause_cntr;
shft = en_cnt;
if (bit_cntr == 5'h10) begin
rst_cnt = 1'b1;
nxt_state = TRAIL;
end else nxt_state = BITS;
end
default: begin // this is TRAIL state
//////////////////////////////////////////
// This state keeps SS_n low till 16 //
// clocks after the last fall of SCLK //
///////////////////////////////////////
SS_n = 1'b0;
en_cnt = 1'b1;
if (bit_cntr == 5'h10) begin
done = 1'b1;
nxt_state = IDLE;
end
end
endcase
end
endmodule
| 8.236484 |
module SPI_TestBench ();
reg [7:0] data_in;
wire [7:0] data_out;
initial data_in = 0;
reg clock;
initial clock = 0;
always #(1) clock <= ~clock;
wire rst;
wire SCK, MO, CS;
reg data_in_valid, MI;
initial data_in_valid = 0;
initial MI = 0;
wire data_out_valid;
SPI_slave spi_s (
.SCK(SCK),
.MI(MI),
.MO(MO),
.CS(CS),
.data_in(data_in),
.data_in_valid(data_in_valid),
.data_out(data_out),
.data_out_valid(data_out_valid),
.rst(rst),
.clk(clock)
);
reg [2:0] resetn_counter = 0;
always @(posedge clock) begin
if (!rst) resetn_counter <= resetn_counter + 1;
end
assign rst = &resetn_counter;
initial begin
$dumpfile("SPI_TestBench.vcd");
$dumpvars(0, spi_m);
$dumpvars(0, data_out);
#20 data_in_valid <= 1;
data_in <= 8'd55;
#200 $finish;
end
endmodule
| 7.278138 |
module spi_oled #(
parameter integer CLOCK_FREQ_HZ = 0,
parameter integer CS_LENGTH = 32
) (
input clk,
input resetn,
input ctrl_wr,
input ctrl_rd,
input [7:0] ctrl_addr,
input [31:0] ctrl_wdat,
output reg [31:0] ctrl_rdat,
output reg ctrl_done,
inout mosi,
sclk,
cs,
dc,
rst
);
reg spi_mosi, spi_sclk, spi_cs, spi_dc, spi_rst;
reg mode_cpol;
reg mode_cpha;
reg [7:0] prescale_cnt;
reg [7:0] prescale_cfg;
reg [7:0] spi_data;
reg [4:0] spi_state;
SB_IO #(
.PIN_TYPE(6'b0110_01),
.PULLUP (1'b0)
) io_mosi (
.PACKAGE_PIN(mosi),
.D_OUT_0(spi_mosi)
);
SB_IO #(
.PIN_TYPE(6'b0110_01),
.PULLUP (1'b0)
) io_sclk (
.PACKAGE_PIN(sclk),
.D_OUT_0(spi_sclk ^ ~mode_cpol)
);
SB_IO #(
.PIN_TYPE(6'b0110_01),
.PULLUP (1'b0)
) io_cs (
.PACKAGE_PIN(cs),
.D_OUT_0(spi_cs)
);
SB_IO #(
.PIN_TYPE(6'b0110_01),
.PULLUP (1'b0)
) io_dc (
.PACKAGE_PIN(dc),
.D_OUT_0(spi_dc)
);
SB_IO #(
.PIN_TYPE(6'b0110_01),
.PULLUP (1'b0)
) io_rst (
.PACKAGE_PIN(rst),
.D_OUT_0(spi_rst)
);
always @(posedge clk) begin
ctrl_rdat <= 'bx;
ctrl_done <= 0;
if (!resetn) begin
spi_mosi <= 0;
spi_sclk <= 1;
spi_cs <= ~0;
spi_rst <= 1;
spi_dc <= 0;
mode_cpol <= 1;
mode_cpha <= 1;
prescale_cnt <= 0;
prescale_cfg <= 0;
spi_state <= 0;
end else if (!ctrl_done) begin
if (ctrl_wr) begin
ctrl_done <= 1;
if (ctrl_addr == 'h00) prescale_cfg <= ctrl_wdat;
if (ctrl_addr == 'h04) begin
spi_cs <= ctrl_wdat;
ctrl_done <= prescale_cnt == prescale_cfg;
prescale_cnt <= prescale_cnt == prescale_cfg ? 0 : prescale_cnt + 1;
end
if (ctrl_addr == 'h10) begin
spi_dc <= ctrl_wdat;
ctrl_done <= prescale_cnt == prescale_cfg;
prescale_cnt <= prescale_cnt == prescale_cfg ? 0 : prescale_cnt + 1;
end
if (ctrl_addr == 'h14) begin
spi_rst <= ctrl_wdat;
ctrl_done <= prescale_cnt == prescale_cfg;
prescale_cnt <= prescale_cnt == prescale_cfg ? 0 : prescale_cnt + 1;
end
if (ctrl_addr == 'h08) begin
if (!prescale_cnt) begin
if (spi_state == 0) begin
spi_data <= ctrl_wdat;
spi_mosi <= ctrl_wdat[7];
end else begin
if (spi_state[0]) spi_data <= {spi_data, spi_mosi};
else if (spi_state < 16) spi_mosi <= spi_data[7];
end
end
spi_sclk <= spi_state[0] ^ ~mode_cpha;
ctrl_done <= spi_state == (mode_cpha ? 15 : 16) && prescale_cnt == prescale_cfg;
spi_state <= prescale_cnt == prescale_cfg ? (spi_state[4] ? 0 : spi_state + 1) : spi_state;
if (mode_cpha) spi_state[4] <= 0;
prescale_cnt <= prescale_cnt == prescale_cfg ? 0 : prescale_cnt + 1;
end
if (ctrl_addr == 'h0c) begin
{mode_cpol, mode_cpha} <= ctrl_wdat;
ctrl_done <= prescale_cnt == prescale_cfg;
prescale_cnt <= prescale_cnt == prescale_cfg ? 0 : prescale_cnt + 1;
end
end
if (ctrl_rd) begin
ctrl_done <= 1;
if (ctrl_addr == 'h00) ctrl_rdat <= prescale_cfg;
if (ctrl_addr == 'h04) ctrl_rdat <= spi_cs;
if (ctrl_addr == 'h08) ctrl_rdat <= spi_data;
if (ctrl_addr == 'h0c) ctrl_rdat <= {mode_cpol, mode_cpha};
if (ctrl_addr == 'h10) ctrl_rdat <= spi_dc;
if (ctrl_addr == 'h14) ctrl_rdat <= spi_rst;
end
end
end
endmodule
| 7.090459 |
module spi_osd #(
parameter [7:0] c_addr_enable = 8'hFE, // high addr byte of enable byte
parameter [7:0] c_addr_display = 8'hFD, // high addr byte of display data, +0x10000 for inverted
parameter c_start_x = 64, // x1 pixel window h-position
parameter c_start_y = 48, // x1 pixel window v-position
parameter c_chars_x = 64, // x8 pixel window h-size
parameter c_chars_y = 24, // x16 pixel window v-size
parameter c_init_on = 1, // 0:default OFF 1:default ON
parameter c_inverse = 1, // 0:no inverse, 1:inverse support
parameter c_transparency = 0, // 1:see-thru OSD menu 0:opaque
parameter [23:0] c_bgcolor = 24'h503020, // RRGGBB menu background color
parameter c_char_file = "osd.mem", // initial window content, 2 ASCII HEX digits per line
parameter c_font_file = "font_bizcat8x16.mem" // font bitmap, 8 ASCII BIN digits per line
) (
input wire clk_pixel,
clk_pixel_ena,
input wire [7:0] i_r,
input wire [7:0] i_g,
input wire [7:0] i_b,
input wire i_hsync,
i_vsync,
i_blank,
input wire i_csn,
i_sclk,
i_mosi,
inout wire o_miso,
output wire [7:0] o_r,
output wire [7:0] o_g,
output wire [7:0] o_b,
output wire o_hsync,
o_vsync,
o_blank
);
reg [7+c_inverse:0] tile_map[0:c_chars_x*c_chars_y-1]; // tile memory (character map)
initial $readmemh(c_char_file, tile_map);
wire ram_wr;
wire [31:0] ram_addr;
wire [7:0] ram_di;
reg [7:0] ram_do;
spirw_slave_v #(
.c_addr_bits(32),
.c_sclk_capable_pin(1'b0)
) spirw_slave_inst (
.clk(clk_pixel),
.csn(i_csn),
.sclk(i_sclk),
.mosi(i_mosi),
.miso(o_miso),
.wr(ram_wr),
.addr(ram_addr),
.data_in(ram_do),
.data_out(ram_di)
);
always @(posedge clk_pixel) begin
if (ram_wr && (ram_addr[31:24] == c_addr_display))
if (c_inverse)
tile_map[ram_addr] <= {
ram_addr[16], ram_di
}; // ASCII to 0xFDx0xxxx normal, 0xFDx1xxxx inverted
else tile_map[ram_addr] <= ram_di;
//ram_do <= tile_map[ram_addr];
end
reg osd_en = c_init_on;
always @(posedge clk_pixel) begin
if (ram_wr && (ram_addr[31:24] == c_addr_enable)) // write to 0xFExxxxxx enables/disables OSD
osd_en <= ram_di[0];
end
wire [9:0] osd_x, osd_y;
reg [7:0] font[0:4095];
initial $readmemb(c_font_file, font);
reg [ 7:0] data_out;
wire [11:0] tileaddr = (osd_y >> 4) * c_chars_x + (osd_x >> 3);
generate
if (c_inverse)
always @(posedge clk_pixel)
data_out[7:0] <= font[{tile_map[tileaddr], osd_y[3:0]}] ^ {8{tile_map[tileaddr][8]}};
else always @(posedge clk_pixel) data_out[7:0] <= font[{tile_map[tileaddr], osd_y[3:0]}];
endgenerate
wire [7:0] data_out_align = {data_out[0], data_out[7:1]};
wire osd_pixel = data_out_align[7-osd_x[2:0]];
wire [7:0] osd_r = osd_pixel ? 8'hff : c_bgcolor[23:16];
wire [7:0] osd_g = osd_pixel ? 8'hff : c_bgcolor[15:8];
wire [7:0] osd_b = osd_pixel ? 8'hff : c_bgcolor[7:0];
// OSD overlay
osd #(
.C_x_start(c_start_x),
.C_x_stop(c_start_x + 8 * c_chars_x - 1),
.C_y_start(c_start_y),
.C_y_stop(c_start_y + 16 * c_chars_y - 1),
.C_transparency(c_transparency)
) osd_instance (
.clk_pixel(clk_pixel),
.clk_pixel_ena(1'b1),
.i_r(i_r),
.i_g(i_g),
.i_b(i_b),
.i_hsync(i_hsync),
.i_vsync(i_vsync),
.i_blank(i_blank),
.i_osd_en(osd_en),
.o_osd_x(osd_x),
.o_osd_y(osd_y),
.i_osd_r(osd_r),
.i_osd_g(osd_g),
.i_osd_b(osd_b),
.o_r(o_r),
.o_g(o_g),
.o_b(o_b),
.o_hsync(o_hsync),
.o_vsync(o_vsync),
.o_blank(o_blank)
);
endmodule
| 8.360593 |
module spi_pack #(
parameter BASE_ADDR = 8'h00,
parameter BASE2_ADDR = 8'h00 // Takes 1 BASE2 slot at BASE2_ADDR
) (
input clk,
input rst,
// Hardware interface
output spi_cs, // active low chip select
output spi_sck, // serial clock
output spi_copi, // controller out / peripheral in
input spi_cipo, // controller in / peripheral out
output [31:0] spi_cfg_reg,
// PicoRV32 packed MEM Bus interface
input [68:0] mem_packed_fwd, //CPU > SPI
output [32:0] mem_packed_ret //CPU < SPI
);
// ------------------------------------------------------------------------
// SPI Registers
// ------------------------------------------------------------------------
// SPI data register (spi_tx_reg) is at BASE_ADDR
// Writing to the LSB of BASE_ADDR will start the SPI transmission
// Reading BASE_ADDR will return the last complete reception.
// spi_pack will never stall the CPU. So block on the BUSY bit in firmware.
// The configuration register is at BASE_ADDR + 4. It contains:
localparam BIT_CLK_DIV = 0; // 8 bit clock prescaler (halfperiod cycle count)
localparam BIT_NBITS = 8; // Send / Receive N bits per transfer (1-32)
localparam BIT_CPOL = 16; // Clock polarity: 0 = idle low, 1 = idle high
localparam BIT_CPHA = 17; // Clock phase: 0 = sample on 1st edge, 1 = 2nd
localparam BIT_LSB = 18; // When set, transmit LSB first, otherwise MSB
localparam BIT_SS_MAN = 25; // 0 = Automatic, 1 = Manual control of SS pin
localparam BIT_SS_CTRL = 26; // Set state of SS pin (when BIT_SS_MAN == 1)
localparam BIT_BUSY = 30; // BIT_BUSY == 1 while spi_engine is busy
localparam BIT_MISO = 31; // Status of MISO pin
wire [2*32-1:0] sfRegsOut;
wire [2*32-1:0] sfRegsWrStr;
wire [2*32-1:0] sfRegsIn;
wire [ 31:0] spi_rdata;
wire spi_busy;
wire spi_cs_auto;
sfr_pack #(
.BASE_ADDR (BASE_ADDR),
.BASE2_ADDR(BASE2_ADDR),
.N_REGS (2)
) sfrInst (
.clk (clk),
.rst (rst),
.mem_packed_fwd(mem_packed_fwd),
.mem_packed_ret(mem_packed_ret),
.sfRegsOut (sfRegsOut),
.sfRegsWrStr (sfRegsWrStr),
.sfRegsIn (sfRegsIn)
);
// Connect spi_tx_reg to "write on BASE_ADDR"
wire [31:0] spi_tx_reg = sfRegsOut[0*32+:32];
// Connect spi_rdata to "read on BASE_ADDR"
assign sfRegsIn[0*32+:32] = spi_rdata;
// Connect spi_cfg_reg to "write on BASE_ADDR+4"
assign spi_cfg_reg = sfRegsOut[1*32+:32];
// Connect config word to "read on BASE_ADDR+4"
assign sfRegsIn[1*32+:32] = {spi_cipo, spi_busy, spi_cfg_reg[29:0]};
wire [7:0] cfg_clk_div = spi_cfg_reg[BIT_CLK_DIV+:8]; // Clock divider word
wire [5:0] cfg_nbits = spi_cfg_reg[BIT_NBITS+:6]; // N bits per transf. (1-32)
// Auto / manual control of SS pin
assign spi_cs = spi_cfg_reg[BIT_SS_MAN] ? spi_cfg_reg[BIT_SS_CTRL] : spi_cs_auto;
// ------------------------------------------------------------------------
// Instantiate the SPI engine
// ------------------------------------------------------------------------
spi_engine spi_inst (
.clk (clk),
.reset (rst),
// If lowest bit of `spi_tx_reg` is written, start SPI transmission
.wdata_val (sfRegsWrStr[0]),
.wdata (spi_tx_reg),
.rdata (spi_rdata),
.rdata_val (),
.busy (spi_busy),
.cfg_sckhalfperiod(cfg_clk_div),
.cfg_cpol (spi_cfg_reg[BIT_CPOL]),
.cfg_cpha (spi_cfg_reg[BIT_CPHA]),
.cfg_lsb (spi_cfg_reg[BIT_LSB]),
.cfg_scklen ({2'h0, cfg_nbits}),
.cs (spi_cs_auto),
.sck (spi_sck),
.copi (spi_copi),
.cipo (spi_cipo)
);
endmodule
| 8.56925 |
module spi_passthrough (
input wire iCLK,
input wire RSTin,
input wire ID_in,
input wire IRQ_in,
input wire address_strobe,
input wire [6:0] currentSPIAddr,
input wire [6:0] setSPIAddr,
input wire SCLKin,
input wire SCSNin,
input wire MOSIin,
output wire MISOout,
output wire rst_local,
output wire sclk_local,
output wire scsn_local,
output wire mosi_local,
input wire miso_local,
input wire irq_local,
output wire write_enable,
output wire RSTout,
output wire SCLKout,
output wire SCSNout,
output wire MOSIout,
input wire MISOin,
output wire IRQout
);
// each of the inputs are negated
wire rst_wire;
// //////////////////////////////////////////////////////
// synchronizers
reg [1:0] id_resync;
reg [1:0] reset_resync;
always @(posedge iCLK)
if (rst_wire) begin
id_resync <= 0;
end else begin
id_resync <= {id_resync[0], ID_in};
end
reg [1:0] irq_resync;
always @(posedge iCLK)
if (rst_wire) begin
irq_resync <= 0;
end else begin
irq_resync <= {irq_resync[0], IRQ_in};
end
`ifdef BYPASS_THIS_ASIC
assign IRQout = IRQ_in;
`else
assign IRQout = irq_resync[1] | irq_local;
`endif
always @(posedge iCLK) begin
reset_resync <= {reset_resync[0], !RSTin};
end
// //////////////////////////////////////////////////////
// pass-through signals and pick-off
assign rst_wire = reset_resync[1];
assign rst_local = rst_wire;
assign RSTout = RSTin;
assign SCLKout = SCLKin;
assign sclk_local = SCLKin;
assign SCSNout = SCSNin;
assign scsn_local = SCSNin;
assign MOSIout = MOSIin;
assign mosi_local = MOSIin;
// //////////////////////////////////////////////////////
// MISO mux
wire unique_address_match;
wire id_active;
reg local_address_select;
assign unique_address_match = (currentSPIAddr == setSPIAddr) ? 1'b1 : 1'b0;
assign id_active = id_resync[1];
always @(posedge iCLK)
if (rst_wire) begin
local_address_select <= 0;
end else begin
if (address_strobe) begin
if ((id_active) && (unique_address_match)) begin
local_address_select <= 1;
end else begin
local_address_select <= 0;
end
end
end
`ifdef BYPASS_THIS_ASIC
assign MISOout = MISOin;
`else
assign MISOout = (local_address_select) ? miso_local : MISOin;
`endif
// //////////////////////////////////////////////////////
// Write enable mask
wire global_address_match;
reg global_address_select;
assign global_address_match = (currentSPIAddr == 7'b1111111) ? 1'b1 : 1'b0;
always @(posedge iCLK)
if (rst_wire) begin
global_address_select <= 0;
end else begin
if (address_strobe) begin
if ((id_active) && ((unique_address_match) || (global_address_match))) begin
global_address_select <= 1;
end else begin
global_address_select <= 0;
end
end
end
assign write_enable = global_address_select;
endmodule
| 7.988149 |
module.
// These SPI parameters are used in this module:
// CPOL = 0 (spi_clk idles low)
// CPHA = 0 (data clocked in on rising edge when CPOL is 1)
//
// Note: addr/wdat are synchronous to the SPI clock. we & re are synchronized
//
// A SPI transfer consists of 40 bits, MSB first.
// The first bit is read/write_n.
// The next 7 are address bits.
// The last 32 are data bits
// Read data is sent in current transfer based on early address/direction
//`timescale 1 ns/1 ps
`default_nettype none
module spi_peripheral
#(
parameter asz = 7, // address size
parameter dsz = 32 // databus word size
) (
input wire clk,
input wire reset,
input wire spi_clk,
input wire spi_copi,
output wire spi_cipo,
input wire spi_cs,
output reg we,
output reg re,
output reg [dsz-1:0] wdat,
output reg [asz-1:0] addr,
input wire [dsz-1:0] rdat,
output reg rd,
output wire spi_reset,
output wire mosi_cnt_is_zero);
reg [12:0] mosi_cnt; // input bit counter
reg [dsz-1:0] mosi_shift; // shift reg
reg eoa; // end of address flag
reg eot; // end of transfer flag
assign spi_reset = reset | spi_cs; // combined reset
`ifdef COCOTB_SIM
initial begin
$dumpfile ("spi_peripheral.vcd");
$dumpvars (0, spi_peripheral);
#1;
end
`endif
assign mosi_cnt_is_zero = mosi_cnt == 0;
always @(posedge spi_clk or posedge spi_reset)
if (spi_reset)
begin
mosi_cnt <= 'b0;
mosi_shift <= 'b0;
eoa <= 'b0;
re <= 'b0;
rd <= 'b0;
eot <= 'b0;
end else begin
// Counter keeps track of bits received
mosi_cnt <= mosi_cnt + 1;
// Shift register grabs incoming data
mosi_shift <= {mosi_shift[dsz-2:0], spi_copi};
// Grab Read bit
if(mosi_cnt == 0)
rd <= spi_copi;
// Grab Address
if(mosi_cnt == asz)
begin
addr <= {mosi_shift[asz-2:0],spi_copi};
eoa <= 1'b1;
end
// Generate Read pulse, lasts for one spi_clk pulse
re <= rd & (mosi_cnt == asz);
if(mosi_cnt == (asz+dsz))
begin
// Grab data
wdat <= {mosi_shift[dsz-2:0],spi_copi};
// End-of-transmission (used to generate Write pulse)
eot <= 1'b1;
end
end
// outgoing shift register is clocked on falling edge
reg [dsz-1:0] miso_shift;
always @(negedge spi_clk or posedge spi_reset)
if (spi_reset)
begin
miso_shift <= 'b0;
end
else
begin
if(re)
miso_shift <= rdat;
else
miso_shift <= {miso_shift[dsz-2:0],1'b0};
end
// MISO is just msb of shift reg
assign spi_cipo = eoa ? miso_shift[dsz-1] : 1'b0;
// Delay/Sync & edge detect on eot to generate we
reg [2:0] we_dly;
always @(posedge clk)
if(reset)
begin
we_dly <= 0;
we <= 0;
end
else
begin
we_dly <= {we_dly[1:0],eot};
we <= ~we_dly[2] & we_dly[1] & ~rd;
end
endmodule
| 8.233778 |
module spi_pg #(
parameter DW = 64,
parameter AS = 32,
parameter IDW = 8
) (
input spi_aclk,
input spi_aresetn,
input [IDW-1:0] spi_awid,
input [ AS-1:0] spi_awaddr,
input [ 1:0] spi_awlen,
input [ 2:0] spi_awsize,
input [ 1:0] spi_awburst,
input spi_awvalid,
output spi_awready,
input [ DW-1:0] spi_wdata,
input [(DW>>3)-1:0] spi_wstrb,
input spi_wlast,
input spi_wvalid,
output spi_wready,
// input spi_arvalid,
// input spi_arready,
// input spi_rready,
// input spi_rvalid,
// input spi_rlast,
// //snooping spi port
// input spi_csn,
// spi output port
output o_spi_sck,
output o_spi_csn,
output o_spi_dq0_en, //MOSI
// input o_spi_dq0_i,
output o_spi_dq0_o,
output o_spi_dq1_en, //MISO
// input o_spi_dq1_i,
output o_spi_dq1_o,
output o_spi_dq2_en,
// input o_spi_dq2_i,
output o_spi_dq2_o,
output o_spi_dq3_en,
// input o_spi_dq3_i,
output o_spi_dq3_o
);
wire spi_aw_hsked = spi_awvalid & spi_awready;
//TODO: modify memory space for register.
wire spi_reg_space = (spi_awaddr[27:20] == 8'h18);
//0x0 --- command meta information
//0x4 --- write data queue.
//
//
// -------------------------------------------------------
// -- Command REGISTER
// -------------------------------------------------------
wire [31:0] spi_command_r;
wire [31:0] spi_command_nxt;
wire spi_command_ena;
endmodule
| 7.914416 |
module spi_phy (
input wire spi_cs,
input wire spi_clk,
input wire spi_mosi,
output reg spi_miso,
output reg spi_byte_o_en,
output reg [7:0] spi_byte_o,
input wire spi_byte_i_en,
input wire [7:0] spi_byte_i
);
// serial transfer index counter
reg [2:0] spi_bit_cnt;
always @(posedge spi_cs or posedge spi_clk) begin
if (spi_cs) spi_bit_cnt <= 'd0;
else spi_bit_cnt <= spi_bit_cnt + 'd1;
end
// serial transfer 8bit done
always @(posedge spi_cs or posedge spi_clk) begin
if (spi_cs) spi_byte_o_en <= 1'b0;
else if (spi_bit_cnt == 'd7) spi_byte_o_en <= 1'b1;
else spi_byte_o_en <= 1'b0;
end
// serial transfer 8bit data input
always @(posedge spi_cs or posedge spi_clk) begin
if (spi_cs) spi_byte_o <= 8'd0;
else spi_byte_o <= {spi_byte_o[6:0], spi_mosi};
end
// serial transfer 8bit data output
always @(*) begin // intented to be a latch
if (!spi_clk) spi_miso <= spi_byte_i[7-spi_bit_cnt[2:0]];
end
endmodule
| 6.946697 |
module SPI_PINGPONG_top (
input clk,
input sck,
input ssel,
input rst_n,
input mosi,
output wire miso,
output wire DRDY
);
// SPI
wire byteReceived; // 在第八个sck_risingEdge置为1
wire [7:0] receivedData; // shift register
// wire dataNeeded; // MOSI ready信号
// // wire [7:0] dataToSend;
// reg[1:0] sselr;
// wire ssel_active = ~ssel; // ssel 低电平有效
// RAM0
wire [7:0] doutb0;
wire [6:0] addra0;
wire [6:0] addrb0;
wire finisha0;
wire finishb0;
// reg[7:0] data_counter;
// RAM1
wire [7:0] doutb1;
wire [6:0] addra1;
wire [6:0] addrb1;
wire finisha1;
wire finishb1;
wire [7:0] dina1;
wire wea1;
wire readya0;
assign DRDY = readya0 && readyb1;
SPI_slave u_SPI_slave (
.clk (clk),
.sck (sck),
.rst_n (rst_n),
.mosi (mosi),
.ssel (ssel),
.miso (miso),
.receivedData(receivedData[7:0]),
.dataToSend (doutb1[7:0]),
.byteReceived(byteReceived),
// 可选项
.readya0(readya0),
.readyb1(readyb1),
.addra0 (addra0[6:0]),
.addrb1 (addrb1[6:0]),
.finisha0(finisha0),
.finishb1(finishb1)
);
// MOSI RAM
PINGPONG_RAM u0_PINGPONG_RAM (
.clka (clk),
.rsta (!rst_n),
.addra (addra0[6:0]),
.wea (byteReceived), //
.dina (receivedData[7:0]),
.finisha(finisha0),
.readya (readya0),
.clkb (clk),
.rstb (!rst_n),
.addrb (addrb0[6:0]),
.finishb(finishb0),
.doutb (doutb0[7:0]),
.readyb (readyb0)
);
// MISO RAM
PINGPONG_RAM u1_PINGPONG_RAM (
.clka (clk),
.rsta (!rst_n),
.addra (addra1[6:0]),
.wea (wea1),
.dina (dina1[7:0]),
.finisha(finisha1),
.readya (readya1),
.clkb (clk),
.rstb (!rst_n),
.addrb (addrb1[6:0]),
.finishb(finishb1),
.doutb (doutb1[7:0]),
.readyb (readyb1)
);
// doutb0为输入的数据, dina1为DSP输出的数据
DSP_module DSP_module (
.clk(clk),
.rst_n(rst_n),
.datain(doutb0),
.dataout(dina1),
.readyb0(readyb0),
.readya1(readya1),
.addrb0(addrb0),
.addra1(addra1),
.finishb0(finishb0),
.finisha1(finisha1),
.wea(wea1)
);
endmodule
| 7.532732 |
module SPI_PINGPONG_top_tb;
reg clk;
wire sck;
reg sck_ori;
reg rst_n;
wire mosi;
wire miso;
reg ssel;
wire ssel_active = ~ssel;
// wire readya1;
// wire byteReceived; // received a bit
wire DRDY;
parameter LOOPTIME = 256;
parameter PERIOD = 10; // must be even
parameter SCKPERIOD = 50;
integer f_send, f_receive, f_ssel;
integer counter;
reg [2:0] bitcnt = 3'b000;
reg [1:0] sckr = 2'b00;
reg [1:0] sselr;
reg [7:0] MOSI_data;
reg [7:0] MOSI_data_Buffer;
reg [7:0] MISO_data;
SPI_PINGPONG_top SPI_PINGPONG_top (
clk,
sck,
ssel,
rst_n,
mosi,
miso,
DRDY
);
initial begin
clk = 0;
MOSI_data = 0;
MISO_data = 0;
counter = 0;
rst_n = 0;
sck_ori = 0;
f_send = $fopen("MOSI_data.txt", "r"); //读打开
// f_receive = $fopen("MISO_data.txt","w");//收回的数据
f_ssel = $fopen("ssel_data.txt", "r"); // ssel data
if (f_send == `NULL) $display("fail to open data MOSI_data.txt!");
if (f_receive == `NULL)
// $display("fail to open data MISO_data.txt!");
if (f_ssel == `NULL)
$display("fail to open data ssel_data.txt!");
#PERIOD rst_n = 1;
$fscanf(f_send, "%b", MOSI_data);
end
always #(PERIOD / 2) begin
clk = ~clk;
end
always #(SCKPERIOD / 2) begin
sck_ori = ~sck_ori;
end
assign sck = sck_ori && !ssel;
// load ssel data
always @(posedge clk) begin
if (!$feof(f_ssel)) $fscanf(f_ssel, "%b", ssel);
else $fclose(f_ssel);
end
always @(posedge clk) begin
if (!rst_n) sckr <= 2'b00;
else begin
sckr <= {sckr[0], sck};
end
end
wire sck_risingEdge = (sckr == 2'b01);
wire sck_fallingEdge = (sckr == 2'b10);
// load MOSI_data
always @(posedge clk) begin
if (!$feof(f_send) && (sck_risingEdge) && (bitcnt == 0)) begin
counter <= counter + 1;
$fscanf(f_send, "%b", MOSI_data);
$display("Reading MOSI_data");
end else if ($feof(f_send)) begin
$fclose(f_send);
end
end
// Save MISO_data
// always @(posedge clk) begin
// if()
//
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
sselr <= 2'b00;
end else begin
sselr <= {sselr[0], ssel};
end
end
wire ssel_risingEdge = (sselr == 2'b01);
wire ssel_fallingEdge = (sselr == 2'b10);
always @(posedge clk) begin
if (~ssel_active) begin
bitcnt <= 3'b000;
end else if (sck_risingEdge) begin
bitcnt <= bitcnt + 3'b001;
end
end
always @(posedge clk) begin
if (~ssel_active) MOSI_data_Buffer <= MOSI_data;
else if (((bitcnt == 3'b000) && (sck_fallingEdge)) || ssel_fallingEdge) begin
// if(DRDY)
MOSI_data_Buffer <= MOSI_data;
// else
// MOSI_data_Buffer <= 8'b0;
end else if (sck_fallingEdge) MOSI_data_Buffer <= {MOSI_data_Buffer[6:0], 1'b0};
end
assign mosi = MOSI_data_Buffer[7];
endmodule
| 7.532732 |
module implements a SPI port for use with ADI HSC SPI protocol.
// This version supports only 16-bit instruction phase, MSB transfers.
//
// Dependencies: spi_control.v, spi_decoder.v, spi_encoder.v
//
// Revision: 1.00
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spi_port #
(
parameter integer ADDR_SIZE = 13 // Address size ([1, 13] for current standard)
)
(
//
// ------- Inputs -------
//
input I_sclk, // Serial data clock
input _I_csb, // Active low chip select
input I_sdi, // Serial data input
input [7:0] I_dout, // Parallel data output (input to be encoded into O_sdo)
//
// ------- Outputs -------
//
output O_sdo, // Serial data output
output O_wen, // Write enable for parallel data input
output [ADDR_SIZE - 1:0] O_addr, // Decoded address
output [7:0] O_din // Parallel data input (output decoded from I_sdi)
);
localparam integer DATA_SIZE = 8; // Data size should always be byte-width
wire spi_rw; // Read/write indicator (1 = read, 0 = write)
wire spi_astrobe; // Address strobe to enable address decoding
wire spi_dstrobe; // Data strobe to enable data decoding and encoding
wire spi_sync; // Sync pulse to enable reads or writes from memory
wire spi_data_dec_en; // Enable for decoding from I_sdi (serial) to O_din (parallel)
wire spi_data_enc_en; // Enable for encoding from I_dout (parallel) to O_sdo (serial)
// MSBs of parallel data input from data decoder
wire [DATA_SIZE - 2:0] spi_din_msbs;
// Instantiate SPI FSM controller.
spi_control spi_ctl
(
.I_sclk(I_sclk), // Serial data clock
._I_csb(_I_csb), // Active low chip select
.I_sdi(I_sdi), // Serial data input
.O_rw(spi_rw), // Read/write indicator (1 = read, 0 = write)
.O_astrobe(spi_astrobe), // Address strobe to enable address decoding
.O_dstrobe(spi_dstrobe), // Data strobe to enable data decoding and encoding
.O_sync(spi_sync) // Sync pulse to enable reads or writes from memory
);
// Instantiate SPI address decoder.
spi_decoder #
(
.DATA_SIZE(ADDR_SIZE) // The size of the parallel output data.
)
spi_addr_decoder
(
.I_sclk(I_sclk), // Serial data clock
.I_enable(spi_astrobe), // Enable for the decoder
.I_sdi(I_sdi), // Serial data input
.O_data(O_addr) // Parallel output data
);
// Instantiate SPI input data decoder.
spi_decoder #
(
.DATA_SIZE(DATA_SIZE - 1) // The size of the parallel output data.
)
spi_data_decoder
(
.I_sclk(I_sclk), // Serial data clock
.I_enable(spi_data_dec_en), // Enable for the decoder
.I_sdi(I_sdi), // Serial data input
.O_data(spi_din_msbs) // Parallel output data
);
// Instantiate SPI output data encoder.
spi_encoder #
(
.DATA_SIZE(DATA_SIZE) // The size of the parallel input data.
)
spi_data_encoder
(
.I_sclk(I_sclk), // Serial data clock
.I_enable(spi_data_enc_en), // Enable for the decoder
.I_latch(spi_sync), // Latch for reading data into shift register
.I_data(I_dout), // Parallel input data
.O_sdo(O_sdo) // Serial data output
);
assign O_din = {spi_din_msbs, I_sdi}; // Assign parallel data input.
assign O_wen = spi_sync && !spi_rw; // Assign write enable to memory.
assign spi_data_dec_en = spi_dstrobe && !spi_rw; // Assign data decode enable.
assign spi_data_enc_en = spi_dstrobe && spi_rw; // Assign data encode enable.
endmodule
| 6.904081 |
module spi_process (
input rst_n, //reset ,low active
input clk,
//spi_slave
input mosi,
input csb,
input sck,
output miso,
//internal_bus
input [15:0] reg_dout,
output reg spi_req,
input spi_ack,
output reg [ 6:0] spi_addr,
output reg [15:0] reg_din
);
parameter DELAY = 2;
wire rec_flag;
wire [7:0] rec_data;
reg [7:0] send_data;
reg rec_flag_reg0;
reg rec_flag_reg1;
reg spi_we;
reg [2:0] spi_state;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
rec_flag_reg0 <= #DELAY 1'b0;
rec_flag_reg1 <= #DELAY 1'b0;
end else begin
rec_flag_reg0 <= #DELAY rec_flag;
rec_flag_reg1 <= #DELAY rec_flag_reg0;
end
end
wire rec_flag_dv;
assign rec_flag_dv = rec_flag_reg0 & !rec_flag_reg1;
wire sfd;
assign sfd = (rec_data == 8'hd5);
spi_slave spi_slave_inst (
.clk (clk),
.nrst (rst_n),
.ncs (csb),
.mosi (mosi),
.sck (sck),
.miso (miso),
.send_data(send_data),
.rec_flag (rec_flag),
.rec_data (rec_data)
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
spi_state <= #DELAY 3'b0;
spi_we <= #DELAY 1'b0;
spi_req <= #DELAY 1'b0;
spi_addr <= #DELAY 7'b0;
reg_din <= #DELAY 16'b0;
send_data <= #DELAY 8'hd5;
end else begin
case (spi_state)
3'b000: begin
if (rec_flag_dv & sfd) spi_state <= #DELAY 3'b001;
send_data <= #DELAY 8'hd5;
end
3'b001: begin
if (rec_flag_dv & sfd) begin
spi_state <= #DELAY 3'b010;
send_data <= #DELAY 8'h00;
end else if (rec_flag_dv & !sfd) spi_state <= #DELAY 3'b000;
end
3'b010: begin
if (rec_flag_dv) begin
spi_we <= #DELAY rec_data[7];
spi_addr <= #DELAY rec_data[6:0];
send_data <= #DELAY reg_dout[15:8];
spi_state <= #DELAY 3'b011;
end
end
3'b011: begin
if (rec_flag_dv) begin
reg_din[15:8] <= #DELAY rec_data;
send_data <= #DELAY reg_dout[7:0];
spi_state <= #DELAY 3'b100;
end
end
3'b100: begin
if (rec_flag_dv) begin
spi_req <= #DELAY spi_we;
reg_din[7:0] <= #DELAY rec_data;
send_data <= #DELAY 8'hd5;
spi_state <= #DELAY 3'b110;
end
end
3'b110: begin
if (spi_ack | !spi_req) begin
spi_req <= #DELAY 0;
spi_state <= #DELAY 3'b000;
end
end
endcase
end
end
endmodule
| 8.100182 |
module spi (
input wire clk, //
input wire clken, //
input wire enviar_dato, // a 1 para indicar que queremos enviar un dato por SPI
input wire recibir_dato, // a 1 para indicar que queremos recibir un dato
input wire [7:0] din, // del bus de datos de salida de la CPU
output reg [7:0] dout, // al bus de datos de entrada de la CPU
output wire oe, // el dato en dout es vlido
output reg spi_transfer_in_progress,
output wire sclk, // Interface SPI
output wire mosi, //
input wire miso //
);
reg [7:0] spireg = 8'hFF;
reg [4:0] count = 5'b10000;
reg data_from_miso = 1'b0;
assign mosi = spireg[7];
assign sclk = count[0];
assign oe = recibir_dato;
always @(posedge clk) begin
if (enviar_dato == 1'b1 && spi_transfer_in_progress == 1'b0) begin
spireg <= din;
count <= 5'b11110;
end else if (recibir_dato == 1'b1 && spi_transfer_in_progress == 1'b0) begin
dout <= spireg;
count <= 5'b11100;
end else if (count == 5'b11110) count <= 5'b00000;
else if (count == 5'b11100) begin
count <= 5'b00000;
spireg <= 8'hFF;
end else if (clken == 1'b1) begin
if (spi_transfer_in_progress == 1'b1) begin
if (sclk == 1'b1) // con SCLK a 1, en la transicin de 1 a 0, el registro se desplaza
spireg <= {spireg[6:0], data_from_miso};
else // con SCLK a 0, en la transicin de 0 a 1, MISO se samplea
data_from_miso <= miso;
count <= count + 5'd1;
end
end
end
always @* begin
if (count >= 5'b0000 && count < 5'b10000) spi_transfer_in_progress = 1'b1;
else spi_transfer_in_progress = 1'b0;
end
endmodule
| 7.760909 |
module spi_ram_btn #(
parameter [7:0] c_addr_btn = 8'hFB, // high addr byte of BTNs
parameter [7:0] c_addr_irq = 8'hF1, // high addr byte of IRQ flag
parameter c_debounce_bits = 20, // more -> slower BTNs
parameter c_addr_bits = 32, // don't touch
parameter c_sclk_capable_pin = 0 //, // 0-sclk is generic pin, 1-sclk is clock capable pin
) (
input wire clk, // faster than SPI clock
input wire csn,
sclk,
mosi, // SPI lines to be sniffed
inout wire miso, // 3-state line, active when csn=0
// BTNs
input wire [6:0] btn,
output wire irq,
// BRAM interface
output wire rd,
wr,
output wire [c_addr_bits-1:0] addr,
input wire [7:0] data_in,
output wire [7:0] data_out
);
// IRQ controller tracks BTN state
reg R_btn_irq;
reg [6:0] R_btn, R_btn_latch;
reg R_spi_rd;
reg [c_debounce_bits-1:0] R_btn_debounce;
always @(posedge clk) begin
R_spi_rd <= rd;
if (rd == 1'b0 && R_spi_rd == 1'b1 && addr[c_addr_bits-1:c_addr_bits-8] == c_addr_irq)
R_btn_irq <= 1'b0;
else // BTN state is read from 0xFBxxxxxx
begin
R_btn_latch <= btn;
if (R_btn != R_btn_latch && R_btn_debounce[$bits(
R_btn_debounce
)-1] == 1 && R_btn_irq == 0) begin
R_btn_irq <= 1'b1;
R_btn_debounce <= 0;
R_btn <= R_btn_latch;
end else if (R_btn_debounce[$bits(R_btn_debounce)-1] == 1'b0)
R_btn_debounce <= R_btn_debounce + 1;
end
end
wire [7:0] mux_data_in = addr[c_addr_bits-1:c_addr_bits-8] == c_addr_irq ? {R_btn_irq,7'b0}
: addr[c_addr_bits-1:c_addr_bits-8] == c_addr_btn ? {1'b0,R_btn}
: data_in;
assign irq = R_btn_irq;
spirw_slave_v #(
.c_sclk_capable_pin(c_sclk_capable_pin),
.c_addr_bits(c_addr_bits)
) spirw_slave_v_inst (
.clk(clk),
.csn(csn),
.sclk(sclk),
.mosi(mosi),
.miso(miso),
.wr(wr),
.rd(rd),
.addr(addr),
.data_in(mux_data_in),
.data_out(data_out)
);
endmodule
| 6.997779 |
module uses 24x iCE40 block-RAMs internally. In the iCE40, block-RAMs
* have two independently clocked ports, with one read-only port and one
* write-only port. Therefore, the read-port is clocked by the pixel clock,
* while the read-port
*/
module spi_ram_slave(clk, sck, cs, mosi, ram_addr, ram_data, ram_wr);
localparam WordWidth = 16;
localparam WordCount = 64 * 96;
input clk, sck, cs, mosi;
output [$clog2(WordCount)-1:0] ram_addr;
output [WordWidth-1:0] ram_data;
output ram_wr;
reg [2:0] sckr, csr;
reg [1:0] mosir;
always @(negedge clk) sckr <= {sckr[1:0], sck};
wire sck_rising = sckr[2:1] == 2'b01;
always @(negedge clk) csr <= {csr[1:0], cs};
wire cs_active = !csr[1];
always @(negedge clk) mosir <= {mosir[0], mosi};
wire mosi_data = mosir[1];
reg word_received;
reg [$clog2(WordWidth)-1:0] bits_remain;
reg [$clog2(WordCount)-1:0] addr;
reg [WordWidth-1:0] data;
assign ram_addr = addr;
assign ram_data = {data[7:0], data[15:8]};
assign ram_wr = word_received;
always @(negedge clk) begin
if(!cs_active) begin
bits_remain <= WordWidth - 1;
addr <= 0;
data <= 0;
end else if(sck_rising) begin
data <= {data[WordWidth-2:0], mosi_data};
bits_remain <= (bits_remain == 0) ? WordWidth - 1 : bits_remain - 1;
end
word_received <= (cs_active && sck_rising && bits_remain == 0);
if (word_received)
addr <= addr + 1;
end
endmodule
| 6.919368 |
module spi_rcv(CLK, SCK, MOSI, MISO, SSEL, LED);
input wire CLK, SCK, SSEL, MOSI;
output wire MISO, LED;
wire [7:0] MSG;
spi_slave spi1(.CLK(CLK),
.SCK(SCK),
.MOSI(MOSI),
.MISO(MISO),
.SSEL(SSEL),
.MSG(MSG));
assign LED = (MSG==8'b11111111);*/
module spi_rcv(clk,
led_gnd1, led_gnd2, //LED grounds
led6, led7, led8, led9, led10, led12, led13, led15, led16, led17, led18, led19, led20, led21,
led_second_tick
);
input wire clk;
output wire led_gnd1, led_gnd2;
output wire led6, led7, led8, led9, led10, led12, led13, led15, led16, led17, led18, led19, led20, led21;
output wire led_second_tick;
//clk - general clock 32768
reg [14:0] clk_div; initial clk_div <= 15'd0; //?? may be not implement
always @(posedge clk) clk_div <= clk_div + 1'b1;
wire divided_clk = clk_div[4];
reg divided_clk_prev;
always @(posedge clk) divided_clk_prev <= divided_clk;
wire divided_clk_posedge = ((divided_clk_prev==1'b0)&&(divided_clk==1'b1));
wire res;
pu_reset res_gen(.clk(clk), .res(res));
reg [3:0] gnd_sel;
always @(posedge clk) begin
if (res) begin
gnd_sel <= 4'b0001;
end else begin
if (divided_clk_posedge) gnd_sel <= {gnd_sel[2],gnd_sel[1],gnd_sel[0],gnd_sel[3]};
end
end
assign led_gnd1 = gnd_sel[0];
assign led_gnd2 = gnd_sel[2];
/*
wire [3:0] m = 0;
wire [3:0] mm;
wire [3:0] h;
wire [3:0] hh;
wire [6:0] s_m;
wire [6:0] s_mm;
wire [6:0] s_h;
wire [6:0] s_hh;
bcd2seg sseg_m( .sin(m), .sout(s_m));
bcd2seg sseg_mm(.sin(mm), .sout(s_mm));
bcd2seg sseg_h( .sin(h), .sout(s_h));
bcd2seg sseg_hh(.sin(hh), .sout(s_hh));
wire a1,b1,c1,d1,e1,f1,g1;
wire a2,b2,c2,d2,e2,f2,g2;
wire a3,b3,c3,d3,e3,f3,g3;
wire a4,b4,c4,d4,e4,f4,g4;
assign {g4, f4, e4, d4, c4, b4, a4} = s_m;
assign {g3, f3, e3, d3, c3, b3, a3} = s_mm;
assign {g2, f2, e2, d2, c2, b2, a2} = s_h;
assign {g1, f1, e1, d1, c1, b1, a1} = s_hh;
*/
//hide hour zero
//wire h_show = !(hh==0);
assign led6 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&(b1&&h_show)) || (led_gnd2&&(b1&&h_show)); // b1
assign led7 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&(a1&&h_show)) || (led_gnd2&&(g1&&h_show)); // a1/g1
assign led8 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&(d1&&h_show)) || (led_gnd2&&(e1&&h_show)); // d1/e1
assign led9 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&e2) || (led_gnd2&&(c1&&h_show)); // e2/c1
assign led10 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&g2) || (led_gnd2&&b2); // g2/b2
assign led12 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&d2) || (led_gnd2&&c2); // d2/c2
assign led13 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&f2) || (led_gnd2&&a2); // f2/a2
assign led15 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&a3) || (led_gnd2&&f3); // a3/f3
assign led16 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&b3) || (led_gnd2&&g3); // b3/g3
assign led17 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&c3) || (led_gnd2&&d3); // c3/d3
assign led18 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&e4) || ((led_gnd2)&&e3); // e3/e4 !!
assign led19 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&g4) || ((led_gnd2)&&b4); // g4/b4
assign led20 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&d4) || ((led_gnd2)&&c4); // d4/c4
assign led21 = (led_gnd1 || led_gnd2) ? 1 : 0;//(led_gnd1&&f4) || ((led_gnd2)&&a4); // f4/a4
//one second tick indicator
//assign led_second_tick = led_gnd1 && clk_div[14];
assign led_second_tick = 1;
endmodule
| 6.612991 |
module spi_receiver (
clock,
sclk,
extReset,
mosi,
cs,
transmitting,
// outputs...
op,
data,
execute
);
input clock;
input sclk;
input extReset;
input mosi;
input cs;
input transmitting;
output [7:0] op;
output [31:0] data;
output execute;
parameter READOPCODE = 1'h0, READLONG = 1'h1;
reg state, next_state; // receiver state
reg [1:0] bytecount, next_bytecount; // count rxed bytes of current command
reg [7:0] opcode, next_opcode; // opcode byte
reg [31:0] databuf, next_databuf; // data dword
reg execute, next_execute;
reg [2:0] bitcount, next_bitcount; // count rxed bits of current byte
reg [7:0] spiByte, next_spiByte;
reg byteready, next_byteready;
assign op = opcode;
assign data = databuf;
dly_signal mosi_reg (
clock,
mosi,
sampled_mosi
);
dly_signal dly_sclk_reg (
clock,
sclk,
dly_sclk
);
wire sclk_posedge = !dly_sclk && sclk;
dly_signal dly_cs_reg (
clock,
cs,
dly_cs
);
wire cs_negedge = dly_cs && !cs;
//
// Accumulate byte from serial input...
//
initial bitcount = 0;
always @(posedge clock or posedge extReset) begin
if (extReset) bitcount = 0;
else bitcount = next_bitcount;
end
always @(posedge clock) begin
spiByte = next_spiByte;
byteready = next_byteready;
end
always @* begin
#1;
next_bitcount = bitcount;
next_spiByte = spiByte;
next_byteready = 1'b0;
if (cs_negedge) next_bitcount = 0;
if (sclk_posedge) // detect rising edge of sclk
if (cs) begin
next_bitcount = 0;
next_spiByte = 0;
end else begin
next_bitcount = bitcount + 1'b1;
next_byteready = &bitcount;
next_spiByte = {spiByte[6:0], sampled_mosi};
end
end
//
// Command tracking...
//
initial state = READOPCODE;
always @(posedge clock or posedge extReset) begin
if (extReset) state = READOPCODE;
else state = next_state;
end
initial databuf = 0;
always @(posedge clock) begin
bytecount = next_bytecount;
opcode = next_opcode;
databuf = next_databuf;
execute = next_execute;
end
always @* begin
#1;
next_state = state;
next_bytecount = bytecount;
next_opcode = opcode;
next_databuf = databuf;
next_execute = 1'b0;
case (state)
READOPCODE : // receive byte
begin
next_bytecount = 0;
if (byteready) begin
next_opcode = spiByte;
if (spiByte[7]) next_state = READLONG;
else // short command
begin
next_execute = 1'b1;
next_state = READOPCODE;
end
end
end
READLONG : // receive 4 word parameter
begin
if (byteready) begin
next_bytecount = bytecount + 1'b1;
next_databuf = {spiByte, databuf[31:8]};
if (&bytecount) // execute long command
begin
next_execute = 1'b1;
next_state = READOPCODE;
end
end
end
endcase
end
endmodule
| 7.263457 |
module spi_reg #(
parameter ADDR = 8'h00,
parameter integer BYTES = 1
) (
// Bus interface
input wire [7:0] addr,
input wire [7:0] data,
input wire first,
input wire strobe,
// Reset
input wire [(8*BYTES)-1:0] rst_val,
// Output
output wire [(8*BYTES)-1:0] out_val,
output wire out_stb,
// Clock / Reset
input wire clk,
input wire rst
);
localparam integer WIDTH = 8 * BYTES;
// Signals
wire [WIDTH-1:0] nxt_val;
reg [WIDTH-1:0] cur_val;
wire [BYTES-1:0] hit_delay;
wire hit;
reg out_stb_i;
// History
generate
if (BYTES > 1) begin
reg [WIDTH-9:0] history;
reg [BYTES-2:0] bc;
always @(posedge clk or posedge rst)
if (rst) begin
history <= 0;
bc <= 0;
end else if (strobe) begin
history <= nxt_val[WIDTH-9:0];
bc <= hit_delay[BYTES-2:0];
end
assign nxt_val = {history, data};
assign hit_delay = {bc, first};
end else begin
assign nxt_val = data;
assign hit_delay = {first};
end
endgenerate
// Address match
assign hit = hit_delay[BYTES-1] & strobe & (addr == ADDR);
// Value register
always @(posedge clk or posedge rst)
if (rst) cur_val <= rst_val;
else if (hit) cur_val <= nxt_val;
always @(posedge clk) out_stb_i <= hit;
assign out_val = cur_val;
assign out_stb = out_stb_i;
endmodule
| 7.046065 |
module SPI_ri (
input wire clk,
input wire reset,
input wire [1:0] a,
input wire ce,
input wire wren,
output wire spi_int,
output reg [7:0] to_cpu,
input wire [7:0] from_cpu,
output wire mosi,
input wire miso,
output wire sclk,
output wire [7:0] ncs
);
// Registers:
// 0x0: data register
// 0x1: status register
// 0x2: clock speed register
// 0x3: device select
// Status bits:
// bit 0: TRANSFER_REQ
// bit 1: CPOL
// bit 2: CPHA
// bit 3: reserved
// bit 4: reserved
// bit 5: CONFIG_EN
// bit 6: TRANSFER_ACTIVE
// bit 7: READY
reg transfer_req;
reg transfer_active;
wire busy;
reg [7:0] clk_div;
reg cpol;
reg cpha;
reg [7:0] spi_ncs;
wire transfer_ready;
wire transfer_done;
wire [7:0] from_agent;
reg [7:0] data_from_master;
reg [7:0] data_from_slave;
assign spi_int = transfer_done;
assign ncs = spi_ncs;
assign busy = ce & wren;
always @(posedge clk) begin
if (reset) begin
transfer_req <= 1'b0;
transfer_active <= 1'b0;
clk_div <= 8'h00;
cpol <= 1'b0;
cpha <= 1'b0;
spi_ncs <= 8'hff;
to_cpu <= 8'h00;
end else begin
//CPU reads
case (a)
2'b00: to_cpu <= data_from_slave;
2'b01: to_cpu <= {~(transfer_active | busy), transfer_active, 3'b000, cpha, cpol, 1'b0};
2'b10: to_cpu <= clk_div;
2'b11: to_cpu <= spi_ncs;
endcase
//CPU writes
if (ce & wren) begin
case (a)
2'b00: //write data
begin
data_from_master <= from_cpu;
end
2'b01: //write status
begin
transfer_req <= from_cpu[0];
transfer_active <= from_cpu[0];
if (from_cpu[5]) begin
cpol <= from_cpu[1];
cpha <= from_cpu[2];
end
end
2'b10: //write clk_div
begin
clk_div <= from_cpu;
end
2'b11: //write ncs
begin
spi_ncs <= from_cpu;
end
endcase
end
if (transfer_ready & transfer_req) begin
transfer_req <= 1'b0;
end
if (transfer_done) begin
transfer_active <= 1'b0;
end
if (transfer_done) begin
data_from_slave <= from_agent;
end
end
end
spi_master spi_master_inst (
.clk(clk),
.rst(reset),
.clk_div(clk_div),
.cpol(cpol),
.cpha(cpha),
.sck (sclk),
.mosi(mosi),
.miso(miso),
.transfer_req (transfer_req),
.transfer_ready(transfer_ready),
.transfer_done (transfer_done),
.to_agent (data_from_master),
.from_agent(from_agent)
);
endmodule
| 6.775711 |
module SPI_rsvr (
//General Usage
input wire CLK,
input wire RST,
//Pmod Interface
input wire SDATA,
output reg SCLK,
output reg nCS,
//User Interface Signals
output reg [15:0] DATA,
input wire START,
output reg DONE
);
//--current_state : exectly current state of SPI_Receiver
//--next_state : exectly next state
//--temp : temp data from MIC
//--clk_counter : clk counter
//--shiftCounter : count to 15 and set to 0
//--enShiftCounter : to enable data shift in
//--enParalelLoad : to enable data to load on data register
reg [2:0] current_state;
reg [2:0] next_state;
reg [15:0] temp;
reg clk_div;
reg [31:0] clk_counter;
reg [3:0] shiftCounter;
reg enShiftCounter;
reg enParalelLoad;
initial begin
current_state <= 1;
clk_counter <= 0;
DATA <= 0;
end
//clk divider
parameter max_clk_cnt = 5;
always @(posedge (CLK) or posedge (RST)) begin
if (RST) begin
clk_counter <= 0;
clk_div <= 0;
SCLK <= 0;
//DATA <= 0;
end else if (clk_counter == max_clk_cnt) begin
clk_counter <= 0;
SCLK <= ~SCLK;
clk_div <= ~clk_div;
end else clk_counter <= clk_counter + 1;
end
//data counter
always @(posedge (clk_div)) begin
if (enShiftCounter == 1) begin
temp <= {temp[14:0], SDATA}; //sdata shift in and temp shift left
shiftCounter <= shiftCounter + 1; //shift counter plus 1
end else if (enParalelLoad) begin
shiftCounter <= 0;
DATA <= temp; //pass [11:0] effective bits to DATA
end
end
//SYNC_PROC
always @(posedge (clk_div) or posedge (RST)) begin
if (RST) begin
current_state <= 1; //current <= `Idle
end else current_state <= next_state;
end
//state decoder
always @(*) begin
if (current_state == 1) begin
enShiftCounter <= 0;
DONE <= 1;
nCS <= 1;
enParalelLoad <= 0;
end else if (current_state == 2) begin
enShiftCounter <= 1;
DONE <= 0;
nCS <= 0; //when nCS is low, data could be transfered
enParalelLoad <= 0;
end else begin //SyncData
enShiftCounter <= 0;
DONE <= 0;
nCS <= 1;
enParalelLoad <= 1;
end
end
//1: IDLE
//2: DATA SHIFT IN
//3: LOAD DATA
//FSM Schematics
//
//
//
// IDLE ------> DATA_SHIFT_IN ---------> LOAD_DATA
// ^ |
// |_____________________|
//
always @(*) begin //posedge(clk_div)
case (current_state)
1: begin
if (START) begin
next_state <= 2;
end else next_state <= current_state;
end
2: begin
if (shiftCounter == 15) begin
next_state <= 3;
end else next_state <= current_state;
end
3: begin
if (START == 0) begin
next_state <= 1;
end else next_state <= 2;
end
default: next_state <= current_state;
endcase
end
endmodule
| 7.080609 |
module spi_rx_test ();
reg clk, reset_n, ss_n;
wire [7:0] data, adrs;
wire valid, sdi;
reg [15:0] shift_reg;
assign sdi = shift_reg[15];
initial begin
clk <= 0;
reset_n <= 0;
ss_n <= 0;
shift_reg <= 16'h51AB;
#21 reset_n <= 1;
end
parameter CLOCK_INT = 10;
always #(CLOCK_INT / 2) clk <= ~clk;
always @(posedge clk) begin
if (!reset_n) begin
shift_reg <= shift_reg;
end else begin
shift_reg <= {shift_reg[14:0], shift_reg[15]};
end
end
spi_rx spi_rx (
.clk(clk),
.reset_n(reset_n),
.sdi(sdi),
.sck(clk),
.ss_n(ss_n),
.adrs(adrs),
.data(data),
.rx_valid(valid)
);
endmodule
| 6.802184 |
module spi_s (
input i_clk,
input i_reset,
input i_spi_mosi,
input i_spi_cs_n,
input i_spi_clk,
output [7:0] o_rx_data,
output o_rx_dataValid
);
// Registers
reg r_spi_mosi;
reg r_spi_cs_n;
reg r_spi_clk;
reg r_prev_spi_clk;
reg r_prev_spi_nss;
reg [7:0] r_rx_data;
reg [2:0] r_rx_indx;
// Wires
wire w_rising_spi_clk;
wire w_valid_spi_bit;
wire w_spi_packet_start;
wire [7:0] w_rx_data;
wire [2:0] w_rx_indx;
wire w_rx_dataValid;
always @(posedge i_clk) begin
// Buffered input data
r_spi_mosi <= i_spi_mosi;
r_spi_cs_n <= i_spi_cs_n;
r_spi_clk <= i_spi_clk;
// Previous state history
r_prev_spi_clk <= r_spi_clk;
r_prev_spi_nss <= r_spi_cs_n;
end
assign w_rising_spi_clk = r_spi_clk & ~r_prev_spi_clk; // Pulse on rising spi clk edge
assign w_valid_spi_bit = w_rising_spi_clk & ~r_spi_cs_n; // Valid spi bit when nss is low
assign w_spi_packet_start = r_prev_spi_nss & ~r_spi_cs_n; // Packet start on falling nss edge
// Capture incoming SPI Data
always @(posedge i_clk) begin
if (w_valid_spi_bit) begin
r_rx_data[w_rx_indx] <= r_spi_mosi;
r_rx_indx <= (w_rx_indx > 0 ? w_rx_indx - 1 : 7);
end else begin
r_rx_indx <= w_rx_indx;
end
end
assign w_rx_indx = (i_reset || w_spi_packet_start ? 7 : r_rx_indx);
assign w_rx_data = {r_rx_data[7:1], r_spi_mosi};
assign w_rx_dataValid = (w_valid_spi_bit && w_rx_indx == 0 ? 1 : 0);
// Push wires to output ports
assign o_rx_data = w_rx_data;
assign o_rx_dataValid = w_rx_dataValid;
endmodule
| 7.625664 |
module spi_sd (
input wire clk,
input wire spi_in,
output wire spi_out,
output wire cs,
output wire sck,
output wire led
);
zrb_sd_core #(8) spi_core (
clk,
8'b0,
1'b0,
spi_in,
1'b0
,,
led,
spi_out,
cs,
sck
);
endmodule
| 6.811218 |
module SPI_send (
input clk_50M, //50M
input rst_n,
input ENABLE,
input [15:0] DATA,
output reg CSB,
output SCLK,
output SDIN,
output DONE
);
reg [12:0] Divide_Cnt;
reg [3:0] Sel_Cnt;
reg clk_10K;
assign SCLK = (ENABLE) ? clk_10K : 0;
assign SDIN = (ENABLE) ? DATA[~Sel_Cnt] : 0;
assign DONE = CSB;
always @(posedge clk_50M or negedge rst_n) begin
if (!rst_n) CSB <= 1;
else if (Sel_Cnt == 15 && ENABLE) CSB <= 0;
else CSB <= 1;
end
always @(posedge clk_50M or negedge rst_n) begin
if (!rst_n) Divide_Cnt <= 13'd0;
else if(Divide_Cnt > 5000/2-1 && ENABLE)//10k
begin
Divide_Cnt <= 13'd0;
clk_10K <= ~clk_10K;
end else if (ENABLE) Divide_Cnt <= Divide_Cnt + 13'd1;
end
always @(negedge clk_10K or negedge rst_n) begin
if (!rst_n) Sel_Cnt <= 4'd0;
else Sel_Cnt <= Sel_Cnt + 4'd1;
end
endmodule
| 6.998533 |
module spi_sender (
input clk,
input sclk_posedge,
input sclk_negedge,
input reset,
input en,
input [DATA_BITS-1:0] data,
output reg out,
output done
);
parameter DATA_BITS = 48;
// Keep track of which bit we are on, so that we always
// start at bit 7 for synchonous byte-oriented communication
reg [2:0] bit_counter = 7;
always @(posedge clk) begin
if (sclk_negedge) begin
bit_counter <= bit_counter - 1;
end
end
// State machine logic
localparam STATE_IDLE = 0;
localparam STATE_SYNC = 1;
localparam STATE_ENABLED = 2;
reg [ 1:0] state = STATE_IDLE;
reg [$clog2(DATA_BITS)-1:0] out_index = DATA_BITS - 1;
reg [ DATA_BITS-1:0] saved_data = 0;
assign done = (STATE_IDLE == state) && !en;
always @(posedge clk) begin
if (reset) begin
state <= STATE_IDLE;
out = 1;
end else begin
case (state)
// Wait here until we get the enabled signal
STATE_IDLE: begin
out = 1;
if (en) begin
state <= STATE_SYNC;
out_index <= DATA_BITS - 1;
saved_data <= data;
end
end
// Wait until we are sending the MSB of the next byte
STATE_SYNC: begin
out = 1;
if (7 == bit_counter) begin
state <= STATE_ENABLED;
end
end
// Serialize bits onto the output wire, shifting to the
// next one on the falling clock edge
STATE_ENABLED: begin
out = saved_data[out_index];
if (out_index == 0) begin
state <= STATE_IDLE;
end else if (sclk_negedge) begin
out_index <= out_index - 1'b1;
end
end
endcase
end
end
endmodule
| 7.210176 |
module spi_sequence_detector #(
parameter KEY = 64'h929d9a9b2935a265,
parameter KEY_SIZE = 64
) (
input wire clk,
input wire rst,
input wire sin,
input wire sclk,
output wire match
);
reg [KEY_SIZE - 1 - 1:0] bitstream;
reg sclk_prev;
reg match_reg;
wire [KEY_SIZE - 1:0] key;
wire posedge_sclk, negedge_sclk;
assign key = {bitstream, sin};
assign posedge_sclk = (sclk == 1) && (sclk_prev == 0);
assign negedge_sclk = (sclk == 0) && (sclk_prev == 1);
assign match = negedge_sclk && match_reg;
always @(posedge clk) begin
if (rst) begin
bitstream <= 0;
sclk_prev <= 0;
match_reg <= 0;
end else begin
sclk_prev <= sclk;
if (posedge_sclk) begin
bitstream <= (bitstream << 1) | sin;
match_reg <= key == KEY;
end else if (negedge_sclk) begin
match_reg <= 0;
end
end
end
endmodule
| 8.533479 |
module spi_serdes (
// Host side signals
input reset_n,
input spi_clk,
input spi_clk_out,
input [15:0] data_tx,
input start,
output done,
output reg [ 7:0] data_rx,
// SPI side signals
output SPI_SDI,
input SPI_SDO,
output SPI_CSN,
output SPI_CLK
);
//=======================================================
// REG/WIRE declarations
//=======================================================
//
// State Encodings
localparam IDLE = 0; // Wait for start.
localparam WRITE = 1; // Write out data.
localparam READ = 2; // Read data.
localparam STALL = 3; // Stall for 1 cycle while asserting "done"
reg [1:0] state = IDLE;
reg [3:0] count;
reg [15:0] data_tx_reg;
reg read;
wire spi_active;
assign spi_active = (state == READ || state == WRITE);
// Chip select
assign SPI_CSN = ~(spi_active || start);
// SPI CLK
assign SPI_CLK = spi_active ? spi_clk_out : 1'b1;
// SPI Data. Hold high if not writing.
assign SPI_SDI = (state == WRITE) ? data_tx_reg[count] : 1'b1;
// Signal to higher level module that transaction is complete.
assign done = (state == STALL);
/* Theory of operation:
*
* - Wait in the idle state until the "start" signal is asserted.
* - Capture the contents of the TX input.
* - Capture the upper most bit of the TX input. If it is '1', this is a read
* operation and expect to receive 8 bits from the secondary.
*
* On the otherhand, if it is a '0', this is a read operation and thus
* the first 8 bits of TX data is an address, and the lower 8 bits are
* data.
*
* - Write out the first 8 bits. If reading, switch to the read state and
* shift in 8 bits of read data. Otherwise, write out the last 8 bits.
*
* - Branch to a STALL state to assert the "done" signal before returning
* to IDLE. Unfortunately necessary for timing at a higher level.
*/
always @(posedge spi_clk or negedge reset_n) begin
if (reset_n == 1'b0) begin
state <= IDLE;
end else begin
case (state)
IDLE: begin
count <= 4'hf;
if (start) begin
read <= data_tx[15];
data_tx_reg <= data_tx;
state <= WRITE;
end
end
WRITE: begin
// Decrement event counter
count <= count - 4'b0001;
// If reading and we're writing the last bit
// Stay here if performing a write. Otherwise, branch to the
// READ state.
if (read && (count == 8)) begin
state <= READ;
end else if (count == 0) begin
state <= STALL;
end
end
READ: begin
// Decrement event counter
count <= count - 4'b0001;
// Shift in data
data_rx <= {data_rx[6:0], SPI_SDO};
if (count == 0) begin
state <= STALL;
end
end
// One clock cycle idle state.
STALL: state <= IDLE;
endcase
end
end
endmodule
| 7.584351 |
module spi_shift_in (
clk,
rst,
go,
pos_edge,
neg_edge,
rx_negedge,
tip,
last,
p_out,
s_clk,
s_in
);
parameter Tp = 1;
input clk; // system clock
input rst; // reset
// input [`SPI_ADC_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
input go; // start stansfer
input pos_edge; // recognize posedge of sclk
input neg_edge; // recognize negedge of sclk
input rx_negedge; // s_in is sampled on negative edge
output tip; // transfer in progress
output last; // last bit
output [`SPI_ADC_CHAR-1:0] p_out; // parallel out
input s_clk; // serial clk
input s_in; // serial in
reg tip;
reg [ `SPI_ADC_CHAR_LEN_BITS:0] cnt; // data bit count
reg [ `SPI_ADC_CHAR-1:0] data; // shift register
wire [ `SPI_ADC_CHAR_LEN_BITS:0] rx_bit_pos; // next bit position
wire rx_clk; // rx clock enable
wire [`SPI_ADC_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
assign len = 'h20; //Fix LEN since that won't be changing, unless you only want to sample one channel
assign p_out = data;
//LSB last
assign rx_bit_pos = (rx_negedge ? cnt : cnt - {{`SPI_ADC_CHAR_LEN_BITS{1'b0}}, 1'b1});
assign last = !(|cnt);
assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
// Character bit counter
always @(posedge clk or posedge rst) begin
if (rst) cnt <= #Tp{`SPI_ADC_CHAR_LEN_BITS + 1{1'b0}};
else begin
if (tip) cnt <= #Tp pos_edge ? (cnt - {{`SPI_ADC_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
else cnt <= #Tp !(|len) ? {1'b1, {`SPI_ADC_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
end
end
// Transfer in progress
always @(posedge clk or posedge rst) begin
if (rst) tip <= #Tp 1'b0;
else if (go && ~tip) tip <= #Tp 1'b1;
else if (tip && last && pos_edge) tip <= #Tp 1'b0;
end
// Receiving bits from the line
always @(posedge clk or posedge rst) begin
if (rst) data <= #Tp{`SPI_ADC_CHAR{1'b0}};
else if (tip)
data[rx_bit_pos[`SPI_ADC_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_ADC_CHAR_LEN_BITS-1:0]];
end
endmodule
| 7.4541 |
module spi_shift_out (
clk,
rst,
len,
lsb,
go,
pos_edge,
neg_edge,
tx_negedge,
capture,
tip,
last,
p_in,
s_out
);
parameter Tp = 1;
input clk; // system clock
input rst; // reset
input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
input lsb; // lbs first on the line
input go; // start stansfer
input capture; //
input pos_edge; // recognize posedge of sclk
input neg_edge; // recognize negedge of sclk
input tx_negedge; // s_out is driven on negative edge
output tip; // transfer in progress
output last; // last bit
input [23:0] p_in; // parallel in
output s_out; // serial out
reg s_out;
reg tip;
reg [`SPI_CHAR_LEN_BITS:0] cnt; // data bit count
reg [ `SPI_MAX_CHAR-1:0] data; // shift register
wire [`SPI_CHAR_LEN_BITS:0] tx_bit_pos; // next bit position
wire tx_clk; // tx clock enable
assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1};
assign last = !(|cnt);
assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
// Character bit counter
always @(posedge clk or posedge rst) begin
if (rst) cnt <= #Tp{`SPI_CHAR_LEN_BITS + 1{1'b0}};
else begin
if (tip) cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
else cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
end
end
// Transfer in progress
always @(posedge clk or posedge rst) begin
if (rst) tip <= #Tp 1'b0;
else if (go && ~tip) tip <= #Tp 1'b1;
else if (tip && last && pos_edge) tip <= #Tp 1'b0;
end
// Sending bits to the line
always @(posedge clk or posedge rst) begin
if (rst) s_out <= #Tp 1'b0;
else s_out <= #Tp(tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
end
// Capture data from p_in to the
always @(posedge clk or posedge rst) begin
if (rst) data <= #Tp{24{1'b0}};
else if (!tip && capture) data <= #Tp p_in;
end
endmodule
| 7.503529 |
module spi_simple (
// SPI pads
input wire spi_mosi,
output wire spi_miso,
input wire spi_cs_n,
input wire spi_clk,
// Interface
output wire [7:0] addr,
output wire [7:0] data,
output reg first,
output reg last,
output wire strobe,
input wire [7:0] out,
// Clock / Reset
input wire clk,
input wire rst
);
// Signals
// -------
wire spi_cs_n_i;
wire spi_cs_n_r;
wire spi_cs_n_f;
wire spi_clk_r;
wire spi_clk_f;
wire spi_mosi_i;
reg spi_miso_out;
wire spi_miso_oe;
reg [8:0] shift_reg;
reg [7:0] addr_reg;
reg [2:0] bit_cnt;
reg has_byte;
reg addr_done;
reg strobe_addr;
reg strobe_ext;
// IOs
// ---
// IOs
spi_simple_io_in cs_n_io_I (
.pad (spi_cs_n),
.val (spi_cs_n_i),
.rise(spi_cs_n_r),
.fall(spi_cs_n_f),
.clk (clk),
.rst (rst)
);
spi_simple_io_in clk_io_I (
.pad (spi_clk),
.val (),
.rise(spi_clk_r),
.fall(spi_clk_f),
.clk (clk),
.rst (rst)
);
spi_simple_io_in mosi_io_I (
.pad (spi_mosi),
.val (spi_mosi_i),
.rise(),
.fall(),
.clk (clk),
.rst (rst)
);
spi_simple_io_out miso_io_I (
.pad(spi_miso),
.val(spi_miso_out),
.oe (spi_miso_oe),
.clk(clk),
.rst(rst)
);
// Control logic
// -------------
// Output of single byte
assign spi_miso_oe = ~spi_cs_n_i;
always @(posedge clk)
if (spi_cs_n_f) spi_miso_out <= out[7];
else if (spi_clk_f) spi_miso_out <= shift_reg[7] & ~(has_byte | addr_done);
// Shift register
always @(posedge clk)
if (spi_cs_n_f) shift_reg <= {1'b0, out};
else if (spi_clk_r | spi_cs_n_r) shift_reg <= {shift_reg[7:0], spi_mosi_i};
// Bit counter
always @(posedge clk)
if (spi_cs_n_f) bit_cnt <= 0;
else bit_cnt <= bit_cnt + spi_clk_r;
// Strobes
always @(posedge clk)
if (spi_cs_n_f) begin
// Technically reset isn't needed ... but sharing it should allow
// packing in the same TILE as the other bit using that reset line
has_byte <= 1'b0;
strobe_addr <= 1'b0;
strobe_ext <= 1'b0;
end else begin
has_byte <= (has_byte & ~(spi_clk_r | spi_cs_n_r)) | ((bit_cnt == 3'b111) & spi_clk_r);
strobe_addr <= has_byte & (spi_clk_r | spi_cs_n_r) & ~addr_done;
strobe_ext <= has_byte & (spi_clk_r | spi_cs_n_r) & addr_done;
end
// Address register
always @(posedge clk)
if (spi_cs_n_f) addr_done <= 1'b0;
else addr_done <= addr_done | strobe_addr;
always @(posedge clk) if (strobe_addr) addr_reg <= shift_reg[8:1];
// Outputs
assign addr = addr_reg;
assign data = shift_reg[8:1];
assign strobe = strobe_ext;
always @(posedge clk) begin
if (spi_cs_n_f) begin
first <= 1'b1;
last <= 1'b0;
end else begin
first <= first & ~strobe_ext;
last <= last | spi_cs_n_r;
end
end
endmodule
| 7.87219 |
module spi_simple_io_in (
input wire pad,
output wire val,
output reg rise,
output reg fall,
input wire clk,
input wire rst
);
// Signals
wire iob_out;
reg val_i;
// IOB
SB_IO #(
.PIN_TYPE(6'b000000),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0),
.IO_STANDARD("SB_LVCMOS")
) cs_n_iob_I (
.PACKAGE_PIN(pad),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(clk),
// .OUTPUT_CLK(1'b0),
.OUTPUT_ENABLE(1'b0),
.D_OUT_0(1'b0),
.D_OUT_1(1'b0),
.D_IN_0(iob_out),
.D_IN_1()
);
// Value and transition registers
always @(posedge clk or posedge rst)
if (rst) begin
val_i <= 1'b0;
rise <= 1'b0;
fall <= 1'b0;
end else begin
val_i <= iob_out;
rise <= iob_out & ~val_i;
fall <= ~iob_out & val_i;
end
assign val = val_i;
endmodule
| 6.608719 |
module spi_simple_io_out (
output wire pad,
input wire val,
input wire oe,
input wire clk,
input wire rst
);
SB_IO #(
.PIN_TYPE(6'b101001),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0),
.IO_STANDARD("SB_LVCMOS")
) miso_iob_I (
.PACKAGE_PIN(pad),
.CLOCK_ENABLE(1'b1),
.INPUT_CLK(clk),
.OUTPUT_CLK(1'b0),
.OUTPUT_ENABLE(oe),
.D_OUT_0(val),
.D_OUT_1(1'b0),
.D_IN_0(),
.D_IN_1()
);
endmodule
| 6.608719 |
module SPI_Slave (
clk,
SCK,
SSEL,
MOSI,
MISO //SPI communication pin
);
input clk;
input SCK, SSEL, MOSI;
output MISO;
reg [7:0] mem;
assign MISO = MOSI;
always @(posedge SCK) begin
if (SSEL) begin
if (mem == 255) begin
mem <= 0;
end else begin
mem <= mem + 1;
end
end
end
endmodule
| 6.615248 |
module spi_slave_88 (
input clk,
input rst,
input ss,
input mosi,
output reg miso,
input sck,
output reg done,
input [7:0] data_in,
output reg [7:0] data_out
);
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
reg [2:0] M_bit_ct_d, M_bit_ct_q = 1'h0;
reg [7:0] M_data_d, M_data_q = 1'h0;
reg M_mosi_reg_d, M_mosi_reg_q = 1'h0;
reg M_miso_reg_d, M_miso_reg_q = 1'h0;
reg [1:0] M_sck_reg_d, M_sck_reg_q = 1'h0;
reg M_ss_reg_d, M_ss_reg_q = 1'h0;
reg [7:0] M_data_out_reg_d, M_data_out_reg_q = 1'h0;
reg M_done_reg_d, M_done_reg_q = 1'h0;
always @* begin
M_sck_reg_d = M_sck_reg_q;
M_mosi_reg_d = M_mosi_reg_q;
M_done_reg_d = M_done_reg_q;
M_ss_reg_d = M_ss_reg_q;
M_data_d = M_data_q;
M_bit_ct_d = M_bit_ct_q;
M_data_out_reg_d = M_data_out_reg_q;
M_miso_reg_d = M_miso_reg_q;
miso = M_miso_reg_q;
done = M_done_reg_q;
data_out = M_data_out_reg_q;
M_ss_reg_d = ss;
M_mosi_reg_d = mosi;
M_sck_reg_d = {M_sck_reg_q[0+0-:1], sck};
M_done_reg_d = 1'h0;
if (M_ss_reg_q) begin
M_bit_ct_d = 3'h7;
M_data_d = data_in;
M_miso_reg_d = data_in[7+0-:1];
end else begin
if (M_sck_reg_q == 2'h1) begin
M_data_out_reg_d[(M_bit_ct_q)*1+0-:1] = M_mosi_reg_q;
M_bit_ct_d = M_bit_ct_q - 1'h1;
if (M_bit_ct_q == 1'h0) begin
M_done_reg_d = 1'h1;
M_data_d = data_in;
end
end else begin
if (M_sck_reg_q == 2'h2) begin
M_miso_reg_d = M_data_q[(M_bit_ct_q)*1+0-:1];
end
end
end
end
always @(posedge clk) begin
M_mosi_reg_q <= M_mosi_reg_d;
M_miso_reg_q <= M_miso_reg_d;
M_sck_reg_q <= M_sck_reg_d;
M_ss_reg_q <= M_ss_reg_d;
M_data_out_reg_q <= M_data_out_reg_d;
M_done_reg_q <= M_done_reg_d;
if (rst == 1'b1) begin
M_bit_ct_q <= 1'h0;
M_data_q <= 1'h0;
end else begin
M_bit_ct_q <= M_bit_ct_d;
M_data_q <= M_data_d;
end
end
endmodule
| 6.539713 |
module will get 64 bytes and then return the count 64 at next clks
*******************************************************************************/
module spi_slave_b2b_reduced(
clk,sck,mosi,miso,ssel,rst_n,recived_status
);
input clk;
input rst_n;
input sck,mosi,ssel;
output miso;
output recived_status;
reg recived_status;
reg sselr;
reg [7:0] byte_data_sent;
reg [7:0] next_byte_data_sent;
reg [7:0] bit_cnt;
wire ssel_active;
wire sck_risingedge;
wire sck_fallingedge;
wire ssel_startmessage;
wire ssel_endmessage;
/*******************************************************************************
*detect the rising edge and falling edge of sck
*******************************************************************************/
reg curr, last;
always@(posedge clk)
begin
if(!rst_n) begin
curr <= 1'b0;
last <= 1'b0;
end
else begin
curr <= sck;
last <= curr;
end
end
//Raising edge
assign sck_risingedge = curr & (~last);
//failing edge
assign sck_fallingedge = ~curr & (last);
/*******************************************************************************
*detect ssel status
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
sselr <= 1'h1;
else
sselr <= ssel;
end
assign ssel_active = (~sselr) ? 1'b0 : 1'b1; // SSEL is active high
/*******************************************************************************
*read from mosi
*******************************************************************************/
/*******************************************************************************
*SPI slave reveive in 8-bits format
*******************************************************************************/
/*******************************************************************************
*SPI slave send data
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
byte_data_sent <= 8'h1;
next_byte_data_sent <= 8'h2;
bit_cnt <= 8'h0;
end
else begin
if(ssel_active && sck_fallingedge)
begin
if(next_byte_data_sent == 8'h41)
next_byte_data_sent <= 8'h1;
if (bit_cnt == 8'h7f)
begin
byte_data_sent <= next_byte_data_sent;
bit_cnt <= {bit_cnt[6:0], 1'b1};
end
else
byte_data_sent <= {byte_data_sent[6:0], 1'b0};
bit_cnt <= {bit_cnt[6:0], 1'b1};
end
else begin
if(ssel_active && sck_risingedge) begin
/*
update the next byte
*/
if(bit_cnt == 8'hff)
begin
bit_cnt <= 8'h0;
next_byte_data_sent <= next_byte_data_sent + 1;
end
end
end
end
end
assign miso = byte_data_sent[7]; // send MSB first
endmodule
| 7.500858 |
module will get 64 bytes and then return the count 64 at next clks
*******************************************************************************/
module spi_slave_b2b_reduced(
clk,sck,mosi,miso,ssel,rst_n,recived_status
);
input clk;
input rst_n;
input sck,mosi,ssel;
output miso;
output recived_status;
reg recived_status;
reg sselr;
reg [7:0] byte_data_sent;
reg [7:0] next_byte_data_sent;
reg [7:0] bit_cnt;
wire ssel_active;
wire sck_risingedge;
wire sck_fallingedge;
wire ssel_startmessage;
wire ssel_endmessage;
/*******************************************************************************
*detect the rising edge and falling edge of sck
*******************************************************************************/
reg curr, last;
always@(posedge clk)
begin
if(!rst_n) begin
curr <= 1'b0;
last <= 1'b0;
end
else begin
curr <= sck;
last <= curr;
end
end
//Raising edge
assign sck_risingedge = curr & (~last);
//failing edge
assign sck_fallingedge = ~curr & (last);
/*******************************************************************************
*detect ssel status
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
sselr <= 1'h1;
else
sselr <= ssel;
end
assign ssel_active = (~sselr) ? 1'b1 : 1'b0; // SSEL is active low
/*******************************************************************************
*read from mosi
*******************************************************************************/
/*******************************************************************************
*SPI slave reveive in 8-bits format
*******************************************************************************/
/*******************************************************************************
*SPI slave send data
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
byte_data_sent <= 8'h1;
next_byte_data_sent <= 8'h2;
bit_cnt <= 8'h0;
end
else begin
if(ssel_active && sck_fallingedge)
begin
if(next_byte_data_sent == 8'h41)
next_byte_data_sent <= 8'h1;
if (bit_cnt == 8'h7f)
begin
byte_data_sent <= next_byte_data_sent;
bit_cnt <= {bit_cnt[6:0], 1'b1};
end
else
byte_data_sent <= {byte_data_sent[6:0], 1'b0};
bit_cnt <= {bit_cnt[6:0], 1'b1};
end
else begin
if(ssel_active && sck_risingedge) begin
/*
update the next byte
*/
if(bit_cnt == 8'hff)
begin
bit_cnt <= 8'h0;
next_byte_data_sent <= next_byte_data_sent + 1;
end
end
end
end
end
assign miso = byte_data_sent[7]; // send MSB first
endmodule
| 7.500858 |
module spi_slave (
spi1_miso_io,
spi1_mosi_io,
spi1_sck_io,
spi1_scs_n_i,
spi1_mcs_n_o,
rst_i,
ipload_i,
ipdone_o,
sb_clk_i,
sb_wr_i,
sb_stb_i,
sb_adr_i,
sb_dat_i,
sb_dat_o,
sb_ack_o,
spi_pirq_o,
spi_pwkup_o
) /* synthesis syn_black_box syn_declare_black_box=1 */;
inout spi1_miso_io;
inout spi1_mosi_io;
inout spi1_sck_io;
input spi1_scs_n_i;
output [3:0] spi1_mcs_n_o;
input rst_i;
input ipload_i;
output ipdone_o;
input sb_clk_i;
input sb_wr_i;
input sb_stb_i;
input [7:0] sb_adr_i;
input [7:0] sb_dat_i;
output [7:0] sb_dat_o;
output sb_ack_o;
output [1:0] spi_pirq_o;
output [1:0] spi_pwkup_o;
endmodule
| 7.335456 |
module SPI_SLAVE_BOT_1_LATE_DATA_REFLECTOR #(
parameter CPHA =1, //clock phase
parameter CPOL =1, //clock polarity
parameter PACK_LENGTH =8, //number of bits in package
parameter PACK_BIT_SEQUENCE_TRANSMIT=1,//1-major bit forward;0-junior bit forward;
parameter PACK_BIT_SEQUENCE_RECEIVE=1//1-major bit forward;0-junior bit forward;
) (
input wire MOSI,
input wire CS,
input wire SCLK,
input wire IN_RESET,
output wire MISO
);
reg [PACK_LENGTH-1:0] REG_DATA;
initial begin
REG_DATA = 0;
end
wire [PACK_LENGTH-1:0] OUT_RECEIVE_DATA, IN_TRANSMIT_DATA;
SPI_FPGA_SLAVE #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(PACK_BIT_SEQUENCE_RECEIVE)
) SLAVE (
IN_TRANSMIT_DATA,
MOSI,
CS,
SCLK,
IN_RESET,
MISO,
OUT_RECEIVE_DATA
);
always @(posedge CS) begin
REG_DATA <= OUT_RECEIVE_DATA;
end
assign IN_TRANSMIT_DATA = REG_DATA;
endmodule
| 7.117769 |
module spi_slave_buffer (
input wire reset,
input wire clk,
input wire mosi,
output reg miso,
input wire sel,
output reg [7:0] buffer
);
always @(posedge clk or posedge reset) begin
if (reset) begin
buffer <= 8'h00;
miso <= 1'b0;
end else if (sel) begin
buffer <= buffer << 1;
buffer[0] <= mosi;
miso <= 1'b1;
end
end
endmodule
| 6.811609 |
module spi_slave_cpha0 (
clk,
sck,
mosi,
miso,
ssel,
rst_n
);
input clk;
input rst_n;
input sck, mosi, ssel;
output miso;
reg recived_status;
reg [2:0] sckr;
reg [2:0] sselr;
reg [1:0] mosir;
reg [2:0] bitcnt;
reg [7:0] bytecnt;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
wire ssel_active;
wire sck_risingedge;
wire sck_fallingedge;
wire mosi_data;
/*******************************************************************************
*detect the rising edge and falling edge of sck
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if (!rst_n) sckr <= 3'h0;
else sckr <= {sckr[1:0], sck};
end
assign sck_risingedge = (sckr[2:1] == 2'b01) ? 1'b1 : 1'b0;
assign sck_fallingedge = (sckr[2:1] == 2'b10) ? 1'b1 : 1'b0;
/*******************************************************************************
*detect starts at falling edge and stops at rising edge of ssel
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if (!rst_n) sselr <= 3'h0;
else sselr <= {sselr[1:0], ssel};
end
assign ssel_active = (~sselr[1]) ? 1'b1 : 1'b0; // SSEL is active low
/*******************************************************************************
*read from mosi we double sample the data
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if (!rst_n) mosir <= 2'h0;
else mosir <= {mosir[0], mosi};
end
assign mosi_data = mosir[1];
/*******************************************************************************
*SPI slave reveive in 8-bits format
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
bitcnt <= 3'b000;
byte_data_received <= 8'h0;
end else begin
if (~ssel_active) bitcnt <= 3'b000;
else begin
if (sck_risingedge) begin
bitcnt <= bitcnt + 3'b001;
byte_data_received <= {byte_data_received[6:0], mosi_data};
end else begin
bitcnt <= bitcnt;
byte_data_received <= byte_data_received;
end
end
end
end
/* indicate a byte has been received */
always @(posedge clk or negedge rst_n) begin
if (!rst_n) byte_received <= 1'b0;
else byte_received <= ssel_active && sck_risingedge && (bitcnt == 3'b111);
end
/*******************************************************************************
*SPI slave send date
*******************************************************************************/
assign miso = mosi_data; // send MSB first
endmodule
| 7.373032 |
module spi_slave_dc_fifo #(
parameter DATA_WIDTH = 32,
parameter BUFFER_DEPTH = 8
) (
clk_a,
rstn_a,
data_a,
valid_a,
ready_a,
clk_b,
rstn_b,
data_b,
valid_b,
ready_b
);
//parameter DATA_WIDTH = 32;
//parameter BUFFER_DEPTH = 8;
input wire clk_a;
input wire rstn_a;
input wire [DATA_WIDTH - 1:0] data_a;
input wire valid_a;
output wire ready_a;
input wire clk_b;
input wire rstn_b;
output wire [DATA_WIDTH - 1:0] data_b;
output wire valid_b;
input wire ready_b;
wire [ DATA_WIDTH - 1:0] data_async;
wire [BUFFER_DEPTH - 1:0] write_token;
wire [BUFFER_DEPTH - 1:0] read_pointer;
dc_token_ring_fifo_din #(
.DATA_WIDTH (DATA_WIDTH),
.BUFFER_DEPTH(BUFFER_DEPTH)
) u_din (
.clk(clk_a),
.rstn(rstn_a),
.data(data_a),
.valid(valid_a),
.ready(ready_a),
.write_token(write_token),
.read_pointer(read_pointer),
.data_async(data_async)
);
dc_token_ring_fifo_dout #(
.DATA_WIDTH (DATA_WIDTH),
.BUFFER_DEPTH(BUFFER_DEPTH)
) u_dout (
.clk(clk_b),
.rstn(rstn_b),
.data(data_b),
.valid(valid_b),
.ready(ready_b),
.write_token(write_token),
.read_pointer(read_pointer),
.data_async(data_async)
);
endmodule
| 8.005999 |
module spi (
input wire iCLK,
input wire RST,
input wire SCLK,
input wire SCSN,
input wire MOSI,
output reg start_of_transfer,
output reg end_of_transfer,
output reg [7:0] mosi_data_out,
output reg mosi_data_ready,
output reg MISO,
output reg miso_data_request,
input [7:0] miso_data_in
);
// //////////////////////////////////////////////////////
// synchronizers
reg [1:0] scsn_resync;
reg [1:0] sclk_resync;
reg [1:0] mosi_resync;
reg [1:0] scsn_edge;
reg [1:0] sclk_edge;
wire scsn_rs;
wire mosi_rs;
reg rising_sclk;
reg falling_sclk;
always @(posedge iCLK)
if (RST) begin
sclk_resync <= 0;
sclk_edge <= 'h0;
scsn_resync <= 'h3;
scsn_edge <= 'h3;
mosi_resync <= 0;
end else begin
scsn_resync <= {scsn_resync[0], SCSN};
scsn_edge <= {scsn_edge[0], scsn_resync[1]};
sclk_resync <= {sclk_resync[0], SCLK};
sclk_edge <= {sclk_edge[0], sclk_resync[1]};
mosi_resync <= {mosi_resync[0], MOSI};
end
assign scsn_rs = scsn_resync[1];
assign mosi_rs = mosi_resync[1];
always @(posedge iCLK)
if (RST) begin
rising_sclk <= 0;
falling_sclk <= 0;
start_of_transfer <= 0;
end_of_transfer <= 0;
end else begin
rising_sclk <= !sclk_edge[1] & sclk_edge[0] & !scsn_rs;
falling_sclk <= sclk_edge[1] & !sclk_edge[0] & !scsn_rs;
start_of_transfer <= scsn_edge[1] & !scsn_edge[0];
end_of_transfer <= !scsn_edge[1] & scsn_edge[0];
end
// //////////////////////////////////////////////////////
// strobes
reg [2:0] bitcount;
reg byteCountStrobe;
always @(posedge iCLK)
if (RST) begin
bitcount <= 0;
byteCountStrobe <= 0;
end else if (start_of_transfer) begin
bitcount <= 0;
byteCountStrobe <= 0;
end else if (falling_sclk) begin
bitcount <= bitcount + 1'b1;
byteCountStrobe <= (bitcount == 'h7);
end else if (byteCountStrobe | scsn_rs) byteCountStrobe <= 0;
// //////////////////////////////////////////////////////
// MOSI snapshot register and output
reg [7:0] mosi_data_shift_reg;
always @(posedge iCLK)
if (RST) begin
mosi_data_shift_reg <= 0;
end else if (rising_sclk) begin
mosi_data_shift_reg <= {mosi_data_shift_reg[6:0], mosi_rs};
end
always @(posedge iCLK)
if (RST) begin
mosi_data_out <= 0;
end else if (byteCountStrobe) begin
mosi_data_out <= mosi_data_shift_reg;
end
always @(posedge iCLK)
if (RST) mosi_data_ready <= 0;
else mosi_data_ready <= byteCountStrobe;
// //////////////////////////////////////////////////////
// MISO input capture and presentation to host
reg [7:0] miso_data_shift_reg;
always @(posedge iCLK)
if (RST) miso_data_request <= 0;
else miso_data_request <= byteCountStrobe;
always @(posedge iCLK)
if (RST) begin
miso_data_shift_reg <= 0;
end else if (miso_data_request) begin
miso_data_shift_reg <= miso_data_in;
end else if (falling_sclk) miso_data_shift_reg <= {miso_data_shift_reg[6:0], 1'b0};
always @(posedge iCLK)
if (RST) MISO <= 0;
else MISO <= miso_data_shift_reg[7];
endmodule
| 7.760909 |
module spi_slave (
input wire reset,
input wire en,
input wire DATA_IN0,
input wire DATA_IN1,
input wire SCK,
input wire SSEL,
input wire clk,
// input [31:0] data32, //added feb03
//output MISO,
output wire [31:0] rx_out0,
output wire [31:0] rx_out1,
output wire rdy
);
//define wires and regs
reg [2:0] SCKr;
wire SCK_risingedge, SCK_fallingedge;
reg [2:0] SSELr;
wire SSEL_active, SSEL_startmessage;
//wire SSEL_endmessage;
reg [1:0] MOSIr_0, MOSIr_1;
wire MOSI_data_0, MOSI_data_1;
//counts 32 bits - need 5-bit counter
reg [ 4:0] bitcnt = 5'b00000;
reg [31:0] data_sent = 32'hF0F0F0;
reg [31:0] data_received_internal_0 = 0, data_received_0 = 0;
reg [31:0] data_received_internal_1 = 0, data_received_1 = 0;
reg rdy_internal = 0;
//some combination logics
assign SCK_risingedge = (SCKr[2:0] == 3'b011);
assign SCK_fallingedge = (SCKr[2:0] == 3'b100);
assign SSEL_startmessage = (SSELr[2:0] == 3'b100);
//assign SSEL_endmessage = (SSELr[2:0] == 3'b011);
assign SSEL_active = ~SSELr[1]; //SSEL active low
assign MOSI_data_0 = MOSIr_0[1];
assign MOSI_data_1 = MOSIr_1[1];
always @(negedge clk) begin
//keep track of SPI signals
SCKr <= {SCKr[1:0], SCK};
SSELr <= {SSELr[1:0], SSEL};
MOSIr_0 <= {MOSIr_0[0], DATA_IN0};
MOSIr_1 <= {MOSIr_1[0], DATA_IN1};
end
//******************************************************//
//DATA_IN
//******************************************************//
always @(posedge clk) begin
if (reset || ~SSEL_active || ~en) begin
bitcnt <= 5'b00000;
rdy_internal <= 0;
end else if (SCK_risingedge) begin
bitcnt <= bitcnt + 5'b00001;
//shift-left reg (MSB --> LSB)
data_received_internal_0 <= {data_received_internal_0[30:0], MOSI_data_0};
data_received_internal_1 <= {data_received_internal_1[30:0], MOSI_data_1};
end
rdy_internal <= (bitcnt == 5'b11111) && SSEL_active && SCK_risingedge;
if (rdy_internal) begin
data_received_0 <= data_received_internal_0;
data_received_1 <= data_received_internal_1;
end
end
assign rdy = rdy_internal;
//******************************************************//
//MISO
//******************************************************//
reg [31:0] ack = 0;
always @(posedge clk) begin
if (SSEL_startmessage) ack <= ack + 1; //just ack with cnt
else if (reset) ack <= 0;
end
//
// always @ (posedge clk)
// if(SSEL_active)
// begin
// if(SSEL_startmessage)
// data_sent <=data32;
// else
// if(SCK_fallingedge)
// begin
// if(bitcnt==5'b00000)
// data_sent <= 32'h00000000;
// else
// data_sent <= {data_sent[30:0], 1'b0};
// end
// end
//assign MISO = data_sent[31]; // send MSB first
assign rx_out0 = data_received_0;
assign rx_out1 = data_received_1;
endmodule
| 7.335456 |
module spi_slave_model (
input wire csn;
input wire sck
input wire di;
output wire do
);
//
// Variable declaration
//
wire debug = 1'b1;
wire cpol = 1'b0;
wire cpha = 1'b0;
reg [7:0] mem [7:0]; // initiate memory
reg [2:0] mem_adr; // memory address
reg [7:0] mem_do; // memory data output
reg [7:0] sri, sro; // 8bit shift register
reg [2:0] bit_cnt;
reg ld;
wire clk;
//
// module body
//
assign clk = cpol ^ cpha ^ sck;
// generate shift registers
always @(posedge clk)
sri <= #1 {sri[6:0],di};
always @(posedge clk)
if (&bit_cnt)
sro <= #1 mem[mem_adr];
else
sro <= #1 {sro[6:0],1'bx};
assign do = sro[7];
//generate bit-counter
always @(posedge clk, posedge csn)
if(csn)
bit_cnt <= #1 3'b111;
else
bit_cnt <= #1 bit_cnt - 3'h1;
//generate access done signal
always @(posedge clk)
ld <= #1 ~(|bit_cnt);
always @(negedge clk)
if (ld) begin
mem[mem_adr] <= #1 sri;
mem_adr <= #1 mem_adr + 1'b1;
end
initial
begin
bit_cnt=3'b111;
mem_adr = 0;
sro = mem[mem_adr];
end
endmodule
| 7.009262 |
module SPI_SLAVE_PWM #(
parameter CPHA = 1, //clock phase
parameter CPOL = 1, //clock polarity
parameter PACK_LENGTH = 8, //number of bits in package
parameter PACK_BIT_SEQUENCE_TRANSMIT = 1, //1-major bit forward;0-junior bit forward;
parameter PACK_BIT_SEQUENCE_RECEIVE = 1, //1-major bit forward;0-junior bit forward;
parameter CLOCK_FREQUENCY = 50000000,
parameter PWM_FREQUENCY = CLOCK_FREQUENCY / (MAX_VALUE - 1),
parameter MAX_VALUE = 2 ** PACK_LENGTH - 1,
parameter DEEP_FILL_FACTOR = PACK_LENGTH
) (
input IN_CLOCK,
input MOSI,
input CS,
input IN_RESET,
output OUT_PWM_SIGNAL
);
wire IN_ENABLE;
assign IN_ENABLE = 1'b1;
wire [DEEP_FILL_FACTOR-1:0] IN_PWM_FILL_FACTOR;
wire [PACK_LENGTH-1:0] OUT_RECEIVE_DATA;
assign IN_PWM_FILL_FACTOR = OUT_RECEIVE_DATA;
assign IN_RESET_SLAVE = IN_RESET;
assign IN_RESET_PWM = CS;
PWM_FPGA #(
.CLOCK_FREQUENCY(CLOCK_FREQUENCY),
.PWM_FREQUENCY(PWM_FREQUENCY),
.MAX_VALUE(MAX_VALUE),
.DEEP_FILL_FACTOR(DEEP_FILL_FACTOR)
) PWM_MODULE (
IN_CLOCK,
IN_RESET_PWM,
IN_ENABLE,
IN_PWM_FILL_FACTOR,
OUT_PWM_SIGNAL
);
SPI_FPGA_SLAVE #(
.CPHA(CPHA),
.CPOL(CPOL),
.PACK_LENGTH(PACK_LENGTH),
.PACK_BIT_SEQUENCE_TRANSMIT(PACK_BIT_SEQUENCE_TRANSMIT),
.PACK_BIT_SEQUENCE_RECEIVE(PACK_BIT_SEQUENCE_RECEIVE),
) SLAVE_MODULE (
IN_TRANSMIT_DATA,
MOSI,
CS,
SCLK,
IN_RESET_SLAVE,
MISO,
OUT_RECEIVE_DATA
);
endmodule
| 7.872544 |
module spi_slave_r (
input rst,
input clk,
//fifo
input fifo_full,
output [7:0] fifo_d,
output fifo_w_en,
//spi slave
input sclk,
input sdin
);
//sck edge check
reg [1:0] sclk_edge = 2'b00;
always @(posedge clk) begin
if (!rst) begin
sclk_edge <= 2'b00;
end else begin
sclk_edge <= {sclk_edge[0], sclk};
end
end
reg w_en_reg = 0;
reg [7:0] d_reg = 8'd0;
assign fifo_w_en = w_en_reg;
assign fifo_d = d_reg;
reg [4:0] bit_index = 5'd0;
reg [4:0] sta_cur = 0;
always @(posedge clk) begin
if (!rst) begin
w_en_reg <= 1'b0;
d_reg <= 8'd0;
bit_index <= 5'd0;
sta_cur <= 0;
end else begin
case (sta_cur)
0: begin
d_reg <= 8'd0;
bit_index <= 5'd0;
sta_cur <= 1;
end
1: begin
if (sclk_edge == 2'b01) begin
d_reg[0] <= sdin;
sta_cur <= 2;
end
end
2: begin
bit_index <= bit_index + 1;
sta_cur <= 3;
end
3: begin
if (bit_index == 8) begin
if (fifo_full != 1) w_en_reg <= 1;
sta_cur <= 4;
end else begin
d_reg <= {d_reg[6:0], 1'b0};
sta_cur <= 1;
end
end
4: begin
w_en_reg <= 0;
sta_cur <= 0;
end
endcase
end
end
endmodule
| 7.320152 |
module spi_slave_regs #(
parameter REG_SIZE = 8
) (
sclk,
rstn,
wr_data,
wr_addr,
wr_data_valid,
rd_data,
rd_addr,
dummy_cycles,
en_qpi,
wrap_length
);
//parameter REG_SIZE = 8;
input wire sclk;
input wire rstn;
input wire [REG_SIZE - 1:0] wr_data;
input wire [1:0] wr_addr;
input wire wr_data_valid;
output reg [REG_SIZE - 1:0] rd_data;
input wire [1:0] rd_addr;
output wire [7:0] dummy_cycles;
output wire en_qpi;
output wire [15:0] wrap_length;
reg [REG_SIZE - 1:0] reg0;
reg [REG_SIZE - 1:0] reg1;
reg [REG_SIZE - 1:0] reg2;
reg [REG_SIZE - 1:0] reg3;
assign en_qpi = reg0[0];
assign dummy_cycles = reg1;
assign wrap_length = {reg3, reg2};
always @(*)
case (rd_addr)
2'b00: rd_data = reg0;
2'b01: rd_data = reg1;
2'b10: rd_data = reg2;
2'b11: rd_data = reg3;
endcase
always @(posedge sclk or negedge rstn)
if (rstn == 0) begin
reg0 <= 'h0;
reg1 <= 'd32;
reg2 <= 'h0;
reg3 <= 'h0;
end else if (wr_data_valid)
case (wr_addr)
2'b00: reg0 <= wr_data;
2'b01: reg1 <= wr_data;
2'b10: reg2 <= wr_data;
2'b11: reg3 <= wr_data;
endcase
endmodule
| 7.107196 |
module spi_slave_syncro #(
parameter AXI_ADDR_WIDTH = 32
) (
sys_clk,
rstn,
cs,
address,
address_valid,
rd_wr,
cs_sync,
address_sync,
address_valid_sync,
rd_wr_sync
);
//parameter AXI_ADDR_WIDTH = 32;
input wire sys_clk;
input wire rstn;
input wire cs;
input wire [AXI_ADDR_WIDTH - 1:0] address;
input wire address_valid;
input wire rd_wr;
output wire cs_sync;
output wire [AXI_ADDR_WIDTH - 1:0] address_sync;
output wire address_valid_sync;
output wire rd_wr_sync;
reg [1:0] cs_reg;
reg [2:0] valid_reg;
reg [1:0] rdwr_reg;
assign cs_sync = cs_reg[1];
assign address_valid_sync = ~valid_reg[2] & valid_reg[1];
assign address_sync = address;
assign rd_wr_sync = rdwr_reg[1];
always @(posedge sys_clk or negedge rstn)
if (rstn == 1'b0) begin
cs_reg <= 2'b11;
valid_reg <= 3'b000;
rdwr_reg <= 2'b00;
end else begin
cs_reg <= {cs_reg[0], cs};
valid_reg <= {valid_reg[1:0], address_valid};
rdwr_reg <= {rdwr_reg[0], rd_wr};
end
endmodule
| 7.177815 |
module spi_slave_tb ();
parameter N = 8;
integer i;
reg [N-1:0] din;
wire [N-1:0] dout;
reg [N-1:0] gotback;
reg [N-1:0] tosend;
wire miso;
reg mosi, sclk, ssbar;
task send;
input [N-1:0] dataout;
output [N-1:0] gotdata;
reg [N-1:0] temp;
begin
#10;
ssbar = 0;
for (i = N - 1; i >= 0; i = i - 1) begin
sclk = 0;
mosi = dataout[i];
#10;
sclk = 1;
temp = {temp[N-2:0], miso};
#10;
end
sclk = 0;
ssbar = 1;
gotdata = temp;
#10;
end
endtask
spi_slave U0 (
.mosi (mosi),
.sclk (sclk),
.ssbar(ssbar),
.miso (miso),
.din (din),
.dout (dout)
);
initial begin
$dumpfile("op.vcd");
$dumpvars;
mosi = 0;
ssbar = 1;
sclk = 0;
din = 0;
gotback = 0;
#100;
din = 1;
tosend = 8'h12;
send(tosend, gotback);
#100;
din = 20;
tosend = 55;
send(tosend, gotback);
#100;
$finish;
end
endmodule
| 7.301482 |
module to test api slaves
//
// This allows SPI data to be sent and received
// from tests
module spi_slave_tester(
input wire clk,
input wire rst,
input wire sout,
output wire sin,
output wire sclk
);
integer period;
reg phase;
reg polarity;
task send;
input reg [7:0] to_dut;
reg [7:0] unused;
begin
transfer(to_dut, unused);
end
endtask
task transfer;
input reg [7:0] to_dut;
output reg [7:0] from_dut;
integer data_pos;
begin
data_pos = 7;
from_dut = 0;
if (phase == 0) begin
repeat (8) begin
// Write data
sin_nosync = to_dut[data_pos];
// wait
#(period/2);
// Read on the first clock edge after idle
sclk_nosync = !polarity;
from_dut[data_pos] = sout;
data_pos = data_pos - 1;
// wait
#(period/2);
// Return to idle
sclk_nosync = polarity;
end
end else begin
repeat (8) begin
// Write data on the first clock edge after idle
sclk_nosync = !polarity;
sin_nosync = to_dut[data_pos];
// wait
#(period/2);
// Read data on the second clock edge after idle
sclk_nosync = polarity;
from_dut[data_pos] = sout;
data_pos = data_pos - 1;
// wait
#(period/2);
end
end
end
endtask
reg sin_sync;
reg sin_nosync;
reg sclk_sync;
reg sclk_nosync;
assign sin = sin_sync;
assign sclk = sclk_sync;
initial begin
period = 100;
phase = 0;
polarity = 0;
sin_sync = 0;
sclk_sync = 0;
sin_nosync = 0;
sclk_nosync = 0;
end
always @(posedge clk) begin
sin_sync <= sin_nosync;
sclk_sync <= sclk_nosync;
end
endmodule
| 7.078078 |
module SPI_SM (
output reg latch_cmd,
output reg rd_select,
output reg wr_select,
input wire clk,
input wire [3:0] cmd,
input wire done,
input wire rst
);
// state bits
parameter IDLE = 3'b000, LATCH = 3'b001, READ = 3'b010, WRITE = 3'b011, WRITE_WAIT = 3'b100;
reg [2:0] state;
reg [2:0] nextstate;
// comb always block
always @* begin
nextstate = state; // default to hold value because implied_loopback is set
case (state)
IDLE: begin
if (done) begin
nextstate = LATCH;
end
end
LATCH: begin
if (cmd == `RD) begin
nextstate = READ;
end else if (cmd == `WR) begin
nextstate = WRITE_WAIT;
end else begin
nextstate = IDLE; // return to idle on invalid cmd
end
end
READ: begin
if (done) begin
nextstate = IDLE;
end
end
WRITE: begin
begin
nextstate = IDLE;
end
end
WRITE_WAIT: begin
if (done) begin
nextstate = WRITE;
end
end
endcase
end
// Assign reg'd outputs to state bits
// sequential always block
always @(posedge clk) begin
if (rst) state <= IDLE;
else state <= nextstate;
end
// datapath sequential always block
always @(posedge clk) begin
if (rst) begin
latch_cmd <= 0;
rd_select <= 0;
wr_select <= 0;
end else begin
latch_cmd <= 0; // default
rd_select <= 0; // default
wr_select <= 0; // default
case (nextstate)
LATCH: begin
latch_cmd <= 1;
end
READ: begin
rd_select <= 1;
end
WRITE: begin
wr_select <= 1;
end
endcase
end
end
// This code allows you to see state names in simulation
`ifndef SYNTHESIS
reg [79:0] statename;
always @* begin
case (state)
IDLE: statename = "IDLE";
LATCH: statename = "LATCH";
READ: statename = "READ";
WRITE: statename = "WRITE";
WRITE_WAIT: statename = "WRITE_WAIT";
default: statename = "XXXXXXXXXX";
endcase
end
`endif
endmodule
| 7.946031 |
module spi_tb (
output reg SCK,
output reg CS,
output reg MOSI,
output reg FLAG,
output reg [7:0] readed,
input MISO
);
localparam PERIOD = 3.2; //312.5 MHz SoC
localparam PERIOD_SPI = 50; //20 MHz SPI SCK
//****** SEQUENCE OF STIMULUS ***********
initial begin
//**INITIAL VALUES***
SCK = 0;
MOSI = 1;
CS = 1;
FLAG = 0;
readed = 0;
//*******************
#(5 * PERIOD); //Wait to be sure that amazilia its on reset state
//************AMAZILIA PROGRAMING ZONE************
//HOW TO USE IT
//write_drac(address,data); //writes "data" over register asosiated with "address"
//read_drac(address,output_register); // reads register asosiated with "address" and put the value in "output_register"
//Example:
write_drac(7'd14, 8'd0); //FFRO PD TO 0
write_drac(7'd25, 8'd0); //HSS PD TO 0
read_drac(7'd5, readed); //READ THE CRSCTLE
//*************************************************
#(PERIOD); // 1 cycle dalay
FLAG = 0; //this flag says amazilia programing step ends
end
//************************************
//****** ATOMATED TASK ***********
task write_drac;
//author : Hanssel
//abstract : this task generates stimulus to perform a write transaction
// over the direct register access controller through spi
input [6:0] addr;
input [7:0] word;
begin
CS = 0;
spi_send({1'b1, addr});
spi_send(word);
#(PERIOD_SPI / 2);
CS = 1;
#(PERIOD_SPI / 2);
end
endtask
task read_drac;
//author : Hanssel
//abstract : this task generates stimulus to perform a read transaction
// over the direct register access controller through spi
input [6:0] addr;
output [7:0] word;
begin
CS = 0;
spi_send({1'b0, addr});
spi_read(word);
#(PERIOD_SPI / 2);
CS = 1;
#(PERIOD_SPI / 2);
end
endtask
task spi_send;
//author : Hanssel
//abstract : this task generates SPI MODE 0 standart
// write transaction of 8 bits using SCK and MOSI lines
input [7:0] word;
integer c;
begin
for (c = 0; c <= 7; c = c + 1) begin
MOSI = word[7-c];
#(PERIOD_SPI / 2);
SCK = 1;
#(PERIOD_SPI / 2);
SCK = 0;
end
end
endtask
task spi_read;
//author : Hanssel
//abstract : this task generates SCK clock and read MISO line
// to get 8 bits of date all in SPI MODE 0 standart
output [7:0] word;
integer c;
begin
for (c = 0; c <= 7; c = c + 1) begin
#(PERIOD_SPI / 2);
word[7-c] = MISO;
SCK = 1;
#(PERIOD_SPI / 2);
SCK = 0;
end
#(PERIOD_SPI / 2);
end
endtask
task burst_drac;
//author : Hanssel
//abstract : this task generates stimulus to perform a burst transaction
// over the direct register access controller through spi
// changing all registers to 0
integer i;
begin
#(PERIOD_SPI / 2);
CS = 0;
spi_send(8'hFF);
for (i = 0; i < 8'h15; i = i + 1) begin
spi_send(8'h0);
end
#(PERIOD_SPI / 2);
CS = 1;
#(PERIOD_SPI / 2);
end
endtask
//************************************
endmodule
| 7.608779 |
module spi_sub (
input wire i_clk,
input wire i_reset_n,
// SPI bus
input wire i_spi_cs_n,
input wire i_spi_sck,
input wire i_spi_si,
output wire o_spi_so,
// shared
output wire [4:0] o_slave_addr,
output wire o_wr_req,
output wire [7:0] o_data_wr,
// slaves connections
output wire o_slave0_sel,
input wire [7:0] o_stave0_rdata,
output wire o_slave1_sel,
input wire [7:0] o_stave1_rdata,
output wire o_slave2_sel,
input wire [7:0] o_stave2_rdata,
output wire o_slave3_sel,
input wire [7:0] o_stave3_rdata
);
wire [7:0] w_data_rd;
wire [7:0] w_addr;
spi_master u_master (
.i_clk (i_clk),
.i_reset_n (i_reset_n),
.i_spi_cs_n (i_spi_cs_n),
.i_spi_sck (i_spi_sck),
.i_spi_si (i_spi_si),
.o_spi_so (o_spi_so),
.o_addr (w_addr),
.o_data_wr (o_data_wr),
.i_data_rd (w_data_rd),
.o_wr_req (o_wr_req)
);
slave_mux u_mux (
.i_addr (w_addr[6:5]),
.o_data_wr (w_data_rd),
.o_sel0 (o_slave0_sel),
.i_data_wr0 (o_stave0_rdata),
.o_sel1 (o_slave1_sel),
.i_data_wr1 (o_stave1_rdata),
.o_sel2 (o_slave2_sel),
.i_data_wr2 (o_stave2_rdata),
.o_sel3 (o_slave3_sel),
.i_data_wr3 (o_stave3_rdata)
);
assign o_slave_addr = w_addr[4:0];
endmodule
| 7.473618 |
module name:spi_switch
//file name: spi_switch.v
//version: 1.0
//author: zxc
//date: 2008.09.08
//function: spi switch control
///////////////////////////////////////////////////
//revision history
`timescale 1ns/1ns
module spi_switch (
rstb_i, //reset
clk_i, //system clock
spi_en_i, //spi enable
master_i, //master slave switch signal
send_data_i, //send data
master_load_end_i, //master load end
slave_load_end_i, //slave load end
master_convey_end_i, //master convey end
slave_convey_end_i, //slave convey end
master_frame_end_i, //master frame end
slave_frame_end_i, //slave frame end
master_rcv_data_i, //master receive data
slave_rcv_data_i, //slave receive data
rstb_general_o, //general reset
rstb_master_o, //master reset
rstb_slave_o, //slave reset
master_send_data_o, //master send data
slave_send_data_o, //slave send data
load_end_o, //load end signal
convey_end_o, //convey end signal
frame_end_o, //frame end
rcv_data_o, //received data
ss_oe_o, //ss pad output enable
sck_oe_o, //sck pad output enable
mosi_oe_o, //mosi pad output enable
miso_oe_o //miso pad output enable
);
input rstb_i;
input clk_i;
input spi_en_i;
input master_i;
input [7:0]send_data_i;
input master_load_end_i;
input slave_load_end_i;
input master_convey_end_i;
input slave_convey_end_i;
input master_frame_end_i;
input slave_frame_end_i;
input [7:0]master_rcv_data_i;
input [7:0]slave_rcv_data_i;
output rstb_general_o;
output rstb_master_o;
output rstb_slave_o;
output [7:0]master_send_data_o;
output [7:0]slave_send_data_o;
output load_end_o;
output convey_end_o;
output frame_end_o;
output [7:0]rcv_data_o;
output ss_oe_o;
output sck_oe_o;
output mosi_oe_o;
output miso_oe_o;
reg ss_oe_o;
reg sck_oe_o;
reg mosi_oe_o;
reg miso_oe_o;
//reset
assign rstb_general_o = rstb_i & spi_en_i;
assign rstb_master_o = rstb_i & spi_en_i & master_i;
assign rstb_slave_o = rstb_i & spi_en_i & (~master_i);
//send_data
assign master_send_data_o = master_i ? send_data_i : 8'h00;
assign slave_send_data_o = master_i ? 8'h00 : send_data_i;
//load_end_o
assign load_end_o = master_i ? master_load_end_i : slave_load_end_i;
//convey_end_o
assign convey_end_o = master_i ? master_convey_end_i : slave_convey_end_i;
//frame_end_o
assign frame_end_o = master_i ? master_frame_end_i : slave_frame_end_i;
//rcv_data_o
assign rcv_data_o = master_i ? master_rcv_data_i : slave_rcv_data_i;
//ss_oe_o
always @(posedge clk_i or negedge rstb_i)
begin
if(!rstb_i)
ss_oe_o <= 1'b0;
else
ss_oe_o <= master_i;
end
//sck_oe_o
always @(posedge clk_i or negedge rstb_i)
begin
if(!rstb_i)
sck_oe_o <= 1'b0;
else
sck_oe_o <= master_i;
end
//mosi_oe_o
always @(posedge clk_i or negedge rstb_i)
begin
if(!rstb_i)
mosi_oe_o <= 1'b0;
else
mosi_oe_o <= master_i;
end
//miso_oe_o
always @(posedge clk_i or negedge rstb_i)
begin
if(!rstb_i)
miso_oe_o <= 1'b0;
else
miso_oe_o <= ~master_i;
end
endmodule
| 8.275824 |
module spi_synchronizer (
input clk,
input sck,
sdi,
cs,
output sck_out,
sdi_out,
cs_out
);
parameter integer SYNC_STAGES = 2;
parameter integer SYNC_MSB = SYNC_STAGES - 1;
reg [SYNC_MSB:0] sck_sync;
reg [SYNC_MSB:0] sdi_sync;
reg [SYNC_MSB:0] cs_sync;
assign sck_out = sck_sync[SYNC_MSB];
assign sdi_out = sdi_sync[SYNC_MSB];
assign cs_out = cs_sync[SYNC_MSB];
// Core synchronizer.
always @(posedge clk) begin
sck_sync = {sck_sync[SYNC_MSB-1 : 0], sck};
sdi_sync = {sdi_sync[SYNC_MSB-1 : 0], sdi};
cs_sync = {cs_sync[SYNC_MSB-1 : 0], cs};
end
endmodule
| 6.67042 |
module SPI_TestBench();
wire [7:0] data_in;
reg [7:0] data_out;
initial data_out = 0;
reg [7:0]testdata;
initial testdata = 8'h1275;
reg clock;
initial clock = 0;
always #(1) clock <= ~clock;
wire rst;
reg SCK,MO,CS;
wire MI;
initial SCK = 1;
initial MO = 0;
initial CS = 1;
SPI_slave rpi_spi_dev(
.clk(clock),
.SCK(SCK),
.MOSI(MO),
.MISO(MI),
.SSEL(CS),
.LED(),
.byte_data_received(data_in),
.byte_received(byte_received),
.byte_sent(data_out)
);
reg [2:0] resetn_counter = 0;
always @(posedge clock) begin
if (!rst)
resetn_counter <= resetn_counter + 1;
end
assign rst = &resetn_counter;
reg [31:0] registers [7:0];
reg [31:0] rpi_out;
wire [39:0] data_in;
wire rw_select = data_in[7];
wire [31:0]rpi_data_in = data_in[39:8];
wire [6:0] rpi_address = data_in[6:0];
wire rpi_byte_received;
always @(posedge clock) begin
if (!rst) begin
registers <= 0;
end
else
if(rpi_byte_received & rw_select) begin
registers[rpi_address] <= rpi_data_in;
end
else if(rpi_byte_received & ~rw_select) begin
rpi_out <= registers[rpi_address];
end
end
end
initial begin
$dumpfile("SPI_TestBench.vcd");
$dumpvars(0, rpi_spi_dev);
$dumpvars(0, rpi_out);
$dumpvars(0, registers);
#20
CS <= 0;
#1
SCK <= 0;
#3
MO <= 1;
SCK <= 0;
#3
SCK <= 1;
#3
MO <= 1;
SCK <= 0;
#3
SCK <= 1;
#3
MO <= 0;
SCK <= 0;
#3
SCK <= 1;
#3
MO <= 1;
SCK <= 0;
#3
SCK <= 1;
#3
MO <= 1;
SCK <= 0;
#3
SCK <= 1;
#3
MO <= 1;
SCK <= 0;
#3
SCK <= 1;
#3
MO <= 0;
SCK <= 0;
#3
SCK <= 1;
#3
MO <= 1;
SCK <= 0;
#3
SCK <= 1;
#3
CS <= 1;
#3
SCK <= 1;
#200
$finish;
end
endmodule
| 7.278138 |
module spi_t (
input clk,
input rst,
input miso,
output mosi,
output sck,
input start,
input [7:0] data_in,
output [7:0] data_out,
output busy,
output new_data
);
localparam CLK_DIV = 2;
localparam STATE_SIZE = 2;
localparam IDLE = 2'd0, WAIT_HALF = 2'd1, TRANSFER = 2'd2;
reg [STATE_SIZE-1:0] state_d, state_q;
reg [7:0] data_d, data_q;
reg [CLK_DIV-1:0] sck_d, sck_q;
reg mosi_d, mosi_q;
reg [2:0] ctr_d, ctr_q;
reg new_data_d, new_data_q;
reg [7:0] data_out_d, data_out_q;
assign mosi = mosi_q;
assign sck = (~sck_q[CLK_DIV-1]) & (state_q == TRANSFER);
assign busy = state_q != IDLE;
assign data_out = data_out_q;
assign new_data = new_data_q;
always @(*) begin
sck_d = sck_q;
data_d = data_q;
mosi_d = mosi_q;
ctr_d = ctr_q;
new_data_d = 1'b0;
data_out_d = data_out_q;
state_d = state_q;
case (state_q)
IDLE: begin
sck_d = 4'b0; // reset clock counter
ctr_d = 3'b0; // reset bit counter
if (start == 1'b1) begin // if start command
data_d = data_in; // copy data to send
state_d = WAIT_HALF; // change state
end
end
WAIT_HALF: begin
sck_d = sck_q + 1'b1; // increment clock counter
if (sck_q == {CLK_DIV - 1{1'b1}}) begin // if clock is half full (about to fall)
sck_d = 1'b0; // reset to 0
state_d = TRANSFER; // change state
end
end
TRANSFER: begin
sck_d = sck_q + 1'b1; // increment clock counter
if (sck_q == 4'b0000) begin // if clock counter is 0
mosi_d = data_q[7]; // output the MSB of data
end else if (sck_q == {CLK_DIV - 1{1'b1}}) begin // else if it's half full (about to fall)
data_d = {data_q[6:0], miso}; // read in data (shift in)
end else if (sck_q == {CLK_DIV{1'b1}}) begin // else if it's full (about to rise)
ctr_d = ctr_q + 1'b1; // increment bit counter
if (ctr_q == 3'b111) begin // if we are on the last bit
state_d = IDLE; // change state
data_out_d = data_q; // output data
new_data_d = 1'b1; // signal data is valid
end
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
ctr_q <= 3'b0;
data_q <= 8'b0;
sck_q <= 4'b0;
mosi_q <= 1'b0;
state_q <= IDLE;
data_out_q <= 8'b0;
new_data_q <= 1'b0;
end else begin
ctr_q <= ctr_d;
data_q <= data_d;
sck_q <= sck_d;
mosi_q <= mosi_d;
state_q <= state_d;
data_out_q <= data_out_d;
new_data_q <= new_data_d;
end
end
endmodule
| 8.335937 |
module combining the SPI stack (SPI Minion, SPI Minion Adapter, and Loopthrough)
// that connects to the individual project group's block module. This was used for the
// efabless tapeout in Spring 2022.
//
// Author : Jack Brzozowski
// Date : May 9th, 2022
`include "SPI_v3/components/SPIstackVRTL.v"
`include "tapeout/BlockPlaceholderVRTL.v"
`include "tut4_verilog/gcd/GcdUnitRTL.v"
// ADD INCLUDES HERE FOR YOUR MODULE
module tapeout_SPI_TapeOutBlockVRTL
#(
parameter nbits = 34, // the size of the val/rdy msg for the SPI Minion (includes the two flow control bits)
parameter num_entries = 5
)(
input logic clk,
input logic reset,
input logic loopthrough_sel,
output logic minion_parity,
output logic adapter_parity,
// SPI Minion Ifc
input logic spi_min_sclk,
input logic spi_min_cs,
input logic spi_min_mosi,
output logic spi_min_miso
);
parameter packet_nbits = nbits - 2; //remove control flow bits
parameter gcd_msg_size = packet_nbits/2;
logic send_val;
logic [packet_nbits-1:0] send_msg;
logic send_rdy;
logic recv_val;
logic [packet_nbits-1:0] recv_msg;
logic [gcd_msg_size-1:0] gcd_msg;
logic recv_rdy;
logic reset_presync;
logic reset_sync;
always_ff @(posedge clk) begin
reset_presync <= reset;
reset_sync <= reset_presync;
end
// We add two to nbits for the two SPI minion flow control bits
SPI_v3_components_SPIstackVRTL #(nbits, num_entries) SPIstack
(
.clk(clk),
.reset(reset_sync),
.loopthrough_sel(loopthrough_sel),
.minion_parity(minion_parity),
.adapter_parity(adapter_parity),
// SPI Minion Ifc
.sclk(spi_min_sclk),
.cs(spi_min_cs),
.mosi(spi_min_mosi),
.miso(spi_min_miso),
// Send/Recv Ifc
.send_val(send_val),
.send_msg(send_msg),
.send_rdy(send_rdy),
.recv_val(recv_val),
.recv_msg(recv_msg),
.recv_rdy(recv_rdy)
);
//=============================================================================
// TAPEOUT TASK: Instantiate your module below and connect it to the SPI stack
//=============================================================================
// tapeout_BlockPlaceholderVRTL #(packet_nbits) Placeholder
// (
// // Send/Recv Ifc
// .send_val(send_val),
// .send_msg(send_msg),
// .send_rdy(send_rdy),
// .recv_val(recv_val),
// .recv_msg(recv_msg),
// .recv_rdy(recv_rdy)
// );
always @(*) begin
recv_msg = { {(gcd_msg_size){gcd_msg[gcd_msg_size-1]}}, gcd_msg };
end
tut4_verilog_gcd_GcdUnitRTL GCD (
.clk (clk),
.reset (reset_sync),
.recv_val (send_val),
.recv_rdy (send_rdy),
.recv_msg (send_msg),
.send_val (recv_val),
.send_rdy (recv_rdy),
.send_msg (gcd_msg)
);
endmodule
| 9.386012 |
module SPI_v3_components_LoopThroughVRTL (
clk,
reset,
sel,
upstream_req_val,
upstream_req_msg,
upstream_req_rdy,
upstream_resp_val,
upstream_resp_msg,
upstream_resp_rdy,
downstream_req_val,
downstream_req_msg,
downstream_req_rdy,
downstream_resp_val,
downstream_resp_msg,
downstream_resp_rdy
);
parameter nbits = 32;
input wire clk;
input wire reset;
input wire sel;
input wire upstream_req_val;
input wire [nbits - 1:0] upstream_req_msg;
output wire upstream_req_rdy;
output wire upstream_resp_val;
output wire [nbits - 1:0] upstream_resp_msg;
input wire upstream_resp_rdy;
output wire downstream_req_val;
output wire [nbits - 1:0] downstream_req_msg;
input wire downstream_req_rdy;
input wire downstream_resp_val;
input wire [nbits - 1:0] downstream_resp_msg;
output wire downstream_resp_rdy;
assign upstream_resp_val = (sel ? upstream_req_val : downstream_resp_val);
assign upstream_resp_msg = (sel ? upstream_req_msg : downstream_resp_msg);
assign downstream_req_val = (sel ? 0 : upstream_req_val);
assign downstream_req_msg = upstream_req_msg;
assign upstream_req_rdy = (sel ? upstream_resp_rdy : downstream_req_rdy);
assign downstream_resp_rdy = (sel ? 0 : upstream_resp_rdy);
endmodule
| 7.522988 |
module ShiftReg (
clk,
in_,
load_data,
load_en,
out,
reset,
shift_en
);
parameter nbits = 8;
input wire clk;
input wire in_;
input wire [nbits - 1:0] load_data;
input wire load_en;
output reg [nbits - 1:0] out;
input wire reset;
input wire shift_en;
always @(posedge clk)
if (reset) out <= {nbits{1'b0}};
else if (load_en) out <= load_data;
else if (~load_en & shift_en) out <= {out[nbits-2:0], in_};
endmodule
| 8.65434 |
module SPI_v3_components_SPIMinionVRTL (
clk,
cs,
miso,
mosi,
reset,
sclk,
pull_en,
pull_msg,
push_en,
push_msg,
parity
);
parameter nbits = 8;
input wire clk;
input wire cs;
output wire miso;
input wire mosi;
input wire reset;
input wire sclk;
output wire pull_en;
input wire [nbits - 1:0] pull_msg;
output wire push_en;
output wire [nbits - 1:0] push_msg;
output wire parity;
wire cs_sync_clk;
wire cs_sync_in_;
wire cs_sync_negedge_;
wire cs_sync_out;
wire cs_sync_posedge_;
wire cs_sync_reset;
Synchronizer #(
.reset_value(1'b1)
) cs_sync (
.clk(cs_sync_clk),
.in_(cs_sync_in_),
.negedge_(cs_sync_negedge_),
.out(cs_sync_out),
.posedge_(cs_sync_posedge_),
.reset(cs_sync_reset)
);
wire mosi_sync_clk;
wire mosi_sync_in_;
wire mosi_sync_negedge_;
wire mosi_sync_out;
wire mosi_sync_posedge_;
wire mosi_sync_reset;
Synchronizer #(
.reset_value(1'b0)
) mosi_sync (
.clk(mosi_sync_clk),
.in_(mosi_sync_in_),
.negedge_(mosi_sync_negedge_),
.out(mosi_sync_out),
.posedge_(mosi_sync_posedge_),
.reset(mosi_sync_reset)
);
wire sclk_sync_clk;
wire sclk_sync_in_;
wire sclk_sync_negedge_;
wire sclk_sync_out;
wire sclk_sync_posedge_;
wire sclk_sync_reset;
Synchronizer #(
.reset_value(1'b0)
) sclk_sync (
.clk(sclk_sync_clk),
.in_(sclk_sync_in_),
.negedge_(sclk_sync_negedge_),
.out(sclk_sync_out),
.posedge_(sclk_sync_posedge_),
.reset(sclk_sync_reset)
);
wire shreg_in_clk;
wire shreg_in_in_;
wire [nbits - 1:0] shreg_in_load_data;
wire shreg_in_load_en;
wire [nbits - 1:0] shreg_in_out;
wire shreg_in_reset;
reg shreg_in_shift_en;
ShiftReg #(
.nbits(nbits)
) shreg_in (
.clk(shreg_in_clk),
.in_(shreg_in_in_),
.load_data(shreg_in_load_data),
.load_en(shreg_in_load_en),
.out(shreg_in_out),
.reset(shreg_in_reset),
.shift_en(shreg_in_shift_en)
);
wire shreg_out_clk;
wire shreg_out_in_;
wire [nbits - 1:0] shreg_out_load_data;
wire shreg_out_load_en;
wire [nbits - 1:0] shreg_out_out;
wire shreg_out_reset;
reg shreg_out_shift_en;
ShiftReg #(
.nbits(nbits)
) shreg_out (
.clk(shreg_out_clk),
.in_(shreg_out_in_),
.load_data(shreg_out_load_data),
.load_en(shreg_out_load_en),
.out(shreg_out_out),
.reset(shreg_out_reset),
.shift_en(shreg_out_shift_en)
);
always @(*) begin
shreg_in_shift_en = ~cs_sync_out & sclk_sync_posedge_;
shreg_out_shift_en = ~cs_sync_out & sclk_sync_negedge_;
end
assign cs_sync_clk = clk;
assign cs_sync_reset = reset;
assign cs_sync_in_ = cs;
assign sclk_sync_clk = clk;
assign sclk_sync_reset = reset;
assign sclk_sync_in_ = sclk;
assign mosi_sync_clk = clk;
assign mosi_sync_reset = reset;
assign mosi_sync_in_ = mosi;
assign shreg_in_clk = clk;
assign shreg_in_reset = reset;
assign shreg_in_in_ = mosi_sync_out;
assign shreg_in_load_en = 1'b0;
assign shreg_in_load_data = {nbits{1'b0}};
assign shreg_out_clk = clk;
assign shreg_out_reset = reset;
assign shreg_out_in_ = 1'b0;
assign shreg_out_load_en = pull_en;
assign shreg_out_load_data = pull_msg;
assign miso = shreg_out_out[nbits-1];
assign pull_en = cs_sync_negedge_;
assign push_en = cs_sync_posedge_;
assign push_msg = shreg_in_out;
assign parity = ^push_msg[nbits-3:0] & push_en;
endmodule
| 7.522988 |
module vc_Reg (
clk,
q,
d
);
parameter p_nbits = 1;
input wire clk;
output reg [p_nbits - 1:0] q;
input wire [p_nbits - 1:0] d;
always @(posedge clk) q <= d;
endmodule
| 7.27876 |
module vc_ResetReg (
clk,
reset,
q,
d
);
parameter p_nbits = 1;
parameter p_reset_value = 0;
input wire clk;
input wire reset;
output reg [p_nbits - 1:0] q;
input wire [p_nbits - 1:0] d;
always @(posedge clk) q <= (reset ? p_reset_value : d);
endmodule
| 6.831298 |
module vc_EnReg (
clk,
reset,
q,
d,
en
);
parameter p_nbits = 1;
input wire clk;
input wire reset;
output reg [p_nbits - 1:0] q;
input wire [p_nbits - 1:0] d;
input wire en;
always @(posedge clk) if (en) q <= d;
endmodule
| 7.427182 |
module vc_EnResetReg (
clk,
reset,
q,
d,
en
);
parameter p_nbits = 1;
parameter p_reset_value = 0;
input wire clk;
input wire reset;
output reg [p_nbits - 1:0] q;
input wire [p_nbits - 1:0] d;
input wire en;
always @(posedge clk) if (reset || en) q <= (reset ? p_reset_value : d);
endmodule
| 7.207198 |
module vc_Mux2 (
in0,
in1,
sel,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
input wire sel;
output reg [p_nbits - 1:0] out;
always @(*)
case (sel)
1'd0: out = in0;
1'd1: out = in1;
default: out = {p_nbits{1'bx}};
endcase
endmodule
| 7.493918 |
module vc_Mux3 (
in0,
in1,
in2,
sel,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
input wire [p_nbits - 1:0] in2;
input wire [1:0] sel;
output reg [p_nbits - 1:0] out;
always @(*)
case (sel)
2'd0: out = in0;
2'd1: out = in1;
2'd2: out = in2;
default: out = {p_nbits{1'bx}};
endcase
endmodule
| 7.892776 |
module vc_Mux4 (
in0,
in1,
in2,
in3,
sel,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
input wire [p_nbits - 1:0] in2;
input wire [p_nbits - 1:0] in3;
input wire [1:0] sel;
output reg [p_nbits - 1:0] out;
always @(*)
case (sel)
2'd0: out = in0;
2'd1: out = in1;
2'd2: out = in2;
2'd3: out = in3;
default: out = {p_nbits{1'bx}};
endcase
endmodule
| 7.741558 |
module vc_Mux5 (
in0,
in1,
in2,
in3,
in4,
sel,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
input wire [p_nbits - 1:0] in2;
input wire [p_nbits - 1:0] in3;
input wire [p_nbits - 1:0] in4;
input wire [2:0] sel;
output reg [p_nbits - 1:0] out;
always @(*)
case (sel)
3'd0: out = in0;
3'd1: out = in1;
3'd2: out = in2;
3'd3: out = in3;
3'd4: out = in4;
default: out = {p_nbits{1'bx}};
endcase
endmodule
| 7.614878 |
module vc_Mux6 (
in0,
in1,
in2,
in3,
in4,
in5,
sel,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
input wire [p_nbits - 1:0] in2;
input wire [p_nbits - 1:0] in3;
input wire [p_nbits - 1:0] in4;
input wire [p_nbits - 1:0] in5;
input wire [2:0] sel;
output reg [p_nbits - 1:0] out;
always @(*)
case (sel)
3'd0: out = in0;
3'd1: out = in1;
3'd2: out = in2;
3'd3: out = in3;
3'd4: out = in4;
3'd5: out = in5;
default: out = {p_nbits{1'bx}};
endcase
endmodule
| 7.692722 |
module vc_Mux7 (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
input wire [p_nbits - 1:0] in2;
input wire [p_nbits - 1:0] in3;
input wire [p_nbits - 1:0] in4;
input wire [p_nbits - 1:0] in5;
input wire [p_nbits - 1:0] in6;
input wire [2:0] sel;
output reg [p_nbits - 1:0] out;
always @(*)
case (sel)
3'd0: out = in0;
3'd1: out = in1;
3'd2: out = in2;
3'd3: out = in3;
3'd4: out = in4;
3'd5: out = in5;
3'd6: out = in6;
default: out = {p_nbits{1'bx}};
endcase
endmodule
| 7.845565 |
module vc_Mux8 (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
input wire [p_nbits - 1:0] in2;
input wire [p_nbits - 1:0] in3;
input wire [p_nbits - 1:0] in4;
input wire [p_nbits - 1:0] in5;
input wire [p_nbits - 1:0] in6;
input wire [p_nbits - 1:0] in7;
input wire [2:0] sel;
output reg [p_nbits - 1:0] out;
always @(*)
case (sel)
3'd0: out = in0;
3'd1: out = in1;
3'd2: out = in2;
3'd3: out = in3;
3'd4: out = in4;
3'd5: out = in5;
3'd6: out = in6;
3'd7: out = in7;
default: out = {p_nbits{1'bx}};
endcase
endmodule
| 7.77376 |
module vc_MuxN (
in,
sel,
out
);
parameter p_nbits = 1;
parameter p_ninputs = 2;
input wire [(p_ninputs * p_nbits) - 1:0] in;
input wire [$clog2(p_ninputs) - 1:0] sel;
output wire [p_nbits - 1:0] out;
assign out = in[sel*p_nbits+:p_nbits];
endmodule
| 7.320871 |
module vc_Regfile_1r1w (
clk,
reset,
read_addr,
read_data,
write_en,
write_addr,
write_data
);
parameter p_data_nbits = 1;
parameter p_num_entries = 2;
parameter c_addr_nbits = $clog2(p_num_entries);
input wire clk;
input wire reset;
input wire [c_addr_nbits - 1:0] read_addr;
output wire [p_data_nbits - 1:0] read_data;
input wire write_en;
input wire [c_addr_nbits - 1:0] write_addr;
input wire [p_data_nbits - 1:0] write_data;
reg [p_data_nbits - 1:0] rfile[p_num_entries - 1:0];
assign read_data = rfile[read_addr];
always @(posedge clk) if (write_en) rfile[write_addr] <= write_data;
endmodule
| 7.208433 |
module vc_ResetRegfile_1r1w (
clk,
reset,
read_addr,
read_data,
write_en,
write_addr,
write_data
);
parameter p_data_nbits = 1;
parameter p_num_entries = 2;
parameter p_reset_value = 0;
parameter c_addr_nbits = $clog2(p_num_entries);
input wire clk;
input wire reset;
input wire [c_addr_nbits - 1:0] read_addr;
output wire [p_data_nbits - 1:0] read_data;
input wire write_en;
input wire [c_addr_nbits - 1:0] write_addr;
input wire [p_data_nbits - 1:0] write_data;
reg [p_data_nbits - 1:0] rfile[p_num_entries - 1:0];
assign read_data = rfile[read_addr];
genvar i;
generate
for (i = 0; i < p_num_entries; i = i + 1) begin : wport
always @(posedge clk)
if (reset) rfile[i] <= p_reset_value;
else if (write_en && (i[c_addr_nbits-1:0] == write_addr)) rfile[i] <= write_data;
end
endgenerate
endmodule
| 6.956174 |
module vc_Regfile_2r1w (
clk,
reset,
read_addr0,
read_data0,
read_addr1,
read_data1,
write_en,
write_addr,
write_data
);
parameter p_data_nbits = 1;
parameter p_num_entries = 2;
parameter c_addr_nbits = $clog2(p_num_entries);
input wire clk;
input wire reset;
input wire [c_addr_nbits - 1:0] read_addr0;
output wire [p_data_nbits - 1:0] read_data0;
input wire [c_addr_nbits - 1:0] read_addr1;
output wire [p_data_nbits - 1:0] read_data1;
input wire write_en;
input wire [c_addr_nbits - 1:0] write_addr;
input wire [p_data_nbits - 1:0] write_data;
reg [p_data_nbits - 1:0] rfile[p_num_entries - 1:0];
assign read_data0 = rfile[read_addr0];
assign read_data1 = rfile[read_addr1];
always @(posedge clk) if (write_en) rfile[write_addr] <= write_data;
endmodule
| 6.740536 |
module vc_Regfile_2r2w (
clk,
reset,
read_addr0,
read_data0,
read_addr1,
read_data1,
write_en0,
write_addr0,
write_data0,
write_en1,
write_addr1,
write_data1
);
parameter p_data_nbits = 1;
parameter p_num_entries = 2;
parameter c_addr_nbits = $clog2(p_num_entries);
input wire clk;
input wire reset;
input wire [c_addr_nbits - 1:0] read_addr0;
output wire [p_data_nbits - 1:0] read_data0;
input wire [c_addr_nbits - 1:0] read_addr1;
output wire [p_data_nbits - 1:0] read_data1;
input wire write_en0;
input wire [c_addr_nbits - 1:0] write_addr0;
input wire [p_data_nbits - 1:0] write_data0;
input wire write_en1;
input wire [c_addr_nbits - 1:0] write_addr1;
input wire [p_data_nbits - 1:0] write_data1;
reg [p_data_nbits - 1:0] rfile[p_num_entries - 1:0];
assign read_data0 = rfile[read_addr0];
assign read_data1 = rfile[read_addr1];
always @(posedge clk) begin
if (write_en0) rfile[write_addr0] <= write_data0;
if (write_en1) rfile[write_addr1] <= write_data1;
end
endmodule
| 6.740536 |
module vc_Regfile_2r1w_zero (
clk,
reset,
rd_addr0,
rd_data0,
rd_addr1,
rd_data1,
wr_en,
wr_addr,
wr_data
);
input wire clk;
input wire reset;
input wire [4:0] rd_addr0;
output wire [31:0] rd_data0;
input wire [4:0] rd_addr1;
output wire [31:0] rd_data1;
input wire wr_en;
input wire [4:0] wr_addr;
input wire [31:0] wr_data;
wire [31:0] rf_read_data0;
wire [31:0] rf_read_data1;
vc_Regfile_2r1w #(
.p_data_nbits (32),
.p_num_entries(32)
) rfile (
.clk(clk),
.reset(reset),
.read_addr0(rd_addr0),
.read_data0(rf_read_data0),
.read_addr1(rd_addr1),
.read_data1(rf_read_data1),
.write_en(wr_en),
.write_addr(wr_addr),
.write_data(wr_data)
);
assign rd_data0 = (rd_addr0 == 5'd0 ? 32'd0 : rf_read_data0);
assign rd_data1 = (rd_addr1 == 5'd0 ? 32'd0 : rf_read_data1);
endmodule
| 6.740536 |
module vc_QueueCtrl1 (
clk,
reset,
recv_val,
recv_rdy,
send_val,
send_rdy,
write_en,
bypass_mux_sel,
num_free_entries
);
parameter p_type = 4'b0000;
input wire clk;
input wire reset;
input wire recv_val;
output wire recv_rdy;
output wire send_val;
input wire send_rdy;
output wire write_en;
output wire bypass_mux_sel;
output wire num_free_entries;
reg full;
wire full_next;
always @(posedge clk) full <= (reset ? 1'b0 : full_next);
assign num_free_entries = (full ? 1'b0 : 1'b1);
localparam c_pipe_en = |(p_type & 4'b0001);
localparam c_bypass_en = |(p_type & 4'b0010);
wire do_enq;
assign do_enq = recv_rdy && recv_val;
wire do_deq;
assign do_deq = send_rdy && send_val;
wire empty;
assign empty = ~full;
wire do_pipe;
assign do_pipe = ((c_pipe_en && full) && do_enq) && do_deq;
wire do_bypass;
assign do_bypass = ((c_bypass_en && empty) && do_enq) && do_deq;
assign write_en = do_enq && ~do_bypass;
assign bypass_mux_sel = empty;
assign recv_rdy = ~full || ((c_pipe_en && full) && send_rdy);
assign send_val = ~empty || ((c_bypass_en && empty) && recv_val);
assign full_next = (do_deq && ~do_pipe ? 1'b0 : (do_enq && ~do_bypass ? 1'b1 : full));
endmodule
| 7.312115 |
module vc_QueueCtrl (
clk,
reset,
recv_val,
recv_rdy,
send_val,
send_rdy,
write_en,
write_addr,
read_addr,
bypass_mux_sel,
num_free_entries
);
parameter p_type = 4'b0000;
parameter p_num_msgs = 2;
parameter c_addr_nbits = $clog2(p_num_msgs);
input wire clk;
input wire reset;
input wire recv_val;
output wire recv_rdy;
output wire send_val;
input wire send_rdy;
output wire write_en;
output wire [c_addr_nbits - 1:0] write_addr;
output wire [c_addr_nbits - 1:0] read_addr;
output wire bypass_mux_sel;
output wire [c_addr_nbits:0] num_free_entries;
wire [c_addr_nbits - 1:0] enq_ptr;
wire [c_addr_nbits - 1:0] enq_ptr_next;
vc_ResetReg #(
.p_nbits(c_addr_nbits)
) enq_ptr_reg (
.clk(clk),
.reset(reset),
.d(enq_ptr_next),
.q(enq_ptr)
);
wire [c_addr_nbits - 1:0] deq_ptr;
wire [c_addr_nbits - 1:0] deq_ptr_next;
vc_ResetReg #(
.p_nbits(c_addr_nbits)
) deq_ptr_reg (
.clk(clk),
.reset(reset),
.d(deq_ptr_next),
.q(deq_ptr)
);
assign write_addr = enq_ptr;
assign read_addr = deq_ptr;
wire full;
wire full_next;
vc_ResetReg #(
.p_nbits(1)
) full_reg (
.clk(clk),
.reset(reset),
.d(full_next),
.q(full)
);
localparam c_pipe_en = |(p_type & 4'b0001);
localparam c_bypass_en = |(p_type & 4'b0010);
wire do_enq;
assign do_enq = recv_rdy && recv_val;
wire do_deq;
assign do_deq = send_rdy && send_val;
wire empty;
assign empty = ~full && (enq_ptr == deq_ptr);
wire do_pipe;
assign do_pipe = ((c_pipe_en && full) && do_enq) && do_deq;
wire do_bypass;
assign do_bypass = ((c_bypass_en && empty) && do_enq) && do_deq;
assign write_en = do_enq && ~do_bypass;
assign bypass_mux_sel = empty;
assign recv_rdy = ~full || ((c_pipe_en && full) && send_rdy);
assign send_val = ~empty || ((c_bypass_en && empty) && recv_val);
wire [c_addr_nbits - 1:0] deq_ptr_plus1;
assign deq_ptr_plus1 = deq_ptr + 1'b1;
wire [c_addr_nbits - 1:0] deq_ptr_inc;
assign deq_ptr_inc = (deq_ptr_plus1 == p_num_msgs ? {c_addr_nbits{1'b0}} : deq_ptr_plus1);
wire [c_addr_nbits - 1:0] enq_ptr_plus1;
assign enq_ptr_plus1 = enq_ptr + 1'b1;
wire [c_addr_nbits - 1:0] enq_ptr_inc;
assign enq_ptr_inc = (enq_ptr_plus1 == p_num_msgs ? {c_addr_nbits{1'b0}} : enq_ptr_plus1);
assign deq_ptr_next = (do_deq && ~do_bypass ? deq_ptr_inc : deq_ptr);
assign enq_ptr_next = (do_enq && ~do_bypass ? enq_ptr_inc : enq_ptr);
assign full_next = ((do_enq && ~do_deq) && (enq_ptr_inc == deq_ptr) ? 1'b1 : ((do_deq && full) && ~do_pipe ? 1'b0 : full));
assign num_free_entries = (full ? {c_addr_nbits + 1 {1'b0}} : (empty ? p_num_msgs[c_addr_nbits:0] : (enq_ptr > deq_ptr ? p_num_msgs[c_addr_nbits:0] - (enq_ptr - deq_ptr) : (deq_ptr > enq_ptr ? deq_ptr - enq_ptr : {c_addr_nbits + 1 {1'bx}}))));
endmodule
| 6.52014 |
module vc_Queue (
clk,
reset,
recv_val,
recv_rdy,
recv_msg,
send_val,
send_rdy,
send_msg,
num_free_entries
);
parameter p_type = 4'b0000;
parameter p_msg_nbits = 1;
parameter p_num_msgs = 2;
parameter c_addr_nbits = $clog2(p_num_msgs);
input wire clk;
input wire reset;
input wire recv_val;
output wire recv_rdy;
input wire [p_msg_nbits - 1:0] recv_msg;
output wire send_val;
input wire send_rdy;
output wire [p_msg_nbits - 1:0] send_msg;
output wire [c_addr_nbits:0] num_free_entries;
generate
if (p_num_msgs == 1) begin : genblk1
wire write_en;
wire bypass_mux_sel;
vc_QueueCtrl1 #(
.p_type(p_type)
) ctrl (
.clk(clk),
.reset(reset),
.recv_val(recv_val),
.recv_rdy(recv_rdy),
.send_val(send_val),
.send_rdy(send_rdy),
.write_en(write_en),
.bypass_mux_sel(bypass_mux_sel),
.num_free_entries(num_free_entries)
);
vc_QueueDpath1 #(
.p_type(p_type),
.p_msg_nbits(p_msg_nbits)
) dpath (
.clk(clk),
.reset(reset),
.write_en(write_en),
.bypass_mux_sel(bypass_mux_sel),
.recv_msg(recv_msg),
.send_msg(send_msg)
);
end else begin : genblk1
wire write_en;
wire bypass_mux_sel;
wire [c_addr_nbits - 1:0] write_addr;
wire [c_addr_nbits - 1:0] read_addr;
vc_QueueCtrl #(
.p_type(p_type),
.p_num_msgs(p_num_msgs)
) ctrl (
.clk(clk),
.reset(reset),
.recv_val(recv_val),
.recv_rdy(recv_rdy),
.send_val(send_val),
.send_rdy(send_rdy),
.write_en(write_en),
.write_addr(write_addr),
.read_addr(read_addr),
.bypass_mux_sel(bypass_mux_sel),
.num_free_entries(num_free_entries)
);
vc_QueueDpath #(
.p_type(p_type),
.p_msg_nbits(p_msg_nbits),
.p_num_msgs(p_num_msgs)
) dpath (
.clk(clk),
.reset(reset),
.write_en(write_en),
.bypass_mux_sel(bypass_mux_sel),
.write_addr(write_addr),
.read_addr(read_addr),
.recv_msg(recv_msg),
.send_msg(send_msg)
);
end
endgenerate
endmodule
| 7.520267 |
module SPI_v3_components_SPIMinionAdapterVRTL (
clk,
reset,
pull_en,
pull_msg_val,
pull_msg_spc,
pull_msg_data,
push_en,
push_msg_val_wrt,
push_msg_val_rd,
push_msg_data,
recv_msg,
recv_rdy,
recv_val,
send_msg,
send_rdy,
send_val,
parity
);
parameter nbits = 8;
parameter num_entries = 1;
input wire clk;
input wire reset;
input wire pull_en;
output reg pull_msg_val;
output reg pull_msg_spc;
output reg [nbits - 3:0] pull_msg_data;
input wire push_en;
input wire push_msg_val_wrt;
input wire push_msg_val_rd;
input wire [nbits - 3:0] push_msg_data;
input wire [nbits - 3:0] recv_msg;
output wire recv_rdy;
input wire recv_val;
output wire [nbits - 3:0] send_msg;
input wire send_rdy;
output wire send_val;
output wire parity;
reg open_entries;
wire [$clog2(num_entries):0] cm_q_num_free;
wire [nbits - 3:0] cm_q_send_msg;
reg cm_q_send_rdy;
wire cm_q_send_val;
vc_Queue #(
.p_type(4'b0000),
.p_msg_nbits(nbits - 2),
.p_num_msgs(num_entries)
) cm_q (
.clk(clk),
.num_free_entries(cm_q_num_free),
.reset(reset),
.recv_msg(recv_msg),
.recv_rdy(recv_rdy),
.recv_val(recv_val),
.send_msg(cm_q_send_msg),
.send_rdy(cm_q_send_rdy),
.send_val(cm_q_send_val)
);
wire [$clog2(num_entries):0] mc_q_num_free;
wire mc_q_recv_rdy;
reg mc_q_recv_val;
vc_Queue #(
.p_type(4'b0000),
.p_msg_nbits(nbits - 2),
.p_num_msgs(num_entries)
) mc_q (
.clk(clk),
.num_free_entries(mc_q_num_free),
.reset(reset),
.recv_msg(push_msg_data),
.recv_rdy(mc_q_recv_rdy),
.recv_val(mc_q_recv_val),
.send_msg(send_msg),
.send_rdy(send_rdy),
.send_val(send_val)
);
assign parity = ^send_msg & send_val;
always @(*) begin : comb_block
open_entries = mc_q_num_free > 1;
mc_q_recv_val = push_msg_val_wrt & push_en;
pull_msg_spc = mc_q_recv_rdy & (~mc_q_recv_val | open_entries);
cm_q_send_rdy = push_msg_val_rd & pull_en;
pull_msg_val = cm_q_send_rdy & cm_q_send_val;
pull_msg_data = cm_q_send_msg & {nbits - 2{pull_msg_val}};
end
endmodule
| 7.522988 |
module SPI_v3_components_SPIMinionAdapterCompositeVRTL (
clk,
cs,
miso,
mosi,
reset,
sclk,
recv_msg,
recv_rdy,
recv_val,
send_msg,
send_rdy,
send_val,
minion_parity,
adapter_parity
);
parameter nbits = 8;
parameter num_entries = 1;
input wire clk;
input wire cs;
output wire miso;
input wire mosi;
input wire reset;
input wire sclk;
input wire [nbits - 3:0] recv_msg;
output wire recv_rdy;
input wire recv_val;
output wire [nbits - 3:0] send_msg;
input wire send_rdy;
output wire send_val;
output wire minion_parity;
output wire adapter_parity;
wire pull_en;
wire pull_msg_val;
wire pull_msg_spc;
wire [nbits - 3:0] pull_msg_data;
wire push_en;
wire push_msg_val_wrt;
wire push_msg_val_rd;
wire [nbits - 3:0] push_msg_data;
wire [nbits - 1:0] pull_msg;
wire [nbits - 1:0] push_msg;
SPI_v3_components_SPIMinionAdapterVRTL #(
.nbits(nbits),
.num_entries(num_entries)
) adapter (
.clk(clk),
.reset(reset),
.pull_en(pull_en),
.pull_msg_val(pull_msg_val),
.pull_msg_spc(pull_msg_spc),
.pull_msg_data(pull_msg_data),
.push_en(push_en),
.push_msg_val_wrt(push_msg_val_wrt),
.push_msg_val_rd(push_msg_val_rd),
.push_msg_data(push_msg_data),
.recv_msg(recv_msg),
.recv_rdy(recv_rdy),
.recv_val(recv_val),
.send_msg(send_msg),
.send_rdy(send_rdy),
.send_val(send_val),
.parity(adapter_parity)
);
SPI_v3_components_SPIMinionVRTL #(
.nbits(nbits)
) minion (
.clk(clk),
.cs(cs),
.miso(miso),
.mosi(mosi),
.reset(reset),
.sclk(sclk),
.pull_en(pull_en),
.pull_msg(pull_msg),
.push_en(push_en),
.push_msg(push_msg),
.parity(minion_parity)
);
assign pull_msg[nbits-1] = pull_msg_val;
assign pull_msg[nbits-2] = pull_msg_spc;
assign pull_msg[nbits-3:0] = pull_msg_data;
assign push_msg_val_wrt = push_msg[nbits-1];
assign push_msg_val_rd = push_msg[nbits-2];
assign push_msg_data = push_msg[nbits-3:0];
endmodule
| 7.522988 |
module SPI_v3_components_SPIstackVRTL (
clk,
reset,
loopthrough_sel,
minion_parity,
adapter_parity,
sclk,
cs,
mosi,
miso,
send_val,
send_msg,
send_rdy,
recv_val,
recv_msg,
recv_rdy
);
parameter nbits = 34;
parameter num_entries = 1;
input wire clk;
input wire reset;
input wire loopthrough_sel;
output wire minion_parity;
output wire adapter_parity;
input wire sclk;
input wire cs;
input wire mosi;
output wire miso;
output wire send_val;
output wire [nbits - 3:0] send_msg;
input wire send_rdy;
input wire recv_val;
input wire [nbits - 3:0] recv_msg;
output wire recv_rdy;
wire minion_out_val;
wire [nbits - 3:0] minion_out_msg;
wire minion_out_rdy;
wire minion_in_val;
wire [nbits - 3:0] minion_in_msg;
wire minion_in_rdy;
SPI_v3_components_SPIMinionAdapterCompositeVRTL #(
.nbits(nbits),
.num_entries(num_entries)
) minion (
.clk(clk),
.reset(reset),
.cs(cs),
.miso(miso),
.mosi(mosi),
.sclk(sclk),
.minion_parity(minion_parity),
.adapter_parity(adapter_parity),
.recv_val(minion_in_val),
.recv_msg(minion_in_msg),
.recv_rdy(minion_in_rdy),
.send_val(minion_out_val),
.send_msg(minion_out_msg),
.send_rdy(minion_out_rdy)
);
SPI_v3_components_LoopThroughVRTL #(
.nbits(nbits - 2)
) loopthrough (
.clk(clk),
.reset(reset),
.sel(loopthrough_sel),
.upstream_req_val(minion_out_val),
.upstream_req_msg(minion_out_msg),
.upstream_req_rdy(minion_out_rdy),
.upstream_resp_val(minion_in_val),
.upstream_resp_msg(minion_in_msg),
.upstream_resp_rdy(minion_in_rdy),
.downstream_req_val(send_val),
.downstream_req_msg(send_msg),
.downstream_req_rdy(send_rdy),
.downstream_resp_val(recv_val),
.downstream_resp_msg(recv_msg),
.downstream_resp_rdy(recv_rdy)
);
endmodule
| 7.522988 |
module tapeout_BlockPlaceholderVRTL (
send_val,
send_msg,
send_rdy,
recv_val,
recv_msg,
recv_rdy
);
parameter nbits = 32;
output wire send_val;
output wire [nbits - 1:0] send_msg;
input wire send_rdy;
input wire recv_val;
input wire [nbits - 1:0] recv_msg;
output wire recv_rdy;
assign send_val = recv_val;
assign send_msg = recv_msg;
assign recv_rdy = send_rdy;
endmodule
| 7.853688 |
module vc_Adder (
in0,
in1,
cin,
out,
cout
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
input wire cin;
output wire [p_nbits - 1:0] out;
output wire cout;
assign {cout, out} = (in0 + in1) + {{p_nbits - 1{1'b0}}, cin};
endmodule
| 8.30696 |
module vc_SimpleAdder (
in0,
in1,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
output wire [p_nbits - 1:0] out;
assign out = in0 + in1;
endmodule
| 8.112602 |
module vc_Subtractor (
in0,
in1,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
output wire [p_nbits - 1:0] out;
assign out = in0 - in1;
endmodule
| 7.776575 |
module vc_Incrementer (
in,
out
);
parameter p_nbits = 1;
parameter p_inc_value = 1;
input wire [p_nbits - 1:0] in;
output wire [p_nbits - 1:0] out;
assign out = in + p_inc_value;
endmodule
| 8.657353 |
module vc_ZeroExtender (
in,
out
);
parameter p_in_nbits = 1;
parameter p_out_nbits = 8;
input wire [p_in_nbits - 1:0] in;
output wire [p_out_nbits - 1:0] out;
assign out = {{p_out_nbits - p_in_nbits{1'b0}}, in};
endmodule
| 8.062945 |
module vc_SignExtender (
in,
out
);
parameter p_in_nbits = 1;
parameter p_out_nbits = 8;
input wire [p_in_nbits - 1:0] in;
output wire [p_out_nbits - 1:0] out;
assign out = {{p_out_nbits - p_in_nbits{in[p_in_nbits-1]}}, in};
endmodule
| 8.543095 |
module vc_ZeroComparator (
in,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in;
output wire out;
assign out = in == {p_nbits{1'b0}};
endmodule
| 8.972309 |
module vc_EqComparator (
in0,
in1,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
output wire out;
assign out = in0 == in1;
endmodule
| 8.385225 |
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