code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module vc_LtComparator (
in0,
in1,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
output wire out;
assign out = in0 < in1;
endmodule
| 8.571994 |
module vc_GtComparator (
in0,
in1,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
output wire out;
assign out = in0 > in1;
endmodule
| 8.065152 |
module vc_LeftLogicalShifter (
in,
shamt,
out
);
parameter p_nbits = 1;
parameter p_shamt_nbits = 1;
input wire [p_nbits - 1:0] in;
input wire [p_shamt_nbits - 1:0] shamt;
output wire [p_nbits - 1:0] out;
assign out = in << shamt;
endmodule
| 8.380756 |
module vc_RightLogicalShifter (
in,
shamt,
out
);
parameter p_nbits = 1;
parameter p_shamt_nbits = 1;
input wire [p_nbits - 1:0] in;
input wire [p_shamt_nbits - 1:0] shamt;
output wire [p_nbits - 1:0] out;
assign out = in >> shamt;
endmodule
| 8.285177 |
module tapeout_SPI_TapeOutBlockVRTL (
clk,
reset,
loopthrough_sel,
minion_parity,
adapter_parity,
spi_min_sclk,
spi_min_cs,
spi_min_mosi,
spi_min_miso
);
parameter nbits = 34;
parameter num_entries = 5;
input wire clk;
input wire reset;
input wire loopthrough_sel;
output wire minion_parity;
output wire adapter_parity;
input wire spi_min_sclk;
input wire spi_min_cs;
input wire spi_min_mosi;
output wire spi_min_miso;
parameter packet_nbits = nbits - 2;
parameter gcd_msg_size = packet_nbits / 2;
wire send_val;
wire [packet_nbits - 1:0] send_msg;
wire send_rdy;
wire recv_val;
reg [packet_nbits - 1:0] recv_msg;
wire [gcd_msg_size - 1:0] gcd_msg;
wire recv_rdy;
reg reset_presync;
reg reset_sync;
always @(posedge clk) begin
reset_presync <= reset;
reset_sync <= reset_presync;
end
SPI_v3_components_SPIstackVRTL #(
.nbits(nbits),
.num_entries(num_entries)
) SPIstack (
.clk(clk),
.reset(reset_sync),
.loopthrough_sel(loopthrough_sel),
.minion_parity(minion_parity),
.adapter_parity(adapter_parity),
.sclk(spi_min_sclk),
.cs(spi_min_cs),
.mosi(spi_min_mosi),
.miso(spi_min_miso),
.send_val(send_val),
.send_msg(send_msg),
.send_rdy(send_rdy),
.recv_val(recv_val),
.recv_msg(recv_msg),
.recv_rdy(recv_rdy)
);
always @(*) recv_msg = {{gcd_msg_size{gcd_msg[gcd_msg_size-1]}}, gcd_msg};
tut4_verilog_gcd_GcdUnitRTL GCD (
.clk(clk),
.reset(reset_sync),
.recv_val(send_val),
.recv_rdy(send_rdy),
.recv_msg(send_msg),
.send_val(recv_val),
.send_rdy(recv_rdy),
.send_msg(gcd_msg)
);
endmodule
| 6.575478 |
module tapeout_SPI_TapeOutBlockVRTL_sv2v (
output adapter_parity,
input clk,
input loopthrough_sel,
output minion_parity,
input reset,
input spi_min_cs,
output spi_min_miso,
input spi_min_mosi,
input spi_min_sclk
);
tapeout_SPI_TapeOutBlockVRTL #(
.nbits(34),
.num_entries(5)
) v (
.adapter_parity(adapter_parity),
.clk(clk),
.loopthrough_sel(loopthrough_sel),
.minion_parity(minion_parity),
.reset(reset),
.spi_min_cs(spi_min_cs),
.spi_min_miso(spi_min_miso),
.spi_min_mosi(spi_min_mosi),
.spi_min_sclk(spi_min_sclk)
);
endmodule
| 6.575478 |
module spi_target_bfm #(
parameter DAT_WIDTH = 8
) (
input reset,
input sck,
input sdi,
inout sdo,
input csn
);
reg sdo_r = 0;
assign sdo = (~csn)?sdo_r:1'bz;
reg[7:0] wordsize = 8;
reg[63:0] data = 0;
reg[7:0] bitcount = 0;
reg[DAT_WIDTH-1:0] dat_in_r = {DAT_WIDTH{1'b0}};
reg[DAT_WIDTH-1:0] dat_out_v = {DAT_WIDTH{1'b0}};
reg dat_out_valid_v = 0;
reg[DAT_WIDTH-1:0] dat_out_r = {DAT_WIDTH{1'b0}};
// Transmit state machine
always @(negedge sck or posedge reset) begin
if (reset || csn) begin
dat_out_r <= {DAT_WIDTH{1'b0}};
end else begin
if (dat_out_valid_v) begin
sdo_r <= dat_out_v[DAT_WIDTH-1];
dat_out_r <= {dat_out_v[DAT_WIDTH-2:0], 1'b0};
dat_out_v = 0;
dat_out_valid_v = 0;
end else begin
sdo_r <= dat_out_r[DAT_WIDTH-1];
dat_out_r <= {dat_out_r[DAT_WIDTH-2:0], 1'b0};
end
end
end
// Receive state machine
reg recv_state = 0;
reg[7:0] recv_count = 0;
always @(posedge sck or posedge reset or posedge csn) begin
if (reset) begin
recv_state <= 0;
recv_count <= {8{1'b0}};
end else if (csn) begin
_clocked_csn_high();
recv_state <= 0;
end else begin
dat_in_r <= {dat_in_r[DAT_WIDTH-2:0], sdi};
case (recv_state)
0: begin
recv_count <= 1;
recv_state <= 1;
// Notify the Python side so it can
// specify the data to send
_recv_start();
end
1: begin
if (recv_count == DAT_WIDTH-1) begin
recv_state <= 0;
// Send the resulting data back. Note that
// The final bit hasn't been shifted in, so we
// handle that here
_recv({dat_in_r[DAT_WIDTH-2:0], sdi});
end else begin
recv_count <= recv_count + 1;
end
end
endcase
end
end
task init;
begin
$display("spi_target_bfm: %m");
_set_parameters(DAT_WIDTH);
end
endtask
task _send(input reg[63:0] data);
begin
dat_out_v = data[DAT_WIDTH-1:0];
dat_out_valid_v = 1;
end
endtask
// Auto-generated code to implement the BFM API
`ifdef PYBFMS_GEN
${pybfms_api_impl}
`endif
endmodule
| 7.035625 |
module spi_tb ();
// instanciate design under test
SPI dut (
.clk(clk),
.en(enable),
.rw(rw),
.data(data),
.address(address),
.busy(busy),
.spi_clk(spi_clk),
.spi_cs(spi_cs),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso)
);
reg clk;
reg enable;
reg [7:0] set_data = 8'b10101010;
wire [7:0] data = (rw) ? 8'bzzzzzzzz : set_data;
wire busy;
wire spi_clk;
wire spi_cs;
wire spi_mosi;
reg spi_miso = 0;
reg rw = 1;
reg [5:0] address = 6'b111000;
// generate the clock
initial begin
$dumpfile("test_spi_tb.vcd");
$dumpvars(0, spi_tb);
clk = 1'b0;
forever #1 clk = ~clk;
end
// Generate the reset
initial begin
enable = 1'b0;
#10 enable = 1'b1;
//forever #30 enable = ~enable;
end
always @(negedge spi_clk) spi_miso <= ~spi_miso;
initial begin
// Use the monitor task to display the FPGA IO
$monitor(
"time=%3d, clk=%b, enable=%b, busy=%b, data=%8b, cs = %b, spi_clk = %b, spi_mosi = %b, spi_miso = %b \n",
$time, clk, enable, busy, data, spi_cs, spi_clk, spi_mosi, spi_miso);
#1000 $finish;
end
endmodule
| 6.596809 |
module: spi_topf
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module spi_tbf;
// Inputs
reg clk;
reg rst;
reg [1:0] dtf;
reg [1:0] slave;
// Bidirs
wire miso;
wire mosi;
wire sclk;
wire ssb1;
wire ssb2;
// Instantiate the Unit Under Test (UUT)
spi_topf uut (
.clk(clk),
.rst(rst),
.miso(miso),
.mosi(mosi),
.dtf(dtf),
.sclk(sclk),
.ssb1(ssb1),
.ssb2(ssb2),
.slave(slave)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
//miso = 0;
dtf = 0;
//flag = 0;
slave = 0;
// Wait 100 ns for global reset to finish
#10;
rst = 0;
dtf = 2'b10;
//miso = 0;
//flag = 1;
slave = 2'b01;
#6;
slave = 2'b10;
#10;
dtf = 2'b11;
//flag = 0;
#14;
dtf = 0;
// Add stimulus here
end
always #1 clk = !clk;
endmodule
| 6.638107 |
module spi (
input clk,
input rst,
input miso,
input en,
input [7:0] tx_data,
output [7:0] rx_data,
output sclk,
output reg busy,
output ss,
output mosi
);
localparam STATE_RST = 2'd0;
localparam STATE_IDLE = 2'd1;
localparam STATE_RUNNING = 2'd2;
wire [7:0] clk_div;
parameter cpha = 0;
parameter cpol = 0;
reg [7:0] rx_data_reg, tx_data_reg;
reg [1:0] next_state, state;
reg [7:0] cnt;
reg [3:0] cnt_2;
reg ss_reg, mosi_reg;
reg clk_out;
reg ok;
reg data_transmited;
always @(posedge sclk)
if (ok) cnt_2 <= 0;
else if (cnt_2 == 8) cnt_2 <= 4'bz;
else cnt_2 <= cnt_2 + 1;
always @(posedge sclk)
if (~rst) begin
tx_data_reg <= 0;
rx_data_reg <= 0;
end else if (~busy) tx_data_reg <= tx_data;
else if (~ss_reg) begin
mosi_reg <= tx_data_reg[cnt_2];
rx_data_reg[cnt_2] <= miso;
end else mosi_reg <= 1'bz;
always @(posedge clk)
if (~rst) begin
cnt <= 0;
clk_out <= cpol;
end else if (cnt == clk_div) begin
cnt <= 0;
clk_out <= ~clk_out;
end else cnt = cnt + 1;
always @(posedge clk)
if (~rst) state <= STATE_RST;
else state <= next_state;
always @(*)
case (state)
STATE_RST: begin
busy = 1;
ss_reg = 1;
data_transmited = 0;
next_state = STATE_IDLE;
end
STATE_IDLE: begin
ss_reg = 1;
busy = 0;
data_transmited = 0;
if (~en) begin
busy = 1;
ss_reg = 0;
next_state = STATE_RUNNING;
end else next_state = STATE_IDLE;
end
STATE_RUNNING: begin
if (~data_transmited) begin
ok = 1;
end
busy = 1;
ss_reg = 0;
if (cnt_2 == 0) begin
ok = 0;
data_transmited = 1;
end
if (cnt_2 >= 4'd8) begin
busy = 0;
ss_reg = 1;
next_state = STATE_IDLE;
data_transmited = 0;
end else next_state = STATE_RUNNING;
end
default: begin
busy = 1;
ss_reg = 1;
data_transmited = 0;
ok = 0;
next_state = STATE_IDLE;
end
endcase
assign rx_data = rx_data_reg;
assign mosi = mosi_reg;
assign sclk = (~ss_reg) ? clk_out : 1'bz;
assign ss = ss_reg;
assign clk_div = 8'd16;
endmodule
| 6.715906 |
module: spi
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module write_read_spi;
// Inputs
reg clk;
reg rst_n;
reg spi_in;
// Outputs
wire spi_in_flag;
wire ss_n;
wire spi_out;
wire sck;
//????????ns???????????
parameter CYCLE = 20;
//???????????3?????????
parameter RST_TIME = 3 ;
// Instantiate the Unit Under Test (UUT)
register_option_spi uut (
.sys_clk_50M (clk) ,
.sys_reset_n (rst_n) ,
.data_miso_in (spi_in) ,
.ss_n (ss_n) ,
.data_mosi_out (spi_out) ,
.sck (sck) ,
.spi_in_flag (spi_in_flag)
);
//ɱʱ50M
initial begin
clk = 0;
forever
#(CYCLE/2)
clk=~clk;
end
//λź
initial begin
rst_n = 1;
#10;
rst_n = 0;
#(CYCLE*RST_TIME);
rst_n = 1;
end
//źdin0ֵʽ
initial begin
#1;
repeat(300) begin
wait(spi_in_flag==1'b1)
spi_in = 1 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 1 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 1 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 0 ;
#(25*CYCLE) ;
spi_in = 1 ;
#(25*CYCLE) ;
spi_in = 0 ; //1000 0100 0010 0001
end
end
endmodule
| 6.909089 |
module spi_test_tb;
reg clock;
reg RSTB;
reg CSB;
reg power1, power2;
reg power3, power4;
wire gpio;
wire [37:0] mprj_io;
wire [7:0] mprj_io_0;
wand WPn, HOLDn;
assign WPn = 1'b1;
assign HOLDn = 1'b1;
//assign mprj_io_0 = mprj_io[7:0];
// assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
// assign mprj_io[3] = 1'b1;
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
// would be the fast clock.
always #12.5 clock <= (clock === 1'b0);
initial begin
clock = 0;
end
initial begin
$dumpfile("spi_test.vcd");
$dumpvars(0, spi_test_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (30) begin
repeat (1500) @(posedge clock);
// $display("+1000 cycles");
end
$display("%c[1;31m", 27);
`ifdef GL
$display("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
`else
$display("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
`endif
$display("%c[0m", 27);
$finish;
end
initial begin
// Observe Output pins [7:0]
wait(mprj_io[19:0] == 20'hABCDE); // This value is what is read from input pins , its read and output to the gpio
#1 $display("GPIO state = %b ", mprj_io[19:0]);
`ifdef GL
$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
`else
$display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
`endif
$finish;
end
initial begin
RSTB <= 1'b0;
CSB <= 1'b1; // Force CSB high
#2000;
RSTB <= 1'b1; // Release reset
#170000;
CSB = 1'b0; // CSB can be released
end
initial begin // Power-up sequence
power1 <= 1'b0;
power2 <= 1'b0;
power3 <= 1'b0;
power4 <= 1'b0;
#100;
power1 <= 1'b1;
#100;
power2 <= 1'b1;
#100;
power3 <= 1'b1;
#100;
power4 <= 1'b1;
end
always @(mprj_io) begin
#1 $display("GPO state = %h ", mprj_io[19:0]);
end
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire VDD3V3 = power1;
wire VDD1V8 = power2;
wire USER_VDD3V3 = power3;
wire USER_VDD1V8 = power4;
wire VSS = 1'b0;
caravel uut (
.vddio (VDD3V3),
.vssio (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
.vdda1 (USER_VDD3V3),
.vdda2 (USER_VDD3V3),
.vssa1 (VSS),
.vssa2 (VSS),
.vccd1 (USER_VDD1V8),
.vccd2 (USER_VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
.clock (clock),
.gpio (gpio),
.mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
.resetb (RSTB)
);
spiflash #(
.FILENAME("spi_test.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(), // not used
.io3() // not used
);
wire spi_ssel;
wire spi_clk;
wire spi_mosi;
wire spi_miso;
assign spi_ssel = mprj_io[20];
assign spi_clk = mprj_io[22];
assign mprj_io[23] = spi_miso;
assign spi_mosi = mprj_io[24];
W25Q32JVxxIM user_spi_flash (
.CSn(spi_ssel),
.CLK(spi_clk),
.DIO(spi_mosi),
.DO(spi_miso),
.WPn(WPn),
.HOLDn(HOLDn),
.RESETn(RSTB)
);
endmodule
| 6.765356 |
module spi_test_top (
`ifdef SIM
input sim_clk,
`endif
input pin1,
input pin2,
output pin3,
input pin4,
//input pin5,
//input pin6,
//input pin7,
//input pin8,
//output pin9,
//inout pin10_sda,
//inout pin11_scl,
//output pin16,
//output pin17,
//output pin18,
//inout pin19_sclk,
//inout pin20,
//inout pin21,
input pin22
);
wire clk, rst;
assign rst = pin22;
wire sclk, mosi, miso, ss;
assign sclk = pin1;
assign mosi = pin2;
assign miso = pin3;
assign ss = pin4;
wire spi_dv, spi_halt, spi_we;
wire data_register_we;
wire [63:0] d, q;
wire [7:0] o_data;
wire [7:0] i_data;
`ifndef SIM
OSCH #(
.NOM_FREQ("53.2")
) internal_oscillator_inst (
.STDBY(1'b0),
.OSC (clk)
);
`else
assign clk = sim_clk;
`endif
spi_slave #(
.TXWIDTH(8),
.RXWIDTH(8)
) spi (
.clk(clk),
.rst(rst),
.sclk(sclk),
.mosi(mosi),
.miso(miso),
.ss(ss),
.tx_buffer(o_data),
.wr(spi_we),
.tx_halt(spi_halt),
.rx_buffer(i_data),
.rx_dv(spi_dv)
);
register #(
.WIDTH(64)
) data_register (
.clk(clk),
.rst(rst),
.we (data_register_we),
.d (d),
.q (q)
);
spi_fsm controller (
.clk(clk),
.rst(rst),
.spi_we(spi_we),
.spi_dv(spi_dv),
.spi_halt(spi_halt),
.i_data(i_data),
.o_data(o_data),
.buf_dv(data_register_we),
.i_buffer(q),
.o_buffer(d)
);
endmodule
| 7.417432 |
module spi_test_top_tb #(
parameter SCLK_PERIOD = 9
) ();
reg clk, rst, sclk, mosi;
wire miso;
//reset
initial begin
clk = 0;
rst = 1;
#1;
rst = 1;
clk = 1;
#1;
clk = 0;
rst = 1;
#1;
clk = 1;
rst = 0;
#1;
clk = 0;
#1;
clk = 1;
#1;
clk = 0;
forever #1 clk = ~clk;
end
// read transaction
/*
integer idx;
initial begin
sclk = 0;
mosi = 0;
#7 //offset sclk from clk
// write 0x02 (RDCMD) to SPI port
for (idx = 0; idx < 5; idx = idx + 1) begin
sclk = 1; #SCLK_PERIOD;
mosi = 0;
sclk = 0; #SCLK_PERIOD;
end
sclk = 1; #SCLK_PERIOD;
mosi = 1;
sclk = 0; #SCLK_PERIOD;
sclk = 1; #SCLK_PERIOD;
mosi = 0;
sclk = 0; #SCLK_PERIOD;
sclk = 1; #SCLK_PERIOD;
for (idx = 0; idx < 64; idx = idx + 1) begin
sclk = 0; #SCLK_PERIOD;
sclk = 1; #SCLK_PERIOD;
end
$finish;
end
*/
//write transaction
integer idx;
initial begin
sclk = 0;
mosi = 0;
#7 //offset sclk from clk
// write 0x01 (WRCMD) to SPI port
for (
idx = 0; idx < 6; idx = idx + 1
) begin
sclk = 1;
#SCLK_PERIOD;
mosi = 0;
sclk = 0;
#SCLK_PERIOD;
end
sclk = 1;
#SCLK_PERIOD;
mosi = 1;
sclk = 0;
#SCLK_PERIOD;
// write 0xFF_FF_FF_FF_FF_FF_FF_FF
for (idx = 0; idx < 64; idx = idx + 1) begin
sclk = 1;
#SCLK_PERIOD;
mosi = 1;
sclk = 0;
#SCLK_PERIOD;
end
sclk = 1;
#SCLK_PERIOD;
sclk = 0;
#SCLK_PERIOD;
$finish;
end
spi_test_top dut (
.sim_clk(clk),
.pin1(sclk),
.pin2(mosi),
.pin3(miso),
.pin4(1'b0),
.pin22(rst)
);
initial begin
$dumpfile("spi_test_top.vcd");
$dumpvars;
$dumplimit(5000000);
end
endmodule
| 6.90679 |
module spi_three_wire (
reset,
CLK,
GO,
bitcount,
SCLK,
bitcountEN,
rstbitcount,
LDEN,
SHEN,
SCEN,
ORDY,
SPC
);
input reset;
input CLK;
input GO;
input [3:0] bitcount;
tri0 reset;
tri0 GO;
tri0 [3:0] bitcount;
output SCLK;
output bitcountEN;
output rstbitcount;
output LDEN;
output SHEN;
output SCEN;
output ORDY;
output SPC;
reg SCLK;
reg bitcountEN;
reg rstbitcount;
reg LDEN;
reg SHEN;
reg SCEN;
reg ORDY;
reg [3:0] fstate;
reg [3:0] reg_fstate;
parameter X_IDLE = 0, X_START = 1, X_SHIFT = 2, X_STOP = 3;
always @(posedge CLK or posedge reset) begin
if (reset) begin
fstate <= X_IDLE;
end else begin
fstate <= reg_fstate;
end
end
assign SPC = SCLK ? 1 : ~CLK;
always @(fstate or GO or bitcount) begin
SCLK <= 1'b0;
bitcountEN <= 1'b0;
rstbitcount <= 1'b0;
LDEN <= 1'b0;
SHEN <= 1'b0;
SCEN <= 1'b0;
ORDY <= 1'b0;
case (fstate)
X_IDLE: begin
if (GO) reg_fstate <= X_START;
else if (~(GO)) reg_fstate <= X_IDLE;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= X_IDLE;
SCLK <= 1'b1;
bitcountEN <= 1'b0;
rstbitcount <= 1'b0;
LDEN <= 1'b0;
SHEN <= 1'b0;
SCEN <= 1'b1;
ORDY <= 1'b0;
end
X_START: begin
reg_fstate <= X_SHIFT;
SCLK <= 1'b1;
bitcountEN <= 1'b0;
rstbitcount <= 1'b0;
LDEN <= 1'b1;
SHEN <= 1'b0;
SCEN <= 1'b0;
ORDY <= 1'b0;
end
X_SHIFT: begin
if ((bitcount[3:0] == 4'b1111)) reg_fstate <= X_STOP;
else if ((bitcount[3:0] < 4'b1111)) reg_fstate <= X_SHIFT;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= X_SHIFT;
SCLK <= 1'b0;
// SCLK <= 1'b1;
// SCLK <= !CLK;
bitcountEN <= 1'b1;
if ((bitcount[3:0] < 4'b1111)) rstbitcount <= 1'b0;
else if ((bitcount[3:0] == 4'b1111)) rstbitcount <= 1'b1;
// Inserting 'else' block to prevent latch inference
else
rstbitcount <= 1'b0;
LDEN <= 1'b0;
SHEN <= 1'b1;
SCEN <= 1'b0;
ORDY <= 1'b0;
end
X_STOP: begin
reg_fstate <= X_IDLE;
SCLK <= 1'b1;
bitcountEN <= 1'b0;
rstbitcount <= 1'b0;
LDEN <= 1'b0;
SHEN <= 1'b0;
SCEN <= 1'b1;
ORDY <= 1'b1;
end
default: begin
SCLK <= 1'bx;
bitcountEN <= 1'bx;
rstbitcount <= 1'bx;
LDEN <= 1'bx;
SHEN <= 1'bx;
SCEN <= 1'bx;
ORDY <= 1'bx;
$display("Reach undefined state");
end
endcase
end
endmodule
| 7.202294 |
module spi_three_wire (
reset,
CLK,
GO,
bitcount[3:0],
SCLK,
bitcountEN,
rstbitcount,
LDEN,
SHEN,
SCEN,
ORDY
);
input reset;
input CLK;
input GO;
input [3:0] bitcount;
tri0 reset;
tri0 GO;
tri0 [3:0] bitcount;
output SCLK;
output bitcountEN;
output rstbitcount;
output LDEN;
output SHEN;
output SCEN;
output ORDY;
reg SCLK;
reg bitcountEN;
reg rstbitcount;
reg LDEN;
reg SHEN;
reg SCEN;
reg ORDY;
reg [3:0] fstate;
reg [3:0] reg_fstate;
parameter X_IDLE = 0, X_START = 1, X_SHIFT = 2, X_STOP = 3;
always @(posedge CLK or posedge reset) begin
if (reset) begin
fstate <= X_IDLE;
end else begin
fstate <= reg_fstate;
end
end
always @(fstate or GO or bitcount) begin
SCLK <= 1'b0;
bitcountEN <= 1'b0;
rstbitcount <= 1'b0;
LDEN <= 1'b0;
SHEN <= 1'b0;
SCEN <= 1'b0;
ORDY <= 1'b0;
case (fstate)
X_IDLE: begin
if (GO) reg_fstate <= X_START;
else if (~(GO)) reg_fstate <= X_IDLE;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= X_IDLE;
SCLK <= 1'b1;
bitcountEN <= 1'b0;
rstbitcount <= 1'b0;
LDEN <= 1'b0;
SHEN <= 1'b0;
SCEN <= 1'b1;
ORDY <= 1'b0;
end
X_START: begin
reg_fstate <= X_SHIFT;
SCLK <= 1'b1;
bitcountEN <= 1'b0;
rstbitcount <= 1'b0;
LDEN <= 1'b1;
SHEN <= 1'b0;
SCEN <= 1'b0;
ORDY <= 1'b0;
end
X_SHIFT: begin
if ((bitcount[3:0] == 4'b1111)) reg_fstate <= X_STOP;
else if ((bitcount[3:0] < 4'b1111)) reg_fstate <= X_SHIFT;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= X_SHIFT;
SCLK <= 1'b0;
bitcountEN <= 1'b1;
if ((bitcount[3:0] < 4'b1111)) rstbitcount <= 1'b0;
else if ((bitcount[3:0] == 4'b1111)) rstbitcount <= 1'b1;
// Inserting 'else' block to prevent latch inference
else
rstbitcount <= 1'b0;
LDEN <= 1'b0;
SHEN <= 1'b1;
SCEN <= 1'b0;
ORDY <= 1'b0;
end
X_STOP: begin
reg_fstate <= X_IDLE;
SCLK <= 1'b0;
bitcountEN <= 1'b0;
rstbitcount <= 1'b0;
LDEN <= 1'b0;
SHEN <= 1'b0;
SCEN <= 1'b1;
ORDY <= 1'b1;
end
default: begin
SCLK <= 1'bx;
bitcountEN <= 1'bx;
rstbitcount <= 1'bx;
LDEN <= 1'bx;
SHEN <= 1'bx;
SCEN <= 1'bx;
ORDY <= 1'bx;
$display("Reach undefined state");
end
endcase
end
endmodule
| 7.202294 |
module spi_three_wire_test;
reg reset;
reg CLK;
reg GO;
reg [3:0] bitcount;
wire SCLK;
wire bitcountEN;
wire rstbitcount;
wire LDEN;
wire SHEN;
wire SCEN;
wire ORDY;
wire SPC;
spi_three_wire spi0 (
reset,
CLK,
GO,
bitcount,
SCLK,
bitcountEN,
rstbitcount,
LDEN,
SHEN,
SCEN,
ORDY,
SPC
);
initial begin
CLK = 0;
while (1) #50 CLK = ~CLK;
end
initial begin
reset = 1;
while (1) #100 reset = 0;
end
initial begin
GO = 0;
#100 GO = 1;
#100 GO = 0;
end
initial begin
bitcount = 0;
#350 bitcount = 1;
#100 bitcount = 2;
#100 bitcount = 3;
#100 bitcount = 4;
#100 bitcount = 5;
#100 bitcount = 6;
#100 bitcount = 7;
#100 bitcount = 8;
#100 bitcount = 9;
#100 bitcount = 10;
#100 bitcount = 11;
#100 bitcount = 12;
#100 bitcount = 13;
#100 bitcount = 14;
#100 bitcount = 15;
end
initial begin
$display($time,
"CLK=%d reset=%d bitcount=%d LDEN=%d SHEN=%d SCLK=%d SCEN=%d ,ORDY=%d ,SPC=%d ", CLK,
reset, bitcount, LDEN, SHEN, SCLK, SCEN, ORDY, SPC);
end
endmodule
| 7.202294 |
module for output. BLOCK RAM address is
// updated upon receiving the DONE signal from I2S_master
//
//////////////////////////////////////////////////////////////////////////////////
module SPI_to_I2S_bridge(
input clk, rst,
input [15:0] spkr_data,
output data_out, m_clk, LR_clk, s_clk, DONE
);
reg [8:0] adr;
wire [15:0] memdata;
i2s_output i2s (clk, spkr_data, spkr_data, DONE, data_out, LR_clk, s_clk, m_clk);
endmodule
| 7.712233 |
module spi_transceiver (
input wire sys_rst,
input wire sys_clk,
input wire spi_miso,
output wire spi_mosi,
output reg spi_sck,
input wire [3:0] divisor,
input wire spi_enable,
output wire [7:0] rx_data,
input wire [7:0] tx_data,
input wire tx_wr,
output reg spi_done,
input wire cpol,
input wire cpha
);
localparam IDLE = 2'b00;
localparam CP2 = 2'b01;
localparam CP1 = 2'b10;
reg [1:0] state;
reg ena;
reg [11:0] count;
// ena signal generation, sck clock divider
always @(posedge sys_clk, posedge sys_rst) begin
if (sys_rst) count <= 12'd1;
else if (spi_enable && (state != IDLE) && (count != 12'b0)) count <= count - 12'h1;
else
case (divisor) // reload counter
4'h0: count <= 12'd1; // div = 2;
4'h1: count <= 12'd3; // div = 4;
4'h2: count <= 12'd7; // div = 8;
4'h3: count <= 12'd7; // div = 16;
4'h4: count <= 12'd15; // div = 32;
4'h5: count <= 12'd63; // div = 64;
4'h6: count <= 12'd127; // div = 128;
4'h7: count <= 12'd255; // div = 256;
4'h8: count <= 12'd511; // div = 512;
4'h9: count <= 12'd1023; // div = 1024;
4'hA: count <= 12'd2047; // div = 2048;
4'hB: count <= 12'd4095; // div = 4096;
default: count <= 12'd1; // div = 2;
endcase
;
end
wire sclk_ena = ~|count; // sck enable signal
reg [2:0] bcnt;
reg [7:0] data_reg;
// transfer state machine
always @(posedge sys_clk, posedge sys_rst) begin
if (sys_rst) begin
state <= IDLE;
bcnt <= 3'd0;
data_reg <= 8'd0;
spi_sck <= 1'b0;
end else if (~spi_enable) begin
state <= IDLE;
bcnt <= 3'd0;
data_reg <= 8'd0;
spi_sck <= 1'b0;
end else begin
spi_done <= 1'b0;
case (state)
IDLE: begin
bcnt <= 3'd7;
if (~tx_wr) begin
data_reg <= 8'd0;
spi_sck <= cpol; // set clock polarity
end else begin // start transfer
state <= CP2;
data_reg <= tx_data; // load tx data
if (cpha) spi_sck <= ~spi_sck; // set clock phase, cpha = 1, add an extra edge change
end
end
CP2: begin // clock phase 2, next data
if (sclk_ena) begin
spi_sck <= ~spi_sck;
state <= CP1;
end
end
CP1: begin
if (sclk_ena) begin
data_reg <= {data_reg[6:0], spi_miso}; // sample MISO
bcnt <= bcnt - 3'd1;
if (~|bcnt) begin // bcnt = 3'b000;
state <= IDLE;
spi_sck <= cpol;
spi_done <= 1'b1;
end else begin
state <= CP2;
spi_sck <= ~spi_sck;
end
end
end
default: state <= IDLE; // invaild state
endcase
;
end
end
assign spi_mosi = data_reg[7];
assign rx_data = data_reg;
endmodule
| 7.275178 |
module SPI_Transmitter #(
parameter SPI_DATALENGTH = 6'd32
) (
input clk,
input rst,
output reg sendComplete,
output MOSI,
output reg SCLK,
output reg CS,
input MISO,
input [31:0] sendData,
output reg [31:0] recvData
);
reg [31:0] sendData_reg;
reg [ 5:0] counter;
reg [ 1:0] state;
localparam DEFSTATE = 2'b00;
localparam CLKUP = 2'b01;
localparam CLKDOWN = 2'b10;
localparam DATACHANGE = 2'b11;
assign MOSI = sendData_reg[31];
reg [31:0] recvData_tmp;
always @(posedge clk or negedge rst) begin
if (rst == 1'b0) begin
sendComplete <= 1'b0;
recvData <= 32'h0000_0000;
recvData_tmp <= 32'h0000_0000;
SCLK <= 1'b0;
CS <= 1'b1;
counter <= 6'b000000;
sendData_reg <= sendData;
state <= DEFSTATE;
end else begin
case (state)
DEFSTATE: begin
sendComplete <= 1'b0;
SCLK <= 1'b0;
CS <= 1'b0;
state <= CLKUP;
recvData <= recvData;
recvData_tmp <= recvData_tmp;
end
CLKUP: begin
sendComplete <= 1'b0;
SCLK <= 1'b1;
CS <= 1'b0;
state <= CLKDOWN;
recvData <= recvData;
recvData_tmp <= recvData_tmp;
end
CLKDOWN: begin
sendComplete <= 1'b0;
SCLK <= 1'b0;
CS <= 1'b0;
state <= DATACHANGE;
recvData <= recvData;
recvData_tmp <= {recvData_tmp[30:0],MISO};
end
DATACHANGE: begin
SCLK <= SCLK;
recvData_tmp <= recvData_tmp;
if (counter == SPI_DATALENGTH - 6'b000001) begin
sendComplete <= 1'b1;
CS <= 1'b1;
state <= DATACHANGE;
counter <= counter;
recvData <= recvData_tmp;
end else begin
sendComplete <= 1'b0;
sendData_reg <= {sendData_reg[30:0], 1'b0};
state <= CLKUP;
counter <= counter + 6'b000001;
recvData <= recvData;
end
end
default: SCLK <= 1'b0;
endcase
end
end
endmodule
| 7.538449 |
module SPI_trig_v2 (
input wire clk,
input wire trig,
input wire i_TX_ready,
//input reg[32:0] i_TX_Data,
output reg o_TX_DV
);
reg [0:0] trig_flag;
reg [0:0] ready_flag;
reg [1:0] DV_flag;
always @(posedge trig) begin
o_TX_DV <= 1'b1;
DV_flag <= 2'h1;
end
always @(posedge i_TX_ready) begin
//o_TX_DV <= 1'b1;
DV_flag <= 2'h1;
end
always @(posedge clk) begin
if (DV_flag == 2'h1) begin
//o_TX_DV <= 1'b0;
DV_flag <= 2'h2;
end
if (DV_flag == 2'h2) begin
//o_TX_DV <= 1'b0;
DV_flag <= 2'h0;
end
end
endmodule
| 6.838976 |
module SPI_TX (
input clk,
input CW_CLK_MSI,
input RSTn,
input [23:0] data,
input SPI_tx_en,
output MSI_SDATA, //! port 30, connected to pin N9
output wire MSI_SCLK, //! port 29, connected to pin M9
output reg MSI_CS //! port 31, connected to pin P9
);
//FIFO 24bit-24depth
wire FIFOrd_en;
wire FIFOwr_en;
wire [24:0] FIFOdata;
wire FIFOempty;
wire FIFOfull;
wire [24:0] data_add_onebit;
assign data_add_onebit = {data[23], data};
FIFO_SPI FIFO_SPI (
.clock(clk),
.sclr (RSTn),
.rdreq(FIFOrd_en),
.wrreq(FIFOwr_en),
.full (FIFOfull),
.empty(FIFOempty),
.data (data_add_onebit),
.q (FIFOdata)
);
//FIFO write control
assign FIFOwr_en = (~FIFOfull) & SPI_tx_en;
//SPI TX
reg count_en;
//according to MSI001 datasheet, 1 SPI Word will transmit 24bit,
//interword delay need 300ns. now we use 50M clk which the interword delay need 15000 clk.
//so the counter will be 15024, we need 14bit to store the counter
reg [13:0] counter;
wire trans_finish;
assign trans_finish = (counter == 14'd15024); //14'd15024
wire trans_start;
assign trans_start = (~FIFOempty) & (~count_en);
always @(posedge clk or negedge RSTn) begin
if (~RSTn) count_en <= 1'b0;
else if (trans_start) count_en <= 1'b1;
else if (trans_finish) begin
count_en <= 1'b0;
end
end
always @(posedge clk or negedge RSTn) begin
if (~RSTn) counter <= 14'h0;
else if (counter == 14'd15024) counter <= 14'h0; //14'd15025
else if (count_en) counter <= counter + 1'b1;
end
reg data_temp;
reg MSI_clk_en;
wire [24:0] read_fifo;
assign read_fifo = FIFOdata;
always @(posedge clk or negedge RSTn) begin
if (~RSTn) begin
MSI_CS <= 1'b1;
MSI_clk_en <= 1'b0;
data_temp <= 25'h0;
end else if (count_en) begin
case (counter)
14'd0: begin
MSI_CS <= 1'b0;
data_temp <= read_fifo[24];
MSI_clk_en <= 1'b0;
end
14'd1: begin
data_temp <= read_fifo[23];
MSI_clk_en <= 1'b1;
end
14'd2: data_temp <= read_fifo[22];
14'd3: data_temp <= read_fifo[21];
14'd4: data_temp <= read_fifo[20];
14'd5: data_temp <= read_fifo[19];
14'd6: data_temp <= read_fifo[18];
14'd7: data_temp <= read_fifo[17];
14'd8: data_temp <= read_fifo[16];
14'd9: data_temp <= read_fifo[15];
14'd10: data_temp <= read_fifo[14];
14'd11: data_temp <= read_fifo[13];
14'd12: data_temp <= read_fifo[12];
14'd13: data_temp <= read_fifo[11];
14'd14: data_temp <= read_fifo[10];
14'd15: data_temp <= read_fifo[9];
14'd16: data_temp <= read_fifo[8];
14'd17: data_temp <= read_fifo[7];
14'd18: data_temp <= read_fifo[6];
14'd19: data_temp <= read_fifo[5];
14'd20: data_temp <= read_fifo[4];
14'd21: data_temp <= read_fifo[3];
14'd22: data_temp <= read_fifo[2];
14'd23: data_temp <= read_fifo[1];
14'd24: data_temp <= read_fifo[0];
14'd25: MSI_clk_en <= 1'b0;
default: begin
MSI_CS <= 1'b1;
end
endcase
end
end
assign MSI_SDATA = data_temp;
assign MSI_SCLK = MSI_clk_en ? ~clk : 1'b0;
//FIFO read control
assign FIFOrd_en = (~FIFOempty) & trans_finish;
endmodule
| 6.689109 |
module spi_video (
input wire clk,
output wire oled_csn,
output wire oled_clk,
output wire oled_mosi,
output wire oled_dc,
output wire oled_resn,
output reg [7:0] x,
output reg [5:0] y,
input wire [7:0] color
);
wire [7:0] init_block[0:43];
// NOP
assign init_block[00] = 8'hBC;
// Set display off
assign init_block[01] = 8'hAE;
// Set data format
assign init_block[02] = 8'hA0;
assign init_block[03] = 8'b00100010;
// Set display start line
assign init_block[04] = 8'hA1;
assign init_block[05] = 8'h00;
// Set display offset
assign init_block[06] = 8'hA2;
assign init_block[07] = 8'h00;
// Set display mode normal
assign init_block[08] = 8'hA4;
// Set multiplex ratio
assign init_block[09] = 8'hA8;
assign init_block[10] = 8'b00111111;
// Set master configuration
assign init_block[11] = 8'hAD;
assign init_block[12] = 8'b10001110;
// Set power save mode
assign init_block[13] = 8'hB0;
assign init_block[14] = 8'h00;
// Phase 1/2 period adjustment
assign init_block[15] = 8'hB1;
assign init_block[16] = 8'h74;
// Set display clock divider
assign init_block[17] = 8'hF0;
assign init_block[18] = 8'hF0;
// Set precharge A
assign init_block[19] = 8'h8A;
assign init_block[20] = 8'h64;
// Set precharge B
assign init_block[21] = 8'h8B;
assign init_block[22] = 8'h78;
// Set precharge C
assign init_block[23] = 8'h8C;
assign init_block[24] = 8'h64;
// Set precharge voltage
assign init_block[25] = 8'hBB;
assign init_block[26] = 8'h31;
// Set contrast A
assign init_block[27] = 8'h81;
assign init_block[28] = 8'hFF;
// Set contrast B
assign init_block[29] = 8'h82;
assign init_block[30] = 8'hFF;
// Set contrast C
assign init_block[31] = 8'h83;
assign init_block[32] = 8'hFF;
// Set Vcomh voltage
assign init_block[33] = 8'hBE;
assign init_block[34] = 8'h3E;
// Master current control
assign init_block[35] = 8'h87;
assign init_block[36] = 8'h06;
// Set column address
assign init_block[37] = 8'h15;
assign init_block[38] = 8'h00;
assign init_block[39] = 8'h5F;
// Set row address
assign init_block[40] = 8'h75;
assign init_block[41] = 8'h00;
assign init_block[42] = 8'h3F;
// Set display on
assign init_block[43] = 8'hAF;
localparam INIT_SIZE = 44;
reg [1:0] reset_cnt;
reg [22:0] counter;
reg [9:0] init_cnt;
reg [7:0] data;
reg dc;
always @(posedge clk) begin
counter <= counter + 1;
if (reset_cnt != 2'b10) begin
reset_cnt <= reset_cnt + 1;
init_cnt <= 10'd0;
data <= 8'd0;
dc <= 0;
x <= 95;
y <= 0;
end else if (init_cnt[9:4] != INIT_SIZE) begin
init_cnt <= init_cnt + 1;
if (init_cnt[3:0] == 4'b0000) begin
if (dc == 0) data <= init_block[init_cnt[9:4]];
else begin
data <= color;
if (x == 0) begin
x <= 95;
y <= y + 1;
end else x <= x - 1;
end
end else if (init_cnt[0] == 1'b0) begin
data[7:0] <= {data[6:0], 1'b0};
end
end
if (init_cnt[9:4] == INIT_SIZE) begin
dc <= 1'b1;
end
if (init_cnt[9:4] == INIT_SIZE) begin
init_cnt[9:4] <= INIT_SIZE - 1;
end
end
assign oled_resn = ~reset_cnt[0];
assign oled_csn = reset_cnt[0];
assign oled_dc = dc;
assign oled_clk = ~init_cnt[0];
assign oled_mosi = data[7];
endmodule
| 6.749762 |
module spi_wrap_decode( input aclk,
input aresetn,
input [63:0] s_axis_tdata,
output s_axis_tready,
input s_axis_tvalid,
input s_axis_tlast,
input [7:0] s_axis_tuser,
output [63:0] m_axis_tdata,
input m_axis_tready,
output m_axis_tvalid,
output [7:0] m_axis_tuser,
output m_axis_tlast,
output rst_o,
output [15:0] dat_o,
input [15:0] dat_i,
input dat_valid_i,
output [1:0] adr_o,
output en_o,
output wr_o );
parameter [7:0] TUSER_OUT_MASK = {8{1'b0}};
parameter [7:0] TUSER_OUT = {8{1'b0}};
localparam [15:0] STATUS_HEADER = 16'h57A7;
localparam [3:0] STATUS_SOF = 4'hF;
localparam [3:0] STATUS_EOF = 4'hF;
localparam FSM_BITS = 2;
localparam [FSM_BITS-1:0] RESET = 0;
localparam [FSM_BITS-1:0] IDLE = 1; // nothing, or only a write
localparam [FSM_BITS-1:0] OUT_WAIT_VALID = 2; // read seen and issued, waiting for dat_valid_i (always 1 clock latency)
localparam [FSM_BITS-1:0] OUT_WAIT_READY = 3; // dat valid was seen, waiting for out ready
reg [FSM_BITS-1:0] state = RESET;
reg [7:0] out_tuser = {8{1'b0}};
reg [15:0] out_data = {16{1'b0}};
reg [21:0] out_addr = {22{1'b0}};
// in_addr is tx_word1[3:0] and tx_word2[15:4].
// tx_word1[3:0] = 16 +: 4
// tx_word2[15:4] = 36 +: 12
wire [21:0] in_addr = {s_axis_tdata[16 +: 10],s_axis_tdata[36 +: 12]};
wire [1:0] type = s_axis_tdata[26 +: 2];
localparam [1:0] TYPE_NOP = 2'b00;
localparam [1:0] TYPE_WRITE = 2'b01;
localparam [1:0] TYPE_READ = 2'b10;
localparam [1:0] TYPE_UPDATE = 2'b11;
// This is the wrap decode, the matching and address decoding's done upstream
always @(posedge aclk) begin
if (!aresetn) state <= #1 RESET;
else case (state)
RESET: state <= #1 IDLE;
IDLE: if (s_axis_tvalid && (type == TYPE_READ)) state <= #1 OUT_WAIT_VALID;
OUT_WAIT_VALID: if (dat_valid_i) state <= #1 OUT_WAIT_READY;
OUT_WAIT_READY: if (m_axis_tready) state <= #1 IDLE;
endcase
if (dat_valid_i) out_data <= #1 dat_i;
if (state == IDLE && s_axis_tvalid) out_addr <= #1 in_addr;
if (state == IDLE && s_axis_tvalid) out_tuser <= #1 (s_axis_tuser & ~TUSER_OUT_MASK) | (TUSER_OUT_MASK & TUSER_OUT);
end
assign m_axis_tdata[0 +: 16] = STATUS_HEADER;
assign m_axis_tdata[16 +: 16] = { STATUS_SOF, TYPE_READ, out_addr[12 +: 10] };
assign m_axis_tdata[32 +: 16] = { out_addr[0 +: 12], out_data[12 +: 4] };
assign m_axis_tdata[48 +: 16] = { out_data[0 +: 12], STATUS_EOF };
assign m_axis_tvalid = (state == OUT_WAIT_READY);
assign m_axis_tuser = out_tuser;
assign m_axis_tlast = 1'b1;
assign s_axis_tready = (state == IDLE);
assign en_o = (state == IDLE && s_axis_tvalid);
assign wr_o = (type == TYPE_WRITE || type == TYPE_UPDATE);
assign dat_o = {s_axis_tdata[32 +: 4],s_axis_tdata[52 +: 12]};
assign adr_o = in_addr[1:0];
assign rst_o = (state == RESET);
endmodule
| 7.598736 |
module spi_write (
CLK,
SPC,
SDAT,
regdata,
GO, //GO transfor
ORDY,
reset,
SCEN
);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
input CLK;
input GO;
input reset;
input [15:0] regdata;
//input READ;
inout SDAT;
output SPC;
output SCEN;
output ORDY;
//=======================================================
// REG/WIRE declarations
//=======================================================
wire LDEN;
wire SHEN;
wire rstbitcount;
wire bitcountEN;
reg [3:0] bitcount;
wire SCLK;
//=======================================================
// Structural coding
//=======================================================
spi_three_wire spi1 (
.reset(reset),
.CLK(CLK),
.GO(GO),
.bitcount(bitcount),
.bitcountEN(bitcountEN),
.rstbitcount(rstbitcount),
.LDEN(LDEN),
.SHEN(SHEN),
.SCLK(SCLK),
.SCEN(SCEN),
.ORDY(ORDY),
.SPC(SPC)
);
always @(posedge CLK or posedge reset) begin
if (reset) bitcount <= 0;
else begin
if (rstbitcount) bitcount <= 0;
else if (bitcountEN) bitcount <= bitcount + 1;
end
end
reg [15:0] Q;
always @(posedge CLK or posedge reset) begin
if (reset) Q <= 0;
else begin
if (LDEN) Q <= regdata;
else if (SHEN) begin
Q[15:1] <= Q[14:0]; //shift left
Q[0] <= 0;
end
end
end
assign SDAT = (SCEN | SCLK) ? 1'bz : Q[15];
endmodule
| 7.229781 |
module spi_writebyte (
input clk, //时钟信号 1m的时钟
input rst_n, //复位信号 按键复位
input ena_write, //spi写使能信号
input [7:0] data, //spi写的数据
output reg sclk, //oled的时钟信号（d0）
output reg mosi, //oled的数据信号（d1）
output write_done //spi写完成信号
);
parameter S0 = 0, S1 = 1, S2 = 2, Done = 3;
reg [1:0] state, next_state;
reg [3:0] cnt; //写数据的位计数器
//状态机下一个状态确认
always @(*) begin
if (!rst_n) begin
next_state <= 2'd0;
end else begin
case (state)
S0: //等待写使能信号
next_state = ena_write ? S1 : S0;
S1: next_state = S2;
S2: //从s1到s2的位置cnt才加1所以需要cnt到8再到下一个状态
next_state = (cnt == 4'd8) ? Done : S1;
Done: //这个状态主要用来产生done信号输出
next_state = S0;
endcase
end
end
//赋值和状态转换分开
//解决reg输出Latch的问题
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
sclk = 1'b1;
mosi = 1'b0;
end else begin
case (state)
S0: begin //等待写使能信号
sclk = 1'b1;
mosi = 1'b0;
end
S1: begin
sclk = 1'b0;
mosi = data[3'd7-cnt] ? 1'b1 : 1'b0;
end
S2: begin //从s1到s2的位置cnt才加1所以需要cnt到8再到下一个状态
sclk = 1'b1;
end
endcase
end
end
//状态流转
always @(posedge clk, negedge rst_n) begin
if (~rst_n) state <= S0;
else state <= next_state;
end
//计数器计数
always @(posedge clk, negedge rst_n) begin
if (~rst_n) begin
cnt <= 4'd0;
end else begin
if (state == S1) cnt <= cnt + 1'b1;
else if (state == S0) cnt <= 4'd0;
else cnt <= cnt;
end
end
assign write_done = (state == Done); //done信号输出
endmodule
| 7.575758 |
module spi_writebyte_tb ();
reg clk;
reg ena;
reg rst;
reg [7:0] data;
wire sclk;
wire mosi;
wire done;
spi_writebyte spi_writebyte_inst (
.clk(clk),
.ena_write(ena),
.rst_n(rst),
.data(data),
.sclk(sclk),
.mosi(mosi),
.write_done(done)
);
initial begin
#0 clk = 0; //clk初始为0
data = 8'b11010011;
ena = 0;
rst = 0;
#20 ena = 1;
rst = 1;
end
always #5 clk = ~clk; //每5个时钟单位 clk取反一次
endmodule
| 7.575758 |
module spi_xillybus_interface (
input bus_clk, //
input spi_clk, //
input reset, //
input [15:0] FIFO_DATA_STREAM,
input FIFO_DATA_STREAM_WEN,
input user_r_neural_data_32_open,
input user_r_neural_data_32_rden,
output user_r_neural_data_32_eof,
output user_r_neural_data_32_empty,
output [31:0] user_r_neural_data_32_data,
output reg fifo_overflow
);
wire [31:0] data_reverse;
wire fifo_full;
wire fifo_reset;
wire fifo_wen;
assign fifo_reset = reset | ~user_r_neural_data_32_open; //reset the fifo when the pipe closes even if the interface is opened
assign fifo_wen = FIFO_DATA_STREAM_WEN & ~fifo_overflow; //If the fifo overflows, stop writing to it
fifo_w16_4096_r32_2048 data_fifo (
.rst (fifo_reset),
.wr_clk(spi_clk),
.rd_clk(bus_clk),
.din (FIFO_DATA_STREAM),
.wr_en (fifo_wen),
.rd_en (user_r_neural_data_32_rden),
.dout (data_reverse),
.full (fifo_full),
.empty (user_r_neural_data_32_empty)
);
assign user_r_neural_data_32_eof = fifo_overflow & user_r_neural_data_32_empty; //Generate EOF after overflow (this helps signal overflow to the host)
assign user_r_neural_data_32_data = {
data_reverse[15:0], data_reverse[31:16]
}; //To keep a "16-bit endianess"-like format, to avoid rewriting the existing Rhythm API, which used 16bit words for transmission
//fifo_overflow goes to 1 when there the fifo is full and only resets on fifo reset (file close or global reset)
always @(posedge spi_clk or posedge fifo_reset) begin
if (fifo_reset) fifo_overflow <= 1'b0;
else begin
if (fifo_full & fifo_wen) fifo_overflow <= 1'b1;
end
end
endmodule
| 7.055226 |
module spk_clf_labels_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 9;
parameter MEM_SIZE = 500;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./spk_clf_labels_V_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 6.896574 |
module spk_clf_labels_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd500;
parameter AddressWidth = 32'd9;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
spk_clf_labels_V_ram spk_clf_labels_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0)
);
endmodule
| 6.896574 |
module spk_clf_vq_comp_V_0_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 9;
parameter MEM_SIZE = 500;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./spk_clf_vq_comp_V_0_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 6.571734 |
module spk_clf_vq_comp_V_0 (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd500;
parameter AddressWidth = 32'd9;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
spk_clf_vq_comp_V_0_ram spk_clf_vq_comp_V_0_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0)
);
endmodule
| 6.571734 |
module spk_counter #(
parameter NUM = 8
) (
input [NUM-1 : 0] fan_in,
output reg [ 7 : 0] counter // TODO: why reg?
);
integer i;
always @(fan_in) begin
counter = 0; //initialize count variable.
for (i = 0; i < NUM; i = i + 1) //for all the bits.
counter = counter + fan_in[i]; //Add the bit to the count.
end
endmodule
| 6.813319 |
module spk_dect_buf_2d_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 9;
parameter MEM_SIZE = 320;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./spk_dect_buf_2d_V_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 6.655023 |
module spk_dect_buf_2d_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd320;
parameter AddressWidth = 32'd9;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
spk_dect_buf_2d_V_ram spk_dect_buf_2d_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0)
);
endmodule
| 6.655023 |
module spk_dect_cnt_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 3;
parameter AWIDTH = 8;
parameter MEM_SIZE = 160;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./spk_dect_cnt_V_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 7.134716 |
module spk_dect_cnt_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd3;
parameter AddressRange = 32'd160;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
spk_dect_cnt_V_ram spk_dect_cnt_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0)
);
endmodule
| 7.134716 |
module spk_dect_Mn_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 8;
parameter MEM_SIZE = 160;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./spk_dect_Mn_V_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 6.805281 |
module spk_dect_Mn_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd160;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
spk_dect_Mn_V_ram spk_dect_Mn_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0)
);
endmodule
| 6.805281 |
module spk_dect_mux_4to1_sel2_8_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din1,
input [7 : 0] din2,
input [7 : 0] din3,
input [7 : 0] din4,
input [1 : 0] din5,
output [7 : 0] dout
);
// puts internal signals
wire [1 : 0] sel;
// level 1 signals
wire [7 : 0] mux_1_0;
wire [7 : 0] mux_1_1;
// level 2 signals
wire [7 : 0] mux_2_0;
assign sel = din5;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din1 : din2;
assign mux_1_1 = (sel[0] == 0) ? din3 : din4;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
// output logic
assign dout = mux_2_0;
endmodule
| 6.863406 |
module spk_dect_start_cnt_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 1;
parameter AWIDTH = 8;
parameter MEM_SIZE = 160;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./spk_dect_start_cnt_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 6.770323 |
module spk_dect_start_cnt (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd1;
parameter AddressRange = 32'd160;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
spk_dect_start_cnt_ram spk_dect_start_cnt_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0)
);
endmodule
| 6.770323 |
module spk_dect_state_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 2;
parameter AWIDTH = 8;
parameter MEM_SIZE = 160;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./spk_dect_state_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 7.061612 |
module spk_dect_state (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd2;
parameter AddressRange = 32'd160;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
spk_dect_state_ram spk_dect_state_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0)
);
endmodule
| 7.061612 |
module spk_packet_rx_mac_muladd_6ns_8ns_5ns_13_3_DSP48_0 (
input clk,
input rst,
input ce,
input [6 - 1:0] in0,
input [8 - 1:0] in1,
input [5 - 1:0] in2,
output [13 - 1:0] dout
);
wire signed [25 - 1:0] a;
wire signed [18 - 1:0] b;
wire signed [48 - 1:0] c;
wire signed [43 - 1:0] m;
wire signed [48 - 1:0] p;
reg signed [43 - 1:0] m_reg;
reg signed [25 - 1:0] a_reg;
reg signed [18 - 1:0] b_reg;
assign a = $unsigned(in0);
assign b = $unsigned(in1);
assign c = $unsigned(in2);
assign m = a_reg * b_reg;
assign p = m_reg + c;
always @(posedge clk) begin
if (rst) begin
m_reg <= 0;
a_reg <= 0;
b_reg <= 0;
end else if (ce) begin
m_reg <= m;
a_reg <= a;
b_reg <= b;
end
end
assign dout = p;
endmodule
| 7.194255 |
module spk_packet_rx_mac_muladd_6ns_8ns_5ns_13_3 (
clk,
reset,
ce,
din0,
din1,
din2,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter din2_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input [din0_WIDTH - 1:0] din0;
input [din1_WIDTH - 1:0] din1;
input [din2_WIDTH - 1:0] din2;
output [dout_WIDTH - 1:0] dout;
spk_packet_rx_mac_muladd_6ns_8ns_5ns_13_3_DSP48_0 spk_packet_rx_mac_muladd_6ns_8ns_5ns_13_3_DSP48_0_U(
.clk (clk),
.rst (reset),
.ce (ce),
.in0 (din0),
.in1 (din1),
.in2 (din2),
.dout(dout)
);
endmodule
| 7.194255 |
module spk_packet_rx_mul_6ns_8ns_13_3_MulnS_0 (
clk,
ce,
a,
b,
p
);
input clk;
input ce;
input [6 - 1 : 0] a; // synthesis attribute keep a "true"
input [8 - 1 : 0] b; // synthesis attribute keep b "true"
output [13 - 1 : 0] p;
reg [ 6 - 1 : 0] a_reg0;
reg [ 8 - 1 : 0] b_reg0;
wire [13 - 1 : 0] tmp_product;
reg [13 - 1 : 0] buff0;
assign p = buff0;
assign tmp_product = a_reg0 * b_reg0;
always @(posedge clk) begin
if (ce) begin
a_reg0 <= a;
b_reg0 <= b;
buff0 <= tmp_product;
end
end
endmodule
| 7.194255 |
module spk_packet_rx_mul_6ns_8ns_13_3 (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input [din0_WIDTH - 1:0] din0;
input [din1_WIDTH - 1:0] din1;
output [dout_WIDTH - 1:0] dout;
spk_packet_rx_mul_6ns_8ns_13_3_MulnS_0 spk_packet_rx_mul_6ns_8ns_13_3_MulnS_0_U (
.clk(clk),
.ce (ce),
.a (din0),
.b (din1),
.p (dout)
);
endmodule
| 7.194255 |
module spk_packet_rx_spk_A_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 128;
parameter AWIDTH = 12;
parameter MEM_SIZE = 3040;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./spk_packet_rx_spk_A_V_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 7.194255 |
module spk_packet_rx_spk_A_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd128;
parameter AddressRange = 32'd3040;
parameter AddressWidth = 32'd12;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
spk_packet_rx_spk_A_V_ram spk_packet_rx_spk_A_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0)
);
endmodule
| 7.194255 |
module spk_packet_tx_buf_2d_V_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 128;
parameter AWIDTH = 13;
parameter MEM_SIZE = 5120;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./spk_packet_tx_buf_2d_V_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) begin
ram[addr1] <= d1;
end
end
end
endmodule
| 6.917827 |
module spk_packet_tx_buf_2d_V (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd128;
parameter AddressRange = 32'd5120;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
spk_packet_tx_buf_2d_V_ram spk_packet_tx_buf_2d_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.d1(d1),
.we1(we1)
);
endmodule
| 6.917827 |
module spk_packet_tx_cnt_A_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 5;
parameter AWIDTH = 8;
parameter MEM_SIZE = 160;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./spk_packet_tx_cnt_A_V_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 6.917827 |
module spk_packet_tx_cnt_A_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd5;
parameter AddressRange = 32'd160;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
spk_packet_tx_cnt_A_V_ram spk_packet_tx_cnt_A_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0)
);
endmodule
| 6.917827 |
module spk_packet_tx_state_A_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 2;
parameter AWIDTH = 8;
parameter MEM_SIZE = 160;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./spk_packet_tx_state_A_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 6.917827 |
module spk_packet_tx_state_A (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd2;
parameter AddressRange = 32'd160;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
spk_packet_tx_state_A_ram spk_packet_tx_state_A_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0)
);
endmodule
| 6.917827 |
module adder (
a,
b,
c
); //DUT code start
input [15:0] a, b;
output [16:0] c;
assign c = a + b;
endmodule
| 7.4694 |
module SplashInterface (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B, // VGA Blue[9:0]
HEX0,
HEX1,
HEX2,
HEX3,
LEDR
);
input CLOCK_50; // 50 MHz
input [9:0] SW;
input [3:0] KEY;
// Declare your inputs and outputs here
// Do not change the following outputs
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK_N; // VGA BLANK
output VGA_SYNC_N; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
output [9:0] LEDR;
output [6:0] HEX0, HEX1, HEX2, HEX3;
wire [2:0] colour;
//RESET
wire rst = SW[0];
// Create an Instance of a VGA controller - there can be only one!
// Define the number of colours as well as the initial background
// image file (.MIF) for the controller.
vga_adapter VGA (
.resetn(rst),
.clock(CLOCK_50),
.colour(colour),
.x(x),
.y(y),
.plot(wren),
/* Signals for the DAC to drive the monitor. */
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK)
);
defparam VGA.RESOLUTION = "160x120"; defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1; defparam VGA.BACKGROUND_IMAGE = "black.mif";
// Put your code here. Your code should produce signals x,y,colour and writeEn/plot
// for the VGA controller, in addition to any other functionality your design may require.
wire showTitle, drawBlack, showGameOver, flash, go;
wire [7:0] x;
wire [6:0] y;
rate_divider rd (
CLOCK_50,
rst,
32'd25_000_000,
tick
);
splash spl (
CLOCK_50,
rst,
SW[1],
KEY[0],
tick,
showTitle,
drawBlack,
showGameOver,
flash,
go,
wren
);
DrawBlack db (
CLOCK_50,
rst,
showTitle,
drawBlack,
showGameOver,
flash,
x,
y,
colour
);
endmodule
| 9.804532 |
module rate_divider (
input clk,
input reset_n,
input [31:0] val,
output en
);
wire [31:0] top_rate = val;
reg [31:0] curr;
always @(posedge clk, negedge reset_n) begin
if (!reset_n) curr <= top_rate;
else if (curr > 0) begin
curr <= curr - 1'b1;
end else curr <= top_rate;
end
assign en = ~|curr;
endmodule
| 7.346866 |
module Spline_formulation (
Xin_DELAY,
start,
CLK,
A,
B,
C,
D,
P1,
P2,
x,
I,
CSI_done,
Xout,
follow_start
);
input Xin_DELAY, start, CLK;
input A, B, C, D, P1, P2, x, I;
output CSI_done, Xout, follow_start;
wire signed [19:0] A, B, C, D, P1, P2;
wire signed [15:0] x;
reg CSI_done;
reg signed [19:0] Xout = 0;
reg follow_start = 0;
//
reg [5:0] num_clk = 0;
always @(CLK) begin
if (CLK == 1 && start == 1) begin
num_clk = num_clk + (num_clk != 31);
CSI_done = (num_clk == 30);
if (num_clk == 30) follow_start = 1;
end
if (x == P2 - 1) CSI_done = ~CLK;
end
always @(x) begin
//CSIֵ
//Բֵ
if (B == 0) begin
Xout = Xin_DELAY;
end else begin
Xout = (16 * A + B * (x - P1)) / 16;
end
end
endmodule
| 6.875911 |
module split16 (
Out,
In
);
input In;
output [15:0] Out;
assign Out = {In, In, In, In, In, In, In, In, In, In, In, In, In, In, In, In};
endmodule
| 6.830892 |
module Split16to2 (
input [15:0] Bus16,
output [ 7:0] Bus_8_1,
output [ 7:0] Bus_8_2
);
assign Bus_8_1 = Bus16[7:0];
assign Bus_8_2 = Bus16[15:8];
endmodule
| 7.202958 |
module Split8to2 (
input [7:0] Bus8,
output [3:0] Bus4_1,
output [7:4] Bus4_2
);
assign Bus4_1 = Bus8[3:0];
assign Bus4_2 = Bus8[7:4];
endmodule
| 6.627024 |
module splitbits (
d,
ultimos4,
penultimos4
);
input [31:0] d;
output [3:0] ultimos4, penultimos4;
assign ultimos4[3:0] = d[3:0];
assign penultimos4[3:0] = d[7:4];
endmodule
| 7.361263 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module splitter #(
parameter NUM_M = 2)(
input clk,
input resetn,
input s_valid,
output s_ready,
output [NUM_M-1:0] m_valid,
input [NUM_M-1:0] m_ready
);
reg [NUM_M-1:0] acked;
assign s_ready = &(m_ready | acked);
assign m_valid = s_valid ? ~acked : {NUM_M{1'b0}};
always @(posedge clk)
begin
if (resetn == 1'b0) begin
acked <= {NUM_M{1'b0}};
end else begin
if (s_valid & s_ready)
acked <= {NUM_M{1'b0}};
else
acked <= acked | (m_ready & m_valid);
end
end
endmodule
| 8.180735 |
module splitter36 (
input clk,
input rst,
input clr,
input [35:0] inp_data,
input inp_valid,
output inp_ready,
output [35:0] out0_data,
output out0_valid,
input out0_ready,
output [35:0] out1_data,
output out1_valid,
input out1_ready
);
localparam STATE_COPY_BOTH = 0;
localparam STATE_COPY_ZERO = 1;
localparam STATE_COPY_ONE = 2;
reg [ 1:0] state;
reg [35:0] data_reg;
assign out0_data = (state == STATE_COPY_BOTH) ? inp_data : data_reg;
assign out1_data = (state == STATE_COPY_BOTH) ? inp_data : data_reg;
assign out0_valid =
(state == STATE_COPY_BOTH)? inp_valid : (
(state == STATE_COPY_ZERO)? 1'b1 : (
1'b0));
assign out1_valid =
(state == STATE_COPY_BOTH)? inp_valid : (
(state == STATE_COPY_ONE)? 1'b1 : (
1'b0));
assign inp_ready = (state == STATE_COPY_BOTH) ? (out0_ready | out1_ready) : 1'b0;
always @(posedge clk)
if (rst | clr) begin
state <= STATE_COPY_BOTH;
end else begin
case (state)
STATE_COPY_BOTH: begin
if ((out0_valid & out0_ready) & ~(out1_valid & out1_ready)) begin
state <= STATE_COPY_ONE;
end else if (~(out0_valid & out0_ready) & (out1_valid & out1_ready)) begin
state <= STATE_COPY_ZERO;
end
data_reg <= inp_data;
end
STATE_COPY_ZERO: begin
if (out0_valid & out0_ready) begin
state <= STATE_COPY_BOTH;
end
end
STATE_COPY_ONE: begin
if (out1_valid & out1_ready) begin
state <= STATE_COPY_BOTH;
end
end
endcase //state
end
endmodule
| 7.454427 |
module splitter_2 #(
parameter bit_width = 1
) (
in,
d_out,
i_out,
enable,
selector
);
input [bit_width-1:0] in;
input enable;
input selector; // [D or I]
output reg [bit_width-1:0] d_out, i_out;
parameter DIRECT_TO_D = 0;
parameter DIRECT_TO_I = 1;
always @(in, selector, enable)
if (enable == 1) begin
case (selector)
DIRECT_TO_D: begin
d_out <= in;
i_out <= 1;
end
DIRECT_TO_I: begin
i_out <= in;
d_out <= 1;
end
default: begin
i_out <= 1;
d_out <= 1;
end
endcase
end else begin
d_out <= 1;
i_out <= 1;
end
endmodule
| 8.017089 |
module top_module (
input wire [15:0] in,
output wire [ 7:0] out_hi,
output wire [ 7:0] out_lo
);
assign out_hi = in[15:8];
assign out_lo = in[7:0];
// Concatenation operator also works: assign {out_hi, out_lo} = in;
endmodule
| 7.203305 |
module Split_16B_t ();
reg [15:0] input_a;
reg [7:0] output_low, output_high;
Split_16B s (
input_a,
output_low,
output_high
);
initial begin
$dumpfile("Split_16B.vcd");
$dumpvars;
input_a = 16'b1111_0000_1010_0101;
#50;
$finish;
end
endmodule
| 6.562617 |
module split_add (
a,
b,
o
);
parameter LS_WIDTH = 10;
parameter MS_WIDTH = 10;
parameter WIDTH = LS_WIDTH + MS_WIDTH;
input [WIDTH-1:0] a, b;
output [WIDTH-1:0] o;
wire [WIDTH-1:0] o;
// Build the less significant adder with an extra bit on the top to get
// the carry chain onto the normal routing. The keep pragma prevents
// synthesis from undoing the split.
wire [LS_WIDTH-1+1:0] ls_adder;
wire cross_carry = ls_adder[LS_WIDTH] /* synthesis keep */;
assign ls_adder = {1'b0, a[LS_WIDTH-1:0]} + {1'b0, b[LS_WIDTH-1:0]};
// Build the more significant adder with an extra low bit to incorporate
// the carry from the split lower chain.
wire [MS_WIDTH-1+1:0] ms_adder;
assign ms_adder = {a[WIDTH-1:WIDTH-MS_WIDTH],cross_carry} +
{b[WIDTH-1:WIDTH-MS_WIDTH],cross_carry};
// collect the sum back together, drop the two internal bits
assign o = {ms_adder[MS_WIDTH:1], ls_adder[LS_WIDTH-1:0]};
endmodule
| 7.54164 |
module split_add_tb ();
parameter LS_WIDTH = 15;
parameter MS_WIDTH = 20;
parameter WIDTH = LS_WIDTH + MS_WIDTH;
reg [WIDTH-1:0] a, b;
wire [WIDTH-1:0] oa, ob;
assign ob = a + b; // functional model
split_add s (
.a(a),
.b(b),
.o(oa)
);
defparam s.LS_WIDTH = LS_WIDTH; defparam s.MS_WIDTH = MS_WIDTH;
always begin
#100 a = {$random, $random};
b = {$random, $random};
#10
if (oa !== ob) begin
$display("Mismatch at time %d", $time);
$stop();
end
end
initial begin
#1000000 $display("PASS");
$stop();
end
endmodule
| 7.649568 |
module split_combine (
in,
num1,
num2,
num3,
num4,
number
);
input [7:0] in;
output [1:0] num1, num2, num3, num4;
output [8:0] number;
assign num1 = in[1:0];
assign num2 = in[3:2];
assign num3 = in[5:4];
assign num4 = in[7:6];
assign number = {num1, num2, num3, num4, 1'b1};
endmodule
| 6.520055 |
module: split_combine
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module split_combine_tb;
// Inputs
reg [7:0] in;
// Outputs
wire [8:0] number;
wire [1:0] num1;
wire [1:0] num2;
wire [1:0] num3;
wire [1:0] num4;
// Instantiate the Unit Under Test (UUT)
split_combine uut (
.number(number),
.num1(num1),
.num2(num2),
.num3(num3),
.num4(num4),
.in(in)
);
initial begin
// Initialize Inputs
$monitor($time,"in=%b,num1=%b,num2=%b,num3=%b,num4=%b,number=%b",in, num1, num2, num3, num4, number);
in = 8'b00110101;
#100;
end
endmodule
| 6.763509 |
module split_complex #(
parameter WIDTH = 16
) (
input [WIDTH*2-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [WIDTH-1:0] oi_tdata,
output oi_tlast,
output oi_tvalid,
input oi_tready,
output [WIDTH-1:0] oq_tdata,
output oq_tlast,
output oq_tvalid,
input oq_tready,
output error
);
assign oi_tdata = i_tdata[WIDTH*2-1:WIDTH];
assign oq_tdata = i_tdata[WIDTH-1:0];
assign oi_tlast = i_tlast;
assign oq_tlast = i_tlast;
assign oi_tvalid = i_tvalid;
assign oq_tvalid = i_tvalid;
assign i_tready = oi_tready;
assign error = oi_tready ^ oq_tready;
endmodule
| 8.546271 |
module split_data #(
parameter AXIS_TDATA_WIDTH = 32
) (
input [AXIS_TDATA_WIDTH-1:0] S_AXIS_tdata,
input S_AXIS_tvalid,
output [AXIS_TDATA_WIDTH/2-1:0] M_AXIS_OUT1_tdata,
output M_AXIS_OUT1_tvalid,
output [AXIS_TDATA_WIDTH/2-1:0] M_AXIS_OUT2_tdata,
output M_AXIS_OUT2_tvalid
);
assign M_AXIS_OUT1_tdata = S_AXIS_tdata[AXIS_TDATA_WIDTH/2-1:0];
assign M_AXIS_OUT2_tdata = S_AXIS_tdata[AXIS_TDATA_WIDTH-1:AXIS_TDATA_WIDTH/2];
assign M_AXIS_OUT1_tvalid = S_AXIS_tvalid;
assign M_AXIS_OUT2_tvalid = S_AXIS_tvalid;
endmodule
| 8.582444 |
module split_rgb (
input [23 : 0] pixel_in,
output [7 : 0] r_out,
output [7 : 0] g_out,
output [7 : 0] b_out
);
assign r_out = pixel_in[23-:8];
assign g_out = pixel_in[15-:8];
assign b_out = pixel_in[7 : 0];
endmodule
| 7.083255 |
module split_stream #(
parameter WIDTH = 16,
parameter ACTIVE_MASK = 4'b1111
) (
input clk,
input reset,
input clear, // These are not used in plain split_stream
input [WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [WIDTH-1:0] o0_tdata,
output o0_tlast,
output o0_tvalid,
input o0_tready,
output [WIDTH-1:0] o1_tdata,
output o1_tlast,
output o1_tvalid,
input o1_tready,
output [WIDTH-1:0] o2_tdata,
output o2_tlast,
output o2_tvalid,
input o2_tready,
output [WIDTH-1:0] o3_tdata,
output o3_tlast,
output o3_tvalid,
input o3_tready
);
assign {o0_tlast, o0_tdata} = {i_tlast, i_tdata};
assign {o1_tlast, o1_tdata} = {i_tlast, i_tdata};
assign {o2_tlast, o2_tdata} = {i_tlast, i_tdata};
assign {o3_tlast, o3_tdata} = {i_tlast, i_tdata};
// NOTE -- this violates the AXI spec because tvalids are dependent on treadys.
// It will be ok most of the time, but muxes and demuxes will need a fifo in
// the middle to avoid deadlock
assign i_tready = ~|(~{o3_tready, o2_tready, o1_tready, o0_tready} & ACTIVE_MASK);
assign {o3_tvalid, o2_tvalid, o1_tvalid, o0_tvalid} = {4{i_tready & i_tvalid}};
endmodule
| 8.09162 |
module split_stream_fifo #(
parameter WIDTH = 16,
parameter FIFO_SIZE = 5,
parameter ACTIVE_MASK = 4'b1111
) (
input clk,
input reset,
input clear,
input [WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [WIDTH-1:0] o0_tdata,
output o0_tlast,
output o0_tvalid,
input o0_tready,
output [WIDTH-1:0] o1_tdata,
output o1_tlast,
output o1_tvalid,
input o1_tready,
output [WIDTH-1:0] o2_tdata,
output o2_tlast,
output o2_tvalid,
input o2_tready,
output [WIDTH-1:0] o3_tdata,
output o3_tlast,
output o3_tvalid,
input o3_tready
);
wire [WIDTH-1:0] o0_tdata_int, o1_tdata_int, o2_tdata_int, o3_tdata_int;
wire o0_tlast_int, o1_tlast_int, o2_tlast_int, o3_tlast_int;
wire o0_tvalid_int, o1_tvalid_int, o2_tvalid_int, o3_tvalid_int;
wire o0_tready_int, o1_tready_int, o2_tready_int, o3_tready_int;
split_stream #(
.WIDTH(WIDTH),
.ACTIVE_MASK(ACTIVE_MASK)
) split_stream (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tdata(i_tdata),
.i_tlast(i_tlast),
.i_tvalid(i_tvalid),
.i_tready(i_tready),
.o0_tdata(o0_tdata_int),
.o0_tlast(o0_tlast_int),
.o0_tvalid(o0_tvalid_int),
.o0_tready(o0_tready_int),
.o1_tdata(o1_tdata_int),
.o1_tlast(o1_tlast_int),
.o1_tvalid(o1_tvalid_int),
.o1_tready(o1_tready_int),
.o2_tdata(o2_tdata_int),
.o2_tlast(o2_tlast_int),
.o2_tvalid(o2_tvalid_int),
.o2_tready(o2_tready_int),
.o3_tdata(o3_tdata_int),
.o3_tlast(o3_tlast_int),
.o3_tvalid(o3_tvalid_int),
.o3_tready(o3_tready_int)
);
generate
if (ACTIVE_MASK[0])
axi_fifo #(
.WIDTH(WIDTH + 1),
.SIZE (FIFO_SIZE)
) axi_fifo0 (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tdata({o0_tlast_int, o0_tdata_int}),
.i_tvalid(o0_tvalid_int),
.i_tready(o0_tready_int),
.o_tdata({o0_tlast, o0_tdata}),
.o_tvalid(o0_tvalid),
.o_tready(o0_tready),
.occupied(),
.space()
);
if (ACTIVE_MASK[1])
axi_fifo #(
.WIDTH(WIDTH + 1),
.SIZE (FIFO_SIZE)
) axi_fifo1 (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tdata({o1_tlast_int, o1_tdata_int}),
.i_tvalid(o1_tvalid_int),
.i_tready(o1_tready_int),
.o_tdata({o1_tlast, o1_tdata}),
.o_tvalid(o1_tvalid),
.o_tready(o1_tready),
.occupied(),
.space()
);
if (ACTIVE_MASK[2])
axi_fifo #(
.WIDTH(WIDTH + 1),
.SIZE (FIFO_SIZE)
) axi_fifo2 (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tdata({o2_tlast_int, o2_tdata_int}),
.i_tvalid(o2_tvalid_int),
.i_tready(o2_tready_int),
.o_tdata({o2_tlast, o2_tdata}),
.o_tvalid(o2_tvalid),
.o_tready(o2_tready),
.occupied(),
.space()
);
if (ACTIVE_MASK[3])
axi_fifo #(
.WIDTH(WIDTH + 1),
.SIZE (FIFO_SIZE)
) axi_fifo3 (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tdata({o3_tlast_int, o3_tdata_int}),
.i_tvalid(o3_tvalid_int),
.i_tready(o3_tready_int),
.o_tdata({o3_tlast, o3_tdata}),
.o_tvalid(o3_tvalid),
.o_tready(o3_tready),
.occupied(),
.space()
);
endgenerate
endmodule
| 6.6635 |
module spll_tb ();
reg clk_250Mhz = 0;
reg i_ld = 0;
reg [31:0] i_step = 0;
reg i_ce = 0;
reg clk_2kHz = 0;
reg [ 4:0] i_lgcoeff = 0;
wire [31:0] o_phase;
wire [ 1:0] o_err;
wire o_freq;
always begin
#2 clk_250Mhz = ~clk_250Mhz;
end
initial begin
#300000;
forever begin
clk_2kHz = 0;
#250000 clk_2kHz = 1'b1;
#250000;
end
end
initial begin
#1000 i_lgcoeff = 6;
//i_step = 32'd140737488;
i_step = 32'd34360; //2khz
//i_step = 32'd36078; //2.1khz
i_ld = 1;
#1001 i_ld = 0;
#1050 i_ce = 1;
end
//PLL
spll spll (
.i_clk(clk_250Mhz),
.i_ld (i_ld),
.i_step(i_step),
.i_ce (i_ce),
.i_input (clk_2kHz),
.i_lgcoeff(i_lgcoeff),
.o_phase (o_phase),
.o_err (o_err),
.o_freq (o_freq)
);
endmodule
| 6.605266 |
module spl_pt_mem #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input wire clk,
// port 0, read/write
input wire we0,
input wire re0,
input wire [ADDR_WIDTH-1:0] addr0,
input wire [DATA_WIDTH-1:0] din0,
output reg [DATA_WIDTH-1:0] dout0,
// port 1, read only
input wire re1,
input wire [ADDR_WIDTH-1:0] addr1,
output reg [DATA_WIDTH-1:0] dout1
);
`ifdef VENDOR_XILINX
(* ram_extract = "yes", ram_style = "block" *)
reg [DATA_WIDTH-1:0] mem[0:2**ADDR_WIDTH-1];
`else
(* ramstyle = "AUTO, no_rw_check" *) reg [DATA_WIDTH-1:0] mem[0:2**ADDR_WIDTH-1];
`endif
always @(posedge clk) begin
if (we0) mem[addr0] <= din0;
else if (re0) dout0 <= mem[addr0];
if (re1) dout1 <= mem[addr1];
end
endmodule
| 7.541383 |
module spl_sdp_mem #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input wire clk,
input wire we,
input wire re,
input wire [ADDR_WIDTH-1:0] raddr,
input wire [ADDR_WIDTH-1:0] waddr,
input wire [DATA_WIDTH-1:0] din,
output reg [DATA_WIDTH-1:0] dout
);
`ifdef VENDOR_XILINX
(* ram_extract = "yes", ram_style = "block" *)
reg [DATA_WIDTH-1:0] mem[0:2**ADDR_WIDTH-1];
`else
(* ramstyle = "no_rw_check" *) reg [DATA_WIDTH-1:0] mem[0:2**ADDR_WIDTH-1];
`endif
always @(posedge clk) begin
if (we) mem[waddr] <= din;
if (re) dout <= mem[raddr];
end
endmodule
| 8.218122 |
module spl_sp_mem #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input wire clk,
input wire we,
input wire re,
input wire [ADDR_WIDTH-1:0] addr,
input wire [DATA_WIDTH-1:0] din,
output reg [DATA_WIDTH-1:0] dout
);
// (* RAM_STYLE="{AUTO | BLOCK | BLOCK_POWER1 | BLOCK_POWER2}" *)
`ifdef VENDOR_XILINX
(* ram_extract = "yes", ram_style = "block" *)
reg [DATA_WIDTH-1:0] mem[2**ADDR_WIDTH-1:0];
`else
(* ramstyle = "AUTO, no_rw_check" *) reg [DATA_WIDTH-1:0] mem[0:2**ADDR_WIDTH-1];
`endif
always @(posedge clk) begin
if (we) mem[addr] <= din;
else if (re) dout <= mem[addr];
// synthesis translate_off
assert (!(we & re))
else $fatal("read-during-write at same time to location %x", addr);
// synthesis translate_on
end
endmodule
| 7.835296 |
module BSA (
x,
y,
clk,
rst,
s,
start
);
wire _0_;
wire _1_;
wire _2_;
wire _3_;
wire car1;
wire car2;
input clk;
wire fs;
input rst;
output s;
input start;
input x;
input y;
INVX8 _4_ (
.A(car1),
.Y(_2_)
);
NOR2X1 _5_ (
.A(start),
.B(_2_),
.Y(_0_)
);
INVX8 _6_ (
.A(fs),
.Y(_3_)
);
NOR2X1 _7_ (
.A(start),
.B(_3_),
.Y(_1_)
);
DFFSR _8_ (
.CLK(clk),
.D (_0_),
.Q (car2),
.R (rst),
.S (1'b1)
);
DFFSR _9_ (
.CLK(clk),
.D (_1_),
.Q (s),
.R (rst),
.S (1'b1)
);
FA fa (
.a(x),
.b(y),
.c(car2),
.cout(car1),
.out(fs)
);
endmodule
| 6.538219 |
module spm #(
parameter READ = 1,
parameter WRITE = 0
) (
input wire clk,
input wire rst_n,
input wire [31 : 0] if_spm_addr,
input wire if_spm_as_,
input wire if_spm_rw,
input wire [31 : 0] if_spm_wr_data,
output wire [31 : 0] if_spm_rd_data,
input wire [31 : 0] mem_spm_addr,
input wire mem_spm_as_,
input wire mem_spm_rw,
input wire [31 : 0] mem_spm_wr_data,
output wire [31 : 0] mem_spm_rd_data
);
reg [7 : 0] spm[0 : 1023];
integer i;
assign if_spm_rd_data = (!if_spm_as_ && (if_spm_rw == READ)) ?
{ spm[if_spm_addr],
spm[if_spm_addr + 1],
spm[if_spm_addr + 2],
spm[if_spm_addr + 3]} : 32'b0;
assign mem_spm_rd_data = (!mem_spm_as_ && (mem_spm_rw == READ)) ?
{ spm[mem_spm_addr],
spm[mem_spm_addr + 1],
spm[mem_spm_addr + 2],
spm[mem_spm_addr + 3] } : 32'b0;
//always @(posedge clk or negedge rst_n) begin
// if (!rst_n) begin
// for (i = 0; i < 1024;i = i + 1) begin
// spm[i] <= 8'b0;
// end
// end else if (!mem_spm_as_ && (mem_spm_rw == WRITE)) begin
// spm[mem_spm_addr] <= mem_spm_wr_data[31 : 24];
// spm[mem_spm_addr + 1] <= mem_spm_wr_data[23 : 16];
// spm[mem_spm_addr + 2] <= mem_spm_wr_data[15 : 8];
// spm[mem_spm_addr + 3] <= mem_spm_wr_data[7 : 0];
// end else if (!if_spm_as_ && (if_spm_rw == WRITE)) begin
// spm[if_spm_addr] <= if_spm_wr_data[31 : 24];
// spm[if_spm_addr + 1] <= if_spm_wr_data[23 : 16];
// spm[if_spm_addr + 2] <= if_spm_wr_data[15 : 8];
// spm[if_spm_addr + 3] <= if_spm_wr_data[7 : 0];
// end
//end
always @(posedge clk) begin
if (rst_n) begin
if (!mem_spm_as_ && (mem_spm_rw == WRITE)) begin
spm[mem_spm_addr] <= mem_spm_wr_data[31 : 24];
spm[mem_spm_addr+1] <= mem_spm_wr_data[23 : 16];
spm[mem_spm_addr+2] <= mem_spm_wr_data[15 : 8];
spm[mem_spm_addr+3] <= mem_spm_wr_data[7 : 0];
end else if (!if_spm_as_ && (if_spm_rw == WRITE)) begin
spm[if_spm_addr] <= if_spm_wr_data[31 : 24];
spm[if_spm_addr+1] <= if_spm_wr_data[23 : 16];
spm[if_spm_addr+2] <= if_spm_wr_data[15 : 8];
spm[if_spm_addr+3] <= if_spm_wr_data[7 : 0];
end
end
end
endmodule
| 6.559862 |
module SPMUL_TB;
reg clk, rst_an, start;
reg signed [15:0] sig;
reg signed [9:0] coef;
wire signed [15:0] result;
wire done;
SPMUL u_spmul (
.clk (clk),
.rst_an (rst_an),
.sig_in (sig),
.coef_in (coef),
.result_out(result),
.start (start),
.done (done)
);
initial begin
$dumpfile("spmul.vcd");
$dumpvars;
clk = 0;
rst_an = 0;
sig = 16'h7FFF;
coef = 10'h3FF; // sign-magnitude
start = 1;
#3 rst_an = 1;
#10 start = 0;
#1024;
end
always #5 clk = !clk;
always @(posedge done) begin
if ((done == 1) && (start == 0)) begin
$display("Expected: %d, got %d", -32703, result);
$finish;
end
end
endmodule
| 7.235359 |
module generic_fifo_sc_a #(
parameter dw = 8,
parameter aw = 8
) (
clk,
rst,
clr,
din,
we,
dout,
re,
full,
empty
);
parameter max_size = 1 << aw;
input clk, rst, clr;
input [dw-1:0] din;
input we;
output [dw-1:0] dout;
input wire re;
output full;
output empty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
wire [dw-1:0] din_nc;
wire [dw-1:0] out_nc;
reg [aw-1:0] wp;
wire [aw-1:0] wp_pl1;
reg [aw-1:0] rp;
wire [aw-1:0] rp_pl1;
reg gb;
////////////////////////////////////////////////////////////////////
//
// Memory Block
//
dpram #(
.AWIDTH(aw),
.DWIDTH(dw)
) u0 (
.clk(clk),
.address_a(rp),
.wren_a(0),
.data_a(din_nc),
.out_a(dout),
.address_b(wp),
.wren_b(we),
.data_b(din),
.out_b(out_nc)
);
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk or posedge rst)
if (rst) wp <= {aw{1'b0}};
else if (clr) wp <= {aw{1'b0}};
else if (we) wp <= wp_pl1;
assign wp_pl1 = wp + {{aw - 1{1'b0}}, 1'b1};
always @(posedge clk or posedge rst)
if (rst) rp <= {aw{1'b0}};
else if (clr) rp <= {aw{1'b0}};
else if (re) rp <= rp_pl1;
assign rp_pl1 = rp + {{aw - 1{1'b0}}, 1'b1};
////////////////////////////////////////////////////////////////////
//
// Combinatorial Full & Empty Flags
//
assign empty = ((wp == rp) & !gb);
assign full = ((wp == rp) & gb);
// Guard Bit ...
always @(posedge clk or posedge rst)
if (rst) gb <= 1'b0;
else if (clr) gb <= 1'b0;
else if ((wp_pl1 == rp) & we) gb <= 1'b1;
else if (re) gb <= 1'b0;
endmodule
| 6.701278 |
module dpram #(
parameter DWIDTH = 32,
parameter AWIDTH = 10
) (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
parameter NUM_WORDS = 1 << AWIDTH;
input clk;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
input wren_a;
input wren_b;
input [(DWIDTH-1):0] data_a;
input [(DWIDTH-1):0] data_b;
output reg [(DWIDTH-1):0] out_a;
output reg [(DWIDTH-1):0] out_b;
`ifdef SIMULATION
reg [DWIDTH-1:0] ram[NUM_WORDS-1:0];
always @(posedge clk) begin
if (wren_a) begin
ram[address_a] <= data_a;
end else begin
out_a <= ram[address_a];
end
end
always @(posedge clk) begin
if (wren_b) begin
ram[address_b] <= data_b;
end else begin
out_b <= ram[address_b];
end
end
`else
dual_port_ram u_dual_port_ram (
.addr1(address_a),
.we1 (wren_a),
.data1(data_a),
.out1 (out_a),
.addr2(address_b),
.we2 (wren_b),
.data2(data_b),
.out2 (out_b),
.clk (clk)
);
`endif
endmodule
| 7.813216 |
module spram #(
`ifdef SIMULATION
parameter INIT = "init.txt",
`endif
parameter AWIDTH = 5,
parameter NUM_WORDS = 32,
parameter DWIDTH = 16
) (
input clk,
input [(AWIDTH-1):0] address,
input wren,
input [(DWIDTH-1):0] din,
output reg [(DWIDTH-1):0] dout
);
`ifdef SIMULATION
reg [DWIDTH-1:0] mem[NUM_WORDS-1:0];
//initial begin
// $readmemh(INIT, mem);
//end
always @(posedge clk) begin
if (wren) begin
mem[address] <= din;
end else begin
dout <= mem[address];
end
end
`else
single_port_ram u_single_port_ram (
.addr(address),
.we (wren),
.data(din),
.out (dout),
.clk (clk)
);
`endif
endmodule
| 7.319281 |
module spm_tb;
//Inputs
reg clk;
reg rst;
reg signed [7:0] x;
reg signed [7:0] Y;
reg signed [15:0] P;
//Outputs
wire p;
reg [3:0] cnt;
wire done;
reg start;
//Instantiation of Unit Under Test
spm #(8) uut (
.clk(clk),
.rst(rst),
.y (Y[0]),
.x (x),
.p (p)
);
always #5 clk = ~clk;
always @(posedge clk)
if (rst) Y = 0;
else if (start) Y <= {1'b0, Y[7:1]};
always @(posedge clk)
if (rst) P = 0;
else if (start) P <= {p, P[15:1]};
always @(posedge clk)
if (rst) cnt = 0;
else if (start) cnt <= cnt + 1;
assign done = (cnt == 15);
initial begin
$dumpfile("spm.vcd");
$dumpvars(0, spm_tb);
//Inputs initialization
clk = 0;
rst = 0;
#20;
rst = 1;
#20;
rst = 0;
// Even x Even
x = 50;
Y = 50;
#10 start = 1'b1;
wait (done == 1'b1);
wait (done == 1'b0);
#20;
if (P == 2500) $display("[PASS] %d x %d = %d", x, 50, P);
else $display("[FAIL] %d x %d != %d", x, 50, P);
start = 1'b0;
#20;
rst = 1;
#20;
rst = 0;
// Odd x Odd
x = 25;
Y = 65;
#10 start = 1'b1;
wait (done == 1'b1);
wait (done == 1'b0);
#20;
if (P == 1625) $display("[PASS] %d x %d = %d", x, 65, P);
else $display("[FAIL] %d x %d != %d", x, 65, P);
start = 1'b0;
#20;
rst = 1;
#20;
rst = 0;
// Even x Odd
x = 80;
Y = 9;
#10 start = 1'b1;
wait (done == 1'b1);
wait (done == 1'b0);
#20;
if (P == (x * 9)) $display("[PASS] %d x %d = %d", x, 9, P);
else $display("[FAIL] %d x %d != %d", x, 9, P);
start = 1'b0;
#20;
rst = 1;
#20;
rst = 0;
// Odd x Even
x = 9;
Y = 80;
#10 start = 1'b1;
wait (done == 1'b1);
wait (done == 1'b0);
#20;
if (P == (x * 80)) $display("[PASS] %d x %d = %d", x, 80, P);
else $display("[FAIL] %d x %d != %d", x, 80, P);
start = 1'b0;
#20;
rst = 1;
#20;
rst = 0;
// Odd Signed x Even
x = -9;
Y = 80;
#10 start = 1'b1;
wait (done == 1'b1);
wait (done == 1'b0);
#20;
if (P == (x * 80)) $display("[PASS] %d x %d = %d", x, 80, P);
else $display("[FAIL] %d x %d != %d", x, 80, P);
start = 1'b0;
rst = 1;
#20;
rst = 0;
// Even Signed x Even
x = -8;
Y = 80;
#10 start = 1'b1;
wait (done == 1'b1);
wait (done == 1'b0);
#20;
if (P == (x * 80)) $display("[PASS] %d x %d = %d", x, 80, P);
else $display("[FAIL] %d x %d != %d", x, 80, P);
start = 1'b0;
rst = 1;
#20;
rst = 0;
#1000;
$finish;
end
endmodule
| 7.340232 |
module
*
* Change history:
*
**********************************************************************/
`timescale 1ns/1ns
module spm_top(mc, mp ,clk, rst, prod, start, done);
input clk;
input rst;
input [31:0] mc;
input [31:0] mp;
input start;
output reg [63:0] prod;
output done;
wire ybit;
wire prodbit;
wire proddone;
wire ld;
wire shift;
reg [6:0] count; // count number of clk cycles
shift_right shifter ( .x({{32 {mp[31]}},mp[31:0]}) , .clk(clk) , .rst(rst) , .ld(ld), .shift(shift), .out(ybit));
spm multiplier ( .x(mc[31:0]) ,.y(ybit) , .clk(clk) , .rst(rst) , .ld(ld) , .p(prodbit) );
multifsm fsm ( .clk(clk) , .rst(rst) , .proddone(proddone), .start(start), .done(done), .ld(ld), .shift(shift));
always @(posedge clk or posedge rst)
if (rst) begin
prod <= 0;
count <=0;
end
else begin
if (shift) begin // Multiply state
prod <= {prodbit, prod[63:1]};
count <= count+1;
end
else if (ld) begin // idle state
count <= 0;
prod <= 0;
end
else begin // done state
count <= count;
prod <= prod;
end
end
assign proddone = (count==66);
endmodule
| 6.571675 |
module spongent (
clk,
reset,
start_continue,
msg_data_available,
busy,
data_in,
data_out
);
// Define parameters
parameter integer MIN_CAPACITY = 128;
parameter integer RATE = 8; // Input block width
localparam MIN_WIDTH = RATE + MIN_CAPACITY;
localparam STATE_SIZE = MIN_WIDTH <= 88 ? 88 :
MIN_WIDTH <= 136 ? 136 :
MIN_WIDTH <= 176 ? 176 :
MIN_WIDTH <= 240 ? 240 :
MIN_WIDTH <= 264 ? 264 :
MIN_WIDTH <= 272 ? 272 :
MIN_WIDTH <= 336 ? 336 :
MIN_WIDTH <= 384 ? 384 :
MIN_WIDTH <= 480 ? 480 :
MIN_WIDTH <= 672 ? 672 :
MIN_WIDTH <= 768 ? 768 : 'hx;
localparam LFSR_SIZE = STATE_SIZE <= 88 ? 6 : STATE_SIZE <= 240 ? 7 : STATE_SIZE <= 480 ? 8 : 9;
localparam LFSR_POLY = LFSR_SIZE == 6 ? 7'b1100001 :
LFSR_SIZE == 7 ? 8'b11000001 :
LFSR_SIZE == 8 ? 9'b100011101 : 10'b1000010001;
localparam LFSR_INIT = STATE_SIZE == 88 ? 6'h05 :
STATE_SIZE == 136 ? 7'h7a :
STATE_SIZE == 176 ? 7'h45 :
STATE_SIZE == 240 ? 7'h01 :
STATE_SIZE == 264 ? 8'hd2 :
STATE_SIZE == 272 ? 8'h9e :
STATE_SIZE == 336 ? 8'h52 :
STATE_SIZE == 384 ? 8'hfb :
STATE_SIZE == 480 ? 8'ha7 :
STATE_SIZE == 672 ? 9'h105 : 9'h015;
// Define ports
input clk, reset;
input start_continue, msg_data_available;
output busy;
input [RATE - 1:0] data_in;
output [RATE - 1:0] data_out;
// Declare wires
wire reset_state, sample_state;
wire init_lfsr, update_lfsr, lfsr_all_1;
wire select_message;
// Instantiate modules
spongent_fsm fsm_instance (
.clk (clk),
.reset (reset),
.start_continue (start_continue),
.msg_data_available(msg_data_available),
.busy (busy),
.reset_state (reset_state),
.sample_state (sample_state),
.init_lfsr (init_lfsr),
.update_lfsr (update_lfsr),
.lfsr_all_1 (lfsr_all_1),
.select_message (select_message)
);
spongent_datapath #(
.STATE_SIZE(STATE_SIZE),
.RATE (RATE),
.LFSR_POLY (LFSR_POLY),
.LFSR_INIT (LFSR_INIT),
.LFSR_SIZE (LFSR_SIZE)
) datapath_instance (
.clk (clk),
.data_in (data_in),
.data_out (data_out),
.reset_state (reset_state),
.sample_state (sample_state),
.init_lfsr (init_lfsr),
.update_lfsr (update_lfsr),
.lfsr_all_1 (lfsr_all_1),
.select_message(select_message)
);
// debug output ****************************************************************
initial begin
$display("=== Spongent parameters ===");
$display("Rate: %3d", RATE);
$display("State size: %3d", STATE_SIZE);
$display("===========================");
end
endmodule
| 8.572087 |
module spongent_fsm (
clk,
reset,
start_continue,
msg_data_available,
busy,
reset_state,
sample_state,
init_lfsr,
update_lfsr,
lfsr_all_1,
select_message
);
// Define parameters
localparam integer STATE_SIZE = 4;
localparam [STATE_SIZE - 1:0] UNDEFINED = {STATE_SIZE{1'bx}},
RESET = 'b1,
IDLE = 'b10,
ABSORB = 'b100,
ROUNDS = 'b1000;
// Define ports
input clk, reset;
input start_continue, msg_data_available;
output busy;
output reset_state, sample_state;
output init_lfsr, update_lfsr;
input lfsr_all_1;
output select_message;
// Declare registers
reg [STATE_SIZE - 1:0] state_current;
reg [STATE_SIZE - 1:0] state_next;
reg reg_busy;
// Declare "registers" for FSM
wire reset_state;
wire init_lfsr;
reg sample_state;
reg update_lfsr;
reg select_message;
reg set_busy;
reg unset_busy;
// Reset for datapath
assign reset_state = reset;
assign init_lfsr = reset | lfsr_all_1;
// Busy signal
assign busy = reg_busy;
initial reg_busy <= 0;
always @(posedge clk) begin
if (unset_busy) reg_busy <= 0;
else if (set_busy) reg_busy <= 1;
else reg_busy <= reg_busy;
end
// State machine
always @(posedge clk or posedge reset) begin
if (reset) state_current <= RESET;
else state_current <= state_next;
end
// State transitions
always @(*) begin
state_next = UNDEFINED;
case (state_current)
RESET: state_next = IDLE;
IDLE: begin
if (start_continue) begin
if (msg_data_available) state_next = ABSORB;
else state_next = ROUNDS;
end else state_next = IDLE;
end
ABSORB: state_next = ROUNDS;
ROUNDS: begin // Continue as long as not all LFSR bits are one
if (lfsr_all_1) state_next = IDLE;
else state_next = ROUNDS;
end
endcase
end
// State dependent outputs
always @(*) begin
// Default outputs
sample_state = 0;
update_lfsr = 0;
select_message = 0;
set_busy = 0;
unset_busy = 0;
case (state_next)
IDLE: begin
unset_busy = 1;
end
ABSORB: begin
select_message = 1;
sample_state = 1;
update_lfsr = 1;
set_busy = 1;
end
ROUNDS: begin
sample_state = 1;
update_lfsr = 1;
set_busy = 1;
end
endcase
end
/*
always @ (negedge clk) begin
case (state_current)
RESET: $display("%d [RESET]", $time);
IDLE: $display("%d [IDLE]", $time);
ABSORB: $display("%d [ABSORB]", $time);
ROUNDS: $display("%d [ROUNDS]", $time);
default: $display("%d [RESET]", $time);
endcase
end
*/
endmodule
| 8.295983 |
module fifo_sport (
clk_rd,
clk_wr,
d_i,
d_o,
rst,
wr_en,
rd_en,
full,
empty
);
input clk_rd;
input clk_wr;
input [`SPORT_FIFODATAWIDTH-1:0] d_i;
output [`SPORT_FIFODATAWIDTH-1:0] d_o;
input rst;
input wr_en;
input rd_en;
output full;
output empty;
`ifdef SPORT_CUSTOMFIFO
`ifdef SPORT_WIDTH64
wire [7:0] full_int;
wire [7:0] empty_int;
assign full = |full_int;
assign empty = |empty_int;
custom_fifo_dp custom_fifo_dp1 (
clk_rd,
clk_wr,
d_i[63:56],
d_o[63:56],
rst,
wr_en,
rd_en,
full_int[0],
empty_int[0]
);
custom_fifo_dp custom_fifo_dp2 (
clk_rd,
clk_wr,
d_i[55:48],
d_o[55:48],
rst,
wr_en,
rd_en,
full_int[1],
empty_int[1]
);
custom_fifo_dp custom_fifo_dp3 (
clk_rd,
clk_wr,
d_i[47:40],
d_o[47:40],
rst,
wr_en,
rd_en,
full_int[2],
empty_int[2]
);
custom_fifo_dp custom_fifo_dp4 (
clk_rd,
clk_wr,
d_i[39:32],
d_o[39:32],
rst,
wr_en,
rd_en,
full_int[3],
empty_int[3]
);
custom_fifo_dp custom_fifo_dp5 (
clk_rd,
clk_wr,
d_i[31:24],
d_o[31:24],
rst,
wr_en,
rd_en,
full_int[4],
empty_int[4]
);
custom_fifo_dp custom_fifo_dp6 (
clk_rd,
clk_wr,
d_i[23:16],
d_o[23:16],
rst,
wr_en,
rd_en,
full_int[5],
empty_int[5]
);
custom_fifo_dp custom_fifo_dp7 (
clk_rd,
clk_wr,
d_i[15:8],
d_o[15:8],
rst,
wr_en,
rd_en,
full_int[6],
empty_int[6]
);
custom_fifo_dp custom_fifo_dp8 (
clk_rd,
clk_wr,
d_i[7:0],
d_o[7:0],
rst,
wr_en,
rd_en,
full_int[7],
empty_int[7]
);
`elsif SPORT_WIDTH32
wire [3:0] full_int;
wire [3:0] empty_int;
assign full = |full_int;
assign empty = |empty_int;
custom_fifo_dp custom_fifo_dp5 (
clk_rd,
clk_wr,
d_i[31:24],
d_o[31:24],
rst,
wr_en,
rd_en,
full_int[0],
empty_int[0]
);
custom_fifo_dp custom_fifo_dp6 (
clk_rd,
clk_wr,
d_i[23:16],
d_o[23:16],
rst,
wr_en,
rd_en,
full_int[1],
empty_int[1]
);
custom_fifo_dp custom_fifo_dp7 (
clk_rd,
clk_wr,
d_i[15:8],
d_o[15:8],
rst,
wr_en,
rd_en,
full_int[2],
empty_int[2]
);
custom_fifo_dp custom_fifo_dp8 (
clk_rd,
clk_wr,
d_i[7:0],
d_o[7:0],
rst,
wr_en,
rd_en,
full_int[3],
empty_int[3]
);
`elsif SPORT_WIDTH16
wire [1:0] full_int;
wire [1:0] empty_int;
assign full = |full_int;
assign empty = |empty_int;
custom_fifo_dp custom_fifo_dp7 (
clk_rd,
clk_wr,
d_i[15:8],
d_o[15:8],
rst,
wr_en,
rd_en,
full_int[0],
empty_int[0]
);
custom_fifo_dp custom_fifo_dp8 (
clk_rd,
clk_wr,
d_i[7:0],
d_o[7:0],
rst,
wr_en,
rd_en,
full_int[1],
empty_int[1]
);
`else
custom_fifo_dp custom_fifo_dp8 (
clk_rd,
clk_wr,
d_i[7:0],
d_o[7:0],
rst,
wr_en,
rd_en,
full,
empty
);
`endif
`endif
endmodule
| 6.519653 |
module custom_fifo_dp (
clk_rd,
clk_wr,
d_i,
d_o,
rst,
wr_en,
rd_en,
full,
empty
);
input clk_rd;
input clk_wr;
input [7:0] d_i;
output [7:0] d_o;
input rst;
input wr_en;
input rd_en;
output full;
output empty;
reg [`SPORT_FIFODEPTH-1:0] addr_rd;
reg [`SPORT_FIFODEPTH-1:0] addr_wr;
reg [7:0] fifo_out;
wire [7:0] mem_byte_out;
wire [`SPORT_FIFODEPTH-1:0] full_int;
//bytewide memory array in FIFO. user sets depth.
genvar c;
generate
for (c = 0; c < `SPORT_FIFODEPTH; c = c + 1) begin : mem
mem_byte mem_byte (
rst,
clk_wr,
d_i,
mem_byte_out,
addr_wr[c],
addr_rd[c]
);
end
endgenerate
//read logic needed here to handle clock domain change
assign d_o = fifo_out;
always @(posedge clk_rd or posedge rst) begin
if (rst) fifo_out <= 8'h0;
else fifo_out <= mem_byte_out;
end
//addressing logic is simply a circular shift register that gets reset to 1
always @(posedge clk_wr or posedge rst) begin
if (rst) addr_wr <= `SPORT_FIFODEPTH'h1;
else if (wr_en & (~full)) begin
addr_wr[`SPORT_FIFODEPTH-1:1] <= addr_wr[`SPORT_FIFODEPTH-2:0];
addr_wr[0] <= addr_wr[`SPORT_FIFODEPTH-1];
end
end
always @(posedge clk_rd or posedge rst) begin
if (rst) addr_rd <= `SPORT_FIFODEPTH'h1;
else if (rd_en & (~empty)) begin
addr_rd[`SPORT_FIFODEPTH-1:1] <= addr_rd[`SPORT_FIFODEPTH-2:0];
addr_rd[0] <= addr_rd[`SPORT_FIFODEPTH-1];
end
end
//use address logic for flags
assign empty = (addr_wr == addr_rd); //when read addr catches write addr, we're empty
assign full = empty ? 1'b0 : |full_int; //if fifo isn't empty, then OR all full flag outputs
assign full_int[0] = (addr_wr[`SPORT_FIFODEPTH-1] & addr_rd[0]); //when we've written to entire mem, we're full
genvar d;
generate
for (d = 1; d < `SPORT_FIFODEPTH; d = d + 1) begin : flag
assign full_int[d] = (addr_wr[d-1] & addr_rd[d]); //when we've written to entire mem, we're full
end
endgenerate
endmodule
| 7.97417 |
module sporta_demux (
input clk, // timespec 8.0 ns
input [15:0] stream,
input stream_tick,
output reg [13:0] adc1_data,
output reg [ 7:0] adc1_gate,
output reg [23:0] adc2_data,
output reg [ 3:0] adc2_gate,
input oaddr_sync, // wire to haddr[7]: falling edge triggers FIFO reload
input [3:0] oaddr,
output [7:0] fifo_out
);
// This Verilog module parallels mode5x.c
wire [7:0] d = stream[7:0];
wire c3z = stream[8];
wire [3:0] c4 = stream[12:9];
wire c5z = stream[13];
wire [1:0] c6 = stream[15:14];
reg [3:0] c3 = 0;
reg [7:0] lastd1 = 0, lastd2 = 0;
always @(posedge clk) begin
adc1_gate <= 0;
adc2_gate <= 0;
if (stream_tick) begin
c3 <= c3z ? 0 : c3 + 1;
lastd1 <= d;
lastd2 <= lastd1;
if ((c3 == 1) & (c4 > 1) & (c4 < 10)) begin
adc1_data <= {lastd1[6:0], d[7:1]};
adc1_gate[c4-2] <= 1;
end
if (c5z & (c3 == 3) & (c4 == 10)) begin
adc2_data <= {lastd2[6:0], lastd1, d, 1'b0};
adc2_gate[c6] <= 1;
end
end
end
// FIFO to send to USB clock domain
// Ideas and code structure adapted from slow_snap2.v
reg trig1 = 0, trig2 = 0, fifo_arm = 0, fifo_op = 0, fifo_ok = 0;
reg [127:0] shifter = 0; // intended to synthesize to 8 x SRL16E
always @(posedge clk) begin
trig1 <= oaddr_sync;
trig2 <= trig1;
if (~trig1 & trig2) begin // falling edge
fifo_arm <= 1;
fifo_ok <= 0;
end
if (stream_tick) begin
if (fifo_arm & (c4 == 1)) begin
fifo_arm <= 0;
fifo_op <= 1;
end
if (fifo_op & (c3[3:1] == 0) & (c4 > 1) & (c4 < 10)) begin
shifter <= {d, shifter[127:8]};
end
if (c4 == 10) begin
fifo_op <= 0;
fifo_ok <= 1;
end
end
end
wire [7:0] slow_data = shifter[{oaddr, 3'b0}+:8];
assign fifo_out = fifo_ok ? slow_data : 8'h80;
endmodule
| 7.268166 |
module sporta_tb;
reg clk;
wire SCK, SDI, CS_7794, CS_3548, CS_BIAS, SDO_7794, SDO_BIAS;
reg SDO_3548;
wire stream_tick;
wire [15:0] stream;
wire [8:0] sconfig = 9'h28; // led=0, gain=2(x4), filt=8(19.6 Hz)
wire [5:0] switch_sel = 8'h15;
reg switch_op = 0;
sporta mut (
.clk(clk),
.SCK(SCK),
.SDI(SDI),
.CS_7794(CS_7794),
.CS_3548(CS_3548),
.CS_BIAS(CS_BIAS),
.SDO_7794(SDO_7794),
.SDO_3548(SDO_3548),
.SDO_BIAS(SDO_BIAS),
.sconfig(sconfig),
.switch_sel(switch_sel),
.switch_op(switch_op),
.stream(stream),
.stream_tick(stream_tick)
);
integer cc;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("sporta.vcd");
$dumpvars(5, sporta_tb);
end
clk = 0;
for (cc = 0; cc < 50000; cc = cc + 1) begin
#10;
clk = 1;
#11;
clk = 0;
end
end
always @(posedge clk) begin
switch_op <= cc == 10000;
end
// Crude simulation of TLC3548
reg [15:0] sro_3548 = 0;
always @(posedge CS_3548) begin
#30;
SDO_3548 = 1'bz;
end
always @(negedge CS_3548) begin
sro_3548 = 16'h1234;
#30;
SDO_3548 = sro_3548[15];
end
always @(posedge SCK)
if (~CS_3548) begin
SDO_3548 = 1'bx;
#30;
sro_3548 = {sro_3548[14:0], 1'bx};
SDO_3548 = sro_3548[15];
end
// Crude simulation of AD7794
reg d_7794 = 0;
always @(negedge SCK) d_7794 <= $random;
assign SDO_7794 = CS_7794 ? 1'bx : d_7794;
reg [7:0] sri_7794;
integer cnt_7794;
always @(negedge CS_7794) begin
sri_7794 = 8'hxx;
cnt_7794 = 0;
$display("7794 CE");
end
always @(posedge SCK)
if (~CS_7794) begin
sri_7794 = {sri_7794[6:0], SDI};
cnt_7794 = cnt_7794 + 1;
if (cnt_7794 == 8) begin
$display("7794 Rx %x", sri_7794);
cnt_7794 = 0;
end
end
// Instantiate real simulation of CPLD
bias_ctl bias (
.SCK (SCK),
.SDI (SDI),
.STR (CS_BIAS),
.Trip1(1'b0),
.ON1 (1'b0),
.OFF1 (1'b0),
.Trip2(1'b0),
.ON2 (1'b0),
.OFF2 (1'b0),
.Trip3(1'b0),
.ON3 (1'b0),
.OFF3 (1'b0),
.SDO (SDO_BIAS)
);
endmodule
| 6.857347 |
module spram1 (
clk,
address,
wren,
data,
byteen,
out
);
parameter AWIDTH = 10;
parameter NUM_WORDS = 1024;
parameter DWIDTH = 32;
parameter LOG2DWIDTH = $clog2(DWIDTH);
input clk;
input [(AWIDTH-1):0] address;
input wren;
input [(DWIDTH/8)-1:0] byteen;
input [(DWIDTH-1):0] data;
output reg [(DWIDTH-1):0] out;
//`ifdef SIMULATION_MEMORY
integer i;
integer k;
reg [32-1:0] ram[67108864-1:0];
//reg [32-1:0] ram[4096-1:0];
reg [25:0] addr;
initial begin
//This is TOO big for 256 MB RAM! We right shift data by 1
$readmemh("instr.dat", ram, 'h100_0000);
$readmemh("data.dat", ram, 'h400_0000 >> 1);
end
always @(*) begin
addr = address << 26 - AWIDTH;
end
always @(posedge clk) begin
if (wren) begin
for (k = 0; k < DWIDTH / 32; k = k + 1) begin
for (i = 0; i < 4; i = i + 1) begin
if (byteen[((DWIDTH/8-1)-(4*k+i))]) ram[addr+k][i*8+:8] <= data[32*k+i*8+:8];
end
end
end else begin
for (i = 0; i < DWIDTH / 32; i = i + 1) begin
out[32*i+:32] <= ram[addr+i];
end
end
end
//`else
/*
//single_port_ram u_single_port_ram(
.addr(address),
.we(wren),
.data(data),
.out(out),
.clk(clk)
);
`endif
*/
endmodule
| 6.672129 |
modules
module spram128k (
clk,
re,
we,
din,
addr,
dout);
parameter ADDR_WIDTH = 17;
parameter DATA_WIDTH = 128;
input clk;
input re;
input we;
input [DATA_WIDTH-1:0] din;
input [ADDR_WIDTH-1:0] addr;
output [DATA_WIDTH-1:0] dout;
`define SIM_RAM
`ifdef SIM_RAM
spram #(.ADDR_WIDTH(ADDR_WIDTH)) R (
.clk(clk),
.cs(re || we),
.we(we),
.din(din),
.addr(addr),
.dout(dout)
);
`endif
endmodule
| 7.167451 |
module spram2 ( /*AUTOARG*/
// Outputs
ao_data,
// Inputs
clk,
rst,
ai_ce,
ai_we,
ai_oe,
ai_addr_w,
ai_addr_r,
ai_data,
ao_valid
);
//
// Default address and data buses width
//
parameter aw = 1;
parameter dw = 1;
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst;
input ai_ce; // Chip enable input
input ai_we; // Write enable input
input ai_oe; // Output enable input
input [aw-1:0] ai_addr_w; // address bus inputs
input [aw-1:0] ai_addr_r;
input [dw-1:0] ai_data; // input data bus
input ao_valid;
output [dw-1:0] ao_data; // output data bus
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
reg ai_oe_reg;
//
// Data output drivers
//
assign ao_data = (ai_oe_reg) ? mem[addr_reg] : {dw{1'bz}};
//
// RAM address register
//
always @(posedge clk) if (ao_valid) ai_oe_reg <= ai_oe;
always @(posedge clk) if (ai_ce) addr_reg <= ai_addr_r;
//
// RAM write
//
always @(posedge clk) if (ai_ce && ai_we) mem[ai_addr_w] <= ai_data;
endmodule
| 8.345549 |
module spram21x4 (
we,
dataout,
datain,
clk
);
input we;
output [21 - 1:0] dataout;
wire [21 - 1:0] dataout;
input [21 - 1:0] datain;
input clk;
reg [7:0] addr;
always @(posedge clk) begin
addr[0] <= we;
addr[1] <= addr[0];
addr[2] <= addr[1];
addr[3] <= addr[2];
addr[4] <= addr[3];
addr[5] <= addr[4];
addr[6] <= addr[5];
addr[7] <= addr[6];
end
//changed to odin 2 ram specifications
defparam new_ram.ADDR_WIDTH = 8; defparam new_ram.DATA_WIDTH = 21;
single_port_ram new_ram (
.clk (clk),
.we (we),
.data(datain),
.out (dataout),
.addr(addr)
);
endmodule
| 7.461827 |
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