code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module vc_LtComparator (
in0,
in1,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
output wire out;
assign out = in0 < in1;
endmodule
| 8.571994 |
module vc_GtComparator (
in0,
in1,
out
);
parameter p_nbits = 1;
input wire [p_nbits - 1:0] in0;
input wire [p_nbits - 1:0] in1;
output wire out;
assign out = in0 > in1;
endmodule
| 8.065152 |
module vc_LeftLogicalShifter (
in,
shamt,
out
);
parameter p_nbits = 1;
parameter p_shamt_nbits = 1;
input wire [p_nbits - 1:0] in;
input wire [p_shamt_nbits - 1:0] shamt;
output wire [p_nbits - 1:0] out;
assign out = in << shamt;
endmodule
| 8.380756 |
module vc_RightLogicalShifter (
in,
shamt,
out
);
parameter p_nbits = 1;
parameter p_shamt_nbits = 1;
input wire [p_nbits - 1:0] in;
input wire [p_shamt_nbits - 1:0] shamt;
output wire [p_nbits - 1:0] out;
assign out = in >> shamt;
endmodule
| 8.285177 |
module tapeout_SPI_TapeOutBlockVRTL (
clk,
reset,
loopthrough_sel,
minion_parity,
adapter_parity,
spi_min_sclk,
spi_min_cs,
spi_min_mosi,
spi_min_miso
);
parameter nbits = 34;
parameter num_entries = 5;
input wire clk;
input wire reset;
input wire loopthrough_sel;
output ... | 6.575478 |
module tapeout_SPI_TapeOutBlockVRTL_sv2v (
output adapter_parity,
input clk,
input loopthrough_sel,
output minion_parity,
input reset,
input spi_min_cs,
output spi_min_miso,
input spi_min_mosi,
input spi_min_sclk
);
tapeout_SPI_TapeOutBlockVRTL #(
.nbits(34),
.num... | 6.575478 |
module spi_target_bfm #(
parameter DAT_WIDTH = 8
) (
input reset,
input sck,
input sdi,
inout sdo,
input csn
);
reg sdo_r = 0;
assign sdo = (~csn)?sdo_r:1'bz;
reg[7:0] wordsize = 8;
reg[63:0] data = 0;
reg[7:0] bitcount = 0... | 7.035625 |
module spi_tb ();
// instanciate design under test
SPI dut (
.clk(clk),
.en(enable),
.rw(rw),
.data(data),
.address(address),
.busy(busy),
.spi_clk(spi_clk),
.spi_cs(spi_cs),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso)
);
reg clk;
reg enable;
reg [... | 6.596809 |
module: spi_topf
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module spi_tbf;
// Inputs
reg clk;
reg rst;
reg [1:0] dtf;
reg [1:0] slave;
// Bidirs
wire miso;
wire mosi;
wire ... | 6.638107 |
module spi (
input clk,
input rst,
input miso,
input en,
input [7:0] tx_data,
output [7:0] rx_data,
output sclk,
output reg busy,
output ss,
output mosi
);
localparam STATE_RST = 2'd0;
localparam STATE_IDLE = 2'd1;
localparam STATE_RUNNING = 2'd2;
wire [7:0] clk_div;
... | 6.715906 |
module: spi
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module write_read_spi;
// Inputs
reg clk;
reg rst_n;
reg spi_in;
// Outputs
wire spi_in_flag;
wire ss_n;
wire spi_ou... | 6.909089 |
module spi_test_tb;
reg clock;
reg RSTB;
reg CSB;
reg power1, power2;
reg power3, power4;
wire gpio;
wire [37:0] mprj_io;
wire [7:0] mprj_io_0;
wand WPn, HOLDn;
assign WPn = 1'b1;
assign HOLDn = 1'b1;
//assign mprj_io_0 = mprj_io[7:0];
// assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
as... | 6.765356 |
module spi_test_top (
`ifdef SIM
input sim_clk,
`endif
input pin1,
input pin2,
output pin3,
input pin4,
//input pin5,
//input pin6,
//input pin7,
//input pin8,
//output pin9,
//inout pin10_sda,
//inout pin11_scl,
//output pin16,
//output pin17,
//output pi... | 7.417432 |
module spi_test_top_tb #(
parameter SCLK_PERIOD = 9
) ();
reg clk, rst, sclk, mosi;
wire miso;
//reset
initial begin
clk = 0;
rst = 1;
#1;
rst = 1;
clk = 1;
#1;
clk = 0;
rst = 1;
#1;
clk = 1;
rst = 0;
#1;
clk = 0;
#1;
clk = 1;
#1;
clk = 0... | 6.90679 |
module spi_three_wire (
reset,
CLK,
GO,
bitcount,
SCLK,
bitcountEN,
rstbitcount,
LDEN,
SHEN,
SCEN,
ORDY,
SPC
);
input reset;
input CLK;
input GO;
input [3:0] bitcount;
tri0 reset;
tri0 GO;
tri0 [3:0] bitcount;
output SCLK;
output bitcountEN;
output rs... | 7.202294 |
module spi_three_wire (
reset,
CLK,
GO,
bitcount[3:0],
SCLK,
bitcountEN,
rstbitcount,
LDEN,
SHEN,
SCEN,
ORDY
);
input reset;
input CLK;
input GO;
input [3:0] bitcount;
tri0 reset;
tri0 GO;
tri0 [3:0] bitcount;
output SCLK;
output bitcountEN;
output rstbit... | 7.202294 |
module spi_three_wire_test;
reg reset;
reg CLK;
reg GO;
reg [3:0] bitcount;
wire SCLK;
wire bitcountEN;
wire rstbitcount;
wire LDEN;
wire SHEN;
wire SCEN;
wire ORDY;
wire SPC;
spi_three_wire spi0 (
reset,
CLK,
GO,
bitcount,
SCLK,
bitcountEN,
rstbitc... | 7.202294 |
module for output. BLOCK RAM address is
// updated upon receiving the DONE signal from I2S_master
//
//////////////////////////////////////////////////////////////////////////////////
module SPI_to_I2S_bridge(
input clk, rst,
input [15:0] spkr_data,
output data_out, m_clk, LR_clk, s_clk, DONE
);
reg [8... | 7.712233 |
module spi_transceiver (
input wire sys_rst,
input wire sys_clk,
input wire spi_miso,
output wire spi_mosi,
output reg spi_sck,
input wire [3:0] divisor,
input wire spi_enable,
output wire [7:0] rx_data,
input wire [7:0] tx_data,
input wire tx_wr,
output reg spi_done,... | 7.275178 |
module SPI_Transmitter #(
parameter SPI_DATALENGTH = 6'd32
) (
input clk,
input rst,
output reg sendComplete,
output MOSI,
output reg SCLK,
output reg CS,
input MISO,
input [31:0] sendData,
output reg [31:0] recvData
);
reg [31:0] sendData_reg;
reg [ 5:0] counter;
reg [ 1:0... | 7.538449 |
module SPI_trig_v2 (
input wire clk,
input wire trig,
input wire i_TX_ready,
//input reg[32:0] i_TX_Data,
output reg o_TX_DV
);
reg [0:0] trig_flag;
reg [0:0] ready_flag;
reg [1:0] DV_flag;
always @(posedge trig) begin
o_TX_DV <= 1'b1;
DV_flag <= 2'h1;
end
always @(posedge... | 6.838976 |
module SPI_TX (
input clk,
input CW_CLK_MSI,
input RSTn,
input [23:0] data,
input SPI_tx_en,
output MSI_SDATA, //! port 30, connected to pin N9
output wire MSI_SCLK, //! port 29, connected to pin M9
output ... | 6.689109 |
module spi_video (
input wire clk,
output wire oled_csn,
output wire oled_clk,
output wire oled_mosi,
output wire oled_dc,
output wire oled_resn,
output reg [7:0] x,
output reg [5:0] y,
input wire [7:0] color
);
wire [7:0] init_block[0:43];
// NOP
assign init_block[00] = 8'hB... | 6.749762 |
module spi_wrap_decode( input aclk,
input aresetn,
input [63:0] s_axis_tdata,
output s_axis_tready,
input s_axis_tvalid,
input s_axis_tlast,
input [7:0] s_... | 7.598736 |
module spi_write (
CLK,
SPC,
SDAT,
regdata,
GO, //GO transfor
ORDY,
reset,
SCEN
);
//=======================================================
// PARAMETER declarations
//=======================================================
//================================================... | 7.229781 |
module spi_writebyte (
input clk, //时钟信号 1m的时钟
input rst_n, //复位信号 按键复位
input ena_write, //spi写使能信号
input [7:0] data, //spi写的数据
output reg sclk, //oled的时钟信号（d0）
output reg mosi, //oled的数据信号（d1）
output write_done //spi写完成信号
);
parameter S0 = 0, S1 = 1, S2 = 2, Done = 3;
reg [1:0] ... | 7.575758 |
module spi_writebyte_tb ();
reg clk;
reg ena;
reg rst;
reg [7:0] data;
wire sclk;
wire mosi;
wire done;
spi_writebyte spi_writebyte_inst (
.clk(clk),
.ena_write(ena),
.rst_n(rst),
.data(data),
.sclk(sclk),
.mosi(mosi),
.write_done(done)
);
initial begin
... | 7.575758 |
module spi_xillybus_interface (
input bus_clk, //
input spi_clk, //
input reset, //
input [15:0] FIFO_DATA_STREAM,
input FIFO_DATA_STREAM_WEN,
input user_r_neural_dat... | 7.055226 |
module spk_clf_labels_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 9;
parameter MEM_SIZE = 500;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg ... | 6.896574 |
module spk_clf_labels_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd500;
parameter AddressWidth = 32'd9;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0... | 6.896574 |
module spk_clf_vq_comp_V_0_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 9;
parameter MEM_SIZE = 500;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) re... | 6.571734 |
module spk_clf_vq_comp_V_0 (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd500;
parameter AddressWidth = 32'd9;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] ... | 6.571734 |
module spk_counter #(
parameter NUM = 8
) (
input [NUM-1 : 0] fan_in,
output reg [ 7 : 0] counter // TODO: why reg?
);
integer i;
always @(fan_in) begin
counter = 0; //initialize count variable.
for (i = 0; i < NUM; i = i + 1) //for all the bits.
counter = counter + fan_in[i]; ... | 6.813319 |
module spk_dect_buf_2d_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 9;
parameter MEM_SIZE = 320;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg... | 6.655023 |
module spk_dect_buf_2d_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd320;
parameter AddressWidth = 32'd9;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d... | 6.655023 |
module spk_dect_cnt_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 3;
parameter AWIDTH = 8;
parameter MEM_SIZE = 160;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) r... | 7.134716 |
module spk_dect_cnt_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd3;
parameter AddressRange = 32'd160;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
... | 7.134716 |
module spk_dect_Mn_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 8;
parameter MEM_SIZE = 160;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg [DW... | 6.805281 |
module spk_dect_Mn_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd160;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
... | 6.805281 |
module spk_dect_mux_4to1_sel2_8_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din1,
input... | 6.863406 |
module spk_dect_start_cnt_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 1;
parameter AWIDTH = 8;
parameter MEM_SIZE = 160;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" ... | 6.770323 |
module spk_dect_start_cnt (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd1;
parameter AddressRange = 32'd160;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d... | 6.770323 |
module spk_dect_state_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 2;
parameter AWIDTH = 8;
parameter MEM_SIZE = 160;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) r... | 7.061612 |
module spk_dect_state (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd2;
parameter AddressRange = 32'd160;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
... | 7.061612 |
module spk_packet_rx_mac_muladd_6ns_8ns_5ns_13_3_DSP48_0 (
input clk,
input rst,
input ce,
input [6 - 1:0] in0,
input [8 - 1:0] in1,
input [5 - 1:0] in2,
output [13 - 1:0] dout
);
wire signed [25 - 1:0] a;
wire signed [18 - 1:0] b;
wire signed [48 - 1:0] c;
wire signed [43 - 1:0] m;... | 7.194255 |
module spk_packet_rx_mac_muladd_6ns_8ns_5ns_13_3 (
clk,
reset,
ce,
din0,
din1,
din2,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter din2_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
... | 7.194255 |
module spk_packet_rx_mul_6ns_8ns_13_3_MulnS_0 (
clk,
ce,
a,
b,
p
);
input clk;
input ce;
input [6 - 1 : 0] a; // synthesis attribute keep a "true"
input [8 - 1 : 0] b; // synthesis attribute keep b "true"
output [13 - 1 : 0] p;
reg [ 6 - 1 : 0] a_reg0;
reg [ 8 - 1 : 0] b_reg0;
w... | 7.194255 |
module spk_packet_rx_mul_6ns_8ns_13_3 (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input [din0_WIDTH - 1:0] d... | 7.194255 |
module spk_packet_rx_spk_A_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 128;
parameter AWIDTH = 12;
parameter MEM_SIZE = 3040;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block"... | 7.194255 |
module spk_packet_rx_spk_A_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd128;
parameter AddressRange = 32'd3040;
parameter AddressWidth = 32'd12;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth -... | 7.194255 |
module spk_packet_tx_buf_2d_V_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 128;
parameter AWIDTH = 13;
parameter MEM_SIZE = 5120;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDT... | 6.917827 |
module spk_packet_tx_buf_2d_V (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd128;
parameter AddressRange = 32'd5120;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output ... | 6.917827 |
module spk_packet_tx_cnt_A_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 5;
parameter AWIDTH = 8;
parameter MEM_SIZE = 160;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distribute... | 6.917827 |
module spk_packet_tx_cnt_A_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd5;
parameter AddressRange = 32'd160;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0... | 6.917827 |
module spk_packet_tx_state_A_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 2;
parameter AWIDTH = 8;
parameter MEM_SIZE = 160;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distribute... | 6.917827 |
module spk_packet_tx_state_A (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd2;
parameter AddressRange = 32'd160;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0... | 6.917827 |
module adder (
a,
b,
c
); //DUT code start
input [15:0] a, b;
output [16:0] c;
assign c = a + b;
endmodule
| 7.4694 |
module SplashInterface (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
... | 9.804532 |
module rate_divider (
input clk,
input reset_n,
input [31:0] val,
output en
);
wire [31:0] top_rate = val;
reg [31:0] curr;
always @(posedge clk, negedge reset_n) begin
if (!reset_n) curr <= top_rate;
else if (curr > 0) begin
curr <= curr - 1'b1;
end else curr <= top_rate;
en... | 7.346866 |
module Spline_formulation (
Xin_DELAY,
start,
CLK,
A,
B,
C,
D,
P1,
P2,
x,
I,
CSI_done,
Xout,
follow_start
);
input Xin_DELAY, start, CLK;
input A, B, C, D, P1, P2, x, I;
output CSI_done, Xout, follow_start;
wire signed [19:0] A, B, C, D, P1, P2;
wire sig... | 6.875911 |
module split16 (
Out,
In
);
input In;
output [15:0] Out;
assign Out = {In, In, In, In, In, In, In, In, In, In, In, In, In, In, In, In};
endmodule
| 6.830892 |
module Split16to2 (
input [15:0] Bus16,
output [ 7:0] Bus_8_1,
output [ 7:0] Bus_8_2
);
assign Bus_8_1 = Bus16[7:0];
assign Bus_8_2 = Bus16[15:8];
endmodule
| 7.202958 |
module Split8to2 (
input [7:0] Bus8,
output [3:0] Bus4_1,
output [7:4] Bus4_2
);
assign Bus4_1 = Bus8[3:0];
assign Bus4_2 = Bus8[7:4];
endmodule
| 6.627024 |
module splitbits (
d,
ultimos4,
penultimos4
);
input [31:0] d;
output [3:0] ultimos4, penultimos4;
assign ultimos4[3:0] = d[3:0];
assign penultimos4[3:0] = d[7:4];
endmodule
| 7.361263 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module splitter36 (
input clk,
input rst,
input clr,
input [35:0] inp_data,
input inp_valid,
output inp_ready,
output [35:0] out0_data,
output out0_valid,
input out0_ready,
output [35:0] out1_data,
output out1_valid,
input out1_ready
);
localparam STATE_COPY_BOTH = 0;
... | 7.454427 |
module splitter_2 #(
parameter bit_width = 1
) (
in,
d_out,
i_out,
enable,
selector
);
input [bit_width-1:0] in;
input enable;
input selector; // [D or I]
output reg [bit_width-1:0] d_out, i_out;
parameter DIRECT_TO_D = 0;
parameter DIRECT_TO_I = 1;
always @(in, selector, enabl... | 8.017089 |
module top_module (
input wire [15:0] in,
output wire [ 7:0] out_hi,
output wire [ 7:0] out_lo
);
assign out_hi = in[15:8];
assign out_lo = in[7:0];
// Concatenation operator also works: assign {out_hi, out_lo} = in;
endmodule
| 7.203305 |
module Split_16B_t ();
reg [15:0] input_a;
reg [7:0] output_low, output_high;
Split_16B s (
input_a,
output_low,
output_high
);
initial begin
$dumpfile("Split_16B.vcd");
$dumpvars;
input_a = 16'b1111_0000_1010_0101;
#50;
$finish;
end
endmodule
| 6.562617 |
module split_add (
a,
b,
o
);
parameter LS_WIDTH = 10;
parameter MS_WIDTH = 10;
parameter WIDTH = LS_WIDTH + MS_WIDTH;
input [WIDTH-1:0] a, b;
output [WIDTH-1:0] o;
wire [WIDTH-1:0] o;
// Build the less significant adder with an extra bit on the top to get
// the carry chain onto the norm... | 7.54164 |
module split_add_tb ();
parameter LS_WIDTH = 15;
parameter MS_WIDTH = 20;
parameter WIDTH = LS_WIDTH + MS_WIDTH;
reg [WIDTH-1:0] a, b;
wire [WIDTH-1:0] oa, ob;
assign ob = a + b; // functional model
split_add s (
.a(a),
.b(b),
.o(oa)
);
defparam s.LS_WIDTH = LS_WIDTH; defparam s.M... | 7.649568 |
module split_combine (
in,
num1,
num2,
num3,
num4,
number
);
input [7:0] in;
output [1:0] num1, num2, num3, num4;
output [8:0] number;
assign num1 = in[1:0];
assign num2 = in[3:2];
assign num3 = in[5:4];
assign num4 = in[7:6];
assign number = {num1, num2, num3, num4, 1'b1... | 6.520055 |
module: split_combine
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module split_combine_tb;
// Inputs
reg [7:0] in;
// Outputs
wire [8:0] number;
wire [1:0] num1;
wire [1:0] num2... | 6.763509 |
module split_complex #(
parameter WIDTH = 16
) (
input [WIDTH*2-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [WIDTH-1:0] oi_tdata,
output oi_tlast,
output oi_tvalid,
input oi_tready,
output [WIDTH-1:0] oq_tdata,
output oq_tlast,
output oq_tvalid,
... | 8.546271 |
module split_data #(
parameter AXIS_TDATA_WIDTH = 32
) (
input [AXIS_TDATA_WIDTH-1:0] S_AXIS_tdata,
input S_AXIS_tvalid,
output [AXIS_TDATA_WIDTH/2-1:0] M_AXIS_OUT1_tdata,
output M_AXIS_OUT1_tvalid,
output [AXIS_TDATA_WIDTH/2-1:0] M_AXIS_OUT2_t... | 8.582444 |
module split_rgb (
input [23 : 0] pixel_in,
output [7 : 0] r_out,
output [7 : 0] g_out,
output [7 : 0] b_out
);
assign r_out = pixel_in[23-:8];
assign g_out = pixel_in[15-:8];
assign b_out = pixel_in[7 : 0];
endmodule
| 7.083255 |
module split_stream #(
parameter WIDTH = 16,
parameter ACTIVE_MASK = 4'b1111
) (
input clk,
input reset,
input clear, // These are not used in plain split_stream
input [WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [WIDTH-1:0] o0_tdata,
output o0... | 8.09162 |
module split_stream_fifo #(
parameter WIDTH = 16,
parameter FIFO_SIZE = 5,
parameter ACTIVE_MASK = 4'b1111
) (
input clk,
input reset,
input clear,
input [WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [WIDTH-1:0] o0_tdata,
output o0_tlast,
... | 6.6635 |
module spll_tb ();
reg clk_250Mhz = 0;
reg i_ld = 0;
reg [31:0] i_step = 0;
reg i_ce = 0;
reg clk_2kHz = 0;
reg [ 4:0] i_lgcoeff = 0;
wire [31:0] o_phase;
wire [ 1:0] o_err;
wire o_freq;
always begin
#2 clk_250Mhz = ~clk_250Mhz;
end
initial begin
... | 6.605266 |
module spl_pt_mem #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input wire clk,
// port 0, read/write
input wire we0,
input wire re0,
input wire [ADDR_WIDTH-1:0] addr0,
input wire [DATA_WIDTH-1:0] din0,
output reg [DATA_WIDTH-1:0] ... | 7.541383 |
module spl_sdp_mem #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input wire clk,
input wire we,
input wire re,
input wire [ADDR_WIDTH-1:0] raddr,
input wire [ADDR_WIDTH-1:0] waddr,
input wire [DATA_WIDTH-1:0] din,
... | 8.218122 |
module spl_sp_mem #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input wire clk,
input wire we,
input wire re,
input wire [ADDR_WIDTH-1:0] addr,
input wire [DATA_WIDTH-1:0] din,
output reg [DATA_WIDTH-1:0] dout
);
/... | 7.835296 |
module BSA (
x,
y,
clk,
rst,
s,
start
);
wire _0_;
wire _1_;
wire _2_;
wire _3_;
wire car1;
wire car2;
input clk;
wire fs;
input rst;
output s;
input start;
input x;
input y;
INVX8 _4_ (
.A(car1),
.Y(_2_)
);
NOR2X1 _5_ (
.A(start),
.B(_2_),... | 6.538219 |
module spm #(
parameter READ = 1,
parameter WRITE = 0
) (
input wire clk,
input wire rst_n,
input wire [31 : 0] if_spm_addr,
input wire if_spm_as_,
input wire if_spm_rw,
input wire [31 : 0] if_spm_wr_data,
output wire [31 : 0] if_spm_rd_data... | 6.559862 |
module SPMUL_TB;
reg clk, rst_an, start;
reg signed [15:0] sig;
reg signed [9:0] coef;
wire signed [15:0] result;
wire done;
SPMUL u_spmul (
.clk (clk),
.rst_an (rst_an),
.sig_in (sig),
.coef_in (coef),
.result_out(result),
.start (start),
.done ... | 7.235359 |
module generic_fifo_sc_a #(
parameter dw = 8,
parameter aw = 8
) (
clk,
rst,
clr,
din,
we,
dout,
re,
full,
empty
);
parameter max_size = 1 << aw;
input clk, rst, clr;
input [dw-1:0] din;
input we;
output [dw-1:0] dout;
input wire re;
output full;
output empt... | 6.701278 |
module dpram #(
parameter DWIDTH = 32,
parameter AWIDTH = 10
) (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
parameter NUM_WORDS = 1 << AWIDTH;
input clk;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
input wren_a;
... | 7.813216 |
module spram #(
`ifdef SIMULATION
parameter INIT = "init.txt",
`endif
parameter AWIDTH = 5,
parameter NUM_WORDS = 32,
parameter DWIDTH = 16
) (
input clk,
input [(AWIDTH-1):0] address,
input wren,
input [(DWIDTH-1):0] din,
output reg [(DWIDTH-1):0] dout
);
`ifdef SIMULATION
reg [DW... | 7.319281 |
module spm_tb;
//Inputs
reg clk;
reg rst;
reg signed [7:0] x;
reg signed [7:0] Y;
reg signed [15:0] P;
//Outputs
wire p;
reg [3:0] cnt;
wire done;
reg start;
//Instantiation of Unit Under Test
spm #(8) uut (
.clk(clk),
.rst(rst),
.y (Y[0]),
.x (x),
.p (p)
... | 7.340232 |
module
*
* Change history:
*
**********************************************************************/
`timescale 1ns/1ns
module spm_top(mc, mp ,clk, rst, prod, start, done);
input clk;
input rst;
input [31:0] mc;
input [31:0] mp;
input start;
output reg [63:0] prod;
output done;
wire ybit;
wire prodbit;
wir... | 6.571675 |
module spongent (
clk,
reset,
start_continue,
msg_data_available,
busy,
data_in,
data_out
);
// Define parameters
parameter integer MIN_CAPACITY = 128;
parameter integer RATE = 8; // Input block width
localparam MIN_WIDTH = RATE + MIN_CAPACITY;
localparam STATE_SIZE = MIN_WIDTH... | 8.572087 |
module spongent_fsm (
clk,
reset,
start_continue,
msg_data_available,
busy,
reset_state,
sample_state,
init_lfsr,
update_lfsr,
lfsr_all_1,
select_message
);
// Define parameters
localparam integer STATE_SIZE = 4;
localparam [STATE_SIZE - 1:0] UNDEFINED = {STATE_SIZE{1'... | 8.295983 |
module fifo_sport (
clk_rd,
clk_wr,
d_i,
d_o,
rst,
wr_en,
rd_en,
full,
empty
);
input clk_rd;
input clk_wr;
input [`SPORT_FIFODATAWIDTH-1:0] d_i;
output [`SPORT_FIFODATAWIDTH-1:0] d_o;
input rst;
input wr_en;
input rd_en;
output full;
output empty;
`ifdef SPORT_CUS... | 6.519653 |
module custom_fifo_dp (
clk_rd,
clk_wr,
d_i,
d_o,
rst,
wr_en,
rd_en,
full,
empty
);
input clk_rd;
input clk_wr;
input [7:0] d_i;
output [7:0] d_o;
input rst;
input wr_en;
input rd_en;
output full;
output empty;
reg [`SPORT_FIFODEPTH-1:0] addr_rd;
reg [`SPORT_FI... | 7.97417 |
module sporta_demux (
input clk, // timespec 8.0 ns
input [15:0] stream,
input stream_tick,
output reg [13:0] adc1_data,
output reg [ 7:0] adc1_gate,
output reg [23:0] adc2_data,
output reg [ 3:0] adc2_gate,
input oaddr_sync, // wire to haddr[7]: falling edge triggers FIFO reload
... | 7.268166 |
module sporta_tb;
reg clk;
wire SCK, SDI, CS_7794, CS_3548, CS_BIAS, SDO_7794, SDO_BIAS;
reg SDO_3548;
wire stream_tick;
wire [15:0] stream;
wire [8:0] sconfig = 9'h28; // led=0, gain=2(x4), filt=8(19.6 Hz)
wire [5:0] switch_sel = 8'h15;
reg switch_op = 0;
sporta mut (
.clk(clk),
.SCK(... | 6.857347 |
module spram1 (
clk,
address,
wren,
data,
byteen,
out
);
parameter AWIDTH = 10;
parameter NUM_WORDS = 1024;
parameter DWIDTH = 32;
parameter LOG2DWIDTH = $clog2(DWIDTH);
input clk;
input [(AWIDTH-1):0] address;
input wren;
input [(DWIDTH/8)-1:0] byteen;
input [(DWIDTH-1):0] da... | 6.672129 |
modules
module spram128k (
clk,
re,
we,
din,
addr,
dout);
parameter ADDR_WIDTH = 17;
parameter DATA_WIDTH = 128;
input clk;
input re;
input we;
input [DATA_WIDTH-1:0] din;
input [ADDR_WIDTH-1:0] addr;
output [DATA_WIDTH-1:0] dout;
`define SIM_RAM
`ifdef SIM_RAM
spram #(.ADDR_WIDTH(ADDR_... | 7.167451 |
module spram2 ( /*AUTOARG*/
// Outputs
ao_data,
// Inputs
clk,
rst,
ai_ce,
ai_we,
ai_oe,
ai_addr_w,
ai_addr_r,
ai_data,
ao_valid
);
//
// Default address and data buses width
//
parameter aw = 1;
parameter dw = 1;
//
// Generic synchronous single-port RAM... | 8.345549 |
module spram21x4 (
we,
dataout,
datain,
clk
);
input we;
output [21 - 1:0] dataout;
wire [21 - 1:0] dataout;
input [21 - 1:0] datain;
input clk;
reg [7:0] addr;
always @(posedge clk) begin
addr[0] <= we;
addr[1] <= addr[0];
addr[2] <= addr[1];
addr[3] <= addr[2];
add... | 7.461827 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.