code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge ... | 8.023817 |
module spram32k8 (
input clk,
input [14:0] addr,
input write_enable,
input [7:0] data_in,
output [7:0] data_out
);
reg byte_select_reg;
wire [15:0] spram_datain = {data_in, data_in};
wire [3:0] spram_maskwren = addr[0] ? 4'b1100 : 4'b0011;
wire [15:0] spram_dataout;
assign data_out = byt... | 7.484429 |
module spram512x32 (
address,
clock,
data,
wren,
q
);
input [8:0] address;
input clock;
input [31:0] data;
input wren;
output [31:0] q;
spram512x32_bb ram1 (
.address(address),
.clock(clock),
.data(data),
.wren(wren),
.q(q)
);
endmodule
| 6.56129 |
module spramblock (
we,
addr,
datain,
dataout,
clk
);
input we;
input [10 - 1:0] addr;
input [32 - 1:0] datain;
output [32 - 1:0] dataout;
wire [32 - 1:0] dataout;
input clk;
defparam new_ram.ADDR_WIDTH = 10; defparam new_ram.DATA_WIDTH = 32;
single_port_ram new_ram (
.clk ... | 6.53176 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge ... | 8.023817 |
module SPRAM_16Kx16 (
input wire [13:0] addr,
input wire [15:0] din,
input wire [3:0] maskwren,
input wire wren,
input wire clk,
output reg [15:0] dout
);
reg [15:0] RAM[16383:0] /*verilator public*/;
always @(posedge clk) begin
if (wren) begin
if (maskwren[0]) RAM[addr][0+:4] <... | 6.622265 |
module SPRAM_16Kx16 (
input wire [13:0] addr,
input wire [15:0] din,
input wire [3:0] maskwren,
input wire wren,
input wire clk,
output wire [15:0] dout
);
SB_SPRAM256KA ram0 (
.ADDRESS(addr),
.DATAIN(din),
.MASKWREN(maskwren),
.CHIPSELECT(1'b1),
.CLOCK(clk),
... | 6.622265 |
module spram_16kx32 (
input clk,
input sel,
input [3:0] we,
input [15:0] addr,
input [31:0] wdat,
output [31:0] rdat
);
// instantiate the big RAMs
SB_SPRAM256KA mem_lo (
.ADDRESS(addr[15:2]),
.DATAIN(wdat[15:0]),
.MASKWREN({we[1], we[1], we[0], we[0]}),
.WREN(|we),
... | 6.525654 |
module spram_2048_40bit (
clk,
address,
wren,
data,
out
);
parameter AWIDTH = 11;
parameter NUM_WORDS = 2048;
parameter DWIDTH = 40;
input clk;
input [(AWIDTH-1):0] address;
input wren;
input [(DWIDTH-1):0] data;
output [(DWIDTH-1):0] out;
`ifndef hard_mem
reg [(DWIDTH-1):0] out;... | 7.613684 |
module spram_2048_60bit (
clk,
address,
wren,
data,
out
);
parameter AWIDTH = 11;
parameter NUM_WORDS = 2048;
parameter DWIDTH = 60;
input clk;
input [(AWIDTH-1):0] address;
input wren;
input [(DWIDTH-1):0] data;
output [(DWIDTH-1):0] out;
`ifndef hard_mem
reg [(DWIDTH-1):0] out;... | 7.228884 |
module spram_256k (
input clk,
input cs,
input [13:0] address,
input [15:0] write_data,
input [3:0] mask,
input write_en,
output reg [15:0] read_data
);
SB_SPRAM256KA ram (
.ADDRESS(address),
.DATAIN(write_data),
.MASKWREN(mask),
.WREN(write_en),
.CHIPSELECT(c... | 6.740246 |
module spram_4096_40bit (
clk,
address,
wren,
data,
out
);
parameter AWIDTH = 12;
parameter NUM_WORDS = 4096;
parameter DWIDTH = 40;
input clk;
input [(AWIDTH-1):0] address;
input wren;
input [(DWIDTH-1):0] data;
output [(DWIDTH-1):0] out;
`ifndef hard_mem
reg [(DWIDTH-1):0] out;... | 7.400334 |
module spram_4096_60bit (
clk,
address,
wren,
data,
out
);
parameter AWIDTH = 12;
parameter NUM_WORDS = 4096;
parameter DWIDTH = 60;
input clk;
input [(AWIDTH-1):0] address;
input wren;
input [(DWIDTH-1):0] data;
output [(DWIDTH-1):0] out;
`ifndef hard_mem
reg [(DWIDTH-1):0] out;... | 7.29278 |
module spram_4x1 (
input clk,
input [1:0] addr,
input d_in,
input wr_en,
output d_out
);
reg [3:0] mem;
assign d_out = mem[addr];
always @(posedge clk) begin
if (wr_en) begin
mem[addr] <= d_in;
end
end
endmodule
| 7.533622 |
module SPRAM16X16K_ASIC(
88 Q,
89 CLK,
90 CEN,
91 WEN,
92 A,
93 D);
95 parameter Bits = 16;
96 parameter Word_Depth = 16384;
97 parameter Add_Width = 14;
99 output [Bits-1:0] Q; // 数据输出
100 input CLK; // 输入时钟
101 ... | 7.021789 |
module spram_b (
input clk,
input [(7-1):0] address_a,
input wren_a,
input [(`DATA_WIDTH-1):0] data_a,
output reg [(`DATA_WIDTH-1):0] out_a
);
`ifdef SIMULATION_MEMORY
reg [`DATA_WIDTH-1:0] ram[`ARRAY_DEPTH-1:0];
always @(posedge clk) begin
if (wren_a) begin
ram[address_a] <= data_... | 7.38617 |
module spram_behav #(
parameter MEM_WIDTH = 32, // memory (bus) width
parameter MEM_DEPTH = 4096 // memory depth
) (
input wire clk, // system clock
input wire cen, // chip enable (active low)
input wire wen, // write e... | 6.669459 |
module spram_big (
clock,
reset_n,
value_out,
value_in
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`WIDTH-1:0] value_in;
output [`WIDTH-1:0] value_out;
wire [`WIDTH-1:0] value_out;
reg [`DEPTH-1:0] address_counter;
reg [`WIDTH-1:0] temp;
single_port_ram inst1 (
... | 6.721766 |
module spram #(
parameter ADDR_WIDTH = 6,
DATA_WIDTH = 8
) (
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] addr,
input we,
clk,
output [(DATA_WIDTH-1):0] q
);
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] addr_reg;
always @(posedge clk) begin
if (we) ... | 8.813407 |
module spram_u (
input clk,
input [(7-1):0] address_a,
input wren_a,
input [(`uarraysize-1):0] data_a,
output reg [(`uarraysize-1):0] out_a
);
`ifdef SIMULATION_MEMORY
reg [`uarraysize-1:0] ram[`ARRAY_DEPTH-1:0];
always @(posedge clk) begin
if (wren_a) begin
ram[address_a] <= data_... | 6.704553 |
module spram_v (
input clk,
input [(7-1):0] address_a,
input wren_a,
input [(`varraysize-1):0] data_a,
output reg [(`varraysize-1):0] out_a
);
`ifdef SIMULATION_MEMORY
reg [`varraysize-1:0] ram[`ARRAY_DEPTH-1:0];
always @(posedge clk) begin
if (wren_a) begin
ram[address_a] <= data_... | 7.316866 |
module spram_wait ( /*AUTOARG*/
// Outputs
ao_data,
ao_valid,
// Inputs
clk,
rst,
ai_ce,
ai_we,
ai_oe,
ai_addr_w,
ai_addr_r,
ai_data
);
parameter dw = 8, aw = 8;
// ************************************************
input clk;
input rst;
//
input ai_ce;
... | 8.0725 |
module spram_bw_wrapper #(
parameter dw = 32,
aw = 32,
col_w = 8,
nb_w = dw / col_w,
mem_size_bytes = 32'h0000_0400
) (
input clk_i,
input rst_i,
input [ aw-1:0] adr_i,
input ce_i,
input [nb_w-1:0] we_i,
input [ dw-1:0] dat_i,
output [ dw-1:0] dat_o
);
... | 6.871618 |
module sprdma (
input wire clk_in, // 100MHz system clock signal
input wire rst_in, // reset signal
input wire [15:0] cpumc_a_in, // cpu address bus in (to snoop cpu writes of 0x4014)
input wire [ 7:0] cpumc_din_in, // cpumc din bus in (to snoop cpu writes of 0x40... | 6.631217 |
module spread_spectrum (
code_out,
gps_data,
rst,
ss_data
);
input code_out;
input gps_data;
//input gps_clk;
input rst;
//reg code_out_reg,gps_data_reg,ss_en;
output wire ss_data;
assign ss_data = (rst) ? code_out ^ gps_data : 0;
// assign dpsk = dpsk_buf ^ ss_data;
//assig... | 6.644002 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge ... | 8.023817 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module addersub (
opB,
opA,
op,
result_slt,
result
);
//parameter WIDTH=32;
//`DEFINE WIDTH 32
input [31:0] opA;
input [31:0] opB;
//input carry_in;
input [2:0] op;
output result_slt;
output [31:0] result;
wire [32:0] sum;
wire addsub;
wire useless;
assign useless = o... | 7.127372 |
module reg_file (
clk,
resetn,
c_writedatain,
c_reg,
b_reg,
a_reg,
c_we,
b_en,
a_en,
b_readdataout,
a_readdataout
);
//parameter WIDTH=32;
//parameter NUMREGS=32;
//parameter LOG2NUMREGS=5;
input clk;
input resetn;
input a_en;
input b_en;
input [31:0] c_write... | 7.294051 |
module mul (
clk,
resetn,
sa,
dst,
opB,
opA,
op,
start,
stalled,
shift_result,
lo,
hi
);
input clk;
input resetn;
input start;
output stalled;
input [4:0] dst;
input [31:0] opA;
input [31:0] opB;
input [4:0] sa;
input [2:0] op;
output [31:0] shift... | 7.151423 |
module data_mem (
clk,
resetn,
stalled,
d_writedata,
d_address,
op,
d_loadresult
);
input clk;
input resetn;
output stalled;
input [`D_ADDRESSWIDTH-1:0] d_address;
input [3:0] op;
input [31:0] d_writedata;
output [`DM_DATAWIDTH-1:0] d_loadresult;
wire [`DM_BYTEENAWIDTH-1:0... | 7.214114 |
module store_data_translator (
write_data, // data in least significant position
d_address,
store_size,
d_byteena,
d_writedataout // shifted data to coincide with address
);
//parameter WIDTH=32;
input [31:0] write_data;
input [1:0] d_address;
input [1:0] store_size;
output [3:0] d_byt... | 8.280191 |
module load_data_translator (
d_readdatain,
d_loadresult
);
//parameter WIDTH=32;
input [31:0] d_readdatain;
output [31:0] d_loadresult;
wire d_adr_one;
assign d_adr_one = d_address[1];
reg [31:0] d_loadresult;
reg sign;
wire [1:0] d_address;
assign d_address[1:0] = d_readdatain[25:24];
... | 9.105161 |
module logic_unit (
opB,
opA,
op,
result
);
//parameter WIDTH=32;
input [31:0] opA;
input [31:0] opB;
input [1:0] op;
output [31:0] result;
reg [31:0] logic_result;
always @(opA or opB or op)
case (op)
2'b00: logic_result = opA & opB;
2'b01: logic_result = opA | opB;
... | 7.608724 |
module pcadder (
offset,
pc,
result
);
//parameter PC_WIDTH=32;
input [31:0] pc;
input [31:0] offset;
output [31:0] result;
wire dum;
wire useless_inputs;
assign useless_inputs = |offset;
assign {dum, result} = pc + {offset[31:0], 2'b0};
endmodule
| 6.899046 |
module signext16 (
in,
out
);
input [15:0] in;
output [31:0] out;
assign out[30] = in[15];
assign out[31] = in[15];
assign out[29] = in[15];
assign out[28] = in[15];
assign out[27] = in[15];
assign out[26] = in[15];
assign out[25] = in[15];
assign out[24] = in[15];
assig... | 7.934159 |
module lo_reg (
clk,
resetn,
d,
en,
q
);
//parameter WIDTH=32;
input clk;
input resetn;
input en;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk) begin
if (resetn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 8.102353 |
module hi_reg (
clk,
resetn,
d,
en,
q
);
//parameter WIDTH=32;
input clk;
input resetn;
input en;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk ) //used to be asynchronous reset
begin
if (resetn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodu... | 6.976139 |
module register (
d,
clk,
resetn,
en,
q
);
//parameter WIDTH=32;
input clk;
input resetn;
input en;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk) begin
if (resetn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 6.542519 |
module register_1bit (
d,
clk,
resetn,
en,
q
);
//parameter WIDTH=32;
input clk;
input resetn;
input en;
input d;
output q;
reg q;
always @(posedge clk) begin
if (resetn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 6.5297 |
module register_sync (
d,
clk,
resetn,
en,
q
);
//parameter WIDTH=32;
input clk;
input resetn;
input en;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 7.04221 |
module pipereg (
clk,
resetn,
d,
squashn,
en,
q
);
//parameter WIDTH=32;
//`define WIDTH 32
input clk;
input resetn;
input en;
input squashn;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0... | 7.345741 |
module pipereg_w32 (
clk,
resetn,
d,
squashn,
en,
q
);
//parameter WIDTH=32;
//`define WIDTH 32
input clk;
input resetn;
input en;
input squashn;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn... | 7.413603 |
module pipereg_w26 (
clk,
resetn,
d,
squashn,
en,
q
);
//parameter WIDTH=32;
//`define WIDTH 32
input clk;
input resetn;
input en;
input squashn;
input [25:0] d;
output [25:0] q;
reg [25:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn... | 7.064198 |
module pipereg_w6 (
clk,
resetn,
d,
squashn,
en,
q
);
//parameter WIDTH=32;
//`define WIDTH 32
input clk;
input resetn;
input en;
input squashn;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn ... | 7.166746 |
module pipereg_w5 (
clk,
resetn,
d,
squashn,
en,
q
);
//parameter WIDTH=32;
//`define WIDTH 32
input clk;
input resetn;
input en;
input squashn;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn ... | 7.56833 |
module pipereg_w1 (
clk,
resetn,
d,
squashn,
en,
q
);
//parameter WIDTH=32;
//`define WIDTH 32
input clk;
input resetn;
input en;
input squashn;
input d;
output q;
reg q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
els... | 7.073223 |
module pipereg_full (
d,
clk,
resetn,
squashn,
en,
q
);
//parameter WIDTH=32;
input clk;
input resetn;
input en;
input squashn;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
reg squash_save;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || (squash... | 7.204243 |
module zeroer (
d,
en,
q
);
//parameter WIDTH=32;
//`define WIDTH 32
input en;
input [4:0] d;
output [31:0] q;
assign q[4:0] = (en) ? d : 0;
assign q[31:05] = 0;
endmodule
| 8.282203 |
module nop (
d,
q
);
//parameter WIDTH=32;
//`define WIDTH 32
input [31:0] d;
output [31:0] q;
assign q = d;
endmodule
| 7.480252 |
module branch_detector (
opcode,
func,
is_branch
);
input [5:0] opcode;
input [5:0] func;
output is_branch;
wire is_special;
assign is_special = !(|opcode);
assign is_branch = ((!(|opcode[5:3])) && !is_special) || ((is_special) && (func[5:3] == 3'b001));
endmodule
| 7.697954 |
module branchresolve (
rt,
rs,
en,
eqz,
gez,
gtz,
lez,
ltz,
ne,
eq
);
//parameter WIDTH=32;
input en;
input [31:0] rs;
input [31:0] rt;
output eq;
output ne;
output ltz;
output lez;
output gtz;
output gez;
output eqz;
assign eq = (en) & (rs == rt);
a... | 9.028008 |
module SPREQ_FIFO (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull
);
input aclr;
input [39:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [39:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_... | 6.589889 |
module sprinkler_decoder_sprinker_decoder_v_tb ();
// Inputs
reg E;
reg A;
reg B;
reg C;
// Output
wire d0;
wire d1;
wire d2;
wire d3;
wire d4;
wire d5;
wire d6;
wire d7;
// Bidirs
// Instantiate the UUT
sprinkler_decoder UUT (
.d0(d0),
.d1(d1),
.d2(d2),
... | 7.037174 |
module sprinkler_decoder (
//I/o ports
input wire E,
input wire A,
input wire B,
input wire C,
output wire d0,
output wire d1,
output wire d2,
output wire d3,
output wire d4,
output wire d5,
output wire d6,
output wire d7
);
// Using the and4 module to set all ... | 7.037174 |
module sprite (
input wire clk,
input wire [10:0] hc, // posicion X de pantalla
input wire [10:0] vc, // posicion Y de pantalla
input wire [10:0] posx, // posicion X inicial del sprite
input wire [10:0] posy, // posicion Y inicial del sprite
input wire [7:0] rin, // color de pantalla
in... | 6.944101 |
module sprite4 (
input clock,
input resetn,
input move,
input jump,
input [19:0] ground_under_sprite,
input [6:0] ground_under_feet,
input [46:0] jumped_ground,
input rightmost_ground,
input erase,
output [8:0] x,
output [7:0] y,
output [2:0] colour,
output kill,
... | 8.163 |
module sprite_control (
input clock,
input resetn,
input jump,
input move,
input [6:0] ground_under_feet,
input [46:0] jumped_ground,
input rightmost_ground,
output reg [7:0] y0,
output kill,
output [6:0] t_out,
output [2:0] current_state_out,
output reg [11:0] score
);
... | 9.748011 |
module SpriteAnimation (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
LEDR,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA... | 9.179598 |
module translateout (
clock,
out,
coord_x,
coord_y,
x,
y,
colour,
writeEn
);
input clock;
input [15:0] out;
input [7:0] coord_x;
input [6:0] coord_y;
output reg [7:0] x;
output reg [6:0] y;
output reg writeEn;
output reg [2:0] colour;
wire [5:0] x_rel;
wire [5:0] y_re... | 6.708627 |
module SpriteCache #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8,
parameter DATA_DEPTH = 256
) (
input [DATA_WIDTH-1:0] data_in,
input [ADDR_WIDTH-1:0] addr,
input clk,
input we,
output [DATA_WIDTH-1:0] data_out
);
reg [DATA_WIDTH-1:0] da... | 8.147792 |
module SpriteMem (
MemSel,
Address,
DataOut,
Clock,
Resetn,
Width,
Height,
AnimSteps
);
input Clock, Resetn;
input [2:0] MemSel; // enable for 'external' memory (2:0 allows for 8 memories)
input [11:0] Address; // really wide memory address line - for 32*32 sprites with 4 animat... | 6.789277 |
module SpriteRAM (
address,
clock,
data,
wren,
q);
input [11:0] address;
input clock;
input [8:0] data;
input wren;
output [8:0] q;
wire [8:0] sub_wire0;
wire [8:0] q = sub_wire0[8:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (clock),
.address_a (address),
.data_a... | 6.657041 |
module spriteROM #(
ADDR_WIDTH = 10,
DATA_WIDTH = 8,
DEPTH = 32,
DEPTH_BIT = 5,
MEMFILE = ""
) (
input clk
, input [DEPTH_BIT-1:0] addr
, output reg [DATA_WIDTH-1:0] data
);
reg [DATA_WIDTH-1:0] mem[0:DEPTH-1];
initial begin
if (MEMFILE > 0) begin
$display("Loading: " + MEM... | 7.155997 |
module spriteROM0 (
address,
clock,
q
);
input [11:0] address;
input clock;
output [8:0] q;
wire [8:0] sub_wire0;
wire [8:0] q = sub_wire0[8:0];
altsyncram altsyncram_component (
.clock0(clock),
.address_a(address),
.q_a(sub_wire0),
.aclr0(1'b0),
.aclr1(1'b0),
... | 6.581257 |
module dataShifter (
data,
offset,
shiftedData
);
input [15:0] data;
input [4:0] offset;
output reg [15:0] shiftedData;
// Considerando shift para a esquerda negativo e para a direita positivo
always @(*) begin
if (offset[4]) begin
shiftedData = data << offset[3:0];
end else begin
... | 7.154049 |
module mux4 (
data0x,
data1x,
data2x,
data3x,
sel,
result
);
input [3:0] data0x, data1x, data2x, data3x;
input [1:0] sel;
output reg [3:0] result;
always @(sel or data0x or data1x or data2x or data3x) begin
case (sel)
2'd0: result = data0x;
2'd1: result = data1x;
... | 6.570124 |
module mux5 (
data0x,
data1x,
data2x,
data3x,
sel,
result
);
input [4:0] data0x, data1x, data2x, data3x;
input [1:0] sel;
output reg [4:0] result;
always @(sel or data0x or data1x or data2x or data3x) begin
case (sel)
2'd0: result = data0x;
2'd1: result = data1x;
... | 6.966221 |
module S2_interno (
clk,
clkPipeline,
reset_n,
sp0_num,
sp1_num,
sp2_num,
sp3_num,
sp0_line,
sp1_line,
sp2_line,
sp3_line,
sp0_offset,
sp1_offset,
sp2_offset,
sp3_offset,
sp0_en,
sp1_en,
sp2_en,
sp3_en,
v0_int,
v1_int,
v2_int,
v... | 7.150311 |
module S2_module (
clk,
reset_n,
clkPipeline,
sprite0,
sprite1,
sprite2,
sprite3,
v0,
v1,
v2,
v3,
v0_num,
v1_num,
v2_num,
v3_num
);
input clk, clkPipeline, reset_n;
input [14:0] sprite0, sprite1, sprite2, sprite3;
output [15:0] v0, v1, v2, v3;
output ... | 7.533696 |
module S2_pipeline_buffer (
clkPipeline,
v0_int,
v1_int,
v2_int,
v3_int,
v0num_int,
v1num_int,
v2num_int,
v3num_int,
v0,
v1,
v2,
v3,
v0_num,
v1_num,
v2_num,
v3_num
);
input clkPipeline;
input [15:0] v0_int, v1_int, v2_int, v3_int;
input [4:0] v... | 7.215324 |
module splitter (
sprite0,
sprite1,
sprite2,
sprite3,
sp0_num,
sp1_num,
sp2_num,
sp3_num,
sp0_line,
sp1_line,
sp2_line,
sp3_line,
sp0_offset,
sp1_offset,
sp2_offset,
sp3_offset,
sp0_en,
sp1_en,
sp2_en,
sp3_en
);
input [14:0] sprite0, spr... | 7.230286 |
module sram_addr_decoder (
clk,
lineNumber,
spriteNumber,
address
);
input clk;
input [3:0] lineNumber;
input [4:0] spriteNumber;
output [19:0] address;
assign address = (20'd16 * spriteNumber) + lineNumber;
endmodule
| 6.652576 |
module t5_t6 (
v0,
v1,
v2,
v3,
sp0,
sp1,
sp2,
sp3,
clock_25,
clock_maior,
rst,
att_color,
data_color,
blue,
green,
red,
branco
);
// Sinais básicos de controle
input clock_25, rst;
// Vetores com as flags indicando a presenca dos sprites em cad... | 7.632149 |
module t7 (
input wire [7:0] FIFO_Red,
input wire [7:0] FIFO_Green,
input wire [7:0] FIFO_Blue,
input wire [7:0] Sprites_Red,
input wire [7:0] Sprites_Green,
input wire [7:0] Sprites_Blue,
output wire [7:0] VGA_R,
output wire [7:0] VGA_G,
output wire [7:0] VGA_B,
output wire show... | 6.868072 |
module SPITER_testbench (
VGA_R,
VGA_G,
VGA_B
);
// -------------------------------------------- Variáveis -------------------------------------------- //
reg clk_125, clk_25, clk_25_16, n_reset;
wire [9:0] row, column;
wire [7:0] FIFO_Red, FIFO_Green, FIFO_Blue;
wire [23:0] data_color;
ou... | 7.137995 |
module car_bitmap (
input wire [3 : 0] yofs,
output wire [7 : 0] bits
);
/*******************************************************
* WIRE AND REG DECLARATION *
*******************************************************/
reg [7 : 0] bitarray[0 : 15];
/**********************... | 8.422706 |
module sprite_mem (
clk,
addr,
rdata
);
parameter ROM_DATA_FILE = "sprite0.mem";
input clk;
input [9:0] addr;
output reg [7:0] rdata;
reg [7:0] MY_ROM[0:2**10-1];
initial $readmemb(ROM_DATA_FILE, MY_ROM);
always @(posedge clk) rdata <= MY_ROM[addr];
endmodule
| 6.954692 |
module sprite_memory (
input wire [13:0] address,
input wire clock,
input wire reset_done,
input wire [ 8:0] data,
input wire wren,
output reg [8:0] out_data,
output wire read_memory
);
reg r_memory;
wire [8:0] colors;
/*--------Sempre que sentir uma mud... | 7.666376 |
module sprite_rom #(
parameter FILE = "./sprites/test_sprite.mem"
) (
input [9:0] x,
input [9:0] y,
output [7:0] data
);
//combinatorial ROM for square sprites
localparam sq_size = 16;
reg [3:0] memory[0:255];
initial begin
if (FILE != 0) begin
$readmemh(FILE, memory);
end
e... | 8.287406 |
module tank_bitmap (
input wire [7 : 0] addr,
output wire [7 : 0] bits
);
/*******************************************************
* WIRE AND REG DECLARATION *
*******************************************************/
reg [15 : 0] bitarray[0 : 255];
assign bits = (addr... | 6.851062 |
module sprite_renderer2 (
input wire [0 : 0] clk,
input wire [0 : 0] reset,
input wire [0 : 0] vstart,
input wire [0 : 0] load,
input wire [0 : 0] hstart,
output reg [4 : 0] rom_addr,
input wire [7 : 0] rom_bits,
input wire [0 : 0] hmirror,
input wire [0 : 0] vmirror,
ou... | 7.563984 |
module rotation_selector (
input wire [3 : 0] rotation,
output reg [2 : 0] bitmap_num,
output reg [0 : 0] hmirror,
output reg [0 : 0] vmirror
);
/*******************************************************
* OTHER COMB AND SEQ LOGIC *
*******************************... | 8.030049 |
module tank_top (
input wire [0 : 0] clk,
input wire [0 : 0] reset,
input wire [0 : 0] switch_left,
input wire [0 : 0] switch_right,
input wire [0 : 0] switch_up,
output wire [0 : 0] hsync,
output wire [0 : 0] vsync,
output wire [2 : 0] rgb
);
/************************************... | 7.139186 |
module for culling and sorting sprites to be displayed on a particular
// scanline.
// This uses the pre-transformed sprite data to determine if a sprite scanline
// exists on the current line or not.
// It caches data for up to N sprites, which is then read by the line writer
// during the display routine.
// This mo... | 7.623554 |
module example_bitmap_rom (
input wire [15 : 0] addr,
output wire [15 : 0] data
);
/*******************************************************
* WIRE AND REG DECLARATION *
*******************************************************/
reg [15:0] bitarray[0 : 255];
assign data ... | 8.904245 |
module sprite_scanline_renderer_top (
input wire [0 : 0] clk,
input wire [0 : 0] reset,
output wire [0 : 0] hsync,
output wire [0 : 0] vsync,
output wire [2 : 0] rgb
);
/*******************************************************
* PARAMS & LOCALPARAMS *
*****... | 8.642635 |
module Sprite_Sel (
input clk,
input [3:0] inputs,
input [1:0] step,
output reg [8:0] hoffset,
output reg [8:0] voffset
);
wire have_inputs;
reg walk = 0;
assign have_inputs = (inputs == 8 || inputs == 4 || inputs == 2 || inputs == 1);
initial begin
hoffset <= 0;
voffset <= 0;
end... | 6.710373 |
module sprite_subsystem(
input wire rst_n,
input wire CLK_6M,
input wire CLK_1H,
input wire nOBJECT,
input wire nHSYNC,
input wire nVRESET,
input wire [12:0] A,
inout wire [7:0] D,
input wire RnW,
`SRAM_OUTPUT_DEFS(CY6264, sram_10m),
`SRAM_OUTPUT_DEFS(M58725, sram_11k)
);
wire cus35_9m_... | 6.855392 |
module sprom(clk, rst, ce, oe, addr, do);
//
// Default address and data buses width (1024*32)
//
parameter aw = 10; //number of address-bits
parameter dw = 32; //number of data-bits
parameter MEM_INIT_FILE = "";
//
// Generic synchronous single-port ROM interface
//
input clk; // Clock, rising ed... | 8.036795 |
module sprom2phase(
clk,
rst,
ph1_en,
ph1_addr,
ph1_do,
ph2_en,
ph2_addr,
ph2_do
);
parameter aw = 10; //number of address-bits
parameter dw = 32; //number of data-bits
parameter MEM_INIT_FILE = "";
input clk;
input rst;
input ph1_en;
input [aw-1:0] ph1_addr;
output reg [dw-1:0] ph1_do;
... | 7.384423 |
module SPRWI #(
parameter DATA_WIDTH = 4,
parameter ADDR_WIDTH = 6
) (
input [(DATA_WIDTH - 1):0] i_Data,
input [(ADDR_WIDTH - 1):0] i_Addr, // Memory address
input i_WriteEnable,
i_Clock,
output [(DATA_WIDTH - 1):0] o_Data
);
// Declare the RAM variable
reg [(DATA_WIDTH - 1):0] r_Ram... | 8.509193 |
module SPS (
input clk,
in,
in2,
ps2_clk,
ps2_data,
output [6:0] segments,
segments2,
output reg buzzer,
output reg [6:0] f,
u,
l1,
l2
);
wire [7:0] max;
reg [3:0] max1;
keyboard(
max, clk, ps2_clk, ps2_data
);
reg state = 0;
wire [3:0] count1;
wire [... | 6.616976 |
module implements a parameterizable Last-In, First-Out (LIFO) function.
// Parameters allow setting the depth, width, and memory contents. It's intend-
// ed for use as return address stacks for microprogram sequencers, microcompu-
// ters, ALUs, etc.
//
// The module provides a clock enable, and separate push and ... | 6.904081 |
module spsram (
clk,
cs,
we,
addr,
din,
dout
);
parameter mem_depth = 1024;
parameter mem_width = 32;
parameter mem_bitw = 10;
input wire clk;
input wire cs;
input wire we;
input wire [mem_bitw-1:0] addr;
input wire [mem_width-1:0] din;
output reg [mem_width-1:0] dout;
reg... | 7.523016 |
module spu (
input clk,
input rst,
input start, // to start the processor
output stop, // to show that the processor is stopped
//control signals for instruction memory (im)
input [15:0] im_r_data, // 16-bit read data of im
output [ 7:0] im_addr, // 8-bit data address of im
ou... | 6.846924 |
module spu_datapath (
input clk,
input rst,
output pco_en, // if rf[a] equals to 0
//control signal for mux
input rf_s1,
input rf_s0,
//control signals for register file (rf)
input [3:0] rf_w_addr, // 4-bit write address
input rf_w_wr, // write enable
input [3:0... | 7.836836 |
module SPWM_3Phase (
CLK,
RST,
SW,
CCW,
PHA,
PLA,
PHB,
PLB,
PHC,
PLC
);
input CLK, RST, CCW;
input [4:0] SW;
output PHA, PLA, PHB, PLB, PHC, PLC;
wire CP;
wire [3:0] Sublevel;
wire [11:0] PWMA;
wire [11:0] PWMB;
wire [11:0] PWMC;
//实例化时钟脉冲发生器
TimePulGenerator... | 8.862614 |
module top (
input clk,
output out1,
output out2
);
wire [5:0] w_sel1;
wire w_sel2;
wire w_CE;
data_path d1 (
.clk (w_CE),
.sel1(w_sel1),
.sel2(w_sel2),
.out1(out1),
.out2(out2)
);
controller c1 (
.clk (w_CE),
.sel1(w_sel1),
.sel2(w_sel2)
);
... | 7.233807 |
module data_path (
input clk,
input [5:0] sel1,
input sel2,
output out1,
output out2
);
wire w_1, w_2;
spwm s1 (
.clk (clk),
.sel1(sel1),
.out (w_1)
);
spwm s2 (
.clk (clk),
.sel1(sel1),
.out (w_2)
);
H_driver H1 (
.clk (clk),
.sel2(se... | 6.77594 |
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