code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we) begin
ram[addr] <= data;
end else begin
out <= ram[addr];
end
end
endmodule
| 8.023817 |
module spram32k8 (
input clk,
input [14:0] addr,
input write_enable,
input [7:0] data_in,
output [7:0] data_out
);
reg byte_select_reg;
wire [15:0] spram_datain = {data_in, data_in};
wire [3:0] spram_maskwren = addr[0] ? 4'b1100 : 4'b0011;
wire [15:0] spram_dataout;
assign data_out = byte_select_reg ? spram_dataout[15:8] : spram_dataout[7:0];
always @(posedge clk) begin
// Latch byte select at clock edge
byte_select_reg <= addr[0];
end
// ICE40 SPRAM behavior, at +ve clock edge, data read at address is latched
// into data output and data written if present => address needs to be present
// before clock edge.
SB_SPRAM256KA spram (
.CLOCK(clk),
.ADDRESS(addr[14:1]),
.DATAIN(spram_datain),
.MASKWREN(spram_maskwren),
.WREN(write_enable),
.CHIPSELECT(1'b1),
.DATAOUT(spram_dataout),
.SLEEP(1'b0),
.POWEROFF(1'b1),
.STANDBY(1'b0)
);
endmodule
| 7.484429 |
module spram512x32 (
address,
clock,
data,
wren,
q
);
input [8:0] address;
input clock;
input [31:0] data;
input wren;
output [31:0] q;
spram512x32_bb ram1 (
.address(address),
.clock(clock),
.data(data),
.wren(wren),
.q(q)
);
endmodule
| 6.56129 |
module spramblock (
we,
addr,
datain,
dataout,
clk
);
input we;
input [10 - 1:0] addr;
input [32 - 1:0] datain;
output [32 - 1:0] dataout;
wire [32 - 1:0] dataout;
input clk;
defparam new_ram.ADDR_WIDTH = 10; defparam new_ram.DATA_WIDTH = 32;
single_port_ram new_ram (
.clk (clk),
.we (we),
.data(datain),
.out (dataout),
.addr(addr)
);
endmodule
| 6.53176 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we) begin
ram[addr] <= data;
end else begin
out <= ram[addr];
end
end
endmodule
| 8.023817 |
module SPRAM_16Kx16 (
input wire [13:0] addr,
input wire [15:0] din,
input wire [3:0] maskwren,
input wire wren,
input wire clk,
output reg [15:0] dout
);
reg [15:0] RAM[16383:0] /*verilator public*/;
always @(posedge clk) begin
if (wren) begin
if (maskwren[0]) RAM[addr][0+:4] <= din[0+:4];
if (maskwren[1]) RAM[addr][4+:4] <= din[4+:4];
if (maskwren[2]) RAM[addr][8+:4] <= din[8+:4];
if (maskwren[3]) RAM[addr][12+:4] <= din[12+:4];
end else begin
dout <= RAM[addr];
end
end
endmodule
| 6.622265 |
module SPRAM_16Kx16 (
input wire [13:0] addr,
input wire [15:0] din,
input wire [3:0] maskwren,
input wire wren,
input wire clk,
output wire [15:0] dout
);
SB_SPRAM256KA ram0 (
.ADDRESS(addr),
.DATAIN(din),
.MASKWREN(maskwren),
.CHIPSELECT(1'b1),
.CLOCK(clk),
.STANDBY(1'b0),
.SLEEP(1'b0),
.POWEROFF(1'b0),
.DATAOUT(dout)
);
endmodule
| 6.622265 |
module spram_16kx32 (
input clk,
input sel,
input [3:0] we,
input [15:0] addr,
input [31:0] wdat,
output [31:0] rdat
);
// instantiate the big RAMs
SB_SPRAM256KA mem_lo (
.ADDRESS(addr[15:2]),
.DATAIN(wdat[15:0]),
.MASKWREN({we[1], we[1], we[0], we[0]}),
.WREN(|we),
.CHIPSELECT(sel),
.CLOCK(clk),
.STANDBY(1'b0),
.SLEEP(1'b0),
.POWEROFF(1'b1),
.DATAOUT(rdat[15:0])
);
SB_SPRAM256KA mem_hi (
.ADDRESS(addr[15:2]),
.DATAIN(wdat[31:16]),
.MASKWREN({we[3], we[3], we[2], we[2]}),
.WREN(|we),
.CHIPSELECT(sel),
.CLOCK(clk),
.STANDBY(1'b0),
.SLEEP(1'b0),
.POWEROFF(1'b1),
.DATAOUT(rdat[31:16])
);
endmodule
| 6.525654 |
module spram_2048_40bit (
clk,
address,
wren,
data,
out
);
parameter AWIDTH = 11;
parameter NUM_WORDS = 2048;
parameter DWIDTH = 40;
input clk;
input [(AWIDTH-1):0] address;
input wren;
input [(DWIDTH-1):0] data;
output [(DWIDTH-1):0] out;
`ifndef hard_mem
reg [(DWIDTH-1):0] out;
reg [ DWIDTH-1:0] ram [NUM_WORDS-1:0];
always @(posedge clk) begin
if (wren) begin
ram[address] <= data;
end else begin
out <= ram[address];
end
end
`else
defparam u_single_port_ram.ADDR_WIDTH = AWIDTH; defparam u_single_port_ram.DATA_WIDTH = DWIDTH;
single_port_ram u_single_port_ram (
.addr(address),
.we (wren),
.data(data),
.out (out),
.clk (clk)
);
`endif
endmodule
| 7.613684 |
module spram_2048_60bit (
clk,
address,
wren,
data,
out
);
parameter AWIDTH = 11;
parameter NUM_WORDS = 2048;
parameter DWIDTH = 60;
input clk;
input [(AWIDTH-1):0] address;
input wren;
input [(DWIDTH-1):0] data;
output [(DWIDTH-1):0] out;
`ifndef hard_mem
reg [(DWIDTH-1):0] out;
reg [ DWIDTH-1:0] ram [NUM_WORDS-1:0];
always @(posedge clk) begin
if (wren) begin
ram[address] <= data;
end else begin
out <= ram[address];
end
end
`else
defparam u_single_port_ram.ADDR_WIDTH = AWIDTH; defparam u_single_port_ram.DATA_WIDTH = DWIDTH;
single_port_ram u_single_port_ram (
.addr(address),
.we (wren),
.data(data),
.out (out),
.clk (clk)
);
`endif
endmodule
| 7.228884 |
module spram_256k (
input clk,
input cs,
input [13:0] address,
input [15:0] write_data,
input [3:0] mask,
input write_en,
output reg [15:0] read_data
);
SB_SPRAM256KA ram (
.ADDRESS(address),
.DATAIN(write_data),
.MASKWREN(mask),
.WREN(write_en),
.CHIPSELECT(cs),
.CLOCK(clk),
.STANDBY(0),
.SLEEP(0),
.POWEROFF(1),
.DATAOUT(read_data)
);
endmodule
| 6.740246 |
module spram_4096_40bit (
clk,
address,
wren,
data,
out
);
parameter AWIDTH = 12;
parameter NUM_WORDS = 4096;
parameter DWIDTH = 40;
input clk;
input [(AWIDTH-1):0] address;
input wren;
input [(DWIDTH-1):0] data;
output [(DWIDTH-1):0] out;
`ifndef hard_mem
reg [(DWIDTH-1):0] out;
reg [ DWIDTH-1:0] ram [NUM_WORDS-1:0];
always @(posedge clk) begin
if (wren) begin
ram[address] <= data;
end else begin
out <= ram[address];
end
end
`else
defparam u_single_port_ram.ADDR_WIDTH = AWIDTH; defparam u_single_port_ram.DATA_WIDTH = DWIDTH;
single_port_ram u_single_port_ram (
.addr(address),
.we (wren),
.data(data),
.out (out),
.clk (clk)
);
`endif
endmodule
| 7.400334 |
module spram_4096_60bit (
clk,
address,
wren,
data,
out
);
parameter AWIDTH = 12;
parameter NUM_WORDS = 4096;
parameter DWIDTH = 60;
input clk;
input [(AWIDTH-1):0] address;
input wren;
input [(DWIDTH-1):0] data;
output [(DWIDTH-1):0] out;
`ifndef hard_mem
reg [(DWIDTH-1):0] out;
reg [ DWIDTH-1:0] ram [NUM_WORDS-1:0];
always @(posedge clk) begin
if (wren) begin
ram[address] <= data;
end else begin
out <= ram[address];
end
end
`else
defparam u_single_port_ram.ADDR_WIDTH = AWIDTH; defparam u_single_port_ram.DATA_WIDTH = DWIDTH;
single_port_ram u_single_port_ram (
.addr(address),
.we (wren),
.data(data),
.out (out),
.clk (clk)
);
`endif
endmodule
| 7.29278 |
module spram_4x1 (
input clk,
input [1:0] addr,
input d_in,
input wr_en,
output d_out
);
reg [3:0] mem;
assign d_out = mem[addr];
always @(posedge clk) begin
if (wr_en) begin
mem[addr] <= d_in;
end
end
endmodule
| 7.533622 |
module SPRAM16X16K_ASIC(
88 Q,
89 CLK,
90 CEN,
91 WEN,
92 A,
93 D);
95 parameter Bits = 16;
96 parameter Word_Depth = 16384;
97 parameter Add_Width = 14;
99 output [Bits-1:0] Q; // 数据输出
100 input CLK; // 输入时钟
101 input CEN; // SRAM 片选
102 input WEN; // 写使能
103 input [Add_Width-1:0] A; // SRAM 地址
104 input [Bits-1:0] D; // SRAM的数据输入
106 spram #( // 这部分是替换的内容，用于FPGA的综合与仿真
108 .ADDR_WIDTH(Add_Width),.DATA_WIDTH(Bits) )
111 U_RAM (
113 .clk (CLK )
114 ,.data (D)
115 ,.addr (A)
116 ,.we (!WEN && !CEN)
117 ,.q (Q)
118 );
121 endmodule
| 7.021789 |
module spram_b (
input clk,
input [(7-1):0] address_a,
input wren_a,
input [(`DATA_WIDTH-1):0] data_a,
output reg [(`DATA_WIDTH-1):0] out_a
);
`ifdef SIMULATION_MEMORY
reg [`DATA_WIDTH-1:0] ram[`ARRAY_DEPTH-1:0];
always @(posedge clk) begin
if (wren_a) begin
ram[address_a] <= data_a;
end else begin
out_a <= ram[address_a];
end
end
`else
single_port_ram u_single_port_ram (
.addr(address_a),
.we (wren_a),
.data(data_a),
.out (out_a),
.clk (clk)
);
`endif
endmodule
| 7.38617 |
module spram_behav #(
parameter MEM_WIDTH = 32, // memory (bus) width
parameter MEM_DEPTH = 4096 // memory depth
) (
input wire clk, // system clock
input wire cen, // chip enable (active low)
input wire wen, // write enable (active low)
input wire [clog2(MEM_DEPTH)-1:0] addr, // read/write address
input wire [ MEM_WIDTH-1:0] d, // data input (write op)
output reg [ MEM_WIDTH-1:0] q // data output (read op)
);
// -------------------
// Main memory array
// -------------------
reg [MEM_WIDTH-1:0] memory[MEM_DEPTH-1:0];
// ------------------
// Read path
// ------------------
always @(posedge clk) begin
if (cen == 1'b0 && wen == 1'b1) begin
q <= memory[addr];
end
end
// ------------------
// Write path
// ------------------
always @(posedge clk) begin
if (cen == 1'b0 && wen == 1'b0) begin
memory[addr] <= d;
end
end
// -------------------------------
// Initialization of memory array
// -------------------------------
integer j;
initial begin
for (j = 0; j < MEM_DEPTH; j = j + 1) begin
memory[j] = 1;
end
end
// --------------------------------
// Function: clog2
// Returns the ceil of the log2(x)
// --------------------------------
function integer clog2(input integer x);
integer i;
begin
clog2 = 0;
for (i = x - 1; i > 0; i = i >> 1) begin
clog2 = clog2 + 1;
end
end
endfunction
endmodule
| 6.669459 |
module spram_big (
clock,
reset_n,
value_out,
value_in
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`WIDTH-1:0] value_in;
output [`WIDTH-1:0] value_out;
wire [`WIDTH-1:0] value_out;
reg [`DEPTH-1:0] address_counter;
reg [`WIDTH-1:0] temp;
single_port_ram inst1 (
.we (clock),
.data(value_in),
.out (value_out),
.addr(address_counter)
);
always @(posedge clock) begin
if (reset_n == 1'b1) begin
address_counter <= 4'b00000000;
end else begin
address_counter <= address_counter + 1;
end
end
endmodule
| 6.721766 |
module spram #(
parameter ADDR_WIDTH = 6,
DATA_WIDTH = 8
) (
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] addr,
input we,
clk,
output [(DATA_WIDTH-1):0] q
);
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] addr_reg;
always @(posedge clk) begin
if (we) ram[addr] <= data;
addr_reg <= addr;
end
assign q = ram[addr_reg]; // RAMӦFPGA RAM첽
`ifdef BLANK_RAM // RAMʼΪȫ0Altera ֧
integer i;
initial begin
for (i = 0; i < 2 ** ADDR_WIDTH; i = i + 1) ram[i] = 0;
end
`endif
endmodule
| 8.813407 |
module spram_u (
input clk,
input [(7-1):0] address_a,
input wren_a,
input [(`uarraysize-1):0] data_a,
output reg [(`uarraysize-1):0] out_a
);
`ifdef SIMULATION_MEMORY
reg [`uarraysize-1:0] ram[`ARRAY_DEPTH-1:0];
always @(posedge clk) begin
if (wren_a) begin
ram[address_a] <= data_a;
end else begin
out_a <= ram[address_a];
end
end
`else
single_port_ram u_single_port_ram (
.addr(address_a),
.we (wren_a),
.data(data_a),
.out (out_a),
.clk (clk)
);
`endif
endmodule
| 6.704553 |
module spram_v (
input clk,
input [(7-1):0] address_a,
input wren_a,
input [(`varraysize-1):0] data_a,
output reg [(`varraysize-1):0] out_a
);
`ifdef SIMULATION_MEMORY
reg [`varraysize-1:0] ram[`ARRAY_DEPTH-1:0];
always @(posedge clk) begin
if (wren_a) begin
ram[address_a] <= data_a;
end else begin
out_a <= ram[address_a];
end
end
`else
single_port_ram u_single_port_ram (
.addr(address_a),
.we (wren_a),
.data(data_a),
.out (out_a),
.clk (clk)
);
`endif
endmodule
| 7.316866 |
module spram_wait ( /*AUTOARG*/
// Outputs
ao_data,
ao_valid,
// Inputs
clk,
rst,
ai_ce,
ai_we,
ai_oe,
ai_addr_w,
ai_addr_r,
ai_data
);
parameter dw = 8, aw = 8;
// ************************************************
input clk;
input rst;
//
input ai_ce;
input ai_we;
input ai_oe;
input [aw-1:0] ai_addr_w;
input [aw-1:0] ai_addr_r;
input [dw-1:0] ai_data;
output [dw-1:0] ao_data;
output ao_valid;
wire [aw-1:0] ai_addr_reg;
wire [dw-1:0] co_data;
wire fifo_adr_full, fifo_adr_empty;
reg [2:0] cnt;
reg [1:0] delay;
fifo_1depth #(
.dw(aw)
) fifo_adr (
.clk (clk),
.clr (rst),
// input side
.we (ai_ce),
.dati (ai_addr_r),
.full (fifo_adr_full),
// output side
.dato (ai_addr_reg),
.empty(fifo_adr_empty),
.re (ao_valid && !fifo_adr_empty)
);
wire [aw-1:0] co_addr = ao_valid ? ai_addr_r : ai_addr_reg;
wire [dw-1:0] ao_data = ao_valid ? co_data : {dw{1'bx}};
spram2 #(
.dw(dw),
.aw(aw)
) sram (
// Outputs
.ao_data (co_data[dw-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.ai_ce (ai_ce),
.ai_we (ai_we),
.ai_oe (ai_oe),
.ai_addr_w(ai_addr_w),
.ai_addr_r(co_addr[aw-1:0]),
.ai_data (ai_data[dw-1:0]),
.ao_valid (ao_valid)
);
wire ao_valid = (delay == 0);
always @(posedge clk)
if (rst) begin
cnt <= 0;
delay <= 0;
end else if (ai_ce && ai_oe && cnt != 7) begin
cnt <= cnt + 1;
delay <= 0;
end else if (ai_ce && ai_oe && cnt == 7)
if (delay != 3) delay <= delay + 1;
else begin
cnt <= 0;
delay <= 0;
end
else if (delay == 3) begin
cnt <= 0;
delay <= 0;
end else if (delay != 0) delay <= delay + 1;
endmodule
| 8.0725 |
module spram_bw_wrapper #(
parameter dw = 32,
aw = 32,
col_w = 8,
nb_w = dw / col_w,
mem_size_bytes = 32'h0000_0400
) (
input clk_i,
input rst_i,
input [ aw-1:0] adr_i,
input ce_i,
input [nb_w-1:0] we_i,
input [ dw-1:0] dat_i,
output [ dw-1:0] dat_o
);
// Important!
// This is the recommended coding style to describe read-first synchronized byte-write enable functionality for Virtex-6,
// Spartan-6 and newer device families. This coding style is not supported for older device families. In that case, please refer
// to the corresponding 2-bit and 4-bit write enable templates for device families before Virtex-6 and Spartan-6.
//
reg [dw-1:0] dout_r;
reg [dw-1:0] mem [0:mem_size_bytes/nb_w-1];
// The forllowing code is only necessary if you wish to initialize the RAM
// contents via an external file (use $readmemb for binary data)
// initial
// $readmemh("<data_file_name>", <mem>, <begin_adr_i>, <end_adr_i>);
always @(posedge clk_i) begin
dout_r <= mem[adr_i];
end
assign dat_o = dout_r;
generate
genvar i;
for (i = 0; i < nb_w; i = i + 1) begin : sram_bw
always @(posedge clk_i) begin
if (we_i[i]) mem[adr_i][(i+1)*col_w-1:i*col_w] <= dat_i[(i+1)*col_w-1:i*col_w];
end
end
endgenerate
endmodule
| 6.871618 |
module sprdma (
input wire clk_in, // 100MHz system clock signal
input wire rst_in, // reset signal
input wire [15:0] cpumc_a_in, // cpu address bus in (to snoop cpu writes of 0x4014)
input wire [ 7:0] cpumc_din_in, // cpumc din bus in (to snoop cpu writes of 0x4014)
input wire [ 7:0] cpumc_dout_in, // cpumc dout bus in (to receive sprdma read data)
input wire cpu_r_nw_in, // cpu write enable (to snoop cpu writes of 0x4014)
output wire active_out, // high when sprdma is active (de-assert cpu ready signal)
output reg [15:0] cpumc_a_out, // cpu address bus out (for dma cpu mem reads/writes)
output reg [ 7:0] cpumc_d_out, // cpu data bus out (for dma mem writes)
output reg cpumc_r_nw_out // cpu r_nw signal out (for dma mem writes)
);
// Symbolic state representations.
localparam [1:0] S_READY = 2'h0, S_ACTIVE = 2'h1, S_COOLDOWN = 2'h2;
reg [1:0] q_state, d_state; // current fsm state
reg [15:0] q_addr, d_addr; // current cpu address to be copied to sprite ram
reg [1:0] q_cnt, d_cnt; // counter to manage stages of dma copies
reg [7:0] q_data, d_data; // latch for data read from cpu mem
// Update FF state.
always @(posedge clk_in) begin
if (rst_in) begin
q_state <= S_READY;
q_addr <= 16'h0000;
q_cnt <= 2'h0;
q_data <= 8'h00;
end else begin
q_state <= d_state;
q_addr <= d_addr;
q_cnt <= d_cnt;
q_data <= d_data;
end
end
always @* begin
// Default regs to current state.
d_state = q_state;
d_addr = q_addr;
d_cnt = q_cnt;
d_data = q_data;
// Default to no memory action.
cpumc_a_out = 16'h00;
cpumc_d_out = 8'h00;
cpumc_r_nw_out = 1'b1;
if (q_state == S_READY) begin
// Detect write to 0x4014 to begin DMA.
if ((cpumc_a_in == 16'h4014) && !cpu_r_nw_in) begin
d_state = S_ACTIVE;
d_addr = {cpumc_din_in, 8'h00};
end
end else if (q_state == S_ACTIVE) begin
case (q_cnt)
2'h0: begin
cpumc_a_out = q_addr;
d_cnt = 2'h1;
end
2'h1: begin
cpumc_a_out = q_addr;
d_data = cpumc_dout_in;
d_cnt = 2'h2;
end
2'h2: begin
cpumc_a_out = 16'h2004;
cpumc_d_out = q_data;
cpumc_r_nw_out = 1'b0;
d_cnt = 2'h0;
if (q_addr[7:0] == 8'hff) d_state = S_COOLDOWN;
else d_addr = q_addr + 16'h0001;
end
endcase
end else if (q_state == S_COOLDOWN) begin
if (cpu_r_nw_in) d_state = S_READY;
end
end
assign active_out = (q_state == S_ACTIVE);
endmodule
| 6.631217 |
module spread_spectrum (
code_out,
gps_data,
rst,
ss_data
);
input code_out;
input gps_data;
//input gps_clk;
input rst;
//reg code_out_reg,gps_data_reg,ss_en;
output wire ss_data;
assign ss_data = (rst) ? code_out ^ gps_data : 0;
// assign dpsk = dpsk_buf ^ ss_data;
//assign ss_data = (ss_en)? code_out_reg^gps_data_reg:0;//扩频操作
endmodule
| 6.644002 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we) begin
ram[addr] <= data;
end else begin
out <= ram[addr];
end
end
endmodule
| 8.023817 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module addersub (
opB,
opA,
op,
result_slt,
result
);
//parameter WIDTH=32;
//`DEFINE WIDTH 32
input [31:0] opA;
input [31:0] opB;
//input carry_in;
input [2:0] op;
output result_slt;
output [31:0] result;
wire [32:0] sum;
wire addsub;
wire useless;
assign useless = op[1] & op[2];
assign addsub = op[0];
wire not_addsub;
assign not_addsub = ~addsub;
assign result = sum[31:0];
assign result_slt = sum[32];
dummy_add_sub adder32bit (
opA,
opB,
not_addsub,
sum
);
// This is an LPM from Altera, replacing with a dummy one for now
/*
lpm_add_sub adder_inst(
.dataa({signext&opA[WIDTH-1],opA}),
.datab({signext&opB[WIDTH-1],opB}),
.cin(~addsub),
.add_sub(addsub),
.result(sum)
// synopsys translate_off
,
.cout (),
.clken (),
.clock (),
.overflow (),
.aclr ()
// synopsys translate_on
);
//defparam
// adder_inst.lpm_width=WIDTH+1,
// adder_inst.lpm_representation="SIGNED";
*/
endmodule
| 7.127372 |
module reg_file (
clk,
resetn,
c_writedatain,
c_reg,
b_reg,
a_reg,
c_we,
b_en,
a_en,
b_readdataout,
a_readdataout
);
//parameter WIDTH=32;
//parameter NUMREGS=32;
//parameter LOG2NUMREGS=5;
input clk;
input resetn;
input a_en;
input b_en;
input [31:0] c_writedatain;
input c_we;
input [31:0] a_reg;
input [31:0] b_reg;
input [31:0] c_reg;
output [31:0] a_readdataout;
output [31:0] b_readdataout;
//reg [31:0] a_readdataout;
//reg [31:0] b_readdataout;
wire [31:0] a_readdataout_temp;
wire [31:0] b_readdataout_temp;
assign b_readdataout = b_readdataout_temp;
assign a_readdataout = a_readdataout_temp;
wire wren1;
assign wren1 = (c_we & (|c_reg));
defparam regfile1_replace.ADDR_WIDTH = 5; defparam regfile1_replace.DATA_WIDTH = 32;
single_port_ram regfile1_replace (
.clk (clk),
.we (wren1),
.data(c_writedatain),
.out (a_readdataout_temp),
.addr(c_reg[4:0])
);
//Reg file duplicated to avoid contention
//between 2 read and 1 write
//MORE MEMORY
defparam regfile2_replace.ADDR_WIDTH = 5; defparam regfile2_replace.DATA_WIDTH = 32;
single_port_ram regfile2_replace (
.clk (clk),
.we (wren1),
.data(c_writedatain),
.out (b_readdataout_temp),
.addr(c_reg[4:0])
);
//Odin II does not recognize that address
//registers are being used to read and
//write data, so they are assigned to an
//unused wire which is later dropped by the
//optimizer.
wire useless_inputs;
//`a_reg` and `b_reg` were not used correctly in last version
//of `spree.v` according to the comment above this module.
//Investigate whether the comment or the code is wrong
assign useless_inputs = resetn & b_en & a_en & (|a_reg) & (|b_reg);
endmodule
| 7.294051 |
module mul (
clk,
resetn,
sa,
dst,
opB,
opA,
op,
start,
stalled,
shift_result,
lo,
hi
);
input clk;
input resetn;
input start;
output stalled;
input [4:0] dst;
input [31:0] opA;
input [31:0] opB;
input [4:0] sa;
input [2:0] op;
output [31:0] shift_result;
output [31:0] hi;
output [31:0] lo;
/********* Control Signals *********/
wire is_signed;
wire dir;
wire is_mul;
assign is_mul = op[2]; // selects between opB and the computed shift amount
assign is_signed = op[1];
assign dir = op[0]; // selects between 2^sa and 2^(32-sa) for right shift
/********* Circuit Body *********/
wire dum;
wire dum2;
wire dum3;
wire [32:0] opB_mux_out;
wire [4:0] left_sa; // Amount of left shift required for both left/right
reg [32:0] decoded_sa;
wire [31:0] result;
//assign opB_mux_out= (is_mul) ? {is_signed&opB[31],opB} : decoded_sa;
assign opB_mux_out = opB;
dummy_mult fake_mult_one (
opA,
opB_mux_out,
clk,
resetn,
result
);
assign hi = result[15:8];
assign lo = result[7:0];
// Cannot support this now
/*
lpm_mult lpm_mult_component (
.dataa ({is_signed&opA[31],opA}),
.datab (opB_mux_out),
.sum(),
.clock(clk),
.clken(),
.aclr(~resetn),
.result ({dum2,dum,hi,lo}));
defparam
lpm_mult_component.lpm_32a = 32+1,
lpm_mult_component.lpm_32b = 32+1,
lpm_mult_component.lpm_32p = 2*32+2,
lpm_mult_component.lpm_32s = 1,
lpm_mult_component.lpm_pipeline = 1,
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=6";
*/
assign shift_result = (dir & |sa) ? hi : lo;
// 1 cycle stall state machine
wire or_dst;
wire start_and_ismul;
wire request;
assign or_dst = |dst;
assign start_and_ismul = start & is_mul;
assign request = (or_dst & start & ~is_mul) | (start_and_ismul);
onecyclestall staller (
request,
clk,
resetn,
stalled
);
endmodule
| 7.151423 |
module data_mem (
clk,
resetn,
stalled,
d_writedata,
d_address,
op,
d_loadresult
);
input clk;
input resetn;
output stalled;
input [`D_ADDRESSWIDTH-1:0] d_address;
input [3:0] op;
input [31:0] d_writedata;
output [`DM_DATAWIDTH-1:0] d_loadresult;
wire [`DM_BYTEENAWIDTH-1:0] d_byteena;
wire [`DM_DATAWIDTH-1:0] d_readdatain;
wire [`DM_DATAWIDTH-1:0] d_writedatamem;
wire d_write;
wire [1:0] d_address_latched;
assign d_write = op[3];
wire [1:0] d_small_adr;
assign d_small_adr = d_address[1:0];
wire one;
assign one = 1'b1;
wire [1:0] d_adr_one_zero;
assign d_adr_one_zero = d_address[1:0];
wire [1:0] opsize;
assign opsize = op[1:0];
wire opext;
assign opext = op[2];
store_data_translator sdtrans_inst (
.write_data(d_writedata),
.d_address(d_adr_one_zero),
.store_size(op[1:0]),
.d_byteena(d_byteena),
.d_writedataout(d_writedatamem)
);
load_data_translator ldtrans_inst (
.d_readdatain(d_readdatain),
.d_loadresult(d_loadresult)
);
wire dnot_address;
assign dnot_address = ~d_address[31];
wire will_be_wren1;
assign will_be_wren1 = d_write & (dnot_address);
wire [9:0] memaddr_wrd;
assign memaddr_wrd = d_address[`DM_ADDRESSWIDTH:2];
defparam dmem_replace.ADDR_WIDTH = 10; defparam dmem_replace.DATA_WIDTH = `DM_DATAWIDTH;
single_port_ram dmem_replace (
.clk (clk),
.we (will_be_wren1),
.data(d_writedatamem),
.out (d_readdatain),
.addr(memaddr_wrd)
);
// 1 cycle stall state machine
wire en_and_not_d_write;
assign en_and_not_d_write = ~d_write;
onecyclestall staller (
en_and_not_d_write,
clk,
resetn,
stalled
);
wire useless_inputs;
assign useless_inputs = |d_address;
endmodule
| 7.214114 |
module store_data_translator (
write_data, // data in least significant position
d_address,
store_size,
d_byteena,
d_writedataout // shifted data to coincide with address
);
//parameter WIDTH=32;
input [31:0] write_data;
input [1:0] d_address;
input [1:0] store_size;
output [3:0] d_byteena;
output [31:0] d_writedataout;
reg [ 3:0] d_byteena;
reg [31:0] d_writedataout;
always @(write_data or d_address or store_size) begin
case (store_size)
2'b11:
case (d_address[1:0])
2'b00: begin
d_byteena = 4'b1000;
d_writedataout = {write_data[7:0], 24'b0};
end
2'b01: begin
d_byteena = 4'b0100;
d_writedataout = {8'b0, write_data[7:0], 16'b0};
end
2'b10: begin
d_byteena = 4'b0010;
d_writedataout = {16'b0, write_data[7:0], 8'b0};
end
default: begin
d_byteena = 4'b0001;
d_writedataout = {24'b0, write_data[7:0]};
end
endcase
2'b01:
case (d_address[1])
1'b0: begin
d_byteena = 4'b1100;
d_writedataout = {write_data[15:0], 16'b0};
end
default: begin
d_byteena = 4'b0011;
d_writedataout = {16'b0, write_data[15:0]};
end
endcase
default: begin
d_byteena = 4'b1111;
d_writedataout = write_data;
end
endcase
end
endmodule
| 8.280191 |
module load_data_translator (
d_readdatain,
d_loadresult
);
//parameter WIDTH=32;
input [31:0] d_readdatain;
output [31:0] d_loadresult;
wire d_adr_one;
assign d_adr_one = d_address[1];
reg [31:0] d_loadresult;
reg sign;
wire [1:0] d_address;
assign d_address[1:0] = d_readdatain[25:24];
//assume always full-word-access
always @(d_readdatain or d_address) begin
d_loadresult[31:0] = d_readdatain[31:0];
end
/*
Odin II REFUSES TO ACKNOWLEDGE THAT SIGN EXTENDING IS NOT A COMBINATIONAL LOOP
always @(d_readdatain or d_address or load_size or load_sign_ext)
begin
case (load_size)
2'b11:
begin
case (d_address)
2'b00:
begin
d_loadresult[7:0]=d_readdatain[31:24];
sign = d_readdatain[31];
end
2'b01:
begin
d_loadresult[7:0]=d_readdatain[23:16];
sign = d_readdatain[23];
end
2'b10:
begin
d_loadresult[7:0]=d_readdatain[15:8];
sign = d_readdatain[15];
end
default:
begin
d_loadresult[7:0]=d_readdatain[7:0];
sign = d_readdatain[7];
end
endcase
// peter milankov note: do this by hand
// odin II does not support multiple concatenation
//d_loadresult[31:8]={24{load_sign_ext&d_loadresult[7]}};
d_loadresult[31]= load_sign_ext&sign;
d_loadresult[30]= load_sign_ext&sign;
d_loadresult[29]= load_sign_ext&sign;
d_loadresult[28]= load_sign_ext&sign;
d_loadresult[27]= load_sign_ext&sign;
d_loadresult[26]= load_sign_ext&sign;
d_loadresult[25]= load_sign_ext&sign;
d_loadresult[24]= load_sign_ext&sign;
d_loadresult[23]= load_sign_ext&sign;
d_loadresult[22]= load_sign_ext&sign;
d_loadresult[21]= load_sign_ext&sign;
d_loadresult[20]= load_sign_ext&sign;
d_loadresult[19]= load_sign_ext&sign;
d_loadresult[18]= load_sign_ext&sign;
d_loadresult[17]= load_sign_ext&sign;
d_loadresult[16]= load_sign_ext&sign;
d_loadresult[15]= load_sign_ext&sign;
d_loadresult[14]= load_sign_ext&sign;
d_loadresult[13]= load_sign_ext&sign;
d_loadresult[12]= load_sign_ext&sign;
d_loadresult[11]= load_sign_ext&sign;
d_loadresult[10]= load_sign_ext&sign;
d_loadresult[9]= load_sign_ext&sign;
d_loadresult[8]= load_sign_ext&sign;
end
2'b01:
begin
case (d_adr_one)
1'b0:
begin
d_loadresult[15:0]=d_readdatain[31:16];
sign = d_readdatain[31];
end
default:
begin
d_loadresult[15:0]=d_readdatain[15:0];
sign = d_readdatain[15];
end
endcase
// peter milankov note sign extend is concat, do by hand
//d_loadresult[31:16]={16{load_sign_ext&d_loadresult[15]}};
d_loadresult[31]= load_sign_ext&sign;
d_loadresult[30]= load_sign_ext&sign;
d_loadresult[29]= load_sign_ext&sign;
d_loadresult[28]= load_sign_ext&sign;
d_loadresult[27]= load_sign_ext&sign;
d_loadresult[26]= load_sign_ext&sign;
d_loadresult[25]= load_sign_ext&sign;
d_loadresult[24]= load_sign_ext&sign;
d_loadresult[23]= load_sign_ext&sign;
d_loadresult[22]= load_sign_ext&sign;
d_loadresult[21]= load_sign_ext&sign;
d_loadresult[20]= load_sign_ext&sign;
d_loadresult[19]= load_sign_ext&sign;
d_loadresult[18]= load_sign_ext&sign;
d_loadresult[17]= load_sign_ext&sign;
d_loadresult[16]= load_sign_ext&sign;
end
default:
d_loadresult[31:0]=d_readdatain[31:0];
endcase
end
*/
endmodule
| 9.105161 |
module logic_unit (
opB,
opA,
op,
result
);
//parameter WIDTH=32;
input [31:0] opA;
input [31:0] opB;
input [1:0] op;
output [31:0] result;
reg [31:0] logic_result;
always @(opA or opB or op)
case (op)
2'b00: logic_result = opA & opB;
2'b01: logic_result = opA | opB;
2'b10: logic_result = opA ^ opB;
2'b11: logic_result = ~(opA | opB);
endcase
assign result = logic_result;
endmodule
| 7.608724 |
module pcadder (
offset,
pc,
result
);
//parameter PC_WIDTH=32;
input [31:0] pc;
input [31:0] offset;
output [31:0] result;
wire dum;
wire useless_inputs;
assign useless_inputs = |offset;
assign {dum, result} = pc + {offset[31:0], 2'b0};
endmodule
| 6.899046 |
module signext16 (
in,
out
);
input [15:0] in;
output [31:0] out;
assign out[30] = in[15];
assign out[31] = in[15];
assign out[29] = in[15];
assign out[28] = in[15];
assign out[27] = in[15];
assign out[26] = in[15];
assign out[25] = in[15];
assign out[24] = in[15];
assign out[23] = in[15];
assign out[22] = in[15];
assign out[21] = in[15];
assign out[20] = in[15];
assign out[19] = in[15];
assign out[18] = in[15];
assign out[17] = in[15];
assign out[16] = in[15];
assign out[15:0] = in[15:0];
endmodule
| 7.934159 |
module lo_reg (
clk,
resetn,
d,
en,
q
);
//parameter WIDTH=32;
input clk;
input resetn;
input en;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk) begin
if (resetn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 8.102353 |
module hi_reg (
clk,
resetn,
d,
en,
q
);
//parameter WIDTH=32;
input clk;
input resetn;
input en;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk ) //used to be asynchronous reset
begin
if (resetn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 6.976139 |
module register (
d,
clk,
resetn,
en,
q
);
//parameter WIDTH=32;
input clk;
input resetn;
input en;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk) begin
if (resetn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 6.542519 |
module register_1bit (
d,
clk,
resetn,
en,
q
);
//parameter WIDTH=32;
input clk;
input resetn;
input en;
input d;
output q;
reg q;
always @(posedge clk) begin
if (resetn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 6.5297 |
module register_sync (
d,
clk,
resetn,
en,
q
);
//parameter WIDTH=32;
input clk;
input resetn;
input en;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 7.04221 |
module pipereg (
clk,
resetn,
d,
squashn,
en,
q
);
//parameter WIDTH=32;
//`define WIDTH 32
input clk;
input resetn;
input en;
input squashn;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 7.345741 |
module pipereg_w32 (
clk,
resetn,
d,
squashn,
en,
q
);
//parameter WIDTH=32;
//`define WIDTH 32
input clk;
input resetn;
input en;
input squashn;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 7.413603 |
module pipereg_w26 (
clk,
resetn,
d,
squashn,
en,
q
);
//parameter WIDTH=32;
//`define WIDTH 32
input clk;
input resetn;
input en;
input squashn;
input [25:0] d;
output [25:0] q;
reg [25:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 7.064198 |
module pipereg_w6 (
clk,
resetn,
d,
squashn,
en,
q
);
//parameter WIDTH=32;
//`define WIDTH 32
input clk;
input resetn;
input en;
input squashn;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) begin
q[5:0] <= d;
q[31:6] <= 0;
end
end
endmodule
| 7.166746 |
module pipereg_w5 (
clk,
resetn,
d,
squashn,
en,
q
);
//parameter WIDTH=32;
//`define WIDTH 32
input clk;
input resetn;
input en;
input squashn;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) begin
q[4:0] <= d;
q[31:5] <= 0;
end
end
endmodule
| 7.56833 |
module pipereg_w1 (
clk,
resetn,
d,
squashn,
en,
q
);
//parameter WIDTH=32;
//`define WIDTH 32
input clk;
input resetn;
input en;
input squashn;
input d;
output q;
reg q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 7.073223 |
module pipereg_full (
d,
clk,
resetn,
squashn,
en,
q
);
//parameter WIDTH=32;
input clk;
input resetn;
input en;
input squashn;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
reg squash_save;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || (squashn == 0 && en == 1) || (squash_save & en)) q <= 0;
else if (en == 1) q <= d;
end
always @(posedge clk) begin
if (resetn == 1 && squashn == 0 && en == 0) squash_save <= 1;
else squash_save <= 0;
end
endmodule
| 7.204243 |
module zeroer (
d,
en,
q
);
//parameter WIDTH=32;
//`define WIDTH 32
input en;
input [4:0] d;
output [31:0] q;
assign q[4:0] = (en) ? d : 0;
assign q[31:05] = 0;
endmodule
| 8.282203 |
module nop (
d,
q
);
//parameter WIDTH=32;
//`define WIDTH 32
input [31:0] d;
output [31:0] q;
assign q = d;
endmodule
| 7.480252 |
module branch_detector (
opcode,
func,
is_branch
);
input [5:0] opcode;
input [5:0] func;
output is_branch;
wire is_special;
assign is_special = !(|opcode);
assign is_branch = ((!(|opcode[5:3])) && !is_special) || ((is_special) && (func[5:3] == 3'b001));
endmodule
| 7.697954 |
module branchresolve (
rt,
rs,
en,
eqz,
gez,
gtz,
lez,
ltz,
ne,
eq
);
//parameter WIDTH=32;
input en;
input [31:0] rs;
input [31:0] rt;
output eq;
output ne;
output ltz;
output lez;
output gtz;
output gez;
output eqz;
assign eq = (en) & (rs == rt);
assign ne = (en) & ~eq;
assign eqz = (en) & ~(|rs);
assign ltz = (en) & rs[31];
assign lez = (en) & rs[31] | eqz;
assign gtz = (en) & (~rs[31]) & ~eqz;
assign gez = (en) & (~rs[31]);
endmodule
| 9.028008 |
module SPREQ_FIFO (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull
);
input aclr;
input [39:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [39:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [39:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [39:0] q = sub_wire0[39:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
dcfifo dcfifo_component (
.aclr(aclr),
.data(data),
.rdclk(rdclk),
.rdreq(rdreq),
.wrclk(wrclk),
.wrreq(wrreq),
.q(sub_wire0),
.rdempty(sub_wire1),
.wrfull(sub_wire2),
.eccstatus(),
.rdfull(),
.rdusedw(),
.wrempty(),
.wrusedw()
);
defparam dcfifo_component.intended_device_family = "Cyclone 10 LP",
dcfifo_component.lpm_numwords = 256, dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = 40,
dcfifo_component.lpm_widthu = 8, dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 11, dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF", dcfifo_component.wrsync_delaypipe = 11;
endmodule
| 6.589889 |
module sprinkler_decoder_sprinker_decoder_v_tb ();
// Inputs
reg E;
reg A;
reg B;
reg C;
// Output
wire d0;
wire d1;
wire d2;
wire d3;
wire d4;
wire d5;
wire d6;
wire d7;
// Bidirs
// Instantiate the UUT
sprinkler_decoder UUT (
.d0(d0),
.d1(d1),
.d2(d2),
.d3(d3),
.d4(d4),
.d5(d5),
.d6(d6),
.d7(d7),
.E (E),
.A (A),
.B (B),
.C (C)
);
// Initialize Inputs
initial begin
E = 1;
A = 0;
B = 0;
C = 0;
#100; // Wait for 100ns
$display("TC11 ");
if (d0 != 1'b1) $display("Result is wrong");
A = 0;
B = 0;
C = 1;
#100;
$display("TC12 ");
if (d1 != 1'b1) $display("Result is wrong");
A = 0;
B = 1;
C = 0;
#100;
$display("TC13 ");
if (d2 != 1'b1) $display("Result is wrong");
A = 0;
B = 1;
C = 1;
#100;
$display("TC14 ");
if (d3 != 1'b1) $display("Result is wrong");
A = 1;
B = 0;
C = 0;
#100;
$display("TC15 ");
if (d4 != 1'b1) $display("Result is wrong");
A = 1;
B = 0;
C = 1;
#100;
$display("TC16 ");
if (d5 != 1'b1) $display("Result is wrong");
A = 1;
B = 1;
C = 0;
#100;
$display("TC17 ");
if (d6 != 1'b1) $display("Result is wrong");
A = 1;
B = 1;
C = 1;
#100;
$display("TC18 ");
if (d7 != 1'b1) $display("Result is wrong");
// Test cases
E = 1;
A = 0;
B = 0;
C = 0;
end
endmodule
| 7.037174 |
module sprinkler_decoder (
//I/o ports
input wire E,
input wire A,
input wire B,
input wire C,
output wire d0,
output wire d1,
output wire d2,
output wire d3,
output wire d4,
output wire d5,
output wire d6,
output wire d7
);
// Using the and4 module to set all outputs
and4 c1 (
E,
~A,
~B,
~C,
d0
); // E = 0 is enable
and4 c2 (
E,
~A,
~B,
C,
d1
);
and4 c3 (
E,
~A,
B,
~C,
d2
);
and4 c4 (
E,
~A,
B,
C,
d3
);
and4 c5 (
E,
A,
~B,
~C,
d4
);
and4 c6 (
E,
A,
~B,
C,
d5
);
and4 c7 (
E,
A,
B,
~C,
d6
);
and4 c8 (
E,
A,
B,
C,
d7
);
// code
endmodule
| 7.037174 |
module sprite (
input wire clk,
input wire [10:0] hc, // posicion X de pantalla
input wire [10:0] vc, // posicion Y de pantalla
input wire [10:0] posx, // posicion X inicial del sprite
input wire [10:0] posy, // posicion Y inicial del sprite
input wire [7:0] rin, // color de pantalla
input wire [7:0] gin, // proveniente del
input wire [7:0] bin, // modulo anterior (el fondo, por ejemplo)
output reg [7:0] rout, // color de pantalla
output reg [7:0] gout, // actualizado
output reg [7:0] bout // segun haya que pintar o no el sprite
);
localparam TRANSPARENTE = 24'h00FF00, // en nuestro sprite el verde es "transparente"
TAM = 11'd16; // tamano en pixeles tanto horizontal como vertical, del sprite
reg [23:0] spr[0:255]; // memoria que guarda el sprite (16x16 posiciones de 24 bits cada posicion)
initial begin
$readmemh("datos_sprite.hex",
spr); // inicializamos esa memoria desde un fichero con datos hexadecimales
end
wire [3:0] spr_x = hc - posx; // posicion X dentro de la matriz del sprite, en funcion de la posicion X actual de pantalla y posicion inicial X del sprite
wire [3:0] spr_y = vc - posy; // posicion Y dentro de la matriz del sprite, en funcion de la posicion Y actual de pantalla y posicion inicial Y del sprite
reg [23:0] color; // color del pixel actual del sprite
always @(posedge clk) begin
color <= spr[{
spr_y, spr_x
}]; // leemos el color del pixel y lo guardamos (la posicion del pixel podria ser completamente erronea aqui)
if (hc >= posx && hc < (posx + TAM) && vc >= posy && vc < (posy + TAM) && color != TRANSPARENTE) begin // si la posicion actual de pantalla esta dentro de los margenes del sprite, y el color leido del sprite no es el transparente....
rout <= color[23:16]; // en ese caso, el color de salida
gout <= color[15:8]; // es el color del pixel del sprite
bout <= color[7:0]; // que hemos leido
end else begin
rout <= rin; // si no toca pintar el sprite
gout <= gin; // o bien el color que hemos leido es el transparente
bout <= bin; // entonces pasamos a la salida el color que nos dieron a la entrada
end
end
endmodule
| 6.944101 |
module sprite4 (
input clock,
input resetn,
input move,
input jump,
input [19:0] ground_under_sprite,
input [6:0] ground_under_feet,
input [46:0] jumped_ground,
input rightmost_ground,
input erase,
output [8:0] x,
output [7:0] y,
output [2:0] colour,
output kill,
output [7:0] y0_out,
output [11:0] score
);
wire [7:0] y0;
wire [6:0] t_out;
wire [2:0] current_state;
assign y0_out = y0;
// control
sprite_control c0 (
.clock(clock),
.resetn(resetn),
.jump(jump),
.move(move),
.ground_under_feet(ground_under_feet),
.jumped_ground(jumped_ground),
.rightmost_ground(rightmost_ground),
.y0(y0),
.kill(kill),
.t_out(t_out),
.current_state_out(current_state),
.score(score)
);
wire [7:0] y_add;
// datapath
sprite_datapath d0 (
.clock(clock),
.resetn(resetn),
.erase(erase),
.move(move),
.ground_under_sprite(ground_under_sprite),
.y0(y0),
.x(x),
.y(y),
.colour(colour),
.y_add_out(y_add)
);
endmodule
| 8.163 |
module sprite_control (
input clock,
input resetn,
input jump,
input move,
input [6:0] ground_under_feet,
input [46:0] jumped_ground,
input rightmost_ground,
output reg [7:0] y0,
output kill,
output [6:0] t_out,
output [2:0] current_state_out,
output reg [11:0] score
);
reg [2:0] current_state, next_state;
localparam RUNNING = 3'd0, JUMPING = 3'd1, FALLING = 3'd2;
reg [6:0] t;
always @(posedge clock) begin
if (resetn == 1'b0) begin
t <= 1'b0;
end else if (next_state != current_state) begin
t <= 1'b0;
end else if (move) begin
t <= t + 1'b1;
end
end
assign current_state_out = current_state;
assign t_out = t;
// signal to stop jumping
wire stop_jumping = t >= 25 ? 1'b1 : 1'b0;
// signal to start falling
wire fall = &ground_under_feet ? 1'b1 : 1'b0;
// signal to stop falling
wire stop_falling = (y0 == `y_resting && ~&(ground_under_feet)) ? 1'b1 : 1'b0;
// signal that front collides with ground
assign kill = (y0 > `y_resting && rightmost_ground == 0) || y0 > 9'd200 ? 1'b1 : 1'b0;
always @(*) begin : state_table
case (current_state)
RUNNING:
if (jump) begin
next_state = JUMPING;
end else if (fall) begin
next_state = FALLING;
end else next_state = RUNNING;
JUMPING: next_state = stop_jumping ? FALLING : JUMPING;
FALLING: next_state = stop_falling ? RUNNING : FALLING;
default: next_state = RUNNING;
endcase
end
localparam
ZERO = 3'd0,
ONE = 3'd1,
TWO = 3'd2,
THREE = 3'd3,
FOUR = 3'd4,
FIVE = 3'd5,
SIX = 3'd6;
wire [2:0] dy_list[0:25];
assign dy_list[0] = ZERO;
assign dy_list[1] = ZERO;
assign dy_list[2] = ONE;
assign dy_list[3] = ONE;
assign dy_list[4] = ONE;
assign dy_list[5] = ONE;
assign dy_list[6] = TWO;
assign dy_list[7] = TWO;
assign dy_list[8] = TWO;
assign dy_list[9] = TWO;
assign dy_list[10] = TWO;
assign dy_list[11] = THREE;
assign dy_list[12] = THREE;
assign dy_list[13] = THREE;
assign dy_list[14] = FOUR;
assign dy_list[15] = FOUR;
assign dy_list[16] = FOUR;
assign dy_list[17] = FOUR;
assign dy_list[18] = FOUR;
assign dy_list[19] = FIVE;
assign dy_list[20] = FIVE;
assign dy_list[21] = FIVE;
assign dy_list[22] = FIVE;
assign dy_list[23] = SIX;
assign dy_list[24] = SIX;
assign dy_list[25] = SIX;
reg [2:0] dy;
always @(*) begin
case (current_state)
RUNNING: dy = ZERO;
JUMPING: dy = dy_list[25-t];
FALLING:
if (t <= 24) begin
dy = dy_list[t];
end else dy = SIX;
default: dy = ZERO;
endcase
end
always @(posedge clock) begin
if (resetn == 1'b0) y0 <= `y_resting;
else if (move) begin
if (next_state == RUNNING) y0 <= `y_resting;
if (next_state == FALLING) y0 <= y0 + dy;
else if (next_state == JUMPING) y0 <= y0 - dy;
end
end
// current_state registers
always @(posedge clock) begin : state_FFs
if (!resetn) current_state <= RUNNING;
else current_state <= next_state;
end // state_FFS
// scoring
reg jumped_lava;
always @(posedge clock) begin
if (resetn == 1'b0) begin
score <= 1'b0;
jumped_lava <= 1'b0;
end else if ((current_state == JUMPING || current_state == FALLING) && (| ground_under_feet)) begin
jumped_lava <= 1'b1;
end else if (current_state == FALLING && next_state == RUNNING && jumped_lava) begin
score <= score + 1'b1;
jumped_lava <= 1'b0;
end
end
endmodule
| 9.748011 |
module SpriteAnimation (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
LEDR,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B // VGA Blue[9:0]
);
input CLOCK_50; // 50 MHz
input [9:0] SW;
input [3:0] KEY;
output [9:0] LEDR;
// Declare your inputs and outputs here
// Do not change the following outputs
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK_N; // VGA BLANK
output VGA_SYNC_N; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
wire resetn;
assign resetn = KEY[0];
// Create the colour, x, y and writeEn wires that are inputs to the controller.
wire [2:0] colour;
wire [7:0] x;
wire [6:0] y;
wire writeEn;
wire enable, ld_x, ld_y, ld_c;
wire [15:0] out;
wire [ 9:0] addr_read;
// Create an Instance of a VGA controller - there can be only one!
// Define the number of colours as well as the initial background
// image file (.MIF) for the controller.
vga_adapter VGA (
.resetn(resetn),
.clock(CLOCK_50),
.colour(colour),
.x(x),
.y(y),
.plot(writeEn),
/* Signals for the DAC to drive the monitor. */
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK)
);
defparam VGA.RESOLUTION = "160x120"; defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1; defparam VGA.BACKGROUND_IMAGE = "black.mif";
// Put your code here. Your code should produce signals x,y,colour and writeEn/plot
// for the VGA controller, in addition to any other functionality your design may require.
// assign x_coord = SW[7:0];
topramsprite snow (
CLOCK_50,
addr_read,
out
);
drawsnowman d0 (
CLOCK_50,
addr_read
);
translateout t0 (
CLOCK_50,
out,
x_coord,
7'b0010111,
x,
y,
colour,
writeEn_out
);
assign writeEn = ~KEY[2];
// slowclk c1(CLOCK_50, ~resetn, 1'b1, 2'b01, onesecond);
// wire [27:0] q;
// ratedivider(~KEY[1], {2'b00, 26'd49999999}, CLOCK_50, ~resetn, q);
// assign LEDR[1] = ~onesecond;
// assign LEDR[0] = onesecond;
//
// reg a1;
// assign LEDR[2] = a1;
//
// always @(posedge onesecond) begin
// if (a1) begin
// a1 <= 1'b0;
// end
// else begin
// a1<= 1'b1;
// end
// end
// reg [7:0] a_reg;
// wire [7:0] a = a_reg;
//
// always @(onesecond) begin
// if (a == 8'b00010111) begin
// a_reg <= 8'b00101110;
// end
// else begin
// a_reg <= 8'b00010111;
// end
// end
//assign LEDR[0] = onesecond;
// Try shifting the snowman left automatically
//
wire [7:0] x_coord;
wire [6:0] y_coord;
wire onesecond;
slowclk c1 (
CLOCK_50,
~KEY[0],
1'b1,
2'b01,
onesecond
);
coordshifter cs0 (
onesecond,
resetn,
x_coord,
y_coord
);
assign LEDR[0] = x_coord[0];
assign LEDR[1] = x_coord[1];
assign LEDR[2] = x_coord[2];
assign LEDR[3] = x_coord[3];
assign LEDR[4] = x_coord[4];
endmodule
| 9.179598 |
module translateout (
clock,
out,
coord_x,
coord_y,
x,
y,
colour,
writeEn
);
input clock;
input [15:0] out;
input [7:0] coord_x;
input [6:0] coord_y;
output reg [7:0] x;
output reg [6:0] y;
output reg writeEn;
output reg [2:0] colour;
wire [5:0] x_rel;
wire [5:0] y_rel;
wire [2:0] col;
wire wren;
assign x_rel = out[15:10];
assign y_rel = out[9:4];
assign col = out[3:1];
assign wren = out[0];
always @(posedge clock) begin
x <= coord_x + x_rel;
y <= coord_y + y_rel;
colour <= col;
writeEn <= wren;
end
endmodule
| 6.708627 |
module SpriteCache #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8,
parameter DATA_DEPTH = 256
) (
input [DATA_WIDTH-1:0] data_in,
input [ADDR_WIDTH-1:0] addr,
input clk,
input we,
output [DATA_WIDTH-1:0] data_out
);
reg [DATA_WIDTH-1:0] data[DATA_DEPTH-1:0];
assign data_out = data_read;
always @(posedge clk) begin
if (we) data[addr] <= data_in;
else data_read <= data[addr];
end
endmodule
| 8.147792 |
module SpriteMem (
MemSel,
Address,
DataOut,
Clock,
Resetn,
Width,
Height,
AnimSteps
);
input Clock, Resetn;
input [2:0] MemSel; // enable for 'external' memory (2:0 allows for 8 memories)
input [11:0] Address; // really wide memory address line - for 32*32 sprites with 4 animation steps
output [8:0] DataOut; // color received from memory
output [4:0] Width, Height;
output [2:0] AnimSteps;
//
// Multiplexers for Sprite Width, Height and Animation Steps parameters
//
// these values can be hard-coded below, and should correspond to the mif file
// initialized in the memories below. numbered 0 -> 7
//
W_H_Mux InfoWidthMux (
5'd8,
5'd16,
5'd16,
5'd16,
5'd16,
5'd16,
5'd16,
5'd16,
MemSel,
Width
);
W_H_Mux InfoHeightMux (
5'd16,
5'd16,
5'd16,
5'd16,
5'd16,
5'd16,
5'd16,
5'd16,
MemSel,
Height
);
AStep_Mux AnimStepsMux (
3'd0,
3'd0,
3'd0,
3'd0,
3'd0,
3'd0,
3'd0,
3'd0,
MemSel,
AnimSteps
);
// Memories can go here:
wire [8:0] MemOut[7:0]; // 8 sets of 9 wires
/* genvar i;
generate
for (i=0; i <= 7 ;i=i+1)
begin: sprite_memory
SpriteRAM MEM0 (Address, Clock, 9'b0, 1'b0, MemOut[i]); // wren always zero
end
endgenerate
*/
// remember to initialize these!
spriteROM0 MEM0 (
Address,
Clock,
MemOut[0]
);
// multiplex the data (color) output
DataOut_Mux ColorMux (
MemOut[0],
MemOut[1],
MemOut[2],
MemOut[3],
MemOut[4],
MemOut[5],
MemOut[6],
MemOut[7],
MemSel,
DataOut
);
endmodule
| 6.789277 |
module SpriteRAM (
address,
clock,
data,
wren,
q);
input [11:0] address;
input clock;
input [8:0] data;
input wren;
output [8:0] q;
wire [8:0] sub_wire0;
wire [8:0] q = sub_wire0[8:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (clock),
.address_a (address),
.data_a (data),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "sprite_ram_mif_0.mif",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 9,
altsyncram_component.width_byteena_a = 1;
endmodule
| 6.657041 |
module spriteROM #(
ADDR_WIDTH = 10,
DATA_WIDTH = 8,
DEPTH = 32,
DEPTH_BIT = 5,
MEMFILE = ""
) (
input clk
, input [DEPTH_BIT-1:0] addr
, output reg [DATA_WIDTH-1:0] data
);
reg [DATA_WIDTH-1:0] mem[0:DEPTH-1];
initial begin
if (MEMFILE > 0) begin
$display("Loading: " + MEMFILE);
$readmemh(MEMFILE, mem);
$display(MEMFILE + "Loaded");
end
end
always @(posedge clk) begin
data <= mem[addr];
end
endmodule
| 7.155997 |
module spriteROM0 (
address,
clock,
q
);
input [11:0] address;
input clock;
output [8:0] q;
wire [8:0] sub_wire0;
wire [8:0] q = sub_wire0[8:0];
altsyncram altsyncram_component (
.clock0(clock),
.address_a(address),
.q_a(sub_wire0),
.aclr0(1'b0),
.aclr1(1'b0),
.address_b(1'b1),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a(1'b1),
.byteena_b(1'b1),
.clock1(1'b1),
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
.data_a({9{1'b1}}),
.data_b(1'b1),
.eccstatus(),
.q_b(),
.rden_a(1'b1),
.rden_b(1'b1),
.wren_a(1'b0),
.wren_b(1'b0)
);
defparam altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS", altsyncram_component.init_file =
"../sprites/character.mif", altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram", altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM", altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED", altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 9, altsyncram_component.width_byteena_a = 1;
endmodule
| 6.581257 |
module dataShifter (
data,
offset,
shiftedData
);
input [15:0] data;
input [4:0] offset;
output reg [15:0] shiftedData;
// Considerando shift para a esquerda negativo e para a direita positivo
always @(*) begin
if (offset[4]) begin
shiftedData = data << offset[3:0];
end else begin
shiftedData = data >> offset[3:0];
end
end
endmodule
| 7.154049 |
module mux4 (
data0x,
data1x,
data2x,
data3x,
sel,
result
);
input [3:0] data0x, data1x, data2x, data3x;
input [1:0] sel;
output reg [3:0] result;
always @(sel or data0x or data1x or data2x or data3x) begin
case (sel)
2'd0: result = data0x;
2'd1: result = data1x;
2'd2: result = data2x;
2'd3: result = data3x;
endcase
end
endmodule
| 6.570124 |
module mux5 (
data0x,
data1x,
data2x,
data3x,
sel,
result
);
input [4:0] data0x, data1x, data2x, data3x;
input [1:0] sel;
output reg [4:0] result;
always @(sel or data0x or data1x or data2x or data3x) begin
case (sel)
2'd0: result = data0x;
2'd1: result = data1x;
2'd2: result = data2x;
2'd3: result = data3x;
endcase
end
endmodule
| 6.966221 |
module S2_interno (
clk,
clkPipeline,
reset_n,
sp0_num,
sp1_num,
sp2_num,
sp3_num,
sp0_line,
sp1_line,
sp2_line,
sp3_line,
sp0_offset,
sp1_offset,
sp2_offset,
sp3_offset,
sp0_en,
sp1_en,
sp2_en,
sp3_en,
v0_int,
v1_int,
v2_int,
v3_int,
v0num_int,
v1num_int,
v2num_int,
v3num_int
);
input clkPipeline, clk, reset_n;
input [4:0] sp0_num, sp1_num, sp2_num, sp3_num;
input [3:0] sp0_line, sp1_line, sp2_line, sp3_line;
input [4:0] sp0_offset, sp1_offset, sp2_offset, sp3_offset;
input sp0_en, sp1_en, sp2_en, sp3_en;
output [15:0] v0_int, v1_int, v2_int, v3_int;
output [4:0] v0num_int, v1num_int, v2num_int, v3num_int;
wire [15:0] v0_int, v1_int, v2_int, v3_int;
wire [4:0] v0num_int, v1num_int, v2num_int, v3num_int;
wire rd_en, valid_rd;
wire [15:0] data_bus, shiftedData;
wire [3:0] lineNumber;
wire [4:0] spriteNumber, spriteOffset;
wire [1:0] mux_sel;
wire pipeline_rst;
wire [4:0] sp0_num, sp1_num, sp2_num, sp3_num;
wire [3:0] sp0_line, sp1_line, sp2_line, sp3_line;
wire [4:0] sp0_offset, sp1_offset, sp2_offset, sp3_offset;
wire sp0_en, sp1_en, sp2_en, sp3_en;
assign v0num_int = sp0_num;
assign v1num_int = sp1_num;
assign v2num_int = sp2_num;
assign v3num_int = sp3_num;
demux_shapes demux (
.clk(clk),
.reset(pipeline_rst),
.wr_en(valid_rd),
.data_in(shiftedData),
.v0(v0_int),
.v1(v1_int),
.v2(v2_int),
.v3(v3_int),
.sel(mux_sel)
);
mux5 MUX_spnum (
.data0x(sp0_num),
.data1x(sp1_num),
.data2x(sp2_num),
.data3x(sp3_num),
.sel(mux_sel),
.result(spriteNumber)
);
mux4 MUX_spline (
.data0x(sp0_line),
.data1x(sp1_line),
.data2x(sp2_line),
.data3x(sp3_line),
.sel(mux_sel),
.result(lineNumber)
);
SRAM_module SRAM (
.clk(clk),
.reset(pipeline_rst),
.rd_en(rd_en),
.lineNumber(lineNumber),
.spriteNumber(spriteNumber),
.valid_rd(valid_rd),
.q(data_bus)
);
dataShifter offsetter (
.data(data_bus),
.offset(spriteOffset),
.shiftedData(shiftedData)
);
mux5 MUX_spoffset (
.data0x(sp0_offset),
.data1x(sp1_offset),
.data2x(sp2_offset),
.data3x(sp3_offset),
.sel(mux_sel),
.result(spriteOffset)
);
s2_controller fsm (
.reset_n(reset_n),
.clk(clk),
.sp0_en(sp0_en),
.sp1_en(sp1_en),
.sp2_en(sp2_en),
.sp3_en(sp3_en),
.valid_rd(valid_rd),
.clkPipeline(clkPipeline),
.mux_sel(mux_sel),
.pipeline_rst(pipeline_rst),
.rd_en(rd_en)
);
// reset_n,clk,sp0_en,sp1_en,sp2_en,sp3_en,valid_rd,clkPipeline,dmux_en,mux_sel[1:0],pipeline_rst,rd_en);
endmodule
| 7.150311 |
module S2_module (
clk,
reset_n,
clkPipeline,
sprite0,
sprite1,
sprite2,
sprite3,
v0,
v1,
v2,
v3,
v0_num,
v1_num,
v2_num,
v3_num
);
input clk, clkPipeline, reset_n;
input [14:0] sprite0, sprite1, sprite2, sprite3;
output [15:0] v0, v1, v2, v3;
output [4:0] v0_num, v1_num, v2_num, v3_num;
wire [15:0] v0_int, v1_int, v2_int, v3_int;
wire [4:0] v0num_int, v1num_int, v2num_int, v3num_int;
wire rd_en, valid_rd;
wire [15:0] data_bus, shiftedData;
wire [3:0] lineNumber;
wire [4:0] spriteNumber, spriteOffset;
wire [1:0] mux_sel;
wire dmux_en, pipeline_rst;
wire [4:0] sp0_num, sp1_num, sp2_num, sp3_num;
wire [3:0] sp0_line, sp1_line, sp2_line, sp3_line;
wire [4:0] sp0_offset, sp1_offset, sp2_offset, sp3_offset;
wire sp0_en, sp1_en, sp2_en, sp3_en;
splitter wires (
sprite0,
sprite1,
sprite2,
sprite3,
sp0_num,
sp1_num,
sp2_num,
sp3_num,
sp0_line,
sp1_line,
sp2_line,
sp3_line,
sp0_offset,
sp1_offset,
sp2_offset,
sp3_offset,
sp0_en,
sp1_en,
sp2_en,
sp3_en
);
S2_pipeline_buffer saida (
.clkPipeline(clkPipeline),
.v0_int(v0_int),
.v1_int(v1_int),
.v2_int(v2_int),
.v3_int(v3_int),
.v0num_int(v0num_int),
.v1num_int(v1num_int),
.v2num_int(v2num_int),
.v3num_int(v3num_int),
.v0(v0),
.v1(v1),
.v2(v2),
.v3(v3),
.v0_num(v0_num),
.v1_num(v1_num),
.v2_num(v2_num),
.v3_num(v3_num)
);
S2_interno async_s2 (
.clk(clk),
.reset_n(reset_n),
.clkPipeline(clkPipeline),
.sp0_num(sp0_num),
.sp1_num(sp1_num),
.sp2_num(sp2_num),
.sp3_num(sp3_num),
.sp0_line(sp0_line),
.sp1_line(sp1_line),
.sp2_line(sp2_line),
.sp3_line(sp3_line),
.sp0_offset(sp0_offset),
.sp1_offset(sp1_offset),
.sp2_offset(sp2_offset),
.sp3_offset(sp3_offset),
.sp0_en(sp0_en),
.sp1_en(sp1_en),
.sp2_en(sp2_en),
.sp3_en(sp3_en),
.v0_int(v0_int),
.v1_int(v1_int),
.v2_int(v2_int),
.v3_int(v3_int),
.v0num_int(v0num_int),
.v1num_int(v1num_int),
.v2num_int(v2num_int),
.v3num_int(v3num_int)
);
endmodule
| 7.533696 |
module S2_pipeline_buffer (
clkPipeline,
v0_int,
v1_int,
v2_int,
v3_int,
v0num_int,
v1num_int,
v2num_int,
v3num_int,
v0,
v1,
v2,
v3,
v0_num,
v1_num,
v2_num,
v3_num
);
input clkPipeline;
input [15:0] v0_int, v1_int, v2_int, v3_int;
input [4:0] v0num_int, v1num_int, v2num_int, v3num_int;
output reg [15:0] v0, v1, v2, v3;
output reg [4:0] v0_num, v1_num, v2_num, v3_num;
always @(posedge clkPipeline) begin
v0 <= v0_int;
v1 <= v1_int;
v2 <= v2_int;
v3 <= v3_int;
v0_num <= v0num_int;
v1_num <= v1num_int;
v2_num <= v2num_int;
v3_num <= v3num_int;
end
endmodule
| 7.215324 |
module splitter (
sprite0,
sprite1,
sprite2,
sprite3,
sp0_num,
sp1_num,
sp2_num,
sp3_num,
sp0_line,
sp1_line,
sp2_line,
sp3_line,
sp0_offset,
sp1_offset,
sp2_offset,
sp3_offset,
sp0_en,
sp1_en,
sp2_en,
sp3_en
);
input [14:0] sprite0, sprite1, sprite2, sprite3;
output [4:0] sp0_num, sp1_num, sp2_num, sp3_num;
output [3:0] sp0_line, sp1_line, sp2_line, sp3_line;
output [4:0] sp0_offset, sp1_offset, sp2_offset, sp3_offset;
output sp0_en, sp1_en, sp2_en, sp3_en;
assign sp0_num = sprite0[4:0];
assign sp1_num = sprite1[4:0];
assign sp2_num = sprite2[4:0];
assign sp3_num = sprite3[4:0];
assign sp0_line = sprite0[8:5];
assign sp1_line = sprite1[8:5];
assign sp2_line = sprite2[8:5];
assign sp3_line = sprite3[8:5];
assign sp0_offset = sprite0[13:9];
assign sp1_offset = sprite1[13:9];
assign sp2_offset = sprite2[13:9];
assign sp3_offset = sprite3[13:9];
assign sp0_en = sprite0[14];
assign sp1_en = sprite1[14];
assign sp2_en = sprite2[14];
assign sp3_en = sprite3[14];
endmodule
| 7.230286 |
module sram_addr_decoder (
clk,
lineNumber,
spriteNumber,
address
);
input clk;
input [3:0] lineNumber;
input [4:0] spriteNumber;
output [19:0] address;
assign address = (20'd16 * spriteNumber) + lineNumber;
endmodule
| 6.652576 |
module t5_t6 (
v0,
v1,
v2,
v3,
sp0,
sp1,
sp2,
sp3,
clock_25,
clock_maior,
rst,
att_color,
data_color,
blue,
green,
red,
branco
);
// Sinais básicos de controle
input clock_25, rst;
// Vetores com as flags indicando a presenca dos sprites em cada uma das 16 posicoes
input [15:0] v0, v1, v2, v3;
// Indica o codigo do sprite referente a cada um dos vetores anteriormente definidos
input [4:0] sp0, sp1, sp2, sp3;
// Entradas para atualização da memória de cor
input [23:0] data_color; // Dado da cor vindo da mémoria
input att_color; // Sinal para atualizar a memória
// Sinal para descarregar os sinais dos barramentos de entreda
input clock_maior;
//Saidas do modulo
output wire [7:0] red, green, blue;
output branco;
// memória interna de cores da FSM.
reg [23:0] Color_Memory[0:31];
// memória interna de sprites da FSM
reg [15:0] sprites[0:3];
reg [4:0] pos[0:3];
// Registradores de suporte
reg branco;
reg start;
reg [1:0] state;
reg [1:0] next_state;
reg [4:0] elemento;
reg [4:0] next_elemento;
reg [4:0] saida;
reg [3:0] count;
reg [3:0] next_count;
parameter Inicio = 2'b00, Atualizando = 2'b01, Enviando = 2'b10, Sync = 2'b11;
always @* begin
next_state = 5'bxxxxx;
next_elemento = elemento;
next_count = count;
saida = 5'bx;
branco = 1'b1;
case (state)
Inicio: begin // Estado Inicial
next_state = Atualizando;
end
Sync: begin // Estado de sincronização com o clock mais lento (25/16 Mhz)
if (start) begin
if (count == 15) begin
next_state = Enviando;
end else begin
next_state = Sync;
next_count = count + 1'b1;
end
end else begin
next_state = Sync;
end
end
Atualizando: begin // Estado para atualizar a tabela de cores.
if (elemento == 5'd31) begin
next_elemento = 5'b0;
next_state = Sync;
end else begin
next_elemento = elemento + 1'b1;
next_state = Atualizando;
end
end
Enviando: begin // Estado de saída das cores do sprite mais importante
if (att_color) begin
next_elemento = 5'b0;
next_state = Atualizando;
end else begin
next_state = Enviando;
branco = 1'b0;
if (sprites[0][15-elemento[3:0]]) begin
saida = pos[0];
end else if (sprites[1][15-elemento[3:0]]) begin
saida = pos[1];
end else if (sprites[2][15-elemento[3:0]]) begin
saida = pos[2];
end else if (sprites[3][15-elemento[3:0]]) begin
saida = pos[3];
end else begin
branco = 1'b1;
end
next_elemento = elemento + 1'b1;
end
end
default: begin
next_state = Inicio;
end
endcase
end
assign red = (branco) ? 8'b0 : Color_Memory[saida][23:16];
assign green = (branco) ? 8'b0 : Color_Memory[saida][15:8];
assign blue = (branco) ? 8'b0 : Color_Memory[saida][7:0];
always @(posedge clock_maior) begin
if (!rst) begin
sprites[0] <= v0;
sprites[1] <= v1;
sprites[2] <= v2;
sprites[3] <= v3;
pos[0] <= sp0;
pos[1] <= sp1;
pos[2] <= sp2;
pos[3] <= sp3;
if (next_state == Sync) begin
start <= 1'b1;
end else begin
start <= 1'b0;
end
end
end
always @(posedge clock_25) begin
if (rst) begin
state <= Inicio;
elemento <= 5'b0;
count <= 4'b0;
end else begin
state <= next_state;
elemento <= next_elemento;
count <= next_count;
if (next_state == Atualizando) begin
Color_Memory[next_elemento] = data_color;
end
end
end
endmodule
| 7.632149 |
module t7 (
input wire [7:0] FIFO_Red,
input wire [7:0] FIFO_Green,
input wire [7:0] FIFO_Blue,
input wire [7:0] Sprites_Red,
input wire [7:0] Sprites_Green,
input wire [7:0] Sprites_Blue,
output wire [7:0] VGA_R,
output wire [7:0] VGA_G,
output wire [7:0] VGA_B,
output wire showingFIFO
);
assign VGA_R = (Sprites_Red == 0 && Sprites_Green == 0 && Sprites_Blue == 0)? FIFO_Red: Sprites_Red;
assign VGA_G = (Sprites_Red == 0 && Sprites_Green == 0 && Sprites_Blue == 0)? FIFO_Green: Sprites_Green;
assign VGA_B = (Sprites_Red == 0 && Sprites_Green == 0 && Sprites_Blue == 0)? FIFO_Blue: Sprites_Blue;
assign showingFIFO = (Sprites_Red == 0 && Sprites_Green == 0 && Sprites_Blue == 0);
endmodule
| 6.868072 |
module SPITER_testbench (
VGA_R,
VGA_G,
VGA_B
);
// -------------------------------------------- Variáveis -------------------------------------------- //
reg clk_125, clk_25, clk_25_16, n_reset;
wire [9:0] row, column;
wire [7:0] FIFO_Red, FIFO_Green, FIFO_Blue;
wire [23:0] data_color;
output [7:0] VGA_R, VGA_G, VGA_B;
wire n_reset_wire;
integer f;
// ---------------------------------------- Geracao de CLOCK ---------------------------------------- //
initial begin
clk_125 = 1;
clk_25 = 1;
clk_25_16 = 1;
end
always #4 clk_125 = !clk_125;
always #20 clk_25 = !clk_25;
always #320 clk_25_16 = !clk_25_16;
// ---------------------------------------- Geracao de Reset --------------------------------------- //
initial begin
n_reset = 1'b0;
#680 n_reset = 1'b1;
end
// ---------------------------------------- Geracao de hsync ---------------------------------------- //
//initial
// hsync = 1'b1;
//
//always
//begin
// // 640 * 40 (image)
// #25600 hsync = 1'b1;
//
// // 16 * 40 (front porch)
// #640 hsync = 1'b0;
//
// // 96 * 40 (sync)
// #3840 hsync = 1'b1;
//
// // 48 * 40 (back porch)
// #1920 hsync = 1'b1;
//end
//// ------------------------------------- Geracao de row/column ------------------------------------- //
//
//initial
//begin
// row = 9'd0;
//end
//
//always@(posedge hsync)
//begin
// if (row < 480)
// begin
// row = row + 9'd1;
// end
// else
// begin
// row = 0;
// end
//end
// --------------------------- Instanciacao do DUT e Geradores de Sinais --------------------------- //
syncReset regReset (
.clk(clk_25_16),
.rstIn(n_reset),
.rstOut(n_reset_wire)
);
spriter_module DUT (
.clk_100(clk_125),
.clk_25(clk_25),
.clk_sync(clk_25_16),
.address(5'd0),
.rwenable(1'b1),
.datain(19'd0),
.row(row),
.column(column),
.n_reset(n_reset_wire),
.data_color(data_color),
.att_color(1'b0),
.FIFO_Red(FIFO_Red),
.FIFO_Green(FIFO_Green),
.FIFO_Blue(FIFO_Blue),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B)
);
color_preset input_gen (
.reset_n(n_reset_wire),
.clock(clk_25),
.data_color(data_color)
);
VGA_module backgrounder (
.clk75(clk_125),
.clk25(clk_25),
.clk_sync(clk_25_16),
.reset(~n_reset_wire),
.data_bgr(24'h010101),
.wr_en(1'b1),
.freeslots(),
.VGA_B(FIFO_Blue),
.VGA_G(FIFO_Green),
.VGA_R(FIFO_Red),
.VGA_HS(),
.VGA_VS(),
.VGA_SYNC_N(),
.VGA_BLANK_N(),
.row(row),
.column(column)
);
// ----------------------------------- Plotando Waveforms e Texto ---------------------------------- //
initial begin
$dumpfile("spriter_module_tb.vcd");
$dumpvars;
end
initial begin
// f = $fopen("output.txt");
// $fwrite(f, "\t\ttime,\trow,\tcolumn,\tR,\tG,\tB\t\n");
// $fmonitor(f, "%d,\t%d,\t%d,\t%h,\t%h,\t%h\t",$time, row, column_pipeline, VGA_R, VGA_G, VGA_B);
#67200000
// $fclose(f);
$stop;
end
endmodule
| 7.137995 |
module car_bitmap (
input wire [3 : 0] yofs,
output wire [7 : 0] bits
);
/*******************************************************
* WIRE AND REG DECLARATION *
*******************************************************/
reg [7 : 0] bitarray[0 : 15];
/*******************************************************
* ASSIGNMENT *
*******************************************************/
assign bits = bitarray[yofs];
initial $readmemb("../../fpga-examples/car.hex", bitarray);
endmodule
| 8.422706 |
module sprite_mem (
clk,
addr,
rdata
);
parameter ROM_DATA_FILE = "sprite0.mem";
input clk;
input [9:0] addr;
output reg [7:0] rdata;
reg [7:0] MY_ROM[0:2**10-1];
initial $readmemb(ROM_DATA_FILE, MY_ROM);
always @(posedge clk) rdata <= MY_ROM[addr];
endmodule
| 6.954692 |
module sprite_memory (
input wire [13:0] address,
input wire clock,
input wire reset_done,
input wire [ 8:0] data,
input wire wren,
output reg [8:0] out_data,
output wire read_memory
);
reg r_memory;
wire [8:0] colors;
/*--------Sempre que sentir uma mudança na saída da memória é porque uma leitura foi realizada---------*/
always @(posedge clock) begin
out_data <= colors;
if (wren) begin //escrita
r_memory <= 1'b1;
end else if (reset_done == 1'b1 || wren == 1'b0) begin
r_memory <= 1'b0;
end else r_memory <= 1'b0;
end
/*------------------------------------------------------------------------------------------------------*/
assign read_memory = r_memory;
memory memory_inst (
.address(address), // input [13:0] address_sig
.clock (clock), // input clock_sig
.data (data), // input [8:0] data_sig
.wren (wren), // input wren_sig
.q (colors) // output [8:0] q_sig
);
endmodule
| 7.666376 |
module sprite_rom #(
parameter FILE = "./sprites/test_sprite.mem"
) (
input [9:0] x,
input [9:0] y,
output [7:0] data
);
//combinatorial ROM for square sprites
localparam sq_size = 16;
reg [3:0] memory[0:255];
initial begin
if (FILE != 0) begin
$readmemh(FILE, memory);
end
end
assign data = memory[x+(sq_size*y)];
endmodule
| 8.287406 |
module tank_bitmap (
input wire [7 : 0] addr,
output wire [7 : 0] bits
);
/*******************************************************
* WIRE AND REG DECLARATION *
*******************************************************/
reg [15 : 0] bitarray[0 : 255];
assign bits = (addr[0]) ? bitarray[addr>>1][15:8] : bitarray[addr>>1][7:0];
initial $readmemb("../../fpga-examples/tank.hex", bitarray);
endmodule
| 6.851062 |
module sprite_renderer2 (
input wire [0 : 0] clk,
input wire [0 : 0] reset,
input wire [0 : 0] vstart,
input wire [0 : 0] load,
input wire [0 : 0] hstart,
output reg [4 : 0] rom_addr,
input wire [7 : 0] rom_bits,
input wire [0 : 0] hmirror,
input wire [0 : 0] vmirror,
output reg [0 : 0] gfx,
output wire [0 : 0] busy
);
localparam WAIT_FOR_VSTART = 0,
WAIT_FOR_LOAD = 1,
LOAD1_SETUP = 2,
LOAD1_FETCH = 3,
LOAD2_SETUP = 4,
LOAD2_FETCH = 5,
WAIT_FOR_HSTART = 6,
DRAW = 7;
/*******************************************************
* WIRE AND REG DECLARATION *
*******************************************************/
reg [ 2 : 0] state;
reg [ 3 : 0] ycount;
reg [ 3 : 0] xcount;
reg [15 : 0] outbits;
assign busy = state != WAIT_FOR_VSTART;
/*******************************************************
* OTHER COMB AND SEQ LOGIC *
*******************************************************/
always @(posedge clk, posedge reset)
if (reset) begin
gfx <= 0;
state <= WAIT_FOR_VSTART;
ycount <= 0;
xcount <= 0;
outbits <= 0;
rom_addr <= 0;
end else begin
case (state)
WAIT_FOR_VSTART: begin
ycount <= 0;
// set a default value (blank) for pixel output
// note: multiple non-blocking assignments are vendor-specific
gfx <= 0;
if (vstart) state <= WAIT_FOR_LOAD;
end
WAIT_FOR_LOAD: begin
xcount <= 0;
gfx <= 0;
if (load) state <= LOAD1_SETUP;
end
LOAD1_SETUP: begin
rom_addr <= {vmirror ? ~ycount : ycount, 1'b0};
state <= LOAD1_FETCH;
end
LOAD1_FETCH: begin
outbits[0+:8] <= rom_bits;
state <= LOAD2_SETUP;
end
LOAD2_SETUP: begin
rom_addr <= {(vmirror ? ~ycount : ycount), 1'b1};
state <= LOAD2_FETCH;
end
LOAD2_FETCH: begin
outbits[15 : 8] <= rom_bits;
state <= WAIT_FOR_HSTART;
end
WAIT_FOR_HSTART: begin
if (hstart) state <= DRAW;
end
DRAW: begin
// mirror graphics left/right
gfx <= outbits[hmirror?~xcount[3 : 0] : xcount[3 : 0]];
xcount <= xcount + 1;
if (xcount == 15) begin // pre-increment value
ycount <= ycount + 1;
if (ycount == 15) // pre-increment value
state <= WAIT_FOR_VSTART; // done drawing sprite
else state <= WAIT_FOR_LOAD; // done drawing this scanline
end
end
endcase
end
endmodule
| 7.563984 |
module rotation_selector (
input wire [3 : 0] rotation,
output reg [2 : 0] bitmap_num,
output reg [0 : 0] hmirror,
output reg [0 : 0] vmirror
);
/*******************************************************
* OTHER COMB AND SEQ LOGIC *
*******************************************************/
always @(*)
case (rotation[3 : 2]) // 4 quadrants
0: begin // 0..3 -> 0..3
bitmap_num = {1'b0, rotation[1 : 0]};
hmirror = 0;
vmirror = 0;
end
1: begin // 4..7 -> 4..1
bitmap_num = -rotation[2 : 0];
hmirror = 0;
vmirror = 1;
end
2: begin // 8-11 -> 0..3
bitmap_num = {1'b0, rotation[1 : 0]};
hmirror = 1;
vmirror = 1;
end
3: begin // 12-15 -> 4..1
bitmap_num = -rotation[2 : 0];
hmirror = 1;
vmirror = 0;
end
default: begin
bitmap_num = 0;
hmirror = 0;
vmirror = 0;
end
endcase
endmodule
| 8.030049 |
module tank_top (
input wire [0 : 0] clk,
input wire [0 : 0] reset,
input wire [0 : 0] switch_left,
input wire [0 : 0] switch_right,
input wire [0 : 0] switch_up,
output wire [0 : 0] hsync,
output wire [0 : 0] vsync,
output wire [2 : 0] rgb
);
/*******************************************************
* WIRE AND REG DECLARATION *
*******************************************************/
// for working with vhsync generator
wire [ 0 : 0] display_on; // active area
wire [15 : 0] hpos; // horizontal position from hvsync generator
wire [15 : 0] vpos; // vertical position from hvsync generator
// tank bitmap module
wire [ 7 : 0] tank_addr;
wire [ 7 : 0] tank_bits;
// tank graphic
wire [ 0 : 0] tank_gfx;
// walls
wire [ 0 : 0] top_wall;
wire [ 0 : 0] bottom_wall;
wire [ 0 : 0] right_wall;
wire [ 0 : 0] left_wall;
wire [ 0 : 0] wall_gfx;
/*******************************************************
* ASSIGNMENT *
*******************************************************/
// walls
assign top_wall = vpos < 5;
assign bottom_wall = vpos > 475;
assign right_wall = hpos < 5;
assign left_wall = hpos > 635;
assign wall_gfx = top_wall || bottom_wall || right_wall || left_wall;
// VGA rgb
assign rgb = {1'b0, display_on && tank_gfx, display_on && wall_gfx};
/*******************************************************
* MODULE INSTANCES *
*******************************************************/
// creating one tank bitmap
tank_bitmap tank_0 (
.addr(tank_addr),
.bits(tank_bits)
);
// creating one tank controller
tank_controller tank_controller_0 (
.clk (clk),
.reset (reset),
.hpos (hpos),
.vpos (vpos),
.hsync (hsync),
.vsync (vsync),
.sprite_addr (tank_addr),
.sprite_bits (tank_bits),
.gfx (tank_gfx),
.playfield (wall_gfx),
.switch_left (switch_left),
.switch_right(switch_right),
.switch_up (switch_up)
);
// creating one hvsync generator
hvsync_generator hvsync_gen (
.clk (clk),
.reset (reset),
.hsync (hsync),
.vsync (vsync),
.display_on(display_on),
.hpos (hpos),
.vpos (vpos)
);
endmodule
| 7.139186 |
module for culling and sorting sprites to be displayed on a particular
// scanline.
// This uses the pre-transformed sprite data to determine if a sprite scanline
// exists on the current line or not.
// It caches data for up to N sprites, which is then read by the line writer
// during the display routine.
// This module gets kicked off while the walls are being drawn.
// Note how this isn't generally optimized: this has to scan every possible
// sprite once per scanline, then sort, which is only consistently faster than
// the wall draw if there're < 128 sprites in a level.
//
// However, this is fine for this implementation since each sprite cull test
// can be done within a single cycle!
// A better one, and more closely matching the wolf3D engine, would have the
// sprite pre-transform sort sprites into map squares. The raycaster then logs
// which tiles it sees for each ray, which is used to more quickly cull
// sprites. It can also be used to improve ordering since map tiles can be
// examined from near-to-far, so you only have to sort sprites within
// a particular tile.
module sprite_scanline (
input clk,
input rst,
input start,
output reg done,
input [8:0] x, // camera X position
input [15:0] wall_z, // z buffer of casted wall
// transformed sprite metadata
output reg [6:0] stmeta_raddr,
input [119:0] stmeta_read_data,
// hook sorted registers into line writer
input [2:0] sprite_addr,
output reg [119:0] sprite_meta,
output reg [2:0] sprite_count
);
localparam WIDTH = 320;
localparam IDLE = 0,
CULL_FETCH = 1,
CULL = 2;
reg [3:0] state_d, state_q;
reg [6:0] count_d, count_q;
reg [2:0] scount_d, scount_q;
// add an extra bit so we can do signed comparisons.
reg signed [15:0] camera_x_d, camera_x_q;
// FIXME: use pointers instead and serve from stmeta_raddr.
reg [119:0] sprites [2:0];
reg save_meta;
always @(*) begin
state_d = state_q;
count_d = count_q;
stmeta_raddr = count_q;
camera_x_d = camera_x_q;
save_meta = 1'b0;
sprite_count = scount_q;
scount_d = scount_q;
done = 1'b0;
case (state_q)
IDLE: begin
count_d = 0;
if (start) begin
state_d = CULL_FETCH;
camera_x_d = x - 1'b1;
scount_d = 3'd0;
end
end
CULL_FETCH: begin
// load the metadata from RAM
// can remove this step once tested/understood better.
state_d = CULL;
end
CULL: begin
// First test is the wall Z depth cull.
// Then, if camera X is within sprite X draw boundaries
if ($signed(stmeta_read_data[111:96]) < wall_z
&& $signed(stmeta_read_data[111:96]) > 0
&& $signed(stmeta_read_data[31:16]) <= camera_x_q
&& $signed(stmeta_read_data[15:0]) >= camera_x_q
) begin
// save the sprite info if it's visible
save_meta = 1'b1;
scount_d = scount_q + 1'b1;
end
count_d = count_q + 1'b1;
if (count_q == 127 || scount_d == 8) begin
done = 1'b1;
state_d = IDLE;
end else begin
state_d = CULL_FETCH;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_q <= IDLE;
end else begin
state_q <= state_d;
end
count_q <= count_d;
camera_x_q <= camera_x_d;
scount_q <= scount_d;
if (save_meta) begin
sprites[count_q] <= stmeta_read_data;
end
sprite_meta <= sprites[sprite_addr];
end
endmodule
| 7.623554 |
module example_bitmap_rom (
input wire [15 : 0] addr,
output wire [15 : 0] data
);
/*******************************************************
* WIRE AND REG DECLARATION *
*******************************************************/
reg [15:0] bitarray[0 : 255];
assign data = bitarray[addr&15];
initial $readmemb("../../fpga-examples/man.hex", bitarray);
endmodule
| 8.904245 |
module sprite_scanline_renderer_top (
input wire [0 : 0] clk,
input wire [0 : 0] reset,
output wire [0 : 0] hsync,
output wire [0 : 0] vsync,
output wire [2 : 0] rgb
);
/*******************************************************
* PARAMS & LOCALPARAMS *
*******************************************************/
localparam NB = 5, MB = 3;
/*******************************************************
* WIRE AND REG DECLARATION *
*******************************************************/
// for working with vhsync generator
wire [ 0 : 0] display_on; // active area
wire [15 : 0] hpos; // horizontal position from hvsync generator
wire [15 : 0] vpos; // vertical position from hvsync generator
wire [NB : 0] ram_addr;
wire [15 : 0] ram_data;
wire [ 0 : 0] ram_busy;
wire [15 : 0] rom_addr;
wire [15 : 0] rom_data;
wire [ 2 : 0] rgb_ssr;
reg [15 : 0] ram_mem [63 : 0];
/*******************************************************
* ASSIGNMENT *
*******************************************************/
assign ram_data = ram_mem[ram_addr];
assign rgb = {display_on, display_on, display_on} & rgb_ssr;
/*******************************************************
* MODULE INSTANCES *
*******************************************************/
// creating one hvsync generator
hvsync_generator hvsync_gen (
.clk (clk),
.reset (reset),
.hsync (hsync),
.vsync (vsync),
.display_on(display_on),
.hpos (hpos),
.vpos (vpos)
);
// creating one example bitmap rom
example_bitmap_rom example_bitmap_rom_0 (
.addr(rom_addr),
.data(rom_data)
);
// creating one sprite scanline renderer
sprite_scanline_renderer #(
.NB(NB), // 2^NB == number of sprites
.MB(MB) // 2^MB == slots per scanline
) sprite_scanline_renderer_0 (
.clk (clk),
.reset (reset),
.hpos (hpos),
.vpos (vpos),
.rgb (rgb_ssr), // rgb output
.ram_addr(ram_addr), // RAM for sprite data
.ram_data(ram_data), // (2 words per sprite)
.ram_busy(ram_busy), // set when accessing RAM
.rom_addr(rom_addr), // sprite ROM address
.rom_data(rom_data) // sprite ROM data
);
initial $readmemh("../../fpga-examples/ram_mem.hex", ram_mem);
endmodule
| 8.642635 |
module Sprite_Sel (
input clk,
input [3:0] inputs,
input [1:0] step,
output reg [8:0] hoffset,
output reg [8:0] voffset
);
wire have_inputs;
reg walk = 0;
assign have_inputs = (inputs == 8 || inputs == 4 || inputs == 2 || inputs == 1);
initial begin
hoffset <= 0;
voffset <= 0;
end
always @(posedge clk) begin
case (inputs)
4'b1000: voffset <= 16; // up
4'b0100: voffset <= 0; // down
4'b0010: voffset <= 32; //left
4'b0001: voffset <= 48; //right
4'b0000: voffset <= voffset;
default: voffset <= voffset;
endcase
end
always @(step) begin
hoffset <= have_inputs == 1'b0 ? 1'b0 : step % 2 == 1'b0 ? 1'b0 : (voffset == 32 || voffset == 48) ? 16 : step == 3 ? 32 : 16;
walk = step == 1'b1 ? walk + 1'b1 : walk;
end
endmodule
| 6.710373 |
module sprite_subsystem(
input wire rst_n,
input wire CLK_6M,
input wire CLK_1H,
input wire nOBJECT,
input wire nHSYNC,
input wire nVRESET,
input wire [12:0] A,
inout wire [7:0] D,
input wire RnW,
`SRAM_OUTPUT_DEFS(CY6264, sram_10m),
`SRAM_OUTPUT_DEFS(M58725, sram_11k)
);
wire cus35_9m_cs0_n;
wire cus35_9m_cs1_n;
wire cus35_9m_rwe_n;
wire cus35_9m_roe_n;
wire [7:0] cus35_9m_b0;
wire [7:0] cus35_9m_b1;
cus35
cus35_9m
(
.rst_n(rst_n),
// inputs
.CLK_6M(CLK_6M),
.nHSYNC(nHSYNC),
.nVRES(nVRESET),
.nOCS(nOBJECT),
.RnW(RnW),
.A(A),
.D(D),
// outputs
.nCS0(cus35_9m_cs0_n),
.nCS1(cus35_9m_cs1_n),
.nRWE(cus35_9m_rwe_n),
.nROE(cus35_9m_roe_n),
.B0(cus35_9m_b0),
.B1(cus35_9m_b1)
);
wire ls32_6e_y3;
wire ls32_6e_y4;
ls32
ls32_6e
(
.A3(CLK_1H), // pin 9
.B3(A[12]), // pin 10
.A4(CLK_1H), // pin 12
.B4(A[0]), // pin 13
.Y3(ls32_6e_y3), // pin 8 - 10M A11
.Y4(ls32_6e_y4) // pin 11 - to 10M A12
);
// object ram
assign sram_10m_ce_n = cus35_9m_cs1_n;
assign sram_10m_we_n = cus35_9m_rwe_n;
assign sram_10m_oe_n = cus35_9m_roe_n;
assign sram_10m_addr = { ls32_6e_y4, ls32_6e_y3, A[10:0] };
assign sram_10m_data = ~RnW ? cus35_9m_b1 : 8'bz;
assign cus35_9m_b1 = RnW ? sram_10m_data : 8'bz;
assign sram_11k_ce_n = cus35_9m_cs0_n;
assign sram_11k_we_n = cus35_9m_rwe_n;
assign sram_11k_oe_n = cus35_9m_roe_n;
assign sram_11k_addr = { 1'b0, A[11:1] };
assign sram_11k_data = ~RnW ? cus35_9m_b0 : 8'bz;
assign cus35_9m_b0 = RnW ? sram_11k_data : 8'bz;
endmodule
| 6.855392 |
module sprom(clk, rst, ce, oe, addr, do);
//
// Default address and data buses width (1024*32)
//
parameter aw = 10; //number of address-bits
parameter dw = 32; //number of data-bits
parameter MEM_INIT_FILE = "";
//
// Generic synchronous single-port ROM interface
//
input clk; // Clock, rising edge
input rst; // Reset, active high
input ce; // Chip enable input, active high
input oe; // Output enable input, active high
input [aw-1:0] addr; // address bus inputs
output reg [dw-1:0] do; // output data bus
//
// Module body
//
reg [dw-1:0] mem [(1<<aw) -1:0];
reg [aw-1:0] ra;
reg oe_r;
always @(posedge clk)
oe_r <= oe;
always @*
// if (oe_r)
do = mem[ra];
// read operation
always @(posedge clk)
if (ce)
ra <= addr; // read address needs to be registered to read clock
initial begin
/* verilator lint_off WIDTH */
if (MEM_INIT_FILE != "") begin
/* verilator lint_on WIDTH */
$readmemh(MEM_INIT_FILE, mem);
end
end
endmodule
| 8.036795 |
module sprom2phase(
clk,
rst,
ph1_en,
ph1_addr,
ph1_do,
ph2_en,
ph2_addr,
ph2_do
);
parameter aw = 10; //number of address-bits
parameter dw = 32; //number of data-bits
parameter MEM_INIT_FILE = "";
input clk;
input rst;
input ph1_en;
input [aw-1:0] ph1_addr;
output reg [dw-1:0] ph1_do;
input ph2_en;
input [aw-1:0] ph2_addr;
output reg [dw-1:0] ph2_do;
wire [dw-1:0] do;
reg ph1_not_ph2;
always @(posedge clk) begin
if (ph1_en) ph1_not_ph2 <= 1'b1;
else if (ph2_en) ph1_not_ph2 <= 1'b0;
end
always @(posedge clk) begin
if (ph1_en) ph2_do <= do;
end
always @(posedge clk) begin
if (ph2_en) ph1_do <= do;
end
sprom #(
.aw(aw),
.dw(dw),
.MEM_INIT_FILE(MEM_INIT_FILE)
) u_sprom(
.clk(clk),
.rst(rst),
.ce(1'b1),
.oe(1'b1),
.addr(ph1_not_ph2 ? ph1_addr : ph2_addr),
.do(do)
);
endmodule
| 7.384423 |
module SPRWI #(
parameter DATA_WIDTH = 4,
parameter ADDR_WIDTH = 6
) (
input [(DATA_WIDTH - 1):0] i_Data,
input [(ADDR_WIDTH - 1):0] i_Addr, // Memory address
input i_WriteEnable,
i_Clock,
output [(DATA_WIDTH - 1):0] o_Data
);
// Declare the RAM variable
reg [(DATA_WIDTH - 1):0] r_Ram [(2**ADDR_WIDTH - 1):0];
// Variable to hold the registered read address
reg [(ADDR_WIDTH - 1):0] r_Addr;
// Specify the initial contents. You can also use the $readmemb
// system task to initialize the RAM variable from a text file.
// See the $readmemb template page for details.
initial begin : INIT
reg [(ADDR_WIDTH - 1):0] i;
for (i = 0; i < 52; i = i + 1) begin
if (i <= 12) r_Ram[i] = i[3:0];
else if (i > 12 && i <= 25) r_Ram[i] = i[3:0] + 3;
else if (i > 25 && i <= 38) r_Ram[i] = i[3:0] + 6;
else r_Ram[i] = i[3:0] + 9;
end
end
always @(posedge i_Clock) begin
// Write
if (i_WriteEnable) r_Ram[i_Addr] <= i_Data;
r_Addr <= i_Addr;
end
// Continuous assignment implies read returns NEW data.
// This is the natural behavior of the TriMatrix memory
// blocks in Single Port mode.
assign o_Data = r_Ram[r_Addr];
endmodule
| 8.509193 |
module SPS (
input clk,
in,
in2,
ps2_clk,
ps2_data,
output [6:0] segments,
segments2,
output reg buzzer,
output reg [6:0] f,
u,
l1,
l2
);
wire [7:0] max;
reg [3:0] max1;
keyboard(
max, clk, ps2_clk, ps2_data
);
reg state = 0;
wire [3:0] count1;
wire [3:0] count;
wire [3:0] diff;
//assign buzzer = (diff>=max);
second1 g1 (
clk,
in2,
count1
);
second1 g2 (
clk,
in,
count
);
assign diff = count1 - count;
seven_segment_decoder1 s1 (
diff,
segments
);
seven_segment_decoder1 s2 (
max1,
segments2
);
always @(posedge clk) begin
case (max)
8'h45: begin
max1 <= 4'b0000;
end
8'h16: begin
max1 <= 4'b0001;
end
8'h1E: begin
max1 <= 4'b0010;
end
8'h26: begin
max1 <= 4'b0011;
end
8'h25: begin
max1 <= 4'b0100;
end
8'h2E: begin
max1 <= 4'b0101;
end
8'h36: begin
max1 <= 4'b0110;
end
8'h3D: begin
max1 <= 4'b0111;
end
8'h3E: begin
max1 <= 4'b1000;
end
8'h46: begin
max1 <= 4'b1001;
end
default: begin
max1 <= 4'b0010;
end
endcase
if (diff >= max1) begin
buzzer = 1;
f = ~(7'b1110001);
u = ~(7'b0111110);
l1 = ~(7'b0111000);
l2 = ~(7'b0111000);
//buzzer = (diff>=max1);
end else begin
buzzer = 0;
f = (7'b1111111);
u = (7'b1111111);
l1 = (7'b1111111);
l2 = (7'b1111111);
end
end
endmodule
| 6.616976 |
module implements a parameterizable Last-In, First-Out (LIFO) function.
// Parameters allow setting the depth, width, and memory contents. It's intend-
// ed for use as return address stacks for microprogram sequencers, microcompu-
// ters, ALUs, etc.
//
// The module provides a clock enable, and separate push and pop operation con-
// trol inputs. An error output provides an indication that a push operation
// occurred while the storage element is full, or that a pop operation occurred
// while the storage element is empty.
//
// Dependencies:
//
// Revision:
//
// 0.01 13G20 MAM File Created
//
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module SPSLmnCE #(
parameter pDataWidth = 8, // LIFO data bus width
parameter pAddrWidth = 4, // LIFO address bus width
parameter pInit = "Src/SPSLmnCE.mif" // LIFO initial values
)(
input Rst, // Reset
input Clk, // Clock
input En, // Clock Enable
input Psh, // Push - LIFO[++A] <= DI, pre-increment
input Pop, // Pop - DO <= LIFO[A--], post-decrement
input [(pDataWidth - 1):0] DI, // LIFO Input Data Port
output [(pDataWidth - 1):0] DO, // LIFO Output Data Port
output Err // Error Flag
);
///////////////////////////////////////////////////////////////////////////////
//
// Module Parameter List
//
localparam pDepth = (2**pAddrWidth);
///////////////////////////////////////////////////////////////////////////////
//
// Module Level Declarations
//
reg [(pDataWidth - 1):0] LIFO [(pDepth - 1):0];
reg [(pAddrWidth - 1):0] A;
reg FF, EF;
wire Wr;
wire [(pAddrWidth - 1):0] Addr;
///////////////////////////////////////////////////////////////////////////////
//
// Implementation
//
//
// Address Counter
//
always @(posedge Clk)
begin
if(Rst)
A <= #1 0;
else if(En)
A <= #1 ((Psh & ~FF) ? Addr : ((Pop & |A) ? (A - 1) : A));
end
//
// Empty Flag Register
//
always @(posedge Clk)
begin
if(Rst)
EF <= #1 ~0;
else if(En)
EF <= #1 ((Pop & ~EF) ? (~|Addr) : ((Psh) ? 0 : EF));
end
//
// Full Flag Register
//
always @(posedge Clk)
begin
if(Rst)
FF <= #1 0;
else if(En)
FF <= #1 ((Psh & ~FF) ? ( &Addr) : ((Pop) ? 0 : FF));
end
//
// Error Flag Logic
//
assign Err = ((Psh) ? FF : ((Pop) ? EF : 0));
//
// Single-Port Synchronous RAM
//
initial
$readmemh(pInit, LIFO, 0, (pDepth - 1));
assign Wr = (En & Psh & ~FF);
assign Addr = ((Psh & ~FF) ? (A + {{(pAddrWidth - 1){1'b0}},~EF}) : A);
always @(posedge Clk)
begin
if(Wr)
LIFO[Addr] <= #1 DI; // Synchronous Write
end
assign DO = LIFO[Addr]; // Asynchronous Read
endmodule
| 6.904081 |
module spsram (
clk,
cs,
we,
addr,
din,
dout
);
parameter mem_depth = 1024;
parameter mem_width = 32;
parameter mem_bitw = 10;
input wire clk;
input wire cs;
input wire we;
input wire [mem_bitw-1:0] addr;
input wire [mem_width-1:0] din;
output reg [mem_width-1:0] dout;
reg [mem_width-1:0] mem[0:mem_depth-1];
always @(posedge clk) begin
if (cs) begin
if (we) begin
mem[addr] <= din;
end else begin
dout <= mem[addr];
end
end
end
endmodule
| 7.523016 |
module spu (
input clk,
input rst,
input start, // to start the processor
output stop, // to show that the processor is stopped
//control signals for instruction memory (im)
input [15:0] im_r_data, // 16-bit read data of im
output [ 7:0] im_addr, // 8-bit data address of im
output im_rd, // read enable of im
//control signals for data memory (dm)
output [7:0] dm_addr, // 8-bit data address of dm
output dm_rd, // read enable of dm
output dm_wr, // write enable of dm
//data for data memory (dm)
input [15:0] dm_r_data, // 16-bit read data
output [15:0] dm_w_data // 16-bit write data
);
wire pco_en;
//control signal for mux
wire rf_s1;
wire rf_s0;
//control signals for register file (rf)
wire [3:0] rf_w_addr; // 4-bit write address
wire rf_w_wr; // write enable
wire [3:0] rf_rp_addr; // 4-bit p-port read address
wire rf_rp_rd; // p-port read enable
wire [3:0] rf_rq_addr; // 4-bit q-port read address
wire rf_rq_rd; // q-port read enable
//control signal for ALU
wire alu_s1;
wire alu_s0;
wire [7:0] loac;
spu_ctrl c1 (
.clk(clk),
.rst(rst),
.start(start), // to start the processor
.stop (stop), // to show that the processor is stopped
.pco_en(pco_en),
//control signals for instruction memory (im)
.im_r_data(im_r_data), // 16-bit read data of im
.im_addr (im_addr), // 8-bit data address of im
.im_rd (im_rd), // read enable of im
//control signals for data memory (dm)
.dm_addr(dm_addr), // 8-bit data address of dm
.dm_rd (dm_rd), // read enable of dm
.dm_wr (dm_wr), // write enable of dm
//control signal for mux
.rf_s1(rf_s1),
.rf_s0(rf_s0),
//control signals for register file (rf)
.rf_w_addr(rf_w_addr), // 4-bit write address
.rf_w_wr (rf_w_wr), // write enable
.rf_rp_addr(rf_rp_addr), // 4-bit p-port read address
.rf_rp_rd (rf_rp_rd), // p-port read enable
.rf_rq_addr(rf_rq_addr), // 4-bit q-port read address
.rf_rq_rd (rf_rq_rd), // q-port read enable
//control signal for ALU
.alu_s1(alu_s1),
.alu_s0(alu_s0),
.loac(loac)
);
spu_datapath d1 (
.clk(clk),
.rst(rst),
.pco_en(pco_en),
//control signal for mux
.rf_s1(rf_s1),
.rf_s0(rf_s0),
//control signals for register file (rf)
.rf_w_addr(rf_w_addr), // 4-bit write address
.rf_w_wr (rf_w_wr), // write enable
.rf_rp_addr(rf_rp_addr), // 4-bit p-port read address
.rf_rp_rd (rf_rp_rd), // p-port read enable
.rf_rq_addr(rf_rq_addr), // 4-bit q-port read address
.rf_rq_rd (rf_rq_rd), // q-port read enable
//control signal for ALU
.alu_s1(alu_s1),
.alu_s0(alu_s0),
//data for data memory (dm)
.dm_r_data(dm_r_data), // 16-bit read data
.dm_w_data(dm_w_data), // 16-bit write data
.loac(loac)
);
endmodule
| 6.846924 |
module spu_datapath (
input clk,
input rst,
output pco_en, // if rf[a] equals to 0
//control signal for mux
input rf_s1,
input rf_s0,
//control signals for register file (rf)
input [3:0] rf_w_addr, // 4-bit write address
input rf_w_wr, // write enable
input [3:0] rf_rp_addr, // 4-bit p-port read address
input rf_rp_rd, // p-port read enable
input [3:0] rf_rq_addr, // 4-bit q-port read address
input rf_rq_rd, // q-port read enable
//control signal for ALU
input alu_s1,
input alu_s0,
//control signal for constant number is assigned
input [7:0] loac,
//data for data memory (dm)
input [15:0] dm_r_data, // 16-bit read data
output [15:0] dm_w_data // 16-bit write data
);
wire [15:0] mux_out;
//data for rf
wire [15:0] rf_rp_data; // 16-bit rf p-port read data
wire [15:0] rf_rq_data; // 16-bit rf q-port read data
reg [15:0] alu_out;
//mux
assign mux_out = rf_s1 ? loac : rf_s0 ? dm_r_data : alu_out;
assign dm_w_data = rf_rp_data;
assign pco_en = !rf_rp_data;
//register file
reg_file #(
.DEPTH(16),
.ADDR (4),
.WIDTH(16)
) rf (
.rst (rst),
.clk (clk),
.w_en (rf_w_wr), // write enable
.w_addr (rf_w_addr), // write address
.r1_en (rf_rp_rd), // #1-port read enable
.r2_en (rf_rq_rd), // #2-port read enable
.r1_addr(rf_rp_addr), // #1-port read address
.r2_addr(rf_rq_addr), // #2-port read address
.w_data (mux_out), // write data
.r1_data(rf_rp_data), // #1-port read data
.r2_data(rf_rq_data) // #2-port read data
);
always @(*) begin
case ({
alu_s1, alu_s0
})
2'd0: alu_out = rf_rp_data;
2'd1: alu_out = rf_rp_data + rf_rq_data;
2'd2: alu_out = rf_rp_data - rf_rq_data;
default: alu_out = 16'd0;
endcase
end
endmodule
| 7.836836 |
module SPWM_3Phase (
CLK,
RST,
SW,
CCW,
PHA,
PLA,
PHB,
PLB,
PHC,
PLC
);
input CLK, RST, CCW;
input [4:0] SW;
output PHA, PLA, PHB, PLB, PHC, PLC;
wire CP;
wire [3:0] Sublevel;
wire [11:0] PWMA;
wire [11:0] PWMB;
wire [11:0] PWMC;
//实例化时钟脉冲发生器
TimePulGenerator Inst_TimePulGenerator (
.CLK(CLK),
.RST(RST),
.SW(SW),
.CP(CP),
.Sublevel(Sublevel)
);
//实例化细分波形发生器
Interface Inst_Interface (
.CLK(CLK),
.rst(RST),
.CP(CP),
.CCW(CCW),
.SubLevel(Sublevel),
.REFA(PWMA),
.REFB(PWMB),
.REFC(PWMC)
);
//实例化脉宽调制信号发生器
SPWMGenerator SPWMGeneratorA (
.CLK(CLK),
.RST(RST),
.PWM(PWMA),
.PH (PHA),
.PL (PLA)
);
SPWMGenerator SPWMGeneratorB (
.CLK(CLK),
.RST(RST),
.PWM(PWMB),
.PH (PHB),
.PL (PLB)
);
SPWMGenerator SPWMGeneratorC (
.CLK(CLK),
.RST(RST),
.PWM(PWMC),
.PH (PHC),
.PL (PLC)
);
endmodule
| 8.862614 |
module top (
input clk,
output out1,
output out2
);
wire [5:0] w_sel1;
wire w_sel2;
wire w_CE;
data_path d1 (
.clk (w_CE),
.sel1(w_sel1),
.sel2(w_sel2),
.out1(out1),
.out2(out2)
);
controller c1 (
.clk (w_CE),
.sel1(w_sel1),
.sel2(w_sel2)
);
clk_enable e1 (
.clk(clk),
.CE (w_CE)
);
endmodule
| 7.233807 |
module data_path (
input clk,
input [5:0] sel1,
input sel2,
output out1,
output out2
);
wire w_1, w_2;
spwm s1 (
.clk (clk),
.sel1(sel1),
.out (w_1)
);
spwm s2 (
.clk (clk),
.sel1(sel1),
.out (w_2)
);
H_driver H1 (
.clk (clk),
.sel2(sel2),
.in1 (w_1),
.in2 (w_2),
.out1(out1),
.out2(out2)
);
endmodule
| 6.77594 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.