code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module H_driver (
input clk,
input sel2,
input in1,
input in2,
output out1,
output out2
);
reg r_out1, r_out2;
always @(*) begin
case (sel2)
0: r_out1 <= in1;
1: r_out1 <= 0;
endcase
case (sel2)
0: r_out2 <= 0;
1: r_out2 <= in2;
endcase
end
assign out1 = r_out1;
assign out2 = r_out2;
endmodule
| 6.527644 |
module sel2 (
input clk,
input [5:0] sel1,
output sel2
);
reg r_sel2 = 0;
always @(posedge clk) begin
if (sel1 <= 0) r_sel2 <= ~r_sel2;
end
assign sel2 = r_sel2;
endmodule
| 7.289997 |
module clk_enable (
input clk,
output CE //clock enable
);
reg [9:0] r_count = 0;
reg r_CE;
always @(posedge clk) begin
if (r_count <= 250) begin
r_count <= r_count + 1;
r_CE <= 0;
end else begin
r_count <= 0;
r_CE <= 1;
end
end
assign CE = r_CE;
endmodule
| 7.824564 |
module with Wishbone interface to node device(the host) or communication memory.
// "A SpaceWire node comprise one or more SpaceWire link interfaces
// (encoder-decoders) and an interface to the host system,represents an interface between
// a SpaceWire network and an application system using the network services."
//Approximate area:
//Origin: SpaceWire Std-Draft-1 of ECSS(European Cooperation for Space Standardization),ESTEC,ESA
//
//-- TODO:
////////////////////////////////////////////////////////////////////////////////////
//
/*synthesis translate off*/
`include "timescale.v"
/*synthesis translate on */
`define reset 1 // WISHBONE style reset
`define USE_XIL_DEVICE // If use Xilinx device
`define TOOL_NOTSUP_PORT_ARRAY //if the tools not support port array declaration
module SPW_I_vlogcore #(parameter CH_NUM = 3) //Triple Modulo Redundant (TMR)
( output [CH_NUM-1:0] Dout,Doutb, Sout,Soutb, //LVDS pad
input [CH_NUM-1:0] Sin, Sinb, Din, Dinb, //LVDS pad. 8 pads/pin for 1 channel
output int_LnkErr_o,
output TICK_o, TICK_i,
input reset,gclk
);
//////////////
// LVDS IO
//
`ifdef USE_XIL_DEVICE
wire [CH_NUM-1:0] Si,Di, So,Do;
generate
begin:Gen_LVDS_PADS
genvar k;
for (k=0; k<CH_NUM, k=k+1)
IBUFDS_LVDS_25 inst_LVDS_Di ( .I(Din[k]) // P-channel data
.IB(Dinb[k]) // N-channel data
.O(Di[k]) ); // Non-differential data input
IBUFDS_LVDS_25 inst_LVDS_Si ( .I(Sin[k]) // P-channel strobe
.IB(Sinb[k]) // N-channel strobe
.O(Si[k]) ); // Non-differential strobe input
OBUFDS_LVDS_25 inst_LVDS_Do ( .I(Do[k]), //Non-differential data output
.O(Dout[k]), //P-channel output
.OB(Doutb[k]) ); //N-channel output
OBUFDS_LVDS_25 inst_LVDS_So ( .I(So[k]), //Non-differential strobe output
.O(Sout[k]), //P-channel output
.OB(Soutb[k]) ); //N-channel output
end //end block Gen_LVDS_PADS
endgenerate
`endif
//////////////////////////
// Synchronizer
// between 2 clock domain
synchronizer_flop #(WIDTH*2) inst_Syn_flops(.sync_data_out(),
.data_in(),
.clk(),
.async_reset()
);
/********** Instantiations of low level modules ****************/
////// Channels //////
generate
begin:G_channel
genvar i;
for(i=0; i<CHANNEL_NUM; i=i+1)
SPW_CODEC #() CODEC_xChannels (
);
end
endgenerate
Gluelogic inst_fifo_crc ();
WB_COMI_HOCI inst_WB_IF ();
JTAG_spw inst_JTAG_IO ();
endmodule
| 7.055284 |
module/interface definition.
// Ben Rosser <bjr@sas.upenn.edu>
`default_nettype none
module SpyBuffer #(
// The width of input data (e.g. 2^WIDTH bytes + 1 for metadata).
parameter DATA_WIDTH = 64,
// Width of the spy buffer's memory block. (e.g. 2^WIDTH rows of DATA_WIDTH size).
parameter SPY_MEM_WIDTH = 7,
// The width of the flow control buffer's memory.
// If this is pushed to 5 or higher, block RAM will be inferred.
// (Do we want that?)
// (Presumably, the threshold coul also be adjusted!)
parameter FC_FIFO_WIDTH = 3,
// The size and width of the event list / metadata list memory.
parameter EL_MEM_SIZE = 16,
parameter EL_MEM_WIDTH = 4
) (
// The read and write clocks, respectively.
input wire rclock,
input wire wclock,
// TODO: is a reset necessary on both sides? Probably...
input wire rreset,
input wire wreset,
input wire [DATA_WIDTH:0] write_data,
input wire write_enable,
input wire read_enable,
// Freeze the spy buffer.
input wire freeze,
// This is a proxy for some more sophisticated readout mechanism.
// (involving block transfer protocols?)
input wire spy_read_enable,
input wire spy_meta_read_enable,
input wire [SPY_MEM_WIDTH-1:0] spy_read_addr,
input wire [EL_MEM_WIDTH-1:0] spy_meta_read_addr,
output wire [EL_MEM_WIDTH-1:0] spy_meta_write_addr,
output wire [SPY_MEM_WIDTH-1:0] spy_write_addr,
output wire [DATA_WIDTH:0] read_data,
output wire almost_full,
output wire empty,
// Spy outputs.
output wire [DATA_WIDTH:0] spy_data,
output wire [SPY_MEM_WIDTH:0] spy_meta_read_data
);
// To first order, I think we want an asynchronous FIFO.
// The write data should get passed to the spy writer block
// Which should sit on top of a differently structured FIFO for spying.
// And there should be an internal spy controller which reads out.
// So, we grab the aFifo source code here for the "memory".
// Then at some point we modify it's internal memory to use some Xilinx interface.
// Flow control buffer, provided by an aFifo.
aFifo #(
.DSIZE(DATA_WIDTH+1),
.ASIZE(FC_FIFO_WIDTH)
) buffer (
.rdata(read_data),
.wdata(write_data),
.rclk(rclock),
.wclk(wclock),
.rempty(empty),
.walmostfull(almost_full),
.wfull(),
.ralmostempty(),
.wrst_n(wreset),
.rrst_n(rreset),
.winc(write_enable),
.rinc(read_enable)
);
// This is the block that actually is the "spy controller".
// It handles the "spy" part of the "spy buffer".
// It wants to live in the write clock domain.
// Note that with this naive implementation, there is no "spy memory"
// readout block (everything's contained beneath the "spy controller").
// In reality, possibly we would want that to live in the toplevel and
// have some block transfer protocol thing, presumably powered by Xilinx
// libraries.
SpyController #(
.DATAWIDTH(DATA_WIDTH),
.MEMWIDTH(SPY_MEM_WIDTH),
.METASIZE(EL_MEM_SIZE),
.METAWIDTH(EL_MEM_WIDTH)
) spy (
.clock(wclock),
.reset(wreset),
.freeze(freeze),
.data_in(write_data),
.write_enable_in(write_enable),
.read_addr(spy_read_addr),
.read_enable_in(spy_read_enable),
.meta_read_enable(spy_meta_read_enable),
.meta_read_addr(spy_meta_read_addr),
.data_out(spy_data),
.mem_wptr(spy_write_addr),
.meta_write_addr(spy_meta_write_addr),
.meta_read_data(spy_meta_read_data)
);
endmodule
| 10.116876 |
module SpyMemory #(
parameter WIDTH = 6,
// Width of the actual data.
parameter DATAWIDTH = 64
) (
input wire clock,
input wire reset,
// Write enable and write data.
input wire write_enable,
input wire [DATAWIDTH-1:0] write_data,
// Address to read.
input wire [WIDTH-1:0] read_addr,
input wire read_enable,
// Output containing the "write pointer"
// current position.
output wire [WIDTH-1:0] write_pointer,
// Output containing the result of the read command.
output reg [DATAWIDTH-1:0] read_data,
// Output wire that toggles when occupancy == 0.
output wire looped
);
localparam SIZE = 1 << WIDTH;
// Memory block.
reg [DATAWIDTH-1:0] memory[0:SIZE-1];
// Write pointer.
reg [WIDTH-1:0] wptr;
// Continuously update output write pointer.
assign write_pointer = wptr;
// Continuously update the "looped" flag.
// Fire this *when we have looped*, not before.
assign looped = (~|wptr);
// Handle writes to memory.
always @(posedge clock) begin
if (!reset) begin
wptr <= 0;
end else begin
if (write_enable) begin
memory[wptr] <= write_data;
wptr <= wptr + 1;
end
end
end
// Handle reads from the memory.
// We don't care about whether the buffer is "full" or "empty".
// We just assign "rptr" = the read address requested.
// There's a race condition here if wptr = read_addr. I think it's
// okay if we require that never happen.
always @(posedge clock) begin
if (!reset) begin
read_data <= 0;
end else begin
if (read_enable) begin
read_data <= memory[read_addr];
end
end
end
endmodule
| 8.534972 |
module sp_efm #(
parameter WIDTH = 9, // 小数分频的位宽
parameter OUT_REG = 0 // 输出加寄存器
) (
input clk, // 时钟输入
input rst_n, // 复位信号，低有效
input [WIDTH-1:0] x_i, // 一阶的误差反馈调制器（EFM）的输入
input y_i,
output y_o, // 量化输出
output [WIDTH-1:0] e_o // 误差输出，作为下一级 EFM 的输入
);
wire [WIDTH:0] sum;
reg [WIDTH:0] sum_r;
// 实现一阶的误差反馈调制器的功能
assign sum = x_i + y_i + sum_r[WIDTH-1:0];
// 对求和结果延迟一个时钟周期
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
sum_r <= 'b0;
end else begin
sum_r <= sum;
end
end
// // 原始输出
// assign e_o = sum[WIDTH-1:0];
// assign y_o = sum[WIDTH];
// // 优化输出
// // 由于在 y 的输出上插入寄存器不会影响 Sigma-Delta 的传输函数，即不会影响 Sigma-Delta 的特性，因此将 y 用寄存器打一拍再输出，可以减少逻辑路径的长度，提高电路的频率
// // assign y_o = sum_r[WIDTH];
// 输出
generate
if (OUT_REG) begin
// 加寄存器后输出
assign e_o = sum_r[WIDTH-1:0];
assign y_o = sum_r[WIDTH];
end else begin
// 直接输出
assign e_o = sum[WIDTH-1:0];
assign y_o = sum[WIDTH];
end
endgenerate
endmodule
| 7.872091 |
module sp_find_segment_n1_62 (
ph_seg_p_2_1_1_V_read,
th_seg_p_2_1_0_V_read,
th_seg_p_2_1_1_V_read,
cpat_seg_p_2_1_1_V_read,
ap_return_0,
ap_return_1,
ap_return_2,
ap_return_3
);
input [11:0] ph_seg_p_2_1_1_V_read;
input [6:0] th_seg_p_2_1_0_V_read;
input [6:0] th_seg_p_2_1_1_V_read;
input [3:0] cpat_seg_p_2_1_1_V_read;
output [11:0] ap_return_0;
output [3:0] ap_return_1;
output [6:0] ap_return_2;
output [6:0] ap_return_3;
assign ap_return_0 = ph_seg_p_2_1_1_V_read;
assign ap_return_1 = cpat_seg_p_2_1_1_V_read;
assign ap_return_2 = th_seg_p_2_1_0_V_read;
assign ap_return_3 = th_seg_p_2_1_1_V_read;
endmodule
| 6.800849 |
module sp_find_segment_stn1 (
ph_seg_p_1_1_1_V_read,
th_seg_p_1_1_0_V_read,
th_seg_p_1_1_1_V_read,
cpat_seg_p_1_1_1_V_read,
ap_return_0,
ap_return_1,
ap_return_2,
ap_return_3
);
input [11:0] ph_seg_p_1_1_1_V_read;
input [6:0] th_seg_p_1_1_0_V_read;
input [6:0] th_seg_p_1_1_1_V_read;
input [3:0] cpat_seg_p_1_1_1_V_read;
output [11:0] ap_return_0;
output [3:0] ap_return_1;
output [6:0] ap_return_2;
output [6:0] ap_return_3;
assign ap_return_0 = ph_seg_p_1_1_1_V_read;
assign ap_return_1 = cpat_seg_p_1_1_1_V_read;
assign ap_return_2 = th_seg_p_1_1_0_V_read;
assign ap_return_3 = th_seg_p_1_1_1_V_read;
endmodule
| 6.800849 |
module ADDSUB (
dataa,
datab,
add_sub,
result
);
input [35:0] dataa, datab;
input add_sub; // 1 = Addition , 0 = Subtraction
output [35:0] result;
assign result = dataa + (add_sub ? datab : ~datab) + {35'd0, ~add_sub};
endmodule
| 7.706747 |
module Sort (
clk,
rst_n,
in0,
in1,
in2,
in3,
in4,
in5,
out0,
out1,
out2,
out3,
out4,
out5
);
//================================================================
// INPUT AND OUTPUT DECLARATION
//================================================================
input clk, rst_n;
input [8:0] in0, in1, in2, in3, in4, in5;
output [8:0] out0, out1, out2, out3, out4, out5;
//================================================================
// Wire & Registers
//================================================================
wire [8:0] a[0:3], b[0:2], c[0:3], d[0:2], f[0:3], g[0:1];
reg [8:0] e[0:5];
//================================================================
// DESIGN
//================================================================
//
assign a[0] = (in0 < in1) ? in0 : in1;
assign a[1] = (in0 < in1) ? in1 : in0;
assign a[2] = (a[1] < in2) ? a[1] : in2;
assign a[3] = (a[1] < in2) ? in2 : a[1];
assign b[0] = (a[0] < a[2]) ? a[0] : a[2];
assign b[1] = (a[0] < a[2]) ? a[2] : a[0];
assign b[2] = a[3];
//
assign c[0] = (in3 < in4) ? in3 : in4;
assign c[1] = (in3 < in4) ? in4 : in3;
assign c[2] = (c[1] < in5) ? c[1] : in5;
assign c[3] = (c[1] < in5) ? in5 : c[1];
assign d[0] = (c[0] < c[2]) ? c[0] : c[2];
assign d[1] = (c[0] < c[2]) ? c[2] : c[0];
assign d[2] = c[3];
//
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
e[0] <= 0;
e[1] <= 0;
e[2] <= 0;
e[3] <= 0;
e[4] <= 0;
e[5] <= 0;
end else begin
e[0] <= (b[0] < d[0]) ? b[0] : d[0];
e[1] <= (b[0] < d[0]) ? d[0] : b[0];
e[2] <= (b[1] < d[1]) ? b[1] : d[1];
e[3] <= (b[1] < d[1]) ? d[1] : b[1];
e[4] <= (b[2] < d[2]) ? b[2] : d[2];
e[5] <= (b[2] < d[2]) ? d[2] : b[2];
end
end
/*
assign e[0] = ( b[0]<d[0] ) ? b[0] : d[0] ;
assign e[1] = ( b[0]<d[0] ) ? d[0] : b[0] ;
assign e[2] = ( b[1]<d[1] ) ? b[1] : d[1] ;
assign e[3] = ( b[1]<d[1] ) ? d[1] : b[1] ;
assign e[4] = ( b[2]<d[2] ) ? b[2] : d[2] ;
assign e[5] = ( b[2]<d[2] ) ? d[2] : b[2] ;
*/
//
assign out0 = e[0];
assign out5 = e[5];
//
assign f[0] = (e[1] < e[2]) ? e[1] : e[2];
assign f[1] = (e[1] < e[2]) ? e[2] : e[1];
assign f[2] = (e[3] < e[4]) ? e[3] : e[4];
assign f[3] = (e[3] < e[4]) ? e[4] : e[3];
//
assign out1 = f[0];
assign out4 = f[3];
//
assign g[0] = (f[1] < f[2]) ? f[1] : f[2];
assign g[1] = (f[1] < f[2]) ? f[2] : f[1];
//
assign out2 = g[0];
assign out3 = g[1];
endmodule
| 6.626478 |
module sp_mash111 #(
parameter WIDTH = 9, // 小数分频的位宽
parameter OUT_REG = 1 // 输出加寄存器
) (
input clk, // 时钟输入
input rst_n, // 复位信号，低有效
input [WIDTH-1:0] x_i, // Sigma-Delta 调制器的输入，即分频中小数的输入
output [ 3:0] y_o, // 量化输出
output [WIDTH-1:0] e_o // 最后一级 EFM 的误差输出，实际上用不到，不用管
);
// efm inputs or outputs
wire [WIDTH-1:0] x_i_1;
wire [WIDTH-1:0] e_o_1;
wire y_o_1;
wire [WIDTH-1:0] x_i_2;
wire [WIDTH-1:0] e_o_2;
wire y_o_2;
wire [WIDTH-1:0] x_i_3;
wire [WIDTH-1:0] e_o_3;
wire y_o_3;
// ncl Inputs
wire y1_i;
wire y2_i;
wire y3_i;
// // 前一级 efm 的误差输出作为后一级 efm 的输入
assign x_i_1 = x_i;
assign x_i_2 = {e_o_1, 4'b0};
assign x_i_3 = e_o_2;
// e 输出
assign e_o = e_o_3;
// 三级 efm 级联
sp_efm #(
.WIDTH (5),
.OUT_REG(OUT_REG)
) u_sp_efm_1 (
.clk (clk),
.rst_n(rst_n),
.x_i (x_i_1),
.y_i (1'b0),
.y_o(y_o_1),
.e_o(e_o_1)
);
sp_efm #(
.WIDTH (WIDTH),
.OUT_REG(OUT_REG)
) u_sp_efm_2 (
.clk (clk),
.rst_n(rst_n),
.x_i (x_i_2),
.y_i (y_o_1),
.y_o(y_o_2),
.e_o(e_o_2)
);
sp_efm #(
.WIDTH (WIDTH),
.OUT_REG(OUT_REG)
) u_sp_efm_3 (
.clk (clk),
.rst_n(rst_n),
.x_i (x_i_3),
.y_i (y_o_2),
.y_o(y_o_3),
.e_o(e_o_3)
);
// noise cancellation logic
ncl #(
.OUT_REG(1)
) u_ncl (
.clk (clk),
.rst_n(rst_n),
.y1_i (y1_i),
.y2_i (y2_i),
.y3_i (y3_i),
.y_o(y_o)
);
// efm 级间加寄存器
generate
if (OUT_REG) begin
wire y1_reg_0;
wire y1_reg_1;
wire y2_reg_0;
dff #(
.WIDTH (1),
.WITH_RST (0),
.RST_VALUE(0)
) u0_dff (
.clk (clk),
.rst_n(rst_n),
.D (y_o_1),
.Q(y1_reg_0)
);
dff #(
.WIDTH (1),
.WITH_RST (0),
.RST_VALUE(0)
) u1_dff (
.clk (clk),
.rst_n(rst_n),
.D (y1_reg_0),
.Q(y1_reg_1)
);
dff #(
.WIDTH (1),
.WITH_RST (0),
.RST_VALUE(0)
) u2_dff (
.clk (clk),
.rst_n(rst_n),
.D (y_o_2),
.Q(y2_reg_0)
);
assign y1_i = y1_reg_1;
assign y2_i = y2_reg_0;
assign y3_i = y_o_3;
end else begin
assign y1_i = y_o_1;
assign y2_i = y_o_2;
assign y3_i = y_o_3;
end
endgenerate
endmodule
| 7.091773 |
module sp_mux_4to1_sel2_4_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
dout_WIDTH = 32
) (
input [3 : 0] din1,
input [3 : 0] din2,
input [3 : 0] din3,
input [3 : 0] din4,
input [1 : 0] din5,
output [3 : 0] dout
);
// puts internal signals
wire [1 : 0] sel;
// level 1 signals
wire [3 : 0] mux_1_0;
wire [3 : 0] mux_1_1;
// level 2 signals
wire [3 : 0] mux_2_0;
assign sel = din5;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din1 : din2;
assign mux_1_1 = (sel[0] == 0) ? din3 : din4;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
// output logic
assign dout = mux_2_0;
endmodule
| 6.511105 |
module sp_mux_4to1_sel2_7_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
dout_WIDTH = 32
) (
input [6 : 0] din1,
input [6 : 0] din2,
input [6 : 0] din3,
input [6 : 0] din4,
input [1 : 0] din5,
output [6 : 0] dout
);
// puts internal signals
wire [1 : 0] sel;
// level 1 signals
wire [6 : 0] mux_1_0;
wire [6 : 0] mux_1_1;
// level 2 signals
wire [6 : 0] mux_2_0;
assign sel = din5;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din1 : din2;
assign mux_1_1 = (sel[0] == 0) ? din3 : din4;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
// output logic
assign dout = mux_2_0;
endmodule
| 6.511105 |
module sp_mux_6to1_sel3_12_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
din7_WIDTH = 32,
dout_WIDTH = 32
) (
input [11 : 0] din1,
input [11 : 0] din2,
input [11 : 0] din3,
input [11 : 0] din4,
input [11 : 0] din5,
input [11 : 0] din6,
input [ 2 : 0] din7,
output [11 : 0] dout
);
// puts internal signals
wire [ 2 : 0] sel;
// level 1 signals
wire [11 : 0] mux_1_0;
wire [11 : 0] mux_1_1;
wire [11 : 0] mux_1_2;
// level 2 signals
wire [11 : 0] mux_2_0;
wire [11 : 0] mux_2_1;
// level 3 signals
wire [11 : 0] mux_3_0;
assign sel = din7;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din1 : din2;
assign mux_1_1 = (sel[0] == 0) ? din3 : din4;
assign mux_1_2 = (sel[0] == 0) ? din5 : din6;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
assign mux_2_1 = mux_1_2;
// Generate level 3 logic
assign mux_3_0 = (sel[2] == 0) ? mux_2_0 : mux_2_1;
// output logic
assign dout = mux_3_0;
endmodule
| 6.52561 |
module sp_mux_6to1_sel3_7_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
din7_WIDTH = 32,
dout_WIDTH = 32
) (
input [6 : 0] din1,
input [6 : 0] din2,
input [6 : 0] din3,
input [6 : 0] din4,
input [6 : 0] din5,
input [6 : 0] din6,
input [2 : 0] din7,
output [6 : 0] dout
);
// puts internal signals
wire [2 : 0] sel;
// level 1 signals
wire [6 : 0] mux_1_0;
wire [6 : 0] mux_1_1;
wire [6 : 0] mux_1_2;
// level 2 signals
wire [6 : 0] mux_2_0;
wire [6 : 0] mux_2_1;
// level 3 signals
wire [6 : 0] mux_3_0;
assign sel = din7;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din1 : din2;
assign mux_1_1 = (sel[0] == 0) ? din3 : din4;
assign mux_1_2 = (sel[0] == 0) ? din5 : din6;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
assign mux_2_1 = mux_1_2;
// Generate level 3 logic
assign mux_3_0 = (sel[2] == 0) ? mux_2_0 : mux_2_1;
// output logic
assign dout = mux_3_0;
endmodule
| 6.52561 |
module sp_ram #(
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 32,
parameter NUM_WORDS = 256
) (
clk,
en_i,
addr_i,
wdata_i,
rdata_o,
we_i,
be_i
);
//parameter ADDR_WIDTH = 8;
//parameter DATA_WIDTH = 32;
//parameter NUM_WORDS = 256;
input wire clk;
input wire en_i;
input wire [ADDR_WIDTH - 1:0] addr_i;
input wire [DATA_WIDTH - 1:0] wdata_i;
output reg [DATA_WIDTH - 1:0] rdata_o;
input wire we_i;
input wire [(DATA_WIDTH / 8) - 1:0] be_i;
localparam words = NUM_WORDS / (DATA_WIDTH / 8);
reg [((DATA_WIDTH / 8) * 8) - 1:0] mem[0:words - 1];
wire [((DATA_WIDTH / 8) * 8) - 1:0] wdata;
wire [(ADDR_WIDTH - 1) - $clog2(DATA_WIDTH / 8):0] addr;
integer i;
assign addr = addr_i[ADDR_WIDTH-1:$clog2(DATA_WIDTH/8)];
always @(posedge clk) begin
if (en_i && we_i)
for (i = 0; i < (DATA_WIDTH / 8); i = i + 1) if (be_i[i]) mem[addr][i*8+:8] <= wdata[i*8+:8];
rdata_o <= mem[addr];
end
genvar w;
generate
for (w = 0; w < (DATA_WIDTH / 8); w = w + 1) begin : genblk1
assign wdata[w*8+:8] = wdata_i[((w+1)*8)-1:w*8];
end
endgenerate
endmodule
| 7.048193 |
module sp_ram_be_tb;
//Inputs
reg clk;
reg en; // enable access to ram
reg [`NUM_COL-1:0] we; // write enable vector
reg [`ADDR_W-1:0] addr;
reg [`DATA_W-1:0] data_in;
//Ouptuts
reg [`DATA_W-1:0] data_out;
// .hex file
reg [7:0] filemem[0:15];
integer i, a;
parameter clk_per = 10; // clk period = 10 timeticks
initial begin
// optional VCD
`ifdef VCD
$dumpfile("sp_ram.vcd");
$dumpvars();
`endif
//Initialize Inputs
clk = 1;
en = 0;
for (i = 0; i < `NUM_COL; i = i + 1) we[i] = 0;
addr = 0;
// store file for comparison
#clk_per @(posedge clk) #1;
$readmemh(`hex_file1, filemem);
@(posedge clk) #1;
en = 1;
// read from file stored in RAM
@(posedge clk) #1;
for (i = 0; i < 16; i = i + 1) begin
addr = i;
@(posedge clk) #1;
if (filemem[i] != data_out) begin
$display("Test failed: read error in position %d, where tb1.hex=%h but data_out=%h", i,
filemem[i], data_out);
$finish;
end
end
#clk_per $readmemh(`hex_file2, filemem);
// write into RAM in all positions and read from it
@(posedge clk) #1;
for (i = 0; i < 16; i = i + 1) begin
we[i] = 1;
@(posedge clk) #1;
addr = i;
data_in = filemem[i];
@(posedge clk) #1;
end
@(posedge clk) #1;
for (i = 0; i < `NUM_COL; i = i + 1) we = 0;
@(posedge clk) #1;
for (i = 0; i < 16; i = i + 1) begin
addr = i;
@(posedge clk) #1;
if (filemem[i] != data_out) begin
$display("Test failed: write error in position %d, where tb2.hex=%h but data_out=%h", i,
filemem[i], data_out);
$finish;
end
end
// test if output is truly different
// this supposes that both hex files are completely different, including spaces
$readmemh(`hex_file1, filemem);
for (i = 0; i < 16; i = i + 1) begin
addr = i;
@(posedge clk) #1;
if (filemem[i] == data_out) begin
if (filemem[i] != 10) begin // rule out EOL
$display(
"Test failed: read error in position %d, where tb1.hex and data_out are '%h' but should not be the same",
i, data_out);
$finish;
end
end
end
@(posedge clk) #1;
en = 0;
#clk_per $display("%c[1;34m", 27);
$display("Test completed successfully.");
$display("%c[0m", 27);
#(5 * clk_per) $finish;
end
// Instantiate the Unit Under Test (UUT)
iob_sp_ram_be #(
.NUM_COL(`NUM_COL),
.COL_WIDTH(`COL_WIDTH),
.DATA_WIDTH(`DATA_W),
.ADDR_WIDTH(`ADDR_W),
.FILE(`hex_file1)
) uut (
.clk (clk),
.en (en),
.we (we),
.addr(addr),
.din (data_in),
.dout(data_out)
);
// system clock
always #(clk_per / 2) clk = ~clk;
endmodule
| 7.431717 |
module sp_ram_rw_instruction (
clk, // clock
address, // address Input
data_in, // data in
data_out, // data out
re, // read enable
we // write enable
);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter RAM_DEPTH = 16;
//--------------Input Ports-----------------------
input clk;
input [ADDR_WIDTH-1:0] address;
input re;
input we;
input [DATA_WIDTH-1:0] data_in;
//--------------Output Ports-----------------------
output reg [DATA_WIDTH-1:0] data_out;
//--------------Internal variables----------------
reg [DATA_WIDTH-1:0] mem[0:RAM_DEPTH-1];
//--------------Code Starts Here------------------
// Memory Write Block
// Write Operation : When we = 1
//assign data = (re && !we) ? data_out : 8'b0;
always @(negedge clk) begin : MEM_WRITE
if (we) begin
mem[address] <= data_in;
end
end
// Memory Read Block
// Read Operation : When re = 1
always @(posedge clk) begin : MEM_READ
if (re) begin
data_out <= mem[address/4];
end else begin
data_out <= 0;
end
end
endmodule
| 6.820465 |
module sp_ram_tb;
//Inputs
reg clk;
reg en; // enable access to ram
reg we; // write enable
reg [`ADDR_W-1:0] addr;
reg [`DATA_W-1:0] data_in;
//Ouptuts
reg [`DATA_W-1:0] data_out;
// .hex file
reg [7:0] filemem[0:15];
integer i;
parameter clk_per = 10; // clk period = 10 timeticks
initial begin
// optional VCD
`ifdef VCD
$dumpfile("sp_ram.vcd");
$dumpvars();
`endif
//Initialize Inputs
clk = 1;
en = 0;
we = 0;
addr = 0;
// store file for comparison
#clk_per @(posedge clk) #1;
$readmemh(`hex_file1, filemem);
@(posedge clk) #1;
en = 1;
// read from file stored in RAM
@(posedge clk) #1;
for (i = 0; i < 16; i = i + 1) begin
addr = i;
@(posedge clk) #1;
if (filemem[i] != data_out) begin
$display("Test failed: read error in position %d, where tb1.hex=%h but data_out=%h", i,
filemem[i], data_out);
$finish;
end
end
#clk_per $readmemh(`hex_file2, filemem);
// write into RAM and read from it
@(posedge clk) #1;
we = 1;
for (i = 0; i < 16; i = i + 1) begin
addr = i;
data_in = filemem[i];
@(posedge clk) #1;
end
@(posedge clk) #1;
we = 0;
@(posedge clk) #1;
for (i = 0; i < 16; i = i + 1) begin
addr = i;
@(posedge clk) #1;
if (filemem[i] != data_out) begin
$display("Test failed: write error in position %d, where tb2.hex=%h but data_out=%h", i,
filemem[i], data_out);
$finish;
end
end
@(posedge clk) #1;
en = 0;
#clk_per $display("%c[1;34m", 27);
$display("Test completed successfully.");
$display("%c[0m", 27);
#(5 * clk_per) $finish;
end
// Instantiate the Unit Under Test (UUT)
iob_sp_ram #(
.DATA_W(`DATA_W),
.ADDR_W(`ADDR_W),
.FILE (`hex_file1)
) uut (
.clk(clk),
.en(en),
.we(we),
.addr(addr),
.data_in(data_in),
.data_out(data_out)
);
// system clock
always #(clk_per / 2) clk = ~clk;
endmodule
| 6.993272 |
module sp_ram_wrap #(
parameter RAM_SIZE = 32768, // in bytes
parameter ADDR_WIDTH = $clog2(RAM_SIZE),
parameter DATA_WIDTH = 32
) (
`ifdef USE_POWER_PINS
vccd1, // User area 1 1.8V supply
vssd1, // User area 1 digital ground
`endif
clk,
rstn_i,
en_i,
addr_i,
wdata_i,
rdata_o,
we_i,
be_i,
bypass_en_i
);
//parameter RAM_SIZE = 32768;
//parameter ADDR_WIDTH = $clog2(RAM_SIZE);
//parameter DATA_WIDTH = 32;
`ifdef USE_POWER_PINS
inout wire vccd1;
inout wire vssd1;
`endif
input wire clk;
input wire rstn_i;
input wire en_i;
input wire [ADDR_WIDTH - 1:0] addr_i;
input wire [DATA_WIDTH - 1:0] wdata_i;
output wire [DATA_WIDTH - 1:0] rdata_o;
input wire we_i;
input wire [(DATA_WIDTH / 8) - 1:0] be_i;
input wire bypass_en_i;
wire [31:0] ram_out_int;
assign rdata_o = ram_out_int;
sky130_sram_2kbyte_1rw1r_32x512_8 open_ram_2k (
`ifdef USE_POWER_PINS
.vccd1 (vccd1),
.vssd1 (vssd1),
`endif
.clk0 (clk),
.csb0 (1'b0),
.web0 (~(we_i & ~bypass_en_i)),
.wmask0(be_i),
.addr0 (addr_i[10:2]),
.din0 (wdata_i),
.dout0 (ram_out_int),
.clk1 (1'b0),
.csb1 (1'b1),
.addr1 (9'b000000000),
.dout1 ()
);
endmodule
| 6.770199 |
module sp_rcv_ctrl (
clk,
reset,
sp_fifo_wrempty,
sp_fifo_wrfull,
write,
have_sp_data
);
input wire clk;
input wire sp_fifo_wrempty;
input wire sp_fifo_wrfull;
input wire reset;
output wire write;
output wire have_sp_data;
reg state;
reg wrenable;
always @(posedge clk) begin
if (reset) begin
wrenable <= 1'b0;
end
// load SP_fifo with 16k raw 16 bit ADC samples every time it is empty
case (state)
0: begin
if (sp_fifo_wrempty) begin // enable write to SP_fifo
wrenable <= 1'b1;
state <= 1'b1;
end
end
1: begin
if (sp_fifo_wrfull) begin // disable write to SP_fifo
wrenable <= 1'b0;
state <= 1'b0;
end
end
default: state <= 1'b0;
endcase
end
assign write = wrenable;
assign have_sp_data = !wrenable; // indicate data is availble to be read
endmodule
| 6.665428 |
module SP_RF_RAMModule_TopLevel (
// [BEGIN USER PORTS]
// [END USER PORTS]
input wire Clock,
input wire Reset,
input wire [7:0] Address,
input wire [7:0] WriteData,
input wire WE,
output wire [7:0] Data
);
// [BEGIN USER SIGNALS]
// [END USER SIGNALS]
localparam HiSignal = 1'b1;
localparam LoSignal = 1'b0;
wire Zero = 1'b0;
wire One = 1'b1;
wire true = 1'b1;
wire false = 1'b0;
wire [7:0] Inputs_Address;
wire [7:0] Inputs_WriteData;
wire Inputs_WE;
reg [7:0] State_ReadData;
reg [7:0] State_Buff[0 : 255];
initial begin : Init_State_Buff
integer i;
for (i = 0; i < 256; i = i + 1) State_Buff[i] = 0;
end
// inferred single port RAM with read-first behaviour
always @(posedge Clock) begin
if (Inputs_WE) State_Buff[Inputs_Address] <= Inputs_WriteData;
State_ReadData <= State_Buff[Inputs_Address];
end
assign Inputs_Address = Address;
assign Inputs_WriteData = WriteData;
assign Inputs_WE = WE;
assign Data = State_ReadData;
// [BEGIN USER ARCHITECTURE]
// [END USER ARCHITECTURE]
endmodule
| 6.922492 |
module sp_rom (
a_clk,
a_en,
a_addr,
a_dout
);
parameter INIT_FILE = "/mif/";
parameter DATA_WIDTH = 32;
parameter DATA_NUM = 100;
parameter ADDR_WIDTH = `CLOG2(DATA_NUM);
// Port A
input wire a_clk;
input wire a_en;
input wire [ADDR_WIDTH-1:0] a_addr;
output reg [DATA_WIDTH-1:0] a_dout;
// Shared memory
/*(* ram_style = "block" *)*/ reg [DATA_WIDTH-1:0] mem[DATA_NUM-1:0];
generate
if (INIT_FILE != 0) begin : init_gen
initial $readmemh(INIT_FILE, mem);
end
endgenerate
// Port A
always @(posedge a_clk) begin
if (a_en) a_dout <= mem[a_addr];
end
endmodule
| 7.727318 |
module sp_rom_tb;
//Inputs
reg clk;
reg r_en;
reg [`ADDR_W-1:0] addr;
//Ouptuts
reg [`DATA_W-1:0] rdata;
// .hex file
reg [7:0] filemem[0:15];
integer i;
parameter clk_per = 10; // clk period = 10 timeticks
initial begin
// optional VCD
`ifdef VCD
$dumpfile("sp_rom.vcd");
$dumpvars();
`endif
//Initialize Inputs
clk = 1;
r_en = 0;
addr = 0;
// store file for comparison
#clk_per @(posedge clk) #1;
$readmemh(`hex_file, filemem);
@(posedge clk) #1;
r_en = 1;
@(posedge clk) #1;
for (i = 0; i < 16; i = i + 1) begin
addr = i;
@(posedge clk) #1;
if (filemem[i] != rdata) begin
$display("Test failed: read error in position %d, where tb.hex=%h but rdata=%h", i,
filemem[i], rdata);
$finish;
end
end
@(posedge clk) #1;
r_en = 0;
#clk_per $display("%c[1;34m", 27);
$display("Test completed successfully.");
$display("%c[0m", 27);
#(5 * clk_per) $finish;
end
// Instantiate the Unit Under Test (UUT)
sp_rom #(
.DATA_W(`DATA_W),
.ADDR_W(`ADDR_W),
.FILE (`hex_file)
) uut (
.clk (clk),
.r_en (r_en),
.addr (addr),
.rdata(rdata)
);
// system clock
always #(clk_per / 2) clk = ~clk;
endmodule
| 7.689163 |
module sp_sync_fifo #(
parameter WIDTH = 8,
parameter DEPTH = 256,
parameter AWIDTH = `CLOG2(DEPTH)
) (
input rst,
input clk,
input wr,
input rd,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout,
output empty,
output full
);
reg [AWIDTH:0] rd_ptr, wr_ptr;
wire [WIDTH-1:0] ram_dout;
wire [AWIDTH-1:0] ram_addr;
reg wr1;
initial begin
wr1 <= 1'b0;
wr_ptr <= 0;
rd_ptr <= 0;
end
////////////////////////////////////////////////////////////////////////////
// FIFO STATUS
////////////////////////////////////////////////////////////////////////////
assign empty = (wr_ptr == rd_ptr);
assign full = ((wr_ptr[AWIDTH] != rd_ptr[AWIDTH]) && (wr_ptr[AWIDTH-1:0] == rd_ptr[AWIDTH-1:0]));
////////////////////////////////////////////////////////////////////////////
// FIFO POINTERS
////////////////////////////////////////////////////////////////////////////
always @(posedge clk or posedge rst) begin
if (rst) begin
wr1 <= 1'b0;
wr_ptr <= {1'b0, {(AWIDTH - 1) {1'b0}}};
rd_ptr <= {1'b0, {(AWIDTH - 1) {1'b0}}};
end else begin
wr1 <= 1'b0;
if (!full && wr) begin
wr1 <= 1'b1;
wr_ptr <= wr_ptr + 1;
if (wr_ptr[AWIDTH-1:0] == DEPTH) wr_ptr <= {1'b1, {(AWIDTH - 1) {1'b0}}};
end
if (!empty && rd) begin
rd_ptr <= rd_ptr + 1;
if (rd_ptr[AWIDTH-1:0] == DEPTH) rd_ptr <= {1'b1, {(AWIDTH - 1) {1'b0}}};
end
end
end
////////////////////////////////////////////////////////////////////////////
// RAM INTERFACE
////////////////////////////////////////////////////////////////////////////
assign dout = rst ? 0 : ((!empty && rd) ? ram_dout : dout);
assign ram_addr = wr1 ? wr_ptr : (rd ? rd_ptr[AWIDTH-1:0] : 0);
spram fifomem (
.clk (clk),
.we (wr),
.addr(ram_addr),
.din (din),
.dout(ram_dout)
);
defparam fifomem.DATA = WIDTH; defparam fifomem.ADDR = AWIDTH;
dump dumpsim ();
endmodule
| 6.882706 |
module Sp_top (
input clk,
input rst,
output [7:0] Seg,
output [7:0] Sel
);
wire [31:0] reg28;
wire [31:0] disp;
wire [31:0] pc_out;
reg [31:0] seg_idata;
reg [30:0] cnt;
reg clk_50m;
reg flag;
wire clk_cpu;
wire clk_seg;
wire halt;
// wire [31:0] instr;
//wire [31:0] seg_idata = rst ? 32'hffffffff : ((disp == 32'ha0602880) ? 32'ha0602880 : 32'h00000001);
// always @ (*)
// begin
// if(rst)
// begin
// seg_idata <= 32'hffffffff;
// flag <= 0;
// end
// if(disp == 32'ha0602880)
// begin
// seg_idata <= disp;
// flag <= 1;
// end
// else
// begin
// seg_idata <= 32'h00000001;
// end
// end
//assign halt = (disp == 32'ha0602880) ? 1 : 0;
sccomp_dataoverflow sc (
clk_cpu,
rst,
halt,
//instr,
disp,
pc_out,
reg28
);
Seg7x16 segdt (
clk,
rst,
1'b1,
reg28,
Seg,
Sel
);
divider div (
clk,
rst,
clk_seg,
clk_cpu
);
endmodule
| 6.623897 |
module SP_WF_RAMModule_TopLevel (
// [BEGIN USER PORTS]
// [END USER PORTS]
input wire Clock,
input wire Reset,
input wire [7:0] Address,
input wire [7:0] WriteData,
input wire WE,
output wire [7:0] Data
);
// [BEGIN USER SIGNALS]
// [END USER SIGNALS]
localparam HiSignal = 1'b1;
localparam LoSignal = 1'b0;
wire Zero = 1'b0;
wire One = 1'b1;
wire true = 1'b1;
wire false = 1'b0;
wire [7:0] Inputs_Address;
wire [7:0] Inputs_WriteData;
wire Inputs_WE;
wire [7:0] State_ReadData;
reg [7:0] State_Buff[0 : 255];
initial begin : Init_State_Buff
integer i;
for (i = 0; i < 256; i = i + 1) State_Buff[i] = 0;
end
reg [8-1:0] Inputs_Address_reg;
// inferred single port RAM with write-first behaviour
always @(posedge Clock) begin
if (Inputs_WE) State_Buff[Inputs_Address] <= Inputs_WriteData;
Inputs_Address_reg <= Inputs_Address;
end
assign State_ReadData = State_Buff[Inputs_Address_reg];
assign Inputs_Address = Address;
assign Inputs_WriteData = WriteData;
assign Inputs_WE = WE;
assign Data = State_ReadData;
// [BEGIN USER ARCHITECTURE]
// [END USER ARCHITECTURE]
endmodule
| 7.110217 |
module Sort (
clk,
rst_n,
in0,
in1,
in2,
in3,
in4,
in5,
out0,
out1,
out2,
out3,
out4,
out5
);
//================================================================
// INPUT AND OUTPUT DECLARATION
//================================================================
input clk, rst_n;
input [8:0] in0, in1, in2, in3, in4, in5;
output [8:0] out0, out1, out2, out3, out4, out5;
//================================================================
// Wire & Registers
//================================================================
wire [8:0] a[0:3], b[0:2], c[0:3], d[0:2], f[0:3], g[0:1];
reg [8:0] e[0:5];
//================================================================
// DESIGN
//================================================================
//
assign a[0] = (in0 < in1) ? in0 : in1;
assign a[1] = (in0 < in1) ? in1 : in0;
assign a[2] = (a[1] < in2) ? a[1] : in2;
assign a[3] = (a[1] < in2) ? in2 : a[1];
assign b[0] = (a[0] < a[2]) ? a[0] : a[2];
assign b[1] = (a[0] < a[2]) ? a[2] : a[0];
assign b[2] = a[3];
//
assign c[0] = (in3 < in4) ? in3 : in4;
assign c[1] = (in3 < in4) ? in4 : in3;
assign c[2] = (c[1] < in5) ? c[1] : in5;
assign c[3] = (c[1] < in5) ? in5 : c[1];
assign d[0] = (c[0] < c[2]) ? c[0] : c[2];
assign d[1] = (c[0] < c[2]) ? c[2] : c[0];
assign d[2] = c[3];
//
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
e[0] <= 0;
e[1] <= 0;
e[2] <= 0;
e[3] <= 0;
e[4] <= 0;
e[5] <= 0;
end else begin
e[0] <= (b[0] < d[0]) ? b[0] : d[0];
e[1] <= (b[0] < d[0]) ? d[0] : b[0];
e[2] <= (b[1] < d[1]) ? b[1] : d[1];
e[3] <= (b[1] < d[1]) ? d[1] : b[1];
e[4] <= (b[2] < d[2]) ? b[2] : d[2];
e[5] <= (b[2] < d[2]) ? d[2] : b[2];
end
end
/*
assign e[0] = ( b[0]<d[0] ) ? b[0] : d[0] ;
assign e[1] = ( b[0]<d[0] ) ? d[0] : b[0] ;
assign e[2] = ( b[1]<d[1] ) ? b[1] : d[1] ;
assign e[3] = ( b[1]<d[1] ) ? d[1] : b[1] ;
assign e[4] = ( b[2]<d[2] ) ? b[2] : d[2] ;
assign e[5] = ( b[2]<d[2] ) ? d[2] : b[2] ;
*/
//
assign out0 = e[0];
assign out5 = e[5];
//
assign f[0] = (e[1] < e[2]) ? e[1] : e[2];
assign f[1] = (e[1] < e[2]) ? e[2] : e[1];
assign f[2] = (e[3] < e[4]) ? e[3] : e[4];
assign f[3] = (e[3] < e[4]) ? e[4] : e[3];
//
assign out1 = f[0];
assign out4 = f[3];
//
assign g[0] = (f[1] < f[2]) ? f[1] : f[2];
assign g[1] = (f[1] < f[2]) ? f[2] : f[1];
//
assign out2 = g[0];
assign out3 = g[1];
endmodule
| 6.626478 |
module of our architecture.
Use this please cite:
[1] Yang. Zhijie, Wang. Lei, et al., "Bactran: A Hardware Batch Normalization Implementation for CNN Training Engine," in IEEE Embedded Systems Letters, vol. 13, no. 1, pp. 29-32, March 2021.
This code follows the MIT License
Copyright (c) 2021 Yang Zhijie and Wang Lei of National University of Defense Technology, P.R.China
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
module sqa(
stan_dev_in,
avg_in,
valid_in,
valid_out,
var_out,
avg_out
);
parameter DATA_WIDTH = 16;
parameter MINI_BATCH = 64;
parameter ADDR_WIDTH = $clog2(MINI_BATCH);
input signed [DATA_WIDTH-1:0] stan_dev_in;
input signed [DATA_WIDTH-1:0] avg_in;
input valid_in;
output valid_out;
output signed [DATA_WIDTH-1:0] var_out;
output signed [DATA_WIDTH-1:0] avg_out;
assign var_out = valid_in?(stan_dev_in*stan_dev_in):{DATA_WIDTH{1'b0}};
assign avg_out = valid_in?avg_in:{DATA_WIDTH{1'b0}};
assign valid_out = valid_in?valid_in:1'b0;
endmodule
| 6.78689 |
module buffer (
i,
o
);
input i;
output o;
endmodule
| 6.861394 |
module std_const #(
parameter WIDTH = 32,
parameter VALUE = 0
) (
output logic [WIDTH - 1:0] out
);
assign out = VALUE;
endmodule
| 8.794277 |
module std_wire #(
parameter WIDTH = 32
) (
input wire logic [WIDTH - 1:0] in,
output logic [WIDTH - 1:0] out
);
assign out = in;
endmodule
| 8.485736 |
module std_slice #(
parameter IN_WIDTH = 32,
parameter OUT_WIDTH = 32
) (
input wire logic [ IN_WIDTH-1:0] in,
output logic [OUT_WIDTH-1:0] out
);
assign out = in[OUT_WIDTH-1:0];
`ifdef VERILATOR
always_comb begin
if (IN_WIDTH < OUT_WIDTH)
$error(
"std_slice: Input width less than output width\n",
"IN_WIDTH: %0d",
IN_WIDTH,
"OUT_WIDTH: %0d",
OUT_WIDTH
);
end
`endif
endmodule
| 8.248138 |
module std_pad #(
parameter IN_WIDTH = 32,
parameter OUT_WIDTH = 32
) (
input wire logic [ IN_WIDTH-1:0] in,
output logic [OUT_WIDTH-1:0] out
);
localparam EXTEND = OUT_WIDTH - IN_WIDTH;
assign out = {{EXTEND{1'b0}}, in};
`ifdef VERILATOR
always_comb begin
if (IN_WIDTH > OUT_WIDTH)
$error(
"std_pad: Output width less than input width\n",
"IN_WIDTH: %0d",
IN_WIDTH,
"OUT_WIDTH: %0d",
OUT_WIDTH
);
end
`endif
endmodule
| 8.450332 |
module std_not #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] in,
output logic [WIDTH-1:0] out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_not1_1 _impl (
in,
out
);
end else if (WIDTH == 8) begin
lakeroad_xilinx_ultrascale_plus_not8_1 _impl (
in,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 8.707194 |
module std_and #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_and1_2 _impl (
left,
right,
out
);
end else if (WIDTH == 32) begin
lakeroad_xilinx_ultrascale_plus_and32_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 8.159461 |
module std_or #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_or1_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 8.160076 |
module std_xor #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
// if (WIDTH == x) begin
// lakeroad_xilinx_ultrascale_plus_op _impl(in, out);
// end
// //else begin
$error("Unsupported bitwidth %0d", WIDTH);
// end
endmodule
| 8.185133 |
module std_add #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 2) begin
lakeroad_xilinx_ultrascale_plus_add2_2 _impl (
left,
right,
out
);
end else if (WIDTH == 3) begin
lakeroad_xilinx_ultrascale_plus_add3_2 _impl (
left,
right,
out
);
end else if (WIDTH == 4) begin
lakeroad_xilinx_ultrascale_plus_add4_2 _impl (
left,
right,
out
);
end else if (WIDTH == 8) begin
lakeroad_xilinx_ultrascale_plus_add8_2 _impl (
left,
right,
out
);
end else if (WIDTH == 32) begin
lakeroad_xilinx_ultrascale_plus_add32_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 7.105468 |
module std_sub #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 5) begin
lakeroad_xilinx_ultrascale_plus_sub5_2 _impl (
left,
right,
out
);
end else if (WIDTH == 6) begin
lakeroad_xilinx_ultrascale_plus_sub6_2 _impl (
left,
right,
out
);
end else if (WIDTH == 32) begin
lakeroad_xilinx_ultrascale_plus_sub32_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 7.29825 |
module std_gt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 5) begin
lakeroad_xilinx_ultrascale_plus_ugt5_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 7.445889 |
module std_lt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 3) begin
lakeroad_xilinx_ultrascale_plus_ult3_2 _impl (
left,
right,
out
);
end else if (WIDTH == 4) begin
lakeroad_xilinx_ultrascale_plus_ult4_2 _impl (
left,
right,
out
);
end else if (WIDTH == 32) begin
lakeroad_xilinx_ultrascale_plus_ult32_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 7.925865 |
module std_eq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_eq1_2 _impl (
left,
right,
out
);
end else if (WIDTH == 5) begin
lakeroad_xilinx_ultrascale_plus_eq5_2 _impl (
left,
right,
out
);
end else if (WIDTH == 6) begin
lakeroad_xilinx_ultrascale_plus_eq6_2 _impl (
left,
right,
out
);
end else if (WIDTH == 32) begin
lakeroad_xilinx_ultrascale_plus_eq32_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 8.155468 |
module std_neq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (0 == 1) begin
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 7.624981 |
module std_ge #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (0 == 1) begin
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 6.896227 |
module std_le #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 4) begin
lakeroad_xilinx_ultrascale_plus_ule4_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 8.161124 |
module std_lsh #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left << right;
endmodule
| 8.684363 |
module std_rsh #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left >> right;
endmodule
| 8.622539 |
module std_mux #(
parameter WIDTH = 32
) (
input wire logic cond,
input wire logic [WIDTH-1:0] tru,
input wire logic [WIDTH-1:0] fal,
output logic [WIDTH-1:0] out
);
assign out = cond ? tru : fal;
endmodule
| 9.56204 |
module std_reg #(
parameter WIDTH = 32
) (
input wire [ WIDTH-1:0] in,
input wire write_en,
input wire clk,
input wire reset,
// output
output logic [WIDTH - 1:0] out,
output logic done
);
always_ff @(posedge clk) begin
if (reset) begin
out <= 0;
done <= 0;
end else if (write_en) begin
out <= in;
done <= 1'd1;
end else done <= 1'd0;
end
endmodule
| 7.672256 |
module std_mem_d1 #(
parameter WIDTH = 32,
parameter SIZE = 16,
parameter IDX_SIZE = 4
) (
input wire logic [IDX_SIZE-1:0] addr0,
input wire logic [ WIDTH-1:0] write_data,
input wire logic write_en,
input wire logic clk,
output logic [ WIDTH-1:0] read_data,
output logic done
);
logic [WIDTH-1:0] mem[SIZE-1:0];
/* verilator lint_off WIDTH */
assign read_data = mem[addr0];
always_ff @(posedge clk) begin
if (write_en) begin
mem[addr0] <= write_data;
done <= 1'd1;
end else done <= 1'd0;
end
// Check for out of bounds access
`ifdef VERILATOR
always_comb begin
if (addr0 >= SIZE)
$error("std_mem_d1: Out of bounds access\n", "addr0: %0d\n", addr0, "SIZE: %0d", SIZE);
end
`endif
endmodule
| 8.560454 |
module std_mem_d2 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE-1:0] addr0,
input wire logic [D1_IDX_SIZE-1:0] addr1,
input wire logic [ WIDTH-1:0] write_data,
input wire logic write_en,
input wire logic clk,
output logic [ WIDTH-1:0] read_data,
output logic done
);
/* verilator lint_off WIDTH */
logic [WIDTH-1:0] mem[D0_SIZE-1:0][D1_SIZE-1:0];
assign read_data = mem[addr0][addr1];
always_ff @(posedge clk) begin
if (write_en) begin
mem[addr0][addr1] <= write_data;
done <= 1'd1;
end else done <= 1'd0;
end
// Check for out of bounds access
`ifdef VERILATOR
always_comb begin
if (addr0 >= D0_SIZE)
$error("std_mem_d2: Out of bounds access\n", "addr0: %0d\n", addr0, "D0_SIZE: %0d", D0_SIZE);
if (addr1 >= D1_SIZE)
$error("std_mem_d2: Out of bounds access\n", "addr1: %0d\n", addr1, "D1_SIZE: %0d", D1_SIZE);
end
`endif
endmodule
| 8.570777 |
module std_mem_d3 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D2_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4,
parameter D2_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE-1:0] addr0,
input wire logic [D1_IDX_SIZE-1:0] addr1,
input wire logic [D2_IDX_SIZE-1:0] addr2,
input wire logic [ WIDTH-1:0] write_data,
input wire logic write_en,
input wire logic clk,
output logic [ WIDTH-1:0] read_data,
output logic done
);
/* verilator lint_off WIDTH */
logic [WIDTH-1:0] mem[D0_SIZE-1:0][D1_SIZE-1:0][D2_SIZE-1:0];
assign read_data = mem[addr0][addr1][addr2];
always_ff @(posedge clk) begin
if (write_en) begin
mem[addr0][addr1][addr2] <= write_data;
done <= 1'd1;
end else done <= 1'd0;
end
// Check for out of bounds access
`ifdef VERILATOR
always_comb begin
if (addr0 >= D0_SIZE)
$error("std_mem_d3: Out of bounds access\n", "addr0: %0d\n", addr0, "D0_SIZE: %0d", D0_SIZE);
if (addr1 >= D1_SIZE)
$error("std_mem_d3: Out of bounds access\n", "addr1: %0d\n", addr1, "D1_SIZE: %0d", D1_SIZE);
if (addr2 >= D2_SIZE)
$error("std_mem_d3: Out of bounds access\n", "addr2: %0d\n", addr2, "D2_SIZE: %0d", D2_SIZE);
end
`endif
endmodule
| 9.018781 |
module std_mem_d4 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D2_SIZE = 16,
parameter D3_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4,
parameter D2_IDX_SIZE = 4,
parameter D3_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE-1:0] addr0,
input wire logic [D1_IDX_SIZE-1:0] addr1,
input wire logic [D2_IDX_SIZE-1:0] addr2,
input wire logic [D3_IDX_SIZE-1:0] addr3,
input wire logic [ WIDTH-1:0] write_data,
input wire logic write_en,
input wire logic clk,
output logic [ WIDTH-1:0] read_data,
output logic done
);
/* verilator lint_off WIDTH */
logic [WIDTH-1:0] mem[D0_SIZE-1:0][D1_SIZE-1:0][D2_SIZE-1:0][D3_SIZE-1:0];
assign read_data = mem[addr0][addr1][addr2][addr3];
always_ff @(posedge clk) begin
if (write_en) begin
mem[addr0][addr1][addr2][addr3] <= write_data;
done <= 1'd1;
end else done <= 1'd0;
end
// Check for out of bounds access
`ifdef VERILATOR
always_comb begin
if (addr0 >= D0_SIZE)
$error("std_mem_d4: Out of bounds access\n", "addr0: %0d\n", addr0, "D0_SIZE: %0d", D0_SIZE);
if (addr1 >= D1_SIZE)
$error("std_mem_d4: Out of bounds access\n", "addr1: %0d\n", addr1, "D1_SIZE: %0d", D1_SIZE);
if (addr2 >= D2_SIZE)
$error("std_mem_d4: Out of bounds access\n", "addr2: %0d\n", addr2, "D2_SIZE: %0d", D2_SIZE);
if (addr3 >= D3_SIZE)
$error("std_mem_d4: Out of bounds access\n", "addr3: %0d\n", addr3, "D3_SIZE: %0d", D3_SIZE);
end
`endif
endmodule
| 9.168498 |
module fp_sqrt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic clk,
input logic reset,
input logic go,
input logic [WIDTH-1:0] in,
output logic [WIDTH-1:0] out,
output logic done
);
localparam ITERATIONS = WIDTH + FRAC_WIDTH >> 1;
logic [$clog2(ITERATIONS)-1:0] idx;
logic [WIDTH-1:0] x, x_next;
logic [WIDTH-1:0] quotient, quotient_next;
logic [WIDTH+1:0] acc, acc_next;
logic [WIDTH+1:0] tmp;
logic start, running, finished;
assign start = go && !running;
/* verilator lint_off WIDTH */
assign finished = (ITERATIONS - 1) == idx && running;
always_ff @(posedge clk) begin
if (reset || finished) running <= 0;
else if (start) running <= 1;
else running <= running;
end
always_ff @(posedge clk) begin
if (running) idx <= idx + 1;
else idx <= 0;
end
always_comb begin
tmp = acc - {quotient, 2'b01};
if (tmp[WIDTH+1]) begin
// tmp is negative.
{acc_next, x_next} = {acc[WIDTH-1:0], x, 2'b0};
// Append a 0 to the result.
quotient_next = quotient << 1;
end else begin
// tmp is positive.
{acc_next, x_next} = {tmp[WIDTH-1:0], x, 2'b0};
// Append a 1 to the result.
quotient_next = {quotient[WIDTH-2:0], 1'b1};
end
end
always_ff @(posedge clk) begin
if (start) begin
quotient <= 0;
{acc, x} <= {{WIDTH{1'b0}}, in, 2'b0};
end else begin
x <= x_next;
acc <= acc_next;
quotient <= quotient_next;
end
end
always_ff @(posedge clk) begin
if (finished) begin
done <= 1;
out <= quotient_next;
end else if (reset) begin
done <= 0;
out <= 0;
end else begin
done <= 0;
out <= out;
end
end
endmodule
| 7.054716 |
module std_fp_add #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left + right;
endmodule
| 9.124708 |
module std_fp_sub #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left - right;
endmodule
| 8.85803 |
module std_fp_mult_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16,
parameter SIGNED = 0
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
input logic go,
input logic clk,
input logic reset,
output logic [WIDTH-1:0] out,
output logic done
);
logic [ WIDTH-1:0] rtmp;
logic [ WIDTH-1:0] ltmp;
logic [(WIDTH << 1) - 1:0] out_tmp;
// Buffer used to walk through the 3 cycles of the pipeline.
logic done_buf[2:0];
assign done = done_buf[2];
assign out = out_tmp[(WIDTH<<1)-INT_WIDTH-1 : WIDTH-INT_WIDTH];
// If the done buffer is completely empty and go is high then execution
// just started.
logic start;
assign start = go & done_buf[0] == 0 & done_buf[1] == 0;
// Start sending the done signal.
always_ff @(posedge clk) begin
if (start) done_buf[0] <= 1;
else done_buf[0] <= 0;
end
// Push the done signal through the pipeline.
always_ff @(posedge clk) begin
if (go) begin
done_buf[2] <= done_buf[1];
done_buf[1] <= done_buf[0];
end else begin
done_buf[2] <= 0;
done_buf[1] <= 0;
end
end
// Move the multiplication computation through the pipeline.
always_ff @(posedge clk) begin
if (reset) begin
rtmp <= 0;
ltmp <= 0;
out_tmp <= 0;
end else if (go) begin
if (SIGNED) begin
rtmp <= $signed(right);
ltmp <= $signed(left);
out_tmp <= $signed({{WIDTH{ltmp[WIDTH-1]}}, ltmp} * {{WIDTH{rtmp[WIDTH-1]}}, rtmp});
end else begin
rtmp <= right;
ltmp <= left;
out_tmp <= ltmp * rtmp;
end
end else begin
rtmp <= 0;
ltmp <= 0;
out_tmp <= out_tmp;
end
end
endmodule
| 6.609331 |
module std_fp_div_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic go,
input logic clk,
input logic reset,
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out_remainder,
output logic [WIDTH-1:0] out_quotient,
output logic done
);
localparam ITERATIONS = WIDTH + FRAC_WIDTH;
logic [WIDTH-1:0] quotient, quotient_next;
logic [WIDTH:0] acc, acc_next;
logic [$clog2(ITERATIONS)-1:0] idx;
logic start, running, finished, dividend_is_zero;
assign start = go && !running;
assign dividend_is_zero = start && left == 0;
assign finished = idx == ITERATIONS - 1 && running;
always_ff @(posedge clk) begin
if (reset || finished || dividend_is_zero) running <= 0;
else if (start) running <= 1;
else running <= running;
end
always_comb begin
if (acc >= {1'b0, right}) begin
acc_next = acc - right;
{acc_next, quotient_next} = {acc_next[WIDTH-1:0], quotient, 1'b1};
end else begin
{acc_next, quotient_next} = {acc, quotient} << 1;
end
end
// `done` signaling
always_ff @(posedge clk) begin
if (dividend_is_zero || finished) done <= 1;
else done <= 0;
end
always_ff @(posedge clk) begin
if (running) idx <= idx + 1;
else idx <= 0;
end
always_ff @(posedge clk) begin
if (reset) begin
out_quotient <= 0;
out_remainder <= 0;
end else if (start) begin
out_quotient <= 0;
out_remainder <= left;
end else if (go == 0) begin
out_quotient <= out_quotient;
out_remainder <= out_remainder;
end else if (dividend_is_zero) begin
out_quotient <= 0;
out_remainder <= 0;
end else if (finished) begin
out_quotient <= quotient_next;
out_remainder <= out_remainder;
end else begin
out_quotient <= out_quotient;
if (right <= out_remainder) out_remainder <= out_remainder - right;
else out_remainder <= out_remainder;
end
end
always_ff @(posedge clk) begin
if (reset) begin
acc <= 0;
quotient <= 0;
end else if (start) begin
{acc, quotient} <= {{WIDTH{1'b0}}, left, 1'b0};
end else begin
acc <= acc_next;
quotient <= quotient_next;
end
end
endmodule
| 7.871496 |
module std_fp_gt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic out
);
assign out = left > right;
endmodule
| 8.426383 |
module std_fp_sadd #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left + right);
endmodule
| 8.768295 |
module std_fp_ssub #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left - right);
endmodule
| 8.839041 |
module std_fp_smult_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input [WIDTH-1:0] left,
input [WIDTH-1:0] right,
input logic reset,
input logic go,
input logic clk,
output logic [WIDTH-1:0] out,
output logic done
);
std_fp_mult_pipe #(
.WIDTH(WIDTH),
.INT_WIDTH(INT_WIDTH),
.FRAC_WIDTH(FRAC_WIDTH),
.SIGNED(1)
) comp (
.clk(clk),
.done(done),
.reset(reset),
.go(go),
.left(left),
.right(right),
.out(out)
);
endmodule
| 7.173413 |
module std_fp_sdiv_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input clk,
input go,
input reset,
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out_quotient,
output signed [WIDTH-1:0] out_remainder,
output logic done
);
logic signed [WIDTH-1:0]
left_abs, right_abs, comp_out_q, comp_out_r, right_save, out_rem_intermediate;
// Registers to figure out how to transform outputs.
logic different_signs, left_sign, right_sign;
// Latch the value of control registers so that their available after
// go signal becomes low.
always_ff @(posedge clk) begin
if (go) begin
right_save <= right_abs;
left_sign <= left[WIDTH-1];
right_sign <= right[WIDTH-1];
end else begin
left_sign <= left_sign;
right_save <= right_save;
right_sign <= right_sign;
end
end
assign right_abs = right[WIDTH-1] ? -right : right;
assign left_abs = left[WIDTH-1] ? -left : left;
assign different_signs = left_sign ^ right_sign;
assign out_quotient = different_signs ? -comp_out_q : comp_out_q;
// Remainder is computed as:
// t0 = |left| % |right|
// t1 = if left * right < 0 and t0 != 0 then |right| - t0 else t0
// rem = if right < 0 then -t1 else t1
assign out_rem_intermediate = different_signs & |comp_out_r ? $signed(
right_save - comp_out_r
) : comp_out_r;
assign out_remainder = right_sign ? -out_rem_intermediate : out_rem_intermediate;
std_fp_div_pipe #(
.WIDTH(WIDTH),
.INT_WIDTH(INT_WIDTH),
.FRAC_WIDTH(FRAC_WIDTH)
) comp (
.reset(reset),
.clk(clk),
.done(done),
.go(go),
.left(left_abs),
.right(right_abs),
.out_quotient(comp_out_q),
.out_remainder(comp_out_r)
);
endmodule
| 8.37227 |
module std_fp_sgt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed out
);
assign out = $signed(left > right);
endmodule
| 8.236193 |
module std_fp_slt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed out
);
assign out = $signed(left < right);
endmodule
| 8.595041 |
module std_mult_pipe #(
parameter WIDTH = 32
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
input logic reset,
input logic go,
input logic clk,
output logic [WIDTH-1:0] out,
output logic done
);
std_fp_mult_pipe #(
.WIDTH(WIDTH),
.INT_WIDTH(WIDTH),
.FRAC_WIDTH(0),
.SIGNED(0)
) comp (
.reset(reset),
.clk(clk),
.done(done),
.go(go),
.left(left),
.right(right),
.out(out)
);
endmodule
| 7.504255 |
module std_div_pipe #(
parameter WIDTH = 32
) (
input reset,
input clk,
input go,
input [WIDTH-1:0] left,
input [WIDTH-1:0] right,
output logic [WIDTH-1:0] out_remainder,
output logic [WIDTH-1:0] out_quotient,
output logic done
);
logic [WIDTH-1:0] dividend;
logic [(WIDTH-1)*2:0] divisor;
logic [WIDTH-1:0] quotient;
logic [WIDTH-1:0] quotient_msk;
logic start, running, finished, dividend_is_zero;
assign start = go && !running;
assign finished = quotient_msk == 0 && running;
assign dividend_is_zero = start && left == 0;
always_ff @(posedge clk) begin
// Early return if the divisor is zero.
if (finished || dividend_is_zero) done <= 1;
else done <= 0;
end
always_ff @(posedge clk) begin
if (reset || finished || dividend_is_zero) running <= 0;
else if (start) running <= 1;
else running <= running;
end
// Outputs
always_ff @(posedge clk) begin
if (dividend_is_zero || start) begin
out_quotient <= 0;
out_remainder <= 0;
end else if (finished) begin
out_quotient <= quotient;
out_remainder <= dividend;
end else begin
// Otherwise, explicitly latch the values.
out_quotient <= out_quotient;
out_remainder <= out_remainder;
end
end
// Calculate the quotient mask.
always_ff @(posedge clk) begin
if (start) quotient_msk <= 1 << WIDTH - 1;
else if (running) quotient_msk <= quotient_msk >> 1;
else quotient_msk <= quotient_msk;
end
// Calculate the quotient.
always_ff @(posedge clk) begin
if (start) quotient <= 0;
else if (divisor <= dividend) quotient <= quotient | quotient_msk;
else quotient <= quotient;
end
// Calculate the dividend.
always_ff @(posedge clk) begin
if (start) dividend <= left;
else if (divisor <= dividend) dividend <= dividend - divisor;
else dividend <= dividend;
end
always_ff @(posedge clk) begin
if (start) begin
divisor <= right << WIDTH - 1;
end else if (finished) begin
divisor <= 0;
end else begin
divisor <= divisor >> 1;
end
end
// Simulation self test against unsynthesizable implementation.
`ifdef VERILATOR
logic [WIDTH-1:0] l, r;
always_ff @(posedge clk) begin
if (go) begin
l <= left;
r <= right;
end else begin
l <= l;
r <= r;
end
end
always @(posedge clk) begin
if (done && $unsigned(out_remainder) != $unsigned(l % r))
$error(
"\nstd_div_pipe (Remainder): Computed and golden outputs do not match!\n",
"left: %0d",
$unsigned(
l
),
" right: %0d\n",
$unsigned(
r
),
"expected: %0d",
$unsigned(
l % r
),
" computed: %0d",
$unsigned(
out_remainder
)
);
if (done && $unsigned(out_quotient) != $unsigned(l / r))
$error(
"\nstd_div_pipe (Quotient): Computed and golden outputs do not match!\n",
"left: %0d",
$unsigned(
l
),
" right: %0d\n",
$unsigned(
r
),
"expected: %0d",
$unsigned(
l / r
),
" computed: %0d",
$unsigned(
out_quotient
)
);
end
`endif
endmodule
| 6.929139 |
module std_sadd #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left + right);
endmodule
| 8.670882 |
module std_ssub #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left - right);
endmodule
| 8.103836 |
module std_smult_pipe #(
parameter WIDTH = 32
) (
input logic reset,
input logic go,
input logic clk,
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output logic signed [WIDTH-1:0] out,
output logic done
);
std_fp_mult_pipe #(
.WIDTH(WIDTH),
.INT_WIDTH(WIDTH),
.FRAC_WIDTH(0),
.SIGNED(1)
) comp (
.reset(reset),
.clk(clk),
.done(done),
.go(go),
.left(left),
.right(right),
.out(out)
);
endmodule
| 6.968167 |
module std_sdiv_pipe #(
parameter WIDTH = 32
) (
input reset,
input clk,
input go,
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed [WIDTH-1:0] out_quotient,
output logic signed [WIDTH-1:0] out_remainder,
output logic done
);
logic signed [WIDTH-1:0]
left_abs, right_abs, comp_out_q, comp_out_r, right_save, out_rem_intermediate;
// Registers to figure out how to transform outputs.
logic different_signs, left_sign, right_sign;
// Latch the value of control registers so that their available after
// go signal becomes low.
always_ff @(posedge clk) begin
if (go) begin
right_save <= right_abs;
left_sign <= left[WIDTH-1];
right_sign <= right[WIDTH-1];
end else begin
left_sign <= left_sign;
right_save <= right_save;
right_sign <= right_sign;
end
end
assign right_abs = right[WIDTH-1] ? -right : right;
assign left_abs = left[WIDTH-1] ? -left : left;
assign different_signs = left_sign ^ right_sign;
assign out_quotient = different_signs ? -comp_out_q : comp_out_q;
// Remainder is computed as:
// t0 = |left| % |right|
// t1 = if left * right < 0 and t0 != 0 then |right| - t0 else t0
// rem = if right < 0 then -t1 else t1
assign out_rem_intermediate = different_signs & |comp_out_r ? $signed(
right_save - comp_out_r
) : comp_out_r;
assign out_remainder = right_sign ? -out_rem_intermediate : out_rem_intermediate;
std_div_pipe #(
.WIDTH(WIDTH)
) comp (
.reset(reset),
.clk(clk),
.done(done),
.go(go),
.left(left_abs),
.right(right_abs),
.out_quotient(comp_out_q),
.out_remainder(comp_out_r)
);
// Simulation self test against unsynthesizable implementation.
`ifdef VERILATOR
logic signed [WIDTH-1:0] l, r;
always_ff @(posedge clk) begin
if (go) begin
l <= left;
r <= right;
end else begin
l <= l;
r <= r;
end
end
always @(posedge clk) begin
if (done && out_quotient != $signed(l / r))
$error(
"\nstd_sdiv_pipe (Quotient): Computed and golden outputs do not match!\n",
"left: %0d",
l,
" right: %0d\n",
r,
"expected: %0d",
$signed(
l / r
),
" computed: %0d",
$signed(
out_quotient
),
);
if (done && out_remainder != $signed(((l % r) + r) % r))
$error(
"\nstd_sdiv_pipe (Remainder): Computed and golden outputs do not match!\n",
"left: %0d",
l,
" right: %0d\n",
r,
"expected: %0d",
$signed(
((l % r) + r) % r
),
" computed: %0d",
$signed(
out_remainder
),
);
end
`endif
endmodule
| 7.505299 |
module std_sgt #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left > right);
endmodule
| 7.663941 |
module std_slt #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left < right);
endmodule
| 8.095256 |
module std_seq #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left == right);
endmodule
| 8.302327 |
module std_sneq #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left != right);
endmodule
| 7.44378 |
module std_sge #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left >= right);
endmodule
| 7.297458 |
module std_sle #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left <= right);
endmodule
| 8.057164 |
module std_slsh #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = left <<< right;
endmodule
| 7.70425 |
module std_srsh #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = left >>> right;
endmodule
| 8.663189 |
module std_const #(
parameter WIDTH = 32,
parameter VALUE = 0
) (
output logic [WIDTH - 1:0] out
);
assign out = VALUE;
endmodule
| 8.794277 |
module std_wire #(
parameter WIDTH = 32
) (
input wire logic [WIDTH - 1:0] in,
output logic [WIDTH - 1:0] out
);
assign out = in;
endmodule
| 8.485736 |
module std_slice #(
parameter IN_WIDTH = 32,
parameter OUT_WIDTH = 32
) (
input wire logic [ IN_WIDTH-1:0] in,
output logic [OUT_WIDTH-1:0] out
);
assign out = in[OUT_WIDTH-1:0];
`ifdef VERILATOR
always_comb begin
if (IN_WIDTH < OUT_WIDTH)
$error(
"std_slice: Input width less than output width\n",
"IN_WIDTH: %0d",
IN_WIDTH,
"OUT_WIDTH: %0d",
OUT_WIDTH
);
end
`endif
endmodule
| 8.248138 |
module std_pad #(
parameter IN_WIDTH = 32,
parameter OUT_WIDTH = 32
) (
input wire logic [ IN_WIDTH-1:0] in,
output logic [OUT_WIDTH-1:0] out
);
localparam EXTEND = OUT_WIDTH - IN_WIDTH;
assign out = {{EXTEND{1'b0}}, in};
`ifdef VERILATOR
always_comb begin
if (IN_WIDTH > OUT_WIDTH)
$error(
"std_pad: Output width less than input width\n",
"IN_WIDTH: %0d",
IN_WIDTH,
"OUT_WIDTH: %0d",
OUT_WIDTH
);
end
`endif
endmodule
| 8.450332 |
module std_not #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] in,
output logic [WIDTH-1:0] out
);
assign out = ~in;
endmodule
| 8.707194 |
module std_and #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left & right;
endmodule
| 8.159461 |
module std_or #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left | right;
endmodule
| 8.160076 |
module std_xor #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left ^ right;
endmodule
| 8.185133 |
module std_add #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left + right;
endmodule
| 7.105468 |
module std_sub #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left - right;
endmodule
| 7.29825 |
module std_gt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left > right;
endmodule
| 7.445889 |
module std_lt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left < right;
endmodule
| 7.925865 |
module std_eq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left == right;
endmodule
| 8.155468 |
module std_neq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left != right;
endmodule
| 7.624981 |
module std_ge #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left >= right;
endmodule
| 6.896227 |
module std_le #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left <= right;
endmodule
| 8.161124 |
module std_lsh #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left << right;
endmodule
| 8.684363 |
module std_rsh #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left >> right;
endmodule
| 8.622539 |
module std_mux #(
parameter WIDTH = 32
) (
input wire logic cond,
input wire logic [WIDTH-1:0] tru,
input wire logic [WIDTH-1:0] fal,
output logic [WIDTH-1:0] out
);
assign out = cond ? tru : fal;
endmodule
| 9.56204 |
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