code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module H_driver (
input clk,
input sel2,
input in1,
input in2,
output out1,
output out2
);
reg r_out1, r_out2;
always @(*) begin
case (sel2)
0: r_out1 <= in1;
1: r_out1 <= 0;
endcase
case (sel2)
0: r_out2 <= 0;
1: r_out2 <= in2;
endcase
end
a... | 6.527644 |
module sel2 (
input clk,
input [5:0] sel1,
output sel2
);
reg r_sel2 = 0;
always @(posedge clk) begin
if (sel1 <= 0) r_sel2 <= ~r_sel2;
end
assign sel2 = r_sel2;
endmodule
| 7.289997 |
module clk_enable (
input clk,
output CE //clock enable
);
reg [9:0] r_count = 0;
reg r_CE;
always @(posedge clk) begin
if (r_count <= 250) begin
r_count <= r_count + 1;
r_CE <= 0;
end else begin
r_count <= 0;
r_CE <= 1;
end
end
assign CE = r_CE;
endmodule... | 7.824564 |
module with Wishbone interface to node device(the host) or communication memory.
// "A SpaceWire node comprise one or more SpaceWire link interfaces
// (encoder-decoders) and an interface to the host system,represents an interface between
// a SpaceWire network and an a... | 7.055284 |
module/interface definition.
// Ben Rosser <bjr@sas.upenn.edu>
`default_nettype none
module SpyBuffer #(
// The width of input data (e.g. 2^WIDTH bytes + 1 for metadata).
parameter DATA_WIDTH = 64,
// Width of the spy buffer's memory block. (e.g. 2^WIDTH rows of DATA_WIDTH size).
parameter SPY_MEM_WI... | 10.116876 |
module SpyMemory #(
parameter WIDTH = 6,
// Width of the actual data.
parameter DATAWIDTH = 64
) (
input wire clock,
input wire reset,
// Write enable and write data.
input wire write_enable,
input wire [DATAWIDTH-1:0] write_data,
// Address to read.
input wire [WIDTH-1:0] rea... | 8.534972 |
module sp_efm #(
parameter WIDTH = 9, // 小数分频的位宽
parameter OUT_REG = 0 // 输出加寄存器
) (
input clk, // 时钟输入
input rst_n, // 复位信号，低有效
input [WIDTH-1:0] x_i, // 一阶的误差反馈调制器（EFM）的输入
input y_i,
output y_o, // 量化输出
output [WIDTH-1:0] e_o // 误差输出，作为下一级 EFM 的输入
... | 7.872091 |
module sp_find_segment_n1_62 (
ph_seg_p_2_1_1_V_read,
th_seg_p_2_1_0_V_read,
th_seg_p_2_1_1_V_read,
cpat_seg_p_2_1_1_V_read,
ap_return_0,
ap_return_1,
ap_return_2,
ap_return_3
);
input [11:0] ph_seg_p_2_1_1_V_read;
input [6:0] th_seg_p_2_1_0_V_read;
input [6:0] th_seg_p_2_1_1_V_r... | 6.800849 |
module sp_find_segment_stn1 (
ph_seg_p_1_1_1_V_read,
th_seg_p_1_1_0_V_read,
th_seg_p_1_1_1_V_read,
cpat_seg_p_1_1_1_V_read,
ap_return_0,
ap_return_1,
ap_return_2,
ap_return_3
);
input [11:0] ph_seg_p_1_1_1_V_read;
input [6:0] th_seg_p_1_1_0_V_read;
input [6:0] th_seg_p_1_1_1_V_re... | 6.800849 |
module ADDSUB (
dataa,
datab,
add_sub,
result
);
input [35:0] dataa, datab;
input add_sub; // 1 = Addition , 0 = Subtraction
output [35:0] result;
assign result = dataa + (add_sub ? datab : ~datab) + {35'd0, ~add_sub};
endmodule
| 7.706747 |
module Sort (
clk,
rst_n,
in0,
in1,
in2,
in3,
in4,
in5,
out0,
out1,
out2,
out3,
out4,
out5
);
//================================================================
// INPUT AND OUTPUT DECLARATION
//=====================================... | 6.626478 |
module sp_mash111 #(
parameter WIDTH = 9, // 小数分频的位宽
parameter OUT_REG = 1 // 输出加寄存器
) (
input clk, // 时钟输入
input rst_n, // 复位信号，低有效
input [WIDTH-1:0] x_i, // Sigma-Delta 调制器的输入，即分频中小数的输入
output [ 3:0] y_o, // 量化输出
output [WIDTH-1:0] e_o // 最后一级 EFM 的误差输出，实际上用不到，不用管
);
/... | 7.091773 |
module sp_mux_4to1_sel2_4_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
dout_WIDTH = 32
) (
input [3 : 0] din1,
input [3 :... | 6.511105 |
module sp_mux_4to1_sel2_7_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
dout_WIDTH = 32
) (
input [6 : 0] din1,
input [6 :... | 6.511105 |
module sp_mux_6to1_sel3_12_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
din7_WIDTH = 32,
... | 6.52561 |
module sp_mux_6to1_sel3_7_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
din7_WIDTH = 32,
... | 6.52561 |
module sp_ram #(
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 32,
parameter NUM_WORDS = 256
) (
clk,
en_i,
addr_i,
wdata_i,
rdata_o,
we_i,
be_i
);
//parameter ADDR_WIDTH = 8;
//parameter DATA_WIDTH = 32;
//parameter NUM_WORDS = 256;
input wire clk;
input wire en_i;... | 7.048193 |
module sp_ram_be_tb;
//Inputs
reg clk;
reg en; // enable access to ram
reg [`NUM_COL-1:0] we; // write enable vector
reg [`ADDR_W-1:0] addr;
reg [`DATA_W-1:0] data_in;
//Ouptuts
reg [`DATA_W-1:0] data_out;
// .hex file
reg [7:0] filemem[0:15];
integer i, a;
parameter clk_per = 10; // clk... | 7.431717 |
module sp_ram_rw_instruction (
clk, // clock
address, // address Input
data_in, // data in
data_out, // data out
re, // read enable
we // write enable
);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter RAM_DEPTH = 16;
//--------------Input Ports-------------------... | 6.820465 |
module sp_ram_tb;
//Inputs
reg clk;
reg en; // enable access to ram
reg we; // write enable
reg [`ADDR_W-1:0] addr;
reg [`DATA_W-1:0] data_in;
//Ouptuts
reg [`DATA_W-1:0] data_out;
// .hex file
reg [7:0] filemem[0:15];
integer i;
parameter clk_per = 10; // clk period = 10 timeticks
in... | 6.993272 |
module sp_ram_wrap #(
parameter RAM_SIZE = 32768, // in bytes
parameter ADDR_WIDTH = $clog2(RAM_SIZE),
parameter DATA_WIDTH = 32
) (
`ifdef USE_POWER_PINS
vccd1, // User area 1 1.8V supply
vssd1, // User area 1 digital ground
`endif
clk,
rstn_i,
en_i,
addr_i,
wdat... | 6.770199 |
module sp_rcv_ctrl (
clk,
reset,
sp_fifo_wrempty,
sp_fifo_wrfull,
write,
have_sp_data
);
input wire clk;
input wire sp_fifo_wrempty;
input wire sp_fifo_wrfull;
input wire reset;
output wire write;
output wire have_sp_data;
reg state;
reg wrenable;
always @(posedge clk) begi... | 6.665428 |
module SP_RF_RAMModule_TopLevel (
// [BEGIN USER PORTS]
// [END USER PORTS]
input wire Clock,
input wire Reset,
input wire [7:0] Address,
input wire [7:0] WriteData,
input wire WE,
output wire [7:0] Data
);
// [BEGIN USER SIGNALS]
// [END USER SIGNALS]
localparam HiSignal = 1'b1;... | 6.922492 |
module sp_rom (
a_clk,
a_en,
a_addr,
a_dout
);
parameter INIT_FILE = "/mif/";
parameter DATA_WIDTH = 32;
parameter DATA_NUM = 100;
parameter ADDR_WIDTH = `CLOG2(DATA_NUM);
// Port A
input wire a_clk;
input wire a_en;
input wire [ADDR_WIDTH-1:0] a_addr;
output reg [DATA_WIDTH-1:0] a_d... | 7.727318 |
module sp_rom_tb;
//Inputs
reg clk;
reg r_en;
reg [`ADDR_W-1:0] addr;
//Ouptuts
reg [`DATA_W-1:0] rdata;
// .hex file
reg [7:0] filemem[0:15];
integer i;
parameter clk_per = 10; // clk period = 10 timeticks
initial begin
// optional VCD
`ifdef VCD
$dumpfile("sp_rom.vcd");
$dump... | 7.689163 |
module sp_sync_fifo #(
parameter WIDTH = 8,
parameter DEPTH = 256,
parameter AWIDTH = `CLOG2(DEPTH)
) (
input rst,
input clk,
input wr,
input rd,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout,
output empty,
output full
);
reg [AWIDTH:0] rd_ptr, wr_ptr;
wire [WIDTH-1:... | 6.882706 |
module Sp_top (
input clk,
input rst,
output [7:0] Seg,
output [7:0] Sel
);
wire [31:0] reg28;
wire [31:0] disp;
wire [31:0] pc_out;
reg [31:0] seg_idata;
reg [30:0] cnt;
reg clk_50m;
reg flag;
wire clk_cpu;
wire clk_seg;
wire halt;
// wire [31:0] instr;
//wire [31:0] seg_idat... | 6.623897 |
module SP_WF_RAMModule_TopLevel (
// [BEGIN USER PORTS]
// [END USER PORTS]
input wire Clock,
input wire Reset,
input wire [7:0] Address,
input wire [7:0] WriteData,
input wire WE,
output wire [7:0] Data
);
// [BEGIN USER SIGNALS]
// [END USER SIGNALS]
localparam HiSignal = 1'b1;... | 7.110217 |
module Sort (
clk,
rst_n,
in0,
in1,
in2,
in3,
in4,
in5,
out0,
out1,
out2,
out3,
out4,
out5
);
//================================================================
// INPUT AND OUTPUT DECLARATION
//=====================================... | 6.626478 |
module of our architecture.
Use this please cite:
[1] Yang. Zhijie, Wang. Lei, et al., "Bactran: A Hardware Batch Normalization Implementation for CNN Training Engine," in IEEE Embedded Systems Letters, vol. 13, no. 1, pp. 29-32, March 2021.
This code follows the MIT License
Copyright (c) 2021 Yang Zhijie and Wang... | 6.78689 |
module buffer (
i,
o
);
input i;
output o;
endmodule
| 6.861394 |
module std_const #(
parameter WIDTH = 32,
parameter VALUE = 0
) (
output logic [WIDTH - 1:0] out
);
assign out = VALUE;
endmodule
| 8.794277 |
module std_wire #(
parameter WIDTH = 32
) (
input wire logic [WIDTH - 1:0] in,
output logic [WIDTH - 1:0] out
);
assign out = in;
endmodule
| 8.485736 |
module std_slice #(
parameter IN_WIDTH = 32,
parameter OUT_WIDTH = 32
) (
input wire logic [ IN_WIDTH-1:0] in,
output logic [OUT_WIDTH-1:0] out
);
assign out = in[OUT_WIDTH-1:0];
`ifdef VERILATOR
always_comb begin
if (IN_WIDTH < OUT_WIDTH)
$error(
"std_slice: Input width ... | 8.248138 |
module std_pad #(
parameter IN_WIDTH = 32,
parameter OUT_WIDTH = 32
) (
input wire logic [ IN_WIDTH-1:0] in,
output logic [OUT_WIDTH-1:0] out
);
localparam EXTEND = OUT_WIDTH - IN_WIDTH;
assign out = {{EXTEND{1'b0}}, in};
`ifdef VERILATOR
always_comb begin
if (IN_WIDTH > OUT_WIDTH)
... | 8.450332 |
module std_not #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] in,
output logic [WIDTH-1:0] out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_not1_1 _impl (
in,
out
);
end else if (WIDTH == 8) begin
lakeroad_xilinx_ultrascale_plus_not8_1 _impl (
... | 8.707194 |
module std_and #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_and1_2 _impl (
left,
right,
out
);
end else if (WIDTH == 32) ... | 8.159461 |
module std_or #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_or1_2 _impl (
left,
right,
out
);
end else begin
$error("U... | 8.160076 |
module std_xor #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
// if (WIDTH == x) begin
// lakeroad_xilinx_ultrascale_plus_op _impl(in, out);
// end
// //else begin
$error("Unsupported bitwidth %0d", WI... | 8.185133 |
module std_add #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 2) begin
lakeroad_xilinx_ultrascale_plus_add2_2 _impl (
left,
right,
out
);
end else if (WIDTH == 3) ... | 7.105468 |
module std_sub #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 5) begin
lakeroad_xilinx_ultrascale_plus_sub5_2 _impl (
left,
right,
out
);
end else if (WIDTH == 6) b... | 7.29825 |
module std_gt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 5) begin
lakeroad_xilinx_ultrascale_plus_ugt5_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidt... | 7.445889 |
module std_lt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 3) begin
lakeroad_xilinx_ultrascale_plus_ult3_2 _impl (
left,
right,
out
);
end else if (WIDTH == 4) begin
lakeroad_xi... | 7.925865 |
module std_eq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_eq1_2 _impl (
left,
right,
out
);
end else if (WIDTH == 5) begin
lakeroad_xil... | 8.155468 |
module std_neq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (0 == 1) begin
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 7.624981 |
module std_ge #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (0 == 1) begin
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 6.896227 |
module std_le #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 4) begin
lakeroad_xilinx_ultrascale_plus_ule4_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidt... | 8.161124 |
module std_lsh #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left << right;
endmodule
| 8.684363 |
module std_rsh #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left >> right;
endmodule
| 8.622539 |
module std_mux #(
parameter WIDTH = 32
) (
input wire logic cond,
input wire logic [WIDTH-1:0] tru,
input wire logic [WIDTH-1:0] fal,
output logic [WIDTH-1:0] out
);
assign out = cond ? tru : fal;
endmodule
| 9.56204 |
module std_reg #(
parameter WIDTH = 32
) (
input wire [ WIDTH-1:0] in,
input wire write_en,
input wire clk,
input wire reset,
// output
output logic [WIDTH - 1:0] out,
output logic done
);
always_ff @(posedge clk) begin
... | 7.672256 |
module std_mem_d1 #(
parameter WIDTH = 32,
parameter SIZE = 16,
parameter IDX_SIZE = 4
) (
input wire logic [IDX_SIZE-1:0] addr0,
input wire logic [ WIDTH-1:0] write_data,
input wire logic write_en,
input wire logic clk,
output logic [ WIDTH-1:0... | 8.560454 |
module std_mem_d2 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE-1:0] addr0,
input wire logic [D1_IDX_SIZE-1:0] addr1,
input wire logic [ WIDTH-1:0] write_data,
in... | 8.570777 |
module std_mem_d3 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D2_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4,
parameter D2_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE-1:0] addr0,
input wire logic [D1_IDX_SIZE-1:0] addr1,... | 9.018781 |
module std_mem_d4 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D2_SIZE = 16,
parameter D3_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4,
parameter D2_IDX_SIZE = 4,
parameter D3_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE... | 9.168498 |
module fp_sqrt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic clk,
input logic reset,
input logic go,
input logic [WIDTH-1:0] in,
output logic [WIDTH-1:0] out,
output logic done
);
loc... | 7.054716 |
module std_fp_add #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left + right;
endmodule
| 9.124708 |
module std_fp_sub #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left - right;
endmodule
| 8.85803 |
module std_fp_mult_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16,
parameter SIGNED = 0
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
input logic go,
input logic clk,
input logic reset,
... | 6.609331 |
module std_fp_div_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic go,
input logic clk,
input logic reset,
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] o... | 7.871496 |
module std_fp_gt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic out
);
assign out = left > right;
endmodule
| 8.426383 |
module std_fp_sadd #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left + right);
endmodule
| 8.768295 |
module std_fp_ssub #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left - right);
endmodule
| 8.839041 |
module std_fp_smult_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input [WIDTH-1:0] left,
input [WIDTH-1:0] right,
input logic reset,
input logic go,
input logic clk,
output logic [WIDTH-1:0]... | 7.173413 |
module std_fp_sdiv_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input clk,
input go,
input reset,
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH... | 8.37227 |
module std_fp_sgt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed out
);
assign out = $signed(left > right);
endmodule
| 8.236193 |
module std_fp_slt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed out
);
assign out = $signed(left < right);
endmodule
| 8.595041 |
module std_mult_pipe #(
parameter WIDTH = 32
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
input logic reset,
input logic go,
input logic clk,
output logic [WIDTH-1:0] out,
output logic done
);
std_fp_mult_pipe #(
... | 7.504255 |
module std_div_pipe #(
parameter WIDTH = 32
) (
input reset,
input clk,
input go,
input [WIDTH-1:0] left,
input [WIDTH-1:0] right,
output logic [WIDTH-1:0] out_remainder,
output logic [WIDTH-1:0] out_quotient,
out... | 6.929139 |
module std_sadd #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left + right);
endmodule
| 8.670882 |
module std_ssub #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left - right);
endmodule
| 8.103836 |
module std_smult_pipe #(
parameter WIDTH = 32
) (
input logic reset,
input logic go,
input logic clk,
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output logic signed [WIDTH-1:0] out,
output logic... | 6.968167 |
module std_sdiv_pipe #(
parameter WIDTH = 32
) (
input reset,
input clk,
input go,
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed [WIDTH-1:0] out_quotient,
outp... | 7.505299 |
module std_sgt #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left > right);
endmodule
| 7.663941 |
module std_slt #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left < right);
endmodule
| 8.095256 |
module std_seq #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left == right);
endmodule
| 8.302327 |
module std_sneq #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left != right);
endmodule
| 7.44378 |
module std_sge #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left >= right);
endmodule
| 7.297458 |
module std_sle #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left <= right);
endmodule
| 8.057164 |
module std_slsh #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = left <<< right;
endmodule
| 7.70425 |
module std_srsh #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = left >>> right;
endmodule
| 8.663189 |
module std_const #(
parameter WIDTH = 32,
parameter VALUE = 0
) (
output logic [WIDTH - 1:0] out
);
assign out = VALUE;
endmodule
| 8.794277 |
module std_wire #(
parameter WIDTH = 32
) (
input wire logic [WIDTH - 1:0] in,
output logic [WIDTH - 1:0] out
);
assign out = in;
endmodule
| 8.485736 |
module std_slice #(
parameter IN_WIDTH = 32,
parameter OUT_WIDTH = 32
) (
input wire logic [ IN_WIDTH-1:0] in,
output logic [OUT_WIDTH-1:0] out
);
assign out = in[OUT_WIDTH-1:0];
`ifdef VERILATOR
always_comb begin
if (IN_WIDTH < OUT_WIDTH)
$error(
"std_slice: Input width ... | 8.248138 |
module std_pad #(
parameter IN_WIDTH = 32,
parameter OUT_WIDTH = 32
) (
input wire logic [ IN_WIDTH-1:0] in,
output logic [OUT_WIDTH-1:0] out
);
localparam EXTEND = OUT_WIDTH - IN_WIDTH;
assign out = {{EXTEND{1'b0}}, in};
`ifdef VERILATOR
always_comb begin
if (IN_WIDTH > OUT_WIDTH)
... | 8.450332 |
module std_not #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] in,
output logic [WIDTH-1:0] out
);
assign out = ~in;
endmodule
| 8.707194 |
module std_and #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left & right;
endmodule
| 8.159461 |
module std_or #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left | right;
endmodule
| 8.160076 |
module std_xor #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left ^ right;
endmodule
| 8.185133 |
module std_add #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left + right;
endmodule
| 7.105468 |
module std_sub #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left - right;
endmodule
| 7.29825 |
module std_gt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left > right;
endmodule
| 7.445889 |
module std_lt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left < right;
endmodule
| 7.925865 |
module std_eq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left == right;
endmodule
| 8.155468 |
module std_neq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left != right;
endmodule
| 7.624981 |
module std_ge #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left >= right;
endmodule
| 6.896227 |
module std_le #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left <= right;
endmodule
| 8.161124 |
module std_lsh #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left << right;
endmodule
| 8.684363 |
module std_rsh #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left >> right;
endmodule
| 8.622539 |
module std_mux #(
parameter WIDTH = 32
) (
input wire logic cond,
input wire logic [WIDTH-1:0] tru,
input wire logic [WIDTH-1:0] fal,
output logic [WIDTH-1:0] out
);
assign out = cond ? tru : fal;
endmodule
| 9.56204 |
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