code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module std_reg #(
parameter WIDTH = 32
) (
input wire [ WIDTH-1:0] in,
input wire write_en,
input wire clk,
input wire reset,
// output
output logic [WIDTH - 1:0] out,
output logic done
);
always_ff @(posedge clk) begin
... | 7.672256 |
module std_mem_d1 #(
parameter WIDTH = 32,
parameter SIZE = 16,
parameter IDX_SIZE = 4
) (
input wire logic [IDX_SIZE-1:0] addr0,
input wire logic [ WIDTH-1:0] write_data,
input wire logic write_en,
input wire logic clk,
output logic [ WIDTH-1:0... | 8.560454 |
module std_mem_d2 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE-1:0] addr0,
input wire logic [D1_IDX_SIZE-1:0] addr1,
input wire logic [ WIDTH-1:0] write_data,
in... | 8.570777 |
module std_mem_d3 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D2_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4,
parameter D2_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE-1:0] addr0,
input wire logic [D1_IDX_SIZE-1:0] addr1,... | 9.018781 |
module std_mem_d4 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D2_SIZE = 16,
parameter D3_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4,
parameter D2_IDX_SIZE = 4,
parameter D3_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE... | 9.168498 |
module fp_sqrt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic clk,
input logic reset,
input logic go,
input logic [WIDTH-1:0] in,
output logic [WIDTH-1:0] out,
output logic done
);
loc... | 7.054716 |
module std_fp_add #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left + right;
endmodule
| 9.124708 |
module std_fp_sub #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left - right;
endmodule
| 8.85803 |
module std_fp_mult_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16,
parameter SIGNED = 0
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
input logic go,
input logic clk,
input logic reset,
... | 6.609331 |
module std_fp_div_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic go,
input logic clk,
input logic reset,
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] o... | 7.871496 |
module std_fp_gt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic out
);
assign out = left > right;
endmodule
| 8.426383 |
module std_fp_sadd #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left + right);
endmodule
| 8.768295 |
module std_fp_ssub #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left - right);
endmodule
| 8.839041 |
module std_fp_smult_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input [WIDTH-1:0] left,
input [WIDTH-1:0] right,
input logic reset,
input logic go,
input logic clk,
output logic [WIDTH-1:0]... | 7.173413 |
module std_fp_sdiv_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input clk,
input go,
input reset,
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH... | 8.37227 |
module std_fp_sgt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed out
);
assign out = $signed(left > right);
endmodule
| 8.236193 |
module std_fp_slt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed out
);
assign out = $signed(left < right);
endmodule
| 8.595041 |
module std_mult_pipe #(
parameter WIDTH = 32
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
input logic reset,
input logic go,
input logic clk,
output logic [WIDTH-1:0] out,
output logic done
);
std_fp_mult_pipe #(
... | 7.504255 |
module std_div_pipe #(
parameter WIDTH = 32
) (
input reset,
input clk,
input go,
input [WIDTH-1:0] left,
input [WIDTH-1:0] right,
output logic [WIDTH-1:0] out_remainder,
output logic [WIDTH-1:0] out_quotient,
out... | 6.929139 |
module std_sadd #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left + right);
endmodule
| 8.670882 |
module std_ssub #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left - right);
endmodule
| 8.103836 |
module std_smult_pipe #(
parameter WIDTH = 32
) (
input logic reset,
input logic go,
input logic clk,
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output logic signed [WIDTH-1:0] out,
output logic... | 6.968167 |
module std_sdiv_pipe #(
parameter WIDTH = 32
) (
input reset,
input clk,
input go,
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed [WIDTH-1:0] out_quotient,
outp... | 7.505299 |
module std_sgt #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left > right);
endmodule
| 7.663941 |
module std_slt #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left < right);
endmodule
| 8.095256 |
module std_seq #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left == right);
endmodule
| 8.302327 |
module std_sneq #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left != right);
endmodule
| 7.44378 |
module std_sge #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left >= right);
endmodule
| 7.297458 |
module std_sle #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left <= right);
endmodule
| 8.057164 |
module std_slsh #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = left <<< right;
endmodule
| 7.70425 |
module std_srsh #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = left >>> right;
endmodule
| 8.663189 |
module computes the 16-bit square root of a 32-bit number in 16 clock cycles using the
// non-restoring algorithm. Every 2 bits of the input correspond to 1 bit of the output. The
// root (Q) is initialized to zero, then the remainder (R) is computed and the radicand (D) is
// shifted by two on each following clock cyc... | 6.902237 |
module computes the 16-bit square root of a 16-bit number in 16 clock cycles using the
// non-restoring algorithm. Every 2 bits of the input correspond to 1 bit of the output. The
// root (Q) is initialized to zero, then the remainder (R) is computed and the radicand (D) is
// shifted by two on each following clock cyc... | 6.902237 |
module testBench;
parameter ss = 5;
parameter w = 1 << ss; //need to change in 2 places 2/2
//parameter Amax= 2000000;
parameter Amax = 10001; //quick test
reg [w-1:0] A;
reg clk, reset;
wire [(w/2)-1:0] Z;
wire done;
sqrt dut (
.clk(clk),
.rdy(done),
.reset(reset... | 6.519976 |
module sqrtfcn_dcmp_64ns_64ns_1_3 #(
parameter ID = 8,
NUM_STAGE = 3,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 1
) (
input wire clk,
input wire reset,
input wire ce,
input wi... | 6.540151 |
module sqrtfcn_ddiv_64ns_64ns_64_14 #(
parameter ID = 7,
NUM_STAGE = 14,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
) (
input wire clk,
input wire reset,
input wire ce,
input... | 6.882983 |
module sqrtfcn_dmul_64ns_64ns_64_4_max_dsp #(
parameter ID = 6,
NUM_STAGE = 4,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
) (
input wire clk,
input wire reset,
input wire ce,
... | 7.083523 |
module sqrtfcn_fdiv_32ns_32ns_32_8 #(
parameter ID = 2,
NUM_STAGE = 8,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
) (
input wire clk,
input wire reset,
input wire ce,
input ... | 6.504234 |
module sqrtfcn_fmul_32ns_32ns_32_3_max_dsp #(
parameter ID = 1,
NUM_STAGE = 3,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
) (
input wire clk,
input wire reset,
input wire ce,
... | 6.731233 |
module sqrtfcn_fptrunc_64ns_32_3 #(
parameter ID = 3,
NUM_STAGE = 3,
din0_WIDTH = 64,
dout_WIDTH = 32
) (
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
o... | 6.820691 |
module SqrtMantissa (
in,
isFloat,
isExponentOdd,
mantissa,
isDone
);
parameter BINARY_SIZE = 8'd106, // must be even
HALF_BINARY_SIZE = 8'd53, MANTISSA_SIZE = 6'd52;
input isFloat, isExponentOdd;
input [BINARY_SIZE - 1:0] in;
output [MANTISSA_SIZE - 1:0] mantissa;
output isDone;
... | 6.971424 |
module tb ();
reg clk, reset;
reg [30:0] x;
wire [16:0] SqrtValue;
initial begin
clk = 1'b0;
reset = 1'b1;
#30;
reset = 1'b0;
x = 31'b111111_11_11111111_11111111_1111111; // 128
#20;
x = 31'b00000010_00000000_00000000_0000000; // 1
#20;
x = 31'b00000100_00000000_000... | 7.195167 |
module SQRT_BL (
input [2*`m-1:0] X,
output reg [`m-1:0] Q = 0,
input st,
output reg en = 0,
input clk
);
wire [2*`m-1:0] M = Q * Q;
wire DI = (M <= X);
//--- ---
reg [`m:0] T = 0; // T
integer i; // for
always @(posedge clk) begin
T <= st ? 1 << `m : en ? T >> 1 : T; // T
... | 6.633734 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pow_module(Clk, data_in, reset, enable, textOut, n... | 7.088073 |
module SQRT (
CLK,
RST,
DATA_IN,
DATA_OUT
);
input CLK, RST;
input [15:0] DATA_IN;
output [15:0] DATA_OUT;
wire SEL_REG_0;
wire [1:0] SEL_REG_1;
wire [1:0] SEL_REG_2;
wire [1:0] SEL_REG_3;
wire [1:0] SEL_ADD_0;
wire [1:0] SEL_ADD_1;
wire CTRL;
DATAPATH DATAPATH (
// Inp... | 7.3448 |
module DATAPATH (
CLK,
RST,
DATA_IN,
IN_SEL_REG_0,
IN_SEL_REG_1,
IN_SEL_REG_2,
IN_SEL_REG_3,
IN_SEL_ADD_0,
IN_SEL_ADD_1,
CTRL,
DATA_OUT
);
input CLK, RST;
input [15:0] DATA_IN;
input IN_SEL_REG_0;
input [1:0] IN_SEL_REG_1;
input [1:0] IN_SEL_REG_2;
input [1:0... | 6.685613 |
module ADDER (
A,
B,
Y
);
input [15:0] A;
input [15:0] B;
output [15:0] Y;
assign Y = A + B;
endmodule
| 7.327585 |
module COMPARATOR (
A,
B,
Y
);
input [15:0] A;
input [15:0] B;
output Y;
assign Y = A < B;
//always @(A or B) begin
// if (A < B)
// assign Y = 1'b1;
// else
// assign Y = 1'b0;
//end
endmodule
| 7.309761 |
module for the Square Root unit
`timescale 1ns/1ps
module Sqrt_range(exp_f,LZD_Sqrt,y_f,f_temp);
input [5:0] exp_f;
input [5:0] LZD_Sqrt;
input [20:0] y_f;
output [20:0] f_temp;
reg [20:0] f_temp;
reg [5:0] exp_f_1;
always@(exp_f or LZD_Sqrt or y_f or exp_f_1)
begin
//Performing Left or Right shift based of the value ... | 6.768337 |
module sqrt_range_reconst (
input iClk,
input [5:0] iExp_f1,
input [21:0] iY_f,
output [16:0] oF
);
reg [23:0] rf = 0;
// wire [5:0] wExp_f;
reg [5:0] wExp_f, wExp_f1, wExp_f2;
reg [5:0] rExp_f = 0;
reg [5:0] rExp_fr = 0;
// assign wExp_f = iExp_f1;
always @(posedge iClk) begin
w... | 6.766597 |
module sqrt_range_reduction (
// Input data
input wire [30:0] iE,
// Onput data
output wire [25:0] oX_f,
output wire [ 5:0] oExp_f,
output wire [ 5:0] oExp_f1
);
//Intermediate data
wire [ 5:0] wExp_f1;
reg [ 5:0] rExp_f;
reg [ 5:0] rExp_fr;
reg [30:0] rX_f;
reg [30:0] rX_f1;... | 6.766597 |
module sqrt_remainder #(
parameter RADICAND_WIDTH = 8,
parameter STAGE_NUMBER = 3
) (
input wire [`INTEGER_INPUT_WIDTH-1:0] integer_input,
input wire [`REMAINDER_INPUT_WIDTH-1:0] remainder_previous,
input wire [(`RESULT_INPUT_WIDTH-1 + `IS_FIRST_STAGE):0] result_previous, // we need to force the f... | 6.906991 |
module sqrt_ROM (
n,
sqrto
);
input [3:0] n; //unsigned number
output reg [31:0] sqrto;
real sqrt;
wire [1:0] sqrt_int;
wire [29:0] sqrt_dp;
always @(n) begin
case (n + 1)
0: sqrt <= 0.000;
1: sqrt <= 1.000;
2: sqrt <= 1.414;
3: sqrt <= 1.732;
4: sqrt <= 2.000;
... | 7.216778 |
module sqrt_ROMTB ();
reg [ 3:0] n;
wire [31:0] sqrt;
sqrt_ROM(
.n(n), .sqrto(sqrt)
);
initial begin
$monitor("n = %b = %d, sqrt = %f", n, n, $bitstoshortreal(sqrt));
end
initial begin : apply_stimulus
reg [4:0] i;
for (i = 0; i <= 15; i = i + 1) begin
n = i;
#1;
end... | 7.158066 |
module is a test bench for the sqrt32 module. It runs some
* test input values through the sqrt32 module, and checks that the
* output is valid. If an invalid output is generated, print and
* error message and stop immediately. If all the tested values pass,
* then print PASSED after the test is complete.
*/
... | 6.595812 |
module sqrt_Top (
start,
clk,
clear,
num,
result,
ready
);
input start, clk, clear;
input [6:0] num;
output [3:0] result;
output ready;
wire finish, load_data, incr_delta, find_next_sq;
sqrt_controller m1 (
start,
finish,
clk,
clear,
ready,
load_... | 6.659984 |
module sqrt_Top (
start,
clk,
clear,
num,
result,
ready,
test_si,
test_so,
test_se
);
input [6:0] num;
output [3:0] result;
input start, clk, clear, test_si, test_se;
output ready, test_so;
wire finish, load_data, incr_delta, find_next_sq, n3, n5, n6, n7;
sqrt_controller... | 6.659984 |
module sqrt_Top (
start,
clk,
clear,
num,
result,
ready
);
input [6:0] num;
output [3:0] result;
input start, clk, clear;
output ready;
wire finish, load_data, incr_delta, find_next_sq;
sqrt_controller m1 (
.start(start),
.finish(finish),
.clk(clk),
.clear(cl... | 6.659984 |
module sqrt_Top (
start,
clk,
clear,
num,
result,
ready
);
input [6:0] num;
output [3:0] result;
input start, clk, clear;
output ready;
wire finish, load_data, incr_delta, find_next_sq;
sqrt_controller m1 (
.start(start),
.finish(finish),
.clk(clk),
.clear(cl... | 6.659984 |
module m_draw_rectangle #(
parameter ADDR_WIDTH = 8,
DATA_WIDTH = 4,
DEPTH = 256
) (
input wire clk,
input wire i_write,
input wire [10:0] current_x,
input wire [10:0] current_y,
input wire [10:0] half_width,
input wire [10:0] half_height,
input wire [DATA_WIDTH-1:0] i_data,
... | 7.74358 |
module squarediffmult #(
parameter SIZEIN = 16
) (
input clk,
ce,
rst,
input signed [SIZEIN-1:0] a,
b,
output signed [2*SIZEIN+1:0] square_out
);
// Declare registers for intermediate values
reg signed [SIZEIN-1:0] a_reg, b_reg;
reg signed [SIZEIN:0] diff_reg;
reg signed [2*SIZEIN+1... | 6.971873 |
module squaregen (
input wire clk,
input wire en,
input wire [22:0] period,
output wire [23:0] tone,
output wire on
);
parameter amplitude = 24'hfffff; // TODO CHANGE?
//parameter freq = 440;
reg [31:0] count = 0;
//logic[31:0] period = (48000000 / freq);
always @(posedge clk)
if (... | 7.189037 |
module SquareGenTest ();
reg clk;
reg [5:0] note_in;
wire [2:0] offset_multiplier;
wire offset_direction;
reg en;
reg vibra_en;
reg note_clk;
reg [1:0] vibra_speed;
reg [1:0] vibra_depth;
wire [5:0] vibra_out;
wire square_out;
wire freq;
FX_vibrato sq_vibra (
.note_in (note_in), /... | 7.628054 |
module SquareLoop (
rst,
clk,
din,
startf,
carrier,
df
);
input rst; //复位信号，高电平有效
input clk; //FPGA系统时钟：16MHz
input signed [7:0] din; //输入数据：16MHz
input signed [31:0] startf; //输入的载波初始频率
output signed [7:0] carrier; //同步后的载波输出信号
output signed [27:0] df; //环路滤波器输出数据
//实例化NCO... | 7.223118 |
module fa_df (
input a,
b,
cin,
output sum,
cout
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (cin & (a ^ b));
endmodule
| 6.889194 |
module ha_df (
input a,
b,
output sum,
cout
);
assign sum = a ^ b;
assign cout = a & b;
endmodule
| 8.302286 |
module SquareWave (
input wire clk_24M,
input wire btn_a_i, // raise frequency
input wire btn_b_i, // drop frequency
output wire io_b3a
);
// clk_100K
wire clk_100K;
SlowClock #(
.HALFPERIOD(24000000 / 100000)
) clock_100K (
.clk (clk_24M),
.clk_o(clk_100K)
);
// clk... | 6.624113 |
module squarewave_disp (
input clk,
rst_n,
input[2:0] key, //key[0] to move cursor to right,key[1] to move cursor down, key[2] to change waveform pattern
output [4:0] vga_out_r,
output [5:0] vga_out_g,
output [4:0] vga_out_b,
output vga_out_vs,
vga_out_hs
);
wire [11:0] pixel_x, pixel... | 7.820059 |
module Square_Adder_Run ();
// Counter for shaping the test vector of the single bit (Full Adder).
reg [2:0] bit_counter; // { c || b || a }
always #1 bit_counter = bit_counter + 1;
// FA outputs
wire nc;
wire c;
wire ns;
// Counters for enumerating Adder input values
reg [21:0] ab_counter; // { ... | 8.030869 |
module Square_Barrel_Run ();
reg [14:0] val; // {BS[11:0] || SR[2:0]}
output [10:0] S;
always #1 val = val + 1;
SQUARE_BarrelShifter bs (
.BS(val[14:3]),
.SR(val[2:0]),
.S (S)
);
initial begin
$dumpfile("square_barrel.vcd");
$dumpvars(0, bs);
val <= 0;
repeat (32769... | 7.009872 |
module square_cell #(
parameter WIDTH = 4,
parameter STEP = 0
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input [2 * WIDTH - 1:0] radicand,
input [WIDTH - 1:0] last_dout,
input [2 * WIDTH - 1:0] remainder_din,
output reg [WIDTH - 1:0] this_dout,
output ... | 6.639212 |
module Square_Controller (
CLK,
SOUND_WAVE,
RESET,
START,
HURT,
RECOVER,
INVINCIBLE,
OVER,
DROP_READY,
SQUARE_START_Y,
SQUARE_SIZE,
SQUARE_COLOR
);
input CLK; //100Hz
input SOUND_WAVE;
input RESET;
input START;
input HURT; //当游戏机会次数-1时，HURT置为1,随后置为0
input RE... | 7.106526 |
module Square_Coordinate_Controller (
CLK,
RESET,
DROP_START,
FREE_MOVE,
GAME_OVER,
SOUND_LEVEL,
SQUARE_Y_COORDINATE,
DROP_FINISH
);
input CLK;
input RESET;
input DROP_START;
input FREE_MOVE;
input GAME_OVER;
input [`SOUND_LEVEL_ENCODE_LENGTH-1:0] SOUND_LEVEL;
output reg [`... | 8.567771 |
module Square_Duty_Run ();
reg CLK;
reg RES;
wire PHI1;
wire ACLK1;
wire nACLK2;
// Tune CLK/ACLK timing according to 2A03
always #23.28 CLK = ~CLK;
reg WR0; // Used to load the Duty setting into the appropriate register
wire [7:0] DataBus;
reg [1:0] duty_mode;
wire DUTY; // The signal for... | 6.902841 |
module executes a "program" sequence of writes to the Duty register
module RegDriver (PHI1, WR0, duty_mode, DataBus);
input PHI1;
input WR0;
input [1:0] duty_mode;
inout [7:0] DataBus;
assign DataBus = ~PHI1 ? (WR0 ? {duty_mode[1:0],6'b000000} : 8'hzz) : 8'hzz;
endmodule
| 7.110462 |
module square_extractor #(
parameter WIDTH = 4
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input [2 * WIDTH - 1:0] radicand,
output [WIDTH - 1:0] dout,
output [2 * WIDTH - 1:0] remainder
);
genvar i;
generate
for (i = WIDTH - 1; i >= 0; i = i - 1) begin : s... | 7.454079 |
module square_handler (
clk_1Hz,
up,
down,
left,
right,
hcnt,
vcnt,
hcnt_out,
vcnt_out
);
input clk_1Hz, up, down, left, right, hcnt, vcnt;
output hcnt_out, vcnt_out;
wire clk_1Hz;
wire up, down, left, right;
wire [9:0] hcnt, vcnt;
reg [9:0] hcnt_out, vcnt_out;
reg [... | 6.985921 |
module square_logic (
input clk,
input rst_n,
input [9:0] x,
input [9:0] x2,
output reg [9:0] vga_x,
output reg [9:0] vga_y,
output reg [9:0] vga_x2,
output reg [9:0] vga_y2
);
reg [31:0] cnt;
reg x_direct;
reg y_direct;
wire move_en;
param... | 6.885059 |
module square_mag (
input clock,
input reset,
input dv_fft,
input [15:0] xk_re,
input [15:0] xk_im,
output dv_sq_m,
output [31:0] xk_sq_m
);
wire [31:0] xk_re_sq;
wire [31:0] xk_im_sq;
wire dv_fft_d1, dv_fft_d2, dv_fft_d3;
wire dv_sq, dv_sq_d1, dv_sq_d2, dv_sq_d3;
dsp48_mul mu... | 6.557962 |
module square_op (
input Ai,
input Bi,
output Pi,
output Gi,
output Hi
);
always @(*) begin
Pi = Ai ^ Bi;
Gi = Ai & Bi;
Hi = Ai ^ Bi;
end
endmodule
| 7.015104 |
module BogusCPU (
PHI0,
PHI1,
PHI2
);
input PHI0;
output PHI1;
output PHI2;
assign PHI1 = ~PHI0;
assign PHI2 = PHI0;
endmodule
| 7.703679 |
module executes a "program" sequence of writes to various registers
module RegDriver (PHI1, W4000, W4001, W4002, W4003, W4015, DataBus);
input PHI1;
input W4000;
input W4001;
input W4002;
input W4003;
input W4015;
inout [7:0] DataBus;
// W4015 <= 0000000 1 (SQA Length counter enable: 1)
// W4000 <= 10 0 0 0... | 7.110462 |
module square_read_create (
input CLK,
input RST,
output [11:0] square
);
//Load other module(s)
//Definition for Variables in the module
reg [11:0] value[63:0];
//Buffer to sroe
reg [5:0] counter;
//Counter for the value circle
//Logical
assign square = value[counter];
initial begin
... | 7.554065 |
module that sqaures 4 bit input 'n'.
module square_ROM(n, sign, square);
input [3:0] n; //number.
input sign; //signed number if 1, unsigned if 0.
output reg [7:0] square;
always @ (n or sign) begin
if(sign==0) begin //if unsigned (0-15)
case(n)
0: square <= 0;
1: square <= 1;
2: square <= 4;
3: sq... | 6.758992 |
module square_ROMTB ();
reg [3:0] n;
reg sign;
wire [7:0] square;
square_ROM(
.n(n), .sign(sign), .square(square)
);
initial begin
$monitor("n = %b = %d, sign = %b, square = %d", n, n, sign, square);
end
initial begin : apply_stimulus
reg [4:0] i;
n = 0;
sign = 0; //positive o... | 7.221158 |
module square_root_comb #(
parameter N = 8,
M = N / 2
) (
input [ N-1:0] A,
output [N/2-1:0] O
);
wire [N/2:0] Y[0:M];
assign O = Y[M][N/2-1:0];
genvar gv;
generate
for (gv = 0; gv < M; gv = gv + 1) begin : sqr_rt
squar_root_comb_unit #(
.N(N),
.K(gv)
) s... | 6.679579 |
module squar_root_comb_unit #(
parameter N = 8,
K = 0
) (
input [N-1:0] x,
input [ K:0] y_in,
output [K+1:0] y_out
);
wire t, b;
wire [2*K+1:0] y_sqr;
wire [ K+1:0] y;
assign y = {y_in, 1'b1};
MULT #(
.N(K + 1),
.M(K + 1)
) MULT1 (
.A(y[K:0]),
.B(y[K:0]),
... | 6.602703 |
module squar_root_seq_unit #(
parameter N = 8
) (
input [ N-1:0] x,
input [N/2-1:0] y_in,
y0_in,
output [N/2-1:0] y_out,
y0_out
);
wire t, b;
wire [N/2-1:0] y;
wire [ N-1:0] y_sqr;
assign y = y_in | y0_in;
MULT #(
.N(N / 2),
.M(N / 2)
) MULT1 (
.A(y),
.B... | 6.556534 |
module square_root32_element #(
parameter P_IN_N = 4,
parameter P_DFF = 1
) (
input wire iCLOCK,
input wire inRESET,
//Input
input wire iDATA_REQ,
output wire oDATA_BUSY,
input wire [P_IN_N/2-1:0] iDATA_P,
input wire [31:0] iDATA_I,
//Output
output wire oDATA_VALID,
inpu... | 6.737667 |
module calculates the square root value of the provided inputData value. This
is achieved through the usage of the Non-Restoring Square Root algorithm. The data
width of the output must be exactly half the input bit width. Input bit width must
be equal to an even number.
To fully understand how the Non-Restori... | 7.448165 |
module Square_Sweep_Run ();
reg CLK;
reg RES;
wire PHI1;
wire ACLK1;
wire nACLK2;
// Tune CLK/ACLK timing according to 2A03
always #23.28 CLK = ~CLK;
reg WR_Reg1; // Used to simulate writing to the Sweep registers by the "processor" (RegDriver)
wire [7:0] DataBus;
wire n_LFO2;
wire DO_SWEE... | 6.596546 |
module executes a "program" sequence of writes to the SweepUnit registers
module RegDriver (PHI1, WR_Reg1, DataBus);
input PHI1;
input WR_Reg1;
inout [7:0] DataBus;
assign DataBus = ~PHI1 ? (WR_Reg1 ? 8'b11110001 : 8'hzz) : 8'hzz; // Enable=1; Period=7; Negative=0; Shift=1
endmodule
| 7.110462 |
module
`timescale 1ns / 1ps
`define VALUE_WIDTH 12
`define VALUE_MAX 1500
module square_test;
// Inputs
reg signed [`VALUE_WIDTH-1:0] value;
reg clk;
reg reset;
reg data_valid;
// Outputs
wire [(`VALUE_WIDTH-1) * 2 - 1:0] square;
wire new_result;
// Internal variables
reg [(`VALUE_WIDTH-1) * 2 - 1:0] e... | 6.608387 |
module square_wave_gen (
input wire clk,
reset,
input wire [3:0] on_period,
off_period,
output wire signal
);
// signal declaration
localparam BASE_CYCLES = 10;
reg signal_reg, signal_next;
reg [3:0] on_period_reg, off_period_reg;
wire [3:0] on_period_next, off_period_next;
... | 6.641963 |
module square_wave_generator (
clk,
enable,
divider,
out
);
input clk;
input enable;
input [18:0] divider;
reg [18:0] counter;
reg polarity;
output reg signed [31:0] out;
always @(posedge clk) begin
if (!enable) begin
counter <= 19'b0;
out <= 32'b0;
polarity <= 1'b0... | 6.641963 |
module square_wave_gen_tb;
localparam T = 10; // clk period
reg clk, reset;
reg [3:0] on_period, off_period;
wire signal;
// instance of uut
square_wave_gen uut (
.clk(clk),
.reset(reset),
.on_period(on_period),
.off_period(off_period),
.signal(signal)
);
// clock
alw... | 6.641963 |
module square_wave_gen(
input clk,
input rst_n,
output sq_wave
);
// Input clock is 100MHz
localparam CLOCK_FREQUENCY = 100000000;
// Counter for toggling of clock
integer counter = 0;
reg sq_wave_reg = 0;
assign sq_wave = sq_wave_reg;
always @(posedge clk) begin
if (!rst_n) begin
counter <= 8'h00... | 6.641963 |
module sqwaveGen (
clk,
reset,
rise,
fall,
clk_out
);
input wire clk;
input wire reset;
output wire clk_out;
input wire [15:0] rise;
input wire [9:0] fall;
reg [15:0] count, count_on, count_off;
reg pos_or_neg;
always @(posedge reset) begin
pos_or_neg <= 0;
end
always @(pos... | 6.757862 |
module sqwave_gen (
input clk,
rst_n,
input [3:0] m,
n,
output out
);
reg [6:0] m_reg = 0, n_reg = 0; //counter for ON period of m*(100ns) and OFF period of n*(100ns)
reg sq_reg = 0; //square wave output
reg [6:0] m_nxt = 0, n_nxt = 0;
reg sq_nxt = 0;
reg m_max = 0, n_max = 0;
//regi... | 6.58832 |
module sq_mult #(parameter R=14)
(
input clk,rst,
input ref,
input signed [ R-1:0] in,
output signed [ R-1:0] out
);
wire signed [R-1:0] plus_in, minus_in ;
assign plus_in = in ;
assign minus_in = {R{1'b0}}-$signed(in) ;
assign out = r... | 6.829989 |
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