code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module std_reg #(
parameter WIDTH = 32
) (
input wire [ WIDTH-1:0] in,
input wire write_en,
input wire clk,
input wire reset,
// output
output logic [WIDTH - 1:0] out,
output logic done
);
always_ff @(posedge clk) begin
if (reset) begin
out <= 0;
done <= 0;
end else if (write_en) begin
out <= in;
done <= 1'd1;
end else done <= 1'd0;
end
endmodule
| 7.672256 |
module std_mem_d1 #(
parameter WIDTH = 32,
parameter SIZE = 16,
parameter IDX_SIZE = 4
) (
input wire logic [IDX_SIZE-1:0] addr0,
input wire logic [ WIDTH-1:0] write_data,
input wire logic write_en,
input wire logic clk,
output logic [ WIDTH-1:0] read_data,
output logic done
);
logic [WIDTH-1:0] mem[SIZE-1:0];
/* verilator lint_off WIDTH */
assign read_data = mem[addr0];
always_ff @(posedge clk) begin
if (write_en) begin
mem[addr0] <= write_data;
done <= 1'd1;
end else done <= 1'd0;
end
// Check for out of bounds access
`ifdef VERILATOR
always_comb begin
if (addr0 >= SIZE)
$error("std_mem_d1: Out of bounds access\n", "addr0: %0d\n", addr0, "SIZE: %0d", SIZE);
end
`endif
endmodule
| 8.560454 |
module std_mem_d2 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE-1:0] addr0,
input wire logic [D1_IDX_SIZE-1:0] addr1,
input wire logic [ WIDTH-1:0] write_data,
input wire logic write_en,
input wire logic clk,
output logic [ WIDTH-1:0] read_data,
output logic done
);
/* verilator lint_off WIDTH */
logic [WIDTH-1:0] mem[D0_SIZE-1:0][D1_SIZE-1:0];
assign read_data = mem[addr0][addr1];
always_ff @(posedge clk) begin
if (write_en) begin
mem[addr0][addr1] <= write_data;
done <= 1'd1;
end else done <= 1'd0;
end
// Check for out of bounds access
`ifdef VERILATOR
always_comb begin
if (addr0 >= D0_SIZE)
$error("std_mem_d2: Out of bounds access\n", "addr0: %0d\n", addr0, "D0_SIZE: %0d", D0_SIZE);
if (addr1 >= D1_SIZE)
$error("std_mem_d2: Out of bounds access\n", "addr1: %0d\n", addr1, "D1_SIZE: %0d", D1_SIZE);
end
`endif
endmodule
| 8.570777 |
module std_mem_d3 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D2_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4,
parameter D2_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE-1:0] addr0,
input wire logic [D1_IDX_SIZE-1:0] addr1,
input wire logic [D2_IDX_SIZE-1:0] addr2,
input wire logic [ WIDTH-1:0] write_data,
input wire logic write_en,
input wire logic clk,
output logic [ WIDTH-1:0] read_data,
output logic done
);
/* verilator lint_off WIDTH */
logic [WIDTH-1:0] mem[D0_SIZE-1:0][D1_SIZE-1:0][D2_SIZE-1:0];
assign read_data = mem[addr0][addr1][addr2];
always_ff @(posedge clk) begin
if (write_en) begin
mem[addr0][addr1][addr2] <= write_data;
done <= 1'd1;
end else done <= 1'd0;
end
// Check for out of bounds access
`ifdef VERILATOR
always_comb begin
if (addr0 >= D0_SIZE)
$error("std_mem_d3: Out of bounds access\n", "addr0: %0d\n", addr0, "D0_SIZE: %0d", D0_SIZE);
if (addr1 >= D1_SIZE)
$error("std_mem_d3: Out of bounds access\n", "addr1: %0d\n", addr1, "D1_SIZE: %0d", D1_SIZE);
if (addr2 >= D2_SIZE)
$error("std_mem_d3: Out of bounds access\n", "addr2: %0d\n", addr2, "D2_SIZE: %0d", D2_SIZE);
end
`endif
endmodule
| 9.018781 |
module std_mem_d4 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D2_SIZE = 16,
parameter D3_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4,
parameter D2_IDX_SIZE = 4,
parameter D3_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE-1:0] addr0,
input wire logic [D1_IDX_SIZE-1:0] addr1,
input wire logic [D2_IDX_SIZE-1:0] addr2,
input wire logic [D3_IDX_SIZE-1:0] addr3,
input wire logic [ WIDTH-1:0] write_data,
input wire logic write_en,
input wire logic clk,
output logic [ WIDTH-1:0] read_data,
output logic done
);
/* verilator lint_off WIDTH */
logic [WIDTH-1:0] mem[D0_SIZE-1:0][D1_SIZE-1:0][D2_SIZE-1:0][D3_SIZE-1:0];
assign read_data = mem[addr0][addr1][addr2][addr3];
always_ff @(posedge clk) begin
if (write_en) begin
mem[addr0][addr1][addr2][addr3] <= write_data;
done <= 1'd1;
end else done <= 1'd0;
end
// Check for out of bounds access
`ifdef VERILATOR
always_comb begin
if (addr0 >= D0_SIZE)
$error("std_mem_d4: Out of bounds access\n", "addr0: %0d\n", addr0, "D0_SIZE: %0d", D0_SIZE);
if (addr1 >= D1_SIZE)
$error("std_mem_d4: Out of bounds access\n", "addr1: %0d\n", addr1, "D1_SIZE: %0d", D1_SIZE);
if (addr2 >= D2_SIZE)
$error("std_mem_d4: Out of bounds access\n", "addr2: %0d\n", addr2, "D2_SIZE: %0d", D2_SIZE);
if (addr3 >= D3_SIZE)
$error("std_mem_d4: Out of bounds access\n", "addr3: %0d\n", addr3, "D3_SIZE: %0d", D3_SIZE);
end
`endif
endmodule
| 9.168498 |
module fp_sqrt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic clk,
input logic reset,
input logic go,
input logic [WIDTH-1:0] in,
output logic [WIDTH-1:0] out,
output logic done
);
localparam ITERATIONS = WIDTH + FRAC_WIDTH >> 1;
logic [$clog2(ITERATIONS)-1:0] idx;
logic [WIDTH-1:0] x, x_next;
logic [WIDTH-1:0] quotient, quotient_next;
logic [WIDTH+1:0] acc, acc_next;
logic [WIDTH+1:0] tmp;
logic start, running, finished;
assign start = go && !running;
/* verilator lint_off WIDTH */
assign finished = (ITERATIONS - 1) == idx && running;
always_ff @(posedge clk) begin
if (reset || finished) running <= 0;
else if (start) running <= 1;
else running <= running;
end
always_ff @(posedge clk) begin
if (running) idx <= idx + 1;
else idx <= 0;
end
always_comb begin
tmp = acc - {quotient, 2'b01};
if (tmp[WIDTH+1]) begin
// tmp is negative.
{acc_next, x_next} = {acc[WIDTH-1:0], x, 2'b0};
// Append a 0 to the result.
quotient_next = quotient << 1;
end else begin
// tmp is positive.
{acc_next, x_next} = {tmp[WIDTH-1:0], x, 2'b0};
// Append a 1 to the result.
quotient_next = {quotient[WIDTH-2:0], 1'b1};
end
end
always_ff @(posedge clk) begin
if (start) begin
quotient <= 0;
{acc, x} <= {{WIDTH{1'b0}}, in, 2'b0};
end else begin
x <= x_next;
acc <= acc_next;
quotient <= quotient_next;
end
end
always_ff @(posedge clk) begin
if (finished) begin
done <= 1;
out <= quotient_next;
end else if (reset) begin
done <= 0;
out <= 0;
end else begin
done <= 0;
out <= out;
end
end
endmodule
| 7.054716 |
module std_fp_add #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left + right;
endmodule
| 9.124708 |
module std_fp_sub #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left - right;
endmodule
| 8.85803 |
module std_fp_mult_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16,
parameter SIGNED = 0
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
input logic go,
input logic clk,
input logic reset,
output logic [WIDTH-1:0] out,
output logic done
);
logic [ WIDTH-1:0] rtmp;
logic [ WIDTH-1:0] ltmp;
logic [(WIDTH << 1) - 1:0] out_tmp;
// Buffer used to walk through the 3 cycles of the pipeline.
logic done_buf[2:0];
assign done = done_buf[2];
assign out = out_tmp[(WIDTH<<1)-INT_WIDTH-1 : WIDTH-INT_WIDTH];
// If the done buffer is completely empty and go is high then execution
// just started.
logic start;
assign start = go & done_buf[0] == 0 & done_buf[1] == 0;
// Start sending the done signal.
always_ff @(posedge clk) begin
if (start) done_buf[0] <= 1;
else done_buf[0] <= 0;
end
// Push the done signal through the pipeline.
always_ff @(posedge clk) begin
if (go) begin
done_buf[2] <= done_buf[1];
done_buf[1] <= done_buf[0];
end else begin
done_buf[2] <= 0;
done_buf[1] <= 0;
end
end
// Move the multiplication computation through the pipeline.
always_ff @(posedge clk) begin
if (reset) begin
rtmp <= 0;
ltmp <= 0;
out_tmp <= 0;
end else if (go) begin
if (SIGNED) begin
rtmp <= $signed(right);
ltmp <= $signed(left);
out_tmp <= $signed({{WIDTH{ltmp[WIDTH-1]}}, ltmp} * {{WIDTH{rtmp[WIDTH-1]}}, rtmp});
end else begin
rtmp <= right;
ltmp <= left;
out_tmp <= ltmp * rtmp;
end
end else begin
rtmp <= 0;
ltmp <= 0;
out_tmp <= out_tmp;
end
end
endmodule
| 6.609331 |
module std_fp_div_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic go,
input logic clk,
input logic reset,
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out_remainder,
output logic [WIDTH-1:0] out_quotient,
output logic done
);
localparam ITERATIONS = WIDTH + FRAC_WIDTH;
logic [WIDTH-1:0] quotient, quotient_next;
logic [WIDTH:0] acc, acc_next;
logic [$clog2(ITERATIONS)-1:0] idx;
logic start, running, finished, dividend_is_zero;
assign start = go && !running;
assign dividend_is_zero = start && left == 0;
assign finished = idx == ITERATIONS - 1 && running;
always_ff @(posedge clk) begin
if (reset || finished || dividend_is_zero) running <= 0;
else if (start) running <= 1;
else running <= running;
end
always_comb begin
if (acc >= {1'b0, right}) begin
acc_next = acc - right;
{acc_next, quotient_next} = {acc_next[WIDTH-1:0], quotient, 1'b1};
end else begin
{acc_next, quotient_next} = {acc, quotient} << 1;
end
end
// `done` signaling
always_ff @(posedge clk) begin
if (dividend_is_zero || finished) done <= 1;
else done <= 0;
end
always_ff @(posedge clk) begin
if (running) idx <= idx + 1;
else idx <= 0;
end
always_ff @(posedge clk) begin
if (reset) begin
out_quotient <= 0;
out_remainder <= 0;
end else if (start) begin
out_quotient <= 0;
out_remainder <= left;
end else if (go == 0) begin
out_quotient <= out_quotient;
out_remainder <= out_remainder;
end else if (dividend_is_zero) begin
out_quotient <= 0;
out_remainder <= 0;
end else if (finished) begin
out_quotient <= quotient_next;
out_remainder <= out_remainder;
end else begin
out_quotient <= out_quotient;
if (right <= out_remainder) out_remainder <= out_remainder - right;
else out_remainder <= out_remainder;
end
end
always_ff @(posedge clk) begin
if (reset) begin
acc <= 0;
quotient <= 0;
end else if (start) begin
{acc, quotient} <= {{WIDTH{1'b0}}, left, 1'b0};
end else begin
acc <= acc_next;
quotient <= quotient_next;
end
end
endmodule
| 7.871496 |
module std_fp_gt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic out
);
assign out = left > right;
endmodule
| 8.426383 |
module std_fp_sadd #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left + right);
endmodule
| 8.768295 |
module std_fp_ssub #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left - right);
endmodule
| 8.839041 |
module std_fp_smult_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input [WIDTH-1:0] left,
input [WIDTH-1:0] right,
input logic reset,
input logic go,
input logic clk,
output logic [WIDTH-1:0] out,
output logic done
);
std_fp_mult_pipe #(
.WIDTH(WIDTH),
.INT_WIDTH(INT_WIDTH),
.FRAC_WIDTH(FRAC_WIDTH),
.SIGNED(1)
) comp (
.clk(clk),
.done(done),
.reset(reset),
.go(go),
.left(left),
.right(right),
.out(out)
);
endmodule
| 7.173413 |
module std_fp_sdiv_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input clk,
input go,
input reset,
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out_quotient,
output signed [WIDTH-1:0] out_remainder,
output logic done
);
logic signed [WIDTH-1:0]
left_abs, right_abs, comp_out_q, comp_out_r, right_save, out_rem_intermediate;
// Registers to figure out how to transform outputs.
logic different_signs, left_sign, right_sign;
// Latch the value of control registers so that their available after
// go signal becomes low.
always_ff @(posedge clk) begin
if (go) begin
right_save <= right_abs;
left_sign <= left[WIDTH-1];
right_sign <= right[WIDTH-1];
end else begin
left_sign <= left_sign;
right_save <= right_save;
right_sign <= right_sign;
end
end
assign right_abs = right[WIDTH-1] ? -right : right;
assign left_abs = left[WIDTH-1] ? -left : left;
assign different_signs = left_sign ^ right_sign;
assign out_quotient = different_signs ? -comp_out_q : comp_out_q;
// Remainder is computed as:
// t0 = |left| % |right|
// t1 = if left * right < 0 and t0 != 0 then |right| - t0 else t0
// rem = if right < 0 then -t1 else t1
assign out_rem_intermediate = different_signs & |comp_out_r ? $signed(
right_save - comp_out_r
) : comp_out_r;
assign out_remainder = right_sign ? -out_rem_intermediate : out_rem_intermediate;
std_fp_div_pipe #(
.WIDTH(WIDTH),
.INT_WIDTH(INT_WIDTH),
.FRAC_WIDTH(FRAC_WIDTH)
) comp (
.reset(reset),
.clk(clk),
.done(done),
.go(go),
.left(left_abs),
.right(right_abs),
.out_quotient(comp_out_q),
.out_remainder(comp_out_r)
);
endmodule
| 8.37227 |
module std_fp_sgt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed out
);
assign out = $signed(left > right);
endmodule
| 8.236193 |
module std_fp_slt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed out
);
assign out = $signed(left < right);
endmodule
| 8.595041 |
module std_mult_pipe #(
parameter WIDTH = 32
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
input logic reset,
input logic go,
input logic clk,
output logic [WIDTH-1:0] out,
output logic done
);
std_fp_mult_pipe #(
.WIDTH(WIDTH),
.INT_WIDTH(WIDTH),
.FRAC_WIDTH(0),
.SIGNED(0)
) comp (
.reset(reset),
.clk(clk),
.done(done),
.go(go),
.left(left),
.right(right),
.out(out)
);
endmodule
| 7.504255 |
module std_div_pipe #(
parameter WIDTH = 32
) (
input reset,
input clk,
input go,
input [WIDTH-1:0] left,
input [WIDTH-1:0] right,
output logic [WIDTH-1:0] out_remainder,
output logic [WIDTH-1:0] out_quotient,
output logic done
);
logic [WIDTH-1:0] dividend;
logic [(WIDTH-1)*2:0] divisor;
logic [WIDTH-1:0] quotient;
logic [WIDTH-1:0] quotient_msk;
logic start, running, finished, dividend_is_zero;
assign start = go && !running;
assign finished = quotient_msk == 0 && running;
assign dividend_is_zero = start && left == 0;
always_ff @(posedge clk) begin
// Early return if the divisor is zero.
if (finished || dividend_is_zero) done <= 1;
else done <= 0;
end
always_ff @(posedge clk) begin
if (reset || finished || dividend_is_zero) running <= 0;
else if (start) running <= 1;
else running <= running;
end
// Outputs
always_ff @(posedge clk) begin
if (dividend_is_zero || start) begin
out_quotient <= 0;
out_remainder <= 0;
end else if (finished) begin
out_quotient <= quotient;
out_remainder <= dividend;
end else begin
// Otherwise, explicitly latch the values.
out_quotient <= out_quotient;
out_remainder <= out_remainder;
end
end
// Calculate the quotient mask.
always_ff @(posedge clk) begin
if (start) quotient_msk <= 1 << WIDTH - 1;
else if (running) quotient_msk <= quotient_msk >> 1;
else quotient_msk <= quotient_msk;
end
// Calculate the quotient.
always_ff @(posedge clk) begin
if (start) quotient <= 0;
else if (divisor <= dividend) quotient <= quotient | quotient_msk;
else quotient <= quotient;
end
// Calculate the dividend.
always_ff @(posedge clk) begin
if (start) dividend <= left;
else if (divisor <= dividend) dividend <= dividend - divisor;
else dividend <= dividend;
end
always_ff @(posedge clk) begin
if (start) begin
divisor <= right << WIDTH - 1;
end else if (finished) begin
divisor <= 0;
end else begin
divisor <= divisor >> 1;
end
end
// Simulation self test against unsynthesizable implementation.
`ifdef VERILATOR
logic [WIDTH-1:0] l, r;
always_ff @(posedge clk) begin
if (go) begin
l <= left;
r <= right;
end else begin
l <= l;
r <= r;
end
end
always @(posedge clk) begin
if (done && $unsigned(out_remainder) != $unsigned(l % r))
$error(
"\nstd_div_pipe (Remainder): Computed and golden outputs do not match!\n",
"left: %0d",
$unsigned(
l
),
" right: %0d\n",
$unsigned(
r
),
"expected: %0d",
$unsigned(
l % r
),
" computed: %0d",
$unsigned(
out_remainder
)
);
if (done && $unsigned(out_quotient) != $unsigned(l / r))
$error(
"\nstd_div_pipe (Quotient): Computed and golden outputs do not match!\n",
"left: %0d",
$unsigned(
l
),
" right: %0d\n",
$unsigned(
r
),
"expected: %0d",
$unsigned(
l / r
),
" computed: %0d",
$unsigned(
out_quotient
)
);
end
`endif
endmodule
| 6.929139 |
module std_sadd #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left + right);
endmodule
| 8.670882 |
module std_ssub #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left - right);
endmodule
| 8.103836 |
module std_smult_pipe #(
parameter WIDTH = 32
) (
input logic reset,
input logic go,
input logic clk,
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output logic signed [WIDTH-1:0] out,
output logic done
);
std_fp_mult_pipe #(
.WIDTH(WIDTH),
.INT_WIDTH(WIDTH),
.FRAC_WIDTH(0),
.SIGNED(1)
) comp (
.reset(reset),
.clk(clk),
.done(done),
.go(go),
.left(left),
.right(right),
.out(out)
);
endmodule
| 6.968167 |
module std_sdiv_pipe #(
parameter WIDTH = 32
) (
input reset,
input clk,
input go,
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed [WIDTH-1:0] out_quotient,
output logic signed [WIDTH-1:0] out_remainder,
output logic done
);
logic signed [WIDTH-1:0]
left_abs, right_abs, comp_out_q, comp_out_r, right_save, out_rem_intermediate;
// Registers to figure out how to transform outputs.
logic different_signs, left_sign, right_sign;
// Latch the value of control registers so that their available after
// go signal becomes low.
always_ff @(posedge clk) begin
if (go) begin
right_save <= right_abs;
left_sign <= left[WIDTH-1];
right_sign <= right[WIDTH-1];
end else begin
left_sign <= left_sign;
right_save <= right_save;
right_sign <= right_sign;
end
end
assign right_abs = right[WIDTH-1] ? -right : right;
assign left_abs = left[WIDTH-1] ? -left : left;
assign different_signs = left_sign ^ right_sign;
assign out_quotient = different_signs ? -comp_out_q : comp_out_q;
// Remainder is computed as:
// t0 = |left| % |right|
// t1 = if left * right < 0 and t0 != 0 then |right| - t0 else t0
// rem = if right < 0 then -t1 else t1
assign out_rem_intermediate = different_signs & |comp_out_r ? $signed(
right_save - comp_out_r
) : comp_out_r;
assign out_remainder = right_sign ? -out_rem_intermediate : out_rem_intermediate;
std_div_pipe #(
.WIDTH(WIDTH)
) comp (
.reset(reset),
.clk(clk),
.done(done),
.go(go),
.left(left_abs),
.right(right_abs),
.out_quotient(comp_out_q),
.out_remainder(comp_out_r)
);
// Simulation self test against unsynthesizable implementation.
`ifdef VERILATOR
logic signed [WIDTH-1:0] l, r;
always_ff @(posedge clk) begin
if (go) begin
l <= left;
r <= right;
end else begin
l <= l;
r <= r;
end
end
always @(posedge clk) begin
if (done && out_quotient != $signed(l / r))
$error(
"\nstd_sdiv_pipe (Quotient): Computed and golden outputs do not match!\n",
"left: %0d",
l,
" right: %0d\n",
r,
"expected: %0d",
$signed(
l / r
),
" computed: %0d",
$signed(
out_quotient
),
);
if (done && out_remainder != $signed(((l % r) + r) % r))
$error(
"\nstd_sdiv_pipe (Remainder): Computed and golden outputs do not match!\n",
"left: %0d",
l,
" right: %0d\n",
r,
"expected: %0d",
$signed(
((l % r) + r) % r
),
" computed: %0d",
$signed(
out_remainder
),
);
end
`endif
endmodule
| 7.505299 |
module std_sgt #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left > right);
endmodule
| 7.663941 |
module std_slt #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left < right);
endmodule
| 8.095256 |
module std_seq #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left == right);
endmodule
| 8.302327 |
module std_sneq #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left != right);
endmodule
| 7.44378 |
module std_sge #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left >= right);
endmodule
| 7.297458 |
module std_sle #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left <= right);
endmodule
| 8.057164 |
module std_slsh #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = left <<< right;
endmodule
| 7.70425 |
module std_srsh #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = left >>> right;
endmodule
| 8.663189 |
module computes the 16-bit square root of a 32-bit number in 16 clock cycles using the
// non-restoring algorithm. Every 2 bits of the input correspond to 1 bit of the output. The
// root (Q) is initialized to zero, then the remainder (R) is computed and the radicand (D) is
// shifted by two on each following clock cycle. The root (Q) is shifted by one on each clock
// cycle. A one is shifted in if there is no carry out from the add or subtract operation.
// Otherwise, a zero is shifted in. The adder/subtractor has two extra LSBs to implement logic
// using the two 2 MSBs of the radicand (D) and the current and previous values of the carry
// output.
//
// 62 LUT6s and 70 registers are used. The maximum clock rate is 176 MHz.
// 46 LUT6s and 54 registers are used if DL=0 and size=0.
//
// Normal Warnings:
// node <r_16> is unconnected.
//
module sqrt16a(
input [15:0] dh,dl, // radicand inputs
input size, // 0 = 16 MSB (LSB=0), 1 = 32-bit
input iv, // input valid
output [15:0] qout, // root
output [15:0] rout, // remainder
output ov, // output valid
input clk, // master clock
input rst // master reset
);
// internal signals
reg [4:0] c; // counter
reg [31:0] d; // radicand (2n bits)
reg [15:0] q; // root (n bits)
reg [17:0] r; // remainder (n+2 bits)
wire [17:0] a; // adder-subtractor
wire s; // subtract
wire nz; // counter is zero
// logic
assign nz = |c; // counter is zero if no bits are one
assign a = {r[15:0],d[31:30]} + (s ? ~{q,r[17],1'b1} : {q,r[17],1'b1}) + s;
assign s = ~r[17];
always @ (posedge clk)
begin
if (rst) c <= 0; // iteration counter
else if (iv) c <= 16; // initialize when radicand loaded
else if (nz) c <= c - 1'b1; // count down to zero
if (iv) d <= {dh,(size ? dl : 16'h0000)}; // load radicand
else if (nz) d <= {d[29:0],2'b00}; // shift left 2 bits every iteration
if (iv) q <= 0; // reset quotient
else if (nz) q <= {q[14:0],~a[17]}; // add one bit every iteration
if (iv) r <= 0; // adder/subtractor latch
else if (nz) r <= a;
end
assign qout = q; // root
assign rout = r[15:0]; // remainder
assign ov = ~nz; // zero while busy computing
endmodule
| 6.902237 |
module computes the 16-bit square root of a 16-bit number in 16 clock cycles using the
// non-restoring algorithm. Every 2 bits of the input correspond to 1 bit of the output. The
// root (Q) is initialized to zero, then the remainder (R) is computed and the radicand (D) is
// shifted by two on each following clock cycle. The root (Q) is shifted by one on each clock
// cycle. A one is shifted in if there is no carry out from the add or subtract operation.
// Otherwise, a zero is shifted in. The adder/subtractor has two extra LSBs to implement logic
// using the two 2 MSBs of the radicand (D) and the current and previous values of the carry
// output. Processing takes 17 clock cycles and the output is not latched.
//
// 54 LUT6s and 50 registers are used. The maximum clock rate is 176 MHz.
//
module sqrt16i16o(
input [15:0] din, // radicand input
input iv, // input valid
output [15:0] dout, // root output (8-bit integer / 8-bit fraction)
output ov, // output valid
input clk // master clock
);
// internal signals
reg [17:1] v; // data valid delay
reg [15:0] d; // radicand (2n bits)
reg [15:0] q; // root (n bits)
reg [17:0] r; // remainder (n+2 bits)
wire [17:0] a; // adder-subtractor
wire s; // subtract
// logic
assign a = {r[15:0],d[15:14]} + (s ? ~{q,r[17],1'b1} : {q,r[17],1'b1}) + s;
assign s = ~r[17];
always @ (posedge clk)
begin
v <= {v[16:1],iv}; // data valid delay
if (iv) d <= din; // load radicand
else d <= {d[13:0],2'b00}; // shift left 2 bits every iteration
if (iv) q <= 0; // reset quotient
else q <= {q[14:0],~a[17]}; // add one bit every iteration
if (iv) r <= 0; // adder/subtractor latch
else r <= a;
end
assign dout = q; // root
assign ov = v[17]; // output valid
endmodule
| 6.902237 |
module testBench;
parameter ss = 5;
parameter w = 1 << ss; //need to change in 2 places 2/2
//parameter Amax= 2000000;
parameter Amax = 10001; //quick test
reg [w-1:0] A;
reg clk, reset;
wire [(w/2)-1:0] Z;
wire done;
sqrt dut (
.clk(clk),
.rdy(done),
.reset(reset),
.x(A),
.acc(Z)
);
(* ivl_synthesis_off *)
always #5 clk = !clk;
task reset_dut;
begin
reset = 1;
@(posedge clk);
#1 reset = 0;
@(negedge clk);
end
endtask
task run_dut;
begin
while (done == 0) begin
@(posedge clk);
end
end
endtask
integer idx, a, z, errCnt;
(* ivl_synthesis_off *)
initial begin
reset = 0;
clk = 0;
$display("ss=%d, width=%d, Amax=%d", ss, w, Amax);
errCnt = 0;
A = 4;
reset_dut;
run_dut;
$display("test=0 x=%d, y=%d", A, Z);
A = Amax / 10;
reset_dut;
run_dut;
$display("test=0 x=%d, y=%d", A, Z);
A = Amax - 1;
reset_dut;
run_dut;
$display("test=0 x=%d, y=%d", A, Z);
for (idx = 1; idx < Amax; idx = 2 * idx) begin
A = idx;
reset_dut;
run_dut;
$display("%d: x=%d, y=%d", idx, A, Z);
a = A;
z = Z;
if (a < (z * z)) begin
$display("test=%d x=%d, y=%d ERROR:y is too big", idx, A, Z);
$display("FAILED");
$finish;
end
if (z<65535) // at this number y*y overflows, so cannot test this way
begin
if (a >= ((z + 1) * (z + 1))) begin
$display("test=%d x=%d, y=%d ERROR: y is too small", idx, A, Z);
$display("FAILED");
$finish;
end
end else begin
$display("Could not verify above number");
end
end
$display("Running tests Amax=%d random input numbers", Amax);
for (idx = 0; idx < Amax; idx = 1 + idx) begin
A = $random;
// A = A - ((A / Amax) * Amax); //this is needed only if <32 bit
//A = idx; //sequential -- comment out to get random tests
if (A < 1 << (w - 1)) begin
reset_dut;
run_dut;
//$display("%d: x=%d, y=%d", idx, A, Z);
a = A;
z = Z;
if (a < (z * z)) begin
$display("test=%d x=%d, y=%d ERROR:y is too big", idx, A, Z);
$display("FAILED");
$finish;
end
if (z<65535) // at this number y*y overflows, so cannot test this way
begin
if (a >= ((z + 1) * (z + 1))) begin
$display("test=%d x=%d, y=%d ERROR: y is too small", idx, A, Z);
$display("FAILED");
$finish;
end
end else begin
$display("Could not verify above number");
end
//$display("%d: x=%d, y=%d", idx, A, Z);
if (idx % 1000 == 0) $display("Finished %d tests", idx);
end // if (A < Amax) begin
end
$display("PASSED");
$finish;
end
endmodule
| 6.519976 |
module sqrtfcn_dcmp_64ns_64ns_1_3 #(
parameter ID = 8,
NUM_STAGE = 3,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 1
) (
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
input wire [ 4:0] opcode,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Parameter----------------------
// AutoESL opcode
localparam [4:0]
AP_OEQ = 5'b00001,
AP_OGT = 5'b00010,
AP_OGE = 5'b00011,
AP_OLT = 5'b00100,
AP_OLE = 5'b00101,
AP_ONE = 5'b00110,
AP_UNO = 5'b01000;
// FPV6 opcode
localparam [7:0]
OP_EQ = 8'b00010100,
OP_GT = 8'b00100100,
OP_GE = 8'b00110100,
OP_LT = 8'b00001100,
OP_LE = 8'b00011100,
OP_NE = 8'b00101100,
OP_UO = 8'b00000100;
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [ 63:0] a_tdata;
wire b_tvalid;
wire [ 63:0] b_tdata;
wire op_tvalid;
reg [ 7:0] op_tdata;
wire r_tvalid;
wire [ 7:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
reg [ 4:0] opcode_buf1;
//------------------------Instantiation------------------
dcmp_v7 dcmp_v7_u (
.aclk (aclk),
.aclken (aclken),
.s_axis_a_tvalid (a_tvalid),
.s_axis_a_tdata (a_tdata),
.s_axis_b_tvalid (b_tvalid),
.s_axis_b_tdata (b_tdata),
.s_axis_operation_tvalid(op_tvalid),
.s_axis_operation_tdata (op_tdata),
.m_axis_result_tvalid (r_tvalid),
.m_axis_result_tdata (r_tdata)
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = r_tdata[0];
always @(*) begin
case (opcode_buf1)
AP_OEQ: op_tdata = OP_EQ;
AP_OGT: op_tdata = OP_GT;
AP_OGE: op_tdata = OP_GE;
AP_OLT: op_tdata = OP_LT;
AP_OLE: op_tdata = OP_LE;
AP_ONE: op_tdata = OP_NE;
AP_UNO: op_tdata = OP_UO;
default: op_tdata = OP_EQ;
endcase
end
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
opcode_buf1 <= opcode;
end
end
endmodule
| 6.540151 |
module sqrtfcn_ddiv_64ns_64ns_64_14 #(
parameter ID = 7,
NUM_STAGE = 14,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
) (
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [ 63:0] a_tdata;
wire b_tvalid;
wire [ 63:0] b_tdata;
wire r_tvalid;
wire [ 63:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
reg [dout_WIDTH-1:0] out_buf0;
reg [dout_WIDTH-1:0] out_buf1;
reg [dout_WIDTH-1:0] out_buf2;
reg [dout_WIDTH-1:0] out_buf3;
reg [dout_WIDTH-1:0] out_buf4;
reg [dout_WIDTH-1:0] out_buf5;
reg [dout_WIDTH-1:0] out_buf6;
reg [dout_WIDTH-1:0] out_buf7;
reg [dout_WIDTH-1:0] out_buf8;
reg [dout_WIDTH-1:0] out_buf9;
reg [dout_WIDTH-1:0] out_buf10;
//------------------------Instantiation------------------
ddiv_v7 ddiv_v7_u (
.aclk (aclk),
.aclken (aclken),
.s_axis_a_tvalid (a_tvalid),
.s_axis_a_tdata (a_tdata),
.s_axis_b_tvalid (b_tvalid),
.s_axis_b_tdata (b_tdata),
.m_axis_result_tvalid(r_tvalid),
.m_axis_result_tdata (r_tdata)
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = out_buf10;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
always @(posedge clk) begin
if (ce) begin
out_buf0 <= r_tdata;
out_buf1 <= out_buf0;
out_buf2 <= out_buf1;
out_buf3 <= out_buf2;
out_buf4 <= out_buf3;
out_buf5 <= out_buf4;
out_buf6 <= out_buf5;
out_buf7 <= out_buf6;
out_buf8 <= out_buf7;
out_buf9 <= out_buf8;
out_buf10 <= out_buf9;
end
end
endmodule
| 6.882983 |
module sqrtfcn_dmul_64ns_64ns_64_4_max_dsp #(
parameter ID = 6,
NUM_STAGE = 4,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
) (
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [ 63:0] a_tdata;
wire b_tvalid;
wire [ 63:0] b_tdata;
wire r_tvalid;
wire [ 63:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
reg [dout_WIDTH-1:0] out_buf0;
//------------------------Instantiation------------------
dmul_v7 dmul_v7_u (
.aclk (aclk),
.aclken (aclken),
.s_axis_a_tvalid (a_tvalid),
.s_axis_a_tdata (a_tdata),
.s_axis_b_tvalid (b_tvalid),
.s_axis_b_tdata (b_tdata),
.m_axis_result_tvalid(r_tvalid),
.m_axis_result_tdata (r_tdata)
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = out_buf0;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
always @(posedge clk) begin
if (ce) begin
out_buf0 <= r_tdata;
end
end
endmodule
| 7.083523 |
module sqrtfcn_fdiv_32ns_32ns_32_8 #(
parameter ID = 2,
NUM_STAGE = 8,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
) (
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [ 31:0] a_tdata;
wire b_tvalid;
wire [ 31:0] b_tdata;
wire r_tvalid;
wire [ 31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
reg [dout_WIDTH-1:0] out_buf0;
reg [dout_WIDTH-1:0] out_buf1;
reg [dout_WIDTH-1:0] out_buf2;
reg [dout_WIDTH-1:0] out_buf3;
reg [dout_WIDTH-1:0] out_buf4;
//------------------------Instantiation------------------
fdiv_v7 fdiv_v7_u (
.aclk (aclk),
.aclken (aclken),
.s_axis_a_tvalid (a_tvalid),
.s_axis_a_tdata (a_tdata),
.s_axis_b_tvalid (b_tvalid),
.s_axis_b_tdata (b_tdata),
.m_axis_result_tvalid(r_tvalid),
.m_axis_result_tdata (r_tdata)
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = out_buf4;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
always @(posedge clk) begin
if (ce) begin
out_buf0 <= r_tdata;
out_buf1 <= out_buf0;
out_buf2 <= out_buf1;
out_buf3 <= out_buf2;
out_buf4 <= out_buf3;
end
end
endmodule
| 6.504234 |
module sqrtfcn_fmul_32ns_32ns_32_3_max_dsp #(
parameter ID = 1,
NUM_STAGE = 3,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
) (
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [ 31:0] a_tdata;
wire b_tvalid;
wire [ 31:0] b_tdata;
wire r_tvalid;
wire [ 31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
fmul_v7 fmul_v7_u (
.aclk (aclk),
.aclken (aclken),
.s_axis_a_tvalid (a_tvalid),
.s_axis_a_tdata (a_tdata),
.s_axis_b_tvalid (b_tvalid),
.s_axis_b_tdata (b_tdata),
.m_axis_result_tvalid(r_tvalid),
.m_axis_result_tdata (r_tdata)
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
| 6.731233 |
module sqrtfcn_fptrunc_64ns_32_3 #(
parameter ID = 3,
NUM_STAGE = 3,
din0_WIDTH = 64,
dout_WIDTH = 32
) (
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [ 63:0] a_tdata;
wire r_tvalid;
wire [ 31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
//------------------------Instantiation------------------
dptofp_v7 dptofp_v7_u (
.aclk (aclk),
.aclken (aclken),
.s_axis_a_tvalid (a_tvalid),
.s_axis_a_tdata (a_tdata),
.m_axis_result_tvalid(r_tvalid),
.m_axis_result_tdata (r_tdata)
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
end
end
endmodule
| 6.820691 |
module SqrtMantissa (
in,
isFloat,
isExponentOdd,
mantissa,
isDone
);
parameter BINARY_SIZE = 8'd106, // must be even
HALF_BINARY_SIZE = 8'd53, MANTISSA_SIZE = 6'd52;
input isFloat, isExponentOdd;
input [BINARY_SIZE - 1:0] in;
output [MANTISSA_SIZE - 1:0] mantissa;
output isDone;
wire [HALF_BINARY_SIZE-1:0] binarySquareRootOut;
reg isBinarySquareRootDone;
SqrtBinary #(
.SIZE(BINARY_SIZE),
.HALF_SIZE(HALF_BINARY_SIZE)
) sqrtBinary (
.p(in),
.u(binarySquareRootOut)
);
always @(binarySquareRootOut[0]) begin
isBinarySquareRootDone = 1;
end
ConvertBinaryToMantissa convertBinaryToMantissa (
.en(isBinarySquareRootDone),
.isFloat(isFloat),
.isExponentOdd(isExponentOdd),
.in(binarySquareRootOut),
.mantissa(mantissa),
.isDone(isDone)
);
endmodule
| 6.971424 |
module tb ();
reg clk, reset;
reg [30:0] x;
wire [16:0] SqrtValue;
initial begin
clk = 1'b0;
reset = 1'b1;
#30;
reset = 1'b0;
x = 31'b111111_11_11111111_11111111_1111111; // 128
#20;
x = 31'b00000010_00000000_00000000_0000000; // 1
#20;
x = 31'b00000100_00000000_00000000_0000000; // 2
#20;
x = 31'b00001000_00000000_00000000_0000000; // 4
#20;
x = 31'b00010010_00000000_00000000_0000000; // 9
#20;
x = 31'b01000110_00000000_00000000_0000000; // 35
#20;
#20;
$finish;
end
always #10 clk = !clk;
always @(posedge clk) $display("Sqrt = %b", SqrtValue);
SQRT_POLY l1 (
clk,
reset,
x,
SqrtValue
);
endmodule
| 7.195167 |
module SQRT_BL (
input [2*`m-1:0] X,
output reg [`m-1:0] Q = 0,
input st,
output reg en = 0,
input clk
);
wire [2*`m-1:0] M = Q * Q;
wire DI = (M <= X);
//--- ---
reg [`m:0] T = 0; // T
integer i; // for
always @(posedge clk) begin
T <= st ? 1 << `m : en ? T >> 1 : T; // T
Q[`m-1] <= st ? 1 : T[`m] ? DI : Q[`m-1]; // Q
for (i = `m - 2; i >= 0; i = i - 1) // for
Q[i] <= st ? 0 : T[i+2] ? 1 : T[i+1] ? DI : Q[i]; // Q
en <= st ? 1 : (T[0] & en) ? 0 : en; //
end
endmodule
| 6.633734 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pow_module(Clk, data_in, reset, enable, textOut, next, done);
input Clk;
input [7:0] data_in;
input reset;
input enable;
input next;
output reg [8*32:0] textOut;
output reg done;
integer data_out;
reg [7:0] input_A;
reg [7:0] input_B;
reg [15:0] out;
reg Ready;
reg [4:0] state;
localparam
START = 5'b00001,
LOAD_A = 5'b00010,
LOAD_B = 5'b00100,
CALCULATE = 5'b01000,
DONE = 5'b10000;
always @(posedge Clk, posedge reset)
begin
//if (!enable)
//begin
//end
//else
//begin
if (reset)
begin
state <= START;
end
else
begin
case (state)
START:
begin
textOut = "Pow Powers a Number ";
input_A <= 0;
done <= 0;
data_out <= 0;
out <= 0;
Ready <= 0;
if (next && enable)
state <= LOAD_A;
end
LOAD_A:
begin
textOut = "Input 1st # Then Press Btnc ";
if (next)
begin
input_A <= data_in;
state <= LOAD_B;
end
end
LOAD_B:
begin
textOut = "Input 2nd # Then Press Btnc ";
if (next)
begin
input_B <= data_in;
data_out <= 1;
if (data_in == 0)
Ready <= 1;
state <= CALCULATE;
end
end
CALCULATE:
begin
textOut = {"Calculating... ",Ready?"Press Btnc ":" "};
if (!Ready)
begin
data_out <= data_out * input_A;
input_B <= input_B - 1;
if (input_B - 1 == 0)
Ready <= 1;
end
else if (next)
state <= DONE;
end
DONE:
begin
textOut = {"The Power is: ", bin2x(data_out[23:20]),bin2x(data_out[19:16]),bin2x(data_out[15:12]),bin2x(data_out[11:8]),bin2x(data_out[7:4]),bin2x(data_out[3:0]), " "};
done <= 1;
end
endcase
end
//end
end
function [7:0] bin2x;
input [3:0] data;
begin
case (data)
4'h0: bin2x = "0";4'h1: bin2x = "1";4'h2: bin2x = "2";4'h3: bin2x = "3";
4'h4: bin2x = "4";4'h5: bin2x = "5";4'h6: bin2x = "6";4'h7: bin2x = "7";
4'h8: bin2x = "8";4'h9: bin2x = "9";4'hA: bin2x = "A";4'hB: bin2x = "B";
4'hC: bin2x = "C";4'hD: bin2x = "D";4'hE: bin2x = "E";4'hF: bin2x = "F";
default:bin2x = "0";
endcase
end
endfunction
endmodule
| 7.088073 |
module SQRT (
CLK,
RST,
DATA_IN,
DATA_OUT
);
input CLK, RST;
input [15:0] DATA_IN;
output [15:0] DATA_OUT;
wire SEL_REG_0;
wire [1:0] SEL_REG_1;
wire [1:0] SEL_REG_2;
wire [1:0] SEL_REG_3;
wire [1:0] SEL_ADD_0;
wire [1:0] SEL_ADD_1;
wire CTRL;
DATAPATH DATAPATH (
// Inputs
CLK,
RST,
DATA_IN,
SEL_REG_0,
SEL_REG_1,
SEL_REG_2,
SEL_REG_3,
SEL_ADD_0,
SEL_ADD_1,
// Outputs
CTRL,
DATA_OUT
);
CONTROLLER CONTROLLER (
// Inputs
CLK,
RST,
CTRL,
// Outputs
SEL_REG_0,
SEL_REG_1,
SEL_REG_2,
SEL_REG_3,
SEL_ADD_0,
SEL_ADD_1
);
endmodule
| 7.3448 |
module DATAPATH (
CLK,
RST,
DATA_IN,
IN_SEL_REG_0,
IN_SEL_REG_1,
IN_SEL_REG_2,
IN_SEL_REG_3,
IN_SEL_ADD_0,
IN_SEL_ADD_1,
CTRL,
DATA_OUT
);
input CLK, RST;
input [15:0] DATA_IN;
input IN_SEL_REG_0;
input [1:0] IN_SEL_REG_1;
input [1:0] IN_SEL_REG_2;
input [1:0] IN_SEL_REG_3;
input [1:0] IN_SEL_ADD_0;
input [1:0] IN_SEL_ADD_1;
output CTRL;
output [15:0] DATA_OUT;
// Registers
reg [15:0] REG_0, REG_1, REG_2, REG_3;
// Wires
wire [15:0] DATA_IN_MUL_0, DATA_IN_MUL_1, DATA_OUT_MUL;
wire [15:0] DATA_IN_DIV_0, DATA_IN_DIV_1, DATA_OUT_DIV;
wire [15:0] DATA_IN_ADD_0, DATA_IN_ADD_1, DATA_OUT_ADD;
wire [15:0] DATA_IN_CMP_0, DATA_IN_CMP_1;
wire [15:0] DATA_IN_SHIFT, DATA_OUT_SHIFT;
always @(posedge CLK or posedge RST) begin
if (RST) begin
REG_0 <= 16'd0;
REG_1 <= 16'd0;
REG_2 <= 16'd0;
REG_3 <= 16'd0;
end else begin
REG_0 <= MUX_2_TO_1(DATA_IN, REG_0, IN_SEL_REG_0);
REG_1 <= MUX_4_TO_1(REG_1, DATA_OUT_ADD, DATA_OUT_DIV, DATA_OUT_SHIFT, IN_SEL_REG_1);
REG_2 <= MUX_3_TO_1(REG_1, DATA_OUT_MUL, DATA_OUT_ADD, IN_SEL_REG_2);
REG_3 <= MUX_3_TO_1(16'b0000000000000000, REG_3, DATA_OUT_ADD, IN_SEL_REG_3);
end
end
// -------------------------------- //
// FU's input
// -------------------------------- //
assign DATA_IN_MUL_0 = 16'b0000000011100011; // これは 0.89
assign DATA_IN_MUL_1 = REG_0;
assign DATA_IN_DIV_0 = REG_0;
assign DATA_IN_DIV_1 = REG_1;
assign DATA_IN_ADD_0 = MUX_3_TO_1(
16'b0000000000111000, 16'b0000000100000000, REG_2, IN_SEL_ADD_0
); // これは 0.22 と 1
assign DATA_IN_ADD_1 = MUX_3_TO_1(REG_1, REG_2, REG_3, IN_SEL_ADD_1);
assign DATA_IN_CMP_0 = REG_3;
assign DATA_IN_CMP_1 = 16'b0000010100000000; // これは 5 (ループ回数 を指定する)
assign DATA_IN_SHIFT = REG_2;
function [15:0] MUX_2_TO_1;
input [15:0] IN_0;
input [15:0] IN_1;
input IN_SEL;
reg [15:0] ANSWER;
begin
if (IN_SEL == 0) ANSWER = IN_0;
else if (IN_SEL == 1) ANSWER = IN_1;
else ANSWER = 16'bxxxxxxxxxxxxxxxx;
MUX_2_TO_1 = ANSWER;
end
endfunction
function [15:0] MUX_3_TO_1;
input [15:0] IN_0;
input [15:0] IN_1;
input [15:0] IN_2;
input [1:0] IN_SEL;
reg [15:0] ANSWER;
begin
if (IN_SEL == 0) ANSWER = IN_0;
else if (IN_SEL == 1) ANSWER = IN_1;
else if (IN_SEL == 2) ANSWER = IN_2;
else ANSWER = 16'bxxxxxxxxxxxxxxxx;
MUX_3_TO_1 = ANSWER;
end
endfunction
function [15:0] MUX_4_TO_1;
input [15:0] IN_0;
input [15:0] IN_1;
input [15:0] IN_2;
input [15:0] IN_3;
input [1:0] IN_SEL;
reg [15:0] ANSWER;
begin
if (IN_SEL == 0) ANSWER = IN_0;
else if (IN_SEL == 1) ANSWER = IN_1;
else if (IN_SEL == 2) ANSWER = IN_2;
else if (IN_SEL == 3) ANSWER = IN_3;
else ANSWER = 16'bxxxxxxxxxxxxxxxx;
MUX_4_TO_1 = ANSWER;
end
endfunction
ADDER ADDER (
DATA_IN_ADD_0,
DATA_IN_ADD_1,
DATA_OUT_ADD
);
MULTIPLIER MULTIPLIER (
DATA_IN_MUL_0,
DATA_IN_MUL_1,
DATA_OUT_MUL
);
DIVIDER DIVIDER (
DATA_IN_DIV_0,
DATA_IN_DIV_1,
DATA_OUT_DIV
);
COMPARATOR COMPARATOR (
DATA_IN_CMP_0,
DATA_IN_CMP_1,
CTRL
);
SHIFTER SHIFTER (
DATA_IN_SHIFT,
DATA_OUT_SHIFT
);
assign DATA_OUT = REG_1;
endmodule
| 6.685613 |
module ADDER (
A,
B,
Y
);
input [15:0] A;
input [15:0] B;
output [15:0] Y;
assign Y = A + B;
endmodule
| 7.327585 |
module COMPARATOR (
A,
B,
Y
);
input [15:0] A;
input [15:0] B;
output Y;
assign Y = A < B;
//always @(A or B) begin
// if (A < B)
// assign Y = 1'b1;
// else
// assign Y = 1'b0;
//end
endmodule
| 7.309761 |
module for the Square Root unit
`timescale 1ns/1ps
module Sqrt_range(exp_f,LZD_Sqrt,y_f,f_temp);
input [5:0] exp_f;
input [5:0] LZD_Sqrt;
input [20:0] y_f;
output [20:0] f_temp;
reg [20:0] f_temp;
reg [5:0] exp_f_1;
always@(exp_f or LZD_Sqrt or y_f or exp_f_1)
begin
//Performing Left or Right shift based of the value of exp_f[0]
exp_f_1 <= (exp_f[0])?((LZD_Sqrt-6'b010001) < 6)?((6 - (LZD_Sqrt-6'b010001))>>1):(((LZD_Sqrt-6'b010001) - 5)>>1):((LZD_Sqrt-6'b010001) < 6)?((5 - (LZD_Sqrt-6'b010001))>>1):(((LZD_Sqrt-6'b010001) - 5)>>1);
f_temp <= ((LZD_Sqrt-6'b010001) < 6)?(y_f << exp_f_1):(y_f >> exp_f_1);
end
endmodule
| 6.768337 |
module sqrt_range_reconst (
input iClk,
input [5:0] iExp_f1,
input [21:0] iY_f,
output [16:0] oF
);
reg [23:0] rf = 0;
// wire [5:0] wExp_f;
reg [5:0] wExp_f, wExp_f1, wExp_f2;
reg [5:0] rExp_f = 0;
reg [5:0] rExp_fr = 0;
// assign wExp_f = iExp_f1;
always @(posedge iClk) begin
wExp_f2 <= iExp_f1;
wExp_f1 <= wExp_f2;
wExp_f <= wExp_f1;
end
always @(posedge iClk) begin
if (wExp_f <= 5) begin
rExp_f = {6'b000101} - {wExp_f};
if (rExp_f[0] == 1'b1) rExp_fr = {rExp_f + 1} >> 1;
else rExp_fr = {rExp_f} >> 1;
rf = {2'b00, iY_f} << rExp_fr;
end else if (wExp_f == 6) rf = {2'b00, iY_f};
else begin
rExp_f = {wExp_f} - {3'd5};
if (rExp_f[0] == 1'b1) rExp_fr = {rExp_f} >> 1;
else rExp_fr = {rExp_f} >> 1;
rf = {2'b00, iY_f} >> rExp_fr;
end
end
assign oF = rf[23:7];
endmodule
| 6.766597 |
module sqrt_range_reduction (
// Input data
input wire [30:0] iE,
// Onput data
output wire [25:0] oX_f,
output wire [ 5:0] oExp_f,
output wire [ 5:0] oExp_f1
);
//Intermediate data
wire [ 5:0] wExp_f1;
reg [ 5:0] rExp_f;
reg [ 5:0] rExp_fr;
reg [30:0] rX_f;
reg [30:0] rX_f1;
wire [25:0] wX_f1;
wire [19:0] wY_f;
reg [19:0] rf;
//3 bit leading zero detector
LZD1 lzd2 (
.data_in (iE),
.data_out(wExp_f1)
);
always @* begin
//when input data >1.0000
if (wExp_f1 <= 5) begin
rExp_f = {6'b000101} - {wExp_f1};
rX_f1 = iE >> {rExp_f};
end //when input data =1.0000
else if (wExp_f1 == 6) begin
rX_f1 = iE;
rExp_f = 0;
end //when input data <1.0000
else begin
rExp_f = {wExp_f1} - {3'd5};
rX_f1 = iE << {rExp_f};
end
// rX_f1 = wE >> {wExp_f};
if (rExp_f[0] == 1'b1) rX_f = rX_f1 >> 1'b1;
else rX_f = rX_f1;
end
assign wX_f1 = rX_f1[25:0];
assign oX_f = rX_f[25:0];
assign oExp_f = rExp_f;
assign oExp_f1 = wExp_f1;
endmodule
| 6.766597 |
module sqrt_remainder #(
parameter RADICAND_WIDTH = 8,
parameter STAGE_NUMBER = 3
) (
input wire [`INTEGER_INPUT_WIDTH-1:0] integer_input,
input wire [`REMAINDER_INPUT_WIDTH-1:0] remainder_previous,
input wire [(`RESULT_INPUT_WIDTH-1 + `IS_FIRST_STAGE):0] result_previous, // we need to force the first input to have a size of 1 for the first block
output reg [`INTEGER_OUTPUT_WIDTH-1:0] integer_output,
output reg signed [`REMAINDER_OUTPUT_WIDTH-1:0] remainder,
output reg [`RESULT_OUTPUT_WIDTH-1:0] result,
input wire reset,
input wire clk
);
reg phase; // state variable
// the following wires are used to force twos-complement arithmetic
wire signed [`REMAINDER_OUTPUT_WIDTH-1:0] remainder_new_without_add;
assign remainder_new_without_add = {
remainder_previous[`REMAINDER_INPUT_WIDTH-2:0], // drop the sign bit
integer_input[{STAGE_NUMBER, 1'b1}], // integer_input[2 * bit + 1]
integer_input[{STAGE_NUMBER, 1'b0}] // integer_input[2 * bit]
};
wire signed [`REMAINDER_OUTPUT_WIDTH-1:0] remainder_greater_than_or_equal_to_0_subtractor;
wire signed [`REMAINDER_OUTPUT_WIDTH-1:0] remainder_less_than_0_addition;
assign remainder_greater_than_or_equal_to_0_subtractor = {result_previous, 2'b01};
assign remainder_less_than_0_addition = {result_previous, 2'b11};
reg signed [`REMAINDER_OUTPUT_WIDTH-1:0] remainder_delay;
reg [`INTEGER_INPUT_WIDTH-1:0] integer_output_delay;
reg [(`RESULT_INPUT_WIDTH-1 + `IS_FIRST_STAGE):0] result_previous_delay;
always @(posedge clk) begin
//if (reset == 1'b0) phase <= 0;
//else begin
//if (phase == 1'b0) begin
// phase 1: calculate new remainder
if (remainder_previous[`REMAINDER_INPUT_WIDTH-1] == 1'b0) begin // if sign bit indicates the number is positive
remainder_delay <= remainder_new_without_add - remainder_greater_than_or_equal_to_0_subtractor;
end else begin
remainder_delay <= remainder_new_without_add + remainder_less_than_0_addition;
end
remainder <= remainder_delay;
// save the integer into our local shift register, while dropping the top two bits
// we need to force the output to have a size of 1 for the last block in the chain
integer_output_delay <= integer_input[(`INTEGER_OUTPUT_WIDTH-1+`IS_LAST_STAGE):0];
integer_output <= integer_output_delay;
//end else begin
result_previous_delay <= result_previous;
// phase 2: calculate new result
if (remainder_delay[`REMAINDER_OUTPUT_WIDTH-1] != 1'b1) begin // if it is positive
result <= {result_previous_delay, 1'b1};
end else begin
result <= {result_previous_delay, 1'b0};
if (`IS_LAST_STAGE) remainder <= remainder_delay + {result_previous_delay, 2'b01};
end
//end
//phase <= ~phase;
//end
end
// initial begin
// $display("sqrt_remainder block: RADICAND_WIDTH: %d, STAGE_NUMBER: %d (IS_FIRST_STAGE: %d, IS_LAST_STAGE: %d)", RADICAND_WIDTH, STAGE_NUMBER, `IS_FIRST_STAGE, `IS_LAST_STAGE);
// $display("\tINTEGER_INPUT_WIDTH: \t\t%d", `INTEGER_INPUT_WIDTH);
// $display("\tINTEGER_OUTPUT_WIDTH: \t\t%d", `INTEGER_OUTPUT_WIDTH);
// $display("\tREMAINDER_INPUT_WIDTH: \t\t%d", `REMAINDER_INPUT_WIDTH);
// $display("\tREMAINDER_OUTPUT_WIDTH: \t\t%d", `REMAINDER_OUTPUT_WIDTH);
// $display("\tRESULT_INPUT_WIDTH: \t\t%d", `RESULT_INPUT_WIDTH);
// $display("\tRESULT_OUTPUT_WIDTH: \t\t%d", `RESULT_OUTPUT_WIDTH);
// end
endmodule
| 6.906991 |
module sqrt_ROM (
n,
sqrto
);
input [3:0] n; //unsigned number
output reg [31:0] sqrto;
real sqrt;
wire [1:0] sqrt_int;
wire [29:0] sqrt_dp;
always @(n) begin
case (n + 1)
0: sqrt <= 0.000;
1: sqrt <= 1.000;
2: sqrt <= 1.414;
3: sqrt <= 1.732;
4: sqrt <= 2.000;
5: sqrt <= 2.236;
6: sqrt <= 2.448;
7: sqrt <= 2.645;
8: sqrt <= 2.828;
9: sqrt <= 3.000;
10: sqrt <= 3.162;
11: sqrt <= 3.316;
12: sqrt <= 3.464;
13: sqrt <= 3.605;
14: sqrt <= 3.741;
15: sqrt <= 3.872;
default: sqrt <= 0.000;
endcase
sqrto = $shortrealtobits(sqrt);
end
assign sqrt_int = sqrto[31:30];
assign sqrt_dp = sqrto[29:0];
endmodule
| 7.216778 |
module sqrt_ROMTB ();
reg [ 3:0] n;
wire [31:0] sqrt;
sqrt_ROM(
.n(n), .sqrto(sqrt)
);
initial begin
$monitor("n = %b = %d, sqrt = %f", n, n, $bitstoshortreal(sqrt));
end
initial begin : apply_stimulus
reg [4:0] i;
for (i = 0; i <= 15; i = i + 1) begin
n = i;
#1;
end
#1;
end
endmodule
| 7.158066 |
module is a test bench for the sqrt32 module. It runs some
* test input values through the sqrt32 module, and checks that the
* output is valid. If an invalid output is generated, print and
* error message and stop immediately. If all the tested values pass,
* then print PASSED after the test is complete.
*/
module main;
reg [31:0] x;
reg clk, reset;
wire [15:0] y;
wire rdy;
chip_root dut(.clk(clk), .reset(reset), .rdy(rdy), .x(x), .y(y));
(* ivl_synthesis_off *)
always #5 clk = !clk;
task reset_dut;
begin
reset = 1;
#1 reset = 0;
@(negedge clk) ;
end
endtask // reset_dut
task crank_dut;
begin
while (rdy == 0) begin
@(posedge clk) /* wait */;
end
end
endtask // crank_dut
reg GSR;
assign glbl.GSR = GSR;
integer idx;
(* ivl_synthesis_off *)
initial begin
reset = 0;
clk = 0;
/* If doing a post-map simulation, when we need to wiggle
The GSR bit to simulate chip power-up. */
GSR = 1;
#100 GSR = 0;
#100 x = 1;
reset_dut;
crank_dut;
$display("x=%d, y=%d", x, y);
x = 3;
reset_dut;
crank_dut;
$display("x=%d, y=%d", x, y);
x = 4;
reset_dut;
crank_dut;
$display("x=%d, y=%d", x, y);
for (idx = 0 ; idx < 200 ; idx = idx + 1) begin
x = $random;
reset_dut;
crank_dut;
$display("x=%d, y=%d", x, y);
if (x < (y * y)) begin
$display("ERROR: y is too big");
$finish;
end
if (x > ((y + 1)*(y + 1))) begin
$display("ERROR: y is too small");
$finish;
end
end
$display("PASSED");
$finish;
end
endmodule
| 6.595812 |
module sqrt_Top (
start,
clk,
clear,
num,
result,
ready
);
input start, clk, clear;
input [6:0] num;
output [3:0] result;
output ready;
wire finish, load_data, incr_delta, find_next_sq;
sqrt_controller m1 (
start,
finish,
clk,
clear,
ready,
load_data,
incr_delta,
find_next_sq
);
sqrt_data_path m2 (
num,
load_data,
incr_delta,
find_next_sq,
clk,
finish,
result,
clear
);
endmodule
| 6.659984 |
module sqrt_Top (
start,
clk,
clear,
num,
result,
ready,
test_si,
test_so,
test_se
);
input [6:0] num;
output [3:0] result;
input start, clk, clear, test_si, test_se;
output ready, test_so;
wire finish, load_data, incr_delta, find_next_sq, n3, n5, n6, n7;
sqrt_controller_test_1 m1 (
.start(start),
.finish(finish),
.clk(clk),
.clear(clear),
.ready(ready),
.load_data(load_data),
.incr_delta(incr_delta),
.find_next_sq(find_next_sq),
.test_si(test_si),
.test_so(n3),
.test_se(n6)
);
sqrt_data_path_test_1 m2 (
.num(num),
.load_data(load_data),
.incr_delta(incr_delta),
.find_next_sq(find_next_sq),
.clk(clk),
.finish(finish),
.result(result),
.clear(clear),
.test_si(n3),
.test_so(test_so),
.test_se(n6)
);
INVX0 U1 (
.INP(n7),
.ZN (n5)
);
INVX0 U2 (
.INP(n5),
.ZN (n6)
);
DELLN2X2 U3 (
.INP(test_se),
.Z (n7)
);
endmodule
| 6.659984 |
module sqrt_Top (
start,
clk,
clear,
num,
result,
ready
);
input [6:0] num;
output [3:0] result;
input start, clk, clear;
output ready;
wire finish, load_data, incr_delta, find_next_sq;
sqrt_controller m1 (
.start(start),
.finish(finish),
.clk(clk),
.clear(clear),
.ready(ready),
.load_data(load_data),
.incr_delta(incr_delta),
.find_next_sq(find_next_sq)
);
sqrt_data_path m2 (
.num(num),
.load_data(load_data),
.incr_delta(incr_delta),
.find_next_sq(find_next_sq),
.clk(clk),
.finish(finish),
.result(result),
.clear(clear)
);
endmodule
| 6.659984 |
module sqrt_Top (
start,
clk,
clear,
num,
result,
ready
);
input [6:0] num;
output [3:0] result;
input start, clk, clear;
output ready;
wire finish, load_data, incr_delta, find_next_sq;
sqrt_controller m1 (
.start(start),
.finish(finish),
.clk(clk),
.clear(clear),
.ready(ready),
.load_data(load_data),
.incr_delta(incr_delta),
.find_next_sq(find_next_sq)
);
sqrt_data_path m2 (
.num(num),
.load_data(load_data),
.incr_delta(incr_delta),
.find_next_sq(find_next_sq),
.clk(clk),
.finish(finish),
.result(result),
.clear(clear)
);
endmodule
| 6.659984 |
module m_draw_rectangle #(
parameter ADDR_WIDTH = 8,
DATA_WIDTH = 4,
DEPTH = 256
) (
input wire clk,
input wire i_write,
input wire [10:0] current_x,
input wire [10:0] current_y,
input wire [10:0] half_width,
input wire [10:0] half_height,
input wire [DATA_WIDTH-1:0] i_data,
output reg [DATA_WIDTH-1:0] o_data
);
wire [ADDR_WIDTH-1:0] address;
wire [DATA_WIDTH-1:0] data;
wire [DATA_WIDTH-1:0] color;
wire [10:0] ctr_x = 400, ctr_y = 300;
sram #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(DEPTH),
.MEMFILE("")
) vram_read (
.i_addr(address),
.clk(clk),
.i_write(i_write), // we're always reading
.i_data(color),
.o_data(data)
);
assign i_write = (((ctr_x - half_width <= current_x) && (current_x < ctr_x + half_width)) &&
((ctr_y - half_height <= current_y) && (current_y < ctr_y + half_height)));
assign color = i_data;
assign address = (i_write) ? ((current_y - ctr_y) * half_height * 2 + (current_x - ctr_x)) : 0;
always @(posedge clk) o_data <= data;
endmodule
| 7.74358 |
module squarediffmult #(
parameter SIZEIN = 16
) (
input clk,
ce,
rst,
input signed [SIZEIN-1:0] a,
b,
output signed [2*SIZEIN+1:0] square_out
);
// Declare registers for intermediate values
reg signed [SIZEIN-1:0] a_reg, b_reg;
reg signed [SIZEIN:0] diff_reg;
reg signed [2*SIZEIN+1:0] m_reg, p_reg;
always @(posedge clk) begin
if (rst) begin
a_reg <= 0;
b_reg <= 0;
diff_reg <= 0;
m_reg <= 0;
p_reg <= 0;
end else if (ce) begin
a_reg <= a;
b_reg <= b;
diff_reg <= a_reg - b_reg;
m_reg <= diff_reg * diff_reg;
p_reg <= m_reg;
end
end
// Output result
assign square_out = p_reg;
endmodule
| 6.971873 |
module squaregen (
input wire clk,
input wire en,
input wire [22:0] period,
output wire [23:0] tone,
output wire on
);
parameter amplitude = 24'hfffff; // TODO CHANGE?
//parameter freq = 440;
reg [31:0] count = 0;
//logic[31:0] period = (48000000 / freq);
always @(posedge clk)
if (count >= period) count <= 0;
else if (en) count <= count + 1;
assign on = (count > (period >> 1));
assign tone = en ? (count > (period >> 1)) ? amplitude : -amplitude // TODO CHANGE BOUNDS
: 0;
//assign tone = count << 6;
endmodule
| 7.189037 |
module SquareGenTest ();
reg clk;
reg [5:0] note_in;
wire [2:0] offset_multiplier;
wire offset_direction;
reg en;
reg vibra_en;
reg note_clk;
reg [1:0] vibra_speed;
reg [1:0] vibra_depth;
wire [5:0] vibra_out;
wire square_out;
wire freq;
FX_vibrato sq_vibra (
.note_in (note_in), //6 bits
.note_clk (note_clk), //1 bit
.note_out (vibra_out), //6 bits
.speed (vibra_speed), //speed: two bits FXA
.depth (vibra_depth), //depth: two bits FXB
.offset_mul (offset_multiplier), //3 bits
.offset_dir (offset_direction), //1 bit
.en (vibra_en), //1 bit
.clk50mhz (clk) //1 bit
);
base_freq_genx64 freqgen (
.note_in(vibra_out),
.clk50mhz(clk),
.freq_out(freq),
.offset_mult(offset_multiplier),
.offset_dir(offset_direction)
);
/*
module base_freq_genx64(
note_in,
clk50mhz,
freq_out,
offset_mult,
offset_dir
);
*/
square_gen sqgen (
.base_freq (freq),
.square_out (square_out),
.en (en)
);
initial begin
#1 clk = 0;
#1 note_clk = 0;
#1 note_in = 42;
#1 en = 1;
#1 vibra_speed = 0;
#1 vibra_speed = 0;
#100000 vibra_en = 1;
#100000 vibra_speed = 3;
#100000 vibra_depth = 3;
//#100000 offset_direction = 1;
//#1 offset_multiplier = 6;
#200000 note_in = 52;
#50000000 vibra_depth = 1;
//#10000000 note_in = 51;
//#10000000 note_in = 39;
end
always begin
#1 clk = ~clk;
end
always begin
#390625 note_clk = ~note_clk; //this is so that note_clk * 32 = 1/4 second; 390625.
end
endmodule
| 7.628054 |
module SquareLoop (
rst,
clk,
din,
startf,
carrier,
df
);
input rst; //复位信号，高电平有效
input clk; //FPGA系统时钟：16MHz
input signed [7:0] din; //输入数据：16MHz
input signed [31:0] startf; //输入的载波初始频率
output signed [7:0] carrier; //同步后的载波输出信号
output signed [27:0] df; //环路滤波器输出数据
//实例化NCO核所需的接口信号
wire reset_n, out_valid, clken;
wire signed [9:0] sin, cosine;
wire signed [31:0] frequency_df;
wire signed [27:0] Loopout;
assign reset_n = !rst;
assign clken = 1'b1;
//assign startf=32'd872415232;//3.25MHz
assign frequency_df = {{4{Loopout[27]}}, Loopout}; //根据NCO核接口，扩展为32位
//实例化NCO核
//Quartus提供的NCO核输出数据最小位宽为10比特，根据环路设计需求，只取高8比特参与后续运算
nco u0 (
.phi_inc_i(startf),
.clk(clk),
.reset_n(reset_n),
.clken(clken),
.freq_mod_i(frequency_df),
.fsin_o(sin),
.fcos_o(cosine),
.out_valid(out_valid)
);
assign carrier = sin[9:2];
//实例化NCO同相正交支路乘法运算器核
wire signed [15:0] oc_out;
mult8_8 u1 (
.clock (clk),
.dataa (sin[9:2]),
.datab (cosine[9:2]),
.result(oc_out)
);
//实例化鉴相器乘法运算器核
wire signed [15:0] mult_out;
mult8_8 u4 (
.clock (clk),
.dataa (oc_out[14:7]),
.datab (din),
.result(mult_out)
);
//实例化低通滤波器核
wire signed [27:0] pd;
wire ast_sink_valid, ast_source_ready;
wire [1:0] ast_sink_error;
assign ast_sink_valid = 1'b1;
assign ast_source_ready = 1'b1;
assign ast_sink_error = 2'd0;
wire sink_ready, source_valid;
wire [1:0] source_error;
locklpf u3 (
.clk(clk),
.reset_n(reset_n),
.ast_sink_data(mult_out[14:0]),
.ast_sink_valid(ast_sink_valid),
.ast_source_ready(ast_source_ready),
.ast_sink_error(ast_sink_error),
.ast_source_data(pd),
.ast_sink_ready(sink_ready),
.ast_source_valid(source_valid),
.ast_source_error(source_error)
);
//实例化环路滤波器模块
LoopFilter u6 (
.rst(rst),
.clk(clk),
.pd(pd),
.frequency_df(Loopout)
);
//将环路滤波器数据送至输出端口查看
assign df = Loopout;
endmodule
| 7.223118 |
module fa_df (
input a,
b,
cin,
output sum,
cout
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (cin & (a ^ b));
endmodule
| 6.889194 |
module ha_df (
input a,
b,
output sum,
cout
);
assign sum = a ^ b;
assign cout = a & b;
endmodule
| 8.302286 |
module SquareWave (
input wire clk_24M,
input wire btn_a_i, // raise frequency
input wire btn_b_i, // drop frequency
output wire io_b3a
);
// clk_100K
wire clk_100K;
SlowClock #(
.HALFPERIOD(24000000 / 100000)
) clock_100K (
.clk (clk_24M),
.clk_o(clk_100K)
);
// clk_100M
wire clk_100M;
Gowin_rPLL clock_100M (
.clkout(clk_100M), //output clkout
.clkin (clk_24M) //input clkin
);
// button filter
wire btnPress_a;
wire btnPress_b;
ButtonFilter buttonFilter_a (
.clk_100K(clk_100K),
.btn_i(btn_a_i),
.btn_o(),
.btnPress(btnPress_a),
.btnRelease()
);
ButtonFilter buttonFilter_b (
.clk_100K(clk_100K),
.btn_i(btn_b_i),
.btn_o(),
.btnPress(btnPress_b),
.btnRelease()
);
// frequency control with button
localparam COUNTWIDTH = 32;
localparam INITIALDIVIDE = 50000000; // 1Hz from 100MHz
localparam MAXFREQDIVIDE = 5; // 10MHz
localparam MINFREQDIVIDE = 500000000; // 0.1Hz
reg [COUNTWIDTH-1:0] divider = INITIALDIVIDE;
localparam ST_1 = 0;
localparam ST_2 = 1;
localparam ST_5 = 2;
reg [2:0] state = ST_1;
always @(posedge clk_100K) begin
if (btnPress_a && divider > MAXFREQDIVIDE) begin
case (state)
ST_1: begin
state <= ST_2;
divider <= divider / 2;
end
ST_2: begin
state <= ST_5;
divider <= divider * 2 / 5;
end
ST_5: begin
state <= ST_1;
divider <= divider / 2;
end
endcase
end else if (btnPress_b && divider < MINFREQDIVIDE) begin
case (state)
ST_1: begin
state <= ST_5;
divider <= divider * 2;
end
ST_2: begin
state <= ST_1;
divider <= divider * 2;
end
ST_5: begin
state <= ST_2;
divider <= divider / 2 * 5;
end
endcase
end else begin
end
end
reg [COUNTWIDTH-1:0] divider_r;
always @(posedge clk_100K) begin
divider_r <= divider - 1;
end
// square wave generation
reg wave;
reg [COUNTWIDTH-1:0] counter;
always @(posedge clk_100M) begin
if (btnPress_b | btnPress_a) begin
counter <= 0;
end else if (counter > divider_r) begin
counter <= 0;
end else if (counter == divider_r) begin
counter <= 0;
wave <= ~wave;
end else begin
counter <= counter + 1'b1;
end
end
assign io_b3a = wave;
endmodule
| 6.624113 |
module squarewave_disp (
input clk,
rst_n,
input[2:0] key, //key[0] to move cursor to right,key[1] to move cursor down, key[2] to change waveform pattern
output [4:0] vga_out_r,
output [5:0] vga_out_g,
output [4:0] vga_out_b,
output vga_out_vs,
vga_out_hs
);
wire [11:0] pixel_x, pixel_y;
wire video_on;
wire [2:0] rgb;
assign vga_out_r = rgb[2] ? 5'b111_11 : 0;
assign vga_out_g = rgb[1] ? 6'b111_111 : 0;
assign vga_out_b = rgb[0] ? 5'b111_11 : 0;
vga_core m0 (
.clk(clk_out), //clock must be 25MHz for 640x480
.rst_n(rst_n),
.hsync(vga_out_hs),
.vsync(vga_out_vs),
.video_on(video_on),
.pixel_x(pixel_x),
.pixel_y(pixel_y)
);
full_screen_gen m1 //generates square-wave patterns with variable cursor location
(
.clk(clk_out),
.rst_n(rst_n),
.key(key),
.pixel_x(pixel_x),
.pixel_y(pixel_y),
.video_on(video_on),
.rgb(rgb)
);
dcm_25MHz m2 ( // Clock in ports
.clk (clk), // IN
// Clock out ports
.clk_out(clk_out), // OUT
// Status and control signals
.RESET (RESET), // IN
.LOCKED (LOCKED)
);
endmodule
| 7.820059 |
module Square_Adder_Run ();
// Counter for shaping the test vector of the single bit (Full Adder).
reg [2:0] bit_counter; // { c || b || a }
always #1 bit_counter = bit_counter + 1;
// FA outputs
wire nc;
wire c;
wire ns;
// Counters for enumerating Adder input values
reg [21:0] ab_counter; // { b[10:0] || a[10:0] }
always #1 ab_counter = ab_counter + 1;
wire [10:0] Fx; // Input A
wire [10:0] S; // Input B (or vice versa, since group)
wire [10:0] n_sum; // Output A + B (inverse polarity)
wire [10:0] sum; // Just for convenience
wire n_COUT; // Output carry (inverse polarity)
wire COUT; // Just for convenience
assign Fx = ab_counter[10:0]; // low half
assign S = ab_counter[21:11]; // high half
assign sum = ~n_sum;
assign COUT = ~n_COUT;
SQUARE_AdderBit adder_bit (
.F(bit_counter[0]),
.nF(~bit_counter[0]),
.S(bit_counter[1]),
.nS(~bit_counter[1]),
.C(bit_counter[2]),
.nC(~bit_counter[2]),
.n_cout(nc),
.cout(c),
.n_sum(ns)
);
// Using the input carry connection option for Square1 (n_carry=1 aka carry=0)
SQUARE_Adder adder (
.CarryMode(1'b1),
.INC(1'b0),
.nFx(~Fx),
.Fx(Fx),
.S(S),
.n_sum(n_sum),
.n_COUT(n_COUT)
);
initial begin
$dumpfile("square_adder.vcd");
$dumpvars(0, adder_bit);
$dumpvars(1, adder);
$dumpvars(2, sum);
$dumpvars(3, COUT);
bit_counter <= 0;
ab_counter <= 0;
// Run full adder
repeat (8) @(bit_counter);
// Run whole
repeat ((1 << 22) - 7) @(ab_counter);
$finish;
end
endmodule
| 8.030869 |
module Square_Barrel_Run ();
reg [14:0] val; // {BS[11:0] || SR[2:0]}
output [10:0] S;
always #1 val = val + 1;
SQUARE_BarrelShifter bs (
.BS(val[14:3]),
.SR(val[2:0]),
.S (S)
);
initial begin
$dumpfile("square_barrel.vcd");
$dumpvars(0, bs);
val <= 0;
repeat (32769) @(val);
$finish;
end
endmodule
| 7.009872 |
module square_cell #(
parameter WIDTH = 4,
parameter STEP = 0
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input [2 * WIDTH - 1:0] radicand,
input [WIDTH - 1:0] last_dout,
input [2 * WIDTH - 1:0] remainder_din,
output reg [WIDTH - 1:0] this_dout,
output reg [2 * WIDTH - 1:0] remainder_dout
);
wire [2 * WIDTH - 1:0] target_data = {remainder_din[2*WIDTH-3:0], radicand[2*STEP+:2]};
wire [2 * WIDTH - 1:0] try_data = {last_dout, 2'b01};
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
{this_dout, remainder_dout} <= 'b0;
end else begin
if (target_data >= try_data) begin
this_dout <= {last_dout[WIDTH-2:0], 1'b1};
remainder_dout <= target_data - try_data;
end else begin
this_dout <= {last_dout[WIDTH-2:0], 1'b0};
remainder_dout <= target_data;
end
end
end
endmodule
| 6.639212 |
module Square_Controller (
CLK,
SOUND_WAVE,
RESET,
START,
HURT,
RECOVER,
INVINCIBLE,
OVER,
DROP_READY,
SQUARE_START_Y,
SQUARE_SIZE,
SQUARE_COLOR
);
input CLK; //100Hz
input SOUND_WAVE;
input RESET;
input START;
input HURT; //当游戏机会次数-1时，HURT置为1,随后置为0
input RECOVER; //机会次数+1
input INVINCIBLE; //有效时代表方块处于不死状态
input OVER; //游戏结束信号
output DROP_READY;
output [`COORDINATE_LENGTH-1:0] SQUARE_START_Y; //要显示的方块左上角的Y坐标
output [`SQUARE_SIZE_LENGTH-1:0] SQUARE_SIZE; //要显示的方块边长
output [`SQUARE_STATE_ENCODE_LENGTH-1:0] SQUARE_COLOR; //方块的颜色
/*
*该模块负责告知VGA显示模块方块的位置以及颜色
*与外部进行通信，接收启动、重置、停止等指令
*发送DROP_READY信号告知外部方块已就位
*HURT RECOVER INVINCIBLE等信号标志游戏机会的增加与减少等等
*OVER信号有效时，代表游戏结束
*与声音采样编码器进行通信，接收音高等级
*/
/*
向VGA显示模块传递以下数值即可显示
input [9:0]SQUARE_START_Y;//要显示的方块左上角的Y坐标
input [9:0]SQUARE_SIZE;//要显示的方块边长
input [1:0]SQUARE_COLOR;//方块的颜色
*/
assign SQUARE_SIZE = `SQUARE_DEFAULT_SIZE; //'d12;//考虑后期进行调整
wire [`SOUND_LEVEL_ENCODE_LENGTH-1:0] sound_level;
Sound_Encoder get_sound_level (
CLK,
SOUND_WAVE,
sound_level
);
//以下实例化了一个控制方块颜色的电路
reg color_reset = 0; //有效时颜色复位
Square_Color_Controller color_controller (
.CLK(CLK),
.RESET(color_reset),
.HURT(HURT),
.RECOVER(RECOVER),
.INVINCIBLE_ENABLE(INVINCIBLE),
.SQUARE_COLOR(SQUARE_COLOR)
);
reg coordinate_reset = 0;
reg drop_start = 0;
reg free_move_start = 0;
Square_Coordinate_Controller coordinate_controller (
.CLK(CLK),
.RESET(coordinate_reset),
.DROP_START(drop_start),
.FREE_MOVE(free_move_start),
.GAME_OVER(OVER),
.SOUND_LEVEL(sound_level),
.SQUARE_Y_COORDINATE(SQUARE_START_Y),
.DROP_FINISH(DROP_READY)
);
/*
状态机需要控制以下信号
reg color_reset=0;
reg coordinate_reset=0;
reg drop_start=0;
reg free_move_start=0;
*/
//状态机描述
parameter HIDE = 2'b00;
parameter DROP = 2'b01;
parameter FREE_MOVE = 2'b11;
parameter GAME_OVER = 2'b10;
reg [1:0] current_state = HIDE;
reg [1:0] next_state;
always @(posedge CLK) begin
if (RESET) begin
current_state <= HIDE;
end else begin
current_state <= next_state;
end
end
always @(current_state or START or DROP_READY or OVER) begin
case (current_state)
HIDE: begin
if (START) begin
next_state = DROP;
end else begin
next_state = HIDE;
end
end
DROP: begin
if (DROP_READY) begin
next_state = FREE_MOVE;
end else begin
next_state = DROP;
end
end
FREE_MOVE: begin
if (!OVER) begin
next_state = FREE_MOVE;
end else begin
next_state = GAME_OVER;
end
end
GAME_OVER: begin
next_state = GAME_OVER; //这个状态下只有接收到RESET信号才能复位
end
default: begin
next_state = HIDE;
end
endcase
end
always @(posedge CLK) begin
case (next_state)
HIDE: begin
color_reset <= 1;
coordinate_reset <= 1;
end
DROP: begin
color_reset <= 0;
coordinate_reset <= 0;
end
FREE_MOVE: begin
color_reset <= 0;
coordinate_reset <= 0;
end
GAME_OVER: begin
color_reset <= 0;
coordinate_reset <= 0;
end
default: begin
color_reset <= 1;
coordinate_reset <= 1;
end
endcase
end
always @(posedge CLK) begin
case (next_state)
HIDE: begin
drop_start <= 0;
free_move_start <= 0;
end
DROP: begin
drop_start <= 1;
free_move_start <= 0;
end
FREE_MOVE: begin
drop_start <= 0;
free_move_start <= 1;
end
GAME_OVER: begin
drop_start <= 0;
free_move_start <= 0;
end
default: begin
drop_start <= 0;
free_move_start <= 0;
end
endcase
end
endmodule
| 7.106526 |
module Square_Coordinate_Controller (
CLK,
RESET,
DROP_START,
FREE_MOVE,
GAME_OVER,
SOUND_LEVEL,
SQUARE_Y_COORDINATE,
DROP_FINISH
);
input CLK;
input RESET;
input DROP_START;
input FREE_MOVE;
input GAME_OVER;
input [`SOUND_LEVEL_ENCODE_LENGTH-1:0] SOUND_LEVEL;
output reg [`COORDINATE_LENGTH-1:0] SQUARE_Y_COORDINATE;
output reg DROP_FINISH;
parameter IDLE = 3'b000;
parameter DROP = 3'b001;
parameter MOVE_WAIT = 3'b011;
parameter MOVE = 3'b010;
parameter OVER = 3'b110;
reg [2:0] current_state = IDLE;
reg [2:0] next_state;
always @(posedge CLK) begin
if (RESET) begin
current_state <= IDLE;
end else begin
current_state <= next_state;
end
end
wire drop_finish;
assign drop_finish = (SQUARE_Y_COORDINATE >= 'd180);
always @(current_state or DROP_START or drop_finish or FREE_MOVE or GAME_OVER) begin
case (current_state)
IDLE: begin
if (DROP_START) begin
next_state = DROP;
end else begin
next_state = IDLE;
end
end
DROP: begin
if (drop_finish) begin
next_state = MOVE_WAIT;
end else begin
next_state = DROP;
end
end
MOVE_WAIT: begin
if (FREE_MOVE) begin
next_state = MOVE;
end else begin
next_state = MOVE_WAIT;
end
end
MOVE: begin
if (GAME_OVER) begin
next_state = OVER;
end else begin
next_state = MOVE;
end
end
OVER: begin
next_state = OVER;
end
default: begin
next_state = IDLE;
end
endcase
end
always @(posedge CLK) begin
case (next_state)
IDLE: begin
DROP_FINISH <= 0;
end
DROP: begin
DROP_FINISH <= 0;
end
MOVE_WAIT: begin
DROP_FINISH <= 1;
end
MOVE: begin
DROP_FINISH <= 0;
end
OVER: begin
DROP_FINISH <= 0;
end
default: begin
DROP_FINISH <= 0;
end
endcase
end
//以下代码决定方块的y坐标
wire y_up_movable;
wire y_down_movable;
assign y_up_movable = (SQUARE_Y_COORDINATE >= 'd42);
assign y_down_movable = (SQUARE_Y_COORDINATE <= 'd492);
always @(posedge CLK) begin
case (next_state)
IDLE: begin
SQUARE_Y_COORDINATE <= 'd20;
end
DROP: begin
SQUARE_Y_COORDINATE <= SQUARE_Y_COORDINATE + 'd2;
end
MOVE_WAIT: begin
SQUARE_Y_COORDINATE <= SQUARE_Y_COORDINATE;
end
MOVE: begin
case (SOUND_LEVEL)
`NO_SOUND: begin
if (y_down_movable) begin
SQUARE_Y_COORDINATE <= SQUARE_Y_COORDINATE + 'd4;
end else begin
SQUARE_Y_COORDINATE <= SQUARE_Y_COORDINATE;
end
end
`LEVEL_1: begin
if (y_up_movable) begin
SQUARE_Y_COORDINATE <= SQUARE_Y_COORDINATE - 'd1;
end else begin
SQUARE_Y_COORDINATE <= SQUARE_Y_COORDINATE;
end
end
`LEVEL_2: begin
if (y_up_movable) begin
SQUARE_Y_COORDINATE <= SQUARE_Y_COORDINATE - 'd3;
end else begin
SQUARE_Y_COORDINATE <= SQUARE_Y_COORDINATE;
end
end
`LEVEL_3: begin
if (y_up_movable) begin
SQUARE_Y_COORDINATE <= SQUARE_Y_COORDINATE - 'd5;
end else begin
SQUARE_Y_COORDINATE <= SQUARE_Y_COORDINATE;
end
end
`LEVEL_4: begin
if (y_up_movable) begin
SQUARE_Y_COORDINATE <= SQUARE_Y_COORDINATE - 'd7;
end else begin
SQUARE_Y_COORDINATE <= SQUARE_Y_COORDINATE;
end
end
`LEVEL_5: begin
if (y_up_movable) begin
SQUARE_Y_COORDINATE <= SQUARE_Y_COORDINATE - 'd10;
end else begin
SQUARE_Y_COORDINATE <= SQUARE_Y_COORDINATE;
end
end
default: begin
if (y_down_movable) begin
SQUARE_Y_COORDINATE <= SQUARE_Y_COORDINATE + 'd4;
end else begin
SQUARE_Y_COORDINATE <= SQUARE_Y_COORDINATE;
end
end
endcase
end
OVER: begin
SQUARE_Y_COORDINATE <= SQUARE_Y_COORDINATE;
end
default: begin
SQUARE_Y_COORDINATE <= SQUARE_Y_COORDINATE;
end
endcase
end
endmodule
| 8.567771 |
module Square_Duty_Run ();
reg CLK;
reg RES;
wire PHI1;
wire ACLK1;
wire nACLK2;
// Tune CLK/ACLK timing according to 2A03
always #23.28 CLK = ~CLK;
reg WR0; // Used to load the Duty setting into the appropriate register
wire [7:0] DataBus;
reg [1:0] duty_mode;
wire DUTY; // The signal for which the test is performed
AclkGenStandalone aclk (
.CLK(CLK),
.RES(RES),
.PHI1(PHI1),
.nACLK2(nACLK2),
.ACLK1(ACLK1)
);
RegDriver reg_driver (
.PHI1(PHI1),
.WR0(WR0),
.duty_mode(duty_mode),
.DataBus(DataBus)
);
SQUARE_Duty duty_unit (
.ACLK1(ACLK1),
.RES(RES),
.FLOAD(~ACLK1 & ~WR0), // Make the counter always step complementary to the Keep state (ACLK1)
.FCO(1'b1), // Make the input carry always active for continuous counting. In reality the carry is activated only when the frequency counter counts are completed.
.WR0(WR0),
.WR3(1'b0), // This test does not check the clearing of the Duty counter when writing to the length counter
.DB(DataBus),
.DUTY(DUTY)
);
initial begin
$dumpfile("square_duty.vcd");
$dumpvars(0, aclk);
$dumpvars(1, duty_unit);
$dumpvars(2, DUTY);
$dumpvars(3, duty_mode);
CLK <= 1'b0;
RES <= 1'b0;
WR0 <= 1'b0;
// Check Duty = 2
duty_mode <= 2'b10;
WR0 <= 1'b1;
repeat (`CoreCyclesPerCLK) @(posedge CLK);
repeat (`CoreCyclesPerCLK) @(posedge CLK);
WR0 <= 1'b0;
repeat (192) @(posedge CLK);
$finish;
end
endmodule
| 6.902841 |
module executes a "program" sequence of writes to the Duty register
module RegDriver (PHI1, WR0, duty_mode, DataBus);
input PHI1;
input WR0;
input [1:0] duty_mode;
inout [7:0] DataBus;
assign DataBus = ~PHI1 ? (WR0 ? {duty_mode[1:0],6'b000000} : 8'hzz) : 8'hzz;
endmodule
| 7.110462 |
module square_extractor #(
parameter WIDTH = 4
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input [2 * WIDTH - 1:0] radicand,
output [WIDTH - 1:0] dout,
output [2 * WIDTH - 1:0] remainder
);
genvar i;
generate
for (i = WIDTH - 1; i >= 0; i = i - 1) begin : square
wire [2 * WIDTH - 1:0] remainder_dout, remainder_din;
wire [WIDTH - 1:0] this_dout, last_dout;
if (i == WIDTH - 1) begin
assign remainder_din = 'b0;
assign last_dout = 'b0;
end else begin
assign remainder_din = square[i+1].remainder_dout;
assign last_dout = square[i+1].this_dout;
end
square_cell #(
.WIDTH(WIDTH),
.STEP (i)
) u_square_cell (
.clk (clk), // Clock
.rst_n(rst_n), // Asynchronous reset active low
.radicand(radicand),
.last_dout(last_dout),
.remainder_din(remainder_din),
.this_dout(this_dout),
.remainder_dout(remainder_dout)
);
end
endgenerate
assign dout = square[0].this_dout;
assign remainder = square[0].remainder_dout;
endmodule
| 7.454079 |
module square_handler (
clk_1Hz,
up,
down,
left,
right,
hcnt,
vcnt,
hcnt_out,
vcnt_out
);
input clk_1Hz, up, down, left, right, hcnt, vcnt;
output hcnt_out, vcnt_out;
wire clk_1Hz;
wire up, down, left, right;
wire [9:0] hcnt, vcnt;
reg [9:0] hcnt_out, vcnt_out;
reg [9:0] up_count;
reg [9:0] down_count;
reg [9:0] left_count;
reg [9:0] right_count;
initial begin
up_count <= 0;
down_count <= 0;
left_count <= 0;
right_count <= 0;
end
always @(*) begin
hcnt_out <= hcnt + right_count - left_count;
vcnt_out <= vcnt + down_count - up_count;
end
always @(posedge (clk_1Hz)) begin
if (up) begin
up_count <= up_count + 1;
end else if (down) begin
down_count <= down_count + 1;
end else if (right) begin
right_count <= right_count + 1;
end else if (left) begin
left_count <= left_count + 1;
end else begin
up_count <= up_count;
down_count <= down_count;
left_count <= left_count;
right_count <= right_count;
end
end
endmodule
| 6.985921 |
module square_logic (
input clk,
input rst_n,
input [9:0] x,
input [9:0] x2,
output reg [9:0] vga_x,
output reg [9:0] vga_y,
output reg [9:0] vga_x2,
output reg [9:0] vga_y2
);
reg [31:0] cnt;
reg x_direct;
reg y_direct;
wire move_en;
parameter T_10ms = 500_000;
parameter side = 40;
parameter block = 40;
parameter stick = 75;
parameter vga_xdis = 800;
parameter vga_ydis = 600;
parameter y = 462;
parameter y2 = 136;
always @(posedge clk, negedge rst_n) begin
if (rst_n == 1'b0) cnt <= 32'd0;
else if (cnt < T_10ms - 1) cnt <= cnt + 32'd1;
else cnt <= 32'd0;
end
assign move_en = (cnt == T_10ms - 1) ? 1'b1 : 1'b0;
always @(posedge clk, negedge rst_n) begin
if (rst_n == 1'b0) begin
vga_x <= 10'd379;
vga_y <= 10'd420;
end else if (move_en == 1'b1) begin
if ((vga_x >= x2 - 10'd40 && vga_x < (x2 + 10'd115) && vga_y == y2) || vga_y == 1'b0) begin
vga_x <= x + 17;
vga_y <= 10'd420;
end else vga_y <= vga_y - 10'd1;
end
end
always @(posedge clk, negedge rst_n) begin
if (rst_n == 1'b0) begin
vga_x2 <= 10'd379;
vga_y2 <= 10'd140;
end else if (move_en == 1'b1) begin
if((vga_x2>=x-10'd40 && vga_x2<(x+10'd115) && vga_y2 == y-side) || vga_y2 == vga_ydis-side) begin
vga_x2 <= x2 + 17;
vga_y2 <= 10'd140;
end else vga_y2 <= vga_y2 + 10'd1;
end
end
endmodule
| 6.885059 |
module square_mag (
input clock,
input reset,
input dv_fft,
input [15:0] xk_re,
input [15:0] xk_im,
output dv_sq_m,
output [31:0] xk_sq_m
);
wire [31:0] xk_re_sq;
wire [31:0] xk_im_sq;
wire dv_fft_d1, dv_fft_d2, dv_fft_d3;
wire dv_sq, dv_sq_d1, dv_sq_d2, dv_sq_d3;
dsp48_mul mul_xk_re (
.clk(clock),
.sclr(reset),
.a(xk_re), // Bus [15 : 0]
.b(xk_re), // Bus [15 : 0]
.p(xk_re_sq)
); // Bus [31 : 0]
dsp48_mul mul_xk_im (
.clk(clock),
.sclr(reset),
.a(xk_im), // Bus [15 : 0]
.b(xk_im), // Bus [15 : 0]
.p(xk_im_sq)
); // Bus [31 : 0]
FFD ffd_fft_d1 (
.q (dv_fft_d1),
.clk(clock),
.rst(reset),
.d (dv_fft)
);
FFD ffd_fft_d2 (
.q (dv_fft_d2),
.clk(clock),
.rst(reset),
.d (dv_fft_d1)
);
FFD ffd_fft_d3 (
.q (dv_fft_d3),
.clk(clock),
.rst(reset),
.d (dv_fft_d2)
);
FFD ffd_fft_d4 (
.q (dv_sq),
.clk(clock),
.rst(reset),
.d (dv_fft_d3)
);
FFD ffd_sq_d1 (
.q (dv_sq_d1),
.clk(clock),
.rst(reset),
.d (dv_sq)
);
FFD ffd_sq_d2 (
.q (dv_sq_m),
.clk(clock),
.rst(reset),
.d (dv_sq_d1)
);
/*FFD ffd_sq_d3(
.q(dv_sq_d3),
.clk(clock),
.rst(reset),
.d(dv_sq_d2)
);
FFD ffd_sq_d4(
.q(dv_sq_m),
.clk(clock),
.rst(reset),
.d(dv_sq_d3)
);*/
add adder_sq_m (
.a(xk_re_sq), // Bus [31 : 0]
.b(xk_im_sq), // Bus [31 : 0]
.clk(clock),
.sclr(reset),
.s(xk_sq_m)
); // Bus [31 : 0]
endmodule
| 6.557962 |
module square_op (
input Ai,
input Bi,
output Pi,
output Gi,
output Hi
);
always @(*) begin
Pi = Ai ^ Bi;
Gi = Ai & Bi;
Hi = Ai ^ Bi;
end
endmodule
| 7.015104 |
module BogusCPU (
PHI0,
PHI1,
PHI2
);
input PHI0;
output PHI1;
output PHI2;
assign PHI1 = ~PHI0;
assign PHI2 = PHI0;
endmodule
| 7.703679 |
module executes a "program" sequence of writes to various registers
module RegDriver (PHI1, W4000, W4001, W4002, W4003, W4015, DataBus);
input PHI1;
input W4000;
input W4001;
input W4002;
input W4003;
input W4015;
inout [7:0] DataBus;
// W4015 <= 0000000 1 (SQA Length counter enable: 1)
// W4000 <= 10 0 0 0110 (D=2, Length Counter #carry in=0, ConstVol=0, Vol=6)
// W4001 <= 1 001 0 010 (Sweep=1, Period=1, Negative=0, Magnitude=2^2)
// W4002 <= 0110 1001 (Freq Lo=0x69)
// W4003 <= 11111 010 (Length=11111, Freq Hi=2)
assign DataBus = ~PHI1 ? (W4000 ? 8'b10000110 : (W4001 ? 8'b10010010 : (W4002 ? 8'b01101001 : (W4003 ? 8'b11111010 : (W4015 ? 8'b00000001 : 8'hzz))))) : 8'hzz;
endmodule
| 7.110462 |
module square_read_create (
input CLK,
input RST,
output [11:0] square
);
//Load other module(s)
//Definition for Variables in the module
reg [11:0] value[63:0];
//Buffer to sroe
reg [5:0] counter;
//Counter for the value circle
//Logical
assign square = value[counter];
initial begin
$readmemh("square_table.txt", value);
//Get the square values
end
always @(posedge CLK or negedge RST) begin
if (!RST) begin
counter <= 6'h00;
//Reset
end else begin
counter <= counter + 6'h01;
//Increase
end
end
endmodule
| 7.554065 |
module that sqaures 4 bit input 'n'.
module square_ROM(n, sign, square);
input [3:0] n; //number.
input sign; //signed number if 1, unsigned if 0.
output reg [7:0] square;
always @ (n or sign) begin
if(sign==0) begin //if unsigned (0-15)
case(n)
0: square <= 0;
1: square <= 1;
2: square <= 4;
3: square <= 9;
4: square <= 16;
5: square <= 25;
6: square <= 36;
7: square <= 49;
8: square <= 64;
9: square <= 81;
10: square <= 100;
11: square <= 121;
12: square <= 144;
13: square <= 169;
14: square <= 196;
15: square <= 255;
default: square <= 0;
endcase
end
else begin //if signed (-8-+7)
case(n)
0: square <= 0;
1: square <= 1;
2: square <= 4;
3: square <= 9;
4: square <= 16;
5: square <= 25;
6: square <= 36;
7: square <= 49;
8: square <= 64; //-8
9: square <= 1; //-1
10: square <= 4; //-2
11: square <= 9; //-3
12: square <= 16; //-4
13: square <= 25; //-5
14: square <= 36; //-6
15: square <= 49; //-7
endcase
end
end
endmodule
| 6.758992 |
module square_ROMTB ();
reg [3:0] n;
reg sign;
wire [7:0] square;
square_ROM(
.n(n), .sign(sign), .square(square)
);
initial begin
$monitor("n = %b = %d, sign = %b, square = %d", n, n, sign, square);
end
initial begin : apply_stimulus
reg [4:0] i;
n = 0;
sign = 0; //positive only (0-15)
for (i = 0; i <= 15; i = i + 1) begin
#1 n = i;
end
#1 n = 0;
sign = 1; //(-8-+7) n=9 square is 1 since 9 is 1001 = -1 if msb is sign bit.
for (i = 0; i <= 15; i = i + 1) begin
#1 n = i;
end
end
endmodule
| 7.221158 |
module square_root_comb #(
parameter N = 8,
M = N / 2
) (
input [ N-1:0] A,
output [N/2-1:0] O
);
wire [N/2:0] Y[0:M];
assign O = Y[M][N/2-1:0];
genvar gv;
generate
for (gv = 0; gv < M; gv = gv + 1) begin : sqr_rt
squar_root_comb_unit #(
.N(N),
.K(gv)
) squar_root_comb_unit (
.x(A),
.y_in(Y[gv][N/2:N/2-gv]),
.y_out(Y[gv+1][N/2:N/2-gv-1])
);
end
endgenerate
endmodule
| 6.679579 |
module squar_root_comb_unit #(
parameter N = 8,
K = 0
) (
input [N-1:0] x,
input [ K:0] y_in,
output [K+1:0] y_out
);
wire t, b;
wire [2*K+1:0] y_sqr;
wire [ K+1:0] y;
assign y = {y_in, 1'b1};
MULT #(
.N(K + 1),
.M(K + 1)
) MULT1 (
.A(y[K:0]),
.B(y[K:0]),
.O(y_sqr)
);
COMP #(
.N(2 * K + 2)
) COMP1 (
.A(x[N-1:N-2*K-2]),
.B(y_sqr),
.O(t)
);
MUX #(
.N(1)
) MUX1 (
.A(1'b0),
.B(1'b1),
.S(t),
.O(b)
);
assign y_out = {y_in, b};
endmodule
| 6.602703 |
module squar_root_seq_unit #(
parameter N = 8
) (
input [ N-1:0] x,
input [N/2-1:0] y_in,
y0_in,
output [N/2-1:0] y_out,
y0_out
);
wire t, b;
wire [N/2-1:0] y;
wire [ N-1:0] y_sqr;
assign y = y_in | y0_in;
MULT #(
.N(N / 2),
.M(N / 2)
) MULT1 (
.A(y),
.B(y),
.O(y_sqr)
);
COMP #(
.N(N)
) COMP1 (
.A(x),
.B(y_sqr),
.O(t)
);
MUX #(
.N(1)
) MUX1 (
.A(1'b0),
.B(1'b1),
.S(t),
.O(b)
);
assign y_out = y_in | (y0_in & {(N / 2) {b}});
assign y0_out = y0_in >> 1;
endmodule
| 6.556534 |
module square_root32_element #(
parameter P_IN_N = 4,
parameter P_DFF = 1
) (
input wire iCLOCK,
input wire inRESET,
//Input
input wire iDATA_REQ,
output wire oDATA_BUSY,
input wire [P_IN_N/2-1:0] iDATA_P,
input wire [31:0] iDATA_I,
//Output
output wire oDATA_VALID,
input wire iDATA_BUSY,
output wire [P_IN_N/2-1:0] oDATA_P,
output wire [31:0] oDATA_I
);
function [P_IN_N/2-1:0] func_cell_gen;
input [P_IN_N/2-1:0] func_data_p;
input [31:0] func_data_i;
reg [P_IN_N-1:0] func_pri_data;
begin
func_pri_data = func_data_p * func_data_p;
if (func_data_i[31:32-P_IN_N] >= func_pri_data) begin
func_cell_gen = func_data_p;
end else begin
func_cell_gen = {func_data_p[P_IN_N/2-1:1], 1'b0};
end
end
endfunction
generate
if (P_DFF) begin
//D-FF Delay
reg b_buffer_req;
reg [P_IN_N/2-1:0] b_buffer_p;
reg [31:0] b_buffer_i;
always @(posedge iCLOCK or negedge inRESET) begin
if (!inRESET) begin
b_buffer_req <= 1'b0;
end else if (iDATA_BUSY) begin
b_buffer_req <= b_buffer_req;
end else begin
b_buffer_req <= iDATA_REQ;
end
end
always @(posedge iCLOCK or negedge inRESET) begin
if (!inRESET) begin
b_buffer_p <= {P_IN_N / 2{1'b0}};
end else if (iDATA_BUSY) begin
b_buffer_p <= b_buffer_p;
end else begin
b_buffer_p <= func_cell_gen(iDATA_P, iDATA_I);
end
end
always @(posedge iCLOCK or negedge inRESET) begin
if (!inRESET) begin
b_buffer_i <= 32'h0;
end else if (iDATA_BUSY) begin
b_buffer_i <= b_buffer_i;
end else begin
b_buffer_i <= iDATA_I;
end
end
assign oDATA_VALID = b_buffer_req;
assign oDATA_P = b_buffer_p;
assign oDATA_I = b_buffer_i;
end else begin
//Combination
assign oDATA_VALID = iDATA_REQ;
assign oDATA_P = func_cell_gen(iDATA_P, iDATA_I);
assign oDATA_I = iDATA_I;
end
endgenerate
assign oDATA_BUSY = iDATA_BUSY;
endmodule
| 6.737667 |
module calculates the square root value of the provided inputData value. This
is achieved through the usage of the Non-Restoring Square Root algorithm. The data
width of the output must be exactly half the input bit width. Input bit width must
be equal to an even number.
To fully understand how the Non-Restoring Square Root method works pleas read
the following:
- http://www.ijcte.org/papers/281-G850.pdf
- https://digitalsystemdesign.in/non-restoring-algorithm-for-square-root/
- http://www.ijceronline.com/papers/(NCASSGC)/W107-116.pdf
*/
module square_root_cal #(
parameter INPUT_DATA_WIDTH = 84,
parameter OUTPUT_DATA_WIDTH = 42
)(
input clock,
input enable,
input [INPUT_DATA_WIDTH - 1:0] inputData,
output reg [OUTPUT_DATA_WIDTH - 1:0] outputData
);
// Creating the local parameters.
reg [INPUT_DATA_WIDTH - 1:0] currentBits;
reg [INPUT_DATA_WIDTH - 1:0] subtractBits;
reg [INPUT_DATA_WIDTH - 1:0] remainderBits;
reg [INPUT_DATA_WIDTH - 1:0] dataIn;
reg [OUTPUT_DATA_WIDTH - 1:0] tempOut;
// Setting the localparam
initial begin
currentBits <= {(INPUT_DATA_WIDTH){1'd0}};
subtractBits <= {(INPUT_DATA_WIDTH){1'd0}};
remainderBits <= {(INPUT_DATA_WIDTH){1'd0}};
dataIn <= {(INPUT_DATA_WIDTH){1'd0}};
tempOut <= {(OUTPUT_DATA_WIDTH){1'd0}};
outputData <= {(OUTPUT_DATA_WIDTH){1'd0}};
end
// Creating the integers which are used for the for loops in the always block.
integer i;
integer n;
always @ (posedge clock) begin
// If enable do the square root operation.
if(enable) begin
// With each new enable/value, reset the main parameters
dataIn = inputData;
currentBits = {(INPUT_DATA_WIDTH){1'd0}};
subtractBits = {(INPUT_DATA_WIDTH){1'd0}};
remainderBits = {(INPUT_DATA_WIDTH){1'd0}};
tempOut = {(OUTPUT_DATA_WIDTH){1'd0}};
// A for loop which goes through all the values in. The for loop iterations
// must equal half of inputData bit width.
for(i = OUTPUT_DATA_WIDTH - 1; i >= -0; i = i - 1) begin
// Adding the MSB 2 bits of dataIn to the start of currentBits. Hence shift
// currentBits to the left by 2 positions and setting bits 0 and 1 to the 2
// MSB's of dataIn.
currentBits = {currentBits[INPUT_DATA_WIDTH - 3:0], dataIn[INPUT_DATA_WIDTH - 1:INPUT_DATA_WIDTH - 2]};
// Shifting dataIn two positions so that in the next for loop iteration, the
// corresponding 2 bits of dataIn are processed.
dataIn = dataIn << 2;
// Setting subtractBits to remainderBits bit shifted by 2 values, with bits
// 1 and 0 being set to 2'b01.
subtractBits = {remainderBits[INPUT_DATA_WIDTH - 3:0], 2'd1};
// Check if the remainder of currentBits - subtractBits is negative. If
// subtractBits is larger than currentBits, then the remainder would be
// negative, else it would be posative (0 is considered posative).
if(subtractBits > currentBits) begin
// If subtractBits > currentBits, set the current tempOut bit to 0.
tempOut[i] = 1'd0;
end
else begin
// If currentBits > subtractBits (remainder is posative), set the
// current tempOut bit to 1. Then recalculate currentBits. This is equal
// to the remainder value of currentBits - subtractBits.
tempOut[i] = 1'd1;
currentBits = currentBits - subtractBits;
end
// Reset remainderBits, then set its value to the shifted value of
// tempOut.
remainderBits = {(INPUT_DATA_WIDTH){1'd0}};
remainderBits = remainderBits + (tempOut >> (i));
end
// Set the final value of tempOut to outputData.
outputData = tempOut;
end
// If enable is low, set outputData to 0.
else begin
outputData = {(OUTPUT_DATA_WIDTH){1'd0}};
end
end
endmodule
| 7.448165 |
module Square_Sweep_Run ();
reg CLK;
reg RES;
wire PHI1;
wire ACLK1;
wire nACLK2;
// Tune CLK/ACLK timing according to 2A03
always #23.28 CLK = ~CLK;
reg WR_Reg1; // Used to simulate writing to the Sweep registers by the "processor" (RegDriver)
wire [7:0] DataBus;
wire n_LFO2;
wire DO_SWEEP; // The signal for which it is all about
AclkGenStandalone aclk (
.CLK(CLK),
.RES(RES),
.PHI1(PHI1),
.nACLK2(nACLK2),
.ACLK1(ACLK1)
);
BogusLFO lfo (
.CLK(CLK),
.RES(RES),
.nACLK2(nACLK2),
.LFO(n_LFO2)
);
RegDriver reg_driver (
.PHI1(PHI1),
.WR_Reg1(WR_Reg1),
.DataBus(DataBus)
);
SQUARE_Sweep sweep_unit (
.ACLK1(ACLK1),
.RES(RES),
.WR1(WR_Reg1),
.SR(3'b111), // Make a convenient value of the frequency shift magnitude so that the SRZ signal does not occur
.DEC(1'b1), // Make decrement mode to ignore overflow
.n_COUT(1'b1), // Set the Adder output carry to a convenient value
.SW_UVF(1'b0), // Pretend that the frequency is greater than the minimum value (>= 4)
.NOSQ(1'b0), // Pretend that the length counter is not stopped
.n_LFO2(n_LFO2), // Dummy accelerated LFO signal
.DB(DataBus),
.DO_SWEEP(DO_SWEEP)
);
initial begin
$dumpfile("square_sweep.vcd");
$dumpvars(0, aclk);
$dumpvars(1, sweep_unit);
$dumpvars(2, DO_SWEEP);
CLK <= 1'b0;
RES <= 1'b0;
WR_Reg1 <= 1'b0;
// Perform a reset to reset the counter to zero
RES <= 1'b1;
repeat (`CoreCyclesPerCLK) @(posedge CLK);
RES <= 1'b0;
// Set the initial values of the Sweep registers
WR_Reg1 <= 1'b1;
repeat (`CoreCyclesPerCLK) @(posedge CLK);
WR_Reg1 <= 1'b0;
repeat (`CoreCyclesPerCLK) @(posedge CLK);
// Continue the Sweep Unit and see in the .vcd what you get
repeat (2048) @(posedge CLK);
$finish;
end
endmodule
| 6.596546 |
module executes a "program" sequence of writes to the SweepUnit registers
module RegDriver (PHI1, WR_Reg1, DataBus);
input PHI1;
input WR_Reg1;
inout [7:0] DataBus;
assign DataBus = ~PHI1 ? (WR_Reg1 ? 8'b11110001 : 8'hzz) : 8'hzz; // Enable=1; Period=7; Negative=0; Shift=1
endmodule
| 7.110462 |
module
`timescale 1ns / 1ps
`define VALUE_WIDTH 12
`define VALUE_MAX 1500
module square_test;
// Inputs
reg signed [`VALUE_WIDTH-1:0] value;
reg clk;
reg reset;
reg data_valid;
// Outputs
wire [(`VALUE_WIDTH-1) * 2 - 1:0] square;
wire new_result;
// Internal variables
reg [(`VALUE_WIDTH-1) * 2 - 1:0] expected_square;
reg [(`VALUE_WIDTH-1) * 2 - 1:0] expected_square1;
reg [(`VALUE_WIDTH-1) * 2 - 1:0] expected_square2;
wire error;
// Instantiate the Unit Under Test (UUT)
square #(
.VALUE_WIDTH(`VALUE_WIDTH),
.VALUE_MAX(`VALUE_MAX)
) uut (
.value(value),
.square(square),
.new_result(new_result),
.clk(clk),
.reset(reset),
.data_valid(data_valid)
);
// Initialize Inputs
initial begin
value = -`VALUE_MAX;
clk = 1;
reset = 1;
data_valid = 1;
expected_square = 0;
expected_square1 = 0;
expected_square2 = 0;
#20
reset = 0;
end
// Clock
always begin
#5 clk = ~clk;
end
// Counter
always @(posedge clk) begin
if (~reset) begin
if (value + 9 <= `VALUE_MAX)
value <= value + 9;
else
value <= -`VALUE_MAX;
expected_square2 <= value * value;
expected_square1 <= expected_square2;
expected_square <= expected_square1;
end
end
// Error checking
assign error = square != expected_square;
endmodule
| 6.608387 |
module square_wave_gen (
input wire clk,
reset,
input wire [3:0] on_period,
off_period,
output wire signal
);
// signal declaration
localparam BASE_CYCLES = 10;
reg signal_reg, signal_next;
reg [3:0] on_period_reg, off_period_reg;
wire [3:0] on_period_next, off_period_next;
reg [3:0] period_counter_reg, period_counter_next;
reg [4:0] base_counter_reg;
wire [4:0] base_counter_next;
wire base_tick;
// body
// register
always @(posedge clk, posedge reset) begin
if (reset) begin
signal_reg <= 1'b0;
base_counter_reg <= 0;
period_counter_reg <= 0;
on_period_reg <= 0;
off_period_reg <= 0;
end else begin
signal_reg <= signal_next;
on_period_reg <= on_period_next;
off_period_reg <= off_period_next;
base_counter_reg <= base_counter_next;
period_counter_reg <= period_counter_next;
end
end
// next-state logic
// read input
assign on_period_next = on_period;
assign off_period_next = off_period;
assign base_counter_next = (base_counter_reg == BASE_CYCLES - 1) ? 0 : base_counter_reg + 1;
assign base_tick = (base_counter_reg == BASE_CYCLES - 1) ? 1'b1 : 1'b0;
// detect when to go high or low
always @* begin
// default: keep old value
signal_next = signal_reg;
period_counter_next = period_counter_reg;
// every 100ns
if (base_tick) begin
period_counter_next = period_counter_reg + 1;
// if high
if (signal_reg) begin
// check if configured period already passed
// inequality, so if the user changes to a smaller period, the signal
// will be changed on next clk
// if on or off period are zero, then they will switch by the smallest period (100ns)
if (period_counter_reg >= on_period_reg - 1 || on_period_reg == 0) begin
signal_next = 1'b0; // go to low
period_counter_next = 0;
end
end // if low
else begin
// check if configured period already passed
if (period_counter_reg >= off_period_reg - 1 || off_period_reg == 0) begin
signal_next = 1'b1; // go to high
period_counter_next = 0;
end
end
end
end
// output
assign signal = signal_reg;
endmodule
| 6.641963 |
module square_wave_generator (
clk,
enable,
divider,
out
);
input clk;
input enable;
input [18:0] divider;
reg [18:0] counter;
reg polarity;
output reg signed [31:0] out;
always @(posedge clk) begin
if (!enable) begin
counter <= 19'b0;
out <= 32'b0;
polarity <= 1'b0;
end else begin
counter <= counter + 1;
if (counter == divider) begin
counter <= 32'b0;
polarity <= !polarity;
end
out <= polarity ? 32'd65534 : -32'd65534;
end
end
endmodule
| 6.641963 |
module square_wave_gen_tb;
localparam T = 10; // clk period
reg clk, reset;
reg [3:0] on_period, off_period;
wire signal;
// instance of uut
square_wave_gen uut (
.clk(clk),
.reset(reset),
.on_period(on_period),
.off_period(off_period),
.signal(signal)
);
// clock
always begin
clk = 1'b0;
#(T / 2);
clk = 1'b1;
#(T / 2);
end
initial begin
reset = 1'b1;
#(T / 2);
reset = 1'b0;
end
initial begin
on_period = 4'b0011;
off_period = 4'b0001;
repeat (100) @(negedge clk);
on_period = 4'b0000;
off_period = 4'b0010;
repeat (100) @(negedge clk);
$stop;
end
endmodule
| 6.641963 |
module square_wave_gen(
input clk,
input rst_n,
output sq_wave
);
// Input clock is 100MHz
localparam CLOCK_FREQUENCY = 100000000;
// Counter for toggling of clock
integer counter = 0;
reg sq_wave_reg = 0;
assign sq_wave = sq_wave_reg;
always @(posedge clk) begin
if (!rst_n) begin
counter <= 8'h00;
sq_wave_reg <= 1'b0;
end
else begin
// If counter is zero, toggle sq_wave_reg
if (counter == 8'h00) begin
sq_wave_reg <= ~sq_wave_reg;
// Generate 1Hz Frequency
counter <= CLOCK_FREQUENCY/2 - 1;
end
// Else count down
else
counter <= counter - 1;
end
end
endmodule
| 6.641963 |
module sqwaveGen (
clk,
reset,
rise,
fall,
clk_out
);
input wire clk;
input wire reset;
output wire clk_out;
input wire [15:0] rise;
input wire [9:0] fall;
reg [15:0] count, count_on, count_off;
reg pos_or_neg;
always @(posedge reset) begin
pos_or_neg <= 0;
end
always @(posedge clk, negedge reset) begin
if (~reset) begin
count <= 0;
//count <= 0;
pos_or_neg <= 1;
end else if ((pos_or_neg == 1)) begin
if ((count == count_on - 1)) begin
count <= 0;
pos_or_neg <= 0;
end else count <= count + 1;
end else if ((pos_or_neg == 0)) begin
if ((count == count_off - 1)) begin
count <= 0;
pos_or_neg <= 1;
end else count <= count + 1;
end
end
always @(posedge reset) begin
pos_or_neg <= 0;
end
always @(rise, fall) begin
count_on <= rise;
count_off <= fall;
end
assign clk_out = pos_or_neg;
endmodule
| 6.757862 |
module sqwave_gen (
input clk,
rst_n,
input [3:0] m,
n,
output out
);
reg [6:0] m_reg = 0, n_reg = 0; //counter for ON period of m*(100ns) and OFF period of n*(100ns)
reg sq_reg = 0; //square wave output
reg [6:0] m_nxt = 0, n_nxt = 0;
reg sq_nxt = 0;
reg m_max = 0, n_max = 0;
//registers
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
m_reg <= 0;
n_reg <= 0;
sq_reg <= 0;
end else begin
m_reg <= m_nxt;
n_reg <= n_nxt;
sq_reg <= sq_nxt;
end
end
//next-state logic
always @* begin
m_nxt = m_reg;
n_nxt = n_reg;
m_max = 0;
n_max = 0;
sq_nxt = 0;
if (m == 4'd0 || n == 4'd0) begin //if m or n is zero then out must remain in one position
m_nxt = 0;
n_nxt = 0;
casez ({
|m, |n
}) //reduction operator
2'b00: sq_nxt = 0;
2'b01: sq_nxt = 0;
2'b10: sq_nxt = 1;
default: sq_nxt = 0;
endcase
end //OFF logic with duration of n*100ns
else if (sq_reg == 0) begin
m_nxt = 0;
n_nxt = (n_reg == 5 * n - 1) ? 0 : n_reg + 1; //50MHz*100ns*n=5*n
n_max = (n_reg == 5 * n - 1) ? 1 : 0; //50MHz*100ns*n=5*n
sq_nxt = n_max ? 1 : 0;
end //ON logic with duration of m*100ns
else if (sq_reg == 1) begin
n_nxt = 0;
m_nxt = (m_reg == 5 * m - 1) ? 0 : m_reg + 1;
m_max = (m_reg == 5 * m - 1) ? 1 : 0;
sq_nxt = m_max ? 0 : 1;
end
end
assign out = sq_reg;
endmodule
| 6.58832 |
module sq_mult #(parameter R=14)
(
input clk,rst,
input ref,
input signed [ R-1:0] in,
output signed [ R-1:0] out
);
wire signed [R-1:0] plus_in, minus_in ;
assign plus_in = in ;
assign minus_in = {R{1'b0}}-$signed(in) ;
assign out = ref ? plus_in : minus_in ;
endmodule
| 6.829989 |
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