code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module srlatch (
q,
q_not,
en,
s,
r
);
output q, q_not;
input en, s, r;
wire w1, w2;
nand (w1, en, s);
nand (w2, en, r);
nand (q, w1, q_not);
nand (q_not, w2, q);
endmodule
| 7.226086 |
module sr04 (
input clk,
input rst,
input echo,
output reg trig,
output [12:0] dis
);
parameter TRIG_US = 10; //trig signal holds 10us
parameter TRIG_CNT_MAX = 1_000_000; //1MHz, send trig every secend
reg [19:0] trig_cnt;
reg [15:0] echo_cnt;
reg [15:0] echo_cnt_reg;
always @(posedge clk_div or posedge rst) begin
if (rst == 1'b1) begin
trig <= 1'b0;
trig_cnt <= 20'd0;
end else if (trig_cnt == TRIG_US - 1) begin
trig <= 1'b0;
trig_cnt <= trig_cnt + 1;
end else if (trig_cnt == TRIG_CNT_MAX - 1) begin
trig <= 1'b1;
trig_cnt <= 20'd0;
end else begin
trig <= trig;
trig_cnt <= trig_cnt + 1;
end
end
always @(posedge clk_div or posedge rst) begin
if (rst == 1'b1) begin
echo_cnt <= 16'd0;
echo_cnt_reg <= 16'd0;
end else if (echo == 1'b1) begin
echo_cnt <= echo_cnt + 1;
echo_cnt_reg <= echo_cnt + 1;
end else begin
echo_cnt <= 16'd0;
echo_cnt_reg <= echo_cnt_reg;
end
end
assign dis = echo_cnt_reg[15:3]; //dis = echo_cnt / 8 , which is 0.0013864m by scale
clk_div clk_div_m0 (
.clk_50M(clk),
.rst (rst),
.clk_div(clk_div)
);
endmodule
| 7.291364 |
module sr04_control #(
parameter DELAY_TRIGGER = 10,
DELAY_ECHO = 25000,
DELAY_POSTFIX = 500000,
DELAY_WIDTH = $clog2(DELAY_POSTFIX)
) (
input clk,
input rst_n,
input strobe_us,
input strobe_cm,
input echo,
output reg trigger,
output reg measure_cm,
output reg measure_end
);
localparam S_TRIGGER = 0, // trigger input to module
S_ECHO = 1, // wait for echo signal
S_SAVE = 2, // save the result
S_POSTFIX = 3; // measurement cycle final delay,
// S_SAVE ---.
// |
// state : <- S_TRIGGER -><- S_ECHO ->X<- S_POSTFIX ->
// trigger : .../`````````````\__________________________________...
// echo : ...___________________/```````````\_________________...
// State variables
wire [1:0] state;
reg [1:0] state_nx;
prm_register #(2) state_r (
clk,
rst_n,
state_nx,
state
);
wire [DELAY_WIDTH-1:0] delay;
wire [DELAY_WIDTH-1:0] delay_nx = (state_nx != state) ? 0 : delay + 1;
wire delay_we = strobe_us;
prm_register_we #(DELAY_WIDTH) delay_r (
clk,
rst_n,
delay_we,
delay_nx,
delay
);
// next state variables value
always @(*) begin
state_nx = state;
case (state)
S_TRIGGER: if (delay == DELAY_TRIGGER) state_nx = S_ECHO;
S_ECHO: if (delay == DELAY_ECHO) state_nx = S_SAVE;
S_SAVE: state_nx = S_POSTFIX;
S_POSTFIX: if (delay == DELAY_POSTFIX) state_nx = S_TRIGGER;
endcase
end
// fsm output
always @(*) begin
trigger = 1'b0;
measure_cm = 1'b0;
measure_end = 1'b0;
case (state)
S_TRIGGER: trigger = 1'b1;
S_ECHO: measure_cm = strobe_cm & echo;
S_SAVE: measure_end = 1'b1;
endcase
end
endmodule
| 6.755506 |
module sr04_receiver #(
parameter RANGE_WIDTH = 16,
DELAY_CLK_1US = 50,
DELAY_1US_1SM = 58,
DELAY_TRIGGER_US = 10,
DELAY_ECHO_US = 400 * DELAY_1US_1SM, //max measured distance is 400 cm
DELAY_POSTFIX_US = 500000
) (
input clk,
input rst_n,
input echo,
output trigger,
output [RANGE_WIDTH-1:0] range
);
// +---------------+ +---------------+
// | strobe_gen_cm | | strobe_gen_us |
// +-------+-------+ +--------+------+
// | |
// +-------v--------------------v------+
// echo +-----> sr04_control +----> trigger
// +-------+-------------------+-------+
// | |
// +-------v-------+ +-------v-------+
// | counter +---> output buffer +----> range
// +---------------+ +---------------+
wire strobe_us; // micro second strobe
wire strobe_cm; // centimetre strobe
wire measure_cm; // centimetre was measured
wire measure_end; // measurement end
strobe_gen #(
.DELAY(DELAY_CLK_1US)
) strobe_gen_us (
.clk (clk),
.rst_n (rst_n),
.en (1'b1),
.strobe(strobe_us)
);
strobe_gen #(
.DELAY(DELAY_1US_1SM)
) strobe_gen_cm (
.clk (clk),
.rst_n (rst_n),
.en (strobe_us),
.strobe(strobe_cm)
);
sr04_control #(
.DELAY_TRIGGER(DELAY_TRIGGER_US),
.DELAY_ECHO (DELAY_ECHO_US),
.DELAY_POSTFIX(DELAY_POSTFIX_US)
) control (
.clk (clk),
.rst_n (rst_n),
.strobe_us (strobe_us),
.strobe_cm (strobe_cm),
.echo (echo),
.trigger (trigger),
.measure_cm (measure_cm),
.measure_end(measure_end)
);
// range counter
wire [RANGE_WIDTH-1:0] rcntr;
wire [RANGE_WIDTH-1:0] rcntr_nx = measure_end ? 0 : rcntr + 1;
wire rcntr_we = measure_end | measure_cm;
prm_register_we #(RANGE_WIDTH) rcntr_r (
clk,
rst_n,
rcntr_we,
rcntr_nx,
rcntr
);
// output buffer
prm_register_we #(RANGE_WIDTH) obuff_r (
clk,
rst_n,
measure_end,
rcntr,
range
);
endmodule
| 7.334079 |
module SR16 (
input clk,
input rst_n,
input [11:0] in_r, //(6,6)
input [11:0] in_i, //(6,6)
output [11:0] out_r, //(6,6)
output [11:0] out_i //(6,6)
);
// change LENGTH here to set up the length of this shift register
//=================================================
parameter LENGTH = 16;
//=================================================
integer i;
reg [11:0] r_bus[LENGTH-1:0];
reg [11:0] i_bus[LENGTH-1:0];
assign out_r = r_bus[0];
assign out_i = i_bus[0];
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
for (i = 0; i < LENGTH; i = i + 1) begin
r_bus[i] <= 0;
i_bus[i] <= 0;
end
end else begin
r_bus[LENGTH-1] <= in_r;
i_bus[LENGTH-1] <= in_i;
for (i = 0; i < (LENGTH - 1); i = i + 1) begin
r_bus[i] <= r_bus[i+1];
i_bus[i] <= i_bus[i+1];
end
end
end
endmodule
| 7.140839 |
module SR1MUX (
input [2:0] IR11to9,
input [2:0] IR8to6,
input SR1MUX,
output reg [2:0] SR1
);
initial SR1 = 0;
always @(*) begin
case (SR1MUX)
2'b00: SR1 = IR11to9;
2'b01: SR1 = IR8to6;
2'b10: SR1 = 3'b110;
default: SR1 = 0;
endcase
end
endmodule
| 6.813198 |
module sr2mux (
imm,
sreg,
sel,
out
);
input wire [15:0] imm; // immediate value
input wire [15:0] sreg; // source register
input wire sel; // select
output wire [15:0] out; // output
// TODO: `define the values of select
assign out = sel ? imm : sreg;
endmodule
| 9.861934 |
module SR4 (
input clk,
input rst_n,
input [15:0] in_r,
input [15:0] in_i,
output [15:0] out_r,
output [15:0] out_i
);
// change LENGTH here to set up the length of this shift register
//=================================================
parameter LENGTH = 4;
//=================================================
integer i;
reg [15:0] r_bus[LENGTH-1:0];
reg [15:0] i_bus[LENGTH-1:0];
assign out_r = r_bus[0];
assign out_i = i_bus[0];
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
for (i = 0; i < LENGTH; i = i + 1) begin
r_bus[i] <= 0;
i_bus[i] <= 0;
end
end else begin
r_bus[LENGTH-1] <= in_r;
i_bus[LENGTH-1] <= in_i;
for (i = 0; i < (LENGTH - 1); i = i + 1) begin
r_bus[i] <= r_bus[i+1];
i_bus[i] <= i_bus[i+1];
end
end
end
endmodule
| 6.653427 |
module SR8 (
input clk,
input rst_n,
input [14:0] in_r,
input [14:0] in_i,
output [14:0] out_r,
output [14:0] out_i
);
// change LENGTH here to set up the length of this shift register
//=================================================
parameter LENGTH = 8;
//=================================================
integer i;
reg [14:0] r_bus[LENGTH-1:0];
reg [14:0] i_bus[LENGTH-1:0];
assign out_r = r_bus[0];
assign out_i = i_bus[0];
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
for (i = 0; i < LENGTH; i = i + 1) begin
r_bus[i] <= 0;
i_bus[i] <= 0;
end
end else begin
r_bus[LENGTH-1] <= in_r;
i_bus[LENGTH-1] <= in_i;
for (i = 0; i < (LENGTH - 1); i = i + 1) begin
r_bus[i] <= r_bus[i+1];
i_bus[i] <= i_bus[i+1];
end
end
end
endmodule
| 7.181758 |
module sra (
result,
data_operand,
shamt
);
input [31:0] data_operand;
input [4:0] shamt;
output [31:0] result;
wire [31:0] sixteen, eight, four, two, one, mux1, mux2, mux3, mux4;
shiftright_sixteen rightsixteen (
sixteen,
data_operand
);
mux_2 sixteenmux (
mux1,
shamt[4],
data_operand,
sixteen
);
shiftright_eight righteight (
eight,
mux1
);
mux_2 eightmux (
mux2,
shamt[3],
mux1,
eight
);
shiftright_four rightfour (
four,
mux2
);
mux_2 fourmux (
mux3,
shamt[2],
mux2,
four
);
shiftright_two righttwo (
two,
mux3
);
mux_2 twomux (
mux4,
shamt[1],
mux3,
two
);
shiftright_one rightone (
one,
mux4
);
mux_2 onemux (
result,
shamt[0],
mux4,
one
);
endmodule
| 7.159712 |
module sra1 (
out,
in
);
input [31:0] in;
output [31:0] out;
assign out[31] = in[31];
assign out[30:0] = in[31:1];
endmodule
| 6.724727 |
module sra2 (
out,
in
);
input [31:0] in;
output [31:0] out;
assign out[31] = in[31];
assign out[30] = in[31];
assign out[29:0] = in[31:2];
endmodule
| 6.902233 |
module sra4 (
out,
in
);
input [31:0] in;
output [31:0] out;
assign out[31] = in[31];
assign out[30] = in[31];
assign out[29] = in[31];
assign out[28] = in[31];
assign out[27:0] = in[31:4];
endmodule
| 6.570184 |
module sradd (
input wire [31:0] a,
input wire [31:0] b,
output wire [31:0] z
);
// Assume (should assert) that sign[a] = sign[b]
// SP floating point fields
`define sign 31
`define exponent 30:23
`define mantissa 22:0
// various other constants
`define zero 32'b0
`define NaN 32'hFFFFFFFF
// Extract sign, exponent, mantissa
wire as = a[`sign];
// Extract sign, exponent, mantissa
wire [7:0] ae;
assign ae = a[`exponent];
wire [7:0] be;
assign be = b[`exponent];
// Restore hidden one's, use 48-bit precision
wire [47:0] am;
assign am = {24'b0, 1'b1, a[`mantissa]};
wire [47:0] bm;
assign bm = {24'b0, 1'b1, b[`mantissa]};
// NORMALIZE
// Shift the smaller operand left ediff bits, and reduce exp accordingly
// Can left-shift smaller mantissa as much as 22 bits and still get valid result maybe
wire [7:0] ediff;
assign ediff = (ae >= be) ? (ae - be) : (be - ae);
// Ummmmmm...if ediff too great, then somebody is essentially zero...
wire ignore_a;
assign ignore_a = (a == 32'b0) || ((ediff > 8'd22) && (be > ae));
wire ignore_b;
assign ignore_b = (b == 32'b0) || ((ediff > 8'd22) && (ae > be));
wire [47:0] am_adj;
assign am_adj = (ae > be) ? (am << ediff) : am;
wire [47:0] bm_adj;
assign bm_adj = (be > ae) ? (bm << ediff) : bm;
// smaller operand shifts up and back, so end up with larger exponent right?
wire [7:0] ze;
assign ze = (ae > be) ? ae : be;
// FIXME check to see if exp will go l.t. zero
// FIXME not sure what that means exc. need extensive testing!
// am range 0000_0080_0000 to 7FFF_8000_0000
// bm range 0000_0080_0000 to 7FFF_8000_0000
// am+bm range 0000_0100_0000 to FFFF_FFFF_FFFF
//
// ...riiight? And then when you shift it back down again:
//
// zm range 0000_0080_0000 to 0000_01FF_FFFF maybe?
wire [47:0] am_plus_bm;
assign am_plus_bm = am_adj + bm_adj;
// wire [24:0] zm; assign zm = am_plus_bm >> ediff;
wire [47:0] zm48;
assign zm48 = am_plus_bm >> ediff;
wire [24:0] zm;
assign zm = zm48[24:0];
// 'magic name "unused" (-unused-regexp) is recognized by Verilator and suppresses warnings' //
wire _unused_ok_zm = &{1'b0, zm48[47:23]};
// The 'one' bit will *always* be at position 23 or 24, RIGHT??
// So adjust exp, mantissa accordingly.
// Hidden one happens at the end...RIGHT???
wire [22:0] zm_final;
assign zm_final = zm[24] == 1'b1 ? zm[23:1] : zm[22:0];
// FIXME can ze overflow??
wire [7:0] ze_final;
assign ze_final = zm[24] == 1'b1 ? ze + 1 : ze;
////////////////////////////////////////////////////////////////
assign z = ignore_a ? b : ignore_b ? a : {as, ze_final, zm_final};
// FIXME not supposed to use adder if signs not equal!
// FIXME need some kind of ASSERT a[`sign] == b[`sign]
// DEBUGGING
// FIXME Technically I think these are supposed to be OUTSIDE the module def
//`define DBG1
//`define DBG9
`ifdef DBG1
// DEBUGGING
always @(*) begin
if (a == a) begin
//if (a == 32'h3f800000) begin
//if ((a != 0) && (b != 0)) begin
//if ((a != 0) && (b == 32'h40000000)) begin
$display("%m");
$display("%m a=bsr'%08X (%08X) b=bsr'%08X (%08X) z=bsr'%08X (%08X)", a, a, b, b, z, z);
`ifdef DBG9
$display("%m ae=%02x be=%02x", ae, be);
$display("%m ae+bias=%1d be+bias=%1d", ae - 8'd127, be - 8'd127);
$display("%m ediff=%2d", ediff);
$display("%m am=%06X bm=%06X", am, bm);
$display("%m am_adj=%012X", am_adj);
$display("%m bm_adj=%012X", bm_adj);
$display("%m am+bm =%012X", am_plus_bm);
$display("%m ze =%02X", ze);
$display("%m ze_final=%02X", ze_final);
$display("%m zm =%06X", zm);
$display("%m zm_final=%06X", zm_final);
$display("%m ");
`endif // DBG9
end // if ((a != 0) && (b != 0))
end // always @ (*)
`endif // DBG1
endmodule
| 8.298691 |
module SRAM_8bit (
input sys_CLK, // clock
input [ 1:0] sys_CMD, // 00=nop, 01=write 256 bytes, 11=read 256 bytes
input [18:0] sys_ADDR, // word address, multiple of 2 words (4 bytes)
input [15:0] sys_DIN, // data input
output reg [15:0] sys_DOUT,
output reg sys_rd_data_valid = 0, // data valid out
output reg sys_wr_data_valid = 0, // data valid in
input sram_clk,
output sram_n_WE, // SRAM #WE
output reg [20:0] sram_ADDR, // SRAM address
inout [ 7:0] sram_DATA // SRAM data
);
reg [ 2:0] STATE = 0;
reg [ 2:0] RET; // return state
reg [ 6:0] DLY; // delay
reg [ 1:0] sys_cmd_ack = 0; // command acknowledged
reg [15:0] reg_din;
reg [ 5:0] out_data_valid = 0;
assign sram_DATA = out_data_valid[2] ? sram_ADDR[0] ? reg_din[15:8] : reg_din[7:0] : 8'hzz;
assign sram_n_WE = out_data_valid[2] ? 0 : 1;
reg [7:0] sram_data2;
always @(posedge sram_clk) begin
sram_data2 <= sram_DATA;
case (STATE)
0: begin
if (|sys_CMD) begin
sram_ADDR <= {sys_ADDR[18:0], 2'b00};
end
end
1: begin
if ((sys_rd_data_valid == 1'b1) || (out_data_valid[2] == 1'b1)) begin
sram_ADDR <= sram_ADDR + 1'b1;
end
end
7: begin
if (sys_cmd_ack[1]) begin
sram_ADDR <= sram_ADDR + 1;
end
end
endcase
end
always @(posedge sys_CLK) begin
STATE <= 1;
reg_din <= sys_DIN;
out_data_valid <= {out_data_valid[1:0], sys_wr_data_valid};
DLY <= DLY - 1;
sys_DOUT <= {sram_DATA, sram_data2};
case (STATE)
0: begin
sys_rd_data_valid <= 1'b0;
if (|sys_CMD) begin
sys_cmd_ack <= sys_CMD;
STATE <= 5;
end else begin
sys_cmd_ack <= 2'b00;
STATE <= 0;
end
end
1: begin
if (DLY == 3) sys_wr_data_valid <= 1'b0;
if (DLY == 0) STATE <= RET; // NOP for DLY clocks, return to RET state
end
5: begin // read/write
RET <= 7;
if (sys_cmd_ack[1]) begin // read
STATE <= 7;
end else begin // write
DLY <= 1;
sys_wr_data_valid <= 1'b1;
end
end
7: begin // init read/write phase
if (sys_cmd_ack[1]) begin
sys_rd_data_valid <= 1'b1;
end
RET <= 0;
DLY <= sys_cmd_ack[1] ? 128 - 2 : 128 - 1;
end
endcase
end
endmodule
| 7.508107 |
module sram0 #(
parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 5
) (
input clk,
input en_n,
input wren_n,
input [ADDR_WIDTH-1:0] addr,
input [DATA_WIDTH-1:0] data_i,
output reg [DATA_WIDTH-1:0] data_o
);
reg [DATA_WIDTH-1:0] register[2**ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (!wren_n && !en_n) register[addr] <= data_i;
end
always @(posedge clk) begin
if (wren_n && !en_n) data_o <= register[addr];
end
endmodule
| 8.93449 |
module sram146880x6 (
CLK,
A,
CEN,
WEN,
D,
Q
);
parameter A_WID = 18, D_WID = 6;
input CLK;
input [A_WID-1:0] A;
input [D_WID-1:0] D;
input CEN;
input WEN;
output [D_WID-1:0] Q;
reg [D_WID-1:0] Q;
/*********************************************/
/* this part should be replaced by ASIC sram */
reg [D_WID-1:0] mem[0:146879];
always @(posedge CLK) if (~CEN && ~WEN) mem[A] <= #1 D;
always @(posedge CLK) if (~CEN && WEN) Q <= #1 mem[A];
/*********************************************/
endmodule
| 6.71811 |
module sram16 #(
parameter adr_width = 18
) (
input [adr_width-1:0] adr,
inout [ 15:0] dat,
input ub_n,
input lb_n,
input cs_n,
input we_n,
input oe_n
);
parameter dat_width = 16;
//---------------------------------------------------------------------------
// Actual RAM cells
//---------------------------------------------------------------------------
reg [7:0] mem_ub[0:1<<adr_width];
reg [7:0] mem_lb[0:1<<adr_width];
//---------------------------------------------------------------------------
//
//---------------------------------------------------------------------------
wire [15:0] mem = {mem_ub[adr], mem_lb[adr]};
wire [15:0] zzz = 16'bz;
// Drive output
assign dat = (!cs_n && !oe_n) ? mem : zzz;
// Write to UB
always @(*) if (!cs_n && !we_n && !ub_n) mem_ub[adr] = dat[15:8];
// Write to LB
always @(*) if (!cs_n && !we_n && !lb_n) mem_lb[adr] = dat[7:0];
always @(*) if (!we_n && !oe_n) $display("Operational error in RamChip: OE and WE both active");
endmodule
| 8.616669 |
module sram256x32_1p (
A,
DIN,
WE,
CS,
CLK,
DOUT
);
input [7:0] A;
input [31:0] DIN;
input WE, CS, CLK;
output [31:0] DOUT;
//
reg [31:0] Mem [0:255];
//
reg [ 7:0] A_i;
always @(posedge CLK) begin
if (CS) A_i <= A;
end
always @(posedge CLK) begin
if (CS & WE) Mem[A] <= DIN;
end
//
assign #3 DOUT = Mem[A_i];
endmodule
| 7.243826 |
module SRAM2RW32x32_1bit (
CE1_i,
CE2_i,
WEB1_i,
WEB2_i,
A1_i,
A2_i,
OEB1_i,
OEB2_i,
CSB1_i,
CSB2_i,
I1_i,
I2_i,
O1_i,
O2_i
);
input CSB1_i, CSB2_i;
input OEB1_i, OEB2_i;
input CE1_i, CE2_i;
input WEB1_i, WEB2_i;
input [`numAddr-1:0] A1_i, A2_i;
input [0:0] I1_i, I2_i;
output [0:0] O1_i, O2_i;
reg [0:0] O1_i, O2_i;
reg [0:0] memory[`numWords-1:0];
reg [0:0] data_out1, data_out2;
wire RE1;
wire WE1;
wire RE2;
wire WE2;
and u1 (RE1, ~CSB1_i, WEB1_i);
and u2 (WE1, ~CSB1_i, ~WEB1_i);
and u3 (RE2, ~CSB2_i, WEB2_i);
and u4 (WE2, ~CSB2_i, ~WEB2_i);
// Initialization for simulation
integer i;
initial begin
O1_i = $urandom_range(1);
O2_i = $urandom_range(1);
for (i = 0; i < `numWords; i = i + 1) begin
memory[i] = $urandom_range(1);
end
data_out1 = $urandom_range(1);
data_out2 = $urandom_range(1);
end
//Primary ports
always @(posedge CE1_i) if (RE1) data_out1 = memory[A1_i];
always @(posedge CE1_i) if (WE1) memory[A1_i] = I1_i;
always @(data_out1 or OEB1_i)
if (!OEB1_i) O1_i = data_out1;
else O1_i = 1'bz;
//Dual ports
always @(posedge CE2_i) if (RE2) data_out2 = memory[A2_i];
always @(posedge CE2_i) if (WE2) memory[A2_i] = I2_i;
always @(data_out2 or OEB2_i)
if (!OEB2_i) O2_i = data_out2;
else O2_i = 1'bz;
endmodule
| 6.791928 |
module SRAM2_Interface (
input iCLK,
input iCLKMem, // usar pelo menos 4xiCLK
inout [31:0] SRAM_DQ, // SRAM Data Bus 32 Bits
output [18:0] oSRAM_A, // SRAM Address bus 21 Bits
output oSRAM_ADSC_N, // SRAM Controller Address Status
output oSRAM_ADSP_N, // SRAM Processor Address Status
output oSRAM_ADV_N, // SRAM Burst Address Advance
output [3:0] oSRAM_BE_N, // SRAM Byte Write Enable
output oSRAM_CE1_N, // SRAM Chip Enable
output oSRAM_CE2, // SRAM Chip Enable
output oSRAM_CE3_N, // SRAM Chip Enable
output oSRAM_CLK, // SRAM Clock
output oSRAM_GW_N, // SRAM Global Write Enable
output oSRAM_OE_N, // SRAM Output Enable
output oSRAM_WE_N, // SRAM Write Enable
// Barramento de IO
input wReadEnable,
wWriteEnable,
input [3:0] wByteEnable,
input [31:0] wAddress,
wWriteData,
output [31:0] wReadData,
// Barramento de DMA para o Sintetizador, read only
input wReadEnableS,
input [31:0] wAddressS,
output [31:0] wReadDataS
);
initial begin
clkP <= 0;
clkS <= 0;
end
reg clkP, clkS;
always @(posedge iCLKMem) clkP = ~clkP; //iCLKmem/2
always @(posedge clkP) clkS = ~clkS; //iCLKmem/4
// reg MemWritten;
// initial MemWritten <= 1'b0;
// always @(iCLKMem) MemWritten <= iCLKMem;
wire [31:0] wSRAMReadData;
wire wSRAMWrite = clkS && (wAddress >= BEGINNING_SRAM) && (wAddress <= END_SRAM && wWriteEnable);// && ~MemWritten);
assign oSRAM_A = (clkS ? wAddress[20:2] : wAddressS[20:2]);
assign oSRAM_BE_N = ~wByteEnable; //byteena=1111->oSRAM_BE_N=0000
assign oSRAM_CE1_N = 1'b0;
assign oSRAM_CE2 = 1'b1;
assign oSRAM_CE3_N = 1'b0;
assign oSRAM_ADV_N = 1'b1;
assign oSRAM_ADSC_N = 1'b1;
assign oSRAM_ADSP_N = wSRAMWrite;
assign oSRAM_WE_N = (~wSRAMWrite);
assign oSRAM_GW_N = 1'b1;
assign oSRAM_OE_N = 1'b0;
assign oSRAM_CLK = iCLKMem;
// If write is disabled, then float bus, so that SRAM can drive it (READ)
// If write is enables, drive it with data from input to be stored in SRAM (WRITE)
assign SRAM_DQ = (wSRAMWrite ? wWriteData : 32'hzzzzzzzz);
assign wSRAMReadData = SRAM_DQ;
reg [31:0] BwReadData, BwReadDataS; // buffers de saida da memoria
initial begin
BwReadData = 32'b0;
BwReadDataS = 32'b0;
end
always @(negedge clkS) BwReadData <= wSRAMReadData;
always @(posedge clkS) BwReadDataS <= wSRAMReadData;
always @(*) begin
if (wReadEnable) //Leitura
if (wAddress >= BEGINNING_SRAM && wAddress <= END_SRAM) wReadData <= BwReadData;
else wReadData <= 32'hzzzzzzzz;
else wReadData <= 32'hzzzzzzzz;
if (wReadEnableS) //Leitura para o Sintetizador
if (wAddressS >= BEGINNING_SRAM && wAddressS <= END_SRAM) wReadDataS <= BwReadDataS;
else wReadDataS <= 32'hzzzzzzzz;
else wReadDataS <= 32'hzzzzzzzz;
end
endmodule
| 7.64085 |
module sram2_pack #(
parameter BASE_ADDR = 8'h00
) (
input clk,
// SRAM hardware interface
inout [ 7:0] ram_data_z,
(* IOB = "TRUE" *) output reg [23:0] ram_address,
(* IOB = "TRUE" *) output reg ram_nwe,
output ram_nce,
output ram_noe,
// PicoRV32 look-ahead mem interface
input mem_la_read,
input mem_la_write,
input [31:0] mem_la_addr,
input [31:0] mem_la_wdata,
input [ 3:0] mem_la_wstrb,
// PicoRV32 packed MEM Bus interface
output [32:0] mem_packed_ret
);
assign ram_nce = 0;
assign ram_noe = 0;
initial ram_nwe = 1'b1;
(* IOB = "TRUE" *)reg [7:0] w_reg = 8'h0;
(* IOB = "TRUE" *)reg [7:0] r_reg = 8'h0;
assign ram_data_z = ram_nwe ? 8'hzz : w_reg;
// --------------------------------------------------------------
// Unpack the MEM bus
// --------------------------------------------------------------
// What comes out of unpack
reg [23:0] mem_rdata;
reg mem_ready;
munpack mu (
.clk (clk),
.mem_packed_fwd(69'h0),
.mem_packed_ret(mem_packed_ret),
.mem_wdata(),
.mem_wstrb(),
.mem_valid(),
.mem_addr (),
.mem_ready(mem_ready),
// Hack to safe a cycle while keeping r_reg in IOB
.mem_rdata({(mem_ready ? r_reg : 8'h0), mem_rdata})
);
reg [2:0] cycle = 3'h0;
// isSelected is high during the entire access cycle (4 or 5 clocks)
wire isSelected = (mem_la_addr[31:24] == BASE_ADDR) &&
(mem_la_read | mem_la_write | cycle > 0) &&
!mem_ready;
// mem_la_write is a pulse,
// isWrite is valid as long as isSelected is high
reg mem_la_write_ = 1'b0;
wire isWrite = mem_la_write_ | mem_la_write;
always @(posedge clk) begin
mem_ready <= 1'b0;
ram_nwe <= 1'b1;
if (isSelected) begin
// write enable line for this byte
if (isWrite && mem_la_wstrb[cycle]) ram_nwe <= 1'b0;
// always read when selected, picorv ignores it if it's writing
r_reg <= ram_data_z;
mem_rdata[8*(cycle-2)+:8] <= r_reg;
// latch mem_la_write
if (mem_la_write) mem_la_write_ <= 1'b1;
// signal end of access cycle
// read is one clock longer than write. There must be a better way!
if (cycle >= (isWrite ? 3'h3 : 3'h4)) mem_ready <= 1'b1;
cycle <= cycle + 1;
end else begin
mem_rdata <= 24'h0;
cycle <= 3'h0;
mem_la_write_ <= 1'b0;
end
w_reg <= mem_la_wdata[8*cycle+:8];
ram_address <= mem_la_addr[23:0] + cycle;
end
endmodule
| 7.970763 |
module SRAM3 (
input clk,
input [10:0] addr,
input [10:0] addr_r,
output [9:0] data_out,
input [9:0] data_in,
input we,
output reg carry
);
reg [9:0] mem[0:2047];
always @(posedge clk) begin
if (we) mem[addr] <= data_in;
if (addr == 11'b11111111111) carry <= 1'b1;
else carry <= 1'b0;
end
assign data_out = mem[addr_r];
endmodule
| 6.714029 |
module sram32 #(
parameter AW = 10,
VERBOSE = 1
) (
input wire clk,
input wire cs,
input wire [ 3:0] we,
input wire [AW-1:0] A,
input wire [ 31:0] Di,
output reg [ 31:0] Do
);
reg [31:0] ram[(2**AW)-1:0];
always @(posedge clk)
if (cs) begin
Do <= ram[A];
if (we[0]) ram[A][7:0] <= Di[7:0];
if (we[1]) ram[A][15:8] <= Di[15:8];
if (we[2]) ram[A][23:16] <= Di[23:16];
if (we[3]) ram[A][31:24] <= Di[31:24];
if (VERBOSE == 1) begin
if (we == 0) $display("SRAM READ from %0h data %0h", A, Do);
else $display("SRAM Write (%0h): %0h to %0h", we, Di, A);
end
end
endmodule
| 7.281926 |
module sram4 (
clk_i,
address_i,
data_i,
data_o,
wr_i
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter [31:0] SRAM_ADDR_WIDTH = 14;
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input clk_i /*verilator public*/;
input [31:0] address_i /*verilator public*/;
input [31:0] data_i /*verilator public*/;
output [31:0] data_o /*verilator public*/;
input [3:0] wr_i /*verilator public*/;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
wire [31:0] address;
wire [31:0] data_o;
//-----------------------------------------------------------------
// Implementation
//-----------------------------------------------------------------
assign address = {2'b00, address_i[31:2]};
generate
begin : sram_gen
genvar i;
for (i = 0; i < 4; i = i + 1) begin : sram_loop
sram #(
.WIDTH(8),
.SIZE (SRAM_ADDR_WIDTH)
) u1_bram (
.clk_i(clk_i),
.dat_o(data_o[(((i+1)*8)-1):(i*8)]),
.dat_i(data_i[(((i+1)*8)-1):(i*8)]),
.adr_i(address[(SRAM_ADDR_WIDTH-1):0]),
.wr_i (wr_i[i])
);
end
end
endgenerate
endmodule
| 7.435184 |
module SRAM4x16 (
input clk,
rst,
wr,
input [3:0] data,
addr,
output reg [3:0] out
);
reg [3:0] mem[15:0];
always @(posedge clk) begin
if (rst) out <= 0;
else begin
if (wr) //wr is for write
mem[addr] <= data;
else out <= mem[addr];
end
end
endmodule
| 7.842857 |
module tb_golden_SRAM ();
reg clk, rst, wr;
reg [3:0] data, addr;
wire [3:0] out;
integer i, j = 4'd15;
integer k = 4'd15;
SRAM4x16 DUT (
clk,
rst,
wr,
data,
addr,
out
);
/////////////// Parameters for Timing ///////
parameter SETUP_TIME = 1;
parameter HOLD_TIME = 1;
parameter TIME_PERIOD = 10;
initial begin
clk = 0;
forever #5 clk = ~clk;
end
// Calling the write task
initial begin
SRAM_write(1, 1, 1111, 0110);
for (i = 0; i < 16; i = i + 1) begin
#1 SRAM_write(0, 1, i, j); // j is the data, i is the address
j = j - 1;
end
// Calling the read task
for (i = 0; i < 16; i = i + 1) begin
SRAM_read(0, 0, i, k); //k is the exp_out, i is the address
k = k - 1;
end
end
////////// Task for write function //////////
task SRAM_write;
input rst_t;
input wr_t;
input [3:0] addr_t;
input [3:0] data_t;
begin
#(TIME_PERIOD / 2 - SETUP_TIME);
rst = rst_t;
wr = wr_t;
addr = addr_t;
data = data_t;
@(posedge clk);
#(HOLD_TIME);
rst = 1'b0;
wr = ~wr;
addr = 4'bx;
data = 4'bx;
#(TIME_PERIOD / 2 - SETUP_TIME);
if (wr_t) $display("Data entered at %0t :: address = %b, data = %b", $time, addr_t, data_t);
else $display("Some error occured at %0t :: address = %b, data = %b", $time, addr_t, data_t);
end
endtask
//////////// Task for read function ///////
task SRAM_read;
input rst_t;
input wr_t;
input [3:0] addr_t;
input [3:0] exp_out;
begin
#(TIME_PERIOD / 2 - SETUP_TIME);
rst = rst_t;
wr = wr_t;
addr = addr_t;
@(posedge clk);
#(HOLD_TIME);
rst = 1'b0;
wr = ~wr;
addr = 4'bx;
#(TIME_PERIOD / 2 - SETUP_TIME);
if (out == exp_out)
$display("Correct Data read at %0t :: address = %b, output = %b", $time, addr_t, out);
else
$display(
"Wrong data read at %0t :: address = %b, output = %b, exp_out = %b",
$time,
addr_t,
out,
exp_out
);
end
endtask
endmodule
| 6.961187 |
module for read operation//////
module SRAM_ref(input clk, rst, wr, [3:0] data, addr, output [3:0] out_exp);
SRAM4x16 REF_inst(clk, rst, wr, data, addr, out_exp);
endmodule
| 7.77664 |
module SRAM4x16_tb ();
reg clk, rst_tb, wr;
reg [3:0] data, addr;
wire [3:0] out, out_exp;
SRAM4x16 DUT (
clk,
rst_tb,
wr,
data,
addr,
out
);
SRAM_ref REF (
clk,
rst_tb,
wr,
data,
addr,
out_exp
);
parameter SETUP_TIME = 1;
parameter HOLD_TIME = 1;
parameter TIME_PERIOD = 10;
initial begin
clk = 0;
forever #5 clk = ~clk;
end
// Calling the write tasks
initial begin
ram_write_chk(1, 1, $random, $random);
repeat (10) begin
ram_write_chk(0, 1, $random, $random);
end
//Calling read task
repeat (10) begin
ram_read_chk(0, 0, $random);
end
end
task ram_write_chk;
input rst_t;
input wr_t;
input [3:0] data_t;
input [3:0] addr_t;
begin
#(TIME_PERIOD / 2 - SETUP_TIME);
rst_tb = rst_t;
wr = wr_t;
data = data_t;
addr = addr_t;
@(posedge clk);
#(HOLD_TIME);
rst_tb = 1'b0;
wr = ~wr;
#(TIME_PERIOD / 2 - SETUP_TIME);
if (wr_t == 1'b1)
$display("Data written at %0t :: address = %b, data = %b", $time, addr_t, data_t);
else $display("Error occured at %0t", $time);
end
endtask
task ram_read_chk;
input rst_t;
input wr_t;
input [3:0] addr_t;
begin
#(TIME_PERIOD / 2 - SETUP_TIME);
rst_tb = rst_t;
wr = wr_t;
addr = addr_t;
@(posedge clk);
#(HOLD_TIME);
rst_tb = 1'b0;
wr = ~wr;
#(TIME_PERIOD / 2 - SETUP_TIME);
if ((wr_t == 1'b0) && (out == out_exp))
$display("Correct data read at %0t :: address = %b, data = %b", $time, addr_t, out);
else $display("Error occured at %0t:: address = %b, data = %b", $time, addr_t, out);
end
endtask
endmodule
| 8.099517 |
module sram69120x8 (
CLK,
A,
CEN,
WEN,
D,
Q
);
parameter A_WID = 17, D_WID = 8;
input CLK;
input [A_WID-1:0] A;
input [D_WID-1:0] D;
input CEN;
input WEN;
output [D_WID-1:0] Q;
reg [D_WID-1:0] Q;
/*********************************************/
/* this part should be replaced by ASIC sram */
reg [D_WID-1:0] mem[0:69119];
always @(posedge CLK) if (~CEN && ~WEN) mem[A] <= #1 D;
always @(posedge CLK) if (~CEN && WEN) Q <= #1 mem[A];
/*********************************************/
endmodule
| 7.207276 |
module SRAM64 (
input CLK,
input RST,
input SRAM_WE_N,
input [16:0] SRAM_ADDR, // 17 Bits (was 19)
inout signed [63:0] SRAM_DQ // Data 64 Bits (Write 32 Least Significant Bits When WE)
);
reg [31:0] memory[0:127]; // 65535
assign #30 SRAM_DQ = SRAM_WE_N ? {memory[{SRAM_ADDR[16:1], 1'b1}], memory[{SRAM_ADDR[16:1], 1'b0}]}: 64'bz;
always @(posedge CLK) begin
if (~SRAM_WE_N) begin
$display("SRAM WRITE mem[%d] = %d", SRAM_ADDR, SRAM_DQ);
memory[SRAM_ADDR] <= SRAM_DQ[31:0]; // write in SRAM
end
end
endmodule
| 7.454498 |
module SRAM64x14 (
A,
CE,
WEB,
OEB,
CSB,
I,
O
);
input CE;
input WEB;
input OEB;
input CSB;
input [`numAddr-1:0] A;
input [`wordLength-1:0] I;
output [`wordLength-1:0] O;
reg [`wordLength-1:0] memory [`numWords-1:0];
reg [`wordLength-1:0] data_out1;
reg [`wordLength-1:0] O;
wire RE;
wire WE;
and u1 (RE, ~CSB, WEB);
and u2 (WE, ~CSB, ~WEB);
always @(posedge CE)
if (RE) data_out1 = memory[A];
else if (WE) memory[A] = I;
always @(data_out1 or OEB)
if (!OEB) O = data_out1;
else O = 64'bz;
endmodule
| 6.917022 |
module sramctrl (
input wire clk_in,
input wire rst_in,
input wire trig_in,
input wire rw_in,
input wire [18:0] addr_in,
input wire [7:0] w_data_in,
output reg [7:0] r_data_out,
output reg done_out,
output reg we_n_out,
output reg ce_n_out,
output reg oe_n_out,
output reg lb_n_out,
output reg ub_n_out,
output reg [17:0] addr_out,
inout wire [15:0] data_io
);
reg [2:0] state;
localparam init = 3'b000, idle = 3'b001, read = 3'b010, write = 3'b011, latch = 3'b100;
reg [15:0] data_io_reg;
reg trig_buf;
reg [15:0] r_data, w_data;
assign data_io = data_io_reg;
always @(posedge clk_in, negedge rst_in) begin
if (!rst_in) begin
state <= init;
end else begin
case (state)
init: begin
oe_n_out <= 1'b1;
ce_n_out <= 1'b1;
we_n_out <= 1'b1;
addr_out <= 18'b0;
data_io_reg <= 16'b0;
state <= idle;
end
idle: begin
we_n_out <= 1'b1;
if (trig_in) begin
if (rw_in) begin
oe_n_out <= 1'b0;
addr_out <= addr_in[18:1];
data_io_reg <= 16'bz;
done_out <= 1;
state <= read;
end else begin
oe_n_out <= 1'b1;
addr_out <= addr_in[18:1];
data_io_reg <= w_data;
done_out <= 1;
state <= write;
end
end else begin
oe_n_out <= 1'b1;
ce_n_out <= 1'b0;
we_n_out <= 1'b1;
done_out <= 1'b1;
addr_out <= 18'b0;
state <= idle;
end
end
read: begin
ce_n_out <= 1'b0;
oe_n_out <= 1'b0;
we_n_out <= 1'b1;
r_data <= data_io;
done_out <= 1'b0;
state <= latch;
end
write: begin
ce_n_out <= 1'b0;
oe_n_out <= 1'b1;
we_n_out <= 1'b0;
done_out <= 1'b0;
state <= latch;
end
latch: begin
r_data <= data_io;
state <= idle;
end
default: begin
state <= init;
end
endcase
end
end
always @* begin
if (!rw_in) begin
if (addr_in[0]) begin
ub_n_out <= 1'b1;
lb_n_out <= 1'b0;
w_data[15:8] <= w_data_in;
w_data[7:0] <= 8'b0;
r_data_out <= r_data[7:0];
end else begin
ub_n_out <= 1'b0;
lb_n_out <= 1'b1;
w_data[15:8] <= 8'b0;
w_data[7:0] <= w_data_in;
r_data_out <= r_data[15:8];
end
end else begin
if (addr_in[0]) begin
ub_n_out <= 1'b0;
lb_n_out <= 1'b0;
w_data[15:8] <= w_data_in;
w_data[7:0] <= 8'b0;
r_data_out <= r_data[7:0];
end else begin
ub_n_out <= 1'b0;
lb_n_out <= 1'b0;
w_data[15:8] <= 8'b0;
r_data_out <= r_data[15:8];
w_data[7:0] <= w_data_in;
end
end
end
endmodule
| 7.072356 |
module sramDemo (
LEDR,
SW,
KEY,
CLOCK_50
);
output [9:0] LEDR;
input CLOCK_50;
input [9:0] SW;
input [3:0] KEY;
reg nOE;
reg read;
reg [10:0] adrx;
reg [15:0] mem;
wire [15:0] data;
wire rst;
wire enterWrite;
wire enterRead;
reg [9:0] ledDriver;
wire [31:0] clk; // choosing from 32 different clock speeds
// instantiate clock_divider module
clock_divider cdiv (
.clk_out (clk),
.clk_in (CLOCK_50),
.slowDown(SW[8])
);
// instantiate the sram module
sram mySram (
.data(data),
.clk (clk),
.adrx(adrx),
.nOE (nOE),
.read(read)
);
// tri-state driver for the inout port
assign data = nOE ? mem : 16'bz;
assign rst = SW[9];
assign enterRead = ~KEY[0];
assign enterWrite = ~KEY[1];
assign LEDR = ledDriver;
// state encoding
parameter [2:0] idle = 3'b000, writeSet = 3'b001, writeDo = 3'b011;
parameter [2:0] readSet = 3'b111, readDo = 3'b110;
reg [2:0] state;
always @(posedge clk) begin
//Initialize the system to allow reading and writing
if (rst) begin
ledDriver[0] <= 1;
ledDriver[1] <= 0;
nOE <= 1;
read <= 1;
adrx <= 11'b0;
mem <= 16'b0000000001111111;
state <= idle;
end else begin
case (state)
// transition state between write and read
idle: begin
if (enterRead) begin
ledDriver <= 10'b0;
adrx <= 11'b0;
nOE <= 0;
read <= 1;
state <= readDo;
end else if (enterWrite) begin
ledDriver <= 10'b0000000011;
adrx <= 11'b0;
mem <= 16'b0000000001111111;
nOE <= 1;
read <= 0;
state <= writeDo;
end else begin
//When waiting for a command, light up led[1]
ledDriver <= 10'b0000000010;
end
end
//Tells the SRAM to write the prepared byte of data
writeDo: begin
read <= 1;
state <= writeSet;
end
//Initializes conditions for writing the next byte
writeSet: begin
if (adrx[7:0] == 8'b01111111) begin
read <= 1;
state <= idle;
end else begin
mem <= mem - 1'b1;
adrx <= adrx + 1'b1;
read <= 0;
state <= writeDo;
end
end
//Displays the read byte on the output LEDs
readDo: begin
ledDriver[9:2] <= data[7:0];
state <= readSet;
end
//Prepares to read the next byte of data from the SRAM
readSet: begin
if (adrx[7:0] == 8'b01111111) begin
adrx <= 11'b0;
state <= idle;
end else begin
adrx <= adrx + 1'b1;
state <= readDo;
end
end
default: begin
state <= idle;
end
endcase
end
end
endmodule
| 7.084993 |
module clock_divider (
clk_out,
clk_in,
slowDown
);
output clk_out;
reg [31:0] divided_clocks;
input clk_in, slowDown;
assign clk_out = slowDown ? divided_clocks[23] : clk_in;
initial divided_clocks = 0;
always @(posedge clk_in) divided_clocks = divided_clocks + 1;
endmodule
| 6.818038 |
module
// so the outer module corresponds to an SRAM generated with the
// OpenRAM memory compiler.
`ifndef SRAM_SRAM_GENERIC_V
`define SRAM_SRAM_GENERIC_V
module sram_SramGeneric
#(
parameter p_data_nbits = 1,
parameter p_num_entries = 2,
// Local constants not meant to be set from outside the module
parameter c_addr_nbits = $clog2(p_num_entries),
parameter c_data_nbytes = (p_data_nbits+7)/8 // $ceil(p_data_nbits/8)
)(
input logic clk0, // clk
input logic web0, // bar( write en )
input logic csb0, // bar( whole SRAM en )
input logic [c_addr_nbits-1:0] addr0, // address
input logic [p_data_nbits-1:0] din0, // write data
output logic [p_data_nbits-1:0] dout0 // read data
);
logic [p_data_nbits-1:0] mem[p_num_entries-1:0];
logic [p_data_nbits-1:0] data_out1;
logic [p_data_nbits-1:0] wdata1;
always @( posedge clk0 ) begin
// Read path
if ( ~csb0 && web0 )
data_out1 <= mem[addr0];
else
data_out1 <= {p_data_nbits{1'bx}};
end
// Write path
genvar i;
generate
for ( i = 0; i < c_data_nbytes; i = i + 1 )
begin : write
always @( posedge clk0 ) begin
if ( ~csb0 && ~web0 )
mem[addr0][ (i+1)*8-1 : i*8 ] <= din0[ (i+1)*8-1 : i*8 ];
end
end
endgenerate
assign dout0 = data_out1;
endmodule
| 8.153305 |
module
// so the outer module corresponds to an SRAM generated with the
// OpenRAM memory compiler.
`ifndef SRAM_SRAM_GENERIC_V
`define SRAM_SRAM_GENERIC_V
module sram_SramGenericVRTL
#(
parameter p_data_nbits = 1,
parameter p_num_entries = 2,
// Local constants not meant to be set from outside the module
parameter c_addr_nbits = $clog2(p_num_entries),
parameter c_data_nbytes = (p_data_nbits+7)/8 // $ceil(p_data_nbits/8)
)(
input logic clk0, // clk
input logic web0, // bar( write en )
input logic csb0, // bar( whole SRAM en )
input logic [c_addr_nbits-1:0] addr0, // address
input logic [p_data_nbits-1:0] din0, // write data
output logic [p_data_nbits-1:0] dout0 // read data
);
logic [p_data_nbits-1:0] mem[p_num_entries-1:0];
logic [p_data_nbits-1:0] data_out1;
logic [p_data_nbits-1:0] wdata1;
always @( posedge clk0 ) begin
// Read path
if ( ~csb0 && web0 )
data_out1 <= mem[addr0];
else
data_out1 <= {p_data_nbits{1'bx}};
end
// Write path
genvar i;
generate
for ( i = 0; i < c_data_nbytes; i = i + 1 )
begin : write
always @( posedge clk0 ) begin
if ( ~csb0 && ~web0 )
mem[addr0][ (i+1)*8-1 : i*8 ] <= din0[ (i+1)*8-1 : i*8 ];
end
end
endgenerate
assign dout0 = data_out1;
endmodule
| 8.153305 |
module sramGTK;
// connect the two modules
wire [9:0] ledrBench;
wire clockBench;
wire [9:0] swBench;
wire [3:0] keyBench;
// declare an instance of the sramTop module
sramDemo mySramDemo (
ledrBench,
swBench,
keyBench,
clockBench
);
// declare an instance of the testbench
Tester aTester (
swBench,
keyBench,
clockBench,
ledrBench
);
// file for gtkwave
initial begin
$dumpfile("sramGTK.vcd");
$dumpvars(1, mySramDemo);
end
endmodule
| 7.263598 |
module sramR (
input clk100mhz,
input w,
ce,
input [15:0] dataBus,
output [15:0] LED
);
reg [15:0] data;
always @(posedge clk100mhz) begin
if (w && (ce == 0)) begin
data <= dataBus;
end
end
/*if(changeaddr==0) addrBus= addrBus1;
else if(changeaddr) addrBus= addrBus1;*/
assign LED = data;
endmodule
| 6.871882 |
module datapath_latch_sramsp2048x128 (
CLK,
Q_update,
D_update,
SE,
SI,
D,
DFTRAMBYP,
mem_path,
XQ,
Q
);
input CLK, Q_update, D_update, SE, SI, D, DFTRAMBYP, mem_path, XQ;
output Q;
reg D_int;
reg Q;
// Model PHI2 portion
always @(CLK or SE or SI or D) begin
if (CLK === 1'b0) begin
if (SE === 1'b1) D_int = SI;
else if (SE === 1'bx) D_int = 1'bx;
else D_int = D;
end
end
// model output side of RAM latch
always @(posedge Q_update or posedge D_update or mem_path or posedge XQ) begin
if (XQ === 1'b0) begin
if (DFTRAMBYP === 1'b1 || D_update == 1'b1) Q = D_int;
else Q = mem_path;
end else Q = 1'bx;
end
endmodule
| 6.596005 |
module datapath_latch_sramsp32768x36 (
CLK,
Q_update,
D_update,
SE,
SI,
D,
DFTRAMBYP,
mem_path,
XQ,
Q
);
input CLK, Q_update, D_update, SE, SI, D, DFTRAMBYP, mem_path, XQ;
output Q;
reg D_int;
reg Q;
// Model PHI2 portion
always @(CLK or SE or SI or D) begin
if (CLK === 1'b0) begin
if (SE === 1'b1) D_int = SI;
else if (SE === 1'bx) D_int = 1'bx;
else D_int = D;
end
end
// model output side of RAM latch
always @(posedge Q_update or posedge D_update or mem_path or posedge XQ) begin
if (XQ === 1'b0) begin
if (DFTRAMBYP === 1'b1 || D_update == 1'b1) Q = D_int;
else Q = mem_path;
end else Q = 1'bx;
end
endmodule
| 6.596005 |
module datapath_latch_sramsp4096x128 (
CLK,
Q_update,
D_update,
SE,
SI,
D,
DFTRAMBYP,
mem_path,
XQ,
Q
);
input CLK, Q_update, D_update, SE, SI, D, DFTRAMBYP, mem_path, XQ;
output Q;
reg D_int;
reg Q;
// Model PHI2 portion
always @(CLK or SE or SI or D) begin
if (CLK === 1'b0) begin
if (SE === 1'b1) D_int = SI;
else if (SE === 1'bx) D_int = 1'bx;
else D_int = D;
end
end
// model output side of RAM latch
always @(posedge Q_update or posedge D_update or mem_path or posedge XQ) begin
if (XQ === 1'b0) begin
if (DFTRAMBYP === 1'b1 || D_update == 1'b1) Q = D_int;
else Q = mem_path;
end else Q = 1'bx;
end
endmodule
| 6.596005 |
module datapath_latch_sramsp4096x144 (
CLK,
Q_update,
D_update,
SE,
SI,
D,
DFTRAMBYP,
mem_path,
XQ,
Q
);
input CLK, Q_update, D_update, SE, SI, D, DFTRAMBYP, mem_path, XQ;
output Q;
reg D_int;
reg Q;
// Model PHI2 portion
always @(CLK or SE or SI or D) begin
if (CLK === 1'b0) begin
if (SE === 1'b1) D_int = SI;
else if (SE === 1'bx) D_int = 1'bx;
else D_int = D;
end
end
// model output side of RAM latch
always @(posedge Q_update or posedge D_update or mem_path or posedge XQ) begin
if (XQ === 1'b0) begin
if (DFTRAMBYP === 1'b1 || D_update == 1'b1) Q = D_int;
else Q = mem_path;
end else Q = 1'bx;
end
endmodule
| 6.596005 |
module datapath_latch_sramsp8192x128 (
CLK,
Q_update,
D_update,
SE,
SI,
D,
DFTRAMBYP,
mem_path,
XQ,
Q
);
input CLK, Q_update, D_update, SE, SI, D, DFTRAMBYP, mem_path, XQ;
output Q;
reg D_int;
reg Q;
// Model PHI2 portion
always @(CLK or SE or SI or D) begin
if (CLK === 1'b0) begin
if (SE === 1'b1) D_int = SI;
else if (SE === 1'bx) D_int = 1'bx;
else D_int = D;
end
end
// model output side of RAM latch
always @(posedge Q_update or posedge D_update or mem_path or posedge XQ) begin
if (XQ === 1'b0) begin
if (DFTRAMBYP === 1'b1 || D_update == 1'b1) Q = D_int;
else Q = mem_path;
end else Q = 1'bx;
end
endmodule
| 6.596005 |
module datapath_latch_sramsp8192x144 (
CLK,
Q_update,
D_update,
SE,
SI,
D,
DFTRAMBYP,
mem_path,
XQ,
Q
);
input CLK, Q_update, D_update, SE, SI, D, DFTRAMBYP, mem_path, XQ;
output Q;
reg D_int;
reg Q;
// Model PHI2 portion
always @(CLK or SE or SI or D) begin
if (CLK === 1'b0) begin
if (SE === 1'b1) D_int = SI;
else if (SE === 1'bx) D_int = 1'bx;
else D_int = D;
end
end
// model output side of RAM latch
always @(posedge Q_update or posedge D_update or mem_path or posedge XQ) begin
if (XQ === 1'b0) begin
if (DFTRAMBYP === 1'b1 || D_update == 1'b1) Q = D_int;
else Q = mem_path;
end else Q = 1'bx;
end
endmodule
| 6.596005 |
module datapath_latch_sramsp8192x32 (
CLK,
Q_update,
D_update,
SE,
SI,
D,
DFTRAMBYP,
mem_path,
XQ,
Q
);
input CLK, Q_update, D_update, SE, SI, D, DFTRAMBYP, mem_path, XQ;
output Q;
reg D_int;
reg Q;
// Model PHI2 portion
always @(CLK or SE or SI or D) begin
if (CLK === 1'b0) begin
if (SE === 1'b1) D_int = SI;
else if (SE === 1'bx) D_int = 1'bx;
else D_int = D;
end
end
// model output side of RAM latch
always @(posedge Q_update or posedge D_update or mem_path or posedge XQ) begin
if (XQ === 1'b0) begin
if (DFTRAMBYP === 1'b1 || D_update == 1'b1) Q = D_int;
else Q = mem_path;
end else Q = 1'bx;
end
endmodule
| 6.596005 |
module dual_port_sram_TB ();
parameter RAM_WIDTH = 8;
parameter RAM_DEPTH = 64;
parameter ADDR_SIZE = 8;
reg clk, reset, rwenable_A, rwenable_B;
reg [RAM_WIDTH-1:0] data_A, data_B;
reg [ADDR_SIZE-1:0] addr_A, addr_B;
wire [RAM_WIDTH-1:0] outputData_A, outputData_B;
integer i;
dual_port_sram DUT (
clk,
reset,
data_A,
data_B,
rwenable_A,
rwenable_B,
addr_A,
addr_B,
outputData_A,
outputData_B
);
always begin
#10 clk = ~clk;
end
task initialize;
begin
clk = 0;
reset = 1;
rwenable_A = 0;
rwenable_B = 0;
data_A = 8'bx;
data_B = 8'bx;
addr_A = 8'bx;
addr_B = 8'bx;
end
endtask
initial begin
$dumpfile("SRAMwaveform.vcd");
$dumpvars(0, dual_port_sram_TB);
end
initial begin
initialize;
$display("Writing to RAM\n");
for (i = 1; i < 5; i = i + 1) begin
@(negedge clk);
#5 reset = 0;
addr_A = i;
rwenable_A = 1;
data_A = 15 + i;
addr_B = i + 4;
rwenable_B = 1;
data_B = 19 + i;
$display($time, " Writing in addr %d = %d", addr_A, data_A);
$display($time, " Writing in addr %d = %d", addr_B, data_B);
end
#20 // one clock cycle
$display(
"Reading from RAM\n"
);
for (i = 1; i < 9; i = i + 1) begin
@(negedge clk) #5 rwenable_A = 0;
rwenable_B = 0;
addr_A = 9 - i;
$display($time, "The value in Address %d is %d", addr_A, outputData_B);
end
#10 $finish;
end
endmodule
| 9.237963 |
module SRAMVerilogAWS #(
parameter WORDS = 1024,
parameter AWIDTH = 10,
parameter DWIDTH = 32
) (
input clk,
input [AWIDTH-1:0] raddr,
input [AWIDTH-1:0] waddr,
input raddrEn,
input waddrEn,
input wen,
input [DWIDTH-1:0] wdata,
input flow,
output reg [DWIDTH-1:0] rdata
);
reg [DWIDTH-1:0] mem[0:WORDS-1];
always @(posedge clk) begin
if (wen) mem[waddr] <= wdata;
if (flow) rdata <= mem[raddr];
end
endmodule
| 6.817776 |
module SRAMVerilogSim #(
parameter WORDS = 1024,
parameter AWIDTH = 10,
parameter DWIDTH = 32
) (
input clk,
input [AWIDTH-1:0] raddr,
input [AWIDTH-1:0] waddr,
input raddrEn,
input waddrEn,
input wen,
input [DWIDTH-1:0] wdata,
output reg [DWIDTH-1:0] rdata
);
reg [DWIDTH-1:0] mem[0:WORDS-1];
always @(negedge clk) begin
if (wen) begin
mem[waddr] <= wdata;
end
end
always @(posedge clk) begin
rdata <= mem[raddr];
end
endmodule
| 6.966284 |
module are prefixed by port0_, meaning all reads
// and writes happen through the only port. Multiported SRAMs have ports
// prefixed by port1_, port2_, etc.
//
// The following list describes each port of this module.
//
// Port Name Direction Description
// ----------------------------------------------------------------------
// port0_val I port enable (1 = enabled)
// port0_type I transaction type, 0 = read, 1 = write
// port0_idx I index of the SRAM
// port0_wdata I write data
// port0_rdata O read data output
//
`ifndef SRAM_SRAM_VRTL
`define SRAM_SRAM_VRTL
`include "sram/SramGenericVRTL.v"
`include "sram/SRAM_32x256_1rw.v"
`include "sram/SRAM_128x256_1rw.v"
// ''' TUTORIAL TASK '''''''''''''''''''''''''''''''''''''''''''''''''''''
// Include new SRAM configuration RTL model
// '''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
module sram_SramVRTL
#(
parameter p_data_nbits = 32,
parameter p_num_entries = 256,
// Local constants not meant to be set from outside the module
parameter c_addr_nbits = $clog2(p_num_entries),
parameter c_data_nbytes = (p_data_nbits+7)/8 // $ceil(p_data_nbits/8)
)(
input logic clk,
input logic reset,
input logic port0_val,
input logic port0_type,
input logic [c_addr_nbits-1:0] port0_idx,
input logic [p_data_nbits-1:0] port0_wdata,
output logic [p_data_nbits-1:0] port0_rdata
);
logic clk0;
logic web0;
logic csb0;
logic [c_addr_nbits-1:0] addr0;
logic [p_data_nbits-1:0] din0;
logic [p_data_nbits-1:0] dout0;
assign clk0 = clk;
assign web0 = ~port0_type;
assign csb0 = ~port0_val;
assign addr0 = port0_idx;
assign din0 = port0_wdata;
assign port0_rdata = dout0;
generate
if ( p_data_nbits == 32 && p_num_entries == 256 ) SRAM_32x256_1rw sram (.*);
else if ( p_data_nbits == 128 && p_num_entries == 256 ) SRAM_128x256_1rw sram (.*);
// ''' TUTORIAL TASK '''''''''''''''''''''''''''''''''''''''''''''''''
// Choose new SRAM configuration RTL model
// '''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
else
sram_SramGenericVRTL#(p_data_nbits,p_num_entries) sram (.*);
endgenerate
endmodule
| 7.792858 |
module sram_0 (
// inputs:
iADDR,
iBE_N,
iCE_N,
iCLK,
iDATA,
iOE_N,
iWE_N,
// outputs:
SRAM_ADDR,
SRAM_CE_N,
SRAM_DQ,
SRAM_LB_N,
SRAM_OE_N,
SRAM_UB_N,
SRAM_WE_N,
oDATA
);
output [17:0] SRAM_ADDR;
output SRAM_CE_N;
inout [15:0] SRAM_DQ;
output SRAM_LB_N;
output SRAM_OE_N;
output SRAM_UB_N;
output SRAM_WE_N;
output [15:0] oDATA;
input [17:0] iADDR;
input [1:0] iBE_N;
input iCE_N;
input iCLK;
input [15:0] iDATA;
input iOE_N;
input iWE_N;
wire [17:0] SRAM_ADDR;
wire SRAM_CE_N;
wire [15:0] SRAM_DQ;
wire SRAM_LB_N;
wire SRAM_OE_N;
wire SRAM_UB_N;
wire SRAM_WE_N;
wire [15:0] oDATA;
SRAM_16Bit_512K the_SRAM_16Bit_512K (
.SRAM_ADDR(SRAM_ADDR),
.SRAM_CE_N(SRAM_CE_N),
.SRAM_DQ (SRAM_DQ),
.SRAM_LB_N(SRAM_LB_N),
.SRAM_OE_N(SRAM_OE_N),
.SRAM_UB_N(SRAM_UB_N),
.SRAM_WE_N(SRAM_WE_N),
.iADDR (iADDR),
.iBE_N (iBE_N),
.iCE_N (iCE_N),
.iCLK (iCLK),
.iDATA (iDATA),
.iOE_N (iOE_N),
.iWE_N (iWE_N),
.oDATA (oDATA)
);
endmodule
| 7.13854 |
module SRAM_1 #(
parameter DATA_WIDTH = 1280,
parameter ADDR_WIDTH = 5
) (
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] addr,
input we,
clk,
output [(DATA_WIDTH-1):0] q
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
// Variable to hold the registered read address
// reg [ADDR_WIDTH-1:0] addr_reg;
always @(posedge clk) begin
// Write
if (we) begin
ram[addr] <= data;
end
// addr_reg <= addr;
end
assign q = ram[addr];
endmodule
| 8.196529 |
module sram_1024x32 (
addr,
clk,
din,
dout,
we
);
input clk, we;
input [9:0] addr;
input [31:0] din;
output reg [31:0] dout;
reg [31:0] mem[0:1023];
always @(posedge clk) begin
if (!we) begin
// write
mem[addr] <= din[31:0];
dout <= 32'bz;
end else if (we)
// read
dout <= mem[addr];
else dout <= 32'bz;
end
endmodule
| 6.627708 |
module sram_112x128 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
spare_wen0,
addr0,
din0,
dout0
);
parameter NUM_WMASKS = 14;
parameter DATA_WIDTH = 113;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [ADDR_WIDTH-1:0] addr0;
input [NUM_WMASKS-1:0] wmask0; // write mask
input spare_wen0; // spare mask
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
endmodule
| 6.883001 |
module SRAM_16Bit_512K ( // Host Data
oDATA,
iDATA,
iADDR,
iWE_N,
iOE_N,
iCE_N,
iCLK,
iBE_N,
// SRAM
SRAM_DQ,
SRAM_ADDR,
SRAM_UB_N,
SRAM_LB_N,
SRAM_WE_N,
SRAM_CE_N,
SRAM_OE_N
);
// Host Side
input [15:0] iDATA;
output [15:0] oDATA;
input [17:0] iADDR;
input iWE_N, iOE_N;
input iCE_N, iCLK;
input [1:0] iBE_N;
// SRAM Side
inout [15:0] SRAM_DQ;
output [17:0] SRAM_ADDR;
output SRAM_UB_N, SRAM_LB_N, SRAM_WE_N, SRAM_CE_N, SRAM_OE_N;
assign SRAM_DQ = SRAM_WE_N ? 16'hzzzz : iDATA;
assign oDATA = SRAM_DQ;
assign SRAM_ADDR = iADDR;
assign SRAM_WE_N = iWE_N;
assign SRAM_OE_N = iOE_N;
assign SRAM_CE_N = iCE_N;
assign SRAM_UB_N = iBE_N[1];
assign SRAM_LB_N = iBE_N[0];
endmodule
| 7.900918 |
module sram_16x128b (
input clk,
input csb, //chip enable
input wsb, //write enable
input [128-1:0] wdata, //write data
input [5:0] waddr, //write address
input [5:0] raddr, //read address
output reg [16*8-1:0] rdata //read data
);
localparam WEIGHT_WIDTH = 16;
localparam WEIGHT_PIXEL_NUM = 8;
/*
/////////////////////
index 0~19 : conv1_w(20)
index 20 : conv1_b(1)
index 21 ~ 1020 conv2_w(1000)
index 1021 ~ 1022 conv2_b(2)
index 1100 ~ 17099 fc1_w(16000)
index 17100 ~ 17299 score_w(200)
/////////////////////
*/
reg [WEIGHT_PIXEL_NUM*WEIGHT_WIDTH-1:0] mem[0:16-1];
reg [WEIGHT_PIXEL_NUM*WEIGHT_WIDTH-1:0] _rdata;
always @(posedge clk) if (~csb && ~wsb) mem[waddr] <= wdata;
always @(posedge clk) if (~csb) _rdata <= mem[raddr];
always @* begin
//rdata = #(`cycle_period*0.2) _rdata;
rdata = _rdata;
end
task load_w(input integer index, input [16*8-1:0] weight_input);
mem[index] = weight_input;
endtask
task dis();
integer i;
for (i = 21; i < 41; i = i + 1) begin
$display("%b", mem[i]);
end
endtask
endmodule
| 6.707188 |
module sky130_sram_1kbyte_1rw1r_32x256_8#(
// parameter NUM_WMASKS = 4,
// parameter DATA_WIDTH = 32,
// parameter ADDR_WIDTH = 8,
// parameter RAM_DEPTH = 256,
// parameter DELAY = 0
// )(
// input clk0, // clock
// input csb0, // active low chip select
// input web0, // active low write control
// input [NUM_WMASKS-1:0] wmask0, // write mask
// input [ADDR_WIDTH-1:0] addr0,
// input [DATA_WIDTH-1:0] din0,
// output reg [DATA_WIDTH-1:0] dout0,
// input clk1, // clock
// input csb1, // active low chip select
// input [ADDR_WIDTH-1:0] addr1,
// output reg [DATA_WIDTH-1:0] dout1
// );
// reg csb0_reg;
// reg web0_reg;
// reg [NUM_WMASKS-1:0] wmask0_reg;
// reg [ADDR_WIDTH-1:0] addr0_reg;
// reg [DATA_WIDTH-1:0] din0_reg;
// reg csb1_reg;
// reg [ADDR_WIDTH-1:0] addr1_reg;
// reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
// // All inputs are registers
// always @(posedge clk0)
// begin
// csb0_reg = csb0;
// web0_reg = web0;
// wmask0_reg = wmask0;
// addr0_reg = addr0;
// din0_reg = din0;
// dout0 = 32'bx;
// // if ( !csb0_reg && web0_reg )
// // $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
// // if ( !csb0_reg && !web0_reg )
// // $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
// end
// // All inputs are registers
// always @(posedge clk1)
// begin
// csb1_reg = csb1;
// addr1_reg = addr1;
// if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
// $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
// dout1 = 32'bx;
// // if ( !csb1_reg )
// // $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
// end
// // Memory Write Block Port 0
// // Write Operation : When web0 = 0, csb0 = 0
// always @ (negedge clk0)
// begin : MEM_WRITE0
// if ( !csb0_reg && !web0_reg ) begin
// if (wmask0_reg[0])
// mem[addr0_reg][7:0] = din0_reg[7:0];
// if (wmask0_reg[1])
// mem[addr0_reg][15:8] = din0_reg[15:8];
// if (wmask0_reg[2])
// mem[addr0_reg][23:16] = din0_reg[23:16];
// if (wmask0_reg[3])
// mem[addr0_reg][31:24] = din0_reg[31:24];
// end
// end
// // Memory Read Block Port 0
// // Read Operation : When web0 = 1, csb0 = 0
// always @ (negedge clk0)
// begin : MEM_READ0
// if (!csb0_reg && web0_reg)
// dout0 <= #(DELAY) mem[addr0_reg];
// end
// // Memory Read Block Port 1
// // Read Operation : When web1 = 1, csb1 = 0
// always @ (negedge clk1)
// begin : MEM_READ1
// if (!csb1_reg)
// dout1 <= #(DELAY) mem[addr1_reg];
// end
// endmodule
| 7.095527 |
module sram_1r1w #(
parameter DATA_WIDTH = 32,
parameter SIZE = 1024,
parameter ADDR_WIDTH = $clog2(SIZE)
) (
input clk,
input [ADDR_WIDTH - 1:0] rd_addr,
output reg [DATA_WIDTH - 1:0] rd_data = 0,
input wr_enable,
input [ADDR_WIDTH - 1:0] wr_addr,
input [DATA_WIDTH - 1:0] wr_data
);
reg [DATA_WIDTH - 1:0] data[0:SIZE - 1];
integer i;
initial begin
for (i = 0; i < SIZE; i = i + 1) data[i] = 0;
rd_data = 0;
$readmemh("microcode.hex", data);
end
always @(posedge clk) begin
if (wr_enable) data[wr_addr] <= wr_data;
if (wr_addr == rd_addr && wr_enable) rd_data <= wr_data;
else rd_data <= data[rd_addr];
end
endmodule
| 6.797447 |
module sram_1rw0r0w_32_128_freepdk45 (
`ifdef USE_POWER_PINS
vdd,
gnd,
`endif
// Port 0: RW
clk0,
csb0,
web0,
addr0,
din0,
dout0
);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 7;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 0;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vdd;
inout gnd;
`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
reg csb0_reg;
reg web0_reg;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
reg [DATA_WIDTH-1:0] dout0;
// All inputs are registers
always @(posedge clk0) begin
csb0_reg = csb0;
web0_reg = web0;
addr0_reg = addr0;
din0_reg = din0;
end
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0
always @(negedge clk0) begin : MEM_WRITE0
if (!csb0_reg && !web0_reg) begin
mem[addr0_reg][31:0] = din0_reg[31:0];
end
end
// Memory Read Block Port 0
// Read Operation : When web0 = 1, csb0 = 0
always @(negedge clk0) begin : MEM_READ0
if (!csb0_reg && web0_reg) dout0 <= #(DELAY) mem[addr0_reg];
end
endmodule
| 7.442043 |
module sram_1rw1r_32_256_8_sky130 (
`ifdef USE_POWER_PINS
vdd,
gnd,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
`ifdef USE_POWER_PINS
inout vdd;
inout gnd;
`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [NUM_WMASKS-1:0] wmask0; // write mask
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
input clk1; // clock
input csb1; // active low chip select
input [ADDR_WIDTH-1:0] addr1;
output [DATA_WIDTH-1:0] dout1;
reg csb0_reg;
reg web0_reg;
reg [NUM_WMASKS-1:0] wmask0_reg;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
reg [DATA_WIDTH-1:0] dout0;
// All inputs are registers
always @(posedge clk0) begin
csb0_reg = csb0;
web0_reg = web0;
wmask0_reg = wmask0;
addr0_reg = addr0;
din0_reg = din0;
dout0 = #(DELAY) 32'bx;
`ifdef DBG
if (!csb0_reg && web0_reg)
$display($time, " Reading %m addr0=%b dout0=%b", addr0_reg, mem[addr0_reg]);
if (!csb0_reg && !web0_reg)
$display($time, " Writing %m addr0=%b din0=%b wmask0=%b", addr0_reg, din0_reg, wmask0_reg);
`endif
end
reg csb1_reg;
reg [ADDR_WIDTH-1:0] addr1_reg;
reg [DATA_WIDTH-1:0] dout1;
// All inputs are registers
always @(posedge clk1) begin
csb1_reg = csb1;
addr1_reg = addr1;
`ifdef DBG
if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
$display(
$time, " WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!", addr0, addr1
);
dout1 = 32'bx;
if (!csb1_reg) $display($time, " Reading %m addr1=%b dout1=%b", addr1_reg, mem[addr1_reg]);
`endif
end
reg [DATA_WIDTH-1:0] mem[0:RAM_DEPTH-1];
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0
always @(negedge clk0) begin : MEM_WRITE0
if (!csb0_reg && !web0_reg) begin
if (wmask0_reg[0]) mem[addr0_reg][7:0] = din0_reg[7:0];
if (wmask0_reg[1]) mem[addr0_reg][15:8] = din0_reg[15:8];
if (wmask0_reg[2]) mem[addr0_reg][23:16] = din0_reg[23:16];
if (wmask0_reg[3]) mem[addr0_reg][31:24] = din0_reg[31:24];
end
end
// Memory Read Block Port 0
// Read Operation : When web0 = 1, csb0 = 0
always @(negedge clk0) begin : MEM_READ0
if (!csb0_reg && web0_reg) dout0 <= #(DELAY) mem[addr0_reg];
end
// Memory Read Block Port 1
// Read Operation : When web1 = 1, csb1 = 0
always @(negedge clk1) begin : MEM_READ1
if (!csb1_reg) dout1 <= #(DELAY) mem[addr1_reg];
end
endmodule
| 6.906604 |
module sram_20000x100b (
input clk,
input csb, //chip enable
input wsb, //write enable
input wdata, //write data
input [9:0] waddr, //write address
input [16:0] raddr, //read address
output reg [99:0] rdata //read data
);
localparam WEIGHT_WIDTH = 4;
localparam WEIGHT_PIXEL_NUM = 25;
/*
/////////////////////
index 0~19 : conv1_w(20)
index 20 : conv1_b(1)
index 21 ~ 1020 conv2_w(1000)
index 1021 ~ 1022 conv2_b(2)
index 1100 ~ 17099 fc1_w(16000)
index 17100 ~ 17299 score_w(200)
/////////////////////
*/
reg [WEIGHT_PIXEL_NUM*WEIGHT_WIDTH-1:0] mem[0:20000];
reg [99:0] _rdata;
always @(posedge clk) if (~csb && ~wsb) mem[waddr] <= wdata;
always @(posedge clk) if (~csb) _rdata <= mem[raddr];
always @* begin
rdata = #(`cycle_period * 0.2) _rdata;
end
task load_w(input integer index, input [99:0] weight_input);
mem[index] = weight_input;
endtask
task dis();
integer i;
for (i = 21; i < 41; i = i + 1) begin
$display("%b", mem[i]);
end
endtask
endmodule
| 6.699095 |
module sram_24x4096 (
input clk_i,
input rst_i,
input wr_en_i,
input rd_en_i,
input [11:0] addr_i,
input [23:0] wdata_i,
output [23:0] rdata_o
);
reg [23:0] bram [4095:0];
integer i;
reg [23:0] data;
//add implementation code here
always @(posedge clk_i or negedge rst_i) begin
if (!rst_i) begin
for (i = 0; i <= 4095; i = i + 1) //reset, 按字操作
bram[i] <= 23'b0;
end else if (wr_en_i) begin
bram[addr_i] <= wdata_i;
end else if (rd_en_i) begin
data <= bram[addr_i];
end
// else begin
// data <= 23'bz; //读写均无效时，为高阻态。若不加此句，时序会出现问题
//end
end
assign rdata_o = data;
endmodule
| 6.542987 |
module sram_24x4096 (
input clk_i,
input rst_i,
input wr_en_i,
input rd_en_i,
input [11:0] addr_i,
input [23:0] wdata_i,
output [23:0] rdata_o
);
reg [23:0] bram [4095:0];
integer i;
reg [23:0] data;
//add implementation code here
always @(posedge clk_i or negedge rst_i) begin
if (!rst_i) begin
for (i = 0; i <= 2047; i = i + 1) //reset, 按字操作
bram[i] <= 23'b0;
end else if (wr_en_i) begin
bram[addr_i] <= wdata_i;
end else if (rd_en_i) begin
data <= bram[addr_i];
end
// else begin
// data <= 23'bz; //读写均无效时，为高阻态。若不加此句，时序会出现问题
//end
end
assign rdata_o = data;
endmodule
| 6.542987 |
module sram_128x32b (
input clk,
input [3:0] bytemask,
input csb, //chip enable
input wsb, //write enable
input [7:0] wdata, //write data
input [9:0] waddr, //write address
input [9:0] raddr, //read address
output reg [31:0] rdata //read data
);
reg [31:0] _rdata;
reg [31:0] mem[0:256-1];
///////改bytemask
always @(posedge clk) begin
if (~csb && ~wsb) begin
case (bytemask)
4'b0001: mem[waddr][7:0] <= wdata;
4'b0010: mem[waddr][15:8] <= wdata;
4'b0100: mem[waddr][23:16] <= wdata;
4'b1000: mem[waddr][31:24] <= wdata;
default: mem[waddr] <= 0;
endcase
end
end
always @(posedge clk) begin
if (~csb) begin
_rdata <= mem[raddr];
end
end
always @* begin
//rdata = #(`cycle_period*0.2) _rdata;
rdata = _rdata;
end
task char2sram(input [31:0] index, input [31:0] char_in);
mem[index] = char_in;
endtask
task display();
integer this_i, this_j;
reg signed [7:0] index_0, index_1, index_2, index_3;
begin
for (this_i = 0; this_i < 80; this_i = this_i + 1) begin
index_0 = mem[this_i][31:24];
index_1 = mem[this_i][23:16];
index_2 = mem[this_i][15:8];
index_3 = mem[this_i][7:0];
$write("%d %d %d %d \n", index_0, index_1, index_2, index_3);
end
end
endtask
endmodule
| 7.208115 |
module sram (
input clk,
input CEN,
input WEN,
input [31:0] Din,
input [8:0] Address,
output reg signed [31:0] Dout //512 32-bits SRAMs
);
reg signed [31:0] temp[511:0];
reg signed [31:0] out_buffer;
reg notice;
////////////timing specification
specify
//$setuphold(posedge clk, Din, 20, 20, notice); //setup time 20ps, hold time 20ps
$setup(Din, posedge clk, 20, notice);
$hold(posedge clk, Din, 20, notice);
$period(posedge clk, 500, notice); //Maximum Freq 2GHz, Minimum period 500ps
endspecify
always @(notice) begin
Dout <= 32'hXXXXXXXX;
temp[Address] <= 32'hXXXXXXXX;
end
//////////sram function
always @(posedge clk) begin
if(!CEN) //CEN=0 enable
begin
if (!WEN) //WEN=0 Write Operation
temp[Address] <= Din;
else if (WEN) //WEN=1 Read Operation
out_buffer = temp[Address];
#450 Dout = out_buffer;
end else if (CEN) //CEN=1 Disable
Dout <= 32'h0;
end
endmodule
| 7.547687 |
module sram_32_16_sky130 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
spare_wen0,
addr0,
din0,
dout0
);
parameter DATA_WIDTH = 33;
parameter ADDR_WIDTH = 5;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [ADDR_WIDTH-1:0] addr0;
input spare_wen0; // spare mask
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
reg csb0_reg;
reg web0_reg;
reg spare_wen0_reg;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
reg [DATA_WIDTH-1:0] dout0;
// All inputs are registers
always @(posedge clk0) begin
csb0_reg = csb0;
web0_reg = web0;
spare_wen0_reg = spare_wen0;
addr0_reg = addr0;
din0_reg = din0;
#(T_HOLD) dout0 = 32'bx;
if (!csb0_reg && web0_reg && VERBOSE)
$display($time, " Reading %m addr0=%b dout0=%b", addr0_reg, mem[addr0_reg]);
if (!csb0_reg && !web0_reg && VERBOSE)
$display($time, " Writing %m addr0=%b din0=%b", addr0_reg, din0_reg);
end
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0
always @(negedge clk0) begin : MEM_WRITE0
if (!csb0_reg && !web0_reg) begin
mem[addr0_reg][30:0] = din0_reg[30:0];
if (spare_wen0_reg) mem[addr0_reg][32] = din0_reg[32];
end
end
// Memory Read Block Port 0
// Read Operation : When web0 = 1, csb0 = 0
always @(negedge clk0) begin : MEM_READ0
if (!csb0_reg && web0_reg) dout0 <= #(DELAY) mem[addr0_reg];
end
endmodule
| 7.670028 |
module sram_32_256_sky130A (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
addr0,
din0,
dout0
);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
reg csb0_reg;
reg web0_reg;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
reg [DATA_WIDTH-1:0] dout0;
// All inputs are registers
always @(posedge clk0) begin
csb0_reg = csb0;
web0_reg = web0;
addr0_reg = addr0;
din0_reg = din0;
#(T_HOLD) dout0 = 32'bx;
if (!csb0_reg && web0_reg && VERBOSE)
$display($time, " Reading %m addr0=%b dout0=%b", addr0_reg, mem[addr0_reg]);
if (!csb0_reg && !web0_reg && VERBOSE)
$display($time, " Writing %m addr0=%b din0=%b", addr0_reg, din0_reg);
end
reg [DATA_WIDTH-1:0] mem[0:RAM_DEPTH-1];
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0
always @(negedge clk0) begin : MEM_WRITE0
if (!csb0_reg && !web0_reg) begin
mem[addr0_reg][31:0] = din0_reg[31:0];
end
end
// Memory Read Block Port 0
// Read Operation : When web0 = 1, csb0 = 0
always @(negedge clk0) begin : MEM_READ0
if (!csb0_reg && web0_reg) dout0 <= #(DELAY) mem[addr0_reg];
end
endmodule
| 7.678513 |
module sram_336x128 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
spare_wen0,
addr0,
din0,
dout0
);
parameter NUM_WMASKS = 42;
parameter DATA_WIDTH = 337;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [ADDR_WIDTH-1:0] addr0;
input [NUM_WMASKS-1:0] wmask0; // write mask
input spare_wen0; // spare mask
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
endmodule
| 7.297617 |
module SRAM_4R4W_AMT (
addr0_i,
addr1_i,
addr2_i,
addr3_i,
addr0wr_i,
we0_i,
data0wr_i,
addr1wr_i,
we1_i,
data1wr_i,
addr2wr_i,
we2_i,
data2wr_i,
addr3wr_i,
we3_i,
data3wr_i,
clk,
reset,
data0_o,
data1_o,
data2_o,
data3_o
);
parameter SRAM_DEPTH = 32;
parameter SRAM_INDEX = 5;
parameter SRAM_WIDTH = 7;
input [SRAM_INDEX-1:0] addr0_i;
input [SRAM_INDEX-1:0] addr1_i;
input [SRAM_INDEX-1:0] addr2_i;
input [SRAM_INDEX-1:0] addr3_i;
input [SRAM_INDEX-1:0] addr0wr_i;
input [SRAM_INDEX-1:0] addr1wr_i;
input [SRAM_INDEX-1:0] addr2wr_i;
input [SRAM_INDEX-1:0] addr3wr_i;
input [SRAM_WIDTH-1:0] data0wr_i;
input [SRAM_WIDTH-1:0] data1wr_i;
input [SRAM_WIDTH-1:0] data2wr_i;
input [SRAM_WIDTH-1:0] data3wr_i;
input we0_i;
input we1_i;
input we2_i;
input we3_i;
input clk;
input reset;
output [SRAM_WIDTH-1:0] data0_o;
output [SRAM_WIDTH-1:0] data1_o;
output [SRAM_WIDTH-1:0] data2_o;
output [SRAM_WIDTH-1:0] data3_o;
/* Defining register file for SRAM */
reg [SRAM_WIDTH-1:0] sram[SRAM_DEPTH-1:0];
integer i;
assign data0_o = sram[addr0_i];
assign data1_o = sram[addr1_i];
assign data2_o = sram[addr2_i];
assign data3_o = sram[addr3_i];
always @(posedge clk) begin
if (reset) begin
for (i = 0; i < SRAM_DEPTH; i = i + 1) sram[i] <= i;
end else begin
if (we0_i) sram[addr0wr_i] <= data0wr_i;
if (we1_i) sram[addr1wr_i] <= data1wr_i;
if (we2_i) sram[addr2wr_i] <= data2wr_i;
if (we3_i) sram[addr3wr_i] <= data3wr_i;
end
end
endmodule
| 6.628596 |
module implements SRAM.
# Author: FabGen
*******************************************************************************/
`timescale 1ns/100ps
module SRAM_4R4W_FREELIST(
clk,
reset,
addr0_i,
addr1_i,
addr2_i,
addr3_i,
addr0wr_i,
addr1wr_i,
addr2wr_i,
addr3wr_i,
we0_i,
we1_i,
we2_i,
we3_i,
data0wr_i,
data1wr_i,
data2wr_i,
data3wr_i,
data0_o,
data1_o,
data2_o,
data3_o
);
/* Parameters */
parameter SRAM_DEPTH = 16;
parameter SRAM_INDEX = 4;
parameter SRAM_WIDTH = 8;
/* Input and output wires and regs */
input wire clk;
input wire reset;
input wire [SRAM_INDEX-1:0] addr0_i;
input wire [SRAM_INDEX-1:0] addr1_i;
input wire [SRAM_INDEX-1:0] addr2_i;
input wire [SRAM_INDEX-1:0] addr3_i;
input wire [SRAM_INDEX-1:0] addr0wr_i;
input wire [SRAM_INDEX-1:0] addr1wr_i;
input wire [SRAM_INDEX-1:0] addr2wr_i;
input wire [SRAM_INDEX-1:0] addr3wr_i;
input wire we0_i;
input wire we1_i;
input wire we2_i;
input wire we3_i;
input wire [SRAM_WIDTH-1:0] data0wr_i;
input wire [SRAM_WIDTH-1:0] data1wr_i;
input wire [SRAM_WIDTH-1:0] data2wr_i;
input wire [SRAM_WIDTH-1:0] data3wr_i;
output wire [SRAM_WIDTH-1:0] data0_o;
output wire [SRAM_WIDTH-1:0] data1_o;
output wire [SRAM_WIDTH-1:0] data2_o;
output wire [SRAM_WIDTH-1:0] data3_o;
/* The SRAM reg */
reg [SRAM_WIDTH-1:0] sram [SRAM_DEPTH-1:0];
integer i;
/* Read operation */
assign data0_o = sram[addr0_i];
assign data1_o = sram[addr1_i];
assign data2_o = sram[addr2_i];
assign data3_o = sram[addr3_i];
/* Write operation */
always @(posedge clk)
begin
if(reset == 1'b1)
begin
for(i=0; i<SRAM_DEPTH; i=i+1)
begin
sram[i] <= i + `SIZE_RMT;
end
end
else
begin
if(we0_i == 1'b1)
begin
sram[addr0wr_i] <= data0wr_i;
end
if(we1_i == 1'b1)
begin
sram[addr1wr_i] <= data1wr_i;
end
if(we2_i == 1'b1)
begin
sram[addr2wr_i] <= data2wr_i;
end
if(we3_i == 1'b1)
begin
sram[addr3wr_i] <= data3wr_i;
end
end
end
endmodule
| 6.592425 |
module implements SRAM.
# Author: FabGen
*******************************************************************************/
`timescale 1ns/100ps
module SRAM_4R8W(
clk,
reset,
addr0_i,
addr1_i,
addr2_i,
addr3_i,
addr0wr_i,
addr1wr_i,
addr2wr_i,
addr3wr_i,
addr4wr_i,
addr5wr_i,
addr6wr_i,
addr7wr_i,
we0_i,
we1_i,
we2_i,
we3_i,
we4_i,
we5_i,
we6_i,
we7_i,
data0wr_i,
data1wr_i,
data2wr_i,
data3wr_i,
data4wr_i,
data5wr_i,
data6wr_i,
data7wr_i,
data0_o,
data1_o,
data2_o,
data3_o
);
/* Parameters */
parameter SRAM_DEPTH = 16;
parameter SRAM_INDEX = 4;
parameter SRAM_WIDTH = 8;
/* Input and output wires and regs */
input wire clk;
input wire reset;
input wire [SRAM_INDEX-1:0] addr0_i;
input wire [SRAM_INDEX-1:0] addr1_i;
input wire [SRAM_INDEX-1:0] addr2_i;
input wire [SRAM_INDEX-1:0] addr3_i;
input wire [SRAM_INDEX-1:0] addr0wr_i;
input wire [SRAM_INDEX-1:0] addr1wr_i;
input wire [SRAM_INDEX-1:0] addr2wr_i;
input wire [SRAM_INDEX-1:0] addr3wr_i;
input wire [SRAM_INDEX-1:0] addr4wr_i;
input wire [SRAM_INDEX-1:0] addr5wr_i;
input wire [SRAM_INDEX-1:0] addr6wr_i;
input wire [SRAM_INDEX-1:0] addr7wr_i;
input wire we0_i;
input wire we1_i;
input wire we2_i;
input wire we3_i;
input wire we4_i;
input wire we5_i;
input wire we6_i;
input wire we7_i;
input wire [SRAM_WIDTH-1:0] data0wr_i;
input wire [SRAM_WIDTH-1:0] data1wr_i;
input wire [SRAM_WIDTH-1:0] data2wr_i;
input wire [SRAM_WIDTH-1:0] data3wr_i;
input wire [SRAM_WIDTH-1:0] data4wr_i;
input wire [SRAM_WIDTH-1:0] data5wr_i;
input wire [SRAM_WIDTH-1:0] data6wr_i;
input wire [SRAM_WIDTH-1:0] data7wr_i;
output wire [SRAM_WIDTH-1:0] data0_o;
output wire [SRAM_WIDTH-1:0] data1_o;
output wire [SRAM_WIDTH-1:0] data2_o;
output wire [SRAM_WIDTH-1:0] data3_o;
/* The SRAM reg */
reg [SRAM_WIDTH-1:0] sram [SRAM_DEPTH-1:0];
integer i;
/* Read operation */
assign data0_o = sram[addr0_i];
assign data1_o = sram[addr1_i];
assign data2_o = sram[addr2_i];
assign data3_o = sram[addr3_i];
/* Write operation */
always @(posedge clk)
begin
if(reset == 1'b1)
begin
for(i=0; i<SRAM_DEPTH; i=i+1)
begin
sram[i] <= 0;
end
end
else
begin
if(we0_i == 1'b1)
begin
sram[addr0wr_i] <= data0wr_i;
end
if(we1_i == 1'b1)
begin
sram[addr1wr_i] <= data1wr_i;
end
if(we2_i == 1'b1)
begin
sram[addr2wr_i] <= data2wr_i;
end
if(we3_i == 1'b1)
begin
sram[addr3wr_i] <= data3wr_i;
end
if(we4_i == 1'b1)
begin
sram[addr4wr_i] <= data4wr_i;
end
if(we5_i == 1'b1)
begin
sram[addr5wr_i] <= data5wr_i;
end
if(we6_i == 1'b1)
begin
sram[addr6wr_i] <= data6wr_i;
end
if(we7_i == 1'b1)
begin
sram[addr7wr_i] <= data7wr_i;
end
end
end
endmodule
| 6.592425 |
module tsyncram_4x32 (
CLK,
CLKN,
ADDR,
WEN,
WE,
REN,
RE,
CSN,
CSB,
DATA_IN,
DATA_OUT
);
input CLK;
input CLKN;
input [1:0] ADDR;
input WEN;
input WE;
input REN;
input RE;
input CSN;
input CSB;
input [31:0] DATA_IN;
output [31:0] DATA_OUT;
SYHD130_8X32X1CM2 SRAM (
.A0(ADDR[0]),
.A1(ADDR[1]),
.A2(1'b0),
.CK(CLK),
.CSB(1'b0),
.WEB(WEN),
.DI0 (DATA_IN[0]),
.DI1 (DATA_IN[1]),
.DI2 (DATA_IN[2]),
.DI3 (DATA_IN[3]),
.DI4 (DATA_IN[4]),
.DI5 (DATA_IN[5]),
.DI6 (DATA_IN[6]),
.DI7 (DATA_IN[7]),
.DI8 (DATA_IN[8]),
.DI9 (DATA_IN[9]),
.DI10(DATA_IN[10]),
.DI11(DATA_IN[11]),
.DI12(DATA_IN[12]),
.DI13(DATA_IN[13]),
.DI14(DATA_IN[14]),
.DI15(DATA_IN[15]),
.DI16(DATA_IN[16]),
.DI17(DATA_IN[17]),
.DI18(DATA_IN[18]),
.DI19(DATA_IN[19]),
.DI20(DATA_IN[20]),
.DI21(DATA_IN[21]),
.DI22(DATA_IN[22]),
.DI23(DATA_IN[23]),
.DI24(DATA_IN[24]),
.DI25(DATA_IN[25]),
.DI26(DATA_IN[26]),
.DI27(DATA_IN[27]),
.DI28(DATA_IN[28]),
.DI29(DATA_IN[29]),
.DI30(DATA_IN[30]),
.DI31(DATA_IN[31]),
.DO0 (DATA_OUT[0]),
.DO1 (DATA_OUT[1]),
.DO2 (DATA_OUT[2]),
.DO3 (DATA_OUT[3]),
.DO4 (DATA_OUT[4]),
.DO5 (DATA_OUT[5]),
.DO6 (DATA_OUT[6]),
.DO7 (DATA_OUT[7]),
.DO8 (DATA_OUT[8]),
.DO9 (DATA_OUT[9]),
.DO10(DATA_OUT[10]),
.DO11(DATA_OUT[11]),
.DO12(DATA_OUT[12]),
.DO13(DATA_OUT[13]),
.DO14(DATA_OUT[14]),
.DO15(DATA_OUT[15]),
.DO16(DATA_OUT[16]),
.DO17(DATA_OUT[17]),
.DO18(DATA_OUT[18]),
.DO19(DATA_OUT[19]),
.DO20(DATA_OUT[20]),
.DO21(DATA_OUT[21]),
.DO22(DATA_OUT[22]),
.DO23(DATA_OUT[23]),
.DO24(DATA_OUT[24]),
.DO25(DATA_OUT[25]),
.DO26(DATA_OUT[26]),
.DO27(DATA_OUT[27]),
.DO28(DATA_OUT[28]),
.DO29(DATA_OUT[29]),
.DO30(DATA_OUT[30]),
.DO31(DATA_OUT[31])
);
endmodule
| 6.639607 |
module sram_512w_16b (
Q,
CLK,
CEN,
WEN,
A,
D,
EMA,
EMAW,
EMAS,
TEN,
BEN,
RET1N,
STOV
);
output reg [15:0] Q;
input CLK;
input CEN;
input WEN;
input [8:0] A;
input [15:0] D;
input [2:0] EMA;
input [1:0] EMAW;
input EMAS;
input TEN;
input BEN;
input RET1N;
input STOV;
reg [15:0] data_array[0:511];
always @(posedge CLK) begin
// Use all the unused wires (note at least one of them must be nonzero!)
if (|{EMA, EMAW, EMAS, TEN, BEN, RET1N, STOV}) begin
if (CEN == 1'b0) begin // ACTIVE LOW!!
Q = data_array[A];
if (WEN == 1'b0) data_array[A] = D; // ACTIVE LOW!!
end
end
end
endmodule
| 7.552978 |
module sram_64x512b (
input clk,
input csb, //chip enable
input wsb, //write enable
input [511:0] wdata, //write data
input [5:0] waddr, //write address
input [5:0] raddr, //read address
output reg [511:0] rdata //read data
);
localparam WEIGHT_WIDTH = 16;
localparam WEIGHT_PIXEL_NUM = 32;
/*
/////////////////////
index 0~19 : conv1_w(20)
index 20 : conv1_b(1)
index 21 ~ 1020 conv2_w(1000)
index 1021 ~ 1022 conv2_b(2)
index 1100 ~ 17099 fc1_w(16000)
index 17100 ~ 17299 score_w(200)
/////////////////////
*/
reg [WEIGHT_PIXEL_NUM*WEIGHT_WIDTH-1:0] mem[0:64-1];
reg [511:0] _rdata;
always @(posedge clk) if (~csb && ~wsb) mem[waddr] <= wdata;
always @(posedge clk) if (~csb) _rdata <= mem[raddr];
always @* begin
rdata = #(`cycle_period * 0.2) _rdata;
//rdata = _rdata;
end
task load_w(input integer index, input [511:0] weight_input);
mem[index] = weight_input;
endtask
task dis();
integer i;
for (i = 21; i < 41; i = i + 1) begin
$display("%b", mem[i]);
end
endtask
endmodule
| 7.039658 |
module sram_64x64 (
input clk_i,
input rst_i,
input wr_en_i,
input rd_en_i,
input [ 5:0] addr_i,
input [63:0] wdata_i,
output [63:0] rdata_o
);
reg [63:0] bram [63:0];
integer i;
reg [63:0] data;
//add implementation code here
always @(posedge clk_i or negedge rst_i) begin
if (~rst_i) begin
for (i = 0; i <= 63; i = i + 1) //reset, ֲ
bram[i] <= 64'b0;
end else if (wr_en_i) begin
bram[addr_i] <= wdata_i;
end else if (rd_en_i) begin
data <= bram[addr_i];
end
// else begin
// data <= 64'bz; //дЧʱΪ̬Ӵ˾䣬ʱ
//end
end
assign rdata_o = data;
endmodule
| 7.551375 |
module sram_64x8b #( //for bias
parameter BIAS_PER_ADDR = 1,
parameter BW_PER_PARAM = 8
) (
input clk,
input csb, //chip enable
input wsb, //write enable
input [BIAS_PER_ADDR*BW_PER_PARAM-1:0] wdata, //write data
input [5:0] waddr, //write address
input [5:0] raddr, //read address
output reg [BIAS_PER_ADDR*BW_PER_PARAM-1:0] rdata
);
/*
Data location
/////////////////////
addr 0~3: conv1 bias(4)
addr 4~15: conv2 bias(12)
addr 16~63: conv3 bias(48)
/////////////////////
*/
reg [BIAS_PER_ADDR*BW_PER_PARAM-1:0] mem[0:63];
reg [BIAS_PER_ADDR*BW_PER_PARAM-1:0] _rdata;
always @(posedge clk) begin
if (~csb && ~wsb) mem[waddr] <= wdata;
end
always @(posedge clk) begin
if (~csb) _rdata <= mem[raddr];
end
always @* begin
rdata = #(1) _rdata;
end
task load_param(input integer index, input [BIAS_PER_ADDR*BW_PER_PARAM-1:0] param_input);
mem[index] = param_input;
endtask
endmodule
| 6.793474 |
module SRAM_8Kx32 (
output [31:0] Q,
input [31:0] D,
input [14:0] A,
input clk,
input cen,
input [3:0] wen
);
reg [31:0] RAM[4*1024-1:0];
reg [31:0] DATA;
wire [31:0] data = RAM[A];
assign Q = DATA;
always @(posedge clk) DATA <= data;
always @(posedge clk)
if (cen) begin
if (wen[0]) RAM[A] <= {data[32:8], D[7:0]};
if (wen[1]) RAM[A] <= {data[32:16], D[15:8], data[7:0]};
if (wen[2]) RAM[A] <= {data[32:24], D[23:16], data[15:0]};
if (wen[3]) RAM[A] <= {D[31:24], data[23:0]};
RAM[A] <= D;
end
endmodule
| 7.190322 |
module implements SRAM.
# Author: FabGen
*******************************************************************************/
`timescale 1ns/100ps
module SRAM_8R4W_PIPE(
clk,
reset,
addr0_i,
addr1_i,
addr2_i,
addr3_i,
addr4_i,
addr5_i,
addr6_i,
addr7_i,
addr0wr_i,
addr1wr_i,
addr2wr_i,
addr3wr_i,
we0_i,
we1_i,
we2_i,
we3_i,
data0wr_i,
data1wr_i,
data2wr_i,
data3wr_i,
decoded_addr0_o,
decoded_addr1_o,
decoded_addr2_o,
decoded_addr3_o,
decoded_addr4_o,
decoded_addr5_o,
decoded_addr6_o,
decoded_addr7_o,
decoded_addr0wr_o,
we0_o,
decoded_addr1wr_o,
we1_o,
decoded_addr2wr_o,
we2_o,
decoded_addr3wr_o,
we3_o,
data0_o,
data1_o,
data2_o,
data3_o,
data4_o,
data5_o,
data6_o,
data7_o
);
/* Parameters */
parameter SRAM_DEPTH = 16;
parameter SRAM_INDEX = 4;
parameter SRAM_WIDTH = 8;
input clk;
input reset;
/* The SRAM reg */
input [SRAM_INDEX-1:0] addr0_i;
input [SRAM_INDEX-1:0] addr1_i;
input [SRAM_INDEX-1:0] addr2_i;
input [SRAM_INDEX-1:0] addr3_i;
input [SRAM_INDEX-1:0] addr4_i;
input [SRAM_INDEX-1:0] addr5_i;
input [SRAM_INDEX-1:0] addr6_i;
input [SRAM_INDEX-1:0] addr7_i;
input [SRAM_INDEX-1:0] addr0wr_i;
input [SRAM_INDEX-1:0] addr1wr_i;
input [SRAM_INDEX-1:0] addr2wr_i;
input [SRAM_INDEX-1:0] addr3wr_i;
input we0_i;
input we1_i;
input we2_i;
input we3_i;
input [SRAM_WIDTH-1:0] data0wr_i;
input [SRAM_WIDTH-1:0] data1wr_i;
input [SRAM_WIDTH-1:0] data2wr_i;
input [SRAM_WIDTH-1:0] data3wr_i;
output [SRAM_DEPTH-1:0] decoded_addr0_o;
output [SRAM_DEPTH-1:0] decoded_addr1_o;
output [SRAM_DEPTH-1:0] decoded_addr2_o;
output [SRAM_DEPTH-1:0] decoded_addr3_o;
output [SRAM_DEPTH-1:0] decoded_addr4_o;
output [SRAM_DEPTH-1:0] decoded_addr5_o;
output [SRAM_DEPTH-1:0] decoded_addr6_o;
output [SRAM_DEPTH-1:0] decoded_addr7_o;
output [SRAM_DEPTH-1:0] decoded_addr0wr_o;
output we0_o;
output [SRAM_DEPTH-1:0] decoded_addr1wr_o;
output we1_o;
output [SRAM_DEPTH-1:0] decoded_addr2wr_o;
output we2_o;
output [SRAM_DEPTH-1:0] decoded_addr3wr_o;
output we3_o;
output [SRAM_WIDTH-1:0] data0_o;
output [SRAM_WIDTH-1:0] data1_o;
output [SRAM_WIDTH-1:0] data2_o;
output [SRAM_WIDTH-1:0] data3_o;
output [SRAM_WIDTH-1:0] data4_o;
output [SRAM_WIDTH-1:0] data5_o;
output [SRAM_WIDTH-1:0] data6_o;
output [SRAM_WIDTH-1:0] data7_o;
reg [SRAM_WIDTH-1:0] sram [SRAM_DEPTH-1:0];
assign data0_o = sram[addr0_i];
assign decoded_addr0_o = 1 << addr0_i;
assign data1_o = sram[addr1_i];
assign decoded_addr1_o = 1 << addr1_i;
assign data2_o = sram[addr2_i];
assign decoded_addr2_o = 1 << addr2_i;
assign data3_o = sram[addr3_i];
assign decoded_addr3_o = 1 << addr3_i;
assign data4_o = sram[addr4_i];
assign decoded_addr4_o = 1 << addr4_i;
assign data5_o = sram[addr5_i];
assign decoded_addr5_o = 1 << addr5_i;
assign data6_o = sram[addr6_i];
assign decoded_addr6_o = 1 << addr6_i;
assign data7_o = sram[addr7_i];
assign decoded_addr7_o = 1 << addr7_i;
assign decoded_addr0wr_o = we0_i << addr0wr_i;
assign we0_o = we0_i;
assign decoded_addr1wr_o = we1_i << addr1wr_i;
assign we1_o = we1_i;
assign decoded_addr2wr_o = we2_i << addr2wr_i;
assign we2_o = we2_i;
assign decoded_addr3wr_o = we3_i << addr3wr_i;
assign we3_o = we3_i;
integer i,j;
/* Write operation */
always @(posedge clk)
begin
if(reset == 1'b1)
begin
for(i=`SIZE_RMT; i<SRAM_DEPTH; i=i+1)
begin
sram[i] <= 0;
end
end
else
begin
if(we0_i == 1'b1)
begin
sram[addr0wr_i] <= data0wr_i;
end
if(we1_i == 1'b1)
begin
sram[addr1wr_i] <= data1wr_i;
end
if(we2_i == 1'b1)
begin
sram[addr2wr_i] <= data2wr_i;
end
if(we3_i == 1'b1)
begin
sram[addr3wr_i] <= data3wr_i;
end
end
end
endmodule
| 6.592425 |
module implements SRAM.
# Author: FabGen
*******************************************************************************/
`timescale 1ns/100ps
module SRAM_8R4W_RMT(
clk,
reset,
addr0_i,
addr1_i,
addr2_i,
addr3_i,
addr4_i,
addr5_i,
addr6_i,
addr7_i,
addr0wr_i,
addr1wr_i,
addr2wr_i,
addr3wr_i,
we0_i,
we1_i,
we2_i,
we3_i,
data0wr_i,
data1wr_i,
data2wr_i,
data3wr_i,
data0_o,
data1_o,
data2_o,
data3_o,
data4_o,
data5_o,
data6_o,
data7_o
);
/* Parameters */
parameter SRAM_DEPTH = 16;
parameter SRAM_INDEX = 4;
parameter SRAM_WIDTH = 8;
/* Input and output wires and regs */
input wire clk;
input wire reset;
input wire [SRAM_INDEX-1:0] addr0_i;
input wire [SRAM_INDEX-1:0] addr1_i;
input wire [SRAM_INDEX-1:0] addr2_i;
input wire [SRAM_INDEX-1:0] addr3_i;
input wire [SRAM_INDEX-1:0] addr4_i;
input wire [SRAM_INDEX-1:0] addr5_i;
input wire [SRAM_INDEX-1:0] addr6_i;
input wire [SRAM_INDEX-1:0] addr7_i;
input wire [SRAM_INDEX-1:0] addr0wr_i;
input wire [SRAM_INDEX-1:0] addr1wr_i;
input wire [SRAM_INDEX-1:0] addr2wr_i;
input wire [SRAM_INDEX-1:0] addr3wr_i;
input wire we0_i;
input wire we1_i;
input wire we2_i;
input wire we3_i;
input wire [SRAM_WIDTH-1:0] data0wr_i;
input wire [SRAM_WIDTH-1:0] data1wr_i;
input wire [SRAM_WIDTH-1:0] data2wr_i;
input wire [SRAM_WIDTH-1:0] data3wr_i;
output wire [SRAM_WIDTH-1:0] data0_o;
output wire [SRAM_WIDTH-1:0] data1_o;
output wire [SRAM_WIDTH-1:0] data2_o;
output wire [SRAM_WIDTH-1:0] data3_o;
output wire [SRAM_WIDTH-1:0] data4_o;
output wire [SRAM_WIDTH-1:0] data5_o;
output wire [SRAM_WIDTH-1:0] data6_o;
output wire [SRAM_WIDTH-1:0] data7_o;
/* The SRAM reg */
reg [SRAM_WIDTH-1:0] sram [SRAM_DEPTH-1:0];
integer i;
/* Read operation */
assign data0_o = sram[addr0_i];
assign data1_o = sram[addr1_i];
assign data2_o = sram[addr2_i];
assign data3_o = sram[addr3_i];
assign data4_o = sram[addr4_i];
assign data5_o = sram[addr5_i];
assign data6_o = sram[addr6_i];
assign data7_o = sram[addr7_i];
/* Write operation */
always @(posedge clk)
begin
if(reset == 1'b1)
begin
for(i=0; i<SRAM_DEPTH; i=i+1)
begin
sram[i] <= i;
end
end
else
begin
if(we0_i == 1'b1)
begin
sram[addr0wr_i] <= data0wr_i;
end
if(we1_i == 1'b1)
begin
sram[addr1wr_i] <= data1wr_i;
end
if(we2_i == 1'b1)
begin
sram[addr2wr_i] <= data2wr_i;
end
if(we3_i == 1'b1)
begin
sram[addr3wr_i] <= data3wr_i;
end
end
end
endmodule
| 6.592425 |
module SRAM_AddressMapping (
input [31:0] ALU_result,
output [17:0] address
);
wire [31:0] address_base;
assign address_base = (ALU_result - 1024);
assign address = address_base[18:1];
endmodule
| 6.94907 |
module sram_addr_decoder (
clk,
lineNumber,
spriteNumber,
address
);
input clk;
input [3:0] lineNumber;
input [4:0] spriteNumber;
output [19:0] address;
assign address = (20'd16 * spriteNumber) + lineNumber;
endmodule
| 6.652576 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_announce
#(parameter DATA_WIDTH = 8, ADDR_WIDTH = 16, RAM_SIZE = 65536)
(input clk, input we, input en,
input [ADDR_WIDTH-1 : 0] addr,
input [DATA_WIDTH-1 : 0] data_i,
output reg [DATA_WIDTH-1 : 0] data_o);
// Declareation of the memory cells
(* ram_style = "distributed" *)reg [DATA_WIDTH-1 : 0] RAM [RAM_SIZE - 1:0];
integer idx;
// ------------------------------------
// SRAM cell initialization
// ------------------------------------
// Initialize the sram cells with the values defined in "image.dat."
initial begin
$readmemh("announce.mem", RAM);
end
// ------------------------------------
// SRAM read operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
data_o <= data_i;
else
data_o <= RAM[addr];
end
// ------------------------------------
// SRAM write operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
RAM[addr] <= data_i;
end
endmodule
| 6.896868 |
module sram_async #(
parameter W_DATA = 16, // Must be power of 2, >= 8
parameter DEPTH = 1 << 18, // == 0.5 MiB for 16 bit interface
parameter PRELOAD_FILE = "",
parameter W_ADDR = $clog2(DEPTH), // Let this default
parameter W_BYTES = W_DATA / 8 // Let this default
) (
input wire [W_ADDR-1:0] addr,
inout wire [W_DATA-1:0] dq,
input wire ce_n,
input wire oe_n,
input wire we_n,
input wire [W_BYTES-1:0] ben_n
);
reg [W_DATA-1:0] dq_r;
assign dq = dq_r;
reg [W_DATA-1:0] mem[0:DEPTH-1];
initial begin : preload
`ifdef SIM
integer n;
for (n = 0; n < DEPTH; n = n + 1) mem[n] = {W_DATA{1'b0}};
`endif
if (PRELOAD_FILE != "") $readmemh(PRELOAD_FILE, mem);
end
always @(*) begin : readport
integer i;
for (i = 0; i < W_BYTES; i = i + 1) begin
dq_r[i*8+:8] = !ce_n && !oe_n && we_n && !ben_n[i] ? mem[addr][i*8+:8] : 8'hz;
end
end
always @(negedge we_n) begin : writeport
integer i;
for (i = 0; i < W_BYTES; i = i + 1) begin
if (!ce_n && !ben_n[i]) mem[addr][i*8+:8] <= dq[i*8+:8];
end
end
endmodule
| 7.470036 |
module SRAM_async3 #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 10,
DELAY = 25,
DATA_HEX_FILE = "dump.hex"
) (
input wire [ADDR_WIDTH-1:0] ADDR,
input wire CE1n,
input wire CE2,
input wire OEn,
input wire WEn,
inout wire [DATA_WIDTH-1:0] DATA
);
reg [DATA_WIDTH-1:0] mem[0:(2**ADDR_WIDTH)-1];
reg [DATA_WIDTH-1:0] data_out;
wire ce;
initial begin
$readmemh(DATA_HEX_FILE, mem);
end
assign ce = ~CE1n & CE2;
always @(*) begin : mem_write
if (ce && !WEn) begin
mem[ADDR] = DATA;
end
end
always @(*) begin : mem_read
if (ce && WEn && !OEn) begin
data_out = mem[ADDR];
end
end
assign #DELAY DATA = (ce && WEn && !OEn) ? data_out : 8'hzz;
//assign #DELAY DATA = (ce && !OEn) ? data_out : 8'hzz;
endmodule
| 9.155359 |
module SRAM_async3 #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 10,
DELAY = 25,
DATA_HEX_FILE = "dump.hex"
) (
input wire [ADDR_WIDTH-1:0] ADDR,
input wire CE1n,
input wire CE2,
input wire OEn,
input wire WEn,
inout wire [DATA_WIDTH-1:0] DATA
);
reg [DATA_WIDTH-1:0] mem[0:(2**ADDR_WIDTH)-1];
reg [DATA_WIDTH-1:0] data_out;
wire ce;
initial begin
$readmemh(DATA_HEX_FILE, mem);
end
assign ce = ~CE1n & CE2;
always @(*) begin : mem_write
if (ce && !WEn) begin
mem[ADDR] = DATA;
end
end
always @(*) begin : mem_read
if (ce && WEn && !OEn) begin
data_out = mem[ADDR];
end
end
assign #DELAY DATA = (ce && WEn && !OEn) ? data_out : 8'hzz;
//assign #DELAY DATA = (ce && !OEn) ? data_out : 8'hzz;
endmodule
| 9.155359 |
module SRAM_async_alwaysdout #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 10,
DELAY = 25,
DATA_HEX_FILE = "dump.hex"
) (
input wire [ADDR_WIDTH-1:0] ADDR,
input wire CE1n,
input wire CE2,
input wire OEn,
input wire WEn,
inout wire [DATA_WIDTH-1:0] DATA
);
reg [DATA_WIDTH-1:0] mem[0:(2**ADDR_WIDTH)-1];
reg [DATA_WIDTH-1:0] data_out;
wire ce;
initial begin
$readmemh(DATA_HEX_FILE, mem);
end
assign ce = ~CE1n & CE2;
always @(*) begin : mem_write
if (ce && !WEn) begin
mem[ADDR] = DATA;
end
end
always @(*) begin : mem_read
if (ce && WEn && !OEn) begin
data_out = mem[ADDR];
end
end
//assign #DELAY DATA = (ce && WEn && !OEn) ? data_out : 8'hzz;
assign #DELAY DATA = (ce && !OEn) ? data_out : 8'hzz;
endmodule
| 9.276724 |
module: sram_axi_adapter
//
// Module adapted from The picoRV32 AXI adapter to allow
// back to back read/write address channel requests and bus fault
// propagation.
//
module sram_axi_adapter (
input g_clk ,
input g_resetn ,
// AXI4-lite master memory interface
output mem_axi_awvalid ,
input mem_axi_awready ,
output [31:0] mem_axi_awaddr ,
output [ 2:0] mem_axi_awprot ,
output mem_axi_wvalid ,
input mem_axi_wready ,
output [31:0] mem_axi_wdata ,
output [ 3:0] mem_axi_wstrb ,
input mem_axi_bvalid ,
output mem_axi_bready ,
output mem_axi_arvalid ,
input mem_axi_arready ,
output [31:0] mem_axi_araddr ,
output [ 2:0] mem_axi_arprot ,
input mem_axi_rvalid ,
output mem_axi_rready ,
input [31:0] mem_axi_rdata ,
input mem_instr , // Is this an instruction fetch?
input mem_cen ,
output mem_stall ,
output mem_error ,
input [31:0] mem_addr ,
input [31:0] mem_wdata ,
input [ 3:0] mem_wstrb ,
output [31:0] mem_rdata
);
reg ack_awvalid;
reg ack_arvalid;
reg ack_wvalid;
reg xfer_done;
assign mem_axi_awvalid = mem_cen && |mem_wstrb;
assign mem_axi_awaddr = mem_addr;
assign mem_axi_awprot = 0;
assign mem_axi_arvalid = mem_cen && !mem_wstrb;
assign mem_axi_araddr = mem_addr;
assign mem_axi_arprot = mem_instr ? 3'b100 : 3'b000;
assign mem_axi_wvalid = mem_cen && |mem_wstrb && !ack_wvalid;
assign mem_axi_wdata = mem_wdata;
assign mem_axi_wstrb = mem_wstrb;
wire mem_ready = mem_axi_bvalid || mem_axi_rvalid;
assign mem_stall = !mem_ready;
assign mem_axi_bready = mem_cen && |mem_wstrb;
// Always accept read responses immediately.
assign mem_axi_rready = 1'b1;
assign mem_rdata = mem_axi_rdata;
// TODO: implement this.
assign mem_error = 1'b0;
always @(posedge g_clk) begin
if (!g_resetn) begin
ack_awvalid <= 0;
end else begin
xfer_done <= mem_cen && mem_ready;
if (mem_axi_awready && mem_axi_awvalid)
ack_awvalid <= 1;
if (mem_axi_arready && mem_axi_arvalid)
ack_arvalid <= 1;
if (mem_axi_wready && mem_axi_wvalid)
ack_wvalid <= 1;
if (xfer_done || !mem_cen) begin
ack_awvalid <= 0;
ack_arvalid <= 0;
ack_wvalid <= 0;
end
end
end
endmodule
| 7.108475 |
module SRAM_1R1W (
addr0_i,
addrWr_i,
we_i,
data_i,
clk,
reset,
data0_o
);
parameter SRAM_DEPTH = 64;
parameter SRAM_INDEX = 6;
parameter SRAM_WIDTH = 32;
input [SRAM_INDEX-1:0] addr0_i;
input [SRAM_INDEX-1:0] addrWr_i;
input we_i;
input clk;
input reset;
input [SRAM_WIDTH-1:0] data_i;
output [SRAM_WIDTH-1:0] data0_o;
/* Defining register file for SRAM */
reg [SRAM_WIDTH-1:0] sram[SRAM_DEPTH-1:0];
integer i;
assign data0_o = sram[addr0_i];
always @(posedge clk) begin
if (reset) begin
for (i = 0; i < SRAM_DEPTH; i = i + 1) sram[i] <= 0;
end else begin
if (we_i) sram[addrWr_i] <= data_i;
end
end
endmodule
| 7.248883 |
module SRAM_1R1W_i (
addr0_i,
addrWr_i,
we_i,
data_i,
clk,
reset,
data0_o
);
parameter SRAM_DEPTH = 64;
parameter SRAM_INDEX = 6;
parameter SRAM_WIDTH = 32;
input [SRAM_INDEX-1:0] addr0_i;
input [SRAM_INDEX-1:0] addrWr_i;
input we_i;
input clk;
input reset;
input [SRAM_WIDTH-1:0] data_i;
output [SRAM_WIDTH-1:0] data0_o;
/* Defining register file for SRAM */
reg [SRAM_WIDTH-1:0] sram[SRAM_DEPTH-1:0];
integer i;
assign data0_o = sram[addr0_i];
always @(posedge clk) begin
if (we_i) sram[addrWr_i] <= data_i;
end
endmodule
| 7.480097 |
module SRAM_2R1W_HY (
re0_i,
addr0_i,
re1_i,
addr1_i,
addrWr_i,
we_i,
data_i,
clk,
reset,
data0_o,
data1_o
);
parameter SRAM_DEPTH = 64;
parameter SRAM_INDEX = 6;
parameter SRAM_WIDTH = 2;
parameter SRAM_FETCH_BANDWIDTH = 4;
parameter SRAM_FETCH_BANDWIDTH_LOG = 2;
input re0_i;
input [SRAM_INDEX-SRAM_FETCH_BANDWIDTH_LOG-1:0] addr0_i;
input re1_i;
input [SRAM_INDEX-1:0] addr1_i;
input [SRAM_INDEX-1:0] addrWr_i;
input we_i;
input clk;
input reset;
input [SRAM_WIDTH-1:0] data_i;
output [SRAM_FETCH_BANDWIDTH*SRAM_WIDTH-1:0] data0_o;
output [SRAM_WIDTH-1:0] data1_o;
reg [SRAM_INDEX-1:0] full_addr0;
reg [SRAM_FETCH_BANDWIDTH*SRAM_WIDTH-1:0] data0;
/* Defining register file for SRAM */
reg [SRAM_WIDTH-1:0] sram[SRAM_DEPTH-1:0];
integer i;
integer j;
integer k;
always @(*) begin
data0 = 0;
full_addr0 = addr0_i << SRAM_FETCH_BANDWIDTH_LOG;
for (j = 0; j < SRAM_FETCH_BANDWIDTH; j = j + 1) begin
for (k = 0; k < SRAM_WIDTH; k = k + 1) begin
data0[SRAM_WIDTH*(SRAM_FETCH_BANDWIDTH-j)-1-k] = sram[full_addr0+j][SRAM_WIDTH-k-1];
end
end
end
assign data0_o = re0_i ? data0 : 0;
assign data1_o = re1_i ? sram[addr1_i] : 0;
always @(posedge clk) begin
if (reset) begin
for (i = 0; i < SRAM_DEPTH; i = i + 1) sram[i] <= 2'b10;
end else if (we_i) sram[addrWr_i] <= data_i;
end
endmodule
| 7.643707 |
module SRAM_1R1W_2stage_pipelined (
addr0_i,
re_i,
addrWr_i,
we_i,
data_i,
stall_i,
flush_i,
clk,
reset,
data0_o
);
parameter SRAM_DEPTH = 64;
parameter SRAM_INDEX = 6;
parameter SRAM_WIDTH = 32;
input [SRAM_INDEX-1:0] addr0_i;
input re_i;
input [SRAM_INDEX-1:0] addrWr_i;
input we_i;
input stall_i;
input flush_i;
input clk;
input reset;
input [SRAM_WIDTH-1:0] data_i;
output [SRAM_WIDTH-1:0] data0_o;
/* Defining register file for SRAM */
reg [SRAM_WIDTH-1:0] sram[SRAM_DEPTH-1:0];
/* Defining register for Pipeling read and write */
reg [SRAM_INDEX-1:0] addr0;
reg re;
reg [SRAM_INDEX-1:0] addrWr;
reg we;
reg [SRAM_WIDTH-1:0] data;
integer i;
assign data0_o = re ? sram[addr0] : 0;
always @(posedge clk) begin
if (reset || flush_i) begin
addr0 <= 0;
re <= 0;
end else if (~stall_i) begin
addr0 <= addr0_i;
re <= re_i;
end
end
always @(posedge clk) begin
if (reset) begin
addrWr <= 0;
we <= 0;
data <= 0;
end else begin
addrWr <= addrWr_i;
we <= we_i;
data <= data_i;
end
end
always @(posedge clk) begin
if (reset) begin
for (i = 0; i < SRAM_DEPTH; i = i + 1) sram[i] <= 0;
end else begin
if (we) sram[addrWr] <= data;
end
end
endmodule
| 8.128236 |
module SRAM_1R1W_2stage_pipelined_fifo (
addr0_i,
re_i,
addrWr_i,
we_i,
data_i,
stall_i,
flush_i,
clk,
reset,
data0_o
);
parameter SRAM_DEPTH = 64;
parameter SRAM_INDEX = 6;
parameter SRAM_WIDTH = 8;
input [SRAM_INDEX-1:0] addr0_i;
input re_i;
input [SRAM_INDEX-1:0] addrWr_i;
input we_i;
input stall_i;
input flush_i;
input clk;
input reset;
input [SRAM_WIDTH-1:0] data_i;
output [SRAM_WIDTH-1:0] data0_o;
/* Defining register file for SRAM */
reg [SRAM_WIDTH-1:0] sram[SRAM_DEPTH-1:0];
/* Defining register for Pipeling read and write */
reg [SRAM_INDEX-1:0] addr0;
reg re;
reg [SRAM_INDEX-1:0] addrWr;
reg we;
reg [SRAM_WIDTH-1:0] data;
integer i;
assign data0_o = re ? sram[addr0] : 0;
always @(posedge clk) begin
if (reset || flush_i) begin
addr0 <= 0;
re <= 0;
end else if (~stall_i) begin
addr0 <= addr0_i;
re <= re_i;
end
end
always @(posedge clk) begin
if (reset) begin
addrWr <= 0;
we <= 0;
data <= 0;
end else begin
addrWr <= addrWr_i;
we <= we_i;
data <= data_i;
end
end
always @(posedge clk) begin
if (reset) begin
for (i = 0; i < SRAM_DEPTH; i = i + 1) sram[i] <= 8'b11100100;
end else begin
if (we) sram[addrWr] <= data;
end
end
endmodule
| 8.128236 |
module SRAM_2R1W_2stage_pipelined (
addr0_i,
re0_i,
addr1_i,
re1_i,
addrWr_i,
we_i,
data_i,
stall_i,
flush_i,
clk,
reset,
data0_o,
data1_o
);
parameter SRAM_DEPTH = 64;
parameter SRAM_INDEX = 6;
parameter SRAM_WIDTH = 8;
input [SRAM_INDEX-1:0] addr0_i;
input [SRAM_INDEX-1:0] addr1_i;
input re0_i;
input re1_i;
input [SRAM_INDEX-1:0] addrWr_i;
input we_i;
input stall_i;
input flush_i;
input clk;
input reset;
input [SRAM_WIDTH-1:0] data_i;
output [SRAM_WIDTH-1:0] data0_o;
output [SRAM_WIDTH-1:0] data1_o;
/* Defining register file for SRAM */
reg [SRAM_WIDTH-1:0] sram[SRAM_DEPTH-1:0];
/* Defining register for Pipeling read and write */
reg [SRAM_INDEX-1:0] addr0;
reg [SRAM_INDEX-1:0] addr1;
reg re0;
reg re1;
reg [SRAM_INDEX-1:0] addrWr;
reg we;
reg [SRAM_WIDTH-1:0] data;
integer i;
integer j;
assign data0_o = re0 ? sram[addr0] : 0;
assign data1_o = re1 ? sram[addr1] : 0;
always @(posedge clk) begin
if (reset || flush_i) begin
addr0 <= 0;
re0 <= 0;
end else if (~stall_i) begin
addr0 <= addr0_i;
re0 <= re0_i;
end
end
always @(posedge clk) begin
if (reset) begin
addr1 <= 0;
re1 <= 0;
addrWr <= 0;
we <= 0;
data <= 0;
end else begin
addr1 <= addr1_i;
re1 <= re1_i;
addrWr <= addrWr_i;
we <= we_i;
data <= data_i;
end
end
always @(posedge clk) begin
if (reset) begin
for (i = 0; i < SRAM_DEPTH; i = i + 1) begin
for (j = 0; j < SRAM_WIDTH; j = j + 1) begin
if (j % 2 == 0) sram[i][j] <= 1'b0;
else sram[i][j] <= 1'b1;
end
end
end else begin
if (we) sram[addrWr] <= data;
end
end
endmodule
| 8.010394 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_ball
#(parameter DATA_WIDTH = 8, ADDR_WIDTH = 16, RAM_SIZE = 65536)
(input clk, input we, input en,
input [ADDR_WIDTH-1 : 0] addr,
input [DATA_WIDTH-1 : 0] data_i,
output reg [DATA_WIDTH-1 : 0] data_o);
// Declareation of the memory cells
(* ram_style = "block" *) reg [DATA_WIDTH-1 : 0] RAM [RAM_SIZE - 1:0];
integer idx;
// ------------------------------------
// SRAM cell initialization
// ------------------------------------
// Initialize the sram cells with the values defined in "image.dat."
initial begin
$readmemh("ball.mem", RAM);
end
// ------------------------------------
// SRAM read operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
data_o <= data_i;
else
data_o <= RAM[addr];
end
// ------------------------------------
// SRAM write operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
RAM[addr] <= data_i;
end
endmodule
| 6.896868 |
module sram (
clk_clk,
reset_reset,
sram_DQ,
sram_ADDR,
sram_LB_N,
sram_UB_N,
sram_CE_N,
sram_OE_N,
sram_WE_N,
sram_io_address,
sram_io_byteenable,
sram_io_read,
sram_io_write,
sram_io_writedata,
sram_io_readdata,
sram_io_readdatavalid
);
input clk_clk;
input reset_reset;
inout [15:0] sram_DQ;
output [19:0] sram_ADDR;
output sram_LB_N;
output sram_UB_N;
output sram_CE_N;
output sram_OE_N;
output sram_WE_N;
input [19:0] sram_io_address;
input [1:0] sram_io_byteenable;
input sram_io_read;
input sram_io_write;
input [15:0] sram_io_writedata;
output [15:0] sram_io_readdata;
output sram_io_readdatavalid;
endmodule
| 6.9173 |
module cde_sram_be #(
parameter ADDR = 10,
WIDTH = 8,
WORDS = 1024,
WRITETHRU = 0,
DEFAULT = {WIDTH{1'b1}},
INIT_FILE = "NONE",
INSTANCE_NAME = "U1"
) (
input wire clk,
input wire cs,
input wire rd,
input wire wr,
input wire be,
input wire [ ADDR-1 : 0] addr,
input wire [WIDTH-1 : 0] wdata,
output reg [WIDTH-1 : 0] rdata
);
// Memory Array
reg [WIDTH-1:0] mem[0:WORDS-1];
// If used as Rom then load a memory image at startup
initial begin
if (INIT_FILE == "NONE") begin
end else begin
$readmemh(INIT_FILE, mem);
end
end
// Write function
always @(posedge clk) if (wr && cs && be) mem[addr[ADDR-1:0]] <= wdata[WIDTH-1:0];
generate
if (WRITETHRU) begin
// Read function gets new data if also a write cycle
// latch the read addr for next cycle
reg [ADDR-1:0] l_raddr;
reg l_cycle;
always @(posedge clk) begin
l_raddr <= addr;
l_cycle <= rd && cs;
end
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block
wire [7:0] tmp_rdata;
assign tmp_rdata = (l_cycle) ? mem[{l_raddr[ADDR-1:0]}] : DEFAULT;
always @(*) rdata = tmp_rdata;
end else begin
// Read function gets old data if also a write cycle
always @(posedge clk)
if (rd && cs) rdata <= mem[{addr[ADDR-1:0]}];
else rdata <= DEFAULT;
end
endgenerate
endmodule
| 7.353037 |
module sram #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 16
) (
input clk_i,
input i_bus_we,
input i_bus_en,
input [ADDR_WIDTH-1:0] i_bus_addr,
input [ 1:0] i_bus_size,
inout [DATA_WIDTH-1:0] b_bus_data,
//bus interface going outside
output o_bus_ready,
input ready
);
localparam RAM_DEPTH = 16384; //64kB of memory
reg [DATA_WIDTH-1:0] ram[0:RAM_DEPTH-1];
reg bus_push_data;
reg [31:0] d_read_data;
/*read request*/
assign #1 o_bus_ready = ready; // comb read so slave always ready
always @(posedge clk_i) begin
if (o_bus_ready && i_bus_en && !i_bus_we) begin
d_read_data <= ram[i_bus_addr[15:2]];
bus_push_data <= 1'b1;
end else bus_push_data <= 1'b0;
end
assign #1 b_bus_data = bus_push_data ? d_read_data : 32'hZZZZZZZZ;
/*write request*/
always @(posedge clk_i) begin
if ((i_bus_en == 1'b1) && (i_bus_we == 1'b1)) begin
if (i_bus_size == 2'd0) begin
case ({
i_bus_addr[1], i_bus_addr[0]
})
2'b00: ram[i_bus_addr[15:2]][7 : 0] <= b_bus_data[7 : 0];
2'b01: ram[i_bus_addr[15:2]][15 : 8] <= b_bus_data[15 : 8];
2'b10: ram[i_bus_addr[15:2]][23 : 16] <= b_bus_data[23 : 16];
2'b11: ram[i_bus_addr[15:2]][31 : 24] <= b_bus_data[31 : 24];
endcase
end else if (i_bus_size == 2'd1) begin
if (({i_bus_addr[1], i_bus_addr[0]}) == 2'd0) begin
ram[i_bus_addr[15:2]][15 : 0] <= b_bus_data[15 : 0];
end
if (({i_bus_addr[1], i_bus_addr[0]}) == 2'd0) begin
ram[i_bus_addr[15:2]][31 : 16] <= b_bus_data[31 : 16];
end
end else if (i_bus_size == 2'd2) begin
if (({i_bus_addr[1], i_bus_addr[0]}) == 2'd0) begin
ram[i_bus_addr[15:2]][31 : 0] <= b_bus_data[31 : 0];
end
end
end
end
endmodule
| 7.388143 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_bg
#(parameter DATA_WIDTH = 8, ADDR_WIDTH = 16, RAM_SIZE = 65536)
(input clk, input we, input en,
input [ADDR_WIDTH-1 : 0] addr,
input [DATA_WIDTH-1 : 0] data_i,
output reg [DATA_WIDTH-1 : 0] data_o);
// Declareation of the memory cells
(* ram_style = "block" *) reg [DATA_WIDTH-1 : 0] RAM [RAM_SIZE - 1:0];
integer idx;
// ------------------------------------
// SRAM cell initialization
// ------------------------------------
// Initialize the sram cells with the values defined in "image.dat."
initial begin
$readmemh("seabed.mem", RAM);
end
// ------------------------------------
// SRAM read operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
data_o <= data_i;
else
data_o <= RAM[addr];
end
// ------------------------------------
// SRAM write operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
RAM[addr] <= data_i;
end
endmodule
| 6.896868 |
module SRAM_BIST (
input logic Clock,
input logic Resetn,
input logic BIST_start,
output logic [17:0] BIST_address,
output logic [15:0] BIST_write_data,
output logic BIST_we_n,
input logic [15:0] BIST_read_data,
output logic BIST_finish,
output logic BIST_mismatch
);
enum logic [2:0] {
S_IDLE,
S_DELAY_1,
S_DELAY_2,
S_WRITE_CYCLE,
S_READ_CYCLE,
S_DELAY_3,
S_DELAY_4
} BIST_state;
logic BIST_start_buf;
logic [15:0] BIST_expected_data;
// write the 16 least significant bits of the address bus in each memory location
//
// NOTE: this particular BACKGROUND pattern is specific to this BIST implementation
assign BIST_write_data[15:0] = BIST_address[15:0];
// based on the way how this particular BIST engine is implemented,
// the BIST expected data can be computed on-the-fly by
// decrementing the 16 least significant bits of the address
//
// NOTE: the expected data must change if the memory is traversed in a different way
//assign BIST_expected_data[15:0] = BIST_address[15:0] - 16'd1;
// this specific BIST engine for this reference implementation works as follows
// write location 0 -> read location 0 ->
// write location 1 -> read location 1 + compare location 0 ->
// write location 2 -> read location 2 + compare location 1 ->
// ... go through the entire address range
always_ff @(posedge Clock or negedge Resetn) begin
if (Resetn == 1'b0) begin
BIST_state <= S_IDLE;
BIST_mismatch <= 1'b0;
BIST_finish <= 1'b0;
BIST_address <= 18'd0;
BIST_we_n <= 1'b1;
BIST_start_buf <= 1'b0;
BIST_expected_data <= 16'd0;
end else begin
BIST_start_buf <= BIST_start;
case (BIST_state)
S_IDLE: begin
if (BIST_start & ~BIST_start_buf) begin
// start the BIST engine
BIST_address <= 18'd0;
BIST_we_n <= 1'b1;
BIST_mismatch <= 1'b0;
BIST_finish <= 1'b0;
BIST_state <= S_WRITE_CYCLE;
end else begin
BIST_address <= 18'd0;
BIST_we_n <= 1'b1;
BIST_finish <= 1'b1;
end
end
S_WRITE_CYCLE: begin
if (BIST_address < 18'h3FFFF) begin
BIST_we_n <= 1'b0;
BIST_expected_data <= BIST_expected_data + 16'd1;
BIST_address <= BIST_address + 18'd1;
end else begin
BIST_we_n <= 1'b1;
BIST_state <= S_DELAY_1;
BIST_expected_data <= 16'd0; // Reinitialize expected data to be 0
BIST_address <= 18'd0; // Reinitialize SRAM memory address back to 0
end
end
// a couple of delay states to initiate the first WRITE and first READ
S_DELAY_1: begin
BIST_we_n <= 1'b1; // initiate first READ (NOTE: registers updated NEXT clock cycle)
BIST_address <= BIST_address + 18'd1;
BIST_state <= S_DELAY_2;
end
S_DELAY_2: begin
BIST_we_n <= 1'b1;
BIST_address <= BIST_address + 18'd1;
BIST_state <= S_READ_CYCLE;
end
S_READ_CYCLE: begin
// complete the READ initiated two clock cycles earlier and perform comparison
if (BIST_read_data != BIST_expected_data) begin
BIST_mismatch <= 1'b1;
end
if (BIST_address < 18'h3FFFF) begin
// increment address and continue by initiating a new WRITE
BIST_expected_data <= BIST_expected_data + 16'd1;
BIST_address <= BIST_address + 18'd1;
BIST_we_n <= 1'b1;
end else begin
// delay for checking the last address
BIST_state <= S_DELAY_3;
BIST_expected_data <= BIST_expected_data + 16'd1;
end
end
S_DELAY_3: begin
BIST_state <= S_DELAY_4;
BIST_expected_data <= BIST_expected_data + 16'd1;
if (BIST_read_data != BIST_expected_data) begin
BIST_mismatch <= 1'b1;
end
end
S_DELAY_4: begin
// check for data mismatch
if (BIST_read_data != BIST_expected_data) begin
BIST_mismatch <= 1'b1;
end
// finish the whole SRAM
BIST_state <= S_IDLE;
BIST_finish <= 1'b1;
end
default: BIST_state <= S_IDLE;
endcase
end
end
endmodule
| 8.623769 |
module sram_bus_duelport_ram #(
parameter DP = 2048,
parameter FORCE_X2ZERO = 0,
parameter DW = 32,
parameter MW = 4,
parameter AW = 32
) (
input clk,
input rst_n,
input cs,
input req_a,
input req_b,
input [DW-1 : 0] din_a,
input [DW-1 : 0] din_b,
input [AW-1 : 0] addr_a,
input [AW-1 : 0] addr_b,
input we_a,
input we_b,
input [ MW-1:0] wem_a,
input [ MW-1:0] wem_b,
output [ DW-1:0] dout_a,
output [ DW-1:0] dout_b,
output mem_addr_ok_a,
output mem_data_ok_a,
output mem_addr_ok_b,
output mem_data_ok_b
);
reg [DW-1:0] mem_r[0:DP-1];
reg [AW-1:0] addr_a_r;
reg [AW-1:0] addr_b_r;
wire [MW-1:0] wen_a;
wire [MW-1:0] wen_b;
wire ren_a;
wire ren_b;
wire read_a_disable;
assign read_a_disable = (addr_a == addr_b) ? we_b : 1'b0;
reg read_data_ok_a;
wire write_data_ok_a;
reg read_data_ok_b;
reg write_data_ok_b;
assign mem_addr_ok_a = (!read_a_disable);
assign mem_addr_ok_b = 1'b1;
assign ren_a = rst_n & req_a & (!read_a_disable);
assign ren_b = 1'b0;
assign mem_data_ok_a = write_data_ok_a | read_data_ok_a;
assign mem_data_ok_b = write_data_ok_b | read_data_ok_b;
assign wen_a = 1'b0;
assign wen_b = ({MW{rst_n & req_b & we_b}} & wem_b);
always @(posedge clk) begin
if (!rst_n) begin
addr_a_r <= 0;
read_data_ok_a <= 1'b0;
end else if (ren_a) begin
addr_a_r <= addr_a;
read_data_ok_a <= 1'b1;
end else begin
read_data_ok_a <= 1'b0;
end
end
always @(posedge clk) begin
if (!rst_n) begin
addr_b_r <= 0;
read_data_ok_b <= 1'b0;
end else if (ren_b) begin
addr_b_r <= addr_b;
read_data_ok_b <= 1'b1;
end else begin
read_data_ok_b <= 1'b0;
end
end
assign write_data_ok_a = 1'b0;
always @(posedge clk) begin
if (~rst_n) begin
write_data_ok_b <= 1'b0;
end else if (wen_b) begin
write_data_ok_b <= 1'b1;
end else begin
write_data_ok_b <= 1'b0;
end
end
genvar i;
generate
for (i = 0; i < MW; i = i + 1) begin : mem
if ((8 * i + 8) > DW) begin : last
always @(posedge clk) begin
if (wen_a[i]) begin
mem_r[addr_a][DW-1:8*i] <= din_a[DW-1:8*i];
end else if (wen_b[i]) begin
mem_r[addr_b][DW-1:8*i] <= din_b[DW-1:8*i];
end
end
end else begin : non_last
always @(posedge clk) begin
if (wen_a[i]) begin
mem_r[addr_a][8*i+7:8*i] <= din_a[8*i+7:8*i];
end else if (wen_b[i]) begin
mem_r[addr_b][8*i+7:8*i] <= din_b[8*i+7:8*i];
end
end
end
end
endgenerate
wire [DW-1:0] dout_pre_a;
wire [DW-1:0] dout_pre_b;
assign dout_pre_a = mem_r[addr_a_r];
assign dout_pre_b = mem_r[addr_b_r];
generate
if (FORCE_X2ZERO == 1) begin : force_x_to_zero
for (i = 0; i < DW; i = i + 1) begin : force_x_gen
`ifndef SYNTHESIS //{
assign dout_a[i] = (dout_pre_a[i] === 1'bx) ? 1'b0 : dout_pre_a[i];
assign dout_b[i] = (dout_pre_b[i] === 1'bx) ? 1'b0 : dout_pre_b[i];
`else //}{
assign dout_a[i] = dout_pre_a[i];
assign dout_b[i] = dout_pre_b[i];
`endif //}
end
end else begin : no_force_x_to_zero
assign dout_a = dout_pre_a;
assign dout_b = dout_pre_b;
end
endgenerate
endmodule
| 6.760325 |
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