code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module srlatch (
q,
q_not,
en,
s,
r
);
output q, q_not;
input en, s, r;
wire w1, w2;
nand (w1, en, s);
nand (w2, en, r);
nand (q, w1, q_not);
nand (q_not, w2, q);
endmodule
| 7.226086 |
module sr04 (
input clk,
input rst,
input echo,
output reg trig,
output [12:0] dis
);
parameter TRIG_US = 10; //trig signal holds 10us
parameter TRIG_CNT_MAX = 1_000_000; //1MHz, send trig every secend
reg [19:0] trig_cnt;
reg [15:0] echo_cnt;
reg [15:0] echo_cnt_reg;
always @(posedg... | 7.291364 |
module sr04_control #(
parameter DELAY_TRIGGER = 10,
DELAY_ECHO = 25000,
DELAY_POSTFIX = 500000,
DELAY_WIDTH = $clog2(DELAY_POSTFIX)
) (
input clk,
input rst_n,
input strobe_us,
input strobe_cm,
input echo,
output reg trigger,
output reg measure_... | 6.755506 |
module sr04_receiver #(
parameter RANGE_WIDTH = 16,
DELAY_CLK_1US = 50,
DELAY_1US_1SM = 58,
DELAY_TRIGGER_US = 10,
DELAY_ECHO_US = 400 * DELAY_1US_1SM, //max measured distance is 400 cm
DELAY_POSTFIX_US = 500000
) (
input ... | 7.334079 |
module SR16 (
input clk,
input rst_n,
input [11:0] in_r, //(6,6)
input [11:0] in_i, //(6,6)
output [11:0] out_r, //(6,6)
output [11:0] out_i //(6,6)
);
// change LENGTH here to set up the length of this shift register
//=================================================
... | 7.140839 |
module SR1MUX (
input [2:0] IR11to9,
input [2:0] IR8to6,
input SR1MUX,
output reg [2:0] SR1
);
initial SR1 = 0;
always @(*) begin
case (SR1MUX)
2'b00: SR1 = IR11to9;
2'b01: SR1 = IR8to6;
2'b10: SR1 = 3'b110;
default: SR1 = 0;
endcase
end
endmodule
| 6.813198 |
module sr2mux (
imm,
sreg,
sel,
out
);
input wire [15:0] imm; // immediate value
input wire [15:0] sreg; // source register
input wire sel; // select
output wire [15:0] out; // output
// TODO: `define the values of select
assign out = sel ? imm : sreg;
endmodule
| 9.861934 |
module SR4 (
input clk,
input rst_n,
input [15:0] in_r,
input [15:0] in_i,
output [15:0] out_r,
output [15:0] out_i
);
// change LENGTH here to set up the length of this shift register
//=================================================
parameter LENGTH = 4;
//=======... | 6.653427 |
module SR8 (
input clk,
input rst_n,
input [14:0] in_r,
input [14:0] in_i,
output [14:0] out_r,
output [14:0] out_i
);
// change LENGTH here to set up the length of this shift register
//=================================================
parameter LENGTH = 8;
//=======... | 7.181758 |
module sra (
result,
data_operand,
shamt
);
input [31:0] data_operand;
input [4:0] shamt;
output [31:0] result;
wire [31:0] sixteen, eight, four, two, one, mux1, mux2, mux3, mux4;
shiftright_sixteen rightsixteen (
sixteen,
data_operand
);
mux_2 sixteenmux (
mux1,
sham... | 7.159712 |
module sra1 (
out,
in
);
input [31:0] in;
output [31:0] out;
assign out[31] = in[31];
assign out[30:0] = in[31:1];
endmodule
| 6.724727 |
module sra2 (
out,
in
);
input [31:0] in;
output [31:0] out;
assign out[31] = in[31];
assign out[30] = in[31];
assign out[29:0] = in[31:2];
endmodule
| 6.902233 |
module sra4 (
out,
in
);
input [31:0] in;
output [31:0] out;
assign out[31] = in[31];
assign out[30] = in[31];
assign out[29] = in[31];
assign out[28] = in[31];
assign out[27:0] = in[31:4];
endmodule
| 6.570184 |
module sradd (
input wire [31:0] a,
input wire [31:0] b,
output wire [31:0] z
);
// Assume (should assert) that sign[a] = sign[b]
// SP floating point fields
`define sign 31
`define exponent 30:23
`define mantissa 22:0
// various other constants
`define zero 32'b0
`define NaN 32'hFFFFFF... | 8.298691 |
module SRAM_8bit (
input sys_CLK, // clock
input [ 1:0] sys_CMD, // 00=nop, 01=write 256 bytes, 11=read 256 bytes
input [18:0] sys_ADDR, // word address, multiple of 2 words (4 bytes)
input [15:0] sys_DIN, // data inpu... | 7.508107 |
module sram0 #(
parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 5
) (
input clk,
input en_n,
input wren_n,
input [ADDR_WIDTH-1:0] addr,
input [DATA_WIDTH-1:0] data_i,
output reg [DATA_WIDTH-1:0] data_o
);
reg [DATA_WIDTH-1:0] register[2**ADDR_WIDTH-1:0];
always @(posedge clk) be... | 8.93449 |
module sram146880x6 (
CLK,
A,
CEN,
WEN,
D,
Q
);
parameter A_WID = 18, D_WID = 6;
input CLK;
input [A_WID-1:0] A;
input [D_WID-1:0] D;
input CEN;
input WEN;
output [D_WID-1:0] Q;
reg [D_WID-1:0] Q;
/*********************************************/
/* this part should be repl... | 6.71811 |
module sram16 #(
parameter adr_width = 18
) (
input [adr_width-1:0] adr,
inout [ 15:0] dat,
input ub_n,
input lb_n,
input cs_n,
input we_n,
input oe_n
);
parameter dat_width = 16;
//------------... | 8.616669 |
module sram256x32_1p (
A,
DIN,
WE,
CS,
CLK,
DOUT
);
input [7:0] A;
input [31:0] DIN;
input WE, CS, CLK;
output [31:0] DOUT;
//
reg [31:0] Mem [0:255];
//
reg [ 7:0] A_i;
always @(posedge CLK) begin
if (CS) A_i <= A;
end
always @(posedge CLK) begin
if (CS & WE) Me... | 7.243826 |
module SRAM2RW32x32_1bit (
CE1_i,
CE2_i,
WEB1_i,
WEB2_i,
A1_i,
A2_i,
OEB1_i,
OEB2_i,
CSB1_i,
CSB2_i,
I1_i,
I2_i,
O1_i,
O2_i
);
input CSB1_i, CSB2_i;
input OEB1_i, OEB2_i;
input CE1_i, CE2_i;
input WEB1_i, WEB2_i;
input [`numAddr-1:0] A1_i, A2_i;
inpu... | 6.791928 |
module SRAM2_Interface (
input iCLK,
input iCLKMem, // usar pelo menos 4xiCLK
inout [31:0] SRAM_DQ, // SRAM Data Bus 32 Bits
output [18:0] oSRAM_A, // SRAM Address bus 21 Bits
output oSRAM_ADSC_N, // SRAM Controller Address Status
output oSRAM_ADSP_N, // SRAM Processor Address Status
o... | 7.64085 |
module sram2_pack #(
parameter BASE_ADDR = 8'h00
) (
input clk,
// SRAM hardware interface
inout [ 7:0] ram_data_z,
(* IOB = "TRUE" *) output reg [23:0] ram_address,
(* IOB = "TRUE" *) output reg ram_nwe,
output ram_nce,
... | 7.970763 |
module SRAM3 (
input clk,
input [10:0] addr,
input [10:0] addr_r,
output [9:0] data_out,
input [9:0] data_in,
input we,
output reg carry
);
reg [9:0] mem[0:2047];
always @(posedge clk) begin
if (we) mem[addr] <= data_in;
if (addr == 11'b11111111111) carry <= 1'b1;
else carry... | 6.714029 |
module sram32 #(
parameter AW = 10,
VERBOSE = 1
) (
input wire clk,
input wire cs,
input wire [ 3:0] we,
input wire [AW-1:0] A,
input wire [ 31:0] Di,
output reg [ 31:0] Do
);
reg [31:0] ram[(2**AW)-1:0];
always @(posedge clk)
if (cs) begin
Do <=... | 7.281926 |
module sram4 (
clk_i,
address_i,
data_i,
data_o,
wr_i
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter [31:0] SRAM_ADDR_WIDTH = 14;
//--------------------------------------------... | 7.435184 |
module SRAM4x16 (
input clk,
rst,
wr,
input [3:0] data,
addr,
output reg [3:0] out
);
reg [3:0] mem[15:0];
always @(posedge clk) begin
if (rst) out <= 0;
else begin
if (wr) //wr is for write
mem[addr] <= data;
else out <= mem[addr];
end
end
endmodule
| 7.842857 |
module tb_golden_SRAM ();
reg clk, rst, wr;
reg [3:0] data, addr;
wire [3:0] out;
integer i, j = 4'd15;
integer k = 4'd15;
SRAM4x16 DUT (
clk,
rst,
wr,
data,
addr,
out
);
/////////////// Parameters for Timing ///////
parameter SETUP_TIME = 1;
parameter HOLD_TI... | 6.961187 |
module for read operation//////
module SRAM_ref(input clk, rst, wr, [3:0] data, addr, output [3:0] out_exp);
SRAM4x16 REF_inst(clk, rst, wr, data, addr, out_exp);
endmodule
| 7.77664 |
module SRAM4x16_tb ();
reg clk, rst_tb, wr;
reg [3:0] data, addr;
wire [3:0] out, out_exp;
SRAM4x16 DUT (
clk,
rst_tb,
wr,
data,
addr,
out
);
SRAM_ref REF (
clk,
rst_tb,
wr,
data,
addr,
out_exp
);
parameter SETUP_TIME = 1;
para... | 8.099517 |
module sram69120x8 (
CLK,
A,
CEN,
WEN,
D,
Q
);
parameter A_WID = 17, D_WID = 8;
input CLK;
input [A_WID-1:0] A;
input [D_WID-1:0] D;
input CEN;
input WEN;
output [D_WID-1:0] Q;
reg [D_WID-1:0] Q;
/*********************************************/
/* this part should be repla... | 7.207276 |
module SRAM64 (
input CLK,
input RST,
input SRAM_WE_N,
input [16:0] SRAM_ADDR, // 17 Bits (was 19)
inout signed [63:0] SRAM_DQ // Data 64 Bits (Write 32 Least Significant Bits When WE)
);
reg [31:0] memory[0:127]; // 65535
assign #30 SRAM_DQ = SRAM_WE_N ? {memory[{SRAM_ADDR[16:1], 1'b1}],... | 7.454498 |
module SRAM64x14 (
A,
CE,
WEB,
OEB,
CSB,
I,
O
);
input CE;
input WEB;
input OEB;
input CSB;
input [`numAddr-1:0] A;
input [`wordLength-1:0] I;
output [`wordLength-1:0] O;
reg [`wordLength-1:0] memory [`numWords-1:0];
reg [`wordLength-1:0] data_out1;
reg [`wordLen... | 6.917022 |
module sramctrl (
input wire clk_in,
input wire rst_in,
input wire trig_in,
input wire rw_in,
input wire [18:0] addr_in,
input wire [7:0] w_data_in,
output reg [7:0] r_data_out,
output reg done_out,
output reg we_n_out,
output reg ce_n_out,
output reg oe_n_out,
output re... | 7.072356 |
module sramDemo (
LEDR,
SW,
KEY,
CLOCK_50
);
output [9:0] LEDR;
input CLOCK_50;
input [9:0] SW;
input [3:0] KEY;
reg nOE;
reg read;
reg [10:0] adrx;
reg [15:0] mem;
wire [15:0] data;
wire rst;
wire enterWrite;
wire enterRead;
reg [9:0] ledDriver;
wire [31:0] clk; // choos... | 7.084993 |
module clock_divider (
clk_out,
clk_in,
slowDown
);
output clk_out;
reg [31:0] divided_clocks;
input clk_in, slowDown;
assign clk_out = slowDown ? divided_clocks[23] : clk_in;
initial divided_clocks = 0;
always @(posedge clk_in) divided_clocks = divided_clocks + 1;
endmodule
| 6.818038 |
module
// so the outer module corresponds to an SRAM generated with the
// OpenRAM memory compiler.
`ifndef SRAM_SRAM_GENERIC_V
`define SRAM_SRAM_GENERIC_V
module sram_SramGeneric
#(
parameter p_data_nbits = 1,
parameter p_num_entries = 2,
// Local constants not meant to be set from outside the module
param... | 8.153305 |
module
// so the outer module corresponds to an SRAM generated with the
// OpenRAM memory compiler.
`ifndef SRAM_SRAM_GENERIC_V
`define SRAM_SRAM_GENERIC_V
module sram_SramGenericVRTL
#(
parameter p_data_nbits = 1,
parameter p_num_entries = 2,
// Local constants not meant to be set from outside the module
p... | 8.153305 |
module sramGTK;
// connect the two modules
wire [9:0] ledrBench;
wire clockBench;
wire [9:0] swBench;
wire [3:0] keyBench;
// declare an instance of the sramTop module
sramDemo mySramDemo (
ledrBench,
swBench,
keyBench,
clockBench
);
// declare an instance of the testbench
... | 7.263598 |
module sramR (
input clk100mhz,
input w,
ce,
input [15:0] dataBus,
output [15:0] LED
);
reg [15:0] data;
always @(posedge clk100mhz) begin
if (w && (ce == 0)) begin
data <= dataBus;
end
end
/*if(changeaddr==0) addrBus= addrBus1;
else if(changeaddr) addrBus= addrBus1;*/
a... | 6.871882 |
module datapath_latch_sramsp2048x128 (
CLK,
Q_update,
D_update,
SE,
SI,
D,
DFTRAMBYP,
mem_path,
XQ,
Q
);
input CLK, Q_update, D_update, SE, SI, D, DFTRAMBYP, mem_path, XQ;
output Q;
reg D_int;
reg Q;
// Model PHI2 portion
always @(CLK or SE or SI or D) begin
if... | 6.596005 |
module datapath_latch_sramsp32768x36 (
CLK,
Q_update,
D_update,
SE,
SI,
D,
DFTRAMBYP,
mem_path,
XQ,
Q
);
input CLK, Q_update, D_update, SE, SI, D, DFTRAMBYP, mem_path, XQ;
output Q;
reg D_int;
reg Q;
// Model PHI2 portion
always @(CLK or SE or SI or D) begin
if... | 6.596005 |
module datapath_latch_sramsp4096x128 (
CLK,
Q_update,
D_update,
SE,
SI,
D,
DFTRAMBYP,
mem_path,
XQ,
Q
);
input CLK, Q_update, D_update, SE, SI, D, DFTRAMBYP, mem_path, XQ;
output Q;
reg D_int;
reg Q;
// Model PHI2 portion
always @(CLK or SE or SI or D) begin
if... | 6.596005 |
module datapath_latch_sramsp4096x144 (
CLK,
Q_update,
D_update,
SE,
SI,
D,
DFTRAMBYP,
mem_path,
XQ,
Q
);
input CLK, Q_update, D_update, SE, SI, D, DFTRAMBYP, mem_path, XQ;
output Q;
reg D_int;
reg Q;
// Model PHI2 portion
always @(CLK or SE or SI or D) begin
if... | 6.596005 |
module datapath_latch_sramsp8192x128 (
CLK,
Q_update,
D_update,
SE,
SI,
D,
DFTRAMBYP,
mem_path,
XQ,
Q
);
input CLK, Q_update, D_update, SE, SI, D, DFTRAMBYP, mem_path, XQ;
output Q;
reg D_int;
reg Q;
// Model PHI2 portion
always @(CLK or SE or SI or D) begin
if... | 6.596005 |
module datapath_latch_sramsp8192x144 (
CLK,
Q_update,
D_update,
SE,
SI,
D,
DFTRAMBYP,
mem_path,
XQ,
Q
);
input CLK, Q_update, D_update, SE, SI, D, DFTRAMBYP, mem_path, XQ;
output Q;
reg D_int;
reg Q;
// Model PHI2 portion
always @(CLK or SE or SI or D) begin
if... | 6.596005 |
module datapath_latch_sramsp8192x32 (
CLK,
Q_update,
D_update,
SE,
SI,
D,
DFTRAMBYP,
mem_path,
XQ,
Q
);
input CLK, Q_update, D_update, SE, SI, D, DFTRAMBYP, mem_path, XQ;
output Q;
reg D_int;
reg Q;
// Model PHI2 portion
always @(CLK or SE or SI or D) begin
if ... | 6.596005 |
module dual_port_sram_TB ();
parameter RAM_WIDTH = 8;
parameter RAM_DEPTH = 64;
parameter ADDR_SIZE = 8;
reg clk, reset, rwenable_A, rwenable_B;
reg [RAM_WIDTH-1:0] data_A, data_B;
reg [ADDR_SIZE-1:0] addr_A, addr_B;
wire [RAM_WIDTH-1:0] outputData_A, outputData_B;
integer i;
dual_port_sram DUT (
... | 9.237963 |
module SRAMVerilogAWS #(
parameter WORDS = 1024,
parameter AWIDTH = 10,
parameter DWIDTH = 32
) (
input clk,
input [AWIDTH-1:0] raddr,
input [AWIDTH-1:0] waddr,
input raddrEn,
input waddrEn,
input wen,
input [DWIDTH-1:0] wdata,
input flow,
output reg [DWIDTH-1:0] rdata
)... | 6.817776 |
module SRAMVerilogSim #(
parameter WORDS = 1024,
parameter AWIDTH = 10,
parameter DWIDTH = 32
) (
input clk,
input [AWIDTH-1:0] raddr,
input [AWIDTH-1:0] waddr,
input raddrEn,
input waddrEn,
input wen,
input [DWIDTH-1:0] wdata,
output reg [DWIDTH-1:0] rdata
);
reg [DWIDTH... | 6.966284 |
module are prefixed by port0_, meaning all reads
// and writes happen through the only port. Multiported SRAMs have ports
// prefixed by port1_, port2_, etc.
//
// The following list describes each port of this module.
//
// Port Name Direction Description
// -----------------------------------------------------... | 7.792858 |
module sram_0 (
// inputs:
iADDR,
iBE_N,
iCE_N,
iCLK,
iDATA,
iOE_N,
iWE_N,
// outputs:
SRAM_ADDR,
SRAM_CE_N,
SRAM_DQ,
SRAM_LB_N,
SRAM_OE_N,
SRAM_UB_N,
SRAM_WE_N,
oDATA
);
output [17:0] SRAM_ADDR;
output SRAM_CE_N;
inout [15:0] SRAM_DQ;
output... | 7.13854 |
module SRAM_1 #(
parameter DATA_WIDTH = 1280,
parameter ADDR_WIDTH = 5
) (
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] addr,
input we,
clk,
output [(DATA_WIDTH-1):0] q
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
// Variable to hold the regis... | 8.196529 |
module sram_1024x32 (
addr,
clk,
din,
dout,
we
);
input clk, we;
input [9:0] addr;
input [31:0] din;
output reg [31:0] dout;
reg [31:0] mem[0:1023];
always @(posedge clk) begin
if (!we) begin
// write
mem[addr] <= din[31:0];
dout <= 32'bz;
end else if (... | 6.627708 |
module sram_112x128 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
spare_wen0,
addr0,
din0,
dout0
);
parameter NUM_WMASKS = 14;
parameter DATA_WIDTH = 113;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIX... | 6.883001 |
module SRAM_16Bit_512K ( // Host Data
oDATA,
iDATA,
iADDR,
iWE_N,
iOE_N,
iCE_N,
iCLK,
iBE_N,
// SRAM
SRAM_DQ,
SRAM_ADDR,
SRAM_UB_N,
SRAM_LB_N,
SRAM_WE_N,
SRAM_CE_N,
SRAM_OE_N
);
// Host Side
input [15:0] iDATA;
output [15:0] oDATA;
input [17:0] iA... | 7.900918 |
module sram_16x128b (
input clk,
input csb, //chip enable
input wsb, //write enable
input [128-1:0] wdata, //write data
input [5:0] waddr, //write address
input [5:0] raddr, //read address
output reg [16*8-1:0] rdata //read data
);
localparam WEIGHT_WIDTH = 16;
localparam WEIGHT_... | 6.707188 |
module sky130_sram_1kbyte_1rw1r_32x256_8#(
// parameter NUM_WMASKS = 4,
// parameter DATA_WIDTH = 32,
// parameter ADDR_WIDTH = 8,
// parameter RAM_DEPTH = 256,
// parameter DELAY = 0
// )(
// input clk0, // clock
// input csb0, // active low chip select
// input web0, // active low write control
//... | 7.095527 |
module sram_1r1w #(
parameter DATA_WIDTH = 32,
parameter SIZE = 1024,
parameter ADDR_WIDTH = $clog2(SIZE)
) (
input clk,
input [ADDR_WIDTH - 1:0] rd_addr,
output reg [DATA_WIDTH - 1:0] rd_data = 0,
input wr_enable,
input [ADDR_WID... | 6.797447 |
module sram_1rw0r0w_32_128_freepdk45 (
`ifdef USE_POWER_PINS
vdd,
gnd,
`endif
// Port 0: RW
clk0,
csb0,
web0,
addr0,
din0,
dout0
);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 7;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELA... | 7.442043 |
module sram_1rw1r_32_256_8_sky130 (
`ifdef USE_POWER_PINS
vdd,
gnd,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 8... | 6.906604 |
module sram_20000x100b (
input clk,
input csb, //chip enable
input wsb, //write enable
input wdata, //write data
input [9:0] waddr, //write address
input [16:0] raddr, //read address
output reg [99:0] rdata //read data
);
localparam WEIGHT_WIDTH = 4;
localparam WEIGHT_PIXEL_NUM =... | 6.699095 |
module sram_24x4096 (
input clk_i,
input rst_i,
input wr_en_i,
input rd_en_i,
input [11:0] addr_i,
input [23:0] wdata_i,
output [23:0] rdata_o
);
reg [23:0] bram [4095:0];
integer i;
reg [23:0] data;
//add implementation code here
... | 6.542987 |
module sram_24x4096 (
input clk_i,
input rst_i,
input wr_en_i,
input rd_en_i,
input [11:0] addr_i,
input [23:0] wdata_i,
output [23:0] rdata_o
);
reg [23:0] bram [4095:0];
integer i;
reg [23:0] data;
//add implementation code here
... | 6.542987 |
module sram_128x32b (
input clk,
input [3:0] bytemask,
input csb, //chip enable
input wsb, //write enable
input [7:0] wdata, //write data
input [9:0] waddr, //write address
input [9:0] raddr, //read address
output reg [31:0] rdata //read data
);
reg [31:0] _rdata;
reg [31:0] ... | 7.208115 |
module sram (
input clk,
input CEN,
input WEN,
input [31:0] Din,
input [8:0] Address,
output reg signed [31:0] Dout //512 32-bits SRAMs
);
reg signed [31:0] temp[511:0];
reg signed [31:0] out_buffer;
reg notice;
////////////timing specification
specify
//$setuphold(posedge clk, ... | 7.547687 |
module sram_32_16_sky130 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
spare_wen0,
addr0,
din0,
dout0
);
parameter DATA_WIDTH = 33;
parameter ADDR_WIDTH = 5;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parame... | 7.670028 |
module sram_32_256_sky130A (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
addr0,
din0,
dout0
);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;... | 7.678513 |
module sram_336x128 (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
spare_wen0,
addr0,
din0,
dout0
);
parameter NUM_WMASKS = 42;
parameter DATA_WIDTH = 337;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIX... | 7.297617 |
module SRAM_4R4W_AMT (
addr0_i,
addr1_i,
addr2_i,
addr3_i,
addr0wr_i,
we0_i,
data0wr_i,
addr1wr_i,
we1_i,
data1wr_i,
addr2wr_i,
we2_i,
data2wr_i,
addr3wr_i,
we3_i,
data3wr_i,
clk,
reset,
data0_o,
data1_o,
data2_o,
data3_o
);
par... | 6.628596 |
module implements SRAM.
# Author: FabGen
*******************************************************************************/
`timescale 1ns/100ps
module SRAM_4R4W_FREELIST(
clk,
reset,
addr0_i,
addr1_i,
addr2_i,
addr3_i,
addr0wr_i,
addr1wr_i,
addr2wr_i,
addr3wr_i,
we0_i,
we1_i,
we2_i,
we3_i,
data0wr_i,
... | 6.592425 |
module implements SRAM.
# Author: FabGen
*******************************************************************************/
`timescale 1ns/100ps
module SRAM_4R8W(
clk,
reset,
addr0_i,
addr1_i,
addr2_i,
addr3_i,
addr0wr_i,
addr1wr_i,
addr2wr_i,
addr3wr_i,
addr4wr_i,
addr5wr_i,
addr6wr_i,
addr7wr_i,
we0_... | 6.592425 |
module tsyncram_4x32 (
CLK,
CLKN,
ADDR,
WEN,
WE,
REN,
RE,
CSN,
CSB,
DATA_IN,
DATA_OUT
);
input CLK;
input CLKN;
input [1:0] ADDR;
input WEN;
input WE;
input REN;
input RE;
input CSN;
input CSB;
input [31:0] DATA_IN;
output [31:0] DATA_OUT;
SYHD130_8... | 6.639607 |
module sram_512w_16b (
Q,
CLK,
CEN,
WEN,
A,
D,
EMA,
EMAW,
EMAS,
TEN,
BEN,
RET1N,
STOV
);
output reg [15:0] Q;
input CLK;
input CEN;
input WEN;
input [8:0] A;
input [15:0] D;
input [2:0] EMA;
input [1:0] EMAW;
input EMAS;
input TEN;
input BEN;
... | 7.552978 |
module sram_64x512b (
input clk,
input csb, //chip enable
input wsb, //write enable
input [511:0] wdata, //write data
input [5:0] waddr, //write address
input [5:0] raddr, //read address
output reg [511:0] rdata //read data
);
localparam WEIGHT_WIDTH = 16;
localparam WEIGHT_PIXEL... | 7.039658 |
module sram_64x64 (
input clk_i,
input rst_i,
input wr_en_i,
input rd_en_i,
input [ 5:0] addr_i,
input [63:0] wdata_i,
output [63:0] rdata_o
);
reg [63:0] bram [63:0];
integer i;
reg [63:0] data;
//add implementation code here
alwa... | 7.551375 |
module sram_64x8b #( //for bias
parameter BIAS_PER_ADDR = 1,
parameter BW_PER_PARAM = 8
) (
input clk,
input csb, //chip enable
input wsb, //write enable
input [BIAS_PER_ADDR*BW_PER_PARAM-1:0] wdata, //write data
input [5:0] waddr, //write address
input [5:0] raddr, //read address... | 6.793474 |
module SRAM_8Kx32 (
output [31:0] Q,
input [31:0] D,
input [14:0] A,
input clk,
input cen,
input [3:0] wen
);
reg [31:0] RAM[4*1024-1:0];
reg [31:0] DATA;
wire [31:0] data = RAM[A];
assign Q = DATA;
always @(posedge clk) DATA <= data;
always @(posedge clk)
if (cen) begin
if... | 7.190322 |
module implements SRAM.
# Author: FabGen
*******************************************************************************/
`timescale 1ns/100ps
module SRAM_8R4W_PIPE(
clk,
reset,
addr0_i,
addr1_i,
addr2_i,
addr3_i,
addr4_i,
addr5_i,
addr6_i,
addr7_i,
addr0wr_i,
addr1wr_i,
addr2wr_i,
addr3wr_i,
we0_i,
... | 6.592425 |
module implements SRAM.
# Author: FabGen
*******************************************************************************/
`timescale 1ns/100ps
module SRAM_8R4W_RMT(
clk,
reset,
addr0_i,
addr1_i,
addr2_i,
addr3_i,
addr4_i,
addr5_i,
addr6_i,
addr7_i,
addr0wr_i,
addr1wr_i,
addr2wr_i,
addr3wr_i,
we0_i,
... | 6.592425 |
module SRAM_AddressMapping (
input [31:0] ALU_result,
output [17:0] address
);
wire [31:0] address_base;
assign address_base = (ALU_result - 1024);
assign address = address_base[18:1];
endmodule
| 6.94907 |
module sram_addr_decoder (
clk,
lineNumber,
spriteNumber,
address
);
input clk;
input [3:0] lineNumber;
input [4:0] spriteNumber;
output [19:0] address;
assign address = (20'd16 * spriteNumber) + lineNumber;
endmodule
| 6.652576 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_an... | 6.896868 |
module sram_async #(
parameter W_DATA = 16, // Must be power of 2, >= 8
parameter DEPTH = 1 << 18, // == 0.5 MiB for 16 bit interface
parameter PRELOAD_FILE = "",
parameter W_ADDR = $clog2(DEPTH), // Let this default
parameter W_BYTES = W_DATA / 8 // ... | 7.470036 |
module SRAM_async3 #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 10,
DELAY = 25,
DATA_HEX_FILE = "dump.hex"
) (
input wire [ADDR_WIDTH-1:0] ADDR,
input wire CE1n,
input wire CE2,
input wire OEn,
input wire WEn,
inout wire [DATA_WIDTH-1:0] DATA
);
reg [DATA_WIDTH-1:0] mem[0:(2**ADD... | 9.155359 |
module SRAM_async3 #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 10,
DELAY = 25,
DATA_HEX_FILE = "dump.hex"
) (
input wire [ADDR_WIDTH-1:0] ADDR,
input wire CE1n,
input wire CE2,
input wire OEn,
input wire WEn,
inout wire [DATA_WIDTH-1:0] DATA
);
reg [DATA_WIDTH-1:0] mem[0:(2**ADD... | 9.155359 |
module SRAM_async_alwaysdout #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 10,
DELAY = 25,
DATA_HEX_FILE = "dump.hex"
) (
input wire [ADDR_WIDTH-1:0] ADDR,
input wire CE1n,
input wire CE2,
input wire OEn,
input wire WEn,
inout wire [DATA_WIDTH-1:0] DATA
);
reg [DATA_WIDTH-1:0] mem... | 9.276724 |
module: sram_axi_adapter
//
// Module adapted from The picoRV32 AXI adapter to allow
// back to back read/write address channel requests and bus fault
// propagation.
//
module sram_axi_adapter (
input g_clk ,
input g_resetn ,
// AXI4-lite master memory interface
output mem... | 7.108475 |
module SRAM_1R1W (
addr0_i,
addrWr_i,
we_i,
data_i,
clk,
reset,
data0_o
);
parameter SRAM_DEPTH = 64;
parameter SRAM_INDEX = 6;
parameter SRAM_WIDTH = 32;
input [SRAM_INDEX-1:0] addr0_i;
input [SRAM_INDEX-1:0] addrWr_i;
input we_i;
input clk;
input reset;
input [SRAM_WID... | 7.248883 |
module SRAM_1R1W_i (
addr0_i,
addrWr_i,
we_i,
data_i,
clk,
reset,
data0_o
);
parameter SRAM_DEPTH = 64;
parameter SRAM_INDEX = 6;
parameter SRAM_WIDTH = 32;
input [SRAM_INDEX-1:0] addr0_i;
input [SRAM_INDEX-1:0] addrWr_i;
input we_i;
input clk;
input reset;
input [SRAM_W... | 7.480097 |
module SRAM_2R1W_HY (
re0_i,
addr0_i,
re1_i,
addr1_i,
addrWr_i,
we_i,
data_i,
clk,
reset,
data0_o,
data1_o
);
parameter SRAM_DEPTH = 64;
parameter SRAM_INDEX = 6;
parameter SRAM_WIDTH = 2;
parameter SRAM_FETCH_BANDWIDTH = 4;
parameter SRAM_FETCH_BANDWIDTH_LOG = 2... | 7.643707 |
module SRAM_1R1W_2stage_pipelined (
addr0_i,
re_i,
addrWr_i,
we_i,
data_i,
stall_i,
flush_i,
clk,
reset,
data0_o
);
parameter SRAM_DEPTH = 64;
parameter SRAM_INDEX = 6;
parameter SRAM_WIDTH = 32;
input [SRAM_INDEX-1:0] addr0_i;
input re_i;
input [SRAM_INDEX-1:0] add... | 8.128236 |
module SRAM_1R1W_2stage_pipelined_fifo (
addr0_i,
re_i,
addrWr_i,
we_i,
data_i,
stall_i,
flush_i,
clk,
reset,
data0_o
);
parameter SRAM_DEPTH = 64;
parameter SRAM_INDEX = 6;
parameter SRAM_WIDTH = 8;
input [SRAM_INDEX-1:0] addr0_i;
input re_i;
input [SRAM_INDEX-1:0]... | 8.128236 |
module SRAM_2R1W_2stage_pipelined (
addr0_i,
re0_i,
addr1_i,
re1_i,
addrWr_i,
we_i,
data_i,
stall_i,
flush_i,
clk,
reset,
data0_o,
data1_o
);
parameter SRAM_DEPTH = 64;
parameter SRAM_INDEX = 6;
parameter SRAM_WIDTH = 8;
input [SRAM_INDEX-1:0] addr0_i;
inp... | 8.010394 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_ba... | 6.896868 |
module sram (
clk_clk,
reset_reset,
sram_DQ,
sram_ADDR,
sram_LB_N,
sram_UB_N,
sram_CE_N,
sram_OE_N,
sram_WE_N,
sram_io_address,
sram_io_byteenable,
sram_io_read,
sram_io_write,
sram_io_writedata,
sram_io_readdata,
sram_io_readdatavalid
);
input clk_clk;... | 6.9173 |
module cde_sram_be #(
parameter ADDR = 10,
WIDTH = 8,
WORDS = 1024,
WRITETHRU = 0,
DEFAULT = {WIDTH{1'b1}},
INIT_FILE = "NONE",
INSTANCE_NAME = "U1"
) (
input wire clk,
input wire cs,
input wire rd,
input wire wr,
input wire be,
input wire [ ADDR-1 : 0] addr,
i... | 7.353037 |
module sram #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 16
) (
input clk_i,
input i_bus_we,
input i_bus_en,
input [ADDR_WIDTH-1:0] i_bus_addr,
input [ 1:0] i_bus_size,
inout [DATA_WIDTH-1:0] b_bus_data,
//bus... | 7.388143 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_bg... | 6.896868 |
module SRAM_BIST (
input logic Clock,
input logic Resetn,
input logic BIST_start,
output logic [17:0] BIST_address,
output logic [15:0] BIST_write_data,
output logic BIST_we_n,
input logic [15:0] BIST_read_data,
output logic BIST_finish,
output logic BIST_mismatch
);
enum logic ... | 8.623769 |
module sram_bus_duelport_ram #(
parameter DP = 2048,
parameter FORCE_X2ZERO = 0,
parameter DW = 32,
parameter MW = 4,
parameter AW = 32
) (
input clk,
input rst_n,
input cs,
input req_a,
input req_b,
input [DW-1 : 0... | 6.760325 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.