code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sram_byte_en
#(
parameter DATA_WIDTH = 128,
parameter ADDRESS_WIDTH = 7
)
(
input i_clk,
input [DATA_WIDTH-1:0] i_write_data,
input i_write_enable,
input [ADDRESS_WIDTH-1:0] i_address,
input [DATA_WIDTH/8-1:0] i_byte_enable,
output ... | 7.273859 |
module sram_byte_en_model #(
parameter NB_COL = 4, // Specify number of columns (number of bytes)
parameter COL_WIDTH = 8, // Specify column width (byte width, typically 8 or 9)
parameter RAM_DEPTH = 8192, // Specify RAM depth (number of entries)
parameter INIT_FILE = "./firmware.hex" // Specify nam... | 7.409979 |
module sram_code #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input clk,
input en,
input [ADDR_WIDTH-1:0] addr,
output [DATA_WIDTH-1:0] dout
);
localparam SRAM_SIZE = (1 << (ADDR_WIDTH - 1));
reg [DATA_WIDTH-1:0] sram[SRAM_SIZE-1:0];
reg ... | 7.579163 |
module SRAM_Controller64 (
input clk,
input rst,
// Golden Inputs
input write_en,
read_en,
input [31:0] address,
input [31:0] writeData,
// WB
output signed [63:0] readData,
// Freeze
output ready,
// SRAM
inout signed [63:0] SRAM_DQ,
output [16:0] SRAM_ADDR,
... | 7.111397 |
module SRAM_CONTROLLER_NEOGEO (
input clk,
input reset_n,
output [16:0] sram_a,
inout [15:0] sram_dq,
output sram_oe_n,
output sram_we_n,
output sram_ub_n,
output sram_lb_n,
input [15:0] M68K_ADDR_RAM,
input [15:0] M68K_DATA_RAM,
output [15:0]... | 7.484689 |
module test_sramcontroller ();
parameter CLK_PHASE = 5;
parameter MAX_MESSAGE_LENGTH = 8;
parameter SYMBOL_WIDTH = 32;
reg clk;
reg reset;
reg enable_sig;
reg rw_sig;
reg [$clog2(MAX_MESSAGE_LENGTH)-1:0] addr_sig;
reg [SYMBOL_WIDTH-1:0] write_data_sig;
wire [SYMBOL_WIDTH-1:0] sram_out_signal;
... | 6.537707 |
module sram_fsm (
output wire CE_N,
output wire LB_N,
output wire OE_N,
output wire UB_N,
output wire WE_N,
output wire rd_valid,
output wire wr_valid,
input wire clk,
input wire rd_en,
input wire reset,
input wire wr_en
);
// state bits
parameter IDLE = 7'b0011111, ... | 8.198219 |
module sram_core_sword (
input wire clk, // main clock
input wire rst, // synchronous reset
input wire cs, // chip select
input wire we, // write enable
input wire [ADDR_BITS-1:2] addr, // address
input wire [3:0] sel, // byte select
input wire burst, // burst mode flag
input wire... | 7.719674 |
module hold (
input Clk,
input Reset,
input In,
output Out
);
//
reg [1:0] Cnt;
reg CntEn;
always @(posedge Clk or posedge Reset) begin
if (Reset) CntEn <= #`dh 0;
else begin
if (In) CntEn <= #`dh 1;
else if (Cnt == 3) CntEn <= #`dh 0;
end
end
//
always @(... | 6.555699 |
module interact with the external sram
/// write process takes 3 clk cycles
/// read process asynchronous
///@port clk 100mhz
///@port rst_n active-low reset
///@port {input} wr_req active-high prior to rd_req, writes $write_data into sram with the address specified by write_addr
///@port {input} rd_req simply set rd_r... | 7.774385 |
module sram_ctrl2 (
input wire clk, // Clock signal
input wire reset, // Reset signal
input wire rw, // With this signal, we select reading or writing operation
input wire [20:0] addr, // Address bus
input wire [ 7:0] data_f2s, // Data to be writteb in the SRAM
output ... | 6.903876 |
module sram_data #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input clk,
input en,
input [ 3:0] we,
input [ADDR_WIDTH-1:0] addr,
input [DATA_WIDTH-1:0] din,
output [DATA_WIDTH-1:0] dout
);
localparam SRAM_SIZE = (1 << (ADD... | 7.69927 |
module sram_data_collector #(
parameter NUM_RULE_BYTES = 48,
parameter ENTRY_DATA_WIDTH = 128,
parameter ENTRY_ADDR_WIDTH = 15,
parameter FLIP_BYTE_ORDER = 1, // flip the bytes ordering of the lookup/data
parameter SRAM_ADDR_WIDTH = 19,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA... | 7.515567 |
module SRAM_DATA_IO (
Data,
Y,
Trien,
PAD
);
input [15:0] Data;
output [15:0] Y;
input Trien;
inout [15:0] PAD;
BIBUF_LVCMOS33 \BIBUF_LVCMOS33[5] (
.PAD(PAD[5]),
.D (Data[5]),
.E (Trien),
.Y (Y[5])
);
BIBUF_LVCMOS33 \BIBUF_LVCMOS33[0] (
.PAD(PAD[0]),
... | 6.516769 |
module sram_data_reader #(
parameter NUM_RULE_BYTES = 48,
parameter ENTRY_DATA_WIDTH = 128,
parameter ENTRY_ADDR_WIDTH = 15,
parameter SRAM_ADDR_WIDTH = 19,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH / 8
) ( // --- Interface to rule checker
input [ENTRY_ADDR_WIDTH-1:0] fou... | 8.007721 |
module cde_sram_def #(
parameter ADDR = 10,
WIDTH = 8,
WORDS = 1024,
WRITETHRU = 0,
DEFAULT = {WIDTH{1'b1}},
INIT_FILE = "NONE",
INSTANCE_NAME = "U1"
) (
input wire clk,
input wire cs,
input wire rd,
input wire wr,
... | 7.771816 |
module sram_dog #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 16,
RAM_SIZE = 65536
) (
input clk,
input we,
input en,
input [ADDR_WIDTH-1 : 0] addr,
input [DATA_WIDTH-1 : 0] data_i,
output reg [DATA_WIDTH-1 : 0] data_o
);
// Declareation of the memory cells
(* ram_style = "block" *)... | 7.659376 |
module sram_driver (
input wire clk, // expecting 12Mhz, adjust WAIT_TIME if this changes
input wire reset, // reset high
// module control
input wire re, // read enable, otherwise write
input wire start, // start a transaction
output reg ready, /... | 7.789387 |
module chipselects reads and writes to the sram, with 2-cycle *
* read latency and one cycle write latency. *
* *
*****************************************************************************/
module sram_dr... | 7.349016 |
module SRAM_dual_async3 #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 10,
DELAY = 25,
DATA_HEX_FILE = "dump.hex"
) (
input wire [ADDR_WIDTH-1:0] ADDRA,
input wire [ADDR_WIDTH-1:0] ADDRB,
input wire CEA1n,
input wire CEA2,
input wire OEAn,
input wire WEAn,
input wire CEB1n,
in... | 9.271563 |
module
* Copyright Robert Schmidt <rschmidt@uni-bremen.de>, 2020
*
* This documentation describes Open Hardware and is licensed under the
* CERN-OHL-W v2.
*
* You may redistribute and modify this documentation under the terms
* of the CERN-OHL-W v2. (https://cern.ch/cern-ohl). This documentation
* is distribute... | 8.161218 |
module SRAM_dual_sync #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 10
) (
input wire clk0,
input wire clk1,
input wire [ADDR_WIDTH-1:0] ADDR0,
input wire [ADDR_WIDTH-1:0] ADDR1,
input wire [DATA_WIDTH-1:0] DATA0,
input wire [DATA_WIDTH-1:0] DATA1,
(* direct_enable = 1 *) input wire cen0... | 8.146296 |
module SRAM_dual_sync_init #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 10,
DATA_HEX_FILE = "dump.hex"
) (
input wire clk0,
input wire clk1,
input wire [ADDR_WIDTH-1:0] ADDR0,
input wire [ADDR_WIDTH-1:0] ADDR1,
input wire [DATA_WIDTH-1:0] DATA0,
input wire [DATA_WIDTH-1:0] DATA1,
(*... | 8.146296 |
module sram_evrisim (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: W
clk0,
csb0,
addr0,
din0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter DATA_WIDTH = 11;
parameter ADDR_WIDTH = 9;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arb... | 7.299402 |
module sram_exec_tb;
reg clock;
reg power1;
always #10 clock <= (clock === 1'b0);
initial begin
clock <= 0;
end
initial begin
$dumpfile("sram_exec.vcd");
$dumpvars(0, sram_exec_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (200) begin
repeat ... | 7.333427 |
module SRAM_FIFO (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull
);
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output wrfull;
wire [31:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [31:0] q... | 6.679314 |
module SRAM_FIFO (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull
);
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output wrfull;
endmodule
| 6.679314 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_fi... | 6.896868 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_fi... | 6.896868 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_fi... | 6.896868 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_fi... | 6.896868 |
module sram_fish5 #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 16,
RAM_SIZE = 65536
) (
input clk,
input we,
input en,
input [ADDR_WIDTH-1 : 0] addr,
input [DATA_WIDTH-1 : 0] data_i,
output reg [DATA_WIDTH-1 : 0] data_o
);
// Declareation of the memory cells
(* ram_style = "block" ... | 8.107337 |
module sram_for_debugging_async (
data_out,
data_in,
address,
read_enable,
write_enable
);
parameter NUM_ADDR_BITS = 1;
parameter NUM_DATA_BITS = 1;
output [NUM_DATA_BITS - 1 : 0] data_out;
input [NUM_DATA_BITS - 1 : 0] data_in;
input [NUM_ADDR_BITS - 1 : 0] address;
input read_enable;
... | 7.71909 |
module sram_histogram (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: W
clk0,
csb0,
addr0,
din0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter DATA_WIDTH = 17;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is a... | 7.728822 |
module SRAM_Image_100M (
//---------------------- Avalon -----------------------
csi_clk, //100MHz Clock
csi_reset_n,
avs_chipselect,
avs_address,
avs_read,
avs_readdata,
avs_write,
avs_writedata,
//---------------------- User Interface --------------------
coe_oSRAM_ADDR,
coe_ioS... | 6.944417 |
module SRAM_Image_BW (
//---------------------- Avalon -----------------------
csi_clk, //100MHz Clock
csi_reset_n,
avs_chipselect,
avs_address,
avs_read,
avs_readdata,
avs_write,
avs_writedata,
//---------------------- User Interface --------------------
coe_oSRAM_ADDR,
coe_ioSRA... | 6.739371 |
module SRAM_Image_UI(
//---------------------- Avalon -----------------------
csi_clk, //100MHz Clock
csi_reset_n,
avs_chipselect,
avs_address,
avs_read,
avs_readdata,
avs_write,
avs_writedata,
//---------------------- User Interface --------------------
coe_oSRAM_ADDR,
coe_ioSRAM... | 6.688935 |
module sram_imem (
write_addr, // Address Write Input
read_addr, // Address Read Input
write_data, // Data Write Input
read_data, // Data Read Output
write_en // Write Enable/Disable
);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
//---... | 6.956669 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_in... | 6.896868 |
module sram_issi_if (
d,
addr,
wbe,
en,
clk,
q,
sram_dio,
sram_addr,
sram_oe_n,
sram_ce_n,
sram_we_n,
sram_lb_n,
sram_ub_n
);
parameter DWIDTH = 16;
parameter AWIDTH = 19; //! 只有17bit有效, 2Mbit ~ 512Kb ~256k half word sram的地址只有A0-16 17bits
//naive sync sram int... | 7.662946 |
module sram_l (
input [14:0] ADDR,
inout [7:0] DATA,
input nCE,
input nOE,
input nWE
);
reg [7:0] RAMDATA[0:32767];
wire [7:0] DATA_OUT;
integer k;
initial begin
//Clean init to 0 since the speed-patched system ROM skips SRAM init
//for (k = 0; k < 32767; k = k + 1)
// RAMDATA... | 6.692954 |
module sram_l2_data (
input wire MEMCLK,
input wire RESET_N,
input wire CE,
input wire [`L2_DATA_ARRAY_HEIGHT_LOG2-1:0] A,
input wire RDWEN,
input wire [`L2_DATA_ARRAY_WIDTH-1:0] BW,
input wire [`L2_DATA_ARRAY_WIDTH-1:0] DIN,
output wire [`L2_DATA_ARRAY_WIDTH-1:0] DOUT,
input wire [`... | 6.678163 |
module sram_l2_dir (
input wire MEMCLK,
input wire RESET_N,
input wire CE,
input wire [`L2_DIR_ARRAY_HEIGHT_LOG2-1:0] A,
input wire RDWEN,
input wire [`L2_DIR_ARRAY_WIDTH-1:0] BW,
input wire [`L2_DIR_ARRAY_WIDTH-1:0] DIN,
output wire [`L2_DIR_ARRAY_WIDTH-1:0] DOUT,
input wire [`BIST_... | 6.593691 |
module sram_ldv #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 16,
RAM_SIZE = 65536
) (
input clk,
input we,
input en,
input [ADDR_WIDTH-1 : 0] addr,
input [DATA_WIDTH-1 : 0] data_i,
output reg [DATA_WIDTH-1 : 0] data_o
);
// Declareation of the memory cells
(* ram_style = "block" *)... | 8.291475 |
module sram_led_tester (
KEY,
SW,
CLOCK_50,
LEDR,
SRAM_ADDR,
SRAM_DQ,
SRAM_WE_N,
SRAM_CE_N,
SRAM_OE_N,
SRAM_UB_N,
SRAM_LB_N
);
input [3:0] KEY;
input [17:0] SW;
input CLOCK_50;
output [19:0] SRAM_ADDR;
output [17:0] LEDR;
inout [15:0] SRAM_DQ;
output SRAM_WE_N... | 7.037576 |
module sram_line_en
#(
parameter DATA_WIDTH = 128,
parameter ADDRESS_WIDTH = 7,
parameter INITIALIZE_TO_ZERO = 0
)
(
input i_clk,
input [ADDRESS_WIDTH-1:0] i_address,
input [DATA_WIDTH-1:0] i_write_data,
input i_write_enable,
output [DATA_WIDTH-1:0] o_read_data
);
wire [DATA_WIDTH-1:0] sub... | 6.963436 |
module sram_map(SRAM_ADDR, SRAM_DQ, SRAM_WE_N, SRAM_UB_N, SRAM_LB_N,
set_dq_to_dout, memwr_n, abus, dout, din, ramdisk_page,
jtag_addr, jtag_din, jtag_do, jtag_jtag, jtag_nwe);
output [17:0] SRAM_ADDR;
inout reg[15:0] SRAM_DQ;
output SRAM_WE_N;
output SRAM_UB_N;
output SRAM_LB_N;
input... | 6.57397 |
module sram_controller_tb ();
`define SRAM_ADDR_WIDTH 20
`define SRAM_DATA_WIDTH 16
reg [`SRAM_ADDR_WIDTH - 1:0] sram_addr_reg;
reg oe_n_reg, ce_n_reg, we_n_reg;
// bidirectional data bus
wire [`SRAM_DATA_WIDTH - 1:0] sram_data_inout;
reg [`SRAM_DATA_WIDTH - 1:0] data_to_write;
reg data_we;
assign sr... | 6.758857 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_op... | 6.896868 |
module sram_pack #(
parameter BASE_ADDR = 8'h00
) (
input clk,
// SRAM hardware interface
inout [ 7:0] ram_data_z,
(* IOB = "TRUE" *) output reg [23:0] ram_address,
(* IOB = "TRUE" *) output reg ram_nwe,
output ram_nce,
... | 7.466122 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_pl... | 6.896868 |
module sram_properties(i_clk, i_ce_n, i_oe_n, i_we_n, i_lb, i_ub,
i_addr, i_data, o_data);
parameter CLOCKRATE_HZ = 50_000_000;
parameter AW = 16, DW = 16;
//
parameter tRC = 12e-9;
parameter tAA = 12e-9;
parameter tCHA = 3e-9;
parameter tACE = 12e-9;
parameter tDOE = 12e-9;
parameter tHZOE = 12... | 6.519397 |
module sram_rat #(
parameter ADDRW = 5,
parameter DATAW = 1
) (
input clk,
input rst,
input rd_en1,
input [ADDRW-1:0] rd_addr1,
output reg [DATAW-1:0] rd_data1,
input rd_en2,
input [ADDRW-1:0] rd_addr2,
... | 6.530307 |
module on github
Copyright (C) 2018 IdlessChaye
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This p... | 7.164691 |
module
Copyright (C) 2018 IdlessChaye
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is ... | 6.67566 |
module sram_response_gen (
//Inputs
hclk, // AHB Clock
n_hreset, // AHB reset - Active low
// AHB interface
hsel, // AHB2APB select
htrans, // Transfer type
hsize, // AHB Access type - byte, half-word, word
hready_in, // Combined hready across all slaves
RWconflict, // Read co... | 9.353755 |
module sram_rom #(
parameter WIDTH = 32,
parameter DEPTH = 1024
) (
input clka,
input ena,
input [$clog2(DEPTH)-1:0] addra,
output [ WIDTH-1:0] douta
);
reg [WIDTH-1:0] rom[DEPTH];
reg [$clog2(DEPTH)-1:0] addr_r;
// Port A
always @(pose... | 7.162179 |
module sram_ro_tb;
reg clock;
reg power1;
reg power2;
always #10 clock <= (clock === 1'b0);
initial begin
clock <= 0;
end
initial begin
$dumpfile("sram_ro.vcd");
$dumpvars(0, sram_ro_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (25) begin
... | 6.731765 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_sc... | 6.896868 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_se... | 6.896868 |
module SRAM_sim (
ADDR,
DATA,
WE_N,
OE_N,
UB_N,
LB_N,
CE_N
);
input [17:0] ADDR;
inout [15:0] DATA;
input WE_N;
input OE_N;
input UB_N;
input LB_N;
input CE_N;
reg [15:0] MEM[0:262143];
assign DATA[7:0] = (!CE_N && !OE_N && !LB_N) ? Q[7:0] : 8'bz;
assign DATA[15:8] = (... | 6.894424 |
module sram_sp #(
parameter WIDTH = 32,
parameter DEPTH = 10234
) (
input clka,
input ena,
input wea,
input [$clog2(DEPTH)-1:0] addra,
input [ WIDTH-1:0] dina,
output [ WIDTH-1:0] douta
);
reg [WIDTH-1:0] ... | 7.120601 |
module SRAM_SP_4kx32_wrap (
Q,
CLK,
ME,
WE,
ADR,
D,
reset_n,
scan_mode
);
input [31:0] D;
input CLK;
input ME;
input [3:0] WE;
input [11:0] ADR;
input reset_n;
input scan_mode;
output [31:0] Q;
wire write_accs;
// Detect a write to any byte
assign write_accs = W... | 6.723958 |
module sram_sp_be_behave (
clk,
adr,
wr_ena,
wr_dat,
rd_ena,
rd_dat
);
//*** PARAMETER DECLARATION ****************************************************
parameter ADR_WD = 5;
parameter ADR = (1 << ADR_WD);
parameter DAT_WD = 8;
parameter COL_WD = 8;
//*** INPUT/OUTPUT DECLARATION... | 6.665006 |
module chipselects reads and writes to the sram, with 2-cycle *
* read latency and one cycle write latency. *
* *
******************************************************************************/
modul... | 7.349016 |
module sram_512w_16b (
Q,
CLK,
CEN,
WEN,
A,
D,
EMA,
EMAW,
EMAS,
TEN,
BEN,
RET1N,
STOV
);
output reg [15:0] Q;
input CLK;
input CEN;
input WEN;
input [8:0] A;
input [15:0] D;
input [2:0] EMA;
input [1:0] EMAW;
input EMAS;
input TEN;
input BEN;
... | 7.552978 |
module SRAM_sync #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 10
) (
input wire clk,
input wire [ADDR_WIDTH-1:0] ADDR,
input wire [DATA_WIDTH-1:0] DATA,
(* direct_enable = 1 *) input wire CEn,
input wire OEn,
input wire WEn,
output reg [DATA_WIDTH-1:0] Q
);
reg [DATA_WIDTH-1:0] mem[0... | 8.485738 |
module sram_sync_1r1w #(
parameter WIDTH = 16,
parameter DEPTH = 1 << 8,
parameter WRITE_GRANULE = WIDTH,
parameter R2W_FORWARDING = 0,
parameter PRELOAD_FILE = "",
parameter W_ADDR = $clog2(DEPTH) // let this default
) (
input wire clk,
input wire [ W_ADDR-1:0] waddr,
... | 7.079754 |
module SRAM_sync_init #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 10,
DATA_HEX_FILE = "dump.hex"
) (
input wire clk,
input wire [ADDR_WIDTH-1:0] ADDR,
input wire [DATA_WIDTH-1:0] DATA,
(* direct_enable = 1 *) input wire cen,
input wire we,
output reg [DATA_WIDTH-1:0] Q
);
(* ramstyl... | 7.936776 |
module SRAM_sync_noinit #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 10
) (
input wire clk,
input wire [ADDR_WIDTH-1:0] ADDR,
input wire [DATA_WIDTH-1:0] DATA,
(* direct_enable = 1 *) input wire cen,
input wire we,
output reg [DATA_WIDTH-1:0] Q
);
(* ramstyle = "no_rw_check" *) reg [DATA... | 7.156682 |
module sram_tb;
`define NULL 0
reg CLK = 0;
reg [10:0] A = 0;
reg [31:0] D = 0;
reg CEN_EXT = 0;
reg CEN_Q;
reg WEN_EXT = 1;
reg WEN_Q;
wire [31:0] Q;
integer x_file, x_scan_file; // file_handler
integer captured_data;
integer t, i, error;
reg [31:0] D_2D[63:0];
parameter run_cycle = 6... | 7.84119 |
module so that it is clearer that
// this is for testing only; it is not an SRAM size that is used in the
// Ravenna chip hardware.
//************************************************************************/
`timescale 1ns/10ps
module XSPRAMBLP_16384X32_M8P (Q, D, A, CLK, CEn, WEn, RDY);
output [31:0] Q; // RAM da... | 8.348533 |
module sram #(
parameter ADDR_WIDTH = 8,
DATA_WIDTH = 8,
DEPTH = 256,
MEMFILE = ""
) (
input wire i_clk,
input wire [ADDR_WIDTH-1:0] i_addr,
input wire i_write,
input wire [DATA_WIDTH-1:0] i_data,
output reg [DATA_WIDTH-1:0] o_data
);
reg [DATA_WIDTH-1:0] memory_array[0:DEPTH-1];
... | 7.388143 |
module SRAM_unq1
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq1
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip ... | 7.057234 |
module SRAM_unq10
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq10
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chi... | 6.5598 |
module SRAM_unq11
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq11
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chi... | 7.122281 |
module SRAM_unq12
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq12
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chi... | 7.067232 |
module SRAM_unq13
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq13
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chi... | 7.190063 |
module SRAM_unq14
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq14
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chi... | 7.704758 |
module SRAM_unq15
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq15
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chi... | 7.681546 |
module SRAM_unq16
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq16
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chi... | 7.597338 |
module SRAM_unq2
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq2
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip ... | 7.017644 |
module SRAM_unq3
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq3
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip ... | 7.043515 |
module SRAM_unq4
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq4
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip ... | 7.435426 |
module SRAM_unq5
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq5
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip ... | 6.988692 |
module SRAM_unq6
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq6
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip ... | 6.716065 |
module SRAM_unq7
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq7
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip ... | 6.962574 |
module SRAM_unq8
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq8
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip ... | 7.289581 |
module SRAM_unq9
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq9
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip ... | 6.622155 |
module SRAM_V #(
parameter mem_size = 1024,
parameter word_size = 8,
parameter addr_size = 10
) (
d_in,
i_clk,
rw,
addr_in,
data_out
);
input i_clk;
input wire [word_size-1:0] d_in; ///data input //
input rw; ///read/write , if rw => 0 , write to memory else read from the memor... | 8.132946 |
module sram_w (
input clk,
w,
rst,
cs,
input [11:0] addr,
input [7:0] data_in,
output reg [7:0] data_out
);
reg signed [7:0] memory[2047:0]; //动态参数
always @(posedge clk, negedge rst) begin
if (!rst) data_out <= 8'd0;
else
case (cs)
1: begin
if (w == 1) ... | 7.812766 |
module sram_width_converter #(
parameter aw = 10
) (
input wire i_clk,
//8-bit Subservient interface
input wire [aw-1:0] i_sram_waddr,
input wire [7:0] i_sram_wdata,
input wire i_sram_wen,
input wire [aw-1:0] i_sram_raddr,
output wire [7:0] o_sram_rdata,
input wire i_sram_ren,
//... | 7.752413 |
module sram_wrapper (
input wire clk,
input wire rstn,
// data bus interface
input wire [ `XLEN-1:0] d_addr, // byte addr
input wire d_w_rb,
input wire [$clog2(`BUS_ACC_CNT)-1:0] d_acc,
output wire [ `BUS_WIDTH-1:0] d_rdata,
inp... | 6.559872 |
module SRAM_Wrapper_top #(
parameter WIDTH_WB_DATA = 32,
parameter WIDTH_ADD = 32,
parameter IMC_OUT_WIDTH = 16, // Deepak -30/12/22 -edited to 16 bit(previously 64 bit)for MPW8
parameter SRAM_OUT_WIDTH = 16,
parameter MEM_ROW = 16
) (
inout VCLP, // connect to Analog IO
inout EN, //... | 7.345005 |
module on github
Copyright (C) 2018 IdlessChaye
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This p... | 7.164691 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sran1
#... | 6.896868 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sran2
#... | 6.896868 |
module srash (
a,
sh,
b
) /* synthesis syn_builtin_du = "weak" */;
parameter A_width = 64;
parameter SH_width = 6;
input signed [A_width:0] a;
input [SH_width-1:0] sh;
output wire [A_width:0] b;
assign b = a >>> sh;
endmodule
| 7.197473 |
module srasll (
u0,
u1,
s0,
s1,
y0,
y1,
y2,
y3,
y4,
y5,
y6,
y7,
x0,
x1,
x2,
x3,
x4,
x5,
x6,
x7
);
input [4:0] u0;
input [2:0] u1;
input signed [3:0] s0;
input signed [5:0] s1;
output [15:0] y0;
output [15:0] y1;
output [15:0... | 6.857687 |
module SRA_1_4bit (
out,
cin,
cout,
a
); //select=0 leftshift, select=1 rightshift
input [3:0] a;
input cin;
output [3:0] out;
output cout;
Shift_1_4bit S (
out,
cin,
cout,
a,
1'b1
);
endmodule
| 6.784122 |
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