code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sram_byte_en
#(
parameter DATA_WIDTH = 128,
parameter ADDRESS_WIDTH = 7
)
(
input i_clk,
input [DATA_WIDTH-1:0] i_write_data,
input i_write_enable,
input [ADDRESS_WIDTH-1:0] i_address,
input [DATA_WIDTH/8-1:0] i_byte_enable,
output [DATA_WIDTH-1:0] o_read_data
);
wire [DATA_WIDTH-1:0] sub_wire0;
assign o_read_data = sub_wire0;
altsyncram altsyncram_component (
.address_a (i_address),
.byteena_a (i_byte_enable),
.clock0 (i_clk),
.data_a (i_write_data),
.wren_a (i_write_enable),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2**ADDRESS_WIDTH,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = ADDRESS_WIDTH,
altsyncram_component.width_a = DATA_WIDTH,
altsyncram_component.width_byteena_a = DATA_WIDTH/8;
endmodule
| 7.273859 |
module sram_byte_en_model #(
parameter NB_COL = 4, // Specify number of columns (number of bytes)
parameter COL_WIDTH = 8, // Specify column width (byte width, typically 8 or 9)
parameter RAM_DEPTH = 8192, // Specify RAM depth (number of entries)
parameter INIT_FILE = "./firmware.hex" // Specify name/location of RAM initialization file if using one (leave blank if not)
//parameter INIT_FILE = "./fw.hex" // Specify name/location of RAM initialization file if using one (leave blank if not)
) (
input [clogb2(RAM_DEPTH-1)-1:0] addra, // Address bus, width determined from RAM_DEPTH
input [(NB_COL*COL_WIDTH)-1:0] dina, // RAM input data
input clka, // Clock
input [NB_COL-1:0] wea, // Byte-write enable
input ena, // RAM Enable, for additional power savings, disable port when not in use
output [(NB_COL*COL_WIDTH)-1:0] douta // RAM output data
);
reg [(NB_COL*COL_WIDTH)-1:0] mem[RAM_DEPTH-1:0] /*synthesis syn_ramstyle = "block_ram" */;
reg [(NB_COL*COL_WIDTH)-1:0] q = {(NB_COL * COL_WIDTH) {1'b0}};
// The following code either initializes the memory values to a specified file or to all zeros to match hardware
generate
if (INIT_FILE != "") begin : use_init_file
initial $readmemh(INIT_FILE, mem, 0, RAM_DEPTH - 1);
end else begin : init_bram_to_zero
integer ram_index;
initial
for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1)
mem[ram_index] = {(NB_COL * COL_WIDTH) {1'b0}};
end
endgenerate
always @(posedge clka)
if (ena) q <= mem[addra];
else q <= 'h0;
generate
genvar i;
for (i = 0; i < NB_COL; i = i + 1) begin : byte_write
always @(posedge clka)
if (ena)
if (wea[i]) begin
mem[addra][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= dina[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
end
end // for
endgenerate
// The following is a 1 clock cycle read latency at the cost of a longer clock-to-out timing
assign douta = q;
// assign douta = ena ? mem[addra] : {(NB_COL*COL_WIDTH){1'b0}};
// The following function calculates the address width based on specified RAM depth
function integer clogb2;
input integer depth;
for (clogb2 = 0; depth > 0; clogb2 = clogb2 + 1) depth = depth >> 1;
endfunction
endmodule
| 7.409979 |
module sram_code #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input clk,
input en,
input [ADDR_WIDTH-1:0] addr,
output [DATA_WIDTH-1:0] dout
);
localparam SRAM_SIZE = (1 << (ADDR_WIDTH - 1));
reg [DATA_WIDTH-1:0] sram[SRAM_SIZE-1:0];
reg [DATA_WIDTH-1:0] dout_reg;
initial begin
$readmemh("../../Presim/code.txt", sram);
end
always @(posedge clk) begin
if (!en) dout_reg <= 0;
else begin
dout_reg <= sram[addr];
end
end
assign dout = dout_reg;
endmodule
| 7.579163 |
module SRAM_Controller64 (
input clk,
input rst,
// Golden Inputs
input write_en,
read_en,
input [31:0] address,
input [31:0] writeData,
// WB
output signed [63:0] readData,
// Freeze
output ready,
// SRAM
inout signed [63:0] SRAM_DQ,
output [16:0] SRAM_ADDR,
output SRAM_UB_N,
output SRAM_LB_N,
output SRAM_WE_N,
output SRAM_CE_N,
output SRAM_OE_N
);
assign {SRAM_UB_N, SRAM_LB_N, SRAM_CE_N, SRAM_OE_N} = 4'b0; // Active
// Fix Address
wire [`ADDRESS_LEN - 1:0] address_1024;
wire [16:0] physical_address;
assign address_1024 = address - 1024;
assign physical_address = address_1024[17:2]; // Memory Adr Starts From 1024 and must be multiplication of 4
// Controller Regs
wire [1:0] ps, ns;
parameter S_IDLE = 2'b00, S_READ = 2'b01, S_WRITE = 2'b10; // States
Regular_Register #(
.SIZE(2)
) ps_reg (
.q (ps),
.d (ns),
.clk(clk),
.rst(rst)
);
wire [2:0] counter, next_counter;
Regular_Register #(
.SIZE(3)
) counter_reg (
.q (counter),
.d (next_counter),
.clk(clk),
.rst(rst)
);
// ns Reg
assign ns = (ps == S_IDLE && read_en) ? S_READ :
(ps == S_IDLE && write_en) ? S_WRITE :
(ps == S_READ && counter != `SRAM_WAIT_CYCLES) ? S_READ :
(ps == S_WRITE && counter != `SRAM_WAIT_CYCLES) ? S_WRITE :
S_IDLE;
// Counter
assign next_counter = (ps == S_READ && counter != `SRAM_WAIT_CYCLES) ? counter + 1 :
(ps == S_WRITE && counter != `SRAM_WAIT_CYCLES) ? counter + 1 :
3'b0;
assign SRAM_ADDR = physical_address;
assign SRAM_DQ = (ps == S_WRITE && counter != `SRAM_WAIT_CYCLES) ? writeData : 64'bz;
assign SRAM_WE_N = (ps == S_WRITE && counter != `SRAM_WAIT_CYCLES) ? 1'b0 : 1'b1; // 0 is Active
assign readData = SRAM_DQ;
assign ready = (ps == S_READ && counter != `SRAM_WAIT_CYCLES) ? 1'b0 :
(ps == S_WRITE && counter != `SRAM_WAIT_CYCLES) ? 1'b0 :
((ps == S_IDLE) && (read_en || write_en)) ? 1'b0 :
1'b1;
always @(posedge clk) begin
if (read_en && counter == `SRAM_WAIT_CYCLES - 1)
$display("READ mem[%d] = %d", physical_address, SRAM_DQ);
if (write_en && counter == `SRAM_WAIT_CYCLES - 1)
$display("WRITE mem[%d] = %d", physical_address, SRAM_DQ);
end
endmodule
| 7.111397 |
module SRAM_CONTROLLER_NEOGEO (
input clk,
input reset_n,
output [16:0] sram_a,
inout [15:0] sram_dq,
output sram_oe_n,
output sram_we_n,
output sram_ub_n,
output sram_lb_n,
input [15:0] M68K_ADDR_RAM,
input [15:0] M68K_DATA_RAM,
output [15:0] SRAM_OUT,
input nWRL,
input nWRU,
input sram_nWWL,
input sram_nWWU
);
// this will clean the SRAM everytime it is booted. Has to run at 12mhz as this is just a counter and direct access.
reg [19:0] reset_counter = 0;
always @(posedge clk) begin
reset_counter <= reset_counter + 1;
end
assign sram_a = reset_n ? {2'b0, M68K_ADDR_RAM[15:1]} : reset_counter[16:1];
assign sram_dq[7:0] = reset_n ? (sram_nWWL ? 8'bzz : M68K_DATA_RAM[7:0]) : reset_counter[10:3];
assign sram_dq[15:8] = reset_n ? (sram_nWWU ? 8'bzz : M68K_DATA_RAM[15:8]) : reset_counter[11:4];
assign sram_oe_n = reset_n ? &{nWRL, nWRU} : 1'b1;
assign sram_we_n = reset_n ? &{sram_nWWL, sram_nWWU} : 1'b0;
assign sram_ub_n = reset_n ? &{sram_nWWU, nWRU} : 1'b0;
assign sram_lb_n = reset_n ? &{sram_nWWL, nWRL} : 1'b0;
assign SRAM_OUT = sram_dq;
endmodule
| 7.484689 |
module test_sramcontroller ();
parameter CLK_PHASE = 5;
parameter MAX_MESSAGE_LENGTH = 8;
parameter SYMBOL_WIDTH = 32;
reg clk;
reg reset;
reg enable_sig;
reg rw_sig;
reg [$clog2(MAX_MESSAGE_LENGTH)-1:0] addr_sig;
reg [SYMBOL_WIDTH-1:0] write_data_sig;
wire [SYMBOL_WIDTH-1:0] sram_out_signal;
wire dat_ready_sig;
wire [SYMBOL_WIDTH-1:0] out_data_sig;
wire sram_enable_sig;
wire sram_rw_sig;
wire [SYMBOL_WIDTH-1:0] sram_wdata_sig;
wire [$clog2(MAX_MESSAGE_LENGTH)-1:0] sram_addr_sig;
initial begin
$dumpfile("sram_controller_test.vcd");
$dumpvars;
clk = 1'b0;
reset = 1;
enable_sig = 0;
rw_sig = 0;
addr_sig = {$clog2(MAX_MESSAGE_LENGTH) {1'b0}};
write_data_sig = {SYMBOL_WIDTH{1'b0}};
#5 reset = 0;
addr_sig = 3'd1;
enable_sig = 1'b1;
#10 addr_sig = 3'd2;
enable_sig = 1'b1;
#10 enable_sig = 1'b0;
#10 enable_sig = 1'b1;
rw_sig = 1'b1;
addr_sig = 3'd3;
write_data_sig = 32'h56789ABC;
#10 enable_sig = 1'b1;
rw_sig = 1'b0;
addr_sig = 3'd3;
#10 enable_sig = 1'b0;
rw_sig = 1'b0;
#100 $finish;
end
always #CLK_PHASE clk = ~clk;
sram #(
.ADDR_WIDTH($clog2(MAX_MESSAGE_LENGTH)),
.DATA_WIDTH(SYMBOL_WIDTH),
.MEM_INIT_FILE("../../HDL/run_s/sram_controller_test.dat")
) msg_mem (
.address(sram_addr_sig),
.write_data(sram_wdata_sig),
.read_data(sram_out_signal),
.enable(sram_enable_sig),
.write(sram_rw_sig),
.clock(clk)
);
sram_controller #(
.ADDR_WIDTH($clog2(MAX_MESSAGE_LENGTH)),
.DATA_WIDTH(SYMBOL_WIDTH)
) message_mem_sram_controller (
//Input to the SRAM Controller
.clock ( clk ),
.reset ( reset ),
.memctrl_enable ( enable_sig ),
.memctrl_rw ( rw_sig ),
.memctrl_addr ( addr_sig ),
.memctrl_write_data ( write_data_sig ),
//Input from the SRAM to SRAM Controller
.sram_out_data ( sram_out_signal ),
//Output from the SRAM Controller
.dat_ready ( dat_ready_sig ),
.memctrl_out_data ( out_data_sig ),
//Output from the SRAM Controller to SRAM
.sram_enable ( sram_enable_sig ),
.sram_rw ( sram_rw_sig ),
.sram_write_data ( sram_wdata_sig ),
.sram_addr ( sram_addr_sig )
);
endmodule
| 6.537707 |
module sram_fsm (
output wire CE_N,
output wire LB_N,
output wire OE_N,
output wire UB_N,
output wire WE_N,
output wire rd_valid,
output wire wr_valid,
input wire clk,
input wire rd_en,
input wire reset,
input wire wr_en
);
// state bits
parameter IDLE = 7'b0011111, // wr_valid=0 rd_valid=0 WE_N=1 UB_N=1 OE_N=1 LB_N=1 CE_N=1
READ = 7'b0010000, // wr_valid=0 rd_valid=0 WE_N=1 UB_N=0 OE_N=0 LB_N=0 CE_N=0
READ_OK = 7'b0110000, // wr_valid=0 rd_valid=1 WE_N=1 UB_N=0 OE_N=0 LB_N=0 CE_N=0
WRITE = 7'b0010100, // wr_valid=0 rd_valid=0 WE_N=1 UB_N=0 OE_N=1 LB_N=0 CE_N=0
WRITE_OK = 7'b1000000; // wr_valid=1 rd_valid=0 WE_N=0 UB_N=0 OE_N=0 LB_N=0 CE_N=0
reg [6:0] state;
reg [6:0] nextstate;
// comb always block
always @* begin
// Warning I2: Neither implied_loopback nor default_state_is_x attribute is set on state machine - defaulting to implied_loopback to avoid latches being inferred
nextstate = state; // default to hold value because implied_loopback is set
case (state)
IDLE: begin
// Warning P3: State IDLE has multiple exit transitions, and transition trans0 has no defined priority
// Warning P3: State IDLE has multiple exit transitions, and transition trans3 has no defined priority
// Warning P3: State IDLE has multiple exit transitions, and transition trans6 has no defined priority
if (rd_en && ~wr_en) begin
nextstate = READ;
end else if (wr_en) begin
nextstate = WRITE;
end else if (~rd_en && ~wr_en) begin
nextstate = IDLE;
end
end
READ: begin
begin
nextstate = READ_OK;
end
end
READ_OK: begin
begin
nextstate = IDLE;
end
end
WRITE: begin
begin
nextstate = WRITE_OK;
end
end
WRITE_OK: begin
begin
nextstate = IDLE;
end
end
endcase
end
// Assign reg'd outputs to state bits
assign CE_N = state[0];
assign LB_N = state[1];
assign OE_N = state[2];
assign UB_N = state[3];
assign WE_N = state[4];
assign rd_valid = state[5];
assign wr_valid = state[6];
// sequential always block
always @(posedge clk) begin
if (reset) state <= IDLE;
else state <= nextstate;
end
// This code allows you to see state names in simulation
`ifndef SYNTHESIS
reg [63:0] statename;
always @* begin
case (state)
IDLE: statename = "IDLE";
READ: statename = "READ";
READ_OK: statename = "READ_OK";
WRITE: statename = "WRITE";
WRITE_OK: statename = "WRITE_OK";
default: statename = "XXXXXXXX";
endcase
end
`endif
endmodule
| 8.198219 |
module sram_core_sword (
input wire clk, // main clock
input wire rst, // synchronous reset
input wire cs, // chip select
input wire we, // write enable
input wire [ADDR_BITS-1:2] addr, // address
input wire [3:0] sel, // byte select
input wire burst, // burst mode flag
input wire [31:0] din, // data to write
output reg [31:0] dout, // data read in
output reg busy, // busy flag
output reg ack, // acknowledge
// SRAM interfaces
output reg sram_ce_n,
output reg sram_oe_n,
output reg sram_we_n,
output reg [ADDR_BITS-1:2] sram_addr,
input wire [47:0] sram_din,
output reg [47:0] sram_dout
);
`include "function.vh"
parameter CLK_FREQ = 100, // main clock frequency in MHz
ADDR_BITS = 22; // address length for SRAM
localparam S_IDLE = 0, // idle
S_START = 1, // set address and read operation
S_READ = 2, // read data
S_WRITE = 3; // write data
reg [1:0] state = 0;
reg [1:0] next_state;
always @(*) begin
next_state = 0;
case (state)
S_IDLE: begin
if (cs) next_state = S_START;
else next_state = S_IDLE;
end
S_START: begin
if (~we) next_state = S_READ;
else next_state = S_WRITE;
end
S_READ: begin
if (cs && burst) next_state = S_START;
else next_state = S_IDLE;
end
S_WRITE: begin
if (cs && burst) next_state = S_START;
else next_state = S_IDLE;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state <= 0;
end else begin
state <= next_state;
end
end
reg bursting = 0;
always @(posedge clk) begin
busy <= 0;
ack <= 0;
sram_ce_n <= 1;
sram_oe_n <= 1;
sram_we_n <= 1;
sram_addr <= 0;
sram_dout <= 0;
bursting <= 0;
dout <= 0;
if (~rst)
case (next_state)
S_IDLE: begin
bursting <= 0;
end
S_START: begin
busy <= 1;
sram_ce_n <= 0;
sram_oe_n <= 0;
sram_addr <= bursting ? sram_addr + 1'h1 : addr;
bursting <= cs & burst;
ack <= we; // acknowledge must be uttered earlier than normal as we need one clock to fetch next data
end
S_READ: begin
busy <= 1;
sram_ce_n <= 0;
sram_oe_n <= 0;
sram_addr <= sram_addr;
bursting <= cs & burst;
dout <= sram_din;
ack <= 1;
end
S_WRITE: begin
busy <= 1;
sram_ce_n <= 0;
sram_we_n <= 0;
sram_addr <= sram_addr;
sram_dout[31:24] <= sel[3] ? din[31:24] : sram_din[31:24];
sram_dout[23:16] <= sel[2] ? din[23:16] : sram_din[23:16];
sram_dout[15:8] <= sel[1] ? din[15:8] : sram_din[15:8];
sram_dout[7:0] <= sel[0] ? din[7:0] : sram_din[7:0];
bursting <= cs & burst;
end
endcase
end
endmodule
| 7.719674 |
module hold (
input Clk,
input Reset,
input In,
output Out
);
//
reg [1:0] Cnt;
reg CntEn;
always @(posedge Clk or posedge Reset) begin
if (Reset) CntEn <= #`dh 0;
else begin
if (In) CntEn <= #`dh 1;
else if (Cnt == 3) CntEn <= #`dh 0;
end
end
//
always @(posedge Clk or posedge Reset) begin
if (Reset) Cnt <= #`dh 0;
else if (CntEn) Cnt <= #`dh Cnt + 1'b1;
end
//
assign Out = CntEn;
//
endmodule
| 6.555699 |
module interact with the external sram
/// write process takes 3 clk cycles
/// read process asynchronous
///@port clk 100mhz
///@port rst_n active-low reset
///@port {input} wr_req active-high prior to rd_req, writes $write_data into sram with the address specified by write_addr
///@port {input} rd_req simply set rd_req=~wr_req
///@port {input}[15:0] write_data
///@port {output}[15:0] read_data
///@port {input} [18:0] write_addr
///@port {input} [18:0] read_addr
module sram_ctrl(
//user interface
clk,
rst_n,
wr_req,
rd_req,
write_data,
read_data,
write_addr,
read_addr,
//hardware interface
sram_we_n, //output
sram_oe_n, //output
sram_ce_n, //output
sram_addr, //output
sram_data, //inout
sram_lb_n, //output
sram_ub_n //output
,state_o
);
input clk;
input rst_n;
input wr_req;
input rd_req;
input [15:0] write_data;
output reg [15:0] read_data;
input [18:0] write_addr;
input [18:0] read_addr;
inout [15:0] sram_data;
output sram_lb_n;
output sram_ub_n;
output reg sram_we_n;
output reg sram_oe_n;
output sram_ce_n;
output reg [18:0] sram_addr;
parameter IDLE = 3'b000;
parameter WRT0 = 3'b001;
parameter WRT1 = 3'b010;
parameter WRT2 = 3'b011;
parameter READ = 3'b100;
reg [2:0]state_c;
reg [2:0]state_n;
reg isWrite;
reg [15:0] sync_write_data;
reg [18:0] sync_write_addr;
assign sram_data = isWrite?sync_write_data:16'bzzzz_zzzz_zzzz_zzzz;
assign sram_ce_n = 0;
assign sram_lb_n = 0;
assign sram_ub_n = 0;
always@(posedge clk, negedge rst_n)begin
if(~rst_n) state_c<=IDLE;
else state_c<=state_n;
end
always@(state_c,state_n, wr_req, rd_req)begin
case(state_c)
IDLE:
if(wr_req) state_n=WRT0;
else if(rd_req) state_n=READ;
else state_n=IDLE;
WRT0: state_n=WRT1;
WRT1: state_n=WRT2;
WRT2: state_n=IDLE;
READ:
begin
if(~wr_req) state_n=READ;
else state_n=IDLE;
end
default: state_n=IDLE;
endcase
end
always@(posedge clk, negedge rst_n)
begin
if(~rst_n) begin sync_write_data <= 0; sync_write_addr <= 0; end
else if(state_c == WRT0) begin sync_write_data <= write_data; sync_write_addr <= write_addr; end
end
always@(posedge clk, negedge rst_n)
begin
if(~rst_n) sram_addr<=19'd0;
else if(state_c==WRT0) sram_addr<=sync_write_addr;
else if(state_c==READ) sram_addr<=read_addr;
end
always@(posedge clk, negedge rst_n)
begin
if(~rst_n) read_data<=16'd0;
else if((state_c==READ)) read_data<=sram_data;
end
always@(posedge clk, negedge rst_n)
begin
if(~rst_n) isWrite<=1'b0;
else if(state_c==WRT0) isWrite<=1'b1;
else if(state_c==WRT1) isWrite<=1'b1;
else if(state_c==WRT2) isWrite<=1'b1;
else if(state_c==READ) isWrite<=1'b0;
end
always@(posedge clk, negedge rst_n)
begin
if(~rst_n) sram_oe_n<=1'b1;
else if(state_c==READ) sram_oe_n<=1'b0;
else sram_oe_n<=1'b1;
end
always@(posedge clk, negedge rst_n)
begin
if(~rst_n) sram_we_n<=1'b1;
else if(state_c==WRT1 | state_c==WRT2) sram_we_n<=1'b0;
else sram_we_n<=1'b1;
end
output [1:0] state_o;
assign state_o=state_c[1:0];
endmodule
| 7.774385 |
module sram_ctrl2 (
input wire clk, // Clock signal
input wire reset, // Reset signal
input wire rw, // With this signal, we select reading or writing operation
input wire [20:0] addr, // Address bus
input wire [ 7:0] data_f2s, // Data to be writteb in the SRAM
output reg [7:0] data_s2f_r, // It is the 8-bit registered data retrieved from the SRAM (the -s2f suffix stands for SRAM to FPGA)
output wire [20:0] ad, // Address bus
output wire we_n, // Write enable (active-low)
output wire oe_n, // Output enable (active-low)
inout wire [7:0] dio_a, // Data bus
output wire ce_a_n // Chip enable (active-low). Disables or enables the chip.
);
assign ce_a_n = 1'b0;
assign oe_n = 1'b0;
assign we_n = rw;
assign ad = addr;
assign dio_a = (rw == 1'b1) ? 8'hZZ : data_f2s;
always @(posedge clk) begin
if (rw == 1'b1) data_s2f_r <= dio_a;
end
endmodule
| 6.903876 |
module sram_data #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input clk,
input en,
input [ 3:0] we,
input [ADDR_WIDTH-1:0] addr,
input [DATA_WIDTH-1:0] din,
output [DATA_WIDTH-1:0] dout
);
localparam SRAM_SIZE = (1 << (ADDR_WIDTH - 1));
reg [DATA_WIDTH-1:0] sram[SRAM_SIZE-1:0];
reg [DATA_WIDTH-1:0] dout_reg;
always @(posedge clk) begin
if (!en) dout_reg <= 0;
else begin
dout_reg <= sram[addr];
sram[addr][7:0] <= we[0] ? din[7:0] : sram[addr][7:0];
sram[addr][15:8] <= we[1] ? din[15:8] : sram[addr][15:8];
sram[addr][23:16] <= we[2] ? din[23:16] : sram[addr][23:16];
sram[addr][31:24] <= we[3] ? din[31:24] : sram[addr][31:24];
end
end
assign dout = dout_reg;
endmodule
| 7.69927 |
module sram_data_collector #(
parameter NUM_RULE_BYTES = 48,
parameter ENTRY_DATA_WIDTH = 128,
parameter ENTRY_ADDR_WIDTH = 15,
parameter FLIP_BYTE_ORDER = 1, // flip the bytes ordering of the lookup/data
parameter SRAM_ADDR_WIDTH = 19,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH / 8
) ( // --- SRAM Interface
input rd_vld,
input [DATA_WIDTH-1:0] rd_data,
// --- Lookup results
output [ENTRY_DATA_WIDTH-1:0] entry_data,
output reg [ DATA_WIDTH-1:0] entry_counters,
output reg entry_data_vld,
// --- Misc
input reset,
input clk
);
`LOG2_FUNC
`CEILDIV_FUNC
//-------------------- Internal Parameters ------------------------
localparam NUM_RULE_WORDS = ceildiv(NUM_RULE_BYTES * 8, DATA_WIDTH);
localparam NUM_DATA_WORDS = ceildiv(ENTRY_DATA_WIDTH, DATA_WIDTH);
localparam WAIT_FOR_DATA = 0;
localparam COLLECT_DATA_WORDS = 1;
//---------------------- Wires and regs----------------------------
reg state;
reg [log2(NUM_DATA_WORDS):0] count;
wire [log2(NUM_DATA_WORDS):0] count_plus_1;
reg [ DATA_WIDTH-1:0] entry_data_words[NUM_DATA_WORDS-1:0];
wire [ ENTRY_DATA_WIDTH-1:0] entry_data_int;
//-------------------------- Logic --------------------------------
assign count_plus_1 = count + 1'b1;
generate
genvar i;
for (i = 0; i < NUM_DATA_WORDS - 1; i = i + 1) begin : gen_data_words
assign entry_data_int[(i+1)*DATA_WIDTH-1:i*DATA_WIDTH] = entry_data_words[i];
end
assign entry_data_int[ENTRY_DATA_WIDTH-1:(NUM_DATA_WORDS-1)*DATA_WIDTH]
= entry_data_words[NUM_DATA_WORDS-1];
if (FLIP_BYTE_ORDER) begin
for (i = 0; i < ENTRY_DATA_WIDTH / 8; i = i + 1) begin : swap_data_bytes
assign entry_data[8*i+7:8*i] = entry_data_int[ENTRY_DATA_WIDTH-1-i*8:ENTRY_DATA_WIDTH-8-i*8];
end
end else begin
assign entry_data = entry_data_int;
end
endgenerate
always @(posedge clk) begin
if (reset) begin
state <= WAIT_FOR_DATA;
entry_data_vld <= 1'b0;
end else begin
entry_data_vld <= 1'b0;
case (state)
WAIT_FOR_DATA: begin
if (rd_vld) begin
/* first word is the counters word */
entry_counters <= rd_data;
state <= COLLECT_DATA_WORDS;
count <= 0;
end
end
COLLECT_DATA_WORDS: begin
if (rd_vld) begin
if (count >= NUM_DATA_WORDS - 1) begin
state <= WAIT_FOR_DATA;
entry_data_vld <= 1'b1;
end
entry_data_words[count] <= rd_data;
count <= count_plus_1;
end // if (rd_rdy)
end
endcase // case(state)
end // else: !if(reset)
end // always @ (posedge clk)
endmodule
| 7.515567 |
module SRAM_DATA_IO (
Data,
Y,
Trien,
PAD
);
input [15:0] Data;
output [15:0] Y;
input Trien;
inout [15:0] PAD;
BIBUF_LVCMOS33 \BIBUF_LVCMOS33[5] (
.PAD(PAD[5]),
.D (Data[5]),
.E (Trien),
.Y (Y[5])
);
BIBUF_LVCMOS33 \BIBUF_LVCMOS33[0] (
.PAD(PAD[0]),
.D (Data[0]),
.E (Trien),
.Y (Y[0])
);
BIBUF_LVCMOS33 \BIBUF_LVCMOS33[14] (
.PAD(PAD[14]),
.D (Data[14]),
.E (Trien),
.Y (Y[14])
);
BIBUF_LVCMOS33 \BIBUF_LVCMOS33[11] (
.PAD(PAD[11]),
.D (Data[11]),
.E (Trien),
.Y (Y[11])
);
BIBUF_LVCMOS33 \BIBUF_LVCMOS33[12] (
.PAD(PAD[12]),
.D (Data[12]),
.E (Trien),
.Y (Y[12])
);
BIBUF_LVCMOS33 \BIBUF_LVCMOS33[9] (
.PAD(PAD[9]),
.D (Data[9]),
.E (Trien),
.Y (Y[9])
);
BIBUF_LVCMOS33 \BIBUF_LVCMOS33[3] (
.PAD(PAD[3]),
.D (Data[3]),
.E (Trien),
.Y (Y[3])
);
BIBUF_LVCMOS33 \BIBUF_LVCMOS33[4] (
.PAD(PAD[4]),
.D (Data[4]),
.E (Trien),
.Y (Y[4])
);
BIBUF_LVCMOS33 \BIBUF_LVCMOS33[13] (
.PAD(PAD[13]),
.D (Data[13]),
.E (Trien),
.Y (Y[13])
);
BIBUF_LVCMOS33 \BIBUF_LVCMOS33[1] (
.PAD(PAD[1]),
.D (Data[1]),
.E (Trien),
.Y (Y[1])
);
BIBUF_LVCMOS33 \BIBUF_LVCMOS33[6] (
.PAD(PAD[6]),
.D (Data[6]),
.E (Trien),
.Y (Y[6])
);
BIBUF_LVCMOS33 \BIBUF_LVCMOS33[8] (
.PAD(PAD[8]),
.D (Data[8]),
.E (Trien),
.Y (Y[8])
);
BIBUF_LVCMOS33 \BIBUF_LVCMOS33[7] (
.PAD(PAD[7]),
.D (Data[7]),
.E (Trien),
.Y (Y[7])
);
BIBUF_LVCMOS33 \BIBUF_LVCMOS33[2] (
.PAD(PAD[2]),
.D (Data[2]),
.E (Trien),
.Y (Y[2])
);
BIBUF_LVCMOS33 \BIBUF_LVCMOS33[15] (
.PAD(PAD[15]),
.D (Data[15]),
.E (Trien),
.Y (Y[15])
);
BIBUF_LVCMOS33 \BIBUF_LVCMOS33[10] (
.PAD(PAD[10]),
.D (Data[10]),
.E (Trien),
.Y (Y[10])
);
endmodule
| 6.516769 |
module sram_data_reader #(
parameter NUM_RULE_BYTES = 48,
parameter ENTRY_DATA_WIDTH = 128,
parameter ENTRY_ADDR_WIDTH = 15,
parameter SRAM_ADDR_WIDTH = 19,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH / 8
) ( // --- Interface to rule checker
input [ENTRY_ADDR_WIDTH-1:0] found_entry_hash,
input entry_hit,
// --- SRAM Interface
input rd_rdy,
output reg [SRAM_ADDR_WIDTH-1:0] rd_addr,
output reg rd_req,
// --- Misc
input reset,
input clk
);
`LOG2_FUNC
`CEILDIV_FUNC
//-------------------- Internal Parameters ------------------------
localparam NUM_RULE_WORDS = ceildiv(NUM_RULE_BYTES * 8, DATA_WIDTH);
localparam NUM_DATA_WORDS = ceildiv(ENTRY_DATA_WIDTH, DATA_WIDTH);
localparam ENTRY_IDX_WIDTH = SRAM_ADDR_WIDTH - ENTRY_ADDR_WIDTH;
localparam WAIT_FOR_HIT = 0;
localparam READ_DATA_WORDS = 1;
//---------------------- Wires and regs----------------------------
reg hash_fifo_rd_en;
wire [ ENTRY_ADDR_WIDTH-1:0] dout_hash;
reg state;
reg [log2(NUM_DATA_WORDS):0] count;
wire [log2(NUM_DATA_WORDS):0] count_plus_1;
wire [ SRAM_ADDR_WIDTH-1:0] rd_addr_plus_1;
//------------------------- Modules -------------------------------
fallthrough_small_fifo #(
.WIDTH(ENTRY_ADDR_WIDTH),
.MAX_DEPTH_BITS(1)
) hashes_fifo (
.din (found_entry_hash),
.wr_en (entry_hit),
.rd_en (hash_fifo_rd_en),
.dout (dout_hash),
.full (),
.prog_full (),
.nearly_full(),
.empty (hash_fifo_empty),
.reset (reset),
.clk (clk)
);
//-------------------------- Logic --------------------------------
assign rd_addr_plus_1 = rd_addr + 1'b1;
assign count_plus_1 = count + 1'b1;
always @(posedge clk) begin
if (reset) begin
rd_req <= 0;
state <= WAIT_FOR_HIT;
hash_fifo_rd_en <= 0;
end else begin
// defaults
rd_req <= 0;
hash_fifo_rd_en <= 0;
case (state)
WAIT_FOR_HIT: begin
if (!hash_fifo_empty && rd_rdy) begin
/* first word is the counters word */
rd_addr <= {dout_hash, NUM_RULE_WORDS[ENTRY_IDX_WIDTH-1:0]};
rd_req <= 1'b1;
state <= READ_DATA_WORDS;
count <= 0;
hash_fifo_rd_en <= 1'b1;
end
end
READ_DATA_WORDS: begin
if (rd_rdy) begin
if (count >= NUM_DATA_WORDS - 1) begin
state <= WAIT_FOR_HIT;
end
rd_addr <= rd_addr_plus_1;
rd_req <= 1'b1;
count <= count_plus_1;
end // if (rd_rdy)
end
endcase // case(state)
end // else: !if(reset)
end // always @ (posedge clk)
endmodule
| 8.007721 |
module cde_sram_def #(
parameter ADDR = 10,
WIDTH = 8,
WORDS = 1024,
WRITETHRU = 0,
DEFAULT = {WIDTH{1'b1}},
INIT_FILE = "NONE",
INSTANCE_NAME = "U1"
) (
input wire clk,
input wire cs,
input wire rd,
input wire wr,
input wire [ ADDR-1 : 0] addr,
input wire [WIDTH-1 : 0] wdata,
output reg [WIDTH-1 : 0] rdata
);
// Memory Array
reg [WIDTH-1:0] mem[0:WORDS-1];
// If used as Rom then load a memory image at startup
initial begin
if (INIT_FILE == "NONE") begin
end else begin
$readmemh(INIT_FILE, mem);
end
end
// Write function
always @(posedge clk) if (wr && cs) mem[addr[ADDR-1:0]] <= wdata[WIDTH-1:0];
generate
if (WRITETHRU) begin
// Read function gets new data if also a write cycle
// latch the read addr for next cycle
reg [ADDR-1:0] l_raddr;
reg l_cycle;
always @(posedge clk) begin
l_raddr <= addr;
l_cycle <= rd && cs;
end
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block
wire [WIDTH-1:0] tmp_rdata;
assign tmp_rdata = (l_cycle) ? mem[{l_raddr[ADDR-1:0]}] : DEFAULT;
always @(*) rdata = tmp_rdata;
end else begin
// Read function gets old data if also a write cycle
always @(posedge clk)
if (rd && cs) rdata <= mem[{addr[ADDR-1:0]}];
else rdata <= DEFAULT;
end
endgenerate
endmodule
| 7.771816 |
module sram_dog #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 16,
RAM_SIZE = 65536
) (
input clk,
input we,
input en,
input [ADDR_WIDTH-1 : 0] addr,
input [DATA_WIDTH-1 : 0] data_i,
output reg [DATA_WIDTH-1 : 0] data_o
);
// Declareation of the memory cells
(* ram_style = "block" *) reg [DATA_WIDTH-1 : 0] RAM[RAM_SIZE - 1:0];
integer idx;
// ------------------------------------
// SRAM cell initialization
// ------------------------------------
// Initialize the sram cells with the values defined in "image.dat."
initial begin
$readmemh("dog.mem", RAM);
end
// ------------------------------------
// SRAM read operation
// ------------------------------------
always @(posedge clk) begin
if (en & we) data_o <= data_i;
else data_o <= RAM[addr];
end
// ------------------------------------
// SRAM write operation
// ------------------------------------
always @(posedge clk) begin
if (en & we) RAM[addr] <= data_i;
end
endmodule
| 7.659376 |
module sram_driver (
input wire clk, // expecting 12Mhz, adjust WAIT_TIME if this changes
input wire reset, // reset high
// module control
input wire re, // read enable, otherwise write
input wire start, // start a transaction
output reg ready, // assert high when ready for a new transaction
input wire [12:0] address, // input address
input wire [ 7:0] data_write, // data to write here
output reg [ 7:0] data_read, // data read is here
// memory control
output reg [12:0] sram_address, // sram address
output reg [7:0] sram_data_write, // sram data pins out
input wire [7:0] sram_data_read, // sram data pins in
output reg sram_data_pins_oe, // sram data pins direction, high for data out
output wire n_ce1, // !ce1
output wire ce2, // ce2 - combination of these chip enables standby - this driver connects them both together
output wire n_we, // !we - low to write
output wire n_oe // !oe - low to enable outputs
);
parameter WAIT_TIME = 2; // parameter to set how long to wait before a read or write is done
// doc for ds2064 says 200ns max, so 3 cycles at 12MHz is enough
// less confusing names for the io control of the sram chip
reg ce = 0;
reg oe = 0;
reg we = 0;
assign n_we = !we;
assign n_oe = !oe;
assign n_ce1 = !ce;
assign ce2 = ce;
// state machine setup
reg [3:0] state = STATE_WAIT;
localparam N = $clog2(WAIT_TIME);
reg [N-1:0] counter = 0;
localparam STATE_WAIT = 0;
localparam STATE_READ = 1;
localparam STATE_WRITE = 2;
always @(posedge clk) begin
// sync reset
if (reset) begin
state <= STATE_WAIT;
ready <= 0;
data_read <= 0;
sram_address <= 0;
sram_data_pins_oe <= 0;
ce <= 0;
oe <= 0;
we <= 0;
counter <= 0;
end else begin
// state machine
case (state)
STATE_WAIT: begin
ready <= 1;
if (start) begin
ready <= 0;
sram_address <= address;
counter <= WAIT_TIME;
if (re) begin
sram_data_pins_oe <= 0;
state <= STATE_READ;
ce <= 1;
oe <= 1;
we <= 0;
end else begin
sram_data_pins_oe <= 1;
state <= STATE_WRITE;
sram_data_write <= data_write;
ce <= 1;
oe <= 0;
we <= 1;
end
end
end
STATE_READ: begin
counter <= counter - 1;
if (counter == 0) begin
ce <= 0;
ready <= 1;
data_read <= sram_data_read;
state <= STATE_WAIT;
end
end
STATE_WRITE: begin
counter <= counter - 1;
if (counter == 0) begin
ce <= 0;
we <= 0;
ready <= 1;
state <= STATE_WAIT;
end
end
endcase
end
end
endmodule
| 7.789387 |
module chipselects reads and writes to the sram, with 2-cycle *
* read latency and one cycle write latency. *
* *
*****************************************************************************/
module sram_drvr (
// Inputs
clk,
reset,
address,
byteenable,
chipselect,
read,
write,
writedata,
// Bi-Directional
SRAM_DQ,
// Outputs
SRAM_ADDR,
SRAM_LB_N,
SRAM_UB_N,
SRAM_CE_N,
SRAM_OE_N,
SRAM_WE_N,
readdata
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [17:0] address;
input [1:0] byteenable;
input chipselect;
input read;
input write;
input [15:0] writedata;
// Bi-Directional
inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits
// Outputs
output reg [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits
output reg SRAM_LB_N; // SRAM Low-byte Data Mask
output reg SRAM_UB_N; // SRAM High-byte Data Mask
output reg SRAM_CE_N; // SRAM Chip chipselect
output reg SRAM_OE_N; // SRAM Output chipselect
output reg SRAM_WE_N; // SRAM Write chipselect
output reg [15:0] readdata;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [15:0] writedata_reg;
// State Machine Registers
/*****************************************************************************
* Output assignments *
*****************************************************************************/
assign SRAM_DQ = ((~SRAM_WE_N) ? writedata_reg : 16'hzzzz);
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b0)
begin
readdata <= 16'h0000;
writedata_reg <= 16'h0000;
SRAM_ADDR <= 18'h00000;
SRAM_LB_N <= 1'b1;
SRAM_UB_N <= 1'b1;
SRAM_CE_N <= 1'b1;
SRAM_OE_N <= 1'b1;
SRAM_WE_N <= 1'b1;
end
else
begin
readdata <= SRAM_OE_N ? readdata : SRAM_DQ;
writedata_reg <= writedata;
SRAM_ADDR <= address;
SRAM_LB_N <= ~(byteenable[0] & chipselect);
SRAM_UB_N <= ~(byteenable[1] & chipselect);
SRAM_CE_N <= ~(chipselect);
SRAM_OE_N <= ~(read & chipselect);
SRAM_WE_N <= ~(write & chipselect);
end
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
| 7.349016 |
module SRAM_dual_async3 #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 10,
DELAY = 25,
DATA_HEX_FILE = "dump.hex"
) (
input wire [ADDR_WIDTH-1:0] ADDRA,
input wire [ADDR_WIDTH-1:0] ADDRB,
input wire CEA1n,
input wire CEA2,
input wire OEAn,
input wire WEAn,
input wire CEB1n,
input wire CEB2,
input wire OEBn,
input wire WEBn,
inout wire [DATA_WIDTH-1:0] DATA_A,
inout wire [DATA_WIDTH-1:0] DATA_B
);
reg [DATA_WIDTH-1:0] mem[0:(2**ADDR_WIDTH)-1];
reg [DATA_WIDTH-1:0] data_outA;
reg [DATA_WIDTH-1:0] data_outB;
wire ce_A;
wire ce_B;
initial begin
$readmemh(DATA_HEX_FILE, mem);
end
assign ce_A = ~CEA1n & CEA2;
always @(*) begin : mem_writeA
if (ce_A && !WEAn) begin
mem[ADDRA] = DATA_A;
end
end
always @(*) begin : mem_readA
if (ce_A && WEAn && !OEAn) begin
data_outA = mem[ADDRA];
end
end
assign #DELAY DATA_A = (ce_A && WEAn && !OEAn) ? data_outA : 8'bz;
//--------------------------------------------------------------
assign ce_B = ~CEB1n & CEB2;
always @(*) begin : mem_writeB
if (ce_B && !WEBn) begin
mem[ADDRB] = DATA_B;
end
end
always @(*) begin : mem_readB
if (ce_B && WEBn && !OEBn) begin
data_outB = mem[ADDRB];
end
end
assign #DELAY DATA_B = (ce_B && WEBn && !OEBn) ? data_outB : 8'hzz;
endmodule
| 9.271563 |
module
* Copyright Robert Schmidt <rschmidt@uni-bremen.de>, 2020
*
* This documentation describes Open Hardware and is licensed under the
* CERN-OHL-W v2.
*
* You may redistribute and modify this documentation under the terms
* of the CERN-OHL-W v2. (https://cern.ch/cern-ohl). This documentation
* is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF
* MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR
* PURPOSE. Please see the CERN-OHL-W v2 for applicable conditions.
*/
module sram_dual_port #(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 9,
parameter FILE = ""
)(
input wire wclk_i,
input wire rclk_i,
input wire wen_i,
input wire [ADDR_WIDTH-1:0] waddr_i,
input wire [DATA_WIDTH-1:0] data_i,
input wire [ADDR_WIDTH-1:0] raddr_i,
output reg [DATA_WIDTH-1:0] data_o
);
reg [DATA_WIDTH-1:0] mem [(1<<ADDR_WIDTH)-1:0];
initial
begin
if (FILE != "") $readmemh(FILE, mem);
end
always @(posedge wclk_i)
begin
if (wen_i)
mem[waddr_i] <= data_i;
end
always @(posedge rclk_i)
begin
data_o <= mem[raddr_i];
end
endmodule
| 8.161218 |
module SRAM_dual_sync #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 10
) (
input wire clk0,
input wire clk1,
input wire [ADDR_WIDTH-1:0] ADDR0,
input wire [ADDR_WIDTH-1:0] ADDR1,
input wire [DATA_WIDTH-1:0] DATA0,
input wire [DATA_WIDTH-1:0] DATA1,
(* direct_enable = 1 *) input wire cen0,
(* direct_enable = 1 *) input wire cen1,
input wire we0,
input wire we1,
output reg [DATA_WIDTH-1:0] Q0,
output reg [DATA_WIDTH-1:0] Q1
);
(* ramstyle = "no_rw_check" *) reg [DATA_WIDTH-1:0] mem[0:(2**ADDR_WIDTH)-1];
always @(posedge clk0) begin
Q0 <= mem[ADDR0];
if (cen0 && we0) begin
mem[ADDR0] <= DATA0;
end
end
always @(posedge clk1) begin
Q1 <= mem[ADDR1];
if (cen1 && we1) begin
mem[ADDR1] <= DATA1;
end
end
endmodule
| 8.146296 |
module SRAM_dual_sync_init #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 10,
DATA_HEX_FILE = "dump.hex"
) (
input wire clk0,
input wire clk1,
input wire [ADDR_WIDTH-1:0] ADDR0,
input wire [ADDR_WIDTH-1:0] ADDR1,
input wire [DATA_WIDTH-1:0] DATA0,
input wire [DATA_WIDTH-1:0] DATA1,
(* direct_enable = 1 *) input wire cen0,
(* direct_enable = 1 *) input wire cen1,
input wire we0,
input wire we1,
output reg [DATA_WIDTH-1:0] Q0,
output reg [DATA_WIDTH-1:0] Q1
);
(* ramstyle = "no_rw_check" *) reg [DATA_WIDTH-1:0] mem[0:(2**ADDR_WIDTH)-1];
initial begin
$readmemh(DATA_HEX_FILE, mem);
end
always @(posedge clk0) begin
Q0 <= mem[ADDR0];
if (cen0 && we0) begin
mem[ADDR0] <= DATA0;
end
end
always @(posedge clk1) begin
Q1 <= mem[ADDR1];
if (cen1 && we1) begin
mem[ADDR1] <= DATA1;
end
end
endmodule
| 8.146296 |
module sram_evrisim (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: W
clk0,
csb0,
addr0,
din0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter DATA_WIDTH = 11;
parameter ADDR_WIDTH = 9;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
input clk1; // clock
input csb1; // active low chip select
input [ADDR_WIDTH-1:0] addr1;
output [DATA_WIDTH-1:0] dout1;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
reg csb0_reg;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
// All inputs are registers
always @(posedge clk0) begin
csb0_reg = csb0;
addr0_reg = addr0;
din0_reg = din0;
/*if ( !csb0_reg && VERBOSE )
$display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);*/
end
reg csb1_reg;
reg [ADDR_WIDTH-1:0] addr1_reg;
reg [DATA_WIDTH-1:0] dout1;
// All inputs are registers
always @(posedge clk1) begin
csb1_reg = csb1;
addr1_reg = addr1;
if (!csb0 && !csb1 && (addr0 == addr1))
$display(
$time,
" WARNING: Evrisim Writing and reading addr0=%b and addr1=%b simultaneously!",
addr0,
addr1
);
#(T_HOLD) dout1 = 17'bx;
/*if ( !csb1_reg && VERBOSE )
$display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);*/
end
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0
always @(negedge clk0) begin : MEM_WRITE0
if (!csb0_reg) begin
mem[addr0_reg][10:0] = din0_reg[10:0];
end
end
// Memory Read Block Port 1
// Read Operation : When web1 = 1, csb1 = 0
always @(negedge clk1) begin : MEM_READ1
if (!csb1_reg) dout1 <= #(DELAY) mem[addr1_reg];
end
endmodule
| 7.299402 |
module sram_exec_tb;
reg clock;
reg power1;
always #10 clock <= (clock === 1'b0);
initial begin
clock <= 0;
end
initial begin
$dumpfile("sram_exec.vcd");
$dumpvars(0, sram_exec_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (200) begin
repeat (1000) @(posedge clock);
$display("+1000 cycles");
end
$display("%c[1;31m", 27);
`ifdef GL
$display("Monitor: Timeout, Test SRAM exec (GL) Failed");
`else
$display("Monitor: Timeout, Test SRAM exec (RTL) Failed");
`endif
$display("%c[0m", 27);
$finish;
end
wire [37:0] mprj_io; // Most of these are no-connects
wire [ 3:0] status;
wire [ 3:0] checkbits;
assign checkbits = mprj_io[19:16];
assign status = mprj_io[35:32];
assign mprj_io[3] = 1'b1; // Force CSB high.
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire gpio;
reg RSTB;
// Monitor
initial begin
wait (status == 4'h5);
`ifdef GL
$display("Monitor: Test SRAM exec (GL) Started");
`else
$display("Monitor: Test SRAM exec (RTL) Started");
`endif
wait (status == 4'ha);
`ifdef GL
$display("Monitor: Test SRAM exec (GL) called SRAM routine");
`else
$display("Monitor: Test SRAM exec (RTL) called SRAM routine");
`endif
wait (status == 4'hc);
`ifdef GL
$display("Monitor: Test SRAM exec (GL) Passed");
`else
$display("Monitor: Test SRAM exec (RTL) Passed");
`endif
$finish;
end
initial begin
RSTB <= 1'b0;
#1000;
RSTB <= 1'b1; // Release reset
#2000;
end
initial begin // Power-up
power1 <= 1'b0;
#200;
power1 <= 1'b1;
end
always @(checkbits, status) begin
#1 $display("GPIO state = %b (%b)", checkbits, status);
end
wire VDD5V0;
wire VSS;
assign VDD5V0 = power1;
assign VSS = 1'b0;
// These are the mappings of mprj_io GPIO pads that are set to
// specific functions on startup:
//
// JTAG = mgmt_gpio_io[0] (inout)
// SDO = mgmt_gpio_io[1] (output)
// SDI = mgmt_gpio_io[2] (input)
// CSB = mgmt_gpio_io[3] (input)
// SCK = mgmt_gpio_io[4] (input)
// ser_rx = mgmt_gpio_io[5] (input)
// ser_tx = mgmt_gpio_io[6] (output)
// irq = mgmt_gpio_io[7] (input)
caravel uut (
.VDD (VDD5V0),
.VSS (VSS),
.clock (clock),
.gpio (gpio),
.mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
.resetb (RSTB)
);
spiflash #(
.FILENAME("sram_exec.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(), // not used
.io3() // not used
);
endmodule
| 7.333427 |
module SRAM_FIFO (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull
);
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output wrfull;
wire [31:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [31:0] q = sub_wire0[31:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
dcfifo dcfifo_component (
.data(data),
.rdclk(rdclk),
.rdreq(rdreq),
.wrclk(wrclk),
.wrreq(wrreq),
.q(sub_wire0),
.rdempty(sub_wire1),
.wrfull(sub_wire2),
.aclr(),
.eccstatus(),
.rdfull(),
.rdusedw(),
.wrempty(),
.wrusedw()
);
defparam dcfifo_component.intended_device_family = "Cyclone IV E",
dcfifo_component.lpm_numwords = 16, dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = 32,
dcfifo_component.lpm_widthu = 4, dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 3, dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON", dcfifo_component.wrsync_delaypipe = 3;
endmodule
| 6.679314 |
module SRAM_FIFO (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull
);
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output wrfull;
endmodule
| 6.679314 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_fish1
#(parameter DATA_WIDTH = 8, ADDR_WIDTH = 16, RAM_SIZE = 65536)
(input clk, input we, input en,
input [ADDR_WIDTH-1 : 0] addr,
input [DATA_WIDTH-1 : 0] data_i,
output reg [DATA_WIDTH-1 : 0] data_o);
// Declareation of the memory cells
(* ram_style = "block" *) reg [DATA_WIDTH-1 : 0] RAM [RAM_SIZE - 1:0];
integer idx;
// ------------------------------------
// SRAM cell initialization
// ------------------------------------
// Initialize the sram cells with the values defined in "image.dat."
initial begin
$readmemh("fish0.mem", RAM);
end
// ------------------------------------
// SRAM read operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
data_o <= data_i;
else
data_o <= RAM[addr];
end
// ------------------------------------
// SRAM write operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
RAM[addr] <= data_i;
end
endmodule
| 6.896868 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_fish2
#(parameter DATA_WIDTH = 8, ADDR_WIDTH = 16, RAM_SIZE = 65536)
(input clk, input we, input en,
input [ADDR_WIDTH-1 : 0] addr,
input [DATA_WIDTH-1 : 0] data_i,
output reg [DATA_WIDTH-1 : 0] data_o);
// Declareation of the memory cells
(* ram_style = "block" *) reg [DATA_WIDTH-1 : 0] RAM [RAM_SIZE - 1:0];
integer idx;
// ------------------------------------
// SRAM cell initialization
// ------------------------------------
// Initialize the sram cells with the values defined in "image.dat."
initial begin
$readmemh("fish2_all.mem", RAM);
end
// ------------------------------------
// SRAM read operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
data_o <= data_i;
else
data_o <= RAM[addr];
end
// ------------------------------------
// SRAM write operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
RAM[addr] <= data_i;
end
endmodule
| 6.896868 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_fish3
#(parameter DATA_WIDTH = 8, ADDR_WIDTH = 16, RAM_SIZE = 65536)
(input clk, input we, input en,
input [ADDR_WIDTH-1 : 0] addr,
input [DATA_WIDTH-1 : 0] data_i,
output reg [DATA_WIDTH-1 : 0] data_o);
// Declareation of the memory cells
(* ram_style = "block" *) reg [DATA_WIDTH-1 : 0] RAM [RAM_SIZE - 1:0];
integer idx;
// ------------------------------------
// SRAM cell initialization
// ------------------------------------
// Initialize the sram cells with the values defined in "image.dat."
initial begin
$readmemh("fish0.mem", RAM);
end
// ------------------------------------
// SRAM read operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
data_o <= data_i;
else
data_o <= RAM[addr];
end
// ------------------------------------
// SRAM write operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
RAM[addr] <= data_i;
end
endmodule
| 6.896868 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_fish4
#(parameter DATA_WIDTH = 8, ADDR_WIDTH = 16, RAM_SIZE = 65536)
(input clk, input we, input en,
input [ADDR_WIDTH-1 : 0] addr,
input [DATA_WIDTH-1 : 0] data_i,
output reg [DATA_WIDTH-1 : 0] data_o);
// Declareation of the memory cells
(* ram_style = "block" *) reg [DATA_WIDTH-1 : 0] RAM [RAM_SIZE - 1:0];
integer idx;
// ------------------------------------
// SRAM cell initialization
// ------------------------------------
// Initialize the sram cells with the values defined in "image.dat."
initial begin
$readmemh("fish0.mem", RAM);
end
// ------------------------------------
// SRAM read operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
data_o <= data_i;
else
data_o <= RAM[addr];
end
// ------------------------------------
// SRAM write operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
RAM[addr] <= data_i;
end
endmodule
| 6.896868 |
module sram_fish5 #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 16,
RAM_SIZE = 65536
) (
input clk,
input we,
input en,
input [ADDR_WIDTH-1 : 0] addr,
input [DATA_WIDTH-1 : 0] data_i,
output reg [DATA_WIDTH-1 : 0] data_o
);
// Declareation of the memory cells
(* ram_style = "block" *) reg [DATA_WIDTH-1 : 0] RAM[RAM_SIZE - 1:0];
integer idx;
// ------------------------------------
// SRAM cell initialization
// ------------------------------------
// Initialize the sram cells with the values defined in "image.dat."
initial begin
$readmemh("fish5.mem", RAM);
end
// ------------------------------------
// SRAM read operation
// ------------------------------------
always @(posedge clk) begin
if (en & we) data_o <= data_i;
else data_o <= RAM[addr];
end
// ------------------------------------
// SRAM write operation
// ------------------------------------
always @(posedge clk) begin
if (en & we) RAM[addr] <= data_i;
end
endmodule
| 8.107337 |
module sram_for_debugging_async (
data_out,
data_in,
address,
read_enable,
write_enable
);
parameter NUM_ADDR_BITS = 1;
parameter NUM_DATA_BITS = 1;
output [NUM_DATA_BITS - 1 : 0] data_out;
input [NUM_DATA_BITS - 1 : 0] data_in;
input [NUM_ADDR_BITS - 1 : 0] address;
input read_enable;
input write_enable;
reg [NUM_DATA_BITS - 1 : 0] data_storage[31:0]; // 32 entries of SRAM storage
reg [NUM_ADDR_BITS - 1 : 0] address_storage[31:0]; // 32 entries of SRAM storage
reg [5:0] write_counter; // enough to count to 63
reg [NUM_DATA_BITS - 1 : 0] stored_write_address; // store bit number of address LSB set to 1
integer i, j, k, l;
// synopsys translate_off
initial begin
for (i = 6'h00; i != 6'h20; i = i + 6'h01) begin
address_storage[i] = {NUM_ADDR_BITS{1'bX}};
data_storage[i] = {NUM_DATA_BITS{1'bX}};
stored_write_address[NUM_DATA_BITS-1 : 0] = {NUM_DATA_BITS{1'bX}};
write_counter[5:0] = 6'h00;
end
end
// synopsys translate_on
// Write to next address, remember which LSB write address bit was ~0
always @(posedge write_enable) begin
address_storage[write_counter[4:0]] = address[NUM_ADDR_BITS-1 : 0];
data_storage[write_counter[4:0]] = data_in[NUM_DATA_BITS-1 : 0];
for (j = 0; j < NUM_ADDR_BITS; j = j + 1) begin
if (((address[NUM_ADDR_BITS-1 : 0] >> j) & 1'b1) != 1'b0) begin
stored_write_address[NUM_DATA_BITS-1 : 0] = j;
j = NUM_ADDR_BITS + 1; // only remember the FIRST bit set
end
end
if (j == NUM_ADDR_BITS) // NO bit was set
begin
stored_write_address[NUM_DATA_BITS-1 : 0] = NUM_ADDR_BITS;
end
write_counter[5:0] = (write_counter[5:0] + 6'h01) & 6'h1F;
end
// Starting at the newest, search back to oldest to find if the word has been written
reg [NUM_DATA_BITS - 1 : 0] data_out;
reg [4:0] read_address;
always @(read_enable) begin
if ((read_enable !== 1'b1) | ((^address[NUM_DATA_BITS - 1 : 0]) === 1'bX)) // no read, return X's
begin
data_out[NUM_DATA_BITS-1 : 0] = {NUM_DATA_BITS{1'bX}};
end else begin
if ((address[NUM_ADDR_BITS - 1 : 0] >> (NUM_ADDR_BITS - 8)) == 8'hAA) // read magic location, return Address Bit Number
begin
data_out[NUM_DATA_BITS-1 : 0] = stored_write_address[NUM_DATA_BITS-1 : 0];
end else // otherwise search history to see if the word has been written recently
begin
k = write_counter[5:0];
for (
l = k + 6'h1F; // half way around, same as last minus 1;
l >= k; // write address not valid
l = l - 1
) begin
read_address[4:0] = l;
if (address[NUM_ADDR_BITS-1 : 0] === address_storage[read_address[4:0]]) begin
data_out[NUM_DATA_BITS-1 : 0] = data_storage[read_address[4:0]];
l = k - 2;
end
end
if (l == (k - 1)) // didn't find it at all!
begin
data_out[NUM_DATA_BITS-1 : 0] = {NUM_DATA_BITS{1'bX}};
end
end
end
end
// synopsys translate_off
initial begin
if (NUM_ADDR_BITS < 8) begin
$display("*** Exiting because %m sram_for_debugging_async Number of Address bits %d < 8",
NUM_ADDR_BITS);
$finish;
end
if (NUM_DATA_BITS < 8) begin
$display("*** Exiting because %m sram_for_debugging_async Number of Data bits %d < 8",
NUM_DATA_BITS);
$finish;
end
end
// synopsys translate_on
endmodule
| 7.71909 |
module sram_histogram (
`ifdef USE_POWER_PINS
vccd1,
vssd1,
`endif
// Port 0: W
clk0,
csb0,
addr0,
din0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter DATA_WIDTH = 17;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
parameter VERBOSE = 1; //Set to 0 to only display warnings
parameter T_HOLD = 1; //Delay to hold dout value after posedge. Value is arbitrary
`ifdef USE_POWER_PINS
inout vccd1;
inout vssd1;
`endif
input clk0; // clock
input csb0; // active low chip select
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
input clk1; // clock
input csb1; // active low chip select
input [ADDR_WIDTH-1:0] addr1;
output [DATA_WIDTH-1:0] dout1;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
reg csb0_reg;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
// All inputs are registers
always @(posedge clk0) begin
csb0_reg = csb0;
addr0_reg = addr0;
din0_reg = din0;
/*if ( !csb0_reg && VERBOSE )
$display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);*/
end
reg csb1_reg;
reg [ADDR_WIDTH-1:0] addr1_reg;
reg [DATA_WIDTH-1:0] dout1;
// All inputs are registers
always @(posedge clk1) begin
csb1_reg = csb1;
addr1_reg = addr1;
if (!csb0 && !csb1 && (addr0 == addr1))
$display(
$time,
" WARNING: Histogram Writing and reading addr0=%b and addr1=%b simultaneously!",
addr0,
addr1
);
#(T_HOLD) dout1 = 17'bx;
/*if ( !csb1_reg && VERBOSE )
$display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);*/
end
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0
always @(negedge clk0) begin : MEM_WRITE0
if (!csb0_reg) begin
mem[addr0_reg][16:0] = din0_reg[16:0];
end
end
// Memory Read Block Port 1
// Read Operation : When web1 = 1, csb1 = 0
always @(negedge clk1) begin : MEM_READ1
if (!csb1_reg) dout1 <= #(DELAY) mem[addr1_reg];
end
endmodule
| 7.728822 |
module SRAM_Image_100M (
//---------------------- Avalon -----------------------
csi_clk, //100MHz Clock
csi_reset_n,
avs_chipselect,
avs_address,
avs_read,
avs_readdata,
avs_write,
avs_writedata,
//---------------------- User Interface --------------------
coe_oSRAM_ADDR,
coe_ioSRAM_DQ,
coe_oSRAM_WE_N,
coe_oSRAM_OE_N,
coe_oSRAM_UB_N,
coe_oSRAM_LB_N,
coe_oSRAM_CE_N,
coe_iRST_n, // Reset signal with lcd_timing_controller
coe_oSRAM_DATA, // Output data from SRAM to lcd_timing_controller
coe_iREAD_SRAM_EN, // Whether the reading loop continues
coe_oCLK50M, // 25M clock for lcd_timing_controller
);
// Avalon
input csi_clk;
input csi_reset_n;
input avs_chipselect;
input [3:0] avs_address;
input avs_read;
output reg [31:0] avs_readdata;
input avs_write;
input [31:0] avs_writedata; //[31:12]Address, [11]High(1) or Low(0), [10:3] data byte
// User Interface
output [19:0] coe_oSRAM_ADDR;
inout [15:0] coe_ioSRAM_DQ;
output coe_oSRAM_WE_N;
output coe_oSRAM_OE_N;
output coe_oSRAM_UB_N;
output coe_oSRAM_LB_N;
output coe_oSRAM_CE_N;
input coe_iRST_n;
output [31:0] coe_oSRAM_DATA; //[31:24]R, [23:16]G, [15:8]B
input coe_iREAD_SRAM_EN;
output coe_oCLK50M;
reg clk_50M;
assign coe_oCLK50M = clk_50M;
always@(posedge csi_clk or negedge csi_reset_n or negedge coe_iRST_n)
begin
if((!csi_reset_n) || (!coe_iRST_n))
clk_50M <= 0;
else
clk_50M <= (clk_50M == 1) ? 0 : 1;
end
reg SW; //1: read, 0: write
reg [19:0] read_counter; // Address to be read
reg [19:0] write_counter; // Address to be written
reg [15:0] write_data_word; // Data (16bit, word) to be written
reg [31:0] coe_oSRAM_DATA;
reg UB_N, LB_N;
assign coe_oSRAM_ADDR = (SW) ? read_counter : write_counter;
assign coe_ioSRAM_DQ = (SW) ? 16'hzzzz : write_data_word;
assign coe_oSRAM_UB_N = UB_N;
assign coe_oSRAM_LB_N = LB_N;
assign coe_oSRAM_CE_N = 1'b0;
assign coe_oSRAM_WE_N = (SW ? 1'b1 : 1'b0);
assign coe_oSRAM_OE_N = (SW ? 1'b0 : 1'b1);
wire [15:0] SRAM_OUT;
assign SRAM_OUT = SW ? coe_ioSRAM_DQ : 16'b0;
reg avs_write_flag_clear;
always@(posedge csi_clk or negedge coe_iRST_n)
begin
if(!coe_iRST_n)
begin
read_counter = 20'd0;
coe_oSRAM_DATA = 32'd0;
SW = 1;
UB_N = 0;
LB_N = 0;
end
else
begin
if((avs_chipselect == 1) && (avs_write == 1)) // write data to SRAM
begin
SW = 0;
write_counter = avs_writedata[31:12];
if(avs_writedata[11])
begin
UB_N = 1;
write_data_word = {avs_writedata[10:3], 8'd0};
end
else
begin
LB_N = 1;
write_data_word = {8'd0, avs_writedata[10:3]};
end
end
else // read data from SRAM
begin
SW = 1;
UB_N = 0;
LB_N = 0;
if(clk_50M == 1)
coe_oSRAM_DATA[31:16] = SRAM_OUT;
else
coe_oSRAM_DATA[15:0] = SRAM_OUT;
if(coe_iREAD_SRAM_EN)
read_counter = read_counter + 20'd1;
if(read_counter == 20'd768000) // 800*480*2, 2 words stores color for 1 pixel
read_counter = 20'd0;
end
end
end
endmodule
| 6.944417 |
module SRAM_Image_BW (
//---------------------- Avalon -----------------------
csi_clk, //100MHz Clock
csi_reset_n,
avs_chipselect,
avs_address,
avs_read,
avs_readdata,
avs_write,
avs_writedata,
//---------------------- User Interface --------------------
coe_oSRAM_ADDR,
coe_ioSRAM_DQ,
coe_oSRAM_WE_N,
coe_oSRAM_OE_N,
coe_oSRAM_UB_N,
coe_oSRAM_LB_N,
coe_oSRAM_CE_N,
coe_iRST_n, // 重置信号，需要与扫描显示模块lcd_timing_controller同步
coe_oSRAM_DATA, // 输出32bit颜色信息到扫描显示模块lcd_timing_controller
coe_iREAD_SRAM_EN, // 扫描使能，有效时每收到一个时钟信号指针read_counter后移一位
coe_iCLK25M, // 扫描显示模块lcd_timing_controller使用的25MHz时钟，需要两模块同步
);
// Avalon
input csi_clk;
input csi_reset_n;
input avs_chipselect;
input [3:0] avs_address;
input avs_read;
output reg [31:0] avs_readdata;
input avs_write;
input [31:0] avs_writedata; //[31:12]位为写入目标地址，[7:0]位为写入数据（表示像素的灰度）
// User Interface
output [19:0] coe_oSRAM_ADDR; //当前读/写地址
inout [15:0] coe_ioSRAM_DQ; //（三态）数据输入输出
output coe_oSRAM_WE_N; //写使能（WRITE ENABLE）
output coe_oSRAM_OE_N; //读使能（OUTPUT ENABLE）
output coe_oSRAM_UB_N; //高字节控制
output coe_oSRAM_LB_N; //低字节控制
output coe_oSRAM_CE_N; //片选
input coe_iRST_n;
output [31:0] coe_oSRAM_DATA;
input coe_iREAD_SRAM_EN;
input coe_iCLK25M;
reg SW; // 读写标志，1为读0为写
reg [19:0] read_counter; // 读数据指针（需要扫描）
reg [19:0] write_counter; // 写数据指针（需要随机访问）
reg [15:0] write_data_word; // 写入的数据（1个字）
assign coe_oSRAM_ADDR = (SW) ? read_counter : write_counter;
assign coe_ioSRAM_DQ = (SW) ? 16'hzzzz : write_data_word; //三态门控制（写）
assign coe_oSRAM_UB_N = 1'b0;
assign coe_oSRAM_LB_N = 1'b0;
assign coe_oSRAM_CE_N = 1'b0; //片选固定为有效，不使用高/低字节控制
assign coe_oSRAM_WE_N = (SW ? 1'b1 : 1'b0);
assign coe_oSRAM_OE_N = (SW ? 1'b0 : 1'b1);
wire [15:0] SRAM_OUT;
assign SRAM_OUT = SW ? coe_ioSRAM_DQ : 16'b1111111100000000; //三态门控制（读），端口被占用时默认输出0xff00，即白色
assign coe_oSRAM_DATA = {SRAM_OUT[15:8], SRAM_OUT[15:8], SRAM_OUT[15:8], 8'd0};
//默认输出灰度，即RGB值相等
reg [1:0] countdown;
reg [31:0] avs_write_data_buf;
// DE2-115板的SRAM最高支持125MHz时钟，在此用100MHz的csi_clk
always@(posedge csi_clk or negedge csi_reset_n)
begin
if(!csi_reset_n)
begin
SW = 1;
countdown = 2'd0;
end
else
begin
if(countdown == 2'd0)
SW = 1;
else
begin
SW = 0;
countdown = countdown - 2'd1;
end
if((avs_chipselect == 1) && (avs_write == 1))
begin
SW = 0;
avs_write_data_buf = avs_writedata;
write_counter = avs_write_data_buf[31:12]; //获取地址
write_data_word = {avs_write_data_buf[7:0], 8'd0}; //获取灰度数据
countdown = 2'd2; //设置SW=0并延时，使得下一个时钟到来时数据能够顺利写入
end
end
end
always@(posedge coe_iCLK25M or negedge coe_iRST_n)
begin
if(!coe_iRST_n)
begin
read_counter = 20'd0; //与扫描显示模块同部重置，使屏幕上的（0, 0）点对应内存中的0位置
end
else
begin
if(coe_iREAD_SRAM_EN)
read_counter = read_counter + 20'd1; //扫描使能有效时每一个时钟到来时指针后移一位
if(read_counter == 20'd384000) //一个循环为384000（800*480）位
read_counter = 20'd0;
end
end
endmodule
| 6.739371 |
module SRAM_Image_UI(
//---------------------- Avalon -----------------------
csi_clk, //100MHz Clock
csi_reset_n,
avs_chipselect,
avs_address,
avs_read,
avs_readdata,
avs_write,
avs_writedata,
//---------------------- User Interface --------------------
coe_oSRAM_ADDR,
coe_ioSRAM_DQ,
coe_oSRAM_WE_N,
coe_oSRAM_OE_N,
coe_oSRAM_UB_N,
coe_oSRAM_LB_N,
coe_oSRAM_CE_N,
coe_iRST_n,
coe_oSRAM_DATA,
coe_iREAD_SRAM_EN,
coe_oCLK25M,
);
// Avalon
input csi_clk;
input csi_reset_n;
input avs_chipselect;
input [3:0] avs_address;
input avs_read;
output reg [31:0] avs_readdata;
input avs_write;
input [31:0] avs_writedata;
// User Interface
output [19:0] coe_oSRAM_ADDR;
inout [15:0] coe_ioSRAM_DQ;
output coe_oSRAM_WE_N; //写使能（WRITE ENABLE）
output coe_oSRAM_OE_N; //读使能（OUTPUT ENABLE）
output coe_oSRAM_UB_N; //高字节控制
output coe_oSRAM_LB_N; //低字节控制
output coe_oSRAM_CE_N; //片选
input coe_iRST_n;
output [31:0] coe_oSRAM_DATA;
input coe_iREAD_SRAM_EN;
output coe_oCLK25M;
reg clk_50M, clk_25M;
reg [1:0] clk_disp_cnt;
always@(posedge csi_clk or negedge csi_reset_n)
begin
if(!csi_reset_n)
begin
clk_50M <= 0;
clk_25M <= 0;
clk_disp_cnt <= 2'b00;
end
else
begin
case(clk_disp_cnt)
2'b00: begin clk_50M <= 1; clk_25M <= 0; end
2'b01: begin clk_50M <= 0; clk_25M <= 0; end
2'b10: begin clk_50M <= 1; clk_25M <= 1; end
2'b11: begin clk_50M <= 0; clk_25M <= 1; end
endcase
clk_disp_cnt <= clk_disp_cnt + 2'b01;
end
end
assign coe_oCLK25M = clk_25M;
reg SW; //1: read, 0: write
reg [19:0] read_counter; // Address to be read
reg [19:0] write_counter; // Address to be written
reg [15:0] write_data_word; // Data (16bit, word) to be written
reg [31:0] coe_oSRAM_DATA;
reg UB_N, LB_N;
assign coe_oSRAM_ADDR = (SW) ? read_counter : write_counter;
assign coe_ioSRAM_DQ = (SW) ? 16'hzzzz : write_data_word;
assign coe_oSRAM_UB_N = UB_N;
assign coe_oSRAM_LB_N = LB_N;
assign coe_oSRAM_CE_N = 1'b0;
assign coe_oSRAM_WE_N = (SW ? 1'b1 : 1'b0);
assign coe_oSRAM_OE_N = (SW ? 1'b0 : 1'b1);
wire [15:0] SRAM_OUT;
assign SRAM_OUT = SW ? coe_ioSRAM_DQ : 16'b0;
reg avs_write_flag_clear;
always@(posedge clk_50M or negedge coe_iRST_n)
begin
if(!coe_iRST_n)
begin
read_counter = 20'd0;
coe_oSRAM_DATA = 32'd0;
SW = 1;
UB_N = 0;
LB_N = 0;
end
else
begin
if(avs_write_flag)
begin
SW = 0; // write;
write_counter = avs_writedata_buf[31:12];
if(avs_writedata_buf[11])
begin
UB_N = 1;
write_data_word = {avs_writedata_buf[10:3], 8'd0};
end
else
begin
LB_N = 1;
write_data_word = {8'd0, avs_writedata_buf[10:3]};
end
avs_write_flag_clear = 1;
end
else
begin
SW = 1;
if(clk_25M == 0)
coe_oSRAM_DATA[31:16] = SRAM_OUT;
else
coe_oSRAM_DATA[15:0] = SRAM_OUT;
end
end
end
reg [31:0] avs_writedata_buf;
reg avs_write_flag;
always@(posedge csi_clk or negedge csi_reset_n)
begin
if((avs_chipselect == 1) && (avs_write == 1))
begin
avs_write_flag <= 1;
avs_writedata_buf <= avs_writedata;
end
if(avs_write_flag_clear == 1)
avs_write_flag <= 0;
end
endmodule
| 6.688935 |
module sram_imem (
write_addr, // Address Write Input
read_addr, // Address Read Input
write_data, // Data Write Input
read_data, // Data Read Output
write_en // Write Enable/Disable
);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
//--------------Input Ports-----------------------
input wire [ADDR_WIDTH-1:0] write_addr;
input wire [ADDR_WIDTH-1:0] read_addr;
input wire [DATA_WIDTH-1:0] write_data;
input wire write_en;
//--------------Output Ports-----------------------
output reg [DATA_WIDTH-1:0] read_data;
//--------------Internal variables----------------
reg [DATA_WIDTH-1:0] mem[0:RAM_DEPTH-1];
//--------------Code Starts Here------------------
// Memory Write Block
// Write Operation : When write_en = 1,
always @(*) begin : MEM_WRITE
if (write_en) mem[write_addr] = write_data;
end
// Memory Read Block
// Read Operation :
always @(*) begin : MEM_READ
read_data = mem[read_addr];
end
endmodule
| 6.956669 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_instruct
#(parameter DATA_WIDTH = 8, ADDR_WIDTH = 16, RAM_SIZE = 65536)
(input clk, input we, input en,
input [ADDR_WIDTH-1 : 0] addr,
input [DATA_WIDTH-1 : 0] data_i,
output reg [DATA_WIDTH-1 : 0] data_o);
// Declareation of the memory cells
(* ram_style = "distributed" *)reg [DATA_WIDTH-1 : 0] RAM [RAM_SIZE - 1:0];
integer idx;
// ------------------------------------
// SRAM cell initialization
// ------------------------------------
// Initialize the sram cells with the values defined in "image.dat."
initial begin
$readmemh("instruct.mem", RAM);
end
// ------------------------------------
// SRAM read operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
data_o <= data_i;
else
data_o <= RAM[addr];
end
// ------------------------------------
// SRAM write operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
RAM[addr] <= data_i;
end
endmodule
| 6.896868 |
module sram_issi_if (
d,
addr,
wbe,
en,
clk,
q,
sram_dio,
sram_addr,
sram_oe_n,
sram_ce_n,
sram_we_n,
sram_lb_n,
sram_ub_n
);
parameter DWIDTH = 16;
parameter AWIDTH = 19; //! 只有17bit有效, 2Mbit ~ 512Kb ~256k half word sram的地址只有A0-16 17bits
//naive sync sram interface
input [DWIDTH-1:0] d; // Data input
input [AWIDTH-1:0] addr; // Address input
input [DWIDTH/8-1:0] wbe; // write-byte-enable Only can write or read 16 bit at once
input en;
input clk; //T > 20ns make sure sram works
output [DWIDTH-1:0] q; //ok
//To issi asram
inout [DWIDTH-1:0] sram_dio;
output [AWIDTH-1:0] sram_addr; //ok
output sram_oe_n; // write enter writing status, set oe to high for writing speed ok
output sram_ce_n; // always low ok
output sram_we_n; // write control ok
output sram_lb_n; // if read always low, if write depence on wbe ok
output sram_ub_n; // if read always low, if write depence on wbe ok
wire we;
wire [DWIDTH-1:0] sram_q;
reg [DWIDTH-1:0] q_reg;
//if any write, we = 1
assign we = |wbe;
assign sram_ce_n = ~en;
assign sram_oe_n = we; //if we output disable
assign sram_we_n = ~we | ~clk; //half clk cycle write
// assign sram_lb_n = ~sram_we_n & ~wbe[0];
// assign sram_ub_n = ~sram_we_n & ~wbe[1];
assign sram_lb_n = 0; //Only can write or read 16 bit at once
assign sram_ub_n = 0;
assign sram_addr = addr;
assign q = sram_q;
//tri state buffer
genvar i;
generate
for (i = 0; i < DWIDTH; i = i + 1) begin
//xilix IOBUF is low active output
IOBUF IOBUF_00 (
.O (sram_q[i]), // Buffer output
.IO(sram_dio[i]), // Buffer inout port (connect directly to top-level port)
.I (d[i]), // Buffer input
.T (~sram_oe_n) // 3-state enable input, high=input, low=output
);
end
endgenerate
endmodule
| 7.662946 |
module sram_l (
input [14:0] ADDR,
inout [7:0] DATA,
input nCE,
input nOE,
input nWE
);
reg [7:0] RAMDATA[0:32767];
wire [7:0] DATA_OUT;
integer k;
initial begin
//Clean init to 0 since the speed-patched system ROM skips SRAM init
//for (k = 0; k < 32767; k = k + 1)
// RAMDATA[k] = 0;
$readmemh("raminit_sram_l.txt", RAMDATA);
end
assign #120 DATA_OUT = RAMDATA[ADDR];
assign DATA = (!nCE && !nOE) ? DATA_OUT : 8'bzzzzzzzz;
always @(nCE or nWE) if (!nCE && !nWE) #30 RAMDATA[ADDR] <= DATA;
// DEBUG begin
always @(nWE or nCE) if (!nWE && !nOE) $display("ERROR: SRAML: nOE and nWE are both active !");
//always @(negedge nWE)
// if (!nCE) $display("Wrote %H to SRAML %H", DATA, ADDR);
// DEBUG end
endmodule
| 6.692954 |
module sram_l2_data (
input wire MEMCLK,
input wire RESET_N,
input wire CE,
input wire [`L2_DATA_ARRAY_HEIGHT_LOG2-1:0] A,
input wire RDWEN,
input wire [`L2_DATA_ARRAY_WIDTH-1:0] BW,
input wire [`L2_DATA_ARRAY_WIDTH-1:0] DIN,
output wire [`L2_DATA_ARRAY_WIDTH-1:0] DOUT,
input wire [`BIST_OP_WIDTH-1:0] BIST_COMMAND,
input wire [`SRAM_WRAPPER_BUS_WIDTH-1:0] BIST_DIN,
output reg [`SRAM_WRAPPER_BUS_WIDTH-1:0] BIST_DOUT,
input wire [`BIST_ID_WIDTH-1:0] SRAMID
);
// `ifdef SYNTHESIZABLE_BRAM
// wire [`L2_DATA_ARRAY_WIDTH-1:0] DOUT_bram;
// assign DOUT = DOUT_bram;
// bram_1rw_wrapper #(
// .NAME ("" ),
// .DEPTH (`L2_DATA_ARRAY_HEIGHT),
// .ADDR_WIDTH (`L2_DATA_ARRAY_HEIGHT_LOG2),
// .BITMASK_WIDTH (`L2_DATA_ARRAY_WIDTH),
// .DATA_WIDTH (`L2_DATA_ARRAY_WIDTH)
// ) sram_l2_data (
// .MEMCLK (MEMCLK ),
// .RESET_N (RESET_N ),
// .CE (CE ),
// .A (A ),
// .RDWEN (RDWEN ),
// .BW (BW ),
// .DIN (DIN ),
// .DOUT (DOUT_bram )
// );
// `else
// reg [`L2_DATA_ARRAY_WIDTH-1:0] cache [`L2_DATA_ARRAY_HEIGHT-1:0];
reg [`L2_DATA_ARRAY_WIDTH-1:0] cache [3:0];
// integer i;
// initial
// begin
// for (i = 0; i < `L2_DATA_ARRAY_HEIGHT; i = i + 1)
// begin
// cache[i] = 0;
// end
// end
reg [`L2_DATA_ARRAY_WIDTH-1:0] dout_f;
assign DOUT = dout_f;
always @(posedge MEMCLK) begin
if (!RESET_N) begin // ILA: add initial states
cache[0] <= 0;
cache[1] <= 0;
cache[2] <= 0;
cache[3] <= 0;
end else if (CE) begin
if (RDWEN == 1'b0) cache[A] <= (DIN & BW) | (cache[A] & ~BW);
else dout_f <= cache[A];
end
end
// `endif
endmodule
| 6.678163 |
module sram_l2_dir (
input wire MEMCLK,
input wire RESET_N,
input wire CE,
input wire [`L2_DIR_ARRAY_HEIGHT_LOG2-1:0] A,
input wire RDWEN,
input wire [`L2_DIR_ARRAY_WIDTH-1:0] BW,
input wire [`L2_DIR_ARRAY_WIDTH-1:0] DIN,
output wire [`L2_DIR_ARRAY_WIDTH-1:0] DOUT,
input wire [`BIST_OP_WIDTH-1:0] BIST_COMMAND,
input wire [`SRAM_WRAPPER_BUS_WIDTH-1:0] BIST_DIN,
output reg [`SRAM_WRAPPER_BUS_WIDTH-1:0] BIST_DOUT,
input wire [`BIST_ID_WIDTH-1:0] SRAMID
);
// `ifdef SYNTHESIZABLE_BRAM
// wire [`L2_DIR_ARRAY_WIDTH-1:0] DOUT_bram;
// assign DOUT = DOUT_bram;
// bram_1rw_wrapper #(
// .NAME ("" ),
// .DEPTH (`L2_DIR_ARRAY_HEIGHT),
// .ADDR_WIDTH (`L2_DIR_ARRAY_HEIGHT_LOG2),
// .BITMASK_WIDTH (`L2_DIR_ARRAY_WIDTH),
// .DATA_WIDTH (`L2_DIR_ARRAY_WIDTH)
// ) sram_l2_dir (
// .MEMCLK (MEMCLK ),
// .RESET_N (RESET_N ),
// .CE (CE ),
// .A (A ),
// .RDWEN (RDWEN ),
// .BW (BW ),
// .DIN (DIN ),
// .DOUT (DOUT_bram )
// );
// `else
// reg [`L2_DIR_ARRAY_WIDTH-1:0] cache [`L2_DIR_ARRAY_HEIGHT-1:0];
reg [`L2_DIR_ARRAY_WIDTH-1:0] cache [1:0];
// integer i;
// initial
// begin
// for (i = 0; i < `L2_DIR_ARRAY_HEIGHT; i = i + 1)
// begin
// cache[i] = 0;
// end
// end
reg [`L2_DIR_ARRAY_WIDTH-1:0] dout_f;
assign DOUT = dout_f;
always @(posedge MEMCLK) begin
if (!RESET_N) begin
cache[0] <= 0;
cache[1] <= 0;
end else if (CE) begin
if (RDWEN == 1'b0) cache[A] <= (DIN & BW) | (cache[A] & ~BW);
else dout_f <= cache[A];
end
end
// `endif
endmodule
| 6.593691 |
module sram_ldv #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 16,
RAM_SIZE = 65536
) (
input clk,
input we,
input en,
input [ADDR_WIDTH-1 : 0] addr,
input [DATA_WIDTH-1 : 0] data_i,
output reg [DATA_WIDTH-1 : 0] data_o
);
// Declareation of the memory cells
(* ram_style = "block" *) reg [DATA_WIDTH-1 : 0] RAM[RAM_SIZE - 1:0];
integer idx;
// ------------------------------------
// SRAM cell initialization
// ------------------------------------
// Initialize the sram cells with the values defined in "image.dat."
initial begin
$readmemh("ldv.mem", RAM);
end
// ------------------------------------
// SRAM read operation
// ------------------------------------
always @(posedge clk) begin
if (en & we) data_o <= data_i;
else data_o <= RAM[addr];
end
// ------------------------------------
// SRAM write operation
// ------------------------------------
always @(posedge clk) begin
if (en & we) RAM[addr] <= data_i;
end
endmodule
| 8.291475 |
module sram_led_tester (
KEY,
SW,
CLOCK_50,
LEDR,
SRAM_ADDR,
SRAM_DQ,
SRAM_WE_N,
SRAM_CE_N,
SRAM_OE_N,
SRAM_UB_N,
SRAM_LB_N
);
input [3:0] KEY;
input [17:0] SW;
input CLOCK_50;
output [19:0] SRAM_ADDR;
output [17:0] LEDR;
inout [15:0] SRAM_DQ;
output SRAM_WE_N, SRAM_CE_N, SRAM_OE_N, SRAM_UB_N, SRAM_LB_N;
//wire clk125;
//pelele pll(.inclk0(CLOCK_50), .c0(clk125));
sram_fsm controller (
.CE_N(SRAM_CE_N),
.LB_N(SRAM_LB_N),
.OE_N(SRAM_OE_N),
.UB_N(SRAM_UB_N),
.WE_N(SRAM_WE_N),
.rd_valid(),
.wr_valid(),
.clk(CLOCK_50),
.rd_en(1'b1),
.reset(~KEY[0]),
.wr_en(1'b0)
);
sram_addr_decoder dec (
.lineNumber(SW[3:0]),
.spriteNumber(5'd0),
.address(SRAM_ADDR)
);
assign LEDR[15:0] = SRAM_DQ;
endmodule
| 7.037576 |
module sram_line_en
#(
parameter DATA_WIDTH = 128,
parameter ADDRESS_WIDTH = 7,
parameter INITIALIZE_TO_ZERO = 0
)
(
input i_clk,
input [ADDRESS_WIDTH-1:0] i_address,
input [DATA_WIDTH-1:0] i_write_data,
input i_write_enable,
output [DATA_WIDTH-1:0] o_read_data
);
wire [DATA_WIDTH-1:0] sub_wire0;
assign o_read_data = sub_wire0;
altsyncram altsyncram_component (
.address_a (i_address),
.clock0 (i_clk),
.data_a (i_write_data),
.wren_a (i_write_enable),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "16ktag.rif"
`else
altsyncram_component.init_file = "16ktag.hex"
`endif
,
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2**ADDRESS_WIDTH,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = ADDRESS_WIDTH,
altsyncram_component.width_a = DATA_WIDTH,
altsyncram_component.width_byteena_a = 1;
endmodule
| 6.963436 |
module sram_map(SRAM_ADDR, SRAM_DQ, SRAM_WE_N, SRAM_UB_N, SRAM_LB_N,
set_dq_to_dout, memwr_n, abus, dout, din, ramdisk_page,
jtag_addr, jtag_din, jtag_do, jtag_jtag, jtag_nwe);
output [17:0] SRAM_ADDR;
inout reg[15:0] SRAM_DQ;
output SRAM_WE_N;
output SRAM_UB_N;
output SRAM_LB_N;
input set_dq_to_dout;
input memwr_n;
input [15:0] abus;
input [7:0] dout;
output [7:0] din;
input [2:0] ramdisk_page;
input [17:0] jtag_addr;
input [15:0] jtag_din;
output [15:0] jtag_do = SRAM_DQ;//16'hc3e0;//
input jtag_jtag;
input jtag_nwe;
assign SRAM_ADDR = jtag_jtag ? jtag_addr : {ramdisk_page, abus[15:1]};
assign SRAM_UB_N = jtag_jtag ? 1'b0 : ~abus[0];
assign SRAM_LB_N = jtag_jtag ? 1'b0 : abus[0];
assign SRAM_WE_N = jtag_jtag ? jtag_nwe : memwr_n;
always
if (jtag_jtag & ~jtag_nwe)
SRAM_DQ[15:0] <= jtag_din;
else if (set_dq_to_dout)
SRAM_DQ[15:0] <= abus[0] ? {dout, 8'bZZZZZZZZ} : {8'bZZZZZZZZ, dout};
else
SRAM_DQ[15:0] <= 16'bZZZZZZZZZZZZZZZZ;
assign din = abus[0] ? SRAM_DQ[15:8] : SRAM_DQ[7:0];
endmodule
| 6.57397 |
module sram_controller_tb ();
`define SRAM_ADDR_WIDTH 20
`define SRAM_DATA_WIDTH 16
reg [`SRAM_ADDR_WIDTH - 1:0] sram_addr_reg;
reg oe_n_reg, ce_n_reg, we_n_reg;
// bidirectional data bus
wire [`SRAM_DATA_WIDTH - 1:0] sram_data_inout;
reg [`SRAM_DATA_WIDTH - 1:0] data_to_write;
reg data_we;
assign sram_data_inout = data_we ? data_to_write : `SRAM_DATA_WIDTH'hzzzz;
initial begin
data_we = 1'b0;
dut.mem_array[`SRAM_ADDR_WIDTH'haaaaa] = `SRAM_DATA_WIDTH'h1111;
dut.mem_array[`SRAM_ADDR_WIDTH'h55555] = `SRAM_DATA_WIDTH'haaaa;
oe_n_reg = 1;
ce_n_reg = 1;
we_n_reg = 1;
sram_addr_reg = `SRAM_ADDR_WIDTH'haaaaa;
//case 1 - activate oe_n_reg, then ce_n_reg
#10 // 10ns
oe_n_reg = 0;
ce_n_reg = 1;
we_n_reg = 1;
#10 //20ns
oe_n_reg = 0;
ce_n_reg = 0;
we_n_reg = 1;
#10 //30 ns
if (sram_data_inout != `SRAM_DATA_WIDTH'h1111) begin
$display("test fail");
$stop;
end
#40 //70ns
oe_n_reg = 1;
ce_n_reg = 1;
we_n_reg = 1;
//case 2 - activate ce_n_reg, then oe_n_reg
#10 //80ns
ce_n_reg = 0;
oe_n_reg = 0;
we_n_reg = 1;
#10 //90 ns
if (sram_data_inout != `SRAM_DATA_WIDTH'h1111) begin
$display("test fail");
$stop;
end
#40 //130ns
oe_n_reg = 1;
ce_n_reg = 1;
we_n_reg = 1;
//case 3 - the address changes when ce_n_reg and oe_n_reg is active
#10 //140ns
oe_n_reg = 0;
ce_n_reg = 0;
we_n_reg = 1;
#10 //150 ns
if (sram_data_inout != `SRAM_DATA_WIDTH'h1111) begin
$display("test fail");
$stop;
end
#15 //165ns
sram_addr_reg = `SRAM_ADDR_WIDTH'h55555;
#10 //175
if (sram_data_inout != `SRAM_DATA_WIDTH'haaaa) begin
$display("test fail");
$stop;
end
#15 //190ns
oe_n_reg = 1;
ce_n_reg = 1;
we_n_reg = 1;
//----------------------
//write test
#10 //200ns
oe_n_reg = 0;
ce_n_reg = 0;
we_n_reg = 1;
#10 //210ns
oe_n_reg = 0;
ce_n_reg = 0;
we_n_reg = 0;
#10 //220ns
data_to_write = `SRAM_DATA_WIDTH'h5555;
data_we = 1;
#1 //221
we_n_reg = 1; // hold data
#1 //222
data_we = 0;
#48; //270
if (dut.mem_array[`SRAM_ADDR_WIDTH'h55555] != `SRAM_DATA_WIDTH'h5555) begin
$display("test fail");
$stop;
end
$display("test passed");
$stop;
end
sram_controller dut (
// inputs
.sram_addr_in(sram_addr_reg),
.oe_n(oe_n_reg),
.ce_n(ce_n_reg),
.we_n(we_n_reg),
// bidirectional data bus
.sram_data_inout(sram_data_inout)
);
endmodule
| 6.758857 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_options
#(parameter DATA_WIDTH = 8, ADDR_WIDTH = 16, RAM_SIZE = 65536)
(input clk, input we, input en,
input [ADDR_WIDTH-1 : 0] addr,
input [DATA_WIDTH-1 : 0] data_i,
output reg [DATA_WIDTH-1 : 0] data_o);
// Declareation of the memory cells
(* ram_style = "distributed" *)reg [DATA_WIDTH-1 : 0] RAM [RAM_SIZE - 1:0];
integer idx;
// ------------------------------------
// SRAM cell initialization
// ------------------------------------
// Initialize the sram cells with the values defined in "image.dat."
initial begin
$readmemh("button.mem", RAM);
end
// ------------------------------------
// SRAM read operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
data_o <= data_i;
else
data_o <= RAM[addr];
end
// ------------------------------------
// SRAM write operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
RAM[addr] <= data_i;
end
endmodule
| 6.896868 |
module sram_pack #(
parameter BASE_ADDR = 8'h00
) (
input clk,
// SRAM hardware interface
inout [ 7:0] ram_data_z,
(* IOB = "TRUE" *) output reg [23:0] ram_address,
(* IOB = "TRUE" *) output reg ram_nwe,
output ram_nce,
output ram_noe,
// PicoRV32 packed MEM Bus interface
input [68:0] mem_packed_fwd,
output [32:0] mem_packed_ret
);
assign ram_nce = 0;
assign ram_noe = 0;
initial ram_nwe = 1'b1;
(* IOB = "TRUE" *)reg [7:0] w_reg = 8'h0;
(* IOB = "TRUE" *)reg [7:0] r_reg = 8'h0;
assign ram_data_z = ram_nwe ? 8'hzz : w_reg;
// --------------------------------------------------------------
// Unpack the MEM bus
// --------------------------------------------------------------
// What comes out of unpack
wire [31:0] mem_wdata;
wire [ 3:0] mem_wstrb;
wire mem_valid;
wire [31:0] mem_addr;
reg [23:0] mem_rdata;
reg mem_ready;
munpack mu (
.clk (clk),
.mem_packed_fwd(mem_packed_fwd),
.mem_packed_ret(mem_packed_ret),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_valid(mem_valid),
.mem_addr (mem_addr),
.mem_ready(mem_ready),
// Hack to safe a cycle while keeping r_reg in IOB
.mem_rdata({(mem_ready ? r_reg : 8'h0), mem_rdata})
);
wire isSelected = (mem_addr[31:24] == BASE_ADDR) && mem_valid;
reg [2:0] cycle = 3'h0;
always @(posedge clk) begin
mem_ready <= 1'b0;
ram_nwe <= 1'b1;
if (isSelected && !mem_ready) begin
if (mem_wstrb[cycle]) ram_nwe <= 1'b0;
// always read when selected, picorv ignores it if it's writing
r_reg <= ram_data_z;
mem_rdata[8*(cycle-2)+:8] <= r_reg;
// signal end of access cycle
// read is one clock longer than write because of addr. latch cycle
if (cycle >= (|mem_wstrb ? 3'h3 : 3'h4)) mem_ready <= 1'b1;
cycle <= cycle + 1;
end else begin
mem_rdata <= 24'h0;
cycle <= 3'h0;
end
w_reg <= mem_wdata[8*cycle+:8];
ram_address <= mem_addr[23:0] + cycle;
end
endmodule
| 7.466122 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_player
#(parameter DATA_WIDTH = 8, ADDR_WIDTH = 16, RAM_SIZE = 65536)
(input clk, input we, input en,
input [ADDR_WIDTH-1 : 0] addr,
input [DATA_WIDTH-1 : 0] data_i,
output reg [DATA_WIDTH-1 : 0] data_o);
// Declareation of the memory cells
(* ram_style = "block" *) reg [DATA_WIDTH-1 : 0] RAM [RAM_SIZE - 1:0];
integer idx;
// ------------------------------------
// SRAM cell initialization
// ------------------------------------
// Initialize the sram cells with the values defined in "image.dat."
initial begin
$readmemh("pokemon.mem", RAM);
end
// ------------------------------------
// SRAM read operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
data_o <= data_i;
else
data_o <= RAM[addr];
end
// ------------------------------------
// SRAM write operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
RAM[addr] <= data_i;
end
endmodule
| 6.896868 |
module sram_properties(i_clk, i_ce_n, i_oe_n, i_we_n, i_lb, i_ub,
i_addr, i_data, o_data);
parameter CLOCKRATE_HZ = 50_000_000;
parameter AW = 16, DW = 16;
//
parameter tRC = 12e-9;
parameter tAA = 12e-9;
parameter tCHA = 3e-9;
parameter tACE = 12e-9;
parameter tDOE = 12e-9;
parameter tHZOE = 12e-9;
parameter tHZCE = 3e-9;
parameter tLZCE = 12e-9;
parameter tBA = 6.5e-9;
parameter tHZB = 6.5e-9;
//
parameter tWC = 12e-9;
parameter tSCE = 9e-9;
parameter tAW = 9e-9;
parameter tPWB = 9e-9;
parameter tPWE1 = 9e-9;
parameter tPWE2 = 11e-9;
parameter tSD = 9e-9;
parameter tHD = 9e-9;
parameter tHZWE = 9e-9;
parameter tLZWE = 9e-9;
//
parameter CK_RC = tRC * CLOCKRATE_HZ;
parameter CK_AA = tAA * CLOCKRATE_HZ - 1;
parameter CK_CHA = tCHA * CLOCKRATE_HZ;
parameter CK_ACE = tACE * CLOCKRATE_HZ;
parameter CK_DOE = tDOE * CLOCKRATE_HZ;
parameter CK_HZOE = tHZOE * CLOCKRATE_HZ;
parameter CK_HZCE = tHZCE * CLOCKRATE_HZ;
parameter CK_LZCE = tLZCE * CLOCKRATE_HZ;
parameter CK_BA = tBA * CLOCKRATE_HZ;;
parameter CK_HZB = tHZB * CLOCKRATE_HZ;;
//
input wire i_clk;
//
input wire i_ce_n, i_oe_n, i_we_n;
input wire i_lb, i_ub;
//
input wire [AW-1:0] i_addr;
input wire [DW-1:0] i_data;
output wire [DW-1:0] o_data;
reg [DW-1:0] mem [0:((1<<AW)-1)];
reg [4:0] clocks_since_ce_change;
reg [4:0] clocks_since_oe_change;
reg [4:0] clocks_since_we_change;
reg [4:0] clocks_since_addr_change;
initial clocks_since_ce_change = 0;
always @(posedge i_clk)
if (i_ce_n != $past(i_ce_n))
clocks_since_ce_change = 0;
else if (!(&clocks_since_ce_change)
clocks_since_ce_change <= clocks_since_ce_change+1;
initial clocks_since_oe_change = 0;
always @(posedge i_clk)
if (i_oe_n != $past(i_oe_n))
clocks_since_oe_change = 0;
else if (!(&clocks_since_oe_change)
clocks_since_oe_change <= clocks_since_oe_change+1;
initial clocks_since_we_change = 0;
always @(posedge i_clk)
if (i_we_n != $past(i_we_n))
clocks_since_we_change = 0;
else if (!(&clocks_since_we_change)
clocks_since_we_change <= clocks_since_we_change+1;
initial clocks_since_addr_change = 0;
always @(posedge i_clk)
if (i_addr != $past(i_addr))
clocks_since_addr_change = 0;
else if (!(&clocks_since_addr_change)
clocks_since_addr_change <= clocks_since_addr_change+1;
wire [AW+5-1:0] read_request;
assign read_request = { i_ce_n, i_oe_n, i_we_n, i_lb, i_ub };
reg [AW+5-1:0] past_read_request;
always @(posedge i_clk)
past_read_request <= read_request;
reg [AW-1:0] past_addr;
always @(posedge i_clk)
past_addr <= i_addr;
wire invalid_read_data;
always @(*)
begin
invalid_data = 1'b0;
if (read_request != past_read_request)
invalid_data = 1'b1;
if (clocks_since_ce_change < CK_AA)
invalid_data = 1'b1;
if (clocks_since_oe_change < CK_AA)
invalid_data = 1'b1;
if (clocks_since_addr_change < CK_AA)
invalid_data = 1'b1;
end
always @(posedge i_clk)
if ((!i_ce_n)&&(!$past(i_ce_n))
&&(!i_oe_n)&&(!$past(i_oe_n))
&&(invalid_data))
assert($stable(i_addr));
always @(posedge i_clk)
if ((!i_ce_n)&&(!i_oe_n)&&(!i_we_n)
&&($past((!i_ce_n)&&(!i_oe_n)&&(!i_we_n)))
&&($past(clocks_since_addr_change < CK_RC)))
assert($stable(read_request));
endmodule
| 6.519397 |
module sram_rat #(
parameter ADDRW = 5,
parameter DATAW = 1
) (
input clk,
input rst,
input rd_en1,
input [ADDRW-1:0] rd_addr1,
output reg [DATAW-1:0] rd_data1,
input rd_en2,
input [ADDRW-1:0] rd_addr2,
output reg [DATAW-1:0] rd_data2,
input wr_en,
input [ADDRW-1:0] wr_addr,
input [DATAW-1:0] wr_data
);
reg rd_en1_r;
reg [ADDRW-1:0] rd_addr1_r;
reg [DATAW-1:0] rd_data1_r;
reg rd_en2_r;
reg [ADDRW-1:0] rd_addr2_r;
reg [DATAW-1:0] rd_data2_r;
reg wr_en_r;
reg [ADDRW-1:0] wr_addr_r;
reg [DATAW-1:0] wr_data_r;
reg [DATAW-1:0] memory [0:(1<<ADDRW)-1];
always @(posedge clk) begin
if (rst) begin
rd_en1_r <= 0;
rd_en2_r <= 0;
wr_en_r <= 0;
end else begin
rd_en1_r <= rd_en1;
rd_addr1_r <= rd_addr1;
rd_data1_r <= rd_data1;
rd_en2_r <= rd_en2;
rd_addr2_r <= rd_addr2;
rd_data2_r <= rd_data2;
wr_en_r <= wr_en;
wr_addr_r <= wr_addr;
wr_data_r <= wr_data;
end
end
always @(negedge clk) begin
if (rd_en1_r) rd_data1 <= rd_addr1_r ? memory[rd_addr1_r] : 0;
if (rd_en2_r) rd_data2 <= rd_addr2_r ? memory[rd_addr2_r] : 0;
if (wr_en_r && wr_addr_r) memory[wr_addr_r] <= wr_data_r;
end
endmodule
| 6.530307 |
module on github
Copyright (C) 2018 IdlessChaye
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
`timescale 1ns / 1ns
module sram_read(
input wclk,
input rst,
input enable,
input[4:0] num_read, // the num continue to read
input[18:0] addr,
output reg selec,
output reg write,
output reg read,
output reg[18:0] addr_wr,
output reg done
);
reg[4:0] count_read;
localparam s_idle = 4'b0000;
localparam s_read = 4'b0001;
reg[3:0] status = s_idle;
always @ (posedge wclk) begin
if(rst) begin
selec <= 0;
write <= 0;
read <= 0;
addr_wr <= 0;
count_read <= 0;
done <= 0;
status <= s_idle;
end else begin
case(status)
s_idle: begin
done <= 0;
selec <= 1;
write <= 0;
read <= 1;
addr_wr <= addr;
count_read <= num_read;
if(enable) begin
status <= s_read;
end
end
s_read: begin
count_read <= count_read - 1;
if(count_read == 1) begin
done <= 1;
status <= s_idle;
end else begin
addr_wr <= addr;
end
end
default: begin
status <= s_idle;
end
endcase
end
end
endmodule
| 7.164691 |
module
Copyright (C) 2018 IdlessChaye
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
`timescale 1ns / 1ns
module sram_read_controller(
input enable,
output reg selec_reader,
output reg write_reader,
output reg read_reader,
output reg[18:0] addr_wr_reader,
input[15:0] data_wr_out_reader,
input[18:0] addr_wr,
output[15:0] data_wr_out
);
assign data_wr_out = data_wr_out_reader;
always@* begin
if(enable) begin
selec_reader = 1;
read_reader = 1;
write_reader = 0;
addr_wr_reader = addr_wr;
end else begin
selec_reader = 0;
read_reader = 0;
write_reader = 0;
addr_wr_reader = 0;
end
end
endmodule
| 6.67566 |
module sram_response_gen (
//Inputs
hclk, // AHB Clock
n_hreset, // AHB reset - Active low
// AHB interface
hsel, // AHB2APB select
htrans, // Transfer type
hsize, // AHB Access type - byte, half-word, word
hready_in, // Combined hready across all slaves
RWconflict, // Read coinciding with 2nd stage of write
// Outputs
// AHB interface
hready, // Ready for new bus cycle from target slave
hresp, // Response from the bridge
valid_access
);
// Inputs
// system signals
input hclk; // AHB Clock
input n_hreset; // AHB reset - Active low
// AHB interface
input hsel; // select from AHB bus
input [1:0] htrans; // Transfer type
input [2:0] hsize; // AHB Access type - byte, half-word, word
input hready_in; // Combined hready across all slaves
input RWconflict;
// Outputs
// AHB interface
output hready; // Ready for new bus cycle from target slave
output [1:0] hresp; // Response from the bridge
output valid_access;
wire size_error;
//wire hresp_0_next;
wire valid_access;
wire hready_RWconflict;
wire sram_subs_access;
wire hready_error;
reg r_hresp_0;
reg r_hready;
// Lower hready for one cycle of there is a Read's address phase coinciding
// with a write's data phase for the same mem group
// -------------------------------------------------------------------------
assign hready_RWconflict = RWconflict ? 1'b0 : 1'b1;
// Flag error if access size is 64 bits or more
// hsize [2:0]
// 000 - 8 bit
// 001 - 16 bit
// 010 - 32 bit
// 011 - 64 bit
// 1xx > 64 bit
// htrans [1:0]
// 00 = idle
// 01 = busy
// 10 = non-seq
// 11 = seq
// hresp
// 00 = OK
// 01 = Error
// 10 = Retry
// 11 = Split
// Access > 32 bit is error
assign size_error = (hsize[2] | (hsize[1] & hsize[0])) ? 1'b1 : 1'b0;
//assign valid_access= ( (htrans[1] & hsel) & (~size_error) & (hready_in))?
// 1'b1 : 1'b0;
// Sram subsystem access,
assign sram_subs_access = ((htrans[1] & hsel) & (hready_in)) ? 1'b1 : 1'b0;
// valid access: sram sub system is access and there is not size error
assign valid_access = sram_subs_access & ~size_error;
// Pull hready low only if there is an access has a size error
//assign hready_error = ( ( hsel & htrans[1] & hready_in) & (size_error)) ?
// 1'b0 : 1'b1;
assign hready_error = sram_subs_access & size_error;
// Flag error or ignore access that occurs when hready output is low
//assign hresp_0_next = ((hready_error) | hready_in) ?
// 1'b0 :1'b1;
always @(posedge hclk or negedge n_hreset) begin
if (~n_hreset) begin
r_hready <= 1'b1;
r_hresp_0 <= 1'b0;
end // if (!n_hreset)
else
begin
r_hready <= (~hready_error & hready_RWconflict);
if (hready_error) r_hresp_0 <= 1'b1;
else if (hready_in) r_hresp_0 <= 1'b0;
end
end // always @(posedge hclk ..
assign hready = r_hready;
assign hresp[0] = r_hresp_0;
// Tie hresp[1] to '0' as it is common to both error and OK responses
assign hresp[1] = 1'b0;
endmodule
| 9.353755 |
module sram_rom #(
parameter WIDTH = 32,
parameter DEPTH = 1024
) (
input clka,
input ena,
input [$clog2(DEPTH)-1:0] addra,
output [ WIDTH-1:0] douta
);
reg [WIDTH-1:0] rom[DEPTH];
reg [$clog2(DEPTH)-1:0] addr_r;
// Port A
always @(posedge clka) begin
if (ena) begin
addr_r <= addra;
end
end
assign douta = rom[addr_r];
endmodule
| 7.162179 |
module sram_ro_tb;
reg clock;
reg power1;
reg power2;
always #10 clock <= (clock === 1'b0);
initial begin
clock <= 0;
end
initial begin
$dumpfile("sram_ro.vcd");
$dumpvars(0, sram_ro_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (25) begin
repeat (1000) @(posedge clock);
$display("+1000 cycles");
end
$display("%c[1;31m", 27);
`ifdef GL
$display("Monitor: Timeout, Test GPIO (GL) Failed");
`else
$display("Monitor: Timeout, Test GPIO (RTL) Failed");
`endif
$display("%c[0m", 27);
$finish;
end
wire [37:0] mprj_io; // Most of these are no-connects
wire [15:0] checkbits;
assign checkbits = mprj_io[31:16];
assign mprj_io[3] = 1'b1; // Force CSB high.
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire gpio;
reg RSTB;
// Monitor
initial begin
wait (checkbits == 16'h4800);
`ifdef GL
$display("Monitor: Test R/O SRAM (GL) Started");
`else
$display("Monitor: Test R/O SRAM (RTL) Started");
`endif
wait (checkbits == 16'h0403);
wait (checkbits == 16'haa55);
wait (checkbits == 16'h55aa);
wait (checkbits == 16'hcc33);
wait (checkbits == 16'hff00);
wait (checkbits == 16'h4801);
`ifdef GL
$display("Monitor: Test R/O SRAM (GL) Midpoint");
`else
$display("Monitor: Test R/O SRAM (RTL) Midpoint");
`endif
wait (checkbits == 16'hff00);
wait (checkbits == 16'hcc33);
wait (checkbits == 16'h55aa);
wait (checkbits == 16'haa55);
wait (checkbits == 16'h0403);
wait (checkbits == 16'h4802);
`ifdef GL
$display("Monitor: Test R/O SRAM (GL) Passed");
`else
$display("Monitor: Test R/O SRAM (RTL) Passed");
`endif
$finish;
end
initial begin
RSTB <= 1'b0;
#1000;
RSTB <= 1'b1; // Release reset
#2000;
end
initial begin // Power-up
power1 <= 1'b0;
power2 <= 1'b0;
#200;
power1 <= 1'b1;
#200;
power2 <= 1'b1;
end
always @(checkbits) begin
#1 $display("GPIO state = %b", checkbits);
end
wire VDD3V3;
wire VDD1V8;
wire VSS;
assign VDD3V3 = power1;
assign VDD1V8 = power2;
assign VSS = 1'b0;
// These are the mappings of mprj_io GPIO pads that are set to
// specific functions on startup:
//
// JTAG = mgmt_gpio_io[0] (inout)
// SDO = mgmt_gpio_io[1] (output)
// SDI = mgmt_gpio_io[2] (input)
// CSB = mgmt_gpio_io[3] (input)
// SCK = mgmt_gpio_io[4] (input)
// ser_rx = mgmt_gpio_io[5] (input)
// ser_tx = mgmt_gpio_io[6] (output)
// irq = mgmt_gpio_io[7] (input)
caravel uut (
.vddio (VDD3V3),
.vssio (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
.vdda1 (VDD3V3),
.vdda2 (VDD3V3),
.vssa1 (VSS),
.vssa2 (VSS),
.vccd1 (VDD1V8),
.vccd2 (VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
.clock (clock),
.gpio (gpio),
.mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
.resetb (RSTB)
);
spiflash #(
.FILENAME("sram_ro.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(), // not used
.io3() // not used
);
endmodule
| 6.731765 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_score
#(parameter DATA_WIDTH = 8, ADDR_WIDTH = 16, RAM_SIZE = 65536)
(input clk, input we, input en,
input [ADDR_WIDTH-1 : 0] addr,
input [DATA_WIDTH-1 : 0] data_i,
output reg [DATA_WIDTH-1 : 0] data_o);
// Declareation of the memory cells
(* ram_style = "distributed" *)reg [DATA_WIDTH-1 : 0] RAM [RAM_SIZE - 1:0];
integer idx;
// ------------------------------------
// SRAM cell initialization
// ------------------------------------
// Initialize the sram cells with the values defined in "image.dat."
initial begin
$readmemh("score.mem", RAM);
end
// ------------------------------------
// SRAM read operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
data_o <= data_i;
else
data_o <= RAM[addr];
end
// ------------------------------------
// SRAM write operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
RAM[addr] <= data_i;
end
endmodule
| 6.896868 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sram_sea
#(parameter DATA_WIDTH = 8, ADDR_WIDTH = 16, RAM_SIZE = 65536)
(input clk, input we, input en,
input [ADDR_WIDTH-1 : 0] addr,
input [DATA_WIDTH-1 : 0] data_i,
output reg [DATA_WIDTH-1 : 0] data_o);
// Declareation of the memory cells
(* ram_style = "block" *) reg [DATA_WIDTH-1 : 0] RAM [RAM_SIZE - 1:0];
integer idx;
// ------------------------------------
// SRAM cell initialization
// ------------------------------------
// Initialize the sram cells with the values defined in "image.dat."
initial begin
$readmemh("beach.mem", RAM);
end
// ------------------------------------
// SRAM read operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
data_o <= data_i;
else
data_o <= RAM[addr];
end
// ------------------------------------
// SRAM write operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
RAM[addr] <= data_i;
end
endmodule
| 6.896868 |
module SRAM_sim (
ADDR,
DATA,
WE_N,
OE_N,
UB_N,
LB_N,
CE_N
);
input [17:0] ADDR;
inout [15:0] DATA;
input WE_N;
input OE_N;
input UB_N;
input LB_N;
input CE_N;
reg [15:0] MEM[0:262143];
assign DATA[7:0] = (!CE_N && !OE_N && !LB_N) ? Q[7:0] : 8'bz;
assign DATA[15:8] = (!CE_N && !OE_N && !UB_N) ? Q[15:0] : 8'bz;
wire [15:0] Q = MEM[ADDR];
reg [15:0] D;
initial begin
$readmemh("test", MEM, 0, 7);
end
always @(CE_N or WE_N or UB_N or LB_N or ADDR or DATA or D) begin
if (!CE_N && !WE_N) begin
D[15:0] = MEM[ADDR];
if (!UB_N) begin
D[15:8] = DATA[15:8];
end
if (!LB_N) begin
D[7:0] = DATA[7:0];
end
MEM[ADDR] = D[15:0];
end
end
endmodule
| 6.894424 |
module sram_sp #(
parameter WIDTH = 32,
parameter DEPTH = 10234
) (
input clka,
input ena,
input wea,
input [$clog2(DEPTH)-1:0] addra,
input [ WIDTH-1:0] dina,
output [ WIDTH-1:0] douta
);
reg [WIDTH-1:0] ram[0:DEPTH-1];
reg [$clog2(DEPTH)-1:0] addr_r;
// Port A
always @(posedge clka) begin
if (ena) begin
if (wea) ram[addra] <= dina;
addr_r <= addra;
end
end
assign douta = ram[addr_r];
endmodule
| 7.120601 |
module SRAM_SP_4kx32_wrap (
Q,
CLK,
ME,
WE,
ADR,
D,
reset_n,
scan_mode
);
input [31:0] D;
input CLK;
input ME;
input [3:0] WE;
input [11:0] ADR;
input reset_n;
input scan_mode;
output [31:0] Q;
wire write_accs;
// Detect a write to any byte
assign write_accs = WE[3] | WE[2] | WE[1] | WE[0];
generic_sram_bit #(32, 4096, 12) i_ram (
.clk(CLK),
.n_cs(1'b0),
.n_we(~(write_accs & ME)),
.n_oe(1'b0),
.mask(~{WE[3], WE[3], WE[3], WE[3], WE[3], WE[3], WE[3], WE[3], WE[2], WE[2], WE[2], WE[2], WE[2], WE[2], WE[2], WE[2], WE[1], WE[1], WE[1], WE[1], WE[1], WE[1], WE[1], WE[1], WE[0], WE[0], WE[0], WE[0], WE[0], WE[0], WE[0], WE[0]}),
.ad(ADR),
.din(D),
.dout(Q)
);
endmodule
| 6.723958 |
module sram_sp_be_behave (
clk,
adr,
wr_ena,
wr_dat,
rd_ena,
rd_dat
);
//*** PARAMETER DECLARATION ****************************************************
parameter ADR_WD = 5;
parameter ADR = (1 << ADR_WD);
parameter DAT_WD = 8;
parameter COL_WD = 8;
//*** INPUT/OUTPUT DECLARATION *************************************************
input clk;
input [ADR_WD -1 : 0] adr;
input [DAT_WD/COL_WD-1 : 0] wr_ena;
input [DAT_WD -1 : 0] wr_dat;
input rd_ena;
output reg [DAT_WD -1 : 0] rd_dat;
//*** WIRE & REG DECLARATION ***************************************************
reg [DAT_WD -1 : 0] mem_array[ADR-1 : 0];
//*** MAIN BODY ****************************************************************
genvar i;
generate
for (i = 0; i < DAT_WD / COL_WD; i = i + 1) begin
always @(posedge clk) begin
if (wr_ena[i]) begin
mem_array[adr][(i+1)*COL_WD-1:i*COL_WD] <= wr_dat[(i+1)*COL_WD-1:i*COL_WD];
end
end
end
endgenerate
always @(posedge clk) begin
if (rd_ena) begin
rd_dat <= mem_array[adr];
end else begin
rd_dat <= {{DAT_WD{1'b0}}};
end
end
//*** DEBUG ********************************************************************
`ifndef BEHAVE_MODEL
initial begin
#1;
$display("\t calling sram_sp_be_behave @%m");
end
`endif
endmodule
| 6.665006 |
module chipselects reads and writes to the sram, with 2-cycle *
* read latency and one cycle write latency. *
* *
******************************************************************************/
module sram_sram_0 (
// Inputs
clk,
reset,
address,
byteenable,
read,
write,
writedata,
// Bi-Directional
SRAM_DQ,
// Outputs
readdata,
readdatavalid,
SRAM_ADDR,
SRAM_LB_N,
SRAM_UB_N,
SRAM_CE_N,
SRAM_OE_N,
SRAM_WE_N
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [19: 0] address;
input [ 1: 0] byteenable;
input read;
input write;
input [15: 0] writedata;
// Bi-Directional
inout [15: 0] SRAM_DQ; // SRAM Data bus 16 Bits
// Outputs
output reg [15: 0] readdata;
output reg readdatavalid;
output reg [19: 0] SRAM_ADDR; // SRAM Address bus 18 Bits
output reg SRAM_LB_N; // SRAM Low-byte Data Mask
output reg SRAM_UB_N; // SRAM High-byte Data Mask
output reg SRAM_CE_N; // SRAM Chip chipselect
output reg SRAM_OE_N; // SRAM Output chipselect
output reg SRAM_WE_N; // SRAM Write chipselect
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg is_read;
reg is_write;
reg [15: 0] writedata_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
readdata <= SRAM_DQ;
readdatavalid <= is_read;
SRAM_ADDR <= address;
SRAM_LB_N <= ~(byteenable[0] & (read | write));
SRAM_UB_N <= ~(byteenable[1] & (read | write));
SRAM_CE_N <= ~(read | write);
SRAM_OE_N <= ~read;
SRAM_WE_N <= ~write;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
is_read <= 1'b0;
else
is_read <= read;
end
always @(posedge clk)
begin
if (reset)
is_write <= 1'b0;
else
is_write <= write;
end
always @(posedge clk)
begin
writedata_reg <= writedata;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign SRAM_DQ = (is_write) ? writedata_reg : 16'hzzzz;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
| 7.349016 |
module sram_512w_16b (
Q,
CLK,
CEN,
WEN,
A,
D,
EMA,
EMAW,
EMAS,
TEN,
BEN,
RET1N,
STOV
);
output reg [15:0] Q;
input CLK;
input CEN;
input WEN;
input [8:0] A;
input [15:0] D;
input [2:0] EMA;
input [1:0] EMAW;
input EMAS;
input TEN;
input BEN;
input RET1N;
input STOV;
reg [15:0] data_array[0:511];
always @(posedge CLK) begin
// Use all the unused wires (note at least one of them must be nonzero!)
if (|{EMA, EMAW, EMAS, TEN, BEN, RET1N, STOV}) begin
if (CEN == 1'b0) begin // ACTIVE LOW!!
if (WEN == 1'b0) data_array[A] = D; // ACTIVE LOW!!
else Q = data_array[A];
end
end
end
endmodule
| 7.552978 |
module SRAM_sync #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 10
) (
input wire clk,
input wire [ADDR_WIDTH-1:0] ADDR,
input wire [DATA_WIDTH-1:0] DATA,
(* direct_enable = 1 *) input wire CEn,
input wire OEn,
input wire WEn,
output reg [DATA_WIDTH-1:0] Q
);
reg [DATA_WIDTH-1:0] mem[0:(2**ADDR_WIDTH)-1];
reg [DATA_WIDTH-1:0] data_out;
always @(posedge clk) begin
if (!CEn) begin
if (!OEn) begin
Q <= mem[ADDR];
end
end
if (!CEn) begin
if (!WEn) begin
mem[ADDR] <= DATA;
end
end
end
endmodule
| 8.485738 |
module sram_sync_1r1w #(
parameter WIDTH = 16,
parameter DEPTH = 1 << 8,
parameter WRITE_GRANULE = WIDTH,
parameter R2W_FORWARDING = 0,
parameter PRELOAD_FILE = "",
parameter W_ADDR = $clog2(DEPTH) // let this default
) (
input wire clk,
input wire [ W_ADDR-1:0] waddr,
input wire [ WIDTH-1:0] wdata,
input wire [WIDTH/WRITE_GRANULE-1:0] wen,
input wire [W_ADDR-1:0] raddr,
output wire [ WIDTH-1:0] rdata,
input wire ren
);
`ifdef YOSYS
(* no_rw_check *)
`endif
reg [WIDTH-1:0] mem[0:DEPTH-1];
initial
if (PRELOAD_FILE != "") begin : preload
$readmemh(PRELOAD_FILE, mem);
end
reg [WIDTH-1:0] rdata_raw;
always @(posedge clk) begin : read_port
if (ren) begin
rdata_raw <= mem[raddr];
end
end
always @(posedge clk) begin : write_port
integer i;
for (i = 0; i < WIDTH / WRITE_GRANULE; i = i + 1) begin
if (wen[i]) begin
mem[waddr][i*WRITE_GRANULE+:WRITE_GRANULE] <= wdata[i*WRITE_GRANULE+:WRITE_GRANULE];
end
end
end
// Optional forwarding of write to read data when a read and write of the same
// address are coincident (without this logic you can get garbage)
generate
if (R2W_FORWARDING == 0) begin : no_r2w_forwarding
assign rdata = rdata_raw;
end else begin : r2w_forwarding
genvar g;
reg [ W_ADDR-1:0] raddr_prev;
reg [ W_ADDR-1:0] waddr_prev;
reg [ WIDTH-1:0] wdata_prev;
reg [WIDTH/WRITE_GRANULE-1:0] wen_prev;
always @(posedge clk) begin
raddr_prev <= raddr;
waddr_prev <= waddr;
wdata_prev <= wdata;
wen_prev <= wen;
end
for (g = 0; g < WIDTH / WRITE_GRANULE; g = g + 1) begin
assign rdata[g * WRITE_GRANULE +: WRITE_GRANULE] = raddr_prev == waddr_prev && wen_prev[g] ?
wdata_prev[g * WRITE_GRANULE +: WRITE_GRANULE] : rdata_raw[g * WRITE_GRANULE +: WRITE_GRANULE];
end
end
endgenerate
endmodule
| 7.079754 |
module SRAM_sync_init #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 10,
DATA_HEX_FILE = "dump.hex"
) (
input wire clk,
input wire [ADDR_WIDTH-1:0] ADDR,
input wire [DATA_WIDTH-1:0] DATA,
(* direct_enable = 1 *) input wire cen,
input wire we,
output reg [DATA_WIDTH-1:0] Q
);
(* ramstyle = "no_rw_check" *) reg [DATA_WIDTH-1:0] mem[0:(2**ADDR_WIDTH)-1];
initial begin
$readmemh(DATA_HEX_FILE, mem);
end
always @(posedge clk) begin
Q <= mem[ADDR];
if (cen && we) begin
mem[ADDR] <= DATA;
end
end
endmodule
| 7.936776 |
module SRAM_sync_noinit #(
parameter DATA_WIDTH = 8,
ADDR_WIDTH = 10
) (
input wire clk,
input wire [ADDR_WIDTH-1:0] ADDR,
input wire [DATA_WIDTH-1:0] DATA,
(* direct_enable = 1 *) input wire cen,
input wire we,
output reg [DATA_WIDTH-1:0] Q
);
(* ramstyle = "no_rw_check" *) reg [DATA_WIDTH-1:0] mem[0:(2**ADDR_WIDTH)-1];
always @(posedge clk) begin
Q <= mem[ADDR];
if (cen && we) begin
mem[ADDR] <= DATA;
end
end
endmodule
| 7.156682 |
module sram_tb;
`define NULL 0
reg CLK = 0;
reg [10:0] A = 0;
reg [31:0] D = 0;
reg CEN_EXT = 0;
reg CEN_Q;
reg WEN_EXT = 1;
reg WEN_Q;
wire [31:0] Q;
integer x_file, x_scan_file; // file_handler
integer captured_data;
integer t, i, error;
reg [31:0] D_2D[63:0];
parameter run_cycle = 64;
parameter col = 0;
sram_32b_w2048 sram_instance (
.CLK(CLK),
.CEN(CEN_Q),
.WEN(WEN_Q),
.A (A),
.D (D),
.Q (Q)
);
initial begin
$dumpfile("sram_tb.vcd");
$dumpvars(0, sram_tb);
x_file = $fopen("activation.txt", "r");
// Following three lines are to remove the first three comment lines of the file
x_scan_file = $fscanf(x_file, "%s", captured_data);
x_scan_file = $fscanf(x_file, "%s", captured_data);
x_scan_file = $fscanf(x_file, "%s", captured_data);
#20 CLK = 1'b1;
#20 CLK = 1'b0;
WEN_EXT = 0;
#20 CLK = 1'b1;
for (t = 0; t < run_cycle - 1; t = t + 1) begin
#20 CLK = 1'b0;
A = A + 1;
x_scan_file = $fscanf(x_file, "%32b", D);
D_2D[t][31:0] = D;
$display("%2d-th written data is %h", t, D);
#20 CLK = 1'b1;
end
#20 CLK = 1'b0;
WEN_EXT = 1;
A = 0;
#20 CLK = 1'b1;
#20 CLK = 1'b0;
A = A + 1;
error = 0;
#20 CLK = 1'b1;
for (t = 0; t < run_cycle - 1; t = t + 1) begin // +5 is just for safe buffer
#20 CLK = 1'b0;
A = A + 1;
if (D_2D[t][31:0] == Q) $display("%2d-th read data is %h --- Data matched", t, Q);
else begin
$display("%2d-th read data is %h --- Data ERROR !!!", t, Q);
error = error + 1;
end
#20 CLK = 1'b1;
end
$display("###### Total %2d errors are detected ######", error);
#10 $finish;
end
always @(posedge CLK) begin
WEN_Q <= WEN_EXT;
CEN_Q <= CEN_EXT;
end
endmodule
| 7.84119 |
module so that it is clearer that
// this is for testing only; it is not an SRAM size that is used in the
// Ravenna chip hardware.
//************************************************************************/
`timescale 1ns/10ps
module XSPRAMBLP_16384X32_M8P (Q, D, A, CLK, CEn, WEn, RDY);
output [31:0] Q; // RAM data output
input [31:0] D; // RAM data input bus
input [13:0] A; // RAM address bus
input CLK; // RAM clock
input CEn; // RAM enable
input [31:0] WEn; // RAM per-bit write enable, 0-active
output RDY; // Test output
reg [31:0] mem [0:16384];
reg [31:0] Q;
reg RDY;
integer i, b;
initial begin
for (i = 0; i < 16384; i = i + 1)
mem[i] = 32'b0;
end
always @(posedge CLK or posedge CEn) begin
if (CEn) begin
RDY <= 0;
Q <= 32'b0;
end else begin
RDY <= 1;
for (b = 0; b < 32; b = b + 1)
if (!WEn[b]) mem[A][b] <= D[b];
Q <= mem[A];
end
end
endmodule
| 8.348533 |
module sram #(
parameter ADDR_WIDTH = 8,
DATA_WIDTH = 8,
DEPTH = 256,
MEMFILE = ""
) (
input wire i_clk,
input wire [ADDR_WIDTH-1:0] i_addr,
input wire i_write,
input wire [DATA_WIDTH-1:0] i_data,
output reg [DATA_WIDTH-1:0] o_data
);
reg [DATA_WIDTH-1:0] memory_array[0:DEPTH-1];
initial begin
if (MEMFILE > 0) begin
$display("Loading memory init file '" + MEMFILE + "' into array.");
$readmemh(MEMFILE, memory_array);
end
end
always @(posedge i_clk) begin
if (i_write) begin
memory_array[i_addr] <= i_data;
end else begin
o_data <= memory_array[i_addr];
end
end
endmodule
| 7.388143 |
module SRAM_unq1
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq1
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip select
input logic wz_i; // Active low write control
input logic [0:0] addr_i; // Address bus
output logic [63:0] rd_data_o; // Read data OUT.
input logic [63:0] wr_data_i; // Write data IN.
reg [63:0] mem[0:1]; // memory cells
// Only dpump uses clk_i; this may or may not be the best way to address that
wire unused_ok; assign unused_ok = clk_i;
//////////////////////////////////////////////////////////////////////////////
// READ TRUE_1PORT
assign rd_data_o = (~ez_i & wz_i) ? mem[addr_i] : 'x; // READ TRUE_1PORT
// READ DEBUG
// READ INFO (historical) (also for analyze_reads_and_writes.pl -d9)
always @(ez_i or wz_i or addr_i) if (~ez_i & wz_i) begin
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Reading rd_data_o mem[%1d] <= %16x", $time, addr_i, rd_data_o);
$display("SRAM000 t5 %5d: Read(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)",
$time, addr_i, rd_data_o[63:32], rd_data_o[31: 0]);
$display("");
end
// sync sram see http://www.asic-world.com/examples/verilog/ram_sp_sr_sw.html
// async sram see http://www.asic-world.com/examples/verilog/ram_sp_ar_aw.html
//////////////////////////////////////////////////////////////////////////////
// WRITE TRUE_1PORT
// FIXME use a proper async SRAM (see above)!!! fiddle w/signals outside, in wrapper :(
//
// always @(ez_i or wz_i) begin // doesn't work for verilator
// always @(ez_i or wz_i) begin // NOT AN EDGE!!!!!!!!!
//
always @(negedge wz_i) begin // trial/error debugging - saw behavior on (correct) vcs wave
if (~ez_i & ~wz_i) begin
// WRITE TRUE_1PORT
mem[addr_i] <= wr_data_i;
// WRITE DEBUG
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Wrote wr_data_i mem[%1d] <= %16x", $time, addr_i, wr_data_i);
$display("SRAM000 t5 %5d: Wrote(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)",
$time, addr_i, wr_data_i[63:32], wr_data_i[31: 0]);
$display("");
end
end
endmodule
| 7.057234 |
module SRAM_unq10
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq10
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip select
input logic wz_i; // Active low write control
input logic [5:0] addr_i; // Address bus
output logic [63:0] rd_data_o; // Read data OUT.
input logic [63:0] wr_data_i; // Write data IN.
reg [63:0] mem[0:63]; // memory cells
// Only dpump uses clk_i; this may or may not be the best way to address that
wire unused_ok; assign unused_ok = clk_i;
// True 2-port SRAM *can* read and write at the same time.
assign rd_data_o = (~ez_i) ? mem[addr_i] : 'x; // READ TRUE_2PORT
always @(ez_i or addr_i) if (~ez_i) begin
// READ INFO (historical) (also for analyze_reads_and_writes.pl -d9)
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Reading rd_data_o mem[%1d] <= %16x", $time, addr_i, rd_data_o);
$display("SRAM009 t5 %5d: Read(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, rd_data_o[63:32], rd_data_o[31: 0]);
$display("");
end
//always @(ez_i or wz_i) //does not work for verilator
always @(negedge wz_i) // will it...? it did!!!
if (~ez_i & ~wz_i) begin // WRITE TRUE_2PORT
mem[addr_i] <= wr_data_i;
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Wrote wr_data_i mem[%1d] <= %16x", $time, addr_i, wr_data_i);
$display("SRAM009 t5 %5d: Wrote(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, wr_data_i[63:32], wr_data_i[31: 0]);
$display("");
end
// // This might keep lint from complaining that clk_i is "unused." NOPE
// always @(posedge clk_i) assert (0==0);
endmodule
| 6.5598 |
module SRAM_unq11
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq11
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip select
input logic wz_i; // Active low write control
input logic [5:0] addr_i; // Address bus
output logic [63:0] rd_data_o; // Read data OUT.
input logic [63:0] wr_data_i; // Write data IN.
reg [63:0] mem[0:63]; // memory cells
// Only dpump uses clk_i; this may or may not be the best way to address that
wire unused_ok; assign unused_ok = clk_i;
// True 2-port SRAM *can* read and write at the same time.
assign rd_data_o = (~ez_i) ? mem[addr_i] : 'x; // READ TRUE_2PORT
always @(ez_i or addr_i) if (~ez_i) begin
// READ INFO (historical) (also for analyze_reads_and_writes.pl -d9)
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Reading rd_data_o mem[%1d] <= %16x", $time, addr_i, rd_data_o);
$display("SRAM010 t5 %5d: Read(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, rd_data_o[63:32], rd_data_o[31: 0]);
$display("");
end
//always @(ez_i or wz_i) //does not work for verilator
always @(negedge wz_i) // will it...? it did!!!
if (~ez_i & ~wz_i) begin // WRITE TRUE_2PORT
mem[addr_i] <= wr_data_i;
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Wrote wr_data_i mem[%1d] <= %16x", $time, addr_i, wr_data_i);
$display("SRAM010 t5 %5d: Wrote(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, wr_data_i[63:32], wr_data_i[31: 0]);
$display("");
end
// // This might keep lint from complaining that clk_i is "unused." NOPE
// always @(posedge clk_i) assert (0==0);
endmodule
| 7.122281 |
module SRAM_unq12
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq12
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip select
input logic wz_i; // Active low write control
input logic [5:0] addr_i; // Address bus
output logic [63:0] rd_data_o; // Read data OUT.
input logic [63:0] wr_data_i; // Write data IN.
reg [63:0] mem[0:63]; // memory cells
// Only dpump uses clk_i; this may or may not be the best way to address that
wire unused_ok; assign unused_ok = clk_i;
// True 2-port SRAM *can* read and write at the same time.
assign rd_data_o = (~ez_i) ? mem[addr_i] : 'x; // READ TRUE_2PORT
always @(ez_i or addr_i) if (~ez_i) begin
// READ INFO (historical) (also for analyze_reads_and_writes.pl -d9)
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Reading rd_data_o mem[%1d] <= %16x", $time, addr_i, rd_data_o);
$display("SRAM011 t5 %5d: Read(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, rd_data_o[63:32], rd_data_o[31: 0]);
$display("");
end
//always @(ez_i or wz_i) //does not work for verilator
always @(negedge wz_i) // will it...? it did!!!
if (~ez_i & ~wz_i) begin // WRITE TRUE_2PORT
mem[addr_i] <= wr_data_i;
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Wrote wr_data_i mem[%1d] <= %16x", $time, addr_i, wr_data_i);
$display("SRAM011 t5 %5d: Wrote(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, wr_data_i[63:32], wr_data_i[31: 0]);
$display("");
end
// // This might keep lint from complaining that clk_i is "unused." NOPE
// always @(posedge clk_i) assert (0==0);
endmodule
| 7.067232 |
module SRAM_unq13
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq13
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip select
input logic wz_i; // Active low write control
input logic [5:0] addr_i; // Address bus
output logic [63:0] rd_data_o; // Read data OUT.
input logic [63:0] wr_data_i; // Write data IN.
reg [63:0] mem[0:63]; // memory cells
// Only dpump uses clk_i; this may or may not be the best way to address that
wire unused_ok; assign unused_ok = clk_i;
// True 2-port SRAM *can* read and write at the same time.
assign rd_data_o = (~ez_i) ? mem[addr_i] : 'x; // READ TRUE_2PORT
always @(ez_i or addr_i) if (~ez_i) begin
// READ INFO (historical) (also for analyze_reads_and_writes.pl -d9)
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Reading rd_data_o mem[%1d] <= %16x", $time, addr_i, rd_data_o);
$display("SRAM012 t5 %5d: Read(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, rd_data_o[63:32], rd_data_o[31: 0]);
$display("");
end
//always @(ez_i or wz_i) //does not work for verilator
always @(negedge wz_i) // will it...? it did!!!
if (~ez_i & ~wz_i) begin // WRITE TRUE_2PORT
mem[addr_i] <= wr_data_i;
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Wrote wr_data_i mem[%1d] <= %16x", $time, addr_i, wr_data_i);
$display("SRAM012 t5 %5d: Wrote(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, wr_data_i[63:32], wr_data_i[31: 0]);
$display("");
end
// // This might keep lint from complaining that clk_i is "unused." NOPE
// always @(posedge clk_i) assert (0==0);
endmodule
| 7.190063 |
module SRAM_unq14
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq14
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip select
input logic wz_i; // Active low write control
input logic [5:0] addr_i; // Address bus
output logic [63:0] rd_data_o; // Read data OUT.
input logic [63:0] wr_data_i; // Write data IN.
reg [63:0] mem[0:63]; // memory cells
// Only dpump uses clk_i; this may or may not be the best way to address that
wire unused_ok; assign unused_ok = clk_i;
// True 2-port SRAM *can* read and write at the same time.
assign rd_data_o = (~ez_i) ? mem[addr_i] : 'x; // READ TRUE_2PORT
always @(ez_i or addr_i) if (~ez_i) begin
// READ INFO (historical) (also for analyze_reads_and_writes.pl -d9)
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Reading rd_data_o mem[%1d] <= %16x", $time, addr_i, rd_data_o);
$display("SRAM013 t5 %5d: Read(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, rd_data_o[63:32], rd_data_o[31: 0]);
$display("");
end
//always @(ez_i or wz_i) //does not work for verilator
always @(negedge wz_i) // will it...? it did!!!
if (~ez_i & ~wz_i) begin // WRITE TRUE_2PORT
mem[addr_i] <= wr_data_i;
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Wrote wr_data_i mem[%1d] <= %16x", $time, addr_i, wr_data_i);
$display("SRAM013 t5 %5d: Wrote(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, wr_data_i[63:32], wr_data_i[31: 0]);
$display("");
end
// // This might keep lint from complaining that clk_i is "unused." NOPE
// always @(posedge clk_i) assert (0==0);
endmodule
| 7.704758 |
module SRAM_unq15
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq15
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip select
input logic wz_i; // Active low write control
input logic [5:0] addr_i; // Address bus
output logic [63:0] rd_data_o; // Read data OUT.
input logic [63:0] wr_data_i; // Write data IN.
reg [63:0] mem[0:63]; // memory cells
// Only dpump uses clk_i; this may or may not be the best way to address that
wire unused_ok; assign unused_ok = clk_i;
// True 2-port SRAM *can* read and write at the same time.
assign rd_data_o = (~ez_i) ? mem[addr_i] : 'x; // READ TRUE_2PORT
always @(ez_i or addr_i) if (~ez_i) begin
// READ INFO (historical) (also for analyze_reads_and_writes.pl -d9)
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Reading rd_data_o mem[%1d] <= %16x", $time, addr_i, rd_data_o);
$display("SRAM014 t5 %5d: Read(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, rd_data_o[63:32], rd_data_o[31: 0]);
$display("");
end
//always @(ez_i or wz_i) //does not work for verilator
always @(negedge wz_i) // will it...? it did!!!
if (~ez_i & ~wz_i) begin // WRITE TRUE_2PORT
mem[addr_i] <= wr_data_i;
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Wrote wr_data_i mem[%1d] <= %16x", $time, addr_i, wr_data_i);
$display("SRAM014 t5 %5d: Wrote(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, wr_data_i[63:32], wr_data_i[31: 0]);
$display("");
end
// // This might keep lint from complaining that clk_i is "unused." NOPE
// always @(posedge clk_i) assert (0==0);
endmodule
| 7.681546 |
module SRAM_unq16
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq16
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip select
input logic wz_i; // Active low write control
input logic [5:0] addr_i; // Address bus
output logic [63:0] rd_data_o; // Read data OUT.
input logic [63:0] wr_data_i; // Write data IN.
reg [63:0] mem[0:63]; // memory cells
// Only dpump uses clk_i; this may or may not be the best way to address that
wire unused_ok; assign unused_ok = clk_i;
// True 2-port SRAM *can* read and write at the same time.
assign rd_data_o = (~ez_i) ? mem[addr_i] : 'x; // READ TRUE_2PORT
always @(ez_i or addr_i) if (~ez_i) begin
// READ INFO (historical) (also for analyze_reads_and_writes.pl -d9)
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Reading rd_data_o mem[%1d] <= %16x", $time, addr_i, rd_data_o);
$display("SRAM015 t5 %5d: Read(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, rd_data_o[63:32], rd_data_o[31: 0]);
$display("");
end
//always @(ez_i or wz_i) //does not work for verilator
always @(negedge wz_i) // will it...? it did!!!
if (~ez_i & ~wz_i) begin // WRITE TRUE_2PORT
mem[addr_i] <= wr_data_i;
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Wrote wr_data_i mem[%1d] <= %16x", $time, addr_i, wr_data_i);
$display("SRAM015 t5 %5d: Wrote(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, wr_data_i[63:32], wr_data_i[31: 0]);
$display("");
end
// // This might keep lint from complaining that clk_i is "unused." NOPE
// always @(posedge clk_i) assert (0==0);
endmodule
| 7.597338 |
module SRAM_unq2
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq2
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip select
input logic wz_i; // Active low write control
input logic [0:0] addr_i; // Address bus
output logic [63:0] rd_data_o; // Read data OUT.
input logic [63:0] wr_data_i; // Write data IN.
reg [63:0] mem[0:1]; // memory cells
// Only dpump uses clk_i; this may or may not be the best way to address that
wire unused_ok; assign unused_ok = clk_i;
//////////////////////////////////////////////////////////////////////////////
// READ TRUE_1PORT
assign rd_data_o = (~ez_i & wz_i) ? mem[addr_i] : 'x; // READ TRUE_1PORT
// READ DEBUG
// READ INFO (historical) (also for analyze_reads_and_writes.pl -d9)
always @(ez_i or wz_i or addr_i) if (~ez_i & wz_i) begin
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Reading rd_data_o mem[%1d] <= %16x", $time, addr_i, rd_data_o);
$display("SRAM001 t5 %5d: Read(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)",
$time, addr_i, rd_data_o[63:32], rd_data_o[31: 0]);
$display("");
end
// sync sram see http://www.asic-world.com/examples/verilog/ram_sp_sr_sw.html
// async sram see http://www.asic-world.com/examples/verilog/ram_sp_ar_aw.html
//////////////////////////////////////////////////////////////////////////////
// WRITE TRUE_1PORT
// FIXME use a proper async SRAM (see above)!!! fiddle w/signals outside, in wrapper :(
//
// always @(ez_i or wz_i) begin // doesn't work for verilator
// always @(ez_i or wz_i) begin // NOT AN EDGE!!!!!!!!!
//
always @(negedge wz_i) begin // trial/error debugging - saw behavior on (correct) vcs wave
if (~ez_i & ~wz_i) begin
// WRITE TRUE_1PORT
mem[addr_i] <= wr_data_i;
// WRITE DEBUG
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Wrote wr_data_i mem[%1d] <= %16x", $time, addr_i, wr_data_i);
$display("SRAM001 t5 %5d: Wrote(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)",
$time, addr_i, wr_data_i[63:32], wr_data_i[31: 0]);
$display("");
end
end
endmodule
| 7.017644 |
module SRAM_unq3
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq3
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip select
input logic wz_i; // Active low write control
input logic [0:0] addr_i; // Address bus
output logic [63:0] rd_data_o; // Read data OUT.
input logic [63:0] wr_data_i; // Write data IN.
reg [63:0] mem[0:1]; // memory cells
// Only dpump uses clk_i; this may or may not be the best way to address that
wire unused_ok; assign unused_ok = clk_i;
//////////////////////////////////////////////////////////////////////////////
// READ TRUE_1PORT
assign rd_data_o = (~ez_i & wz_i) ? mem[addr_i] : 'x; // READ TRUE_1PORT
// READ DEBUG
// READ INFO (historical) (also for analyze_reads_and_writes.pl -d9)
always @(ez_i or wz_i or addr_i) if (~ez_i & wz_i) begin
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Reading rd_data_o mem[%1d] <= %16x", $time, addr_i, rd_data_o);
$display("SRAM002 t5 %5d: Read(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)",
$time, addr_i, rd_data_o[63:32], rd_data_o[31: 0]);
$display("");
end
// sync sram see http://www.asic-world.com/examples/verilog/ram_sp_sr_sw.html
// async sram see http://www.asic-world.com/examples/verilog/ram_sp_ar_aw.html
//////////////////////////////////////////////////////////////////////////////
// WRITE TRUE_1PORT
// FIXME use a proper async SRAM (see above)!!! fiddle w/signals outside, in wrapper :(
//
// always @(ez_i or wz_i) begin // doesn't work for verilator
// always @(ez_i or wz_i) begin // NOT AN EDGE!!!!!!!!!
//
always @(negedge wz_i) begin // trial/error debugging - saw behavior on (correct) vcs wave
if (~ez_i & ~wz_i) begin
// WRITE TRUE_1PORT
mem[addr_i] <= wr_data_i;
// WRITE DEBUG
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Wrote wr_data_i mem[%1d] <= %16x", $time, addr_i, wr_data_i);
$display("SRAM002 t5 %5d: Wrote(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)",
$time, addr_i, wr_data_i[63:32], wr_data_i[31: 0]);
$display("");
end
end
endmodule
| 7.043515 |
module SRAM_unq4
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq4
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip select
input logic wz_i; // Active low write control
input logic [0:0] addr_i; // Address bus
output logic [63:0] rd_data_o; // Read data OUT.
input logic [63:0] wr_data_i; // Write data IN.
reg [63:0] mem[0:1]; // memory cells
// Only dpump uses clk_i; this may or may not be the best way to address that
wire unused_ok; assign unused_ok = clk_i;
//////////////////////////////////////////////////////////////////////////////
// READ TRUE_1PORT
assign rd_data_o = (~ez_i & wz_i) ? mem[addr_i] : 'x; // READ TRUE_1PORT
// READ DEBUG
// READ INFO (historical) (also for analyze_reads_and_writes.pl -d9)
always @(ez_i or wz_i or addr_i) if (~ez_i & wz_i) begin
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Reading rd_data_o mem[%1d] <= %16x", $time, addr_i, rd_data_o);
$display("SRAM003 t5 %5d: Read(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)",
$time, addr_i, rd_data_o[63:32], rd_data_o[31: 0]);
$display("");
end
// sync sram see http://www.asic-world.com/examples/verilog/ram_sp_sr_sw.html
// async sram see http://www.asic-world.com/examples/verilog/ram_sp_ar_aw.html
//////////////////////////////////////////////////////////////////////////////
// WRITE TRUE_1PORT
// FIXME use a proper async SRAM (see above)!!! fiddle w/signals outside, in wrapper :(
//
// always @(ez_i or wz_i) begin // doesn't work for verilator
// always @(ez_i or wz_i) begin // NOT AN EDGE!!!!!!!!!
//
always @(negedge wz_i) begin // trial/error debugging - saw behavior on (correct) vcs wave
if (~ez_i & ~wz_i) begin
// WRITE TRUE_1PORT
mem[addr_i] <= wr_data_i;
// WRITE DEBUG
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Wrote wr_data_i mem[%1d] <= %16x", $time, addr_i, wr_data_i);
$display("SRAM003 t5 %5d: Wrote(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)",
$time, addr_i, wr_data_i[63:32], wr_data_i[31: 0]);
$display("");
end
end
endmodule
| 7.435426 |
module SRAM_unq5
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq5
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip select
input logic wz_i; // Active low write control
input logic [5:0] addr_i; // Address bus
output logic [63:0] rd_data_o; // Read data OUT.
input logic [63:0] wr_data_i; // Write data IN.
reg [63:0] mem[0:63]; // memory cells
// Only dpump uses clk_i; this may or may not be the best way to address that
wire unused_ok; assign unused_ok = clk_i;
// True 2-port SRAM *can* read and write at the same time.
assign rd_data_o = (~ez_i) ? mem[addr_i] : 'x; // READ TRUE_2PORT
always @(ez_i or addr_i) if (~ez_i) begin
// READ INFO (historical) (also for analyze_reads_and_writes.pl -d9)
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Reading rd_data_o mem[%1d] <= %16x", $time, addr_i, rd_data_o);
$display("SRAM004 t5 %5d: Read(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, rd_data_o[63:32], rd_data_o[31: 0]);
$display("");
end
//always @(ez_i or wz_i) //does not work for verilator
always @(negedge wz_i) // will it...? it did!!!
if (~ez_i & ~wz_i) begin // WRITE TRUE_2PORT
mem[addr_i] <= wr_data_i;
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Wrote wr_data_i mem[%1d] <= %16x", $time, addr_i, wr_data_i);
$display("SRAM004 t5 %5d: Wrote(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, wr_data_i[63:32], wr_data_i[31: 0]);
$display("");
end
// // This might keep lint from complaining that clk_i is "unused." NOPE
// always @(posedge clk_i) assert (0==0);
endmodule
| 6.988692 |
module SRAM_unq6
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq6
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip select
input logic wz_i; // Active low write control
input logic [5:0] addr_i; // Address bus
output logic [63:0] rd_data_o; // Read data OUT.
input logic [63:0] wr_data_i; // Write data IN.
reg [63:0] mem[0:63]; // memory cells
// Only dpump uses clk_i; this may or may not be the best way to address that
wire unused_ok; assign unused_ok = clk_i;
// True 2-port SRAM *can* read and write at the same time.
assign rd_data_o = (~ez_i) ? mem[addr_i] : 'x; // READ TRUE_2PORT
always @(ez_i or addr_i) if (~ez_i) begin
// READ INFO (historical) (also for analyze_reads_and_writes.pl -d9)
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Reading rd_data_o mem[%1d] <= %16x", $time, addr_i, rd_data_o);
$display("SRAM005 t5 %5d: Read(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, rd_data_o[63:32], rd_data_o[31: 0]);
$display("");
end
//always @(ez_i or wz_i) //does not work for verilator
always @(negedge wz_i) // will it...? it did!!!
if (~ez_i & ~wz_i) begin // WRITE TRUE_2PORT
mem[addr_i] <= wr_data_i;
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Wrote wr_data_i mem[%1d] <= %16x", $time, addr_i, wr_data_i);
$display("SRAM005 t5 %5d: Wrote(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, wr_data_i[63:32], wr_data_i[31: 0]);
$display("");
end
// // This might keep lint from complaining that clk_i is "unused." NOPE
// always @(posedge clk_i) assert (0==0);
endmodule
| 6.716065 |
module SRAM_unq7
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq7
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip select
input logic wz_i; // Active low write control
input logic [5:0] addr_i; // Address bus
output logic [63:0] rd_data_o; // Read data OUT.
input logic [63:0] wr_data_i; // Write data IN.
reg [63:0] mem[0:63]; // memory cells
// Only dpump uses clk_i; this may or may not be the best way to address that
wire unused_ok; assign unused_ok = clk_i;
// True 2-port SRAM *can* read and write at the same time.
assign rd_data_o = (~ez_i) ? mem[addr_i] : 'x; // READ TRUE_2PORT
always @(ez_i or addr_i) if (~ez_i) begin
// READ INFO (historical) (also for analyze_reads_and_writes.pl -d9)
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Reading rd_data_o mem[%1d] <= %16x", $time, addr_i, rd_data_o);
$display("SRAM006 t5 %5d: Read(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, rd_data_o[63:32], rd_data_o[31: 0]);
$display("");
end
//always @(ez_i or wz_i) //does not work for verilator
always @(negedge wz_i) // will it...? it did!!!
if (~ez_i & ~wz_i) begin // WRITE TRUE_2PORT
mem[addr_i] <= wr_data_i;
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Wrote wr_data_i mem[%1d] <= %16x", $time, addr_i, wr_data_i);
$display("SRAM006 t5 %5d: Wrote(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, wr_data_i[63:32], wr_data_i[31: 0]);
$display("");
end
// // This might keep lint from complaining that clk_i is "unused." NOPE
// always @(posedge clk_i) assert (0==0);
endmodule
| 6.962574 |
module SRAM_unq8
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq8
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip select
input logic wz_i; // Active low write control
input logic [5:0] addr_i; // Address bus
output logic [63:0] rd_data_o; // Read data OUT.
input logic [63:0] wr_data_i; // Write data IN.
reg [63:0] mem[0:63]; // memory cells
// Only dpump uses clk_i; this may or may not be the best way to address that
wire unused_ok; assign unused_ok = clk_i;
// True 2-port SRAM *can* read and write at the same time.
assign rd_data_o = (~ez_i) ? mem[addr_i] : 'x; // READ TRUE_2PORT
always @(ez_i or addr_i) if (~ez_i) begin
// READ INFO (historical) (also for analyze_reads_and_writes.pl -d9)
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Reading rd_data_o mem[%1d] <= %16x", $time, addr_i, rd_data_o);
$display("SRAM007 t5 %5d: Read(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, rd_data_o[63:32], rd_data_o[31: 0]);
$display("");
end
//always @(ez_i or wz_i) //does not work for verilator
always @(negedge wz_i) // will it...? it did!!!
if (~ez_i & ~wz_i) begin // WRITE TRUE_2PORT
mem[addr_i] <= wr_data_i;
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Wrote wr_data_i mem[%1d] <= %16x", $time, addr_i, wr_data_i);
$display("SRAM007 t5 %5d: Wrote(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, wr_data_i[63:32], wr_data_i[31: 0]);
$display("");
end
// // This might keep lint from complaining that clk_i is "unused." NOPE
// always @(posedge clk_i) assert (0==0);
endmodule
| 7.289581 |
module SRAM_unq9
//
// Usage: SRAM(n_words), where
//
// nwords is the number of (32-bit) words in the SRAM.
// WARNING test_mode "TEST5" is setting data_width to 64
module SRAM_unq9
(clk_i, ez_i, wz_i, addr_i, rd_data_o, wr_data_i);
input logic clk_i;
input logic ez_i; // Active low chip select
input logic wz_i; // Active low write control
input logic [5:0] addr_i; // Address bus
output logic [63:0] rd_data_o; // Read data OUT.
input logic [63:0] wr_data_i; // Write data IN.
reg [63:0] mem[0:63]; // memory cells
// Only dpump uses clk_i; this may or may not be the best way to address that
wire unused_ok; assign unused_ok = clk_i;
// True 2-port SRAM *can* read and write at the same time.
assign rd_data_o = (~ez_i) ? mem[addr_i] : 'x; // READ TRUE_2PORT
always @(ez_i or addr_i) if (~ez_i) begin
// READ INFO (historical) (also for analyze_reads_and_writes.pl -d9)
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Reading rd_data_o mem[%1d] <= %16x", $time, addr_i, rd_data_o);
$display("SRAM008 t5 %5d: Read(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, rd_data_o[63:32], rd_data_o[31: 0]);
$display("");
end
//always @(ez_i or wz_i) //does not work for verilator
always @(negedge wz_i) // will it...? it did!!!
if (~ez_i & ~wz_i) begin // WRITE TRUE_2PORT
mem[addr_i] <= wr_data_i;
$display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i);
$display("%m %1d: Wrote wr_data_i mem[%1d] <= %16x", $time, addr_i, wr_data_i);
$display("SRAM008 t5 %5d: Wrote(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", $time, addr_i, wr_data_i[63:32], wr_data_i[31: 0]);
$display("");
end
// // This might keep lint from complaining that clk_i is "unused." NOPE
// always @(posedge clk_i) assert (0==0);
endmodule
| 6.622155 |
module SRAM_V #(
parameter mem_size = 1024,
parameter word_size = 8,
parameter addr_size = 10
) (
d_in,
i_clk,
rw,
addr_in,
data_out
);
input i_clk;
input wire [word_size-1:0] d_in; ///data input //
input rw; ///read/write , if rw => 0 , write to memory else read from the memory///
///for
input [addr_size -1:0] addr_in; ///address bus ///
output reg [word_size-1:0] data_out; //data bus ///
///defining a memory ///
reg [word_size-1:0] mem[mem_size-1:0];
always @(posedge i_clk) begin
if (rw == 1'b0) begin
mem[addr_in] <= d_in;
end else begin
data_out <= mem[addr_in];
end
end
endmodule
| 8.132946 |
module sram_w (
input clk,
w,
rst,
cs,
input [11:0] addr,
input [7:0] data_in,
output reg [7:0] data_out
);
reg signed [7:0] memory[2047:0]; //动态参数
always @(posedge clk, negedge rst) begin
if (!rst) data_out <= 8'd0;
else
case (cs)
1: begin
if (w == 1) memory[addr] <= data_in;
else data_out <= memory[addr];
end
default: ;
endcase
end
endmodule
| 7.812766 |
module sram_width_converter #(
parameter aw = 10
) (
input wire i_clk,
//8-bit Subservient interface
input wire [aw-1:0] i_sram_waddr,
input wire [7:0] i_sram_wdata,
input wire i_sram_wen,
input wire [aw-1:0] i_sram_raddr,
output wire [7:0] o_sram_rdata,
input wire i_sram_ren,
//32-bit OpenRAM interface
output wire o_csb0,
output wire o_web0,
output wire [3:0] o_wmask0,
output wire [aw-3:0] o_addr0,
output wire [32:0] o_din0,
input wire [32:0] i_dout0
);
assign o_csb0 = !(i_sram_wen | i_sram_ren);
assign o_web0 = !i_sram_wen;
assign o_wmask0 = 4'd1 << i_sram_waddr[1:0]; //Decode address LSB to write mask
assign o_addr0 = i_sram_wen ? i_sram_waddr[aw-1:2] : i_sram_raddr[aw-1:2]; //Memory is 32-bit word-addressed. Cut off 2 LSB
assign o_din0 = {1'b0, {4{i_sram_wdata}}}; //Mirror write data to all byte lanes
reg [1:0] sram_bsel;
always @(posedge i_clk) sram_bsel <= i_sram_raddr[1:0];
assign o_sram_rdata = i_dout0[sram_bsel*8+:8]; //Pick the right byte from the read data
endmodule
| 7.752413 |
module sram_wrapper (
input wire clk,
input wire rstn,
// data bus interface
input wire [ `XLEN-1:0] d_addr, // byte addr
input wire d_w_rb,
input wire [$clog2(`BUS_ACC_CNT)-1:0] d_acc,
output wire [ `BUS_WIDTH-1:0] d_rdata,
input wire [ `BUS_WIDTH-1:0] d_wdata,
input wire d_req,
output wire d_resp,
output wire sram_d_fault,
// instruction bus interface
input wire [ `XLEN-1:0] i_addr, // byte addr
input wire i_w_rb,
input wire [$clog2(`BUS_ACC_CNT)-1:0] i_acc,
output wire [ `BUS_WIDTH-1:0] i_rdata,
input wire [ `BUS_WIDTH-1:0] i_wdata,
input wire i_req,
output wire i_resp,
output wire sram_i_fault,
output wire sram_ce_bar,
output wire sram_oe_bar,
output wire sram_we_bar,
output wire sram_data_dir,
input wire [ 7:0] sram_data_in,
output wire [ 7:0] sram_data_out,
output wire [18:0] sram_addr
);
wire [ `XLEN-1:0] addr;
wire w_rb;
wire [$clog2(`BUS_ACC_CNT)-1:0] acc;
wire [ `BUS_WIDTH-1:0] rdata;
wire [ `BUS_WIDTH-1:0] wdata;
wire req;
wire resp;
wire fault;
bus_duplexer bus_duplexer (
.clk (clk),
.rstn(rstn),
.d_addr (d_addr),
.d_w_rb (d_w_rb),
.d_acc (d_acc),
.d_wdata(d_wdata),
.d_rdata(d_rdata),
.d_req (d_req),
.d_resp (d_resp),
.periph_d_fault(sram_d_fault),
.i_addr (i_addr),
.i_w_rb (i_w_rb),
.i_acc (i_acc),
.i_wdata(i_wdata),
.i_rdata(i_rdata),
.i_req (i_req),
.i_resp (i_resp),
.periph_i_fault(sram_i_fault),
.addr (addr),
.w_rb (w_rb),
.acc (acc),
.rdata(rdata),
.wdata(wdata),
.req (req),
.resp (resp),
.fault(fault)
);
sram_controller sram_controller (
.clk (clk),
.rstn(rstn),
.addr (addr[$clog2(`SRAM_SIZE)-1:0]),
.w_rb (w_rb),
.acc (acc),
.rdata(rdata),
.wdata(wdata),
.req (req),
.resp (resp),
.fault(fault),
.sram_ce_bar (sram_ce_bar),
.sram_oe_bar (sram_oe_bar),
.sram_we_bar (sram_we_bar),
.sram_data_dir(sram_data_dir),
.sram_data_in (sram_data_in),
.sram_data_out(sram_data_out),
.sram_addr (sram_addr)
);
endmodule
| 6.559872 |
module SRAM_Wrapper_top #(
parameter WIDTH_WB_DATA = 32,
parameter WIDTH_ADD = 32,
parameter IMC_OUT_WIDTH = 16, // Deepak -30/12/22 -edited to 16 bit(previously 64 bit)for MPW8
parameter SRAM_OUT_WIDTH = 16,
parameter MEM_ROW = 16
) (
inout VCLP, // connect to Analog IO
inout EN, // connect to Analog IO
inout Iref0, // connect to Analog IO
inout Iref1, // connect to Analog IO
inout Iref2, // connect to Analog IO
inout Iref3, // connect to Analog IO
inout VDD,
inout VSS,
inout Iout0, // Deepak -30/12/22 - added for MPW8
inout Iout1, // Deepak -30/12/22 - added for MPW8
inout Iout2, // Deepak -30/12/22 - added for MPW8
inout Iout3, // Deepak -30/12/22 - added for MPW8
input clk, //Common clock
input reset_n, //wb_rst_i
input wbs_we_i, //wbs_we_i=0 for read ;wbs_we_i=1 for write
input [WIDTH_WB_DATA - 1 : 0] wishbone_buffer_data_in, //wbs_dat_i
input [WIDTH_ADD - 1 : 0] wishbone_rw_addr, //wishbone_addr
output [WIDTH_WB_DATA - 1 : 0] wishbone_databus_out, //wbs_dat_o
output EN_VCLP, //Deepak_28/11/22: needs to be passed to analog_DUT for EN & VCLP enable
//currently taking out to LA
output MAC_starting, // Deepak : Enable for MUX for Iref
output [1:0] OB_demux, // Deepak: select line for Irefs
output [2:0] controller_opcode,
output [1:0] controller_ext_state,
output [2:0] controller_int_state,
output full_IB,
output full_WB,
output full_SA,
output full_OB,
output empty_IB,
output empty_WB,
output empty_SA,
output empty_OB
);
//=============================== Signal Declaration =========================================
wire [ IMC_OUT_WIDTH -1 : 0] IMC_out;
wire [SRAM_OUT_WIDTH -1 : 0] SA_out;
wire [ MEM_ROW -1 : 0] SRAM_Din; // RICHA : New!!
wire PRE_SRAM;
wire [ MEM_ROW -1:0] WWL;
wire WE;
wire PRE_VLSA;
wire PRE_CLSA;
wire PRE_A;
wire [ MEM_ROW -1:0] RWL;
wire [ MEM_ROW -1:0] RWLB;
wire SAEN;
wire EN_VCLP; // RICHA : enable for EN and VCLP
reg [ 7:0] WWLD;
//===========================================================================
//===========SRAM Controller Instantiation =================================
top Digital_DUT (
.clk(clk),
.reset_n(reset_n),
.wbs_we_i(wbs_we_i),
.wishbone_buffer_data_in(wishbone_buffer_data_in),
.wishbone_rw_addr(wishbone_rw_addr),
.wishbone_databus_out(wishbone_databus_out),
.IMC_out(IMC_out),
.SA_out(SA_out),
.SRAM_Din(SRAM_Din),
.PRE_SRAM(PRE_SRAM),
.WWL(WWL),
.WE(WE),
.PRE_VLSA(PRE_VLSA),
.PRE_CLSA(PRE_CLSA),
.PRE_A(PRE_A),
.RWL(RWL),
.RWLB(RWLB),
.SAEN(SAEN),
.en(EN_VCLP),
.WWLD(WWLD),
.MAC_starting(MAC_starting),
.OB_demux(OB_demux),
.controller_opcode(controller_opcode),
.controller_ext_state(controller_ext_state),
.controller_int_state(controller_int_state),
.full_IB(full_IB),
.full_WB(full_WB),
.full_SA(full_SA),
.full_OB(full_OB),
.empty_IB(empty_IB),
.empty_WB(empty_WB),
.empty_SA(empty_SA),
.empty_OB(empty_OB)
);
//===========================================================================
//============================ SRAM Array Analog part instantiation =========
Integrated_bitcell_with_dummy_cells Analog_DUT (
.WWL(WWL),
.WWLD(WWLD),
.RWL(RWL),
.RWLB(RWLB),
.Din(SRAM_Din),
.WE(WE),
.PRE_SRAM(PRE_SRAM),
.PRE_VLSA(PRE_VLSA),
.PRE_CLSA(PRE_CLSA),
.PRE_A(PRE_A),
.SAEN(SAEN),
.VCLP(VCLP),
.EN(EN),
.Iref0(Iref0),
.Iref1(Iref1),
.Iref2(Iref2),
.Iref3(Iref3),
.Iout0(Iout0), // Deepak -30/12/22 - added for MPW8
.Iout1(Iout1), // Deepak -30/12/22 - added for MPW8
.Iout2(Iout2), // Deepak -30/12/22 - added for MPW8
.Iout3(Iout3), // Deepak -30/12/22 - added for MPW8
.VSS(VSS),
.VDD(VDD),
.OUT(IMC_out[15:0]), // Deepak -30/12/22 - edited for MPW8(CLSA output)
.SA_OUT(SA_out)
);
//===========================================================================
endmodule
| 7.345005 |
module on github
Copyright (C) 2018 IdlessChaye
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
`timescale 1ns / 1ns
module sram_write(
input wclk,
input rst,
input enable,
input[4:0] num_write, // the num continue to write
input[18:0] addr,
input[15:0] data,
output reg selec,
output reg write,
output reg read,
output reg[18:0] addr_wr,
output reg[15:0] data_wr_in,
output reg done
);
reg[4:0] count_write;
localparam s_idle = 4'b0000;
localparam s_write = 4'b0001;
localparam s_write_wait = 4'b0010;
reg[3:0] status = s_idle;
always @ (posedge wclk) begin
if(rst) begin
selec <= 0;
write <= 0;
read <= 0;
addr_wr <= 0;
data_wr_in <= 0;
count_write <= 0;
done <= 0;
status <= s_idle;
end else begin
case(status)
s_idle: begin
done <= 0;
selec <= 1;
write <= 1;
read <= 0;
addr_wr <= addr;
data_wr_in <= data;
count_write <= num_write;
if(enable) begin
status <= s_write_wait;
end
end
s_write: begin
count_write <= count_write - 1;
if(count_write == 1) begin
done <= 1;
status <= s_idle;
end else begin
addr_wr <= addr;
data_wr_in <= data;
status <= s_write_wait;
end
end
s_write_wait: begin
status <= s_write;
end
default: begin
status <= s_idle;
end
endcase
end
end
endmodule
| 7.164691 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sran1
#(parameter DATA_WIDTH = 8, ADDR_WIDTH = 16, RAM_SIZE = 65536)
(input clk, input we, input en,
input [ADDR_WIDTH-1 : 0] addr,
input [DATA_WIDTH-1 : 0] data_i,
output reg [DATA_WIDTH-1 : 0] data_o);
// Declareation of the memory cells
(* ram_style = "block" *) reg [DATA_WIDTH-1 : 0] RAM [RAM_SIZE - 1:0];
integer idx;
// ------------------------------------
// SRAM cell initialization
// ------------------------------------
// Initialize the sram cells with the values defined in "image.dat."
initial begin
$readmemh("images1.mem", RAM);
end
// ------------------------------------
// SRAM read operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
data_o <= data_i;
else
data_o <= RAM[addr];
end
// ------------------------------------
// SRAM write operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
RAM[addr] <= data_i;
end
endmodule
| 6.896868 |
module show you how to infer an initialized SRAM block
// in your circuit using the standard Verilog code. The initial
// values of the SRAM cells is defined in the text file "image.dat"
// Each line defines a cell value. The number of data in image.dat
// must match the size of the sram block exactly.
module sran2
#(parameter DATA_WIDTH = 8, ADDR_WIDTH = 16, RAM_SIZE = 65536)
(input clk, input we, input en,
input [ADDR_WIDTH-1 : 0] addr,
input [DATA_WIDTH-1 : 0] data_i,
output reg [DATA_WIDTH-1 : 0] data_o);
// Declareation of the memory cells
(* ram_style = "block" *) reg [DATA_WIDTH-1 : 0] RAM [RAM_SIZE - 1:0];
integer idx;
// ------------------------------------
// SRAM cell initialization
// ------------------------------------
// Initialize the sram cells with the values defined in "image.dat."
initial begin
$readmemh("firework.mem", RAM);
end
// ------------------------------------
// SRAM read operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
data_o <= data_i;
else
data_o <= RAM[addr];
end
// ------------------------------------
// SRAM write operation
// ------------------------------------
always@(posedge clk)
begin
if (en & we)
RAM[addr] <= data_i;
end
endmodule
| 6.896868 |
module srash (
a,
sh,
b
) /* synthesis syn_builtin_du = "weak" */;
parameter A_width = 64;
parameter SH_width = 6;
input signed [A_width:0] a;
input [SH_width-1:0] sh;
output wire [A_width:0] b;
assign b = a >>> sh;
endmodule
| 7.197473 |
module srasll (
u0,
u1,
s0,
s1,
y0,
y1,
y2,
y3,
y4,
y5,
y6,
y7,
x0,
x1,
x2,
x3,
x4,
x5,
x6,
x7
);
input [4:0] u0;
input [2:0] u1;
input signed [3:0] s0;
input signed [5:0] s1;
output [15:0] y0;
output [15:0] y1;
output [15:0] y2;
output [15:0] y3;
output [15:0] y4;
output [15:0] y5;
output [15:0] y6;
output [15:0] y7;
output signed [13:0] x0;
output signed [13:0] x1;
output signed [13:0] x2;
output signed [13:0] x3;
output signed [13:0] x4;
output signed [13:0] x5;
output signed [13:0] x6;
output signed [13:0] x7;
assign y0 = s0 >> s1;
assign y1 = s0 >>> s1;
assign y2 = u0 >> s1;
assign y3 = u0 >>> s1;
assign y4 = s0 >> u1;
assign y5 = s0 >>> u1;
assign y6 = u0 >> u1;
assign y7 = u0 >>> u1;
assign x0 = s0 >> s1;
assign x1 = s0 >>> s1;
assign x2 = u0 >> s1;
assign x3 = u0 >>> s1;
assign x4 = s0 >> u1;
assign x5 = s0 >>> u1;
assign x6 = u0 >> u1;
assign x7 = u0 >>> u1;
endmodule
| 6.857687 |
module SRA_1_4bit (
out,
cin,
cout,
a
); //select=0 leftshift, select=1 rightshift
input [3:0] a;
input cin;
output [3:0] out;
output cout;
Shift_1_4bit S (
out,
cin,
cout,
a,
1'b1
);
endmodule
| 6.784122 |
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