code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module SRA_2 (
shiftA,
A
);
input [64:0] A;
output [64:0] shiftA;
assign shiftA[62:0] = A[64:2];
assign shiftA[63] = A[64];
assign shiftA[64] = A[64];
endmodule
| 6.647093 |
module sra_control_ID_EX_stage (
input signal_sra,
input clock,
output reg out_sra_control_reg
);
always @(posedge clock) out_sra_control_reg = signal_sra;
endmodule
| 6.694562 |
module sra_module_testbench ();
reg [31:0] inp;
wire [31:0] outfifth;
reg select1, select2, select3, select4, select5;
sra_module call (
outfifth,
inp,
select1,
select2,
select3,
select4,
select5
);
initial begin
inp = 32'b11111111111111111111111111111110;
select1 = 1'b1;
select2 = 1'b0;
select3 = 1'b0;
select4 = 1'b0;
select5 = 1'b0;
#`DELAY;
inp = 32'b11111111111111111111111111111010;
select1 = 1'b0;
select2 = 1'b1;
select3 = 1'b0;
select4 = 1'b0;
select5 = 1'b0;
#`DELAY;
inp = 32'b11111111111111111111111111110010;
select1 = 1'b1;
select2 = 1'b1;
select3 = 1'b0;
select4 = 1'b0;
select5 = 1'b0;
#`DELAY;
inp = 32'b10000000000000000000000000000000;
select1 = 1'b0;
select2 = 1'b0;
select3 = 1'b0;
select4 = 1'b0;
select5 = 1'b1;
#`DELAY;
inp = 32'b10000000000000000000000000000000;
select1 = 1'b1;
select2 = 1'b1;
select3 = 1'b1;
select4 = 1'b1;
select5 = 1'b0;
#`DELAY;
inp = 32'b10000000000000000000000000000000;
select1 = 1'b1;
select2 = 1'b1;
select3 = 1'b1;
select4 = 1'b1;
select5 = 1'b1;
#`DELAY;
end
initial begin
$monitor(
"time = %2d, inp =%32b, out=%32b, select1=%1b, select2=%1b, select3=%1b, select4=%1b, select5=%1b ",
$time, inp, outfifth, select1, select2, select3, select4, select5);
end
endmodule
| 6.619815 |
module sra_srl (
funct7,
datain_A,
datain_B,
out
);
parameter WIRE = 32;
input [WIRE-1:0] datain_A, datain_B;
input funct7;
output [WIRE-1:0] out;
assign out = funct7 ? {1'b1, (datain_A[WIRE-2:0] >> datain_B[5:0])} : datain_A >> datain_B[5:0];
endmodule
| 6.669447 |
module
module src2dest#(
parameter DATAWIDTH = 8
)
(
input src_CLK ,
input dest_CLK ,
input RSTn ,
input [ DATAWIDTH - 1 : 0 ] src_data_in ,
output [ DATAWIDTH - 1 : 0 ] dest_data_out ,
output src_data_valid ,
output dest_data_valid
);
wire [ DATAWIDTH - 1 : 0 ] src2dest_data;
wire [ DATAWIDTH - 1 :0 ] src2dest_load;
src_domain src_domain_inst( .CLK (src_CLK ) ,
.RSTn (RSTn ) ,
.src_data_in (src_data_in ) ,
.src2dest_data (src2dest_data ) ,
.src2dest_load (src2dest_load ) ,
.src_data_valid (src_data_valid )) ;
dest_domain dest_domain_inst(.CLK (dest_CLK ) ,
.RSTn (RSTn ) ,
.src2dest_data (src2dest_data ) ,
.src2dest_load (src2dest_load ) ,
.dest_data_valid (dest_data_valid) ,
.dest_data_out (dest_data_out )) ;
endmodule
| 7.342644 |
module srcA (
input [`ICODEBUS] icode,
input [ `REGBUS] rA,
output [ `REGBUS] d_srcA
);
assign d_srcA= (icode == `IRRMOVQ |icode == `IRMMOVQ | icode == `IOPQ |icode == `IPUSHQ )?rA:
(icode == `IRET | icode == `IPOPQ ) ? `RRSP:
`RNONE;
endmodule
| 6.810107 |
module src_a_mux (
input wire [`SRC_A_SEL_WIDTH-1:0] src_a_sel,
input wire [ `ADDR_LEN-1:0] pc,
input wire [ `DATA_LEN-1:0] rs1,
output reg [ `DATA_LEN-1:0] alu_src_a
);
always @(*) begin
case (src_a_sel)
`SRC_A_RS1: alu_src_a = rs1;
`SRC_A_PC: alu_src_a = pc;
default: alu_src_a = 0;
endcase // case (src_a_sel)
end
endmodule
| 8.370023 |
module src_b_mux (
input wire [`SRC_B_SEL_WIDTH-1:0] src_b_sel,
input wire [ `DATA_LEN-1:0] imm,
input wire [ `DATA_LEN-1:0] rs2,
output reg [ `DATA_LEN-1:0] alu_src_b
);
always @(*) begin
case (src_b_sel)
`SRC_B_RS2: alu_src_b = rs2;
`SRC_B_IMM: alu_src_b = imm;
`SRC_B_FOUR: alu_src_b = 4;
default: alu_src_b = 0;
endcase // case (src_b_sel)
end
endmodule
| 7.757127 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module dmac_src_axi_stream #(
parameter ID_WIDTH = 3,
parameter S_AXIS_DATA_WIDTH = 64,
parameter LENGTH_WIDTH = 24,
parameter BEATS_PER_BURST_WIDTH = 4)(
input s_axis_aclk,
input s_axis_aresetn,
input enable,
output enabled,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
input eot,
output rewind_req_valid,
input rewind_req_ready,
output [ID_WIDTH+3-1:0] rewind_req_data,
output bl_valid,
input bl_ready,
output [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length,
output block_descr_to_dst,
output [ID_WIDTH-1:0] source_id,
output source_eot,
output s_axis_ready,
input s_axis_valid,
input [S_AXIS_DATA_WIDTH-1:0] s_axis_data,
input [0:0] s_axis_user,
input s_axis_last,
output s_axis_xfer_req,
output fifo_valid,
output [S_AXIS_DATA_WIDTH-1:0] fifo_data,
output fifo_last,
output fifo_partial_burst,
input req_valid,
output req_ready,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input req_sync_transfer_start,
input req_xlast
);
assign enabled = enable;
dmac_data_mover # (
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(S_AXIS_DATA_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
.ALLOW_ABORT(1)
) i_data_mover (
.clk(s_axis_aclk),
.resetn(s_axis_aresetn),
.xfer_req(s_axis_xfer_req),
.request_id(request_id),
.response_id(response_id),
.eot(eot),
.rewind_req_valid(rewind_req_valid),
.rewind_req_ready(rewind_req_ready),
.rewind_req_data(rewind_req_data),
.bl_valid(bl_valid),
.bl_ready(bl_ready),
.measured_last_burst_length(measured_last_burst_length),
.block_descr_to_dst(block_descr_to_dst),
.source_id(source_id),
.source_eot(source_eot),
.req_valid(req_valid),
.req_ready(req_ready),
.req_last_burst_length(req_last_burst_length),
.req_sync_transfer_start(req_sync_transfer_start),
.req_xlast(req_xlast),
.s_axi_valid(s_axis_valid),
.s_axi_ready(s_axis_ready),
.s_axi_data(s_axis_data),
.s_axi_last(s_axis_last),
.s_axi_sync(s_axis_user[0]),
.m_axi_valid(fifo_valid),
.m_axi_data(fifo_data),
.m_axi_last(fifo_last),
.m_axi_partial_burst(fifo_partial_burst)
);
endmodule
| 8.180735 |
module src_a_mux (
// from controller
input [31 : 0] pc,
// from regfile
input [31 : 0] rs1_data,
// from decoder
input [31 : 0] imm,
input [`SEL_SRC_A_WIDTH - 1 : 0] select,
// to alu
output reg [31 : 0] alu_src_a
);
always @(*) begin
case (select)
`SEL_SRC_A_PC: alu_src_a = pc;
`SEL_SRC_A_RS1: alu_src_a = rs1_data;
`SEL_SRC_A_IMM: alu_src_a = imm;
default: alu_src_a = 32'b0;
endcase
end // always @(*)
endmodule
| 8.370023 |
module src_b_mux (
// from regfile
input [31 : 0] rs2_data,
// from decoder
input [31 : 0] imm,
input [`SEL_SRC_B_WIDTH - 1 : 0] select,
// to alu
output reg [31 : 0] alu_src_b
);
always @(*) begin
case (select)
`SEL_SRC_B_RS2: alu_src_b = rs2_data;
`SEL_SRC_B_IMM: alu_src_b = imm;
`SEL_SRC_B_0: alu_src_b = 32'h0;
`SEL_SRC_B_4: alu_src_b = 32'h4;
default: alu_src_b = 32'b0;
endcase
end // always @(*)
endmodule
| 7.757127 |
module src_domain #(
parameter DATAWIDTH = 8
) (
input CLK,
input RSTn,
input [DATAWIDTH - 1 : 0] src_data_in,
output reg [DATAWIDTH - 1 : 0] src2dest_data,
output reg src2dest_load,
output reg src_data_valid
);
reg [DATAWIDTH - 1 : 0] src_data_in_reg;
always @(posedge CLK or negedge RSTn) begin
if (!RSTn) begin
// reset
src2dest_data <= 0;
src2dest_load <= 0;
src_data_in_reg <= 0;
end else begin
src2dest_load <= src2dest_load ^ src_data_valid;
src_data_in_reg <= src_data_in;
end
if (src_data_valid) begin
src2dest_data <= src_data_in;
end
end
/**********src_data_in changed signal**********/
always @(posedge CLK or negedge RSTn) begin
if (!RSTn) begin
// reset
src_data_valid <= 0;
end else if (src_data_in != src_data_in_reg) begin
src_data_valid <= 1;
end else src_data_valid <= 0;
end
endmodule
| 8.092851 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module dmac_src_fifo_inf #(
parameter ID_WIDTH = 3,
parameter DATA_WIDTH = 64,
parameter BEATS_PER_BURST_WIDTH = 4)(
input clk,
input resetn,
input enable,
output enabled,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
input eot,
output bl_valid,
input bl_ready,
output [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length,
input en,
input [DATA_WIDTH-1:0] din,
output reg overflow,
input sync,
output xfer_req,
output fifo_valid,
output [DATA_WIDTH-1:0] fifo_data,
output fifo_last,
input req_valid,
output req_ready,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input req_sync_transfer_start
);
wire ready;
wire valid;
assign enabled = enable;
assign valid = en & ready;
always @(posedge clk)
begin
if (enable) begin
overflow <= en & ~ready;
end else begin
overflow <= en;
end
end
dmac_data_mover # (
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
) i_data_mover (
.clk(clk),
.resetn(resetn),
.xfer_req(xfer_req),
.request_id(request_id),
.response_id(response_id),
.eot(eot),
.bl_valid(bl_valid),
.bl_ready(bl_ready),
.measured_last_burst_length(measured_last_burst_length),
.req_valid(req_valid),
.req_ready(req_ready),
.req_last_burst_length(req_last_burst_length),
.req_sync_transfer_start(req_sync_transfer_start),
.req_xlast(1'b0),
.s_axi_ready(ready),
.s_axi_valid(valid),
.s_axi_data(din),
.s_axi_sync(sync),
.s_axi_last(1'b0),
.m_axi_valid(fifo_valid),
.m_axi_data(fifo_data),
.m_axi_last(fifo_last)
);
endmodule
| 8.180735 |
module SRC_imm_MUX (
instr,
src1sel,
l_sw,
en,
imm_src1
); //selet immdiate value if lw/sw/jal encoutered
input [7:0] instr;
input src1sel, l_sw;
output en;
output [15:0] imm_src1;
wire [15:0] s1, s2;
assign en = (src1sel || l_sw);
assign s1 = {{8{instr[7]}}, instr[7:0]};
assign s2 = {{12{instr[3]}}, instr[3:0]};
assign imm_src1 = (src1sel) ? s1 : (l_sw) ? s2 : 16'h0;
endmodule
| 6.515118 |
module src_manager (
input wire [`DATA_LEN-1:0] opr,
input wire opr_rdy,
input wire [`DATA_LEN-1:0] exrslt1,
input wire [ `RRF_SEL-1:0] exdst1,
input wire kill_spec1,
input wire [`DATA_LEN-1:0] exrslt2,
input wire [ `RRF_SEL-1:0] exdst2,
input wire kill_spec2,
input wire [`DATA_LEN-1:0] exrslt3,
input wire [ `RRF_SEL-1:0] exdst3,
input wire kill_spec3,
input wire [`DATA_LEN-1:0] exrslt4,
input wire [ `RRF_SEL-1:0] exdst4,
input wire kill_spec4,
input wire [`DATA_LEN-1:0] exrslt5,
input wire [ `RRF_SEL-1:0] exdst5,
input wire kill_spec5,
output wire [`DATA_LEN-1:0] src,
output wire resolved
);
assign src = opr_rdy ? opr :
~kill_spec1 & (exdst1 == opr) ? exrslt1 :
~kill_spec2 & (exdst2 == opr) ? exrslt2 :
~kill_spec3 & (exdst3 == opr) ? exrslt3 :
~kill_spec4 & (exdst4 == opr) ? exrslt4 :
~kill_spec5 & (exdst5 == opr) ? exrslt5 : opr;
assign resolved = opr_rdy |
(~kill_spec1 & (exdst1 == opr)) |
(~kill_spec2 & (exdst2 == opr)) |
(~kill_spec3 & (exdst3 == opr)) |
(~kill_spec4 & (exdst4 == opr)) |
(~kill_spec5 & (exdst5 == opr));
endmodule
| 6.961538 |
module src_min (
input clk,
input rst_n,
//ǰ
input pre_frame_vsync,
input pre_frame_href,
input pre_frame_clken,
input [ 23:0] pre_img,
//
output post_frame_vsync,
output post_frame_href,
output post_frame_clken,
output [7 : 0] post_img
);
reg pre_frame_vsync_d1;
reg pre_frame_href_d1;
reg pre_frame_clken_d1;
reg [7 : 0] pixel_min_of_rgb;
wire [7 : 0] pixel_of_r;
wire [7 : 0] pixel_of_g;
wire [7 : 0] pixel_of_b;
wire [7 : 0] pixel_min_of_rgb_1st;
wire [7 : 0] pixel_min_of_rgb_2st;
assign pixel_of_r = pre_img[23 : 16];
assign pixel_of_g = pre_img[15 : 8];
assign pixel_of_b = pre_img[7 : 0];
assign pixel_min_of_rgb_1st = pixel_of_r > pixel_of_g ? pixel_of_g : pixel_of_r;
assign pixel_min_of_rgb_2st = pixel_of_b > pixel_min_of_rgb_1st ? pixel_min_of_rgb_1st : pixel_of_b;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
pixel_min_of_rgb <= 0;
end else if (pre_frame_href & pre_frame_clken) begin
pixel_min_of_rgb <= pixel_min_of_rgb_2st;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
pre_frame_vsync_d1 <= 0;
pre_frame_href_d1 <= 0;
pre_frame_clken_d1 <= 0;
end else begin
pre_frame_vsync_d1 <= pre_frame_vsync;
pre_frame_href_d1 <= pre_frame_href;
pre_frame_clken_d1 <= pre_frame_clken;
end
end
assign post_frame_vsync = pre_frame_vsync_d1;
assign post_frame_href = pre_frame_href_d1;
assign post_frame_clken = pre_frame_clken_d1;
assign post_img = pixel_min_of_rgb;
endmodule
| 7.003508 |
module src_mux (
clk,
stall_ID_EX,
stall_EX_DM,
src0sel_ID_EX,
src1sel_ID_EX,
p0,
p1,
imm_ID_EX,
pc_ID_EX,
p0_EX_DM,
src0,
src1,
dst_EX_DM,
dst_DM_WB,
byp0_EX,
byp0_DM,
byp1_EX,
byp1_DM
);
input clk;
input stall_ID_EX, stall_EX_DM; // stall signal
input [1:0] src0sel_ID_EX, src1sel_ID_EX; // mux selectors for src0 and src1 busses
input [15:0] p0; // port 0 from register file
input [15:0] p1; // port 1 from register file
input [15:0] pc_ID_EX; // Next PC for JAL instruction
input [11:0] imm_ID_EX; // immediate from instruction stream goes on src0
input [15:0] dst_EX_DM; // EX_DM results for bypassing RF reads
input [15:0] dst_DM_WB; // DM_WB results for bypassing RF reads
input byp0_EX, byp1_EX; // From ID, selects EX results to bypass RF sources
input byp0_DM, byp1_DM; // From ID, selects DM results to bypass RF sources
output reg [15:0] p0_EX_DM; // need to output this as data for SW instructions
output [15:0] src0, src1; // source busses
/////////////////////////////////
// registers needed for flops //
///////////////////////////////
reg [15:0] p0_ID_EX, p1_ID_EX; // need to flop register file outputs to form _ID_EX versions
wire [15:0] RF_p0, RF_p1; // output of bypass muxes for RF sources
/////////////////////
// include params //
///////////////////
`include "common_params.inc"
/////////////////////////////////////////////////
// Flop the read ports from the register file //
///////////////////////////////////////////////
always @(posedge clk)
if (!stall_ID_EX) begin
p0_ID_EX <= p0;
p1_ID_EX <= p1;
end
/////////////////////////////
// Bypass Muxes for port0 //
///////////////////////////
assign RF_p0 = (byp0_EX) ? dst_EX_DM : // EX gets priority because it represents more recent data
(byp0_DM) ? dst_DM_WB : p0_ID_EX;
/////////////////////////////
// Bypass Muxes for port1 //
///////////////////////////
assign RF_p1 = (byp1_EX) ? dst_EX_DM : // EX gets priority because it represents more recent data
(byp1_DM) ? dst_DM_WB : p1_ID_EX;
////////////////////////////////////////////////////
// Need to pipeline the data to be stored for SW //
//////////////////////////////////////////////////
always @(posedge clk) if (!stall_EX_DM) p0_EX_DM <= RF_p0;
assign src0 = (src0sel_ID_EX == RF2SRC0) ? RF_p0 :
(src0sel_ID_EX == IMM_BR2SRC0) ? {{7{imm_ID_EX[8]}},imm_ID_EX[8:0]} : // branch immediates
(src0sel_ID_EX == IMM_JMP2SRC0) ? {{4{imm_ID_EX[11]}}, imm_ID_EX[11:0]} : // JMP immediates
{{12{imm_ID_EX[3]}}, imm_ID_EX[3:0]}; // for address immediates for DM operations
assign src1 = (src1sel_ID_EX == RF2SRC1) ? RF_p1 :
(src1sel_ID_EX == NPC2SRC1) ? pc_ID_EX : // for JAL
{{8{imm_ID_EX[7]}}, imm_ID_EX[7:0]}; // for LHB/LLB (sign extended 8-bit immediate
endmodule
| 7.908347 |
module src_shift_reg (
source1_data,
source2_data,
source3_data,
source_vcc_value,
source_exec_value,
src_buffer_wr_en,
src_buffer_shift_en,
alu_source1_data,
alu_source2_data,
alu_source3_data,
alu_source_vcc_value,
alu_source_exec_value,
clk,
rst
);
input [2047:0] source1_data;
input [2047:0] source2_data;
input [2047:0] source3_data;
input [63:0] source_vcc_value;
input [63:0] source_exec_value;
input src_buffer_wr_en;
input src_buffer_shift_en;
output [511:0] alu_source1_data;
output [511:0] alu_source2_data;
output [511:0] alu_source3_data;
output [15:0] alu_source_vcc_value;
output [15:0] alu_source_exec_value;
input clk;
input rst;
shift_in #(32) src1_shift (
.data_in(source1_data),
.wr_en(src_buffer_wr_en),
.shift_en(src_buffer_shift_en),
.data_out(alu_source1_data),
.clk(clk),
.rst(rst)
);
shift_in #(32) src2_shift (
.data_in(source2_data),
.wr_en(src_buffer_wr_en),
.shift_en(src_buffer_shift_en),
.data_out(alu_source2_data),
.clk(clk),
.rst(rst)
);
shift_in #(32) src3_shift (
.data_in(source3_data),
.wr_en(src_buffer_wr_en),
.shift_en(src_buffer_shift_en),
.data_out(alu_source3_data),
.clk(clk),
.rst(rst)
);
shift_in #(1) exec_shift (
.data_in(source_exec_value),
.wr_en(src_buffer_wr_en),
.shift_en(src_buffer_shift_en),
.data_out(alu_source_exec_value),
.clk(clk),
.rst(rst)
);
shift_in #(1) vcc_shift (
.data_in(source_vcc_value),
.wr_en(src_buffer_wr_en),
.shift_en(src_buffer_shift_en),
.data_out(alu_source_vcc_value),
.clk(clk),
.rst(rst)
);
endmodule
| 7.950969 |
module sReg (
output reg [15:0] DataOut,
input [2:0] Addr,
input Clk1,
input Clk2,
input [15:0] DataIn,
input RD,
input WR,
input WR_l,
input WR_h
);
reg [15:0] scalar [7:0];
reg [ 2:0] address;
wire [ 3:0] cmd;
parameter read = 4'b1000, write = 4'b0100, wr_low = 4'b0010, wr_high = 4'b0001;
assign cmd = {RD, WR, WR_l, WR_h};
always @(posedge Clk1) begin
case (cmd)
read: begin
DataOut <= scalar[address];
scalar[address] <= scalar[address];
end
write: begin
scalar[address] <= DataIn;
DataOut <= DataOut;
end
wr_low: begin
scalar[address] <= {scalar[address][15:8], DataIn[7:0]};
DataOut <= DataOut;
end
wr_high: begin
scalar[address] <= {DataIn[15:8], scalar[address][7:0]};
DataOut <= DataOut;
end
default: begin
scalar[address] <= scalar[address];
DataOut <= DataOut;
end
endcase
end
always @(posedge Clk2) begin
address <= Addr;
end
endmodule
| 7.974086 |
module sreg8 (
output reg [7:0] Q,
input ShiftIn,
input Enable,
input Clock,
input nReset
);
reg [7:0] Qr;
// Calculo asncrono de registro auxiliar Qr
always @(Q, ShiftIn, Enable) begin
Qr = Q;
if (Enable == 1) Qr = {ShiftIn, Q[7:1]};
end
// Reset y asignacin de Qr con clock
always @(posedge Clock, negedge nReset) begin
if (nReset == 0) #2 Q = 0;
else #2 Q = Qr;
end
endmodule
| 6.950812 |
module sreg_10 (
clk,
load,
data,
en,
q
);
input clk;
input load;
input [9:0] data;
input en;
output q;
// IO regs
reg [9:0] sreg;
always @(posedge clk) begin
if (load) sreg <= data;
else if (en) sreg <= {sreg[8:0], 1'b0};
end
assign q = sreg[9];
endmodule
| 6.903676 |
module sreg_block (
// configuration
input [12:0] addr_base,
// The FPGA internal I/O bus
input clk,
input [12:0] iADDR, // I/O address
input iBS7, // address is on the I/O page
output iREAD_MATCH, // this device will read that address
output iWRITE_MATCH, // this device will write that address
input [15:0] iWDATA,
input iWRITE,
output [15:0] iRDATA
);
parameter count = 2; // how many registers in the block (at least 2)
localparam cbits = $clog2(count);
wire [cbits-1:0] reg_index = iADDR[cbits:1];
wire match;
reg [ 15:0] reg_data [0:count-1]; // the actual registers
// figure out if we're being addressed
assign match = (iBS7 && !iADDR[0] && // address is on the I/O page and is not odd
(iADDR[12:cbits+1] == addr_base[12:cbits+1])); // and matches the high bits
// this decouples match from iREAD_MATCH and iWRITE_MATCH so they don't feed back in even
// though they're declared as outputs
assign iREAD_MATCH = match ? 1 : 0;
assign iWRITE_MATCH = match ? 1 : 0;
// if we match the address, then place the register data on iRDATA just in case it needs to
// be read
assign iRDATA = match ? reg_data[reg_index] : 16'bZ;
// write data to register
always @(posedge clk) if (iWRITE && match) reg_data[reg_index] <= iWDATA;
`ifdef SIM
// initialize the registers' contents for testing purposes
integer i;
initial begin
for (i = 0; i < count; i = i + 1) reg_data[i] = 'o123456;
end
`endif
endmodule
| 7.500528 |
module sreg_file (
clk,
r_addr,
data_out
);
parameter addr_w = 4, data_w = 8;
input clk;
input [addr_w-1:0] r_addr;
output reg [data_w-1:0] data_out;
reg [data_w-1:0] sregfile[2**addr_w-1:0];
initial begin
$readmemb("sreg_file_init.txt", sregfile);
end
always @(posedge clk) begin
data_out <= sregfile[r_addr];
end
endmodule
| 7.304686 |
module test_jbimu;
// Inputs
reg clks;
reg clock;
reg reset;
reg start;
wire miso;
// Outputs
wire [15:0] roll;
wire [15:0] pitch;
wire [15:0] yaw;
wire [15:0] roll_rate;
wire [15:0] pitch_rate;
wire [15:0] yaw_rate;
wire [15:0] accel_x;
wire [15:0] accel_y;
wire [15:0] accel_z;
wire done;
wire mosi;
wire sck;
wire ss;
// Instantiate the Unit Under Test (UUT)
jb_imu uut (
.clock(clock),
.reset(reset),
.start(start),
.roll(roll),
.pitch(pitch),
.yaw(yaw),
.roll_rate(roll_rate),
.pitch_rate(pitch_rate),
.yaw_rate(yaw_rate),
.accel_x(accel_x),
.accel_y(accel_y),
.accel_z(accel_z),
90
.done(done),
.miso(miso),
.mosi(mosi),
.sck(sck),
.ss(ss)
);
wire slave_done;
reg [7:0] din;
wire [7:0] slave_dout;
spi_slave slave(
.clk(clks),
.rst(reset),
.ss(ss),
.mosi(mosi),
.miso(miso),
.sck(sck),
.done(slave_done),
.din(din),
.dout(slave_dout)
);
always #10 clock = ~clock; //50Mhz = 20 ns period
always #20 clks = ~clks; //25 Mhz slave clock
always @(slave_done) begin
if(slave_done) begin
din = din + 1'b1;
end
end
initial begin
// Initialize Inputs
clock = 0;
clks=0;
reset = 0;
start = 0;
din = 0;
// Wait 100 ns for global reset to finish
reset = 1;
#100;
reset = 0;
// Add stimulus here
din = 8'h00;
#20;
91
start = 1;
#20;
start = 0;
#10000;
end
endmodule
| 6.632599 |
modules
#-- Copyright (c) 1995-2008 by Xilinx, Inc. All rights reserved.
#-- This text/file contains proprietary, confidential
#-- information of Xilinx, Inc., is distributed under license
#-- from Xilinx, Inc., and may be used, copied and/or
#-- disclosed only pursuant to the terms of a valid license
#-- agreement with Xilinx, Inc. Xilinx hereby grants you a
#-- license to use this text/file solely for design, simulation,
#-- implementation and creation of design files limited
#-- to Xilinx devices or technologies. Use with non-Xilinx
#-- devices or technologies is expressly prohibited and
#-- immediately terminates your license unless covered by
#-- a separate agreement.
#--
#-- Xilinx is providing this design, code, or information
#-- "as-is" solely for use in developing programs and
#-- solutions for Xilinx devices, with no obligation on the
#-- part of Xilinx to provide support. By providing this design,
#-- code, or information as one possible implementation of
#-- this feature, application or standard, Xilinx is making no
#-- representation that this implementation is free from any
#-- claims of infringement. You are responsible for
#-- obtaining any rights you may require for your implementation.
#-- Xilinx expressly disclaims any warranty whatsoever with
#-- respect to the adequacy of the implementation, including
#-- but not limited to any warranties or representations that this
#-- implementation is free from claims of infringement, implied
#-- warranties of merchantability or fitness for a particular
#-- purpose.
#--
#-- Xilinx products are not intended for use in life support
#-- appliances, devices, or systems. Use in such applications is
#-- expressly prohibited.
#--
#-- Any modifications that are made to the Source Code are
#-- done at the user's sole risk and will be unsupported.
#--
#-- This copyright and support notice must be retained as part
#-- of this text at all times. (c) Copyright 1995-2008 Xilinx, Inc.
#-- All rights reserved.
*******************************************************************************/
//-------------------------------------------------------------------
//
// ILA core module declaration
//
//-------------------------------------------------------------------
module phy_ila // synthesis syn_black_box .noprune = 1
(
control,
clk,
data,
trig0
);
input [35:0] control;
input clk;
input [255:0] data;
input [31:0] trig0;
endmodule
| 7.855861 |
module srl #(
parameter WIDTH = 18
) (
input clk,
input write,
input [WIDTH-1:0] in,
input [3:0] addr,
output [WIDTH-1:0] out
);
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : gen_srl
SRL16E srl16e (
.Q (out[i]),
.A0 (addr[0]),
.A1 (addr[1]),
.A2 (addr[2]),
.A3 (addr[3]),
.CE (write),
.CLK(clk),
.D (in[i])
);
end
endgenerate
endmodule
| 7.644441 |
module SRL1 (
input [1:0] in
, output out
);
parameter NUM_GATES = 2;
wire [NUM_GATES - 1:0] LW;
wire [NUM_GATES - 1:0] w;
genvar i;
generate
for (i = 0; i < NUM_GATES; i++) begin : L
LCELL lcell_inst (
.in (LW[i])
, .out(w[i])
);
end
endgenerate
nor (LW[0], in[0], w[1]);
nor (LW[1], in[1], w[0]);
assign out = w[1];
endmodule
| 6.697605 |
module srl16e_bbl (
clock,
ce,
adr,
d,
q
);
// Generic
parameter WIDTH = 19;
initial $display("srl16e_bbl: WIDTH=%d", WIDTH);
// Ports
input clock;
input ce;
input [3:0] adr;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
// Generate MXSRL instances of SRL16E
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : srlgen
SRL16E u00 (
.CLK(clock),
.CE (ce),
.D (d[i]),
.A0 (adr[0]),
.A1 (adr[1]),
.A2 (adr[2]),
.A3 (adr[3]),
.Q (q[i])
);
end
endgenerate
//-----------------------------------------------------------------------------------------------------------------------
endmodule
| 7.422285 |
module srl16e_bit (
clock,
adr,
d,
q
);
//-------------------------------------------------------------------------------------------------------------------
// Generics caller may override
//-------------------------------------------------------------------------------------------------------------------
parameter ADR_WIDTH = 8; // Addess width
parameter SRL_DEPTH = 256; // Shift register stages may be less than 2**ADR_WIDTH
initial $display("srl16e_bit: ADR_WIDTH=%d", ADR_WIDTH);
initial $display("srl16e_bit: SRL_DEPTH=%d", SRL_DEPTH);
//-------------------------------------------------------------------------------------------------------------------
// Ports
//-------------------------------------------------------------------------------------------------------------------
input clock;
input [ADR_WIDTH-1:0] adr;
input d;
output q;
// Shift d left by adr places
reg [SRL_DEPTH-1:0] srl = 0;
always @(posedge clock) begin
srl <= {srl[SRL_DEPTH-2:0], d};
end
assign q = srl[adr];
//-----------------------------------------------------------------------------------------------------------------------
endmodule
| 7.708922 |
module srl16e_fifo #(
parameter c_width = 8,
c_awidth = 4,
c_depth = 16
) (
input Clk, // Main System Clock (Sync FIFO)
input Rst, // FIFO Counter Reset (Clk
input WR_EN, // FIFO Write Enable (Clk)
input RD_EN, // FIFO Read Enable (Clk)
input [c_width-1:0] DIN, // FIFO Data Input (Clk)
output [c_width-1:0] DOUT, // FIFO Data Output (Clk)
output FULL, // FIFO FULL Status (Clk)
output EMPTY // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [c_awidth-1:0] c_empty = ~(0);
localparam [c_awidth-1:0] c_full = c_empty - 1;
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [c_width-1:0] memory[c_depth-1:0];
reg [c_awidth-1:0] cnt_read;
///////////////////////////////////////
// Main SRL16E FIFO Array
///////////////////////////////////////
always @(posedge Clk) begin : blkSRL
integer i;
if (WR_EN) begin
for (i = 0; i < c_depth - 1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= DIN;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge Clk) begin
if (Rst) cnt_read <= c_empty;
else if (WR_EN & !RD_EN) cnt_read <= cnt_read + 1'b1;
else if (!WR_EN & RD_EN) cnt_read <= cnt_read - 1'b1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign FULL = (cnt_read == c_full);
assign EMPTY = (cnt_read == c_empty);
assign DOUT = (c_depth == 1) ? memory[0] : memory[cnt_read];
endmodule
| 7.171691 |
module srl16e_fifo_protect #(
parameter c_width = 8,
c_awidth = 4,
c_depth = 16
) (
input Clk, // Main System Clock (Sync FIFO)
input Rst, // FIFO Counter Reset (Clk
input WR_EN, // FIFO Write Enable (Clk)
input RD_EN, // FIFO Read Enable (Clk)
input [c_width-1:0] DIN, // FIFO Data Input (Clk)
output [c_width-1:0] DOUT, // FIFO Data Output (Clk)
output ALMOST_FULL,
output FULL, // FIFO FULL Status (Clk)
output ALMOST_EMPTY,
output EMPTY // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [c_awidth-1:0] c_empty = ~(0);
localparam [c_awidth-1:0] c_empty_pre = (0);
localparam [c_awidth-1:0] c_empty_pre1 = (1);
localparam [c_awidth-1:0] c_full = c_empty - 1;
localparam [c_awidth-1:0] c_full_pre = c_full - 1;
localparam [c_awidth-1:0] c_full_pre1 = c_full - 2;
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [c_width-1:0] memory[c_depth-1:0];
reg [c_awidth-1:0] cnt_read;
///////////////////////////////////////
// Main SRL16E FIFO Array
///////////////////////////////////////
always @(posedge Clk) begin : blkSRL
integer i;
if (WR_EN) begin
for (i = 0; i < c_depth - 1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= DIN;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
///////////////////////////////////////
always @(posedge Clk) begin
if (Rst) cnt_read <= c_empty;
else if (WR_EN & !RD_EN & !FULL) cnt_read <= cnt_read + 1;
else if (!WR_EN & RD_EN & !EMPTY) cnt_read <= cnt_read - 1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign FULL = (cnt_read == c_full);
assign EMPTY = (cnt_read == c_empty);
assign ALMOST_FULL = (cnt_read == c_full_pre || c_full_pre1 == cnt_read);
assign ALMOST_EMPTY = (cnt_read == c_empty_pre || c_empty_pre1 == cnt_read);
assign DOUT = (c_depth == 1) ? memory[0] : memory[cnt_read];
endmodule
| 7.156099 |
module srl2_32 (
in,
out
);
input signed [31:0] in;
output signed [31:0] out;
assign out = in >>> 1;
endmodule
| 7.611714 |
module srl32 (
input [31:0] A,
input [31:0] B,
output [31:0] res
);
assign res = A >> B[10:6];
endmodule
| 7.07749 |
module SRL32E #(
parameter [31:0] INIT = 32'h0,
parameter [0:0] IS_CLK_INVERTED = 1'b0
) (
// Clock
input wire CLK,
// Clock enable
input wire CE,
// Bit output position
input wire [4:0] A,
// Data in
input wire D,
// Data out
output wire Q
);
// 32-bit shift register
reg [31:0] _r_srl;
// Power-up value
initial begin
_r_srl = INIT;
end
// Shifter logic
generate
if (IS_CLK_INVERTED) begin : GEN_CLK_NEG
always @(negedge CLK) begin : SHIFTER_32B
if (CE) begin
_r_srl <= {_r_srl[30:0], D};
end
end
end else begin : GEN_CLK_POS
always @(posedge CLK) begin : SHIFTER_32B
if (CE) begin
_r_srl <= {_r_srl[30:0], D};
end
end
end
endgenerate
// Data out
assign Q = _r_srl[A];
endmodule
| 7.202101 |
module srl32x4e (
y,
d,
a,
ce,
clk
);
output [3:0] y; // output selected by address
input [3:0] d; // input word
input [4:0] a; // address of output word
input ce; // enable input
input clk; // clock input
// 4 32-bit shift registers
SRLC32E sr0 (
.D (d[0]),
.A (a),
.CLK(clk),
.CE (ce),
.Q (y[0]),
.Q31()
);
SRLC32E sr1 (
.D (d[1]),
.A (a),
.CLK(clk),
.CE (ce),
.Q (y[1]),
.Q31()
);
SRLC32E sr2 (
.D (d[2]),
.A (a),
.CLK(clk),
.CE (ce),
.Q (y[2]),
.Q31()
);
SRLC32E sr3 (
.D (d[3]),
.A (a),
.CLK(clk),
.CE (ce),
.Q (y[3]),
.Q31()
);
endmodule
| 6.802363 |
module SRL64E (
Q,
D,
A,
CE,
CLK
);
output Q;
input D;
input [5:0] A;
input CE;
input CLK;
// 2 shift registers and 1 multiplexer
wire q31; // inter-SRLC32E bit
wire qa, qb; // SRLC32E outputs
SRLC32E sr0 (
.D (D),
.A (A[4:0]),
.Q (qa),
.Q31(q31),
.CE (CE),
.CLK(CLK)
);
SRLC32E sr1 (
.D (q31),
.A (A[4:0]),
.Q (qb),
.Q31(),
.CE (CE),
.CLK(CLK)
);
MUXF7 mux (
.I0(qa),
.I1(qb),
.S (A[5]),
.O (Q)
);
endmodule
| 7.055696 |
module Srlatch (
input wire S,
R,
output wire Q,
Q_not
);
assign Q = ~(R | Q_not);
assign Q_not = ~(S | Q);
endmodule
| 7.860565 |
module SRlatchnand (
input S,
R,
CLK,
output Q
);
wire i, k, y;
assign #(7) i = (S | ~CLK);
assign #(7) k = (R | ~CLK);
assign #(7) Q = ~(i & y);
assign #(7) y = ~(Q & k);
endmodule
| 6.603362 |
module SRLC16 (
Q,
Q15,
A0,
A1,
A2,
A3,
CLK,
D
);
parameter INIT = 16'h0000;
output Q, Q15;
input A0, A1, A2, A3, CLK, D;
reg [15:0] data;
wire [3:0] addr;
wire q_int;
wire q15_int;
buf b_a3 (addr[3], A3);
buf b_a2 (addr[2], A2);
buf b_a1 (addr[1], A1);
buf b_a0 (addr[0], A0);
buf b_q_int (q_int, data[addr]);
buf b_q (Q, q_int);
buf b_q15_int (q15_int, data[15]);
buf b_q15 (Q15, q15_int);
initial begin
assign data = INIT;
while (CLK === 1'b1 || CLK === 1'bX) #10;
deassign data;
end
always @(posedge CLK) begin
{data[15:0]} <= #100{data[14:0], D};
end
endmodule
| 6.770168 |
module SRLC16E (
Q,
Q15,
A0,
A1,
A2,
A3,
CE,
CLK,
D
);
parameter INIT = 16'h0000;
output Q, Q15;
input A0, A1, A2, A3, CE, CLK, D;
reg [15:0] data;
wire [3:0] addr;
wire q_int;
wire q15_int;
buf b_a3 (addr[3], A3);
buf b_a2 (addr[2], A2);
buf b_a1 (addr[1], A1);
buf b_a0 (addr[0], A0);
buf b_q_int (q_int, data[addr]);
buf b_q (Q, q_int);
buf b_q15_int (q15_int, data[15]);
buf b_q15 (Q15, q15_int);
initial begin
assign data = INIT;
while (CLK === 1'b1 || CLK === 1'bX) #10;
deassign data;
end
always @(posedge CLK) begin
if (CE == 1'b1) begin
{data[15:0]} <= #100{data[14:0], D};
end
end
endmodule
| 6.802804 |
module SRLC16E_1 (
Q,
Q15,
A0,
A1,
A2,
A3,
CE,
CLK,
D
);
parameter INIT = 16'h0000;
output Q, Q15;
input A0, A1, A2, A3, CE, CLK, D;
reg [15:0] data;
wire [3:0] addr;
wire clk_;
wire q_int;
wire q15_int;
buf b_a3 (addr[3], A3);
buf b_a2 (addr[2], A2);
buf b_a1 (addr[1], A1);
buf b_a0 (addr[0], A0);
buf b_q_int (q_int, data[addr]);
buf b_q (Q, q_int);
buf b_q15_int (q15_int, data[15]);
buf b_q15 (Q15, q15_int);
not i_c (clk_, CLK);
initial begin
assign data = INIT;
while (clk_ === 1'b1 || clk_ === 1'bX) #10;
deassign data;
end
always @(posedge clk_) begin
if (CE == 1'b1) begin
{data[15:0]} <= #100{data[14:0], D};
end
end
endmodule
| 6.554028 |
module SRLC16_1 (
Q,
Q15,
A0,
A1,
A2,
A3,
CLK,
D
);
parameter INIT = 16'h0000;
output Q, Q15;
input A0, A1, A2, A3, CLK, D;
reg [15:0] data;
wire [3:0] addr;
wire clk_;
wire q_int;
wire q15_int;
buf b_a3 (addr[3], A3);
buf b_a2 (addr[2], A2);
buf b_a1 (addr[1], A1);
buf b_a0 (addr[0], A0);
buf b_q_int (q_int, data[addr]);
buf b_q (Q, q_int);
buf b_q15_int (q15_int, data[15]);
buf b_q15 (Q15, q15_int);
not i_c (clk_, CLK);
initial begin
assign data = INIT;
while (clk_ === 1'b1 || clk_ === 1'bX) #10;
deassign data;
end
always @(posedge clk_) begin
{data[15:0]} <= #100{data[14:0], D};
end
endmodule
| 6.699982 |
module SRLC32E (
Q,
Q31,
A,
CE,
CLK,
D
);
parameter INIT = 32'h00000000;
output Q;
output Q31;
input [4:0] A;
input CE, CLK, D;
reg [31:0] data;
assign Q = data[A];
assign Q31 = data[31];
initial begin
assign data = INIT;
while (CLK === 1'b1 || CLK === 1'bX) #10;
deassign data;
end
always @(posedge CLK) if (CE == 1'b1) data <= #100{data[30:0], D};
endmodule
| 7.008473 |
module SRLNXE #(
WIDTH = 32,
DEPTH = 128
) (
input wire clk,
input wire [$clog2(DEPTH)-1:0] addr,
input wire wen,
input wire [WIDTH-1:0] data_i,
output wire [WIDTH-1:0] data_o
);
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : gen_srlnxE
SRLXE #(
.DEPTH(DEPTH)
) srlxe (
.clk(clk),
.addr(addr),
.wen(wen),
.data_i(data_i[i]),
.data_o(data_o[i])
);
end
endgenerate
endmodule
| 7.971678 |
module SRLXE #(
DEPTH = 128
) (
input wire clk,
input wire [$clog2(DEPTH)-1:0] addr,
input wire wen,
input wire data_i,
output wire data_o
);
reg [DEPTH-1:0] mem;
// Data is latched on the positive edge of the clock
always @(posedge clk) if (wen) mem[DEPTH-1:0] <= {mem[DEPTH-2:0], data_i};
assign data_o = mem[addr];
endmodule
| 6.926966 |
module srl_cam_32x32 (
clk,
cmp_data_mask,
cmp_din,
data_mask,
din,
we,
wr_addr,
busy,
match,
match_addr
);
input clk;
input [31 : 0] cmp_data_mask;
input [31 : 0] cmp_din;
input [31 : 0] data_mask;
input [31 : 0] din;
input we;
input [4 : 0] wr_addr;
output busy;
output match;
output [4 : 0] match_addr;
// synthesis translate_off
CAM_V5_1 #(
.c_addr_type(0),
.c_cmp_data_mask_width(32),
.c_cmp_din_width(32),
.c_data_mask_width(32),
.c_depth(32),
.c_din_width(32),
.c_enable_rlocs(0),
.c_has_cmp_data_mask(1),
.c_has_cmp_din(1),
.c_has_data_mask(1),
.c_has_en(0),
.c_has_multiple_match(0),
.c_has_read_warning(0),
.c_has_single_match(0),
.c_has_we(1),
.c_has_wr_addr(1),
.c_match_addr_width(5),
.c_match_resolution_type(0),
.c_mem_init(0),
.c_mem_init_file("srl_cam_32x32.mif"),
.c_mem_type(0),
.c_read_cycles(1),
.c_reg_outputs(0),
.c_ternary_mode(1),
.c_width(32),
.c_wr_addr_width(5)
) inst (
.CLK(clk),
.CMP_DATA_MASK(cmp_data_mask),
.CMP_DIN(cmp_din),
.DATA_MASK(data_mask),
.DIN(din),
.WE(we),
.WR_ADDR(wr_addr),
.BUSY(busy),
.MATCH(match),
.MATCH_ADDR(match_addr),
.EN(),
.MULTIPLE_MATCH(),
.READ_WARNING(),
.SINGLE_MATCH()
);
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of srl_cam_32x32 is "black_box"
endmodule
| 7.031469 |
module srl_cam_64x32 (
clk,
cmp_data_mask,
cmp_din,
data_mask,
din,
we,
wr_addr,
busy,
match,
match_addr
);
input clk;
input [31 : 0] cmp_data_mask;
input [31 : 0] cmp_din;
input [31 : 0] data_mask;
input [31 : 0] din;
input we;
input [5 : 0] wr_addr;
output busy;
output match;
output [5 : 0] match_addr;
// synthesis translate_off
CAM_V5_1 #(
.c_addr_type(0),
.c_cmp_data_mask_width(32),
.c_cmp_din_width(32),
.c_data_mask_width(32),
.c_depth(64),
.c_din_width(32),
.c_enable_rlocs(0),
.c_has_cmp_data_mask(1),
.c_has_cmp_din(1),
.c_has_data_mask(1),
.c_has_en(0),
.c_has_multiple_match(0),
.c_has_read_warning(0),
.c_has_single_match(0),
.c_has_we(1),
.c_has_wr_addr(1),
.c_match_addr_width(6),
.c_match_resolution_type(0),
.c_mem_init(0),
.c_mem_init_file("srl_cam_64x32.mif"),
.c_mem_type(0),
.c_read_cycles(1),
.c_reg_outputs(0),
.c_ternary_mode(1),
.c_width(32),
.c_wr_addr_width(6)
) inst (
.CLK(clk),
.CMP_DATA_MASK(cmp_data_mask),
.CMP_DIN(cmp_din),
.DATA_MASK(data_mask),
.DIN(din),
.WE(we),
.WR_ADDR(wr_addr),
.BUSY(busy),
.MATCH(match),
.MATCH_ADDR(match_addr),
.EN(),
.MULTIPLE_MATCH(),
.READ_WARNING(),
.SINGLE_MATCH()
);
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of srl_cam_64x32 is "black_box"
endmodule
| 7.594453 |
module srl_fifo #(
parameter WIDTH = 1,
parameter DEPTH_LOG = 3,
parameter FALLTHROUGH = "true"
) (
input clock,
input reset,
input push,
input [WIDTH-1:0] din,
output full,
input pop,
output reg [WIDTH-1:0] dout,
output empty
);
//check parameter sanity
initial begin
if ((FALLTHROUGH != "true") & (FALLTHROUGH != "false")) begin
$display("Incorrect setting for FALLTHROUGH parameter, please set to true/false");
$finish();
end
end
reg [WIDTH-1:0] mem[0:2**DEPTH_LOG-1];
reg [DEPTH_LOG:0] count;
integer i;
//SRL shift register, we shift new data in on push
always @(posedge clock)
if (push) begin
mem[0] <= din;
for (i = 1; i < 2 ** DEPTH_LOG; i = i + 1) begin
mem[i] <= mem[i-1];
end
end
//output from SRL
generate
if (FALLTHROUGH == "true") begin : out_comb
always @(*) dout = mem[count];
end else if (FALLTHROUGH == "false") begin : out_reg
always @(posedge clock) if (pop) dout <= mem[count];
end
endgenerate
//modify count on push or pop
always @(posedge clock)
if (reset) count <= {(DEPTH_LOG + 1) {1'b1}};
else if (pop & ~push) count <= count - 1;
else if (push & ~pop) count <= count + 1;
assign empty = count[DEPTH_LOG];
assign full = ~count[DEPTH_LOG] & &count[DEPTH_LOG-1:0];
endmodule
| 6.896375 |
module srl_macro (
clk,
ce,
din,
dout
);
input clk;
input ce;
input [`DATA_WIDTH*2-1:0] din;
output [`DATA_WIDTH*2-1:0] dout;
//reg [`DATA_WIDTH*2-1:0] dout;
//wire [`DATA_WIDTH*2-1:0] srl_out;
// SRLC32E: 32-Bit Shift Register Look-Up Table (LUT)
parameter A = 5'b11111;
genvar i;
generate
for (i = 0; i < `DATA_WIDTH * 2; i = i + 1) begin : srl_32
SRLC32E #(
.INIT(32'h00000000), // Initial contents of shift register
.IS_CLK_INVERTED(1'b0) // Optional inversion for CLK
) SRLC32E_inst (
.Q (dout[i]), // 1-bit output: SRL Data
.Q31(Q31), // 1-bit output: SRL Cascade Data
.A (A), // 5-bit input: Selects SRL depth
.CE (ce), // 1-bit input: Clock enable
.CLK(clk), // 1-bit input: Clock
.D (din[i]) // 1-bit input: SRL Data
);
end
endgenerate
//always @(posedge clk)
// dout <= srl_out;
// End of SRLC32E_inst instantiation
endmodule
| 6.91484 |
module srmul (
input wire [31:0] a,
input wire [31:0] b,
output wire [31:0] z
);
// SP floating point fields
`define sign 31
`define exponent 30:23
`define mantissa 22:0
// various other constants
`define zero 32'b0
`define NaN 32'hFFFFFFFF
////////////////////////////////////////////////////////////////
// Sign is easy.
wire zs;
assign zs = a[`sign] ^ b[`sign];
////////////////////////////////////////////////////////////////
// Mantissa is hard. Remember mantissa is [22:0]
// Restore hidden one's, use 48-bit precision
wire [47:0] am;
assign am = {24'b0, 1'b1, a[`mantissa]};
wire [47:0] bm;
assign bm = {24'b0, 1'b1, b[`mantissa]};
wire [47:0] ab;
assign ab = am * bm;
// Normalized result will have leading '0' e.g. 01x01=0100
// Else "too big", must make mantissa smaller (rshft 1) and exp bigger (add 1)
wire too_big;
assign too_big = (ab[47] == 1'b1);
// am,bm range = 80,0000-FF,FFFF; ab range = 4000,0000,0000 - 8000,0000,0001
wire [23:0] zm_true;
assign zm_true = too_big ? ab[47:24] : ab[46:23];
wire [22:0] zm_hidden;
assign zm_hidden = zm_true[22:0];
// Final z mantissa is zm with hidden (implied) leading 'one' bit
wire [22:0] zm;
assign zm = zm_hidden[22:0];
////////////////////////////////////////////////////////////////
// Exponent. Use 9-bit computation to get accurate final 8-bit result.
wire [8:0] bias;
assign bias = 9'd127;
wire [8:0] a_exp;
assign a_exp = {1'b0, a[`exponent]};
wire [8:0] b_exp;
assign b_exp = {1'b0, b[`exponent]};
wire [8:0] ae_plus_be;
assign ae_plus_be = a_exp + b_exp;
wire [8:0] ze_prenorm;
assign ze_prenorm = ae_plus_be - bias;
wire [8:0] ze_norm;
assign ze_norm = too_big ? (ze_prenorm + 9'b1) : ze_prenorm;
// Final z exponent
wire [7:0] ze;
assign ze = ze_norm[7:0];
////////////////////////////////////////////////////////////////
// overflow and underflow
wire ufw;
assign ufw = too_big ? ((ae_plus_be + 9'b1) < bias) : (ae_plus_be < bias);
wire ofw;
assign ofw = (ze_norm[8] == 1'b1);
////////////////////////////////////////////////////////////////
/*
assign z = (a==`zero) ? `zero : (
(b==`zero) ? `zero : (
(ufw) ? `zero : (
(ofw) ? `NaN : (
{zs, ze, zm}
))));
*/
assign z = (a == `zero) ? `zero : ((b == `zero) ? `zero : ((ofw) ? `NaN : ({zs, ze, zm})));
// `define DBG1
// `define DBG9
`ifdef DBG1
// DEBUGGING
always @(*) begin
if ((a != 0) && (b != 0)) begin
// if ((a != 0) && (b == 32'h40000000)) begin
$display("srmul a=bsr'%08X (%08X) b=bsr'%08X (%08X) z=bsr'%08X (%08X)", a, a, b, b, z, z);
`ifdef DBG9
$display("srmul as=%1x bs=%1x zs=%1x", a[`sign], b[`sign], z[`sign]);
$display("srmul ----");
$display("srmul ae8=%09b be8=%09b ze8=%09b", a[`exponent], b[`exponent], z[`exponent]);
$display("srmul ae9=%09b be9=%09b ze9=%09b", a_exp, b_exp, ze);
$display("srmul ae_plus_be=%09b", ae_plus_be);
$display("srmul ze_prenorm=%09b", ze_prenorm);
$display("srmul too_big=%1b ze_norm=%09b", too_big, ze_norm);
$display("srmul aeb=%09b beb=%09b zeb=%09b", a_exp - bias, b_exp - bias, ze - bias);
$display("srmul ----");
$display("srmul am=%06X bm=%06X zm=%06X", am, bm, zm);
$display("srmul ab=%012X ab[47:46]=%02b", ab, ab[47:46]);
$display("srmul zm_true=%06X", zm_true);
$display("srmul zm_hidden=%06X", zm_hidden);
$display("srmul zm_true[23]=%1b ab[46]=%1b", zm_true[23], ab[46]);
$display("srmul ----");
$display("srmul ufw=%1b ofw=%1b", ufw, ofw);
$display("srmul ");
`endif
end // if ((a != 0) && (b != 0))
end // always @ (*)
`endif
endmodule
| 7.230632 |
module SRAM_4096x128_wrapper (
// Global inputs
input CK, // Clock (synchronous read/write)
input [1:0] SM, // Speed mode
// Control and data inputs
input CS, // Chip select (active high)
input WE, // Write enable (active high)
input [ 11:0] A, // Address bus
input [127:0] D, // Data input bus (write)
input [127:0] M, // Mask bus (write, 1=overwrite)
// Data output
output [127:0] Q // Data output bus (read)
);
`ifdef SRAM_BEHAV
// Simple behavioral code for simulation, to be replaced by a 4096-word 128-bit SRAM macro
// or Block RAM (BRAM) memory with the same format for FPGA implementations.
reg [127:0] SRAM[4095:0];
reg [127:0] Qr;
always @(posedge CK) begin
Qr <= CS ? SRAM[A] : Qr;
if (CS & WE) SRAM[A] <= (D & M) | (SRAM[A] & ~M);
end
assign Q = Qr;
`else
// //
// SRAM macro instantiation goes here //
// (technology-specific cells/macros have been removed) //
// //
`endif
endmodule
| 7.030444 |
module SRAM_512x128_wrapper (
// Global inputs
input CK, // Clock (synchronous read/write)
input [1:0] SM, // Speed mode
// Control and data inputs
input CS, // Chip select (active high)
input WE, // Write enable (active high)
input [ 8:0] A, // Address bus
input [127:0] D, // Data input bus (write)
input [127:0] M, // Mask bus (write, 1=overwrite)
// Data output
output [127:0] Q // Data output bus (read)
);
`ifdef SRAM_BEHAV
// Simple behavioral code for simulation, to be replaced by a 512-word 128-bit SRAM macro
// or Block RAM (BRAM) memory with the same format for FPGA implementations.
reg [127:0] SRAM[511:0];
reg [127:0] Qr;
always @(posedge CK) begin
Qr <= CS ? SRAM[A] : Qr;
if (CS & WE) SRAM[A] <= (D & M) | (SRAM[A] & ~M);
end
assign Q = Qr;
`else
// //
// SRAM macro instantiation goes here //
// (technology-specific cells/macros have been removed) //
// //
`endif
endmodule
| 7.124347 |
module SRAM_128x128_wrapper (
// Global inputs
input CK, // Clock (synchronous read/write)
input [1:0] SM, // Speed mode
// Control and data inputs
input CS, // Chip select (active high)
input WE, // Write enable (active high)
input [ 6:0] A, // Address bus
input [127:0] D, // Data input bus (write)
input [127:0] M, // Mask bus (write, 1=overwrite)
// Data output
output [127:0] Q // Data output bus (read)
);
`ifdef SRAM_BEHAV
// Simple behavioral code for simulation, to be replaced by a 128-word 128-bit SRAM macro
// or Block RAM (BRAM) memory with the same format for FPGA implementations.
reg [127:0] SRAM[127:0];
reg [127:0] Qr;
always @(posedge CK) begin
Qr <= CS ? SRAM[A] : Qr;
if (CS & WE) SRAM[A] <= (D & M) | (SRAM[A] & ~M);
end
assign Q = Qr;
`else
// //
// SRAM macro instantiation goes here //
// (technology-specific cells/macros have been removed) //
// //
`endif
endmodule
| 6.883647 |
module output_act_err (
input wire en,
input wire regr,
input wire act,
input wire label,
input wire signed [15:0] target,
input wire signed [15:0] vo,
output wire signed [15:0] e
);
reg signed [15:0] yt;
reg signed [15:0] y;
wire signed [15:0] e_temp;
wire ovfl_p, ovfl_n;
// Output
always @(*)
if (en)
if (act)
if (vo > $signed(16'd2047)) y = $signed(16'd2048);
else if (vo < $signed(-16'd2048)) y = $signed(16'd0);
else y = $signed((vo + $signed(16'd2048)) >>> 1);
else y = vo;
else y = $signed(16'd0);
// Target
always @(*)
if (en)
if (regr) // Regression
yt = target;
else // Classification
yt = label ? $signed(16'd2048) : $signed(16'd0);
else yt = $signed(16'd0);
// Error
assign e_temp = yt - y;
assign ovfl_p = ~yt[15] & y[15] & e_temp[15];
assign ovfl_n = yt[15] & ~y[15] & ~e_temp[15];
assign e = ovfl_p ? $signed(16'h7FFF) : (ovfl_n ? $signed(16'h8000) : e_temp);
endmodule
| 8.045176 |
module stoch_update #(
parameter WIDTH_IN = 16,
parameter LR_IN = 4
) (
input wire signed [WIDTH_IN-1:0] prob,
input wire signed [ 7:0] w_in,
input wire en,
input wire [ LR_IN-1:0] lr_r,
input wire [ LR_IN-1:0] lr_p,
input wire [WIDTH_IN-1:0] rnd,
output wire signed [ 7:0] w_out,
output wire [ 7:0] mask
);
wire prob_0, prob_m, prob_ovfl;
wire update;
wire overflow;
wire no_change;
wire signed [7:0] w_updated;
wire [WIDTH_IN-1:0] prob_abs, prob_tot;
wire [WIDTH_IN+(1<<LR_IN)-1:0] prob_lrp;
assign prob_0 = (prob == 'd0) | ~en;
assign prob_m = (~|prob[WIDTH_IN-2:0] & prob[WIDTH_IN-1]);
assign prob_abs = prob_0 ? 'd0 : (prob[WIDTH_IN-1] ? {$signed(~prob) + $signed('d1)} : prob);
assign prob_lrp = {{(1 << LR_IN) {1'b0}}, prob_abs} << lr_p;
assign prob_ovfl = |prob_lrp[WIDTH_IN+(1<<LR_IN)-1:WIDTH_IN];
assign prob_tot = (prob_ovfl ? {WIDTH_IN{1'b1}} : prob_lrp[WIDTH_IN-1:0]) >> lr_r;
assign update = prob_m | (prob_tot >= rnd);
assign no_change = prob_0 | ~update;
assign w_updated = prob[WIDTH_IN-1] ? (w_in - $signed(8'd1)) : (w_in + $signed(8'd1));
assign overflow = (w_in[7] & ~w_updated[7] & prob[WIDTH_IN-1]) | (~w_in[7] & w_updated[7] & ~prob[WIDTH_IN-1]);
assign w_out = (no_change | overflow) ? w_in : w_updated;
assign mask = {8{~no_change}};
endmodule
| 6.646789 |
module.
//
// -----------------------------History-----------------------------------//
// Date BY Version Change Description
//
// 20200101 PODES 1.0 Initial Release.
// Use SRAM replace the SROM in FPGA, so that program code
// can be downloaded repeatedly for debugging.
//
//************************************************************************//
// --- CVS information:
// --- $Author: $
// --- $Revision: $
// --- $Id: $
// --- $Log$
//
//************************************************************************//
module srom_model(
clk,
boot_ctrl,
//SRAM interface
romcs_n,
romaddr,
romdout,
romdin,
romben,
romwr_n
);
//-----------------------------------------------------------//
// PARAMETERS //
//-----------------------------------------------------------//
parameter MDW = 32;
parameter MAW = 32;
parameter MAM = 4096; // 4K words for sim.
//-----------------------------------------------------------//
// INPUTS/OUTPUTS //
//-----------------------------------------------------------//
input clk;
input boot_ctrl;
output [MDW-1:0] romdout;
input romcs_n;
input [MAW-1:0] romaddr;
input [MDW-1:0] romdin;
input [3:0] romben;
input romwr_n;
wire [31:0] boot_romdout;
wire [31:0] code_romdout;
assign romdout = boot_ctrl ? boot_romdout : code_romdout;
wire wren = ~romcs_n & ~romwr_n;
ram32x4096 ram32x4096_u0 (
.clk (clk ),
.dout (code_romdout ),
.addr (romaddr[13:2] ),
.din (romdin ),
.ben (romben ),
.wren (wren )
);
ram32x256 ram32x256_u0 (
.clk (clk ),
.dout (boot_romdout ),
.addr (romaddr[9:2] ),
.din (32'b0 ),
.ben (romben ),
.wren (1'b0 )
);
endmodule
| 6.769864 |
module srrc_filter #(
parameter DATA_IN_WIDTH = 16,
parameter DATA_OUT_WIDTH = 16,
parameter PATH_DATA_WIDTH = 24
) (
input clk_in,
input [DATA_IN_WIDTH-1:0] data_in_I,
input [DATA_IN_WIDTH-1:0] data_in_Q,
input data_in_valid,
output data_in_ready,
output [DATA_OUT_WIDTH-1:0] data_out_I,
output [DATA_OUT_WIDTH-1:0] data_out_Q,
output data_out_valid
);
`ifdef USE_XILINX_IP
// USE XILINX IP
// WARNING : START UP LATENCY = 17 CLKs
// AXI4 Stream Port Structure
// S_AXIS_DATA
// Data Field Type
// Q PATH_1(31:16) fix16_0
// I PATH_0(15: 0) fix16_0
// M_AXIS_DATA
// Data Field Type
// Q PATH_1(40:24) fix17_2
// I PATH_0(16: 0) fix17_2
// [16:0] -> {1'b0,[16:2]} -> 4(I) -> [15:0]
wire [DATA_IN_WIDTH*2-1:0] data_in;
assign data_in = {data_in_Q, data_in_I};
wire [PATH_DATA_WIDTH*2-1:0] data_out;
assign data_out_I = data_out[DATA_OUT_WIDTH+PATH_DATA_WIDTH*0-1:PATH_DATA_WIDTH*0];
assign data_out_Q = data_out[DATA_OUT_WIDTH+PATH_DATA_WIDTH*1-1:PATH_DATA_WIDTH*1];
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
srrc_filter_0 srrc_filter_0_inst (
.aclk (clk_in), // input wire aclk
.s_axis_data_tvalid(data_in_valid), // input wire s_axis_data_tvalid
.s_axis_data_tready(data_in_ready), // output wire s_axis_data_tready
.s_axis_data_tdata (data_in), // input wire [31 : 0] s_axis_data_tdata
.m_axis_data_tvalid(data_out_valid), // output wire m_axis_data_tvalid
.m_axis_data_tdata (data_out) // output wire [47 : 0] m_axis_data_tdata
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
`endif
endmodule
| 8.122411 |
module SRSG #(
parameter n = 8
) (
clk,
rst,
en,
poly,
seed,
Sout
);
input clk, rst, en;
input [n - 1:0] seed;
input [n - 1:0] poly;
output Sout;
reg [n - 1:0] data;
integer i;
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) data = seed;
else if (en == 1'b1) begin
data[n-1] <= data[0];
for (i = 0; i < n - 1; i = i + 1) begin
data[i] <= (data[0] & poly[i]) ^ data[i+1];
end
end
end
assign Sout = data[0];
endmodule
| 6.970692 |
module SRSystem_DL (
pd,
d,
Q
);
input wire pd;
input wire [7:0] d;
output reg [7:0] Q;
always @(posedge pd) Q <= d;
endmodule
| 7.313147 |
module SRSystem_Parity (
qst,
q,
opn,
qsp,
P
);
input wire qst, opn, qsp;
input wire [7:0] q;
output wire P;
assign P = qst ^ opn ^ q[0] ^ q[1] ^ q[2] ^ q[3] ^ q[4] ^ q[5] ^ q[6] ^ q[7] ^ qsp;
endmodule
| 7.391556 |
module SRTSystem_TD (
clk,
send,
rst,
d,
en,
ERR,
Q,
extra_ack
); //extra_ack
input wire clk, send, rst, en;
input wire [0:7] d;
output wire ERR;
output wire [0:7] Q;
output wire [0:1] extra_ack; //extra
wire stsack, srsack, dry, rts, tx, pd;
STSystem_TD STSystem (
.clk(clk),
.send(send),
.rst(rst),
.ack(stsack),
.d(d),
.RTS(rts),
.TX(tx),
.PD(pd)
);
SRTSystem_ACK STSACK (
.ready(rts),
.clk (clk),
.ACK (stsack)
);
SRSystem_TD SRSystem (
.clk(clk),
.ack(srsack),
.en (en),
.rst(rst),
.rx (tx),
.st (~pd),
.DRY(dry),
.ERR(ERR),
.Q (Q)
);
SRTSystem_ACK SRSACK (
.ready(dry),
.clk (clk),
.ACK (srsack)
);
assign extra_ack = {stsack, srsack}; //extra
endmodule
| 6.596584 |
module SRTSystem_testbench();
reg clk,send,rst;
reg [0:7] d;
wire ERR;
wire [0:7]Q;
wire [0:1] extra_ack; //extra
SRTSystem_TD SRTS_testbench(.clk(clk), .send(send), .rst(rst), .d(d), .en(1'b1), .ERR(ERR), .Q(Q), .extra_ack(extra_ack));//extra
reg [0:7] Mem [0:29];
reg [7:0]counter;
initial
begin
clk=0;
send=0;
rst=0;
d=0;
counter=0;
#10
rst=1;
send=1;
d=Mem[0];
end
reg [11:0] w_file;
initial
w_file = $fopen(data/SRTStb_Input_data12.bin");
always @(posedge clk)
begin
$fdisplay(w_file,"%b",{d,send,rst,extra_ack});
end
always@(posedge extra_ack[0])
begin
counter=counter+1;
if(counter==30)
$stop;
else
d=Mem[counter];
end
initial
$readmemb("data/randomdin.txt",Mem);
//r_file = $fopen("D:/study/notepad/matlab/MATLABSRTS/data/randomdin.txt");
always #1 clk<=~clk;
endmodule
| 7.001608 |
module srt_corr_top (
input sys_clk_in,
input sys_rst,
input uart_rx,
input start_button,
input adc_dav_1,
input adc_dav_2,
input [1:0] delay_sel,
input [15:0] data_in_1,
input [15:0] data_in_2,
// DEBUG PINS -- TO BE REMOVED
output done,
output failure,
//
output clk_sample_p_1,
output clk_sample_p_2,
output uart_tx
);
// PAR SIMULATION PARAMETERS
// parameter LPF_TAP=32;
// parameter LPF_LOG2=5;
// parameter HPF_TAP=64;
// parameter HPF_LOG2=6;
// parameter NSAMPLES = 25'd1024;
// parameter LOG2_NSAMPLES = 25;
// IMPLEMENTATION PARAMETERS
parameter LPF_TAP = 32;
parameter LPF_LOG2 = 5;
parameter HPF_TAP = 64;
parameter HPF_LOG2 = 6;
parameter NSAMPLES = 32'd5000000; // default 5E06 samples (0.200 sec. at 25Mhz)
parameter LOG2_NSAMPLES = 32;
wire locked_out;
wire [7:0] uart_byte;
wire [31:0] cr;
wire [31:0] sr_out;
wire [63:0] sum_x_2;
wire [63:0] sum_y_2;
wire [63:0] sum_xy;
wire [63:0] sum_xy90;
wire [63:0] sum_y90_2;
wire [63:0] sum_y_y90;
wire clk_sample_p;
wire sample_cnt_shift;
assign master_reset = ~sys_rst | ~locked_out;
assign clk_sample_p_1 = clk_sample_p;
assign clk_sample_p_2 = clk_sample_p;
// DEBUG SIGNALS
assign done = sr_out[0];
assign failure = sr_out[1];
//
// MASTER CONTROL
master_top MASTER_CONTROL (
.sys_clk(sys_clk),
.sys_rst(master_reset),
.start_button(start_button),
.uart_rx(uart_rx),
.sr_in(sr_out),
.sum_x_2(sum_x_2),
.sum_y_2(sum_y_2),
.sum_xy(sum_xy),
.sum_xy90(sum_xy90),
.sum_y90_2(sum_y90_2),
.sum_y_y90(sum_y_y90),
.uart_tx(uart_tx),
.corr_reset(corr_reset),
.we(we),
.sample_cnt_shift(sample_cnt_shift),
.uart_byte(uart_byte),
.cr(cr)
);
// CORRELATOR
top_corr #(
// Filter Parameters
// Warning: Do not use a LPF_TAP value greater than HPF_TAP value
LPF_TAP, LPF_LOG2, HPF_TAP, HPF_LOG2, NSAMPLES, LOG2_NSAMPLES) CORRELATOR (
.sys_clk(sys_clk),
.clk_2x(clk_2x),
.rst(corr_reset),
.adc_dav_1(adc_dav_1),
.adc_dav_2(adc_dav_2),
.we(we),
.sample_cnt_shift(sample_cnt_shift),
.delay_sel(delay_sel),
.data_in_1(data_in_1),
.data_in_2(data_in_2),
.uart_byte(uart_byte),
.cr_in(cr),
.clk_sample_p(clk_sample_p),
.clk_sample_n(clk_sample_n),
.sr_out(sr_out),
.sum_x_2(sum_x_2),
.sum_y_2(sum_y_2),
.sum_xy(sum_xy),
.sum_xy90(sum_xy90),
.sum_y90_2(sum_y90_2),
.sum_y_y90(sum_y_y90)
);
// DCM MODULE --> 2x
dcm_module DCM_MODULE (
.CLKIN_IN(sys_clk_in),
.RST_IN(~sys_rst),
.CLKIN_IBUFG_OUT(sys_clk_in_ibuf),
.CLK0_OUT(sys_clk),
.CLK2X_OUT(clk_2x),
.LOCKED_OUT(locked_out)
);
endmodule
| 7.10729 |
module SRT_tb ();
reg [3:0] x0, x1, x2, x3;
reg clk, rst;
wire [3:0] s0, s1, s2, s3;
wire done;
SRT DUT (
.x0 (x0),
.x1 (x1),
.x2 (x2),
.x3 (x3),
.clk (clk),
.rst (rst),
.s0 (s0),
.s1 (s1),
.s2 (s2),
.s3 (s3),
.done(done)
);
integer k;
initial begin
x0 = 4'd4;
x1 = 4'd3;
x2 = 4'd2;
x3 = 4'd1;
clk = 0;
k = 0;
rst = 0;
#20 rst = 1;
#20 rst = 0;
#100 clk = ~clk;
while (k < 15) begin
#50 clk = ~clk;
k = k + 1;
end
end
endmodule
| 6.710606 |
module sru_dcscmd_par (
input dcs_rx_clk,
input [7:0] dcs_rxd,
input dcs_rx_dv,
input gclk_40m,
output reg udp_cmd_dv = 1'b0,
output reg [31:0] udp_cmd_addr = 32'h0,
output reg [31:0] udp_cmd_data = 32'h0,
input udp_reply_stored,
input reset
);
reg fifo_rd_en = 1'b0;
wire [31:0] fifo_rd_dout;
wire fifo_rd_empty;
parameter st0 = 0;
parameter st1 = 1;
parameter st2 = 2;
parameter st3 = 3;
parameter st4 = 4;
parameter st5 = 5;
parameter st6 = 6;
parameter st7 = 7;
parameter st8 = 8;
parameter st9 = 9;
reg [3:0] st = st0;
reg [7:0] clkcnt = 8'h0;
fifo_8to32b u_fifo_8to32b (
.rst(reset), // input rst
.wr_clk(dcs_rx_clk), // input wr_clk
.rd_clk(gclk_40m), // input rd_clk
.din(dcs_rxd), // input [7 : 0] din
.wr_en(dcs_rx_dv), // input wr_en
.rd_en(fifo_rd_en), // input rd_en
.dout(fifo_rd_dout), // output [31 : 0] dout
.full(), // output full
.empty(fifo_rd_empty) // output empty
);
always @(posedge gclk_40m)
if (reset) begin
fifo_rd_en <= 1'b0;
udp_cmd_dv <= 1'b0;
udp_cmd_addr <= 32'h0;
udp_cmd_data <= 32'h0;
clkcnt <= 8'h0;
st <= st0;
end else
case (st)
st0: begin
fifo_rd_en <= 1'b0;
udp_cmd_dv <= 1'b0;
udp_cmd_addr <= 32'h0;
udp_cmd_data <= 32'h0;
clkcnt <= 8'h0;
if (fifo_rd_empty) st <= st0;
else st <= st1;
end
st1: begin
fifo_rd_en <= 1'b0;
udp_cmd_dv <= 1'b0;
udp_cmd_addr <= 32'h0;
udp_cmd_data <= 32'h0;
clkcnt <= 8'h0;
if (dcs_rx_dv) st <= st1;
else st <= st9;
end
st9: begin
fifo_rd_en <= 1'b0;
udp_cmd_dv <= 1'b0;
udp_cmd_addr <= 32'h0;
udp_cmd_data <= 32'h0;
clkcnt <= clkcnt + 4'd1;
if (clkcnt == 4'd10) st <= st2;
else st <= st9;
end
st2: begin
fifo_rd_en <= 1'b1;
udp_cmd_dv <= 1'b0;
udp_cmd_addr <= 32'h0;
udp_cmd_data <= 32'h0;
clkcnt <= 8'h0;
st <= st3;
end
st3: begin
fifo_rd_en <= 1'b1;
udp_cmd_dv <= 1'b0;
udp_cmd_addr <= udp_cmd_addr;
udp_cmd_data <= udp_cmd_data;
clkcnt <= 8'h0;
st <= st4;
end
st4: begin
fifo_rd_en <= 1'b0;
udp_cmd_dv <= 1'b0;
udp_cmd_addr <= fifo_rd_dout;
udp_cmd_data <= udp_cmd_data;
clkcnt <= 8'h0;
st <= st5;
end
st5: begin
fifo_rd_en <= 1'b0;
udp_cmd_dv <= 1'b1;
udp_cmd_addr <= udp_cmd_addr;
udp_cmd_data <= fifo_rd_dout;
clkcnt <= clkcnt + 8'h1;
if (udp_cmd_addr[31]) //read
st <= st6;
else st <= st7;
end
st6: begin
fifo_rd_en <= 1'b0;
udp_cmd_dv <= 1'b1;
udp_cmd_addr <= udp_cmd_addr;
udp_cmd_data <= fifo_rd_dout;
clkcnt <= clkcnt + 8'h1;
if (udp_reply_stored) //read
st <= st7;
else if (clkcnt == 8'd250) st <= st8;
else st <= st6;
end
st7: begin
fifo_rd_en <= 1'b0;
udp_cmd_dv <= 1'b1;
udp_cmd_addr <= udp_cmd_addr;
udp_cmd_data <= fifo_rd_dout;
clkcnt <= clkcnt + 8'h1;
if (udp_reply_stored)
if (clkcnt == 8'd200) st <= st8;
else st <= st7;
else st <= st8;
end
st8: begin
fifo_rd_en <= 1'b0;
udp_cmd_dv <= 1'b0;
udp_cmd_addr <= udp_cmd_addr;
udp_cmd_data <= udp_cmd_data;
clkcnt <= 8'h0;
if (fifo_rd_empty) st <= st0;
else st <= st2;
end
default: begin
fifo_rd_en <= 1'b0;
udp_cmd_dv <= 1'b0;
udp_cmd_addr <= 32'h0;
udp_cmd_data <= 32'h0;
clkcnt <= 8'h0;
st <= st0;
end
endcase
endmodule
| 7.424978 |
module sru_dcs_fifo (
input gclk_40m,
input dcs_rx_clk,
input [7:0] dcs_rxd,
input dcs_rx_dv,
//DCS rx_fifo read interface
input dcs_rd_clk, //40MHz
output dcs_rd_sof_n,
output [ 7:0] dcs_rd_data_out,
output dcs_rd_eof_n,
output dcs_rd_src_rdy_n,
input dcs_rd_dst_rdy_n,
input [ 5:0] dcs_rd_addr,
output [ 3:0] dcs_rx_fifo_status,
output dcs_rx_overflow,
input [15:0] dcs_udp_dst_port,
input [15:0] dcs_udp_src_port,
input [63:0] dcs_cmd_reply,
input dcs_cmd_update,
output udp_cmd_dv,
output [31:0] udp_cmd_addr,
output [31:0] udp_cmd_data,
input reset
);
wire dcs_wr_clk, udp_reply_stored;
parameter SruFifoAddr = 6'd41;
dcs_client_fifo_wr_fsm #(
.DcsNode(6'd41),
.DcsFifoAddr(SruFifoAddr)
) u_dcs_client_fifo_wr_fsm (
//Fifo RD interface
.dcs_rd_clk (dcs_rd_clk),
.dcs_rd_data_out (dcs_rd_data_out),
.dcs_rd_sof_n (dcs_rd_sof_n),
.dcs_rd_eof_n (dcs_rd_eof_n),
.dcs_rd_src_rdy_n (dcs_rd_src_rdy_n),
.dcs_rd_dst_rdy_n (dcs_rd_dst_rdy_n),
.dcs_rd_addr (dcs_rd_addr),
.dcs_rx_fifo_status(dcs_rx_fifo_status),
.dcs_rx_overflow (dcs_rx_overflow),
.dcs_udp_dst_port (dcs_udp_dst_port),
.dcs_udp_src_port (dcs_udp_src_port),
//command reply
.dcs_wr_clk (dcs_wr_clk),
.dcs_cmd_reply (dcs_cmd_reply),
.dcs_cmd_update (dcs_cmd_update),
.udp_reply_stored(udp_reply_stored),
.reset(reset)
);
sru_dcscmd_par u_sru_dcscmd_par (
.dcs_rx_clk(dcs_rx_clk),
.dcs_rxd(dcs_rxd),
.dcs_rx_dv(dcs_rx_dv),
.gclk_40m(gclk_40m),
.udp_cmd_dv(udp_cmd_dv),
.udp_cmd_addr(udp_cmd_addr),
.udp_cmd_data(udp_cmd_data),
.udp_reply_stored(udp_reply_stored),
.reset(reset)
);
assign dcs_wr_clk = gclk_40m;
endmodule
| 7.454628 |
module is a 128-bit shift register. It works the same way as the provided code
// for a 4-bit shift register, but is now extended to 128 bits.
// Purpose: A 128-bit shift register is needed to whole important key and message encryption values
// The module is instantiated in AES.sv
module SR_128b (input Clk, Reset, Load1, Load2,
input [127:0] data_1, data_2, // 128-bit extension
output reg [127:0] Data_Out); // 128-bit extension
always @ (posedge Clk)
begin
if (Reset) //notice, this is a sycnrhonous reset, which is recommended on the FPGA
Data_Out <= 128'h0;
else if (Load1)
Data_Out <= data_1;
else if (Load2)
Data_Out <= data_2;
end
endmodule
| 7.872268 |
module top (
input clk_16mhz,
output [7:0] pmod_a
);
// sr_74595 wires and registers
reg [24:0] counter = 0;
always @(posedge clk_16mhz) begin
counter <= counter + 1;
end
reg sr_oe = 0;
reg sr_lat = 0;
reg sr_ser = 0;
reg [3:0] line = 0;
reg [1:0] line_counter = 0;
reg [7:0] line_buffer = 0;
reg [3:0] col_counter = 0;
reg commit_row = 0;
reg [7:0] frame_buffer[3:0];
reg [7:0] lfsr = 1;
reg update = 0;
// Signals <-> PMOD
// Use below for standard PMOD
assign pmod_a[3:0] = line[3:0];
assign pmod_a[4] = sr_oe;
assign pmod_a[5] = sr_lat;
assign pmod_a[6] = counter[1];
assign pmod_a[7] = sr_ser;
// Use below for flipped connector on horizontal breakout
// assign pmod_a[3] = line[0];
// assign pmod_a[2] = line[1];
// assign pmod_a[1] = line[2];
// assign pmod_a[0] = line[3];
// assign pmod_a[7] = sr_oe;
// assign pmod_a[6] = sr_lat;
// assign pmod_a[5] = counter[1];
// assign pmod_a[4] = sr_ser;
// Time to display all the things!
always @(posedge counter[1]) begin
case (line_counter)
2'b00: begin
line = 4'b0001;
end
2'b01: begin
line = 4'b0010;
end
2'b10: begin
line = 4'b0100;
end
2'b11: begin
line = 4'b1000;
end
endcase
if (col_counter == 0 && commit_row == 0) begin
sr_lat <= 1;
sr_oe <= 1;
line_counter <= line_counter + 1;
commit_row <= 1;
line_buffer <= frame_buffer[line_counter+2];
end else begin
sr_lat <= 0;
sr_oe <= 0;
commit_row <= 0;
sr_ser <= line_buffer[col_counter];
col_counter <= col_counter + 1;
end
if (counter[20] == 1 && update == 0) begin
if (col_counter == 0 && line_counter == 0) begin
update <= 1;
lfsr <= {lfsr[6:0], ~(lfsr[7] ^ lfsr[2])};
frame_buffer[3] <= frame_buffer[2];
frame_buffer[2] <= frame_buffer[1];
frame_buffer[1] <= frame_buffer[0];
frame_buffer[0] <= lfsr;
end
end else if (counter[20] == 0) begin
update <= 0;
end
end
endmodule
| 7.233807 |
module sr_cpu_vc (
input clk, // clock
input rst_n, // reset
input [ 4:0] regAddr, // debug access reg address
output [31:0] regData, // debug access reg data
output [31:0] imAddr, // instruction memory address
input [31:0] imData, // instruction memory data
output reg [31:0] vcu_reg_control, // control register for video control unit (vcu)
output reg vcu_reg_control_we, // 1 - new data in the vcu_reg_control
output reg [31:0] vcu_reg_wdata, // data register for video control unit (vcu)
output reg vcu_reg_wdata_we, // 1 - new data in the vcu_reg_wdata
input [31:0] vcu_reg_rdata // input data
);
//control wires
wire aluZero;
wire pcSrc;
wire regWrite;
wire aluSrc;
wire wdSrc;
wire [ 2:0] aluControl;
//instruction decode wires
wire [ 6:0] cmdOp;
wire [ 4:0] rd;
wire [ 2:0] cmdF3;
wire [ 4:0] rs1;
wire [ 4:0] rs2;
wire [ 6:0] cmdF7;
wire [31:0] immI;
wire [31:0] immB;
wire [31:0] immU;
//program counter
wire [31:0] pc;
wire [31:0] pcBranch = pc + immB;
wire [31:0] pcPlus4 = pc + 4;
wire [31:0] pcNext = pcSrc ? pcBranch : pcPlus4;
sm_register r_pc (
clk,
rst_n,
pcNext,
pc
);
//program memory access
assign imAddr = pc >> 2;
wire [31:0] instr = imData;
//instruction decode
sr_decode id (
.instr(instr),
.cmdOp(cmdOp),
.rd (rd),
.cmdF3(cmdF3),
.rs1 (rs1),
.rs2 (rs2),
.cmdF7(cmdF7),
.immI (immI),
.immB (immB),
.immU (immU)
);
//register file
wire [31:0] rd0;
wire [31:0] rd1;
wire [31:0] rd2;
wire [31:0] wd3;
sm_register_file_vc rf (
.clk (clk),
.a0 (regAddr),
.a1 (rs1),
.a2 (rs2),
.a3 (rd),
.rd0 (rd0),
.rd1 (rd1),
.rd2 (rd2),
.wd3 (wd3),
.we3 (regWrite),
.vcu_reg_rdata(vcu_reg_rdata)
);
//debug register access
assign regData = (regAddr != 0) ? rd0 : pc;
// VCU register
always @(posedge clk) begin
if (~rst_n) vcu_reg_control <= 0;
else if (regWrite & rd == 5'b11111) vcu_reg_control <= wd3;
if (rd == 5'b11111) vcu_reg_control_we <= regWrite;
else vcu_reg_control_we <= 0;
if (~rst_n) vcu_reg_wdata <= 0;
else if (regWrite & rd == 5'b11110) vcu_reg_wdata <= wd3;
if (rd == 5'b11110) vcu_reg_wdata_we <= regWrite;
else vcu_reg_wdata_we <= 0;
end
//alu
wire [31:0] srcB = aluSrc ? immI : rd2;
wire [31:0] aluResult;
sr_alu alu (
.srcA (rd1),
.srcB (srcB),
.oper (aluControl),
.zero (aluZero),
.result(aluResult)
);
assign wd3 = wdSrc ? immU : aluResult;
//control
sr_control sm_control (
.cmdOp (cmdOp),
.cmdF3 (cmdF3),
.cmdF7 (cmdF7),
.aluZero (aluZero),
.pcSrc (pcSrc),
.regWrite (regWrite),
.aluSrc (aluSrc),
.wdSrc (wdSrc),
.aluControl(aluControl)
);
endmodule
| 7.19695 |
module sr_decode (
input [31:0] instr,
output [ 6:0] cmdOp,
output [ 4:0] rd,
output [ 2:0] cmdF3,
output [ 4:0] rs1,
output [ 4:0] rs2,
output [ 6:0] cmdF7,
output reg [31:0] immI,
output reg [31:0] immB,
output reg [31:0] immU
);
assign cmdOp = instr[ 6: 0];
assign rd = instr[11: 7];
assign cmdF3 = instr[14:12];
assign rs1 = instr[19:15];
assign rs2 = instr[24:20];
assign cmdF7 = instr[31:25];
// I-immediate
always @(*) begin
immI[10:0] = instr[30:20];
immI[31:11] = {21{instr[31]}};
end
// B-immediate
always @(*) begin
immB[0] = 1'b0;
immB[4:1] = instr[11:8];
immB[10:5] = instr[30:25];
immB[11] = instr[7];
immB[31:12] = {20{instr[31]}};
end
// U-immediate
always @(*) begin
immU[11:0] = 12'b0;
immU[31:12] = instr[31:12];
end
endmodule
| 7.840724 |
module sr_alu (
input [31:0] srcA,
input [31:0] srcB,
input [ 2:0] oper,
output zero,
output reg [31:0] result
);
always @(*) begin
case (oper)
default: result = srcA + srcB;
`ALU_ADD: result = srcA + srcB;
`ALU_OR: result = srcA | srcB;
`ALU_SRL: result = srcA >> srcB[4:0];
`ALU_SLTU: result = (srcA < srcB) ? 1 : 0;
`ALU_SUB: result = srcA - srcB;
endcase
end
assign zero = (result == 0);
endmodule
| 7.51464 |
module sm_register_file_vc (
input clk,
input [ 4:0] a0,
input [ 4:0] a1,
input [ 4:0] a2,
input [ 4:0] a3,
output [31:0] rd0,
output [31:0] rd1,
output [31:0] rd2,
input [31:0] wd3,
input we3,
input [31:0] vcu_reg_rdata
);
reg [31:0] rf[31:0];
assign rd0 = (a0 != 0) ? rf[a0] : 32'b0;
assign rd1 = (a1 != 0) ? rf[a1] : 32'b0;
assign rd2 = (a2 != 0) ? rf[a2] : 32'b0;
always @(posedge clk) begin
if (a3 != 5'b11110) if (we3) rf[a3] <= wd3;
rf[5'b11110] <= vcu_reg_rdata;
end
endmodule
| 7.126393 |
module SR_DECOMP (
input wire rst_n,
input wire clk,
input wire valid_i,
input wire [63:0] data_i,
input wire sop_i,
input wire eop_i,
input wire ready_i,
output wire ready_o,
output reg sop_o,
output reg eop_o,
output wire valid_o,
output wire [63:0] data_o
);
reg ready;
reg [63:0] data_out;
reg valid_out;
reg [3:0] bcnt, bcnt_n; // burst count
// Sequential logic //////////////////////////////////////////////
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
bcnt <= 4'b0;
end else begin
bcnt <= bcnt_n;
end
end
////////////////////////////////////////////////////////////////////////////////////
// rstn ____----------------------------------------------------------------
// clk ____----____----____----____----____----____----____----____----____
// sop_i ____--------________________________________________________________
// data_i ____x===============x===============x===============x===============
// valid_i ____----------------------------------------------------------------
// ready_o ____--------________--------________--------________--------________
// data_o ____x=======x=======x=======x=======x=======x=======x=======x=======
// bcnt ____x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7
// valid_o ____----------------------------------------------------------------
// ready_i ____----------------------------------------------------------------
// Combination logic////////////////////////////////////////////////////////////////
always @(*) begin
bcnt_n = bcnt;
valid_out = 0;
data_out = 0;
if (bcnt % 2 == 0) begin
ready = 1;
end else begin
ready = 0;
end
if (valid_i) begin
if (!valid_out | (valid_out & ready_i)) begin
if (bcnt == 0) begin
data_out[63:55] = data_i[62] ? 9'b111111111 : 9'b000000000;
data_out[54:48] = data_i[62:56];
data_out[47:40] = data_i[55] ? 8'b11111111 : 8'b00000000;
data_out[39:32] = data_i[55:48];
data_out[31:24] = data_i[47] ? 8'b11111111 : 8'b00000000;
data_out[23:16] = data_i[47:40];
data_out[15:8] = data_i[39] ? 8'b11111111 : 8'b00000000;
data_out[7:0] = data_i[39:32];
valid_out = 1;
bcnt_n = 1;
end else if (bcnt % 2 == 0) begin
data_out[63:56] = data_i[63] ? 8'b11111111 : 8'b00000000;
data_out[55:48] = data_i[63:56];
data_out[47:40] = data_i[55] ? 8'b11111111 : 8'b00000000;
data_out[39:32] = data_i[55:48];
data_out[31:24] = data_i[47] ? 8'b11111111 : 8'b00000000;
data_out[23:16] = data_i[47:40];
data_out[15:8] = data_i[39] ? 8'b11111111 : 8'b00000000;
data_out[7:0] = data_i[39:32];
valid_out = 1;
bcnt_n = bcnt + 1;
end else if (bcnt % 2 == 1) begin
data_out[63:56] = data_i[31] ? 8'b11111111 : 8'b00000000;
data_out[55:48] = data_i[31:24];
data_out[47:40] = data_i[23] ? 8'b11111111 : 8'b00000000;
data_out[39:32] = data_i[23:16];
data_out[31:24] = data_i[15] ? 8'b11111111 : 8'b00000000;
data_out[23:16] = data_i[15:8];
data_out[15:8] = data_i[7] ? 8'b11111111 : 8'b00000000;
data_out[7:0] = data_i[7:0];
valid_out = 1;
bcnt_n = bcnt + 1;
end
end
end
sop_o = (bcnt == 0 & valid_out);
eop_o = (bcnt == 15 & valid_out);
end
assign ready_o = ready;
assign data_o = data_out;
assign valid_o = valid_out;
endmodule
| 6.780054 |
module sr_ff_behavioural (
input clk,
input S,
input R,
output Q,
output Qbar
);
reg M, N;
always @(posedge clk) begin
M <= !(S & clk);
N <= !(R & clk);
end
assign Q = !(M & Qbar);
assign Qbar = !(N & Q);
endmodule
| 6.689558 |
module sr_ff_behavioural (
input S,
input R,
input clk,
output reg Q,
output reg QBar
);
always @(posedge clk) begin
case ({
S, R
})
0: begin
Q <= Q;
QBar <= QBar;
end
1: begin
Q <= 1'b0;
QBar <= 1'b1;
end
2: begin
Q <= 1'b1;
QBar <= 1'b0;
end
3: begin
Q <= 1'b0;
QBar <= 1'b0;
end
endcase
end
endmodule
| 6.689558 |
module sr_ff_data (
q,
qb,
s,
r,
clk
);
input s, r, clk;
output q, qb;
assign q = ~((~(s & clk)) & qb);
assign qb = ~((~(r & clk)) & q);
endmodule
| 7.601979 |
module: sr_ff
// Revision 0.01 - File Created
// Additional Comments:
////////////////////////////////////////////////////////////////////////////////
module sr_ff_tb;
// Inputs
reg s;
reg r;
reg clk;
reg rst;
// Outputs
wire q;
wire qbar;
// Instantiate the Unit Under Test (UUT)
sr_ff uut (
.s(s),
.r(r),
.clk(clk),
.rst(rst),
.q(q),
.qbar(qbar)
);
initial begin
clk = 0;
rst =1;
#100;rst = 0;
s = 0;r = 0;
#100; $display($time, " s=%b r=%b q=%b qbar=%b ",s,r,q,qbar);
s = 0;r = 1;
#100; $display($time, " s=%b r=%b q=%b qbar=%b ",s,r,q,qbar);
s = 1;r = 0;
#100; $display($time, " s=%b r=%b q=%b qbar=%b ",s,r,q,qbar);
s = 1;r = 1;
#100;$display($time, " s=%b r=%b q=%b qbar=%b ",s,r,q,qbar);
// Add stimulus here
end
always
begin
#5 clk=~clk;
end
endmodule
| 6.505935 |
module SR_Latch (
input S,
R,
CLK,
output Q,
Q_bar
);
wire g, p;
nand #8 G1 (g, S, CLK);
nand #8 G2 (p, R, CLK);
nand #8 G3 (Q, g, Q_bar);
nand #8 G4 (Q_bar, p, Q);
endmodule
| 6.774545 |
module sr_latch (
s,
r,
out
);
input s;
input r;
output reg out;
assign out = 1'b0;
//initialize
always @(s or r) begin
if (s == 1'b1 && r == 1'b0) out = 1'b1;
else if (r == 1'b1 && s == 1'b0) out = 1'b0;
else if (r == 1'b0 && s == 1'b0) out = out;
else out = 1'bx; //forbidden
end
endmodule
| 7.007228 |
module sr_latch_enabled (
input A,
input B,
input C,
output Q,
output Qn
);
wire S, R;
wire s, r, q, qn;
and_gate s1 (
A,
C,
s
);
not_gate s2 (
s,
S
);
and_gate r1 (
B,
C,
r
);
not_gate r2 (
r,
R
);
and_gate out1 (
S,
Qn,
q
);
not_gate out2 (
q,
Q
);
and_gate comp1 (
R,
Q,
qn
);
not_gate comp2 (
qn,
Qn
);
endmodule
| 6.919954 |
module sr_latch_s (
input S,
input R,
output Q,
output QB
);
//Qn=SR'+R'Q
//Qn'=S'R+S'Q'
wire neg_R, neg_S, a1, a2, a3, a4;
not (neg_R, R);
and (a1, neg_R, Q);
and (a2, S, neg_R);
or (Q, a1, a2);
not (neg_S, S);
and (a3, neg_S, R);
and (a4, neg_S, QB);
or (QB, a3, a4);
endmodule
| 6.617001 |
module SR_LATCH_TB ();
// INPUT PROBES
reg S, R;
// OUTPUT PROBES
wire Q_gate, QBAR_gate;
wire Q_data, QBAR_data;
wire Q_beh, QBAR_beh;
// FOR TESTING
reg TICK;
reg [31:0] VECTORCOUNT, ERRORS;
reg QEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (gate)
sr_latch_gate UUT_sr_latch_gate (
.s(S),
.r(R),
.q(Q_gate),
.qbar(QBAR_gate)
);
// UNIT UNDER TEST (dataflow)
sr_latch_dataflow UUT_sr_latch_dataflow (
.s(S),
.r(R),
.q(Q_data),
.qbar(QBAR_data)
);
// UNIT UNDER TEST (behavioral)
sr_latch_behavioral UUT_sr_latch_behavioral (
.s(S),
.r(R),
.q(Q_beh),
.qbar(QBAR_beh)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("sr_latch_tb.vcd");
$dumpvars(0, SR_LATCH_TB);
end
// TICK PERIOD
localparam TICKPERIOD = 20;
// TICK
always begin
#(TICKPERIOD / 2) TICK = ~TICK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD = $fopen("sr_latch_tb.tv", "r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b", COMMENT, S, R, QEXPECTED);
TICK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" GATE DATA BEH");
$display(" | TIME(ns) | S | R | Q | Q | Q |");
$display(" --------------------------------------");
// $monitor("%4d %10s | %8d | %1d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, S, R, Q_gate, Q_data, Q_beh);
end
// APPLY TEST VECTORS ON NEG EDGE TICK (ADD DELAY)
always @(negedge TICK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b", COMMENT, S, R, QEXPECTED);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE TICK
always @(posedge TICK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE CLK
$display("%4d %10s | %8d | %1d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time,
S, R, Q_gate, Q_data, Q_beh);
// CHECK EACH VECTOR RESULT
if (Q_gate !== QEXPECTED) begin
$display("***ERROR (gate) - Expected Q = %b", QEXPECTED);
ERRORS = ERRORS + 1;
end
if (Q_data !== QEXPECTED) begin
$display("***ERROR (dataflow) - Expected Q = %b", QEXPECTED);
ERRORS = ERRORS + 1;
end
if (Q_beh !== QEXPECTED) begin
$display("***ERROR (behavioral) - Expected Q = %b", QEXPECTED);
ERRORS = ERRORS + 1;
end
end
endmodule
| 7.332443 |
module Latch_with_control (
input S,
input C,
input R,
output Q,
output Qp
);
wire net1, net2;
nand (net1, S, C);
nand (net2, R, C);
Latch latch (
.S (net1),
.R (net2),
.Q (Q),
.Qp(Qp)
);
endmodule
| 7.201124 |
module SR_PIPO (
d,
clk,
reset,
outputs,
write_check
);
input [4:1] d;
input write_check;
input clk, reset;
wire w[3:1];
output [4:1] outputs;
assign w[1] = (write_check & d[1]) | ((~write_check) & outputs[1]);
assign w[2] = (write_check & d[2]) | ((~write_check) & outputs[2]);
assign w[3] = (write_check & d[3]) | ((~write_check) & outputs[3]);
DFF dff_1 (
d[1],
clk,
reset,
outputs[1]
);
DFF dff_2 (
w[1],
clk,
reset,
outputs[2]
);
DFF dff_3 (
w[2],
clk,
reset,
outputs[3]
);
DFF dff_4 (
w[3],
clk,
reset,
outputs[4]
);
endmodule
| 6.821383 |
module SR_PIPO_tb;
reg clk, reset, write;
wire [4:1] q;
reg [4:1] inp;
initial begin
$dumpfile("SR_PIPO_tb.vcd");
$dumpvars(0, SR_PIPO_tb);
end
SR_PIPO srPIPO (
inp,
clk,
reset,
q,
write
);
initial begin
reset = 0;
clk = 0;
write = 1;
inp = 4'b0000;
#5 write = 1;
inp = 4'b0010;
#5 write = 0;
inp = 4'b0001;
#5 write = 1;
inp = 4'b1010;
#5 write = 0;
inp = 4'b0000;
#5 write = 0;
inp = 4'b0110;
#5 write = 0;
inp = 4'b0001;
#5 write = 0;
inp = 4'b0010;
#5 write = 0;
inp = 4'b0000;
#5 write = 1;
inp = 4'b0010;
#5 write = 0;
inp = 4'b0001;
end
always #5 clk = !clk;
initial $monitor($time, ": clk=%b, rst=%b, inp=%b, q=%b\n", clk, reset, inp, q);
initial #100 $finish;
endmodule
| 6.806384 |
module SR_PISO (
d,
clk,
reset,
q,
write_check
);
input [4:1] d;
input write_check;
input clk, reset;
output q;
wire w[3:1];
wire outputs[3:1];
assign w[1] = (write_check & d[1]) | ((~write_check) & outputs[1]);
assign w[2] = (write_check & d[2]) | ((~write_check) & outputs[2]);
assign w[3] = (write_check & d[3]) | ((~write_check) & outputs[3]);
DFF dff_1 (
d[1],
clk,
reset,
outputs[1]
);
DFF dff_2 (
w[1],
clk,
reset,
outputs[2]
);
DFF dff_3 (
w[2],
clk,
reset,
outputs[3]
);
DFF dff_4 (
w[3],
clk,
reset,
q
);
endmodule
| 6.577162 |
module SR_SIPO (
d,
clk,
reset,
q
);
input d, clk, reset;
output [4:1] q;
DFF dff_1 (
d,
clk,
reset,
q[1]
);
DFF dff_2 (
q[1],
clk,
reset,
q[2]
);
DFF dff_3 (
q[2],
clk,
reset,
q[3]
);
DFF dff_4 (
q[3],
clk,
reset,
q[4]
);
endmodule
| 6.911472 |
module SR_SIPO_tb;
reg clk, reset;
wire [4:1] q;
reg inp;
initial begin
$dumpfile("SR_SIPO_tb.vcd");
$dumpvars(0, SR_SIPO_tb);
end
SR_SIPO srSIPO (
inp,
clk,
reset,
q
);
initial begin
inp = 0;
reset = 0;
clk = 0;
end
always @(negedge clk) inp = ~inp;
always #5 clk = !clk;
initial $monitor($time, ": clk=%b, rst=%b, inp=%b, q=%b\n", clk, reset, inp, q);
initial #100 $finish;
endmodule
| 6.994098 |
module SR_SISO (
d,
clk,
reset,
q
);
input d, clk, reset;
output q;
wire w1, w2, w3;
DFF dff_1 (
d,
clk,
reset,
w1
);
DFF dff_2 (
w1,
clk,
reset,
w2
);
DFF dff_3 (
w2,
clk,
reset,
w3
);
DFF dff_4 (
w3,
clk,
reset,
q
);
endmodule
| 6.588085 |
module SR_SISO_tb;
reg clk, reset;
wire q;
reg inp;
initial begin
$dumpfile("SR_SISO_tb.vcd");
$dumpvars(0, SR_SISO_tb);
end
SR_SISO srsiso (
inp,
clk,
reset,
q
);
initial begin
inp = 0;
reset = 0;
clk = 0;
end
always @(negedge clk) inp = ~inp;
always #5 clk = !clk;
initial $monitor($time, ": clk=%b, rst=%b, inp=%b, q=%b\n", clk, reset, inp, q);
initial #100 $finish;
endmodule
| 6.644447 |
module SR_tb;
reg clk, reset, x;
wire [3:0] out;
SR u_SR (
.clk(clk),
.reset(reset),
.x(x),
.out(out)
);
initial clk = 1'b0;
initial reset = 1'b1;
initial x = 1'b0;
always clk = #20 ~clk;
always @(reset) begin
reset = #30 ~reset;
end
always @(x) begin
x = #50 ~x;
x = #20 ~x;
x = #60 ~x;
x = #20 ~x;
x = #20 ~x;
x = #20 ~x;
end
initial begin
#380 $finish;
end
endmodule
| 6.532249 |
module ssb_out (
input clk,
input [ 1:0] div_state, // div_state [0] I-Q signal
input signed [17:0] drive, // Baseband interleaved I-Q
input enable, // Set output on enable else 0
input ssb_flip, // Flips sign of dac2_out output pair
input [15:0] aftb_coeff, // Coefficient to correct for the linear interpolation between
// two consecutive samples; see afterburner.v for details.
// Example based on FNAL test:
// 1313 MHz LO as timebase, / 16 to get 82.0625 MHz ADC clk
// IF is 13 MHz, 16/101 = 0.1584 of ADC clk
// aftb_coeff = ceil(32768*0.5*sec(2*pi*16/101/2)) = 18646
// local oscillator
input signed [17:0] cosa,
input signed [17:0] sina,
// DDR on both DACs
output signed [15:0] dac1_out0, // Nominally in-phase component
output signed [15:0] dac1_out1,
output signed [15:0] dac2_out0, // Nominally quadrature component
output signed [15:0] dac2_out1
);
wire iq = div_state[0];
// Bring input I and Q to full data rate
wire signed [16:0] drive_i, drive_q;
fiq_interp interp (
.clk(clk),
.a_data(drive[17:2]),
.a_gate(1'b1),
.a_trig(iq),
.i_data(drive_i),
.q_data(drive_q)
);
wire signed [15:0] out1, out2;
// SSB modulation scheme (Hartley modulator) using dot-product for LSB selection:
// (I, Q) . (cos(wLO*t), sin(wLO*t)) = I*cos(wLO*t) + Q*sin(wLO*t)
// In-phase portion of SSB drive signal
flevel_set level1 (
.clk(clk),
.cosd(cosa),
.sind(sina),
.i_data(drive_i),
.i_gate(1'b1),
.i_trig(1'b1),
.q_data(drive_q),
.q_gate(1'b1),
.q_trig(1'b1),
.o_data(out1)
);
wire signed [15:0] outk1 = enable ? out1 : 0;
wire [15:0] dac1_ob0, dac1_ob1; // offset binary outputs from afterburner
afterburner afterburner1 (
.clk(clk),
.data({outk1, 1'b0}),
.coeff(aftb_coeff),
.data_out0(dac1_ob0),
.data_out1(dac1_ob1)
);
// Second (optional) dot-product with 90deg-rotated drive IQ to obtain quadrature component
// Quadrature portion of SSB drive signal
flevel_set level2 (
.clk(clk),
.cosd(cosa),
.sind(sina),
.i_data(~drive_q),
.i_gate(1'b1),
.i_trig(1'b1),
.q_data(drive_i),
.q_gate(1'b1),
.q_trig(1'b1),
.o_data(out2)
);
wire signed [15:0] outf2 = ssb_flip ? ~out2 : out2;
wire signed [15:0] outk2 = enable ? outf2 : 0;
wire [15:0] dac2_ob0, dac2_ob1; // offset binary outputs from afterburner
afterburner afterburner2 (
.clk(clk),
.data({outk2, 1'b0}),
.coeff(aftb_coeff),
.data_out0(dac2_ob0),
.data_out1(dac2_ob1)
);
// afterburner returns offset-binary DAC words, but this module uses signed
// (twos-complement) for its output. Thus the conversions below.
assign dac1_out0 = {~dac1_ob0[15], dac1_ob0[14:0]};
assign dac1_out1 = {~dac1_ob1[15], dac1_ob1[14:0]};
assign dac2_out0 = {~dac2_ob0[15], dac2_ob0[14:0]};
assign dac2_out1 = {~dac2_ob1[15], dac2_ob1[14:0]};
endmodule
| 8.185139 |
module seven (
input clk,
input [12:0] num,
output reg [3:0] Anode,
output reg [6:0] LED_out
);
//assign num =13'd1234;
reg [ 3:0] LED_BCD;
reg [19:0] refresh_counter = 0;
wire [ 1:0] LED_activating_counter;
always @(posedge clk) begin
refresh_counter <= refresh_counter + 1;
end
assign LED_activating_counter = refresh_counter[19:18];
always @(*) begin
case (LED_activating_counter)
2'b00: begin
Anode = 4'b0111;
LED_BCD = num / 1000;
end
2'b01: begin
Anode = 4'b1011;
LED_BCD = (num % 1000) / 100;
end
2'b10: begin
Anode = 4'b1101;
LED_BCD = ((num % 1000) % 100) / 10;
end
2'b11: begin
Anode = 4'b1110;
LED_BCD = ((num % 1000) % 100) % 10;
end
endcase
end
always @(*) begin
case (LED_BCD)
4'b0000: LED_out = 7'b0000001;
4'b0001: LED_out = 7'b1001111;
4'b0010: LED_out = 7'b0010010;
4'b0011: LED_out = 7'b0000110;
4'b0100: LED_out = 7'b1001100;
4'b0101: LED_out = 7'b0100100;
4'b0110: LED_out = 7'b0100000;
4'b0111: LED_out = 7'b0001111;
4'b1000: LED_out = 7'b0000000;
4'b1001: LED_out = 7'b0000100;
default: LED_out = 7'b0000001;
endcase
end
endmodule
| 7.224734 |
module seven (
input clk,
input [12:0] num,
output reg [3:0] Anode,
output reg [6:0] LED_out
);
//assign num =13'd1234;
reg [ 3:0] LED_BCD;
reg [19:0] refresh_counter = 0;
wire [ 1:0] LED_activating_counter;
always @(posedge clk) begin
refresh_counter <= refresh_counter + 1;
end
assign LED_activating_counter = refresh_counter[19:18];
always @(*) begin
case (LED_activating_counter)
2'b00: begin
Anode = 4'b0111;
LED_BCD = num / 1000;
end
2'b01: begin
Anode = 4'b1011;
LED_BCD = (num % 1000) / 100;
end
2'b10: begin
Anode = 4'b1101;
LED_BCD = ((num % 1000) % 100) / 10;
end
2'b11: begin
Anode = 4'b1110;
LED_BCD = ((num % 1000) % 100) % 10;
end
endcase
end
always @(*) begin
case (LED_BCD)
4'b0000: LED_out = 7'b0000001;
4'b0001: LED_out = 7'b1001111;
4'b0010: LED_out = 7'b0010010;
4'b0011: LED_out = 7'b0000110;
4'b0100: LED_out = 7'b1001100;
4'b0101: LED_out = 7'b0100100;
4'b0110: LED_out = 7'b0100000;
4'b0111: LED_out = 7'b0001111;
4'b1000: LED_out = 7'b0000000;
4'b1001: LED_out = 7'b0000100;
default: LED_out = 7'b0000001;
endcase
end
endmodule
| 7.224734 |
module SSD1306_ROM_cfg_mod (
input [`BLOCK_ROM_INIT_ADDR_WIDTH-1:0] addr,
output [`BLOCK_ROM_INIT_DATA_WIDTH-1:0] dout
);
parameter FILENAME = "SSD1306_ROM_script.mem";
localparam LENGTH = 2 ** `BLOCK_ROM_INIT_ADDR_WIDTH;
reg [`BLOCK_ROM_INIT_DATA_WIDTH-1:0] mem[LENGTH-1:0];
initial $readmemh(FILENAME, mem);
assign dout = mem[addr];
endmodule
| 7.296122 |
module ssd1780 (
input CLK
, input [7:0] CMD_DAT
, inout SDA
, output SCL
, input START
, input ASYNC_RST_L
, output BUSY
, output RUNNING
);
reg start;
reg [1:0] busy_mask;
wire i2c_busy;
wire addr_sent;
assign BUSY = RUNNING & (i2c_busy | ~busy_mask[1]);
i2c_master i2c (
CLK,
SDA,
SCL,
i2c_busy,
RUNNING,
START,
1'b0,
addr_sent,
ASYNC_RST_L,
CMD_DAT,
8'h78
);
always @(negedge CLK or negedge ASYNC_RST_L) begin
if (!ASYNC_RST_L) begin
start <= 0;
busy_mask <= 0;
end else begin
start <= START;
if (RUNNING) begin
if (!i2c_busy && !busy_mask[1]) busy_mask <= busy_mask + 1'b1;
end else begin
if (!start && START) busy_mask <= 0;
end
end
end
endmodule
| 6.946914 |
module SSD4ScanDriver (
input CLK,
input [19:0] INPUT,
output [7:0] OUTPUT_SEG,
output reg [3:0] OUTPUT_SEL
);
wire [31:0] MUX_INPUT;
reg [ 1:0] count = 2'b0;
MUX mux0 (
.CLK(CLK),
.INPUT(MUX_INPUT),
.OUTPUT(OUTPUT_SEG)
);
SSDDigitDriver drv0 (
.INPUT_NUM (INPUT[3:0]),
.DIGITPOINT(INPUT[4]),
.SSD_OUTPUT(MUX_INPUT[7:0])
);
SSDDigitDriver drv1 (
.INPUT_NUM (INPUT[8:5]),
.DIGITPOINT(INPUT[9]),
.SSD_OUTPUT(MUX_INPUT[15:8])
);
SSDDigitDriver drv2 (
.INPUT_NUM (INPUT[13:10]),
.DIGITPOINT(INPUT[14]),
.SSD_OUTPUT(MUX_INPUT[23:16])
);
SSDDigitDriver drv3 (
.INPUT_NUM (INPUT[18:15]),
.DIGITPOINT(INPUT[19]),
.SSD_OUTPUT(MUX_INPUT[31:24])
);
always @(posedge CLK) begin
case (count)
2'd0: OUTPUT_SEL <= 4'b1110;
2'd1: OUTPUT_SEL <= 4'b1101;
2'd2: OUTPUT_SEL <= 4'b1011;
2'd3: OUTPUT_SEL <= 4'b0111;
endcase
count = count + 1;
end
endmodule
| 6.778657 |
module SSDDigitDriver (
input [3:0] INPUT_NUM,
input DIGITPOINT,
output reg [7:0] SSD_OUTPUT
);
reg [6:0] SSD_Charmap[0:15];
integer value;
initial $readmemb("SSD_Charmap.mem", SSD_Charmap);
always @(INPUT_NUM) begin
value = INPUT_NUM;
SSD_OUTPUT <= {DIGITPOINT, SSD_Charmap[value]};
end
endmodule
| 6.882329 |
module SSDecoder (
c,
ss
);
input [3:0] c;
output reg [6:0] ss;
//Declare input and output.
always @(c)
case (c)
4'b0000: ss[6:0] = 7'b1000000;
4'b0001: ss[6:0] = 7'b1111001;
4'b0010: ss[6:0] = 7'b0100100;
4'b0011: ss[6:0] = 7'b0110000;
4'b0100: ss[6:0] = 7'b0011001;
4'b0101: ss[6:0] = 7'b0010010;
4'b0110: ss[6:0] = 7'b0000010;
4'b0111: ss[6:0] = 7'b1111000;
4'b1000: ss[6:0] = 7'b0000000;
4'b1001: ss[6:0] = 7'b0010000;
default: ss[6:0] = 7'b1000000;
endcase
//Cases for 0-9, default to 0.
endmodule
| 7.013451 |
module ssdhex (
input wire Clk,
input wire Reset,
input wire [3:0] SSD0,
input wire [3:0] SSD1,
input wire [3:0] SSD2,
input wire [3:0] SSD3,
input wire Active,
output wire [3:0] Enables,
output reg [7:0] Cathodes
);
wire [ 1:0] ssdscan_clk;
reg [26:0] DIV_CLK;
reg [ 3:0] SSD;
// Clock division
always @(posedge Clk, posedge Reset) begin : CLOCK_DIVIDER
if (Reset) DIV_CLK <= 0;
else
// just incrementing makes our life easier
DIV_CLK <= DIV_CLK + 1'b1;
end
assign ssdscan_clk = DIV_CLK[18:17];
assign An0 = !(~(ssdscan_clk[1]) && ~(ssdscan_clk[0])); // when ssdscan_clk = 00
assign An1 = !(~(ssdscan_clk[1]) && (ssdscan_clk[0])); // when ssdscan_clk = 01
assign An2 = !((ssdscan_clk[1]) && ~(ssdscan_clk[0])); // when ssdscan_clk = 10
assign An3 = !((ssdscan_clk[1]) && (ssdscan_clk[0])); // when ssdscan_clk = 11
assign Enables = {An3, An2, An1, An0};
always @(ssdscan_clk, SSD0, SSD1, SSD2, SSD3) begin : SSD_SCAN_OUT
case (ssdscan_clk)
2'b00: SSD = SSD0;
2'b01: SSD = SSD1;
2'b10: SSD = SSD2;
2'b11: SSD = SSD3;
endcase
end
// Following is Hex-to-SSD conversion
always @(SSD) begin : HEX_TO_SSD
if (Active) begin
case (SSD) // in this solution file the dot points are made to glow by making Dp = 0
4'b0000: Cathodes = 8'b00000011; // 0
4'b0001: Cathodes = 8'b10011111; // 1
4'b0010: Cathodes = 8'b00100101; // 2
4'b0011: Cathodes = 8'b00001101; // 3
4'b0100: Cathodes = 8'b10011001; // 4
4'b0101: Cathodes = 8'b01001001; // 5
4'b0110: Cathodes = 8'b01000001; // 6
4'b0111: Cathodes = 8'b00011111; // 7
4'b1000: Cathodes = 8'b00000001; // 8
4'b1001: Cathodes = 8'b00001001; // 9
4'b1010: Cathodes = 8'b00010000; // A
4'b1011: Cathodes = 8'b11000000; // B
4'b1100: Cathodes = 8'b01100010; // C
4'b1101: Cathodes = 8'b10000100; // D
4'b1110: Cathodes = 8'b01100000; // E
4'b1111: Cathodes = 8'b01110000; // F
default: Cathodes = 8'bXXXXXXXX; // default is not needed as we covered all cases
endcase
end else Cathodes = 8'b11111111;
end
endmodule
| 7.303008 |
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