code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module SRA_2 (
shiftA,
A
);
input [64:0] A;
output [64:0] shiftA;
assign shiftA[62:0] = A[64:2];
assign shiftA[63] = A[64];
assign shiftA[64] = A[64];
endmodule
| 6.647093 |
module sra_control_ID_EX_stage (
input signal_sra,
input clock,
output reg out_sra_control_reg
);
always @(posedge clock) out_sra_control_reg = signal_sra;
endmodule
| 6.694562 |
module sra_module_testbench ();
reg [31:0] inp;
wire [31:0] outfifth;
reg select1, select2, select3, select4, select5;
sra_module call (
outfifth,
inp,
select1,
select2,
select3,
select4,
select5
);
initial begin
inp = 32'b11111111111111111111111111111110;
... | 6.619815 |
module sra_srl (
funct7,
datain_A,
datain_B,
out
);
parameter WIRE = 32;
input [WIRE-1:0] datain_A, datain_B;
input funct7;
output [WIRE-1:0] out;
assign out = funct7 ? {1'b1, (datain_A[WIRE-2:0] >> datain_B[5:0])} : datain_A >> datain_B[5:0];
endmodule
| 6.669447 |
module
module src2dest#(
parameter DATAWIDTH = 8
)
(
input src_CLK ,
input dest_CLK ,
input RSTn ,
input [ DATAWIDTH - 1 : 0 ] src_data_in ,
output [ DATAWIDTH - 1 : 0 ] dest_data_out ,
output src_data_valid ,
output dest_data_valid
);
wire [ DATAWIDTH - 1 : 0 ... | 7.342644 |
module srcA (
input [`ICODEBUS] icode,
input [ `REGBUS] rA,
output [ `REGBUS] d_srcA
);
assign d_srcA= (icode == `IRRMOVQ |icode == `IRMMOVQ | icode == `IOPQ |icode == `IPUSHQ )?rA:
(icode == `IRET | icode == `IPOPQ ) ? `RRSP:
`RNONE;
endmodule
| 6.810107 |
module src_a_mux (
input wire [`SRC_A_SEL_WIDTH-1:0] src_a_sel,
input wire [ `ADDR_LEN-1:0] pc,
input wire [ `DATA_LEN-1:0] rs1,
output reg [ `DATA_LEN-1:0] alu_src_a
);
always @(*) begin
case (src_a_sel)
`SRC_A_RS1: alu_src_a = rs1;
`SRC_A_PC: alu_src_a = pc;
... | 8.370023 |
module src_b_mux (
input wire [`SRC_B_SEL_WIDTH-1:0] src_b_sel,
input wire [ `DATA_LEN-1:0] imm,
input wire [ `DATA_LEN-1:0] rs2,
output reg [ `DATA_LEN-1:0] alu_src_b
);
always @(*) begin
case (src_b_sel)
`SRC_B_RS2: alu_src_b = rs2;
`SRC_B_IMM: alu_src_b = imm... | 7.757127 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module src_a_mux (
// from controller
input [31 : 0] pc,
// from regfile
input [31 : 0] rs1_data,
// from decoder
input [31 : 0] imm,
input [`SEL_SRC_A_WIDTH - 1 : 0] select,
// to alu
output reg [31 : 0] alu_src_a
);
always @(*) begin
case (select)
`SEL_SRC_A_PC: alu_s... | 8.370023 |
module src_b_mux (
// from regfile
input [31 : 0] rs2_data,
// from decoder
input [31 : 0] imm,
input [`SEL_SRC_B_WIDTH - 1 : 0] select,
// to alu
output reg [31 : 0] alu_src_b
);
always @(*) begin
case (select)
`SEL_SRC_B_RS2: alu_src_b = rs2_data;
`SEL_SRC_B_IMM: alu_sr... | 7.757127 |
module src_domain #(
parameter DATAWIDTH = 8
) (
input CLK,
input RSTn,
input [DATAWIDTH - 1 : 0] src_data_in,
output reg [DATAWIDTH - 1 : 0] src2dest_data,
output reg src2dest_load,
output reg src... | 8.092851 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module SRC_imm_MUX (
instr,
src1sel,
l_sw,
en,
imm_src1
); //selet immdiate value if lw/sw/jal encoutered
input [7:0] instr;
input src1sel, l_sw;
output en;
output [15:0] imm_src1;
wire [15:0] s1, s2;
assign en = (src1sel || l_sw);
assign s1 = {{8{instr[7]}}, instr[7:0]};
assign s2 ... | 6.515118 |
module src_manager (
input wire [`DATA_LEN-1:0] opr,
input wire opr_rdy,
input wire [`DATA_LEN-1:0] exrslt1,
input wire [ `RRF_SEL-1:0] exdst1,
input wire kill_spec1,
input wire [`DATA_LEN-1:0] exrslt2,
input wire [ `RRF_SEL-1:0] exdst2,
input wire... | 6.961538 |
module src_min (
input clk,
input rst_n,
//ǰ
input pre_frame_vsync,
input pre_frame_href,
input pre_frame_clken,
input [ 23:0] pre_img,
//
output post_frame_vsync,
output post_frame_href,
output post_frame_... | 7.003508 |
module src_mux (
clk,
stall_ID_EX,
stall_EX_DM,
src0sel_ID_EX,
src1sel_ID_EX,
p0,
p1,
imm_ID_EX,
pc_ID_EX,
p0_EX_DM,
src0,
src1,
dst_EX_DM,
dst_DM_WB,
byp0_EX,
byp0_DM,
byp1_EX,
byp1_DM
);
input clk;
input stall_ID_EX, stall_EX_DM; // stall s... | 7.908347 |
module src_shift_reg (
source1_data,
source2_data,
source3_data,
source_vcc_value,
source_exec_value,
src_buffer_wr_en,
src_buffer_shift_en,
alu_source1_data,
alu_source2_data,
alu_source3_data,
alu_source_vcc_value,
alu_source_exec_value,
clk,
rst
);
input [20... | 7.950969 |
module sReg (
output reg [15:0] DataOut,
input [2:0] Addr,
input Clk1,
input Clk2,
input [15:0] DataIn,
input RD,
input WR,
input WR_l,
input WR_h
);
reg [15:0] scalar [7:0];
reg [ 2:0] address;
wire [ 3:0] cmd;
parameter read = 4'b1000, write = 4'b0100, wr_low = 4'b0010,... | 7.974086 |
module sreg8 (
output reg [7:0] Q,
input ShiftIn,
input Enable,
input Clock,
input nReset
);
reg [7:0] Qr;
// Calculo asncrono de registro auxiliar Qr
always @(Q, ShiftIn, Enable) begin
Qr = Q;
if (Enable == 1) Qr = {ShiftIn, Q[7:1]};
end
// Reset y asignacin de Qr con clock
a... | 6.950812 |
module sreg_10 (
clk,
load,
data,
en,
q
);
input clk;
input load;
input [9:0] data;
input en;
output q;
// IO regs
reg [9:0] sreg;
always @(posedge clk) begin
if (load) sreg <= data;
else if (en) sreg <= {sreg[8:0], 1'b0};
end
assign q = sreg[9];
endmodule
| 6.903676 |
module sreg_block (
// configuration
input [12:0] addr_base,
// The FPGA internal I/O bus
input clk,
input [12:0] iADDR, // I/O address
input iBS7, // address is on the I/O page
output iREAD_MATCH, // this device will read that address
output iWRITE_MATCH, // this device will write ... | 7.500528 |
module sreg_file (
clk,
r_addr,
data_out
);
parameter addr_w = 4, data_w = 8;
input clk;
input [addr_w-1:0] r_addr;
output reg [data_w-1:0] data_out;
reg [data_w-1:0] sregfile[2**addr_w-1:0];
initial begin
$readmemb("sreg_file_init.txt", sregfile);
end
always @(posedge clk) begin
... | 7.304686 |
module test_jbimu;
// Inputs
reg clks;
reg clock;
reg reset;
reg start;
wire miso;
// Outputs
wire [15:0] roll;
wire [15:0] pitch;
wire [15:0] yaw;
wire [15:0] roll_rate;
wire [15:0] pitch_rate;
wire [15:0] yaw_rate;
wire [15:0] accel_x;
wire [15:0] accel_y;
wire [15:0] accel_z;
wire done;
wire mosi;
wire sck;
wire ss;... | 6.632599 |
modules
#-- Copyright (c) 1995-2008 by Xilinx, Inc. All rights reserved.
#-- This text/file contains proprietary, confidential
#-- information of Xilinx, Inc., is distributed under license
#-- from Xilinx, Inc., and may be used, copied and/or
#-- disclosed only pursuant to the terms of a valid license
#-- agreement wi... | 7.855861 |
module srl #(
parameter WIDTH = 18
) (
input clk,
input write,
input [WIDTH-1:0] in,
input [3:0] addr,
output [WIDTH-1:0] out
);
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : gen_srl
SRL16E srl16e (
.Q (out[i]),
.A0 (addr[0]),
.A1 (add... | 7.644441 |
module SRL1 (
input [1:0] in
, output out
);
parameter NUM_GATES = 2;
wire [NUM_GATES - 1:0] LW;
wire [NUM_GATES - 1:0] w;
genvar i;
generate
for (i = 0; i < NUM_GATES; i++) begin : L
LCELL lcell_inst (
.in (LW[i])
, .out(w[i])
);
end
endgenerate
nor (... | 6.697605 |
module srl16e_bbl (
clock,
ce,
adr,
d,
q
);
// Generic
parameter WIDTH = 19;
initial $display("srl16e_bbl: WIDTH=%d", WIDTH);
// Ports
input clock;
input ce;
input [3:0] adr;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
// Generate MXSRL instances of SRL16E
genvar i;
generat... | 7.422285 |
module srl16e_bit (
clock,
adr,
d,
q
);
//-------------------------------------------------------------------------------------------------------------------
// Generics caller may override
//---------------------------------------------------------------------------------------------------------... | 7.708922 |
module srl16e_fifo #(
parameter c_width = 8,
c_awidth = 4,
c_depth = 16
) (
input Clk, // Main System Clock (Sync FIFO)
input Rst, // FIFO Counter Reset (Clk
input WR_EN, // FIFO Write Enable (Clk)
input RD_EN, // FIFO Rea... | 7.171691 |
module srl16e_fifo_protect #(
parameter c_width = 8,
c_awidth = 4,
c_depth = 16
) (
input Clk, // Main System Clock (Sync FIFO)
input Rst, // FIFO Counter Reset (Clk
input WR_EN, // FIFO Write Enable (Clk)
input ... | 7.156099 |
module srl2_32 (
in,
out
);
input signed [31:0] in;
output signed [31:0] out;
assign out = in >>> 1;
endmodule
| 7.611714 |
module srl32 (
input [31:0] A,
input [31:0] B,
output [31:0] res
);
assign res = A >> B[10:6];
endmodule
| 7.07749 |
module SRL32E #(
parameter [31:0] INIT = 32'h0,
parameter [0:0] IS_CLK_INVERTED = 1'b0
) (
// Clock
input wire CLK,
// Clock enable
input wire CE,
// Bit output position
input wire [4:0] A,
// Data in
input wire D,
// Data out
output wire Q
);
... | 7.202101 |
module srl32x4e (
y,
d,
a,
ce,
clk
);
output [3:0] y; // output selected by address
input [3:0] d; // input word
input [4:0] a; // address of output word
input ce; // enable input
input clk; // clock input
// 4 32-bit shift registers
SRLC32E sr0 (
.D (d[0]),
.A (a),
... | 6.802363 |
module SRL64E (
Q,
D,
A,
CE,
CLK
);
output Q;
input D;
input [5:0] A;
input CE;
input CLK;
// 2 shift registers and 1 multiplexer
wire q31; // inter-SRLC32E bit
wire qa, qb; // SRLC32E outputs
SRLC32E sr0 (
.D (D),
.A (A[4:0]),
.Q (qa),
.Q31(q31),
... | 7.055696 |
module Srlatch (
input wire S,
R,
output wire Q,
Q_not
);
assign Q = ~(R | Q_not);
assign Q_not = ~(S | Q);
endmodule
| 7.860565 |
module SRlatchnand (
input S,
R,
CLK,
output Q
);
wire i, k, y;
assign #(7) i = (S | ~CLK);
assign #(7) k = (R | ~CLK);
assign #(7) Q = ~(i & y);
assign #(7) y = ~(Q & k);
endmodule
| 6.603362 |
module SRLC16 (
Q,
Q15,
A0,
A1,
A2,
A3,
CLK,
D
);
parameter INIT = 16'h0000;
output Q, Q15;
input A0, A1, A2, A3, CLK, D;
reg [15:0] data;
wire [3:0] addr;
wire q_int;
wire q15_int;
buf b_a3 (addr[3], A3);
buf b_a2 (addr[2], A2);
buf b_a1 (addr[1], A1);
buf b_a... | 6.770168 |
module SRLC16E (
Q,
Q15,
A0,
A1,
A2,
A3,
CE,
CLK,
D
);
parameter INIT = 16'h0000;
output Q, Q15;
input A0, A1, A2, A3, CE, CLK, D;
reg [15:0] data;
wire [3:0] addr;
wire q_int;
wire q15_int;
buf b_a3 (addr[3], A3);
buf b_a2 (addr[2], A2);
buf b_a1 (addr[1], A... | 6.802804 |
module SRLC16E_1 (
Q,
Q15,
A0,
A1,
A2,
A3,
CE,
CLK,
D
);
parameter INIT = 16'h0000;
output Q, Q15;
input A0, A1, A2, A3, CE, CLK, D;
reg [15:0] data;
wire [3:0] addr;
wire clk_;
wire q_int;
wire q15_int;
buf b_a3 (addr[3], A3);
buf b_a2 (addr[2], A2);
buf b... | 6.554028 |
module SRLC16_1 (
Q,
Q15,
A0,
A1,
A2,
A3,
CLK,
D
);
parameter INIT = 16'h0000;
output Q, Q15;
input A0, A1, A2, A3, CLK, D;
reg [15:0] data;
wire [3:0] addr;
wire clk_;
wire q_int;
wire q15_int;
buf b_a3 (addr[3], A3);
buf b_a2 (addr[2], A2);
buf b_a1 (addr[1],... | 6.699982 |
module SRLC32E (
Q,
Q31,
A,
CE,
CLK,
D
);
parameter INIT = 32'h00000000;
output Q;
output Q31;
input [4:0] A;
input CE, CLK, D;
reg [31:0] data;
assign Q = data[A];
assign Q31 = data[31];
initial begin
assign data = INIT;
while (CLK === 1'b1 || CLK === 1'bX) #1... | 7.008473 |
module SRLNXE #(
WIDTH = 32,
DEPTH = 128
) (
input wire clk,
input wire [$clog2(DEPTH)-1:0] addr,
input wire wen,
input wire [WIDTH-1:0] data_i,
output wire [WIDTH-1:0] data_o
);
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : gen_srlnxE
SRLXE #(
.DEPT... | 7.971678 |
module SRLXE #(
DEPTH = 128
) (
input wire clk,
input wire [$clog2(DEPTH)-1:0] addr,
input wire wen,
input wire data_i,
output wire data_o
);
reg [DEPTH-1:0] mem;
// Data is latched on the positive edge of the clock
always @(posedge clk) if (wen) mem[DEPTH-1:0] <= {mem[DEPTH-2:0], data... | 6.926966 |
module srl_cam_32x32 (
clk,
cmp_data_mask,
cmp_din,
data_mask,
din,
we,
wr_addr,
busy,
match,
match_addr
);
input clk;
input [31 : 0] cmp_data_mask;
input [31 : 0] cmp_din;
input [31 : 0] data_mask;
input [31 : 0] din;
input we;
input [4 : 0] wr_addr;
output bus... | 7.031469 |
module srl_cam_64x32 (
clk,
cmp_data_mask,
cmp_din,
data_mask,
din,
we,
wr_addr,
busy,
match,
match_addr
);
input clk;
input [31 : 0] cmp_data_mask;
input [31 : 0] cmp_din;
input [31 : 0] data_mask;
input [31 : 0] din;
input we;
input [5 : 0] wr_addr;
output bus... | 7.594453 |
module srl_fifo #(
parameter WIDTH = 1,
parameter DEPTH_LOG = 3,
parameter FALLTHROUGH = "true"
) (
input clock,
input reset,
input push,
input [WIDTH-1:0] din,
output full,
input pop,
output reg [WIDTH-1:0] dout,
output empty
);
//check parameter sanity
initial begin
... | 6.896375 |
module srl_macro (
clk,
ce,
din,
dout
);
input clk;
input ce;
input [`DATA_WIDTH*2-1:0] din;
output [`DATA_WIDTH*2-1:0] dout;
//reg [`DATA_WIDTH*2-1:0] dout;
//wire [`DATA_WIDTH*2-1:0] srl_out;
// SRLC32E: 32-Bit Shift Register Look-Up Table (LUT)
parameter A = 5'b11111;
genvar i;
... | 6.91484 |
module srmul (
input wire [31:0] a,
input wire [31:0] b,
output wire [31:0] z
);
// SP floating point fields
`define sign 31
`define exponent 30:23
`define mantissa 22:0
// various other constants
`define zero 32'b0
`define NaN 32'hFFFFFFFF
//////////////////////////////////////////////... | 7.230632 |
module SRAM_4096x128_wrapper (
// Global inputs
input CK, // Clock (synchronous read/write)
input [1:0] SM, // Speed mode
// Control and data inputs
input CS, // Chip select (active high)
input WE, // Write enable (active high)
input [ 11:0] A, // Address bus
... | 7.030444 |
module SRAM_512x128_wrapper (
// Global inputs
input CK, // Clock (synchronous read/write)
input [1:0] SM, // Speed mode
// Control and data inputs
input CS, // Chip select (active high)
input WE, // Write enable (active high)
input [ 8:0] A, // Address bus
... | 7.124347 |
module SRAM_128x128_wrapper (
// Global inputs
input CK, // Clock (synchronous read/write)
input [1:0] SM, // Speed mode
// Control and data inputs
input CS, // Chip select (active high)
input WE, // Write enable (active high)
input [ 6:0] A, // Address bus
... | 6.883647 |
module output_act_err (
input wire en,
input wire regr,
input wire act,
input wire label,
input wire signed [15:0] target,
input wire signed [15:0] vo,
output wire signed [15:0] e
);
reg signed [15:0] yt;
reg signed [15:0] y... | 8.045176 |
module stoch_update #(
parameter WIDTH_IN = 16,
parameter LR_IN = 4
) (
input wire signed [WIDTH_IN-1:0] prob,
input wire signed [ 7:0] w_in,
input wire en,
input wire [ LR_IN-1:0] lr_r,
input wire [ LR_IN-1:0] lr_p,
input wire ... | 6.646789 |
module.
//
// -----------------------------History-----------------------------------//
// Date BY Version Change Description
//
// 20200101 PODES 1.0 Initial Release.
// Use SRAM replace the SROM in FPGA, so that program code
// can be downloaded ... | 6.769864 |
module srrc_filter #(
parameter DATA_IN_WIDTH = 16,
parameter DATA_OUT_WIDTH = 16,
parameter PATH_DATA_WIDTH = 24
) (
input clk_in,
input [DATA_IN_WIDTH-1:0] data_in_I,
input [DATA_IN_WIDTH-1:0] data_in_Q,
input data_in_valid,
output data_in_ready,
output [DATA_OUT_WIDTH-1:0] data... | 8.122411 |
module SRSG #(
parameter n = 8
) (
clk,
rst,
en,
poly,
seed,
Sout
);
input clk, rst, en;
input [n - 1:0] seed;
input [n - 1:0] poly;
output Sout;
reg [n - 1:0] data;
integer i;
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) data = seed;
else if (en == 1'b... | 6.970692 |
module SRSystem_DL (
pd,
d,
Q
);
input wire pd;
input wire [7:0] d;
output reg [7:0] Q;
always @(posedge pd) Q <= d;
endmodule
| 7.313147 |
module SRSystem_Parity (
qst,
q,
opn,
qsp,
P
);
input wire qst, opn, qsp;
input wire [7:0] q;
output wire P;
assign P = qst ^ opn ^ q[0] ^ q[1] ^ q[2] ^ q[3] ^ q[4] ^ q[5] ^ q[6] ^ q[7] ^ qsp;
endmodule
| 7.391556 |
module SRTSystem_TD (
clk,
send,
rst,
d,
en,
ERR,
Q,
extra_ack
); //extra_ack
input wire clk, send, rst, en;
input wire [0:7] d;
output wire ERR;
output wire [0:7] Q;
output wire [0:1] extra_ack; //extra
wire stsack, srsack, dry, rts, tx, pd;
STSystem_TD STSystem (
... | 6.596584 |
module SRTSystem_testbench();
reg clk,send,rst;
reg [0:7] d;
wire ERR;
wire [0:7]Q;
wire [0:1] extra_ack; //extra
SRTSystem_TD SRTS_testbench(.clk(clk), .send(send), .rst(rst), .d(d), .en(1'b1), .ERR(ERR), .Q(Q), .extra_ack(extra_ack));//extra
reg [0:7] Mem [0:29];
reg [7:0]counter;
initial
begin
clk=0;
send=0;
rst=... | 7.001608 |
module srt_corr_top (
input sys_clk_in,
input sys_rst,
input uart_rx,
input start_button,
input adc_dav_1,
input adc_dav_2,
input [1:0] delay_sel,
input [15:0] data_in_1,
input [15:0] data_in_2,
// DEBUG PINS -- TO BE REMOVED
output done,
output failure,
//
... | 7.10729 |
module SRT_tb ();
reg [3:0] x0, x1, x2, x3;
reg clk, rst;
wire [3:0] s0, s1, s2, s3;
wire done;
SRT DUT (
.x0 (x0),
.x1 (x1),
.x2 (x2),
.x3 (x3),
.clk (clk),
.rst (rst),
.s0 (s0),
.s1 (s1),
.s2 (s2),
.s3 (s3),
.done(done)
);
integ... | 6.710606 |
module sru_dcscmd_par (
input dcs_rx_clk,
input [7:0] dcs_rxd,
input dcs_rx_dv,
input gclk_40m,
output reg udp_cmd_dv = 1'b0,
output reg [31:0] udp_cmd_addr = 32'h0,
output reg [31:0] udp_cmd_data = 32'h0,
input udp_reply_stored,
input reset
);
re... | 7.424978 |
module sru_dcs_fifo (
input gclk_40m,
input dcs_rx_clk,
input [7:0] dcs_rxd,
input dcs_rx_dv,
//DCS rx_fifo read interface
input dcs_rd_clk, //40MHz
output dcs_rd_sof_n,
output [ 7:0] dcs_rd_data_out,
output dcs_rd_eof_n,
output ... | 7.454628 |
module is a 128-bit shift register. It works the same way as the provided code
// for a 4-bit shift register, but is now extended to 128 bits.
// Purpose: A 128-bit shift register is needed to whole important key and message encryption values
// The module is instantiated in AES.sv
module SR_128b (input Clk, ... | 7.872268 |
module top (
input clk_16mhz,
output [7:0] pmod_a
);
// sr_74595 wires and registers
reg [24:0] counter = 0;
always @(posedge clk_16mhz) begin
counter <= counter + 1;
end
reg sr_oe = 0;
reg sr_lat = 0;
reg sr_ser = 0;
reg [3:0] line = 0;
reg [1:0] line_counter = 0;
reg [7:0] line_bu... | 7.233807 |
module sr_cpu_vc (
input clk, // clock
input rst_n, // reset
input [ 4:0] regAddr, // debug access reg address
output [31:0] regData, // debug access reg data
output [31:0] imAddr, // instruction memory address
input [31:0] imData, // instruction memory data
... | 7.19695 |
module sr_decode (
input [31:0] instr,
output [ 6:0] cmdOp,
output [ 4:0] rd,
output [ 2:0] cmdF3,
output [ 4:0] rs1,
output [ 4:0] rs2,
output [ 6:0] cmdF7,
output reg [31:0] immI,
output reg [31:0] immB,
output reg [31:0] immU
);
assign cmdOp = in... | 7.840724 |
module sr_alu (
input [31:0] srcA,
input [31:0] srcB,
input [ 2:0] oper,
output zero,
output reg [31:0] result
);
always @(*) begin
case (oper)
default: result = srcA + srcB;
`ALU_ADD: result = srcA + srcB;
`ALU_OR: result = srcA | srcB;
`... | 7.51464 |
module sm_register_file_vc (
input clk,
input [ 4:0] a0,
input [ 4:0] a1,
input [ 4:0] a2,
input [ 4:0] a3,
output [31:0] rd0,
output [31:0] rd1,
output [31:0] rd2,
input [31:0] wd3,
input we3,
input [31:0] vcu_reg_rdata
);
reg [31:0] rf[31:0];
ass... | 7.126393 |
module SR_DECOMP (
input wire rst_n,
input wire clk,
input wire valid_i,
input wire [63:0] data_i,
input wire sop_i,
input wire eop_i,
input wire ready_i,
output wire ready_o,
output reg sop_o,
output reg eop_o,
output wire valid_o,
output wire [63:0] data_o
);
r... | 6.780054 |
module sr_ff_behavioural (
input clk,
input S,
input R,
output Q,
output Qbar
);
reg M, N;
always @(posedge clk) begin
M <= !(S & clk);
N <= !(R & clk);
end
assign Q = !(M & Qbar);
assign Qbar = !(N & Q);
endmodule
| 6.689558 |
module sr_ff_behavioural (
input S,
input R,
input clk,
output reg Q,
output reg QBar
);
always @(posedge clk) begin
case ({
S, R
})
0: begin
Q <= Q;
QBar <= QBar;
end
1: begin
Q <= 1'b0;
QBar <= 1'b1;
end
2: begin
... | 6.689558 |
module sr_ff_data (
q,
qb,
s,
r,
clk
);
input s, r, clk;
output q, qb;
assign q = ~((~(s & clk)) & qb);
assign qb = ~((~(r & clk)) & q);
endmodule
| 7.601979 |
module: sr_ff
// Revision 0.01 - File Created
// Additional Comments:
////////////////////////////////////////////////////////////////////////////////
module sr_ff_tb;
// Inputs
reg s;
reg r;
reg clk;
reg rst;
// Outputs
wire q;
wire qbar;
// Instantiate the Unit Under Test (UUT)
sr_ff uut (
.s(s),
... | 6.505935 |
module SR_Latch (
input S,
R,
CLK,
output Q,
Q_bar
);
wire g, p;
nand #8 G1 (g, S, CLK);
nand #8 G2 (p, R, CLK);
nand #8 G3 (Q, g, Q_bar);
nand #8 G4 (Q_bar, p, Q);
endmodule
| 6.774545 |
module sr_latch (
s,
r,
out
);
input s;
input r;
output reg out;
assign out = 1'b0;
//initialize
always @(s or r) begin
if (s == 1'b1 && r == 1'b0) out = 1'b1;
else if (r == 1'b1 && s == 1'b0) out = 1'b0;
else if (r == 1'b0 && s == 1'b0) out = out;
else out = 1'bx; //forbidde... | 7.007228 |
module sr_latch_enabled (
input A,
input B,
input C,
output Q,
output Qn
);
wire S, R;
wire s, r, q, qn;
and_gate s1 (
A,
C,
s
);
not_gate s2 (
s,
S
);
and_gate r1 (
B,
C,
r
);
not_gate r2 (
r,
R
);
and_gate out1 ... | 6.919954 |
module sr_latch_s (
input S,
input R,
output Q,
output QB
);
//Qn=SR'+R'Q
//Qn'=S'R+S'Q'
wire neg_R, neg_S, a1, a2, a3, a4;
not (neg_R, R);
and (a1, neg_R, Q);
and (a2, S, neg_R);
or (Q, a1, a2);
not (neg_S, S);
and (a3, neg_S, R);
and (a4, neg_S, QB);
or (QB, a3, a4);
endmodul... | 6.617001 |
module SR_LATCH_TB ();
// INPUT PROBES
reg S, R;
// OUTPUT PROBES
wire Q_gate, QBAR_gate;
wire Q_data, QBAR_data;
wire Q_beh, QBAR_beh;
// FOR TESTING
reg TICK;
reg [31:0] VECTORCOUNT, ERRORS;
reg QEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (gate)
sr_latch_... | 7.332443 |
module Latch_with_control (
input S,
input C,
input R,
output Q,
output Qp
);
wire net1, net2;
nand (net1, S, C);
nand (net2, R, C);
Latch latch (
.S (net1),
.R (net2),
.Q (Q),
.Qp(Qp)
);
endmodule
| 7.201124 |
module SR_PIPO (
d,
clk,
reset,
outputs,
write_check
);
input [4:1] d;
input write_check;
input clk, reset;
wire w[3:1];
output [4:1] outputs;
assign w[1] = (write_check & d[1]) | ((~write_check) & outputs[1]);
assign w[2] = (write_check & d[2]) | ((~write_check) & outputs[2]);
a... | 6.821383 |
module SR_PIPO_tb;
reg clk, reset, write;
wire [4:1] q;
reg [4:1] inp;
initial begin
$dumpfile("SR_PIPO_tb.vcd");
$dumpvars(0, SR_PIPO_tb);
end
SR_PIPO srPIPO (
inp,
clk,
reset,
q,
write
);
initial begin
reset = 0;
clk = 0;
write = 1;
inp ... | 6.806384 |
module SR_PISO (
d,
clk,
reset,
q,
write_check
);
input [4:1] d;
input write_check;
input clk, reset;
output q;
wire w[3:1];
wire outputs[3:1];
assign w[1] = (write_check & d[1]) | ((~write_check) & outputs[1]);
assign w[2] = (write_check & d[2]) | ((~write_check) & outputs[2]);
... | 6.577162 |
module SR_SIPO (
d,
clk,
reset,
q
);
input d, clk, reset;
output [4:1] q;
DFF dff_1 (
d,
clk,
reset,
q[1]
);
DFF dff_2 (
q[1],
clk,
reset,
q[2]
);
DFF dff_3 (
q[2],
clk,
reset,
q[3]
);
DFF dff_4 (
q[3],
... | 6.911472 |
module SR_SIPO_tb;
reg clk, reset;
wire [4:1] q;
reg inp;
initial begin
$dumpfile("SR_SIPO_tb.vcd");
$dumpvars(0, SR_SIPO_tb);
end
SR_SIPO srSIPO (
inp,
clk,
reset,
q
);
initial begin
inp = 0;
reset = 0;
clk = 0;
end
always @(negedge clk) inp = ... | 6.994098 |
module SR_SISO (
d,
clk,
reset,
q
);
input d, clk, reset;
output q;
wire w1, w2, w3;
DFF dff_1 (
d,
clk,
reset,
w1
);
DFF dff_2 (
w1,
clk,
reset,
w2
);
DFF dff_3 (
w2,
clk,
reset,
w3
);
DFF dff_4 (
w3,
... | 6.588085 |
module SR_SISO_tb;
reg clk, reset;
wire q;
reg inp;
initial begin
$dumpfile("SR_SISO_tb.vcd");
$dumpvars(0, SR_SISO_tb);
end
SR_SISO srsiso (
inp,
clk,
reset,
q
);
initial begin
inp = 0;
reset = 0;
clk = 0;
end
always @(negedge clk) inp = ~inp;... | 6.644447 |
module SR_tb;
reg clk, reset, x;
wire [3:0] out;
SR u_SR (
.clk(clk),
.reset(reset),
.x(x),
.out(out)
);
initial clk = 1'b0;
initial reset = 1'b1;
initial x = 1'b0;
always clk = #20 ~clk;
always @(reset) begin
reset = #30 ~reset;
end
always @(x) begin
x = #50... | 6.532249 |
module ssb_out (
input clk,
input [ 1:0] div_state, // div_state [0] I-Q signal
input signed [17:0] drive, // Baseband interleaved I-Q
input enable, // Set output on enable else 0
input ssb_flip, // Flips sign of dac2_out output p... | 8.185139 |
module seven (
input clk,
input [12:0] num,
output reg [3:0] Anode,
output reg [6:0] LED_out
);
//assign num =13'd1234;
reg [ 3:0] LED_BCD;
reg [19:0] refresh_counter = 0;
wire [ 1:0] LED_activating_counter;
always @(posedge clk) begin
refresh_counter <= refresh_counter + 1;
end
as... | 7.224734 |
module seven (
input clk,
input [12:0] num,
output reg [3:0] Anode,
output reg [6:0] LED_out
);
//assign num =13'd1234;
reg [ 3:0] LED_BCD;
reg [19:0] refresh_counter = 0;
wire [ 1:0] LED_activating_counter;
always @(posedge clk) begin
refresh_counter <= refresh_counter + 1;
end
as... | 7.224734 |
module SSD1306_ROM_cfg_mod (
input [`BLOCK_ROM_INIT_ADDR_WIDTH-1:0] addr,
output [`BLOCK_ROM_INIT_DATA_WIDTH-1:0] dout
);
parameter FILENAME = "SSD1306_ROM_script.mem";
localparam LENGTH = 2 ** `BLOCK_ROM_INIT_ADDR_WIDTH;
reg [`BLOCK_ROM_INIT_DATA_WIDTH-1:0] mem[LENGTH-1:0];
initial $readmemh(FILENAME... | 7.296122 |
module ssd1780 (
input CLK
, input [7:0] CMD_DAT
, inout SDA
, output SCL
, input START
, input ASYNC_RST_L
, output BUSY
, output RUNNING
);
reg start;
reg [1:0] busy_mask;
wire i2c_busy;
wire addr_sent;
assign BUSY = RUNNING & (i2c_busy | ~busy_mask[1]);
i2c_master i2c (... | 6.946914 |
module SSD4ScanDriver (
input CLK,
input [19:0] INPUT,
output [7:0] OUTPUT_SEG,
output reg [3:0] OUTPUT_SEL
);
wire [31:0] MUX_INPUT;
reg [ 1:0] count = 2'b0;
MUX mux0 (
.CLK(CLK),
.INPUT(MUX_INPUT),
.OUTPUT(OUTPUT_SEG)
);
SSDDigitDriver drv0 (
.INPUT_NUM (INPUT[3:0... | 6.778657 |
module SSDDigitDriver (
input [3:0] INPUT_NUM,
input DIGITPOINT,
output reg [7:0] SSD_OUTPUT
);
reg [6:0] SSD_Charmap[0:15];
integer value;
initial $readmemb("SSD_Charmap.mem", SSD_Charmap);
always @(INPUT_NUM) begin
value = INPUT_NUM;
SSD_OUTPUT <= {DIGITPOINT, SSD_Charmap[value]};
end
... | 6.882329 |
module SSDecoder (
c,
ss
);
input [3:0] c;
output reg [6:0] ss;
//Declare input and output.
always @(c)
case (c)
4'b0000: ss[6:0] = 7'b1000000;
4'b0001: ss[6:0] = 7'b1111001;
4'b0010: ss[6:0] = 7'b0100100;
4'b0011: ss[6:0] = 7'b0110000;
4'b0100: ss[6:0] = 7'b0011001;
... | 7.013451 |
module ssdhex (
input wire Clk,
input wire Reset,
input wire [3:0] SSD0,
input wire [3:0] SSD1,
input wire [3:0] SSD2,
input wire [3:0] SSD3,
input wire Active,
output wire [3:0] Enables,
output reg [7:0] Cathodes
);
wire [ 1:0] ssdscan_clk;
reg [26:0] DIV_CLK;
reg [ 3:0] SSD... | 7.303008 |
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