code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module full_adder__0_656 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_... | 6.521523 |
module full_adder__0_652 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_647 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_car... | 6.521523 |
module full_adder__0_643 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_676 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_... | 6.521523 |
module full_adder__0_672 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_667 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_car... | 6.521523 |
module full_adder__0_663 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_696 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_... | 6.521523 |
module full_adder__0_692 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_687 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_car... | 6.521523 |
module full_adder__0_683 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_716 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_... | 6.521523 |
module full_adder__0_712 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_707 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_car... | 6.521523 |
module full_adder__0_703 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_736 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_... | 6.521523 |
module full_adder__0_732 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_727 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_car... | 6.521523 |
module full_adder__0_723 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_756 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_... | 6.521523 |
module full_adder__0_752 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_747 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_car... | 6.521523 |
module full_adder__0_743 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_776 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_... | 6.521523 |
module full_adder__0_772 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_0)
);
XOR2_X1 i_0_1 (
.A(n_0_0),
.B(i_carry),
... | 6.521523 |
module full_adder__0_767 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_car... | 6.521523 |
module full_adder__0_763 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_0)
);
XOR2_X1 i_0_1 (
.A(n_0_0),
.B(i_carry),
... | 6.521523 |
module full_adder__0_843 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_c... | 6.521523 |
module full_adder__0_872 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_c... | 6.521523 |
module full_adder__0_892 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_c... | 6.521523 |
module full_adder__0_912 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_c... | 6.521523 |
module full_adder__0_932 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_c... | 6.521523 |
module full_adder__0_952 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_c... | 6.521523 |
module full_adder__0_972 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_c... | 6.521523 |
module full_adder__0_992 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_c... | 6.521523 |
module full_adder__0_1012 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_... | 6.521523 |
module full_adder__0_1032 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_... | 6.521523 |
module full_adder__0_1052 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_... | 6.521523 |
module full_adder__0_1072 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_... | 6.521523 |
module Register (
clk,
rst,
load,
data_in,
data_out
);
input clk;
input rst;
input load;
input [15:0] data_in;
output [15:0] data_out;
wire n_0_0;
CLKGATETST_X1 clk_gate_data_out_reg (
.CK (clk),
.E (n_1),
.SE (1'b0),
.GCK(n_0)
);
DFF_X1 \data_out_reg[15]... | 7.117303 |
module stepMotor (
saatDarbesi,
rst,
motorCikis
);
// stepMotor MODÜLÜ TANIMI
//-------------Giriş Portları-----------------------------
input saatDarbesi, rst; //saatDarbesi, rst giriş olarak tanımlanmıştır
//-------------Çıkış Portları-----------------------------
output [3:0] motorCikis; ... | 8.567374 |
module StepMotorControllerTop (
clk,
rst,
speedKey,
stepSizeKey,
rotateDirectionKey,
operationModekey,
quarterTurnKey,
unitsDisplay,
tensDisplay,
out
);
input wire clk, rst, speedKey, stepSizeKey, rotateDirectionKey, operationModekey, quarterTurnKey;
output wire [3:0] out;
... | 8.393388 |
module StepMotorInterface #(
parameter STEPS_PER_REVOLUTION = 64 * 2 * 64,
parameter [0:0] SIDE = 1'b1
) (
input CLK,
input RST_N,
input char_vld,
input [7:0] char,
output enb,
output reg dir,
input stepped
);
reg [31:0] count;
assign enb = count > 0;
always @(posedge CLK) b... | 6.637225 |
module StepperControl (
clock,
reset,
direction,
stop,
led,
stepperPins
);
input clock, reset, direction, stop;
output [2:0] led;
reg [ 2:0] SevenCount;
reg [31:0] Count1;
localparam RATE = 50000000;
// Count to 7, in rate of actual seconds
// Gives us a basis of how fast the m... | 7.85677 |
module stepper_motor (input clk,
input reset,
input en,
input dir,
input steps,
output dir_... | 6.691174 |
module step_button (
input button,
input [2:0] secim1,
input [2:0] secim2,
input [2:0] secim3,
input [2:0] es1,
input [2:0] es2,
input [2:0] es3,
input rst,
output reg [3:0] step_2
);
initial step_2 <= 4'b0000;
always @(posedge button or posedge rst) begin
if (rst) step_2 ... | 6.898181 |
module Step_Control (
input clk, //100MHz
input rst_n,
input [2:0] speed,
input [4:0] openess,
output reg dir,
output reg pul
);
//==============Clock Devider==============
localparam time_1ms = 'd9_999;
reg [15:0] cnt_1ms;
reg clk_1KHz;
reg [2:0] cnt;
always @(posedge clk or neged... | 7.454521 |
module step_ex_cpf (
clk,
rst_,
ena_,
rdy_,
reg_id,
r0_din,
r0_we_,
r0_dout,
r1_dout,
r2_dout,
r3_dout,
r4_dout,
r5_dout,
fl_dout,
pc_dout
);
input clk;
input rst_;
input ena_;
output rdy_;
input [3:0] reg_id;
output [7:0] r0_din;
output r0_we_;
... | 6.791333 |
module step_ex_ld (
clk,
rst_,
ena_,
rdy_,
mem_re_,
abus,
dbus,
r1_dout,
r0_din,
r0_we_
);
input clk;
input rst_;
input ena_;
output rdy_;
output mem_re_;
output [7:0] abus;
input [7:0] dbus;
input [7:0] r1_dout;
output [7:0] r0_din;
output r0_we_;
reg rdy_... | 7.914585 |
module step_ex_nop (
clk,
rst_,
ena_,
rdy_
);
input clk;
input rst_;
input ena_;
output rdy_;
reg rdy_en;
assign rdy_ = rdy_en ? 1'b0 : 1'bZ;
always @(negedge rst_ or posedge clk)
if (!rst_) rdy_en <= 0;
else if (!ena_) rdy_en <= 1;
else rdy_en <= 0;
endmodule
| 7.274001 |
module step_ex_st (
clk,
rst_,
ena_,
rdy_,
mem_we_,
abus,
dbus,
r0_dout,
r1_dout
);
input clk;
input rst_;
input ena_;
output rdy_;
output mem_we_;
output [7:0] abus;
output [7:0] dbus;
input [7:0] r0_dout, r1_dout;
reg rdy_en;
assign rdy_ = rdy_en ? 1'b0 : 1'bZ;... | 7.689086 |
module step_ex_sub (
clk,
rst_,
ena_,
rdy_,
r0_dout,
r1_dout,
r0_din,
r0_we_
);
input clk;
input rst_;
input ena_;
output rdy_;
input [7:0] r0_dout, r1_dout;
output [7:0] r0_din;
output r0_we_;
reg rdy_en;
assign rdy_ = rdy_en ? 1'b0 : 1'bZ;
reg [7:0] r0_din;
reg r... | 6.772242 |
module step_ex_tce (
clk,
rst_,
ena_,
rdy_,
fl_din,
fl_dout,
fl_we_
);
input clk;
input rst_;
input ena_;
output rdy_;
output [7:0] fl_din;
input [7:0] fl_dout;
output fl_we_;
reg rdy_en;
assign rdy_ = rdy_en ? 1'b0 : 1'bZ;
reg fl_din_en;
assign fl_din = fl_din_en ? {f... | 7.047431 |
module step_ex_ts (
clk,
rst_,
ena_,
rdy_,
mode,
r0_dout,
fl_din,
fl_dout,
fl_we_
);
input clk;
input rst_;
input ena_;
output rdy_;
input [1:0] mode;
input [7:0] r0_dout;
output [7:0] fl_din;
input [7:0] fl_dout;
output fl_we_;
reg rdy_en;
assign rdy_ = rdy_en... | 6.86986 |
module step_gen (
clk50,
reset_n,
period,
dir_in,
dir_out,
step_out,
en,
location
);
input clk50;
input reset_n;
input [31:0] period;
input dir_in;
output dir_out;
output reg step_out;
input en;
output reg [31:0] location;
reg [31:0] counter;
assign dir_out = dir_in;... | 6.677307 |
module step_id (
inst,
ena_,
cond_dout,
rdy_nop_,
rdy_cpf_,
rdy_cpt_,
rdy_ld_,
rdy_st_,
rdy_clr_,
rdy_im_,
rdy_tce_,
rdy_ts_,
rdy_add_,
rdy_sub_
);
input [7:0] inst;
input ena_;
input cond_dout;
output rdy_nop_, rdy_cpf_, rdy_cpt_, rdy_ld_, rdy_st_, rdy_cl... | 6.506263 |
module step_if (
clk,
rst_,
ena_,
rdy_,
mem_re_,
abus,
dbus,
pc_din,
pc_dout,
pc_we_,
inst
);
input clk;
input rst_;
input ena_;
output rdy_;
output mem_re_;
output [7:0] abus;
input [7:0] dbus;
output [7:0] pc_din;
input [7:0] pc_dout;
output pc_we_;
ou... | 6.889496 |
module step_limiter (
input do_step_limit,
input [31:0] step_limit,
input i_run,
input i_step,
input i_reset,
input i_clk,
output reg stop
);
reg [31:0] count = 0;
reg last_run_p = 0;
always @(posedge i_clk) last_run_p <= i_run;
reg last_run_n = 0;
always @(negedge i_clk) last_r... | 7.099693 |
module step_limiter_test;
reg clk = 0;
reg [31:0] limit = 5;
reg run = 0;
reg do_limit = 1;
wire stop;
step_limiter test (
do_limit,
limit,
run,
clk,
stop
);
initial begin
$dumpfile("step_limiter_test.v");
$dumpvars(0, step_limiter_test);
#100 run <= 1;
... | 6.578378 |
module step_motor_controller (
input wire change, //key 3- increase/decrease the motor speed
input wire rst,
input wire clk, //50MHz
output wire [2:0] speed
);
//State definition
parameter start = 3'b001, s20 = 3'b010, s30 = 3'b011, s40 = 3'b100, s50 = 3'b101, s60 = 3'b110;
reg change_o;
reg... | 7.198306 |
module step_motor_controller_tb;
reg clock;
reg RSTB;
reg CSB;
reg power1, power2;
reg power3, power4;
wire gpio;
wire [37:0] mprj_io;
wire [15:0] checkbits;
wire [15:0] errorbits;
reg [7:0] cmd_addr;
reg [7:0] cmd_data;
assign checkbits = mprj_io[31:16];
assign errorbits = mprj_io[15:0];
... | 7.198306 |
module step_motor_mode (
input wire rst,
input wire mode, //sw2: 0 for quadrater cycle, 1 for continous
input wire move, //key1 = move quadrater cycle
input wire pulse,
output reg zero_state
);
reg [6:0] num2count;
reg new_pressed;
always @(posedge pulse or negedge rst) begin
if (~rst)... | 6.604109 |
module step_motor_speed (
input wire [2:0] speed,
input wire clk,
input wire rst,
//output reg [19:0] num_to_pulse);
output wire step_pulse
);
reg [19:0] num_to_pulse;
always @(speed) begin
case (speed)
3'b001: num_to_pulse = 20'hB5B8D8; // counts until 375000
3'b010: num_to_pu... | 7.318572 |
module top_module (
output one
);
// Insert your code here
assign one = 1'b1;
endmodule
| 7.203305 |
module name : Stereo
//
//modification history
//---------------------------------
//firt finish 2006
// 2007-07-27 11:30:00
//***********************************************************
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`define DLY 0
module Stereo... | 6.783777 |
module wrapper_norm_corr_20 (
clk,
wen,
d_l_1,
d_l_2,
d_r_1,
d_r_2,
corr_out_0,
corr_out_1,
corr_out_2,
corr_out_3,
corr_out_4,
corr_out_5,
corr_out_6,
corr_out_7,
corr_out_8,
corr_out_9,
corr_out_10,
corr_out_11,
corr_out_12,
corr_out_13,
... | 6.699338 |
module wrapper_norm_corr_10 (
clk,
wen,
d_l_1,
d_l_2,
d_r_1,
d_r_2,
corr_out_0,
corr_out_1,
corr_out_2,
corr_out_3,
corr_out_4,
corr_out_5,
corr_out_6,
corr_out_7,
corr_out_8,
corr_out_9,
corr_out_10
);
parameter sh_reg_w = 4'b1000;
input clk;
i... | 6.699338 |
module wrapper_norm_corr_5_seq (
clk,
wen,
d_l_1,
d_l_2,
d_r_1,
d_r_2,
corr_out_0,
corr_out_1,
corr_out_2,
corr_out_3,
corr_out_4,
corr_out_5
);
parameter sh_reg_w = 4'b1000;
input clk;
input wen;
input [15:0] d_l_1;
input [15:0] d_l_2;
input [15:0] d_r_1;
... | 6.699338 |
module wrapper_corr_5_seq (
tm3_clk_v0,
wen,
d_l_1,
d_l_2,
d_r_1,
d_r_2,
corr_out_0,
corr_out_1,
corr_out_2,
corr_out_3,
corr_out_4,
corr_out_5
);
parameter sh_reg_w = 4'b1000;
input tm3_clk_v0;
input wen;
input [7:0] d_l_1;
input [7:0] d_l_2;
input [7:0] d_... | 6.720326 |
module wrapper_norm_seq (
clk,
nd,
din_1,
din_2,
dout_1,
dout_2
);
parameter sh_reg_w = 4'b1000;
input clk;
input nd;
input [15:0] din_1;
input [15:0] din_2;
output [sh_reg_w - 1:0] dout_1;
wire [sh_reg_w - 1:0] dout_1;
output [sh_reg_w - 1:0] dout_2;
wire [sh_reg_w - 1:0] dou... | 6.699338 |
module my_wrapper_divider (
rst,
clk,
data_in_a,
data_in_b,
data_out
);
parameter INPUT_WIDTH_A = 5'b10000;
parameter INPUT_WIDTH_B = 5'b10001;
parameter OUTPUT_WIDTH = 4'b1000;
parameter S1 = 2'b00;
parameter S2 = 2'b01;
parameter S3 = 2'b10;
parameter S4 = 2'b11;
input rst;
inp... | 7.258611 |
module my_divider (
clk,
rst,
start,
LA,
EB,
data_in_a,
data_in_b,
Remainder,
data_out,
Done
);
parameter INPUT_WIDTH_A = 5'b10000;
parameter INPUT_WIDTH_B = 5'b10001;
parameter OUTPUT_WIDTH = 4'b1000;
parameter LOGN = 3'b100;
parameter S1 = 2'b00;
parameter S2 = 2'... | 7.482014 |
module my_fir_f1 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=29,101,-15,-235,-15,101,29;
//parameter `WIDTH = 5'b10000;
input clk;
input [`WIDTH_5B - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg outp... | 7.162286 |
module my_fir_f2 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=4,42,163,255,163,42,4;
// parameter WIDTH = 5'b10000;
input clk;
input [`WIDTH_5B - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_d... | 7.093413 |
module my_fir_f3 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=-12,-77,-148,0,148,77,12;
// parameter `WIDTH = 5'b10000;
input clk;
input [`WIDTH_5B - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg outpu... | 7.589128 |
module my_fir_h1 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=-15,25,193,0,-193,-25,15;
// parameter `WIDTH = 5'b10000;
input clk;
input [`WIDTH_5B - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg outp... | 7.258261 |
module my_fir_h2 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=4,42,163,255,163,42,4;
// parameter `WIDTH = 5'b10000;
input clk;
input [`WIDTH_5B - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_d... | 7.118788 |
module my_fir_h3 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=-9,-56,-109,0,109,56,9;
// parameter WIDTH = 5'b10000;
input clk;
input [`WIDTH_5B - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_da... | 7.61466 |
module my_fir_h4 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=-9,-56,-109,0,109,56,9;
// parameter WIDTH = 5'b10000;
input clk;
input [`WIDTH_5B - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_da... | 7.756091 |
module stereo_audio_parallelizer #(
parameter audio_width = 32
) (
input wire reset,
input wire clk,
input wire i_valid,
output reg i_ready,
input wire i_is_left,
input wire [audio_width-1:0] i_audio,
output wire o_valid,
input wire o_ready,
output reg [audio_width-1:0] o_left,
... | 7.004634 |
module stereo_audio_parallelizer_tb ();
localparam CLK_TIME = 1000000000 / (44100 * 32) * 2; // 44.1KHz * 32 * 2
initial begin
$dumpfile("stereo_audio_parallelizer_tb.vcd");
$dumpvars;
end
reg clk;
initial begin
clk = 1'b0;
forever begin
#(CLK_TIME / 2) clk = ~clk;
end
end
r... | 7.004634 |
module stereo_audio_parallel_serial_tb ();
localparam CLK_TIME = 1000000000 / (44100 * 32) * 2; // 44.1KHz * 32 * 2
initial begin
$dumpfile("stereo_audio_parallel_serial_tb.vcd");
$dumpvars;
end
reg clk;
initial begin
clk = 1'b0;
forever begin
#(CLK_TIME / 2) clk = ~clk;
end
en... | 7.004634 |
module stereo_audio_serializer #(
parameter audio_width = 32
) (
input wire reset,
input wire clk,
input wire i_valid,
output reg i_ready,
input wire [audio_width-1:0] i_left,
input wire [audio_width-1:0] i_right,
output wire o_valid,
input wire o_ready,
output reg o_is_left,
... | 7.004634 |
module stereo_audio_serializer_tb ();
localparam SCLK_TIME = 1000000000 / (44100 * 32) * 1; // 44.1KHz * 32
localparam lrclk_polarity = 1'b1;
localparam is_i2s = 1'b0;
localparam audio_width = 32;
initial begin
$dumpfile("stereo_audio_serializer_tb.vcd");
$dumpvars;
end
reg sclk;
initial be... | 7.004634 |
module stereo_fm_mx (
input clock,
input reset,
input clken48kHz,
input clken192kHz,
input [3:0] Ks,
input [3:0] Kd,
input [3:0] Kp,
input [7:0] Kf,
input signed [17:0] LEFTin,
input signed [17:0] RIGHTin,
output signed [23:0] FMout
);
wire signed [17:0] LEFTout;
wire... | 6.660598 |
module stereo_tb ();
reg clk, reset;
reg [15:0] codec_sample;
wire [15:0] codec_sample_left;
wire [15:0] codec_sample_right;
stereo DUT (
.clk(clk),
.reset(reset),
.codec_sample(codec_sample),
.codec_sample_right(codec_sample_right),
.codec_sample_left(codec_sample_left)
);
... | 7.627022 |
module stereo_vision_control (
input nRESET,
input CLK,
//
inout STEREO_SDA,
inout STEREO_SCL,
//
input MODE_CAMERA, // 0 master, 1 slave
//
input GAIN_TO_SLAVE,
output GAIN_FROM_MASTER,
input [31:0] INT_TIME_TO_SLAVE,
output [31:0] INT_TIME_FROM_MASTER,
input [31:0]... | 6.843168 |
module sterm (
input wire clk,
input wire [7:0] rdata,
input wire rdempty,
input wire [15:0] q,
output wire [15:0] wdata,
output wire [12:0] wadr,
output wire wr,
output wire [12:0] radr,
output wire ack
);
parameter SCR_STRIDE = 128; /* number of chars in line*/
parameter SCR... | 6.905827 |
module PROG_COUNTER (
BCLK,
BRESET,
NEW,
LOAD_PC,
NEW_PC,
NEXT_ADR,
NEXT_PCA,
DISP,
PC_NEW,
USED,
USER,
SAVE_PC,
FPU_TRAP,
ADIVAR,
PC_ARCHI,
PC_ICACHE,
PC_SAVE,
ALSB,
IC_USER
);
input BCLK, BRESET;
input NEW;
input LOAD_PC;
input NEW_P... | 7.080149 |
module REG_LIST (
DIN,
IPOS,
INIT,
OPOS,
VALID
);
// Detects set bits in register list for SAVE/RESTORE & ENTER/EXIT
input [7:0] DIN;
input [2:0] IPOS;
input INIT;
output [2:0] OPOS;
output VALID;
reg [7:1] filter;
wire [7:0] mdat_0;
wire [3:0] mdat_1;
always @(IPOS or DIN)
... | 6.811924 |
module ste_joypad (
input [15:0] joy, // R3,L3,R2,L2
// R,L,Y,X
// Start, Select, B, A
// UDLR
input [ 3:0] din, // pins 1-4
output reg [ 7:0] dout, // pins 11-14, 1-4
output reg [ 1:0] butt... | 7.426012 |
module ste_joystick (
// system interface
input clk,
input reset,
// cpu register interface
input [15:0] din,
input sel,
input [ 4:0] addr,
input uds,
input lds,
input rw,
output reg [15:0] dout
);
// no functional... | 7.088991 |
module STFT #(
parameter TWIDDLE_FILE = "/home/saviour/study/fpga_spectrogram/src/stft/factor.txt",
WORD_WIDTH = 16,
FFT_SIZE = 256
) (
input wire clk,
input wire SAMPLE_VALID, //FROM I2S RECEIVER
input wire signed [23:0] SAMPLE, // FROM I2S RECEIVER
input wire reset,
output wire wr_... | 6.716928 |
module stft2RAM #(
parameter COUNT_HIGH = 20,
FFT_SIZE = 256,
WORD_WIDTH = 16,
NO_FFTS = 50,
ADDRESS_WIDTH = 12,
NO_BANKS = 2
) (
input wire clk, //27MHz
input wire reset,
input wire wr_en,
input wire [$clog2(FFT_SIZE/2)-1:0] idx,
input wire [WORD_WIDTH*2-1:0] i_data,
o... | 6.645288 |
module STFT_SM #(
parameter WORD_WIDTH = 16,
FFT_SIZE = 256
) (
input wire clk,
reset,
input wire start_compute,
input wire signed [WORD_WIDTH-1:0] SAMPLE,
input wire signed [WORD_WIDTH-1:0] OLDEST_SAMPLE,
output reg signed [WORD_WIDTH-1:0] sample_diff,
output reg sample_wr_en,
... | 6.930028 |
module stickyRound (
sign,
lsb,
guard,
round,
sticky,
rndMode,
rndUp
);
input sign, lsb, guard, round, sticky;
input [1:0] rndMode;
output rndUp;
wire signComp, rndPos, rndNeg, rndNearEven, andOp1, andOp2, andOp3, orOp;
not n (signComp, sign);
or o (orOp, guard, round);
and a1 ... | 6.920456 |
module mux_4_1 (
a,
b,
c,
d,
s1,
s2,
y
);
input a, b, c, d, s1, s2;
output y;
assign y = ((~s1) & (~s2) & a) | ((~s1) & (s2) & b) | ((s1) & (~s2) & c) | ((s1) & (s2) & d);
endmodule
| 8.152157 |
module sticky_bit (
input wire CLK,
RST,
input wire [22:0] leastbits,
input wire Mul_MSB,
input wire Ez_add_MSB,
output wire sticky
);
reg Mul_MSB_f; //Mul_MSB_ff ;
reg Ez_add_MSB_f1, Ez_add_MSB_f2, Ez_add_MSB_f3;
reg [22:0] leastbits_f;
assign sticky = (Mu... | 7.575018 |
module comparator #(
parameter DW = 8
) (
input wire [DW - 1:0] inp,
input wire substract,
input wire clk,
output wire [DW - 1:0] out_max,
output reg [DW - 1:0] out_min
);
//wire [DW - 1: 0] out_min_in;
// wire [DW - 1: 0] out_max_in;
reg [DW - 1:0] max;
initial max = 0;
always @(in... | 7.565129 |
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