code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module full_adder__0_656 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_652 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_647 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_643 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_676 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_672 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_667 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_663 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_696 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_692 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_687 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_683 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_716 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_712 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_707 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_703 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_736 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_732 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_727 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_723 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_756 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_752 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_747 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_743 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_776 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_772 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_0)
);
XOR2_X1 i_0_1 (
.A(n_0_0),
.B(i_carry),
.Z(o_sum)
);
endmodule
| 6.521523 |
module full_adder__0_767 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_763 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_0)
);
XOR2_X1 i_0_1 (
.A(n_0_0),
.B(i_carry),
.Z(o_sum)
);
endmodule
| 6.521523 |
module full_adder__0_843 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_872 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_892 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_912 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_932 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_952 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_972 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_992 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1012 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1032 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1052 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1072 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module Register (
clk,
rst,
load,
data_in,
data_out
);
input clk;
input rst;
input load;
input [15:0] data_in;
output [15:0] data_out;
wire n_0_0;
CLKGATETST_X1 clk_gate_data_out_reg (
.CK (clk),
.E (n_1),
.SE (1'b0),
.GCK(n_0)
);
DFF_X1 \data_out_reg[15] (
.D (n_17),
.CK(n_0),
.Q (data_out[15]),
.QN()
);
DFF_X1 \data_out_reg[14] (
.D (n_16),
.CK(n_0),
.Q (data_out[14]),
.QN()
);
DFF_X1 \data_out_reg[13] (
.D (n_15),
.CK(n_0),
.Q (data_out[13]),
.QN()
);
DFF_X1 \data_out_reg[12] (
.D (n_14),
.CK(n_0),
.Q (data_out[12]),
.QN()
);
DFF_X1 \data_out_reg[11] (
.D (n_13),
.CK(n_0),
.Q (data_out[11]),
.QN()
);
DFF_X1 \data_out_reg[10] (
.D (n_12),
.CK(n_0),
.Q (data_out[10]),
.QN()
);
DFF_X1 \data_out_reg[9] (
.D (n_11),
.CK(n_0),
.Q (data_out[9]),
.QN()
);
DFF_X1 \data_out_reg[8] (
.D (n_10),
.CK(n_0),
.Q (data_out[8]),
.QN()
);
DFF_X1 \data_out_reg[7] (
.D (n_9),
.CK(n_0),
.Q (data_out[7]),
.QN()
);
DFF_X1 \data_out_reg[6] (
.D (n_8),
.CK(n_0),
.Q (data_out[6]),
.QN()
);
DFF_X1 \data_out_reg[5] (
.D (n_7),
.CK(n_0),
.Q (data_out[5]),
.QN()
);
DFF_X1 \data_out_reg[4] (
.D (n_6),
.CK(n_0),
.Q (data_out[4]),
.QN()
);
DFF_X1 \data_out_reg[3] (
.D (n_5),
.CK(n_0),
.Q (data_out[3]),
.QN()
);
DFF_X1 \data_out_reg[2] (
.D (n_4),
.CK(n_0),
.Q (data_out[2]),
.QN()
);
DFF_X1 \data_out_reg[1] (
.D (n_3),
.CK(n_0),
.Q (data_out[1]),
.QN()
);
DFF_X1 \data_out_reg[0] (
.D (n_2),
.CK(n_0),
.Q (data_out[0]),
.QN()
);
OR2_X1 i_0_0 (
.A1(load),
.A2(rst),
.ZN(n_1)
);
INV_X1 i_0_1 (
.A (rst),
.ZN(n_0_0)
);
AND2_X1 i_0_2 (
.A1(n_0_0),
.A2(data_in[0]),
.ZN(n_2)
);
AND2_X1 i_0_3 (
.A1(n_0_0),
.A2(data_in[1]),
.ZN(n_3)
);
AND2_X1 i_0_4 (
.A1(n_0_0),
.A2(data_in[2]),
.ZN(n_4)
);
AND2_X1 i_0_5 (
.A1(n_0_0),
.A2(data_in[3]),
.ZN(n_5)
);
AND2_X1 i_0_6 (
.A1(n_0_0),
.A2(data_in[4]),
.ZN(n_6)
);
AND2_X1 i_0_7 (
.A1(n_0_0),
.A2(data_in[5]),
.ZN(n_7)
);
AND2_X1 i_0_8 (
.A1(n_0_0),
.A2(data_in[6]),
.ZN(n_8)
);
AND2_X1 i_0_9 (
.A1(n_0_0),
.A2(data_in[7]),
.ZN(n_9)
);
AND2_X1 i_0_10 (
.A1(n_0_0),
.A2(data_in[8]),
.ZN(n_10)
);
AND2_X1 i_0_11 (
.A1(n_0_0),
.A2(data_in[9]),
.ZN(n_11)
);
AND2_X1 i_0_12 (
.A1(n_0_0),
.A2(data_in[10]),
.ZN(n_12)
);
AND2_X1 i_0_13 (
.A1(n_0_0),
.A2(data_in[11]),
.ZN(n_13)
);
AND2_X1 i_0_14 (
.A1(n_0_0),
.A2(data_in[12]),
.ZN(n_14)
);
AND2_X1 i_0_15 (
.A1(n_0_0),
.A2(data_in[13]),
.ZN(n_15)
);
AND2_X1 i_0_16 (
.A1(n_0_0),
.A2(data_in[14]),
.ZN(n_16)
);
AND2_X1 i_0_17 (
.A1(n_0_0),
.A2(data_in[15]),
.ZN(n_17)
);
endmodule
| 7.117303 |
module stepMotor (
saatDarbesi,
rst,
motorCikis
);
// stepMotor MODÜLÜ TANIMI
//-------------Giriş Portları-----------------------------
input saatDarbesi, rst; //saatDarbesi, rst giriş olarak tanımlanmıştır
//-------------Çıkış Portları-----------------------------
output [3:0] motorCikis; //motorCikis 12 bitlik çıkış olarak tanımlanmıştır
//-------------Çıkış Portları Veri Tipleri------------------
// Çıkış portları bellek elemanı(reg-yazmaç) veya bir tel olabilir
reg [ 3:0] motorCikis; //motorCikis register(kayıtcısının oluşturulması)
reg [31:0] sayac; //sayac register(kayıtcısının oluşturulması)
//------------Kod Burada Başlamaktadır-------------------------
// Ana döngü bloğu
// Bu sayaç yükselen kenar tetiklemeli olduğundan,
// Bu bloğu saatin yükselen kenarına veya,
// reset butonun alçalan kenarına göre tetikleyeceğiz.
always @(posedge saatDarbesi) begin
sayac <= sayac + 1;
end
always @(posedge saatDarbesi or negedge rst) begin
case (sayac[29:29])
0: begin
case (sayac[18:16]) //case döngüsünün sayaç ile döndürülmesi
// 4 bitlik stepMotor çıkış değerlerinin registere ve oradanda çıkışa aktarılması
0: motorCikis <= 4'b0001;
1: motorCikis <= 4'b0011;
2: motorCikis <= 4'b0010;
3: motorCikis <= 4'b0110;
4: motorCikis <= 4'b0100;
5: motorCikis <= 4'b1100;
6: motorCikis <= 4'b1000;
7: motorCikis <= 4'b1001;
default: motorCikis <= 4'b0000;
endcase
end
1: begin
case (sayac[18:16]) //case döngüsünün sayaç ile döndürülmesi
// 4 bitlik stepMotor çıkış değerlerinin registere ve oradanda çıkışa aktarılması
0: motorCikis <= 4'b1001;
1: motorCikis <= 4'b1000;
2: motorCikis <= 4'b1100;
3: motorCikis <= 4'b0100;
4: motorCikis <= 4'b0110;
5: motorCikis <= 4'b0010;
6: motorCikis <= 4'b0011;
7: motorCikis <= 4'b0001;
default: motorCikis <= 4'b0000;
endcase
end
endcase
end
endmodule
| 8.567374 |
module StepMotorControllerTop (
clk,
rst,
speedKey,
stepSizeKey,
rotateDirectionKey,
operationModekey,
quarterTurnKey,
unitsDisplay,
tensDisplay,
out
);
input wire clk, rst, speedKey, stepSizeKey, rotateDirectionKey, operationModekey, quarterTurnKey;
output wire [3:0] out;
output wire [6:0] unitsDisplay;
output wire [6:0] tensDisplay;
wire [3:0] speedValueBusWire;
wire speedControllerOutWire;
speed speed (
.rst(rst),
.speedKey(speedKey),
.unitsDisplay(unitsDisplay),
.tensDisplay(tensDisplay),
.speedValue(speedValueBusWire)
);
motorController motorController (
.clk(clk),
.rst(rst),
.speedValue(speedValueBusWire),
.stepSizeKey(stepSizeKey),
.quarterTurnKey(quarterTurnKey),
.operationModekey(operationModekey),
.speedControllerOut(speedConvertorOutWire)
);
motorStateMachine motorStateMachine (
.clk(clk),
.rst(rst),
.make_step(speedConvertorOutWire),
.rotateDirectionKey(rotateDirectionKey),
.stepSizeKey(stepSizeKey),
.out(out)
);
endmodule
| 8.393388 |
module StepMotorInterface #(
parameter STEPS_PER_REVOLUTION = 64 * 2 * 64,
parameter [0:0] SIDE = 1'b1
) (
input CLK,
input RST_N,
input char_vld,
input [7:0] char,
output enb,
output reg dir,
input stepped
);
reg [31:0] count;
assign enb = count > 0;
always @(posedge CLK) begin
if (!RST_N) begin
count <= 0;
dir <= 1;
end else begin
if (char_vld) begin
case (char)
"F": begin
dir <= SIDE ? 1 : 0;
count <= STEPS_PER_REVOLUTION;
end
"B": begin
dir <= SIDE ? 0 : 1;
count <= STEPS_PER_REVOLUTION;
end
"L": begin
dir <= 1;
count <= STEPS_PER_REVOLUTION;
end
"R": begin
dir <= 0;
count <= STEPS_PER_REVOLUTION;
end
"S": begin
dir <= 0;
count <= 0;
end
endcase
end else if (count > 0 && stepped) begin
count <= count - 1;
end
end
end
endmodule
| 6.637225 |
module StepperControl (
clock,
reset,
direction,
stop,
led,
stepperPins
);
input clock, reset, direction, stop;
output [2:0] led;
reg [ 2:0] SevenCount;
reg [31:0] Count1;
localparam RATE = 50000000;
// Count to 7, in rate of actual seconds
// Gives us a basis of how fast the motor will spin
// relative to actual seconds
always @(posedge clock) begin
if (SevenCount == 3'b111 || reset == 0) SevenCount <= 1'b0;
Count1 = Count1 + 1'b1;
if (Count1 == RATE) begin
Count1 <= 1'b0;
SevenCount <= SevenCount + 1'b1;
end
end
// diagnostic LEDs
assign led = ~SevenCount;
// GPIO output pins
output [3:0] stepperPins;
reg [ 3:0] stepperPins;
// Count to help determine how often to increase our step
reg [31:0] Count2;
// The stepper motor takes 8 steps for a complete rotation
reg [ 2:0] step;
always @(posedge clock) begin
// if stop is high, we slow the motor down
// to the point it is not spinning at all
if (stop) begin
if (Count2 >= 5000000 * (SevenCount + 1)) begin
step <= step + 1'b1;
Count2 <= 1'b0;
end else Count2 <= Count2 + 1'b1;
end // otherwise spin the motor as fast as we can
// 450000 seems to be the sweet spot.
else if (Count2 >= 45000 * (SevenCount + 1)) begin
step <= step + 1'b1;
Count2 <= 1'b0;
end else Count2 <= Count2 + 1'b1;
end
// every time step changes, we we will change StepperPins depending on direction
always @(step) begin
case (step)
// ternary operator that checks direction
0: stepperPins <= direction ? 4'b1000 : 4'b0001;
1: stepperPins <= direction ? 4'b1100 : 4'b0011;
2: stepperPins <= direction ? 4'b0100 : 4'b0010;
3: stepperPins <= direction ? 4'b0110 : 4'b0110;
4: stepperPins <= direction ? 4'b0010 : 4'b0100;
5: stepperPins <= direction ? 4'b0011 : 4'b1100;
6: stepperPins <= direction ? 4'b0001 : 4'b1000;
7: stepperPins <= direction ? 4'b1001 : 4'b1001;
endcase
end
endmodule
| 7.85677 |
module stepper_motor (input clk,
input reset,
input en,
input dir,
input steps,
output dir_out,
output step_out,
);
parameter COUNTER_WIDTH = 16;
reg step;
reg [COUNTER_WIDTH-1:0] count;
reg div_clk;
initial begin
count <= 0;
end
assign dir_out = dir;
//assign step_out = (en == 1'b1) ? step : 1'b0;
assign step_out = steps;
always @ (posedge clk or posedge rst)
begin
if (rst) begin
step <= 1'b0;
count <= 0;
div_clk <= 1'b0;
end else begin
if (count==16'd5000) begin
div_clk <= ~div_clk;
count <= 16'd0;
end else begin
count = count + 1'b1;
end
end
end
endmodule
| 6.691174 |
module step_button (
input button,
input [2:0] secim1,
input [2:0] secim2,
input [2:0] secim3,
input [2:0] es1,
input [2:0] es2,
input [2:0] es3,
input rst,
output reg [3:0] step_2
);
initial step_2 <= 4'b0000;
always @(posedge button or posedge rst) begin
if (rst) step_2 <= 4'b0000;
else begin
if (step_2 == 4'b0000) step_2 <= 4'b0001;
else if (step_2 == 4'b0001) step_2 <= 4'b0010;
else if (step_2 == 4'b0010) begin
if((secim1==3'b000 && es1==3'b110) || (secim1==3'b110 && es1==3'b000) || (secim1==3'b001 && es1==3'b100) || (secim1==3'b100 && es1==3'b001) || (secim1==3'b010 && es1==3'b011) || (secim1==3'b011 && es1==3'b010) || (secim1==3'b101 && es1==3'b111) || (secim1==3'b111 && es1==3'b101) )
step_2 <= 4'b0011;
else step_2 <= 4'b0000;
end else if (step_2 == 4'b0011) step_2 <= 4'b0100;
else if (step_2 == 4'b0100) step_2 <= 4'b0101;
else if (step_2 == 4'b0101) begin
if((secim2==3'b000 && es2==3'b110) || (secim2==3'b110 && es2==3'b000) || (secim2==3'b001 && es2==3'b100) || (secim2==3'b100 && es2==3'b001) || (secim2==3'b010 && es2==3'b011) || (secim2==3'b011 && es2==3'b010) || (secim2==3'b101 && es2==3'b111) || (secim2==3'b111 && es2==3'b101) )
step_2 <= 4'b0110;
else step_2 <= 4'b0011;
end else if (step_2 == 4'b0110) step_2 <= 4'b0111;
else if (step_2 == 4'b0111) step_2 <= 4'b1000;
else if (step_2 == 4'b1000) begin
if((secim3==3'b000 && es3==3'b110) || (secim3==3'b110 && es3==3'b000) || (secim3==3'b001 && es3==3'b100) || (secim3==3'b100 && es3==3'b001) || (secim3==3'b010 && es3==3'b011) || (secim3==3'b011 && es3==3'b010) || (secim3==3'b101 && es3==3'b111) || (secim3==3'b111 && es3==3'b101) )
step_2 <= 4'b1001;
else step_2 <= 4'b0110;
end else if (step_2 == 4'b1001) step_2 <= 4'b1010;
else if (step_2 == 4'b1010) step_2 <= 4'b1011;
else if (step_2 == 4'b1011) step_2 <= 4'b1100;
end
end
endmodule
| 6.898181 |
module Step_Control (
input clk, //100MHz
input rst_n,
input [2:0] speed,
input [4:0] openess,
output reg dir,
output reg pul
);
//==============Clock Devider==============
localparam time_1ms = 'd9_999;
reg [15:0] cnt_1ms;
reg clk_1KHz;
reg [2:0] cnt;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt_1ms <= 0;
clk_1KHz <= 0;
cnt <= 0;
end else if (cnt_1ms == time_1ms) begin
cnt_1ms <= 0;
if (cnt == (3'd5 - speed)) begin
clk_1KHz <= ~clk_1KHz;
cnt <= 0;
end else cnt <= cnt + 1;
end else cnt_1ms <= cnt_1ms + 1;
end
//Position Control
reg [18:0] crt_pos = 0, next_pos = 0;
always @(posedge clk) next_pos <= {openess, 14'b0} + {openess, 12'b0};
always @(posedge clk_1KHz) begin
if (crt_pos < next_pos) begin
dir <= 1;
pul <= ~pul;
crt_pos <= crt_pos + 1;
end else if (crt_pos > next_pos) begin
dir <= 0;
pul <= ~pul;
crt_pos <= crt_pos - 1;
end
end
endmodule
| 7.454521 |
module step_ex_cpf (
clk,
rst_,
ena_,
rdy_,
reg_id,
r0_din,
r0_we_,
r0_dout,
r1_dout,
r2_dout,
r3_dout,
r4_dout,
r5_dout,
fl_dout,
pc_dout
);
input clk;
input rst_;
input ena_;
output rdy_;
input [3:0] reg_id;
output [7:0] r0_din;
output r0_we_;
input [7:0] r0_dout, r1_dout, r2_dout, r3_dout, r4_dout, r5_dout, fl_dout, pc_dout;
reg rdy_en;
assign rdy_ = rdy_en ? 1'b0 : 1'bZ;
reg r0_din_en;
assign r0_din = r0_din_en ? regs_dout[reg_id] : 8'bZ;
reg r0_we_en;
assign r0_we_ = r0_we_en ? 1'b0 : 1'bZ;
reg state;
tri0 [7:0] regs_dout[15:0];
assign regs_dout[0] = r0_dout;
assign regs_dout[1] = r1_dout;
assign regs_dout[2] = r2_dout;
assign regs_dout[3] = r3_dout;
assign regs_dout[4] = r4_dout;
assign regs_dout[5] = r5_dout;
assign regs_dout[10] = fl_dout;
assign regs_dout[14] = 8'hff;
assign regs_dout[15] = pc_dout;
always @(negedge rst_ or posedge clk)
if (!rst_) begin
rdy_en <= 0;
r0_din_en <= 0;
r0_we_en <= 0;
state <= 0;
end else if (!ena_) begin
rdy_en <= 0;
r0_din_en <= 1;
r0_we_en <= 0;
state <= 1;
end else if (state) begin
rdy_en <= 1;
r0_din_en <= 1;
r0_we_en <= 1;
state <= 0;
end else begin
rdy_en <= 0;
r0_din_en <= 0;
r0_we_en <= 0;
end
endmodule
| 6.791333 |
module step_ex_ld (
clk,
rst_,
ena_,
rdy_,
mem_re_,
abus,
dbus,
r1_dout,
r0_din,
r0_we_
);
input clk;
input rst_;
input ena_;
output rdy_;
output mem_re_;
output [7:0] abus;
input [7:0] dbus;
input [7:0] r1_dout;
output [7:0] r0_din;
output r0_we_;
reg rdy_en;
assign rdy_ = rdy_en ? 1'b0 : 1'bZ;
reg mem_re_en;
assign mem_re_ = mem_re_en ? 1'b0 : 1'bZ;
assign abus = mem_re_en ? r1_dout : 8'bZ;
assign r0_din = mem_re_en ? dbus : 8'bZ;
reg r0_we_en;
assign r0_we_ = r0_we_en ? 1'b0 : 1'bZ;
reg [1:0] state;
always @(negedge rst_ or posedge clk)
if (!rst_) begin
rdy_en <= 0;
mem_re_en <= 0;
r0_we_en <= 0;
state <= 0;
end else begin
/*
State 0: ena_=0 state=00
rdy_en=0 mem_re_en=1 r0_we_en=0 state=01
State 1: ena_=1 state=01
rdy_en=0 mem_re_en=1 r0_we_en=1 state=10
State 2: ena_=1 state=10
rdy_en=1 mem_re_en=0 r0_we_en=0 state=00
State 3: ena_=1 state=00
rdy_en=0 mem_re_en=0 r0_we_en=0 state=00
*/
rdy_en <= state[1];
mem_re_en <= state[0] | ~ena_;
r0_we_en <= state[0];
state <= {state[0], ~ena_};
end
endmodule
| 7.914585 |
module step_ex_nop (
clk,
rst_,
ena_,
rdy_
);
input clk;
input rst_;
input ena_;
output rdy_;
reg rdy_en;
assign rdy_ = rdy_en ? 1'b0 : 1'bZ;
always @(negedge rst_ or posedge clk)
if (!rst_) rdy_en <= 0;
else if (!ena_) rdy_en <= 1;
else rdy_en <= 0;
endmodule
| 7.274001 |
module step_ex_st (
clk,
rst_,
ena_,
rdy_,
mem_we_,
abus,
dbus,
r0_dout,
r1_dout
);
input clk;
input rst_;
input ena_;
output rdy_;
output mem_we_;
output [7:0] abus;
output [7:0] dbus;
input [7:0] r0_dout, r1_dout;
reg rdy_en;
assign rdy_ = rdy_en ? 1'b0 : 1'bZ;
reg mem_we_en;
assign mem_we_ = mem_we_en ? 1'b0 : 1'bZ;
reg bus_en;
assign abus = bus_en ? r1_dout : 8'bZ;
assign dbus = bus_en ? r0_dout : 8'bZ;
reg [1:0] state;
always @(negedge rst_ or posedge clk)
if (!rst_) begin
rdy_en <= 0;
bus_en <= 0;
state <= 0;
end else begin
/*
State 0: ena_=0 state=00
rdy_en=0 bus_en=1 state=01
State 1: ena_=1 state=01
rdy_en=0 bus_en=1 state=10
State 2: ena_=1 state=10
rdy_en=1 bus_en=0 state=00
State 3: ena_=1 state=00
rdy_en=0 bus_en=0 state=00
*/
rdy_en <= state[1];
bus_en <= state[0] | ~ena_;
state <= {state[0], ~ena_};
end
always @(negedge rst_ or negedge clk)
if (!rst_) mem_we_en <= 0;
else
/*
State 0.5: state=01
mem_we_en=1
State 1.5: state=10
mem_we_en=0
State 2.5: state=00
mem_we_en=0
*/
mem_we_en <= state[0];
endmodule
| 7.689086 |
module step_ex_sub (
clk,
rst_,
ena_,
rdy_,
r0_dout,
r1_dout,
r0_din,
r0_we_
);
input clk;
input rst_;
input ena_;
output rdy_;
input [7:0] r0_dout, r1_dout;
output [7:0] r0_din;
output r0_we_;
reg rdy_en;
assign rdy_ = rdy_en ? 1'b0 : 1'bZ;
reg [7:0] r0_din;
reg r0_we_en;
assign r0_we_ = r0_we_en ? 1'b0 : 1'bZ;
reg state;
always @(negedge rst_ or posedge clk)
if (!rst_) begin
rdy_en <= 0;
r0_din <= 8'bZ;
r0_we_en <= 0;
state <= 0;
end else if (!ena_) begin
rdy_en <= 0;
r0_din <= r0_dout - r1_dout;
r0_we_en <= 0;
state <= 1;
end else if (state) begin
rdy_en <= 1;
r0_din <= r0_dout - r1_dout;
r0_we_en <= 1;
state <= 0;
end else begin
rdy_en <= 0;
r0_din <= 8'bZ;
r0_we_en <= 0;
end
endmodule
| 6.772242 |
module step_ex_tce (
clk,
rst_,
ena_,
rdy_,
fl_din,
fl_dout,
fl_we_
);
input clk;
input rst_;
input ena_;
output rdy_;
output [7:0] fl_din;
input [7:0] fl_dout;
output fl_we_;
reg rdy_en;
assign rdy_ = rdy_en ? 1'b0 : 1'bZ;
reg fl_din_en;
assign fl_din = fl_din_en ? {fl_dout[7:1], ~fl_dout[0]} : 8'bZ;
reg fl_we_en;
assign fl_we_ = fl_we_en ? 1'b0 : 1'bZ;
reg state;
always @(negedge rst_ or posedge clk)
if (!rst_) begin
rdy_en <= 0;
fl_din_en <= 0;
fl_we_en <= 0;
state <= 0;
end else if (!ena_) begin
rdy_en <= 0;
fl_din_en <= 1;
fl_we_en <= 0;
state <= 1;
end else if (state) begin
rdy_en <= 1;
fl_din_en <= 1;
fl_we_en <= 1;
state <= 0;
end else begin
rdy_en <= 0;
fl_din_en <= 0;
fl_we_en <= 0;
end
endmodule
| 7.047431 |
module step_ex_ts (
clk,
rst_,
ena_,
rdy_,
mode,
r0_dout,
fl_din,
fl_dout,
fl_we_
);
input clk;
input rst_;
input ena_;
output rdy_;
input [1:0] mode;
input [7:0] r0_dout;
output [7:0] fl_din;
input [7:0] fl_dout;
output fl_we_;
reg rdy_en;
assign rdy_ = rdy_en ? 1'b0 : 1'bZ;
wire result = mode[1] ? mode[0] ? r0_dout[7] : r0_dout != 8'b0 : r0_dout[0];
reg fl_din_en;
assign fl_din = fl_din_en ? {fl_dout[7:1], result} : 8'bZ;
reg fl_we_en;
assign fl_we_ = fl_we_en ? 1'b0 : 1'bZ;
reg state;
always @(negedge rst_ or posedge clk)
if (!rst_) begin
rdy_en <= 0;
fl_din_en <= 0;
fl_we_en <= 0;
state <= 0;
end else if (!ena_) begin
rdy_en <= 0;
fl_din_en <= 1;
fl_we_en <= 0;
state <= 1;
end else if (state) begin
rdy_en <= 1;
fl_din_en <= 1;
fl_we_en <= 1;
state <= 0;
end else begin
rdy_en <= 0;
fl_din_en <= 0;
fl_we_en <= 0;
end
endmodule
| 6.86986 |
module step_gen (
clk50,
reset_n,
period,
dir_in,
dir_out,
step_out,
en,
location
);
input clk50;
input reset_n;
input [31:0] period;
input dir_in;
output dir_out;
output reg step_out;
input en;
output reg [31:0] location;
reg [31:0] counter;
assign dir_out = dir_in;
always @(posedge clk50 or negedge reset_n) begin // Step generator
if (!reset_n) begin
counter <= 0;
step_out <= 0;
end else begin
if (en) begin
if (counter > period) begin
counter <= 0;
step_out <= ~step_out;
end else begin
counter <= counter + 1;
step_out <= step_out;
end
end else begin
counter <= 0;
step_out <= 0;
end
end
end
reg last_step_out;
always @(posedge clk50) begin
last_step_out <= step_out;
end
always@(posedge clk50 or negedge reset_n) begin // steps accumulator. 0 is at 32h 80 00 00 00. MSb is sign. 1 is positive
if (!reset_n) begin
location <= 32'h80000000;
end else begin
if (step_out == 1 && last_step_out == 0) begin // step pulse sent
if (dir_out) begin
location <= location + 1;
end else begin
location <= location - 1;
end
end else begin
location <= location;
end
end
end
endmodule
| 6.677307 |
module step_id (
inst,
ena_,
cond_dout,
rdy_nop_,
rdy_cpf_,
rdy_cpt_,
rdy_ld_,
rdy_st_,
rdy_clr_,
rdy_im_,
rdy_tce_,
rdy_ts_,
rdy_add_,
rdy_sub_
);
input [7:0] inst;
input ena_;
input cond_dout;
output rdy_nop_, rdy_cpf_, rdy_cpt_, rdy_ld_, rdy_st_, rdy_clr_, rdy_im_, rdy_tce_, rdy_ts_, rdy_add_, rdy_sub_;
wire cond_ = inst[7] ^ cond_dout;
wire [6:0] inst_cond = inst[6:0] & {7{~(cond_ | ena_)}};
assign rdy_nop_ = inst_cond[6:0] != 7'b0000000 || ena_;
assign rdy_cpf_ = inst_cond[6:4] != 3'b010 || inst_cond[3:0] == 4'b0000;
assign rdy_cpt_ = inst_cond[6:4] != 3'b011 || inst_cond[3:0] == 4'b0000;
assign rdy_ld_ = {inst_cond[6:2], inst_cond[0]} != {5'b10001, 1'b0};
assign rdy_st_ = {inst_cond[6:2], inst_cond[0]} != {5'b10001, 1'b1};
assign rdy_clr_ = inst_cond != 7'b1010000;
assign rdy_im_ = inst_cond[6:5] != 2'b11;
assign rdy_tce_ = inst_cond != 7'b0001100;
assign rdy_ts_ = {inst_cond[6], inst_cond[3:0]} != {1'b0, 4'b0000} || inst_cond[5:4] == 2'b00;
assign rdy_add_ = inst_cond != 7'b1010110;
assign rdy_sub_ = inst_cond != 7'b1010111;
endmodule
| 6.506263 |
module step_if (
clk,
rst_,
ena_,
rdy_,
mem_re_,
abus,
dbus,
pc_din,
pc_dout,
pc_we_,
inst
);
input clk;
input rst_;
input ena_;
output rdy_;
output mem_re_;
output [7:0] abus;
input [7:0] dbus;
output [7:0] pc_din;
input [7:0] pc_dout;
output pc_we_;
output [7:0] inst;
reg rdy_;
reg mem_re_en;
assign mem_re_ = mem_re_en ? 1'b0 : 1'bZ;
assign abus = mem_re_en ? pc_dout : 8'bZ;
reg [7:0] pc_din;
reg pc_we_en;
assign pc_we_ = pc_we_en ? 1'b0 : 1'bZ;
reg [7:0] inst;
reg [3:0] state;
always @(negedge clk or negedge rst_)
if (!rst_) begin
rdy_ <= 1;
mem_re_en <= 0;
pc_din <= 8'bZ;
pc_we_en <= 0;
inst <= 0;
state <= 0;
end else begin
/*
State 0: ena_=0 state=x000
rdy_=1 mem_re_en=1 pc_din=ZZZZZZZZ pc_we_en=0 state=0001
State 1: ena_=1 state=0001
rdy_=1 mem_re_en=1 pc_din=ZZZZZZZZ pc_we_en=0 state=0010 inst=dbus
State 2: ena_=1 state=0010
rdy_=1 mem_re_en=0 pc_din=pc_dout+1 pc_we_en=0 state=0100
State 3: ena_=1 state=0100
rdy_=1 mem_re_en=0 pc_din=pc_dout+1 pc_we_en=1 state=1000
State 4: ena_=1 state=1000
rdy_=0 mem_re_en=0 pc_din=ZZZZZZZZ pc_we_en=0 state=0000
State 5: ena_=1 state=0000
rdy_=1 mem_re_en=0 pc_din=ZZZZZZZZ pc_we_en=0 state=0000
*/
rdy_ <= ~state[3];
mem_re_en <= ~ena_ | state[0];
pc_din <= (state[1] | state[2]) ? (pc_dout + 8'd1) : 8'bZ;
pc_we_en <= state[2];
inst <= state[0] ? dbus : inst;
state <= {state[2:0], ~ena_};
end
endmodule
| 6.889496 |
module step_limiter (
input do_step_limit,
input [31:0] step_limit,
input i_run,
input i_step,
input i_reset,
input i_clk,
output reg stop
);
reg [31:0] count = 0;
reg last_run_p = 0;
always @(posedge i_clk) last_run_p <= i_run;
reg last_run_n = 0;
always @(negedge i_clk) last_run_n <= i_run;
wire condition;
assign condition = (i_step & do_step_limit) | (~last_run_n & ~last_run_p) | i_reset;
always @(posedge condition) begin
if (i_run & ~i_reset) begin
count <= count + 1;
if (count >= step_limit) begin
stop <= 1;
count <= 0;
end
end else begin
count <= 0;
stop <= 0;
end
end
endmodule
| 7.099693 |
module step_limiter_test;
reg clk = 0;
reg [31:0] limit = 5;
reg run = 0;
reg do_limit = 1;
wire stop;
step_limiter test (
do_limit,
limit,
run,
clk,
stop
);
initial begin
$dumpfile("step_limiter_test.v");
$dumpvars(0, step_limiter_test);
#100 run <= 1;
#50 $finish;
end
always @(posedge stop) #1 run <= 0;
always begin
#1 clk <= 1;
#2 clk <= 0;
#1 clk <= 0;
end
endmodule
| 6.578378 |
module step_motor_controller (
input wire change, //key 3- increase/decrease the motor speed
input wire rst,
input wire clk, //50MHz
output wire [2:0] speed
);
//State definition
parameter start = 3'b001, s20 = 3'b010, s30 = 3'b011, s40 = 3'b100, s50 = 3'b101, s60 = 3'b110;
reg change_o;
reg [2:0] cs;
reg [2:0] ns;
reg faster = 1'b1; // If key 3 makes the motor faster or slower
always @(posedge clk) begin
change_o <= change;
end
//every clock insert ns to cs
always @(posedge change_o or negedge rst) begin
if (~rst) begin
cs <= start;
faster <= 1'b1;
end else begin
cs <= ns;
if (cs == start) begin
faster <= 1'b1;
end
if (cs == s60) begin
faster <= 1'b0;
end
end
end
//Next state logic
always @(cs)//Will actevaite when cs or the in change
begin
case (cs)
start: ns = s20;
s20: ns = faster ? s30 : start;
s30: ns = faster ? s40 : s20;
s40: ns = faster ? s50 : s30;
s50: ns = faster ? s60 : s40;
s60: ns = s50;
default: ns = start;
endcase
end
assign speed = cs;
endmodule
| 7.198306 |
module step_motor_controller_tb;
reg clock;
reg RSTB;
reg CSB;
reg power1, power2;
reg power3, power4;
wire gpio;
wire [37:0] mprj_io;
wire [15:0] checkbits;
wire [15:0] errorbits;
reg [7:0] cmd_addr;
reg [7:0] cmd_data;
assign checkbits = mprj_io[31:16];
assign errorbits = mprj_io[15:0];
assign (pull1, pull0) mprj_io[37:0] = 38'b11111111111111111111111111111111111111;
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
// would be the fast clock.
always #12.5 clock <= (clock === 1'b0);
initial begin
clock = 0;
end
initial begin
$dumpfile("step_motor_controller.vcd");
$dumpvars(0, step_motor_controller_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (7000) begin
repeat (1000) @(posedge clock);
// $display("+1000 cycles");
end
$display("%c[1;31m", 27);
`ifdef GL
$display("Monitor: Timeout, Test Mega-Project WB Port (GL) Failed");
`else
$display("Monitor: Timeout, Test Mega-Project WB Port (RTL) Failed");
`endif
$display("%c[0m", 27);
$finish;
end
initial begin
wait (checkbits == 16'hAB60);
$display("Monitor: MPRJ-Logic WB Started");
wait (checkbits == 16'hAB61);
if (errorbits == 16'h0000) begin
`ifdef GL
$display("Monitor: Mega-Project WB (GL) Passed");
`else
$display("Monitor: Mega-Project WB (RTL) Passed");
`endif
end else begin
`ifdef GL
$display("Monitor: Mega-Project WB (GL) Failed [0x%h errors]", errorbits);
`else
$display("Monitor: Mega-Project WB (RTL) Failed [0x%h errors]", errorbits);
`endif
end
$finish;
end
initial begin
RSTB <= 1'b0;
CSB <= 1'b1; // Force CSB high
#2000;
RSTB <= 1'b1; // Release reset
#100000;
CSB = 1'b0; // CSB can be released
end
initial begin // Power-up sequence
power1 <= 1'b0;
power2 <= 1'b0;
#200;
power1 <= 1'b1;
#200;
power2 <= 1'b1;
end
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire VDD3V3 = power1;
wire VDD1V8 = power2;
wire VSS = 1'b0;
caravel uut (
.vddio (VDD3V3),
.vddio_2 (VDD3V3),
.vssio (VSS),
.vssio_2 (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
.vdda1 (VDD3V3),
.vdda1_2 (VDD3V3),
.vdda2 (VDD3V3),
.vssa1 (VSS),
.vssa1_2 (VSS),
.vssa2 (VSS),
.vccd1 (VDD1V8),
.vccd2 (VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
.clock (clock),
.gpio (gpio),
.mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
.resetb (RSTB)
);
spiflash #(
.FILENAME("step_motor_controller.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(), // not used
.io3() // not used
);
endmodule
| 7.198306 |
module step_motor_mode (
input wire rst,
input wire mode, //sw2: 0 for quadrater cycle, 1 for continous
input wire move, //key1 = move quadrater cycle
input wire pulse,
output reg zero_state
);
reg [6:0] num2count;
reg new_pressed;
always @(posedge pulse or negedge rst) begin
if (~rst) begin
new_pressed <= 1'b1;
num2count <= 7'h0;
end else if (mode == 1'b1) begin
zero_state <= 1'b0;
end else begin
if (~move & new_pressed) begin
new_pressed <= 1'b0;
if (num2count == 7'h0) num2count <= 7'h64; //100 in decimal basis
end else if (move) new_pressed <= 1'b1;
if (num2count > 7'h0) begin
num2count <= num2count - 7'h1;
zero_state <= 1'b0;
end else if (num2count == 7'h0) zero_state <= 1'b1;
end
end
endmodule
| 6.604109 |
module step_motor_speed (
input wire [2:0] speed,
input wire clk,
input wire rst,
//output reg [19:0] num_to_pulse);
output wire step_pulse
);
reg [19:0] num_to_pulse;
always @(speed) begin
case (speed)
3'b001: num_to_pulse = 20'hB5B8D8; // counts until 375000
3'b010: num_to_pulse = 20'h2DC6C; // counts until 187500
3'b011: num_to_pulse = 20'h1E848; // counts until 125000
3'b100: num_to_pulse = 20'h16E36; // counts until 93750
3'b101: num_to_pulse = 20'h124F8; // counts until 75000
3'b110: num_to_pulse = 20'hF424; // counts until 62500
default num_to_pulse = 20'hB5B8D8; // counts until 375000
endcase
end
counter counter_inst (
.clk(clk),
.rst(rst),
.num_to_pulse(num_to_pulse),
.step_pulse(step_pulse)
);
endmodule
| 7.318572 |
module top_module (
output one
);
// Insert your code here
assign one = 1'b1;
endmodule
| 7.203305 |
module name : Stereo
//
//modification history
//---------------------------------
//firt finish 2006
// 2007-07-27 11:30:00
//***********************************************************
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`define DLY 0
module Stereo(Clk,
Rst,
Enable,
Done,
Mulin1_ste,
Mulin2_ste,
Mulout,
Ram_WEN,
Ram_CEN,
Ram_A,
Ram_D,
Ram_Q,
Mode,
Mode_ext);
input Clk;
input Rst;
input Enable;
input[19:0] Ram_Q;
input signed[39:0] Mulout;
input[1 :0] Mode;
input[1 :0] Mode_ext;
output Done;
output Ram_CEN;
output Ram_WEN;
output[12:0] Ram_A;
output[19:0] Ram_D;
output signed[19:0] Mulin1_ste;
output signed[19:0] Mulin2_ste;
reg Done;
reg Ram_CEN;
reg Ram_WEN;
reg[12:0] Ram_A;
reg[19:0] Ram_D;
reg signed[19:0] Mulin2_ste;
//register
reg[1 :0] CS,NS;
parameter
IDLE=2'b00,
MSTE=2'b01,
DONE=2'b10;
reg[3 :0] Ms_Cnt;
reg[9 :0] Line_Cnt;
reg signed[20:0] Data0_reg;
reg signed[20:0] Data1_reg;
//variable
reg Ramwen;
reg Ramcen;
reg[12:0] Ramaddr;
//******************************MAIN***************************************
always@(posedge Clk)
begin
if(!Rst)
CS<=#`DLY IDLE;
else
CS<=#`DLY NS;
end
always@(CS or Line_Cnt or Enable or Mode or Mode_ext)
begin
case(CS)
IDLE:if(Enable)
begin
if((Mode==1)&&(Mode_ext==2))
NS=MSTE;
else
NS=DONE;
end
else
NS=IDLE;
MSTE:if(Line_Cnt==576)
NS=DONE;
else
NS=MSTE;
DONE:NS=IDLE;
default:NS=IDLE;
endcase
end
//calculate MS Stereo
always@(posedge Clk)
begin
if(NS==IDLE)
Line_Cnt<=#`DLY 10'b0;
else if(Ms_Cnt[3]==1)
Line_Cnt<=#`DLY Line_Cnt+1;
end
always@(posedge Clk)
begin
if(NS==IDLE||Ms_Cnt[3]==1)
Ms_Cnt<=#`DLY 4'b0;
else if(CS==MSTE)
Ms_Cnt<=#`DLY Ms_Cnt+1;
end
always@(posedge Clk)
begin
if(Ms_Cnt==2)
Data0_reg<=#`DLY {1'b0,Ram_Q};
else if(Ms_Cnt==5||Ms_Cnt==6)
Data0_reg<=#`DLY Mulout[38:18];
end
always@(posedge Clk)
begin
if(Ms_Cnt==3)
Data1_reg<=#`DLY {1'b0,Ram_Q};
end
always@(posedge Clk)
begin
if((Line_Cnt==576)&&(CS==MSTE)||(CS==DONE))
Done<=#`DLY 1'b1;
else
Done<=#`DLY 1'b0;
end
//Multipiler
assign Mulin1_ste= 20'd370728;
always@(Data0_reg or Data1_reg or Ms_Cnt)
begin
case(Ms_Cnt)
4:Mulin2_ste= Data0_reg[19:0]+Data1_reg[19:0];
5:Mulin2_ste= Data0_reg[19:0]-Data1_reg[19:0];
default: Mulin2_ste= 20'b0;
endcase
end
//Ram read and write
always@(Ms_Cnt or Line_Cnt)
begin
case(Ms_Cnt)
0:begin
Ramwen=1'b1;
Ramcen=1'b0;
Ramaddr={3'b010,Line_Cnt};
end
1:begin
Ramwen=1'b1;
Ramcen=1'b0;
Ramaddr={3'b011,Line_Cnt};
end
6:begin
Ramwen=1'b0;
Ramcen=1'b0;
Ramaddr={3'b010,Line_Cnt};
end
7:begin
Ramwen=1'b0;
Ramcen=1'b0;
Ramaddr={3'b011,Line_Cnt};
end
default:
begin
Ramwen=1'b1;
Ramcen=1'b1;
Ramaddr=13'b0;
end
endcase
end
always@(posedge Clk)
begin
Ram_WEN<=#`DLY Ramwen;
Ram_CEN<=#`DLY Ramcen;
Ram_A <=#`DLY Ramaddr;
end
always@(posedge Clk)
begin
if(Ms_Cnt==6||Ms_Cnt==7)
Ram_D<=#`DLY Data0_reg[20:1]+Data0_reg[0];
else
Ram_D<=#`DLY 20'b0;
end
endmodule
| 6.783777 |
module wrapper_norm_corr_20 (
clk,
wen,
d_l_1,
d_l_2,
d_r_1,
d_r_2,
corr_out_0,
corr_out_1,
corr_out_2,
corr_out_3,
corr_out_4,
corr_out_5,
corr_out_6,
corr_out_7,
corr_out_8,
corr_out_9,
corr_out_10,
corr_out_11,
corr_out_12,
corr_out_13,
corr_out_14,
corr_out_15,
corr_out_16,
corr_out_17,
corr_out_18,
corr_out_19,
corr_out_20
);
parameter sh_reg_w = 4'b1000;
input clk;
input wen;
input [15:0] d_l_1;
input [15:0] d_l_2;
input [15:0] d_r_1;
input [15:0] d_r_2;
output [2 * sh_reg_w - 1:0] corr_out_0;
wire [2 * sh_reg_w - 1:0] corr_out_0;
output [2 * sh_reg_w - 1:0] corr_out_1;
wire [2 * sh_reg_w - 1:0] corr_out_1;
output [2 * sh_reg_w - 1:0] corr_out_2;
wire [2 * sh_reg_w - 1:0] corr_out_2;
output [2 * sh_reg_w - 1:0] corr_out_3;
wire [2 * sh_reg_w - 1:0] corr_out_3;
output [2 * sh_reg_w - 1:0] corr_out_4;
wire [2 * sh_reg_w - 1:0] corr_out_4;
output [2 * sh_reg_w - 1:0] corr_out_5;
wire [2 * sh_reg_w - 1:0] corr_out_5;
output [2 * sh_reg_w - 1:0] corr_out_6;
wire [2 * sh_reg_w - 1:0] corr_out_6;
output [2 * sh_reg_w - 1:0] corr_out_7;
wire [2 * sh_reg_w - 1:0] corr_out_7;
output [2 * sh_reg_w - 1:0] corr_out_8;
wire [2 * sh_reg_w - 1:0] corr_out_8;
output [2 * sh_reg_w - 1:0] corr_out_9;
wire [2 * sh_reg_w - 1:0] corr_out_9;
output [2 * sh_reg_w - 1:0] corr_out_10;
wire [2 * sh_reg_w - 1:0] corr_out_10;
output [2 * sh_reg_w - 1:0] corr_out_11;
wire [2 * sh_reg_w - 1:0] corr_out_11;
output [2 * sh_reg_w - 1:0] corr_out_12;
wire [2 * sh_reg_w - 1:0] corr_out_12;
output [2 * sh_reg_w - 1:0] corr_out_13;
wire [2 * sh_reg_w - 1:0] corr_out_13;
output [2 * sh_reg_w - 1:0] corr_out_14;
wire [2 * sh_reg_w - 1:0] corr_out_14;
output [2 * sh_reg_w - 1:0] corr_out_15;
wire [2 * sh_reg_w - 1:0] corr_out_15;
output [2 * sh_reg_w - 1:0] corr_out_16;
wire [2 * sh_reg_w - 1:0] corr_out_16;
output [2 * sh_reg_w - 1:0] corr_out_17;
wire [2 * sh_reg_w - 1:0] corr_out_17;
output [2 * sh_reg_w - 1:0] corr_out_18;
wire [2 * sh_reg_w - 1:0] corr_out_18;
output [2 * sh_reg_w - 1:0] corr_out_19;
wire [2 * sh_reg_w - 1:0] corr_out_19;
output [2 * sh_reg_w - 1:0] corr_out_20;
wire [2 * sh_reg_w - 1:0] corr_out_20;
wire [sh_reg_w - 1:0] d_l_1_nrm;
wire [sh_reg_w - 1:0] d_l_2_nrm;
wire [sh_reg_w - 1:0] d_r_1_nrm;
wire [sh_reg_w - 1:0] d_r_2_nrm;
wrapper_norm norm_inst_left (
.clk(clk),
.nd(wen),
.din_1(d_l_1),
.din_2(d_l_2),
.dout_1(d_l_1_nrm),
.dout_2(d_l_2_nrm)
);
wrapper_norm norm_inst_right (
.clk(clk),
.nd(wen),
.din_1(d_r_1),
.din_2(d_r_2),
.dout_1(d_r_1_nrm),
.dout_2(d_r_2_nrm)
);
wrapper_corr_20 corr_20_inst (
.clk(clk),
.wen(wen),
.d_l_1(d_l_1_nrm),
.d_l_2(d_l_2_nrm),
.d_r_1(d_r_1_nrm),
.d_r_2(d_r_2_nrm),
.corr_out_0(corr_out_0),
.corr_out_1(corr_out_1),
.corr_out_2(corr_out_2),
.corr_out_3(corr_out_3),
.corr_out_4(corr_out_4),
.corr_out_5(corr_out_5),
.corr_out_6(corr_out_6),
.corr_out_7(corr_out_7),
.corr_out_8(corr_out_8),
.corr_out_9(corr_out_9),
.corr_out_10(corr_out_10),
.corr_out_11(corr_out_11),
.corr_out_12(corr_out_12),
.corr_out_13(corr_out_13),
.corr_out_14(corr_out_14),
.corr_out_15(corr_out_15),
.corr_out_16(corr_out_16),
.corr_out_17(corr_out_17),
.corr_out_18(corr_out_18),
.corr_out_19(corr_out_19),
.corr_out_20(corr_out_20)
);
endmodule
| 6.699338 |
module wrapper_norm_corr_10 (
clk,
wen,
d_l_1,
d_l_2,
d_r_1,
d_r_2,
corr_out_0,
corr_out_1,
corr_out_2,
corr_out_3,
corr_out_4,
corr_out_5,
corr_out_6,
corr_out_7,
corr_out_8,
corr_out_9,
corr_out_10
);
parameter sh_reg_w = 4'b1000;
input clk;
input wen;
input [15:0] d_l_1;
input [15:0] d_l_2;
input [15:0] d_r_1;
input [15:0] d_r_2;
output [2 * sh_reg_w - 1:0] corr_out_0;
wire [2 * sh_reg_w - 1:0] corr_out_0;
output [2 * sh_reg_w - 1:0] corr_out_1;
wire [2 * sh_reg_w - 1:0] corr_out_1;
output [2 * sh_reg_w - 1:0] corr_out_2;
wire [2 * sh_reg_w - 1:0] corr_out_2;
output [2 * sh_reg_w - 1:0] corr_out_3;
wire [2 * sh_reg_w - 1:0] corr_out_3;
output [2 * sh_reg_w - 1:0] corr_out_4;
wire [2 * sh_reg_w - 1:0] corr_out_4;
output [2 * sh_reg_w - 1:0] corr_out_5;
wire [2 * sh_reg_w - 1:0] corr_out_5;
output [2 * sh_reg_w - 1:0] corr_out_6;
wire [2 * sh_reg_w - 1:0] corr_out_6;
output [2 * sh_reg_w - 1:0] corr_out_7;
wire [2 * sh_reg_w - 1:0] corr_out_7;
output [2 * sh_reg_w - 1:0] corr_out_8;
wire [2 * sh_reg_w - 1:0] corr_out_8;
output [2 * sh_reg_w - 1:0] corr_out_9;
wire [2 * sh_reg_w - 1:0] corr_out_9;
output [2 * sh_reg_w - 1:0] corr_out_10;
wire [2 * sh_reg_w - 1:0] corr_out_10;
wire [sh_reg_w - 1:0] d_l_1_nrm;
wire [sh_reg_w - 1:0] d_l_2_nrm;
wire [sh_reg_w - 1:0] d_r_1_nrm;
wire [sh_reg_w - 1:0] d_r_2_nrm;
wrapper_norm norm_inst_left (
.clk(clk),
.nd(wen),
.din_1(d_l_1),
.din_2(d_l_2),
.dout_1(d_l_1_nrm),
.dout_2(d_l_2_nrm)
);
wrapper_norm norm_inst_right (
.clk(clk),
.nd(wen),
.din_1(d_r_1),
.din_2(d_r_2),
.dout_1(d_r_1_nrm),
.dout_2(d_r_2_nrm)
);
wrapper_corr_10 corr_5_inst (
.clk(clk),
.wen(wen),
.d_l_1(d_l_1_nrm),
.d_l_2(d_l_2_nrm),
.d_r_1(d_r_1_nrm),
.d_r_2(d_r_2_nrm),
.corr_out_0(corr_out_0),
.corr_out_1(corr_out_1),
.corr_out_2(corr_out_2),
.corr_out_3(corr_out_3),
.corr_out_4(corr_out_4),
.corr_out_5(corr_out_5),
.corr_out_6(corr_out_6),
.corr_out_7(corr_out_7),
.corr_out_8(corr_out_8),
.corr_out_9(corr_out_9),
.corr_out_10(corr_out_10)
);
endmodule
| 6.699338 |
module wrapper_norm_corr_5_seq (
clk,
wen,
d_l_1,
d_l_2,
d_r_1,
d_r_2,
corr_out_0,
corr_out_1,
corr_out_2,
corr_out_3,
corr_out_4,
corr_out_5
);
parameter sh_reg_w = 4'b1000;
input clk;
input wen;
input [15:0] d_l_1;
input [15:0] d_l_2;
input [15:0] d_r_1;
input [15:0] d_r_2;
output [2 * sh_reg_w - 1:0] corr_out_0;
wire [2 * sh_reg_w - 1:0] corr_out_0;
output [2 * sh_reg_w - 1:0] corr_out_1;
wire [2 * sh_reg_w - 1:0] corr_out_1;
output [2 * sh_reg_w - 1:0] corr_out_2;
wire [2 * sh_reg_w - 1:0] corr_out_2;
output [2 * sh_reg_w - 1:0] corr_out_3;
wire [2 * sh_reg_w - 1:0] corr_out_3;
output [2 * sh_reg_w - 1:0] corr_out_4;
wire [2 * sh_reg_w - 1:0] corr_out_4;
output [2 * sh_reg_w - 1:0] corr_out_5;
wire [2 * sh_reg_w - 1:0] corr_out_5;
wire [sh_reg_w - 1:0] d_l_1_nrm;
wire [sh_reg_w - 1:0] d_l_2_nrm;
wire [sh_reg_w - 1:0] d_r_1_nrm;
wire [sh_reg_w - 1:0] d_r_2_nrm;
wrapper_norm_seq norm_inst_left (
.clk(clk),
.nd(wen),
.din_1(d_l_1),
.din_2(d_l_2),
.dout_1(d_l_1_nrm),
.dout_2(d_l_2_nrm)
);
wrapper_norm_seq norm_inst_right (
.clk(clk),
.nd(wen),
.din_1(d_r_1),
.din_2(d_r_2),
.dout_1(d_r_1_nrm),
.dout_2(d_r_2_nrm)
);
wrapper_corr_5_seq corr_5_inst (
.tm3_clk_v0(clk),
.wen(wen),
.d_l_1(d_l_1_nrm),
.d_l_2(d_l_2_nrm),
.d_r_1(d_r_1_nrm),
.d_r_2(d_r_2_nrm),
.corr_out_0(corr_out_0),
.corr_out_1(corr_out_1),
.corr_out_2(corr_out_2),
.corr_out_3(corr_out_3),
.corr_out_4(corr_out_4),
.corr_out_5(corr_out_5)
);
endmodule
| 6.699338 |
module wrapper_corr_5_seq (
tm3_clk_v0,
wen,
d_l_1,
d_l_2,
d_r_1,
d_r_2,
corr_out_0,
corr_out_1,
corr_out_2,
corr_out_3,
corr_out_4,
corr_out_5
);
parameter sh_reg_w = 4'b1000;
input tm3_clk_v0;
input wen;
input [7:0] d_l_1;
input [7:0] d_l_2;
input [7:0] d_r_1;
input [7:0] d_r_2;
output [15:0] corr_out_0;
reg [15:0] corr_out_0;
output [15:0] corr_out_1;
reg [15:0] corr_out_1;
output [15:0] corr_out_2;
reg [15:0] corr_out_2;
output [15:0] corr_out_3;
reg [15:0] corr_out_3;
output [15:0] corr_out_4;
reg [15:0] corr_out_4;
output [15:0] corr_out_5;
reg [15:0] corr_out_5;
wire [sh_reg_w - 1:0] out_r1;
wire [sh_reg_w - 1:0] out_01;
wire [sh_reg_w - 1:0] out_11;
wire [sh_reg_w - 1:0] out_21;
wire [sh_reg_w - 1:0] out_31;
wire [sh_reg_w - 1:0] out_41;
wire [sh_reg_w - 1:0] out_51;
wire [sh_reg_w - 1:0] out_r2;
wire [sh_reg_w - 1:0] out_02;
wire [sh_reg_w - 1:0] out_12;
wire [sh_reg_w - 1:0] out_22;
wire [sh_reg_w - 1:0] out_32;
wire [sh_reg_w - 1:0] out_42;
wire [sh_reg_w - 1:0] out_52;
wire [2 * sh_reg_w - 1:0] corr_out_0_tmp;
wire [2 * sh_reg_w - 1:0] corr_out_1_tmp;
wire [2 * sh_reg_w - 1:0] corr_out_2_tmp;
wire [2 * sh_reg_w - 1:0] corr_out_3_tmp;
wire [2 * sh_reg_w - 1:0] corr_out_4_tmp;
wire [2 * sh_reg_w - 1:0] corr_out_5_tmp;
sh_reg inst_sh_reg_r_1 (
tm3_clk_v0,
wen,
d_r_1,
d_r_2,
out_r1,
out_r2
);
sh_reg inst_sh_reg_0 (
tm3_clk_v0,
wen,
d_l_1,
d_l_2,
out_01,
out_02
);
sh_reg inst_sh_reg_1 (
tm3_clk_v0,
wen,
out_01,
out_02,
out_11,
out_12
);
sh_reg inst_sh_reg_2 (
tm3_clk_v0,
wen,
out_11,
out_12,
out_21,
out_22
);
sh_reg inst_sh_reg_3 (
tm3_clk_v0,
wen,
out_21,
out_22,
out_31,
out_32
);
sh_reg inst_sh_reg_4 (
tm3_clk_v0,
wen,
out_31,
out_32,
out_41,
out_42
);
sh_reg inst_sh_reg_5 (
tm3_clk_v0,
wen,
out_41,
out_42,
out_51,
out_52
);
corr_seq inst_corr_0 (
tm3_clk_v0,
wen,
out_01,
out_02,
out_r1,
out_r2,
corr_out_0_tmp
);
corr_seq inst_corr_1 (
tm3_clk_v0,
wen,
out_11,
out_12,
out_r1,
out_r2,
corr_out_1_tmp
);
corr_seq inst_corr_2 (
tm3_clk_v0,
wen,
out_21,
out_22,
out_r1,
out_r2,
corr_out_2_tmp
);
corr_seq inst_corr_3 (
tm3_clk_v0,
wen,
out_31,
out_32,
out_r1,
out_r2,
corr_out_3_tmp
);
corr_seq inst_corr_4 (
tm3_clk_v0,
wen,
out_41,
out_42,
out_r1,
out_r2,
corr_out_4_tmp
);
corr_seq inst_corr_5 (
tm3_clk_v0,
wen,
out_51,
out_52,
out_r1,
out_r2,
corr_out_5_tmp
);
always @(posedge tm3_clk_v0) begin
if (wen == 1'b1) begin
corr_out_0 <= corr_out_0_tmp;
corr_out_1 <= corr_out_1_tmp;
corr_out_2 <= corr_out_2_tmp;
corr_out_3 <= corr_out_3_tmp;
corr_out_4 <= corr_out_4_tmp;
corr_out_5 <= corr_out_5_tmp;
end else begin
corr_out_0 <= corr_out_0;
corr_out_1 <= corr_out_1;
corr_out_2 <= corr_out_2;
corr_out_3 <= corr_out_3;
corr_out_4 <= corr_out_4;
corr_out_5 <= corr_out_5;
end
end
endmodule
| 6.720326 |
module wrapper_norm_seq (
clk,
nd,
din_1,
din_2,
dout_1,
dout_2
);
parameter sh_reg_w = 4'b1000;
input clk;
input nd;
input [15:0] din_1;
input [15:0] din_2;
output [sh_reg_w - 1:0] dout_1;
wire [sh_reg_w - 1:0] dout_1;
output [sh_reg_w - 1:0] dout_2;
wire [sh_reg_w - 1:0] dout_2;
reg [15:0] din_1_reg;
reg [15:0] din_2_reg;
reg [15:0] din_1_tmp1;
reg [15:0] din_2_tmp1;
reg [15:0] din_1_tmp2;
reg [15:0] din_2_tmp2;
reg [15:0] addin_1;
reg [15:0] addin_2;
reg [16:0] add_out;
my_wrapper_divider my_div_inst_1 (
nd,
clk,
din_1_tmp2,
add_out,
dout_1
);
my_wrapper_divider my_div_inst_2 (
nd,
clk,
din_2_tmp2,
add_out,
dout_2
);
always @(posedge clk) begin
if (nd == 1'b1) begin
din_1_reg <= din_1;
din_2_reg <= din_2;
end else begin
din_1_reg <= din_1_reg;
din_2_reg <= din_2_reg;
end
din_1_tmp1 <= din_1_reg;
din_1_tmp2 <= din_1_tmp1;
din_2_tmp1 <= din_2_reg;
din_2_tmp2 <= din_2_tmp1;
if ((din_1_reg[15]) == 1'b0) begin
addin_1 <= din_1_reg;
end else begin
addin_1 <= 16'b0000000000000000 - din_1_reg;
end
if ((din_2_reg[15]) == 1'b0) begin
addin_2 <= din_2_reg + 16'b0000000000000001;
end else begin
addin_2 <= 16'b0000000000000001 - din_2_reg;
end
add_out <= ({addin_1[15], addin_1}) + ({addin_2[15], addin_2});
end
endmodule
| 6.699338 |
module my_wrapper_divider (
rst,
clk,
data_in_a,
data_in_b,
data_out
);
parameter INPUT_WIDTH_A = 5'b10000;
parameter INPUT_WIDTH_B = 5'b10001;
parameter OUTPUT_WIDTH = 4'b1000;
parameter S1 = 2'b00;
parameter S2 = 2'b01;
parameter S3 = 2'b10;
parameter S4 = 2'b11;
input rst;
input clk;
input [INPUT_WIDTH_A-1:0] data_in_a;
input [INPUT_WIDTH_B-1:0] data_in_b;
output [OUTPUT_WIDTH-1:0] data_out;
wire [OUTPUT_WIDTH-1:0] data_out;
wire [OUTPUT_WIDTH-1:0] Remainder;
reg start, LA, EB;
wire Done;
reg [1:0] y, Y;
my_divider my_divider_inst (
clk,
rst,
start,
LA,
EB,
data_in_a,
data_in_b,
Remainder,
data_out,
Done
);
always @(posedge clk) begin
if (rst == 0) y <= S1;
else y <= Y;
end
always @(y) begin
case (y)
S1: begin
LA = 0;
EB = 0;
start = 0;
Y = S2;
end
S2: begin
LA = 1;
EB = 1;
start = 0;
Y = S3;
end
S3: begin
LA = 0;
EB = 0;
start = 1;
Y = S4;
end
S4: begin
LA = 0;
EB = 0;
start = 0;
if (Done == 1'b1) begin
Y = S1;
end else begin
Y = S4;
end
end
endcase
end
endmodule
| 7.258611 |
module my_divider (
clk,
rst,
start,
LA,
EB,
data_in_a,
data_in_b,
Remainder,
data_out,
Done
);
parameter INPUT_WIDTH_A = 5'b10000;
parameter INPUT_WIDTH_B = 5'b10001;
parameter OUTPUT_WIDTH = 4'b1000;
parameter LOGN = 3'b100;
parameter S1 = 2'b00;
parameter S2 = 2'b01;
parameter S3 = 2'b10;
input clk;
input [INPUT_WIDTH_A-1:0] data_in_a;
input [INPUT_WIDTH_B-1:0] data_in_b;
input rst;
input start;
input LA;
input EB;
output [OUTPUT_WIDTH-1:0] data_out;
wire [OUTPUT_WIDTH-1:0] data_out;
output [OUTPUT_WIDTH-1:0] Remainder;
reg [OUTPUT_WIDTH-1:0] Remainder;
output Done;
reg Done;
wire Cout, zero;
wire [INPUT_WIDTH_A-1:0] Sum;
reg [1:0] y, Y;
reg [LOGN-1:0] Count;
reg EA, Rsel, LR, ER, ER0, LC, EC;
reg [INPUT_WIDTH_B-1:0] RegB;
reg [INPUT_WIDTH_A-1:0] DataA;
reg ff0;
always @(start or y or zero) begin
case (y)
S1: begin
if (start == 0) Y = S1;
else Y = S2;
end
S2: begin
if (zero == 0) Y = S2;
else Y = S3;
end
S3: begin
if (start == 1) Y = S3;
else Y = S1;
end
default: begin
Y = 2'b00;
end
endcase
end
always @(posedge clk) begin
if (rst == 0) y <= S1;
else y <= Y;
end
always @(y or start or Cout or zero) begin
case (y)
S1: begin
LC = 1;
ER = 1;
EC = 0;
Rsel = 0;
Done = 0;
if (start == 0) begin
LR = 1;
ER0 = 1;
EA = 0;
end else begin
LR = 0;
EA = 1;
ER0 = 1;
end
end
S2: begin
LC = 0;
ER = 1;
Rsel = 1;
Done = 0;
ER0 = 1;
EA = 1;
if (Cout) LR = 1;
else LR = 0;
if (zero == 0) EC = 1;
else EC = 0;
end
S3: begin
Done = 1;
LR = 0;
LC = 0;
ER = 0;
EC = 0;
Rsel = 0;
ER0 = 0;
EA = 0;
end
default: begin
Done = 0;
LR = 0;
LC = 0;
ER = 0;
EC = 0;
Rsel = 0;
ER0 = 0;
EA = 0;
end
endcase
end
always @(posedge clk) begin
if (rst == 1) begin
RegB <= 0;
Remainder <= 0;
DataA <= 0;
ff0 <= 0;
Count <= 0;
end else begin
if (EB == 1) begin
RegB <= data_in_b;
end else begin
RegB <= RegB;
end
if (LR == 1) begin
Remainder <= Rsel ? Sum : 0;
end else if (ER == 1) begin
Remainder <= (Remainder << 1) | ff0;
end else begin
Remainder <= Remainder;
end
if (LA == 1) begin
DataA <= data_in_a;
end else if (EA == 1) begin
DataA <= (DataA << 1) | Cout;
end else begin
DataA <= DataA;
end
if (ER0 == 1) begin
ff0 <= DataA[INPUT_WIDTH_A-1];
end else begin
ff0 <= 0;
end
if (LC == 1) begin
Count <= 0;
end else if (EC == 1) begin
Count <= Count + 1;
end else begin
Count <= Count;
end
end
end
assign zero = (Count == 0);
assign Sum = {Remainder, ff0} + (~RegB + 1);
assign Cout = Sum[INPUT_WIDTH_A-1:0];
assign data_out = DataA;
endmodule
| 7.482014 |
module my_fir_f1 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=29,101,-15,-235,-15,101,29;
//parameter `WIDTH = 5'b10000;
input clk;
input [`WIDTH_5B - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_data_ready;
reg [`WIDTH_5B - 1:0] n_delay_reg1;
reg [`WIDTH_5B - 1:0] n_delay_reg2;
reg [`WIDTH_5B - 1:0] n_delay_reg3;
reg [`WIDTH_5B - 1:0] n_delay_reg4;
reg [`WIDTH_5B - 1:0] n_delay_reg5;
reg [`WIDTH_5B - 1:0] n_delay_reg6;
always @(posedge clk) begin
if (new_data_rdy == 1'b1) begin
n_delay_reg1 <= din;
n_delay_reg2 <= n_delay_reg1;
n_delay_reg3 <= n_delay_reg2;
n_delay_reg4 <= n_delay_reg3;
n_delay_reg5 <= n_delay_reg4;
n_delay_reg6 <= n_delay_reg5;
output_data_ready <= 1'b1;
dout <= (din * `COEF0_b) +
(n_delay_reg1 * `COEF1_b) +
(n_delay_reg2 * `COEF2_b) +
(n_delay_reg3 * `COEF3_b) +
(n_delay_reg4 * `COEF4_b) +
(n_delay_reg5 * `COEF5_b) +
(n_delay_reg6 * `COEF6_b);
end else begin
output_data_ready <= 1'b0;
end
end
endmodule
| 7.162286 |
module my_fir_f2 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=4,42,163,255,163,42,4;
// parameter WIDTH = 5'b10000;
input clk;
input [`WIDTH_5B - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_data_ready;
reg [`WIDTH_5B - 1:0] n_delay_reg1;
reg [`WIDTH_5B - 1:0] n_delay_reg2;
reg [`WIDTH_5B - 1:0] n_delay_reg3;
reg [`WIDTH_5B - 1:0] n_delay_reg4;
reg [`WIDTH_5B - 1:0] n_delay_reg5;
reg [`WIDTH_5B - 1:0] n_delay_reg6;
always @(posedge clk) begin
if (new_data_rdy == 1'b1) begin
n_delay_reg1 <= din;
n_delay_reg2 <= n_delay_reg1;
n_delay_reg3 <= n_delay_reg2;
n_delay_reg4 <= n_delay_reg3;
n_delay_reg5 <= n_delay_reg4;
n_delay_reg6 <= n_delay_reg5;
output_data_ready <= 1'b1;
dout <= (din * `COEF0_c) +
(n_delay_reg1 * `COEF1_c) +
(n_delay_reg2 * `COEF2_c) +
(n_delay_reg3 * `COEF3_c) +
(n_delay_reg4 * `COEF4_c) +
(n_delay_reg5 * `COEF5_c) +
(n_delay_reg6 * `COEF6_c);
end else begin
output_data_ready <= 1'b0;
end
end
endmodule
| 7.093413 |
module my_fir_f3 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=-12,-77,-148,0,148,77,12;
// parameter `WIDTH = 5'b10000;
input clk;
input [`WIDTH_5B - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_data_ready;
reg [`WIDTH_5B - 1:0] n_delay_reg1;
reg [`WIDTH_5B - 1:0] n_delay_reg2;
reg [`WIDTH_5B - 1:0] n_delay_reg3;
reg [`WIDTH_5B - 1:0] n_delay_reg4;
reg [`WIDTH_5B - 1:0] n_delay_reg5;
reg [`WIDTH_5B - 1:0] n_delay_reg6;
always @(posedge clk) begin
if (new_data_rdy == 1'b1) begin
n_delay_reg1 <= din;
n_delay_reg2 <= n_delay_reg1;
n_delay_reg3 <= n_delay_reg2;
n_delay_reg4 <= n_delay_reg3;
n_delay_reg5 <= n_delay_reg4;
n_delay_reg6 <= n_delay_reg5;
output_data_ready <= 1'b1;
dout <= (din * `COEF0_d) +
(n_delay_reg1 * `COEF1_d) +
(n_delay_reg2 * `COEF2_d) +
(n_delay_reg4 * `COEF4_d) +
(n_delay_reg5 * `COEF5_d) +
(n_delay_reg6 * `COEF6_d);
end else begin
output_data_ready <= 1'b0;
end
end
endmodule
| 7.589128 |
module my_fir_h1 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=-15,25,193,0,-193,-25,15;
// parameter `WIDTH = 5'b10000;
input clk;
input [`WIDTH_5B - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_data_ready;
reg [`WIDTH_5B - 1:0] n_delay_reg1;
reg [`WIDTH_5B - 1:0] n_delay_reg2;
reg [`WIDTH_5B - 1:0] n_delay_reg3;
reg [`WIDTH_5B - 1:0] n_delay_reg4;
reg [`WIDTH_5B - 1:0] n_delay_reg5;
reg [`WIDTH_5B - 1:0] n_delay_reg6;
always @(posedge clk) begin
if (new_data_rdy == 1'b1) begin
n_delay_reg1 <= din;
n_delay_reg2 <= n_delay_reg1;
n_delay_reg3 <= n_delay_reg2;
n_delay_reg4 <= n_delay_reg3;
n_delay_reg5 <= n_delay_reg4;
n_delay_reg6 <= n_delay_reg5;
output_data_ready <= 1'b1;
dout <= (din * `COEF0_1) +
(n_delay_reg1 * `COEF1_1) +
(n_delay_reg2 * `COEF2_1) +
(n_delay_reg4 * `COEF4_1) +
(n_delay_reg5 * `COEF5_1) +
(n_delay_reg6 * `COEF6_1);
end else begin
output_data_ready <= 1'b0;
end
end
endmodule
| 7.258261 |
module my_fir_h2 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=4,42,163,255,163,42,4;
// parameter `WIDTH = 5'b10000;
input clk;
input [`WIDTH_5B - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_data_ready;
reg [`WIDTH_5B - 1:0] n_delay_reg1;
reg [`WIDTH_5B - 1:0] n_delay_reg2;
reg [`WIDTH_5B - 1:0] n_delay_reg3;
reg [`WIDTH_5B - 1:0] n_delay_reg4;
reg [`WIDTH_5B - 1:0] n_delay_reg5;
reg [`WIDTH_5B - 1:0] n_delay_reg6;
always @(posedge clk) begin
if (new_data_rdy == 1'b1) begin
n_delay_reg1 <= din;
n_delay_reg2 <= n_delay_reg1;
n_delay_reg3 <= n_delay_reg2;
n_delay_reg4 <= n_delay_reg3;
n_delay_reg5 <= n_delay_reg4;
n_delay_reg6 <= n_delay_reg5;
output_data_ready <= 1'b1;
dout <= (din * `COEF0_2) +
(n_delay_reg1 * `COEF1_2) +
(n_delay_reg2 * `COEF2_2) +
(n_delay_reg3 * `COEF3_2) +
(n_delay_reg4 * `COEF4_2) +
(n_delay_reg5 * `COEF5_2) +
(n_delay_reg6 * `COEF6_2);
end else begin
output_data_ready <= 1'b0;
end
end
endmodule
| 7.118788 |
module my_fir_h3 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=-9,-56,-109,0,109,56,9;
// parameter WIDTH = 5'b10000;
input clk;
input [`WIDTH_5B - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_data_ready;
reg [`WIDTH_5B - 1:0] n_delay_reg1;
reg [`WIDTH_5B - 1:0] n_delay_reg2;
reg [`WIDTH_5B - 1:0] n_delay_reg3;
reg [`WIDTH_5B - 1:0] n_delay_reg4;
reg [`WIDTH_5B - 1:0] n_delay_reg5;
reg [`WIDTH_5B - 1:0] n_delay_reg6;
always @(posedge clk) begin
if (new_data_rdy == 1'b1) begin
n_delay_reg1 <= din;
n_delay_reg2 <= n_delay_reg1;
n_delay_reg3 <= n_delay_reg2;
n_delay_reg4 <= n_delay_reg3;
n_delay_reg5 <= n_delay_reg4;
n_delay_reg6 <= n_delay_reg5;
output_data_ready <= 1'b1;
dout <= (din * `COEF0_3) +
(n_delay_reg1 * `COEF1_3) +
(n_delay_reg2 * `COEF2_3) +
(n_delay_reg4 * `COEF4_3) +
(n_delay_reg5 * `COEF5_3) +
(n_delay_reg6 * `COEF6_3);
end else begin
output_data_ready <= 1'b0;
end
end
endmodule
| 7.61466 |
module my_fir_h4 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=-9,-56,-109,0,109,56,9;
// parameter WIDTH = 5'b10000;
input clk;
input [`WIDTH_5B - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_data_ready;
reg [`WIDTH_5B - 1:0] n_delay_reg1;
reg [`WIDTH_5B - 1:0] n_delay_reg2;
reg [`WIDTH_5B - 1:0] n_delay_reg3;
reg [`WIDTH_5B - 1:0] n_delay_reg4;
reg [`WIDTH_5B - 1:0] n_delay_reg5;
reg [`WIDTH_5B - 1:0] n_delay_reg6;
always @(posedge clk) begin
if (new_data_rdy == 1'b1) begin
n_delay_reg1 <= din;
n_delay_reg2 <= n_delay_reg1;
n_delay_reg3 <= n_delay_reg2;
n_delay_reg4 <= n_delay_reg3;
n_delay_reg5 <= n_delay_reg4;
n_delay_reg6 <= n_delay_reg5;
output_data_ready <= 1'b1;
dout <= (din * `COEF0_4) +
(n_delay_reg1 * `COEF1_4) +
(n_delay_reg2 * `COEF2_4) +
(n_delay_reg4 * `COEF4_4) +
(n_delay_reg5 * `COEF5_4) +
(n_delay_reg6 * `COEF6_4);
end else begin
output_data_ready <= 1'b0;
end
end
endmodule
| 7.756091 |
module stereo_audio_parallelizer #(
parameter audio_width = 32
) (
input wire reset,
input wire clk,
input wire i_valid,
output reg i_ready,
input wire i_is_left,
input wire [audio_width-1:0] i_audio,
output wire o_valid,
input wire o_ready,
output reg [audio_width-1:0] o_left,
output reg [audio_width-1:0] o_right
);
assign o_valid = !i_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
i_ready <= 1'b1;
o_left <= 0;
o_right <= 0;
end else begin
if (i_ready) begin
if (i_valid) begin
if (i_is_left) o_left <= i_audio;
else o_right <= i_audio;
i_ready <= i_is_left;
end
end else i_ready <= o_ready;
end
end
endmodule
| 7.004634 |
module stereo_audio_parallelizer_tb ();
localparam CLK_TIME = 1000000000 / (44100 * 32) * 2; // 44.1KHz * 32 * 2
initial begin
$dumpfile("stereo_audio_parallelizer_tb.vcd");
$dumpvars;
end
reg clk;
initial begin
clk = 1'b0;
forever begin
#(CLK_TIME / 2) clk = ~clk;
end
end
reg reset;
reg i_valid;
wire i_ready;
reg i_is_left;
reg [31:0] i_audio;
wire o_valid;
reg o_ready;
wire [31:0] o_left;
wire [31:0] o_right;
integer intake_count = 0;
integer outlet_count = 0;
stereo_audio_parallelizer parallelizer_ (
.reset(reset),
.clk(clk),
.i_valid(i_valid),
.i_ready(i_ready),
.i_is_left(i_is_left),
.i_audio(i_audio),
.o_valid(o_valid),
.o_ready(o_ready),
.o_left(o_left),
.o_right(o_right)
);
task intake(input is_left, input reg [31:0] value);
begin
i_valid <= 1'b1;
i_is_left <= is_left;
i_audio <= value;
wait (i_ready) @(posedge clk);
i_valid <= 1'b0;
@(posedge clk);
intake_count++;
end
endtask
initial begin
o_ready <= 1'b0;
i_valid <= 1'b0;
reset = 1'b1;
repeat (2) @(posedge clk);
reset = 1'b0;
repeat (2) @(posedge clk);
intake(1'b1, 32'h00010000);
intake(1'b0, 32'h1fed1fed);
intake(1'b1, 32'h2eef2eef);
intake(1'b0, 32'h33333333);
intake(1'b1, 32'h12345678);
intake(1'b0, 32'h1fed1fed);
intake(1'b1, 32'h99911223);
intake(1'b0, 32'hABCDEF01);
intake(1'b1, 32'h55555555);
intake(1'b0, 32'h44444444);
wait (intake_count != outlet_count) @(posedge clk);
$finish();
end
always @(posedge clk or posedge reset) begin
if (reset) begin
o_ready <= 1'b1;
end else if (o_valid && o_ready) begin
$write("l = %08h / r = %08h\n", o_left, o_right);
o_ready <= 1'b0;
repeat (4) @(posedge clk);
o_ready <= 1'b1;
outlet_count += 2;
end
end
endmodule
| 7.004634 |
module stereo_audio_parallel_serial_tb ();
localparam CLK_TIME = 1000000000 / (44100 * 32) * 2; // 44.1KHz * 32 * 2
initial begin
$dumpfile("stereo_audio_parallel_serial_tb.vcd");
$dumpvars;
end
reg clk;
initial begin
clk = 1'b0;
forever begin
#(CLK_TIME / 2) clk = ~clk;
end
end
reg reset;
reg i_valid;
wire i_ready;
reg i_is_left;
reg [31:0] i_audio;
wire o_valid;
wire o_ready;
wire [31:0] o_left;
wire [31:0] o_right;
integer intake_count = 0;
integer outlet_count = 0;
stereo_audio_parallelizer parallelizer_ (
.reset(reset),
.clk(clk),
.i_valid(i_valid),
.i_ready(i_ready),
.i_is_left(i_is_left),
.i_audio(i_audio),
.o_valid(o_valid),
.o_ready(o_ready),
.o_left(o_left),
.o_right(o_right)
);
wire o_serial_valid;
reg o_serial_ready;
wire o_serial_is_left;
wire [31:0] o_serial_audio;
stereo_audio_serializer serializer_ (
.reset(reset),
.clk(clk),
.i_valid(o_valid),
.i_ready(o_ready),
.i_left(o_left),
.i_right(o_right),
.o_valid(o_serial_valid),
.o_ready(o_serial_ready),
.o_is_left(o_serial_is_left),
.o_audio(o_serial_audio)
);
task intake(input is_left, input reg [31:0] value);
begin
i_valid <= 1'b1;
i_is_left <= is_left;
i_audio <= value;
@(posedge clk);
if (!i_ready) wait (i_ready) @(posedge clk);
intake_count++;
end
endtask
initial begin
// o_ready <= 1'b0;
i_valid <= 1'b0;
reset = 1'b1;
repeat (2) @(posedge clk);
reset = 1'b0;
repeat (2) @(posedge clk);
intake(1'b1, 32'h00010000);
intake(1'b0, 32'h1fed1fed);
intake(1'b1, 32'h2eef2eef);
intake(1'b0, 32'h33333333);
intake(1'b1, 32'h12345678);
intake(1'b0, 32'h1fed1fed);
intake(1'b1, 32'h99911223);
intake(1'b0, 32'hABCDEF01);
intake(1'b1, 32'h55555555);
intake(1'b0, 32'h44444444);
@(posedge clk);
i_valid <= 1'b0;
wait (intake_count != outlet_count) @(posedge clk);
repeat (32) @(posedge clk);
$finish();
end
always @(posedge clk or posedge reset) begin
if (reset) begin
o_serial_ready <= 1'b1;
end else if (o_serial_valid && o_serial_ready) begin
$write("Outlet: is_left = %d / audio = %08h\n", o_serial_is_left, o_serial_audio);
outlet_count += 2;
end
end
endmodule
| 7.004634 |
module stereo_audio_serializer #(
parameter audio_width = 32
) (
input wire reset,
input wire clk,
input wire i_valid,
output reg i_ready,
input wire [audio_width-1:0] i_left,
input wire [audio_width-1:0] i_right,
output wire o_valid,
input wire o_ready,
output reg o_is_left,
output wire [audio_width-1:0] o_audio
);
reg [audio_width-1:0] right;
reg [audio_width-1:0] left;
assign o_audio = o_is_left ? left : right;
assign o_valid = !i_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
i_ready <= 1'b1;
o_is_left <= 1'b1;
right <= 0;
left <= 0;
end else begin
if (i_valid && i_ready) begin
i_ready <= 1'b0;
right <= i_right;
left <= i_left;
end else if (o_valid && o_ready) begin
o_is_left <= !o_is_left;
i_ready <= !o_is_left;
end
end
end
endmodule
| 7.004634 |
module stereo_audio_serializer_tb ();
localparam SCLK_TIME = 1000000000 / (44100 * 32) * 1; // 44.1KHz * 32
localparam lrclk_polarity = 1'b1;
localparam is_i2s = 1'b0;
localparam audio_width = 32;
initial begin
$dumpfile("stereo_audio_serializer_tb.vcd");
$dumpvars;
end
reg sclk;
initial begin
sclk = 1'b0;
forever begin
#(SCLK_TIME / 2) sclk = ~sclk;
end
end
reg reset;
reg aligned_i_valid;
wire aligned_i_ready;
reg [audio_width-1:0] aligned_i_left;
reg [audio_width-1:0] aligned_i_right;
wire aligned_o_valid;
reg aligned_o_ready;
wire aligned_o_is_left;
wire [audio_width-1:0] aligned_o_audio;
stereo_audio_serializer #(
.audio_width(audio_width)
) stereo_serializer_ (
.reset(reset),
.clk(sclk),
.i_valid(aligned_i_valid),
.i_ready(aligned_i_ready),
.i_left(aligned_i_left),
.i_right(aligned_i_right),
.o_valid(aligned_o_valid),
.o_ready(aligned_o_ready),
.o_is_left(aligned_o_is_left),
.o_audio(aligned_o_audio)
);
reg [31:0] encoder_audio;
reg encoder_is_left;
always @(posedge sclk or posedge reset) begin
if (reset) begin
aligned_o_ready <= 1'b1;
encoder_audio <= 0;
encoder_is_left <= 1'b0;
end else begin
if (aligned_o_valid && aligned_o_ready) begin
encoder_audio <= aligned_o_audio;
encoder_is_left <= aligned_o_is_left;
$write("deodoer: is_left = %d / audio = %08h\n", aligned_o_is_left, aligned_o_audio);
repeat (1) @(posedge sclk);
end
end
end
task out_data(input [audio_width-1:0] left, input [audio_width-1:0] right);
begin
aligned_i_left <= left;
aligned_i_right <= right;
aligned_i_valid <= 1'b1;
wait (aligned_i_ready) @(posedge sclk);
aligned_i_valid <= 1'b0;
@(posedge sclk);
end
endtask
initial begin
aligned_i_valid = 1'b0;
aligned_i_left = 16'hcccc;
aligned_i_right = 16'hdddd;
repeat (2) @(posedge sclk) reset = 1'b1;
repeat (20) @(posedge sclk) reset = 1'b0;
out_data(16'hABCD, 16'h0123);
out_data(16'h5555, 16'haaaa);
out_data(16'h3456, 16'h9321);
out_data(16'h6666, 16'h1111);
repeat (32) @(posedge sclk);
$finish();
end
endmodule
| 7.004634 |
module stereo_fm_mx (
input clock,
input reset,
input clken48kHz,
input clken192kHz,
input [3:0] Ks,
input [3:0] Kd,
input [3:0] Kp,
input [7:0] Kf,
input signed [17:0] LEFTin,
input signed [17:0] RIGHTin,
output signed [23:0] FMout
);
wire signed [17:0] LEFTout;
wire signed [17:0] RIGHTout;
wire signed [17:0] LEFT4xout;
wire signed [17:0] RIGHT4xout;
module48 module48_1 (
.clock(clock),
.reset(reset),
.enableclk(clken48kHz),
.LEFTin(LEFTin),
.RIGHTin(RIGHTin),
.LEFTout(LEFTout),
.RIGHTout(RIGHTout),
.Ks(Ks),
.Kd(Kd)
);
interpol4x interpolL (
.clock(clock),
.reset(reset),
.clkenin(clken48kHz),
.clken4x(clken192kHz),
.xkin(LEFTout),
.ykout(LEFT4xout)
);
interpol4x interpolR (
.clock(clock),
.reset(reset),
.clkenin(clken48kHz),
.clken4x(clken192kHz),
.xkin(RIGHTout),
.ykout(RIGHT4xout)
);
module192 module192_1 (
.clock(clock),
.reset(reset),
.enableclk(clken192kHz),
.LEFTin(LEFT4xout),
.RIGHTin(RIGHT4xout),
.FMout(FMout),
.Kp(Kp),
.Kf(Kf)
);
endmodule
| 6.660598 |
module stereo_tb ();
reg clk, reset;
reg [15:0] codec_sample;
wire [15:0] codec_sample_left;
wire [15:0] codec_sample_right;
stereo DUT (
.clk(clk),
.reset(reset),
.codec_sample(codec_sample),
.codec_sample_right(codec_sample_right),
.codec_sample_left(codec_sample_left)
);
// Clock and reset
initial begin
clk = 1'b0;
reset = 1'b1;
repeat (4) #5 clk = ~clk;
reset = 1'b0;
forever #5 clk = ~clk;
end
initial begin
#10 codec_sample = 16'b1000_0000_0000_1000;
#50000 $stop;
end
endmodule
| 7.627022 |
module stereo_vision_control (
input nRESET,
input CLK,
//
inout STEREO_SDA,
inout STEREO_SCL,
//
input MODE_CAMERA, // 0 master, 1 slave
//
input GAIN_TO_SLAVE,
output GAIN_FROM_MASTER,
input [31:0] INT_TIME_TO_SLAVE,
output [31:0] INT_TIME_FROM_MASTER,
input [31:0] ZOOM_TO_SLAVE,
output [31:0] ZOOM_FROM_MASTER
);
parameter [6:0] control_start_word = 42;
reg sda_in;
reg scl_in;
reg sda_out;
reg scl_out;
reg sda = 1;
//reg scl;
// Declare states of state machine
reg state_master;
parameter state_master_pause = 0, state_master_tx = 1;
reg state_slave;
parameter state_slave_pause = 0, state_slave_rx = 1;
reg [15:0] counter_master;
reg [15:0] counter_slave;
reg [71:0] data_input;
reg [71:0] data_out;
reg gain_from_master_reg;
reg [31:0] int_time_from_master_reg;
reg [31:0] zoom_from_master_reg;
assign GAIN_FROM_MASTER = gain_from_master_reg;
assign INT_TIME_FROM_MASTER = int_time_from_master_reg;
assign ZOOM_FROM_MASTER = zoom_from_master_reg;
assign STEREO_SDA = (!MODE_CAMERA) ? sda_out : 1'bz; // if master then STEREO_SDA <- sda_out
assign STEREO_SCL = (!MODE_CAMERA) ? scl_out : 1'bz; // if master then STEREO_SCL <- scl_out
always @(*) begin
if (MODE_CAMERA) begin
sda_in <= STEREO_SDA;
scl_in <= STEREO_SCL;
end else begin
sda_out <= sda;
scl_out <= CLK;
end
end
// i2c master proccess
always @(posedge CLK) begin
if ((nRESET) && (!MODE_CAMERA)) begin
case (state_master)
state_master_pause: begin
sda = 1;
data_out[0] = 0;
data_out[6:1] = control_start_word;
data_out[7] = GAIN_TO_SLAVE;
data_out[39:8] = INT_TIME_TO_SLAVE;
data_out[71:40] = ZOOM_TO_SLAVE;
if (counter_master < 50) begin
counter_master = counter_master + 1;
end else begin
counter_master = 0;
state_master <= state_master_tx;
end
end
state_master_tx: begin
if (counter_master < 72) begin
sda = data_out[counter_master];
counter_master = counter_master + 1;
end else begin
sda = 1;
counter_master = 0;
state_master <= state_master_pause;
end
end
default: begin
counter_master = 0;
state_master <= state_master_pause;
end
endcase
end else begin
sda = 1;
counter_master = 0;
state_master <= state_master_pause;
end
end
// i2c SLAVE proccess
always @(posedge scl_in) begin
if ((nRESET) && (MODE_CAMERA)) begin
case (state_slave)
state_slave_pause: begin
if (data_input[6:1] == control_start_word) begin
gain_from_master_reg = data_input[7];
int_time_from_master_reg = data_input[39:8];
zoom_from_master_reg = data_input[71:40];
end
if (!sda_in) begin
data_input[0] = sda_in;
counter_slave = 1;
state_slave <= state_slave_rx;
end
end
state_slave_rx: begin
if (counter_slave < 72) begin
data_input[counter_slave] = sda_in;
counter_slave = counter_slave + 1;
end else begin
counter_slave = 0;
state_slave <= state_slave_pause;
end
end
default: begin
counter_slave = 0;
state_slave <= state_slave_pause;
end
endcase
end
end
endmodule
| 6.843168 |
module sterm (
input wire clk,
input wire [7:0] rdata,
input wire rdempty,
input wire [15:0] q,
output wire [15:0] wdata,
output wire [12:0] wadr,
output wire wr,
output wire [12:0] radr,
output wire ack
);
parameter SCR_STRIDE = 128; /* number of chars in line*/
parameter SCR_WIDTH = 80; /* number of visible chars in line */
parameter SCR_HEIGHT = 56; /* number of screen lines */
localparam STATE_WAIT_CHAR = 0; /* wait until char appear from FIFO */
localparam STATE_WRITE_CHAR = 1; /* write received char into screen */
localparam STATE_SCROLL = 2; /* scroll whole screen */
reg [1:0] state = STATE_WAIT_CHAR;
//catch received byte from fifo
reg [7:0] rbyte;
assign ack = (rdempty == 0 && state == STATE_WAIT_CHAR);
always @(posedge clk) if (ack) rbyte <= rdata;
wire wr_single_byte;
assign wr_single_byte = (state == STATE_WRITE_CHAR && rbyte != 8'h0D && rbyte != 8'h0A);
wire scrolled;
assign scrolled = (scroll_rd_adr == ((SCR_HEIGHT + 1) * SCR_STRIDE));
wire wr_scroll;
assign wr_scroll = (state == STATE_SCROLL && ~scrolled);
reg [7:0] line_addr = 0;
always @(posedge clk)
if (state == STATE_SCROLL) line_addr <= 0;
else if (wr_single_byte) begin
if (tab_char) line_addr <= (line_addr + 5) & 8'hFC;
else line_addr <= (line_addr + 1);
end
//in case of TAB char write SPACE char
wire tab_char;
assign tab_char = (rbyte == 8'h09);
wire [7:0] rbyte_;
assign rbyte_ = tab_char ? 8'h20 : rbyte;
assign wdata = wr_single_byte ? {8'h1F, rbyte_} : q;
assign wr = wr_single_byte || scroll_wr_cycle;
assign wadr = wr_scroll ? scroll_wr_adr : (line_addr + (SCR_HEIGHT - 1) * SCR_STRIDE);
reg [12:0] scroll_rd_adr;
reg [12:0] scroll_wr_adr;
reg scroll_rd_cycle;
wire scroll_wr_cycle;
assign scroll_wr_cycle = ~scroll_rd_cycle;
assign radr = scroll_rd_adr;
always @(posedge clk) begin
if (state == STATE_SCROLL) begin
scroll_rd_cycle <= scroll_rd_cycle ^ 1;
scroll_rd_adr <= scroll_rd_adr + scroll_rd_cycle;
scroll_wr_adr <= scroll_wr_adr + scroll_wr_cycle;
end else begin
scroll_rd_adr <= SCR_STRIDE;
scroll_wr_adr <= 0;
scroll_rd_cycle <= 1;
end
end
always @(posedge clk) begin
case (state)
STATE_WAIT_CHAR: begin
//wait for received byte
if (rdempty == 0) state <= STATE_WRITE_CHAR;
end
STATE_WRITE_CHAR: begin
if (rbyte == 8'h0D) state <= STATE_SCROLL; //should scroll
else state <= STATE_WAIT_CHAR; //should write byte and wait next
end
STATE_SCROLL: begin
//scroll screen
if (scrolled) state <= STATE_WAIT_CHAR;
end
endcase
end
endmodule
| 6.905827 |
module PROG_COUNTER (
BCLK,
BRESET,
NEW,
LOAD_PC,
NEW_PC,
NEXT_ADR,
NEXT_PCA,
DISP,
PC_NEW,
USED,
USER,
SAVE_PC,
FPU_TRAP,
ADIVAR,
PC_ARCHI,
PC_ICACHE,
PC_SAVE,
ALSB,
IC_USER
);
input BCLK, BRESET;
input NEW;
input LOAD_PC;
input NEW_PC;
input NEXT_ADR;
input NEXT_PCA;
input [31:0] DISP;
input [31:0] PC_NEW;
input [2:0] USED;
input USER;
input SAVE_PC;
input FPU_TRAP;
input ADIVAR;
output [31:0] PC_ARCHI; // goes to Datapath
output [31:0] PC_ICACHE;
output [31:0] PC_SAVE; // is the return address
output [1:0] ALSB;
output IC_USER;
reg [31:0] PC_ARCHI;
reg [31:0] pc_adduse;
reg [31:0] pc_ic_reg;
reg [31:0] fpu_trap_pc;
reg IC_USER;
wire [31:0] branch, pc_jump, pc_icache_i;
assign PC_SAVE = pc_adduse + {29'h0, USED};
assign branch = PC_ARCHI + DISP;
assign pc_jump = LOAD_PC ? PC_NEW : branch;
always @(posedge BCLK or negedge BRESET)
if (!BRESET) pc_adduse <= 32'h0;
else pc_adduse <= NEW ? pc_jump : PC_SAVE; // Only at NEW is the DISP correct !
// The Architectur - PC : Address mode "Programm Memory"-relativ
// no BRESET because NEXT_PCA is immediately valid
always @(posedge BCLK)
if (FPU_TRAP) PC_ARCHI <= fpu_trap_pc; // go back !
else if (NEXT_PCA) PC_ARCHI <= pc_adduse;
always @(posedge BCLK)
if (SAVE_PC)
fpu_trap_pc <= PC_ARCHI; // Special storage for PC for FPU Trap
always @(posedge BCLK or negedge BRESET)
if (!BRESET) pc_ic_reg <= 32'h0;
else pc_ic_reg <= pc_icache_i;
// NEW is only one cycle long - but in pc_adduse is the PC stored when ACC_OK is not there and therefore NEW_PC
// is used to initiate a new access in ICACHE
assign pc_icache_i = NEW_PC ? (NEW ? pc_jump : pc_adduse) : (NEXT_ADR ? ({pc_ic_reg[31:2],2'b00} + 32'h0000_0004) : pc_ic_reg);
// This MUX is extra for LMR IVAR,... and CINV build in
assign PC_ICACHE = {(ADIVAR ? PC_NEW[31:4] : pc_icache_i[31:4]), pc_icache_i[3:0]};
assign ALSB = pc_ic_reg[1:0]; // for OPDEC_REG
// The IC_USER flag is allowed to switch synchronously with one cycle delay to PC_ICACHE
always @(posedge BCLK or negedge BRESET)
if (!BRESET) IC_USER <= 1'b0;
else if (NEW_PC) IC_USER <= USER;
endmodule
| 7.080149 |
module REG_LIST (
DIN,
IPOS,
INIT,
OPOS,
VALID
);
// Detects set bits in register list for SAVE/RESTORE & ENTER/EXIT
input [7:0] DIN;
input [2:0] IPOS;
input INIT;
output [2:0] OPOS;
output VALID;
reg [7:1] filter;
wire [7:0] mdat_0;
wire [3:0] mdat_1;
always @(IPOS or DIN)
case (IPOS)
3'd0: filter = DIN[7:1];
3'd1: filter = {DIN[7:2], 1'b0};
3'd2: filter = {DIN[7:3], 2'b0};
3'd3: filter = {DIN[7:4], 3'b0};
3'd4: filter = {DIN[7:5], 4'b0};
3'd5: filter = {DIN[7:6], 5'b0};
3'd6: filter = {DIN[7], 6'b0};
3'd7: filter = 7'b0;
endcase
assign mdat_0 = INIT ? DIN : {filter, 1'b0};
assign OPOS[2] = (mdat_0[3:0] == 4'h0);
assign mdat_1 = OPOS[2] ? mdat_0[7:4] : mdat_0[3:0];
assign OPOS[1] = (mdat_1[1:0] == 2'b00);
assign OPOS[0] = ~((mdat_1[2:1] == 2'b10) | mdat_1[0]);
assign VALID = (mdat_1 != 4'b0000);
endmodule
| 6.811924 |
module ste_joypad (
input [15:0] joy, // R3,L3,R2,L2
// R,L,Y,X
// Start, Select, B, A
// UDLR
input [ 3:0] din, // pins 1-4
output reg [ 7:0] dout, // pins 11-14, 1-4
output reg [ 1:0] buttons // pins 10,6
);
// To account for users with a procontroller,
// X is mapped to 9, Y to 8 and Z to 7.
// L and R are mapped to 4 and 6 respectively.
always @(*) begin
dout = 8'hff;
buttons = 2'b11;
//#0*U
dout[4] = ~(/*(~din[3] & joy[xx]) | (~din[2] & joy[xx]) | (~din[1] & joy[xx]) |*/ (~din[0] & joy[3]));
//987D
dout[5] = ~((~din[3] & joy[8]) | (~din[2] & joy[9]) | (~din[1] & joy[12]) | (~din[0] & joy[2]));
//654L
dout[6] = ~((~din[3] & joy[11]) |/* (~din[2] & joy[xx]) |*/ (~din[1] & joy[10]) | (~din[0] & joy[1]));
//321R
dout[7] = ~(/*(~din[3] & joy[xx]) | (~din[2] & joy[xx]) | (~din[1] & joy[xx]) |*/ (~din[0] & joy[0]));
//OCBA
buttons[1] = ~((~din[3] & joy[7]) | (~din[2] & joy[6]) | (~din[1] & joy[5]) | (~din[0] & joy[4]));
//Pause
buttons[0] = ~((~din[0] & joy[13]));
end
endmodule
| 7.426012 |
module ste_joystick (
// system interface
input clk,
input reset,
// cpu register interface
input [15:0] din,
input sel,
input [ 4:0] addr,
input uds,
input lds,
input rw,
output reg [15:0] dout
);
// no functionality implemented yet
always @(sel, rw, uds, lds, addr) begin
dout = 16'h0000;
if (sel && rw) begin
if (addr == 5'h00) dout = 16'hffff; // no fire button pressed
if (addr == 5'h01) dout = 16'hffff; // no direction set
end
end
endmodule
| 7.088991 |
module STFT #(
parameter TWIDDLE_FILE = "/home/saviour/study/fpga_spectrogram/src/stft/factor.txt",
WORD_WIDTH = 16,
FFT_SIZE = 256
) (
input wire clk,
input wire SAMPLE_VALID, //FROM I2S RECEIVER
input wire signed [23:0] SAMPLE, // FROM I2S RECEIVER
input wire reset,
output wire wr_en,
output wire [$clog2(FFT_SIZE)-1:0] wr_idx,
output wire [WORD_WIDTH*2-1:0] wr_data
);
wire [WORD_WIDTH-1:0] o_SAMPLE;
wire start_compute;
//in an ideal world, I would isolate the path for the disp_wr_en signal
//it's too tightly coupled with the stft as is
//but that would mean having to handle buffers and delays explicitly
//Will try to decouple when logic is good
STFT_CONTROL #(
.word_width(16),
.FFT_SIZE (FFT_SIZE)
) this_stft_control (
.clk(clk), //27Mhz
.RESET(reset),
.SAMPLE_VALID(SAMPLE_VALID), // from i2s clock domain
.i_SAMPLE(SAMPLE), // from i2s clock domain
.o_SAMPLE(o_SAMPLE),
.start_compute(start_compute)
);
wire signed [15:0] sample_diff;
wire sample_wr_en;
wire [$clog2(FFT_SIZE)-1:0] oldest_sample_address;
wire [$clog2(FFT_SIZE)-1:0] dft_idx;
wire dft_wr_en;
wire [WORD_WIDTH-1:0] oldest_sample;
STFT_SM #(
.WORD_WIDTH(16),
.FFT_SIZE (FFT_SIZE)
) this_stft_sm (
.clk(clk),
.reset(reset),
.start_compute(start_compute),
.SAMPLE(o_SAMPLE),
.OLDEST_SAMPLE(oldest_sample),
.sample_diff(sample_diff),
.sample_wr_en(sample_wr_en),
.oldest_sample_address(oldest_sample_address),
.idx(dft_idx), // TO TWIDDLE ADDRESS GENERATION UNIT
.wr_en(dft_wr_en)
);
iRAM #(
.WORD_WIDTH(WORD_WIDTH),
.ADDRESS_WIDTH($clog2(FFT_SIZE))
) SAMPLE_RAM (
.clk(clk),
.wr_en(sample_wr_en),
.wr_data(o_SAMPLE),
.wr_addr(oldest_sample_address),
.rd_addr(oldest_sample_address),
.rd_data(oldest_sample)
);
wire [WORD_WIDTH*2-1:0] Xk_prev, Xk, twiddle;
wire o_dft_wr_en;
wire [$clog2(FFT_SIZE)-1:0] o_dft_idx;
twiddleROM #(
.N(FFT_SIZE),
.word_size(WORD_WIDTH),
.memory_file(TWIDDLE_FILE)
) this_twiddleROM (
.read_address(dft_idx),
.twiddle(twiddle)
);
SPU #(
.WORD_WIDTH(WORD_WIDTH),
.FFT_SIZE (FFT_SIZE)
) this_SPU (
.clk(clk),
.sample_diff(sample_diff),
.twiddle(twiddle),
.Xk_prev(Xk_prev),
.wr_en(dft_wr_en),
.o_wr_en(o_dft_wr_en),
.i_idx(dft_idx),
.Xk(Xk),
.o_idx(o_dft_idx)
);
iRAM #(
.WORD_WIDTH(2 * WORD_WIDTH),
.ADDRESS_WIDTH($clog2(FFT_SIZE))
) FFT_RAM (
.clk(clk),
.wr_en(o_dft_wr_en),
.wr_data(Xk),
.wr_addr(o_dft_idx),
.rd_addr(dft_idx),
.rd_data(Xk_prev)
);
assign wr_en = o_dft_wr_en;
assign wr_idx = o_dft_idx;
assign wr_data = Xk;
initial begin
$dumpfile("stft.vcd");
$dumpvars(0, STFT);
end
endmodule
| 6.716928 |
module stft2RAM #(
parameter COUNT_HIGH = 20,
FFT_SIZE = 256,
WORD_WIDTH = 16,
NO_FFTS = 50,
ADDRESS_WIDTH = 12,
NO_BANKS = 2
) (
input wire clk, //27MHz
input wire reset,
input wire wr_en,
input wire [$clog2(FFT_SIZE/2)-1:0] idx,
input wire [WORD_WIDTH*2-1:0] i_data,
output reg [$clog2(NO_FFTS)-1:0] OLDEST_FFT_IDX,
output reg disp_wr_en,
output wire [NO_BANKS-1:0] bank_wr,
output wire [ADDRESS_WIDTH-1:0] addr_wr,
output reg [3:0] data_wr
);
wire pulse;
wire count_true;
//COMBINATIONAL **yes, I see the clk, lol**
//All necessary signals are ready before hand
pulseDetectCount #(
.COUNTHIGH(COUNT_HIGH)
) thisPulseDetectCount (
.clk(clk),
.reset(reset),
.wr_en(wr_en),
.count_true(count_true),
.pulse(pulse)
);
always @(posedge clk) disp_wr_en <= wr_en && count_true;
// 1 clk cycle delay
// assign DIN = i_data[2*WORD_WIDTH-1-:23];
// always @(posedge clk) begin
// data_wr <= DOUT[7-:4];
// end
magnitudeAndLog #(
.WORD_WIDTH(WORD_WIDTH)
) thisMagnitudeAndLog (
.clk(clk),
.Xk (i_data),
.log(data_wr)
);
// 1 cycle delay
idx2RAM #(
.ADDRESS_WIDTH(ADDRESS_WIDTH),
.NO_FFTS(NO_FFTS),
.FFT_SIZE(FFT_SIZE),
.NO_BANKS(NO_BANKS)
) thisidx2RAM (
.clk(clk),
.FFT_IDX(OLDEST_FFT_IDX), //write newest dft to location of oldest fft
.sample_idx(idx),
.bank_select(bank_wr),
.wr_address(addr_wr)
);
//READY BEFORE HAND
always @(posedge clk) begin
if (reset) begin
OLDEST_FFT_IDX <= 0;
end else begin
if (pulse && count_true) begin
if (OLDEST_FFT_IDX == 0) OLDEST_FFT_IDX <= NO_FFTS - 1;
else OLDEST_FFT_IDX <= OLDEST_FFT_IDX - 1'b1;
end else;
end
end
// initial begin
// $dumpfile("stft2RAM.vcd");
// $dumpvars(0, stft2RAM);
// end
endmodule
| 6.645288 |
module STFT_SM #(
parameter WORD_WIDTH = 16,
FFT_SIZE = 256
) (
input wire clk,
reset,
input wire start_compute,
input wire signed [WORD_WIDTH-1:0] SAMPLE,
input wire signed [WORD_WIDTH-1:0] OLDEST_SAMPLE,
output reg signed [WORD_WIDTH-1:0] sample_diff,
output reg sample_wr_en,
output reg [$clog2(FFT_SIZE)-1:0] oldest_sample_address,
output reg [$clog2(FFT_SIZE)-1:0] idx, // TO TWIDDLE ADDRESS GENERATION UNIT
output reg wr_en
);
reg [WORD_WIDTH-1:0] SAMPLE_RAM[FFT_SIZE-1:0];
reg [1:0] COMPUTE_STATE;
localparam IDLE = 2'b00;
localparam BUSY = 2'b10;
always @(posedge clk) begin
if (reset) begin
idx <= 0;
wr_en <= 0;
COMPUTE_STATE <= IDLE;
oldest_sample_address <= FFT_SIZE - 1;
end else begin
case (COMPUTE_STATE)
IDLE: begin
idx <= 0;
wr_en <= 0;
if (start_compute) begin
COMPUTE_STATE <= BUSY;
wr_en <= 1'b1;
sample_diff <= -SAMPLE + OLDEST_SAMPLE;
sample_wr_en <= 1'b1;
end
end
BUSY: begin
sample_wr_en <= 1'b0;
idx <= idx + 1'b1;
if (&idx) begin
COMPUTE_STATE <= IDLE;
wr_en <= 0;
oldest_sample_address <= (oldest_sample_address + 1'b1);
end
end
default: COMPUTE_STATE <= IDLE;
endcase
end
end
endmodule
| 6.930028 |
module stickyRound (
sign,
lsb,
guard,
round,
sticky,
rndMode,
rndUp
);
input sign, lsb, guard, round, sticky;
input [1:0] rndMode;
output rndUp;
wire signComp, rndPos, rndNeg, rndNearEven, andOp1, andOp2, andOp3, orOp;
not n (signComp, sign);
or o (orOp, guard, round);
and a1 (andOp1, signComp, orOp);
and a2 (andOp2, sign, orOp);
and a3 (andOp3, lsb, guard);
mux_2_1 m1 (
andOp1,
signComp,
sticky,
rndPos
);
mux_2_1 m2 (
andOp2,
sign,
sticky,
rndNeg
);
mux_2_1 m3 (
andOp3,
guard,
sticky,
rndNearEven
);
mux_4_1 m4 (
1'b0,
rndPos,
rndNeg,
rndNearEven,
rndMode[1],
rndMode[0],
rndUp
);
endmodule
| 6.920456 |
module mux_4_1 (
a,
b,
c,
d,
s1,
s2,
y
);
input a, b, c, d, s1, s2;
output y;
assign y = ((~s1) & (~s2) & a) | ((~s1) & (s2) & b) | ((s1) & (~s2) & c) | ((s1) & (s2) & d);
endmodule
| 8.152157 |
module sticky_bit (
input wire CLK,
RST,
input wire [22:0] leastbits,
input wire Mul_MSB,
input wire Ez_add_MSB,
output wire sticky
);
reg Mul_MSB_f; //Mul_MSB_ff ;
reg Ez_add_MSB_f1, Ez_add_MSB_f2, Ez_add_MSB_f3;
reg [22:0] leastbits_f;
assign sticky = (Mul_MSB_f || Ez_add_MSB_f3) ? |leastbits_f : |leastbits_f[21:0];
always @(posedge CLK or negedge RST) begin
if (!RST) begin
////////inputs RST
Mul_MSB_f <= 0;
//Mul_MSB_ff <= 0;
Ez_add_MSB_f1 <= 0;
Ez_add_MSB_f2 <= 0;
Ez_add_MSB_f3 <= 0;
leastbits_f <= 0;
end else begin
////////inputs Reg
Mul_MSB_f <= Mul_MSB;
//Mul_MSB_ff <= Mul_MSB_f;
Ez_add_MSB_f1 <= Ez_add_MSB;
Ez_add_MSB_f2 <= Ez_add_MSB_f1;
Ez_add_MSB_f3 <= Ez_add_MSB_f2;
leastbits_f <= leastbits;
end
end
endmodule
| 7.575018 |
module comparator #(
parameter DW = 8
) (
input wire [DW - 1:0] inp,
input wire substract,
input wire clk,
output wire [DW - 1:0] out_max,
output reg [DW - 1:0] out_min
);
//wire [DW - 1: 0] out_min_in;
// wire [DW - 1: 0] out_max_in;
reg [DW - 1:0] max;
initial max = 0;
always @(inp, max)
if (inp > max) begin
out_min <= max;
max <= inp;
end else begin
out_min <= inp;
max <= max;
end
// always @ (posedge clk) begin
//if (substract == 1'b1)begin // these lines do not play any effect
// max[0] <= 0;
//end
// end
//assign out_min = out_min_in;
assign out_max = max;
endmodule
| 7.565129 |
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