code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module step3 (
input clk25MHz,
input up,
input down,
input right,
input left,
input [3:0] step_2,
input [2:0] secim1,
input [2:0] es1,
output reg [2:0] secim2
);
parameter [2:0] kare0=3'b000, kare1=3'b001, kare2=3'b010, kare3=3'b011, kare4=3'b100, kare5=3'b101, kare6=3'b110, kare7=3'b111;
integer mover = 0;
always @(posedge clk25MHz) begin
if (step_2 == 4'b0011) begin
if (mover == 0) begin
mover = 1;
if ((secim1 == kare0) || (secim1 == kare6)) secim2 = kare1;
else secim2 = kare0;
end
if (up) begin
if (mover == 1) begin
mover = 2;
if (secim2 == kare0) secim2 = kare5;
else if (secim2 == kare1) secim2 = kare6;
else if (secim2 == kare2) secim2 = kare7;
else if (secim2 == kare3) secim2 = kare4;
else if (secim2 == kare4) secim2 = kare0;
else if (secim2 == kare5) secim2 = kare1;
else if (secim2 == kare6) secim2 = kare2;
else if (secim2 == kare7) secim2 = kare3;
end
end else if (down) begin
if (mover == 1) begin
mover = 2;
if (secim2 == 3'b000) secim2 = kare4;
else if (secim2 == 3'b001) secim2 = kare5;
else if (secim2 == 3'b010) secim2 = kare6;
else if (secim2 == 3'b011) secim2 = kare7;
else if (secim2 == 3'b100) secim2 = kare1;
else if (secim2 == 3'b101) secim2 = kare2;
else if (secim2 == 3'b110) secim2 = kare3;
else if (secim2 == 3'b111) secim2 = kare0;
end
end else if (right) begin
if (mover == 1) begin
mover = 2;
if (secim2 == 3'b000) secim2 = kare1;
else if (secim2 == 3'b001) secim2 = kare2;
else if (secim2 == 3'b010) secim2 = kare3;
else if (secim2 == 3'b011) secim2 = kare4;
else if (secim2 == 3'b100) secim2 = kare5;
else if (secim2 == 3'b101) secim2 = kare6;
else if (secim2 == 3'b110) secim2 = kare7;
else if (secim2 == 3'b111) secim2 = kare0;
end
end else if (left) begin
if (mover == 1) begin
mover = 2;
if (secim2 == 3'b000) secim2 = kare7;
else if (secim2 == 3'b001) secim2 = kare0;
else if (secim2 == 3'b010) secim2 = kare1;
else if (secim2 == 3'b011) secim2 = kare2;
else if (secim2 == 3'b100) secim2 = kare3;
else if (secim2 == 3'b101) secim2 = kare4;
else if (secim2 == 3'b110) secim2 = kare5;
else if (secim2 == 3'b111) secim2 = kare6;
end
end else mover = 1;
if (secim1 == secim2 || es1 == secim2) mover = 1;
end
end
endmodule
| 6.695704 |
module step3_loop (
input clk,
rst,
output reg [7:0] led
);
always @(posedge clk or posedge rst) begin
if (rst) led <= 8'b0000_0111;
else led <= {led[6:0], led[7]};
end
endmodule
| 7.004172 |
module top (
input [7:0] sw,
output reg [2:0] led,
output error
);
assign error = ~(|sw);
always @(*) begin
if (sw[7]) led = 3'b111;
else if (sw[6]) led = 3'b110;
else if (sw[5]) led = 3'b101;
else if (sw[4]) led = 3'b100;
else if (sw[3]) led = 3'b011;
else if (sw[2]) led = 3'b010;
else if (sw[1]) led = 3'b001;
else if (sw[0]) led = 3'b000;
else led = 3'b000;
end
endmodule
| 7.233807 |
module step4 (
input clk25MHz,
input up,
input down,
input right,
input left,
input [3:0] step_2,
input [2:0] secim1,
input [2:0] secim2,
input [2:0] es1,
output reg [2:0] es2
);
parameter [2:0] kare0=3'b000, kare1=3'b001, kare2=3'b010, kare3=3'b011, kare4=3'b100, kare5=3'b101, kare6=3'b110, kare7=3'b111;
integer mover = 0;
initial es2 <= kare0;
always @(posedge clk25MHz) begin
if (step_2 == 4'b0100) begin
if (mover == 0) begin
mover = 1;
if ((secim1 == kare0) || (es1 == kare0) || (secim2 == kare0))
if ((secim1 == kare1) || (es1 == kare1) || (secim2 == kare1)) es2 = kare2;
else es2 = kare1;
else es2 = kare0;
end
if (up) begin
if (mover == 1) begin
mover = 2;
if (es2 == kare0) es2 = kare5;
else if (es2 == kare1) es2 = kare6;
else if (es2 == kare2) es2 = kare7;
else if (es2 == kare3) es2 = kare4;
else if (es2 == kare4) es2 = kare0;
else if (es2 == kare5) es2 = kare1;
else if (es2 == kare6) es2 = kare2;
else if (es2 == kare7) es2 = kare3;
end
end else if (down) begin
if (mover == 1) begin
mover = 2;
if (es2 == 3'b000) es2 = kare4;
else if (es2 == 3'b001) es2 = kare5;
else if (es2 == 3'b010) es2 = kare6;
else if (es2 == 3'b011) es2 = kare7;
else if (es2 == 3'b100) es2 = kare1;
else if (es2 == 3'b101) es2 = kare2;
else if (es2 == 3'b110) es2 = kare3;
else if (es2 == 3'b111) es2 = kare0;
end
end else if (right) begin
if (mover == 1) begin
mover = 2;
if (es2 == 3'b000) es2 = kare1;
else if (es2 == 3'b001) es2 = kare2;
else if (es2 == 3'b010) es2 = kare3;
else if (es2 == 3'b011) es2 = kare4;
else if (es2 == 3'b100) es2 = kare5;
else if (es2 == 3'b101) es2 = kare6;
else if (es2 == 3'b110) es2 = kare7;
else if (es2 == 3'b111) es2 = kare0;
end
end else if (left) begin
if (mover == 1) begin
mover = 2;
if (es2 == 3'b000) es2 = kare7;
else if (es2 == 3'b001) es2 = kare0;
else if (es2 == 3'b010) es2 = kare1;
else if (es2 == 3'b011) es2 = kare2;
else if (es2 == 3'b100) es2 = kare3;
else if (es2 == 3'b101) es2 = kare4;
else if (es2 == 3'b110) es2 = kare5;
else if (es2 == 3'b111) es2 = kare6;
end
end else mover = 1;
if (secim1 == es2 || es1 == es2 || secim2 == es2) mover = 1;
end
end
endmodule
| 6.953996 |
module stepdir #(
parameter MOVE_TYPE_KLIPPER = 3'b000,
parameter MOVE_TYPE_BITS = 0,
parameter STEP_INTERVAL_BITS = 0,
parameter STEP_COUNT_BITS = 0,
parameter STEP_ADD_BITS = 0,
parameter MOVE_COUNT = 0
) (
input wire clk,
input wire [MOVE_TYPE_BITS + STEP_INTERVAL_BITS + STEP_COUNT_BITS + STEP_ADD_BITS + 1 - 1:0] queue_wr_data,
input wire queue_wr_en,
output wire queue_empty,
input wire dedge,
input wire do_reset_clock,
input wire [31:0] reset_clock,
input wire [31:0] clock,
input wire reset,
output reg step = 0,
output reg dir = 0,
output reg [31:0] position = 0,
output wire [31:0] next_step_time,
output reg missed_clock = 0,
output wire queue_full,
output wire [$clog2(MOVE_COUNT)-1:0] elemcnt,
output wire [15:0] debug
);
localparam DATA_WIDTH = MOVE_TYPE_BITS + STEP_INTERVAL_BITS + STEP_COUNT_BITS + STEP_ADD_BITS + 1;
localparam MOVE_ADDR_BITS = $clog2(MOVE_COUNT);
wire [DATA_WIDTH-1:0] queue_rd_data;
reg queue_rd_en = 0;
fifo #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(MOVE_ADDR_BITS)
) u_fifo (
.clk(clk),
.clr(reset),
.din(queue_wr_data),
.wr_en(queue_wr_en),
.full(queue_full),
.dout(queue_rd_data),
.rd_en(queue_rd_en),
.empty(queue_empty),
.elemcnt(elemcnt)
);
/*
* queue is 100 bits wide:
* <dir:1> <interval:32> <count:32> <add:32> <move type:3>
*
* move type has to be last, otherwise yosys won't infer block ram.
* This has to do with the fact that we don't use the move_type yet.
*/
/* for convenient access */
wire [MOVE_TYPE_BITS-1:0] q_move_type;
wire [STEP_INTERVAL_BITS-1:0] q_interval;
wire q_dir;
wire [STEP_COUNT_BITS-1:0] q_count;
wire [STEP_ADD_BITS-1:0] q_add;
assign {q_dir, q_interval, q_count, q_add, q_move_type} = queue_rd_data;
reg [STEP_INTERVAL_BITS-1:0] interval = 0;
reg [STEP_COUNT_BITS-1:0] count = 0;
reg [STEP_ADD_BITS-1:0] add = 0;
wire [STEP_INTERVAL_BITS-1:0] signed_add = {
{(STEP_INTERVAL_BITS - STEP_ADD_BITS) {add[STEP_ADD_BITS-1]}}, add
};
reg [31:0] next_step = 0;
reg next_dir = 0;
reg delayed_reset = 0;
assign next_step_time = next_step;
reg [2:0] step_delay = 0;
always @(posedge clk) begin
if (queue_rd_en) queue_rd_en <= 0;
if (count == 0 && !queue_empty && !delayed_reset && !reset) begin
/*
* currently this condition is only here to make use of all bits
* of the fifo. Otherwise yosys won't infer a block ram for it
*/
count <= q_count;
add <= q_add;
interval <= q_interval;
next_step <= next_step + q_interval;
next_dir <= q_dir;
queue_rd_en <= 1;
/* check if next_step + q_interval is behind sysclock. if so, set error flag */
if (next_step + q_interval - clock >= 32'hc0000000) missed_clock <= 1;
end else if (count != 0 && clock == next_step) begin
count <= count - 1;
if (count != 1) begin
interval <= interval + signed_add;
next_step <= next_step + interval + signed_add;
end else if (!queue_empty) begin
count <= q_count;
add <= q_add;
interval <= q_interval;
next_step <= next_step + q_interval;
next_dir <= q_dir;
queue_rd_en <= 1;
end
if (dedge) step <= !step;
else step <= 1;
step_delay <= 7;
if (dir) position <= position + 1;
else position <= position - 1;
end
if (do_reset_clock) next_step <= reset_clock;
if (step_delay) begin
step_delay <= step_delay - 1;
end else begin
if (!dedge && step) step <= 0;
dir <= next_dir;
end
if (reset) begin
count <= 0;
/*
* because queue_empty is delayed by one slot, we also need
* to delay our check of it
*/
delayed_reset <= 1;
end
if (delayed_reset) delayed_reset <= 0;
end
assign debug[8:0] = elemcnt;
assign debug[15:9] = next_step[31:25];
endmodule
| 8.015169 |
module stepgen (
clk,
enable,
position,
velocity,
dirtime,
steptime,
step,
dir,
tap
);
`define STATE_STEP 0
`define STATE_DIRCHANGE 1
`define STATE_DIRWAIT 2
parameter W = 12;
parameter F = 10;
parameter T = 5;
input clk, enable;
output [W+F-1:0] position;
reg [W+F-1:0] position;
input [F:0] velocity;
input [T-1:0] dirtime, steptime;
input [1:0] tap;
output step, dir;
reg step, dir;
reg [T-1:0] timer;
reg [1:0] state;
reg ones;
wire dbit = velocity[F];
wire pbit = (tap == 0 ? position[F]
: (tap == 1 ? position[F+1]
: (tap == 2 ? position[F+2]
: position[F+3])));
wire [W+F-1:0] xvelocity = {{W{velocity[F]}}, {1{velocity[F-1:0]}}};
`ifdef TESTING
// for testing:
initial position = 1'b0;
initial state = `STATE_STEP;
initial timer = 0;
initial dir = 0;
initial ones = 0;
`endif
always @(posedge clk) begin
if (enable) begin
// $display("state=%d timer=%d position=%h velocity=%h dir=%d dbit=%d pbit=%d ones=%d", state, timer, position, xvelocity, dir, dbit, pbit, ones);
if ((dir != dbit) && (pbit == ones)) begin
if (state == `STATE_DIRCHANGE) begin
if (timer == 0) begin
dir <= dbit;
timer <= dirtime;
state <= `STATE_DIRWAIT;
end else begin
timer <= timer - 1'd1;
end
end else begin
if (timer == 0) begin
step <= 0;
timer <= dirtime;
state <= `STATE_DIRCHANGE;
end else begin
timer <= timer - 1'd1;
end
end
end else if (state == `STATE_DIRWAIT) begin
if (timer == 0) begin
state <= `STATE_STEP;
end else begin
timer <= timer - 1'd1;
end
end else begin
if (timer == 0) begin
if (pbit != ones) begin
ones <= pbit;
step <= 1'd1;
timer <= steptime;
end else begin
step <= 0;
end
end else begin
timer <= timer - 1'd1;
end
if (dir == dbit) position <= position + xvelocity;
end
end
end
endmodule
| 8.620791 |
module full_adder__0_476 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_472 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_467 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_463 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_496 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_492 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_487 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_483 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_516 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_512 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_507 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_503 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_536 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_532 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_527 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_523 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_556 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_552 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_547 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_543 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_576 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_572 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_567 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_563 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_596 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_592 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_587 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_583 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_616 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_612 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_607 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_603 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1387 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
INV_X1 i_3 (
.A (i_bit1),
.ZN(o_sum)
);
endmodule
| 6.521523 |
module full_adder__0_1383 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1412 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_453 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
endmodule
| 6.521523 |
module full_adder__0_1156 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1152 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1147 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1143 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1176 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1172 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1167 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1163 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1196 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1192 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1187 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1183 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1216 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1212 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1207 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1203 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1236 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1232 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1227 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1223 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1256 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1252 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1247 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1243 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1276 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1272 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1267 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1263 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1296 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1292 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1287 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1283 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1316 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1312 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1307 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1303 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1336 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1332 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1327 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1323 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1356 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1352 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1347 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1343 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1376 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit1),
.B (i_bit2),
.ZN(o_sum)
);
endmodule
| 6.521523 |
module full_adder__0_1367 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
endmodule
| 6.521523 |
module full_adder__0_1107 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
INV_X1 i_3 (
.A (i_bit1),
.ZN(o_sum)
);
endmodule
| 6.521523 |
module full_adder__0_1103 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1573 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1555 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1535 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1515 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1495 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1475 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1455 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_1435 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
endmodule
| 6.521523 |
module full_adder__0_627 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carry)
);
endmodule
| 6.521523 |
module full_adder__0_623 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B(i_carry),
.Z(o_sum)
);
AOI22_X1 i_0_2 (
.A1(n_0_1),
.A2(i_carry),
.B1(i_bit1),
.B2(i_bit2),
.ZN(n_0_0)
);
INV_X1 i_0_3 (
.A (n_0_0),
.ZN(o_carry)
);
endmodule
| 6.521523 |
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