code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module test_lattice_sim;
wire [27:0] SUM;
reg ADDNSUB, SignA, SignB, CLK0, CE0, RST0;
reg [9:0] A0;
reg [16:0] B0;
reg [9:0] A1;
reg [16:0] B1;
wire VCCI_sig = 1;
GSR GSR_INST (.GSR(VCCI_sig));
PUR PUR_INST (.PUR(VCCI_sig));
integer index;
integer maddsub_10x17_dynamic_vlog_gen_out;
parameter width = 60, pattern = 68, step = 95;
reg [1:width] mem[1:pattern];
maddsub_10x17_dynamic_vlog post (
.ADDNSUB(ADDNSUB),
.SignA(SignA),
.SignB(SignB),
.CLK0(CLK0),
.CE0(CE0),
.RST0(RST0),
.SUM(SUM),
.A0(A0),
.B0(B0),
.A1(A1),
.B1(B1)
);
initial begin
maddsub_10x17_dynamic_vlog_gen_out = $fopen("./maddsub_10x17_dynamic_vlog.sim");
$readmemb("maddsub_10x17_dynamic_vlog.in", mem);
for (index = 1; index <= pattern; index = index + 1) begin
#5{A0, B0, A1, B1, ADDNSUB, SignA, SignB, CE0, RST0, CLK0} = mem[index];
//#step $display ($time, " %b_%b_%b_%b_%b_%b_%b_%b%b%b %b", A0,B0,A1,B1,ADDNSUB,SignA,SignB,CE0,RST0,CLK0,SUM);
#5
$fdisplay(
maddsub_10x17_dynamic_vlog_gen_out,
" %d %b%b%b%b%b%b%b%b%b%b %b",
index,
A0,
B0,
A1,
B1,
ADDNSUB,
SignA,
SignB,
CE0,
RST0,
CLK0,
SUM
);
end
end
endmodule
| 6.812784 |
module: ThreeInputExorGate
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module stimulus2;
// Inputs
reg i1;
reg i2;
reg i3;
// Outputs
wire Output;
integer i;
integer j;
// Instantiate the Unit Under Test (UUT)
ThreeInputExorGate uut (
.i1(i1),
.i2(i2),
.i3(i3),
.Output(Output)
);
initial begin
// Initialize Inputs
i1 = 0;
i2 = 0;
i3 = 0;
// Wait 100 ns for global reset to finish
#100;
end
always @ (i1,i2,i3)
begin
//generate truth table
for (i= 0 ; i < 8 ; i =i + 1 )
#10 {i1,i2,i3}= i ;
#10 $stop;
end
// for (i = 0; i < 8 ; i = i+1)
// begin : Xor_block
// always $monitor("i=%d",i);
// always #1 i1 = ~i1;
// always #2 i2 = ~i2;
// always #3 i3 = ~i3;
// end
// Add stimulus here
/* #50 i1 = 1;
#50 i1 = 0;
#60 i3 = 1; */
initial begin
for (j=0 ; j<8 ; j=j+1)begin
$monitor("Output=%d, i1=%d, i2=%d, i3=%d\n",Output,i1,i2,i3);
end
end
endmodule
| 7.231613 |
module stimulus_trisc ();
parameter ncs = 3;
parameter cw = (1 << ncs) - 1; //number of conditional inputs (cw+1 must be a power of 2)
parameter ow = 28; //control output size
reg [cw-1:0] cond;
wire [ow-1:0] out_sig;
reg clk;
reg reset_n;
trisc processor (
cond,
out_sig,
clk,
reset_n
);
initial begin
clk = 0;
reset_n = 1;
cond = 0;
#1 reset_n = 0;
#1 reset_n = 1;
cond = 1;
end
always #5 clk = ~clk;
endmodule
| 7.379504 |
module stim_code;
// Parameters
parameter MODE = 1; // 0->query; 1->ref
parameter bitwidth = 16;
parameter SQG_SIZE = 250;
parameter REF_SIZE = 29898;
// Module IO
reg clk = 0;
reg rst;
reg running;
reg [31:0] ref_len = REF_SIZE;
reg op_mode;
wire busy;
wire load_done;
wire src_fifo_rden;
reg src_fifo_empty;
wire [15:0] src_fifo_data;
reg [14:0] src_fifo_addr;
wire sink_fifo_wren;
reg sink_fifo_full;
wire [31:0] sink_fifo_data;
reg started;
/* IO assignment */
// Reference FIFO
stim_mem #(
.init_mode(MODE)
) inst_stim_mem (
.clk(clk),
.addrR(src_fifo_addr),
.addrW(15'b0),
.wren(1'b0),
.datain(16'b0),
.dataout(src_fifo_data)
);
dtw_core #(
.dtw_dwidth(bitwidth),
.axi_dwidth(32),
.SQG_SIZE (SQG_SIZE),
.init_ref (0)
) inst_dtw_core (
.clk (clk),
.rst (rst),
.rs (running),
.ref_len (ref_len),
.op_mode (op_mode),
.busy (busy),
.load_done(load_done),
.src_fifo_rden (src_fifo_rden),
.src_fifo_empty(src_fifo_empty),
.src_fifo_data ({16'b0, src_fifo_data}),
.sink_fifo_wren(sink_fifo_wren),
.sink_fifo_full(sink_fifo_full),
.sink_fifo_data(sink_fifo_data)
);
// Clock gen
always #5 clk = ~clk;
//assign src_fifo_empty = 1'b0;
always begin
src_fifo_empty <= 1'b0;
#65 src_fifo_empty <= 1'b1;
#10 src_fifo_empty <= 1'b0;
#5 src_fifo_empty <= 1'b0;
end
always @(posedge clk) begin
if (rst) begin
src_fifo_addr <= 0;
end else if (!src_fifo_empty && started && src_fifo_rden) begin
src_fifo_addr <= src_fifo_addr + 1;
end
end
initial begin
rst = 1;
running = 0;
started = 0;
op_mode = MODE;
sink_fifo_full = 1'b0;
#20 rst = 0;
running = 1;
started = 1;
#1000000 $finish;
end
endmodule
| 6.712298 |
module aastim_final;
reg [2:0] req_floor1, req_floor2;
reg clk;
reg [10:0] weight;
reg [7:0] temperature_input;
wire [1:0] fan_speed;
wire [11:0] fan_rpm;
wire [2:0] powerlevel_1, powerlevel_2;
wire [7:0] turnover1, turnover2;
wire [1:0] direction1, direction2;
wire complete1, complete2;
wire over_weight1, over_weight2;
wire [2:0] out_floor1, out_floor2;
wire [6:0] segment1, segment2;
integer temp_log, temp_log_;
main_ m1 (
req_floor1,
req_floor2,
weight,
clk,
complete1,
complete2,
direction1,
direction2,
over_weight1,
over_weight2,
out_floor1,
out_floor2,
powerlevel_1,
powerlevel_2,
fan_speed,
fan_rpm,
temperature_input,
turnover1,
turnover2,
segment1,
segment2
);
initial begin
#2 clk = 1'b0;
end
always begin
#1 clk = ~clk;
end
always begin
temp_log_ = $fscanf(temp_log, "%d", temperature_input);
#5;
end
initial begin
temp_log = $fopen("temp_readings.log", "r");
//normal
/*req_floor1=3;temperature_input=30;weight=250;req_floor2=3;
#1; req_floor1=5;temperature_input=40;weight=500;req_floor2=5;
#4; req_floor1=4;temperature_input=20;weight=350;req_floor2=4;
#8 req_floor1=7;temperature_input=30;weight=250;req_floor2=7;*/
//diff between algorithms turnover better for 2nd
req_floor1 = 4;
temperature_input = 30;
weight = 250;
req_floor2 = 4;
#1 req_floor1 = 7;
temperature_input = 20;
weight = 350;
req_floor2 = 7;
#5 req_floor1 = 2;
temperature_input = 40;
weight = 500;
req_floor2 = 2;
//overweight
/*req_floor1=4;temperature_input=30;weight=250;req_floor2=4;
#2 req_floor1=7;temperature_input=20;weight=1000;req_floor2=7;
#3 req_floor1=2;temperature_input=40;weight=500;req_floor2=2;*/
//turnover better for 1st
/*req_floor1=3;temperature_input=40;weight=500;req_floor2=3;
#1 req_floor1=7;temperature_input=40;weight=200;req_floor2=7;
#3 req_floor1=1;temperature_input=40;weight=700;req_floor2=1;
#10 req_floor1=2;temperature_input=50;weight=500;
#10 req_floor2=2;*/
req_floor1 = 4;
temperature_input = 45;
weight = 300;
req_floor2 = 4;
#2 req_floor1 = 2;
temperature_input = 45;
weight = 500;
req_floor2 = 2;
#2 req_floor1 = 1;
temperature_input = 60;
weight = 700;
req_floor2 = 1;
#2 req_floor1 = 6;
temperature_input = 45;
weight = 400;
req_floor2 = 6;
#2 req_floor1 = 2;
temperature_input = 70;
weight = 300;
req_floor2 = 2;
end
endmodule
| 6.946558 |
module stitcher (
input clk,
input rst_n,
input left_data_valid,
input [ 7:0] left_data,
input right_data_valid,
input [ 7:0] right_data,
input keypoint_valid,
input [31:0] left_keypoint,
input [31:0] right_keypoint,
output data_valid,
output [ 7:0] data
);
reg [7:0] L_DATA[0:(3*N*M - 1)];
reg [7:0] R_DATA[0:(3*N*M - 1)];
reg [7:0] IMAGE[0:(6*N*M - 1)];
reg [7:0] pixel_value;
reg [7:0] out;
reg [2:0] PS, NS;
parameter IDLE = 3'b000, STORE = 3'b001, LOAD = 3'b010, COMPUTE = 3'b011, BLEND = 3'b100, DISPLAY = 3'b101;
parameter N = 450, M = 450;
integer i, j, k, p, q, o, row1, row2, col1, col2, ref_keypoint1, ref_keypoint2;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) PS <= IDLE;
else PS <= NS;
end
always @(posedge clk) begin
if (left_data_valid) begin
L_DATA[i] <= left_data;
i <= i + 1;
end else i <= i;
end
always @(posedge clk) begin
if (right_data_valid) begin
R_DATA[i] <= right_data;
j <= j + 1;
end else j <= j;
end
always @(left_data_valid, right_data_valid, left_data, right_data, keypoint_valid, PS) begin
case (PS)
IDLE: begin
i = 0;
j = 0;
k = 0;
p = 0;
q = 0;
o = 0;
row1 = 0;
row2 = 0;
col1 = 0;
col2 = 0;
ref_keypoint1 = 0;
ref_keypoint2 = 0;
pixel_value = 0;
for (p = 0; p < 6 * N * M; p = p + 1) begin
IMAGE[p] = 0;
end
if (left_data_valid || right_data_valid) NS = STORE;
else NS = IDLE;
end
STORE: begin
NS = (i == 3 * N * M - 1 && j == 3 * N * M - 1) ? LOAD : STORE;
end
LOAD: begin
ref_keypoint1 = (keypoint_valid == 1'b1) ? left_keypoint : ref_keypoint1;
ref_keypoint2 = (keypoint_valid == 1'b1) ? right_keypoint : ref_keypoint2;
NS = (keypoint_valid == 1'b1) ? COMPUTE : LOAD;
end
COMPUTE: begin
row1 = ref_keypoint1 / M;
row2 = ref_keypoint2 / M;
col1 = 3 * (ref_keypoint1 - (row1 * M));
col2 = 3 * (ref_keypoint2 - (row2 * M));
NS = BLEND;
end
BLEND: begin
pixel_value = (q <= col1) ? L_DATA[q+(o*3*M)] : R_DATA[col2+(q-col1)+(o*3*M)];
IMAGE[q+(6*o*M)] = pixel_value;
o = (q == (((3 * M) - col2) + col1) - 1) ? o + 1 : o;
q = (q == (((3 * M) - col2) + col1) - 1) ? 0 : q + 1;
NS = DISPLAY;
end
DISPLAY: begin
out = IMAGE[k];
k = k + 1;
NS = (k == 6 * N * M) ? IDLE : BLEND;
end
endcase
end
assign data_valid = (PS == DISPLAY) ? 1'b1 : 1'b0;
assign data = (PS == DISPLAY) ? out : 8'hzz;
endmodule
| 6.850973 |
module STI_DAC (
clk,
reset,
load,
pi_data,
pi_length,
pi_fill,
pi_msb,
pi_low,
pi_end,
so_data,
so_valid,
oem_finish,
oem_dataout,
oem_addr,
odd1_wr,
odd2_wr,
odd3_wr,
odd4_wr,
even1_wr,
even2_wr,
even3_wr,
even4_wr
);
input [15:0] pi_data;
input [1:0] pi_length;
output [7:0] oem_dataout;
output [4:0] oem_addr;
input clk, reset, load, pi_fill, pi_msb, pi_low, pi_end;
output so_data, so_valid, oem_finish, odd1_wr, odd2_wr, odd3_wr, odd4_wr,
even1_wr, even2_wr, even3_wr, even4_wr;
wire n2, _read_done, _out_done, _mem_done;
wire [2:0] _cur_state;
BUFX12 U1 (
.A(n2),
.Y(so_data)
);
CTRL CTRL (
.clk(clk),
.reset(reset),
.pi_end(pi_end),
.read_done(_read_done),
.out_done(_out_done),
.mem_done(_mem_done),
.cur_state(_cur_state),
.so_valid(so_valid),
.oem_finish(oem_finish)
);
PROC PROC (
.clk(clk),
.reset(reset),
.cur_state(_cur_state),
.load(load),
.pi_data(pi_data),
.pi_length(pi_length),
.pi_fill(pi_fill),
.pi_msb(pi_msb),
.pi_low(pi_low),
.read_done(_read_done),
.out_done(_out_done),
.so_data(n2)
);
DAC DAC (
.clk(clk),
.reset(reset),
.cur_state(_cur_state),
.so_valid(so_valid),
.so_data(n2),
.odd1_wr(odd1_wr),
.odd2_wr(odd2_wr),
.odd3_wr(odd3_wr),
.odd4_wr(odd4_wr),
.even1_wr(even1_wr),
.even2_wr(even2_wr),
.even3_wr(even3_wr),
.even4_wr(even4_wr),
.oem_addr(oem_addr),
.oem_dataout(oem_dataout),
.mem_done(_mem_done)
);
endmodule
| 6.965528 |
module STI_DAC (
clk,
reset,
load,
pi_data,
pi_length,
pi_fill,
pi_msb,
pi_low,
pi_end,
so_data,
so_valid,
oem_finish,
oem_dataout,
oem_addr,
odd1_wr,
odd2_wr,
odd3_wr,
odd4_wr,
even1_wr,
even2_wr,
even3_wr,
even4_wr
);
input clk, reset;
input load, pi_msb, pi_low, pi_end;
input [15:0] pi_data;
input [1:0] pi_length;
input pi_fill;
output so_data, so_valid;
output oem_finish, odd1_wr, odd2_wr, odd3_wr, odd4_wr, even1_wr, even2_wr, even3_wr, even4_wr;
output [4:0] oem_addr;
output [7:0] oem_dataout;
//==============================================================================
wire [2:0] _cur_state;
wire _read_done;
wire _out_done;
wire _mem_done;
CTRL CTRL (
.clk(clk),
.reset(reset),
.pi_end(pi_end),
.read_done(_read_done),
.out_done(_out_done),
.mem_done(_mem_done),
.cur_state(_cur_state),
.so_valid(so_valid),
.oem_finish(oem_finish)
);
PROC PROC (
.clk(clk),
.reset(reset),
.cur_state(_cur_state),
.load(load),
.pi_data(pi_data),
.pi_length(pi_length),
.pi_fill(pi_fill),
.pi_msb(pi_msb),
.pi_low(pi_low),
.read_done(_read_done),
.out_done(_out_done),
.so_data(so_data)
);
DAC DAC (
.clk(clk),
.reset(reset),
.cur_state(_cur_state),
.so_valid(so_valid),
.so_data(so_data),
.odd1_wr(odd1_wr),
.odd2_wr(odd2_wr),
.odd3_wr(odd3_wr),
.odd4_wr(odd4_wr),
.even1_wr(even1_wr),
.even2_wr(even2_wr),
.even3_wr(even3_wr),
.even4_wr(even4_wr),
.oem_addr(oem_addr),
.oem_dataout(oem_dataout),
.mem_done(_mem_done)
);
endmodule
| 6.965528 |
module PROC (
clk,
reset,
cur_state,
load,
pi_data,
pi_length,
pi_fill,
pi_msb,
pi_low,
read_done,
out_done,
so_data
);
input clk, reset;
input [2:0] cur_state;
input load;
input [15:0] pi_data;
input [1:0] pi_length;
input pi_fill, pi_msb, pi_low;
reg [15:0] data;
reg [ 1:0] length;
reg fill, msb, low;
output reg read_done;
parameter [2:0] STATE_READ = 3'b000,
STATE_PROC = 3'b001,
STATE_OUT = 3'b010,
STATE_MEM = 3'b011,
STATE_FIN = 3'b111;
// STATE_READ
always @(posedge clk or posedge reset) begin
if (reset) begin
data <= 16'b0;
length <= 2'b0;
fill <= 1'b0;
msb <= 1'b0;
low <= 1'b0;
read_done <= 1'b0;
end else begin
if (load) begin
data <= pi_data;
length <= pi_length;
fill <= pi_fill;
msb <= pi_msb;
low <= pi_low;
read_done <= 1'b1;
end else begin
read_done <= 1'b0;
end
end
end
reg [31:0] proc_data;
always @(posedge clk or posedge reset) begin
if (reset) begin
proc_data <= 32'b0;
end else begin
case (length)
2'b00: begin // 8 bits
if (low) proc_data <= {24'b0, data[15:8]};
else proc_data <= {24'b0, data[7:0]};
end
2'b01: begin // 16 bits
proc_data[15:0] <= {16'b0, data};
end
2'b10: begin // 24 bits
if (fill) proc_data <= {8'b0, data, 8'b0};
else proc_data <= {8'b0, 8'b0, data};
end
2'b11: begin // 32 bits
if (fill) proc_data <= {data, 16'b0};
else proc_data <= {16'b0, data};
end
endcase
end
end
reg [4:0] origin;
reg [4:0] destin;
output out_done;
output so_data;
assign out_done = (origin == destin) ? 1'b1 : 1'b0;
assign so_data = proc_data[origin];
// origin
always @(posedge clk or posedge reset) begin
if (reset) begin
origin <= 5'b0;
end else begin
case (cur_state)
STATE_PROC: begin
if (msb) begin
case (length)
2'b00: origin <= 5'b00111;
2'b01: origin <= 5'b01111;
2'b10: origin <= 5'b10111;
2'b11: origin <= 5'b11111;
endcase
end else origin <= 5'b0;
end
STATE_OUT: begin
if (msb) origin <= origin - 1;
else origin <= origin + 1;
end
endcase
end
end
// destin
always @(posedge clk or posedge reset) begin
if (reset) begin
destin <= 5'b0;
end else begin
case (cur_state)
STATE_PROC: begin
if (msb) destin <= 5'b0;
else begin
case (length)
2'b00: destin <= 5'b00111;
2'b01: destin <= 5'b01111;
2'b10: destin <= 5'b10111;
2'b11: destin <= 5'b11111;
endcase
end
end
endcase
end
end
endmodule
| 6.599199 |
module STK_Decoder (
SC,
HEX4,
HEX5,
HEX6,
HEX5DP
);
input [2:0] SC;
output reg [6:0] HEX4, HEX5, HEX6;
output reg HEX5DP;
always @(SC[2:0]) begin
HEX4 = 7'b1101101;
HEX5 = 7'b1111000;
HEX5DP = 1'b1;
case (SC[2:0])
3'b000: begin //Empty
HEX6 = 7'b1111001;
end
3'b001: begin //Empty
HEX6 = 7'b0000110;
end
3'b010: begin //Empty
HEX6 = 7'b1011011;
end
3'b011: begin //Empty
HEX6 = 7'b1001111;
end
3'b100: begin //Empty
HEX6 = 7'b1100110;
end
3'b101: begin //Empty
HEX6 = 7'b1101101;
end
3'b110: begin //Empty
HEX6 = 7'b1111101;
end
3'b111: begin //Empty
HEX6 = 7'b0000111;
end
endcase
end
endmodule
| 6.638044 |
module Stl (
input [31:0] A,
input [31:0] B,
output [31:0] result
);
wire cin, zero;
wire [31:0] add_result;
assign cin = 1;
Adder(
.input1(A), .input2(B), .cin(cin), .result(add_result)
);
assign zero = &add_result;
assign result = zero ? 32'h0000_0000 : 32'h0000_0001;
endmodule
| 7.224633 |
module SYMM_TEST (
input clk_test,
input en_test,
input signed [25:0] i11,
i12,
i13,
i14,
input signed [25:0] i21,
i22,
i23,
i24,
input signed [25:0] i31,
i32,
i33,
i34,
input signed [25:0] i41,
i42,
i43,
i44,
input signed [25:0] i11_2,
i12_2,
i13_2,
i14_2,
input signed [25:0] i21_2,
i22_2,
i23_2,
i24_2,
input signed [25:0] i31_2,
i32_2,
i33_2,
i34_2,
input signed [25:0] i41_2,
i42_2,
i43_2,
i44_2,
output reg signed [25:0] o11,
o12,
o13,
o14,
output reg signed [25:0] o21,
o22,
o23,
o24,
output reg signed [25:0] o31,
o32,
o33,
o34,
output reg signed [25:0] o41,
o42,
o43,
o44,
output reg isOrth
);
wire signed [29:0] orthtest;
assign orthtest = i11_2 + i12_2 + i13_2 + i14_2
+ i21_2 + i22_2 + i23_2 + i24_2
+ i31_2 + i32_2 + i33_2 + i34_2
+ i41_2 + i42_2 + i43_2 + i44_2;
always @(posedge clk_test) begin
if (en_test) begin
o11 <= i11;
o12 <= i12;
o13 <= i13;
o14 <= i14;
o21 <= i21;
o22 <= i22;
o23 <= i23;
o24 <= i24;
o31 <= i31;
o32 <= i32;
o33 <= i33;
o34 <= i34;
o41 <= i41;
o42 <= i42;
o43 <= i43;
o44 <= i44;
if (orthtest <= 30'd1) isOrth <= 1;
else isOrth <= 0;
end else begin
// o11 <= i11; o12 <= i12; o13 <= i13; o14 <= i14;
// o21 <= i21; o22 <= i22; o23 <= i23; o24 <= i24;
// o31 <= i31; o32 <= i32; o33 <= i33; o34 <= i34;
// o41 <= i41; o42 <= i42; o43 <= i43; o44 <= i44;
isOrth <= 0;
end
end
endmodule
| 6.830955 |
module stm_axi_test (
input clk_240Mhz,
output reg m_axis_tvalid,
input m_axis_tready,
output reg [63:0] m_axis_tdata,
output m_axis_tlast,
output m_axis_tstrb,
output [3:0] m_axis_tkeep
);
// always @(posedge clk_240Mhz)
//begin
// case (dwnl_state)
// // WAITING
// 2'b00 : begin
// if (m_axis_tready & m_axis_tvalid_o)
// dwnl_state <= 'b01;
// else begin
// m_axis_tready_i <= 0;
// m_axis_tvalid <= 0;
// end
// end
// // READ FIFO AND IF FIFO EMPTY
// 2'b01 : begin
// //
// if (axis_prog_empty & !m_axis_tready) begin
// dwnl_state <= 2'b10;
// m_axis_tready_i <= 0;
// m_axis_tvalid <= 0;
// end else begin
// m_axis_tready_i <= m_axis_tready;
// m_axis_tvalid <= m_axis_tvalid_o;
// end
// m_axis_tdata <= data_fifo_ff;
// end
// // WAITING FOR FULL FIFO
// 2'b10 : begin
// if (axis_prog_full)
// dwnl_state <= 2'b00;
// end
// 2'b11 : begin
// dwnl_state <= 2'b00;
// end
// default: begin
// dwnl_state <= 2'b00;
// end
// endcase
//end
endmodule
| 8.257282 |
module stock_code_512x70 (
input [ 8:0] addr_a,
input [69:0] din_a,
output reg [69:0] dout_a,
input clk_a,
input we_a
/* input [8:0] addr_b,
input [48:0] din_b,
output reg [48:0] dout_b,
input clk_b,
input we_b
*/
);
(* ram_style = "block" *) reg [69:0] ram[0:511];
// (* ram_style = "auto" *) reg [69:0] ram [0:511];
//-----------------------
// Port A
//-----------------------
always @(posedge clk_a) begin
if (we_a) begin
ram[addr_a] <= din_a;
dout_a <= din_a;
end else dout_a <= ram[addr_a];
end
/*
//-----------------------
// Port B
//-----------------------
always@(posedge clk_b) begin
if (we_b) begin
ram[addr_b] <= din_b;
dout_b <= din_b;
end
else
dout_b <= ram[addr_b];
end
*/
endmodule
| 6.736274 |
module stock_price_512x49 (
input [ 8:0] addr_a,
input [48:0] din_a,
output reg [48:0] dout_a,
input clk_a,
input we_a
/* input [8:0] addr_b,
input [48:0] din_b,
output reg [48:0] dout_b,
input clk_b,
input we_b
*/
);
(* ram_style = "block" *) reg [48:0] ram[0:511];
// (* ram_style = "auto" *) reg [48:0] ram [0:511];
//-----------------------
// Port A
//-----------------------
always @(posedge clk_a) begin
if (we_a) begin
ram[addr_a] <= din_a;
dout_a <= din_a;
end else dout_a <= ram[addr_a];
end
/*
//-----------------------
// Port B
//-----------------------
always@(posedge clk_b) begin
if (we_b) begin
ram[addr_b] <= din_b;
dout_b <= din_b;
end
else
dout_b <= ram[addr_b];
end
*/
endmodule
| 6.992376 |
module stopping (
input clock,
input [3:0] present_INs,
output stoppedAndWaitingForDetection //boolean
);
reg waitingForAudioSignal_reg;
wire [27:0] countedUpTo_wire;
reg [3:0] isStopped;
parameter COUNT_PERIOD_HALF_SEC = 28'd200000000;
parameter P_25_MILLI_SEC = COUNT_PERIOD_HALF_SEC >> 1;
parameter P_12_MILLI_SEC = COUNT_PERIOD_HALF_SEC >> 2;
parameter P_38_MILLI_SEC = P_12_MILLI_SEC + P_25_MILLI_SEC; //ACTUALLy 37.5 ms
always @(posedge clock) begin //tests for intersections
if (countedUpTo_wire > 0 && countedUpTo_wire < P_12_MILLI_SEC) begin
if (present_INs == 4'b0000) isStopped[0] <= 1;
else isStopped[0] <= 0;
end else if (countedUpTo_wire > P_12_MILLI_SEC && countedUpTo_wire < P_25_MILLI_SEC) begin
if (present_INs == 4'b0000) isStopped[1] <= 1;
else isStopped[1] <= 0;
end else if (countedUpTo_wire > P_25_MILLI_SEC && countedUpTo_wire < P_38_MILLI_SEC) begin
if (present_INs == 4'b0000) isStopped[2] <= 1;
else isStopped[2] <= 0;
end else if (P_38_MILLI_SEC > P_25_MILLI_SEC && countedUpTo_wire < COUNT_PERIOD_HALF_SEC) begin
if (present_INs == 4'b0000) isStopped[3] <= 1;
else isStopped[3] <= 0;
end
if (isStopped == 4'b1111) waitingForAudioSignal_reg <= 1'b1;
else waitingForAudioSignal_reg <= 1'b0;
end //end of always@(posedge clock) begin
counter_up stopCounter ( //counter_up( clk, counterPeriod, countedUpTo )
.clock(clock),
.reset(1'b0),
.counterPeriod(COUNT_PERIOD_HALF_SEC), //.5 second
.countedUpTo(countedUpTo_wire)
);
assign stoppedAndWaitingForDetection = waitingForAudioSignal_reg;
endmodule
| 7.279662 |
module stopstart (
input b0down,
output reg [1:0] state,
input userclock,
input switch,
input switch2
);
reg [1:0] next_state;
initial begin //we set the initial state to be zero
state = 0; //this way, we start with a "paused" stopwatch
next_state = 0;
end
always @(posedge userclock) begin
state <= next_state; //FSM
end
always @(posedge userclock) begin //same as my diagram
if (state == 0 && b0down && switch && !switch2) next_state <= 1;
if (state == 0 && !b0down && switch && !switch2) next_state <= 0;
if (state == 1 && b0down && switch && !switch2) next_state <= 1;
if (state == 1 && !b0down && switch && !switch2) next_state <= 2;
if (state == 2 && b0down && switch && !switch2) next_state <= 3;
if (state == 2 && !b0down && switch && !switch2) next_state <= 2;
if (state == 3 && b0down && switch && !switch2) next_state <= 3;
if (state == 3 && !b0down && switch && !switch2) next_state <= 0;
end
endmodule
| 6.949633 |
module StopwatchImpl (
input Clk,
input [3:0] Btn,
input [6:0] Switch,
output wire [3:0] LED,
output wire [0:6] IO_LED1,
output wire [0:6] IO_LED2,
output wire [0:6] IO_LED3,
output wire [0:6] IO_LED4
);
wire [3:0] BtnDebounced;
wire BtnExtDebounced;
wire [6:0] SwitchSync;
Genvar gi;
generate
for (gi = 0; gi <= 5; gi = gi + 1) begin : gensynch
Synchronizer(
.Clk(Clk), .Input(Switch[gi]), .Output(SwitchSync[gi])
);
end
endgenerate
generate
for (gi = 0; gi <= 3; gi = gi + 1) begin : gensynch
Debouncer debounce0 (
.Clk(Clk),
.Input(!Btn[gi]),
.Output(BtnDebounced[gi])
);
end
endgenerate
Debouncer debounceExtBtn (
.Clk(Clk),
.Input(Switch[6]),
.Output(BtnExtDebounced)
);
Stopwatch stopwatch (
.Clk(Clk),
.Clk2(BtnExtDebounced),
.ClkSel(SwitchSync[5]),
.Reset(BtnDebounced[0]),
.Stop(BtnDebounced[1]),
.Up(BtnDebounced[2]),
.Down(BtnDebounced[3]),
.Speed(SwitchSync[4:0]),
.ModeOutput0(LED[0]),
.ModeOutput1(LED[1]),
.ModeOutput2(LED[2]),
.ClkOutput(LED[3]),
.LEDDisp3(IO_LED1[0:6]),
.LEDDisp2(IO_LED2[0:6]),
.LEDDisp1(IO_LED3[0:6]),
.LEDDisp0(IO_LED4[0:6])
);
endmodule
| 6.633212 |
module stopwatch_fsm (
input clkIn,
input rstIn,
input btnRunIn,
input btnPauseIn,
input btnClearIn,
output reg enCounterOut,
output reg clrCounterOut
);
parameter IDLE = 4'b0001;
parameter RUN = 4'b0010;
parameter PAUSE = 4'b0100;
parameter CLEAR = 4'b1000;
reg [3:0] state;
always @(posedge clkIn) begin
if (rstIn == 1'b1) begin
state <= IDLE;
enCounterOut <= 1'b0;
clrCounterOut <= 1'b0;
end else begin
case (state)
IDLE: begin
enCounterOut <= 1'b0;
clrCounterOut <= 1'b0;
if (btnRunIn == 1'b1) begin
state <= RUN;
end else if (btnClearIn == 1'b1) begin
state <= CLEAR;
end
end
RUN: begin
enCounterOut <= 1'b1;
clrCounterOut <= 1'b0;
if (btnPauseIn == 1'b1) begin
state <= PAUSE;
end else if (btnClearIn == 1'b1) begin
state <= CLEAR;
end
end
PAUSE: begin
enCounterOut <= 1'b0;
clrCounterOut <= 1'b0;
if (btnRunIn == 1'b1) begin
state <= RUN;
end else if (btnClearIn == 1'b1) begin
state <= CLEAR;
end
end
CLEAR: begin
enCounterOut <= 1'b0;
clrCounterOut <= 1'b1;
state <= IDLE;
end
default: state <= IDLE;
endcase
end
end
endmodule
| 6.675491 |
module stopwatch_l5 (
input [1:0] KEY,
input CLOCK_50,
output reg [6:0] HEX0,
output reg [6:0] HEX1,
output reg [6:0] HEX2,
output reg [6:0] HEX3,
output reg [9:0] LEDR,
output reg [7:0] LEDG
);
reg [18:0] impulses_cout;
reg [ 3:0] one_first_sec; // 1
reg [ 3:0] one_second_sec; // 11
reg [ 3:0] one_third_sec; // 111
reg [ 3:0] one_fourth_sec; // 1111
initial HEX0 = 7'b1111111;
initial HEX1 = 7'b1111111;
initial HEX2 = 7'b1111111;
initial HEX3 = 7'b1111111;
initial LEDR = 10'b0000000000;
initial one_first_sec = 4'b0;
initial one_second_sec = 4'b0;
initial one_third_sec = 4'b0;
initial one_fourth_sec = 4'b0;
always @(posedge CLOCK_50 or posedge KEY[0]) begin
if (KEY[0]) begin // Если 1, то сбрасыет время
one_first_sec <= one_first_sec;
one_second_sec <= one_second_sec;
one_third_sec <= one_third_sec;
one_fourth_sec <= one_fourth_sec;
end else begin
impulses_cout <= impulses_cout + 1;
// Если в проектируемом таймере использовать кварцевый генератор с
// частотой 50 МГц, то одной секунде соответствует 50 миллионов тактовых импульсов, а
// одной сотой секунды соответствует 500 тысяч тактовых импульсов
/*if (impulses_cout == 19'b1111010000100011111) begin
LEDR[9:0] = 10'b1111111111;
end*/
if (impulses_cout == 19'd49_999_999) begin // 499999
one_first_sec <= one_first_sec + 1;
impulses_cout <= 19'b0;
end
if (one_first_sec == 4'b1010) begin // 10
one_second_sec <= one_second_sec + 1;
one_first_sec <= 0;
end
if (one_second_sec == 4'b1010) begin // 10
one_third_sec <= one_third_sec + 1;
LEDR[9:0] <= 10'b1111111111;
one_second_sec <= 0;
end
if ((one_second_sec == 4'd2) && (one_first_sec == 4'd2)) begin
LEDR[9:0] <= 10'b0000000000;
end
if ((one_third_sec == 4'd0) && (one_second_sec == 4'd1)) begin
LEDG[7:0] <= 10'b00000000;
end
/*if(imp_cout_sixz == 8'd33) begin
LEDR[9:0] <= 10'b1111111111;
end else begin
LEDR[9:0] <= 10'b0000000000;
end*/
if (one_third_sec == 4'b1010) begin // 10
one_fourth_sec <= one_fourth_sec + 1;
LEDG[7:0] <= 10'b11111111;
one_third_sec <= 0;
end
if (one_fourth_sec == 4'b1010) begin // 10
one_first_sec <= 4'b0;
one_second_sec <= 4'b0;
one_third_sec <= 4'b0;
one_fourth_sec <= 4'b0;
end
end
case (one_first_sec)
0: HEX0 = 7'b1000000;
1: HEX0 = 7'b1111001;
2: HEX0 = 7'b0100100;
3: HEX0 = 7'b0110000;
4: HEX0 = 7'b0011001;
5: HEX0 = 7'b0010010;
6: HEX0 = 7'b0000010;
7: HEX0 = 7'b1111000;
8: HEX0 = 7'b0000000;
9: HEX0 = 7'b0010000;
endcase
case (one_second_sec)
0: HEX1 = 7'b1000000;
1: HEX1 = 7'b1111001;
2: HEX1 = 7'b0100100;
3: HEX1 = 7'b0110000;
4: HEX1 = 7'b0011001;
5: HEX1 = 7'b0010010;
6: HEX1 = 7'b0000010;
7: HEX1 = 7'b1111000;
8: HEX1 = 7'b0000000;
9: HEX1 = 7'b0010000;
endcase
case (one_third_sec)
0: HEX2 = 7'b1000000;
1: HEX2 = 7'b1111001;
2: HEX2 = 7'b0100100;
3: HEX2 = 7'b0110000;
4: HEX2 = 7'b0011001;
5: HEX2 = 7'b0010010;
6: HEX2 = 7'b0000010;
7: HEX2 = 7'b1111000;
8: HEX2 = 7'b0000000;
9: HEX2 = 7'b0010000;
endcase
case (one_fourth_sec)
0: HEX3 = 7'b1000000;
1: HEX3 = 7'b1111001;
2: HEX3 = 7'b0100100;
3: HEX3 = 7'b0110000;
4: HEX3 = 7'b0011001;
5: HEX3 = 7'b0010010;
6: HEX3 = 7'b0000010;
7: HEX3 = 7'b1111000;
8: HEX3 = 7'b0000000;
9: HEX3 = 7'b0010000;
endcase
end
endmodule
| 7.836739 |
module show_time (
time_display,
hex5,
hex4,
hex3,
hex2,
hex1,
hex0
);
input [18:0] time_display;
output [6:0] hex5, hex4, hex3, hex2, hex1, hex0;
// Minutes.
sevenseg_decimal(
time_display / 60000, hex5
); sevenseg_decimal(
time_display / 6000 % 10, hex4
);
// Seconds.
sevenseg_decimal(
time_display % 6000 / 1000, hex3
); sevenseg_decimal(
time_display / 100 % 10, hex2
);
// Centiseconds.
sevenseg_decimal(
time_display % 100 / 10, hex1
); sevenseg_decimal(
time_display % 10, hex0
);
endmodule
| 7.555103 |
module show_counting_status (
time_counter,
counting,
led
);
input [18:0] time_counter;
input counting;
output [9:0] led;
// When stopped, all LEDs off.
// When counting, LED light spot moves to the right every second.
// When paused, LED light spot stays at the original position.
assign led = counting ? 1 << (9 - time_counter / 100 % 10) : 0;
endmodule
| 6.546423 |
module.
// Key usage:
// key3: Reset all states (will stop current counting).
// key2: Start / Pause / Resume counting.
// key1: Pause display updating (but counting is still in process), display current time value and freeze.
// key0: Resume display updating.
// When stopped or paused, key1 and key0 will be disabled.
module stopwatch_main(clk, key3, key2, key1, key0, hex5, hex4, hex3, hex2, hex1, hex0, led);
input clk, key3, key2, key1, key0;
output [6:0] hex5, hex4, hex3, hex2, hex1, hex0;
output [9:0] led;
reg [18:0] time_counter, time_display;
reg counting, paused, freeze_display, key1_last;
parameter max_time = 360000 - 1;
initial begin
time_counter <= 0;
time_display <= 0;
counting <= 0;
paused <= 0;
freeze_display <= 0;
key1_last <= 1;
end
show_time(time_display, hex5, hex4, hex3, hex2, hex1, hex0);
show_counting_status(time_counter, counting, led);
// State change of time_counter.
always @(posedge clk or negedge key3) begin
if (!key3) begin // Match sensitive signal list in if tests.
time_counter <= 0;
end
else begin // clk posedge
if (counting && !paused)
time_counter <= time_counter == max_time ? 0 : time_counter + 1; // Increment counter.
end
end
// State change of time_display.
always @(posedge clk or negedge key3 or negedge key1) begin
if (!key3) begin
time_display <= 0;
end
else if (!key1) begin
if (key1 != key1_last && counting && !paused) // Make sure state of key1 changes.
time_display <= time_counter; // Update display.
end
else begin // clk posedge
if (counting && !paused && !freeze_display)
time_display <= time_counter; // Update display.
end
end
// State change of counting and paused.
always @(negedge key3 or negedge key2) begin
if (!key3) begin
counting <= 0;
paused <= 0;
end
else begin // key2 pressed
if (!counting)
counting <= 1; // Start counting.
else
paused <= ~paused; // Toggle pause / resume.
end
end
// State change of freeze_display.
always @(negedge key3 or negedge key1 or negedge key0) begin
if (!key3) begin
freeze_display <= 0;
end
else if (!key1) begin // Note: Key priority: when key1 is long pressed, key0 press will not be responded.
if (counting && !paused)
freeze_display <= 1;
end
else begin // key0 pressed
if (counting && !paused)
freeze_display <= 0;
end
end
// State change of key1_last.
always @(posedge clk)
key1_last <= key1;
endmodule
| 7.309053 |
module clocks (
rst,
master_clock,
clock1hz,
clock2hz,
clock_adjust,
clock_fast
);
input wire rst;
input wire master_clock;
output reg clock1hz;
output reg clock2hz;
output reg clock_adjust;
output reg clock_fast;
reg [27:0] counter1hz;
reg [27:0] counter2hz;
reg [27:0] counter_adjust;
reg [27:0] counter_fast;
parameter cutoff1hz = 50000000;
parameter cutoff2hz = 25000000;
parameter cutoff_adjust = 40000000; //1.25Hz
parameter cutoff_fast = 50000; //100
always @(posedge master_clock) begin
if (rst) begin
counter1hz <= 0;
counter2hz <= 0;
counter_adjust <= 0;
counter_fast <= 0;
clock1hz <= 0;
clock2hz <= 0;
clock_adjust <= 0;
clock_fast <= 0;
end else begin
// increment counters
counter1hz <= counter1hz + 1'b1;
counter2hz <= counter2hz + 1'b1;
counter_adjust <= counter_adjust + 1'b1;
counter_fast <= counter_fast + 1'b1;
//SIMULATION sped up x100
//== cutoff1hz/100
if (counter1hz == 100) begin
counter1hz <= 0;
if (clock1hz == 0) clock1hz <= 1'b1;
else clock1hz <= 1'b0;
end
//SIMULATION sped up x100
//== cutoff2hz/100
if (counter2hz == 50) begin
counter2hz <= 0;
if (clock2hz == 0) clock2hz <= 1'b1;
else clock2hz <= 1'b0;
end
//SIMULATION sped up x100
//== cutoff_adjust/100
if (counter_adjust == 12) begin
counter_adjust <= 0;
if (clock_adjust == 0) clock_adjust <= 1'b1;
else clock_adjust <= 1'b0;
end
//SIMULATION sped up x100
// == cutoff_fast/100
if (counter_fast == 1) begin
counter_fast <= 0;
if (clock_fast == 0) clock_fast <= 1'b1;
else clock_fast <= 1'b0;
end
end
end
endmodule
| 7.033034 |
module stopwatch_timer (
output [7:0] ssd,
output [3:0] ssd_ctl,
output [15:0] LED,
input start_hr,
input pause_min,
input mode_setting,
input rst_n_init,
input clk
);
wire clk1hz, clk_100hz;
wire [1:0] clk_ctl;
wire start, hr, start_hr_debounce, start_hr_one_pulse;
wire pause, min, pause_min_debounce, pause_min_one_pulse;
wire mode, setting, set_longpush, mode_setting_debounce, mode_setting_one_pulse;
wire [3:0] min1, min0, sec1, sec0;
wire [3:0] init0, init1, init2, init3;
wire [3:0] sw3, sw2, sw1, sw0;
wire [3:0] timer3, timer2, timer1, timer0;
reg [3:0] value0, value1, value2, value3;
wire [3:0] BCD;
wire carry;
reg zero;
freq_div U0 (
clk_1hz,
clk_100hz
,,,
clk_ctl,
clk,
rst_n_init
);
debounce U1 (
start_hr_debounce,
start_hr,
clk_100hz,
rst_n_init
);
debounce U2 (
pause_min_debounce,
pause_min,
clk_100hz,
rst_n_init
);
debounce U3 (
mode_setting_debounce,
mode_setting,
clk_100hz,
rst_n_init
);
one_pulse U4 (
start_hr_one_pulse,
start_hr_debounce,
clk_100hz,
rst_n_init
);
one_pulse U5 (
pause_min_one_pulse,
pause_min_debounce,
clk_100hz,
rst_n_init
);
one_pulse U6 (
mode_setting_one_pulse,
mode_setting_debounce,
clk_100hz,
rst_n_init
);
fsm_button U7 (
start,
start_hr_one_pulse,
clk_100hz,
~setting
);
fsm_button U8 (
pause,
pause_min_one_pulse,
clk_100hz,
~setting & start
);
fsm_button U9 (
mode,
mode_setting_one_pulse,
clk_100hz,
rst_n_init
);
fsm_longpush U10 (
hr,
start_hr_debounce,
clk_1hz,
rst_n_init
);
fsm_longpush U11 (
min,
pause_min_debounce,
clk_1hz,
rst_n_init
);
fsm_longpush_state U12 (
setting,
mode_setting_debounce,
clk_1hz,
rst_n_init
);
BCD_counter_2bit U14 (
sec1,
sec0,
carry,
4'd0,
4'd0,
4'd5,
4'd9,
clk_1hz,
~setting,
start
);
BCD_counter_2bit U15 (
min1,
min0
,,
4'd0,
4'd0,
4'd5,
4'd9,
clk_1hz,
~setting,
carry
);
load_reg U16 (
sw0,
sec0,
pause,
clk_100hz,
rst_n_init
);
load_reg U17 (
sw1,
sec1,
pause,
clk_100hz,
rst_n_init
);
load_reg U18 (
sw2,
min0,
pause,
clk_100hz,
rst_n_init
);
load_reg U19 (
sw3,
min1,
pause,
clk_100hz,
rst_n_init
);
BCD_counter_2bit U20 (
init1,
init0
,,
4'd0,
4'd0,
4'd5,
4'd9,
clk_1hz,
rst_n_init,
min
);
BCD_counter_2bit U21 (
init3,
init2
,,
4'd0,
4'd0,
4'd2,
4'd3,
clk_1hz,
rst_n_init,
hr
);
downcounter_6bit U22 (
timer3,
timer2,
timer1,
timer0
,,,
init3,
init2,
init1,
init0,
4'd0,
4'd0,
4'd2,
4'd3,
4'd5,
4'd9,
4'd5,
4'd9,
clk_100hz,
~setting & start,
~pause & ~zero
);
scan_ctl U23 (
BCD,
ssd_ctl,
value3,
value2,
value1,
value0,
clk_ctl
);
D_ssd U24 (
ssd,
BCD
);
always @* begin
if (setting == 1'b1) begin
value3 = init3;
value2 = init2;
value1 = init1;
value0 = init0;
end else if (mode == 1'd0) begin
value3 = sw3;
value2 = sw2;
value1 = sw1;
value0 = sw0;
end else begin
value3 = timer3;
value2 = timer2;
value1 = timer1;
value0 = timer0;
end
if (value3 == 4'd0 && value2 == 4'd0 && value1 == 4'd0 && value0 == 4'd0) zero = 1'b1;
else zero = 1'd0;
end
assign LED = {{14{zero}} & {14{mode}}, setting, mode};
endmodule
| 6.703099 |
module stop_check (
input wire sampled_bit,
input wire stop_check_en,
output reg stop_err
);
always @(*) begin
if (stop_check_en)
if (sampled_bit) stop_err = 1'b0;
else stop_err = 1'b1;
else stop_err = 1'b0;
end
endmodule
| 6.88184 |
module stop_pipe (
input clock,
n_stop_request,
output reg stop
);
reg [3:0] count;
//assign stop1 = ~(~n_stop_request && (count == 4'b0));
always @(posedge clock or negedge n_stop_request) begin
if (!n_stop_request) begin
count <= 4'b1000;
stop <= 1'b0;
end else if (count > 4'b0 && stop == 1'b0) begin
count <= count - 1'b1;
end else begin
stop <= 1'b1;
end
end
endmodule
| 7.107729 |
module stop_pipelined_unit (
input rst_n,
input load_use_hazard,
output reg stop
);
always @(*) begin
if (rst_n == 'b0) begin
stop = 'b0;
end else if (load_use_hazard == 'b1) begin
stop = 'b1;
end else begin
stop = 'b0;
end
end
endmodule
| 7.673042 |
module stop_watch_cascade (
input wire clk,
input wire go,
clr,
output wire [3:0] d2,
d1,
d0
);
// declaration
localparam DVSR = 10000000; // 100MHz, count to 10M to 0.1s tick
reg [23:0] ms_reg;
wire [23:0] ms_next;
reg [3:0] d2_reg, d1_reg, d0_reg;
wire [3:0] d2_next, d1_next, d0_next;
wire d1_en, d2_en, d0_en;
wire ms_tick, d0_tick, d1_tick;
// body
// register
always @(posedge clk) begin
ms_reg <= ms_next;
d2_reg <= d2_next;
d1_reg <= d1_next;
d0_reg <= d0_next;
end
// next-state logic
// 0.1 sec tick generator mod-5.000.000
assign ms_next = (clr || (ms_reg == DVSR && go)) ? 4'b0 : (go) ? ms_reg + 1 : ms_reg;
assign ms_tick = (ms_reg == DVSR) ? 1'b1 : 1'b0;
// 0.1 sec counter
assign d0_en = ms_tick;
assign d0_next = (clr || (d0_en && d0_reg == 9)) ? 4'b0 : (d0_en) ? d0_reg + 1 : d0_reg;
assign d0_tick = (d0_reg == 9) ? 1'b1 : 1'b0;
// 1 sec counter
assign d1_en = ms_tick & d0_tick;
assign d1_next = (clr || (d1_en && d1_reg == 9)) ? 4'b0 : (d1_en) ? d1_reg + 1 : d1_reg;
assign d1_tick = (d1_reg == 9) ? 1'b1 : 1'b0;
// 10 sec counter
assign d2_en = ms_tick & d0_tick & d1_tick;
assign d2_next = (clr || (d2_en && d2_reg == 9)) ? 4'b0 : (d2_en) ? d2_reg + 1 : d2_reg;
// output logic
assign d0 = d0_reg;
assign d1 = d1_reg;
assign d2 = d2_reg;
endmodule
| 6.788192 |
module stop_watch_test (
input wire clk,
input wire btnR,
btnL,
output wire [3:0] an,
output wire [7:0] seg
);
// signal declaration
wire [3:0] d2, d1, d0;
// instantiate 7-seg LED display module
disp_hex_mux disp_unit (
.clk(clk),
.reset(1'b0),
.hex3(4'b0),
.hex2(d2),
.hex1(d1),
.hex0(d0),
.dp_in(4'b1101),
.an(an),
.sseg(seg)
);
// instatiate stopwatch
stop_watch_if counter_unit (
.clk(clk),
.go (btnL),
.clr(btnR),
.d2 (d2),
.d1 (d1),
.d0 (d0)
);
endmodule
| 7.867655 |
module StorageDrive #(
parameter DW = 32,
parameter ADDR_WIDTH = 15,
parameter inputFile = "Program.txt"
) (
input [(ADDR_WIDTH-1):0] data_address,
input [(DW-1):0] input_data,
input write_enable,
read_clock,
write_clock,
output reg [(DW-1):0] output_data
);
// Storage declaration
reg [DW-1:0] hd[2**ADDR_WIDTH-1:0];
//Initialization: loads input file into memory
initial begin
$readmemb(inputFile, hd);
end
// Read port
always @(posedge read_clock) begin
output_data <= hd[data_address];
end
// Write port
always @(posedge write_clock) begin
if (write_enable) hd[data_address] <= input_data;
end
endmodule
| 7.850885 |
module storage_bridge_wb (
// MGMT_AREA R/W WB Interface
input wb_clk_i,
input wb_rst_i,
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input wb_cyc_i,
input [1:0] wb_stb_i,
output reg [1:0] wb_ack_o,
output reg [31:0] wb_rw_dat_o,
// MGMT_AREA RO WB Interface
output [31:0] wb_ro_dat_o,
// MGMT Area native memory interface
output [`RAM_BLOCKS-1:0] mgmt_ena,
output [(`RAM_BLOCKS*4)-1:0] mgmt_wen_mask,
output [`RAM_BLOCKS-1:0] mgmt_wen,
output [7:0] mgmt_addr,
output [31:0] mgmt_wdata,
input [(`RAM_BLOCKS*32)-1:0] mgmt_rdata,
// MGMT_AREA RO Interface
output mgmt_ena_ro,
output [7:0] mgmt_addr_ro,
input [31:0] mgmt_rdata_ro
);
parameter [(`RAM_BLOCKS*24)-1:0] RW_BLOCKS_ADR = {{24'h10_0000}, {24'h00_0000}};
parameter [23:0] RO_BLOCKS_ADR = {{24'h20_0000}};
parameter ADR_MASK = 24'hFF_0000;
wire [1:0] valid;
wire [1:0] wen;
wire [7:0] wen_mask;
assign valid = {2{wb_cyc_i}} & wb_stb_i;
assign wen = wb_we_i & valid;
assign wen_mask = wb_sel_i & {{4{wen[1]}}, {4{wen[0]}}};
// Ack generation
reg [1:0] wb_ack_read;
always @(posedge wb_clk_i) begin
if (wb_rst_i == 1'b1) begin
wb_ack_read <= 2'b0;
wb_ack_o <= 2'b0;
end else begin
wb_ack_o <= wb_we_i ? (valid & ~wb_ack_o) : wb_ack_read;
wb_ack_read <= (valid & ~wb_ack_o) & ~wb_ack_read;
end
end
// Address decoding
wire [`RAM_BLOCKS-1:0] rw_sel;
wire ro_sel;
genvar iS;
generate
for (iS = 0; iS < `RAM_BLOCKS; iS = iS + 1) begin
assign rw_sel[iS] = ((wb_adr_i[23:0] & ADR_MASK) == RW_BLOCKS_ADR[(iS+1)*24-1:iS*24]);
end
endgenerate
// Management R/W interface
assign mgmt_ena = valid[0] ? ~rw_sel : {`RAM_BLOCKS{1'b1}};
assign mgmt_wen = ~{`RAM_BLOCKS{wen[0]}};
assign mgmt_wen_mask = {`RAM_BLOCKS{wen_mask[3:0]}};
assign mgmt_addr = wb_adr_i[9:2];
assign mgmt_wdata = wb_dat_i[31:0];
integer i;
always @(*) begin
wb_rw_dat_o = {32{1'b0}};
for (i = 0; i < (`RAM_BLOCKS * 32); i = i + 1)
wb_rw_dat_o[i%32] = wb_rw_dat_o[i%32] | (rw_sel[i/32] & mgmt_rdata[i]);
end
// RO Interface
assign ro_sel = ((wb_adr_i[23:0] & ADR_MASK) == RO_BLOCKS_ADR);
assign mgmt_ena_ro = valid[1] ? ~ro_sel : 1'b1;
assign mgmt_addr_ro = wb_adr_i[9:2];
assign wb_ro_dat_o = mgmt_rdata_ro;
endmodule
| 6.976351 |
module storage_wrapper (
input clk, //shared wire
input rst, //shared wire
input [7:0] i_tdata,
input i_tlast,
input wren,
input [12:0] wr_ptr,
output [2:0] rd_ptr_tribit,
input greenflag,
output [7:0] o_tdata,
input o_tready,
output o_tvalid,
output o_tlast
);
//Drive pipeline logic wire
wire drive_pipeline;
//wire name is specifyed as "w_(module name)_(outputinterface_of_the_module)"
wire w_readbuf_fsm_storage_rd_newline;
wire w_readbuf_fsm_storage_rd_char_incr;
wire w_read_logic_storage_tlast_flag;
wire [12:0] w_read_logic_storage_rd_ptr;
//Drive pipleine logic
assign drive_pipeline = !(o_tvalid && !o_tready);
//Modules instantiations
readbuf_fsm_onedelay READBUF_FSM_STORAGE1 (
.clk(clk),
.rst(rst),
.greenflag(greenflag),
.lastflag(w_read_logic_storage_tlast_flag),
.tready(drive_pipeline),
.tvalid(o_tvalid),
.tlast(o_tlast),
.rd_newline(w_readbuf_fsm_storage_rd_newline),
.rd_char_incr(w_readbuf_fsm_storage_rd_char_incr)
);
read_logic_storage READ_LOGIC_STORAGE1 (
.clk(clk),
.rst(rst),
.rd_char_incr(w_readbuf_fsm_storage_rd_char_incr),
.rd_newline(w_readbuf_fsm_storage_rd_newline),
.tlastarray_cs_rgs(i_tlast),
.we_rgs(wren),
.wr_ptr_rgs(wr_ptr),
.tlast_flag(w_read_logic_storage_tlast_flag),
.rd_ptr(w_read_logic_storage_rd_ptr),
.rd_ptr_tribit(rd_ptr_tribit)
);
dual_port_syncout_enabled_ram #(
.D_WIDTH(8),
.A_WIDTH(13)
) DUAL_PORT_SYNCOUT_ENABLED_RAM1 (
.clk(clk),
.rst(rst),
.enableout(drive_pipeline),
.we(wren),
.data(i_tdata),
.read_addr(w_read_logic_storage_rd_ptr),
.write_addr(wr_ptr),
.q(o_tdata)
);
endmodule
| 6.79034 |
module StoreAux (
input wire [ 1:0] selector,
input wire [31:0] data_0,
data_1,
output wire [31:0] data_out
);
assign data_out = (selector == 2'b00) ? data_0 :
(selector == 2'b01) ? {data_1[31:16], data_0[15:0]} :
(selector == 2'b10) ? {data_1[31:8], data_0[7:0]} :
32'dx;
endmodule
| 7.281248 |
module FIFO (
clk,
rst,
we_i,
re_i,
waddr_i,
wdata_i,
raddr_o,
rdata_o,
fifo_full_o,
fifo_empty_o,
read_ptr
);
input clk, rst, re_i, we_i;
input [31:0] waddr_i;
input [31:0] wdata_i;
input [5:0] read_ptr;
output reg [31:0] raddr_o;
output reg [31:0] rdata_o;
output wire fifo_full_o;
output wire fifo_empty_o;
// RAM for address and data
reg [31:0] ram_addr [0:31];
reg [31:0] ram_data [0:31];
reg [ 5:0] write_ptr;
assign fifo_full_o = (write_ptr[4:0] == read_ptr[4:0]) & (write_ptr[5] ^ read_ptr[5]);
assign fifo_empty_o = (write_ptr == read_ptr);
// wRITE THE sTORE bUFFER
always @(posedge clk) begin
if (rst) begin
write_ptr <= 5'b0;
end else begin
if (we_i) begin
ram_addr[write_ptr[4:0]] <= waddr_i;
ram_data[write_ptr[4:0]] <= wdata_i;
write_ptr <= write_ptr + 1'b1;
end
end
end
// lOAD THE sTORE bUFFER
always @(*) begin
if (rst) begin
raddr_o = 32'b0;
rdata_o = 32'b0;
end else begin
if (re_i) begin
raddr_o = ram_addr[read_ptr];
rdata_o = ram_data[read_ptr];
end else begin
raddr_o = 32'b0;
rdata_o = 32'b0;
end
end
end
endmodule
| 6.626407 |
module storegen_testbench;
`include "../clk_gen_template.vh"
`include "armleocpu_defines.vh"
initial begin
#100 $finish;
end
reg [1:0] inwordOffset;
reg [1:0] storegenType;
reg [31:0] storegenDataIn;
wire [31:0] storegenDataOut;
wire [3:0] storegenDataMask;
wire storegenMissAligned;
wire storegenUnknownType;
armleocpu_storegen storegen (.*);
integer m;
initial begin
@(negedge clk) storegenType = 2'b11;
@(posedge clk) `assert(storegenUnknownType, 1);
@(negedge clk) storegenType = `STORE_BYTE;
storegenDataIn = 32'hAA;
for (m = 0; m < 4; m = m + 1) begin
@(negedge clk) inwordOffset = m;
@(posedge clk)
//$display(storegenDataMask, 1 << m);
`assert(
storegenDataMask, 1 << m)
`assert(storegenDataOut, storegenDataIn << (m * 8))
`assert(storegenMissAligned, 0);
`assert(storegenUnknownType, 0);
$display("Test Byte - Done inwordOffset=%d", inwordOffset);
end
storegenType = `STORE_HALF;
storegenDataIn = 32'hAAAA;
for (m = 0; m < 2; m = m + 1) begin
@(negedge clk) inwordOffset = m << 1;
@(posedge clk) `assert(storegenUnknownType, 0);
//$display(storegenDataMask, 2'b11 << (m * 2));
`assert(storegenDataMask, 2'b11 << (m * 2));
`assert(storegenDataOut, storegenDataIn << (m * 16));
`assert(storegenMissAligned, 0);
$display("Test Halfword - Done inwordOffset=%d", inwordOffset);
end
@(negedge clk) storegenType = `STORE_WORD;
storegenDataIn = 32'hAAAABBBB;
inwordOffset = 0;
@(posedge clk) `assert(storegenUnknownType, 0);
`assert(storegenDataMask, 4'b1111);
`assert(storegenDataOut, storegenDataIn);
`assert(storegenMissAligned, 0);
$display("Test Word - Done inwordOffset=%d", inwordOffset);
for (m = 1; m < 4; m = m + 1) begin
@(negedge clk) storegenType = `STORE_WORD;
storegenDataIn = 32'hAAAABBBB;
inwordOffset = m;
@(posedge clk) `assert(storegenUnknownType, 0);
`assert(storegenMissAligned, 1);
$display("Test missaligned Word - Done inwordOffset=%d", inwordOffset);
end
for (m = 0; m < 2; m = m + 1) begin
@(negedge clk) storegenType = `STORE_WORD;
storegenDataIn = 32'hAAAABBBB;
inwordOffset = (m << 1) | 1;
@(posedge clk) `assert(storegenUnknownType, 0);
`assert(storegenMissAligned, 1);
$display("Test missaligned half - Done inwordOffset=%d", inwordOffset);
end
end
endmodule
| 6.95758 |
module Storeimm (
Signimm,
CLK,
Outimm,
reset
);
input [31:0] Signimm;
input CLK, reset;
output reg [31:0] Outimm;
always @(posedge CLK or negedge reset) begin
if (!reset) begin
Outimm = 32'b0;
end else begin
Outimm = Signimm;
end
end
endmodule
| 6.970693 |
module StoreLogic (
input [31:0] Data,
input [ 1:0] ALUOutput,
input [ 1:0] DataType,
output reg [31:0] FixedData,
output reg [ 3:0] MemoryByteSel
);
reg [31:0] Byte0;
reg [31:0] Byte1;
reg [31:0] Byte2;
reg [31:0] Byte3;
reg [31:0] Half0;
reg [31:0] Half1;
reg [31:0] Byte;
reg [31:0] Half;
reg [31:0] Word;
always @(*) begin
Byte0 = {24'b0, Data[7:0]};
Byte1 = {16'b0, Data[7:0], 8'b0};
Byte2 = {8'b0, Data[7:0], 16'b0};
Byte3 = {Data[7:0], 24'b0};
Half0 = {16'b0, Data[15:0]};
Half1 = {Data[15:0], 16'b0};
Word = Data;
case (DataType)
0: begin
case (ALUOutput)
0: begin
Byte = Byte0;
MemoryByteSel = 4'b0001;
end
1: begin
Byte = Byte1;
MemoryByteSel = 4'b0010;
end
2: begin
Byte = Byte2;
MemoryByteSel = 4'b0100;
end
3: begin
Byte = Byte3;
MemoryByteSel = 4'b1000;
end
default: begin
Byte = 0;
MemoryByteSel = 4'b0000;
end
endcase
FixedData = Byte;
end
1: begin
case (ALUOutput)
0: begin
Half = Half0;
MemoryByteSel = 4'b0011;
end
2: begin
Half = Half1;
MemoryByteSel = 4'b1100;
end
default: begin
Half = 0;
MemoryByteSel = 4'b0000;
end
endcase
FixedData = Half;
end
2: begin
FixedData = Word;
MemoryByteSel = 4'b1111;
end
default: begin
FixedData = 0;
MemoryByteSel = 4'b0000;
end
endcase
end
endmodule
| 6.674195 |
module StoreMask (
input memwrite,
input [1:0] addr,
input [2:0] funct3,
output [3:0] mask
);
wire [3:0] mask_Byte;
wire [3:0] mask_Half = addr[1] ? 4'b1100 : 4'b0011;
decoder d2_4 (
.data_in (addr),
.data_out(mask_Byte)
);
assign mask = memwrite ? ((funct3 == 3'b000) ? mask_Byte : //byte
(funct3 == 3'b001) ? mask_Half : //half
4'b1111) : 4'b0000; // word
endmodule
| 6.91903 |
module StoreReservationStation_tb;
`include "Utility.v"
wire [OPCODE_LENGTH - 1:0] op;
wire [31:0] vj, vk;
wire [31:0] res;
wire [31:0] vi;
wire [REORDER_BUFFER_SIZE_LOG - 1:0] pos;
wire [FUNCTION_UNIT_NUMBER_LOG - 1:0] qi, qj, qk;
wire [FUNCTION_UNIT_NUMBER * 32 - 1:0] commonDataBus;
reg clk, reset;
wire busy;
wire [REORDER_BUFFER_SIZE_LOG - 1:0] writeBuffer_position;
wire [31:0] writeBuffer_value;
wire [31:0] writeBuffer_storeValue;
StoreReservationStation storeRs (
op,
pos,
qi,
vi,
qj,
vj,
qk,
vk,
commonDataBus,
busy,
writeBuffer_position,
writeBuffer_value,
writeBuffer_storeValue,
reset,
clk
);
always #0.5 clk = ~clk;
initial begin
clk = 0;
reset = 1;
#0.5 reset = 0;
end
wire [661:0] data[1:0];
assign data[0] = {OPCODE_SW, 4'd0, 4'd0, 32'd0, 4'bx, 32'd5, 4'bx, 32'd7, 512'bx, 32'd12};
assign data[1] = {OPCODE_SW, 4'd0, 4'd0, 32'd1, 4'b0, 32'bx, 4'bx, 32'd7, 512'd5, 32'd12};
assign {op, pos, qi, vi, qj, vj, qk, vk, commonDataBus, res} = data[num];
integer num = 0;
always @(posedge clk) begin
#3.71;
if (num < 2) begin
$display(
"op = %d, pos = %d, qi = %d, vi = %d, qj = %d, vj = %d, qk = %d, vk = %d, commonDataBus = %b, writeBuffer_storeValue = %d, pos = %d, AC = %d",
op, pos, qi, vi, qj, vj, qk, vk, commonDataBus, writeBuffer_storeValue,
writeBuffer_value, (writeBuffer_value === res && vi === writeBuffer_storeValue));
end else $finish;
num = num + 1;
end
endmodule
| 6.686507 |
module storeRS (
input wire clock,
input wire [5:0] operatorType,
input wire [31:0] data1,
input wire [5:0] q1,
input wire [31:0] data2,
input wire [5:0] q2,
input reset,
input wire [31:0] offset_in,
input wire [5:0] destRobNum,
output reg [5:0] robNum_out,
output reg available,
input wire iscast,
input wire [31:0] cdbdata,
input wire [5:0] robNum,
input wire iscast2,
input wire [31:0] cdbdata2,
input wire [5:0] robNum2,
input wire ready,
input wire [31:0] value,
output reg [31:0] data1_out,
output reg [31:0] data2_out,
output reg storeEnable,
output reg [5:0] index,
input wire funcUnitEnable
);
parameter swOp = 6'b000111;
parameter invalidNum = 6'b010000;
reg [82:0] rs[0:3];
reg [5:0] destRob[0:3];
reg [31:0] offset[0:3];
integer i;
initial begin
for (i = 0; i < 4; i = i + 1) begin
rs[i] = 82'b0;
end
available = 1'b1;
storeEnable = 1'b0;
end
always @(posedge reset) begin
robNum_out = invalidNum;
for (i = 0; i < 4; i = i + 1) begin
rs[i][82:82] = 1'b0;
end
available = 1'b1;
end
always @(posedge iscast or posedge iscast2) begin
for (i = 0; i < 4; i = i + 1) begin
if (rs[i][82:82] == 1'b1 && iscast == 1'b1) begin
if (rs[i][11:6] == robNum) begin
rs[i][75:44] = cdbdata;
rs[i][11:6] = invalidNum;
end
if (rs[i][5:0] == robNum) begin
rs[i][43:12] = cdbdata;
rs[i][5:0] = invalidNum;
end
end
if (rs[i][82:82] == 1'b1 && iscast2 == 1'b1) begin
if (rs[i][11:6] == robNum2) begin
rs[i][75:44] = cdbdata2;
rs[i][11:6] = invalidNum;
end
if (rs[i][5:0] == robNum2) begin
rs[i][43:12] = cdbdata2;
rs[i][5:0] = invalidNum;
end
end
end
end
reg breakmark;
always @(posedge clock) begin
breakmark = 1'b0;
storeEnable = 1'b0;
for (i = 0; i < 4; i = i + 1) begin
if (rs[i][82:82] == 1'b1 && breakmark == 1'b0) begin
//$display("entered.");
if (rs[i][11:6] == invalidNum && rs[i][5:0] == invalidNum) begin
//$display("entered.");
rs[i][82:82] = 1'b0;
robNum_out = destRob[i];
data1_out = rs[i][75:44];
data2_out = rs[i][43:12] + offset[i];
available = 1'b1;
breakmark = 1'b1;
storeEnable = 1'b1;
end
end
end
end
reg [31:0] data1_tmp;
reg [ 5:0] q1_tmp;
reg [31:0] data2_tmp;
reg [ 5:0] q2_tmp;
always @(posedge funcUnitEnable) begin
if (operatorType == swOp) begin
robNum_out = robNum;
index = q1;
#0.01
data1_tmp = data1;
q1_tmp = q1;
if (index < 16 && ready == 1'b1) begin
data1_tmp = value;
q1_tmp = invalidNum;
end
index = q2;
#0.01
data2_tmp = data2;
q2_tmp = q2;
if (index < 16 && ready == 1'b1) begin
data2_tmp = value;
q2_tmp = invalidNum;
end
index = invalidNum;
breakmark = 1'b0;
for (i = 0; i < 4; i = i + 1) begin
if (rs[i][82:82] == 1'b0 && breakmark == 1'b0) begin
destRob[i] = destRobNum;
offset[i] = offset_in;
rs[i][82:82] = 1'b1;
rs[i][81:76] = operatorType;
rs[i][75:44] = data1_tmp;
rs[i][43:12] = data2_tmp;
rs[i][11:6] = q1_tmp;
rs[i][5:0] = q2_tmp;
breakmark = 1'b1;
end
end
available = 1'b0;
breakmark = 1'b0;
for (i = 0; i < 4; i = i + 1) begin
if (rs[i][82:82] == 1'b0 && breakmark == 1'b0) begin
available = 1'b1;
breakmark = 1'b1;
end
end
end
end
endmodule
| 6.612874 |
module storeunit (
input clk,
output [31:0] data_out,
output [7:0] storesig,
input [31:0] reg0,
input [31:0] reg1,
input [31:0] reg2,
input [31:0] reg3,
input [39:0] instbus1,
input [39:0] instbus2,
input [39:0] addbus,
input [39:0] multbus,
input [39:0] loadbus
);
reg [31:0] ST0;
reg [31:0] ST1;
reg [7:0] ST0_t;
reg [7:0] ST1_t;
reg [1:0] ST0_count;
reg [1:0] ST1_count;
reg ST0_rdy;
reg ST1_rdy;
`define LOAD 8'h01
`define STORE 8'h02
`define ADD 8'h03
`define MULTI 8'h04
`define R0 8'h10
`define R1 8'h11
`define R2 8'h12
`define R3 8'h13
`define A0 8'h20
`define A1 8'h21
`define A2 8'h22
`define M0 8'h30
`define M1 8'h31
`define LD0 8'h40
`define LD1 8'h41
`define ST0 8'h50
`define ST1 8'h51
initial begin
ST0_count <= 2;
ST1_count <= 2;
end
always @(instbus1) begin
case (instbus1[7:0])
`ST0: begin
case (instbus1[39:32])
`R0: begin
ST0 <= reg0;
ST0_rdy <= 1;
end
`R1: begin
ST0 <= reg1;
ST0_rdy <= 1;
end
`R2: begin
ST0 <= reg2;
ST0_rdy <= 1;
end
`R3: begin
ST0 <= reg3;
ST0_rdy <= 1;
end
default: ST0_t <= instbus1[39:32];
endcase
end
`ST1: begin
case (instbus1[39:32])
`R0: begin
ST1 <= reg0;
ST1_rdy <= 1;
end
`R1: begin
ST1 <= reg1;
ST1_rdy <= 1;
end
`R2: begin
ST1 <= reg2;
ST1_rdy <= 1;
end
`R3: begin
ST1 <= reg3;
ST1_rdy <= 1;
end
default: ST1_t <= instbus1[39:32];
endcase
end
endcase
end
always @(instbus2) begin
case (instbus2[7:0])
`ST0: begin
case (instbus2[39:32])
`R0: begin
ST0 <= reg0;
ST0_rdy <= 1;
end
`R1: begin
ST0 <= reg1;
ST0_rdy <= 1;
end
`R2: begin
ST0 <= reg2;
ST0_rdy <= 1;
end
`R3: begin
ST0 <= reg3;
ST0_rdy <= 1;
end
default: ST0_t <= instbus2[39:32];
endcase
end
`ST1: begin
case (instbus2[39:32])
`R0: begin
ST1 <= reg0;
ST1_rdy <= 1;
end
`R1: begin
ST1 <= reg1;
ST1_rdy <= 1;
end
`R2: begin
ST1 <= reg2;
ST1_rdy <= 1;
end
`R3: begin
ST1 <= reg3;
ST1_rdy <= 1;
end
default: ST1_t <= instbus2[39:32];
endcase
end
endcase
end
always @(posedge clk) begin
if (ST0_t == addbus[39:32]) begin
ST0 <= addbus[31:0];
ST0_t <= 0;
ST0_rdy <= 1;
end else if (ST0_t == multbus[39:32]) begin
ST0 <= multbus[31:0];
ST0_t <= 0;
ST0_rdy <= 1;
end else if (ST0_t == loadbus[39:32]) begin
ST0 <= loadbus[31:0];
ST0_t <= 0;
ST0_rdy <= 1;
end
if (ST1_t == addbus[39:32]) begin
ST1 <= addbus[31:0];
ST1_t <= 0;
ST1_rdy <= 1;
end else if (ST1_t == multbus[39:32]) begin
ST1 <= multbus[31:0];
ST1_t <= 0;
ST1_rdy <= 1;
end else if (ST1_t == loadbus[39:32]) begin
ST1 <= loadbus[31:0];
ST1_t <= 0;
ST1_rdy <= 1;
end
end
always @(negedge clk) begin
if (ST0_count != 2) ST0_count <= ST0_count + 1;
if (ST1_count != 2) ST1_count <= ST1_count + 1;
if (ST0_rdy == 1) begin
ST0_count <= 0;
ST0_rdy <= 0;
end else if (ST1_rdy == 1) begin
ST1_count <= 0;
ST1_rdy <= 0;
end
end
assign data_out = (ST0_count == 1) ? ST0 : ((ST1_count == 1) ? ST1 : 32'hz);
assign storesig = (ST0_count == 1) ? `ST0 : ((ST1_count == 1) ? `ST1 : 8'hz);
endmodule
| 6.559264 |
module storeypeak_clock_gen (
input wire i_clk,
output wire o_clk,
output wire o_rst
);
wire clk_fb;
wire locked;
reg [9:0] r;
assign o_rst = r[9];
always @(posedge o_clk)
if (locked) r <= {r[8:0], 1'b0};
else r <= 10'b1111111111;
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("125.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(1),
.output_clock_frequency0("16.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst(1'b0),
.outclk({o_clk}),
.locked(locked),
.fboutclk(),
.fbclk(1'b0),
.refclk(i_clk)
);
endmodule
| 7.387098 |
module instantiates two Store_Hex modules
//These modules share the same hex_in,reset, and enter
//They have seperate outputs, Four_hex1 and Four_hex2
//They have opposite enables meaning we will only store to one module at a time
module Store_2_Hex(
input [3:0] hex_in,
input enable,reset,enter,
output [15:0] Four_hex1,
output [15:0] Four_hex2,
output [3:0] hex_guess1, hex_guess2, hex_guess3, hex_guess4, hex_set1, hex_set2, hex_set3, hex_set4,
output [1:0] counter_guess, counter_set
);
Store_Hex store_guess(hex_in,reset,enter,enable,Four_hex1, hex_guess1, hex_guess2, hex_guess3, hex_guess4,counter_guess);
Store_Hex store_set(hex_in,reset,enter,~enable,Four_hex2, hex_set1, hex_set2, hex_set3, hex_set4,counter_set);
endmodule
| 7.670485 |
module store_b_w_e_gen (
input [1 : 0] addr,
input [2 : 0] store_sel,
output reg [3 : 0] b_w_en
);
wire [1 : 0] byte_sel;
assign byte_sel = addr ^ {2{`BigEndianCPU}};
always @(*) begin
case (store_sel)
// SB
3'b000: begin
case (byte_sel)
0: b_w_en = 4'b0001;
1: b_w_en = 4'b0010;
2: b_w_en = 4'b0100;
3: b_w_en = 4'b1000;
default: b_w_en = 4'b1111;
endcase
end
// SH, assume that addr[0] == 0 for address alignment
3'b001: begin
case (byte_sel[1])
0: b_w_en = 4'b0011;
1: b_w_en = 4'b1100;
default: b_w_en = 4'b1111;
endcase
end
// SW
3'b010: b_w_en = 4'b1111;
// SWL
3'b011: begin
case (byte_sel)
0: b_w_en = 4'b0001;
1: b_w_en = 4'b0011;
2: b_w_en = 4'b0111;
3: b_w_en = 4'b1111;
default: b_w_en = 4'b1111;
endcase
end
// SWR
3'b100: begin
case (byte_sel)
0: b_w_en = 4'b1111;
1: b_w_en = 4'b1110;
2: b_w_en = 4'b1100;
3: b_w_en = 4'b1000;
default: b_w_en = 4'b1111;
endcase
end
default: b_w_en = 4'b1111;
endcase
end
endmodule
| 7.854506 |
module store_data_port_m_axi_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire sclk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge sclk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge sclk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge sclk) begin
if (reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge sclk) begin
if (reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 8.12371 |
module store_data_port_m_axi_fifo #(
parameter DATA_BITS = 8,
DEPTH = 16,
DEPTH_BITS = 4
) (
input wire sclk,
input wire reset,
input wire sclk_en,
output reg empty_n,
output reg full_n,
input wire rdreq,
input wire wrreq,
output reg [DATA_BITS-1:0] q,
input wire [DATA_BITS-1:0] data
);
//------------------------Parameter----------------------
//------------------------Local signal-------------------
wire push;
wire pop;
wire full_cond;
reg data_vld;
reg [DEPTH_BITS-1:0] pout;
reg [ DATA_BITS-1:0] mem [0:DEPTH-1];
//------------------------Body---------------------------
assign push = full_n & wrreq;
assign pop = data_vld & (~(empty_n & ~rdreq));
if (DEPTH >= 2) begin
assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
end else begin
assign full_cond = push && ~pop;
end
// q
always @(posedge sclk) begin
if (reset) q <= 0;
else if (sclk_en) begin
if (~(empty_n & ~rdreq)) q <= mem[pout];
end
end
// empty_n
always @(posedge sclk) begin
if (reset) empty_n <= 1'b0;
else if (sclk_en) begin
if (~(empty_n & ~rdreq)) empty_n <= data_vld;
end
end
// data_vld
always @(posedge sclk) begin
if (reset) data_vld <= 1'b0;
else if (sclk_en) begin
if (push) data_vld <= 1'b1;
else if (~push && pop && pout == 1'b0) data_vld <= 1'b0;
end
end
// full_n
always @(posedge sclk) begin
if (reset) full_n <= 1'b1;
else if (sclk_en) begin
if (pop) full_n <= 1'b1;
else if (full_cond) full_n <= 1'b0;
end
end
// pout
always @(posedge sclk) begin
if (reset) pout <= 1'b0;
else if (sclk_en) begin
if (push & ~pop & data_vld) pout <= pout + 1'b1;
else if (~push && pop && pout != 1'b0) pout <= pout - 1'b1;
end
end
integer i;
always @(posedge sclk) begin
if (sclk_en) begin
if (push) begin
for (i = 0; i < DEPTH - 1; i = i + 1) begin
mem[i+1] <= mem[i];
end
mem[0] <= data;
end
end
end
endmodule
| 8.12371 |
module store_data_port_m_axi_buffer #(
parameter MEM_STYLE = "block",
DATA_WIDTH = 32,
ADDR_WIDTH = 5,
DEPTH = 32
) (
// system signal
input wire clk,
input wire reset,
input wire sclk_en,
// write
output wire if_full_n,
input wire if_write_ce,
input wire if_write,
input wire [DATA_WIDTH-1:0] if_din,
// read
output wire if_empty_n,
input wire if_read_ce,
input wire if_read,
output wire [DATA_WIDTH-1:0] if_dout
);
//------------------------Parameter----------------------
//------------------------Local signal-------------------
(* ram_style = MEM_STYLE *)
reg [DATA_WIDTH-1:0] mem [0:DEPTH-1];
reg [DATA_WIDTH-1:0] q_buf = 1'b0;
reg [ADDR_WIDTH-1:0] waddr = 1'b0;
reg [ADDR_WIDTH-1:0] raddr = 1'b0;
wire [ADDR_WIDTH-1:0] wnext;
wire [ADDR_WIDTH-1:0] rnext;
wire push;
wire pop;
reg [ADDR_WIDTH-1:0] usedw = 1'b0;
reg full_n = 1'b1;
reg empty_n = 1'b0;
reg [DATA_WIDTH-1:0] q_tmp = 1'b0;
reg show_ahead = 1'b0;
reg [DATA_WIDTH-1:0] dout_buf = 1'b0;
reg dout_valid = 1'b0;
//------------------------Instantiation------------------
//------------------------Task and function--------------
//------------------------Body---------------------------
assign if_full_n = full_n;
assign if_empty_n = dout_valid;
assign if_dout = dout_buf;
assign push = full_n & if_write_ce & if_write;
assign pop = empty_n & if_read_ce & (~dout_valid | if_read);
assign wnext = !push ? waddr : (waddr == DEPTH - 1) ? 1'b0 : waddr + 1'b1;
assign rnext = !pop ? raddr : (raddr == DEPTH - 1) ? 1'b0 : raddr + 1'b1;
// waddr
always @(posedge clk) begin
if (reset == 1'b1) waddr <= 1'b0;
else if (sclk_en) waddr <= wnext;
end
// raddr
always @(posedge clk) begin
if (reset == 1'b1) raddr <= 1'b0;
else if (sclk_en) raddr <= rnext;
end
// usedw
always @(posedge clk) begin
if (reset == 1'b1) usedw <= 1'b0;
else if (sclk_en)
if (push & ~pop) usedw <= usedw + 1'b1;
else if (~push & pop) usedw <= usedw - 1'b1;
end
// full_n
always @(posedge clk) begin
if (reset == 1'b1) full_n <= 1'b1;
else if (sclk_en)
if (push & ~pop) full_n <= (usedw != DEPTH - 1);
else if (~push & pop) full_n <= 1'b1;
end
// empty_n
always @(posedge clk) begin
if (reset == 1'b1) empty_n <= 1'b0;
else if (sclk_en)
if (push & ~pop) empty_n <= 1'b1;
else if (~push & pop) empty_n <= (usedw != 1'b1);
end
// mem
always @(posedge clk) begin
if (push) mem[waddr] <= if_din;
end
// q_buf
always @(posedge clk) begin
q_buf <= mem[rnext];
end
// q_tmp
always @(posedge clk) begin
if (reset == 1'b1) q_tmp <= 1'b0;
else if (sclk_en) if (push) q_tmp <= if_din;
end
// show_ahead
always @(posedge clk) begin
if (reset == 1'b1) show_ahead <= 1'b0;
else if (sclk_en)
if (push && usedw == pop) show_ahead <= 1'b1;
else show_ahead <= 1'b0;
end
// dout_buf
always @(posedge clk) begin
if (reset == 1'b1) dout_buf <= 1'b0;
else if (sclk_en) if (pop) dout_buf <= show_ahead ? q_tmp : q_buf;
end
// dout_valid
always @(posedge clk) begin
if (reset == 1'b1) dout_valid <= 1'b0;
else if (sclk_en)
if (pop) dout_valid <= 1'b1;
else if (if_read_ce & if_read) dout_valid <= 1'b0;
end
endmodule
| 8.12371 |
module store_data_port_m_axi_decoder #(
parameter DIN_WIDTH = 3
) (
input wire [ DIN_WIDTH-1:0] din,
output reg [2**DIN_WIDTH-1:0] dout
);
integer i;
always @(din) begin
dout = {2 ** DIN_WIDTH{1'b0}};
for (i = 0; i < din; i = i + 1) dout[i] = 1'b1;
end
endmodule
| 8.12371 |
module store_data_translator (
write_data, // data in least significant position
d_address,
store_size,
d_byteena,
d_writedataout // shifted data to coincide with address
);
//parameter WIDTH=32;
input [31:0] write_data;
input [1:0] d_address;
input [1:0] store_size;
output [3:0] d_byteena;
output [31:0] d_writedataout;
reg [ 3:0] d_byteena;
reg [31:0] d_writedataout;
always @(write_data or d_address or store_size) begin
case (store_size)
2'b11:
case (d_address[1:0])
2'b00: begin
d_byteena = 4'b1000;
d_writedataout = {write_data[7:0], 24'b0};
end
2'b01: begin
d_byteena = 4'b0100;
d_writedataout = {8'b0, write_data[7:0], 16'b0};
end
2'b10: begin
d_byteena = 4'b0010;
d_writedataout = {16'b0, write_data[7:0], 8'b0};
end
default: begin
d_byteena = 4'b0001;
d_writedataout = {24'b0, write_data[7:0]};
end
endcase
2'b01:
case (d_address[1])
1'b0: begin
d_byteena = 4'b1100;
d_writedataout = {write_data[15:0], 16'b0};
end
default: begin
d_byteena = 4'b0011;
d_writedataout = {16'b0, write_data[15:0]};
end
endcase
default: begin
d_byteena = 4'b1111;
d_writedataout = write_data;
end
endcase
end
endmodule
| 8.280191 |
module store_filter (
input wire [31:0] busB,
input wire sb,
input wire sh,
output reg [31:0] mem_write_data
);
wire [31:0] det_sb_out;
wire [31:0] mem_write_data_out;
mux_32 det_sb (
.sel(sb),
.src0(busB),
.src1({24'b0, busB[7:0]}),
.z(det_sb_out)
);
mux_32 det_sh (
.sel(sh),
.src0(det_sb_out),
.src1({16'b0, busB[15:0]}),
.z(mem_write_data_out)
);
always @* mem_write_data = mem_write_data_out;
endmodule
| 7.093907 |
module then concatenates the 4 numbers into the output password
module Store_Hex(
//Input hex_in takes in a 4 bit binary number representing the position of the switches
input [3:0] hex_in,
//Input reset resets the hex input process by resetting the counter
input reset,
//Input enter stores the current hex_in into hex[i]
input enter,
input enable,
//Output of the 4 hex number inputs as a 16 bit password
output reg [15:0] password,
//hex[i] stores the past inputted hex numbers
output reg [3:0] hex1,hex2,hex3,hex4,
//Counts the number of hex numbers the user has entered, when it reaches 2'b11 and the user presses enter,
//the 4 stored hex numbers are concatenated into password
output reg [1:0] counter
);
reg [15:0] undefined_16bit;
reg [3:0] undefined_hex;
always @(posedge enter or posedge reset)begin
if(reset) begin
counter = 2'b00;
password = undefined_16bit;
hex1 = undefined_hex;
hex2 = undefined_hex;
hex3 = undefined_hex;
hex4 = undefined_hex;
end
else if(enter && enable) begin
case(counter)
2'b00: begin
hex1 = hex_in;
counter = counter + 2'b01;
end
2'b01: begin
hex2 = hex_in;
counter = counter + 2'b01;
end
2'b10: begin
hex3 = hex_in;
counter = counter + 2'b01;
end
2'b11: begin
hex4 = hex_in;
counter = 2'b00;
password = {hex1,hex2,hex3,hex4};
end
endcase
end
end
endmodule
| 6.582001 |
module StoreMask (
input wire [31:0] B,
input wire [31:0] MR,
input wire [ 1:0] CT,
output reg [31:0] OUT
);
always @(*) begin
case (CT)
2'b00: OUT = B;
2'b01: begin
OUT[31:16] = MR[31:16];
OUT[15:0] = B[15:0];
end
2'b10: begin
OUT[31:8] = MR[31:8];
OUT[7:0] = B[7:0];
end
default: OUT = B;
endcase
end
endmodule
| 6.91903 |
module store_shifter (
input [1 : 0] addr,
input [2 : 0] store_sel,
input [31 : 0] rt_data,
output reg [31 : 0] real_rt_data
);
wire [1 : 0] byte_sel;
assign byte_sel = addr ^ {2{`BigEndianCPU}};
always @(*) begin
case (store_sel)
// SB
3'b000: begin
case (byte_sel)
0: real_rt_data = rt_data;
1: real_rt_data = rt_data << 8;
2: real_rt_data = rt_data << 16;
3: real_rt_data = rt_data << 24;
default: real_rt_data = rt_data;
endcase
end
// SH, assume that assr[0] == 0 for address alignment
3'b001: begin
case (byte_sel[1])
0: real_rt_data = rt_data;
1: real_rt_data = rt_data << 16;
default: real_rt_data = rt_data;
endcase
end
// SW
3'b010: real_rt_data = rt_data;
// SWL
3'b011: begin
case (byte_sel)
0: real_rt_data = rt_data >> 24;
1: real_rt_data = rt_data >> 16;
2: real_rt_data = rt_data >> 8;
3: real_rt_data = rt_data;
default: real_rt_data = rt_data;
endcase
end
// SWR
3'b100: begin
case (byte_sel)
0: real_rt_data = rt_data;
1: real_rt_data = rt_data << 8;
2: real_rt_data = rt_data << 16;
3: real_rt_data = rt_data << 24;
default: real_rt_data = rt_data;
endcase
end
default: real_rt_data = rt_data;
endcase
end
endmodule
| 8.503495 |
module PIPELINE (
a,
b,
c,
d,
clk,
z
);
parameter W1 = 5, W2 = 2 * W1;
input [W1-1:0] a, b, c, d;
input clk;
output [W2-1:0] z;
reg [W2-1:0] z, z1;
always @(posedge clk) begin
z1 <= a * b + c - d; // Pipeline register #1
z <= z1; // Pipeline register #2
end
endmodule
| 7.740205 |
module DONT_PIPELINE (
a,
b,
c,
clk,
sel,
z
);
parameter W1 = 10, W2 = W1, Wsel = 2;
input [W1-1:0] a, b, c;
input clk;
input [Wsel-1:0] sel;
output [W2-1:0] z;
reg [W2-1:0] z, G1, G2, SUM;
GLUE I_GLUE (
.a(a),
.b(b),
.y(G1),
.z(G2)
);
ARITH I_ARITH (
.a (G1),
.b (G2),
.sum(SUM)
);
RANDOM I_RANDOM (
.a (c),
.b (SUM),
.clk(clk),
.sel(sel),
.z (z)
);
endmodule
| 6.857666 |
module ARITH (
a,
b,
sum
);
parameter W1 = 10, W2 = W1;
input [W1-1:0] a, b;
output [W2-1:0] sum;
reg [W2-1:0] sum;
always @(a, b) begin
sum = a + b;
end
endmodule
| 7.169472 |
module sto_reg (
clk,
rst,
load,
i,
o
);
// parameters
parameter WIDTH = 32;
// common ports
input clk;
input rst;
// control ports
input load;
// input ports
input signed [WIDTH-1:0] i;
// output ports
output signed [WIDTH-1:0] o;
// wires
wire signed [WIDTH-1:0] o_mux;
// registers
reg signed [WIDTH-1:0] o;
multiplexer #(
.WIDTH(WIDTH)
) inst_multiplexer (
.i_a(o),
.i_b(i),
.sel(load),
.o (o_mux)
);
always @(posedge clk or posedge rst) begin
if (rst) o <= {WIDTH{1'b0}};
else o <= o_mux;
end
endmodule
| 7.964978 |
module StP #(
parameter n = 8,
m = 32
) (
input clk,
rst,
enable, //enable = 1 means loading time, enable =0 means loading is finished
input ser_in,
input grant, // send by bus and means 8-bit is written to the i_mem
output reg d_valid,
shift_done, //start = 1 means loading instruction into I_memory is done
output reg [n-1:0] par_out, // data is written into SRAM based on 8-bit width, thus each instruction needs 4*8-bit
output [m-1:0] imem_addr
);
reg [ 3:0] count;
reg [m-1:0] addr;
assign imem_addr = addr;
always @(posedge clk) begin
if (rst) begin
count <= 0;
d_valid <= 0;
shift_done <= 0;
addr <= 0;
end else if (enable) begin
shift_done <= 0;
if (count == 0) begin
d_valid <= 0;
end
if (count == 4'b1000) begin
count <= 0;
d_valid <= 1;
end else begin
par_out <= par_out >> 1;
par_out[n-1] <= ser_in;
count <= count + 1;
end
if (grant) // go to the next i_mem address
addr <= addr + 1;
else addr <= addr;
end else if (!enable) shift_done <= 1;
end
endmodule
| 7.653297 |
module stp02 (
input wire [9:0] acq_data_in, // tap.acq_data_in
input wire [2:0] acq_trigger_in, // .acq_trigger_in
input wire acq_clk // acq_clk.clk
);
sld_signaltap #(
.SLD_DATA_BITS (10),
.SLD_SAMPLE_DEPTH (1024),
.SLD_RAM_BLOCK_TYPE ("AUTO"),
.SLD_STORAGE_QUALIFIER_MODE ("OFF"),
.SLD_TRIGGER_BITS (3),
.SLD_TRIGGER_LEVEL (1),
.SLD_TRIGGER_IN_ENABLED (0),
.SLD_ENABLE_ADVANCED_TRIGGER(0),
.SLD_TRIGGER_LEVEL_PIPELINE (1),
.SLD_TRIGGER_PIPELINE (0),
.SLD_RAM_PIPELINE (0),
.SLD_COUNTER_PIPELINE (0),
.SLD_NODE_INFO (806383104),
.SLD_INCREMENTAL_ROUTING (0),
.SLD_NODE_CRC_BITS (32),
.SLD_NODE_CRC_HIWORD (52490),
.SLD_NODE_CRC_LOWORD (1874)
) signaltap_ii_logic_analyzer_0 (
.acq_data_in (acq_data_in), // input, width = 10, tap.acq_data_in
.acq_trigger_in(acq_trigger_in), // input, width = 3, .acq_trigger_in
.acq_clk (acq_clk) // input, width = 1, acq_clk.clk
);
endmodule
| 7.005585 |
module stp02 (
input wire [9:0] acq_data_in, // tap.acq_data_in
input wire [2:0] acq_trigger_in, // .acq_trigger_in
input wire acq_clk // acq_clk.clk
);
endmodule
| 7.005585 |
module stpu_sopc_tb ();
reg CLOCK_50;
reg rst;
initial begin
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
initial begin
rst = `RstEnable;
#195 rst = `RstDisable;
#4100 $stop;
end
stpu_sopc stpu_sopc0 (
.clk(CLOCK_50),
.rst(rst)
);
endmodule
| 6.645179 |
module stp (
input wire [79:0] acq_data_in, // tap.acq_data_in
input wire [ 2:0] acq_trigger_in, // .acq_trigger_in
input wire acq_clk // acq_clk.clk
);
endmodule
| 7.32169 |
module stp_chk (
input wire CLK,
input wire RST,
input wire sampled_bit,
input wire Enable,
output reg stp_err
);
// error check
always @(posedge CLK or negedge RST) begin
if (!RST) begin
stp_err <= 'b0;
end else if (Enable) begin
stp_err <= 1'b1 ^ sampled_bit;
end
end
endmodule
| 8.119117 |
module stq_buf_A (
clk,
rst,
stallA,
excpt,
wrt0_en,
wrt0_addrE,
wrt0_addrO,
wrt1_en,
wrt1_addrE,
wrt1_addrO,
chk0_en,
chk0_addrEO,
chk0_addrE,
chk0_addrO,
chk1_en,
chk1_addrEO,
chk1_addrE,
chk1_addrO,
chk2_en,
chk2_addrEO,
chk2_addrE,
chk2_addrO,
chk3_en,
chk3_addrEO,
chk3_addrE,
chk3_addrO,
chk4_en,
chk4_addrEO,
chk4_addrE,
chk4_addrO,
chk5_en,
chk5_addrEO,
chk5_addrE,
chk5_addrO,
upd0_en,
upd1_en,
free_en,
free,
upd,
passe,
passe_en
);
localparam WIDTH = 36;
input clk;
input rst;
input stallA;
input excpt;
input wrt0_en;
input [WIDTH-1:0] wrt0_addrE;
input [WIDTH-1:0] wrt0_addrO;
input wrt1_en;
input [WIDTH-1:0] wrt1_addrE;
input [WIDTH-1:0] wrt1_addrO;
input chk0_en;
output [1:0] chk0_addrEO;
input [WIDTH-1:0] chk0_addrE;
input [WIDTH-1:0] chk0_addrO;
input chk1_en;
output [1:0] chk1_addrEO;
input [WIDTH-1:0] chk1_addrE;
input [WIDTH-1:0] chk1_addrO;
input chk2_en;
output [1:0] chk2_addrEO;
input [WIDTH-1:0] chk2_addrE;
input [WIDTH-1:0] chk2_addrO;
input chk3_en;
output [1:0] chk3_addrEO;
input [WIDTH-1:0] chk3_addrE;
input [WIDTH-1:0] chk3_addrO;
input chk4_en;
output [1:0] chk4_addrEO;
input [WIDTH-1:0] chk4_addrE;
input [WIDTH-1:0] chk4_addrO;
input chk5_en;
output [1:0] chk5_addrEO;
input [WIDTH-1:0] chk5_addrE;
input [WIDTH-1:0] chk5_addrO;
input upd0_en;
input upd1_en;
input free_en;
output reg free;
output reg upd;
output reg passe;
input passe_en;
reg [WIDTH-1:0] addrE;
reg [WIDTH-1:0] addrO;
// reg upd;
assign chk0_addrEO[0] = chk0_addrE == addrE && ~free && ~passe;
assign chk1_addrEO[0] = chk1_addrE == addrE && ~free && ~passe;
assign chk2_addrEO[0] = chk2_addrE == addrE && ~free && ~passe;
assign chk3_addrEO[0] = chk3_addrE == addrE && ~free && ~passe;
assign chk4_addrEO[0] = chk4_addrE == addrE && ~free && ~passe;
assign chk5_addrEO[0] = chk5_addrE == addrE && ~free && ~passe;
assign chk0_addrEO[1] = chk0_addrO == addrO && ~free && ~passe;
assign chk1_addrEO[1] = chk1_addrO == addrO && ~free && ~passe;
assign chk2_addrEO[1] = chk2_addrO == addrO && ~free && ~passe;
assign chk3_addrEO[1] = chk3_addrO == addrO && ~free && ~passe;
assign chk4_addrEO[1] = chk4_addrO == addrO && ~free && ~passe;
assign chk5_addrEO[1] = chk5_addrO == addrO && ~free && ~passe;
always @(posedge clk) begin
if (rst) begin
addrE <= 0;
addrO <= 0;
free <= 1'b1;
upd <= 1'b1;
passe <= 1'b0;
end else begin
if (wrt0_en) begin
addrE <= wrt0_addrE;
addrO <= wrt0_addrO;
free <= 1'b0;
//upd<=1'b0;
passe <= 1'b0;
end
if (wrt1_en) begin
addrE <= wrt1_addrE;
addrO <= wrt1_addrO;
free <= 1'b0;
//upd<=1'b0;
passe <= 1'b0;
end
if (upd0_en | upd1_en) begin
upd <= 1'b1;
end
if (passe_en) begin
passe <= 1'b1;
upd <= 1'b0;
end
if (free_en) begin
free <= 1'b1;
passe <= 1'b0;
addrE <= 36'bz;
addrO <= 36'bz;
end
if (excpt & free & passe) begin
passe <= 1'b0;
end
end
end
endmodule
| 6.60366 |
module stq_adata (
clk,
rst,
wrt0_en,
wrt0_WQ,
wrt0_adata,
wrt1_en,
wrt1_WQ,
wrt1_adata,
upd0_WQ,
upd0_adata,
upd1_WQ,
upd1_adata
);
input clk;
input rst;
input wrt0_en;
input [5:0] wrt0_WQ;
input [4:0] wrt0_adata;
input wrt1_en;
input [5:0] wrt1_WQ;
input [4:0] wrt1_adata;
input [5:0] upd0_WQ;
output [4:0] upd0_adata;
input [5:0] upd1_WQ;
output [4:0] upd1_adata;
reg [4:0] BGN[63:0];
assign upd0_adata = BGN[upd0_WQ];
assign upd1_adata = BGN[upd1_WQ];
always @(posedge clk) begin
if (wrt1_en) BGN[wrt1_WQ] <= wrt1_adata;
if (wrt0_en) BGN[wrt0_WQ] <= wrt0_adata;
end
endmodule
| 6.883144 |
module stq_data (
clk,
rst,
wrt0_en,
wrt0_data,
wrt1_en,
wrt1_data,
chk0_en,
chk0_data,
chk1_en,
chk1_data,
chk2_en,
chk2_data,
chk3_en,
chk3_data,
chk4_en,
chk4_data,
chk5_en,
chk5_data,
chk6_en,
chk6_data,
chk7_en,
chk7_data
);
parameter WIDTH = 32;
input clk;
input rst;
input wrt0_en;
input [WIDTH-1:0] wrt0_data;
input wrt1_en;
input [WIDTH-1:0] wrt1_data;
input chk0_en;
output [WIDTH-1:0] chk0_data;
input chk1_en;
output [WIDTH-1:0] chk1_data;
input chk2_en;
output [WIDTH-1:0] chk2_data;
input chk3_en;
output [WIDTH-1:0] chk3_data;
input chk4_en;
output [WIDTH-1:0] chk4_data;
input chk5_en;
output [WIDTH-1:0] chk5_data;
input chk6_en;
output [WIDTH-1:0] chk6_data;
input chk7_en;
output [WIDTH-1:0] chk7_data;
reg [WIDTH-1:0] data;
assign chk0_data = chk0_en ? data : 'z;
assign chk1_data = chk1_en ? data : 'z;
assign chk2_data = chk2_en ? data : 'z;
assign chk3_data = chk3_en ? data : 'z;
assign chk4_data = chk4_en ? data : 'z;
assign chk5_data = chk5_en ? data : 'z;
assign chk6_data = chk6_en ? data : 'z;
assign chk7_data = chk7_en ? data : 'z;
always @(posedge clk) begin
if (wrt0_en) data <= wrt0_data;
if (wrt1_en) data <= wrt1_data;
end
endmodule
| 7.312396 |
module stq_adata_ram (
clk,
rst,
readA_clkEn,
readA_addr,
readA_data,
writeA_wen,
writeA_addr,
writeA_data,
writeB_wen,
writeB_addr,
writeB_data
);
localparam WIDTH = `lsaddr_width + 1; //adata+en
input clk;
input rst;
input read_clkEn;
input [5:0] read_addr;
output [WIDTH-1:0] read_data;
input write_wen;
input [5:0] write_addr;
input [WIDTH-1:0] write_data;
reg [WIDTH-1:0] ram[63:0];
reg [5:0] readA_addr_reg;
assign readA_data = ram[readA_addr_reg];
always @(posedge clk) begin
if (rst) readA_addr_reg <= 6'b0;
else if (readA_clkEn) readA_addr_reg <= readA_addr;
if (writeA_wen) ram[writeA_addr] <= writeA_data;
if (writeB_wen) ram[writeB_addr] <= writeB_data;
end
endmodule
| 7.679879 |
module performs the straight D-Box logic
module Straight_D_Box(
input [31:0] i_data,
output [31:0] o_straightened_data
);
// 1st byte
assign o_straightened_data[0] = i_data[15];
assign o_straightened_data[1] = i_data[6];
assign o_straightened_data[2] = i_data[19];
assign o_straightened_data[3] = i_data[20];
assign o_straightened_data[4] = i_data[28];
assign o_straightened_data[5] = i_data[11];
assign o_straightened_data[6] = i_data[27];
assign o_straightened_data[7] = i_data[16];
// 2nd byte
assign o_straightened_data[8] = i_data[0];
assign o_straightened_data[9] = i_data[14];
assign o_straightened_data[10] = i_data[22];
assign o_straightened_data[11] = i_data[25];
assign o_straightened_data[12] = i_data[4];
assign o_straightened_data[13] = i_data[17];
assign o_straightened_data[14] = i_data[30];
assign o_straightened_data[15] = i_data[9];
// 3rd byte
assign o_straightened_data[16] = i_data[1];
assign o_straightened_data[17] = i_data[7];
assign o_straightened_data[18] = i_data[23];
assign o_straightened_data[19] = i_data[13];
assign o_straightened_data[20] = i_data[31];
assign o_straightened_data[21] = i_data[26];
assign o_straightened_data[22] = i_data[2];
assign o_straightened_data[23] = i_data[8];
// 4th byte
assign o_straightened_data[24] = i_data[18];
assign o_straightened_data[25] = i_data[12];
assign o_straightened_data[26] = i_data[29];
assign o_straightened_data[27] = i_data[5];
assign o_straightened_data[28] = i_data[21];
assign o_straightened_data[29] = i_data[10];
assign o_straightened_data[30] = i_data[3];
assign o_straightened_data[31] = i_data[24];
endmodule
| 7.634754 |
module picdisplay (
output reg [23:0] vga_data,
input [9:0] h_addr,
input [9:0] v_addr,
input clk,
input en
);
//inner signal
reg [18:0] addr;
wire [11:0] data;
pic mypic (
addr,
clk,
data
);
//initial
initial begin
vga_data = 24'd0;
end
//always module
always @(h_addr or v_addr) begin
if (en) begin
addr = {h_addr, v_addr[8:0]};
vga_data = {data[11:8], 4'b0000, data[7:4], 4'b0000, data[3:0], 4'b0000};
end
end
endmodule
| 6.505922 |
module stratixiigx_hssi_aux_clock_div (
clk, // input clock
reset, // reset
enable_d, // enable DPRIO
d, // division factor for DPRIO support
clkout // divided clock
);
input clk, reset;
input enable_d;
input [7:0] d;
output clkout;
parameter clk_divide_by = 1;
parameter extra_latency = 0;
integer clk_edges, m;
reg [2*extra_latency:0] div_n_register;
wire [7:0] d_factor;
assign d_factor = (enable_d === 1'b1) ? d : clk_divide_by;
initial begin
div_n_register = 'b0;
clk_edges = -1;
m = 0;
end
always @(d_factor) begin
div_n_register = 'b0;
clk_edges = -1;
m = 0;
end
always @(posedge clk or negedge clk or posedge reset) begin
if (reset === 1'b1) begin
clk_edges = -1;
div_n_register <= 'b0;
end else begin
if (clk_edges == -1) begin
div_n_register[0] <= clk;
if (clk == 1'b1) clk_edges = 0;
end else if (clk_edges % d_factor == 0) div_n_register[0] <= ~div_n_register[0];
if (clk_edges >= 0 || clk == 1'b1) clk_edges = (clk_edges + 1) % (2 * d_factor);
end
for (m = 0; m < 2 * extra_latency; m = m + 1) div_n_register[m+1] <= div_n_register[m];
end
assign clkout = div_n_register[2*extra_latency];
endmodule
| 6.968456 |
module stratixiigx_hssi_aux_clock_mult (
clk, // input clock
adjust, // adjust frequency
adjust_without_lol,
reset, // reset
enable_m, // enable DPRIO
m, // multiplication factor for DPRIO support
clkout, // multiplied clock
busy // state
);
input clk, adjust, reset;
input adjust_without_lol;
input enable_m;
input [7:0] m;
output clkout;
output [1:0] busy;
reg [1:0] busy;
parameter clk_multiply_by = 1;
`define S2GX_HSSI_CLOCK_MULT_INITIAL 2'b01
`define S2GX_HSSI_CLOCK_MULT_ACTIVE 2'b11
`define S2GX_HSSI_CLOCK_MULT_INACTIVE 2'b00
reg clk_adjust_settled;
real last_rising_edge, clk_period;
integer clk_fast_period, clk_adjust, clk_adjust_interval, clk_adjust_running, clk_sync_period;
reg mult_n;
integer n;
wire [7:0] m_factor;
assign m_factor = (enable_m === 1'b1) ? m : clk_multiply_by;
// At start of reconfiguration, set multiplier to reset state
always @(m_factor) begin
busy <= `S2GX_HSSI_CLOCK_MULT_INITIAL;
last_rising_edge = 0;
mult_n = 'b0;
n = 0;
end
initial begin
busy = `S2GX_HSSI_CLOCK_MULT_INITIAL;
last_rising_edge = 0;
mult_n = 'b0;
n = 0;
end
always @(posedge adjust) busy <= `S2GX_HSSI_CLOCK_MULT_INITIAL;
always @(posedge clk or posedge reset) begin
if (reset === 1'b1) begin
mult_n = 1'b0;
busy <= `S2GX_HSSI_CLOCK_MULT_INITIAL;
end else begin
if (busy == `S2GX_HSSI_CLOCK_MULT_INITIAL && adjust_without_lol == 1'b0) // first rising edge
begin
mult_n = 1'b0;
last_rising_edge = $realtime;
busy <= `S2GX_HSSI_CLOCK_MULT_ACTIVE;
end else begin
if (busy == `S2GX_HSSI_CLOCK_MULT_INITIAL && adjust_without_lol == 1'b1) begin
mult_n = 1'b0;
last_rising_edge = $realtime;
busy <= `S2GX_HSSI_CLOCK_MULT_ACTIVE;
end
if (busy == `S2GX_HSSI_CLOCK_MULT_ACTIVE) // second rising edge
begin
clk_period = $realtime - last_rising_edge;
clk_fast_period = clk_period / m_factor - 0.5;
clk_adjust = clk_period - clk_fast_period * m_factor;
busy <= `S2GX_HSSI_CLOCK_MULT_INACTIVE;
end
mult_n = ~mult_n;
if (clk_adjust > 0) clk_adjust_running = clk_adjust + 1;
clk_adjust_settled = (clk_adjust == 0); // if no adjustment necessary
for (n = m_factor; n >= 1; n = n - 1) begin
if (clk_adjust_settled == 1'b0) begin
clk_adjust_running = clk_adjust_running - 1;
clk_adjust_interval = n / clk_adjust_running;
if (n % clk_adjust_running == 0) clk_adjust_settled = 1'b1;
clk_sync_period = clk_fast_period + 1;
end else begin
if (clk_adjust == 0) clk_sync_period = clk_fast_period;
else begin
if (n % clk_adjust_interval == 0) clk_sync_period = clk_fast_period + 1;
else clk_sync_period = clk_fast_period;
end
end
if (reset == 1'b1) mult_n = 1'b0;
else begin
#(clk_sync_period / 2) mult_n = ~mult_n;
if (n > 1) #(clk_sync_period - clk_sync_period / 2) mult_n = ~mult_n;
end
end
end
end
end
assign clkout = mult_n;
endmodule
| 6.968456 |
module stratixiigx_hssi_aux_clock_phaseshift (
clk, // input clock
clkout // delayed clock
);
input clk;
output clkout;
parameter clk_phase_shift_by = 0;
reg pclk;
always @(clk) pclk <= #(clk_phase_shift_by) clk;
assign clkout = pclk;
endmodule
| 6.968456 |
module stratixiigx_hssi_refclk_divider (
inclk, // input from REFCLK pin
dprioin,
dpriodisable,
clkout, // clock output
dprioout
);
input inclk, dprioin, dpriodisable;
output clkout, dprioout;
wire inclk_ipd;
wire dprioin_ipd;
wire dpriodisable_ipd;
buf buf_inclk (inclk_ipd, inclk);
buf buf_dprioin (dprioin_ipd, dprioin);
buf buf_dpriodisable (dpriodisable_ipd, dpriodisable);
specify
(inclk => clkout) = (0, 0);
endspecify
parameter enable_divider = "true"; // true -> use /2 divider, false -> bypass
parameter divider_number = 0; // 0 or 1 for logical numbering
parameter refclk_coupling_termination = "dc_coupling_external_termination"; // new in 5.1 SP1
parameter dprio_config_mode = 0; // 6.1
wire divide_by_2_out;
stratixiigx_hssi_aux_clock_div divide_by_2 (
.clk (inclk_ipd),
.reset (1'b0),
.enable_d(1'b0), // enable dprio
.d (8'h00), // dprio
.clkout (divide_by_2_out)
);
defparam divide_by_2.clk_divide_by = 2; defparam divide_by_2.extra_latency = 0;
assign clkout = (enable_divider == "true") ? divide_by_2_out : inclk_ipd;
assign dprioout = (dpriodisable_ipd == 1'b1) ? 1'b0 : dprioin_ipd; // temporary, needs to be changed later
endmodule
| 6.968456 |
module stratixiigx_hssi_tx_rx_det_DIV_BY_2 (
CLK,
RESET_N,
CLKOUT
); // synthesis syn_black_box
input CLK, RESET_N;
output CLKOUT;
reg CLKOUT;
wire NEXT_VAL;
// state definition
always @(posedge CLK or negedge RESET_N)
if (!RESET_N) CLKOUT <= 1'b0;
else CLKOUT <= NEXT_VAL;
assign NEXT_VAL = ~CLKOUT;
endmodule
| 6.968456 |
module stratixiigx_hssi_tx_rx_det_CLK_GEN (
CLK,
RESET_N,
CLKOUT
);
input CLK, RESET_N;
output CLKOUT;
wire CLKOUT;
wire CLK8M, CLK4M, CLK2M;
stratixiigx_hssi_tx_rx_det_DIV_BY_2 DIV_1 (
.CLK(CLK),
.RESET_N(RESET_N),
.CLKOUT(CLK8M)
);
stratixiigx_hssi_tx_rx_det_DIV_BY_2 DIV_2 (
.CLK(CLK8M),
.RESET_N(RESET_N),
.CLKOUT(CLK4M)
);
stratixiigx_hssi_tx_rx_det_DIV_BY_2 DIV_3 (
.CLK(CLK4M),
.RESET_N(RESET_N),
.CLKOUT(CLK2M)
);
stratixiigx_hssi_tx_rx_det_DIV_BY_2 DIV_4 (
.CLK(CLK2M),
.RESET_N(RESET_N),
.CLKOUT(CLKOUT)
);
endmodule
| 6.968456 |
module stratixiigx_hssi_tx_rx_det_RCV_DET_SYNC (
CLK,
RESET_N,
RCV_DET,
RCV_DET_OUT
); // synthesis syn_black_box
input CLK, RESET_N, RCV_DET;
output RCV_DET_OUT;
reg RCV_DET_OUT;
reg RCV_DET_MID;
always @(posedge CLK or negedge RESET_N)
if (!RESET_N) begin
RCV_DET_OUT <= 1'b0;
RCV_DET_MID <= 1'b0;
end else begin
RCV_DET_OUT <= RCV_DET_MID;
RCV_DET_MID <= RCV_DET;
end
endmodule
| 6.968456 |
module stratixiigx_hssi_tx_rx_det_RCV_DET_FSM (
CLK,
RESET_N,
COM_PASS,
PROBE_PASS,
DET_ON,
DETECT_VALID,
RCV_FOUND
); // synthesis syn_black_box
input CLK, RESET_N, COM_PASS, PROBE_PASS;
output RCV_FOUND, DET_ON, DETECT_VALID;
reg [2:0] STATE;
reg [2:0] NEXTSTATE;
reg RCV_FOUND, DET_ON, NEXT_RCV_FOUND, DETECT_VALID;
reg FAKE_RCV_PRESENT;
// state definition
parameter RESET = 3'b000;
parameter WAKE = 3'b001;
parameter STATE_1 = 3'b011;
parameter STATE_2 = 3'b101;
parameter HOLD = 3'b100;
initial begin
FAKE_RCV_PRESENT = 1'b1;
end
// State logic and FSM
always @(posedge CLK or negedge RESET_N)
if (!RESET_N) STATE <= RESET;
else STATE <= NEXTSTATE;
always @(STATE or COM_PASS) begin
case (STATE)
RESET: NEXTSTATE = WAKE;
WAKE: begin
if (COM_PASS) NEXTSTATE = STATE_1;
else NEXTSTATE = WAKE;
end
STATE_1: NEXTSTATE = STATE_2;
STATE_2: NEXTSTATE = HOLD;
HOLD: NEXTSTATE = HOLD;
default: NEXTSTATE = RESET;
endcase // case(state)
end // always @ (state or com_pass)
// Output logic
always @(posedge CLK or negedge RESET_N)
if (!RESET_N) RCV_FOUND <= 1'b0;
else RCV_FOUND <= NEXT_RCV_FOUND;
always @(NEXTSTATE or PROBE_PASS or FAKE_RCV_PRESENT) begin
if ((NEXTSTATE == STATE_2) && (!PROBE_PASS) && FAKE_RCV_PRESENT) // probe pass goes up slow -> there is rx
NEXT_RCV_FOUND = 1'b1;
else if ((NEXTSTATE == HOLD) && FAKE_RCV_PRESENT) NEXT_RCV_FOUND = RCV_FOUND;
else // probe pass goes up fast -> no rx
NEXT_RCV_FOUND = 1'b0;
end
// there is no rcv_det_syn
always @(STATE)
if (STATE == RESET) DET_ON = 1'b0;
else DET_ON = 1'b1;
always @(STATE)
if (STATE == HOLD) DETECT_VALID = 1'b1;
else DETECT_VALID = 1'b0;
endmodule
| 6.968456 |
module stratixiigx_hssi_tx_rx_det_RCV_DET_CONTROL (
CLK,
RCV_DET_EN,
RCV_DET_PDB,
COM_PASS,
PROBE_PASS,
DET_ON,
DETECT_VALID,
RCV_FOUND
);
input CLK, RCV_DET_EN, RCV_DET_PDB, COM_PASS, PROBE_PASS;
output DET_ON, DETECT_VALID, RCV_FOUND;
wire RCV_DET_SYN;
stratixiigx_hssi_tx_rx_det_RCV_DET_SYNC XRCV_DET_SYNC (
CLK,
RCV_DET_PDB,
RCV_DET_EN,
RCV_DET_SYN
);
stratixiigx_hssi_tx_rx_det_RCV_DET_FSM XRCV_DET_FSM (
CLK,
RCV_DET_SYN,
COM_PASS,
PROBE_PASS,
DET_ON,
DETECT_VALID,
RCV_FOUND
);
endmodule
| 6.968456 |
module stratixiigx_hssi_tx_rx_det_RCV_DET_DIGITAL (
OSCCLK,
RCV_DET_PDB,
RCV_DET_EN,
COM_PASS,
PROBE_PASS,
DET_ON,
DETECT_VALID,
RCV_FOUND
);
input OSCCLK, RCV_DET_PDB, RCV_DET_EN, COM_PASS, PROBE_PASS;
output DET_ON, RCV_FOUND, DETECT_VALID;
wire CLK;
stratixiigx_hssi_tx_rx_det_CLK_GEN XCLK_GEN (
OSCCLK,
RCV_DET_PDB,
CLK
);
stratixiigx_hssi_tx_rx_det_RCV_DET_CONTROL XRCV_DET_CTRL (
CLK,
RCV_DET_EN,
RCV_DET_PDB,
COM_PASS,
PROBE_PASS,
DET_ON,
DETECT_VALID,
RCV_FOUND
);
endmodule
| 6.968456 |
module is the behavior model for rx_det block
// If there is rx - set parameter RX_EXIST to 1, set to 0 otherwise
`timescale 1ps / 1ps
module stratixiigx_hssi_tx_rx_det (RX_DET_PDB, CLK15M, TX_DET_RX, RX_FOUND, RX_DET_VALID);
input RX_DET_PDB, CLK15M, TX_DET_RX;
output RX_FOUND, RX_DET_VALID;
wire RX_FOUND, RX_DET_VALID;
wire COM_PASS, PROBE_PASS, DET_ON;
parameter RX_EXIST = 1'b1;
assign #100000 COM_PASS = DET_ON;
assign #100000 PROBE_PASS = ~RX_EXIST;
stratixiigx_hssi_tx_rx_det_RCV_DET_DIGITAL XRCV_DET_DIGITAL (.OSCCLK (CLK15M),
.RCV_DET_PDB (RX_DET_PDB),
.RCV_DET_EN (TX_DET_RX),
.COM_PASS (COM_PASS),
.PROBE_PASS (PROBE_PASS),
.DET_ON (DET_ON),
.DETECT_VALID (RX_DET_VALID),
.RCV_FOUND (RX_FOUND));
endmodule
| 7.595207 |
module stratixiigx_hssi_calibration_block (
clk,
powerdn,
enabletestbus,
calibrationstatus
);
input clk;
input powerdn;
input enabletestbus;
output [4:0] calibrationstatus;
parameter use_continuous_calibration_mode = "false";
parameter rx_calibration_write_test_value = 0;
parameter tx_calibration_write_test_value = 0;
parameter enable_rx_calibration_test_write = "false";
parameter enable_tx_calibration_test_write = "false";
parameter send_rx_calibration_status = "true";
endmodule
| 6.968456 |
module stratixiigx_hssi_pcs_reset (
hard_reset,
clk_2_b,
refclk_b_in,
scan_mode,
rxpcs_rst,
txpcs_rst,
rxrst_int,
txrst_int
);
input hard_reset;
input clk_2_b;
input refclk_b_in;
input scan_mode;
input rxpcs_rst;
input txpcs_rst;
output rxrst_int;
output txrst_int;
reg txrst_sync1, txrst_sync2;
reg rxrst_sync1, rxrst_sync2;
wire txrst_int, rxrst_int;
always @(posedge hard_reset or posedge clk_2_b) begin
if (hard_reset) begin
rxrst_sync2 <= 1'b1;
rxrst_sync1 <= 1'b1;
end else begin
rxrst_sync2 <= #1 rxrst_sync1;
rxrst_sync1 <= rxpcs_rst;
end
end
always @(posedge hard_reset or posedge refclk_b_in) begin
if (hard_reset) begin
txrst_sync2 <= 1'b1;
txrst_sync1 <= 1'b1;
end else begin
txrst_sync2 <= #1 txrst_sync1;
txrst_sync1 <= txpcs_rst;
end
end
// 06-14-02 BT Changed SCAN_SHIFT signal to SCAN_MODE
//assign rxrst_int = !SCAN_SHIFT & rxrst_sync2;
//assign txrst_int = !SCAN_SHIFT & txrst_sync2;
assign rxrst_int = !scan_mode & rxrst_sync2;
assign txrst_int = !scan_mode & txrst_sync2;
endmodule
| 6.968456 |
module stratixiigx_hssi_tx_txclk_ctl (
txrst,
pld_tx_clk,
refclk_pma,
txpma_local_clk,
tx_div2_sync_in_ch0,
tx_div2_sync_in_q0_ch0,
rindv_tx,
rtxwrclksel,
rtxrdclksel,
rdwidth_tx,
rfreerun_tx,
rphfifo_master_sel_tx,
scan_mode,
tx_clk_out,
tx_div2_sync_out,
wr_clk_pos,
fifo_rd_clk,
refclk_b
);
input txrst; // reset for the tx_pcs
input pld_tx_clk; // The transmit clock from XGMII.
input refclk_pma; // from the root clock tree
input txpma_local_clk; // Local channel TX PMA clock.
input tx_div2_sync_in_ch0; // from the channel zero tx_div2_sync_out
input tx_div2_sync_in_q0_ch0; // From channel0 of Master Quad
input rindv_tx; // Selects between indiv chan. mode and bundled mode
input rtxwrclksel; // Selects which clock writes into FIFO
input rtxrdclksel; // Selects which clock reads from FIFO and also clocks reest of TX logic
input rdwidth_tx; // divide by 1 or 2 before feeding to FIFO read clock
input rfreerun_tx; // Select whether divider is permamently enabled (free -running) or
// divider should be enabled / reset by TX PCS reset
input rphfifo_master_sel_tx; // TX Phase comp. FIFO tx_div2_sync selection CRAM
input scan_mode; // Scan mode enable signal for selecting scan_clk from refclk_pma
output tx_clk_out; // Drives to the PLD clock tree -- unconnected
output tx_div2_sync_out; // Synchronizes the divided by two clock
output wr_clk_pos; // Drives tx phase comp fifo write side
output fifo_rd_clk; // Drives tx phase comp fifo read side
output refclk_b; // Drives the tx channel clock
wire tx_rst_n, tx_div2_sync;
reg fifo_rd_clk_by2;
wire rd_clk_before_div; //Same as refclk_b. Different name for clarity.
// initial begin ------
initial begin
fifo_rd_clk_by2 = 1'b0;
end
// initial end ------
// Select between the local synchronization signal or the global synchronization signal (either from Channel0 or
// Channel0 of Master Quad
//assign tx_div2_sync = rindv_tx ? tx_div2_sync_out : tx_div2_sync_in;
assign tx_div2_sync = (rphfifo_master_sel_tx == 1'b0) ? tx_div2_sync_in_q0_ch0 :
(rindv_tx == 1'b0) ? tx_div2_sync_in_ch0 : tx_div2_sync_out;
assign tx_div2_sync_out = ~fifo_rd_clk_by2;
// Divide-by-2 FF
always @(negedge tx_rst_n or posedge rd_clk_before_div) begin
if (~tx_rst_n) fifo_rd_clk_by2 <= 1'b0;
else if (rd_clk_before_div) fifo_rd_clk_by2 <= tx_div2_sync; // local divided clock
end
// Reset for Divide-by-2 FF
assign tx_rst_n = (rfreerun_tx) ? 1'b1 : ~txrst;
// Full speed clock for TX PCS
assign refclk_b = rd_clk_before_div; // Internal
// Output clock for PLD
assign tx_clk_out = fifo_rd_clk; // to PLD
// TX FIFO read clock: could be fast or divided by 2
assign fifo_rd_clk = ((rdwidth_tx == 1'b0) || scan_mode) ? rd_clk_before_div : fifo_rd_clk_by2;
assign rd_clk_before_div = (rtxrdclksel || scan_mode) ? refclk_pma : txpma_local_clk; //Same as refclk_b. Different name for clarity.
// TX FIFO write clock: used internal clock when in BIST
assign wr_clk_pos = (rtxwrclksel || scan_mode) ? fifo_rd_clk : pld_tx_clk;
endmodule
| 6.968456 |
module stratixiigx_hssi_mdio_pcs_bus_out_mux (
pcs_ctrl_in1,
pcs_ctrl_in2,
pcs_ctrl_in3,
pcs_ctrl_in4,
pcs_ctrl_in5,
pcs_ctrl_in6,
pcs_ctrl_in7,
pcs_ctrl_in8,
pcs_ctrl_in9,
pcs_ctrl_in10,
pcs_ctrl_in11,
pcs_ctrl_in12,
pcs_ctrl_in13,
pcs_ctrl_in14,
pcs_ctrl_in15,
pcs_ctrl_in16,
hw_address_ctrl_in1,
hw_address_ctrl_in2,
hw_address_ctrl_in3,
hw_address_ctrl_in4,
hw_address_ctrl_in5,
hw_address_ctrl_in6,
hw_address_ctrl_in7,
hw_address_ctrl_in8,
hw_address_ctrl_in9,
hw_address_ctrl_in10,
hw_address_ctrl_in11,
hw_address_ctrl_in12,
hw_address_ctrl_in13,
hw_address_ctrl_in14,
hw_address_ctrl_in15,
hw_address_ctrl_in16,
reg_addr,
pcs_ctrl_out
);
input [15:0] pcs_ctrl_in1;
input [15:0] pcs_ctrl_in2;
input [15:0] pcs_ctrl_in3;
input [15:0] pcs_ctrl_in4;
input [15:0] pcs_ctrl_in5;
input [15:0] pcs_ctrl_in6;
input [15:0] pcs_ctrl_in7;
input [15:0] pcs_ctrl_in8;
input [15:0] pcs_ctrl_in9;
input [15:0] pcs_ctrl_in10;
input [15:0] pcs_ctrl_in11;
input [15:0] pcs_ctrl_in12;
input [15:0] pcs_ctrl_in13;
input [15:0] pcs_ctrl_in14;
input [15:0] pcs_ctrl_in15;
input [15:0] pcs_ctrl_in16;
input [15:0] hw_address_ctrl_in1;
input [15:0] hw_address_ctrl_in2;
input [15:0] hw_address_ctrl_in3;
input [15:0] hw_address_ctrl_in4;
input [15:0] hw_address_ctrl_in5;
input [15:0] hw_address_ctrl_in6;
input [15:0] hw_address_ctrl_in7;
input [15:0] hw_address_ctrl_in8;
input [15:0] hw_address_ctrl_in9;
input [15:0] hw_address_ctrl_in10;
input [15:0] hw_address_ctrl_in11;
input [15:0] hw_address_ctrl_in12;
input [15:0] hw_address_ctrl_in13;
input [15:0] hw_address_ctrl_in14;
input [15:0] hw_address_ctrl_in15;
input [15:0] hw_address_ctrl_in16;
input [15:0] reg_addr;
output [15:0] pcs_ctrl_out;
assign pcs_ctrl_out = (reg_addr == hw_address_ctrl_in1 ) ? pcs_ctrl_in1 :
(reg_addr == hw_address_ctrl_in2 ) ? pcs_ctrl_in2 :
(reg_addr == hw_address_ctrl_in3 ) ? pcs_ctrl_in3 :
(reg_addr == hw_address_ctrl_in4 ) ? pcs_ctrl_in4 :
(reg_addr == hw_address_ctrl_in5 ) ? pcs_ctrl_in5 :
(reg_addr == hw_address_ctrl_in6 ) ? pcs_ctrl_in6 :
(reg_addr == hw_address_ctrl_in7 ) ? pcs_ctrl_in7 :
(reg_addr == hw_address_ctrl_in8 ) ? pcs_ctrl_in8 :
(reg_addr == hw_address_ctrl_in9 ) ? pcs_ctrl_in9 :
(reg_addr == hw_address_ctrl_in10) ? pcs_ctrl_in10 :
(reg_addr == hw_address_ctrl_in11) ? pcs_ctrl_in11 :
(reg_addr == hw_address_ctrl_in12) ? pcs_ctrl_in12 :
(reg_addr == hw_address_ctrl_in13) ? pcs_ctrl_in13 :
(reg_addr == hw_address_ctrl_in14) ? pcs_ctrl_in14 :
(reg_addr == hw_address_ctrl_in15) ? pcs_ctrl_in15 :
(reg_addr == hw_address_ctrl_in16) ? pcs_ctrl_in16 :
16'h0000;
endmodule
| 6.968456 |
module stratixiigx_hssi_bsc_in_r (
reset,
clk,
sig_in,
ext_in,
jtag_mode,
si,
shift,
mdio_dis,
sig_out,
so
) /* synthesis ALTERA_ATTRIBUTE="{-to so} POWER_UP_LEVEL=LOW" */;
input reset; // reset
input clk; // clock
input sig_in; // signal input
input ext_in; // external input port
input jtag_mode;
input si; // scan input
input shift; // 1'b1=shift in data from si into scan flop
// 1'b0=load data from sig_in into scan flop
input mdio_dis; // 1'b1=choose ext_in to the sig_out mux
// 1'b0=choose so to the sign_out mux
output sig_out; // signal output
output so; // scan output
wire sig_out;
wire cram_int;
wire set_int;
reg so;
// select signal output
assign sig_out = (jtag_mode) ? (so & ~shift) : (cram_int);
assign cram_int = (mdio_dis) ? (ext_in) : (so);
// Set signal for the flop
assign set_int = (shift) ? 1'b0 : ext_in;
// scan flop
always @(posedge reset or posedge set_int or posedge clk)
if (reset) so <= 1'b0;
else if (set_int) so <= 1'b1;
else if (shift && jtag_mode) so <= si;
else so <= sig_in;
endmodule
| 6.968456 |
module stratixiigx_hssi_bsc_out (
clk,
jtag_mode,
reset,
shift_load,
si,
sig_in,
sig_out,
so
) /* synthesis synthesis_clearbox=1 */;
input clk;
input jtag_mode;
input reset;
input shift_load;
input si;
input sig_in;
output sig_out;
output so;
reg n1i1;
reg n1i2;
reg ni;
wire wire_nlO_CLRN;
wire wire_nl_dataout;
wire wire_nO_dataout;
wire nlOO;
initial n1i1 = 0;
always @(posedge clk) n1i1 <= n1i2;
event n1i1_event;
initial #1->n1i1_event;
always @(n1i1_event) n1i1 <= {1{1'b1}};
initial n1i2 = 0;
always @(posedge clk) n1i2 <= n1i1;
initial begin
ni = 0;
end
always @(posedge clk or negedge wire_nlO_CLRN) begin
if (wire_nlO_CLRN == 1'b0) begin
ni <= 0;
end else begin
ni <= wire_nl_dataout;
end
end
assign wire_nlO_CLRN = ((n1i2 ^ n1i1) & (~reset));
assign wire_nl_dataout = (shift_load === 1'b1) ? si : sig_in;
assign wire_nO_dataout = (jtag_mode === 1'b1) ? ni : sig_in;
assign nlOO = 1'b1, sig_out = wire_nO_dataout, so = ni;
endmodule
| 6.968456 |
module stratixiii_bmux21 (
MO,
A,
B,
S
);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.269529 |
module stratixiii_b17mux21 (
MO,
A,
B,
S
);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.439168 |
module stratixiii_nmux21 (
MO,
A,
B,
S
);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
| 6.932323 |
module stratixiii_b5mux21 (
MO,
A,
B,
S
);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.647098 |
module stratixiii_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0);
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule
| 7.897097 |
module stratixiii_lvds_tx_reg (
q,
clk,
ena,
d,
clrn,
prn
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// BUFFER INPUTS
wire clk_in;
wire ena_in;
wire d_in;
buf (clk_in, clk);
buf (ena_in, ena);
buf (d_in, d);
// INTERNAL VARIABLES
reg q_tmp;
wire q_wire;
// TIMING PATHS
specify
$setuphold(posedge clk, d, 0, 0);
(posedge clk => (q +: q_tmp)) = (0, 0);
(negedge clrn => (q +: q_tmp)) = (0, 0);
(negedge prn => (q +: q_tmp)) = (0, 0);
endspecify
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q_tmp = 0;
always @(posedge clk_in or negedge clrn or negedge prn) begin
if (prn == 1'b0) q_tmp <= 1;
else if (clrn == 1'b0) q_tmp <= 0;
else if ((clk_in == 1) & (ena_in == 1'b1)) q_tmp <= d_in;
end
assign q_wire = q_tmp;
and (q, q_wire, 1'b1);
endmodule
| 6.593588 |
module stratixiii_lvds_tx_parallel_register (
clk,
enable,
datain,
dataout,
devclrn,
devpor
);
parameter channel_width = 4;
// INPUT PORTS
input [channel_width - 1:0] datain;
input clk;
input enable;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] dataout;
// INTERNAL VARIABLES AND NETS
reg clk_last_value;
reg [channel_width - 1:0] dataout_tmp;
wire clk_ipd;
wire enable_ipd;
wire [channel_width - 1:0] datain_ipd;
buf buf_clk (clk_ipd, clk);
buf buf_enable (enable_ipd, enable);
buf buf_datain[channel_width - 1:0] (datain_ipd, datain);
wire [channel_width - 1:0] dataout_opd;
buf buf_dataout[channel_width - 1:0] (dataout, dataout_opd);
// TIMING PATHS
specify
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
$setuphold(posedge clk, datain, 0, 0);
endspecify
initial begin
clk_last_value = 0;
dataout_tmp = 'b0;
end
always @(clk_ipd or enable_ipd or devpor or devclrn) begin
if ((devpor === 1'b0) || (devclrn === 1'b0)) begin
dataout_tmp <= 'b0;
end else begin
if ((clk_ipd === 1'b1) && (clk_last_value !== clk_ipd)) begin
if (enable_ipd === 1'b1) begin
dataout_tmp <= datain_ipd;
end
end
end
clk_last_value <= clk_ipd;
end // always
assign dataout_opd = dataout_tmp;
endmodule
| 6.593588 |
module stratixiii_lvds_tx_out_block (
clk,
datain,
dataout,
devclrn,
devpor
);
parameter bypass_serializer = "false";
parameter invert_clock = "false";
parameter use_falling_clock_edge = "false";
// INPUT PORTS
input datain;
input clk;
input devclrn;
input devpor;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES AND NETS
reg dataout_tmp;
reg clk_last_value;
wire bypass_mode;
wire invert_mode;
wire falling_clk_out;
// BUFFER INPUTS
wire clk_in;
wire datain_in;
buf (clk_in, clk);
buf (datain_in, datain);
// TEST PARAMETER VALUES
assign falling_clk_out = (use_falling_clock_edge == "true") ? 1'b1 : 1'b0;
assign bypass_mode = (bypass_serializer == "true") ? 1'b1 : 1'b0;
assign invert_mode = (invert_clock == "true") ? 1'b1 : 1'b0;
// TIMING PATHS
specify
if (bypass_mode == 1'b1) (clk => dataout) = (0, 0);
if (bypass_mode == 1'b0 && falling_clk_out == 1'b1)
(negedge clk => (dataout +: dataout_tmp)) = (0, 0);
if (bypass_mode == 1'b0 && falling_clk_out == 1'b0)
(datain => (dataout +: dataout_tmp)) = (0, 0);
endspecify
initial begin
clk_last_value = 0;
dataout_tmp = 0;
end
always @(clk_in or datain_in or devclrn or devpor) begin
if ((devpor === 1'b0) || (devclrn === 1'b0)) begin
dataout_tmp <= 0;
end else begin
if (bypass_serializer == "false") begin
if (use_falling_clock_edge == "false") dataout_tmp <= datain_in;
if ((clk_in === 1'b0) && (clk_last_value !== clk_in)) begin
if (use_falling_clock_edge == "true") dataout_tmp <= datain_in;
end
end // bypass is off
else begin
// generate clk_out
if (invert_clock == "false") dataout_tmp <= clk_in;
else dataout_tmp <= !clk_in;
end // clk output
end
clk_last_value <= clk_in;
end // always
and (dataout, dataout_tmp, 1'b1);
endmodule
| 6.593588 |
module stratixiii_ram_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
parameter delay_pulse = 1'b0;
parameter start_delay = (delay_pulse == 1'b0) ? 1 : 2; // delay write
reg state;
reg clk_prev;
wire clk_ipd;
specify
specparam t_decode = 0, t_access = 0;
(posedge clk => (pulse +: state)) = (t_decode, t_access);
endspecify
buf #(start_delay) (clk_ipd, clk);
wire pulse_opd;
buf buf_pulse (pulse, pulse_opd);
initial clk_prev = 1'bx;
always @(clk_ipd or posedge pulse) begin
if (pulse) state <= 1'b0;
else if (ena && clk_ipd === 1'b1 && clk_prev === 1'b0) state <= 1'b1;
clk_prev = clk_ipd;
end
assign cycle = clk_ipd;
assign pulse_opd = state;
endmodule
| 6.709501 |
module for RAM inputs/outputs
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module stratixiii_ram_register (
d,
clk,
aclr,
devclrn,
devpor,
stall,
ena,
q,
aclrout
);
parameter width = 1; // data width
parameter preset = 1'b0; // clear acts as preset
input [width - 1:0] d; // data
input clk; // clock
input aclr; // asynch clear
input devclrn,devpor; // device wide clear/reset
input stall; // address stall
input ena; // clock enable
output [width - 1:0] q; // register output
output aclrout; // delayed asynch clear
wire ena_ipd;
wire clk_ipd;
wire aclr_ipd;
wire [width - 1:0] d_ipd;
buf buf_ena (ena_ipd,ena);
buf buf_clk (clk_ipd,clk);
buf buf_aclr (aclr_ipd,aclr);
buf buf_d [width - 1:0] (d_ipd,d);
wire stall_ipd;
buf buf_stall (stall_ipd,stall);
wire [width - 1:0] q_opd;
buf buf_q [width - 1:0] (q,q_opd);
reg [width - 1:0] q_reg;
reg viol_notifier;
wire reset;
assign reset = devpor && devclrn && (!aclr_ipd) && (ena_ipd);
specify
$setup (d, posedge clk &&& reset, 0, viol_notifier);
$setup (aclr, posedge clk, 0, viol_notifier);
$setup (ena, posedge clk &&& reset, 0, viol_notifier );
$setup (stall, posedge clk &&& reset, 0, viol_notifier );
$hold (posedge clk &&& reset, d , 0, viol_notifier);
$hold (posedge clk, aclr, 0, viol_notifier);
$hold (posedge clk &&& reset, ena , 0, viol_notifier );
$hold (posedge clk &&& reset, stall, 0, viol_notifier );
(posedge clk => (q +: q_reg)) = (0,0);
(posedge aclr => (q +: q_reg)) = (0,0);
endspecify
initial q_reg <= (preset) ? {width{1'b1}} : 'b0;
always @(posedge clk_ipd or posedge aclr_ipd or negedge devclrn or negedge devpor)
begin
if (aclr_ipd || ~devclrn || ~devpor)
q_reg <= (preset) ? {width{1'b1}} : 'b0;
else if (ena_ipd & !stall_ipd)
q_reg <= d_ipd;
end
assign aclrout = aclr_ipd;
assign q_opd = q_reg;
endmodule
| 7.458522 |
module stratixiii_first_stage_add_sub (
dataa,
datab,
sign,
operation,
dataout
);
//PARAMETERS
parameter dataa_width = 36;
parameter datab_width = 36;
parameter fsa_mode = "add";
// INPUT PORTS
input [71 : 0] dataa;
input [71 : 0] datab;
input sign;
input [3:0] operation;
// OUTPUT PORTS
output [71:0] dataout;
//INTERNAL SIGNALS
reg [71 : 0] dataout_tmp;
reg [71:0] abs_b;
reg [71:0] abs_a;
reg sign_a;
reg sign_b;
specify
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
(sign *> dataout) = (0, 0);
endspecify
//assign the output values
assign dataout = dataout_tmp;
always @(dataa or datab or sign or operation) begin
if((operation == 4'b0111) ||(operation == 4'b1000)|| (operation == 4'b1001)) //36 bit multiply, shift and add
begin
dataout_tmp = {dataa[53:36], dataa[35:0], 18'b0} + datab;
end else begin
sign_a = (sign && dataa[dataa_width-1]);
abs_a = (sign_a) ? (~dataa + 1'b1) : dataa;
sign_b = (sign && datab[datab_width-1]);
abs_b = (sign_b) ? (~datab + 1'b1) : datab;
if (fsa_mode == "add") dataout_tmp = (sign_a ? -abs_a : abs_a) + (sign_b ? -abs_b : abs_b);
else dataout_tmp = (sign_a ? -abs_a : abs_a) - (sign_b ? -abs_b : abs_b);
end
end
endmodule
| 8.305598 |
module stratixiii_round_block (
datain,
round,
datain_width,
dataout
);
parameter round_mode = "nearest_integer";
parameter operation_mode = "output_only";
parameter round_width = 15;
input [71 : 0] datain;
input round;
input [7:0] datain_width;
output [71 : 0] dataout;
reg sign;
reg [71 : 0] result_tmp;
reg [71:0] dataout_tmp;
reg [71 : 0] dataout_value;
integer i, j;
initial begin
result_tmp = {(72) {1'b0}};
end
assign dataout = dataout_value;
always @(datain or round) begin
if (round == 1'b0) dataout_value = datain;
else begin
j = 0;
sign = 0;
dataout_value = datain;
if (datain_width > round_width) begin
for (i = datain_width - round_width; i < datain_width; i = i + 1) begin
result_tmp[j] = datain[i];
j = j + 1;
end
for (i = 0; i < datain_width - round_width - 1; i = i + 1) begin
sign = sign | datain[i];
dataout_value[i] = 1'bX;
end
dataout_value[datain_width-round_width-1] = 1'bX;
//rounding logic
if(datain[datain_width - round_width -1 ] == 1'b0)// fractional < 0.5
begin
dataout_tmp = result_tmp;
end
else if((datain[datain_width - round_width -1 ] == 1'b1) && (sign == 1'b1))//fractional > 0.5
begin
dataout_tmp = result_tmp + 1'b1;
end else begin
if(round_mode == "nearest_even")//unbiased rounding
begin
if (result_tmp % 2) //check for odd integer
dataout_tmp = result_tmp + 1'b1;
else dataout_tmp = result_tmp;
end else //biased rounding
begin
dataout_tmp = result_tmp + 1'b1;
end
end
j = 0;
for (i = datain_width - round_width; i < datain_width; i = i + 1) begin
dataout_value[i] = dataout_tmp[j];
j = j + 1;
end
end
end
end
endmodule
| 7.897097 |
module stratixiii_round_saturate_block (
datain,
round,
saturate,
signa,
signb,
datain_width,
dataout,
saturationoverflow
);
parameter dataa_width = 36;
parameter datab_width = 36;
parameter saturate_width = 15;
parameter round_width = 15;
parameter saturate_mode = " asymmetric";
parameter round_mode = "nearest_integer";
parameter operation_mode = "output_only";
input [71:0] datain;
input round;
input saturate;
input signa;
input signb;
input [7:0] datain_width;
output [71:0] dataout;
output saturationoverflow;
wire [71:0] dataout_round;
wire [ 7:0] datain_width;
wire [ 7:0] fraction_width;
wire [ 7:0] datasize;
specify
(datain *> dataout) = (0, 0);
(round *> dataout) = (0, 0);
(saturate *> dataout) = (0, 0);
(signa *> dataout) = (0, 0);
(signb *> dataout) = (0, 0);
(datain *> saturationoverflow) = (0, 0);
(round *> saturationoverflow) = (0, 0);
(saturate *> saturationoverflow) = (0, 0);
(signa *> saturationoverflow) = (0, 0);
(signb *> saturationoverflow) = (0, 0);
endspecify
stratixiii_round_block round_unit (
.datain(datain),
.round(round),
.datain_width(datain_width),
.dataout(dataout_round)
);
defparam round_unit.round_mode = round_mode; defparam round_unit.operation_mode = operation_mode;
defparam round_unit.round_width = round_width;
stratixiii_saturate_block saturate_unit (
.datain(dataout_round),
.saturate(saturate),
.round(round),
.signa(signa),
.signb(signb),
.datain_width(datain_width),
.dataout(dataout),
.saturation_overflow(saturationoverflow)
);
defparam saturate_unit.dataa_width = dataa_width;
defparam saturate_unit.datab_width = datab_width;
defparam saturate_unit.round_width = round_width;
defparam saturate_unit.saturate_width = saturate_width;
defparam saturate_unit.saturate_mode = saturate_mode;
defparam saturate_unit.operation_mode = operation_mode;
endmodule
| 7.897097 |
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