code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module test_lattice_sim;
wire [27:0] SUM;
reg ADDNSUB, SignA, SignB, CLK0, CE0, RST0;
reg [9:0] A0;
reg [16:0] B0;
reg [9:0] A1;
reg [16:0] B1;
wire VCCI_sig = 1;
GSR GSR_INST (.GSR(VCCI_sig));
PUR PUR_INST (.PUR(VCCI_sig));
integer index;
integer maddsub_10x17_dynamic_vlog_gen_out;
parame... | 6.812784 |
module: ThreeInputExorGate
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module stimulus2;
// Inputs
reg i1;
reg i2;
reg i3;
// Outputs
wire Output;
integer i;
integer j;
// I... | 7.231613 |
module stimulus_trisc ();
parameter ncs = 3;
parameter cw = (1 << ncs) - 1; //number of conditional inputs (cw+1 must be a power of 2)
parameter ow = 28; //control output size
reg [cw-1:0] cond;
wire [ow-1:0] out_sig;
reg clk;
reg reset_n;
trisc processor (
cond,
out_sig,
clk,
... | 7.379504 |
module stim_code;
// Parameters
parameter MODE = 1; // 0->query; 1->ref
parameter bitwidth = 16;
parameter SQG_SIZE = 250;
parameter REF_SIZE = 29898;
// Module IO
reg clk = 0;
reg rst;
reg running;
reg [31:0] ref_len = REF_SIZE;
reg op_mode;
wire busy;
wire load_done;
wire src_fifo_rden... | 6.712298 |
module aastim_final;
reg [2:0] req_floor1, req_floor2;
reg clk;
reg [10:0] weight;
reg [7:0] temperature_input;
wire [1:0] fan_speed;
wire [11:0] fan_rpm;
wire [2:0] powerlevel_1, powerlevel_2;
wire [7:0] turnover1, turnover2;
wire [1:0] direction1, direction2;
wire complete1, complete2;
wire ov... | 6.946558 |
module stitcher (
input clk,
input rst_n,
input left_data_valid,
input [ 7:0] left_data,
input right_data_valid,
input [ 7:0] right_data,
input keypoint_valid,
input [31:0] left_keypoint,
input [31:0] right_keypoint,
output data_... | 6.850973 |
module STI_DAC (
clk,
reset,
load,
pi_data,
pi_length,
pi_fill,
pi_msb,
pi_low,
pi_end,
so_data,
so_valid,
oem_finish,
oem_dataout,
oem_addr,
odd1_wr,
odd2_wr,
odd3_wr,
odd4_wr,
even1_wr,
even2_wr,
even3_wr,
even4_wr
);
input [15:... | 6.965528 |
module STI_DAC (
clk,
reset,
load,
pi_data,
pi_length,
pi_fill,
pi_msb,
pi_low,
pi_end,
so_data,
so_valid,
oem_finish,
oem_dataout,
oem_addr,
odd1_wr,
odd2_wr,
odd3_wr,
odd4_wr,
even1_wr,
even2_wr,
even3_wr,
even4_wr
);
input clk... | 6.965528 |
module PROC (
clk,
reset,
cur_state,
load,
pi_data,
pi_length,
pi_fill,
pi_msb,
pi_low,
read_done,
out_done,
so_data
);
input clk, reset;
input [2:0] cur_state;
input load;
input [15:0] pi_data;
input [1:0] pi_length;
input pi_fill, pi_msb, pi_low;
reg [15:... | 6.599199 |
module STK_Decoder (
SC,
HEX4,
HEX5,
HEX6,
HEX5DP
);
input [2:0] SC;
output reg [6:0] HEX4, HEX5, HEX6;
output reg HEX5DP;
always @(SC[2:0]) begin
HEX4 = 7'b1101101;
HEX5 = 7'b1111000;
HEX5DP = 1'b1;
case (SC[2:0])
3'b000: begin //Empty
HEX6 = 7'b1111... | 6.638044 |
module Stl (
input [31:0] A,
input [31:0] B,
output [31:0] result
);
wire cin, zero;
wire [31:0] add_result;
assign cin = 1;
Adder(
.input1(A), .input2(B), .cin(cin), .result(add_result)
);
assign zero = &add_result;
assign result = zero ? 32'h0000_0000 : 32'h0000_0001;
endmodule
| 7.224633 |
module SYMM_TEST (
input clk_test,
input en_test,
input signed [25:0] i11,
i12,
i13,
i14,
input signed [25:0] i21,
i22,
i23,
i24,
input signed [25:0] i31,
i32,
i33,
i34,
input signed [25:0] i41,
i42,
i43,
i44,
input signed [25:0] i11_2,
i... | 6.830955 |
module stm_axi_test (
input clk_240Mhz,
output reg m_axis_tvalid,
input m_axis_tready,
output reg [63:0] m_axis_tdata,
output m_axis_tlast,
output m_axis_tstrb,
output [3:0] m_axis_tkeep
);
// always @(posedge clk_240Mhz)
//begin
// case (dwnl_state)
// // WAIT... | 8.257282 |
module stock_code_512x70 (
input [ 8:0] addr_a,
input [69:0] din_a,
output reg [69:0] dout_a,
input clk_a,
input we_a
/* input [8:0] addr_b,
input [48:0] din_b,
output reg [48:0] dout_b,
input clk_b,
input we_b
*/
);
... | 6.736274 |
module stock_price_512x49 (
input [ 8:0] addr_a,
input [48:0] din_a,
output reg [48:0] dout_a,
input clk_a,
input we_a
/* input [8:0] addr_b,
input [48:0] din_b,
output reg [48:0] dout_b,
input clk_b,
input we_b
*/
);
... | 6.992376 |
module stopping (
input clock,
input [3:0] present_INs,
output stoppedAndWaitingForDetection //boolean
);
reg waitingForAudioSignal_reg;
wire [27:0] countedUpTo_wire;
reg [3:0] isStopped;
parameter COUNT_PERIOD_HALF_SEC = 28'd200000000;
parameter P_25_MILLI_SEC = COUNT_PERIOD_HALF_SEC >> 1;
p... | 7.279662 |
module stopstart (
input b0down,
output reg [1:0] state,
input userclock,
input switch,
input switch2
);
reg [1:0] next_state;
initial begin //we set the initial state to be zero
state = 0; //this way, we start with a "paused" stopwatch
next_state = 0;
end
always @(posedge usercl... | 6.949633 |
module StopwatchImpl (
input Clk,
input [3:0] Btn,
input [6:0] Switch,
output wire [3:0] LED,
output wire [0:6] IO_LED1,
output wire [0:6] IO_LED2,
output wire [0:6] IO_LED3,
output wire [0:6] IO_LED4
);
wire [3:0] BtnDebounced;
wire BtnExtDebounced;
wire [6:0] SwitchSync;
Genv... | 6.633212 |
module stopwatch_fsm (
input clkIn,
input rstIn,
input btnRunIn,
input btnPauseIn,
input btnClearIn,
output reg enCounterOut,
output reg clrCounterOut
);
parameter IDLE = 4'b0001;
parameter RUN = 4'b0010;
parameter PAUSE = 4'b0100;
parameter CLEAR = 4'b1000;
reg [3:0] state;
a... | 6.675491 |
module stopwatch_l5 (
input [1:0] KEY,
input CLOCK_50,
output reg [6:0] HEX0,
output reg [6:0] HEX1,
output reg [6:0] HEX2,
output reg [6:0] HEX3,
output reg [9:0] LEDR,
output reg [7:0] LEDG
);
reg [18:0] impulses_cout;
reg [ 3:0] one_first_sec; // 1
reg [ 3:0]... | 7.836739 |
module show_time (
time_display,
hex5,
hex4,
hex3,
hex2,
hex1,
hex0
);
input [18:0] time_display;
output [6:0] hex5, hex4, hex3, hex2, hex1, hex0;
// Minutes.
sevenseg_decimal(
time_display / 60000, hex5
); sevenseg_decimal(
time_display / 6000 % 10, hex4
);
// Se... | 7.555103 |
module show_counting_status (
time_counter,
counting,
led
);
input [18:0] time_counter;
input counting;
output [9:0] led;
// When stopped, all LEDs off.
// When counting, LED light spot moves to the right every second.
// When paused, LED light spot stays at the original position.
assign led ... | 6.546423 |
module.
// Key usage:
// key3: Reset all states (will stop current counting).
// key2: Start / Pause / Resume counting.
// key1: Pause display updating (but counting is still in process), display current time value and freeze.
// key0: Resume display updating.
// When stopped or paused, key1 and key... | 7.309053 |
module clocks (
rst,
master_clock,
clock1hz,
clock2hz,
clock_adjust,
clock_fast
);
input wire rst;
input wire master_clock;
output reg clock1hz;
output reg clock2hz;
output reg clock_adjust;
output reg clock_fast;
reg [27:0] counter1hz;
reg [27:0] counter2hz;
reg [27:0] coun... | 7.033034 |
module stopwatch_timer (
output [7:0] ssd,
output [3:0] ssd_ctl,
output [15:0] LED,
input start_hr,
input pause_min,
input mode_setting,
input rst_n_init,
input clk
);
wire clk1hz, clk_100hz;
wire [1:0] clk_ctl;
wire start, hr, start_hr_debounce, start_hr_one_pulse;
wire pause, ... | 6.703099 |
module stop_check (
input wire sampled_bit,
input wire stop_check_en,
output reg stop_err
);
always @(*) begin
if (stop_check_en)
if (sampled_bit) stop_err = 1'b0;
else stop_err = 1'b1;
else stop_err = 1'b0;
end
endmodule
| 6.88184 |
module stop_pipe (
input clock,
n_stop_request,
output reg stop
);
reg [3:0] count;
//assign stop1 = ~(~n_stop_request && (count == 4'b0));
always @(posedge clock or negedge n_stop_request) begin
if (!n_stop_request) begin
count <= 4'b1000;
stop <= 1'b0;
end else if (count > 4'b0... | 7.107729 |
module stop_pipelined_unit (
input rst_n,
input load_use_hazard,
output reg stop
);
always @(*) begin
if (rst_n == 'b0) begin
stop = 'b0;
end else if (load_use_hazard == 'b1) begin
stop = 'b1;
end else begin
stop = 'b0;
end
end
endmodule
| 7.673042 |
module stop_watch_cascade (
input wire clk,
input wire go,
clr,
output wire [3:0] d2,
d1,
d0
);
// declaration
localparam DVSR = 10000000; // 100MHz, count to 10M to 0.1s tick
reg [23:0] ms_reg;
wire [23:0] ms_next;
reg [3:0] d2_reg, d1_reg, d0_reg;
wire [3:0] d2_nex... | 6.788192 |
module stop_watch_test (
input wire clk,
input wire btnR,
btnL,
output wire [3:0] an,
output wire [7:0] seg
);
// signal declaration
wire [3:0] d2, d1, d0;
// instantiate 7-seg LED display module
disp_hex_mux disp_unit (
.clk(clk),
.reset(1'b0),
.hex3(4'b0),... | 7.867655 |
module StorageDrive #(
parameter DW = 32,
parameter ADDR_WIDTH = 15,
parameter inputFile = "Program.txt"
) (
input [(ADDR_WIDTH-1):0] data_address,
input [(DW-1):0] input_data,
input write_enable,
read_clock,
write_clock,
output reg [(DW-1):0] output_data
);
// Storage declaration... | 7.850885 |
module storage_bridge_wb (
// MGMT_AREA R/W WB Interface
input wb_clk_i,
input wb_rst_i,
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input wb_cyc_i,
input [1:0] wb_stb_i,
output reg [1:0] wb_ack_o,
output reg [31:0] wb_rw_dat_o,
//... | 6.976351 |
module storage_wrapper (
input clk, //shared wire
input rst, //shared wire
input [7:0] i_tdata,
input i_tlast,
input wren,
input [12:0] wr_ptr,
output [2:0] rd_ptr_tribit,
input greenflag,
output [7:0] o_tdata,
input o_tready,
output o_tvalid,
output o_tlast
);
//Dri... | 6.79034 |
module StoreAux (
input wire [ 1:0] selector,
input wire [31:0] data_0,
data_1,
output wire [31:0] data_out
);
assign data_out = (selector == 2'b00) ? data_0 :
(selector == 2'b01) ? {data_1[31:16], data_0[15:0]} :
(selector == 2'b10) ? {data_1[31:8], data... | 7.281248 |
module FIFO (
clk,
rst,
we_i,
re_i,
waddr_i,
wdata_i,
raddr_o,
rdata_o,
fifo_full_o,
fifo_empty_o,
read_ptr
);
input clk, rst, re_i, we_i;
input [31:0] waddr_i;
input [31:0] wdata_i;
input [5:0] read_ptr;
output reg [31:0] raddr_o;
output reg [31:0] rdata_o;
... | 6.626407 |
module storegen_testbench;
`include "../clk_gen_template.vh"
`include "armleocpu_defines.vh"
initial begin
#100 $finish;
end
reg [1:0] inwordOffset;
reg [1:0] storegenType;
reg [31:0] storegenDataIn;
wire [31:0] storegenDataOut;
wire [3:0] storegenDataMask;
wire storegenMissAligned;
wire... | 6.95758 |
module Storeimm (
Signimm,
CLK,
Outimm,
reset
);
input [31:0] Signimm;
input CLK, reset;
output reg [31:0] Outimm;
always @(posedge CLK or negedge reset) begin
if (!reset) begin
Outimm = 32'b0;
end else begin
Outimm = Signimm;
end
end
endmodule
| 6.970693 |
module StoreLogic (
input [31:0] Data,
input [ 1:0] ALUOutput,
input [ 1:0] DataType,
output reg [31:0] FixedData,
output reg [ 3:0] MemoryByteSel
);
reg [31:0] Byte0;
reg [31:0] Byte1;
reg [31:0] Byte2;
reg [31:0] Byte3;
reg [31:0] Half0;
reg [31:0] Half1;
reg [31:0] B... | 6.674195 |
module StoreMask (
input memwrite,
input [1:0] addr,
input [2:0] funct3,
output [3:0] mask
);
wire [3:0] mask_Byte;
wire [3:0] mask_Half = addr[1] ? 4'b1100 : 4'b0011;
decoder d2_4 (
.data_in (addr),
.data_out(mask_Byte)
);
assign mask = memwrite ? ((funct3 == 3'b000) ? mask_Byte... | 6.91903 |
module StoreReservationStation_tb;
`include "Utility.v"
wire [OPCODE_LENGTH - 1:0] op;
wire [31:0] vj, vk;
wire [31:0] res;
wire [31:0] vi;
wire [REORDER_BUFFER_SIZE_LOG - 1:0] pos;
wire [FUNCTION_UNIT_NUMBER_LOG - 1:0] qi, qj, qk;
wire [FUNCTION_UNIT_NUMBER * 32 - 1:0] commonDataBus;
reg clk, reset;
... | 6.686507 |
module storeRS (
input wire clock,
input wire [5:0] operatorType,
input wire [31:0] data1,
input wire [5:0] q1,
input wire [31:0] data2,
input wire [5:0] q2,
input reset,
input wire [31:0] offset_in,
input wire [5:0] destRobNum,
output reg [5:0] robNum_out,
output reg availa... | 6.612874 |
module storeunit (
input clk,
output [31:0] data_out,
output [7:0] storesig,
input [31:0] reg0,
input [31:0] reg1,
input [31:0] reg2,
input [31:0] reg3,
input [39:0] instbus1,
input [39:0] instbus2,
input [39:0] addbus,
input [39:0] multbus,
input [39:0] loadbus
);
reg... | 6.559264 |
module storeypeak_clock_gen (
input wire i_clk,
output wire o_clk,
output wire o_rst
);
wire clk_fb;
wire locked;
reg [9:0] r;
assign o_rst = r[9];
always @(posedge o_clk)
if (locked) r <= {r[8:0], 1'b0};
else r <= 10'b1111111111;
altera_pll #(
.fractional_vco... | 7.387098 |
module instantiates two Store_Hex modules
//These modules share the same hex_in,reset, and enter
//They have seperate outputs, Four_hex1 and Four_hex2
//They have opposite enables meaning we will only store to one module at a time
module Store_2_Hex(
input [3:0] hex_in,
input enable,reset,enter,
output [15:... | 7.670485 |
module store_b_w_e_gen (
input [1 : 0] addr,
input [2 : 0] store_sel,
output reg [3 : 0] b_w_en
);
wire [1 : 0] byte_sel;
assign byte_sel = addr ^ {2{`BigEndianCPU}};
always @(*) begin
case (store_sel)
// SB
3'b000: begin
case (byte_sel)
0: b_w_en = 4'b0001;
... | 7.854506 |
module store_data_port_m_axi_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire sclk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:... | 8.12371 |
module store_data_port_m_axi_fifo #(
parameter DATA_BITS = 8,
DEPTH = 16,
DEPTH_BITS = 4
) (
input wire sclk,
input wire reset,
input wire sclk_en,
output reg empty_n,
output reg ... | 8.12371 |
module store_data_port_m_axi_buffer #(
parameter MEM_STYLE = "block",
DATA_WIDTH = 32,
ADDR_WIDTH = 5,
DEPTH = 32
) (
// system signal
input wire clk,
input wire reset,
input wire sclk_en,
// write
output wire if_full_n,
i... | 8.12371 |
module store_data_port_m_axi_decoder #(
parameter DIN_WIDTH = 3
) (
input wire [ DIN_WIDTH-1:0] din,
output reg [2**DIN_WIDTH-1:0] dout
);
integer i;
always @(din) begin
dout = {2 ** DIN_WIDTH{1'b0}};
for (i = 0; i < din; i = i + 1) dout[i] = 1'b1;
end
endmodule
| 8.12371 |
module store_data_translator (
write_data, // data in least significant position
d_address,
store_size,
d_byteena,
d_writedataout // shifted data to coincide with address
);
//parameter WIDTH=32;
input [31:0] write_data;
input [1:0] d_address;
input [1:0] store_size;
output [3:0] d_byt... | 8.280191 |
module store_filter (
input wire [31:0] busB,
input wire sb,
input wire sh,
output reg [31:0] mem_write_data
);
wire [31:0] det_sb_out;
wire [31:0] mem_write_data_out;
mux_32 det_sb (
.sel(sb),
.src0(busB),
.src1({24'b0, busB[7:0]}),
.z(det_sb_out)
);
mux_32 det_sh (
... | 7.093907 |
module then concatenates the 4 numbers into the output password
module Store_Hex(
//Input hex_in takes in a 4 bit binary number representing the position of the switches
input [3:0] hex_in,
//Input reset resets the hex input process by resetting the counter
input reset,
//Input enter stores the curr... | 6.582001 |
module StoreMask (
input wire [31:0] B,
input wire [31:0] MR,
input wire [ 1:0] CT,
output reg [31:0] OUT
);
always @(*) begin
case (CT)
2'b00: OUT = B;
2'b01: begin
OUT[31:16] = MR[31:16];
OUT[15:0] = B[15:0];
end
2'b10: begin
OUT[31:8] = MR... | 6.91903 |
module store_shifter (
input [1 : 0] addr,
input [2 : 0] store_sel,
input [31 : 0] rt_data,
output reg [31 : 0] real_rt_data
);
wire [1 : 0] byte_sel;
assign byte_sel = addr ^ {2{`BigEndianCPU}};
always @(*) begin
case (store_sel)
// SB
3'b000: begin
case (byte_sel)
... | 8.503495 |
module PIPELINE (
a,
b,
c,
d,
clk,
z
);
parameter W1 = 5, W2 = 2 * W1;
input [W1-1:0] a, b, c, d;
input clk;
output [W2-1:0] z;
reg [W2-1:0] z, z1;
always @(posedge clk) begin
z1 <= a * b + c - d; // Pipeline register #1
z <= z1; // Pipeline register #2
end
endmodule... | 7.740205 |
module DONT_PIPELINE (
a,
b,
c,
clk,
sel,
z
);
parameter W1 = 10, W2 = W1, Wsel = 2;
input [W1-1:0] a, b, c;
input clk;
input [Wsel-1:0] sel;
output [W2-1:0] z;
reg [W2-1:0] z, G1, G2, SUM;
GLUE I_GLUE (
.a(a),
.b(b),
.y(G1),
.z(G2)
);
ARITH I_ARITH (... | 6.857666 |
module ARITH (
a,
b,
sum
);
parameter W1 = 10, W2 = W1;
input [W1-1:0] a, b;
output [W2-1:0] sum;
reg [W2-1:0] sum;
always @(a, b) begin
sum = a + b;
end
endmodule
| 7.169472 |
module sto_reg (
clk,
rst,
load,
i,
o
);
// parameters
parameter WIDTH = 32;
// common ports
input clk;
input rst;
// control ports
input load;
// input ports
input signed [WIDTH-1:0] i;
// output ports
output signed [WIDTH-1:0] o;
// wires
wire signed [WIDTH-1:0] o_m... | 7.964978 |
module StP #(
parameter n = 8,
m = 32
) (
input clk,
rst,
enable, //enable = 1 means loading time, enable =0 means loading is finished
input ser_in,
input grant, // send by bus and means 8-bit is written to the i_mem
output reg d_valid,
shift_done, //start = 1 means loading instru... | 7.653297 |
module stp02 (
input wire [9:0] acq_data_in, // tap.acq_data_in
input wire [2:0] acq_trigger_in, // .acq_trigger_in
input wire acq_clk // acq_clk.clk
);
sld_signaltap #(
.SLD_DATA_BITS (10),
.SLD_SAMPLE_DEPTH (1024),
.SLD_RAM_BLOCK_T... | 7.005585 |
module stp02 (
input wire [9:0] acq_data_in, // tap.acq_data_in
input wire [2:0] acq_trigger_in, // .acq_trigger_in
input wire acq_clk // acq_clk.clk
);
endmodule
| 7.005585 |
module stpu_sopc_tb ();
reg CLOCK_50;
reg rst;
initial begin
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
initial begin
rst = `RstEnable;
#195 rst = `RstDisable;
#4100 $stop;
end
stpu_sopc stpu_sopc0 (
.clk(CLOCK_50),
.rst(rst)
);
endmodule
| 6.645179 |
module stp (
input wire [79:0] acq_data_in, // tap.acq_data_in
input wire [ 2:0] acq_trigger_in, // .acq_trigger_in
input wire acq_clk // acq_clk.clk
);
endmodule
| 7.32169 |
module stp_chk (
input wire CLK,
input wire RST,
input wire sampled_bit,
input wire Enable,
output reg stp_err
);
// error check
always @(posedge CLK or negedge RST) begin
if (!RST) begin
stp_err <= 'b0;
end else if (Enable) begin
stp_err <= 1'b1 ^ sampled_bit;
en... | 8.119117 |
module stq_buf_A (
clk,
rst,
stallA,
excpt,
wrt0_en,
wrt0_addrE,
wrt0_addrO,
wrt1_en,
wrt1_addrE,
wrt1_addrO,
chk0_en,
chk0_addrEO,
chk0_addrE,
chk0_addrO,
chk1_en,
chk1_addrEO,
chk1_addrE,
chk1_addrO,
chk2_en,
chk2_addrEO,
chk2_addrE,
... | 6.60366 |
module stq_adata (
clk,
rst,
wrt0_en,
wrt0_WQ,
wrt0_adata,
wrt1_en,
wrt1_WQ,
wrt1_adata,
upd0_WQ,
upd0_adata,
upd1_WQ,
upd1_adata
);
input clk;
input rst;
input wrt0_en;
input [5:0] wrt0_WQ;
input [4:0] wrt0_adata;
input wrt1_en;
input [5:0] wrt1_WQ;
input... | 6.883144 |
module stq_data (
clk,
rst,
wrt0_en,
wrt0_data,
wrt1_en,
wrt1_data,
chk0_en,
chk0_data,
chk1_en,
chk1_data,
chk2_en,
chk2_data,
chk3_en,
chk3_data,
chk4_en,
chk4_data,
chk5_en,
chk5_data,
chk6_en,
chk6_data,
chk7_en,
chk7_data
);
... | 7.312396 |
module stq_adata_ram (
clk,
rst,
readA_clkEn,
readA_addr,
readA_data,
writeA_wen,
writeA_addr,
writeA_data,
writeB_wen,
writeB_addr,
writeB_data
);
localparam WIDTH = `lsaddr_width + 1; //adata+en
input clk;
input rst;
input read_clkEn;
input [5:0] read_addr;
ou... | 7.679879 |
module performs the straight D-Box logic
module Straight_D_Box(
input [31:0] i_data,
output [31:0] o_straightened_data
);
// 1st byte
assign o_straightened_data[0] = i_data[15];
assign o_straightened_data[1] = i_data[6];
assign o_straightened_data[2] = i_data[19];
assign o_straightened_data[3] = i_data[20];
... | 7.634754 |
module picdisplay (
output reg [23:0] vga_data,
input [9:0] h_addr,
input [9:0] v_addr,
input clk,
input en
);
//inner signal
reg [18:0] addr;
wire [11:0] data;
pic mypic (
addr,
clk,
data
);
//initial
initial begin
vga_data = 24'd0;
end
//always module
... | 6.505922 |
module stratixiigx_hssi_aux_clock_div (
clk, // input clock
reset, // reset
enable_d, // enable DPRIO
d, // division factor for DPRIO support
clkout // divided clock
);
input clk, reset;
input enable_d;
input [7:0] d;
output clkout;
parameter clk_divide_by = 1;
parameter extra_lat... | 6.968456 |
module stratixiigx_hssi_aux_clock_mult (
clk, // input clock
adjust, // adjust frequency
adjust_without_lol,
reset, // reset
enable_m, // enable DPRIO
m, // multiplication factor for DPRIO support
clkout, // multiplied clock
busy // state
);
input clk, adjust, reset;
input adj... | 6.968456 |
module stratixiigx_hssi_aux_clock_phaseshift (
clk, // input clock
clkout // delayed clock
);
input clk;
output clkout;
parameter clk_phase_shift_by = 0;
reg pclk;
always @(clk) pclk <= #(clk_phase_shift_by) clk;
assign clkout = pclk;
endmodule
| 6.968456 |
module stratixiigx_hssi_refclk_divider (
inclk, // input from REFCLK pin
dprioin,
dpriodisable,
clkout, // clock output
dprioout
);
input inclk, dprioin, dpriodisable;
output clkout, dprioout;
wire inclk_ipd;
wire dprioin_ipd;
wire dpriodisable_ipd;
buf buf_inclk (inclk_ipd, inclk);
... | 6.968456 |
module stratixiigx_hssi_tx_rx_det_DIV_BY_2 (
CLK,
RESET_N,
CLKOUT
); // synthesis syn_black_box
input CLK, RESET_N;
output CLKOUT;
reg CLKOUT;
wire NEXT_VAL;
// state definition
always @(posedge CLK or negedge RESET_N)
if (!RESET_N) CLKOUT <= 1'b0;
else CLKOUT <= NEXT_VAL;
assign ... | 6.968456 |
module stratixiigx_hssi_tx_rx_det_CLK_GEN (
CLK,
RESET_N,
CLKOUT
);
input CLK, RESET_N;
output CLKOUT;
wire CLKOUT;
wire CLK8M, CLK4M, CLK2M;
stratixiigx_hssi_tx_rx_det_DIV_BY_2 DIV_1 (
.CLK(CLK),
.RESET_N(RESET_N),
.CLKOUT(CLK8M)
);
stratixiigx_hssi_tx_rx_det_DIV_BY_2 DIV... | 6.968456 |
module stratixiigx_hssi_tx_rx_det_RCV_DET_SYNC (
CLK,
RESET_N,
RCV_DET,
RCV_DET_OUT
); // synthesis syn_black_box
input CLK, RESET_N, RCV_DET;
output RCV_DET_OUT;
reg RCV_DET_OUT;
reg RCV_DET_MID;
always @(posedge CLK or negedge RESET_N)
if (!RESET_N) begin
RCV_DET_OUT <= 1'b0;
... | 6.968456 |
module stratixiigx_hssi_tx_rx_det_RCV_DET_FSM (
CLK,
RESET_N,
COM_PASS,
PROBE_PASS,
DET_ON,
DETECT_VALID,
RCV_FOUND
); // synthesis syn_black_box
input CLK, RESET_N, COM_PASS, PROBE_PASS;
output RCV_FOUND, DET_ON, DETECT_VALID;
reg [2:0] STATE;
reg [2:0] NEXTSTATE;
reg RCV_FOUND... | 6.968456 |
module stratixiigx_hssi_tx_rx_det_RCV_DET_CONTROL (
CLK,
RCV_DET_EN,
RCV_DET_PDB,
COM_PASS,
PROBE_PASS,
DET_ON,
DETECT_VALID,
RCV_FOUND
);
input CLK, RCV_DET_EN, RCV_DET_PDB, COM_PASS, PROBE_PASS;
output DET_ON, DETECT_VALID, RCV_FOUND;
wire RCV_DET_SYN;
stratixiigx_hssi_tx_rx_d... | 6.968456 |
module stratixiigx_hssi_tx_rx_det_RCV_DET_DIGITAL (
OSCCLK,
RCV_DET_PDB,
RCV_DET_EN,
COM_PASS,
PROBE_PASS,
DET_ON,
DETECT_VALID,
RCV_FOUND
);
input OSCCLK, RCV_DET_PDB, RCV_DET_EN, COM_PASS, PROBE_PASS;
output DET_ON, RCV_FOUND, DETECT_VALID;
wire CLK;
stratixiigx_hssi_tx_rx_de... | 6.968456 |
module is the behavior model for rx_det block
// If there is rx - set parameter RX_EXIST to 1, set to 0 otherwise
`timescale 1ps / 1ps
module stratixiigx_hssi_tx_rx_det (RX_DET_PDB, CLK15M, TX_DET_RX, RX_FOUND, RX_DET_VALID);
input RX_DET_PDB, CLK15M, TX_DET_RX;
output RX_FOUND, RX_DET_VALID;
wir... | 7.595207 |
module stratixiigx_hssi_calibration_block (
clk,
powerdn,
enabletestbus,
calibrationstatus
);
input clk;
input powerdn;
input enabletestbus;
output [4:0] calibrationstatus;
parameter use_continuous_calibration_mode = "false";
parameter rx_calibration_write_test_value = 0;
parameter tx_ca... | 6.968456 |
module stratixiigx_hssi_pcs_reset (
hard_reset,
clk_2_b,
refclk_b_in,
scan_mode,
rxpcs_rst,
txpcs_rst,
rxrst_int,
txrst_int
);
input hard_reset;
input clk_2_b;
input refclk_b_in;
input scan_mode;
input rxpcs_rst;
input txpcs_rst;
output rxrst_int;
output txrst_int;
r... | 6.968456 |
module stratixiigx_hssi_tx_txclk_ctl (
txrst,
pld_tx_clk,
refclk_pma,
txpma_local_clk,
tx_div2_sync_in_ch0,
tx_div2_sync_in_q0_ch0,
rindv_tx,
rtxwrclksel,
rtxrdclksel,
rdwidth_tx,
rfreerun_tx,
rphfifo_master_sel_tx,
scan_mode,
tx_clk_out,
tx_div2_sync_out,
... | 6.968456 |
module stratixiigx_hssi_mdio_pcs_bus_out_mux (
pcs_ctrl_in1,
pcs_ctrl_in2,
pcs_ctrl_in3,
pcs_ctrl_in4,
pcs_ctrl_in5,
pcs_ctrl_in6,
pcs_ctrl_in7,
pcs_ctrl_in8,
pcs_ctrl_in9,
pcs_ctrl_in10,
pcs_ctrl_in11,
pcs_ctrl_in12,
pcs_ctrl_in13,
pcs_ctrl_in14,
pcs_ctrl_in1... | 6.968456 |
module stratixiigx_hssi_bsc_in_r (
reset,
clk,
sig_in,
ext_in,
jtag_mode,
si,
shift,
mdio_dis,
sig_out,
so
) /* synthesis ALTERA_ATTRIBUTE="{-to so} POWER_UP_LEVEL=LOW" */;
input reset; // reset
input clk; // clock
input sig_in; // signal input
input ext_in; // exte... | 6.968456 |
module stratixiigx_hssi_bsc_out (
clk,
jtag_mode,
reset,
shift_load,
si,
sig_in,
sig_out,
so
) /* synthesis synthesis_clearbox=1 */;
input clk;
input jtag_mode;
input reset;
input shift_load;
input si;
input sig_in;
output sig_out;
output so;
reg n1i1;
reg n1i2;
... | 6.968456 |
module stratixiii_bmux21 (
MO,
A,
B,
S
);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.269529 |
module stratixiii_b17mux21 (
MO,
A,
B,
S
);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.439168 |
module stratixiii_nmux21 (
MO,
A,
B,
S
);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
| 6.932323 |
module stratixiii_b5mux21 (
MO,
A,
B,
S
);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.647098 |
module stratixiii_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0);
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule
| 7.897097 |
module stratixiii_lvds_tx_reg (
q,
clk,
ena,
d,
clrn,
prn
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// BUFFER INPUTS
wire clk_in;
wire ena_in;
wire d_in;
buf (clk_in, clk);
buf (ena_in, ena);
buf (d_in, d);... | 6.593588 |
module stratixiii_lvds_tx_parallel_register (
clk,
enable,
datain,
dataout,
devclrn,
devpor
);
parameter channel_width = 4;
// INPUT PORTS
input [channel_width - 1:0] datain;
input clk;
input enable;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] d... | 6.593588 |
module stratixiii_lvds_tx_out_block (
clk,
datain,
dataout,
devclrn,
devpor
);
parameter bypass_serializer = "false";
parameter invert_clock = "false";
parameter use_falling_clock_edge = "false";
// INPUT PORTS
input datain;
input clk;
input devclrn;
input devpor;
// OUTPUT PORT... | 6.593588 |
module stratixiii_ram_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
parameter delay_pulse = 1'b0;
parameter start_delay = (delay_pulse == 1'b0) ? 1 : 2; // delay write
reg state;
reg... | 6.709501 |
module for RAM inputs/outputs
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module stratixiii_ram_register (
d,
clk,
aclr,
devclrn,
... | 7.458522 |
module stratixiii_first_stage_add_sub (
dataa,
datab,
sign,
operation,
dataout
);
//PARAMETERS
parameter dataa_width = 36;
parameter datab_width = 36;
parameter fsa_mode = "add";
// INPUT PORTS
input [71 : 0] dataa;
input [71 : 0] datab;
input sign;
input [3:0] operation;
// OU... | 8.305598 |
module stratixiii_round_block (
datain,
round,
datain_width,
dataout
);
parameter round_mode = "nearest_integer";
parameter operation_mode = "output_only";
parameter round_width = 15;
input [71 : 0] datain;
input round;
input [7:0] datain_width;
output [71 : 0] dataout;
reg sign;
r... | 7.897097 |
module stratixiii_round_saturate_block (
datain,
round,
saturate,
signa,
signb,
datain_width,
dataout,
saturationoverflow
);
parameter dataa_width = 36;
parameter datab_width = 36;
parameter saturate_width = 15;
parameter round_width = 15;
parameter saturate_mode = " asymmetric... | 7.897097 |
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