code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module stratixiii_rotate_shift_block (
datain,
rotate,
shiftright,
signa,
signb,
dataout
);
parameter dataa_width = 32;
parameter datab_width = 32;
parameter operation_mode = "output_only";
input [71:0] datain;
input rotate;
input shiftright;
input signa;
input signb;
wire sign;
output [71:0] dataout;
reg [71:0] dataout_tmp;
specify
(datain *> dataout) = (0, 0);
(rotate *> dataout) = (0, 0);
(shiftright *> dataout) = (0, 0);
endspecify
assign sign = signa ^ signb;
assign dataout = dataout_tmp;
always @(datain or rotate or shiftright) begin
dataout_tmp = datain;
if ((rotate == 0) && (shiftright == 0)) dataout_tmp[39:8] = datain[39:8];
else if ((rotate == 0) && (shiftright == 1)) dataout_tmp[39:8] = datain[71:40];
else if ((rotate == 1) && (shiftright == 0)) dataout_tmp[39:8] = datain[71:40] | datain[39:8];
else dataout_tmp = datain;
end
endmodule
| 7.897097 |
module for ddr. Gray decoder
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module stratixiii_ddr_gray_decoder (
gin,
bout
);
parameter width = 6;
input [width-1 : 0] gin;
output [width-1 : 0] bout;
reg [width-1 : 0] breg;
integer i;
assign bout = breg;
always @(gin)
begin
breg[width-1] = gin[width-1];
if (width > 1)
begin
for (i=width-2; i >= 0; i=i-1)
breg[i] = breg[i+1] ^ gin[i];
end
end
endmodule
| 7.461079 |
module stratixiii_termination_aux_clock_div (
clk, // input clock
reset, // reset
clkout // divided clock
);
input clk;
input reset;
output clkout;
parameter clk_divide_by = 1;
parameter extra_latency = 0;
integer clk_edges, m;
reg [2*extra_latency:0] div_n_register;
initial begin
div_n_register = 'b0;
clk_edges = -1;
m = 0;
end
always @(posedge clk or negedge clk or posedge reset) begin
if (reset === 1'b1) begin
clk_edges = -1;
div_n_register <= 'b0;
end else begin
if (clk_edges == -1) begin
div_n_register[0] <= clk;
if (clk == 1'b1) clk_edges = 0;
end else if (clk_edges % clk_divide_by == 0) div_n_register[0] <= ~div_n_register[0];
if (clk_edges >= 0 || clk == 1'b1) clk_edges = (clk_edges + 1) % (2 * clk_divide_by);
end
for (m = 0; m < 2 * extra_latency; m = m + 1) div_n_register[m+1] <= div_n_register[m];
end
assign clkout = div_n_register[2*extra_latency];
endmodule
| 7.388711 |
module stratixiii_termination_logic (
serialloadenable,
terminationclock,
parallelloadenable,
terminationdata,
devclrn,
devpor,
seriesterminationcontrol,
parallelterminationcontrol
);
parameter test_mode = "false";
parameter lpm_type = "stratixiii_termination_logic";
input serialloadenable;
input terminationclock;
input parallelloadenable;
input terminationdata;
input devclrn;
input devpor;
output [13:0] seriesterminationcontrol;
output [13:0] parallelterminationcontrol;
tri1 devclrn;
tri1 devpor;
wire usr_clk;
wire shift_clk;
wire pload_clk;
reg [27:0] shift_reg;
reg [27:0] output_reg;
assign seriesterminationcontrol = output_reg[27:14];
assign parallelterminationcontrol = output_reg[13:0];
assign #11 usr_clk = terminationclock;
assign shift_clk = (serialloadenable === 1'b0) ? 1'b0 : usr_clk; // serena & clk
assign pload_clk = (parallelloadenable === 1'b1) ? 1'b1 : 1'b0; // ploaden
initial begin
// does not get reset so whatever power-up values
shift_reg = 'b0;
output_reg = 'b0;
end
always @(posedge shift_clk) shift_reg <= {shift_reg[26:0], terminationdata};
always @(posedge pload_clk) output_reg <= shift_reg;
endmodule
| 7.388711 |
module stratixiii_tsdblock (
offset,
clk,
ce,
clr,
testin,
tsdcalo,
tsdcaldone,
fdbkctrlfromcore,
compouttest,
tsdcompout,
offsetout
);
input [5:0] offset;
input [7:0] testin;
input clk;
input ce;
input clr;
input fdbkctrlfromcore;
input compouttest;
output [7:0] tsdcalo;
output tsdcaldone;
output tsdcompout;
output [5:0] offsetout;
parameter poi_cal_temperature = 85;
parameter clock_divider_enable = "on";
parameter clock_divider_value = 40;
parameter sim_tsdcalo = 0;
parameter user_offset_enable = "off";
parameter lpm_type = "stratixiii_tsdblock";
endmodule
| 7.063645 |
module stratixiii_lvds_rx_fifo_sync_ram (
clk,
datain,
write_reset,
waddr,
raddr,
we,
dataout
);
// INPUT PORTS
input clk;
input write_reset;
input datain;
input [2:0] waddr;
input [2:0] raddr;
input we;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES AND NETS
reg dataout_tmp;
reg [0:5] ram_d;
reg [0:5] ram_q;
wire [0:5] data_reg;
integer i;
initial begin
dataout_tmp = 0;
for (i = 0; i <= 5; i = i + 1) ram_q[i] <= 1'b0;
end
// Write port
always @(posedge clk or posedge write_reset) begin
if (write_reset == 1'b1) begin
for (i = 0; i <= 5; i = i + 1) ram_q[i] <= 1'b0;
end else begin
for (i = 0; i <= 5; i = i + 1) ram_q[i] <= ram_d[i];
end
end
always @(we or data_reg or ram_q) begin
if (we === 1'b1) begin
ram_d <= data_reg;
end else begin
ram_d <= ram_q;
end
end
// Read port
assign data_reg[0] = (waddr == 3'b000) ? datain : ram_q[0];
assign data_reg[1] = (waddr == 3'b001) ? datain : ram_q[1];
assign data_reg[2] = (waddr == 3'b010) ? datain : ram_q[2];
assign data_reg[3] = (waddr == 3'b011) ? datain : ram_q[3];
assign data_reg[4] = (waddr == 3'b100) ? datain : ram_q[4];
assign data_reg[5] = (waddr == 3'b101) ? datain : ram_q[5];
always @(ram_q or we or waddr or raddr) begin
case (raddr)
3'b000: dataout_tmp = ram_q[0];
3'b001: dataout_tmp = ram_q[1];
3'b010: dataout_tmp = ram_q[2];
3'b011: dataout_tmp = ram_q[3];
3'b100: dataout_tmp = ram_q[4];
3'b101: dataout_tmp = ram_q[5];
default: dataout_tmp = 0;
endcase
end
// set output
assign dataout = dataout_tmp;
endmodule
| 6.593588 |
module stratixiii_lvds_rx_fifo (
wclk,
rclk,
dparst,
fiforst,
datain,
dataout
);
parameter channel_width = 10;
// INPUT PORTS
input wclk;
input rclk;
input dparst;
input fiforst;
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES AND NETS
reg dataout_tmp;
wire data_out;
integer i;
reg ram_datain;
wire ram_dataout;
reg [2:0] wrPtr, rdPtr; // writer pointer, read pointer
wire [2:0] rdAddr; // read address
reg ram_we;
reg wclk_last_value, rclk_last_value;
reg write_side_sync_reset;
reg read_side_sync_reset;
specify
(posedge rclk => (dataout +: data_out)) = (0, 0);
(posedge dparst => (dataout +: data_out)) = (0, 0);
endspecify
initial begin
dataout_tmp = 0;
wrPtr = 2'b00;
rdPtr = 2'b11;
write_side_sync_reset = 1'b0;
read_side_sync_reset = 1'b0;
end
assign rdAddr = rdPtr;
stratixiii_lvds_rx_fifo_sync_ram s_fifo_ram (
.clk(wclk),
.datain(ram_datain),
.write_reset(write_side_sync_reset),
.waddr(wrPtr),
.raddr(rdAddr), // rdPtr ??
.we(ram_we),
.dataout(ram_dataout)
);
// update pointer and RAM input
always @(wclk or dparst) begin
if (dparst === 1'b1 || (fiforst === 1'b1 && wclk === 1'b1 && wclk_last_value === 1'b0)) begin
write_side_sync_reset <= 1'b1;
ram_datain <= 1'b0;
wrPtr <= 0;
ram_we <= 'b0;
end
else if (dparst === 1'b0 && (fiforst === 1'b0 && wclk === 1'b1 && wclk_last_value === 1'b0))
begin
write_side_sync_reset <= 1'b0;
end
if (wclk === 1'b1 && wclk_last_value === 1'b0 && write_side_sync_reset === 1'b0 && fiforst === 1'b0 && dparst === 1'b0)
begin
ram_datain <= datain; // input register
ram_we <= 'b1;
wrPtr <= wrPtr + 1;
if (wrPtr == 5) wrPtr <= 0;
end
wclk_last_value = wclk;
end
always @(rclk or dparst) begin
if (dparst === 1'b1 || (fiforst === 1'b1 && rclk === 1'b1 && rclk_last_value === 1'b0)) begin
read_side_sync_reset <= 1'b1;
rdPtr <= 3;
dataout_tmp <= 0;
end
else if (dparst === 1'b0 && (fiforst === 1'b0 && rclk === 1'b1 && rclk_last_value === 1'b0))
begin
read_side_sync_reset <= 0;
end
if (rclk === 1'b1 && rclk_last_value === 1'b0 && read_side_sync_reset === 1'b0 && fiforst === 1'b0 && dparst === 1'b0)
begin
rdPtr <= rdPtr + 1;
if (rdPtr == 5) rdPtr <= 0;
dataout_tmp <= ram_dataout; // output register
end
rclk_last_value = rclk;
end
assign data_out = dataout_tmp;
buf (dataout, data_out);
endmodule
| 6.593588 |
module receives serial data and outputs
// parallel data word of width = channel_width
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratixiii_lvds_rx_deser (
clk,
datain,
devclrn,
devpor,
dataout
);
parameter channel_width = 10;
// INPUT PORTS
input clk;
input datain;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] dataout;
// INTERNAL VARIABLES AND NETS
reg [channel_width - 1:0] dataout_tmp;
reg clk_last_value;
integer i;
specify
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
endspecify
initial
begin
clk_last_value = 0;
dataout_tmp = 'b0;
end
always @(clk or devclrn or devpor)
begin
if (devclrn === 1'b0 || devpor === 1'b0)
begin
dataout_tmp <= 'b0;
end
else if (clk === 1'b1 && clk_last_value === 1'b0)
begin
for (i = (channel_width-1); i > 0; i=i-1)
dataout_tmp[i] <= dataout_tmp[i-1];
dataout_tmp[0] <= datain;
end
clk_last_value <= clk;
end
assign dataout = dataout_tmp;
endmodule
| 6.910834 |
module stratixiii_lvds_rx_parallel_reg (
clk,
enable,
datain,
dataout,
devclrn,
devpor
);
parameter channel_width = 10;
// INPUT PORTS
input [channel_width - 1:0] datain;
input clk;
input enable;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] dataout;
// INTERNAL VARIABLES AND NETS
reg clk_last_value;
reg [channel_width - 1:0] dataout_tmp;
specify
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
endspecify
initial begin
clk_last_value = 0;
dataout_tmp = 'b0;
end
always @(clk or devpor or devclrn) begin
if ((devpor === 1'b0) || (devclrn === 1'b0)) begin
dataout_tmp <= 'b0;
end else begin
if ((clk === 1) && (clk_last_value !== clk)) begin
if (enable === 1) begin
dataout_tmp <= datain;
end
end
end
clk_last_value <= clk;
end //always
assign dataout = dataout_tmp;
endmodule
| 6.593588 |
module stratixiii_lvds_reg (
q,
clk,
ena,
d,
clrn,
prn
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q_tmp;
wire q_wire;
// TIMING PATHS
specify
(posedge clk => (q +: q_tmp)) = (0, 0);
(negedge clrn => (q +: q_tmp)) = (0, 0);
(negedge prn => (q +: q_tmp)) = (0, 0);
endspecify
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q_tmp = 0;
always @(posedge clk or negedge clrn or negedge prn) begin
if (prn == 1'b0) q_tmp <= 1;
else if (clrn == 1'b0) q_tmp <= 0;
else if ((clk == 1) & (ena == 1'b1)) q_tmp <= d;
end
assign q_wire = q_tmp;
and (q, q_wire, 1'b1);
endmodule
| 6.593588 |
module stratixiii_pclk_divider (
clkin,
lloaden,
clkout
);
parameter clk_divide_by = 1;
input clkin;
output lloaden;
output clkout;
reg clkout_tmp;
reg [4:0] cnt;
reg start;
reg count;
reg lloaden_tmp;
assign clkout = (clk_divide_by == 1) ? clkin : clkout_tmp;
assign lloaden = lloaden_tmp;
initial begin
clkout_tmp = 1'b0;
cnt = 5'b00000;
start = 1'b0;
count = 1'b0;
lloaden_tmp = 1'b0;
end
always @(clkin) begin
if (clkin == 1'b1) begin
count = 1'b1;
end
if (count == 1'b1) begin
if (cnt < clk_divide_by) begin
clkout_tmp = 1'b0;
cnt = cnt + 1'b1;
end else begin
if (cnt == 2 * clk_divide_by - 1) cnt = 0;
else begin
clkout_tmp = 1'b1;
cnt = cnt + 1;
end
end
end
end
always @(clkin or cnt) begin
if (cnt == 2 * clk_divide_by - 2) lloaden_tmp = 1'b1;
else if (cnt == 0) lloaden_tmp = 1'b0;
end
endmodule
| 6.568371 |
module stratixiii_pseudo_diff_out (
i,
o,
obar
);
parameter lpm_type = "stratixiii_pseudo_diff_out";
input i;
output o;
output obar;
reg o_tmp;
reg obar_tmp;
assign o = o_tmp;
assign obar = obar_tmp;
always @(i) begin
if (i == 1'b1) begin
o_tmp = 1'b1;
obar_tmp = 1'b0;
end else if (i == 1'b0) begin
o_tmp = 1'b0;
obar_tmp = 1'b1;
end else begin
o_tmp = i;
obar_tmp = i;
end
end
endmodule
| 7.138801 |
module stratixiii_bias_logic (
clk,
shiftnld,
captnupdt,
mainclk,
updateclk,
capture,
update
);
// INPUT PORTS
input clk;
input shiftnld;
input captnupdt;
// OUTPUTPUT PORTS
output mainclk;
output updateclk;
output capture;
output update;
// INTERNAL VARIABLES
reg mainclk_tmp;
reg updateclk_tmp;
reg capture_tmp;
reg update_tmp;
initial begin
mainclk_tmp <= 'b0;
updateclk_tmp <= 'b0;
capture_tmp <= 'b0;
update_tmp <= 'b0;
end
always @(captnupdt or shiftnld or clk) begin
case ({
captnupdt, shiftnld
})
2'b10, 2'b11: begin
mainclk_tmp <= 'b0;
updateclk_tmp <= clk;
capture_tmp <= 'b1;
update_tmp <= 'b0;
end
2'b01: begin
mainclk_tmp <= 'b0;
updateclk_tmp <= clk;
capture_tmp <= 'b0;
update_tmp <= 'b0;
end
2'b00: begin
mainclk_tmp <= clk;
updateclk_tmp <= 'b0;
capture_tmp <= 'b0;
update_tmp <= 'b1;
end
default: begin
mainclk_tmp <= 'b0;
updateclk_tmp <= 'b0;
capture_tmp <= 'b0;
update_tmp <= 'b0;
end
endcase
end
and (mainclk, mainclk_tmp, 1'b1);
and (updateclk, updateclk_tmp, 1'b1);
and (capture, capture_tmp, 1'b1);
and (update, update_tmp, 1'b1);
endmodule
| 8.317317 |
module stratixiii_bias_generator (
din,
mainclk,
updateclk,
capture,
update,
dout
);
// INPUT PORTS
input din;
input mainclk;
input updateclk;
input capture;
input update;
// OUTPUTPUT PORTS
output dout;
parameter TOTAL_REG = 252;
// INTERNAL VARIABLES
reg dout_tmp;
reg generator_reg[TOTAL_REG - 1:0];
reg update_reg[TOTAL_REG - 1:0];
integer i;
initial begin
dout_tmp <= 'b0;
for (i = 0; i < TOTAL_REG; i = i + 1) begin
generator_reg[i] <= 'b0;
update_reg[i] <= 'b0;
end
end
// main generator registers
always @(posedge mainclk) begin
if ((capture == 'b0) && (update == 'b1)) //update main registers
begin
for (i = 0; i < TOTAL_REG; i = i + 1) begin
generator_reg[i] <= update_reg[i];
end
end
end
// update registers
always @(posedge updateclk) begin
dout_tmp <= update_reg[TOTAL_REG-1];
if ((capture == 'b0) && (update == 'b0)) //shift update registers
begin
for (i = (TOTAL_REG - 1); i > 0; i = i - 1) begin
update_reg[i] <= update_reg[i-1];
end
update_reg[0] <= din;
end
else if ((capture == 'b1) && (update == 'b0)) //load update registers
begin
for (i = 0; i < TOTAL_REG; i = i + 1) begin
update_reg[i] <= generator_reg[i];
end
end
end
and (dout, dout_tmp, 1'b1);
endmodule
| 8.317317 |
module stratixiii_bias_block (
clk,
shiftnld,
captnupdt,
din,
dout
);
// INPUT PORTS
input clk;
input shiftnld;
input captnupdt;
input din;
// OUTPUTPUT PORTS
output dout;
parameter lpm_type = "stratixiii_bias_block";
// INTERNAL VARIABLES
reg din_viol;
reg shiftnld_viol;
reg captnupdt_viol;
wire mainclk_wire;
wire updateclk_wire;
wire capture_wire;
wire update_wire;
wire dout_tmp;
specify
$setuphold(posedge clk, din, 0, 0, din_viol);
$setuphold(posedge clk, shiftnld, 0, 0, shiftnld_viol);
$setuphold(posedge clk, captnupdt, 0, 0, captnupdt_viol);
(posedge clk => (dout +: dout_tmp)) = 0;
endspecify
stratixiii_bias_logic logic_block (
.clk(clk),
.shiftnld(shiftnld),
.captnupdt(captnupdt),
.mainclk(mainclk_wire),
.updateclk(updateclk_wire),
.capture(capture_wire),
.update(update_wire)
);
stratixiii_bias_generator bias_generator (
.din(din),
.mainclk(mainclk_wire),
.updateclk(updateclk_wire),
.capture(capture_wire),
.update(update_wire),
.dout(dout_tmp)
);
and (dout, dout_tmp, 1'b1);
endmodule
| 8.317317 |
module stratixiv_bmux21 (
MO,
A,
B,
S
);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.454026 |
module stratixiv_b17mux21 (
MO,
A,
B,
S
);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.572469 |
module stratixiv_nmux21 (
MO,
A,
B,
S
);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
| 7.337416 |
module stratixiv_b5mux21 (
MO,
A,
B,
S
);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.842022 |
module stratixiv_lvds_tx_reg (
q,
clk,
ena,
d,
clrn,
prn
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// BUFFER INPUTS
wire clk_in;
wire ena_in;
wire d_in;
buf (clk_in, clk);
buf (ena_in, ena);
buf (d_in, d);
// INTERNAL VARIABLES
reg q_tmp;
wire q_wire;
// TIMING PATHS
specify
$setuphold(posedge clk, d, 0, 0);
(posedge clk => (q +: q_tmp)) = (0, 0);
(negedge clrn => (q +: q_tmp)) = (0, 0);
(negedge prn => (q +: q_tmp)) = (0, 0);
endspecify
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q_tmp = 0;
always @(posedge clk_in or negedge clrn or negedge prn) begin
if (prn == 1'b0) q_tmp <= 1;
else if (clrn == 1'b0) q_tmp <= 0;
else if ((clk_in == 1) & (ena_in == 1'b1)) q_tmp <= d_in;
end
assign q_wire = q_tmp;
and (q, q_wire, 1'b1);
endmodule
| 6.833933 |
module stratixiv_lvds_tx_parallel_register (
clk,
enable,
datain,
dataout,
devclrn,
devpor
);
parameter channel_width = 4;
// INPUT PORTS
input [channel_width - 1:0] datain;
input clk;
input enable;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] dataout;
// INTERNAL VARIABLES AND NETS
reg clk_last_value;
reg [channel_width - 1:0] dataout_tmp;
wire clk_ipd;
wire enable_ipd;
wire [channel_width - 1:0] datain_ipd;
buf buf_clk (clk_ipd, clk);
buf buf_enable (enable_ipd, enable);
buf buf_datain[channel_width - 1:0] (datain_ipd, datain);
wire [channel_width - 1:0] dataout_opd;
buf buf_dataout[channel_width - 1:0] (dataout, dataout_opd);
// TIMING PATHS
specify
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
$setuphold(posedge clk, datain, 0, 0);
endspecify
initial begin
clk_last_value = 0;
dataout_tmp = 'b0;
end
always @(clk_ipd or enable_ipd or devpor or devclrn) begin
if ((devpor === 1'b0) || (devclrn === 1'b0)) begin
dataout_tmp <= 'b0;
end else begin
if ((clk_ipd === 1'b1) && (clk_last_value !== clk_ipd)) begin
if (enable_ipd === 1'b1) begin
dataout_tmp <= datain_ipd;
end
end
end
clk_last_value <= clk_ipd;
end // always
assign dataout_opd = dataout_tmp;
endmodule
| 6.833933 |
module stratixiv_lvds_tx_out_block (
clk,
datain,
dataout,
devclrn,
devpor
);
parameter bypass_serializer = "false";
parameter invert_clock = "false";
parameter use_falling_clock_edge = "false";
// INPUT PORTS
input datain;
input clk;
input devclrn;
input devpor;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES AND NETS
reg dataout_tmp;
reg clk_last_value;
wire bypass_mode;
wire invert_mode;
wire falling_clk_out;
// BUFFER INPUTS
wire clk_in;
wire datain_in;
buf (clk_in, clk);
buf (datain_in, datain);
// TEST PARAMETER VALUES
assign falling_clk_out = (use_falling_clock_edge == "true") ? 1'b1 : 1'b0;
assign bypass_mode = (bypass_serializer == "true") ? 1'b1 : 1'b0;
assign invert_mode = (invert_clock == "true") ? 1'b1 : 1'b0;
// TIMING PATHS
specify
if (bypass_mode == 1'b1) (clk => dataout) = (0, 0);
if (bypass_mode == 1'b0 && falling_clk_out == 1'b1)
(negedge clk => (dataout +: dataout_tmp)) = (0, 0);
if (bypass_mode == 1'b0 && falling_clk_out == 1'b0)
(datain => (dataout +: dataout_tmp)) = (0, 0);
endspecify
initial begin
clk_last_value = 0;
dataout_tmp = 0;
end
always @(clk_in or datain_in or devclrn or devpor) begin
if ((devpor === 1'b0) || (devclrn === 1'b0)) begin
dataout_tmp <= 0;
end else begin
if (bypass_serializer == "false") begin
if (use_falling_clock_edge == "false") dataout_tmp <= datain_in;
if ((clk_in === 1'b0) && (clk_last_value !== clk_in)) begin
if (use_falling_clock_edge == "true") dataout_tmp <= datain_in;
end
end // bypass is off
else begin
// generate clk_out
if (invert_clock == "false") dataout_tmp <= clk_in;
else dataout_tmp <= !clk_in;
end // clk output
end
clk_last_value <= clk_in;
end // always
and (dataout, dataout_tmp, 1'b1);
endmodule
| 6.833933 |
module stratixiv_ram_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
parameter delay_pulse = 1'b0;
parameter start_delay = (delay_pulse == 1'b0) ? 1 : 2; // delay write
reg state;
reg clk_prev;
wire clk_ipd;
specify
specparam t_decode = 0, t_access = 0;
(posedge clk => (pulse +: state)) = (t_decode, t_access);
endspecify
buf #(start_delay) (clk_ipd, clk);
wire pulse_opd;
buf buf_pulse (pulse, pulse_opd);
initial clk_prev = 1'bx;
always @(clk_ipd or posedge pulse) begin
if (pulse) state <= 1'b0;
else if (ena && clk_ipd === 1'b1 && clk_prev === 1'b0) state <= 1'b1;
clk_prev = clk_ipd;
end
assign cycle = clk_ipd;
assign pulse_opd = state;
endmodule
| 6.695438 |
module for RAM inputs/outputs
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module stratixiv_ram_register (
d,
clk,
aclr,
devclrn,
devpor,
stall,
ena,
q,
aclrout
);
parameter width = 1; // data width
parameter preset = 1'b0; // clear acts as preset
input [width - 1:0] d; // data
input clk; // clock
input aclr; // asynch clear
input devclrn,devpor; // device wide clear/reset
input stall; // address stall
input ena; // clock enable
output [width - 1:0] q; // register output
output aclrout; // delayed asynch clear
wire ena_ipd;
wire clk_ipd;
wire aclr_ipd;
wire [width - 1:0] d_ipd;
buf buf_ena (ena_ipd,ena);
buf buf_clk (clk_ipd,clk);
buf buf_aclr (aclr_ipd,aclr);
buf buf_d [width - 1:0] (d_ipd,d);
wire stall_ipd;
buf buf_stall (stall_ipd,stall);
wire [width - 1:0] q_opd;
buf buf_q [width - 1:0] (q,q_opd);
reg [width - 1:0] q_reg;
reg viol_notifier;
wire reset;
assign reset = devpor && devclrn && (!aclr_ipd) && (ena_ipd);
specify
$setup (d, posedge clk &&& reset, 0, viol_notifier);
$setup (aclr, posedge clk, 0, viol_notifier);
$setup (ena, posedge clk &&& reset, 0, viol_notifier );
$setup (stall, posedge clk &&& reset, 0, viol_notifier );
$hold (posedge clk &&& reset, d , 0, viol_notifier);
$hold (posedge clk, aclr, 0, viol_notifier);
$hold (posedge clk &&& reset, ena , 0, viol_notifier );
$hold (posedge clk &&& reset, stall, 0, viol_notifier );
(posedge clk => (q +: q_reg)) = (0,0);
(posedge aclr => (q +: q_reg)) = (0,0);
endspecify
initial q_reg <= (preset) ? {width{1'b1}} : 'b0;
always @(posedge clk_ipd or posedge aclr_ipd or negedge devclrn or negedge devpor)
begin
if (aclr_ipd || ~devclrn || ~devpor)
q_reg <= (preset) ? {width{1'b1}} : 'b0;
else if (ena_ipd & !stall_ipd)
q_reg <= d_ipd;
end
assign aclrout = aclr_ipd;
assign q_opd = q_reg;
endmodule
| 7.458522 |
module stratixiv_ddio_oe (
oe,
clk,
ena,
areset,
sreset,
dataout,
dfflo,
dffhi,
devpor,
devclrn
);
//Parameters Declaration
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter lpm_type = "stratixiv_ddio_oe";
//Input Ports Declaration
input oe;
input clk;
input ena;
input areset;
input sreset;
input devpor;
input devclrn;
//Output Ports Declaration
output dataout;
//Buried Ports Declaration
output dfflo;
output dffhi;
tri1 devclrn;
tri1 devpor;
//Internal Signals
reg ddioreg_aclr;
reg ddioreg_prn;
reg ddioreg_adatasdata;
reg ddioreg_sclr;
reg ddioreg_sload;
reg viol_notifier;
initial begin
ddioreg_aclr = 1'b1;
ddioreg_prn = 1'b1;
ddioreg_adatasdata = 1'b0;
ddioreg_sclr = 1'b0;
ddioreg_sload = 1'b0;
end
wire dfflo_tmp;
wire dffhi_tmp;
always @(areset or sreset) begin
if (async_mode == "clear") begin
ddioreg_aclr = !areset;
ddioreg_prn = 1'b1;
end else if (async_mode == "preset") begin
ddioreg_aclr = 'b1;
ddioreg_prn = !areset;
end else begin
ddioreg_aclr = 'b1;
ddioreg_prn = 'b1;
end
if (sync_mode == "clear") begin
ddioreg_adatasdata = 'b0;
ddioreg_sclr = sreset;
ddioreg_sload = 'b0;
end else if (sync_mode == "preset") begin
ddioreg_adatasdata = 'b1;
ddioreg_sclr = 'b0;
ddioreg_sload = sreset;
end else begin
ddioreg_adatasdata = 'b0;
ddioreg_sclr = 'b0;
ddioreg_sload = 'b0;
end
end
//DDIO OE Register
dffeas ddioreg_hi (
.d(oe),
.clk(clk),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dffhi_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_hi.power_up = power_up;
//DDIO Low Register
dffeas ddioreg_lo (
.d(dffhi_tmp),
.clk(!clk),
.clrn(ddioreg_aclr),
.aload(1'b0),
.sclr(ddioreg_sclr),
.sload(ddioreg_sload),
.asdata(ddioreg_adatasdata),
.ena(ena),
.prn(ddioreg_prn),
.q(dfflo_tmp),
.devpor(devpor),
.devclrn(devclrn)
);
defparam ddioreg_lo.power_up = power_up;
//registered output
stratixiv_mux21 or_gate (
.MO(dataout),
.A (dffhi_tmp),
.B (dfflo_tmp),
.S (dfflo_tmp)
);
assign dfflo = dfflo_tmp;
assign dffhi = dffhi_tmp;
endmodule
| 6.627073 |
module stratixiv_mac_register (
datain,
clk,
aclr,
sload,
bypass_register,
dataout
);
//PARAMETER
parameter data_width = 18;
//INPUT PORTS
input [data_width -1 : 0] datain;
input clk;
input aclr;
input sload;
input bypass_register;
//OUTPUT PORTS
output [data_width -1 : 0] dataout;
//INTERNAL SIGNALS
reg [data_width -1:0] dataout_tmp;
reg viol_notifier;
reg prev_clk_val;
//TIMING SPECIFICATION
specify
specparam TSU = 0; // Set up time
specparam TH = 0; // Hold time
specparam TCO = 0; // Clock to Output time
specparam TCLR = 0; // Clear time
specparam TCLR_MIN_PW = 0; // Minimum pulse width of clear
specparam TPRE = 0; // Preset time
specparam TPRE_MIN_PW = 0; // Minimum pulse width of preset
specparam TCLK_MIN_PW = 0; // Minimum pulse width of clock
specparam TCE_MIN_PW = 0; // Minimum pulse width of clock enable
specparam TCLKL = 0; // Minimum clock low time
specparam TCLKH = 0; // Minimum clock high time
$setup(datain, posedge clk, 0, viol_notifier);
$hold(posedge clk, datain, 0, viol_notifier);
$setup(sload, posedge clk, 0, viol_notifier);
$hold(posedge clk, sload, 0, viol_notifier);
(posedge aclr => (dataout +: 'b0)) = (0, 0);
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
endspecify
initial begin
dataout_tmp = 0;
prev_clk_val = 1'b0;
end
always @(clk or posedge aclr or bypass_register or datain) begin
if (bypass_register == 1'b1) dataout_tmp <= datain;
else begin
if (aclr == 1'b1) dataout_tmp <= 0;
else if (prev_clk_val == 1'b0 && clk == 1'b1) begin
if (sload == 1'b1) dataout_tmp <= datain;
else dataout_tmp <= dataout_tmp;
end
end
prev_clk_val = clk;
end
assign dataout = dataout_tmp;
endmodule
| 6.775929 |
module stratixiv_mac_multiplier (
dataa,
datab,
signa,
signb,
dataout
);
//PARAMETER
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataout_width = dataa_width + datab_width;
//INPUT PORTS
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;
//OUTPUT PORTS
output [dataout_width -1 : 0] dataout;
//INTERNAL SIGNALS
wire [dataout_width -1:0] product; //product of dataa and datab
wire [dataout_width -1:0] abs_product; //|product| of dataa and datab
wire [ dataa_width-1:0] abs_a; //absolute value of dataa
wire [ datab_width-1:0] abs_b; //absolute value of dadab
wire product_sign; // product sign bit
wire dataa_sign; //dataa sign bit
wire datab_sign; //datab sign bit
//TIMING SPECIFICATION
specify
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
(signa *> dataout) = (0, 0);
(signb *> dataout) = (0, 0);
endspecify
//Outputassignment
assign dataa_sign = dataa[dataa_width-1] && signa;
assign datab_sign = datab[datab_width-1] && signb;
assign product_sign = dataa_sign ^ datab_sign;
assign abs_a = dataa_sign ? (~dataa + 1'b1) : dataa;
assign abs_b = datab_sign ? (~datab + 1'b1) : datab;
assign abs_product = abs_a * abs_b;
assign product = product_sign ? (~abs_product + 1) : abs_product;
assign dataout = product;
endmodule
| 6.775929 |
module stratixiv_first_stage_add_sub (
dataa,
datab,
sign,
operation,
dataout
);
//PARAMETERS
parameter dataa_width = 36;
parameter datab_width = 36;
parameter fsa_mode = "add";
// INPUT PORTS
input [71 : 0] dataa;
input [71 : 0] datab;
input sign;
input [3:0] operation;
// OUTPUT PORTS
output [71:0] dataout;
//INTERNAL SIGNALS
reg [71 : 0] dataout_tmp;
reg [71:0] abs_b;
reg [71:0] abs_a;
reg sign_a;
reg sign_b;
specify
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
(sign *> dataout) = (0, 0);
endspecify
//assign the output values
assign dataout = dataout_tmp;
always @(dataa or datab or sign or operation) begin
if((operation == 4'b0111) ||(operation == 4'b1000)|| (operation == 4'b1001)) //36 bit multiply, shift and add
begin
dataout_tmp = {dataa[53:36], dataa[35:0], 18'b0} + datab;
end else begin
sign_a = (sign && dataa[dataa_width-1]);
abs_a = (sign_a) ? (~dataa + 1'b1) : dataa;
sign_b = (sign && datab[datab_width-1]);
abs_b = (sign_b) ? (~datab + 1'b1) : datab;
if (fsa_mode == "add") dataout_tmp = (sign_a ? -abs_a : abs_a) + (sign_b ? -abs_b : abs_b);
else dataout_tmp = (sign_a ? -abs_a : abs_a) - (sign_b ? -abs_b : abs_b);
end
end
endmodule
| 8.570866 |
module stratixiv_second_stage_add_accum (
dataa,
datab,
accumin,
sign,
operation,
dataout,
overflow
);
//PARAMETERS
parameter dataa_width = 36;
parameter datab_width = 36;
parameter accum_width = dataa_width + 8;
parameter ssa_mode = "add";
// INPUT PORTS
input [71 : 0] dataa;
input [71 : 0] datab;
input [71 : 0] accumin;
input sign;
input [3:0] operation;
// OUTPUT PORTS
output overflow;
output [71 : 0] dataout;
//INTERNAL SIGNALS
reg [71 : 0] dataout_tmp;
reg [71:0] dataa_tmp;
reg [71:0] datab_tmp;
reg [71:0] accum_tmp;
reg sign_a;
reg sign_b;
reg sign_accum;
reg sign_out;
reg overflow_tmp;
reg [71 : 0] abs_a;
reg [71 : 0] abs_b;
reg [71 : 0] abs_accum;
specify
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
(sign *> dataout) = (0, 0);
(dataa *> overflow) = (0, 0);
(datab *> overflow) = (0, 0);
(sign *> overflow) = (0, 0);
if (operation == 4'b0011 || operation == 4'b0100) (accumin *> dataout) = (0, 0);
if (operation == 4'b0011 || operation == 4'b0100) (accumin *> overflow) = (0, 0);
endspecify
//assign the output values
assign dataout = dataout_tmp;
assign overflow = overflow_tmp;
always @(dataa or datab or sign or accumin or operation) begin
sign_accum = (sign && accumin[accum_width-1]);
abs_accum = (sign_accum) ? (~accumin + 1'b1) : accumin;
sign_a = (sign && dataa[dataa_width-1]);
abs_a = (sign_a) ? (~dataa + 1'b1) : dataa;
sign_b = (sign && datab[datab_width-1]);
abs_b = (sign_b) ? (~datab + 1'b1) : datab;
if(operation == 4'b0011 || operation == 4'b0100 )//Accumultor or Accumulator chainout
begin
if (ssa_mode == "add")
dataout_tmp = (sign_accum ? -abs_accum[accum_width -1 : 0] : abs_accum[accum_width -1 : 0]) + (sign_a ? -abs_a[accum_width -1 : 0] : abs_a[accum_width -1 : 0]) + (sign_b ? -abs_b[accum_width -1 : 0] : abs_b[accum_width -1 : 0]);
else
dataout_tmp = (sign_accum ? -abs_accum[accum_width -1 : 0] : abs_accum[accum_width -1 : 0]) - (sign_a ? -abs_a[accum_width -1 : 0] : abs_a[accum_width -1 : 0]) - (sign_b ? -abs_b[accum_width -1 : 0] : abs_b[accum_width -1 : 0]);
if (sign) overflow_tmp = dataout_tmp[accum_width] ^ dataout_tmp[accum_width-1];
else begin
if (ssa_mode == "add") overflow_tmp = dataout_tmp[accum_width];
else overflow_tmp = 1'bX;
end
end
else if( operation == 4'b0101 || operation == 4'b0110)// two level adder or two level with chainout
begin
dataout_tmp = (sign_a ? -abs_a : abs_a) + (sign_b ? -abs_b : abs_b);
overflow_tmp = 'b0;
end
else if(( operation == 4'b0111) ||(operation == 4'b1000)) //36 bit multiply; shift and add
begin
dataout_tmp[71:0] = {dataa[53:0], 18'b0} + datab;
overflow_tmp = 'b0;
end
else if(( operation == 4'b1001) ) //double mode
begin
dataout_tmp[71:0] = dataa + datab;
overflow_tmp = 'b0;
end
end
endmodule
| 6.912358 |
module stratixiv_rotate_shift_block (
datain,
rotate,
shiftright,
signa,
signb,
dataout
);
parameter dataa_width = 32;
parameter datab_width = 32;
parameter operation_mode = "output_only";
input [71:0] datain;
input rotate;
input shiftright;
input signa;
input signb;
wire sign;
output [71:0] dataout;
reg [71:0] dataout_tmp;
specify
(datain *> dataout) = (0, 0);
(rotate *> dataout) = (0, 0);
(shiftright *> dataout) = (0, 0);
endspecify
assign sign = signa ^ signb;
assign dataout = dataout_tmp;
always @(datain or rotate or shiftright) begin
dataout_tmp = datain;
if ((rotate == 0) && (shiftright == 0)) dataout_tmp[39:8] = datain[39:8];
else if ((rotate == 0) && (shiftright == 1)) dataout_tmp[39:8] = datain[71:40];
else if ((rotate == 1) && (shiftright == 0)) dataout_tmp[39:8] = datain[71:40] | datain[39:8];
else dataout_tmp = datain;
end
endmodule
| 8.182462 |
module stratixiv_carry_chain_adder (
dataa,
datab,
dataout
);
// INPUT PORTS
input [71 : 0] dataa;
input [71 : 0] datab;
// OUTPUT PORTS
output [71 : 0] dataout;
reg [71:0] dataout_tmp;
specify
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
endspecify
assign dataout = dataout_tmp;
initial begin
dataout_tmp = 72'b0;
end
always @(dataa or datab) begin
dataout_tmp = {dataa[43], dataa[43:0]} + {datab[43], datab[43:0]};
end
endmodule
| 6.618876 |
module for ddr. Gray decoder
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module stratixiv_ddr_gray_decoder (
gin,
bout
);
parameter width = 6;
input [width-1 : 0] gin;
output [width-1 : 0] bout;
reg [width-1 : 0] breg;
integer i;
assign bout = breg;
always @(gin)
begin
breg[width-1] = gin[width-1];
if (width > 1)
begin
for (i=width-2; i >= 0; i=i-1)
breg[i] = breg[i+1] ^ gin[i];
end
end
endmodule
| 7.461079 |
module stratixiv_termination_aux_clock_div (
clk, // input clock
reset, // reset
clkout // divided clock
);
input clk;
input reset;
output clkout;
parameter clk_divide_by = 1;
parameter extra_latency = 0;
integer clk_edges, m;
reg [2*extra_latency:0] div_n_register;
initial begin
div_n_register = 'b0;
clk_edges = -1;
m = 0;
end
always @(posedge clk or negedge clk or posedge reset) begin
if (reset === 1'b1) begin
clk_edges = -1;
div_n_register <= 'b0;
end else begin
if (clk_edges == -1) begin
div_n_register[0] <= clk;
if (clk == 1'b1) clk_edges = 0;
end else if (clk_edges % clk_divide_by == 0) div_n_register[0] <= ~div_n_register[0];
if (clk_edges >= 0 || clk == 1'b1) clk_edges = (clk_edges + 1) % (2 * clk_divide_by);
end
for (m = 0; m < 2 * extra_latency; m = m + 1) div_n_register[m+1] <= div_n_register[m];
end
assign clkout = div_n_register[2*extra_latency];
endmodule
| 7.896739 |
module stratixiv_termination_logic (
serialloadenable,
terminationclock,
parallelloadenable,
terminationdata,
devclrn,
devpor,
seriesterminationcontrol,
parallelterminationcontrol
);
parameter test_mode = "false";
parameter lpm_type = "stratixiv_termination_logic";
input serialloadenable;
input terminationclock;
input parallelloadenable;
input terminationdata;
input devclrn;
input devpor;
output [13:0] seriesterminationcontrol;
output [13:0] parallelterminationcontrol;
tri1 devclrn;
tri1 devpor;
wire usr_clk;
wire shift_clk;
wire pload_clk;
reg [27:0] shift_reg;
reg [27:0] output_reg;
assign seriesterminationcontrol = output_reg[27:14];
assign parallelterminationcontrol = output_reg[13:0];
assign #11 usr_clk = terminationclock;
assign shift_clk = (serialloadenable === 1'b0) ? 1'b0 : usr_clk; // serena & clk
assign pload_clk = (parallelloadenable === 1'b1) ? 1'b1 : 1'b0; // ploaden
initial begin
// does not get reset so whatever power-up values
shift_reg = 'b0;
output_reg = 'b0;
end
always @(posedge shift_clk) shift_reg <= {shift_reg[26:0], terminationdata};
always @(posedge pload_clk) output_reg <= shift_reg;
endmodule
| 7.896739 |
module stratixiv_tsdblock (
offset,
clk,
ce,
clr,
testin,
tsdcalo,
tsdcaldone,
fdbkctrlfromcore,
compouttest,
tsdcompout,
offsetout
);
input [5:0] offset;
input [7:0] testin;
input clk;
input ce;
input clr;
input fdbkctrlfromcore;
input compouttest;
output [7:0] tsdcalo;
output tsdcaldone;
output tsdcompout;
output [5:0] offsetout;
parameter poi_cal_temperature = 85;
parameter clock_divider_enable = "on";
parameter clock_divider_value = 40;
parameter sim_tsdcalo = 0;
parameter user_offset_enable = "off";
parameter lpm_type = "stratixiv_tsdblock";
endmodule
| 7.11642 |
module stratixiv_lvds_rx_fifo_sync_ram (
clk,
datain,
write_reset,
waddr,
raddr,
we,
dataout
);
// INPUT PORTS
input clk;
input write_reset;
input datain;
input [2:0] waddr;
input [2:0] raddr;
input we;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES AND NETS
reg dataout_tmp;
reg [0:5] ram_d;
reg [0:5] ram_q;
wire [0:5] data_reg;
integer i;
initial begin
dataout_tmp = 0;
for (i = 0; i <= 5; i = i + 1) ram_q[i] <= 1'b0;
end
// Write port
always @(posedge clk or posedge write_reset) begin
if (write_reset == 1'b1) begin
for (i = 0; i <= 5; i = i + 1) ram_q[i] <= 1'b0;
end else begin
for (i = 0; i <= 5; i = i + 1) ram_q[i] <= ram_d[i];
end
end
always @(we or data_reg or ram_q) begin
if (we === 1'b1) begin
ram_d <= data_reg;
end else begin
ram_d <= ram_q;
end
end
// Read port
assign data_reg[0] = (waddr == 3'b000) ? datain : ram_q[0];
assign data_reg[1] = (waddr == 3'b001) ? datain : ram_q[1];
assign data_reg[2] = (waddr == 3'b010) ? datain : ram_q[2];
assign data_reg[3] = (waddr == 3'b011) ? datain : ram_q[3];
assign data_reg[4] = (waddr == 3'b100) ? datain : ram_q[4];
assign data_reg[5] = (waddr == 3'b101) ? datain : ram_q[5];
always @(ram_q or we or waddr or raddr) begin
case (raddr)
3'b000: dataout_tmp = ram_q[0];
3'b001: dataout_tmp = ram_q[1];
3'b010: dataout_tmp = ram_q[2];
3'b011: dataout_tmp = ram_q[3];
3'b100: dataout_tmp = ram_q[4];
3'b101: dataout_tmp = ram_q[5];
default: dataout_tmp = 0;
endcase
end
// set output
assign dataout = dataout_tmp;
endmodule
| 6.833933 |
module stratixiv_lvds_rx_fifo (
wclk,
rclk,
dparst,
fiforst,
datain,
dataout
);
parameter channel_width = 10;
// INPUT PORTS
input wclk;
input rclk;
input dparst;
input fiforst;
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES AND NETS
reg dataout_tmp;
wire data_out;
integer i;
reg ram_datain;
wire ram_dataout;
reg [2:0] wrPtr, rdPtr; // writer pointer, read pointer
wire [2:0] rdAddr; // read address
reg ram_we;
reg wclk_last_value, rclk_last_value;
reg write_side_sync_reset;
reg read_side_sync_reset;
specify
(posedge rclk => (dataout +: data_out)) = (0, 0);
(posedge dparst => (dataout +: data_out)) = (0, 0);
endspecify
initial begin
dataout_tmp = 0;
wrPtr = 2'b00;
rdPtr = 2'b11;
write_side_sync_reset = 1'b0;
read_side_sync_reset = 1'b0;
end
assign rdAddr = rdPtr;
stratixiv_lvds_rx_fifo_sync_ram s_fifo_ram (
.clk(wclk),
.datain(ram_datain),
.write_reset(write_side_sync_reset),
.waddr(wrPtr),
.raddr(rdAddr), // rdPtr ??
.we(ram_we),
.dataout(ram_dataout)
);
// update pointer and RAM input
always @(wclk or dparst) begin
if (dparst === 1'b1 || (fiforst === 1'b1 && wclk === 1'b1 && wclk_last_value === 1'b0)) begin
write_side_sync_reset <= 1'b1;
ram_datain <= 1'b0;
wrPtr <= 0;
ram_we <= 'b0;
end
else if (dparst === 1'b0 && (fiforst === 1'b0 && wclk === 1'b1 && wclk_last_value === 1'b0))
begin
write_side_sync_reset <= 1'b0;
end
if (wclk === 1'b1 && wclk_last_value === 1'b0 && write_side_sync_reset === 1'b0 && fiforst === 1'b0 && dparst === 1'b0)
begin
ram_datain <= datain; // input register
ram_we <= 'b1;
wrPtr <= wrPtr + 1;
if (wrPtr == 5) wrPtr <= 0;
end
wclk_last_value = wclk;
end
always @(rclk or dparst) begin
if (dparst === 1'b1 || (fiforst === 1'b1 && rclk === 1'b1 && rclk_last_value === 1'b0)) begin
read_side_sync_reset <= 1'b1;
rdPtr <= 3;
dataout_tmp <= 0;
end
else if (dparst === 1'b0 && (fiforst === 1'b0 && rclk === 1'b1 && rclk_last_value === 1'b0))
begin
read_side_sync_reset <= 0;
end
if (rclk === 1'b1 && rclk_last_value === 1'b0 && read_side_sync_reset === 1'b0 && fiforst === 1'b0 && dparst === 1'b0)
begin
rdPtr <= rdPtr + 1;
if (rdPtr == 5) rdPtr <= 0;
dataout_tmp <= ram_dataout; // output register
end
rclk_last_value = rclk;
end
assign data_out = dataout_tmp;
buf (dataout, data_out);
endmodule
| 6.833933 |
module receives serial data and outputs
// parallel data word of width = channel_width
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratixiv_lvds_rx_deser (
clk,
datain,
devclrn,
devpor,
dataout
);
parameter channel_width = 10;
// INPUT PORTS
input clk;
input datain;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] dataout;
// INTERNAL VARIABLES AND NETS
reg [channel_width - 1:0] dataout_tmp;
reg clk_last_value;
integer i;
specify
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
endspecify
initial
begin
clk_last_value = 0;
dataout_tmp = 'b0;
end
always @(clk or devclrn or devpor)
begin
if (devclrn === 1'b0 || devpor === 1'b0)
begin
dataout_tmp <= 'b0;
end
else if (clk === 1'b1 && clk_last_value === 1'b0)
begin
for (i = (channel_width-1); i > 0; i=i-1)
dataout_tmp[i] <= dataout_tmp[i-1];
dataout_tmp[0] <= datain;
end
clk_last_value <= clk;
end
assign dataout = dataout_tmp;
endmodule
| 6.910834 |
module stratixiv_lvds_rx_parallel_reg (
clk,
enable,
datain,
dataout,
devclrn,
devpor
);
parameter channel_width = 10;
// INPUT PORTS
input [channel_width - 1:0] datain;
input clk;
input enable;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] dataout;
// INTERNAL VARIABLES AND NETS
reg clk_last_value;
reg [channel_width - 1:0] dataout_tmp;
specify
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
endspecify
initial begin
clk_last_value = 0;
dataout_tmp = 'b0;
end
always @(clk or devpor or devclrn) begin
if ((devpor === 1'b0) || (devclrn === 1'b0)) begin
dataout_tmp <= 'b0;
end else begin
if ((clk === 1) && (clk_last_value !== clk)) begin
if (enable === 1) begin
dataout_tmp <= datain;
end
end
end
clk_last_value <= clk;
end //always
assign dataout = dataout_tmp;
endmodule
| 6.833933 |
module stratixiv_lvds_reg (
q,
clk,
ena,
d,
clrn,
prn
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q_tmp;
wire q_wire;
// TIMING PATHS
specify
(posedge clk => (q +: q_tmp)) = (0, 0);
(negedge clrn => (q +: q_tmp)) = (0, 0);
(negedge prn => (q +: q_tmp)) = (0, 0);
endspecify
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q_tmp = 0;
always @(posedge clk or negedge clrn or negedge prn) begin
if (prn == 1'b0) q_tmp <= 1;
else if (clrn == 1'b0) q_tmp <= 0;
else if ((clk == 1) & (ena == 1'b1)) q_tmp <= d;
end
assign q_wire = q_tmp;
and (q, q_wire, 1'b1);
endmodule
| 6.833933 |
module stratixiv_pclk_divider (
clkin,
lloaden,
clkout
);
parameter clk_divide_by = 1;
input clkin;
output lloaden;
output clkout;
reg clkout_tmp;
reg [4:0] cnt;
reg start;
reg count;
reg lloaden_tmp;
assign clkout = (clk_divide_by == 1) ? clkin : clkout_tmp;
assign lloaden = lloaden_tmp;
initial begin
clkout_tmp = 1'b0;
cnt = 5'b00000;
start = 1'b0;
count = 1'b0;
lloaden_tmp = 1'b0;
end
always @(clkin) begin
if (clkin == 1'b1) begin
count = 1'b1;
end
if (count == 1'b1) begin
if (cnt < clk_divide_by) begin
clkout_tmp = 1'b0;
cnt = cnt + 1'b1;
end else begin
if (cnt == 2 * clk_divide_by - 1) cnt = 0;
else begin
clkout_tmp = 1'b1;
cnt = cnt + 1;
end
end
end
end
always @(clkin or cnt) begin
if (cnt == 2 * clk_divide_by - 2) lloaden_tmp = 1'b1;
else if (cnt == 0) lloaden_tmp = 1'b0;
end
endmodule
| 6.57717 |
module stratixiv_select_ini_phase_dpaclk (
clkin,
loaden,
enable,
clkout,
loadenout
);
parameter initial_phase_select = 0;
input clkin;
input enable;
input loaden;
output clkout;
output loadenout;
wire clkout_tmp;
wire loadenout_tmp;
real clk_period, last_clk_period;
real last_clkin_edge;
reg first_clkin_edge_detect;
reg clk0_tmp;
reg clk1_tmp;
reg clk2_tmp;
reg clk3_tmp;
reg clk4_tmp;
reg clk5_tmp;
reg clk6_tmp;
reg clk7_tmp;
reg loaden0_tmp;
reg loaden1_tmp;
reg loaden2_tmp;
reg loaden3_tmp;
reg loaden4_tmp;
reg loaden5_tmp;
reg loaden6_tmp;
reg loaden7_tmp;
assign clkout_tmp = (initial_phase_select == 1) ? clk1_tmp :
(initial_phase_select == 2) ? clk2_tmp :
(initial_phase_select == 3) ? clk3_tmp :
(initial_phase_select == 4) ? clk4_tmp :
(initial_phase_select == 5) ? clk5_tmp :
(initial_phase_select == 6) ? clk6_tmp :
(initial_phase_select == 7) ? clk7_tmp :
clk0_tmp;
assign loadenout_tmp = (initial_phase_select == 1) ? loaden1_tmp :
(initial_phase_select == 2) ? loaden2_tmp :
(initial_phase_select == 3) ? loaden3_tmp :
(initial_phase_select == 4) ? loaden4_tmp :
(initial_phase_select == 5) ? loaden5_tmp :
(initial_phase_select == 6) ? loaden6_tmp :
(initial_phase_select == 7) ? loaden7_tmp :
loaden0_tmp;
assign clkout = (enable == 1'b1) ? clkout_tmp : clkin;
assign loadenout = (enable == 1'b1) ? loadenout_tmp : loaden;
initial begin
first_clkin_edge_detect = 1'b0;
end
always @(posedge clkin) begin
// Determine the clock frequency
if (first_clkin_edge_detect == 1'b0) begin
first_clkin_edge_detect = 1'b1;
end else begin
last_clk_period = clk_period;
clk_period = $realtime - last_clkin_edge;
end
last_clkin_edge = $realtime;
end
//assign phase shifted clock and data values
always @(clkin) begin
clk0_tmp <= clkin;
clk1_tmp <= #(clk_period * 0.125) clkin;
clk2_tmp <= #(clk_period * 0.25) clkin;
clk3_tmp <= #(clk_period * 0.375) clkin;
clk4_tmp <= #(clk_period * 0.5) clkin;
clk5_tmp <= #(clk_period * 0.625) clkin;
clk6_tmp <= #(clk_period * 0.75) clkin;
clk7_tmp <= #(clk_period * 0.875) clkin;
end
always @(loaden) begin
loaden0_tmp <= loaden;
loaden1_tmp <= #(clk_period * 0.125) loaden;
loaden2_tmp <= #(clk_period * 0.25) loaden;
loaden3_tmp <= #(clk_period * 0.375) loaden;
loaden4_tmp <= #(clk_period * 0.5) loaden;
loaden5_tmp <= #(clk_period * 0.625) loaden;
loaden6_tmp <= #(clk_period * 0.75) loaden;
loaden7_tmp <= #(clk_period * 0.875) loaden;
end
endmodule
| 6.518733 |
module stratixiv_pseudo_diff_out (
i,
o,
obar
);
parameter lpm_type = "stratixiv_pseudo_diff_out";
input i;
output o;
output obar;
reg o_tmp;
reg obar_tmp;
assign o = o_tmp;
assign obar = obar_tmp;
always @(i) begin
if (i == 1'b1) begin
o_tmp = 1'b1;
obar_tmp = 1'b0;
end else if (i == 1'b0) begin
o_tmp = 1'b0;
obar_tmp = 1'b1;
end else begin
o_tmp = i;
obar_tmp = i;
end
end
endmodule
| 7.018754 |
module stratixiv_bias_logic (
clk,
shiftnld,
captnupdt,
mainclk,
updateclk,
capture,
update
);
// INPUT PORTS
input clk;
input shiftnld;
input captnupdt;
// OUTPUTPUT PORTS
output mainclk;
output updateclk;
output capture;
output update;
// INTERNAL VARIABLES
reg mainclk_tmp;
reg updateclk_tmp;
reg capture_tmp;
reg update_tmp;
initial begin
mainclk_tmp <= 'b0;
updateclk_tmp <= 'b0;
capture_tmp <= 'b0;
update_tmp <= 'b0;
end
always @(captnupdt or shiftnld or clk) begin
case ({
captnupdt, shiftnld
})
2'b10, 2'b11: begin
mainclk_tmp <= 'b0;
updateclk_tmp <= clk;
capture_tmp <= 'b1;
update_tmp <= 'b0;
end
2'b01: begin
mainclk_tmp <= 'b0;
updateclk_tmp <= clk;
capture_tmp <= 'b0;
update_tmp <= 'b0;
end
2'b00: begin
mainclk_tmp <= clk;
updateclk_tmp <= 'b0;
capture_tmp <= 'b0;
update_tmp <= 'b1;
end
default: begin
mainclk_tmp <= 'b0;
updateclk_tmp <= 'b0;
capture_tmp <= 'b0;
update_tmp <= 'b0;
end
endcase
end
and (mainclk, mainclk_tmp, 1'b1);
and (updateclk, updateclk_tmp, 1'b1);
and (capture, capture_tmp, 1'b1);
and (update, update_tmp, 1'b1);
endmodule
| 8.658732 |
module stratixiv_bias_generator (
din,
mainclk,
updateclk,
capture,
update,
dout
);
// INPUT PORTS
input din;
input mainclk;
input updateclk;
input capture;
input update;
// OUTPUTPUT PORTS
output dout;
parameter TOTAL_REG = 202;
// INTERNAL VARIABLES
reg dout_tmp;
reg generator_reg[TOTAL_REG - 1:0];
reg update_reg[TOTAL_REG - 1:0];
integer i;
initial begin
dout_tmp <= 'b0;
for (i = 0; i < TOTAL_REG; i = i + 1) begin
generator_reg[i] <= 'b0;
update_reg[i] <= 'b0;
end
end
// main generator registers
always @(posedge mainclk) begin
if ((capture == 'b0) && (update == 'b1)) //update main registers
begin
for (i = 0; i < TOTAL_REG; i = i + 1) begin
generator_reg[i] <= update_reg[i];
end
end
end
// update registers
always @(posedge updateclk) begin
dout_tmp <= update_reg[TOTAL_REG-1];
if ((capture == 'b0) && (update == 'b0)) //shift update registers
begin
for (i = (TOTAL_REG - 1); i > 0; i = i - 1) begin
update_reg[i] <= update_reg[i-1];
end
update_reg[0] <= din;
end
else if ((capture == 'b1) && (update == 'b0)) //load update registers
begin
for (i = 0; i < TOTAL_REG; i = i + 1) begin
update_reg[i] <= generator_reg[i];
end
end
end
and (dout, dout_tmp, 1'b1);
endmodule
| 8.658732 |
module stratixiv_bias_block (
clk,
shiftnld,
captnupdt,
din,
dout
);
// INPUT PORTS
input clk;
input shiftnld;
input captnupdt;
input din;
// OUTPUTPUT PORTS
output dout;
parameter lpm_type = "stratixiv_bias_block";
// INTERNAL VARIABLES
reg din_viol;
reg shiftnld_viol;
reg captnupdt_viol;
wire mainclk_wire;
wire updateclk_wire;
wire capture_wire;
wire update_wire;
wire dout_tmp;
specify
$setuphold(posedge clk, din, 0, 0, din_viol);
$setuphold(posedge clk, shiftnld, 0, 0, shiftnld_viol);
$setuphold(posedge clk, captnupdt, 0, 0, captnupdt_viol);
(posedge clk => (dout +: dout_tmp)) = 0;
endspecify
stratixiv_bias_logic logic_block (
.clk(clk),
.shiftnld(shiftnld),
.captnupdt(captnupdt),
.mainclk(mainclk_wire),
.updateclk(updateclk_wire),
.capture(capture_wire),
.update(update_wire)
);
stratixiv_bias_generator bias_generator (
.din(din),
.mainclk(mainclk_wire),
.updateclk(updateclk_wire),
.capture(capture_wire),
.update(update_wire),
.dout(dout_tmp)
);
and (dout, dout_tmp, 1'b1);
endmodule
| 8.658732 |
module stratixiv_pciehip_dprio_bit (
reset,
clk,
sig_in,
ext_in,
serial_mode,
si,
shift,
mdio_dis,
sig_out,
so
);
input reset; // reset
input clk; // clock
input sig_in; // signal input
input ext_in; // external input port
input serial_mode; // serial shift mode enable
input si; // scan input
input shift; // 1'b1=shift in data from si into scan flop
// 1'b0=load data from sig_in into scan flop
input mdio_dis; // 1'b1=choose ext_in to the sig_out mux
// 1'b0=choose so to the sign_out mux
output sig_out; // signal output
output so; // scan output
wire sig_out;
wire cram_int;
wire set_int;
reg so;
// select signal output
assign sig_out = (serial_mode) ? (so & ~shift) : (cram_int);
assign cram_int = (mdio_dis) ? (ext_in) : (so);
// Set signal for the flop
assign set_int = (shift | reset) ? 1'b0 : ext_in;
// scan flop
always @(posedge reset or posedge set_int or posedge clk)
if (reset) so <= 1'b0;
else if (set_int) so <= 1'b1;
else if (shift && serial_mode) so <= si;
else so <= sig_in;
endmodule
| 6.746782 |
module stratixiv_pciehip_compute_bit (
input wire [63:0] datain,
input wire s,
output wire r
);
// begin
assign r = datain[0] ^ datain[1] ^ datain[2] ^ datain[3] ^ datain[4] ^ datain[5] ^ datain[6] ^ datain[7] ^ datain[10] ^ datain[13] ^ datain[14] ^ datain[17] ^
datain[20] ^ datain[23] ^ datain[24] ^ datain[27] ^ datain[35] ^ datain[43] ^ datain[46] ^ datain[47] ^ datain[51] ^ datain[52] ^ datain[53] ^
datain[56] ^ datain[57] ^ datain[58] ^ s;
// end
endmodule
| 6.746782 |
module stratixiv_pciehip_ecc_gen (
input wire [63:0] datain, // Data on which ECC is required
input wire [ 7:0] syndrome, // Syndrome uses 8'h00 while generating
output wire [ 7:0] result // Result
);
//-----------------------------------------------------------------------------
// Instantiate Result Compute block for 8 bits
//-----------------------------------------------------------------------------
stratixiv_pciehip_compute_bit cb_0 (
.datain(datain),
.s (syndrome[0]),
.r (result[0])
);
stratixiv_pciehip_compute_bit cb_1 (
.datain({datain[7:0], datain[63:8]}),
.s(syndrome[1]),
.r(result[1])
);
stratixiv_pciehip_compute_bit cb_2 (
.datain({datain[15:0], datain[63:16]}),
.s(syndrome[2]),
.r(result[2])
);
stratixiv_pciehip_compute_bit cb_3 (
.datain({datain[23:0], datain[63:24]}),
.s(syndrome[3]),
.r(result[3])
);
stratixiv_pciehip_compute_bit cb_4 (
.datain({datain[31:0], datain[63:32]}),
.s(syndrome[4]),
.r(result[4])
);
stratixiv_pciehip_compute_bit cb_5 (
.datain({datain[39:0], datain[63:40]}),
.s(syndrome[5]),
.r(result[5])
);
stratixiv_pciehip_compute_bit cb_6 (
.datain({datain[47:0], datain[63:48]}),
.s(syndrome[6]),
.r(result[6])
);
stratixiv_pciehip_compute_bit cb_7 (
.datain({datain[55:0], datain[63:56]}),
.s(syndrome[7]),
.r(result[7])
);
endmodule
| 6.746782 |
module stratixiv_pciehip_ecc_decoder (
flag,
derr,
derr_cor
);
input [2:0] flag;
output derr;
output derr_cor;
assign derr = flag[2] & ~(flag[1]) & flag[0];
assign derr_cor = ~(flag[2]) & flag[1] & flag[0];
endmodule
| 6.746782 |
module stratixiv_pciehip_pulse_ext (
core_clk,
rstn,
srst,
derr_cor,
derr_cor_ext
);
input core_clk;
input rstn;
input srst;
input derr_cor;
output derr_cor_ext;
reg n1, derr_cor_ext;
wire n2;
// Pulse width extender
always @(negedge rstn or posedge core_clk) begin
if (rstn == 1'b0) begin
n1 <= 1'b0;
end else begin
if (srst == 1'b1) begin
n1 <= 1'b0;
end else begin
n1 <= derr_cor;
end
end
end
assign n2 = n1 | derr_cor;
always @(negedge rstn or posedge core_clk) begin
if (rstn == 1'b0) begin
derr_cor_ext <= 1'b0;
end else begin
if (srst == 1'b1) begin
derr_cor_ext <= 1'b0;
end else begin
derr_cor_ext <= n2;
end
end
end
endmodule
| 6.746782 |
module stratixiv_pciehip_pciexp_dcfiforam (
data,
wren,
wraddress,
rdaddress,
wrclock,
rdclock,
q
);
parameter addr_width = 4;
parameter data_width = 32;
input [data_width - 1:0] data;
input wren;
input [addr_width - 1:0] wraddress;
input [addr_width - 1:0] rdaddress;
input wrclock;
input rdclock;
output [data_width - 1:0] q;
wire [data_width - 1:0] q;
reg [data_width - 1:0] ram_block[0:2 ** addr_width - 1];
reg [addr_width - 1:0] rdaddr_r;
reg [addr_width - 1:0] wraddr_r;
reg wren_r;
reg [data_width - 1:0] wrdata_r;
// Write process
always @(posedge wrclock) begin
wren_r <= wren;
wraddr_r <= wraddress;
wrdata_r <= data;
if (wren_r == 1'b1) begin
ram_block[wraddr_r] <= wrdata_r;
end
end
// Read process
always @(posedge rdclock) begin
rdaddr_r <= rdaddress;
end
assign q = ram_block[rdaddr_r];
endmodule
| 6.746782 |
module stratixiv_pciehip_pciexp_dcram_rtry (
wrclock,
wren,
wraddress,
data,
rdclock,
rdaddress,
q
);
parameter addr_width = 'd4;
parameter data_width = 'd32;
input wrclock;
input wren;
input [data_width - 1:0] data;
input [addr_width - 1:0] wraddress;
input rdclock;
input [addr_width - 1:0] rdaddress;
output [data_width - 1:0] q;
wire [data_width - 1:0] q;
// -------------------------------------------------------------
reg [data_width - 1:0] ram_block [(1<<addr_width)-1:0];
reg [addr_width - 1:0] read_addr_r;
reg [addr_width - 1:0] wraddr_r;
reg wren_r;
reg [data_width - 1:0] wrdata_r;
// Write process
always @(posedge wrclock) begin : process_1
wren_r <= wren;
wraddr_r <= wraddress;
wrdata_r <= data;
if (wren_r == 1'b1) begin
ram_block[wraddr_r] <= wrdata_r;
end
end
// Read process
always @(posedge rdclock) begin : process_3
read_addr_r <= rdaddress;
end
assign q = ram_block[read_addr_r];
endmodule
| 6.746782 |
module stratixiv_pciehip_pciexp_dcram_rxvc (
wrclock,
wren,
wraddress,
data,
rdclock,
rdaddress,
q
);
parameter addr_width = 'd4;
parameter data_width = 'd32;
input wrclock;
input wren;
input [data_width - 1:0] data;
input [addr_width - 1:0] wraddress;
input rdclock;
input [addr_width - 1:0] rdaddress;
output [data_width - 1:0] q;
wire [data_width - 1:0] q;
// -------------------------------------------------------------
reg [data_width - 1:0] ram_block [(1<<addr_width)-1:0];
reg [addr_width - 1:0] read_addr_r;
reg [addr_width - 1:0] wraddr_r;
reg wren_r;
reg [data_width - 1:0] wrdata_r;
// Write process
always @(posedge wrclock) begin : process_1
wren_r <= wren;
wraddr_r <= wraddress;
wrdata_r <= data;
if (wren_r == 1'b1) begin
ram_block[wraddr_r] <= wrdata_r;
end
end
// Read process
always @(posedge rdclock) begin : process_3
read_addr_r <= rdaddress;
end
assign q = ram_block[read_addr_r];
endmodule
| 6.746782 |
module stratixv_mux21 (
MO,
A,
B,
S
);
input A, B, S;
output MO;
wire A_in;
wire B_in;
wire S_in;
buf (A_in, A);
buf (B_in, B);
buf (S_in, S);
wire tmp_MO;
specify
(A => MO) = (0, 0);
(B => MO) = (0, 0);
(S => MO) = (0, 0);
endspecify
assign tmp_MO = (S_in == 1) ? B_in : A_in;
buf (MO, tmp_MO);
endmodule
| 7.318794 |
module stratixv_mux41 (
MO,
IN0,
IN1,
IN2,
IN3,
S
);
input IN0;
input IN1;
input IN2;
input IN3;
input [1:0] S;
output MO;
wire IN0_in;
wire IN1_in;
wire IN2_in;
wire IN3_in;
wire S1_in;
wire S0_in;
buf (IN0_in, IN0);
buf (IN1_in, IN1);
buf (IN2_in, IN2);
buf (IN3_in, IN3);
buf (S1_in, S[1]);
buf (S0_in, S[0]);
wire tmp_MO;
specify
(IN0 => MO) = (0, 0);
(IN1 => MO) = (0, 0);
(IN2 => MO) = (0, 0);
(IN3 => MO) = (0, 0);
(S[1] => MO) = (0, 0);
(S[0] => MO) = (0, 0);
endspecify
assign tmp_MO = S1_in ? (S0_in ? IN3_in : IN2_in) : (S0_in ? IN1_in : IN0_in);
buf (MO, tmp_MO);
endmodule
| 6.565991 |
module stratixv_bmux21 (
MO,
A,
B,
S
);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.815707 |
module stratixv_b17mux21 (
MO,
A,
B,
S
);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.98582 |
module stratixv_nmux21 (
MO,
A,
B,
S
);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
| 7.531254 |
module stratixv_b5mux21 (
MO,
A,
B,
S
);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 8.107113 |
module stratixv_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0);
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule
| 7.435925 |
module
//--------------------------------------------------------------------------
// Deactivate the following LEDA rules for stratixv_mlab_cell_block.v
// G_521_3B: Use uppercase letters for all parameter names
// leda G_521_3_B off
`timescale 1 ps/1 ps
module stratixv_mlab_cell
(
portadatain,
portaaddr,
portabyteenamasks,
portbaddr,
clk0, clk1,
ena0, ena1,
ena2,
clr,
devclrn,
devpor,
portbdataout
);
// -------- GLOBAL PARAMETERS ---------
parameter logical_ram_name = "lutram";
parameter logical_ram_depth = 0;
parameter logical_ram_width = 0;
parameter first_address = 0;
parameter last_address = 0;
parameter first_bit_number = 0;
parameter mixed_port_feed_through_mode = "new";
parameter init_file = "NONE";
parameter data_width = 20;
parameter address_width = 6;
parameter byte_enable_mask_width = 1;
parameter byte_size = 1;
parameter port_b_data_out_clock = "none";
parameter port_b_data_out_clear = "none";
parameter lpm_type = "stratixv_mlab_cell";
parameter lpm_hint = "true";
parameter mem_init0 = "";
// -------- PORT DECLARATIONS ---------
input [data_width - 1:0] portadatain;
input [address_width - 1:0] portaaddr;
input [byte_enable_mask_width - 1:0] portabyteenamasks;
input [address_width - 1:0] portbaddr;
input clk0;
input clk1;
input ena0;
input ena1;
input ena2;
input clr;
input devclrn;
input devpor;
output [data_width - 1:0] portbdataout;
generic_28nm_hp_mlab_cell_impl my_lutram0
(
.portadatain(portadatain),
.portaaddr(portaaddr),
.portabyteenamasks(portabyteenamasks),
.portbaddr(portbaddr),
.clk0(clk0),
.clk1(clk1),
.ena0(ena0),
.ena1(ena1),
.ena2(ena2),
.clr(clr),
.devclrn(devclrn),
.devpor(devpor),
.portbdataout(portbdataout)
);
defparam my_lutram0.logical_ram_name = logical_ram_name;
defparam my_lutram0.logical_ram_depth = logical_ram_depth;
defparam my_lutram0.logical_ram_width = logical_ram_width;
defparam my_lutram0.first_address = first_address;
defparam my_lutram0.last_address = last_address;
defparam my_lutram0.first_bit_number = first_bit_number;
defparam my_lutram0.mixed_port_feed_through_mode = mixed_port_feed_through_mode;
defparam my_lutram0.init_file = init_file;
defparam my_lutram0.data_width = data_width;
defparam my_lutram0.address_width = address_width;
defparam my_lutram0.byte_enable_mask_width = byte_enable_mask_width;
defparam my_lutram0.byte_size = byte_size;
defparam my_lutram0.port_b_data_out_clock = port_b_data_out_clock;
defparam my_lutram0.port_b_data_out_clear = port_b_data_out_clear;
defparam my_lutram0.lpm_type = lpm_type;
defparam my_lutram0.lpm_hint = lpm_hint;
defparam my_lutram0.mem_init0 = mem_init0;
endmodule
| 8.13663 |
module stratixv_io_ibuf (
i,
ibar,
dynamicterminationcontrol,
o
);
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter differential_mode = "false";
parameter bus_hold = "false";
parameter simulate_z_as = "Z";
parameter lpm_type = "stratixv_io_ibuf";
// SIMULATION_ONLY_PARAMETERS_END
//Input Ports Declaration
input i;
input ibar;
input dynamicterminationcontrol;
//Output Ports Declaration
output o;
// Internal signals
reg out_tmp;
reg o_tmp;
wire out_val;
reg prev_value;
specify
(i => o) = (0, 0);
(ibar => o) = (0, 0);
endspecify
initial begin
prev_value = 1'b0;
end
always @(i or ibar) begin
if (differential_mode == "false") begin
if (i == 1'b1) begin
o_tmp = 1'b1;
prev_value = 1'b1;
end else if (i == 1'b0) begin
o_tmp = 1'b0;
prev_value = 1'b0;
end else if (i === 1'bz) o_tmp = out_val;
else o_tmp = i;
if (bus_hold == "true") out_tmp = prev_value;
else out_tmp = o_tmp;
end else begin
case ({
i, ibar
})
2'b00: out_tmp = 1'bX;
2'b01: out_tmp = 1'b0;
2'b10: out_tmp = 1'b1;
2'b11: out_tmp = 1'bX;
default: out_tmp = 1'bX;
endcase
end
end
assign out_val = (simulate_z_as == "Z") ? 1'bz :
(simulate_z_as == "X") ? 1'bx :
(simulate_z_as == "vcc")? 1'b1 :
(simulate_z_as == "gnd") ? 1'b0 : 1'bz;
pmos (o, out_tmp, 1'b0);
endmodule
| 6.938491 |
module stratixv_io_obuf (
i,
oe,
dynamicterminationcontrol,
seriesterminationcontrol,
parallelterminationcontrol,
devoe,
o,
obar
);
//Parameter Declaration
parameter open_drain_output = "false";
parameter bus_hold = "false";
parameter shift_series_termination_control = "false";
parameter sim_dynamic_termination_control_is_connected = "false";
parameter lpm_type = "stratixv_io_obuf";
//Input Ports Declaration
input i;
input oe;
input devoe;
input dynamicterminationcontrol;
input [15:0] seriesterminationcontrol;
input [15:0] parallelterminationcontrol;
//Outout Ports Declaration
output o;
output obar;
//INTERNAL Signals
reg out_tmp;
reg out_tmp_bar;
reg prev_value;
wire tmp;
wire tmp_bar;
wire tmp1;
wire tmp1_bar;
tri1 devoe;
tri1 oe;
specify
(i => o) = (0, 0);
(i => obar) = (0, 0);
(oe => o) = (0, 0);
(oe => obar) = (0, 0);
endspecify
initial begin
prev_value = 'b0;
out_tmp = 'bz;
end
always @(i or oe) begin
if (oe == 1'b1) begin
if (open_drain_output == "true") begin
if (i == 'b0) begin
out_tmp = 'b0;
out_tmp_bar = 'b1;
prev_value = 'b0;
end else begin
out_tmp = 'bz;
out_tmp_bar = 'bz;
end
end else begin
if (i == 'b0) begin
out_tmp = 'b0;
out_tmp_bar = 'b1;
prev_value = 'b0;
end else if (i == 'b1) begin
out_tmp = 'b1;
out_tmp_bar = 'b0;
prev_value = 'b1;
end else begin
out_tmp = i;
out_tmp_bar = i;
end
end
end else if (oe == 1'b0) begin
out_tmp = 'bz;
out_tmp_bar = 'bz;
end else begin
out_tmp = 'bx;
out_tmp_bar = 'bx;
end
end
assign tmp = (bus_hold == "true") ? prev_value : out_tmp;
assign tmp_bar = (bus_hold == "true") ? !prev_value : out_tmp_bar;
assign tmp1 = ((oe == 1'b1) && (dynamicterminationcontrol == 1'b1) && (sim_dynamic_termination_control_is_connected == "true")) ? 1'bx :(devoe == 1'b1) ? tmp : 1'bz;
assign tmp1_bar =((oe == 1'b1) && (dynamicterminationcontrol == 1'b1)&& (sim_dynamic_termination_control_is_connected == "true")) ? 1'bx : (devoe == 1'b1) ? tmp_bar : 1'bz;
pmos (o, tmp1, 1'b0);
pmos (obar, tmp1_bar, 1'b0);
endmodule
| 7.861686 |
module stratixv_pseudo_diff_out (
i,
o,
obar,
// ports new for StratixV
dtcin,
dtc,
dtcbar,
oein,
oeout,
oebout
);
parameter lpm_type = "stratixv_pseudo_diff_out";
input i;
output o;
output obar;
// ports new for StratixV
input dtcin, oein;
output dtc, dtcbar, oeout, oebout;
reg o_tmp;
reg obar_tmp;
reg dtc_tmp, dtcbar_tmp, oeout_tmp, oebout_tmp;
assign dtc = dtcin;
assign dtcbar = dtcin;
assign oeout = oein;
assign oebout = oein;
assign o = o_tmp;
assign obar = obar_tmp;
always @(i) begin
if (i == 1'b1) begin
o_tmp = 1'b1;
obar_tmp = 1'b0;
end else if (i == 1'b0) begin
o_tmp = 1'b0;
obar_tmp = 1'b1;
end else begin
o_tmp = i;
obar_tmp = i;
end
end // always@ (i)
endmodule
| 7.528855 |
module stratixv_bias_logic (
clk,
shiftnld,
captnupdt,
mainclk,
updateclk,
capture,
update
);
// INPUT PORTS
input clk;
input shiftnld;
input captnupdt;
// OUTPUTPUT PORTS
output mainclk;
output updateclk;
output capture;
output update;
// INTERNAL VARIABLES
reg mainclk_tmp;
reg updateclk_tmp;
reg capture_tmp;
reg update_tmp;
initial begin
mainclk_tmp <= 'b0;
updateclk_tmp <= 'b0;
capture_tmp <= 'b0;
update_tmp <= 'b0;
end
always @(captnupdt or shiftnld or clk) begin
case ({
captnupdt, shiftnld
})
2'b10, 2'b11: begin
mainclk_tmp <= 'b0;
updateclk_tmp <= clk;
capture_tmp <= 'b1;
update_tmp <= 'b0;
end
2'b01: begin
mainclk_tmp <= 'b0;
updateclk_tmp <= clk;
capture_tmp <= 'b0;
update_tmp <= 'b0;
end
2'b00: begin
mainclk_tmp <= clk;
updateclk_tmp <= 'b0;
capture_tmp <= 'b0;
update_tmp <= 'b1;
end
default: begin
mainclk_tmp <= 'b0;
updateclk_tmp <= 'b0;
capture_tmp <= 'b0;
update_tmp <= 'b0;
end
endcase
end
and (mainclk, mainclk_tmp, 1'b1);
and (updateclk, updateclk_tmp, 1'b1);
and (capture, capture_tmp, 1'b1);
and (update, update_tmp, 1'b1);
endmodule
| 8.535763 |
module stratixv_bias_generator (
din,
mainclk,
updateclk,
capture,
update,
dout
);
// INPUT PORTS
input din;
input mainclk;
input updateclk;
input capture;
input update;
// OUTPUTPUT PORTS
output dout;
parameter TOTAL_REG = 202;
// INTERNAL VARIABLES
reg dout_tmp;
reg generator_reg[TOTAL_REG - 1:0];
reg update_reg[TOTAL_REG - 1:0];
integer i;
initial begin
dout_tmp <= 'b0;
for (i = 0; i < TOTAL_REG; i = i + 1) begin
generator_reg[i] <= 'b0;
update_reg[i] <= 'b0;
end
end
// main generator registers
always @(posedge mainclk) begin
if ((capture == 'b0) && (update == 'b1)) //update main registers
begin
for (i = 0; i < TOTAL_REG; i = i + 1) begin
generator_reg[i] <= update_reg[i];
end
end
end
// update registers
always @(posedge updateclk) begin
dout_tmp <= update_reg[TOTAL_REG-1];
if ((capture == 'b0) && (update == 'b0)) //shift update registers
begin
for (i = (TOTAL_REG - 1); i > 0; i = i - 1) begin
update_reg[i] <= update_reg[i-1];
end
update_reg[0] <= din;
end
else if ((capture == 'b1) && (update == 'b0)) //load update registers
begin
for (i = 0; i < TOTAL_REG; i = i + 1) begin
update_reg[i] <= generator_reg[i];
end
end
end
and (dout, dout_tmp, 1'b1);
endmodule
| 8.535763 |
module stratixv_bias_block (
clk,
shiftnld,
captnupdt,
din,
dout
);
// INPUT PORTS
input clk;
input shiftnld;
input captnupdt;
input din;
// OUTPUTPUT PORTS
output dout;
parameter lpm_type = "stratixv_bias_block";
// INTERNAL VARIABLES
reg din_viol;
reg shiftnld_viol;
reg captnupdt_viol;
wire mainclk_wire;
wire updateclk_wire;
wire capture_wire;
wire update_wire;
wire dout_tmp;
specify
$setuphold(posedge clk, din, 0, 0, din_viol);
$setuphold(posedge clk, shiftnld, 0, 0, shiftnld_viol);
$setuphold(posedge clk, captnupdt, 0, 0, captnupdt_viol);
(posedge clk => (dout +: dout_tmp)) = 0;
endspecify
stratixv_bias_logic logic_block (
.clk(clk),
.shiftnld(shiftnld),
.captnupdt(captnupdt),
.mainclk(mainclk_wire),
.updateclk(updateclk_wire),
.capture(capture_wire),
.update(update_wire)
);
stratixv_bias_generator bias_generator (
.din(din),
.mainclk(mainclk_wire),
.updateclk(updateclk_wire),
.capture(capture_wire),
.update(update_wire),
.dout(dout_tmp)
);
and (dout, dout_tmp, 1'b1);
endmodule
| 8.535763 |
module stratixv_dll_offset_ctrl (
clk,
offsetdelayctrlin,
offset,
addnsub,
aload,
offsetctrlout,
offsettestout
);
parameter use_offset = "false";
parameter static_offset = 0;
parameter use_pvt_compensation = "false";
input clk;
input [6:0] offsetdelayctrlin;
input [6:0] offset;
input addnsub;
input aload;
output [6:0] offsetctrlout;
output [6:0] offsettestout;
stratixv_dll_offset_ctrl_encrypted inst (
.clk(clk),
.offsetdelayctrlin(offsetdelayctrlin),
.offset(offset),
.addnsub(addnsub),
.aload(aload),
.offsetctrlout(offsetctrlout),
.offsettestout(offsettestout)
);
defparam inst.use_offset = use_offset; defparam inst.static_offset = static_offset;
defparam inst.use_pvt_compensation = use_pvt_compensation;
endmodule
| 6.951401 |
module stratixv_dll (
aload,
clk,
upndnin,
upndninclkena,
delayctrlout,
dqsupdate,
offsetdelayctrlout,
offsetdelayctrlclkout,
upndnout,
dffin,
locked);
parameter input_frequency = "0 MHz";
parameter delayctrlout_mode = "normal";
parameter jitter_reduction = "false";
parameter use_upndnin = "false";
parameter use_upndninclkena = "false";
parameter dual_phase_comparators = "true";
parameter sim_valid_lock = 16;
parameter sim_valid_lockcount = 0;
parameter sim_buffer_intrinsic_delay = 175;
parameter sim_buffer_delay_increment = 10;
parameter static_delay_ctrl = 0;
parameter lpm_type = "stratixv_dll";
parameter lpm_hint = "unused";
parameter delay_chain_length = 8;
input aload;
input clk;
input upndnin;
input upndninclkena;
output [6:0] delayctrlout;
output dqsupdate;
output [6:0] offsetdelayctrlout;
output offsetdelayctrlclkout;
output upndnout;
output dffin;
output locked;
stratixv_dll_encrypted inst (
.aload(aload),
.clk(clk),
.upndnin(upndnin),
.upndninclkena(upndninclkena),
.delayctrlout(delayctrlout),
.dqsupdate(dqsupdate),
.offsetdelayctrlout(offsetdelayctrlout),
.offsetdelayctrlclkout(offsetdelayctrlclkout),
.upndnout(upndnout),
.dffin(dffin),
.locked(locked));
defparam inst.input_frequency = input_frequency;
defparam inst.delayctrlout_mode = delayctrlout_mode;
defparam inst.jitter_reduction = jitter_reduction;
defparam inst.use_upndnin = use_upndnin;
defparam inst.use_upndninclkena = use_upndninclkena;
defparam inst.dual_phase_comparators = dual_phase_comparators;
defparam inst.sim_valid_lock = sim_valid_lock;
defparam inst.sim_valid_lockcount = sim_valid_lockcount;
defparam inst.sim_buffer_intrinsic_delay = sim_buffer_intrinsic_delay;
defparam inst.sim_buffer_delay_increment = sim_buffer_delay_increment;
defparam inst.static_delay_ctrl = static_delay_ctrl;
defparam inst.lpm_type = lpm_type;
defparam inst.lpm_hint = lpm_hint;
defparam inst.delay_chain_length = delay_chain_length;
endmodule
| 7.461178 |
module stratixv_dqs_delay_chain (
dqsin,
dqsenable,
dqsdisablen,
delayctrlin,
offsetctrlin,
dqsupdateen,
phasectrlin,
testin,
dffin,
dqsbusout);
parameter dqs_period = "unused";
parameter dqs_input_frequency = "unused";
parameter dqs_phase_shift = 0;
parameter use_phasectrlin = "false";
parameter phase_setting = 0;
parameter dqs_offsetctrl_enable = "false";
parameter dqs_ctrl_latches_enable = "false";
parameter use_alternate_input_for_first_stage_delayctrl = "false";
parameter sim_buffer_intrinsic_delay = 175;
parameter sim_buffer_delay_increment = 10;
parameter test_enable = "false";
input dqsin;
input dqsenable;
input [6:0] delayctrlin;
input [6:0] offsetctrlin;
input dqsupdateen;
input [1:0] phasectrlin;
input testin;
input dqsdisablen;
output dffin;
output dqsbusout;
stratixv_dqs_delay_chain_encrypted inst (
.dqsin(dqsin),
.dqsenable(dqsenable),
.delayctrlin(delayctrlin),
.offsetctrlin(offsetctrlin),
.dqsupdateen(dqsupdateen),
.phasectrlin(phasectrlin),
.testin(testin),
.dqsdisablen(dqsdisablen),
.dffin(dffin),
.dqsbusout(dqsbusout) );
defparam inst.dqs_period = dqs_period;
defparam inst.dqs_input_frequency = dqs_input_frequency;
defparam inst.dqs_phase_shift = dqs_phase_shift;
defparam inst.use_phasectrlin = use_phasectrlin;
defparam inst.phase_setting = phase_setting;
defparam inst.dqs_offsetctrl_enable = dqs_offsetctrl_enable;
defparam inst.dqs_ctrl_latches_enable = dqs_ctrl_latches_enable;
defparam inst.use_alternate_input_for_first_stage_delayctrl = use_alternate_input_for_first_stage_delayctrl;
defparam inst.sim_buffer_intrinsic_delay = sim_buffer_intrinsic_delay;
defparam inst.sim_buffer_delay_increment = sim_buffer_delay_increment;
defparam inst.test_enable = test_enable;
endmodule
| 7.461178 |
module stratixv_pll_dll_output #(
// parameter declaration and default value assignemnt
parameter pll_dll_src = "vss" //Valid values: c_0_cnt|c_1_cnt|c_2_cnt|c_3_cnt|c_4_cnt|c_5_cnt|c_6_cnt|c_7_cnt|c_8_cnt|c_9_cnt|c_10_cnt|c_11_cnt|c_12_cnt|c_13_cnt|c_14_cnt|c_15_cnt|c_16_cnt|c_17_cnt|clkin_0|clkin_1|clkin_2|clkin_3|vss
) (
//input and output port declaration
input [17:0] cclk,
input [ 3:0] clkin,
output [ 0:0] clkout
);
stratixv_pll_dll_output_encrypted #(
.pll_dll_src(pll_dll_src)
) stratixv_pll_dll_output_encrypted_inst (
.cclk (cclk),
.clkin (clkin),
.clkout(clkout)
);
endmodule
| 7.867696 |
module stratixv_pll_dpa_output #(
// parameter declaration and default value assignemnt
parameter output_clock_frequency = "", //Valid values:
parameter pll_vcoph_div = 1 //Valid values: 1|2|4
) (
//input and output port declaration
input [0:0] pd,
input [7:0] phin,
output [7:0] phout
);
stratixv_pll_dpa_output_encrypted #(
.output_clock_frequency(output_clock_frequency),
.pll_vcoph_div(pll_vcoph_div)
) stratixv_pll_dpa_output_encrypted_inst (
.pd(pd),
.phin(phin),
.phout(phout)
);
endmodule
| 7.867696 |
module stratixv_pll_extclk_output #(
// parameter declaration and default value assignemnt
parameter pll_extclk_cnt_src = "vss", //Valid values: c_0_cnt|c_1_cnt|c_2_cnt|c_3_cnt|c_4_cnt|c_5_cnt|c_6_cnt|c_7_cnt|c_8_cnt|c_9_cnt|c_10_cnt|c_11_cnt|c_12_cnt|c_13_cnt|c_14_cnt|c_15_cnt|c_16_cnt|c_17_cnt|m0_cnt|m1_cnt|clkin0|clkin1|clkin2|clkin3|vss
parameter pll_extclk_enable = "true", //Valid values: false|true
parameter pll_extclk_invert = "false" //Valid values: false|true
) (
//input and output port declaration
input [17:0] cclk,
input [ 0:0] clken,
input [ 0:0] mcnt0,
input [ 0:0] mcnt1,
output [ 0:0] extclk
);
stratixv_pll_extclk_output_encrypted #(
.pll_extclk_cnt_src(pll_extclk_cnt_src),
.pll_extclk_enable (pll_extclk_enable),
.pll_extclk_invert (pll_extclk_invert)
) stratixv_pll_extclk_output_encrypted_inst (
.cclk (cclk),
.clken (clken),
.mcnt0 (mcnt0),
.mcnt1 (mcnt1),
.extclk(extclk)
);
endmodule
| 7.867696 |
module stratixv_pll_lvds_output #(
// parameter declaration and default value assignemnt
parameter pll_loaden_coarse_dly = "0 ps", //Valid values: 0 ps|200 ps|400 ps|600 ps|800 ps|1000 ps
parameter pll_loaden_enable_disable = "false", //Valid values: false|true
parameter pll_loaden_fine_dly = "0 ps", //Valid values: 0 ps|50 ps|100 ps|150 ps
parameter pll_lvdsclk_coarse_dly = "0 ps", //Valid values: 0 ps|200 ps|400 ps|600 ps|800 ps|1000 ps
parameter pll_lvdsclk_enable_disable = "false", //Valid values: false|true
parameter pll_lvdsclk_fine_dly = "0 ps" //Valid values: 0 ps|50 ps|100 ps|150 ps
) (
//input and output port declaration
input [1:0] ccout,
output [0:0] loaden,
output [0:0] lvdsclk
);
stratixv_pll_lvds_output_encrypted #(
.pll_loaden_coarse_dly(pll_loaden_coarse_dly),
.pll_loaden_enable_disable(pll_loaden_enable_disable),
.pll_loaden_fine_dly(pll_loaden_fine_dly),
.pll_lvdsclk_coarse_dly(pll_lvdsclk_coarse_dly),
.pll_lvdsclk_enable_disable(pll_lvdsclk_enable_disable),
.pll_lvdsclk_fine_dly(pll_lvdsclk_fine_dly)
) stratixv_pll_lvds_output_encrypted_inst (
.ccout (ccout),
.loaden (loaden),
.lvdsclk(lvdsclk)
);
endmodule
| 7.867696 |
module stratixv_pll_output_counter #(
// parameter declaration and default value assignemnt
parameter output_clock_frequency = "", //Valid values:
parameter phase_shift = "", //Valid values:
parameter duty_cycle = 50, //Valid values: 1..99
parameter c_cnt_coarse_dly = "0 ps", //Valid values: 0 ps|200 ps|400 ps|600 ps|800 ps|1000 ps
parameter c_cnt_fine_dly = "0 ps", //Valid values: 0 ps|50 ps|100 ps|150 ps
parameter c_cnt_in_src = "test_clk0", //Valid values: ph_mux_clk|cscd_clk|test_clk0|test_clk1
parameter c_cnt_ph_mux_prst = 0, //Valid values: 0..7
parameter c_cnt_prst = 1, //Valid values: 1..256
parameter cnt_fpll_src = "fpll_0", //Valid values: fpll_0|fpll_1
parameter dprio0_cnt_bypass_en = "false", //Valid values: false|true
parameter dprio0_cnt_hi_div = 1, //Valid values: 1..256
parameter dprio0_cnt_lo_div = 1, //Valid values: 1..256
parameter dprio0_cnt_odd_div_even_duty_en = "false", //Valid values: false|true
parameter dprio1_cnt_bypass_en = "false", //Valid values: false|true
parameter dprio1_cnt_hi_div = 1, //Valid values: 1..256
parameter dprio1_cnt_lo_div = 1, //Valid values: 1..256
parameter dprio1_cnt_odd_div_even_duty_en = "false", //Valid values: false|true
parameter fractional_pll_index = 1, //Valid values:
parameter output_counter_index = 0 //Valid values:
) (
//input and output port declaration
input [0:0] cascadein,
input [0:0] nen0,
input [0:0] nen1,
input [0:0] shift0,
input [0:0] shift1,
input [0:0] shiftdone0i,
input [0:0] shiftdone1i,
input [0:0] shiften,
input [0:0] tclk0,
input [0:0] tclk1,
input [0:0] up0,
input [0:0] up1,
input [7:0] vco0ph,
input [7:0] vco1ph,
output [0:0] cascadeout,
output [0:0] divclk,
output [0:0] shiftdone0o,
output [0:0] shiftdone1o
);
stratixv_pll_output_counter_encrypted #(
.output_clock_frequency(output_clock_frequency),
.phase_shift(phase_shift),
.duty_cycle(duty_cycle),
.c_cnt_coarse_dly(c_cnt_coarse_dly),
.c_cnt_fine_dly(c_cnt_fine_dly),
.c_cnt_in_src(c_cnt_in_src),
.c_cnt_ph_mux_prst(c_cnt_ph_mux_prst),
.c_cnt_prst(c_cnt_prst),
.cnt_fpll_src(cnt_fpll_src),
.dprio0_cnt_bypass_en(dprio0_cnt_bypass_en),
.dprio0_cnt_hi_div(dprio0_cnt_hi_div),
.dprio0_cnt_lo_div(dprio0_cnt_lo_div),
.dprio0_cnt_odd_div_even_duty_en(dprio0_cnt_odd_div_even_duty_en),
.dprio1_cnt_bypass_en(dprio1_cnt_bypass_en),
.dprio1_cnt_hi_div(dprio1_cnt_hi_div),
.dprio1_cnt_lo_div(dprio1_cnt_lo_div),
.dprio1_cnt_odd_div_even_duty_en(dprio1_cnt_odd_div_even_duty_en),
.fractional_pll_index(fractional_pll_index),
.output_counter_index(output_counter_index)
) stratixv_pll_output_counter_encrypted_inst (
.cascadein(cascadein),
.nen0(nen0),
.nen1(nen1),
.shift0(shift0),
.shift1(shift1),
.shiftdone0i(shiftdone0i),
.shiftdone1i(shiftdone1i),
.shiften(shiften),
.tclk0(tclk0),
.tclk1(tclk1),
.up0(up0),
.up1(up1),
.vco0ph(vco0ph),
.vco1ph(vco1ph),
.cascadeout(cascadeout),
.divclk(divclk),
.shiftdone0o(shiftdone0o),
.shiftdone1o(shiftdone1o)
);
endmodule
| 7.867696 |
module stratixv_pll_reconfig #(
// Parameter declarations and default value assignments
parameter fractional_pll_index = 1 //Valid values:
) (
//input and output port declaration
input [ 5:0] addr,
input [ 0:0] atpgmode,
input [ 1:0] byteen,
input [ 0:0] clk,
input [ 0:0] cntnen,
input [ 4:0] cntsel,
input [ 15:0] din,
input [ 0:0] fpllcsrtest,
input [ 0:0] iocsrclkin,
input [ 0:0] iocsrdatain,
input [ 0:0] iocsren,
input [ 0:0] iocsrrstn,
input [ 0:0] mdiodis,
input [ 7:0] mhi,
input [ 0:0] phaseen,
input [ 0:0] read,
input [ 0:0] rstn,
input [ 0:0] scanen,
input [ 0:0] sershiftload,
input [ 0:0] shiftdonei,
input [ 0:0] updn,
input [ 0:0] write,
output [ 0:0] blockselect,
output [ 15:0] dout,
output [815:0] dprioout,
output [ 0:0] iocsrdataout,
output [ 0:0] iocsrenbuf,
output [ 0:0] iocsrrstnbuf,
output [ 0:0] phasedone,
output [ 0:0] shift,
output [ 17:0] shiften,
output [ 0:0] shiftenm,
output [ 0:0] up
);
stratixv_pll_reconfig_encrypted #(
.fractional_pll_index(fractional_pll_index)
) stratixv_pll_reconfig_encrypted_inst (
.addr(addr),
.atpgmode(atpgmode),
.byteen(byteen),
.clk(clk),
.cntnen(cntnen),
.cntsel(cntsel),
.din(din),
.fpllcsrtest(fpllcsrtest),
.iocsrclkin(iocsrclkin),
.iocsrdatain(iocsrdatain),
.iocsren(iocsren),
.iocsrrstn(iocsrrstn),
.mdiodis(mdiodis),
.phaseen(phaseen),
.read(read),
.rstn(rstn),
.scanen(scanen),
.sershiftload(sershiftload),
.shiftdonei(shiftdonei),
.updn(updn),
.write(write),
.blockselect(blockselect),
.dout(dout),
.dprioout(dprioout),
.iocsrdataout(iocsrdataout),
.iocsrenbuf(iocsrenbuf),
.iocsrrstnbuf(iocsrrstnbuf),
.phasedone(phasedone),
.shift(shift),
.shiften(shiften),
.shiftenm(shiftenm),
.up(up)
);
endmodule
| 7.867696 |
module stratixv_pll_refclk_select #(
// parameter declaration and default value assignemnt
parameter pll_auto_clk_sw_en = "false", //Valid values: false|true
parameter pll_clk_loss_edge = "both_edges", //Valid values: both_edges|rising_edge
parameter pll_clk_loss_sw_en = "false", //Valid values: false|true
parameter pll_clk_sw_dly = 0, //Valid values: 0..7
parameter pll_clkin_0_src = "ref_clk0", //Valid values: core_ref_clk|adj_pll_clk|ref_clk0|ref_clk1|clk_0|clk_1|clk_2|clk_3|vss|cmu_iqclk|iqtxrxclk|fpll|pll_iqclk
parameter pll_clkin_1_src = "ref_clk1", //Valid values: core_ref_clk|adj_pll_clk|ref_clk0|ref_clk1|clk_0|clk_1|clk_2|clk_3|vss|cmu_iqclk|iqtxrxclk|fpll|pll_iqclk
parameter pll_manu_clk_sw_en = "false", //Valid values: false|true
parameter pll_sw_refclk_src = "clk_0" //Valid values: clk_0|clk_1
) (
//input and output port declaration
input [0:0] adjpllin,
input [0:0] cclk,
input [3:0] clkin,
input [0:0] coreclkin,
input [0:0] extswitch,
input [0:0] iqtxrxclkin,
input [0:0] plliqclkin,
input [1:0] refiqclk,
input [0:0] rxiqclkin,
output [0:0] clk0bad,
output [0:0] clk1bad,
output [0:0] clkout,
output [0:0] extswitchbuf,
output [0:0] pllclksel
);
stratixv_pll_refclk_select_encrypted #(
.pll_auto_clk_sw_en(pll_auto_clk_sw_en),
.pll_clk_loss_edge(pll_clk_loss_edge),
.pll_clk_loss_sw_en(pll_clk_loss_sw_en),
.pll_clk_sw_dly(pll_clk_sw_dly),
.pll_clkin_0_src(pll_clkin_0_src),
.pll_clkin_1_src(pll_clkin_1_src),
.pll_manu_clk_sw_en(pll_manu_clk_sw_en),
.pll_sw_refclk_src(pll_sw_refclk_src)
) stratixv_pll_refclk_select_encrypted_inst (
.adjpllin(adjpllin),
.cclk(cclk),
.clkin(clkin),
.coreclkin(coreclkin),
.extswitch(extswitch),
.iqtxrxclkin(iqtxrxclkin),
.plliqclkin(plliqclkin),
.refiqclk(refiqclk),
.rxiqclkin(rxiqclkin),
.clk0bad(clk0bad),
.clk1bad(clk1bad),
.clkout(clkout),
.extswitchbuf(extswitchbuf),
.pllclksel(pllclksel)
);
endmodule
| 7.867696 |
module stratixv_input_phase_alignment (
datain,
levelingclk,
zerophaseclk,
areset,
enainputcycledelay,
enaphasetransferreg,
dataout,
dffin,
dff1t,
dffphasetransfer
);
parameter power_up = "low";
parameter async_mode = "no_reset";
parameter add_input_cycle_delay = "false";
parameter bypass_output_register = "false";
parameter add_phase_transfer_reg = "false";
parameter lpm_type = "stratixv_input_phase_alignment";
input datain;
input levelingclk;
input zerophaseclk;
input areset;
input enainputcycledelay;
input enaphasetransferreg;
output dataout;
output dffin;
output dff1t;
output dffphasetransfer;
stratixv_input_phase_alignment_encrypted inst (
.datain(datain),
.levelingclk(levelingclk),
.zerophaseclk(zerophaseclk),
.areset(areset),
.enainputcycledelay(enainputcycledelay),
.enaphasetransferreg(enaphasetransferreg),
.dataout(dataout),
.dffin(dffin),
.dff1t(dff1t),
.dffphasetransfer(dffphasetransfer)
);
defparam inst.power_up = power_up; defparam inst.async_mode = async_mode;
defparam inst.add_input_cycle_delay = add_input_cycle_delay;
defparam inst.bypass_output_register = bypass_output_register;
defparam inst.add_phase_transfer_reg = add_phase_transfer_reg;
defparam inst.lpm_type = lpm_type;
endmodule
| 7.14137 |
module stratixv_lvds_rx (
clock0,
datain,
enable0,
dpareset,
dpahold,
dpaswitch,
fiforeset,
bitslip,
bitslipreset,
serialfbk,
devclrn,
devpor,
dpaclkin,
dataout,
dpalock,
bitslipmax,
serialdataout,
postdpaserialdataout,
divfwdclk,
dpaclkout,
observableout);
parameter data_align_rollover = 2;
parameter enable_dpa = "false";
parameter lose_lock_on_one_change = "false";
parameter reset_fifo_at_first_lock = "true";
parameter align_to_rising_edge_only = "true";
parameter use_serial_feedback_input = "off";
parameter dpa_debug = "false";
parameter x_on_bitslip = "true";
parameter enable_soft_cdr = "false";
parameter dpa_clock_output_phase_shift = 0;
parameter enable_dpa_initial_phase_selection = "false";
parameter dpa_initial_phase_value = 0;
parameter enable_dpa_align_to_rising_edge_only = "false";
parameter net_ppm_variation = 0;
parameter is_negative_ppm_drift = "false";
parameter rx_input_path_delay_engineering_bits = 2;
parameter enable_clock_pin_mode = "false";
parameter lpm_type = "stratixv_lvds_rx";
parameter data_width = 10;
parameter dpa_config = 0;
input clock0;
input datain;
input enable0;
input dpareset;
input dpahold;
input dpaswitch;
input fiforeset;
input bitslip;
input bitslipreset;
input serialfbk;
input devclrn;
input devpor;
input [7:0] dpaclkin;
output [data_width-1:0] dataout;
output dpalock;
output bitslipmax;
output serialdataout;
output postdpaserialdataout;
output divfwdclk;
output dpaclkout;
output [3:0] observableout;
stratixv_lvds_rx_encrypted inst (
.clock0(clock0),
.datain(datain),
.enable0(enable0),
.dpareset(dpareset),
.dpahold(dpahold),
.dpaswitch(dpaswitch),
.fiforeset(fiforeset),
.bitslip(bitslip),
.bitslipreset(bitslipreset),
.serialfbk(serialfbk),
.devclrn(devclrn),
.devpor(devpor),
.dpaclkin(dpaclkin),
.dataout(dataout),
.dpalock(dpalock),
.bitslipmax(bitslipmax),
.serialdataout(serialdataout),
.postdpaserialdataout(postdpaserialdataout),
.divfwdclk(divfwdclk),
.dpaclkout(dpaclkout),
.observableout(observableout) );
defparam inst.data_align_rollover = data_align_rollover;
defparam inst.enable_dpa = enable_dpa;
defparam inst.lose_lock_on_one_change = lose_lock_on_one_change;
defparam inst.reset_fifo_at_first_lock = reset_fifo_at_first_lock;
defparam inst.align_to_rising_edge_only = align_to_rising_edge_only;
defparam inst.use_serial_feedback_input = use_serial_feedback_input;
defparam inst.dpa_debug = dpa_debug;
defparam inst.x_on_bitslip = x_on_bitslip;
defparam inst.enable_soft_cdr = enable_soft_cdr;
defparam inst.dpa_clock_output_phase_shift = dpa_clock_output_phase_shift;
defparam inst.enable_dpa_initial_phase_selection = enable_dpa_initial_phase_selection;
defparam inst.dpa_initial_phase_value = dpa_initial_phase_value;
defparam inst.enable_dpa_align_to_rising_edge_only = enable_dpa_align_to_rising_edge_only;
defparam inst.net_ppm_variation = net_ppm_variation;
defparam inst.is_negative_ppm_drift = is_negative_ppm_drift;
defparam inst.rx_input_path_delay_engineering_bits = rx_input_path_delay_engineering_bits;
defparam inst.enable_clock_pin_mode = enable_clock_pin_mode;
defparam inst.lpm_type = lpm_type;
defparam inst.data_width = data_width;
defparam inst.dpa_config = dpa_config;
endmodule
| 6.728198 |
module stratixv_lvds_tx (
datain,
clock0,
enable0,
serialdatain,
postdpaserialdatain,
devclrn,
devpor,
dpaclkin,
dataout,
serialfdbkout,
observableout
);
parameter bypass_serializer = "false";
parameter invert_clock = "false";
parameter use_falling_clock_edge = "false";
parameter use_serial_data_input = "false";
parameter use_post_dpa_serial_data_input = "false";
parameter is_used_as_outclk = "false";
parameter tx_output_path_delay_engineering_bits = -1;
parameter enable_dpaclk_to_lvdsout = "false";
parameter enable_clock_pin_mode = "false";
parameter lpm_type = "stratixv_lvds_tx";
parameter data_width = 10;
input [data_width-1:0] datain;
input clock0;
input enable0;
input serialdatain;
input postdpaserialdatain;
input devclrn;
input devpor;
input dpaclkin;
output dataout;
output serialfdbkout;
output [2:0] observableout;
stratixv_lvds_tx_encrypted inst (
.datain(datain),
.clock0(clock0),
.enable0(enable0),
.serialdatain(serialdatain),
.postdpaserialdatain(postdpaserialdatain),
.devclrn(devclrn),
.devpor(devpor),
.dpaclkin(dpaclkin),
.dataout(dataout),
.serialfdbkout(serialfdbkout),
.observableout(observableout)
);
defparam inst.bypass_serializer = bypass_serializer; defparam inst.invert_clock = invert_clock;
defparam inst.use_falling_clock_edge = use_falling_clock_edge;
defparam inst.use_serial_data_input = use_serial_data_input;
defparam inst.use_post_dpa_serial_data_input = use_post_dpa_serial_data_input;
defparam inst.is_used_as_outclk = is_used_as_outclk;
defparam inst.tx_output_path_delay_engineering_bits = tx_output_path_delay_engineering_bits;
defparam inst.enable_dpaclk_to_lvdsout = enable_dpaclk_to_lvdsout;
defparam inst.enable_clock_pin_mode = enable_clock_pin_mode;
defparam inst.lpm_type = lpm_type; defparam inst.data_width = data_width;
endmodule
| 7.058885 |
module stratixv_output_alignment (
datain,
clk,
areset,
sreset,
enaoutputcycledelay,
enaphasetransferreg,
dataout,
dffin,
dff1t,
dff2t,
dffphasetransfer
);
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter add_output_cycle_delay = "false";
parameter add_phase_transfer_reg = "false";
input datain;
input clk;
input areset;
input sreset;
input [2:0] enaoutputcycledelay;
input enaphasetransferreg;
output dataout;
output dffin;
output dff1t;
output dff2t;
output dffphasetransfer;
stratixv_output_alignment_encrypted inst (
.datain(datain),
.clk(clk),
.areset(areset),
.sreset(sreset),
.enaoutputcycledelay(enaoutputcycledelay),
.enaphasetransferreg(enaphasetransferreg),
.dataout(dataout),
.dffin(dffin),
.dff1t(dff1t),
.dff2t(dff2t),
.dffphasetransfer(dffphasetransfer)
);
defparam inst.power_up = power_up;
defparam inst.async_mode = async_mode; defparam inst.sync_mode = sync_mode;
defparam inst.add_output_cycle_delay = add_output_cycle_delay;
defparam inst.add_phase_transfer_reg = add_phase_transfer_reg;
endmodule
| 6.796769 |
module stratixv_termination_logic (
s2pload,
serdata,
scanenable,
scanclk,
enser,
seriesterminationcontrol,
parallelterminationcontrol
);
parameter lpm_type = "stratixv_termination_logic";
parameter a_iob_oct_test = "a_iob_oct_test_off";
input s2pload;
input serdata;
input scanenable;
input scanclk;
input enser;
output [15 : 0] parallelterminationcontrol;
output [15 : 0] seriesterminationcontrol;
stratixv_termination_logic_encrypted inst (
.s2pload(s2pload),
.serdata(serdata),
.scanenable(scanenable),
.scanclk(scanclk),
.enser(enser),
.seriesterminationcontrol(seriesterminationcontrol),
.parallelterminationcontrol(parallelterminationcontrol)
);
defparam inst.lpm_type = lpm_type; defparam inst.a_iob_oct_test = a_iob_oct_test;
endmodule
| 7.179578 |
module stratixv_tsdblock (
clk,
ce,
clr,
tsdcalo,
tsdcaldone
);
parameter clock_divider_enable = "on";
parameter clock_divider_value = 40;
parameter sim_tsdcalo = 0;
parameter poi_cal_temperature = 85;
parameter tsdblock_mode = "corner_sense";
parameter use_dft_compout = "false";
parameter lpm_type = "stratixv_tsdblock";
input clk;
input ce;
input clr;
output [7:0] tsdcalo;
output tsdcaldone;
stratixv_tsdblock_encrypted inst (
.clk(clk),
.ce(ce),
.clr(clr),
.tsdcalo(tsdcalo),
.tsdcaldone(tsdcaldone)
);
defparam inst.clock_divider_enable = clock_divider_enable;
defparam inst.clock_divider_value = clock_divider_value;
defparam inst.sim_tsdcalo = sim_tsdcalo; defparam inst.poi_cal_temperature = 85;
defparam inst.tsdblock_mode = "corner_sense"; defparam inst.use_dft_compout = "false";
defparam inst.lpm_type = lpm_type;
endmodule
| 7.046072 |
module stratixv_hssi_pma_aux #(
parameter silicon_rev = "reve", // Valid values: reve|es
// // parameter declaration and default value assignemnt
parameter enable_debug_info = "false", //Valid values: false|true; this is simulation-only parameter, for debug purpose only
parameter continuous_calibration = "false", //Valid values: false|true
parameter rx_cal_override_value_enable = "false", //Valid values: false|true
parameter rx_cal_override_value = 0, //Valid values: 0..31
parameter tx_cal_override_value_enable = "false", //Valid values: false|true
parameter tx_cal_override_value = 0, //Valid values: 0..31
parameter cal_result_status = "pm_aux_result_status_tx", //Valid values: pm_aux_result_status_tx|pm_aux_result_status_rx
parameter rx_imp = "cal_imp_46_ohm", //Valid values: cal_imp_46_ohm|cal_imp_48_ohm|cal_imp_50_ohm|cal_imp_52_ohm
parameter tx_imp = "cal_imp_46_ohm", //Valid values: cal_imp_46_ohm|cal_imp_48_ohm|cal_imp_50_ohm|cal_imp_52_ohm
parameter test_counter_enable = "false", //Valid values: false|true
parameter cal_clk_sel = "pm_aux_iqclk_cal_clk_sel_cal_clk", //Valid values: pm_aux_iqclk_cal_clk_sel_cal_clk|pm_aux_iqclk_cal_clk_sel_iqclk0|pm_aux_iqclk_cal_clk_sel_iqclk1|pm_aux_iqclk_cal_clk_sel_iqclk2|pm_aux_iqclk_cal_clk_sel_iqclk3|pm_aux_iqclk_cal_clk_sel_iqclk4|pm_aux_iqclk_cal_clk_sel_iqclk5|pm_aux_iqclk_cal_clk_sel_iqclk6|pm_aux_iqclk_cal_clk_sel_iqclk7|pm_aux_iqclk_cal_clk_sel_iqclk8|pm_aux_iqclk_cal_clk_sel_iqclk9|pm_aux_iqclk_cal_clk_sel_iqclk10
parameter pm_aux_cal_clk_test_sel = 1'b0, //Valid values: 1
parameter avmm_group_channel_index = 0, //Valid values: 0..2
parameter use_default_base_address = "true", //Valid values: false|true
parameter user_base_address = 0 //Valid values: 0..2047
) (
//input and output port declaration
input [ 0:0] calpdb,
input [ 0:0] calclk,
input [ 0:0] testcntl,
input [10:0] refiqclk,
output [ 0:0] nonusertoio,
output [ 4:0] zrxtx50
);
stratixv_hssi_pma_aux_encrypted #(
.enable_debug_info(enable_debug_info),
.continuous_calibration(continuous_calibration),
.rx_cal_override_value_enable(rx_cal_override_value_enable),
.rx_cal_override_value(rx_cal_override_value),
.tx_cal_override_value_enable(tx_cal_override_value_enable),
.tx_cal_override_value(tx_cal_override_value),
.cal_result_status(cal_result_status),
.rx_imp(rx_imp),
.tx_imp(tx_imp),
.test_counter_enable(test_counter_enable),
.cal_clk_sel(cal_clk_sel),
.pm_aux_cal_clk_test_sel(pm_aux_cal_clk_test_sel),
.avmm_group_channel_index(avmm_group_channel_index),
.use_default_base_address(use_default_base_address),
.user_base_address(user_base_address)
) stratixv_hssi_pma_aux_encrypted_inst (
.calpdb(calpdb),
.calclk(calclk),
.testcntl(testcntl),
.refiqclk(refiqclk),
.nonusertoio(nonusertoio),
.zrxtx50(zrxtx50)
);
endmodule
| 7.134348 |
module stratixv_hssi_avmm_interface #(
parameter num_ch0_atoms = 0,
parameter num_ch1_atoms = 0,
parameter num_ch2_atoms = 0
) (
//input and output port declaration
input [ 0:0] avmmrstn,
input [ 0:0] avmmclk,
input [ 0:0] avmmwrite,
input [ 0:0] avmmread,
input [ 1:0] avmmbyteen,
input [ 10:0] avmmaddress,
input [ 15:0] avmmwritedata,
input [ 89:0] blockselect,
input [1439:0] readdatachnl,
output [15:0] avmmreaddata,
output [ 0:0] clkchnl,
output [ 0:0] rstnchnl,
output [15:0] writedatachnl,
output [10:0] regaddrchnl,
output [ 0:0] writechnl,
output [ 0:0] readchnl,
output [ 1:0] byteenchnl,
//The following ports are not modelled. They exist to match the avmm interface atom interface
input [0:0] refclkdig,
input [0:0] avmmreservedin,
output [0:0] avmmreservedout,
output [0:0] dpriorstntop,
output [0:0] dprioclktop,
output [0:0] mdiodistopchnl,
output [0:0] dpriorstnmid,
output [0:0] dprioclkmid,
output [0:0] mdiodismidchnl,
output [0:0] dpriorstnbot,
output [0:0] dprioclkbot,
output [0:0] mdiodisbotchnl,
output [3:0] dpriotestsitopchnl,
output [3:0] dpriotestsimidchnl,
output [3:0] dpriotestsibotchnl,
//The following ports belong to pm_adce and pm_tst_mux blocks in the PMA
input [11:0] pmatestbussel,
output [23:0] pmatestbus,
//
input [0:0] scanmoden,
input [0:0] scanshiftn,
input [0:0] interfacesel,
input [0:0] sershiftload
);
stratixv_hssi_avmm_interface_encrypted #(
.num_ch0_atoms(num_ch0_atoms),
.num_ch1_atoms(num_ch1_atoms),
.num_ch2_atoms(num_ch2_atoms)
) stratixv_hssi_avmm_interface_encrypted_inst (
.avmmrstn (avmmrstn),
.avmmclk (avmmclk),
.avmmwrite (avmmwrite),
.avmmread (avmmread),
.avmmbyteen (avmmbyteen),
.avmmaddress (avmmaddress),
.avmmwritedata (avmmwritedata),
.blockselect (blockselect),
.readdatachnl (readdatachnl),
.avmmreaddata (avmmreaddata),
.clkchnl (clkchnl),
.rstnchnl (rstnchnl),
.writedatachnl (writedatachnl),
.regaddrchnl (regaddrchnl),
.writechnl (writechnl),
.readchnl (readchnl),
.byteenchnl (byteenchnl),
.refclkdig (refclkdig),
.avmmreservedin (avmmreservedin),
.avmmreservedout (avmmreservedout),
.dpriorstntop (dpriorstntop),
.dprioclktop (dprioclktop),
.mdiodistopchnl (mdiodistopchnl),
.dpriorstnmid (dpriorstnmid),
.dprioclkmid (dprioclkmid),
.mdiodismidchnl (mdiodismidchnl),
.dpriorstnbot (dpriorstnbot),
.dprioclkbot (dprioclkbot),
.mdiodisbotchnl (mdiodisbotchnl),
.dpriotestsitopchnl(dpriotestsitopchnl),
.dpriotestsimidchnl(dpriotestsimidchnl),
.dpriotestsibotchnl(dpriotestsibotchnl),
.pmatestbus (pmatestbus),
.pmatestbussel (pmatestbussel),
.scanmoden (scanmoden),
.scanshiftn (scanshiftn),
.interfacesel (interfacesel),
.sershiftload (sershiftload)
);
endmodule
| 7.134348 |
module stratixv_hssi_aux_clock_div (
clk, // input clock
reset, // reset
enable_d, // enable DPRIO
d, // division factor for DPRIO support
clkout // divided clock
);
input clk, reset;
input enable_d;
input [7:0] d;
output clkout;
parameter clk_divide_by = 1;
parameter extra_latency = 0;
integer clk_edges, m;
reg [2*extra_latency:0] div_n_register;
reg [7:0] d_factor_dly;
reg [31:0] clk_divide_value;
wire [7:0] d_factor;
wire int_reset;
initial begin
div_n_register = 'b0;
clk_edges = -1;
m = 0;
d_factor_dly = 'b0;
clk_divide_value = clk_divide_by;
end
assign d_factor = (enable_d === 1'b1) ? d : clk_divide_value[7:0];
always @(d_factor) begin
d_factor_dly <= d_factor;
end
// create a reset pulse when there is a change in the d_factor value
assign int_reset = (d_factor !== d_factor_dly) ? 1'b1 : 1'b0;
always @(posedge clk or negedge clk or posedge reset or posedge int_reset) begin
div_n_register <= {div_n_register, div_n_register[0]};
if ((reset === 1'b1) || (int_reset === 1'b1)) begin
clk_edges = -1;
div_n_register <= 'b0;
end else begin
if (clk_edges == -1) begin
div_n_register[0] <= clk;
if (clk == 1'b1) clk_edges = 0;
end else if (clk_edges % d_factor == 0) div_n_register[0] <= ~div_n_register[0];
if (clk_edges >= 0 || clk == 1'b1) clk_edges = (clk_edges + 1) % (2 * d_factor);
end
end
assign clkout = div_n_register[2*extra_latency];
endmodule
| 7.134348 |
module stratixv_hssi_pma_deser_att #(
parameter vcobypass = "clk_divrx", // Valid values: clk_divrx|clklow|fref
parameter enable_debug_info = "false", //Valid values: false|true; this is simulation-only parameter, for debug purpose only
parameter silicon_rev = "reve", // Valid values: reve|es
parameter serializer_clk_inv = "non_inv_clk" //Valid values: non_inv_clk|inv_clk
) (
input [ 10:0] avmmaddress,
input [ 1:0] avmmbyteen,
input [ 0:0] avmmclk,
input [ 0:0] avmmread,
output [ 15:0] avmmreaddata,
input [ 0:0] avmmrstn,
input [ 0:0] avmmwrite,
input [ 15:0] avmmwritedata,
output [ 0:0] blockselect,
output [ 0:0] clkdivrx,
output [127:0] dataout,
input [ 0:0] devenadiv2n,
input [ 0:0] devenadiv2p,
input [ 0:0] devenbdiv2n,
input [ 0:0] devenbdiv2p,
input [ 0:0] div2270,
input [ 0:0] div2270n,
input [ 0:0] doddadiv2n,
input [ 0:0] doddadiv2p,
input [ 0:0] doddbdiv2n,
input [ 0:0] doddbdiv2p,
output [ 0:0] observableasyncdata,
output [ 0:0] observableintclk,
input [ 0:0] rstn
);
`ifdef FORCE_SV_HSSI_ES_SIM_MODEL
localparam silicon_rev_local = "es";
`else
`ifdef FORCE_SV_HSSI_REVE_SIM_MODEL
localparam silicon_rev_local = "reve";
`else
localparam silicon_rev_local = silicon_rev;
`endif
`endif
initial begin
$display("module stratixv_hssi_pma_deser_att : simulation model silicon_rev = \"%s\"",
silicon_rev_local);
end
generate
if ((silicon_rev_local == "es") || (silicon_rev_local == "ES")) begin
stratixv_hssi_pma_deser_att_encrypted_ES #(
.enable_debug_info(enable_debug_info),
.vcobypass(vcobypass)
) stratixv_hssi_pma_deser_att_encrypted_ES_inst (
.clkdivrx(clkdivrx),
.avmmclk(avmmclk),
.devenadiv2n(devenadiv2n),
.div2270n(div2270n),
.avmmrstn(avmmrstn),
.devenbdiv2n(devenbdiv2n),
.avmmbyteen(avmmbyteen),
.doddbdiv2p(doddbdiv2p),
.doddadiv2p(doddadiv2p),
.devenadiv2p(devenadiv2p),
.dataout(dataout),
.rstn(rstn),
.devenbdiv2p(devenbdiv2p),
.avmmread(avmmread),
.div2270(div2270),
.doddadiv2n(doddadiv2n),
.blockselect(blockselect),
.avmmreaddata(avmmreaddata),
.doddbdiv2n(doddbdiv2n),
.avmmwrite(avmmwrite),
.observableintclk(observableintclk),
.avmmaddress(avmmaddress),
.avmmwritedata(avmmwritedata)
);
end // if generate ES
else if ((silicon_rev_local == "reve") || (silicon_rev_local == "REVE"))
begin
stratixv_hssi_pma_deser_att_encrypted #(
.enable_debug_info(enable_debug_info),
.vcobypass(vcobypass)
) stratixv_hssi_pma_deser_att_encrypted_inst (
.clkdivrx(clkdivrx),
.avmmclk(avmmclk),
.devenadiv2n(devenadiv2n),
.div2270n(div2270n),
.avmmrstn(avmmrstn),
.devenbdiv2n(devenbdiv2n),
.avmmbyteen(avmmbyteen),
.doddbdiv2p(doddbdiv2p),
.doddadiv2p(doddadiv2p),
.devenadiv2p(devenadiv2p),
.dataout(dataout),
.rstn(rstn),
.devenbdiv2p(devenbdiv2p),
.avmmread(avmmread),
.div2270(div2270),
.doddadiv2n(doddadiv2n),
.blockselect(blockselect),
.avmmreaddata(avmmreaddata),
.doddbdiv2n(doddbdiv2n),
.avmmwrite(avmmwrite),
.observableintclk(observableintclk),
.avmmaddress(avmmaddress),
.avmmwritedata(avmmwritedata)
);
end // if generate REVE
endgenerate
endmodule
| 7.134348 |
module stratixv_hssi_pma_ser_att #(
parameter enable_debug_info = "false", //Valid values: false|true; this is simulation-only parameter, for debug purpose only
parameter ser_loopback = "loopback_disable", // Valid values: loopback_enable|loopback_disable
parameter ser_pdb = "power_down", // Valid values: power_down|power_up
parameter silicon_rev = "reve" // Valid values: reve|es
) (
input [ 10:0] avmmaddress,
input [ 1:0] avmmbyteen,
input [ 0:0] avmmclk,
input [ 0:0] avmmread,
output [ 15:0] avmmreaddata,
input [ 0:0] avmmrstn,
input [ 0:0] avmmwrite,
input [ 15:0] avmmwritedata,
output [ 0:0] blockselect,
input [ 0:0] clk0,
input [ 0:0] clk180,
output [ 0:0] clkdivtxtop,
input [127:0] datain,
output [ 0:0] lbvon,
output [ 0:0] lbvop,
output [ 0:0] observableasyncdatain,
output [ 0:0] observableintclk,
output [ 0:0] observablesyncdatain,
output [ 0:0] oe,
output [ 0:0] oeb,
output [ 0:0] oo,
output [ 0:0] oob,
input [ 0:0] rstn,
input [ 0:0] slpbk
);
`ifdef FORCE_SV_HSSI_ES_SIM_MODEL
localparam silicon_rev_local = "es";
`else
`ifdef FORCE_SV_HSSI_REVE_SIM_MODEL
localparam silicon_rev_local = "reve";
`else
localparam silicon_rev_local = silicon_rev;
`endif
`endif
initial begin
$display("module stratixv_hssi_pma_ser_att : simulation model silicon_rev = \"%s\"",
silicon_rev_local);
end
generate
if ((silicon_rev_local == "es") || (silicon_rev_local == "ES")) begin
stratixv_hssi_pma_ser_att_encrypted_ES #(
.enable_debug_info(enable_debug_info),
.ser_loopback(ser_loopback),
.ser_pdb(ser_pdb)
) stratixv_hssi_pma_ser_att_encrypted_ES_inst (
.datain(datain),
.observableasyncdatain(observableasyncdatain),
.lbvon(lbvon),
.clk0(clk0),
.avmmclk(avmmclk),
.avmmrstn(avmmrstn),
.oe(oe),
.avmmbyteen(avmmbyteen),
.clk180(clk180),
.oeb(oeb),
.lbvop(lbvop),
.rstn(rstn),
.avmmread(avmmread),
.observablesyncdatain(observablesyncdatain),
.clkdivtxtop(clkdivtxtop),
.blockselect(blockselect),
.avmmreaddata(avmmreaddata),
.oob(oob),
.avmmwrite(avmmwrite),
.slpbk(slpbk),
.observableintclk(observableintclk),
.oo(oo),
.avmmaddress(avmmaddress),
.avmmwritedata(avmmwritedata)
);
end // if generate ES
else if ((silicon_rev_local == "reve") || (silicon_rev_local == "REVE"))
begin
stratixv_hssi_pma_ser_att_encrypted #(
.enable_debug_info(enable_debug_info),
.ser_loopback(ser_loopback),
.ser_pdb(ser_pdb)
) stratixv_hssi_pma_ser_att_encrypted_inst (
.datain(datain),
.observableasyncdatain(observableasyncdatain),
.lbvon(lbvon),
.clk0(clk0),
.avmmclk(avmmclk),
.avmmrstn(avmmrstn),
.oe(oe),
.avmmbyteen(avmmbyteen),
.clk180(clk180),
.oeb(oeb),
.lbvop(lbvop),
.rstn(rstn),
.avmmread(avmmread),
.observablesyncdatain(observablesyncdatain),
.clkdivtxtop(clkdivtxtop),
.blockselect(blockselect),
.avmmreaddata(avmmreaddata),
.oob(oob),
.avmmwrite(avmmwrite),
.slpbk(slpbk),
.observableintclk(observableintclk),
.oo(oo),
.avmmaddress(avmmaddress),
.avmmwritedata(avmmwritedata)
);
end // if generate REVE
endgenerate
endmodule
| 7.134348 |
module stratixv_hssi_refclk_divider #(
parameter user_base_address = 0, // Valid values: 0..2047
parameter divide_by = 1, // Valid values: 1|2
parameter avmm_group_channel_index = 0, // Valid values: 0..2
parameter use_default_base_address = "true", // Valid values: false|true
parameter refclk_coupling_termination = "cdb_cdr_refclk_coupling_oct_normal_100_ohm_oct", // Valid values: dc_coupling_external_termination|dc_coupling_100_ohm_oct|normal_100_ohm_oct|unused
parameter enabled = "false", // Valid values: true|false
parameter reference_clock_frequency = "", // Valid values:
parameter silicon_rev = "reve" // Valid values: reve|es
) (
input [10:0] avmmaddress,
input [ 1:0] avmmbyteen,
input [ 0:0] avmmclk,
input [ 0:0] avmmread,
output [15:0] avmmreaddata,
input [ 0:0] avmmrstn,
input [ 0:0] avmmwrite,
input [15:0] avmmwritedata,
output [ 0:0] blockselect,
input [ 0:0] nonuserfrompmaux,
input [ 0:0] refclkin,
output [ 0:0] refclkout
);
`ifdef FORCE_SV_HSSI_ES_SIM_MODEL
localparam silicon_rev_local = "es";
`else
`ifdef FORCE_SV_HSSI_REVE_SIM_MODEL
localparam silicon_rev_local = "reve";
`else
localparam silicon_rev_local = silicon_rev;
`endif
`endif
initial begin
$display("module stratixv_hssi_refclk_divider : simulation model silicon_rev = \"%s\"",
silicon_rev_local);
end
generate
if ((silicon_rev_local == "es") || (silicon_rev_local == "ES")) begin
stratixv_hssi_refclk_divider_encrypted_ES #(
.user_base_address(user_base_address),
.divide_by(divide_by),
.avmm_group_channel_index(avmm_group_channel_index),
.use_default_base_address(use_default_base_address),
.refclk_coupling_termination(refclk_coupling_termination),
.enabled(enabled),
.reference_clock_frequency(reference_clock_frequency)
) stratixv_hssi_refclk_divider_encrypted_ES_inst (
.refclkin(refclkin),
.refclkout(refclkout),
.blockselect(blockselect),
.avmmreaddata(avmmreaddata),
.avmmclk(avmmclk),
.avmmrstn(avmmrstn),
.avmmwrite(avmmwrite),
.avmmbyteen(avmmbyteen),
.nonuserfrompmaux(nonuserfrompmaux),
.avmmaddress(avmmaddress),
.avmmread(avmmread),
.avmmwritedata(avmmwritedata)
);
end // if generate ES
else if ((silicon_rev_local == "reve") || (silicon_rev_local == "REVE"))
begin
stratixv_hssi_refclk_divider_encrypted #(
.user_base_address(user_base_address),
.divide_by(divide_by),
.avmm_group_channel_index(avmm_group_channel_index),
.use_default_base_address(use_default_base_address),
.refclk_coupling_termination(refclk_coupling_termination),
.enabled(enabled),
.reference_clock_frequency(reference_clock_frequency)
) stratixv_hssi_refclk_divider_encrypted_inst (
.refclkin(refclkin),
.refclkout(refclkout),
.blockselect(blockselect),
.avmmreaddata(avmmreaddata),
.avmmclk(avmmclk),
.avmmrstn(avmmrstn),
.avmmwrite(avmmwrite),
.avmmbyteen(avmmbyteen),
.nonuserfrompmaux(nonuserfrompmaux),
.avmmaddress(avmmaddress),
.avmmread(avmmread),
.avmmwritedata(avmmwritedata)
);
end // if generate REVE
endgenerate
endmodule
| 7.134348 |
module strb_ram #(
parameter AWIDTH = 12, // Address Width
parameter DWIDTH = 128, // Data Width
parameter OREG_A = "TRUE", // Optional Port A output pipeline registers
parameter OREG_B = "TRUE" // Optional Port B output pipeline registers
) (
input clk,
input en_a, // Port A enable. Enables or disables the read/write access to the block RAM memory core.
input en_b, // Port B enable. Enables or disables the read/write access to the block RAM memory core.
input we_a,
input we_b,
input [(DWIDTH/4 -1) : 0] nibble_en_a,
input [(DWIDTH/4 -1) : 0] nibble_en_b,
input rst_a, //enout0,
input rst_b,
input [AWIDTH-1:0] addr_a,
input [AWIDTH-1:0] addr_b,
input [DWIDTH-1:0] wr_data_a,
input [DWIDTH-1:0] wr_data_b,
input OREG_CE_A,
input OREG_CE_B,
output [DWIDTH-1:0] rd_data_a,
output [DWIDTH-1:0] rd_data_b
);
reg [DWIDTH-1:0] mem [(1<<AWIDTH)-1:0]; // Memory Declaration
reg [DWIDTH-1:0] memreg_b;
reg [DWIDTH-1:0] memreg_b_reg;
integer nibble_index;
// RAM : Read has one latency, Write has one latency as well.
// Write Logic
always @(posedge clk) begin
if (en_a) begin
if (we_a) begin
for (nibble_index = 0; nibble_index <= (DWIDTH / 4) - 1; nibble_index = nibble_index + 1)
if (nibble_en_a[nibble_index] == 1) begin
// mem[addr_a] <= wr_data_a;
mem[addr_a][(nibble_index*4)+:4] <= wr_data_a[(nibble_index*4)+:4];
end
end
end
end // always @ (posedge clk)
always @(posedge clk) begin
if (rst_b) begin
memreg_b <= 'b0;
end else begin
if (en_b) begin
if (~we_b) begin
memreg_b <= mem[addr_b];
end else begin
memreg_b <= memreg_b;
end
end else begin
memreg_b <= memreg_b;
end
end
end
always @(posedge clk) begin
if (OREG_CE_B == 1'b1) begin
memreg_b_reg <= memreg_b;
end else begin
memreg_b_reg <= memreg_b_reg;
end
end
assign rd_data_a = {DWIDTH{1'b0}};
generate
if (OREG_B == "TRUE") begin
assign rd_data_b = memreg_b_reg;
end else begin
assign rd_data_b = memreg_b;
end
endgenerate
endmodule
| 9.338778 |
module strcmp_testbench ();
reg clk, rst;
parameter CPU_CLOCK_PERIOD = 20;
parameter CPU_CLOCK_FREQ = 1_000_000_000 / CPU_CLOCK_PERIOD;
initial clk = 0;
always #(CPU_CLOCK_PERIOD / 2) clk = ~clk;
wire [31:0] csr;
Riscv151 #(
.CPU_CLOCK_FREQ(CPU_CLOCK_FREQ),
.RESET_PC(32'h1000_0000)
) CPU (
.clk(clk),
.rst(rst),
.FPGA_SERIAL_RX(), // input
.FPGA_SERIAL_TX(), // output
.csr(csr)
);
reg done = 0;
reg [31:0] cycle = 0;
initial begin
#1;
$readmemh("strcmp.mif", CPU.imem.mem);
$readmemh("strcmp.mif", CPU.dmem.mem);
rst = 1;
// Hold reset for a while
repeat (10) @(posedge clk);
rst = 0;
// Delay for some time
repeat (10) @(posedge clk);
// Wait until csr is updated
while (csr === 0) begin
@(posedge clk);
end
done = 1;
if (csr[0] === 1'b1 && csr[31:1] === 31'd0) begin
$display("[%d sim. cycles] CSR test PASSED! Strings matched.", cycle);
end else begin
$display("[%d sim. cycles] CSR test FAILED! Strings mismatched.", cycle);
end
#100;
$finish();
end
initial begin
while (rst == 1) begin
@(posedge clk);
end
for (cycle = 0; cycle < 1000; cycle = cycle + 1) begin
if (!done) @(posedge clk);
end
if (!done) begin
$display("[FAILED] Timing out");
$finish();
end
end
endmodule
| 7.239197 |
module stream2wb #(
parameter integer WB_N = 3,
// auto
parameter integer DL = (32 * WB_N) - 1,
parameter integer CL = WB_N - 1
) (
// Stream interface for command/response
input wire [7:0] rx_data,
input wire rx_valid,
output wire rx_ready,
output wire [7:0] tx_data,
output wire tx_last,
output wire tx_valid,
input wire tx_ready,
// Wishbone
output reg [31:0] wb_wdata,
input wire [DL:0] wb_rdata,
output reg [15:0] wb_addr,
output reg wb_we,
output reg [CL:0] wb_cyc,
input wire [CL:0] wb_ack,
// Aux-CSR
output reg [31:0] aux_csr,
// Clock / Reset
input wire clk,
input wire rst
);
localparam
CMD_SYNC = 4'h0,
CMD_REG_ACCESS = 4'h1,
CMD_DATA_SET = 4'h2,
CMD_DATA_GET = 4'h3,
CMD_AUX_CSR = 4'h4;
// Signals
// -------
// Command RX
reg [39:0] rx_reg;
reg [ 2:0] rx_cnt;
wire [ 3:0] cmd_code;
wire [31:0] cmd_data;
reg cmd_stb;
// Response TX
wire tx_ack;
reg [31:0] tx_reg;
reg [ 2:0] tx_cnt;
reg [31:0] resp_data;
reg resp_ld;
// Wishbone interface
reg [31:0] wb_rdata_i;
wire wb_ack_i;
// Host interface
// --------------
// Command input
always @(posedge clk or posedge rst)
if (rst) rx_cnt <= 3'd0;
else if (rx_valid) rx_cnt <= rx_cnt[2] ? 3'd0 : (rx_cnt + 1);
always @(posedge clk) if (rx_valid) rx_reg <= {rx_reg[31:0], rx_data};
assign rx_ready = 1'b1;
assign cmd_code = rx_reg[39:36];
assign cmd_data = rx_reg[31:0];
always @(posedge clk) cmd_stb <= rx_cnt[2] & rx_valid;
// Response output
always @(posedge clk or posedge rst)
if (rst) tx_cnt <= 3'd0;
else begin
if (resp_ld) tx_cnt <= 3'd4;
else if (tx_ack) tx_cnt <= tx_cnt - 1;
end
always @(posedge clk)
if (resp_ld) tx_reg <= resp_data;
else if (tx_ack) tx_reg <= {tx_reg[23:0], 8'h00};
assign tx_data = tx_reg[31:24];
assign tx_last = (tx_cnt == 3'd1);
assign tx_valid = |tx_cnt;
assign tx_ack = tx_valid & tx_ready;
// Commands
always @(posedge clk) begin
// Defaults
resp_ld <= 1'b0;
resp_data <= 40'hxxxxxxxxxx;
// Commands
if (cmd_stb) begin
case (cmd_code)
CMD_SYNC: begin
resp_data <= 432'hcafebabe;
resp_ld <= 1'b1;
end
CMD_REG_ACCESS: begin
wb_addr <= cmd_data[15:0];
wb_we <= ~cmd_data[20];
wb_cyc <= (1 << cmd_data[19:16]);
end
CMD_DATA_SET: begin
wb_wdata <= cmd_data;
end
CMD_DATA_GET: begin
resp_ld <= 1'b1;
resp_data <= wb_wdata;
end
CMD_AUX_CSR: begin
aux_csr <= cmd_data;
end
endcase
end
if (wb_ack_i) begin
// Cycle done
wb_cyc <= 0;
// Capture read response
if (~wb_we) wb_wdata <= wb_rdata_i;
end
if (rst) begin
wb_cyc <= 0;
aux_csr <= 32'h00031800; // tbl 0, prog 49, 50% w/d
end
end
// Wishbone multi-slave handling
assign wb_ack_i = |wb_ack;
always @(*) begin : rdata
integer i;
wb_rdata_i = 32'h00000000;
for (i = 0; i < WB_N; i = i + 1) wb_rdata_i = wb_rdata_i | wb_rdata[32*i+:32];
end
endmodule
| 7.80852 |
module StreamArbiter_1 (
input clk,
input reset
);
wire streamArbiter_2_io_output_ready;
wire streamArbiter_2_io_inputs_0_ready;
wire streamArbiter_2_io_inputs_1_ready;
wire streamArbiter_2_io_inputs_2_ready;
wire streamArbiter_2_io_output_valid;
wire [7:0] streamArbiter_2_io_output_payload;
wire [1:0] streamArbiter_2_io_chosen;
wire [2:0] streamArbiter_2_io_chosenOH;
wire streamA_valid;
wire streamA_ready;
wire [7:0] streamA_payload;
wire streamB_valid;
wire streamB_ready;
wire [7:0] streamB_payload;
wire streamC_valid;
wire streamC_ready;
wire [7:0] streamC_payload;
StreamArbiter streamArbiter_2 (
.io_inputs_0_valid (streamA_valid), //i
.io_inputs_0_ready (streamArbiter_2_io_inputs_0_ready), //o
.io_inputs_0_payload(streamA_payload[7:0]), //i
.io_inputs_1_valid (streamB_valid), //i
.io_inputs_1_ready (streamArbiter_2_io_inputs_1_ready), //o
.io_inputs_1_payload(streamB_payload[7:0]), //i
.io_inputs_2_valid (streamC_valid), //i
.io_inputs_2_ready (streamArbiter_2_io_inputs_2_ready), //o
.io_inputs_2_payload(streamC_payload[7:0]), //i
.io_output_valid (streamArbiter_2_io_output_valid), //o
.io_output_ready (streamArbiter_2_io_output_ready), //i
.io_output_payload (streamArbiter_2_io_output_payload[7:0]), //o
.io_chosen (streamArbiter_2_io_chosen[1:0]), //o
.io_chosenOH (streamArbiter_2_io_chosenOH[2:0]), //o
.clk (clk), //i
.reset (reset) //i
);
assign streamA_ready = streamArbiter_2_io_inputs_0_ready;
assign streamB_ready = streamArbiter_2_io_inputs_1_ready;
assign streamC_ready = streamArbiter_2_io_inputs_2_ready;
endmodule
| 6.929245 |
module StreamArbiter (
input io_inputs_0_valid,
output io_inputs_0_ready,
input [7:0] io_inputs_0_payload,
input io_inputs_1_valid,
output io_inputs_1_ready,
input [7:0] io_inputs_1_payload,
input io_inputs_2_valid,
output io_inputs_2_ready,
input [7:0] io_inputs_2_payload,
output io_output_valid,
input io_output_ready,
output [7:0] io_output_payload,
output [1:0] io_chosen,
output [2:0] io_chosenOH,
input clk,
input reset
);
wire [5:0] _zz__zz_maskProposal_0_2;
wire [5:0] _zz__zz_maskProposal_0_2_1;
wire [2:0] _zz__zz_maskProposal_0_2_2;
reg [7:0] _zz_io_output_payload;
wire [1:0] _zz_io_output_payload_1;
reg locked;
wire maskProposal_0;
wire maskProposal_1;
wire maskProposal_2;
reg maskLocked_0;
reg maskLocked_1;
reg maskLocked_2;
wire maskRouted_0;
wire maskRouted_1;
wire maskRouted_2;
wire [2:0] _zz_maskProposal_0;
wire [5:0] _zz_maskProposal_0_1;
wire [5:0] _zz_maskProposal_0_2;
wire [2:0] _zz_maskProposal_0_3;
wire io_output_fire;
wire _zz_io_chosen;
wire _zz_io_chosen_1;
assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1);
assign _zz__zz_maskProposal_0_2_2 = {maskLocked_1, {maskLocked_0, maskLocked_2}};
assign _zz__zz_maskProposal_0_2_1 = {3'd0, _zz__zz_maskProposal_0_2_2};
assign _zz_io_output_payload_1 = {maskRouted_2, maskRouted_1};
always @(*) begin
case (_zz_io_output_payload_1)
2'b00: _zz_io_output_payload = io_inputs_0_payload;
2'b01: _zz_io_output_payload = io_inputs_1_payload;
default: _zz_io_output_payload = io_inputs_2_payload;
endcase
end
assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0);
assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1);
assign maskRouted_2 = (locked ? maskLocked_2 : maskProposal_2);
assign _zz_maskProposal_0 = {io_inputs_2_valid, {io_inputs_1_valid, io_inputs_0_valid}};
assign _zz_maskProposal_0_1 = {_zz_maskProposal_0, _zz_maskProposal_0};
assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~_zz__zz_maskProposal_0_2));
assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[5 : 3] | _zz_maskProposal_0_2[2 : 0]);
assign maskProposal_0 = _zz_maskProposal_0_3[0];
assign maskProposal_1 = _zz_maskProposal_0_3[1];
assign maskProposal_2 = _zz_maskProposal_0_3[2];
assign io_output_fire = (io_output_valid && io_output_ready);
assign io_output_valid = (((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)) || (io_inputs_2_valid && maskRouted_2));
assign io_output_payload = _zz_io_output_payload;
assign io_inputs_0_ready = (maskRouted_0 && io_output_ready);
assign io_inputs_1_ready = (maskRouted_1 && io_output_ready);
assign io_inputs_2_ready = (maskRouted_2 && io_output_ready);
assign io_chosenOH = {maskRouted_2, {maskRouted_1, maskRouted_0}};
assign _zz_io_chosen = io_chosenOH[1];
assign _zz_io_chosen_1 = io_chosenOH[2];
assign io_chosen = {_zz_io_chosen_1, _zz_io_chosen};
always @(posedge clk or posedge reset) begin
if (reset) begin
locked <= 1'b0;
maskLocked_0 <= 1'b0;
maskLocked_1 <= 1'b0;
maskLocked_2 <= 1'b1;
end else begin
if (io_output_valid) begin
maskLocked_0 <= maskRouted_0;
maskLocked_1 <= maskRouted_1;
maskLocked_2 <= maskRouted_2;
end
if (io_output_valid) begin
locked <= 1'b1;
end
if (io_output_fire) begin
locked <= 1'b0;
end
end
end
endmodule
| 6.929245 |
module StreamArbiter_2 (
input clk,
input reset
);
wire streamArbiter_1_io_output_ready;
wire streamArbiter_1_io_inputs_0_ready;
wire streamArbiter_1_io_inputs_1_ready;
wire streamArbiter_1_io_inputs_2_ready;
wire streamArbiter_1_io_output_valid;
wire [7:0] streamArbiter_1_io_output_payload;
wire [1:0] streamArbiter_1_io_chosen;
wire [2:0] streamArbiter_1_io_chosenOH;
wire streamD_valid;
wire streamD_ready;
wire [7:0] streamD_payload;
wire streamE_valid;
wire streamE_ready;
wire [7:0] streamE_payload;
wire streamF_valid;
wire streamF_ready;
wire [7:0] streamF_payload;
StreamArbiter streamArbiter_1 (
.io_inputs_0_valid (streamD_valid), //i
.io_inputs_0_ready (streamArbiter_1_io_inputs_0_ready), //o
.io_inputs_0_payload(streamD_payload[7:0]), //i
.io_inputs_1_valid (streamE_valid), //i
.io_inputs_1_ready (streamArbiter_1_io_inputs_1_ready), //o
.io_inputs_1_payload(streamE_payload[7:0]), //i
.io_inputs_2_valid (streamF_valid), //i
.io_inputs_2_ready (streamArbiter_1_io_inputs_2_ready), //o
.io_inputs_2_payload(streamF_payload[7:0]), //i
.io_output_valid (streamArbiter_1_io_output_valid), //o
.io_output_ready (streamArbiter_1_io_output_ready), //i
.io_output_payload (streamArbiter_1_io_output_payload[7:0]), //o
.io_chosen (streamArbiter_1_io_chosen[1:0]), //o
.io_chosenOH (streamArbiter_1_io_chosenOH[2:0]), //o
.clk (clk), //i
.reset (reset) //i
);
assign streamD_ready = streamArbiter_1_io_inputs_0_ready;
assign streamE_ready = streamArbiter_1_io_inputs_1_ready;
assign streamF_ready = streamArbiter_1_io_inputs_2_ready;
endmodule
| 6.929245 |
module StreamArbiter (
input io_inputs_0_valid,
output io_inputs_0_ready,
input [7:0] io_inputs_0_payload,
input io_inputs_1_valid,
output io_inputs_1_ready,
input [7:0] io_inputs_1_payload,
input io_inputs_2_valid,
output io_inputs_2_ready,
input [7:0] io_inputs_2_payload,
output io_output_valid,
input io_output_ready,
output [7:0] io_output_payload,
output [1:0] io_chosen,
output [2:0] io_chosenOH,
input clk,
input reset
);
wire [2:0] _zz__zz_maskProposal_1_1;
reg [7:0] _zz_io_output_payload;
wire [1:0] _zz_io_output_payload_1;
wire locked;
wire maskProposal_0;
wire maskProposal_1;
wire maskProposal_2;
reg maskLocked_0;
reg maskLocked_1;
reg maskLocked_2;
wire maskRouted_0;
wire maskRouted_1;
wire maskRouted_2;
wire [2:0] _zz_maskProposal_1;
wire [2:0] _zz_maskProposal_1_1;
wire _zz_io_chosen;
wire _zz_io_chosen_1;
assign _zz__zz_maskProposal_1_1 = (_zz_maskProposal_1 - 3'b001);
assign _zz_io_output_payload_1 = {maskRouted_2, maskRouted_1};
always @(*) begin
case (_zz_io_output_payload_1)
2'b00: _zz_io_output_payload = io_inputs_0_payload;
2'b01: _zz_io_output_payload = io_inputs_1_payload;
default: _zz_io_output_payload = io_inputs_2_payload;
endcase
end
assign locked = 1'b0;
assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0);
assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1);
assign maskRouted_2 = (locked ? maskLocked_2 : maskProposal_2);
assign _zz_maskProposal_1 = {io_inputs_2_valid, {io_inputs_1_valid, io_inputs_0_valid}};
assign _zz_maskProposal_1_1 = (_zz_maskProposal_1 & (~_zz__zz_maskProposal_1_1));
assign maskProposal_0 = io_inputs_0_valid;
assign maskProposal_1 = _zz_maskProposal_1_1[1];
assign maskProposal_2 = _zz_maskProposal_1_1[2];
assign io_output_valid = (((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)) || (io_inputs_2_valid && maskRouted_2));
assign io_output_payload = _zz_io_output_payload;
assign io_inputs_0_ready = (maskRouted_0 && io_output_ready);
assign io_inputs_1_ready = (maskRouted_1 && io_output_ready);
assign io_inputs_2_ready = (maskRouted_2 && io_output_ready);
assign io_chosenOH = {maskRouted_2, {maskRouted_1, maskRouted_0}};
assign _zz_io_chosen = io_chosenOH[1];
assign _zz_io_chosen_1 = io_chosenOH[2];
assign io_chosen = {_zz_io_chosen_1, _zz_io_chosen};
always @(posedge clk) begin
if (io_output_valid) begin
maskLocked_0 <= maskRouted_0;
maskLocked_1 <= maskRouted_1;
maskLocked_2 <= maskRouted_2;
end
end
endmodule
| 6.929245 |
module StreamBuffer (
input rst_n,
input pclk,
input fclk,
input start,
input din_valid,
output din_ready,
input [7:0] din,
output [63:0] dout,
output dout_valid,
input dout_ready,
output burst_valid,
output [10:0] fifo_cnt
);
reg running;
`REG(pclk, running, 0, start ? 1 : running)
wire de2fifo_valid;
wire de2fifo_ready;
wire [63:0] de2fifo_data;
deserializer #(
.INLOGBITS (3),
.OUTLOGBITS(6)
) inst_deserial (
.clk (pclk),
.rst_n(rst_n),
.in_valid(din_valid && running),
.in_ready(din_ready),
.in_data (din[7:0]),
.out_valid(de2fifo_valid),
.out_ready(de2fifo_ready),
.out_data (de2fifo_data)
);
wire vfifo_full;
wire vfifo_empty;
wire [8:0] vfifo_count;
fifo_64w_64r_512d sfifo_inst (
.rst(!rst_n), // input rst
.wr_clk(pclk), // input wr_clk
.rd_clk(fclk), // input rd_clk
.din(de2fifo_data[63:0]), // input [63 : 0] din
.wr_en(de2fifo_valid), // input wr_en
.rd_en(dout_ready), // input rd_en
.dout(dout), // output [63 : 0] dout
.full(vfifo_full), // output full
.empty(vfifo_empty), // output empty
.rd_data_count(vfifo_count), // output [8 : 0] rd_data_count
.wr_data_count() // output [8 : 0] wr_data_count
);
assign de2fifo_ready = !vfifo_full;
// I need to guarentee that 16 data entries are read out always
assign burst_valid = (vfifo_count > 9'd25);
assign dout_valid = !vfifo_empty;
assign fifo_cnt = vfifo_count;
endmodule
| 6.986803 |
module BufferCC_1 (
input io_dataIn,
output io_dataOut,
input clkb,
input rsta
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clkb or posedge rsta) begin
if (rsta) begin
buffers_0 <= 1'b1;
buffers_1 <= 1'b1;
end else begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
end
endmodule
| 6.574801 |
module BufferCC (
input io_dataIn,
output io_dataOut,
input clka,
input rsta
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clka or posedge rsta) begin
if (rsta) begin
buffers_0 <= 1'b0;
buffers_1 <= 1'b0;
end else begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
end
endmodule
| 6.712921 |
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