code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module stratixiii_rotate_shift_block (
datain,
rotate,
shiftright,
signa,
signb,
dataout
);
parameter dataa_width = 32;
parameter datab_width = 32;
parameter operation_mode = "output_only";
input [71:0] datain;
input rotate;
input shiftright;
input signa;
input signb;
wire si... | 7.897097 |
module for ddr. Gray decoder
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module stratixiii_ddr_gray_decoder (
gin,
bout
);
parameter width = 6;
input [width-1 : 0] gin;
output [width-1 : 0] bout;
reg [width-1 : 0] breg;
integer i;
assign b... | 7.461079 |
module stratixiii_termination_aux_clock_div (
clk, // input clock
reset, // reset
clkout // divided clock
);
input clk;
input reset;
output clkout;
parameter clk_divide_by = 1;
parameter extra_latency = 0;
integer clk_edges, m;
reg [2*extra_latency:0] div_n_register;
initial begin
... | 7.388711 |
module stratixiii_termination_logic (
serialloadenable,
terminationclock,
parallelloadenable,
terminationdata,
devclrn,
devpor,
seriesterminationcontrol,
parallelterminationcontrol
);
parameter test_mode = "false";
parameter lpm_type = "stratixiii_termination_logic";
input seriall... | 7.388711 |
module stratixiii_tsdblock (
offset,
clk,
ce,
clr,
testin,
tsdcalo,
tsdcaldone,
fdbkctrlfromcore,
compouttest,
tsdcompout,
offsetout
);
input [5:0] offset;
input [7:0] testin;
input clk;
input ce;
input clr;
input fdbkctrlfromcore;
input compouttest;
output... | 7.063645 |
module stratixiii_lvds_rx_fifo_sync_ram (
clk,
datain,
write_reset,
waddr,
raddr,
we,
dataout
);
// INPUT PORTS
input clk;
input write_reset;
input datain;
input [2:0] waddr;
input [2:0] raddr;
input we;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES AND NETS
... | 6.593588 |
module stratixiii_lvds_rx_fifo (
wclk,
rclk,
dparst,
fiforst,
datain,
dataout
);
parameter channel_width = 10;
// INPUT PORTS
input wclk;
input rclk;
input dparst;
input fiforst;
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES AND NETS
reg dataout_tm... | 6.593588 |
module receives serial data and outputs
// parallel data word of width = channel_width
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratixiii_lvds_rx_deser (
clk,
datain,
... | 6.910834 |
module stratixiii_lvds_rx_parallel_reg (
clk,
enable,
datain,
dataout,
devclrn,
devpor
);
parameter channel_width = 10;
// INPUT PORTS
input [channel_width - 1:0] datain;
input clk;
input enable;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] datao... | 6.593588 |
module stratixiii_lvds_reg (
q,
clk,
ena,
d,
clrn,
prn
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q_tmp;
wire q_wire;
// TIMING PATHS
specify
(posedge clk => (q +: q_tmp)) = (0, 0)... | 6.593588 |
module stratixiii_pclk_divider (
clkin,
lloaden,
clkout
);
parameter clk_divide_by = 1;
input clkin;
output lloaden;
output clkout;
reg clkout_tmp;
reg [4:0] cnt;
reg start;
reg count;
reg lloaden_tmp;
assign clkout = (clk_divide_by == 1) ? clkin : clkout_tmp;
assign lloaden = llo... | 6.568371 |
module stratixiii_pseudo_diff_out (
i,
o,
obar
);
parameter lpm_type = "stratixiii_pseudo_diff_out";
input i;
output o;
output obar;
reg o_tmp;
reg obar_tmp;
assign o = o_tmp;
assign obar = obar_tmp;
always @(i) begin
if (i == 1'b1) begin
o_tmp = 1'b1;
obar_tmp = 1'b0;
... | 7.138801 |
module stratixiii_bias_logic (
clk,
shiftnld,
captnupdt,
mainclk,
updateclk,
capture,
update
);
// INPUT PORTS
input clk;
input shiftnld;
input captnupdt;
// OUTPUTPUT PORTS
output mainclk;
output updateclk;
output capture;
output update;
// INTERNAL VARIABLES
reg ma... | 8.317317 |
module stratixiii_bias_generator (
din,
mainclk,
updateclk,
capture,
update,
dout
);
// INPUT PORTS
input din;
input mainclk;
input updateclk;
input capture;
input update;
// OUTPUTPUT PORTS
output dout;
parameter TOTAL_REG = 252;
// INTERNAL VARIABLES
reg dout_tmp;
r... | 8.317317 |
module stratixiii_bias_block (
clk,
shiftnld,
captnupdt,
din,
dout
);
// INPUT PORTS
input clk;
input shiftnld;
input captnupdt;
input din;
// OUTPUTPUT PORTS
output dout;
parameter lpm_type = "stratixiii_bias_block";
// INTERNAL VARIABLES
reg din_viol;
reg shiftnld_viol;... | 8.317317 |
module stratixiv_bmux21 (
MO,
A,
B,
S
);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.454026 |
module stratixiv_b17mux21 (
MO,
A,
B,
S
);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.572469 |
module stratixiv_nmux21 (
MO,
A,
B,
S
);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
| 7.337416 |
module stratixiv_b5mux21 (
MO,
A,
B,
S
);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.842022 |
module stratixiv_lvds_tx_reg (
q,
clk,
ena,
d,
clrn,
prn
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// BUFFER INPUTS
wire clk_in;
wire ena_in;
wire d_in;
buf (clk_in, clk);
buf (ena_in, ena);
buf (d_in, d);
... | 6.833933 |
module stratixiv_lvds_tx_parallel_register (
clk,
enable,
datain,
dataout,
devclrn,
devpor
);
parameter channel_width = 4;
// INPUT PORTS
input [channel_width - 1:0] datain;
input clk;
input enable;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] da... | 6.833933 |
module stratixiv_lvds_tx_out_block (
clk,
datain,
dataout,
devclrn,
devpor
);
parameter bypass_serializer = "false";
parameter invert_clock = "false";
parameter use_falling_clock_edge = "false";
// INPUT PORTS
input datain;
input clk;
input devclrn;
input devpor;
// OUTPUT PORTS... | 6.833933 |
module stratixiv_ram_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
parameter delay_pulse = 1'b0;
parameter start_delay = (delay_pulse == 1'b0) ? 1 : 2; // delay write
reg state;
reg ... | 6.695438 |
module for RAM inputs/outputs
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module stratixiv_ram_register (
d,
clk,
aclr,
devclrn,
... | 7.458522 |
module stratixiv_ddio_oe (
oe,
clk,
ena,
areset,
sreset,
dataout,
dfflo,
dffhi,
devpor,
devclrn
);
//Parameters Declaration
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter lpm_type = "stratixiv_ddio_oe";
//Input Por... | 6.627073 |
module stratixiv_mac_register (
datain,
clk,
aclr,
sload,
bypass_register,
dataout
);
//PARAMETER
parameter data_width = 18;
//INPUT PORTS
input [data_width -1 : 0] datain;
input clk;
input aclr;
input sload;
input bypass_register;
//OUTPUT PORTS
output [data_width -1 : 0... | 6.775929 |
module stratixiv_mac_multiplier (
dataa,
datab,
signa,
signb,
dataout
);
//PARAMETER
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataout_width = dataa_width + datab_width;
//INPUT PORTS
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
... | 6.775929 |
module stratixiv_first_stage_add_sub (
dataa,
datab,
sign,
operation,
dataout
);
//PARAMETERS
parameter dataa_width = 36;
parameter datab_width = 36;
parameter fsa_mode = "add";
// INPUT PORTS
input [71 : 0] dataa;
input [71 : 0] datab;
input sign;
input [3:0] operation;
// OUT... | 8.570866 |
module stratixiv_second_stage_add_accum (
dataa,
datab,
accumin,
sign,
operation,
dataout,
overflow
);
//PARAMETERS
parameter dataa_width = 36;
parameter datab_width = 36;
parameter accum_width = dataa_width + 8;
parameter ssa_mode = "add";
// INPUT PORTS
input [71 : 0] dataa... | 6.912358 |
module stratixiv_rotate_shift_block (
datain,
rotate,
shiftright,
signa,
signb,
dataout
);
parameter dataa_width = 32;
parameter datab_width = 32;
parameter operation_mode = "output_only";
input [71:0] datain;
input rotate;
input shiftright;
input signa;
input signb;
wire sig... | 8.182462 |
module stratixiv_carry_chain_adder (
dataa,
datab,
dataout
);
// INPUT PORTS
input [71 : 0] dataa;
input [71 : 0] datab;
// OUTPUT PORTS
output [71 : 0] dataout;
reg [71:0] dataout_tmp;
specify
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
endspecify
assign dataout ... | 6.618876 |
module for ddr. Gray decoder
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module stratixiv_ddr_gray_decoder (
gin,
bout
);
parameter width = 6;
input [width-1 : 0] gin;
output [width-1 : 0] bout;
reg [width-1 : 0] breg;
integer i;
assign bo... | 7.461079 |
module stratixiv_termination_aux_clock_div (
clk, // input clock
reset, // reset
clkout // divided clock
);
input clk;
input reset;
output clkout;
parameter clk_divide_by = 1;
parameter extra_latency = 0;
integer clk_edges, m;
reg [2*extra_latency:0] div_n_register;
initial begin
d... | 7.896739 |
module stratixiv_termination_logic (
serialloadenable,
terminationclock,
parallelloadenable,
terminationdata,
devclrn,
devpor,
seriesterminationcontrol,
parallelterminationcontrol
);
parameter test_mode = "false";
parameter lpm_type = "stratixiv_termination_logic";
input serialloa... | 7.896739 |
module stratixiv_tsdblock (
offset,
clk,
ce,
clr,
testin,
tsdcalo,
tsdcaldone,
fdbkctrlfromcore,
compouttest,
tsdcompout,
offsetout
);
input [5:0] offset;
input [7:0] testin;
input clk;
input ce;
input clr;
input fdbkctrlfromcore;
input compouttest;
output ... | 7.11642 |
module stratixiv_lvds_rx_fifo_sync_ram (
clk,
datain,
write_reset,
waddr,
raddr,
we,
dataout
);
// INPUT PORTS
input clk;
input write_reset;
input datain;
input [2:0] waddr;
input [2:0] raddr;
input we;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES AND NETS
r... | 6.833933 |
module stratixiv_lvds_rx_fifo (
wclk,
rclk,
dparst,
fiforst,
datain,
dataout
);
parameter channel_width = 10;
// INPUT PORTS
input wclk;
input rclk;
input dparst;
input fiforst;
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES AND NETS
reg dataout_tmp... | 6.833933 |
module receives serial data and outputs
// parallel data word of width = channel_width
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratixiv_lvds_rx_deser (
clk,
datain,
... | 6.910834 |
module stratixiv_lvds_rx_parallel_reg (
clk,
enable,
datain,
dataout,
devclrn,
devpor
);
parameter channel_width = 10;
// INPUT PORTS
input [channel_width - 1:0] datain;
input clk;
input enable;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] dataou... | 6.833933 |
module stratixiv_lvds_reg (
q,
clk,
ena,
d,
clrn,
prn
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q_tmp;
wire q_wire;
// TIMING PATHS
specify
(posedge clk => (q +: q_tmp)) = (0, 0);... | 6.833933 |
module stratixiv_pclk_divider (
clkin,
lloaden,
clkout
);
parameter clk_divide_by = 1;
input clkin;
output lloaden;
output clkout;
reg clkout_tmp;
reg [4:0] cnt;
reg start;
reg count;
reg lloaden_tmp;
assign clkout = (clk_divide_by == 1) ? clkin : clkout_tmp;
assign lloaden = lloa... | 6.57717 |
module stratixiv_select_ini_phase_dpaclk (
clkin,
loaden,
enable,
clkout,
loadenout
);
parameter initial_phase_select = 0;
input clkin;
input enable;
input loaden;
output clkout;
output loadenout;
wire clkout_tmp;
wire loadenout_tmp;
real clk_period, last_clk_period;
real last... | 6.518733 |
module stratixiv_pseudo_diff_out (
i,
o,
obar
);
parameter lpm_type = "stratixiv_pseudo_diff_out";
input i;
output o;
output obar;
reg o_tmp;
reg obar_tmp;
assign o = o_tmp;
assign obar = obar_tmp;
always @(i) begin
if (i == 1'b1) begin
o_tmp = 1'b1;
obar_tmp = 1'b0;
... | 7.018754 |
module stratixiv_bias_logic (
clk,
shiftnld,
captnupdt,
mainclk,
updateclk,
capture,
update
);
// INPUT PORTS
input clk;
input shiftnld;
input captnupdt;
// OUTPUTPUT PORTS
output mainclk;
output updateclk;
output capture;
output update;
// INTERNAL VARIABLES
reg mai... | 8.658732 |
module stratixiv_bias_generator (
din,
mainclk,
updateclk,
capture,
update,
dout
);
// INPUT PORTS
input din;
input mainclk;
input updateclk;
input capture;
input update;
// OUTPUTPUT PORTS
output dout;
parameter TOTAL_REG = 202;
// INTERNAL VARIABLES
reg dout_tmp;
re... | 8.658732 |
module stratixiv_bias_block (
clk,
shiftnld,
captnupdt,
din,
dout
);
// INPUT PORTS
input clk;
input shiftnld;
input captnupdt;
input din;
// OUTPUTPUT PORTS
output dout;
parameter lpm_type = "stratixiv_bias_block";
// INTERNAL VARIABLES
reg din_viol;
reg shiftnld_viol;
... | 8.658732 |
module stratixiv_pciehip_dprio_bit (
reset,
clk,
sig_in,
ext_in,
serial_mode,
si,
shift,
mdio_dis,
sig_out,
so
);
input reset; // reset
input clk; // clock
input sig_in; // signal input
input ext_in; // external input port
input serial_mode; // serial shift mode e... | 6.746782 |
module stratixiv_pciehip_compute_bit (
input wire [63:0] datain,
input wire s,
output wire r
);
// begin
assign r = datain[0] ^ datain[1] ^ datain[2] ^ datain[3] ^ datain[4] ^ datain[5] ^ datain[6] ^ datain[7] ^ datain[10] ^ datain[13] ^ datain[14] ^ datain[17] ^
datain[2... | 6.746782 |
module stratixiv_pciehip_ecc_gen (
input wire [63:0] datain, // Data on which ECC is required
input wire [ 7:0] syndrome, // Syndrome uses 8'h00 while generating
output wire [ 7:0] result // Result
);
//-----------------------------------------------------------------------------
// Instan... | 6.746782 |
module stratixiv_pciehip_ecc_decoder (
flag,
derr,
derr_cor
);
input [2:0] flag;
output derr;
output derr_cor;
assign derr = flag[2] & ~(flag[1]) & flag[0];
assign derr_cor = ~(flag[2]) & flag[1] & flag[0];
endmodule
| 6.746782 |
module stratixiv_pciehip_pulse_ext (
core_clk,
rstn,
srst,
derr_cor,
derr_cor_ext
);
input core_clk;
input rstn;
input srst;
input derr_cor;
output derr_cor_ext;
reg n1, derr_cor_ext;
wire n2;
// Pulse width extender
always @(negedge rstn or posedge core_clk) begin
if (rstn... | 6.746782 |
module stratixiv_pciehip_pciexp_dcfiforam (
data,
wren,
wraddress,
rdaddress,
wrclock,
rdclock,
q
);
parameter addr_width = 4;
parameter data_width = 32;
input [data_width - 1:0] data;
input wren;
input [addr_width - 1:0] wraddress;
input [addr_width - 1:0] rdaddress;
input wr... | 6.746782 |
module stratixiv_pciehip_pciexp_dcram_rtry (
wrclock,
wren,
wraddress,
data,
rdclock,
rdaddress,
q
);
parameter addr_width = 'd4;
parameter data_width = 'd32;
input wrclock;
input wren;
input [data_width - 1:0] data;
input [addr_width - 1:0] wraddress;
input rdclock;
input ... | 6.746782 |
module stratixiv_pciehip_pciexp_dcram_rxvc (
wrclock,
wren,
wraddress,
data,
rdclock,
rdaddress,
q
);
parameter addr_width = 'd4;
parameter data_width = 'd32;
input wrclock;
input wren;
input [data_width - 1:0] data;
input [addr_width - 1:0] wraddress;
input rdclock;
input ... | 6.746782 |
module stratixv_mux21 (
MO,
A,
B,
S
);
input A, B, S;
output MO;
wire A_in;
wire B_in;
wire S_in;
buf (A_in, A);
buf (B_in, B);
buf (S_in, S);
wire tmp_MO;
specify
(A => MO) = (0, 0);
(B => MO) = (0, 0);
(S => MO) = (0, 0);
endspecify
assign tmp_MO = (S_in == 1) ... | 7.318794 |
module stratixv_mux41 (
MO,
IN0,
IN1,
IN2,
IN3,
S
);
input IN0;
input IN1;
input IN2;
input IN3;
input [1:0] S;
output MO;
wire IN0_in;
wire IN1_in;
wire IN2_in;
wire IN3_in;
wire S1_in;
wire S0_in;
buf (IN0_in, IN0);
buf (IN1_in, IN1);
buf (IN2_in, IN2);
buf (I... | 6.565991 |
module stratixv_bmux21 (
MO,
A,
B,
S
);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.815707 |
module stratixv_b17mux21 (
MO,
A,
B,
S
);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 7.98582 |
module stratixv_nmux21 (
MO,
A,
B,
S
);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
| 7.531254 |
module stratixv_b5mux21 (
MO,
A,
B,
S
);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
| 8.107113 |
module stratixv_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0);
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule
| 7.435925 |
module
//--------------------------------------------------------------------------
// Deactivate the following LEDA rules for stratixv_mlab_cell_block.v
// G_521_3B: Use uppercase letters for all parameter names
// leda G_521_3_B off
`timescale 1 ps/1 ps
module stratixv_mlab_cell
(
portadatain,
portaa... | 8.13663 |
module stratixv_io_ibuf (
i,
ibar,
dynamicterminationcontrol,
o
);
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter differential_mode = "false";
parameter bus_hold = "false";
parameter simulate_z_as = "Z";
parameter lpm_type = "stratixv_io_ibuf";
// SIMULATION_ONLY_PARAMETERS_END
//Input ... | 6.938491 |
module stratixv_io_obuf (
i,
oe,
dynamicterminationcontrol,
seriesterminationcontrol,
parallelterminationcontrol,
devoe,
o,
obar
);
//Parameter Declaration
parameter open_drain_output = "false";
parameter bus_hold = "false";
parameter shift_series_termination_control = "false";
... | 7.861686 |
module stratixv_pseudo_diff_out (
i,
o,
obar,
// ports new for StratixV
dtcin,
dtc,
dtcbar,
oein,
oeout,
oebout
);
parameter lpm_type = "stratixv_pseudo_diff_out";
input i;
output o;
output obar;
// ports new for StratixV
input dtcin, oein;
output dtc, dtcbar, oeo... | 7.528855 |
module stratixv_bias_logic (
clk,
shiftnld,
captnupdt,
mainclk,
updateclk,
capture,
update
);
// INPUT PORTS
input clk;
input shiftnld;
input captnupdt;
// OUTPUTPUT PORTS
output mainclk;
output updateclk;
output capture;
output update;
// INTERNAL VARIABLES
reg main... | 8.535763 |
module stratixv_bias_generator (
din,
mainclk,
updateclk,
capture,
update,
dout
);
// INPUT PORTS
input din;
input mainclk;
input updateclk;
input capture;
input update;
// OUTPUTPUT PORTS
output dout;
parameter TOTAL_REG = 202;
// INTERNAL VARIABLES
reg dout_tmp;
reg... | 8.535763 |
module stratixv_bias_block (
clk,
shiftnld,
captnupdt,
din,
dout
);
// INPUT PORTS
input clk;
input shiftnld;
input captnupdt;
input din;
// OUTPUTPUT PORTS
output dout;
parameter lpm_type = "stratixv_bias_block";
// INTERNAL VARIABLES
reg din_viol;
reg shiftnld_viol;
r... | 8.535763 |
module stratixv_dll_offset_ctrl (
clk,
offsetdelayctrlin,
offset,
addnsub,
aload,
offsetctrlout,
offsettestout
);
parameter use_offset = "false";
parameter static_offset = 0;
parameter use_pvt_compensation = "false";
input clk;
input [6:0] offsetdelayctrlin;
input [6:0] offset... | 6.951401 |
module stratixv_dll (
aload,
clk,
upndnin,
upndninclkena,
delayctrlout,
dqsupdate,
offsetdelayctrlout,
offsetdelayctrlclkout,
upndnout,
dffin,
locked);
parameter input_frequency = "0 MHz";
parameter delayctrlout_mode = "normal";
parameter ... | 7.461178 |
module stratixv_dqs_delay_chain (
dqsin,
dqsenable,
dqsdisablen,
delayctrlin,
offsetctrlin,
dqsupdateen,
phasectrlin,
testin,
dffin,
dqsbusout);
parameter dqs_period = "unused";
parameter dqs_input_frequency = "unused";
parameter dqs_phase_... | 7.461178 |
module stratixv_pll_dll_output #(
// parameter declaration and default value assignemnt
parameter pll_dll_src = "vss" //Valid values: c_0_cnt|c_1_cnt|c_2_cnt|c_3_cnt|c_4_cnt|c_5_cnt|c_6_cnt|c_7_cnt|c_8_cnt|c_9_cnt|c_10_cnt|c_11_cnt|c_12_cnt|c_13_cnt|c_14_cnt|c_15_cnt|c_16_cnt|c_17_cnt|clkin_0|clkin_1|clkin_2|cl... | 7.867696 |
module stratixv_pll_dpa_output #(
// parameter declaration and default value assignemnt
parameter output_clock_frequency = "", //Valid values:
parameter pll_vcoph_div = 1 //Valid values: 1|2|4
) (
//input and output port declaration
input [0:0] pd,
input [7:0] phin,
output [7:0] phout
)... | 7.867696 |
module stratixv_pll_extclk_output #(
// parameter declaration and default value assignemnt
parameter pll_extclk_cnt_src = "vss", //Valid values: c_0_cnt|c_1_cnt|c_2_cnt|c_3_cnt|c_4_cnt|c_5_cnt|c_6_cnt|c_7_cnt|c_8_cnt|c_9_cnt|c_10_cnt|c_11_cnt|c_12_cnt|c_13_cnt|c_14_cnt|c_15_cnt|c_16_cnt|c_17_cnt|m0_cnt|m1_cnt|c... | 7.867696 |
module stratixv_pll_lvds_output #(
// parameter declaration and default value assignemnt
parameter pll_loaden_coarse_dly = "0 ps", //Valid values: 0 ps|200 ps|400 ps|600 ps|800 ps|1000 ps
parameter pll_loaden_enable_disable = "false", //Valid values: false|true
parameter pll_loaden_fine_dly = "0 ps", ... | 7.867696 |
module stratixv_pll_output_counter #(
// parameter declaration and default value assignemnt
parameter output_clock_frequency = "", //Valid values:
parameter phase_shift = "", //Valid values:
parameter duty_cycle = 50, //Valid values: 1..99
parameter c_cnt_coarse_dly = "0 ps", //Valid values: 0... | 7.867696 |
module stratixv_pll_reconfig #(
// Parameter declarations and default value assignments
parameter fractional_pll_index = 1 //Valid values:
) (
//input and output port declaration
input [ 5:0] addr,
input [ 0:0] atpgmode,
input [ 1:0] byteen,
input [ 0:0] clk,
input [ 0:0] cnt... | 7.867696 |
module stratixv_pll_refclk_select #(
// parameter declaration and default value assignemnt
parameter pll_auto_clk_sw_en = "false", //Valid values: false|true
parameter pll_clk_loss_edge = "both_edges", //Valid values: both_edges|rising_edge
parameter pll_clk_loss_sw_en = "false", //Valid values: fals... | 7.867696 |
module stratixv_input_phase_alignment (
datain,
levelingclk,
zerophaseclk,
areset,
enainputcycledelay,
enaphasetransferreg,
dataout,
dffin,
dff1t,
dffphasetransfer
);
parameter power_up = "low";
parameter async_mode = "no_reset";
parameter add_input_cycle_delay = "false";
... | 7.14137 |
module stratixv_lvds_rx (
clock0,
datain,
enable0,
dpareset,
dpahold,
dpaswitch,
fiforeset,
bitslip,
bitslipreset,
serialfbk,
devclrn,
devpor,
dpaclkin,
dataout,
dpalock,
bitslipmax,
serialdataout,
postdpaserialdataout,
divfwdclk,
dpa... | 6.728198 |
module stratixv_lvds_tx (
datain,
clock0,
enable0,
serialdatain,
postdpaserialdatain,
devclrn,
devpor,
dpaclkin,
dataout,
serialfdbkout,
observableout
);
parameter bypass_serializer = "false";
parameter invert_clock = "false";
parameter use_falling_clock_edge = "false"... | 7.058885 |
module stratixv_output_alignment (
datain,
clk,
areset,
sreset,
enaoutputcycledelay,
enaphasetransferreg,
dataout,
dffin,
dff1t,
dff2t,
dffphasetransfer
);
parameter power_up = "low";
parameter async_mode = "none";
parameter sync_mode = "none";
parameter add_output_c... | 6.796769 |
module stratixv_termination_logic (
s2pload,
serdata,
scanenable,
scanclk,
enser,
seriesterminationcontrol,
parallelterminationcontrol
);
parameter lpm_type = "stratixv_termination_logic";
parameter a_iob_oct_test = "a_iob_oct_test_off";
input s2pload;
input serdata;
input scanen... | 7.179578 |
module stratixv_tsdblock (
clk,
ce,
clr,
tsdcalo,
tsdcaldone
);
parameter clock_divider_enable = "on";
parameter clock_divider_value = 40;
parameter sim_tsdcalo = 0;
parameter poi_cal_temperature = 85;
parameter tsdblock_mode = "corner_sense";
parameter use_dft_compout = "false";
para... | 7.046072 |
module stratixv_hssi_pma_aux #(
parameter silicon_rev = "reve", // Valid values: reve|es
// // parameter declaration and default value assignemnt
parameter enable_debug_info = "false", //Valid values: false|true; this is simulation-only parameter, for debug purpose only
parameter continuous_calibratio... | 7.134348 |
module stratixv_hssi_avmm_interface #(
parameter num_ch0_atoms = 0,
parameter num_ch1_atoms = 0,
parameter num_ch2_atoms = 0
) (
//input and output port declaration
input [ 0:0] avmmrstn,
input [ 0:0] avmmclk,
input [ 0:0] avmmwrite,
input [ 0:0] avmmread,
input [ 1:0] avmm... | 7.134348 |
module stratixv_hssi_aux_clock_div (
clk, // input clock
reset, // reset
enable_d, // enable DPRIO
d, // division factor for DPRIO support
clkout // divided clock
);
input clk, reset;
input enable_d;
input [7:0] d;
output clkout;
parameter clk_divide_by = 1;
parameter extra_latenc... | 7.134348 |
module stratixv_hssi_pma_deser_att #(
parameter vcobypass = "clk_divrx", // Valid values: clk_divrx|clklow|fref
parameter enable_debug_info = "false", //Valid values: false|true; this is simulation-only parameter, for debug purpose only
parameter silicon_rev = "reve", // Valid values: reve|es
paramete... | 7.134348 |
module stratixv_hssi_pma_ser_att #(
parameter enable_debug_info = "false", //Valid values: false|true; this is simulation-only parameter, for debug purpose only
parameter ser_loopback = "loopback_disable", // Valid values: loopback_enable|loopback_disable
parameter ser_pdb = "power_down", // Valid values:... | 7.134348 |
module stratixv_hssi_refclk_divider #(
parameter user_base_address = 0, // Valid values: 0..2047
parameter divide_by = 1, // Valid values: 1|2
parameter avmm_group_channel_index = 0, // Valid values: 0..2
parameter use_default_base_address = "true", // Valid values: false|true
parameter refclk_c... | 7.134348 |
module strb_ram #(
parameter AWIDTH = 12, // Address Width
parameter DWIDTH = 128, // Data Width
parameter OREG_A = "TRUE", // Optional Port A output pipeline registers
parameter OREG_B = "TRUE" // Optional Port B output pipeline registers
) (
input clk,
input en_a, // ... | 9.338778 |
module strcmp_testbench ();
reg clk, rst;
parameter CPU_CLOCK_PERIOD = 20;
parameter CPU_CLOCK_FREQ = 1_000_000_000 / CPU_CLOCK_PERIOD;
initial clk = 0;
always #(CPU_CLOCK_PERIOD / 2) clk = ~clk;
wire [31:0] csr;
Riscv151 #(
.CPU_CLOCK_FREQ(CPU_CLOCK_FREQ),
.RESET_PC(32'h1000_0000)
) CPU (... | 7.239197 |
module stream2wb #(
parameter integer WB_N = 3,
// auto
parameter integer DL = (32 * WB_N) - 1,
parameter integer CL = WB_N - 1
) (
// Stream interface for command/response
input wire [7:0] rx_data,
input wire rx_valid,
output wire rx_ready,
output wire [7:0] tx_data,... | 7.80852 |
module StreamArbiter_1 (
input clk,
input reset
);
wire streamArbiter_2_io_output_ready;
wire streamArbiter_2_io_inputs_0_ready;
wire streamArbiter_2_io_inputs_1_ready;
wire streamArbiter_2_io_inputs_2_ready;
wire streamArbiter_2_io_output_valid;
wire [7:0] streamArbit... | 6.929245 |
module StreamArbiter (
input io_inputs_0_valid,
output io_inputs_0_ready,
input [7:0] io_inputs_0_payload,
input io_inputs_1_valid,
output io_inputs_1_ready,
input [7:0] io_inputs_1_payload,
input io_inputs_2_valid,
output io_inputs_2_ready,
i... | 6.929245 |
module StreamArbiter_2 (
input clk,
input reset
);
wire streamArbiter_1_io_output_ready;
wire streamArbiter_1_io_inputs_0_ready;
wire streamArbiter_1_io_inputs_1_ready;
wire streamArbiter_1_io_inputs_2_ready;
wire streamArbiter_1_io_output_valid;
wire [7:0] streamArbit... | 6.929245 |
module StreamArbiter (
input io_inputs_0_valid,
output io_inputs_0_ready,
input [7:0] io_inputs_0_payload,
input io_inputs_1_valid,
output io_inputs_1_ready,
input [7:0] io_inputs_1_payload,
input io_inputs_2_valid,
output io_inputs_2_ready,
i... | 6.929245 |
module StreamBuffer (
input rst_n,
input pclk,
input fclk,
input start,
input din_valid,
output din_ready,
input [7:0] din,
output [63:0] dout,
output dout_valid,
input dout_ready,
output burst_valid,
output [10:0] fifo_cnt
);
r... | 6.986803 |
module BufferCC_1 (
input io_dataIn,
output io_dataOut,
input clkb,
input rsta
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clkb or posedge rsta) begin
if (rsta) begin
buffers_0 <= 1'b1;
buff... | 6.574801 |
module BufferCC (
input io_dataIn,
output io_dataOut,
input clka,
input rsta
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clka or posedge rsta) begin
if (rsta) begin
buffers_0 <= 1'b0;
buffer... | 6.712921 |
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