code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module StreamDemux (
input [1:0] io_select,
input io_input_valid,
output reg io_input_ready,
input [7:0] io_input_payload,
output reg io_outputs_0_valid,
input io_outputs_0_ready,
output [7:0] io_outputs_0_payload,
output reg io_outputs_1_valid,
input io_outputs_1_ready,
output [7:0] io_outputs_1_payload,
output reg io_outputs_2_valid,
input io_outputs_2_ready,
output [7:0] io_outputs_2_payload
);
wire when_Stream_l884;
wire when_Stream_l884_1;
wire when_Stream_l884_2;
always @(*) begin
io_input_ready = 1'b0;
if (!when_Stream_l884) begin
io_input_ready = io_outputs_0_ready;
end
if (!when_Stream_l884_1) begin
io_input_ready = io_outputs_1_ready;
end
if (!when_Stream_l884_2) begin
io_input_ready = io_outputs_2_ready;
end
end
assign io_outputs_0_payload = io_input_payload;
assign when_Stream_l884 = (2'b00 != io_select);
always @(*) begin
if (when_Stream_l884) begin
io_outputs_0_valid = 1'b0;
end else begin
io_outputs_0_valid = io_input_valid;
end
end
assign io_outputs_1_payload = io_input_payload;
assign when_Stream_l884_1 = (2'b01 != io_select);
always @(*) begin
if (when_Stream_l884_1) begin
io_outputs_1_valid = 1'b0;
end else begin
io_outputs_1_valid = io_input_valid;
end
end
assign io_outputs_2_payload = io_input_payload;
assign when_Stream_l884_2 = (2'b10 != io_select);
always @(*) begin
if (when_Stream_l884_2) begin
io_outputs_2_valid = 1'b0;
end else begin
io_outputs_2_valid = io_input_valid;
end
end
endmodule
| 6.543044 |
module Streamer_Test_Bench ();
wire [7:0] d;
reg rxf, txe;
wire wr, rd, oe;
reg CLKIN;
reg SYS_CLK_100M;
Scaler_Streamer_Top_Block uut (
.ftdi_d (d),
.ftdi_oe (oe),
.ftdi_rd (rd),
.ftdi_wr (wr),
.ftdi_rxf(rxf),
.ftdi_txe(txe),
.ftdi_clk(CLKIN),
.sys_clk (SYS_CLK_100M)
);
reg [7:0] inputData;
reg sendDataFromHost;
//assign outputData = d;
assign d = (sendDataFromHost == 1'b1) ? inputData : 8'bZZZZZZZZ;
// Set up clocks.
initial begin
CLKIN = 0;
sendDataFromHost = 0;
forever begin
#8 CLKIN = ~CLKIN;
end
end
initial begin
SYS_CLK_100M = 0;
forever begin
#5 SYS_CLK_100M = ~SYS_CLK_100M;
end
end
initial begin
$display("Entering Initial state!");
rxf = 1;
txe = 1;
inputData = 8'hAA;
#100;
rxf = 0;
#10 sendDataFromHost = 1;
inputData = 8'hAA;
rxf = 0;
#50 rxf = 1;
sendDataFromHost = 0;
txe = 0;
#1000000000;
#1000000000;
#1000000000;
#1000000000;
#1000000000;
#1000000000;
sendDataFromHost = 1;
$finish;
end
endmodule
| 6.560573 |
module clk_wiz_0 (
clk_out1,
clk_out2,
reset,
locked,
clk_in1
);
output clk_out1;
output clk_out2;
input reset;
output locked;
input clk_in1;
(* IBUF_LOW_PWR *)wire clk_in1;
wire clk_out1;
wire clk_out2;
wire locked;
wire reset;
clk_wiz_0_clk_wiz_0_clk_wiz inst (
.clk_in1(clk_in1),
.clk_out1(clk_out1),
.clk_out2(clk_out2),
.locked(locked),
.reset(reset)
);
endmodule
| 6.750754 |
module StreamFifo_2 (
input din_valid,
output din_ready,
input [7:0] din_payload,
output dout_valid,
input dout_ready,
output [7:0] dout_payload,
input clk,
input reset
);
wire din_fifo_io_push_ready;
wire din_fifo_io_pop_valid;
wire [7:0] din_fifo_io_pop_payload;
wire [4:0] din_fifo_io_occupancy;
StreamFifoLowLatency din_fifo (
.io_push_valid (din_valid), //i
.io_push_ready (din_fifo_io_push_ready), //o
.io_push_payload(din_payload[7:0]), //i
.io_pop_valid (din_fifo_io_pop_valid), //o
.io_pop_ready (dout_ready), //i
.io_pop_payload (din_fifo_io_pop_payload[7:0]), //o
.io_flush (1'b0), //i
.io_occupancy (din_fifo_io_occupancy[4:0]), //o
.clk (clk), //i
.reset (reset) //i
);
assign din_ready = din_fifo_io_push_ready;
assign dout_valid = din_fifo_io_pop_valid;
assign dout_payload = din_fifo_io_pop_payload;
endmodule
| 6.554979 |
module StreamFifo_3 (
input io_din_valid,
output io_din_ready,
input [7:0] io_din_payload,
output io_dout_valid,
input io_dout_ready,
output [7:0] io_dout_payload,
input a_clk,
input a_reset,
input b_clk
);
wire myFifo_io_push_ready;
wire myFifo_io_pop_valid;
wire [7:0] myFifo_io_pop_payload;
wire [7:0] myFifo_io_pushOccupancy;
wire [7:0] myFifo_io_popOccupancy;
StreamFifoCC myFifo (
.io_push_valid (io_din_valid), //i
.io_push_ready (myFifo_io_push_ready), //o
.io_push_payload (io_din_payload[7:0]), //i
.io_pop_valid (myFifo_io_pop_valid), //o
.io_pop_ready (io_dout_ready), //i
.io_pop_payload (myFifo_io_pop_payload[7:0]), //o
.io_pushOccupancy(myFifo_io_pushOccupancy[7:0]), //o
.io_popOccupancy (myFifo_io_popOccupancy[7:0]), //o
.a_clk (a_clk), //i
.a_reset (a_reset), //i
.b_clk (b_clk) //i
);
assign io_din_ready = myFifo_io_push_ready;
assign io_dout_valid = myFifo_io_pop_valid;
assign io_dout_payload = myFifo_io_pop_payload;
endmodule
| 6.965891 |
module BufferCC_1 (
input io_dataIn,
output io_dataOut,
input b_clk,
input a_reset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge b_clk or posedge a_reset) begin
if (a_reset) begin
buffers_0 <= 1'b1;
buffers_1 <= 1'b1;
end else begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
end
endmodule
| 6.574801 |
module BufferCC (
input [7:0] io_dataIn,
output [7:0] io_dataOut,
input a_clk,
input a_reset
);
(* async_reg = "true" *)reg [7:0] buffers_0;
(* async_reg = "true" *)reg [7:0] buffers_1;
assign io_dataOut = buffers_1;
always @(posedge a_clk or posedge a_reset) begin
if (a_reset) begin
buffers_0 <= 8'h0;
buffers_1 <= 8'h0;
end else begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
end
endmodule
| 6.712921 |
module StreamFIFO_tb;
// Parameters
localparam Depth = 8;
localparam WordWidth = 64;
// Ports
reg enq_vld_i = 0;
reg [WordWidth-1:0] enq_payload_i;
wire enq_rdy_o;
wire deq_vld_o;
wire [WordWidth-1:0] deq_payload_o;
reg deq_rdy_i = 0;
reg flush_i = 0;
reg clk = 0;
reg rstn = 0;
bit [WordWidth-1:0] golden_fifo[$];
bit [WordWidth-1:0] random_payload;
bit [WordWidth-1:0] golden_fifo_front;
int iter = 1000000;
initial begin
begin
#10 rstn = 1'b1;
repeat (iter) begin : random_test
@(negedge clk);
enq_vld_i = 1'b0;
deq_rdy_i = 1'b0;
if ($urandom_range(0, 1) && deq_vld_o) begin : test_deq
deq_rdy_i = 1'b1;
golden_fifo_front = golden_fifo.pop_front();
CHECK_EQUALATION :
assert (deq_payload_o == golden_fifo_front)
else begin
$fatal("\n Error: Fail when check equalation, ours[%x] -- gloden[%x]", deq_payload_o,
golden_fifo_front);
end
;
end
if ($urandom_range(0, 1) && enq_rdy_o) begin : test_push
random_payload = $urandom();
enq_vld_i = 1'b1;
enq_payload_i = random_payload;
golden_fifo.push_back(random_payload);
end
end
$info("\n PASS after %d iter \n", iter);
$finish;
end
end
StreamFIFO #(
.Depth(Depth),
.WordWidth(WordWidth)
) StreamFIFO_dut (
.enq_vld_i(enq_vld_i),
.enq_payload_i(enq_payload_i),
.enq_rdy_o(enq_rdy_o),
.deq_vld_o(deq_vld_o),
.deq_payload_o(deq_payload_o),
.deq_rdy_i(deq_rdy_i),
.flush_i(flush_i),
.clk(clk),
.rstn(rstn)
);
`ifdef DUMPON
initial begin : GEN_WAVEFORM
$fsdbDumpfile("StreamFIFO_tb.fsdb");
$fsdbDumpvars(0, StreamFIFO_tb);
$fsdbDumpvars("+mda");
$fsdbDumpvars("+all");
$fsdbDumpon();
end
`endif
always #20 clk = !clk;
endmodule
| 6.649791 |
module TransposedStreamingFIR ( // @[:@3.2]
input clock, // @[:@4.4]
input [ 9:0] io_input, // @[:@6.4]
output [19:0] io_output, // @[:@6.4]
input [ 9:0] io_taps_0, // @[:@6.4]
input [ 9:0] io_taps_1, // @[:@6.4]
input [ 9:0] io_taps_2 // @[:@6.4]
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
wire [19:0] products_1 = $signed(
io_input
) * $signed(
io_taps_1
); // @[SIntTypeClass.scala 44:41:@12.4]
wire [19:0] products_2 = $signed(
io_input
) * $signed(
io_taps_0
); // @[SIntTypeClass.scala 44:41:@13.4]
reg [19:0] last; // @[TransposedStreamingFIR.scala 62:17:@14.4]
reg [19:0] _T_14; // @[TransposedStreamingFIR.scala 64:18:@15.4]
reg [19:0] _T_19; // @[TransposedStreamingFIR.scala 64:18:@20.4]
assign io_output = last;
always @(posedge clock) begin
last <= $signed(_T_19) + $signed(products_2); // @[SIntTypeClass.scala 18:40:@24.4]
_T_14 <= $signed(io_input) * $signed(io_taps_2); // @[SIntTypeClass.scala 44:41:@11.4]
_T_19 <= $signed(_T_14) + $signed(products_1); // @[SIntTypeClass.scala 18:40:@19.4]
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
last = _RAND_0[19:0];
_RAND_1 = {1{`RANDOM}};
_T_14 = _RAND_1[19:0];
_RAND_2 = {1{`RANDOM}};
_T_19 = _RAND_2[19:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 7.27609 |
module TransposedStreamingFIR (
input clock,
input [ 9:0] io_input,
output [19:0] io_output,
input [ 9:0] io_taps_0,
input [ 9:0] io_taps_1,
input [ 9:0] io_taps_2
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
wire [19:0] products_1 = $signed(io_input) * $signed(io_taps_1); // @[SIntTypeClass.scala 44:41]
wire [19:0] products_2 = $signed(io_input) * $signed(io_taps_0); // @[SIntTypeClass.scala 44:41]
reg [19:0] last; // @[TransposedStreamingFIR.scala 62:17]
reg [19:0] _T_14; // @[TransposedStreamingFIR.scala 64:18]
reg [19:0] _T_19; // @[TransposedStreamingFIR.scala 64:18]
assign io_output = last; // @[TransposedStreamingFIR.scala 69:13]
always @(posedge clock) begin
last <= $signed(_T_19) + $signed(products_2); // @[SIntTypeClass.scala 18:40]
_T_14 <= $signed(io_input) * $signed(io_taps_2); // @[SIntTypeClass.scala 44:41]
_T_19 <= $signed(_T_14) + $signed(products_1); // @[SIntTypeClass.scala 18:40]
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
last = _RAND_0[19:0];
_RAND_1 = {1{`RANDOM}};
_T_14 = _RAND_1[19:0];
_RAND_2 = {1{`RANDOM}};
_T_19 = _RAND_2[19:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 7.27609 |
module StreamingFCLayer_Batch_0_Matrix_Vector_Actbkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 10;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_wenlong/code_gen_ipgen_StreamingFCLayer_Batch_0_p9az_gje/project_StreamingFCLayer_Batch_0/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_0_Matrix_Vector_Actbkb_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_0_Matrix_Vector_Actbkb (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd10;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_0_Matrix_Vector_Actbkb_rom StreamingFCLayer_Batch_0_Matrix_Vector_Actbkb_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_0_Matrix_Vector_Actcud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_wenlong/code_gen_ipgen_StreamingFCLayer_Batch_0_p9az_gje/project_StreamingFCLayer_Batch_0/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_0_Matrix_Vector_Actcud_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_0_Matrix_Vector_Actcud (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_0_Matrix_Vector_Actcud_rom StreamingFCLayer_Batch_0_Matrix_Vector_Actcud_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_0_Matrix_Vector_ActdEe_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_wenlong/code_gen_ipgen_StreamingFCLayer_Batch_0_p9az_gje/project_StreamingFCLayer_Batch_0/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_0_Matrix_Vector_ActdEe_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_0_Matrix_Vector_ActdEe (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_0_Matrix_Vector_ActdEe_rom StreamingFCLayer_Batch_0_Matrix_Vector_ActdEe_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_0_mux_42_13_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [12 : 0] din0,
input [12 : 0] din1,
input [12 : 0] din2,
input [12 : 0] din3,
input [ 1 : 0] din4,
output [12 : 0] dout
);
// puts internal signals
wire [ 1 : 0] sel;
// level 1 signals
wire [12 : 0] mux_1_0;
wire [12 : 0] mux_1_1;
// level 2 signals
wire [12 : 0] mux_2_0;
assign sel = din4;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
// output logic
assign dout = mux_2_0;
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_0_mux_94_24_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
din7_WIDTH = 32,
din8_WIDTH = 32,
din9_WIDTH = 32,
dout_WIDTH = 32
) (
input [23 : 0] din0,
input [23 : 0] din1,
input [23 : 0] din2,
input [23 : 0] din3,
input [23 : 0] din4,
input [23 : 0] din5,
input [23 : 0] din6,
input [23 : 0] din7,
input [23 : 0] din8,
input [ 3 : 0] din9,
output [23 : 0] dout
);
// puts internal signals
wire [ 3 : 0] sel;
// level 1 signals
wire [23 : 0] mux_1_0;
wire [23 : 0] mux_1_1;
wire [23 : 0] mux_1_2;
wire [23 : 0] mux_1_3;
wire [23 : 0] mux_1_4;
// level 2 signals
wire [23 : 0] mux_2_0;
wire [23 : 0] mux_2_1;
wire [23 : 0] mux_2_2;
// level 3 signals
wire [23 : 0] mux_3_0;
wire [23 : 0] mux_3_1;
// level 4 signals
wire [23 : 0] mux_4_0;
assign sel = din9;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
assign mux_1_2 = (sel[0] == 0) ? din4 : din5;
assign mux_1_3 = (sel[0] == 0) ? din6 : din7;
assign mux_1_4 = din8;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
assign mux_2_1 = (sel[1] == 0) ? mux_1_2 : mux_1_3;
assign mux_2_2 = mux_1_4;
// Generate level 3 logic
assign mux_3_0 = (sel[2] == 0) ? mux_2_0 : mux_2_1;
assign mux_3_1 = mux_2_2;
// Generate level 4 logic
assign mux_4_0 = (sel[3] == 0) ? mux_3_0 : mux_3_1;
// output logic
assign dout = mux_4_0;
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_0_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire [DataWidth-1:0] B_V_data_1_data_in;
reg [DataWidth-1:0] B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg [DataWidth-1:0] B_V_data_1_payload_A;
reg [DataWidth-1:0] B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_0_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
reg B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg B_V_data_1_payload_A;
reg B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_0_StreamingFCLayer_eOg #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
din7_WIDTH = 32,
din8_WIDTH = 32,
din9_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
input [7 : 0] din1,
input [7 : 0] din2,
input [7 : 0] din3,
input [7 : 0] din4,
input [7 : 0] din5,
input [7 : 0] din6,
input [7 : 0] din7,
input [7 : 0] din8,
input [3 : 0] din9,
output [7 : 0] dout
);
// puts internal signals
wire [3 : 0] sel;
// level 1 signals
wire [7 : 0] mux_1_0;
wire [7 : 0] mux_1_1;
wire [7 : 0] mux_1_2;
wire [7 : 0] mux_1_3;
wire [7 : 0] mux_1_4;
// level 2 signals
wire [7 : 0] mux_2_0;
wire [7 : 0] mux_2_1;
wire [7 : 0] mux_2_2;
// level 3 signals
wire [7 : 0] mux_3_0;
wire [7 : 0] mux_3_1;
// level 4 signals
wire [7 : 0] mux_4_0;
assign sel = din9;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
assign mux_1_2 = (sel[0] == 0) ? din4 : din5;
assign mux_1_3 = (sel[0] == 0) ? din6 : din7;
assign mux_1_4 = din8;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
assign mux_2_1 = (sel[1] == 0) ? mux_1_2 : mux_1_3;
assign mux_2_2 = mux_1_4;
// Generate level 3 logic
assign mux_3_0 = (sel[2] == 0) ? mux_2_0 : mux_2_1;
assign mux_3_1 = mux_2_2;
// Generate level 4 logic
assign mux_4_0 = (sel[3] == 0) ? mux_3_0 : mux_3_1;
// output logic
assign dout = mux_4_0;
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_0_StreamingFCLayer_fYi_Mul_LUT_0 (
a,
b,
p
);
input [8 - 1 : 0] a;
input [2 - 1 : 0] b;
output [10 - 1 : 0] p;
assign p = $signed({1'b0, a}) * $signed(b);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_0_StreamingFCLayer_fYi (
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input [din0_WIDTH - 1:0] din0;
input [din1_WIDTH - 1:0] din1;
output [dout_WIDTH - 1:0] dout;
StreamingFCLayer_Batch_0_StreamingFCLayer_fYi_Mul_LUT_0 StreamingFCLayer_Batch_0_StreamingFCLayer_fYi_Mul_LUT_0_U(
.a(din0),
.b(din1),
.p(dout)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_0_StreamingFCLayer_g8j_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 2;
parameter AWIDTH = 8;
parameter MEM_SIZE = 144;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_wenlong/code_gen_ipgen_StreamingFCLayer_Batch_0_p9az_gje/project_StreamingFCLayer_Batch_0/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_0_StreamingFCLayer_g8j_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_0_StreamingFCLayer_g8j (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd2;
parameter AddressRange = 32'd144;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_0_StreamingFCLayer_g8j_rom StreamingFCLayer_Batch_0_StreamingFCLayer_g8j_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_1_Matrix_Vector_Actbkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 5;
parameter AWIDTH = 5;
parameter MEM_SIZE = 20;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_wenlong/code_gen_ipgen_StreamingFCLayer_Batch_1_m8rnl_py/project_StreamingFCLayer_Batch_1/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_1_Matrix_Vector_Actbkb_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_1_Matrix_Vector_Actbkb (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd5;
parameter AddressRange = 32'd20;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_1_Matrix_Vector_Actbkb_rom StreamingFCLayer_Batch_1_Matrix_Vector_Actbkb_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_1_Matrix_Vector_Actcud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 5;
parameter AWIDTH = 5;
parameter MEM_SIZE = 20;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_wenlong/code_gen_ipgen_StreamingFCLayer_Batch_1_m8rnl_py/project_StreamingFCLayer_Batch_1/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_1_Matrix_Vector_Actcud_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_1_Matrix_Vector_Actcud (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd5;
parameter AddressRange = 32'd20;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_1_Matrix_Vector_Actcud_rom StreamingFCLayer_Batch_1_Matrix_Vector_Actcud_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_1_Matrix_Vector_ActdEe_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 5;
parameter AWIDTH = 5;
parameter MEM_SIZE = 20;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_wenlong/code_gen_ipgen_StreamingFCLayer_Batch_1_m8rnl_py/project_StreamingFCLayer_Batch_1/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_1_Matrix_Vector_ActdEe_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_1_Matrix_Vector_ActdEe (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd5;
parameter AddressRange = 32'd20;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_1_Matrix_Vector_ActdEe_rom StreamingFCLayer_Batch_1_Matrix_Vector_ActdEe_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_1_mux_42_12_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [11 : 0] din0,
input [11 : 0] din1,
input [11 : 0] din2,
input [11 : 0] din3,
input [ 1 : 0] din4,
output [11 : 0] dout
);
// puts internal signals
wire [ 1 : 0] sel;
// level 1 signals
wire [11 : 0] mux_1_0;
wire [11 : 0] mux_1_1;
// level 2 signals
wire [11 : 0] mux_2_0;
assign sel = din4;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
// output logic
assign dout = mux_2_0;
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_1_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire [DataWidth-1:0] B_V_data_1_data_in;
reg [DataWidth-1:0] B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg [DataWidth-1:0] B_V_data_1_payload_A;
reg [DataWidth-1:0] B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_1_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
reg B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg B_V_data_1_payload_A;
reg B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_1_StreamingFCLayer_eOg #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
din7_WIDTH = 32,
din8_WIDTH = 32,
din9_WIDTH = 32,
dout_WIDTH = 32
) (
input [31 : 0] din0,
input [31 : 0] din1,
input [31 : 0] din2,
input [31 : 0] din3,
input [31 : 0] din4,
input [31 : 0] din5,
input [31 : 0] din6,
input [31 : 0] din7,
input [31 : 0] din8,
input [ 3 : 0] din9,
output [31 : 0] dout
);
// puts internal signals
wire [ 3 : 0] sel;
// level 1 signals
wire [31 : 0] mux_1_0;
wire [31 : 0] mux_1_1;
wire [31 : 0] mux_1_2;
wire [31 : 0] mux_1_3;
wire [31 : 0] mux_1_4;
// level 2 signals
wire [31 : 0] mux_2_0;
wire [31 : 0] mux_2_1;
wire [31 : 0] mux_2_2;
// level 3 signals
wire [31 : 0] mux_3_0;
wire [31 : 0] mux_3_1;
// level 4 signals
wire [31 : 0] mux_4_0;
assign sel = din9;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
assign mux_1_2 = (sel[0] == 0) ? din4 : din5;
assign mux_1_3 = (sel[0] == 0) ? din6 : din7;
assign mux_1_4 = din8;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
assign mux_2_1 = (sel[1] == 0) ? mux_1_2 : mux_1_3;
assign mux_2_2 = mux_1_4;
// Generate level 3 logic
assign mux_3_0 = (sel[2] == 0) ? mux_2_0 : mux_2_1;
assign mux_3_1 = mux_2_2;
// Generate level 4 logic
assign mux_4_0 = (sel[3] == 0) ? mux_3_0 : mux_3_1;
// output logic
assign dout = mux_4_0;
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_1_StreamingFCLayer_fYi_Mul_LUT_0 (
a,
b,
p
);
input [2 - 1 : 0] a;
input [2 - 1 : 0] b;
output [4 - 1 : 0] p;
assign p = $signed({1'b0, a}) * $signed(b);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_1_StreamingFCLayer_fYi (
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input [din0_WIDTH - 1:0] din0;
input [din1_WIDTH - 1:0] din1;
output [dout_WIDTH - 1:0] dout;
StreamingFCLayer_Batch_1_StreamingFCLayer_fYi_Mul_LUT_0 StreamingFCLayer_Batch_1_StreamingFCLayer_fYi_Mul_LUT_0_U(
.a(din0),
.b(din1),
.p(dout)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_1_StreamingFCLayer_g8j_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 8;
parameter MEM_SIZE = 180;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_wenlong/code_gen_ipgen_StreamingFCLayer_Batch_1_m8rnl_py/project_StreamingFCLayer_Batch_1/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_1_StreamingFCLayer_g8j_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_1_StreamingFCLayer_g8j (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd180;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_1_StreamingFCLayer_g8j_rom StreamingFCLayer_Batch_1_StreamingFCLayer_g8j_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Actbkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 3;
parameter AWIDTH = 5;
parameter MEM_SIZE = 30;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_wenlong/code_gen_ipgen_StreamingFCLayer_Batch_2__0df8fwp/project_StreamingFCLayer_Batch_2/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_2_Matrix_Vector_Actbkb_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Actbkb (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd3;
parameter AddressRange = 32'd30;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_2_Matrix_Vector_Actbkb_rom StreamingFCLayer_Batch_2_Matrix_Vector_Actbkb_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Actcud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 4;
parameter AWIDTH = 5;
parameter MEM_SIZE = 30;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_wenlong/code_gen_ipgen_StreamingFCLayer_Batch_2__0df8fwp/project_StreamingFCLayer_Batch_2/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_2_Matrix_Vector_Actcud_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Actcud (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd4;
parameter AddressRange = 32'd30;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_2_Matrix_Vector_Actcud_rom StreamingFCLayer_Batch_2_Matrix_Vector_Actcud_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_ActdEe_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 5;
parameter AWIDTH = 5;
parameter MEM_SIZE = 30;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_wenlong/code_gen_ipgen_StreamingFCLayer_Batch_2__0df8fwp/project_StreamingFCLayer_Batch_2/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_2_Matrix_Vector_ActdEe_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_ActdEe (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd5;
parameter AddressRange = 32'd30;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_2_Matrix_Vector_ActdEe_rom StreamingFCLayer_Batch_2_Matrix_Vector_ActdEe_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apbkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 10;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_2_9ao_flvf/project_StreamingFCLayer_Batch_2/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apbkb_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apbkb(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd10;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apbkb_rom StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apbkb_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apcud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_2_9ao_flvf/project_StreamingFCLayer_Batch_2/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apcud_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apcud(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apcud_rom StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apcud_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apdEe_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 12;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_2_9ao_flvf/project_StreamingFCLayer_Batch_2/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apdEe_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apdEe(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd12;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apdEe_rom StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apdEe_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apeOg_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_2_9ao_flvf/project_StreamingFCLayer_Batch_2/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apeOg_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apeOg(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apeOg_rom StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apeOg_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apfYi_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_2_9ao_flvf/project_StreamingFCLayer_Batch_2/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apfYi_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apfYi(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apfYi_rom StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apfYi_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apg8j_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 10;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_2_9ao_flvf/project_StreamingFCLayer_Batch_2/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apg8j_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apg8j(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd10;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apg8j_rom StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apg8j_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_aphbi_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 12;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_2_9ao_flvf/project_StreamingFCLayer_Batch_2/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_aphbi_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_aphbi(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd12;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_aphbi_rom StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_aphbi_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apibs_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_2_9ao_flvf/project_StreamingFCLayer_Batch_2/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apibs_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apibs(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apibs_rom StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apibs_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apjbC_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 12;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_2_9ao_flvf/project_StreamingFCLayer_Batch_2/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apjbC_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apjbC(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd12;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apjbC_rom StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apjbC_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apkbM_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 12;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_2_9ao_flvf/project_StreamingFCLayer_Batch_2/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apkbM_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apkbM(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd12;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apkbM_rom StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apkbM_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_aplbW_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_2_9ao_flvf/project_StreamingFCLayer_Batch_2/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_aplbW_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_aplbW(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_aplbW_rom StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_aplbW_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apmb6_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_2_9ao_flvf/project_StreamingFCLayer_Batch_2/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apmb6_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apmb6(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apmb6_rom StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apmb6_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apncg_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_2_9ao_flvf/project_StreamingFCLayer_Batch_2/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apncg_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apncg(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apncg_rom StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apncg_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apocq_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 7;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_2_9ao_flvf/project_StreamingFCLayer_Batch_2/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apocq_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apocq(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd7;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apocq_rom StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apocq_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_appcA_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_2_9ao_flvf/project_StreamingFCLayer_Batch_2/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_appcA_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_appcA(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_appcA_rom StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_appcA_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apqcK_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 12;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_2_9ao_flvf/project_StreamingFCLayer_Batch_2/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apqcK_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apqcK(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd12;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apqcK_rom StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apqcK_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire [DataWidth-1:0] B_V_data_1_data_in;
reg [DataWidth-1:0] B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg [DataWidth-1:0] B_V_data_1_payload_A;
reg [DataWidth-1:0] B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
reg B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg B_V_data_1_payload_A;
reg B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_StreamingFCLayer_eOg #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
din7_WIDTH = 32,
din8_WIDTH = 32,
din9_WIDTH = 32,
dout_WIDTH = 32
) (
input [39 : 0] din0,
input [39 : 0] din1,
input [39 : 0] din2,
input [39 : 0] din3,
input [39 : 0] din4,
input [39 : 0] din5,
input [39 : 0] din6,
input [39 : 0] din7,
input [39 : 0] din8,
input [ 3 : 0] din9,
output [39 : 0] dout
);
// puts internal signals
wire [ 3 : 0] sel;
// level 1 signals
wire [39 : 0] mux_1_0;
wire [39 : 0] mux_1_1;
wire [39 : 0] mux_1_2;
wire [39 : 0] mux_1_3;
wire [39 : 0] mux_1_4;
// level 2 signals
wire [39 : 0] mux_2_0;
wire [39 : 0] mux_2_1;
wire [39 : 0] mux_2_2;
// level 3 signals
wire [39 : 0] mux_3_0;
wire [39 : 0] mux_3_1;
// level 4 signals
wire [39 : 0] mux_4_0;
assign sel = din9;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
assign mux_1_2 = (sel[0] == 0) ? din4 : din5;
assign mux_1_3 = (sel[0] == 0) ? din6 : din7;
assign mux_1_4 = din8;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
assign mux_2_1 = (sel[1] == 0) ? mux_1_2 : mux_1_3;
assign mux_2_2 = mux_1_4;
// Generate level 3 logic
assign mux_3_0 = (sel[2] == 0) ? mux_2_0 : mux_2_1;
assign mux_3_1 = mux_2_2;
// Generate level 4 logic
assign mux_4_0 = (sel[3] == 0) ? mux_3_0 : mux_3_1;
// output logic
assign dout = mux_4_0;
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_StreamingFCLayer_fYi_Mul_LUT_0 (
a,
b,
p
);
input [2 - 1 : 0] a;
input [2 - 1 : 0] b;
output [4 - 1 : 0] p;
assign p = $signed({1'b0, a}) * $signed(b);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_StreamingFCLayer_fYi (
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input [din0_WIDTH - 1:0] din0;
input [din1_WIDTH - 1:0] din1;
output [dout_WIDTH - 1:0] dout;
StreamingFCLayer_Batch_2_StreamingFCLayer_fYi_Mul_LUT_0 StreamingFCLayer_Batch_2_StreamingFCLayer_fYi_Mul_LUT_0_U(
.a(din0),
.b(din1),
.p(dout)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_StreamingFCLayer_g8j_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 40;
parameter AWIDTH = 9;
parameter MEM_SIZE = 270;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_wenlong/code_gen_ipgen_StreamingFCLayer_Batch_2__0df8fwp/project_StreamingFCLayer_Batch_2/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_2_StreamingFCLayer_g8j_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_StreamingFCLayer_g8j (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd40;
parameter AddressRange = 32'd270;
parameter AddressWidth = 32'd9;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_2_StreamingFCLayer_g8j_rom StreamingFCLayer_Batch_2_StreamingFCLayer_g8j_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Actbkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 3;
parameter AWIDTH = 6;
parameter MEM_SIZE = 60;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_wenlong/code_gen_ipgen_StreamingFCLayer_Batch_3_qmc881x2/project_StreamingFCLayer_Batch_3/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_3_Matrix_Vector_Actbkb_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Actbkb (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd3;
parameter AddressRange = 32'd60;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_3_Matrix_Vector_Actbkb_rom StreamingFCLayer_Batch_3_Matrix_Vector_Actbkb_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Actcud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 4;
parameter AWIDTH = 6;
parameter MEM_SIZE = 60;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./StreamingFCLayer_Batch_3_Matrix_Vector_Actcud_rom.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Actcud (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd4;
parameter AddressRange = 32'd60;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_3_Matrix_Vector_Actcud_rom StreamingFCLayer_Batch_3_Matrix_Vector_Actcud_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_ActdEe_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 5;
parameter AWIDTH = 6;
parameter MEM_SIZE = 60;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_wenlong/code_gen_ipgen_StreamingFCLayer_Batch_3_qmc881x2/project_StreamingFCLayer_Batch_3/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_3_Matrix_Vector_ActdEe_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_ActdEe (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd5;
parameter AddressRange = 32'd60;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_3_Matrix_Vector_ActdEe_rom StreamingFCLayer_Batch_3_Matrix_Vector_ActdEe_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_abkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 9;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_3_rdf8am5y/project_StreamingFCLayer_Batch_3/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_abkb_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_abkb(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd9;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_abkb_rom StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_abkb_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_acud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_3_rdf8am5y/project_StreamingFCLayer_Batch_3/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_acud_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_acud(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_acud_rom StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_acud_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_adEe_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 12;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_3_rdf8am5y/project_StreamingFCLayer_Batch_3/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_adEe_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_adEe(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd12;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_adEe_rom StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_adEe_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_aeOg_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_3_rdf8am5y/project_StreamingFCLayer_Batch_3/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_aeOg_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_aeOg(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_aeOg_rom StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_aeOg_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_afYi_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 10;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh(
"/tmp/finn_dev_nm/code_gen_ipgen_StreamingFCLayer_Batch_3_rdf8am5y/project_StreamingFCLayer_Batch_3/sol1/impl/ip/hdl/verilog/StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_afYi_rom.dat",
ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_afYi(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd10;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_afYi_rom StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_afYi_rom_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0)
);
endmodule
| 6.840686 |
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