code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module StreamDemux (
input [1:0] io_select,
input io_input_valid,
output reg io_input_ready,
input [7:0] io_input_payload,
output reg io_outputs_0_valid,
input io_outputs_0_ready,
output [7:0] io_outputs_0_payload,
output reg io_outpu... | 6.543044 |
module Streamer_Test_Bench ();
wire [7:0] d;
reg rxf, txe;
wire wr, rd, oe;
reg CLKIN;
reg SYS_CLK_100M;
Scaler_Streamer_Top_Block uut (
.ftdi_d (d),
.ftdi_oe (oe),
.ftdi_rd (rd),
.ftdi_wr (wr),
.ftdi_rxf(rxf),
.ftdi_txe(txe),
.ftdi_clk(CLKIN),
.sys_clk (S... | 6.560573 |
module clk_wiz_0 (
clk_out1,
clk_out2,
reset,
locked,
clk_in1
);
output clk_out1;
output clk_out2;
input reset;
output locked;
input clk_in1;
(* IBUF_LOW_PWR *)wire clk_in1;
wire clk_out1;
wire clk_out2;
wire locked;
wire reset;
clk_wiz_0_clk_wiz_0_clk_wiz inst (
.clk_i... | 6.750754 |
module StreamFifo_2 (
input din_valid,
output din_ready,
input [7:0] din_payload,
output dout_valid,
input dout_ready,
output [7:0] dout_payload,
input clk,
input reset
);
wire din_fifo_io_push_ready;
wire din_fifo_io_pop_valid;
... | 6.554979 |
module StreamFifo_3 (
input io_din_valid,
output io_din_ready,
input [7:0] io_din_payload,
output io_dout_valid,
input io_dout_ready,
output [7:0] io_dout_payload,
input a_clk,
input a_reset,
input b_clk
);
wire myFifo_io_push_... | 6.965891 |
module BufferCC_1 (
input io_dataIn,
output io_dataOut,
input b_clk,
input a_reset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge b_clk or posedge a_reset) begin
if (a_reset) begin
buffers_0 <= 1'b1;... | 6.574801 |
module BufferCC (
input [7:0] io_dataIn,
output [7:0] io_dataOut,
input a_clk,
input a_reset
);
(* async_reg = "true" *)reg [7:0] buffers_0;
(* async_reg = "true" *)reg [7:0] buffers_1;
assign io_dataOut = buffers_1;
always @(posedge a_clk or posedge a_reset) begin
if (a_res... | 6.712921 |
module StreamFIFO_tb;
// Parameters
localparam Depth = 8;
localparam WordWidth = 64;
// Ports
reg enq_vld_i = 0;
reg [WordWidth-1:0] enq_payload_i;
wire enq_rdy_o;
wire deq_vld_o;
wire [WordWidth-1:0] deq_payload_o;
reg deq_rdy_i = 0;
reg flush_i = 0;
reg clk = 0;
reg rstn = 0;
bit [WordW... | 6.649791 |
module TransposedStreamingFIR ( // @[:@3.2]
input clock, // @[:@4.4]
input [ 9:0] io_input, // @[:@6.4]
output [19:0] io_output, // @[:@6.4]
input [ 9:0] io_taps_0, // @[:@6.4]
input [ 9:0] io_taps_1, // @[:@6.4]
input [ 9:0] io_taps_2 // @[:@6.4]
);
`ifdef RANDOMIZE_REG... | 7.27609 |
module TransposedStreamingFIR (
input clock,
input [ 9:0] io_input,
output [19:0] io_output,
input [ 9:0] io_taps_0,
input [ 9:0] io_taps_1,
input [ 9:0] io_taps_2
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_... | 7.27609 |
module StreamingFCLayer_Batch_0_Matrix_Vector_Actbkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 10;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:ME... | 6.840686 |
module StreamingFCLayer_Batch_0_Matrix_Vector_Actbkb (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd10;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;... | 6.840686 |
module StreamingFCLayer_Batch_0_Matrix_Vector_Actcud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:ME... | 6.840686 |
module StreamingFCLayer_Batch_0_Matrix_Vector_Actcud (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;... | 6.840686 |
module StreamingFCLayer_Batch_0_Matrix_Vector_ActdEe_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:ME... | 6.840686 |
module StreamingFCLayer_Batch_0_Matrix_Vector_ActdEe (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;... | 6.840686 |
module StreamingFCLayer_Batch_0_mux_42_13_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [12 : 0] di... | 6.840686 |
module StreamingFCLayer_Batch_0_mux_94_24_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH ... | 6.840686 |
module StreamingFCLayer_Batch_0_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_s... | 6.840686 |
module StreamingFCLayer_Batch_0_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1... | 6.840686 |
module StreamingFCLayer_Batch_0_StreamingFCLayer_eOg #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6... | 6.840686 |
module StreamingFCLayer_Batch_0_StreamingFCLayer_fYi_Mul_LUT_0 (
a,
b,
p
);
input [8 - 1 : 0] a;
input [2 - 1 : 0] b;
output [10 - 1 : 0] p;
assign p = $signed({1'b0, a}) * $signed(b);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_0_StreamingFCLayer_fYi (
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input [din0_WIDTH - 1:0] din0;
input [din1_WIDTH - 1:0] din1;
output [dout_... | 6.840686 |
module StreamingFCLayer_Batch_0_StreamingFCLayer_g8j_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 2;
parameter AWIDTH = 8;
parameter MEM_SIZE = 144;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:ME... | 6.840686 |
module StreamingFCLayer_Batch_0_StreamingFCLayer_g8j (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd2;
parameter AddressRange = 32'd144;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;... | 6.840686 |
module StreamingFCLayer_Batch_1_Matrix_Vector_Actbkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 5;
parameter AWIDTH = 5;
parameter MEM_SIZE = 20;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM... | 6.840686 |
module StreamingFCLayer_Batch_1_Matrix_Vector_Actbkb (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd5;
parameter AddressRange = 32'd20;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
... | 6.840686 |
module StreamingFCLayer_Batch_1_Matrix_Vector_Actcud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 5;
parameter AWIDTH = 5;
parameter MEM_SIZE = 20;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM... | 6.840686 |
module StreamingFCLayer_Batch_1_Matrix_Vector_Actcud (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd5;
parameter AddressRange = 32'd20;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
... | 6.840686 |
module StreamingFCLayer_Batch_1_Matrix_Vector_ActdEe_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 5;
parameter AWIDTH = 5;
parameter MEM_SIZE = 20;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM... | 6.840686 |
module StreamingFCLayer_Batch_1_Matrix_Vector_ActdEe (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd5;
parameter AddressRange = 32'd20;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
... | 6.840686 |
module StreamingFCLayer_Batch_1_mux_42_12_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [11 : 0] di... | 6.840686 |
module StreamingFCLayer_Batch_1_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_s... | 6.840686 |
module StreamingFCLayer_Batch_1_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1... | 6.840686 |
module StreamingFCLayer_Batch_1_StreamingFCLayer_eOg #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6... | 6.840686 |
module StreamingFCLayer_Batch_1_StreamingFCLayer_fYi_Mul_LUT_0 (
a,
b,
p
);
input [2 - 1 : 0] a;
input [2 - 1 : 0] b;
output [4 - 1 : 0] p;
assign p = $signed({1'b0, a}) * $signed(b);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_1_StreamingFCLayer_fYi (
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input [din0_WIDTH - 1:0] din0;
input [din1_WIDTH - 1:0] din1;
output [dout_... | 6.840686 |
module StreamingFCLayer_Batch_1_StreamingFCLayer_g8j_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 8;
parameter MEM_SIZE = 180;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[0:MEM_SIZ... | 6.840686 |
module StreamingFCLayer_Batch_1_StreamingFCLayer_g8j (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd180;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Actbkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 3;
parameter AWIDTH = 5;
parameter MEM_SIZE = 30;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Actbkb (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd3;
parameter AddressRange = 32'd30;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Actcud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 4;
parameter AWIDTH = 5;
parameter MEM_SIZE = 30;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Actcud (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd4;
parameter AddressRange = 32'd30;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_ActdEe_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 5;
parameter AWIDTH = 5;
parameter MEM_SIZE = 30;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_ActdEe (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd5;
parameter AddressRange = 32'd30;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apbkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 10;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apbkb(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd10;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth -... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apcud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apcud(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth -... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apdEe_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 12;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apdEe(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd12;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth -... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apeOg_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apeOg(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth -... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apfYi_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apfYi(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth -... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apg8j_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 10;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apg8j(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd10;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth -... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_aphbi_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 12;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_aphbi(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd12;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth -... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apibs_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apibs(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth -... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apjbC_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 12;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apjbC(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd12;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth -... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apkbM_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 12;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apkbM(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd12;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth -... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_aplbW_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_aplbW(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - ... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apmb6_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apmb6(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - ... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apncg_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apncg(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - ... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apocq_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 7;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apocq(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd7;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - ... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_appcA_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_appcA(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth -... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apqcK_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 12;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_2_Matrix_Vector_Activate_Stream_Batch_576u_128u_16u_8u_Slice_ap_int_2u_Slice_apqcK(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd12;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth -... | 6.840686 |
module StreamingFCLayer_Batch_2_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_s... | 6.840686 |
module StreamingFCLayer_Batch_2_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1... | 6.840686 |
module StreamingFCLayer_Batch_2_StreamingFCLayer_eOg #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6... | 6.840686 |
module StreamingFCLayer_Batch_2_StreamingFCLayer_fYi_Mul_LUT_0 (
a,
b,
p
);
input [2 - 1 : 0] a;
input [2 - 1 : 0] b;
output [4 - 1 : 0] p;
assign p = $signed({1'b0, a}) * $signed(b);
endmodule
| 6.840686 |
module StreamingFCLayer_Batch_2_StreamingFCLayer_fYi (
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input [din0_WIDTH - 1:0] din0;
input [din1_WIDTH - 1:0] din1;
output [dout_... | 6.840686 |
module StreamingFCLayer_Batch_2_StreamingFCLayer_g8j_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 40;
parameter AWIDTH = 9;
parameter MEM_SIZE = 270;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[0:MEM_SIZ... | 6.840686 |
module StreamingFCLayer_Batch_2_StreamingFCLayer_g8j (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd40;
parameter AddressRange = 32'd270;
parameter AddressWidth = 32'd9;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0... | 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Actbkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 3;
parameter AWIDTH = 6;
parameter MEM_SIZE = 60;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM... | 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Actbkb (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd3;
parameter AddressRange = 32'd60;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
... | 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Actcud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 4;
parameter AWIDTH = 6;
parameter MEM_SIZE = 60;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM... | 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Actcud (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd4;
parameter AddressRange = 32'd60;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
... | 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_ActdEe_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 5;
parameter AWIDTH = 6;
parameter MEM_SIZE = 60;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM... | 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_ActdEe (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd5;
parameter AddressRange = 32'd60;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
... | 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_abkb_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 9;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_abkb(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd9;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - ... | 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_acud_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_acud(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth -... | 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_adEe_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 12;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_adEe(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd12;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth -... | 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_aeOg_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_aeOg(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth -... | 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_afYi_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 10;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
... | 6.840686 |
module StreamingFCLayer_Batch_3_Matrix_Vector_Activate_Stream_Batch_1152u_128u_16u_4u_Slice_ap_int_2u_Slice_afYi(
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd10;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth -... | 6.840686 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.